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BBB开发板原理图

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bbb开发板原理图,挺有用的资料

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5 REV A4A Initial production Release. 4 Description 3 DATE BY 11/19/2012 GC On the initial production release the processors were to be found incorrect as supplied by TI. A5 Parts while marked AM3359 were actually AM3352. This revision uses the correct parts. 1/2/2013 GC D 1. Deleted R29-R44 from the LCD lines. 2. Added 47pf capacitors C156-C173 to LCD data lines to ground. 3. Changed schematic revision to A5A. 4. Changed a few footprints after PCB update for above changes. A5A 5. Added access point for the battery function of the TPS65217C. 2/8/2013 GC 6. Added Ferrite beads in series with LED power and 5V power rail of the USB host connector. Required to pass FCC/CE testing due to noise emissions on that pin. 7. Added power button to enable sleep, wakeup, power down and power up features on the system. 8. Added Modification to add 100K ohm resistor to ground to prvent crosstalk when serial cable is not plugged in. C 1. Added 100K pulldown on J1 pin 4 to prvent crosstalk when serial cable is A5B not connected into PCB layout. 2. Changed the LED resistors to 4.75K to lower the brightness. 5/21/2013 GC 1. Changed R46, R47,R48 to 0 ohms. A5C 2. Changed R45 to 22 Ohms. 6/12/2013 GC Change was made due to production failures on some boards due to differences in impedances. B This schematic is *NOT SUPPORTED* and DOES NOT constitute a reference design. Only “community” support is allowed via resources at BeagleBoard.org/discuss. THERE IS NO WARRANTY FOR THIS DESIGN , TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE DESIGN “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS A FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE DESIGN IS WITH YOU. SHOULD THE DESIGN PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 5 4 3 2 1 PAGE NO. SCHEMATIC PAGE D 1 COVER PAGE 2 POWER MANAGEMENT 3 PROCESSOR 1 OF 3, JTAG HEADER 4 PROCESSOR 2 OF 3, UAB PORTS 5 PROCESSOR 3 OF 3 6 LED, CONFIGURATION AND BUTTON 7 DDR3 MEMORY 8 eMMC FLASH C 9 10/100 ETHERNET 10 HDMI FRAMER 11 EXP CONN, uSD NOTE: PCB Revision for this board is Rev B4. B A Title BeagleBone Black Cover Page Size Document Number B 450-5500-001 Date: Wednesday, June 12, 2013 Sheet 1 2 1 Rev A5C of 11 5 4 3 2 1 P1 1 D 1 33 2 2 VDD_3V3A PJ-200A DGND 4 PMIC_POWR_EN 11 4,10,11 4,10,11 PWR_BUT I2C0_SCL I2C0_SDA MTG1 C MHOLE MTG2 MHOLE MTG3 MHOLE MTG4 MHOLE B 1.5K,1% R3 1.5K,1% R4 VDD_5V USB_DC C2 10uF,10V C1 10uF,10V DGND DGND C3 0.1uf,6.3V C4 10uF,10V DGND S3 KMR231GLFS 1 2 P_INT_LDO P_BYPASS U2 10 AC 12 USB 17 15 NC1 NC 48 INT_LDO 47 BYPASS 14 MUX_IN 9 44 PWR_EN 25 RESET 28 PB_IN 27 SCL SDA 36 ISET2 3 4 POWER BUTTON DGND SYS_5V DGND C7 10uF,10V 35 ISET1 21 VIN_DCDC1 C8 10uF,10V 22 VIN_DCDC2 C10 10uF,10V SYS_5V DGND C13 10uF,10V 32 VIN_DCDC3 39 LDO3_IN 42 LDO4_IN 2 VINLDO SYS_5V 7 SYS1 8 SYS2 BAT1 4 5 BAT2 6 BAT_SENSE 11 TS MUX_OUT 16 18 VIO 26 PGOOD 46 LDO_PGOOD 13 WAKEUP 45 INT ISINK1 ISINK2 34 33 38 FB_WLED DGND VIO Battery access pins. Pins TP5 TESTPT1 TP6 TESTPT1 TP7 TESTPT1 are randomly placed to fit them in, but will be able to tie into them either with a TP8 TESTPT1 VDD_3V3A cape or wires. Pins will not be populated. R1 100K,1% PMIC_PGOOD 3 LDO_PGOOD 3 WAKEUP 4 PMIC_INT 3 37 L4 20 L1 19 VDCDC1 23 L2 VDCDC2 24 L3 31 29 VDCDC3 40 LDO3 L1 P_L1 1 2 R6 LQM2HPN2R2MG0L VDCDC1 L2 P_L2 1 2 VDCDC2 LQM2HPN2R2MG0L VDDS L3 P_L3 1 2 LQM2HPN2R2MG0L VDCDC3 R9 VIO LDO4 43 VLDO1 3 1 VLDO2 R7 VLDO1 R5 R8 0,1% 0,1% 0,DNI VRTC C16 1.5V 0,1% VDDS_DDR VDD_MPU VDD_CORE VDD_1V8 0,1% C11 C12 C9 10uF,10V 10uF,10V 10uF,10V VDD_3V3A C14 10uF,10V C15 10uF,10V SYS_5V C17 2.2uF,6.3V VDD_3V3AUX U4 2 1 IN 5 EN 7 GND1 GND2 TL5209 DGND 3 OUT 4 ADJ 6 GND3 8 GND4 500mA 470K,1% R10 VDD_3V3B 280K,1% R11 TPS65217C C19 470pF,6.3V C20 0.1uf,6.3V DGND 41 AGND 30 PGND 49 PPAD VDD_3V3AUX 2.2uF,6.3V DGND DGND DGND DGND POWER LED 4.75K,5% D1 PWR_LEDR C18 2.2uF,6.3V LTST-C191TBKT R12 DGND DGND A DGND DGND DGND DGND DGND TP1 TESTPT1 D DGND C B A Title BeagleBone Black Power Management Size Document Number Rev B 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 2 of 11 5 4 3 2 1 5 4 3 2 1 VDD_3V3A C21 D 18pF,50V 3.3V R14 10K,1% S1 D KMR231GLFS C22 2 Y1 1 2 OSC1_OUT1 4 1 3 4 C24 3 2 18pF,50V 32.768KHz MC-306 Y2 24MHz R17 1M,1% 2 LDO_PGOOD 2 PMIC_PGOOD RESET 1uF,10V DGND C25 DGND 1 18pF,50V OSC0_OUT1 U5A OSC0_IN V10 B15 C26 18pF,50V GND_OSC0 OSC0_OUT GND_OSC0 OSC1_IN OSC1_OUT GND_OSC1 OSC0_IN U11 V11 OSC0_OUT VSS_OSC0 A6 OSC1_IN A4 A5 OSC1_OUT VSS_RTC SubArctic AM335x 15mm x 15mm Package PORZn A10 NRESET_INOUT 1.8V RTC_PORZn B5 B18 NNMI A15 EVENT_INTR0/TIMER4/CLKOUT1/SPI1_CS1/PR1PRU1R31_16/EMU2/GPIO0_19 D14 EVENT_INTR1/TCLKIN/CLKOUT2/TIMER7/PR1PRU0_PRUR31_16/EMU3/GPIO0_20 B10 NTRST C11 PROC_A15 R18 JTAG_TRSTn JTAG_TMS 33 XDMA_EVENT_INTR0 CLKOUT_SRC R19 0,1% R20 SYS_RESETn 9,11 PMIC_INT CLKOUT2 0,1% GPIO3_20 2 3,11 4 7 DDR_A[15..0] DDR_A[15..0] DDR_A0 F3 TMS B11 TDI A12 JTAG_TDI JTAG_TCK DDR_A1 H1 DDR_A0 TCK A11 JTAG_TDO DDR_A2 E4 DDR_A1 TDO C14 JTAG_EMU0 DDR_A3 C3 DDR_A2 EMU0/GPIO3_7 B14 JTAG_EMU1 DDR_A4 C2 DDR_A3 EMU1/GPIO3_8 C 7 DDR_BA[2..0] DDR_BA[2..0] DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 DDR_A15 DDR_BA0 DDR_BA1 B1 DDR_A4 D5 DDR_A5 E2 DDR_A6 D4 DDR_A7 C1 DDR_A8 F4 DDR_A9 F2 DDR_A10 E3 DDR_A11 H3 DDR_A12 H4 DDR_A13 D3 DDR_A14 C4 DDR_A15 E1 DDR_BA0 V12 GPMC_CLK/LCD_MEM_CLK/GPMC_WAIT1/MMC2_CLK/PRT1_MII1_TXEN/MCASP0_FSR/GPIO2_1 V6 GPMC_CSN0/GPIO1_29 U9 GPMC_CSN1/GPMC_CLK/MMC1_CLK/PRT1EDIO_DATA_IN6/PRT1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_12/PR1_PRU1_PRU_R31_12/GPIO1_30 V9 GPMC_CSN2/GPMC_BE1N/MMC1_CMD/PR1_EDIO_DATA_IN7/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_13/PR1_PRU1_PRU_R31_13/GPIO1_31 T13 H GPMC_CSN3/MMC2_CMD/PR1_MDIO_DATA/GPIO2_0 U6 GPMC_WEN/TIMER6/GPIO2_4 T7 GPMC_OEN_REN/TIMER7/EMU4/GPIO2_3 R7 GPMC_ADVN_ALE/TIMER4/GPIO2_2 T6 GPMC_BE0N_CLE/TIMER5/GPIO2_5 U18 GPMC_BE1N/GMII2_COL/GPMC_CSN6/MMC2_DAT3/GPMC_DIR/PR1_MII1_RXLINK/MCASP0_ACLKR/GPIO1_28 T17 GPMC_WAIT0/GM112_CRS/GPMC_CSN4/RMII2_CRS_DV/MMC1_SDCD/PR1_MII1_RXDV/UART4_RXD/GPIO0_30 U17 GPMC_WPN/GMII2_RXERR/GPMC_CSN5/RMII2_RXERR/MMC2_SDCD/PR1_MDIO_MDCLK/UART4_TXD/GPIO0_31 U5_T13 GPIO2_1 11 GPIO1_29 11 MMC1_CLK 8,11 MMC1_CMD 8,11 TIMER6 11 TIMER7 11 TIMER4 11 TIMER5 11 GPIO1_28 11 UART4_RXD 11 UART4_TXD 11 U6 1 8 2 CLK VCC 7 12M_LOOP 3 4 D Q PRE 6 CLR 5 GND Q VDD_3V3A R21 33 12MHZ 10 C 7 DDR_D[15..0] DDR_D[15..0] DDR_BA2 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 B3 DDR_BA1 DDR_BA2 M3 M4 DDR_D0 N1 DDR_D1 N2 DDR_D2 N3 DDR_D3 N4 DDR_D4 P3 DDR_D5 P4 DDR_D6 J1 DDR_D7 K1 DDR_D8 K2 DDR_D9 K3 DDR_D10 K4 DDR_D11 L3 DDR_D12 L4 DDR_D13 U7 GPMC_AD0/MMC1_DAT0//////GPIO1_0 V7 GPMC_AD1/MMC1_DAT1//////GPIO1_1 R8 GPMC_AD2/MMC1_DAT2//////GPIO1_2 T8 GPMC_AD3/MMC1_DAT3//////GPIO1_3 U8 GPMC_AD4/MMC1_DAT4//////GPIO1_4 V8 GPMC_AD5/MMC1_DAT5//////GPIO1_5 R9 GPMC_AD6/MMC1_DAT6//////GPIO1_6 T9 GPMC_AD7/MMC1_DAT7//////GPIO1_7 U10 GPMC_AD8/LCD_DATA23/MMC1_DAT0/MMC2_DAT4/EHRPWM2A/PR1_MII_MT0_CLK//GPIO0_22 T10 GPMC_AD9/LCD_DATA22/MMC1_DAT1/MMC2_DAT5/EHRPWM2B/PR1_MII0_CRS//GPIO0_23 T11 GPMC_AD10/LCD_DATA21/MMC1_DAT2/MMC2_DAT6/EHRPWM2_TRIPZONE_INPUT/PR1_MII0_TXEN//GPIO0_26 U12 GPMC_AD11/LCD_DATA20/MMC1_DAT3/MMC2_DAT7/EHRPWM2_SYNCI_O/PR1_MII0_TXD3//GPIO0_27 T12 GPMC_AD12/LCD_DATA19/MMC1_DAT4/MMC2_DAT0/EQEP2A_IN/PR1_MII0_TXD2/PR1_PRU0_PRU_R30_14/GPIO1_12 R12 GPMC_AD13/LCD_DATA18/MMC1_DAT5/MMC2_DAT1/EQEP2B_IN/PR1_MII0_TXD1/PR1_PRU0_PRU_R30_15/GPIO1_13 V13 GPMC_AD14/LCD_DATA17/MMC1_DAT6/MMC2_DAT2/EQEP2_INDEX/PR1_MII0_TXD0/PR1_PRU0_PRU_R31_14/GPIO1_14 U13 GPMC_AD15/LCD_DATA16/MMC1_DAT7/MMC2_DAT3/EQEP2_STROBE/PR1_ECAP0_ECAP_CAPIN_APWM_O/PR1_PRU0_PRU_R31_15/GPIO1_15 MMC1_DAT0 8,11 MMC1_DAT1 8,11 MMC1_DAT2 8,11 MMC1_DAT3 8,11 MMC1_DAT4 8,11 MMC1_DAT5 8,11 MMC1_DAT6 8,11 MMC1_DAT7 8,11 EHRPWM2A 11 EHRPWM2B 11 GPIO0_26 11 GPIO0_27 11 GPIO1_12 11 GPIO1_13 11 GPIO1_14 11 GPIO1_15 11 SN74AUC1G74 DGND C27 0.1uf,6.3V DGND CEC Clock for HDMI Framer Run over ground plane. Do not cross over plane breaks. R161 0,1% B 7 DDR_CLK 7 DDR_CLKn 7 DDR_CKE 7 DDR_CSn 7 DDR_CASn 7 DDR_RASn 7 DDR_WEn 7 DDR_DQM0 7 DDR_DQS0 7 DDR_DQSN0 7 DDR_DQM1 7 DDR_DQS1 7 DDR_DQSN1 7 DDR_ODT 7 DDR_RESETn DDR_D15 M1 DDR_D14 DDR_D15 D2 D1 DDR_CK G3 DDR_NCK H2 DDR_CKE F1 DDR_CSN0 G4 DDR_CASN B2 DDR_RASN DDR_WEn M2 P1 DDR_DQM0 P2 DDR_DQS0 J2 DDR_DQSN0 L1 DDR_DQM1 L2 DDR_DQS1 DDR_DQSN1 G1 G2 DDR_ODT J3 DDR_RESETN DDR_VTP R13 GPMC_A0/GMII2_TXEN/RGMII2_TCTL/RMII2_TXEN/GPMC_A16/PR1_MII_MT1_CLK/EHRPWM1_TRIPZONE_INPUT/GPIO1_16 V14 GPMC_A1/GMII2_RXDV/RGMII2_RCTL/MMC2_DAT0/GPMC_A17/PR1_MII1_TXD3/EHRPWM1_SYNCI_O/GPIO1_17 U14 GPMC_A2/GMII2_TXD3/RGMII2_TD3/MMC2_DAT1/GPMC_A18/PR1_MII1_TXD2/EHRPWM1A/GPIO1_18 T14 GPMC_A3/GMII2_TXD2/RGMII2_TD2/MMC2_DAT2/GPMC_A19/PR1_MII1_TXD1/EHRPWM1B/GPIO1_19 R14 GPMC_A4/GMII2_TXD1/RGMII2_TD1/RMII2_TXD1/GPMC_A20/PR1_MII1_TXD0/EQEP1A_IN/GPIO1_20 V15 GPMC_A5/GMII2_TXD0/RGMII2_TD0/RMII2_TXD0/GPMC_A21/PR1_MII1_RXD3/EQEP1B_IN/GPIO1_21 U15 GPMC_A6/GMII2_TXCLK/RGMII2_TCLK/MMC2_DAT4/GPMC_A22/PR1_MII1_RXD2/EQEP1_INDEX/GPIO1_22 T15 GPMC_A7/GMII2_RXCLK/RGMII2_RCLK/MMC2_DAT5/GPMC_A23/PR1_MII1_RXD1/EQEP1_STROBE/GPIO1_23 V16 GPMC_A8/GMII2_RXD3/RGMII2_RD3/MMC2_DAT6/GPMC_A24/PR1_MII1_RXD0/MCASP0_ACLKX/GPIO1_24 U16 GPMC_A9/GMII2_RXD2/RGMII2_RD2/MMC2_DAT7/GPMC_A25/PR1_MII_MR1_CLK/MCASP0_FSX/GPIO1_25 T16 GPMC_A10/GMII2_RXD1/RGMII2_RD1/RMII2_RXD1/GPMC_A26/PR1_MII1_CRS/MCASP0_AXR0/GPIO1_26 V17 GPMC_A11/GMII2_RXD0/RGMII2_RD0/RMII2_RXD0/GPMC_A27/PR1_MII1_RXER/MCASP0_AXR1/GPIO1_27 U5_R13 GPIO1_17 EHRPWM1A EHRPWM1B USR0 USR1 USR2 USR3 HDMI_INT USB1_OCn 11 11 11 6 6 6 6 10 4 HDMICLK_DISn R160 0,1% Y4 1 OE 4 VCC VDD_3V3A GPIO1_16 11 External clock to the McASP0 interface. G17 MMC0_CLK/GPMC_A24/UART3_CTSN/UART2_RXD/DCAN1_TX/PR1_PRU0_PRU_R30_12/PR1_PRU0_PRU_R31_12/GPIO2_30 G18 MMC0_CMD/GPMC_A25/UART3_RTSN/UART2_TXD/DCAN1_RX/PR1_PRU0_PRU_R30_13/PR1_PRU0_PRU_R31_13/GPIO2_31 G16 MMC0_DAT0/GPMC_A23/UART5_RTSN/UART3_TXD/UART1_RIN/PR1_PRU0_PRU_R30_11/PR1_PRU0_PRU_R31_11/GPIO2_29 G15 MMC0_DAT1/GPMC_A22/UART5_CTSN/UART3_RXD/UART1_DTRN/PR1_PRU0_PRU_R30_10/PR1_PRU0_PRU_R31_10/GPIO2_28 F18 MMC0_DAT2/GPMC_A21/UART4_RTSN/TIMER6/UART1_DSRN/PR1_PRU0_PRU_R30_9/PR1_PRU0_PRU_R31_9/GPIO2_27 F17 MMC0_DAT3/GPMC_A20/UART4_CTSN/TIMER5/UART1_DCDN/PR1_PRU0_PRU_R30_8/PR1_PRU0_PRU_R31_8/GPIO2_26 MMC0_CLKO 11 MMC0_CMD 11 MMC0_DAT0 11 MMC0_DAT1 11 MMC0_DAT2 11 MMC0_DAT3 11 2 GND 3 CLK R167 33 GPIO3_21 6,10,11 B 24.576MHZ C159 0.1uf,6.3V Oscillator can be disabled via SW for power down modes or if GPIO3_21 needs to be used. DDR_VTP 49.9,1% R22 DDR_VREF J4 VREFSSTL DGND DGND C28 0.1uf,6.3V XAM3359AZCZ100 VDD_3V3A C158 DGND DGND DGND VDD_3V3B VDD_3V3B VDD_3V3B R23 P2 JTAG_TMS 1 2 JTAG_TRSTn JTAG_TDI 3 TMS TRSTn 4 R24 JTAG_TDO 5 TDI 7 TVDD TDIS 6 NC 8 4.75K,1% 4.75K,1% JTAG_TCK 9 TDO GND1 10 11 TCKRTN GND2 12 DGND JTAG_EMU0 13 TCK GND3 14 JTAG_EMU1 SYS_RESETn XDMA_EVENT_INTR0 4,11 MMC0_CD 15 17 19 EMU0 SRST EMU2 EMU4 EMU1 16 GND4 18 EMU3 20 GND5 CLKOUT2 3,11 GND VCC U3 5 0.1uf,6.3V 2 A 4 Y SN74LVC1G06DCK 1 NC 3 DGND R162 0,1% eMMC_RSTn 8 C30 0.1uf,6.3V CTI JTAG,DNI C29 0.1uf,6.3V R25 4.75K,1% DGND DGND DGND DGND A A Title BeagleBone Black Processor 1 of 3 and JTAG Size Document Number Rev C 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 3 of 11 5 4 3 2 1 5 4 3 2 1 VDD_3V3B VRTC D R163 4.75K,1% R26 4.75K,1% AIN7 U5B VDD_ADC R27 0,1% C31 C32 0.1uf,6.3V 0.001uf,50V C33 0.1uf,6.3V R164 4.75K,1% 2 PMIC_POWR_EN 2 WAKEUP DGND 11 AIN0 11 AIN1 11 AIN2 11 AIN3 11 AIN4 11 AIN5 11 AIN6 VREFP_ADC VREFN_ADC C6 C5 PMIC_POWER_EN 1.8V EXT_WAKEUP 1.8V B6 C7 AIN0 B7 AIN1 A7 AIN2 C8 AIN3 B8 AIN4 A8 AIN5 C9 AIN6 AIN7 B9 A9 VREFP VREFN SubArctic AM335X 15mm x 15mm Package GMII1_TXCLK/UART2_RXD/RGMII1_TCLK/MMC0_DAT7/MMC1_DAT0/UART1_DCDN/MCASP0_ACLKX/GPIO3_9 GMII1_TXD0/RMII1_TXD0/RGMII1_TD0/MCASP1_AXR2/MCASP1_ACLKR/EQEP0B_IN/MMC1_CLK/GPIO0_28 GMII1_TXD1/RMII1_TXD1/RGMII1_TD1/MCASP1_FSR/MCASP1_AXR1/EQEP0A_IN/MMC1_CMD/GPIO0_21 GMII1_TXD2/DCAN0_RX/RGMII1_TD2/UART4_TXD/MCASP1_AXR0/MMC2_DAT2/MCASP0_AHCLKX/GPIO0_17 GMII1_TXD3/DCAN0_TX/RGMII1_TD3/UART4_RXD/MCASP1_FSX/MMC2_DAT1/MCASP0_FSR/GPIO0_16 GMII1_TXEN/RMII1_TXEN/RGMII1_TCTL/TIMER4/MCASP1_AXR0/EQEP0_INDEX/MMC2_CMD/GPIO3_3 GMII1_CRS/RMII1_CRS_DV/SPI1_D0/I2C1_SDA/MCASP1_ACLKX/UART5_CTSN/UART2_RXD/GPIO3_1 GMII1_COL/RMII2_REFCLK/SPI1_SCLK/UART5_RXD/MCASP1_AXR2/MMC2_DAT3/MCASP0_AXR2/GPIO3_0 GMII1_RXCLK/UART2_TXD/RGMII1_RCLK/MMC0_DAT6/MMC1_DAT1/UART1_DSRN/MCASP0_FSX/GPIO3_10 GMII1_RXD0/RMII1_RXD0/RGMII1_RD0/MCASP1_AHCLKX/MCASP1_AHCLKR/MCASP1_ACLKR/MCASP0_AXR3/GPIO2_21 GMII1_RXD1/RMII1_RXD1/RGMII1_RD1/MCASP1_AXR3/MCASP1_FSR/EQEP0_STROBE/MMC2_CLK/GPIO2_20 GMII1_RXD2/UART3_TXD/RGMII1_RD2/MMC0_DAT4/MMC1_DAT3/UART1_RIN/MCASP0_AXR1/GPIO2_19 GMII1_RXD3/UART3_RXD/RGMII1_RD3/MMC0_DAT5/MMC1_DAT2/UART1_DTRN/MCASP0_AXR0/GPIO2_18 GMII1_RXERR/RMII1_RXERR/SPI1_D1/I2C1_SCL/MCASP1_FSX/UART5_RTSN/UART2_TXD/GPIO3_2 GMII1_RXDV/LCD_MEMORY_CLK/RGMII1_RCTL/UART5_TXD/MCASP1_ACLKX/MMC2_DAT0/MCASP0_ACLKR/GPIO3_4 GNDA_ADC GNDA_ADC J1 Mark pin 1 clearly 1 2 3 4 5 C 6 B_UART0_RX B_UART0_TX HEADER 6 DGND R165 C155 11 11 11 11 3,11 UART2_RXD UART2_TXD I2C1_SDA I2C1_SCL MMC0_CD A17 B17 B16 A16 C15 0.1uf,6.3V UART0_TX E16 U15 UART0_RX E15 1 2 1OE 8 VCC 7 VDD_3V3B E18 E17 3 1A 2OE 6 4 2Y 1Y 5 GND 2A SN74LVC2G241 POWERDOWN ISOLATION DGND 11 UART1_TXD 11 UART1_RXD 11 I2C2_SDA 11 I2C2_SCL D15 D16 D18 D17 UART0 Serial Port USB to TTL Serial Cable DGND 3.3V 100K,1% 2,10,11 I2C0_SCL 2,10,11 I2C0_SDA C16 C17 USB_DC DGND R49 USB0_DP N17 USB0_DM N18 M15 USB0_ID P16 F16 R159 P15 0,1% USB1_DP R17 USB1_DM R18 P18 0,1% USB1_ID P17 USB1_DRVVBUS F15 USB1_VBUS T18 SPI0_SCLK/UART2_RXD/I2C2_SDA/EHRPWM0A/PR1_UART0_CTS_N/PR1_EDIO_SOF/EMU2/GPIO0_2 RMII1_REFCLK/XDMA_EVENT_INTR2/SPI1_CS0/UART5_TXD/MCASP1_AXR3/MMC0_POW/MCASP1_AHCLKX/GPIO0_29 SPI0_D0/UART2_TXD/I2C2_SCL/EHRPWM0B/PR1_UART0_RTS_N/PR1_EDIO_LATCH_IN/EMU3/GPIO0_3 MDIO_CLK/TIMER5/UART5_TXD/UART3_RTSN/MMC0_SDWP/MMC1_CLK/MMC2_CLK/GPIO0_1 SPI0_D1/MMC1_SDWP/I2C1_SDA/EHRPWM0_TRIPZONE_INPUT/PR1_UART0_RXD/PR1_EDIO_DATA_IN0/PR1_EDIO_DATA_OUT0/GPIO0_4 MDIO_DATA/TIMER6/UART5_RXD/UART3_CTSN/MMC0_SDCD/MMC1_CMD/MMC2_CMD/GPIO0_0 SPI0_CS0/MMC2_SDWP/I2C1_SCL/EHRPWM0_SYNCI_O/PR1_UART0_TXD/PR1_EDIO_DATA_IN1/PR1_EDIO_DATA_OUT1/GPIO0_5 SPI0_CS1/UART3_RXD/ECAP1_IN_PWM1_OUT/MMC0_POW/XDMA_EVENT_INTR2/MMC0_SDCD/EMU4/GPIO0_6 LCD_DATA0/GPMC_A0//EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6 UART0_TXD/SPI1_CS1/DCAN0_RX/I2C2_SCL/ECAP1_IN_PWM1_OUT/PR1_PRU1_PRU_R30_15/PR1_PRU1_PRU_R31_15/GPIO1_11 LCD_DATA1/GPMC_A1//EHRPWM2B//PR1_PRU1_PRU_R30_1/PR1_PRU1_PRU_R31_1/GPIO2_7 UART0_RXD/SPI1_CS0/DCAN0_TX/I2C2_SDA/ECAP2_IN_PWM2_OUT/PR1_PRU1_PRU_R30_14/PR1_PRU1_PRU_R31_14/GPIO1_10 LCD_DATA2/GPMC_A2//EHRPWM2_TRIPZONE_INPUT//PR1_PRU1_PRU_R30_2/PR1_PRU1_PRU_R31_2/GPIO2_8 UART0_CTSN/UART4_RXD/DCAN1_TX/I2C1_SDA/SPI1_D0/TIMER7/PR1_EDC_SYNC0_OUT/GPIO1_8 LCD_DATA3/GPMC_A3//EHRPWM2_SYNCI_O//PR1_PRU1_PRU_R30_3/PR1_PRU1_PRU_R31_3/GPIO2_9 UART0_RTSN/UART4_TXD/DCAN1_RX/I2C1_SCL/SPI1_D1/SPI1_CS0/PR1_EDC_SYNC1_OUT/GPIO1_9 LCD_DATA4/GPMC_A4//EQEP2A_IN//PR1_PRU1_PRU_R30_4/PR1_PRU1_PRU_R31_4/GPIO2_10 LCD_DATA5/GPMC_A5//EQEP2B_IN//PR1_PRU1_PRU_R30_5/PR1_PRU1_PRU_R31_5/GPIO2_11 LCD_DATA6/GPMC_A6/PR1_EDIO_DATA_IN6/EQEP2_INDEX/PR1_EDIO_DATA_OUT6/PR1_PRU1_PRU_R30_6/PR1_PRU1_PRU_R31_6/GPIO2_12 LCD_DATA7/GPMC_A7/PR1_EDIO_DATA_IN7/EQEP2_STROBE/PR1_EDIO_DATA_OUT7/PR1_PRU1_PRU_R30_7/PR1_PRU1_PRU_R31_7/GPIO2_13 LCD_DATA8/GPMC_A12/EHRPWM1_TRIPZONE_INPUT/MCASP0_ACLKX/UART5_TXD/PR1_MII0_RXD3/UART2_CTSN/GPIO2_14 UART1_TXD/MMC2_SDWP/DCAN1_RX/I2C1_SCL//PR1_UART0_TXD/PR1_PRU0_PRU_R31_16/GPIO0_15 LCD_DATA9/GPMC_A13/EHRPWM1_SYNCI_O/MCASP0_FSX/UART5_RXD/PR1_MII0_RXD2/UART2_RTSN/GPIO2_15 UART1_RXD/MMC1_SDWP/DCAN1_TX/I2C1_SDA//PR1_UART0_RXD/PR1_PRU1_PRU_R31_16/GPIO0_14 LCD_DATA10/GPMC_A14/EHRPWM1A/MCASP0_AXR0//PR1_MII0_RXD1/UART3_CTSN/GPIO2_16 UART1_CTSN/TIMER6/DCAN0_TX/I2C2_SDA/SPI1_CS0/PR1_UART0_CTS_N/PR1_EDC_LATCH0_IN/GPIO0_12 LCD_DATA11/GPMC_A15/EHRPWM1B/MCASP0_AHCLKR/MCASP0_AXR2/PR1_MII0_RXD0/UART3_RTSN/GPIO2_17 UART1_RTSN/TIMER5/DCAN0_RX/I2C2_SCL/SPI1_CS1/PR1_UART0_RTS_N/PR1_EDC_LATCH1_IN/GPIO0_13 LCD_DATA12/GPMC_A16/EQEP1A_IN/MCASP0_ACLKR/MCASP0_AXR2/PR1_MII0_RXLINK/UART4_CTSN/GPIO0_8 LCD_DATA13/GPMC_A17/EQEP1B_IN/MCASP0_FSR/MCASP0_AXR3/PR1_MII0_RXER/UART4_RTSN/GPIO0_9 I2C0_SCL/TIMER7/UART2_RTSN/ECAP1_IN_PWM1_OUT////GPIO3_6 LCD_DATA14/GPMC_A18/EQEP1_INDEX/MCASP0_AXR1/UART5_RXD/PR1_MII_MR0_CLK/UART5_CTSN/GPIO0_10 I2C0_SDA/TIMER4/UART2_CTSN/ECAP2_IN_PWM2_OUT////GPIO3_5 LCD_DATA15/GPMC_A19/EQEP1_STROBE/MCASP0_AHCLKX/MCASP0_AXR3/PR1_MII0_RXDV/UART5_RTSN/GPIO0_11 USB0_DP USB0_DM USB0_CE USB0_ID USB0_DRVVBUS/GPIO0_18 USB0_VBUS USB1_DP USB1_DM USB1_CE USB1_ID USB1_DRVVBUS/GPIO3_13 USB1_VBUS LCD_PCLK/GPMC_A10//PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24 LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22 LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23 LCD_AC_BIAS_EN/GPMC_A11//PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25 MCASP0_AHCLKX/EQEP0_STROBE/MCASP0_AXR3/MCASP1_AXR1/EMU4/PR1_PRU0_PRU_R30_7/PR1_PRU0_PRU_R31_7/GPIO3_21 MCASP0_ACLKX/EHRPWM0A//SPI1_SCLK/MMC0_SDCD/PR1_PRU0_PRU_R30_0/PR1_PRU0_PRU_R31_0/GPIO3_14 MCASP0_FSX/EHRPWM0B//SPI1_D0/MMC1_SDCD/PR1_PRU0_PRU_R30_1/PR1_PRU0_PRU_R31_1/GPIO3_15 MCASP0_AXR0/EHRPWM0_TRIPZONE_INPUT//SPI1_D1/MMC2_SDCD/PR1_PRU0_PRU_R30_2/PR1_PRU0_PRU_R31_2/GPIO3_16 MCASP0_AHCLKR/EHRPWM0_SYNCI_O/MCASP0_AXR2/SPI1_CS0/ECAP2_IN_PWM2_OUT/PR1_PRU0_PRU_R30_3/PR1_PRU0_PRU_R31_3/GPIO3_17 MCASP0_ACLKR/EQEP0A_IN/MCASP0_AXR2/MCASP1_ACLKX/MMC0_SDWP/PR1_PRU0_PRU_R30_4/PR1_PRU0_PRU_R31_4/GPIO3_18 MCASP0_FSR/EQEP0B_IN/MCASP0_AXR3/MCASP1_FSX/EMU2/PR1_PRU0_PRU_R30_5/PR1_PRU0_PRU_R31_5/GPIO3_19 MCASP0_AXR1/EQEP0_INDEX//MCASP1_AXR0/EMU3/PR1_PRU0_PRU_R30_6/PR1_PRU0_PRU_R31_6/GPIO3_20 K18 K17 K16 K15 J18 J16 H17 H16 L18 M16 L15 L16 L17 J15 J17 H18 U5_H18 R28 M18 M17 R1 R2 R3 R4 T1 T2 T3 T4 U1 U2 U3 U4 V2 V3 V4 T5 V5 LCDPCLK R45 U5 LCDVSYNC R46 R5 LCDVHYNC R47 R6 LCDDE R48 A14 A13 B13 D12 C12 B12 C13 D13 33 22 0 0 0 11 GPIO0_7 R50 R51 0,1% 0,1% GPIO0_7SRC C18 ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7 XAM3359AZCZ100 GPIO3_18 B VDD_3V3A SYS_5V C34 + 100uF,6.3V USB1_DRVVBUS R53 10K,1% DGND U8 2 8 3 IN1 OUT1 7 4 IN2 OUT2 6 1 EN OUT3 5 GND OC 9 PAD TPS2051 (DGN) DGND DGND R52 10K,1% DGND USB HOST FB8 1 2 0.1 Ohm,0805 USB1_PWR USB1_DM USB1_DP U9 1 6 D+ VBUS 2 D- 3 ID 5 NC 4 GND TPD4S012 C35 0.1uf,6.3V DGND A FB7 1 2 VBUS 150OHM800mA DGND P3 87520-0010BLF 1 VBUS 2 D- SHIELD 5 3 D+ 4 GND SHIELD 6 USB1_OCn 3 USB_DC USB0_ID USB0_DP USB0_DM U10 1 6 D+ VBUS 2 D- 3 ID 5 NC 4 GND TPD4S012 5 4 G1 3 ID 2 D+ 1 D- VB DGND P4 C36 0.1uf,6.3V DGND 7 G2 6 G3 9 G4 8 G5 USB5MINI USB PC CONNECTOR D MII1_TXCLK 9 MII1_TXD0 9 MII1_TXD1 9 MII1_TXD2 9 MII1_TXD3 9 MII1_TXEN 9 MII1_CRS_DV 9 MII1_COL 9 MII1_RXCLK 9 MII1_RXD0 9 MII1_RXD1 9 MII1_RXD2 9 MII1_RXD3 9 MII1_RXERR 9 MII1_RXDV 9 MII1_REFCLK 9 MDIO_CLK 9 MDIO_DATA 9 LCD_DATA0 6,10,11 LCD_DATA1 6,10,11 LCD_DATA2 6,10,11 LCD_DATA3 6,10,11 LCD_DATA4 6,10,11 LCD_DATA5 6,10,11 LCD_DATA6 6,10,11 LCD_DATA7 LCD_DATA8 6,10,11 6,10,11 C LCD_DATA9 6,10,11 LCD_DATA10 6,10,11 LCD_DATA11 6,10,11 LCD_DATA12 6,10,11 LCD_DATA13 6,10,11 LCD_DATA14 6,10,11 LCD_DATA15 6,10,11 LCD_PCLK LCD_VSYNC LCD_HSYNC LCD_DE 10,11 10,11 10,11 10,11 GPIO3_21 SPI1_SCLK SPI1_D0 SPI1_D1 SPI1_CS0 GPIO3_19 GPIO3_20 11 10,11 10,11 11 10,11 11 3 B A Title BeagleBone Black Processor 2 of 3, USB, and Serial Size Document Number Rev C 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 4 of 11 5 4 3 2 1 5 4 3 2 1 VDD_3V3A VDD_CORE VDD_CORE C37 0.1uf,6.3V C38 0.1uf,6.3V C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 U5C DGND F6 P7 C56 C57 10uF,10V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 10uF,10V 10uF,10V D F7 VDD_CORE1 G6 VDD_CORE2 VDDSHV11 P8 VDDSHV12 0.1uf,6.3V 0.1uf,6.3V D G7 VDD_CORE3 G10 VDD_CORE4 P10 H11 VDD_CORE5 VDDSHV21 P11 J12 VDD_CORE6 VDDSHV22 DGND K6 VDD_CORE7 K8 VDD_CORE8 K12 VDD_CORE9 L6 VDD_CORE10 P12 VDDSHV31 P13 VDDSHV32 C58 C59 0.1uf,6.3V 0.1uf,6.3V DGND L7 VDD_CORE11 VDD_MPU L8 VDD_CORE12 L9 VDD_CORE13 M11 VDD_CORE14 M13 VDD_CORE15 SubArctic AM335X H14 VDDSHV41 J14 VDDSHV42 C60 0.1uf,6.3V C61 0.1uf,6.3V N8 VDD_CORE16 N9 VDD_CORE17 C62 10uF,10V C63 C64 C65 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V VDD_MPU N12 VDD_CORE18 N13 VDD_CORE19 VDD_CORE20 K14 VDDSHV51 L14 VDDSHV52 C66 C67 VDD_1V8 FB1 1 2 VDD_PLL DGND TP2 VDD_MPUON TESTPT1 F10 F11 VDD_MPU1 F12 VDD_MPU2 F13 VDD_MPU3 G13 VDD_MPU4 H13 VDD_MPU5 J13 VDD_MPU6 A2 VDD_MPU7 VDD_MPU_MON CAP_VDD_SRAM_CORE D9 H15 CAP_VDD_SRAM_CORE VDDS_PLL_MPU 15mm x 15mm Package E10 VDDSHV61 E11 VDDSHV62 E12 VDDSHV63 E13 VDDSHV64 F14 VDDSHV65 G14 VDDSHV66 N5 VDDSHV67 P5 VDDSHV68 P6 VDDSHV69 0.1uf,6.3V 0.1uf,6.3V C68 C69 C70 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V C71 C72 C73 C74 C75 0.1uf,6.3V0.1uf,6.3V0.1uf,6.3V0.1uf,6.3V 0.1uf,6.3V DGND C77 C76 0.1uf,6.3V10uF,10V 150OHM800mA C78 0.1uf,6.3V C79 0.1uf,6.3V VDD_1V8 D10 CAP_VDD_SRAM_MPU D11 CAP_VBB_MPU C10 E9 VDDS_SRAM_MPU_BB CAP_VDD_SRAM_MPU CAP_VBB_MPU VDDS_SRAM_CORE_BG C DGND DGND VDD_3V3A VDD_1V8 C86 0.1uf,6.3V C87 C88 0.1uf,6.3V 0.1uf,6.3V N15 N16 VDDA3P3V_USB0 VDDA1P8V_USB0 M14 VSSA_USB2 R15 R16 VDDA3P3V_USB1 VDDA1P8V_USB1 N14 VSSA_USB1 VDDS E6 VDDS1 E14 VDDS2 F9 VDDS3 K13 C80 C81 C82 C83 C84 C85 VDDS4 N6 VDDS5 P9 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V C VDDS6 P14 VDDS7 D8 VDDA_ADC E8 VSSA_ADC VDD_ADC DGND FB2 1 2 VDD_1V8 FB3 150OHM800mA 1 2 VDDS_DDR DGND VDD_PLL DGND C92 0.1uf,6.3V DGND E7 VDDS_PLL_DDR E5 F5 VDDS_DDR1 G5 VDDS_DDR2 H5 VDDS_DDR3 J5 VDDS_DDR4 K5 VDDS_DDR5 L5 VDDS_DDR6 VDDS_DDR7 M5 VPP R10 VDDS_PLL_CORE_LCD D7 VDDS_RTC D6 CAP_VDD_RTC B4 ENZ_KALDO_1P8V VDD_RTC ENZ_KALDO_1P8V VDDS_OSC TESTOUT R11 TP3 A3 TESTOUT VRTC C93 0.1uf,6.3V VDD_PLL C94 0.1uf,6.3V 150OHM800mA GNDA_ADC DGND GNDA_ADC DGND VDD_PLL C95 10uF,10V C96 10uF,10V C97 C98 0.1uf,6.3V 0.1uf,6.3V C99 0.1uf,6.3V C100 0.1uf,6.3V C103 C101 C102 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V XAM3359AZCZ100 TESTPT1 R54 C104 C105 1uF,10V 0.1uf,6.3V C106 0.1uf,6.3V 1uF,10V C89 1uF,10V C90 1uF,10V C91 A1 A18 VSS1 F8 VSS2 G8 VSS3 G9 VSS4 G11 VSS5 G12 VSS6 H6 VSS7 H7 VSS8 H8 VSS9 H9 VSS10 H10 VSS11 H12 VSS12 J6 VSS13 J7 VSS14 J8 VSS15 J9 VSS16 J10 VSS17 J11 VSS18 K7 VSS19 K9 VSS20 K10 VSS21 K11 VSS22 L10 VSS23 L11 VSS24 L12 VSS25 L13 VSS26 M6 VSS27 M7 VSS28 M8 VSS29 M9 VSS30 M10 VSS31 M12 VSS32 N7 VSS33 N10 VSS34 N11 VSS35 V1 VSS36 V18 VSS37 VSS38 10K,1% DGND DGND DGND DGND B B A A Title BeagleBone Black Processr 3 of 3 Size Document Number Rev C 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 5 of 11 5 4 3 2 1 5 4 VDD_3V3A R70 R69 R68 R67 R66 R65 R64 R63 R62 R61 R60 R59 R58 R57 R56 R55 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1% 100K,1% 100K,1% 100K,1% 100K,1% S2 R75 100,1% KMR231GLFS D 1 2 SYS_BOOT0 SYS_BOOT1 SYS_BOOT2 SYS_BOOT3 SYS_BOOT4 SYS_BOOT5 SYS_BOOT6 SYS_BOOT7 SYS_BOOT8 SYS_BOOT9 SYS_BOOT10 SYS_BOOT11 SYS_BOOT12 SYS_BOOT13 SYS_BOOT14 SYS_BOOT15 LCD_DATA0 LCD_DATA1 LCD_DATA2 LCD_DATA3 LCD_DATA4 LCD_DATA5 LCD_DATA6 LCD_DATA7 LCD_DATA8 LCD_DATA9 LCD_DATA10 LCD_DATA11 LCD_DATA12 LCD_DATA13 LCD_DATA14 LCD_DATA15 Boot Configuration 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 4,10,11 3 4 uSD BOOT DGND R95 R94 R93 R92 R91 R90 R89 R88 R87 R86 R85 R84 R83 R82 R81 R80 C 100K,1% 100K,1% 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1%,DNI 100K,1% 100K,1% 100K,1% 100K,1% 100K,1% 100K,1% 100K,1% 100K,1% 100K,1%,DNI 100K,1% DGND 3 2 1 SYS_5V LEDDA LEDCA LEDBA R72 4.75K,5% R73 4.75K,5% R74 4.75K,5% R71 4.75K,5% D LEDAA 3 LEDDC D2 LTST-C191TBKT USR0 D3 LTST-C191TBKT USR1 D4 LTST-C191TBKT USR2 D5 LTST-C191TBKT USR3 6 LEDCC 3 LEDBC 6 LEDAC 47k 10k 47k 10k 47k 10k 47k 10k User LED's 3 USR0 Q1B Q2A Q1A 5 2 DMC56404 2 DMC56404 DMC56404 Q2B 5 DMC56404 4 R76 100K,1% 1 R77 100K,1% 4 R78 100K,1% 1 R79 100K,1% DGND DGND DGND DGND DGND DGND DGND DGND 3 USR1 C 3 USR2 3 USR3 B B A A Title BeagleBone Black LED, Configuration, and Reset Size Document Number Rev B 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 6 of 11 5 4 3 2 1 5 D C B A 5 4 3 2 1 DGND VDDS_DDR R96 10K,1% R97 1.5K,1% U12 DDR3L SDRAM 3 DDR_RESETn 3 DDR_CLK 3 DDR_CLKn 3 DDR_CKE 3 DDR_CSn 3 DDR_RASn 3 DDR_CASn 3 DDR_WEn 3 DDR_D[15..0] DDR_D0 T2 RESET# J7 K7 CK K9 CKn L2 CKE J3 CSn K3 L3 RASn CASn WEn E3 N3 A0 P7 A1 P3 A2 N2 A3 P8 A4 A5 A6 A7 P2 R8 R2 T8 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A[15..0] DDR_A[15..0] 3 D DDR_D1 DDR_D2 DDR_D3 F7 DQ0 F2 DQ1 F8 DQ2 A8 R3 A9 L7 A10 R7 DDR_A9 DDR_A10 DDR_A11 DDR_D4 DDR_D5 H3 DQ3 H8 DQ4 A11 N7 A12 T3 DDR_A12 DDR_A13 DDR_D6 DDR_D7 DDR_D8 G2 H7 D7 DQ5 DQ6 DQ7 A13 A14 A15 T7 M7 M2 DDR_A14 DDR_A15 DDR_BA0 DDR_BA[2..0] DDR_BA[2..0] 3 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 C3 C8 DQ8 DQ9 C2 DQ10 A7 DQ11 A2 DQ12 BA0 BA1 N8 M3 BA2 K1 ODT DDR_BA1 DDR_BA2 DDR_ODT DDR_ODT 3 DDR_D14 DDR_D15 B8 DQ13 A3 DQ14 DQ15 B2 VDD1 G7 VDD2 R9 VDDS_DDR 3 DDR_DQS1 3 DDR_DQSN1 C7 B7 UDQS UDQSn VDD3 VDD4 VDD5 K2 K8 N1 3 DDR_DQS0 3 DDR_DQSN0 F3 G3 LDQS LDQSn VDD6 N9 VDD7 R1 VDD8 D9 C 3 DDR_DQM1 3 DDR_DQM0 D3 E7 UDM LDM VDD9 A9 VSS1 VSS2 B3 E1 VDDS_DDR VDDS_DDR A1 A8 VDDQ1 VSS3 VSS4 G8 J2 C1 VDDQ2 VSS5 J8 C9 VDDQ3 D2 VDDQ4 VSS6 M1 VSS7 M9 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 E9 VDDQ5 VSS8 P1 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V F1 VDDQ7 VSS9 P9 H2 VDDQ8 VSS10 T1 H9 VDDQ9 VSS11 T9 VDDQ10 VSS12 VDDS_DDR DDR_VREF R98 10K,1% J1 J9 NC1 L1 NC2 L9 NC3 NC4 M8 VREF_CA VSSQ1 B1 B9 VSSQ2 D1 VSSQ3 D8 VSSQ4 E2 VSSQ5 E8 VSSQ6 F9 VSSQ7 VSSQ8 VSSQ9 G1 G9 DGND DGND VDDS_DDR C118 C119 C120 C121 C122 B 10uF,10V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 10uF,10V C123 0.001uf,50V R100 10K,1% C124 H1 VREF_DQ ZQ L8 0.1uf,6.3V MT41K256M16HA -125:E ZQ R99 240 DGND DGND DGND 4Gb DDR3 DGND A Title BeagleBone Black DDR3 Memory Size Document Number Rev B 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 7 of 11 4 3 2 1 5 4 3 2 1 VDD_3V3B R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 R111 VDD_3V3B eMMC_VCCI C125 VDD_3V3B 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% D 2.2uF,6.3V D DGND DGND U13 J10 VCC0 K9 VCC1 F5 VCC2 E6 VCC3 P3 VCCQ1 P5 VCCQ2 N4 VCCQ3 C6 VCCQ4 M4 VCCQ5 N2 VSSQ1 P6 VSSQ2 P4 VSSQ3 C4 VSSQ4 G5 VSS1 E7 VSS2 H10 VSS3 K8 VSS4 N5 VSS5 C2 VCCI 3,11 MMC1_DAT0 3,11 MMC1_DAT1 3,11 MMC1_DAT2 3,11 MMC1_DAT3 3,11 MMC1_DAT4 3,11 MMC1_DAT5 3,11 MMC1_DAT6 3,11 MMC1_DAT7 3,11 MMC1_CMD 3,11 MMC1_CLK 3 eMMC_RSTn C B A3 A4 DAT0 A5 DAT1 B2 DAT2 B3 DAT3 B4 B5 B6 M5 M6 DAT4 DAT5 DAT6 DAT7 CMD K5 CLK RST K6 N6 NC123 E5 NC122 N9 N8 N7 J12 NC121 NC120 NC119 NC118 P14 NC117 N3 NC116 P10 NC115 N1 NC114 M14 NC113 M13 M12 M11 M10 M9 NC112 NC111 NC110 NC109 NC108 M8 NC107 M7 NC106 P11 NC105 P12 NC104 P13 NC103 M3 M2 M1 L14 NC102 NC101 NC100 NC99 L13 NC98 L12 NC97 A10 NC96 A11 NC95 A12 NC94 A13 A14 B1 B7 G1 NC93 NC92 NC91 NC90 NC89 L3 NC88 L2 NC87 L1 NC86 K14 NC85 K13 NC84 K12 NC83 NC82 E1 NC1 E2 C126 C127 C128 C129 C130 NC2 E3 10uF,10V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V 0.1uf,6.3V NC3 A2 NC4 A6 NC5 A7 NC6 A8 NC7 E8 DGND NC8 E9 NC9 E10 NC10 A1 NC11 E12 NC12 E13 NC13 E14 NC14 F1 NC15 F2 NC16 F3 NC17 A9 NC18 B14 NC19 C14 NC20 C13 C NC21 C12 NC22 C11 NC23 F10 NC24 C10 NC25 F12 NC26 F13 NC27 F14 NC28 C9 NC29 C8 NC30 C7 NC31 C5 NC32 C3 NC33 C1 NC34 D14 NC35 D13 NC36 D12 NC37 D4 NC38 D3 NC39 G12 NC40 G13 NC41 G14 NC42 H1 NC43 NC44 H2 H3 B NC45 D2 NC46 H5 NC47 D1 NC48 B13 NC49 B12 NC50 B11 NC51 B10 NC52 B9 NC53 H12 NC54 MEM_MNAND_2GB G2 K10 NC81 G3 NC80 G10 NC79 K7 NC78 N11 NC77 N10 NC76 B8 NC75 K3 NC74 K2 NC73 K1 NC72 J14 NC71 J13 NC70 N12 NC69 N13 NC68 N14 NC67 P1 NC66 P2 NC65 P7 NC64 P9 NC63 P8 NC62 J5 NC61 J3 NC60 J2 NC59 J1 NC58 H14 NC57 H13 NC56 NC55 A A Title Beagle BoneBlack 2G eMMC Size Document Number Rev B 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 8 of 11 5 4 3 2 1 5 4 3 2 1 VDD_PHYA D C131 0.1uf,6.3V C132 0.1uf,6.3V C133 10uF,10V VDD_3V3B C135 0.1uf,6.3V 1 2 150OHM800mA FB4 DGND DGND DGND PHY_VDDCR C136 C134 470pF,6.3V 1uF,10V R119 4 4 C 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 3,11 B MII1_REFCLK MDIO_DATA MDIO_CLK MII1_RXD3 MII1_RXD2 MII1_RXD1 MII1_RXD0 MII1_RXDV MII1_RXCLK MII1_RXERR MII1_TXCLK MII1_TXEN MII1_TXD0 MII1_TXD1 MII1_TXD2 MII1_TXD3 MII1_COL MII1_CRS_DV SYS_RESETn DGND 12 VDDIO 1 VDD2A 27 VDD1A 6 VDDCR 1.5K,1% R125 R126 R127 R128 R129 R131 R133 R124 10,1%,DNI 100,1% 100,1% 100,1% 100,1% 100,1% 100,1% 100,1% 16 17 RXD3/PHYAD2 8 RXD2/RMIISEL 9 RXD1/MODE1 10 RXD0/MODE0 11 RXDV 26 REFCLKO 7 RXER/PHYAD0 13 MDIO MDC RXD3/PHYAD2 RXD2/RMIISEL RXD1/MODE1 RXD0/MODE0 RXDV RXCLK/PHYAD1 RXER/RXD4/PHYAD0 TXP 29 28 TXN 31 RXP 30 RXN R134 100,1% R138 R139 100,1% 100,1% R141 PHY_XTAL1 1M,1%,DNI PHY_XTAL2 TXCLK 20 21 TXCLK U14 22 TXEN 23 TXD0 24 TXD1 LAN8710A 25 TXD2 MODE2 15 TXD3 CRS 14 COL/CRS_DV/MODE2 CRS 3 R140 0,1%,DNI 19 nRST LED1/REGOFF 2 LED2/nINTSEL 18 R142 0,1% RCLKIN5 XTAL1/CLKIN nINT/TXER/TXD4 4 XTAL2 32 RBIAS 33 GND_EP R143 10,1% PHYX Y3 2 1 C142 25.000MHz XTAL150SMD_125X196 30pF,50V C143 30pF,50V QFN32_5X5MM_EP3P3MM DGND DGND TXP TXN RXP RXN C137 C138 C139 C140 15pF,DNI 15pF,DNI 15pF,DNI 15pF,DNI DGND DGND DGND DGND ETH_TXD4 ACTIVE WHEN LINK PRESENT. BLINKS OFF DURING ACTIVITY. ACTIVE WHEN AT 100MB RBIAS R144 12.1K,1% R145 10K,1% DGND DGND 49.9,1% R120 49.9,1% R121 49.9,1% R122 49.9,1% R123 10K,1% R115 10K,1% R116 10K,1% R117 10K,1% R118 1.5K,1% R113 1.5K,1% R114 1.5K,1% R112 REFCLKO RXD2/RMIISEL RXD3/PHYAD2 RXER/PHYAD0 VDD_3V3B D VDD_PHYA MODE2 RXD1/MODE1 RXD0/MODE0 DGND ETHERNET CONNECTOR P5 5 3 TCT 6 TD+ 1 TD2 RD+ 7 NC C 4 RD- 8 RCT GND R130 470,5% R132 470,5% YEL_C YELA GRN_C GRNA 11 13 12 10 9 YELC SHD1 YELA SHD2 GRNC GRNA 14 DGND R135 10K,1% DGND DGND LPJ0011BBNL TCT_RCT C141 VDD_PHYA 0.022uF,10V R137 0,1% R136 ESD_RING .1,0805 DGND DGND B DGND DGND A A Title BeagleBone Black Ethernet Size Document Number Rev B 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 9 of 11 5 4 3 2 1 5 4 3 2 1 DVI_+5V SYS_5V R146 R147 RT1 DVI_+5V PTC_RXEF010 IP4283CZ10-TT t 1.5K,1% 1.5K1% U11 P6 D 4,6,11LCD_DATA11 RED 4,6,11LCD_DATA12 4,6,11LCD_DATA13 4,6,11LCD_DATA14 4,6,11LCD_DATA15 GREEN 4,6,11LCD_DATA5 4,6,11LCD_DATA6 4,6,11LCD_DATA7 4,6,11LCD_DATA8 4,6,11LCD_DATA9 4,6,11LCD_DATA10 4,6,11LCD_DATA0 4,6,11LCD_DATA1 BLUE 4,6,11LCD_DATA2 4,6,11LCD_DATA3 4,6,11LCD_DATA4 4,1L1CD_VSYNC 4,1L1CD_HSYNC C 4,1L1CD_DE 4,1L1CD_PCLK 63 44 62 VPA0 R0 TX2- 45 61 VPA1 TX2+ 60 VPA2 33 RED 59 VPA3 DSCL 32 58 VPA4 DSDA 57 VPA5 56 VPA6 9 VPA7 R7 42 8 VPB0 G0 TX1- 43 7 VPB1 6 VPB2 TX1+ 31 GRN 3 VPB3 HPD 30 2 VPB4 CEC 1 VPB5 64 VPB6 G7 18 VPB7 39 17 VPC0 B0 TX0- 40 16 VPC1 TX0+ BLUE 15 VPC2 13 VPC3 34 12 VPC4 11 VPC5 EXT_SWING 38 10 VPC6 B7 TXC+ 37 21 VPC7 TXC- 22 VSYNC/VREF 20 HSYNC/VREF 4 DE/VREF 47 PCLK VDDA(PLL0)(1.8V) 48 VDDA(PLL1)(1.8V) HDMI_DSCL HDMI_DSDA HDMI_HPD HDMI_CEC HDMI_SWING R148 HDMI_TX2HDMI_TX2+ HDMI_TX1HDMI_TX1+ D8 HDMI_CEC_D RB751V40,115 HDMI_TX0HDMI_TX0+ R166 VDD_3V3B 27K,1% 10K,1% DGND HDMI_TXC+ HDMI_TXC- HDMI_1V8 D6 1 2 4 5 1 2 HDMI_DSCL HDMI_DSDA 5 3 DAT2- 4 DAT2+ 17 DAT2_S D 18 SCL 20 SDA MTG1 21 8 MTG2 6 DAT1- 7 DAT1+ 22 DAT1_SMTG3 HDMI_HPD HDMI_CEC 19 16 1 11 +5V MTG4 23 DDC/CEC GND HPLG 9 DAT0- 10 DAT0+ DAT0_S 15 13 CEC 12 14 CLK_S CLK+ CLK- NC 2 4 5 D7 10118241-001RLF DGND C 2.2uF,6.3V C144 0.1uf,6.3V C145 2.2uF,6.3V C146 0.1uf,6.3V C147 2.2uF,6.3V C148 0.1uf,6.3V C149 0.1uf,6.3V C150 2.2uF,6.3V C151 IP4283CZ10-TT 2,4,11 2,4,11 3 4,11 I2C0_SDA I2C0_SCL VDD_3V3B HDMI_INT SPI1_SCLK R158 10K,1% McASP0_ACLKX (Pin A13 Mode 0) 4,11 SPI1_CS0 4,11 SPI1_D0 3 12MHZ McASP0_AXR2 (Pin C12 Mode 2) McASP0_FSX (Pin B13 Mode 0) 51 52 53 54 50 CSDA CSCL A0_I2C A1_I2C INT 23 28 ACLK 26 AP3 25 AP2 24 AP1 AP0 27 OSC_IN 35 VDDA0(1.8V) VDDA1(TX)(1.8V) VDDA2(TX)(1.8V) VDDA3(TX)(1.8V) 36 41 46 5 VDDDC0(1.8V) 29 VDDDC1(1.8V) 14 VDDIOA(1.8V) 55 VDDIOB(1.8V) TEST VPP PAD 49 19 65 VDD_1V8 FB5 1 2 150OHM800mA 38 DGND 38 DGND DGND TDA19988 R149 0,1% B B 4,6,11LCD_DATA0 4,6,11LCD_DATA1 4,6,11LCD_DATA2 4,6,11LCD_DATA3 4,6,11LCD_DATA4 4,6,11LCD_DATA11 4,6,11LCD_DATA12 4,6,11LCD_DATA13 4,6,11LCD_DATA14 4,6,11LCD_DATA15 4,6,11LCD_DATA5 4,6,11LCD_DATA6 4,6,11LCD_DATA7 4,6,11LCD_DATA8 4,6,11LCD_DATA9 A 4,6,11LCD_DATA10 DGND 5 47pf,6.3V C156 47pf,6.3V C157 47pf,6.3V C160 47pf,6.3V C161 47pf,6.3V C162 47pf,6.3V C163 47pf,6.3V C164 47pf,6.3V C165 47pf,6.3V C166 47pf,6.3V C167 47pf,6.3V C168 47pf,6.3V C169 47pf,6.3V C170 47pf,6.3V C172 47pf,6.3V C171 47pf,6.3V C173 DGND 4 3 A Title BeagleBone Black HDMI Interface Size Document Number Rev B 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 10 of 11 2 1 5 4 3 2 1 CAUTION: USED ON BOARD P8 CAUTION: USED ON BOARD P9 1 2 D 3,8 MMC1_DAT6 3,8 MMC1_DAT2 3 TIMER4 3 TIMER5 3 GPIO1_13 3 EHRPWM2B 3 GPIO1_15 3 GPIO0_27 3 EHRPWM2A 3,8 MMC1_CLK 3,8 MMC1_DAT4 3,8 MMC1_DAT0 4,10 LCD_VSYNC 4,10 LCD_HSYNC 4,6,10 LCD_DATA14 4,6,10 LCD_DATA13 4,6,10 LCD_DATA12 4,6,10 LCD_DATA8 4,6,10 LCD_DATA6 4,6,10 LCD_DATA4 4,6,10 LCD_DATA2 4,6,10 LCD_DATA0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 MMC1_DAT7 3,8 MMC1_DAT3 3,8 TIMER7 3 TIMER6 3 GPIO1_12 3 GPIO0_26 3 GPIO1_14 3 GPIO2_1 3 MMC1_CMD 3,8 MMC1_DAT5 3,8 MMC1_DAT1 3,8 GPIO1_29 3 LCD_PCLK 4,10 LCD_DE 4,10 LCD_DATA15 4,6,10 LCD_DATA11 4,6,10 LCD_DATA10 4,6,10 LCD_DATA9 4,6,10 LCD_DATA7 4,6,10 LCD_DATA5 4,6,10 LCD_DATA3 4,6,10 LCD_DATA1 4,6,10 DGND VDD_3V3B VDD_5V SYS_5V 2 PWR_BUT 3 UART4_RXD 3 UART4_TXD 3 GPIO1_16 4 I2C1_SCL 4 I2C2_SCL 4 UART2_TXD 3 GPIO1_17 4 GPIO3_21 4 GPIO3_19 4,10 SPI1_D0 4,10 SPI1_SCLK 4 AIN4 4 AIN6 4 AIN2 4 AIN0 3 CLKOUT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DGND VDD_3V3B VDD_5V SYS_5V SYS_RESETn 3,9 GPIO1_28 3 EHRPWM1A 3 EHRPWM1B 3 I2C1_SDA 4 I2C2_SDA 4 UART2_RXD 4 UART1_TXD 4 UART1_RXD 4 SPI1_CS0 4,10 SPI1_D1 4 VDD_ADC AIN5 4 AIN3 4 AIN1 4 GPIO0_7 4 D FEMALE HEADER 2x23 FEMALE HEADER 2x23 GNDA_ADC C DGND DGND DGND DGND C EXPANSION HEADER EXPANSION HEADER VDD_3V3B R150 R151 R152 R153 R154 R155 C153 C154 10uF,10V 0.1uf,6.3V B DGND 2,4,10 I2C0_SCL 2,4,10 I2C0_SDA U7 Board ID 1 4 3 SCL VCC SDA VSS 2 VDD_3V3A C152 0.1uf,6.3V 5 WP 24LC32A 256KX8 WP R156 10K,1% DGND TP4 B TESTPT1 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 10K,1% 3 MMC0_DAT2 3 MMC0_DAT3 3 MMC0_CMD 3 MMC0_CLKO 3 MMC0_DAT0 3 MMC0_DAT1 3,4 MMC0_CD DGND P10 1 9 2 DAT2 GND 10 3 CD/DAT3 CD 11 4 CMD GND3 12 5 VDD GND4 13 6 CLOCK GND5 14 7 8 VSS GND6 DAT0 DAT1 microSDGGNNDD78 15 16 SCHA5B0200 DGND uSD CONNECTOR R157 10K,1% VDD_3V3B A A Title BeagleBone Black Expansion Headers, uSD.and EEPROM Size Document Number Rev B 450-5500-001 A5C Date: Wednesday, June 12, 2013 Sheet 11 of 11 5 4 3 2 1

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