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cadence virtoso 目前模拟仿真的强大软件,支持模拟、数字及数模混合的仿真分析,以及layout等功能。

Virtuoso Analog Design Environment Lecture Manual Version 5.1.41 February 10, 2005 © 1990-2005 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134, USA Cadence Trademarks 1st Silicon Success® Allegro® Assura™ BuildGates® Cadence® (brand and logo) CeltIC™ ClockStorm® CoBALT™ Conformal® Connections® Design Foundry® Diva® Dracula® Encounter™ Fire & Ice® First Encounter® FormalCheck® HDL-ICE® Incisive™ IP Gallery™ Nano Encounter™ NanoRoute™ NC-Verilog® OpenBook® online documentation library Orcad® Orcad Capture® Orcad Layout® PacifIC™ Palladium™ Pearl® PowerSuite™ PSpice® QPlace® Quest® SeismIC™ SignalStorm® Silicon Design Chain™ Silicon Ensemble® SoC Encounter™ SourceLink® online customer support Spectre® TtME® UltraSim® Verifault-XL® Verilog® Virtuoso® VoltageStorm® Other Trademarks All other trademarks are the exclusive property of their respective owners. Confidentiality Notice No part of this publication may be reproduced in whole or in part by any means (including photocopying or storage in an information storage/retrieval system) or transmitted in any form or by any means without prior written permission from Cadence Design Systems, Inc. (Cadence). Information in this document is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013. UNPUBLISHED This document contains unpublished confidential information and is not to be disclosed or used except as authorized by written contract with Cadence. Rights reserved under the copyright laws of the United States. Table of Contents Virtuoso Analog Design Environment Table of Contents Virtuoso Analog Design Environment Module 1 Introduction to the Analog Design Environment, Version 5.1.41 Topics in this Module ...................................................................................................... 1-3 Course Objectives ............................................................................................................ 1-5 Course Outline ................................................................................................................. 1-7 Class Schedule ................................................................................................................. 1-9 Getting Help................................................................................................................... 1-11 What’s New in 5.1.41 .................................................................................................... 1-13 Overview of Virtuoso Analog Design Environment ..................................................... 1-15 Design System Initialization Files ................................................................................. 1-17 Overview of the Design Framework II Environment .................................................... 1-19 Advantages of Using Design Framework II .................................................................. 1-21 The Command Interpreter Window (CIW) ................................................................... 1-23 Using a Form ................................................................................................................. 1-25 Initializing the Design Framework II Environment....................................................... 1-27 IC Design Flow, Front to Back ...................................................................................... 1-29 The Library Manager ..................................................................................................... 1-31 The Library Structure..................................................................................................... 1-33 Creating a New Library ................................................................................................. 1-35 Shared Technology Library ........................................................................................... 1-37 Technology File Stored in the Design Library .............................................................. 1-39 Overview of Circuit Simulation..................................................................................... 1-41 Types of Circuit Simulation Analyses ........................................................................... 1-43 Summary ........................................................................................................................ 1-45 Labs................................................................................................................................ 1-47 Lab 1-1 Getting Started............................................................................................ 1-47 Lab 1-2 Top-Down System Modeling ..................................................................... 1-47 Module 2 Schematic Entry Topics in this Module ...................................................................................................... 2-3 Schematic Entry Flow...................................................................................................... 2-5 Contents of a Schematic .................................................................................................. 2-7 Creating a New Cellview ................................................................................................. 2-9 Adding Component Instances ........................................................................................ 2-11 Updating Design Objects ............................................................................................... 2-13 Adding Sources and Ground.......................................................................................... 2-15 February 10, 2005 Cadence Design Systems, Inc. iii Virtuoso Analog Design Environment Table of Contents Pins................................................................................................................................. 2-17 Wires and Wire Labels .................................................................................................. 2-19 Interconnecting Components ......................................................................................... 2-21 Schematic Checking ...................................................................................................... 2-23 Schematic Checking Rules ............................................................................................ 2-25 Component Parameter Types......................................................................................... 2-27 Passing Parameters Through the Hierarchy................................................................... 2-29 Symbol Generation ........................................................................................................ 2-31 Characteristics of an Automatically Generated Symbol................................................ 2-33 Schematic Window Icons and Accelerator Keys........................................................... 2-35 Schematic Editor Command Summary.......................................................................... 2-37 Bindkeys (Accelerator Keys)......................................................................................... 2-39 Using a Hierarchy .......................................................................................................... 2-41 Labs................................................................................................................................ 2-43 Lab 2-1 Schematic Entry ......................................................................................... 2-43 Lab 2-2 Symbol Creation......................................................................................... 2-43 Lab 2-3 Building the Supply Circuit........................................................................ 2-43 Lab 2-4 Building the ampTest Design ..................................................................... 2-43 Lab Reference Material: Mouse Buttons ....................................................................... 2-45 Module 3 Analog Simulation Topics in this Module ...................................................................................................... 3-3 Important Features of the Simulation Window................................................................ 3-5 Analog Simulation Flow .................................................................................................. 3-7 Starting the Simulation Environment .............................................................................. 3-9 Setting the Simulator ..................................................................................................... 3-11 Setting the Model Libraries ........................................................................................... 3-13 Simulation Files ............................................................................................................. 3-15 Setting Design Variables ............................................................................................... 3-17 Choosing Analyses ........................................................................................................ 3-19 Choosing Analyses Details ............................................................................................ 3-21 Simulation Environment Options .................................................................................. 3-23 Simulator Options .......................................................................................................... 3-25 Probing the Schematic to Save Output Data.................................................................. 3-27 Reminder to Terminate Select “Outputs...” ................................................................... 3-29 Outputs Section of Simulation Window ........................................................................ 3-31 Netlisting........................................................................................................................ 3-33 Running the Simulation ................................................................................................. 3-35 Running Additional Simulations ................................................................................... 3-37 Control of Analyses for Simulation ............................................................................... 3-39 iv Cadence Design Systems, Inc. February 10, 2005 Table of Contents Virtuoso Analog Design Environment Additional Options Using ADE ..................................................................................... 3-41 Analog Default Options ................................................................................................. 3-43 Simulation States ........................................................................................................... 3-45 Stimulus Template ......................................................................................................... 3-47 Save Options .................................................................................................................. 3-49 Save Defaults and Save Session .................................................................................... 3-51 Infotimes ........................................................................................................................ 3-53 Infotimes Results ........................................................................................................... 3-55 Captab ............................................................................................................................ 3-57 Selecting the captab Option from ADE ......................................................................... 3-59 Labs................................................................................................................................ 3-61 Lab 3-1 Running Simulation.................................................................................... 3-61 Lab 3-2 Using the Stimulus Template ..................................................................... 3-61 Lab 3-3 Transient Operating Point Analysis, “infotimes”....................................... 3-61 Lab 3-4 Captab......................................................................................................... 3-61 Module 4 Simulation Results Display Tools Topics in this Module ...................................................................................................... 4-3 Overview of Simulation Display Tools ........................................................................... 4-5 WaveScan ........................................................................................................................ 4-7 The WaveScan Results Browser...................................................................................... 4-9 Selecting Signals............................................................................................................ 4-11 Plotting........................................................................................................................... 4-13 Data Ranging ................................................................................................................. 4-17 Parametric Data.............................................................................................................. 4-19 Plotting Options ............................................................................................................. 4-21 Tables (Tools—Table from Results Browser)............................................................... 4-25 Reloading Data .............................................................................................................. 4-27 Digital Signals................................................................................................................ 4-29 Saving and Printing Graphs and Data............................................................................ 4-31 Calculator....................................................................................................................... 4-33 Calculator Functions ...................................................................................................... 4-35 Calculator Filtering ........................................................................................................ 4-39 The Waveform Window (AWD) ................................................................................... 4-41 Waveform Window Features ......................................................................................... 4-43 Waveform Calculator..................................................................................................... 4-45 The Waveform Calculator (AWD Shown) .................................................................... 4-47 Postprocessing Data with the Waveform Calculator ..................................................... 4-49 Waveform Calculator, Special Functions Key .............................................................. 4-51 Controlling Schematic Label Displays .......................................................................... 4-53 February 10, 2005 Cadence Design Systems, Inc. v Virtuoso Analog Design Environment Table of Contents Annotating Simulation Information to the Schematic ................................................... 4-55 Labs................................................................................................................................ 4-57 Lab 4-1 Displaying Results and Using the Calculator with WaveScan .................. 4-57 Lab 4-2 Saving the Simulation Session ................................................................... 4-57 Lab 4-3 Displaying Interpreted Labels Near Schematic Components .................... 4-57 Lab 4-4 Annotating Simulation Results to the Schematic Window ........................ 4-57 Lab 4-5 The Waveform Calculator .......................................................................... 4-57 Lab Reference Material ................................................................................................. 4-59 Module 5 Analyzing Simulation Results Topics in this Module ...................................................................................................... 5-3 Print Engine ..................................................................................................................... 5-5 Printing the Results.......................................................................................................... 5-7 Results Display Window ................................................................................................. 5-9 Run Data Storage Directories ........................................................................................ 5-11 Backing Up Simulation Data Explicitly ........................................................................ 5-13 Selecting Results............................................................................................................ 5-15 Setting Plotting Options................................................................................................. 5-17 Annotating Data to the Waveform Window .................................................................. 5-19 Starting the Results Browser.......................................................................................... 5-21 The Results Browser ...................................................................................................... 5-23 Viewing Presimulation Text Data.................................................................................. 5-25 Interactive Postprocessing Tools ................................................................................... 5-27 Conditional Search and Display .................................................................................... 5-29 Setting Up a Conditional Search.................................................................................... 5-31 The Circuit Conditions Form ......................................................................................... 5-33 Device Check Interface to ADE .................................................................................... 5-35 Device Checking Setup.................................................................................................. 5-37 Editing Device Check .................................................................................................... 5-41 Device/Model/Primitive Tab ................................................................................... 5-41 Parameter Tab .......................................................................................................... 5-43 Expression Tab ........................................................................................................ 5-45 Device Checking Setup Options .................................................................................... 5-47 Simulation Output.......................................................................................................... 5-49 Device Check Violations Display.................................................................................. 5-51 Violations Display ......................................................................................................... 5-53 Display Info ............................................................................................................. 5-55 Sensitivity Analysis ....................................................................................................... 5-59 Setting Up Sensitivity Analysis ..................................................................................... 5-61 Viewing Sensitivity Results........................................................................................... 5-63 vi Cadence Design Systems, Inc. February 10, 2005 Table of Contents Virtuoso Analog Design Environment Spectre Sweep Feature................................................................................................... 5-65 Introduction to Stability Analysis .................................................................................. 5-67 Loop-Based Algorithm .................................................................................................. 5-69 The Device-Based Algorithm ........................................................................................ 5-71 Starting Stability Analysis ............................................................................................. 5-73 Stability Analysis Results .............................................................................................. 5-75 Labs................................................................................................................................ 5-77 Lab 5-1 Managing Simulation Results .................................................................... 5-77 Lab 5-2 Managing Simulation Data with the Results Browser ............................... 5-77 Lab 5-3 Viewing Circuit Conditions ....................................................................... 5-77 Lab 5-4 Using the Spectre Sweep Features ............................................................. 5-77 Lab 5-5 Stability Analysis ....................................................................................... 5-77 Lab 5-6 Device Checking Interface to ADE............................................................ 5-77 Lab Reference Materials ................................................................................................ 5-79 Module 6 SKILL and OCEAN Topics in this Module ...................................................................................................... 6-3 Overview of SKILL and OCEAN ................................................................................... 6-5 Introduction to SKILL ..................................................................................................... 6-7 Using SKILL Commands ................................................................................................ 6-9 Basic SKILL Statements................................................................................................ 6-11 Parentheses and Double Quotes..................................................................................... 6-13 Single Quote and Question Mark................................................................................... 6-15 Introduction to OCEAN................................................................................................. 6-17 Types of OCEAN Commands ....................................................................................... 6-19 Sample OCEAN Script .................................................................................................. 6-21 OCEAN Help ................................................................................................................. 6-23 Data Access Commands ................................................................................................ 6-25 Plotting Commands........................................................................................................ 6-27 Available OCEAN Aliases ............................................................................................ 6-29 Running OCEAN Interactively...................................................................................... 6-31 Creating OCEAN Scripts in ADE ................................................................................. 6-33 Loading OCEAN Scripts ............................................................................................... 6-35 Labs................................................................................................................................ 6-37 Lab 6-1 Using an OCEAN Script to Run a Simple Simulation............................... 6-37 Lab 6-2 Measuring PSRR and CMRR with OCEAN.............................................. 6-37 Lab 6-3 Introduction to SKILL................................................................................ 6-37 Lab 6-4 SKILL Development Tools ........................................................................ 6-37 February 10, 2005 Cadence Design Systems, Inc. vii Virtuoso Analog Design Environment Table of Contents Module 7 Parametric Analysis Topics in this Module ...................................................................................................... 7-3 Introduction to EDFM Design Tools ............................................................................... 7-5 EDFM Tool Usage........................................................................................................... 7-7 Overview of Parametric Analysis and Flow .................................................................... 7-9 Parametric Analysis Methodology................................................................................. 7-11 The Parametric Analysis Environment .......................................................................... 7-13 Parametric Plots ............................................................................................................. 7-15 Accessing the Parametric Analysis Data Structure........................................................ 7-17 Parametric Analysis on Model Parameters .................................................................... 7-19 Parametric Analysis in OCEAN .................................................................................... 7-21 Summary ........................................................................................................................ 7-23 Labs................................................................................................................................ 7-25 Lab 7-1 Running Parametric Analysis..................................................................... 7-25 Module 8 Corners Analysis Topics in this Module ...................................................................................................... 8-3 Corners Analysis Tool ..................................................................................................... 8-5 Corners Analysis Window ............................................................................................... 8-7 Adding a New Process ..................................................................................................... 8-9 Implementing Modeling Styles...................................................................................... 8-11 Single-Model Library Style ........................................................................................... 8-13 Multiple-Model Library Style........................................................................................ 8-15 Other Styles.................................................................................................................... 8-17 Corners Results .............................................................................................................. 8-19 Corners Results Window ............................................................................................... 8-21 Labs................................................................................................................................ 8-23 Lab 8-1 Using the Corners Analysis Tool ............................................................... 8-23 Module 9 Monte Carlo Analysis Topics in this Module ...................................................................................................... 9-3 Overview of Monte Carlo Analysis ................................................................................. 9-5 Simulation Using Process Distributions .......................................................................... 9-7 Example of Monte Carlo Using Simple LPF................................................................... 9-9 Monte Carlo Analysis Environment .............................................................................. 9-11 Support of Spectre Direct .............................................................................................. 9-13 Spectre Direct Statistical Modeling ............................................................................... 9-15 Statistical Modeling ....................................................................................................... 9-17 Other Features in Monte Carlo ...................................................................................... 9-19 viii Cadence Design Systems, Inc. February 10, 2005 Table of Contents Virtuoso Analog Design Environment Monte Carlo Results Analysis ....................................................................................... 9-21 Filtering Output Data ..................................................................................................... 9-25 Summary ........................................................................................................................ 9-27 Labs................................................................................................................................ 9-29 Lab 9-1 Monte Carlo Analysis................................................................................. 9-29 Module 10 Optimization Analysis Topics in this Module .................................................................................................... 10-3 Introduction to the Circuit Optimizer Tool.................................................................... 10-5 Optimization Analysis Flow .......................................................................................... 10-7 Optimization Computational Flow ................................................................................ 10-9 Analog Circuit Optimization Option Form.................................................................. 10-11 Optimization Algorithms ............................................................................................. 10-13 Adding Goals ............................................................................................................... 10-15 Design Variables Menu ............................................................................................... 10-17 Options Menu .............................................................................................................. 10-19 Curve Fitting ................................................................................................................ 10-21 Curve Fitting to User-Defined Waveforms ................................................................. 10-25 Iteration History ........................................................................................................... 10-27 Plotting Options ........................................................................................................... 10-29 OCEAN Interface ........................................................................................................ 10-31 Labs.............................................................................................................................. 10-33 Lab 10-1 Running Optimization Analysis ............................................................. 10-33 Module 11 Component Description Format (CDF) Topics in this Module .................................................................................................... 11-3 CDF Overview ............................................................................................................... 11-5 Types of CDF................................................................................................................. 11-7 Levels of the CDF.......................................................................................................... 11-9 The CDF User Interface Form ..................................................................................... 11-11 Editing Component Parameters in the CDF ................................................................ 11-13 Editing Simulation Information in the CDF ................................................................ 11-15 Summary ...................................................................................................................... 11-19 Labs.............................................................................................................................. 11-21 Lab 11-1 The CDF User Interface ......................................................................... 11-21 Lab 11-2 CDF Effects in Simulation ..................................................................... 11-21 February 10, 2005 Cadence Design Systems, Inc. ix Virtuoso Analog Design Environment Table of Contents Module 12 Macromodels, Subcircuits, and Inline Subcircuits Topics in this Module .................................................................................................... 12-3 Overview........................................................................................................................ 12-5 Advantages of Inline Subcircuits ................................................................................... 12-7 Macromodels and Subcircuits........................................................................................ 12-9 Library Requirements to Use Subcircuits .................................................................... 12-11 Inline Subcircuits ......................................................................................................... 12-13 Inline Subcircuit Example: Parasitic Devices.............................................................. 12-15 Inline Subcircuit Example: Parasitic Estimation ......................................................... 12-17 Generalized Binning .................................................................................................... 12-19 Using Inlines with the Virtuoso Analog Design Environment .................................... 12-21 Labs.............................................................................................................................. 12-23 Lab 12-1 Creating a Parasitic Transistor Model .................................................... 12-23 Lab 12-2 Using Subcircuit Cells............................................................................ 12-23 Lab 12-3 Adding a Subcircuit Representation....................................................... 12-23 Module 13 The Hierarchy Editor Topics in this Module .................................................................................................... 13-3 Applications for the Hierarchy Editor ........................................................................... 13-5 Overview of the Hierarchy Editor ................................................................................. 13-7 Creating a Configuration ............................................................................................... 13-9 The Hierarchy Editor Window .................................................................................... 13-11 Selecting Views with the HED .................................................................................... 13-13 HED Tree Format ........................................................................................................ 13-15 Opening a Configured Schematic ................................................................................ 13-17 Synchronizing the Configured Schematic ................................................................... 13-19 Summary ...................................................................................................................... 13-21 Labs.............................................................................................................................. 13-23 Lab 13-1 Creating a Configuration File with the Hierarchy Editor....................... 13-23 Lab 13-2 Running a Simulation with Subcircuits.................................................. 13-23 Lab 13-3 Rerunning Simulation with the Schematic View ................................... 13-23 Module 14 Inherited Connections Topics in this Module .................................................................................................... 14-3 Applications of Inherited Connections .......................................................................... 14-5 Features of Inherited Connections ................................................................................. 14-7 Defining Inherited Connections..................................................................................... 14-9 Setting a Net Expression.............................................................................................. 14-11 Override Default with the netSet Property................................................................... 14-13 x Cadence Design Systems, Inc. February 10, 2005 Table of Contents Virtuoso Analog Design Environment Netlisting with Inherited Connections ......................................................................... 14-15 Evaluating Net Expressions ......................................................................................... 14-17 Labs.............................................................................................................................. 14-19 Lab 14-1 Inherited Connections ............................................................................ 14-19 Lab 14-2 Using Inherited Connections with the ampTest Design......................... 14-19 Module 15 Overview of Parasitic Simulation Topics in this Module .................................................................................................... 15-3 Background .................................................................................................................... 15-5 Overview of Parasitic Analysis...................................................................................... 15-7 Supported Layout Software ........................................................................................... 15-9 What Happens in Parasitic Simulation?....................................................................... 15-11 An Actual Parasitic Simulation Flow .......................................................................... 15-13 Summary ...................................................................................................................... 15-15 Labs.............................................................................................................................. 15-17 Lab 15-1 Simulating a Schematic Without Parasitics ........................................... 15-17 Module 16 Assura Parasitic Simulation Flow Topics in this Module .................................................................................................... 16-3 Assura in ADE ............................................................................................................... 16-5 What’s New in Assura 5.1.41 ........................................................................................ 16-7 Assura Flow in Virtuoso Analog Design Environment ................................................. 16-9 Menu Changes for Assura............................................................................................ 16-11 Parasitic Show/Hide within ADE ................................................................................ 16-13 Accurate Assura Backannotation................................................................................. 16-15 Total R Values Not Shown Until After DC Simulation .............................................. 16-17 Assura Design Flow..................................................................................................... 16-19 Design Schematic ........................................................................................................ 16-21 Design Layout.............................................................................................................. 16-23 Accessing the Assura Commands................................................................................ 16-25 LVS in Assura.............................................................................................................. 16-27 Run RCX in Assura ..................................................................................................... 16-29 Assura RCX Output ..................................................................................................... 16-31 Creating av_analog_extracted ..................................................................................... 16-33 Create Test Fixture Schematic and Configuration....................................................... 16-35 Choose Views in Configuration................................................................................... 16-37 Running Simulation ..................................................................................................... 16-39 Waveform Analysis ..................................................................................................... 16-41 February 10, 2005 Cadence Design Systems, Inc. xi Virtuoso Analog Design Environment Table of Contents Labs.............................................................................................................................. 16-43 Lab 16-1 Parasitic Simulation Flow ...................................................................... 16-43 Lab 16-2 Running a Simulation without Parasitics ............................................... 16-43 Lab 16-3 Running Simulation with Parasitics ....................................................... 16-43 Lab 16-4 Improved Bus Probing ........................................................................... 16-43 Appendix A Diva Parasitic Simulation Flow Topics in this Module ..................................................................................................... A-3 Diva Parasitic Extraction ................................................................................................ A-5 Diva Design Flow with Parasitic Simulation.................................................................. A-7 Design Schematic ........................................................................................................... A-9 Design Layout............................................................................................................... A-11 Extraction and LVS ...................................................................................................... A-13 Building analog_extracted ............................................................................................A-15 Selective Parasitic Simulation ...................................................................................... A-17 Backannotation ............................................................................................................. A-19 Parasitic Probing ........................................................................................................... A-21 Create Test Fixture Schematic and Configuration........................................................ A-23 Choose Views in Configuration.................................................................................... A-25 Running Simulation ...................................................................................................... A-27 Waveform Analysis ...................................................................................................... A-29 Layout Waveform Analysis .......................................................................................... A-31 Schematic Waveform Analysis..................................................................................... A-33 Labs............................................................................................................................... A-35 Lab A-1 Simulating a Schematic with Parasitics Using the Diva Layout Flow..... A-35 Appendix B Match Analysis, dcmatch Topics in this Module ......................................................................................................B-3 Overview of Device Mismatch ........................................................................................B-5 Design Considerations .....................................................................................................B-7 Layout Matching..............................................................................................................B-9 Special Modeling Requirements for dcmatch................................................................B-11 Starting the dcmatch Analysis .......................................................................................B-13 dcmatch Analysis Selection ...........................................................................................B-15 Labs................................................................................................................................B-17 Lab B-1 dcmatch......................................................................................................B-17 xii Cadence Design Systems, Inc. February 10, 2005 Table of Contents Virtuoso Analog Design Environment Appendix C Advanced Topics in ADE Topics in this Module ......................................................................................................C-3 Overview of Advanced Topics ........................................................................................C-5 Introduction to Verilog-A ................................................................................................C-7 The Verilog-A Module ....................................................................................................C-9 Advantages of Verilog-A...............................................................................................C-11 Introduction to Mixed Signal Design Environment.......................................................C-13 Advantages of Mixed Signal Design Environment .......................................................C-15 Mixed Signal Design Environment and Verilog-A .......................................................C-17 Labs................................................................................................................................C-19 Lab C-1 Verilog-A Overview ..................................................................................C-19 February 10, 2005 Cadence Design Systems, Inc. xiii Virtuoso Analog Design Environment Table of Contents xiv Cadence Design Systems, Inc. February 10, 2005 ® 1 Introduction to the Analog Design Environment, Version 5.1.41 Module 1 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 1-2 Topics in this Module ■ Course objectives ■ Course outline ■ Class schedule ■ Getting help, technical support, and documentation ■ What’s new in 5.1.41 ■ The Design Framework II design environment ■ Accessing design tools ■ Creating a library ■ Creating cells and cell views ■ Schematic capture ■ Analog simulation ■ Analyses ■ Summary Introduction to the Analog Design Environment, Version 5.1.41 1-3 Terms and Definitions CDSDoc CIW command line text field cyclic field library Library Manager Virtuoso Schematic Editor cell cell view instance pin bindkey Cadence® online help tool that uses a Netscape browser interface. Command interpreter window. Interface used to access DFII applications. A line buffer in the CIW that accepts SKILL-based commands. An area on a tool window where the user provides data. Set of selectable options in a tool window, denoted by a small rectangle. A set of design directories that includes ‘cells’ and ‘cellviews’. A Cadence tool that allows user to browse and edit a design library. Schematic editor and symbol generation tool in DFII. A basic unit of a design hierarchy described by cell views. A specific view of a cell that includes schematic, symbol, or layout. A uniquely named placement of a symbol onto a schematic. A connection point on a schematic and symbol used for accessing signals. A predefined key on the keyboard that invokes a preselected command, sometimes called an “accelerator”. 2/10/05 Virtuoso Analog Design Environment 1-4 Course Objectives ■ Learn how to create schematics, symbols, and a design hierarchy ■ Set up and run analog simulations ■ Analyze simulation results ■ Evaluate sensitivities and mismatches to improve circuit performance. ■ Run Corners, Monte Carlo, and Optimization tools to improve yield ■ Create and use OCEAN scripts and SKILL to set up and run simulations ■ Understand the Component Description Format (CDF) ■ Create configurations with the Hierarchy Editor (HED) ■ Use subcircuits and macromodels ■ Run the parasitic simulation flow ■ Use advanced tools to solve special problems Introduction to the Analog Design Environment, Version 5.1.41 1-5 Course Objectives The objective of this class is to provide both instruction and materials on using the Virtuoso Analog Design Environment that will enable you to use the entire front-to-back design flow. 2/10/05 Virtuoso Analog Design Environment 1-6 Course Outline 1 Introduction to the Analog Design Environment, Version 5.1.41 2 Schematic Entry 3 Analog Simulation 4 Simulation Results Display Tools 5 Analyzing Simulation Results 6 SKILL and OCEAN 7 Parametric Analysis 8 Corners Analysis 9 Monte Carlo Analysis 10 Optimization Analysis 11 Component Description Format (CDF) 12 Macromodels, Subcircuits, and Inline Subcircuits 13 The Hierarchy Editor 14 Inherited Connections 15 Overview of Parasitic Simulation 16 Assura Parasitic Simulation Flow Appendixes: A Diva Parasitic Simulation Flow B Match Analysis, dcmatch C Advanced Topics in ADE Introduction to the Analog Design Environment, Version 5.1.41 1-7 Course Outline The Virtuoso Analog Design Environment classroom series is an intensive, fast-paced, 4-day class on using Cadence design software to run analog circuit simulations. This course comprises 16 modules, including both lectures and corresponding lab activities. Module 15 provides an overview of the Parasitic Simulation theory and flow, followed by Module 16, Assura Parasitic Simulation Flow. Appendix A, Diva Parasitic Simulation Flow, will be taught when conditions require this flow to be used. The selection of Diva or Assura will be based on the specific classroom and work site circumstances. Appendix B discusses Match Analysis (dcMatch) and Appendix C, Advanced Topics in ADE, provides a brief overview of Verilog-A and the Mixed Signal Design Environment. 2/10/05 Virtuoso Analog Design Environment 1-8 Class Schedule Day 1 1 Introduction to the Analog Design Environment, Version 5.1.41 2 Schematic Entry 3 Analog Simulation 4 Simulation Results Display Tools Day 2 5 Analyzing Simulation Results 6 SKILL and OCEAN 7 Parametric Analysis 8 Corners Analysis 9 Monte Carlo Analysis Day 3 10 Optimization Analysis 11 Component Description Format (CDF) 12 Macromodels, Subcircuits, and Inline Subcircuits Day 4 13 The Hierarchy Editor 14 Inherited Connections 15 Overview of Parasitic Simulation 16 Assura Parasitic Simulation Flow Class Evaluations Introduction to the Analog Design Environment, Version 5.1.41 1-9 Class Schedule The class schedule listed above is the recommended schedule for the standard 4-day classroom series of ADE 5.1.41. Private classes taught at customer facilities may require adjustments or modifications to this schedule. The class schedule is intended to adequately cover all topics of the ADE course. As such, each day covers 4 to 5 modules. Each module requires 1 to 2 hours to complete both the lecture presentation and the lab activity. To ensure adequate coverage of the lecture material, the instructor may elect to defer answers to detailed questions that are asked during the lecture. The instructor may also deviate from course schedule due to conditions that cause unexpected delays or other circumstances. In any case, the instructor will attempt to answer relative questions in a timely manner or obtain the answer for the student as soon as possible. 2/10/05 Virtuoso Analog Design Environment 1-10 Getting Help You can get help with Cadence software from the following sources: ■ Help button on forms and windows ■ Cadence online documentation (CDSDoc) ■ Education Services training manuals ■ SourceLink® online customer support ■ Customer Response Center (CRC) Introduction to the Analog Design Environment, Version 5.1.41 1-11 Getting Help Online Help Cadence reference manuals and online help files for each product are installed automatically when installing the product. Hard copies of the reference manuals are available from Cadence. All these online documents are part of the online help system, which can be accessed as follows: ■ View relevant product information by clicking the help button on windows and forms. Use this information to complete a form or what can be done in the window. ■ Start the CDSDoc documentation from a UNIX shell by typing cdsdoc& at the command line and search through all Cadence reference manuals and online help systems installed with each product. Also, use CDSDoc to print the reference manuals entirely or just the relevant material. Other Means of Getting Information ■ With a software maintenance agreement, subscribe to the SourceLink online support system and view known problems and solutions or communicate with other users. The SourceLink system is accessible via the internet. To open an account, send email to support@cadence.com. ■ Training manuals, like this one, can supplement reference manuals. ■ When the above information is insufficient, call the Customer Response Center. ❑ North America 1(877)CDS-4911 or 1(877)237-4911 2/10/05 Virtuoso Analog Design Environment 1-12 What’s New in 5.1.41 ■ Spectre device checking interface ■ WaveScan integration ■ UltraSim integration ■ Third-party OASIS integration ■ Parasitic resimulation flow Introduction to the Analog Design Environment, Version 5.1.41 1-13 What’s new in 5.1.41 Spectre Device Checking: This feature allows engineers to specify rules governing safe operating areas of devices on a primitive, a model, or an instance basis. WaveScan Integration: WaveScan is a new waveform viewing tool that is a drop-in replacement for the Analog Waveform Display (AWD) tool. WaveScan is set as the default display and provides performance and capability improvements like trace-legend visibility, X-axis parametric sweep swapping, and the ability to export graphs in .bmp, tiff, and .png formats. UltraSim Integration: UltraSim is now directly integrated into ADE. UltraSim is a hierarchical simulator designed for verification of analog and mixed-signal circuits. UltraSim is not covered in this course. Third-Party OASIS integration: OASIS has been updated to allow third-party simulators to take advantage of Corners capability. Parametric Resimulation Flow: Greatly enhanced in 5.1.41, the parametric resimulation flow has been rewritten to improve usability and limit previous restrictions concerning Assura. You may now backannotate both node voltages and device operating points onto schematics. New capability for parasitic resistance annotation has been added as well. 2/10/05 Virtuoso Analog Design Environment 1-14 Overview of Virtuoso Analog Design Environment The Virtuoso Analog Design Environment is a software tool set within Design Framework II that is used to set up and run analog simulations. The Virtuoso Analog Design Environment also accesses and views the simulation results. The Virtuoso Analog Design Environment allows you to: ■ Choose the simulator host ■ Choose the type of analysis: ac, dc, transient, parametric, sensitivity, etc. ■ Set design variables: Vdd, frequency, Cout, etc. ■ Append model files and include files ■ Netlist and run simulations ■ Quickly alter the simulation setup and rerun the simulation ■ Plot simulation results in the Waveform display tool ■ Evaluate simulation results using waveform expressions ■ Run multiple simulation tools: Corners, Monte Carlo, Optimizer, etc. ■ Automatically set up, save, and run OCEAN scripts Introduction to the Analog Design Environment, Version 5.1.41 1-15 Overview of the Virtuoso Analog Design Environment The Virtuoso Analog Design Environment is a set of software design tools used to set up, control, and run circuit simulations. ADE allows you to choose the simulator host, set design variables, select model files, and to select analyses to add, modify, or delete from next simulation run. The Virtuoso Analog Design Environment provides a user-friendly graphical interface that includes pull-down menus and icons for making fast and easy changes and also provides control for accessing the simulation results and displaying the results to the waveform display tool. The results can be entered into other tools for waveform processing or to obtain specific data using expressions. The Virtuoso Analog Design Environment provides access to multiple simulation tools like Corners, Monte Carlo, and the Circuit Optimizer. ADE also allows you to automatically set up, save, and run OCEAN scripts. 2/10/05 Virtuoso Analog Design Environment 1-16 Design System Initialization Files Login icfb & icms & msfb & Operating System Environment Window System Window Manager Design Framework II ( IC - 5.1.41 ) Analog Design Environment, schematic capture tools, layout, and verification software. .cshrc .login .cdsenv .cdsinit cds.lib Introduction to the Analog Design Environment, Version 5.1.41 1-17 Design System Initialization Files There are some design system initialization files that configure the operating system environment. For example, the .cshrc and .login files configure the UNIX environment when you log in and start a UNIX application. The initialization file, .cdsinit, customizes the Virtuoso Analog Design Environment. The cds.lib file sets the paths to the libraries. These files, along with the .cdsenv file, are discussed later. For more information on configuring your operating system environment for the Virtuoso Analog Design Environment, consult the Cadence Design Framework II Configuration Information guide. 2/10/05 Virtuoso Analog Design Environment 1-18 Overview of the Design Framework II Environment Schematic Capture & Symbol Editor Schematic Editor 2 Window Edit Schematic Update Design Setup Simulation Control, Simulation Results, Waveforms, and Expressions Component Description Parasitic Simulation and Backannotation The Framework Layout Verification WinFdraomweEwdoiTLrtkaoyoMoluastMskasLkayLoauytou3t R: 5 Physical Design Introduction to the Analog Design Environment, Version 5.1.41 1-19 Overview of the Design Framework II Environment The Virtuoso Analog Design Environment is a set of design tools that operate within Design Framework II. Design Framework II is the underlying structure for Cadence design tools for schematic capture, analog simulation, and layout. It provides a single integrated environment for accessing all tools and design data, including the ability to: ■ Access to the Command Interrupter Window (CIW) using icfb, icms, or msfb. ■ Use the Library Manager Tool to browse design libraries and open cell views. ■ Create new libraries, cells, and cell views. ■ Start or edit a schematic view or symbol view. ■ Start or edit a layout design. ■ Run layout verification. ■ Start the Virtuoso Analog Design Environment and run simulations. ■ Access simulation results directly using the Results Browser. ■ Run OCEAN scripts. 2/10/05 Virtuoso Analog Design Environment 1-20 Advantages of Using Design Framework II ■ Common software environment for using schematic capture, simulation, layout, and design verification ■ Easy-to-learn, consistent user interface ■ Similar appearance between most forms and windows ■ Communication between software tools within the DFII environment ■ Tool windows remain open while running other applications ■ Data can be “backannotated” ❏ From layout to schematic ❏ From simulation to schematic ❏ From simulation to layout ■ Applications may be customized or automated using SKILL or the OCEAN command language Introduction to the Analog Design Environment, Version 5.1.41 1-21 Advantages of Using Design Framework II The Cadence Design Framework II environment is an integrated design environment. An integrated environment means that numerous tools and applications operate together. For Design Framework II the environment provides schematic capture, simulation control, netlist generator, circuit simulator, waveform display, layout and verification tools. For the design software tools, DFII provides: ■ Consistent user interface Analog applications in the design framework have the same “look and feel.” Menu items are often in the same place in every application. ■ Consistent database A consistent database stores all design information. Tools share data in real time so long formalized translations between tools are not needed. The DFII environment also saves time during schematic to layout verification, because it updates layout geometries as the schematic component parameters change. ■ Cooperating tools Applications run concurrently, with results available to all other tools, eliminating the need to open and close applications when changing tool contexts. For example, update and simulate a schematic without restarting the simulation environment. Updates are known to the simulation window as soon as they are made in the schematic entry window. 2/10/05 Virtuoso Analog Design Environment 1-22 The Command Interpreter Window (CIW) Enter: icfb &, icms &, or msfb & Pull down menus Text Field (Enter SKILL Commands) Output Area Prompt Line Mouse Button Cues Introduction to the Analog Design Environment, Version 5.1.41 1-23 The Command Interpreter Window (CIW) The Command Interpreter Window (CIW) is at the heart of the framework system. Use this window to access framework-based applications. System and error messages from applications are reported in this window. ■ Output Area The output area displays a running history of the commands used with their results. For example, it issues a status message when a cell library is opened. This data is saved in the Log File whose path appears as the application title of the CIW. Use scroll bars to view previous output pane data without having to resize the CIW. ■ Text Entry Field Enter Cadence SKILL commands in this area. Every pull-down menu command in the Design Framework II environment has an equivalent SKILL command. Advanced users can define and execute their own SKILL commands by entering them here. ■ Prompt Line The prompt line at the bottom of the CIW indicates the next step when carrying out a command executed in any Design Framework II application window. ■ Mouse Button Cues Tells which mouse button to push to execute a command in a Design Framework II window. 2/10/05 Virtuoso Analog Design Environment 1-24 Using a Form A Sample Form OK Cancel Defaults Apply Help Template File Run Directory Load Save Library Browser . Library Name classLib Top Cell Name View Name mux2 Output File layout Output Show Messages Stream DB Library Version 5.1 ASCII Dump Text entry area Toggle Button Cyclic Field Radio Button Introduction to the Analog Design Environment, Version 5.1.41 1-25 Using a Form Forms provide a place to enter the information required by a command. The top of the form has a title bar and a set of banner buttons. The body of the form contains prompts that indicate which option is being set. Next to the prompt is one of the following: ■ radio button, for choosing one of several options ■ text entry area, for typing information ■ toggle button, for turning options on or off ■ cyclic field, for choosing one of many options. Initially only one option is shown. Move the pointer to the field and hold down the left mouse button, the other options appear. The form might also have buttons such as Browse, which shows a browser window, or More Options, which displays another form. Change of an entry on a form is disabled when the name appears in gray instead of black, and the text entry area is shaded. ■ Press the Tab key or mouse to move to the next text entry field. ■ Use the left and right arrows on the keyboard to move the cursor in a text entry field. Press Control-a to go to the beginning of a line; Control-e to go to the end of a line; Control-u to erase to the beginning of a line. 2/10/05 Virtuoso Analog Design Environment 1-26 Initializing the Design Framework II Environment The Design Framework II software reads your .cdsinit file at startup to set up your environment. The .cdsinit file: ■ Sets user-defined bindkeys when the Design Framework II environment is started. ■ Redefines system-wide defaults. ■ Contains SKILL commands. The search order for the .cdsinit file is: ■ /tools/dfII/local ■ the current directory ■ the home directory Here is the path to a sample .cdsinit file: /tools/dfII/samples/artist/cdsinit Introduction to the Analog Design Environment, Version 5.1.41 1-27 Initializing the Design Framework II Environment Start the Design Framework II environment, it reads the .cdsinit file to set up your configuration. The search order for the .cdsinit file is /tools/dfII/local, the current directory, and finally the home directory. When a .cdsinit file is found, the search stops unless a command in a .cdsinit file reads other user files. The .cdsinit file is a text file written in SKILL. A statement in a .cdsinit file can load user-defined bindkeys. Another statement might set Waveform Window defaults. A sample .cdsinit file included with the software contains examples of statements to copy into your own .cdsinit files. It has very detailed comments about command usage. This sample is located at /tools/dfII/cdsuser/.cdsinit. An additional sample .cdsinit file exists for analog designers at /tools/dfII/samples/artist/cdsinit. The Installation Path The Design Framework II software product hierarchy is discussed in detail in the Cadence Design Framework II Configuration Information guide. 2/10/05 Virtuoso Analog Design Environment 1-28 IC Design Flow, Front to Back System Level Design: Product definition, System specifications, Interface definitions, Behavioral simulations Library Manager Schematic Capture AHDL Verilog-A ADE Circuit Simulation Technology Selection: Process selection, Device Models, Layer definition, Layout rules, Primitives Library Manager Technology Files Component Level Design: Circuit topology, Device geometry, Component values, Symbol generation Library Manager Schematic Capture Circuit Analysis: Circuit Simulation, Design Corrections, Optimization, Verify Corners Library Manager Schematic Capture ADE Circuit Simulation System Integration: Schematic Hierarchy, Mixed-Level Simulations Physical Design: Layout, Layout Hierarchy Library Manager Hierarchy Editor ADE Verilog-A Circuit Simulation Library Manager Diva or Assura Introduction to the Analog Design Environment, Version 5.1.41 Back End Verification: LVS, DRC, Parasitic Extraction, Parasitic Simulation Library Manager Diva or Assura Hierarchy Editor ADE Circuit Simulation Design Data Out 1-29 IC Design Flow, Front to Back The graphical flow above shows a Front to Back design flow for integrated circuits or related system design. The blocks show the major steps or design categories. The text below each block shows the software tools used in the corresponding design steps. ■ At the front end, the product, device or system is defined. The system-level specifications are used for behavioral simulation of the system. ■ A fabrication process or technology is selected. ■ A schematic of a specific block is captured. ■ The design of the circuit is simulated. If needed, the circuit is redesigned to achieve specified goals. ■ The circuit is integrated into a hierarchy. The hierarchy is then simulated. ■ Physical design or layout capture of the circuit is completed. The layout of the hierarchy is then completed. ■ Back end verification of the layout includes design rule checks, layout versus schematic checks, and parasitic extraction. The extracted parasitics are “backannotated” to the schematic for parasitic simulation using the circuit simulation software. 2/10/05 Virtuoso Analog Design Environment 1-30 The Library Manager The Library Manager is a graphical data management tool. Object Sensitive Menus A library in the cds.lib file Tools—Library Manager Introduction to the Analog Design Environment, Version 5.1.41 1-31 The Library Manager The Library Manager provides a convenient way to browse libraries containing cells and cell views. The most common use is to display the contents of libraries graphically. Other functionality includes renaming, copying, specifying permissions for, creating categories for, deleting, and viewing properties of design data. Use the Library Manager to create cells and views, to edit or read a design, and to access the design manager. The illustration above shows a fully expanded library. Initially, the Library Manager lists only the library names that are set in the cds.lib file. This file contains the paths to the libraries used in the design session, including example libraries provided by Cadence, such as analogLib and basic. Expand design data with Object Sensitive Menus (OSM) or with the mouse. To expand data, point at the word that represents the data in the Library Manager and choose the appropriate mouse button or menu command. 2/10/05 Virtuoso Analog Design Environment 1-32 The Library Structure Library Training Cell VCO Symbol View Tools—Library Manager... Schematic View Introduction to the Analog Design Environment, Version 5.1.41 1-33 The Library Structure ■ Library A library is a collection of cells. The library also contains all the different views associated with each of the cells. Reference libraries typically contain well-characterized cells that can be instantiated in many different designs. Examples are the analogLib and basic libraries. Design libraries contain cells currently under development by a particular user, group, or for a particular design project. ■ Cells A cell is a logical component in your library. It can be a building block such as a VCO or amplifier. It can also be the top level chip name. ■ Views A view is a particular representation of a cell such as a layout, symbol, or schematic. An application tool, such as Virtuoso Schematic Editor, creates a view. Although a chip can include many levels of cell hierarchy, none of the hierarchical complexity is reflected in the libraries. A library is a flat collection of cells. Details of the design hierarchy exist inside the views that contain instances of other cells. The library treats all cells the same. 2/10/05 Virtuoso Analog Design Environment 1-34 Creating a New Library In the CIW or the Library Manager, select File—New—Library. ■ Specify the library name and path. ■ Specify the design manager to use. ■ For Physical Design and Verification, specify the ASCII technology file or technology file library to be attached to the new library. The new library is entered into the cds.lib file. Introduction to the Analog Design Environment, Version 5.1.41 1-35 Creating a New Library When creating library, use a form to specify the library name and path, the design manager to use, and the technology file to attach to the library. ■ Technology File Contents The technology file is a large data file that specifies all of the technology-dependent parameters associated with that particular library. Design rules, symbolic device definitions, and parasitic values are some of the technology-specific parameters common to all cells in a library. ■ cds.lib File The software automatically updates the cds.lib file when creating a library through the CIW’s File—New—Library command, when copying one library to another name, or renaming a library. This file contains the paths to all of the libraries used in the design session, and can be accessed through CIW’s Tools—Library Path Editor command. 2/10/05 Virtuoso Analog Design Environment 1-36 Shared Technology Library This example shows several libraries sharing the same technology file library. Technology cellTechLib Library drc.rul techfile.cds compare.rul extract.rul symbolic devices Design Library Pcells ntransistor ptransistor Design Library master mux2 layout layout symbol layout Introduction to the Analog Design Environment, Version 5.1.41 1-37 Shared Technology Library Share technology file information between different libraries. Create a technology file library and attach your design libraries to the technology file library. Use the Technology File—Attach To command in the CIW to attach the design library to the technology file library. Sharing a technology file library with other libraries will share the same Assura® rules, layer information, and symbolic devices amongst a group of libraries. Sharing a technology file can help reduce the size of the design libraries, because the technology information is stored at only one location. ■ techfile.cds file The techfile.cds file contains the binary technology file. This file name must be called techfile.cds. ■ Assura Rules The Assura rules are stored as separate ASCII files. For each type of rule (DRC, Extract, and Compare), there is an Assura rules file. ■ Symbolic Devices The symbolic devices such as contacts, pins, transistors, and wire information can be shared between libraries. 2/10/05 Virtuoso Analog Design Environment 1-38 Technology File Stored in the Design Library This example shows a technology file being stored inside a design library and not being shared with other libraries. Design Library master drc.rul extract.rul compare.rul techfile.cds mux2 symbolic devices symbol layout Introduction to the Analog Design Environment, Version 5.1.41 1-39 Technology File Stored in the Design Library A library can have its own technology file information that is stored inside of the library. 2/10/05 Virtuoso Analog Design Environment 1-40 Overview of Circuit Simulation Design Hierarchy or Test Circuit (schematic view) Stimulus: analogLib: vpulse - or - stimulus file - or - schematic Transistor Level Schematic (symbol view) Schematic of amplifier Load analogLib: cap res - or schematic User Inputs Virtuoso ADE Setup simulator Modify Design Variables Choose Analyses Select Model Files Netlist and Run Simulation Plot Simulation Results View waveforms Evaluate expressions OUT: IN: Circuit Simulator Spectre (used in this class), Spectre/Verilog, etc. IN: Netlist, temperature, etc. OUT:.psf,.log, etc. Introduction to the Analog Design Environment, Version 5.1.41 1-41 Overview of Circuit Simulation The block diagram above shows an overview of the circuit simulation process. ■ The circuit schematic is captured or edited. ■ A symbol of the schematic is placed in a hierarchy or test circuit schematic. ■ The Virtuoso Analog Design Environment is started. ■ The user provides input to the Virtuoso Analog Design Environment to set up and control what information is netlisted and then sent to the circuit simulator. ■ The user used the Virtuoso Analog Design Environment to run the circuit simulator. ■ The user selects the information to be printed, plotted, or to be analyzed. ■ The user modifies the setup or edits the schematic for the next simulation. 2/10/05 Virtuoso Analog Design Environment 1-42 Types of Circuit Simulation Analyses Circuit Simulation Software Spectre Single Point Single Sweep Multiple Sweep dc dcop sensitivity mismatch RF Analyses ac transient dc sweep ac sweep noise parametric corners Monte Carlo optimization RF Spectral Analysis Introduction to the Analog Design Environment, Version 5.1.41 1-43 Types of Circuit Simulation Analyses The diagram shows the variety of analyses available with analog circuit simulation. Single-point analyses often include the steady state dc solution of the circuit. The operating point dcop solves the operating point device parameters and low frequency gain of the circuit. Single-sweep analyses often include ac and transient analysis. The ac analysis is a frequency sweep of the circuit. The transient analysis is a time sweep of the circuit operation to a time domain stimulus. A dc sweep analysis is a multiple point dc analysis performed while stepping a parameter such as temperature, design variable, or a model parameter. Solving the dc gain of an amplifier as a function of temperature is often called a temperature sweep. Solving the gain of an amplifier as a function of a model parameter is called a parametric sweep. It is also possible to sweep the ac gain of an amplifier at a specified frequency of the amplifier over temperature. This is called an ac temperature sweep. Multiple sweep analyses refer to sweeping one variable and then stepping another variable between successive sweeps. In parametric analysis, the two or more variables are altered at specified intervals. In the Corners analysis, variables are specified at named corners. In the Monte Carlo analysis, the parameters are altered using random number generators and a specified distribution. In optimization analysis, the parameter are altered using the results of the previous simulation and a search algorithm. The Virtuoso Analog Design Environment and the Spectre circuit simulator are capable of performing the analyses shown above. In addition, the Spectre circuit simulator can perform special steady state ac spectral analysis on RF waveforms. These analyses are discussed in the Spectre RF classes. 2/10/05 Virtuoso Analog Design Environment 1-44 Summary In this module we discussed: ■ Course objectives ■ Course outline ■ Class schedule ■ Getting Help, including CDSDoc ■ Design Framework II environment ■ Using forms ■ Creating a library ■ Creating cells and cell views ■ Overview of schematic capture ■ Overview of circuit simulation in the Virtuoso Analog Design Environment ■ Types of simulation analyses Introduction to the Analog Design Environment, Version 5.1.41 1-45 Summary In this module we provided an introduction to the class, including: ■ Class objectives ■ Class schedule ■ Online documentation This module also provided discussion on the Design Framework II environment, including: ■ Starting DFII with icfb, icms, or msfb. ■ The Command Interpreter Window (CIW) ■ Use of forms ■ Front to Back design flow using Design Framework II ■ Overview of schematic capture ■ Overview of circuit simulation in the Virtuoso Analog Design Environment ■ Types of simulation analyses 2/10/05 Virtuoso Analog Design Environment 1-46 Labs Lab 1-1 Getting Started Lab 1-2 Top-Down System Modeling Introduction to the Analog Design Environment, Version 5.1.41 1-47 Labs 2/10/05 Virtuoso Analog Design Environment 1-48 ® 2 Schematic Entry Module 2 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 2-2 Topics in this Module ■ The schematic capture flow ■ Creating a schematic view ■ Contents of a schematic ■ Adding component instances ■ Adding pins ■ Adding wires ■ Editing object properties ■ Using Accelerator keys (also known as bindkeys) and schematic window icons ■ Checking the schematic for errors ■ Symbol generation and editing ■ Using a design hierarchy Schematic Entry 2-3 Terms and Definitions Terms and Definitions library A set of design directories that includes ‘cells’ and ‘cellviews’. Library Manager A Cadence tool that allows user to browse and edit a design library. Virtuoso Schematic Editor Schematic editor and symbol generation tool in DFII. cell A basic unit of a design hierarchy described by cell views. cell view A specific view of a cell that includes schematic, symbol or layout. instance A uniquely named placement of a symbol onto a schematic. pin A connection point on a schematic and symbol used for accessing signals. bindkey A predefined key on the keyboard that invokes a preselected command. 2/10/05 Virtuoso Analog Design Environment 2-4 Schematic Entry Flow Open Design Add Component Instances Add or Edit Component Parameters Add Pins Add and Name Wires Check Schematic Save Schematic Entry 2-5 Schematic Entry Flow Perform the following steps when creating a schematic: 1. Open the design. Use the CIW or Library Manager tool. 2. Add component instances by placing cellviews from libraries. 3. Add or modify component parameters. 4. Add pins to indicate connections outside of this schematic. 5. Connect the components and pins. Use wires to do this. This step also includes giving meaningful names to signals in the design. 6. Check the design to ensure that it is correct. 7. Save the design. 2/10/05 Virtuoso Analog Design Environment 2-6 Contents of a Schematic Wire Tap Component Instance Pin Wire Label Instance Label Schematic Entry 2-7 Contents of a Schematic ■ Component instances represent instantiations of other cellviews in this cellview. ■ Instance labels display component information in the design entry window. ■ Pins can be inputs and outputs of a schematic or connection point when an instance is placed in another cellview. ■ Wires can be drawn between pins to connect them. ■ Wire labels provide meaningful signal identifiers for simulation results analysis. ■ Analog taps and sources can be included directly in the design. 2/10/05 Virtuoso Analog Design Environment 2-8 Creating a New Cellview In the CIW or Library Manager, select File—New—Cellview. Default View Name subject to override. Select: Composer-Schematic ■ Specify the Library Name, Cell Name, View Name, and Tool to use. The path to the cds.lib file will appear in the form and is not editable. ■ Modify the Tool field to create a layout, verilog, symbol, schematic, vhdl, or ahdl view. For an ADE schematic, select Composer-Schematic from the Tool cyclic field Schematic Entry 2-9 Creating a New Cellview Create a new cell views from the Library Manager or CIW. Specify the Library Name, Cell Name, View Name, and Tool to use. The path to the cds.lib file will appear in the form and is not editable. Modify the Tool field to create a layout, verilog, symbol, schematic, vhdl, or ahdl view. For a schematic, use Composer-Schematic. This will automatically enter schematic into the View Name text field. Important Although schematic is automatically entered into the View Name text field by default, you have the option to name the view anything you want. For example, the View Name may be altered to schem1, and the process repeated for schem2. As such, there are two or more schematic views for the same cell name. This allows parallel circuit designs within the same cell name. A common symbol for both schematics is then used within the hierarchy, until the final schematic is selected. This feature is useful in exploratory designs where the final circuit topology has not yet been finalized. 2/10/05 Virtuoso Analog Design Environment 2-10 Adding Component Instances Select Add—Instance or press the i key to display the Add Instance form. ■ Attach multipliers to values. Enter 1k (not 1 k) so that k is not mistaken as a variable. ■ Parameter units, such as ohms, are implicit. Use these buttons while placing components to control orientation. Schematic Entry 2-11 Adding Component Instances Design components are generally instances of a symbol cellview and might be design primitives. Here are some properties associated with design component instances: Parameter Library Name Cell Name View Name Instance Name Example Value analogLib res symbol R2 The Instance Name is assigned automatically, unless explicitly specified. Find analog design primitives in the analogLib library. This library is included wherever the Virtuoso Analog Design Environment software is installed in the path /tools/dfII/etc/cdslib/artist. Include this path in your library search path to use analogLib components. The system prompts for component parameters when instantiating the components. Attach multiplier suffixes, such as k for 1000, to numerical quantities. Use the Rotate, Upsidedown, and Sideways buttons to change the orientation of your components as they are placed in the schematic. 2/10/05 Virtuoso Analog Design Environment 2-12 Updating Design Objects ■ Select Edit—Properties—Objects or bindkey q to start the form. The Next and Previous buttons highlight single objects in a selected set. ■ Use Design—Renumber Instances to renumber instances in a design. Edit — Properties — Objects Design—Renumber Instances Schematic Entry 2-13 Updating Design Objects You can either update single or multiple objects in a selected set. Use the Next and Previous buttons on the Edit Object Properties form to scroll through a set of selected objects and update them. Only one object at a time will highlight in the schematic window. It is possible to modify most quantities that appear on the form. The most common changes concern components parameters, pin name, and pin direction. In addition, use the Stretch, Copy, Move, Delete, and Rotate commands to update your design. These commands are located under the Edit menu in the schematic window. To display an options form that is associated with any of these commands, use the Cmd Options icon or press the F3 key while these commands are active. Use the Renumber Instances form to renumber instances. This form renumbers component names in sequential order to make it easier to track component totals. In addition, adding and deleting components in a schematic during the design process can leave components labeled improperly. Note: The renumber sequence depends on the order that the symbols were added to the schematic. 2/10/05 Virtuoso Analog Design Environment 2-14 Adding Sources and Ground Sources, taps, and grounds are instances of cells. Sample source cells are in the analogLib library. ■ Choose from independent, dependent, and piece-wise linear (PWL) sources. ■ Choose tap and ground cells, which are used to establish global nets. ■ An instance of the cell gnd is required in the design for DC convergence. vcc vcca vcca vcc vdc + + gnd gnda gnda gnda gnda gnd Schematic Entry 2-15 Adding Sources and Ground ■ Ground Always include the symbol gnd (found in the analogLib library). Analog simulators require that all nodes in the circuit must have a DC path ground. This would be represented as node 0 in the Cadence SPICE circuit simulator, for example. Use other ground symbols, such as gnda, for a ground that is connected to the reference ground through an analog circuit. ■ Voltage Sources Include all of your DC and transient voltage and current sources in the schematic. There are many types of voltage sources in analogLib. For example, some of the independent voltage sources are vdc, vsin, vpulse, vexp, vpwl, and vpwlf. Each source has a current equivalent that begins with the letter i. There are also equivalent dependent sources. All sources generate input waveforms except for pwlf sources, which stimulate a circuit using a text file of data tables. It is not necessary to include sources in the schematic, although this is often convenient. Attaching a stimulus file to the final netlist is discussed in the analog simulation section of this course. ■ Voltage Taps Use tap symbols to transfer voltages and currents throughout the design without using wires. Voltage tap symbols, such as vcc, vdd, vcca, and vccd, are in the analogLib library. 2/10/05 Virtuoso Analog Design Environment 2-16 Pins Pins have a user-defined Name and a Direction (input, output, or input/Output). Pins are one of three types: ■ Schematic pins provide ports to a schematic. ■ Symbol pins provide ports to a symbol representing a schematic, and are connection points to the symbol in a hierarchical design. ■ Offsheet pins are used in large designs without hierarchy. Pin names and directions must match in all cellviews of a cell. Offsheet Pin Schematic Pin IN OUT Symbol Pin IN OUT Schematic Entry 2-17 Pins For analog designers, pins have two primary functions: ■ Pins represent connection points between different cell views such as schematic, symbol, and layout representations. Using named pins identifies equivalent input, output, and I/O ports throughout the design environment. ■ Pins provide connection points for objects that are hierarchically instantiated. Pin Properties Pins have a pin name, pin type, and pin direction. These should be consistent throughout your design. Multiple Sheet Design with Offsheet Pins The Virtuoso Schematic Editor User Guide manual includes a section on multiple sheet design methodology and information on the offsheet pin type. You can get other help for the Schematic Editor software in the Cadence online help. Pins (ipin, opin, iopin, sympin) now come from “basic” library. 2/10/05 Virtuoso Analog Design Environment 2-18 Wires and Wire Labels Automatic routing is the default mode. Wire Label sig1 Route Entered The System Routes When not labeling a wire, the system names the net formed by the wires. If the router cannot find a path between two points, ■ A dotted “flight line” is placed to establish connectivity only. ■ Click on intermediate points to guide the router to yield a solid line of connectivity. ■ Use the Cmd Options icon or F3 key to modify the wiring options. Schematic Entry 2-19 Wires and Wire Labels Draw wires between the instance pins and schematic pins to connect them. Use wide wires to indicate multiple signals on a wire, the system does not force or check this. Draw wires at any angle, but most designers frequently restrain wires to orthogonal lines. ■ Using Route Methodology The route draw mode chooses two points in your design and then it automatically routes a wire around components. If a routed net remains dotted, it is because there was no clear routing channel. This can happen if the instances are too close or overlap the selection boxes. To solve this, move the components further apart to give a routing channel. Route method options exist to wire together two points immediately (the default) or indicate many points to route together later in a single step. More information on route methods is included in the design entry reference documentation. ■ Wire Labels Labeling wires gives the corresponding net a meaningful name in the simulation results data. Otherwise nets are system named. There is some control over the automatically generated names, but these may not be as meaningful as custom names. Click the Cmd Options icon in the schematic window or press the F3 key to change the default wiring setup. 2/10/05 Virtuoso Analog Design Environment 2-20 Interconnecting Components Wire to Wire VCC! Wire to Pin Design Global Net Adoption IN IN Pin to Pin IN OUT By Name (local) IN IN OUT Avoid this when possible. Schematic pins and global symbol pins name wires by adoption. Note: Inherited connections (not shown) are discussed in Module 14. Schematic Entry 2-21 Interconnecting Components ■ Physical Connectivity All physical connections are made by wire-to-pin, wire-to-wire, or pin-to-pin connections. ■ Connectivity by Name If two wires have been labeled with the same name, they become part of the same net when connectivity is established. ■ System-Assigned Names If a net is unnamed, the system generates a name such as net100 or net7. Optionally change the base name from net to something else. If a wire is connected to a schematic pin, then the pin name is used to name the net by adoption when connectivity is established. ■ Global Nets Any net or pin name that ends in an exclamation point will be part of a global net when connectivity is established. Global nets are automatically connected through the hierarchy without the use of wires. For example, voltage taps have symbol pin names that end in an exclamation point. If a wire is connected to a pin that has a global name, the pin name is used to name the net by adoption. This is how voltage and ground signals are propagated throughout a design. Note: A net named net! is not connected to a net named net. 2/10/05 Virtuoso Analog Design Environment 2-22 Schematic Checking During schematic checking, all of the following are performed by default: ■ Update Connectivity This process associates wires and pins with logical connections called nets. ■ Schematic Rules Check ❏ Logical checks ❏ Physical checks ❏ Name checks ■ Cross-View Checker This option checks for pin name and direction consistency between cellviews. Execute Check—Rules Setup from a schematic window to edit the rules. Disable any or all of these schematic checking features, if not needed. Schematic Entry 2-23 Schematic Checking Schematic checking is a critical step in the design process. Either check a single cellview or descend through the hierarchy to check all cellviews in your design. Checking a schematic accomplishes the following: ■ Update Connectivity—When connectivity is established, wires and pins in the design entry window become associated with logical connections called nets. It is necessary to correct connectivity problems prior to going on to the next design phase. ■ Schematic Rules Check—This process checks the schematic with a set of rules. Access them with the Check—Rules Setup command from the schematic window. The checks include: ❑ Logical checks, such as Floating Input Pins and Shorted Output Pins. ❑ Physical checks, such as Unconnected Wires and Overlapping Instances. ❑ Name checks, such as Instance Name Syntax. ■ Cross-View Checker—This option checks the pin consistency between different views of the cell. Pin names and directions must match between cellviews. 2/10/05 Virtuoso Analog Design Environment 2-24 Schematic Checking Rules The system sets the default schematic checking rules. The following set and selections are logical types of rules: Note: There are five sets of Rules Checks as indicated by the tabs. - Logical - Physical - Name - Inherited Connections - AMS Note: Ignored means do not check for a condition. It is permitted to generate a netlist and run a simulation with warnings, but not with errors. Schematic Entry 2-25 Schematic Checking Rules The Schematic Rule Checker (SRC) performs schematic syntax checks. Select and override the default values of schematic rule checks. The defaults are acceptable for most applications. Select and set the severity level for SRCs. There are three levels for each check: ignored warning error SRC does not perform the check. Warnings do not need to be corrected before continuing. SRC treats schematic connectivity as valid. The netlist program can still read the schematic. Problems must be corrected before continuing. SRC treats schematic connectivity as invalid. The netlist program refuses to read the schematic. The checks are done for three different areas: Logical checks These checks consist of component connections that could affect the functionality of the circuit. Physical checks These checks consist of problems dealing with overlapping components, unconnected wires, and solder dots. Name checks These checks consist of problems associated with name syntax, behavioral model syntax, etc. A description of the rules is in the Virtuoso Schematic Editor User Guide. 2/10/05 Virtuoso Analog Design Environment 2-26 Component Parameter Types Use user-defined functions to describe parameters. L = nlen W = nwid Variable L = 10u W = 5u Static constant L =0.9u SKILL function in an expression W = 2 * iPar(“L”) L = nlen*2 W = (nlen*2)/5 Any mathematical expression using the above Note: iPar is only used on the same instance where the iPar is. Schematic Entry 2-27 Component Parameter Types Some basic types are static constants, global variables, and dependent variables. Use these in combination with a mathematical expression to create parameters. To change a value during simulation, assign a variable name. Before running simulation, set design variables. All quantities assigned the same variable name will get the same value. Hierarchical variables, user-defined functions, and user-defined constants are discussed later. SKILL Functions Use built-in SKILL functions that return design parameter values and use them in expressions to set component parameters. For example, to make the width of a MOS device a function of its length. In this example, if the length of a component is defined as L, then the width can be set as w= 2 * iPar(“L”) to make the width of the device twice the length. In general, the SKILL function iPar(“parameter name”) returns the value of a component parameter of the local cell. More information on pPar and iPar is found in CDSDoc. 2/10/05 Virtuoso Analog Design Environment 2-28 Passing Parameters Through the Hierarchy L=pPar(“lp”) W=pPar(“wp”) L=pPar(“ln”) W=pPar(“wn”) Hierarchical variables ln IN OUT wn Cell parameters created lp During ASG wp IN OUT IN OUT IN OUT ln=10u wn=5u lp=5u wp=10u ln=20u wn=8u lp=15u wp=30u ln=25u wn=12u lp=12u wp=30u During Automatic Symbol Generation (ASG), hierarchical variables are scanned. The system creates component parameters for the symbol from these variables. Parameters become editable when the instances are selected. Schematic Entry 2-29 Passing Parameters Through the Hierarchy You can place the same symbol many times and alter its schematic component parameter values at the instance level. To accomplish this, assign expressions to schematic components using the following syntax: pPar(“variable”) The value of the variable will be passed from the symbol level in the hierarchy to a component parameter in the schematic. Set the value of the variable when placing the symbol that was automatically generated from a schematic with hierarchical variables. During Automatic Symbol Generation (ASG), the system analyzes the hierarchical variables to determine what component parameters to prompt for when placing a symbol in another cellview. Automatic Symbol Generation (ASG) Automatic symbol generation assists in the creation of symbols. The quickest way to automatically create a symbol is from another cellview. Creating a symbol from an existing cellview also ensures that the pin properties will match between the cellviews. Other advantages to ASG are the automatic creation of symbol parameters from hierarchical variables in the schematic and the creation of CDF for the cell. 2/10/05 Virtuoso Analog Design Environment 2-30 Symbol Generation Design—Create Cellview—From Cellview Select Apply or OK This form opens with only the top portion, press these buttons to extend the symbol generation capabilities of the form. Select a symbol generation template, other than the .cdsinit entry. Select symbol generation attributes to control the symbol drawing. Schematic Entry 2-31 Symbol Generation Bring up ASG from the schematic window. A template file will be used for the symbol creation. There are different symbol template files for different tools in the Design Framework II environment. To make sure the analog symbol generation template is used in your design, put the following command in your .cdsinit file: schSetEnv( "tsgTemplateType" "analog" ) Note: Failure to set this will result in a digital symbol generation. Notice that the From View Name and To View Name fields can be modified in the Cellview from Cellview form. This provides a way to create other views, such as behavioral or ahdl from your schematics. 2/10/05 Virtuoso Analog Design Environment 2-32 Characteristics of an Automatically Generated Symbol Selection Box Interpreted Labels Pin These features are controlled by the symbol template used. Instance Shape Interpreted labels on the symbol act as “placeholders” for different types of information to be displayed in the schematic. ■ cdsTerm() labels display pin names or the net names. ■ cdsParam() labels display parameters of an instance. ■ cdsName() labels display the instance or cell name. Schematic Entry 2-33 Characteristics of an Automatically Generated Symbol An automatically generated symbol cellview includes pins, a rectangular graphic and labels. It can be modified using the symbol editor. Note: The generation depends on the symbol template selected either in .cdsinit or by the symbol generation form. There is some control over how automatically generated symbols are drawn. By default, pins are placed at the left side of the symbol if their direction is input, at the right side of the symbol if their direction is output, and on top of the symbol if the direction is InputOutput. Options exist to change the pin appearance and order of the pins. Interpreted Labels allow information to appear near the symbol after it is placed in another cellview. For the label generation template, the three label types are: ■ cdsTerm() labels display pin names or the net names pins connect to. ■ Each cdsParam() label can display a parameter of the instance. There can be multiples of this label. ■ cdsName() labels display the instance or cell name. All placeholder labels can be rearranged so that labels on instantiated instances are moved accordingly. These three labels have meaning in the Virtuoso Analog Design Environment. They display certain attributes, which are discussed later. A selection box is drawn around the symbol and can be edited. It defines the symbol’s selectable region after it is placed in another cellview. 2/10/05 Virtuoso Analog Design Environment 2-34 Schematic Window Icons and Accelerator Keys The Virtuoso Schematic Editor software provides both icons and “Accelerator” keys (bindkeys) to simplify schematic capture. The icons and Accelerator keys also reduce the time needed to capture and edit schematics. ■ The icons appear on the left-hand side of the schematic editing window. ■ An icon is activated by using a left click over the icon. ■ Accelerator keys are activated by pressing specified keys on the keyboard. ■ Accelerator keys are sometimes referred to as bindkeys. Schematic Entry 2-35 Schematic Window Icons and Accelerator Keys The term “Accelerator” key and “Bindkey” are used interchangeably. 2/10/05 Virtuoso Analog Design Environment 2-36 Schematic Editor Command Summary Command Bindkey Command Sequence Add Component i Add—Instance Select Component(s) LMB left click, or drag LMB Copy c Edit—Copy Delete Del Edit—Delete Move m Edit—Move Stretch M Edit—Stretch Rotate r Edit—Rotate Repeat RMB Modify Properties q Edit—Properties—Objects... Add Wire w Add—Wire Add Wire Name l Add—Wire—Name... Add Pin p Add—Pin Undo u Edit—Undo Redo U Edit—Redo Icon? yes yes yes yes yes yes yes yes yes yes Schematic Entry 2-37 Composer Command Summary Command Zoom in by 2 Zoom out by 2 Zoom in Zoom out Fit Redraw Check and Save Save As Delete Marker Descend Edit Return Delete All Edits Close Bindkey Command Sequence ] Window—Zoom—zoom in by 2 [ Window—Zoom—zoom out by 2 z Window—Zoom—Zoom in Z shift—RMB f Window—Fit f6 Window—Redraw X Design—Check and Save ^s Design—Save As ^g Check—Delete Marker E Design—Hierarchy—Descend Edit ^e Design—Hierarchy—Return Design—Discard Edits Window—Close Icon? yes yes yes 2/10/05 Virtuoso Analog Design Environment 2-38 Bindkeys (Accelerator Keys) Many of the schematic capture commands have alternative ways to be invoked. 1. A command sequence such as: Edit—Properties—Objects 2. An icon such as: 3. A bindkey such as q Bindkeys include the following features: ■ Speed up schematic capture flow ■ Default set of functions with installation ■ Functions may be customized ■ Full set of may be viewed or changed using Options—Bindkeys in the CIW Schematic Entry 2-39 Bindkeys Bindkeys simplify the schematic capture flow. A default set of bindkeys is provided; however, the keys are programmable. To view the key settings and the corresponding SKILL syntax, select in the CIW: Options—Bindkeys. A “Key or Mouse Binding Window” appears. This window shows bindkeys for the schematic editor and other tools. In the Application Type Prefix cyclic field select schematic. Then select the Show Bind Keys button. The Schematic Bindkeys window will appear. Note: This is a partial list. To view all bindkeys use scroll bar. 2/10/05 Virtuoso Analog Design Environment 2-40 Using a Hierarchy nmos wn=4u ln=0.5u (symbol of primitive “nmos”) LEVEL - Primitive IN pmos wp=8u lp=0.5u Inv1x OUT nmos wn=4u ln=0.5u Inv1x IN OUT (symbol of Inv1x) ringosc IN LEVEL - Schematic using primitives (requires symbol to use in a hierarchy) OUT IN OUT IN OUT oscout ringosc (symbol of rngosc) IN OUT IN OUT IN OUT oscout LEVEL - Schematic with Hierarchy (schematic uses symbols of other schematics and primitives) Schematic Entry 2-41 Using a Hierarchy A hierarchy is the design data of a complex system organized into simple and manageable data at different levels. A hierarchy simplifies the complex structure of a system. It often reduces the storage requirements for the data. It also simplifies and reduces the time to design the system. Primitives are the basic design elements and exist at the bottom of the hierarchy. The design does not descend below this level. A schematic may consist entirely of primitives. Such a schematic is also referred to as a flat schematic or a primitive-level schematic. For large systems, for example a 16-bit analog-to-digital converter, it is difficult capture the design with a flat schematic. A design of a complex system can consist entirely of a single schematic. The flat schematic can be simulated by including sources for power and stimulus. A design using only a flat schematic (without hierarchy) is inefficient when repeated structures are used. Such a schematic becomes difficult to manage as the circuit complexity increases. A schematic can use symbols of primitives and symbols for other schematics. Such a schematic is more efficient to design repeated structures and complex systems. This use of symbols to represent schematics continues to higher and higher levels of hierarchy until the TOP level of the design is reached. A symbol for a schematic view is only required when that schematic is used within a hierarchy. 2/10/05 Virtuoso Analog Design Environment 2-42 Labs Lab 2-1 Schematic Entry Lab 2-2 Symbol Creation Lab 2-3 Building the Supply Circuit Lab 2-4 Building the ampTest Design Schematic Entry Labs 2-43 2/10/05 Virtuoso Analog Design Environment 2-44 Lab Reference Material: Mouse Buttons Left Mouse Button—Select and Deselect Click Select point Double click Extend select Shift-click Select point (add) Control-click Deselect point Draw through Select box or Direct Edit* Shift draw through Select box (add) or Direct Edit* Control draw Deselect box or Direct through Edit* (EF) Add point Middle Mouse Button Pop-Up Menus Click (EF) Pop-up menus Pop-up menus Right Mouse Button Repeat, Zoom, Options Click Repeat last command Draw through Zoom in Shift draw through Zoom out (EF) Command options (command-specific bindings) Note: EF (Enter Function) bindkeys used within an active command. *Direct Edit applies only when over object. Schematic Entry Lab Reference Material: Mouse Buttons 2-45 2/10/05 Virtuoso Analog Design Environment 2-46 ® 3 Analog Simulation Module 3 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 3-2 Topics in this Module ■ Overview of the simulation environment ■ Setting up the simulation environment ■ Model files ■ Design variables ■ Choosing analyses ■ Netlisting ■ Running simulation ■ Viewing simulation results with the Waveform display tool ■ Saving simulator sessions Analog Simulation 3-3 Terms and Definitions Terms and Definitions simulation window The ADE user interface to control and view simulations. analyses field A text field in the simulation widow indicating selected analyses. output field A text field in the simulation widow indicating selected output. Spectre A Cadence simulation tool for simulating analog circuits. simulator host Software tool such as Spectre, cdsSpice, etc. to be used for simulation. model library A text file having model description used by the simulator host. stimulus template A user interface used to establish signals used in simulation. netlist A textual description of a schematic used by the simulator host. Waveform Window A graphical interface used to plot simulation data. direct plot User command used for ‘special’ plots to the Waveform Window. annotating Process of displaying data back to another window or schematic. label display A label attached to a component for displaying information. snapshot A command to the Waveform Window to update intermediate results. 2/10/05 Virtuoso Analog Design Environment 3-4 Important Features of the Simulation Window Menu Choose Design 1 3 2 Command Prompt 4 Plot Mode Analyses Edit Variables Outputs Delete Netlist and Run Run Snap Shot Analog Simulation 3-5 Important Features of the Simulation Window The diagram shows the Virtuoso Analog Design Environment window. The simulation window is annotated with notes used to describe the important features. The are four regions identified by numbered boxes 1, 2, 3, and 4. ■ Region 1 is the “Design Field”. It indicates the library, cell, and cell view to be simulated. ■ Region 2 is the “Design Variables Field”. It shows the design variables and set values. ■ Region 3 is the “Analyses Field”. It shows the status, ranges, and types of analyses. ■ Region 4 is the “Outputs Field”. It indicates the selected outputs and expressions. Important The entries within Regions 2, 3, and 4 are accessible by executing a left mouse click. It is sometimes easier and faster to make changes within these fields than using the menu banner. The simulation window also has a Menu Banner used to select analyses, models, outputs, and other simulation controls. The Menu Banner also has a Tools menu used to set up advanced simulation tools such as Corners, Monte Carlo, and Optimization. The simulation window also has a set of icons for along the right-hand side for quick selection of specific commands. 2/10/05 Virtuoso Analog Design Environment 3-6 Analog Simulation Flow STEP 1. Start the Simulation Environment 2. Select or verify Simulator Host 3. Select model files and include files 4. Set design variables 5. Choose analyses for simulation 6. Set simulator options 7. Select signals for output dc dc sweep ac transient etc. 8. Netlist and run simulation Analog Simulation 3-7 Analog Simulation Flow This diagram shows the major steps required to set up and run an analog circuit simulation in the simulation environment. To set up the simulation the first time, most of these steps are required. However, on all subsequent simulations, perhaps only one or two steps are needed. Each of the steps numbered above shall be discussed within this module. Important If you are unfamiliar with the flow, this may appear to be a large amount of work to set up the simulation. However, after the initial setup is completed, the flow is greatly simplified. Once you are familiar with the flow, all of these steps are performed within a few minutes, or less. 2/10/05 Virtuoso Analog Design Environment 3-8 Starting the Simulation Environment STEP 1. Select Tools—Analog Environment from the schematic menu banner, or select Tools—Analog Environment—Simulation from the CIW. Then the Virtuoso Analog Design Environment “Simulation Window” appears. Analog Simulation 3-9 Starting the Simulation Environment STEP 1. In this class, use the Spectre simulator that is integrated directly into the Virtuoso Analog Design Environment. Start the simulation environment from the schematic window or the CIW. If the simulation environment is started from the design window, the design in the window is understood to be the target of the analysis. Start the simulation environment from the CIW to simulate any design without viewing it. Commands on pull-down menus in the Simulation window establish a simulation flow if used in order, starting at the top and left and ending with the last command on the right most pull-down menu. For analog analysis, include this statement in your .cshrc file before starting the Cadence Design Framework II environment: setenv CDS_Netlisting_Mode “Analog” 2/10/05 Virtuoso Analog Design Environment 3-10 Setting the Simulator STEP 2. Select the simulator to be used. Select: Setup—Simulator/Directory/Host For this class select spectre in the cyclic field. Analog Simulation 3-11 Setting the Simulator STEP 2. The second step of the Analog Simulation Flow is to set the target simulator and Project Directory. The Project Directory is the location where the simulator puts all of the data, including netlists, waveforms, include files, and mapping information. Set the simulator to spectre to start direct simulation with the Spectre tool. Note that a cyclic field appears that allows other host simulator choices, such as spectreVerilog. The Choosing Simulator/Directory/Host form has a button that provides a way to choose the distributed Host Mode. When this button is pressed, there are two additional fields added to your form: Auto Job Submit, and E-Mail Notify. This function uses multiple machines to handle large or computationally intensive jobs. Jobs are sent to the default queue named in your .cdsenv file or to the last setting in the Job Submit form. When Auto Job Submit is not selected, the Job Submit form appears whenever a simulation is run. More information can be found in CDSDoc. 2/10/05 Virtuoso Analog Design Environment 3-12 Setting the Model Libraries STEP 3. Select the model files. In simulation window, select: Setup—Model Libraries... This example uses a relative path. The path is set by the Include Path in the Simulation Files Setup form. Analog Simulation 3-13 Setting the Model Libraries STEP 3. This is a critical step that must be performed to ensure that model files for active devices, such as transistors, are included in the netlist. With Spectre Direct: ■ .scs = Spectre circuit simulator. All files ending in .scs are implied to be Spectre syntax in the netlist unless simulator lang=spice is included in the file. (SPICE in this case means general Berkeley SPICE syntax and NOT cdsSpice). Spectre example: model npn bjt type=npn is=3.26E-16 va=60 bf=100 \ br=6 nc=2 ikr=100m rc=1 vje=0.7 \ cjc=1e-12 fc=0.5 cje=0.7e-12 \ tr=200e-12 tf=25e-12 itf=0.03 vtf=7 xtf=2 ■ There are several modeling techniques to use. The main use model is one file with all of the models contained within. ■ The contents of the model file do not appear in the netlist. The library model file is referenced as an include file. There are samples of all of the models available at: /tools/dfII/samples/artist/models/spectre 2/10/05 Virtuoso Analog Design Environment 3-14 Simulation Files STEP 3. Setup—Simulation Files For setting the path to other simulation files This is a relative path Enter the absolute or relative path into the text field Include Path Path to location of any Model Library Files, Definition Files, and Stimulus Files (the paths in these fields can be relative paths) Definitions Files File or files that contain function definitions and parameter declarations not in the Design Variables section of the Simulation Window Stimulus Files Location of text-based stimulus file ■ Each of the above fields can have one or more paths or file declarations separated by a space. ■ Any type of Spectre include file can be included in the netlist by either using the Definitions Files field above or the Model Libraries Setup form. Analog Simulation 3-15 Simulation Files STEP 3. Include Path—Example of absolute path declaration: “/usr/home/models/project/models” The simulator resolves a relative file name by first looking in the directory where the file is located. Subsequently, it searches for the file in each of the directories specified by the include path, from left to right. Definitions File—Defines functions and global variables that are not design variables. It is included in the netlist before model files. Example: simulator lang=spectre real PiRho() { return 2500; } Functions returning constant values real Rpb(real l, real w) { return PiRho()*l/w; } Simple passing parameters real rpoly(real value, real tdc) { value*(1+.01*(tdc-25)+.002*(tdc-25)**2); } poly resistor function of temperature A sample Definitions File exists at: /tools/dfII/samples/artist/models/spectre/defaults.scs Stimulus File—Enter the full path to the directory where the stimulus file resides. A file name ending in *.scs defaults to Spectre. All other files default to SPICE syntax. 2/10/05 Virtuoso Analog Design Environment 3-16 Setting Design Variables STEP 4. ■ Extract variables in a design with the Copy From button. ■ Copy variable settings back to the design with the Copy To button. ■ Add variables used in parameterized model files that are not extracted. ■ Update a variable value and run simulation. Netlisting does not occur again. ■ Extract new variables added after a simulation run. ■ Use the Find button to locate the Selected Variable in your design. Select Variables—Edit or click the Edit Variables icon. Analog Simulation 3-17 Setting Design Variables STEP 4. Use the Editing Design Variables form to: ■ Enter design variable values. These values can be numbers or expressions. ■ Copy variables from a design, or copy set variables back to the design to be saved. ■ Add new variables. Add variable names to this form that control the simulation engine or appear in model files and then set their values. ■ Find a variable in the design. This useful feature highlights the component to which the selected variable is attached. This can be very helpful in a large design when trying to locate a particular design variable. When starting the simulator from this form, change a variable value, apply the change, and repeat simulations quickly. The system will not create a new netlist when a variable value is updated. Spectre Direct has no character limit for the size of a variable. The following examples are legal statements: parameters thisIsAReallyLongDesignVariableName=10000 desVar2=10p \ desVar3=2u desVar4=1.15 Design variables are not evaluated. They appear in the netlist as Spectre parameter statements. 2/10/05 Virtuoso Analog Design Environment 3-18 Choosing Analyses STEP 5. Select Analyses — Choose or click the Choose Analyses icon. Analog Simulation 3-19 Choosing Analyses STEP 5. Choosing the analyses to perform on the design is a straightforward process. Run analyses together, separately, and in any combination. Analysis units are determined by the simulation engine. Output data is generated for each specified analysis during a simulation. 2/10/05 Virtuoso Analog Design Environment 3-20 Choosing Analyses Details Spectre RF Analyses The Choosing Analysis form dynamically changes based on the host simulator and the selections made on the form. The types of analyses that are available depend on the host simulator. Sweep Variables depend on the selected analysis. Sweep Range Analysis Options are entered by selecting the Options... button. Analog Simulation 3-21 Choosing Analyses Details The Choosing Analysis form depends on the host simulator. The form above is used for the Spectre circuit simulator, which supports 15 types of analyses. These include ac, dc, tran, stb, dcmatch. In addition: ■ sp S-Parameter Analysis Also, the following types of RF analyses are supported by Spectre RF tool: ■ envlp Envelope Following Analysis ■ pss Periodic Steady State ■ pac Periodic AC ■ pnoise Phase Noise Analysis ■ pxf Periodic XF Analysis ■ psp Periodic S-Parameter ■ qpss Quasi-Periodic Steady State Analysis ■ qpac Quasi-Periodic AC ■ qpnoise Quasi-Periodic Noise ■ qpxf Quasi-Periodic XF ■ qpsp Quasi-Periodic S-Parameter For more information on Spectre RF analysis, see CDSDoc. In addition, Cadence Education Services provides training in Spectre RF usage. 2/10/05 Virtuoso Analog Design Environment 3-22 Simulation Environment Options STEP 6. Select Setup—Environment ■ Switch View List and Stop View List establish netlisting rules ■ Parameter Range Checking File ■ Use the SPICE Netlist Reader (spp)—Read in HSPICE/SPICE netlists and run with the Spectre simulator. ■ Checkpoint and Restart Analog Simulation 3-23 Simulation Environment Options STEP 6. The Switch View List specifies the order that the cellviews are netlisted. The Stop View List specifies the view at which the netlist statements are generated. For the Spectre simulator, the Parameter Range Checking File contains the parameter range limits. Use either the full path to the file, or a period (.) to specify a relative path to the directory where the Cadence tools were started. (Optional) Check and set the options for view switching to control how the system netlists hierarchical designs. Normally, there is no need to modify the Switch View List and Stop View list. The SPICE reader (spp) option is provided for include files or subcircuits that are in SPICE syntax. The spp automatically converts them to Spectre syntax, so a Spectre simulation can be run. Starting in 5.1.41, SPP is no longer needed to read SPICE netlists or models into the spectre simulator. A new parser (csfe) has been added with better performance and compatibility with other SPICE simulators. csfe has not been made the default parser, but may be in future releases. Insert following line in .cdsenv file to invoke the new parser: spectre.envOpts useCsfe boolean t The Create Checkpoint File (cp) and Start from Checkpoint File (rec) options allow Spectre to save checkpoint files while a simulation is running, and then restart the analysis from this file. Currently, only transient analysis supports checkpoint and restart. 2/10/05 Virtuoso Analog Design Environment 3-24 Simulator Options STEP 6. Select Simulation—Options—Analog Use this form to set the simulator tolerance values, convergence options, and other settings. NOTE: This is a very long form. The scroll bar indicates the amount of the form that is visible. Analog Simulation 3-25 Simulator Options STEP 6. Select Simulation—Options—Analog to activate the Simulator Options form. Use this form to set convergence, tolerances, and other simulator settings. In addition to this form, the Choosing Analyses form has an Options button for setting specific options for transient, ac, and dc analyses. For example, the Infotimes and Captab options are found by selecting the tran button in the Choosing Analysis form and then selecting the Options button. 2/10/05 Virtuoso Analog Design Environment 3-26 Probing the Schematic to Save Output Data STEP 7. Select signals for output Click on pins to save currents. Click on wires to save voltages and frequency data. Select: Outputs—To Be Plotted—Select On Schematic ■ You must terminate this command by pressing the Esc key. ■ Save and load data sets. Optionally, save quantities associated with all wires, all pins, or both. Analog Simulation 3-27 Probing the Schematic to Save Output Data STEP 7. Specifying Outputs Use Outputs—To Be Plotted—Select On Schematic When using the command to select a set of outputs, click on device pins to save terminal currents or wires to save node voltage or frequency data. Data will be available for plotting and analysis on nodes or terminal pins that are saved before simulation. Select the Edit—Select—Filter command in the schematic window to display the Schematic Selection Filter to choose which objects, such as wires and pins, are selectable. Saving All Outputs Save all quantities associated with wires or pins in a design. 2/10/05 Virtuoso Analog Design Environment 3-28 Reminder to Terminate Select “Outputs...” When doing the lab activities, it is extremely important to remember to terminate the command Outputs—To be Plotted—Select On Schematic. This command allows you to select wires and terminals for plotting. The command continues to select wires and terminals until it is terminated by pressing the Esc key. A common error when using the simulation environment is to continue work without terminating this command. The user will move the mouse to select Netlist and Run, or other commands in the menu banner. Then the user attempts to change a component parameter on a symbol in the schematic. The simulation environment responds by selecting all terminals of the component to be plotted and these appear in the “Outputs” field of the simulation window. Now the user must unselect the terminals and delete the entries in “Outputs” field. Analog Simulation 3-29 “ Reminder to Terminate Select Outputs ...” When using the Outputs—To Be Plotted—Select On Schematic command, it is important to terminate this command. It is terminated using the Esc key (also known as the escape key). Important If you forget to terminate (a common mistake) and later attempt to select a component on the schematic for edit, all terminals of the component will be selected for plotting and appear in the “Outputs” field the simulation window. At this point it is easy to recover. Select the component again. Fortunately, the Outputs—To Be Plotted—Select On Schematic command is a toggle command. The second mouse click is an unselect. The terminals of the component are unselected and also removed from the “Outputs” field. Now press the Esc key. 2/10/05 Virtuoso Analog Design Environment 3-30 Outputs Section of Simulation Window STEP 7. # Name/Signal/Expr Value Plot Save March 1 out 2 input 3 VDC(“/out”) 4 phaseMargin 5 gainMargin wave wave -1.004m 73.64 -16.00 yes allv yes yes allv no yes yes yes Automatically Evaluated Automatically Plotted Analog Simulation 3-31 Outputs Section of Simulation Window STEP 7. In the Outputs section of your Simulation window display the following: ■ Signal names and evaluated expression values (created by the calculator) ■ The signals to plot ■ The signals to save ■ The signals to march (this is an option in spectreS only.) Use calculator expressions to return either a waveform or numeric value. If signals and expressions are saved prior to running the simulation, the Virtuoso Analog Design Environment will automatically plot the waveforms and evaluate the numeric expressions and display their values when the simulation ends. 2/10/05 Virtuoso Analog Design Environment 3-32 Netlisting STEP 8. ■ Netlists are hierarchical and created incrementally. Re-netlist only the modified schematics. ■ Force all schematics to re-netlist with Simulation—Netlist—Recreate Analog Simulation 3-33 Netlisting STEP 8. The system automatically creates netlists when running a simulation, but a netlist can be created and viewed before simulation. Netlisting Use the Simulation—Netlist—Create command to: ■ Use the Virtuoso Analog Design Environment to create a netlist that is simulated in standalone mode. ■ Modify the netlist, perhaps to take advantage of features that the interface to your simulator does not support. ■ Read the netlist before starting the simulation. Incremental Netlisting Incremental netlisting is faster than full hierarchical netlisting because only the schematics that have changed since the previous netlist was generated are re-netlisted. This substantially speeds up netlisting of hierarchical designs containing many small schematics. The system keeps track of the status of each schematic during and between design sessions. 2/10/05 Virtuoso Analog Design Environment 3-34 Running the Simulation STEP 8. After the netlist has been created or recreated, the simulation is ready to run. To run the simulation: ■ Select Simulation—Run or ■ Select the Run icon on the right side of the simulation window. If preselected outputs appear in the output field of the simulation window, then the Waveform display will automatically appear when the simulation is completed. Analog Simulation Running the Simulation 3-35 2/10/05 Virtuoso Analog Design Environment 3-36 Running Additional Simulations The purpose of running a simulation is to verify the operation and performance of the circuit. This often requires running additional simulations. Most steps of the simulation flow have now been completed. So running additional simulations is greatly simplified. ■ To make changes to the simulation, simply modify the entries to the Design Variables, Analyses, or Output fields, and then press the Run icon. ■ To change the temperature, select Setup—Temperature in the menu banner, enter the new value, and the press the Run icon. ■ If you did not edit the schematic, you do not need to netlist the circuit. ■ If you did edit the schematic, you must do a Check and Save in the schematic window. ■ After the Check and Save, you must select Netlist—Recreate within the simulation window. ■ The simulation setup can also be saved for running additional simulations at a later time, or even for running simulations on similar circuits. Analog Simulation 3-37 Running Additional Simulations Upon completion of the first simulation, the setup has been complete. It is now very simple to change the parameters of the next simulation, or set of simulations. Just select by: ■ a mouse sequence using the menu banner, ■ selecting an icon on the right-hand side of the simulation window, or ■ selecting the appropriate line within an editable field of the simulation window, such as the “Analyses” field. If you make changes only to the simulation window, then you are able to run the new simulation without netlisting. If you make changes to the schematic, then the schematic must be checked and saved, and a new netlist must be generated. However, the simulation window accesses the design database using the Design Framework. There is no requirement to open or close additional windows. A few simple clicks and the updated schematic is simulated. 2/10/05 Virtuoso Analog Design Environment 3-38 Control of Analyses for Simulation Analyses Control Field Analog Simulation 3-39 Control of Analyses for Simulation The Virtuoso Analog Design Environment provides additional control for running analyses. The Analyses Control Field lets you select which analyses to complete during the next simulation run. This field displays all analyses that have been activated by using the Choosing Analyses window. To select a specific analysis, move the mouse into the Analyses Control Field and click left to select the specific analysis line. The selected line is highlighted. The menu banner of the Simulation Window provides these options: ■ Select Analyses—Delete to remove the analysis completely! ■ Select Analyses—Enable to include the analysis in the next simulation. ■ Select Analyses—Disable to deactivate analysis, but not delete from Analyses field. The disable mode means the selected analysis does not run for net simulation. However, the setup from Analyses—Choose remains. Simply select, and then enable the analysis to run. 2/10/05 Virtuoso Analog Design Environment 3-40 Additional Options Using ADE The Virtuoso Analog Design Environment provides additional features that simplify running additional simulations, or modify the performance of the simulation. These options are: ■ Analog Default Options ■ Save State ■ Load State ■ Stimulus Template ■ Simulation Environment Options ■ Infotimes ■ Captab Analog Simulation 3-41 Additional Options Using ADE Analog Default Options modifies the default appearance of the simulation window. Save State is used to save the setup of the simulation window for reuse. Load State is used the restore the setup of the simulation window. Stimulus Template is an alternative method to provide stimulus to the circuit. Simulation Environment Options alters the switch view list and the stop view list. Save Options sets the default levels of signals to be saved. 2/10/05 Virtuoso Analog Design Environment 3-42 Analog Default Options In the Simulation window, select Session—Options. Then an Editing Session Options window appears. Select this button to be queried to save the present working state. Analog Simulation 3-43 Analog Default Options With this command, you set up certain options to affect the way the Simulation Environment looks. Choose which method you prefer: Simulation Window-based (default) or Virtuoso Schematic Editor-based (using schematic window menus) or both. In addition, specify the directory to save state files in. State files characterize the Simulation Environment setup, including the Model Library File, convergence parameters, outputs, and design variables. Keep the default ./.artist_states location (this will place the states in the project which launched the Cadence session), or choose one in your design database. The option called Preload the Corners Java is a new feature that works with the Corners Analysis tool. It is turned on by default and can slow down your Simulation Environment start-up time. When not using the Corners tool, to turn it off or add the following statement to your .cdsenv file: asimenv loadCorners boolean nil Also set the Default Design Open Mode and the location of the Simulation window. 2/10/05 Virtuoso Analog Design Environment 3-44 Simulation States Session—Save State Session—Load State Analog Simulation 3-45 Simulation States Save State This command saves simulation states during a session. Items that can be saved include Analyses, Variables and Outputs, and the Waveform Window. Save each of these items individually or in groups. Name the file anything by typing the name in the Save As field. The default name is state1. By default, the files are saved under a directory called ./.artist_states. Change the location of this directory by specifying a new directory in the State Save Directory field in the Editing Session Options form. Access this form with the Session—Options command in the Simulation window. Load State Use the Load State command to load saved states for a design. The cyclic fields next to Library and Cell are used to pick a particular design. The state files are simulator dependent, if Analyses are saved as part of the file. Use Outputs and Variables with any simulator. The State Name listbox will show all of the saved files for the design. Save individual objects. This feature is particularly useful for adding items to the Outputs section. For example, the user might have specific equations that are always used for testing the AC stability of a circuit. Once these equations are defined, they can be loaded them into other designs very quickly. 2/10/05 Virtuoso Analog Design Environment 3-46 Stimulus Template Setup — Stimuli Analog Simulation 3-47 Stimulus Template Use this graphical interface to create a stimulus file for specifying input stimuli and power supply stimuli to your design. Attach any type of source to the input pins or global pins that are in your design. To use input stimuli, instantiate input pins into your top-level schematic for those stimuli signals. The power stimuli requires a defined global name on a signal (such as vdd!). Use this option to create designs that can run in multiple simulation scenarios, that do not require power sources and input stimuli that can clutter up the schematic window. Note: To serve as optional stimuli, use both standard sources mixed with stimuli sources in your schematic. The stimulus template provides other options to creating stimuli for your circuit, depending on the analysis selected. 2/10/05 Virtuoso Analog Design Environment 3-48 Save Options Select: Outputs—Save All Setting none selected lvlpub lvl allpub all Description Does not save any data. (Currently saves one node chosen at random.) Saves only signals selected in schematic. Saves all signals that are normally useful up to nestlvl deep in the subcircuit hierarchy. This option is equivalent to allpub for subcircuits. Saves all signals up to nestlvl deep in subcircuit hierarchy. Relevant to subcircuits. Saves only signals that are normally useful. Saves all signals. Analog Simulation 3-49 Save Options Specify which signals to save with the save parameter. Use the nestlvl parameter when saving signals in subcircuits. (Set save to lvl or lvlpub.) Signals that are “normally useful” include shared node voltages and currents through voltage sources and iprobes. If you use lvl or all instead of lvlpub or allpub, you will also get internal node voltages and currents through other components that happen to compute current. Thus, using *pub excludes internal nodes on devices (the internal collector, base, emitter on a BJT, the internal drain and source on a FET, etc). It also excludes the currents through inductors, controlled sources, transmission lines, transformers, etc. To save power dissipated on a circuit, subcircuit, or device, use the pwr parameter. Power is calculated only during DC and transient analyses. The results are saved as a waveform, representing the instantaneous power dissipated in the circuit, subcircuit, or device. The nestlvl parameter specifies how many levels deep into the subcircuit hierarchy to save signals. The default setting for nestlvl is infinity, which saves all levels. The currents parameter of the options statement computes and saves terminal currents. The selected parameter saves only currents select. The nonlinear parameter saves all terminal currents for nonlinear devices, naturally computed branch currents, and currents specified with save statements. The all parameter saves all currents. The nonlinear and all parameters can significantly increase simulation time. Use the subcktprobelvl parameter to control the calculation of terminal currents for subcircuits. Current probes are added to the terminals of each subcircuit, up to subcktprobelvl deep. Specify all currents to be calculated with current probes by setting userprobe to yes. Note that no AC currents will be saved if you do not userprobe to yes. To save ahdl variables in ahdl instances, set saveahdlvars to selected or all. Sometimes there is a need to set a large number of current probes. This could happen, for example, if one needs to save a number of ACs. (Current probes can find such small signal currents when they are not normally computed.) Specify that all currents be calculated with current probes by placing useprobes=yes in an options statement. To save all the ahdl variables belonging to all the ahdl instances in the design, set the saveahdlvars option to all using a Spectre options command. For example: Saveahdl options saveahdlvars=all. 2/10/05 Virtuoso Analog Design Environment 3-50 Save Defaults and Save Session In the CIW, select Options—Save Defaults. In the CIW, select Options—Save Session. Analog Simulation 3-51 Save Defaults and Save Session The .cdsenv file contains default information for all of the tools in the executable. In the Virtuoso Analog Design Environment, the information that you set in the Editing Session Options form and the Setting Plotting Options form is saved in the .cdsenv file. Additionally, the Simulator and Project Directory are also saved. File Status ■ Overwrite: Stores the values entered in the Save Defaults form by overwriting the previous .cdsenv file in pointed to in the path. ■ Merge values: Stores the modified values entered in the Save Defaults form in the previous .cdsenv file but does not delete pre-existing, unmodified values. ■ Retain values: Stores the values entered in the Save Defaults form by creating another file. It is necessary to enter the name of the file in the Save to File field. Save Session When starting the Design Framework II environment with a -restore option, the specified file is loaded. Windows that were active at the time of the session save will be restored, as well as each open form. Also restore sessions by typing load (“”) in the CIW. Use caution when loading a session file in the CIW, because SKILL commands in the file might interfere with the current design session. The restored session will be added to the existing session, but no existing windows will close. 2/10/05 Virtuoso Analog Design Environment 3-52 Infotimes Infotimes is a transient analysis option that saves transient operating point information at specific timepoints in the simulation. 1. From the Simulation Window, select Analyses—Choose. 2. Select the tran button in the Choosing Analyses form. 3. Select Options at the bottom of the Choosing Analyses form. 4. A very long Transient Options form appears, scroll down to infotimes. 5. Enter infotimes, as shown. The line on the Transient Options form for entering infotimes. Enter your time points in this text field in any order. Analog Simulation 3-53 Infotimes Accessing the infotimes Text Field Multiple values entered in this field should be separated by blank spaces. If invalid separators or non-numeric values are specified here, Spectre reports the error/warning in the simulation output window. For example, if you use “comma” between values, it works but gives you following warning: Warning from spectre during circuit read-in. "input.scs" 75: Use of the comma character in lists will not be supported in future releases. The infotimes netlist statements Netlist from ADE: tran tran stop=100u write="spectre.ic" writefinal="spectre.fc" \ annotate=status infotimes=[5u 29u 68u 87u] maxiters=5 \ infoname=tran_Info tran_Info info what=oppoint where=rawfile 2/10/05 Virtuoso Analog Design Environment 3-54 Infotimes Results Select Results—Print—Transient Operating Points, then click components on the schematic. To print the data of this window as a file select: Window—Print Scroll bar Select additional components! The scroll bar becomes smaller as additional devices are selected on the schematic. The file is getting larger, but the data is added to the bottom of the file. Analog Simulation 3-55 Infotimes Results ■ Once infotimes values are specified, netlist and run the simulation. ■ When the simulation has been completed, select: Results—Print—Transient Operating Point ■ A Results Display window appears. If you have not selected a component, the window will be empty. Select a component in the schematic. ■ The operating point information appears in the window. ■ Select another component, the data is added to the bottom. You may not see it; however, the scroll bar on the window gets smaller. ■ To print the file, select Window—Print in the Results Display Window. 2/10/05 Virtuoso Analog Design Environment 3-56 Captab ■ Transient analysis option or dc analysis option ■ Provides a table of node capacitances at specified times ■ Has three node detail options: node, nodetoground, and nodetonode ■ Has a threshold feature; default is 0.0F ■ Similar to the CAPTAB option in HSPICE ■ Used with infotimes in the transient analysis options form ■ Simple to use Analog Simulation 3-57 Captab Captab provides a tabulation of node and device capacitance, either at the dc operating point or at the specified infotimes. The tabulation appears in the simulation output log file. The CAPTAB parameters detail = node Provides details of the capacitance. Possible values are node, nodetoground, or nodetonode. sort=name How to sort the capacitance table. Possible values are name or value. If sort-by-value is selected, then the table will be sorted in a descending order of the total node capacitance. (The rows with the same “From_Node” will remain together.) If sort-by-name is selected, then the table will be sorted in alphabetical order according to the “From_Node:To_Node” column. threshold=0 F Threshold capacitance value for printing. This feature allows you to specify the threshold capacitance value. The nodes for which the total node capacitance is below the threshold value will not be included in the output. 2/10/05 Virtuoso Analog Design Environment 3-58 Selecting the captab Option from ADE DC and Transient Analysis has CAPTAB PARAMETERS option. For transient analysis: 1. Select Analyses—Choose. 2. Select the tran button in the Choosing Analyses form. 3. Select Options at the bottom of the Choosing Analyses form. 4. On the Transient Options form scroll down to infotimes. 5. Enter infotimes (see page 3-53). 6. Scroll down to CAPTAB PARAMETERS at the bottom of Transient Options form. 7. Enter CAPTAB selections. Analog Simulation Selecting the captab Option from ADE 3-59 2/10/05 Virtuoso Analog Design Environment 3-60 Labs Lab 3-1 Running Simulation Lab 3-2 Using the Stimulus Template Lab 3-3 Transient Operating Point Analysis, “infotimes” Lab 3-4 Captab Analog Simulation Labs 3-61 2/10/05 Virtuoso Analog Design Environment 3-62 ® 4 Simulation Results Display Tools Module 4 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 4-2 Topics in this Module ■ Overview for using Waveform Display tools ■ Introduction to WaveScan ■ Viewing simulation results with the Waveform Window ■ Accessing and appending data on the Waveform Window ■ Accessing the Waveform Calculator ■ Using subwindows ■ Label Displays Simulation Results Display Tools 4-3 Terms and Definitions Terms and Definitions simulation window The ADE user interface to control and view simulations. analyses field A text field in the simulation widow indicating selected analyses. output field A text field in the simulation widow indicating selected output. spectre A Cadence simulation tool for simulating analog circuits. simulator host Software tool such as Spectre, cdsSpice, etc. to be used for simulation. model library A text file having model description used by the simulator host. stimulus template A user interface used to establish signals used in simulation. netlist A textual description of a schematic used by the simulator host. Waveform Window A graphical interface used to plot simulation data. direct plot User command used for ‘special’ plots to the Waveform Window. annotating Process of displaying data back to another window or schematic. label display A label attached to a component for displaying information. snap shot A command to the Waveform Window to update intermediate results. 2/10/05 Virtuoso Analog Design Environment 4-4 Overview of Simulation Display Tools A useful method to evaluate a simulation is to examine and make measurements on the simulation results. Waveform display tools are used to display simulation data. Some waveform display tools and related software tools include: ■ WaveScan ■ Waveform Window (AWD) ■ Waveform Calculator (WaveScan & AWD) ■ Results Browser ■ Snapshot Tool ■ Annotating Component Display Simulation Results Display Tools 4-5 Overview of Simulation Display Tools This module discusses the numerous methods and software tools that are used to display simulation results. Waveforms, printed tables, histograms are some methods that are used. In this module, the focus is on viewing the simulation results. As such, the Waveform Window and the WaveScan tool are discussed. The results of a dc simulation will also be backannotated to the schematic. The Calculator and Result Browser will be discussed in the next module on Analyzing Simulation Results. 2/10/05 Virtuoso Analog Design Environment 4-6 WaveScan ■ Integrated as the default viewer in 5.1.41 ■ Reads psf, digital wsf, and sst2 data ■ Graphical interface is Java-based; data access is C++ ■ Accessible from the Session—Options command window in ADE (to switch between AWD and WaveScan) or from the command line in Unix (enter wavescan) ■ Operates in either MDL or SKILL mode. Simulation Results Display Tools 4-7 WaveScan WaveScan options: -datadir Specifies the data directory to be opened on startup. -expr Run in either SKILL or MDL mode. -h or -help Displays the help message. -graphtemplatefile Specifies the graph template file to be used. The default is none. -readstate Specifies whether WaveScan should read the saved state file at startup. The default is true. -statefile Specifies the state file to be used. The default state file is wavescan.xml. -writestate Specifies whether WaveScan should write a state file when it exits. The default is true. -V or -version Displays the version number for WaveScan. -W Displays the sub-version number for WaveScan. 2/10/05 Virtuoso Analog Design Environment 4-8 The WaveScan Results Browser (Select Tools—Results Browser from ADE) Destination of new graph Menu Bar Toolbar File Location Filter Select Left Pane Right Pane Status Bar ■ Trace Modifier and Graph Type only available for AC data. Simulation Results Display Tools 4-9 The Results Browser Toolbar: Open, Plot signal, Signal to calculator, Difference of two signals, YvsY for two signals, Select sweep dialog Graph Destination: Append, Replace, New SubWin, New Win Location: Lets you type the path to the data directory you want to open. (The pull-down arrow displays the paths to the last 20 data directories opened in WaveScan.) Status Bar: Displays warning and errors or prompts you for further action. In ADE, If you run a simulation and then open WaveScan, the Results Browser displays the simulation results directory. Otherwise, the Results Browser opens up blank. In standalone WaveScan, if you specify a data directory using the -datadir command option, the directory is displayed. If you type the wavescan & command in the data directory that you last opened in the previous session, the directory is displayed. Otherwise, the Results Browser opens up blank. 2/10/05 Virtuoso Analog Design Environment 4-10 Selecting Signals Filter Tabs ■ The following methods are available for filtering signals: ❏ View all signals ❏ View only voltage, current, power, or Logic ❏ View by name: net* ■ Available choices depend on the dataset that is open Simulation Results Display Tools 4-11 Selecting Signals Filtering Datasets ■ Click in the text entry box and type the desired filter pattern. ■ WaveScan supports both regular expression syntax and shell syntax. This pattern works with the value selected from the cyclic field. For example, assume you want to display all voltage signals whose names begin with “net”. ❑ First, select V from the cyclic field next to the Filter field. ❑ Then do one of the following: if you are using regular expression syntax, type net.* to display voltage signals starting with net. ❑ If you are using shell syntax, type net* to display voltage signals starting with net. ❑ Click Apply or press the Enter key. ❑ WaveScan displays the signals meeting the filtering criteria you specified. regular syntax: l.* displays all files beginning with l. shell syntax: l* displays all files beginning with l. This is the default value. 2/10/05 Virtuoso Analog Design Environment 4-12 Plotting All your favorite plotting options are here: ■ Rectangular, Polar, Admittance, Impedance, Real vs. Imaginary ■ Swept Data: ■ Y vs. Y: ■ Difference of two signals: ■ Strip mode ■ Buses ■ Hide/Reveal objects ■ Zoom: X and Y, Pan ■ “Active” window: double-click on anything in window and its associated “Edit Attributes” form pops up. ■ Cursors ■ Labels ■ Accelerator keys: bindkeys Simulation Results Display Tools 4-13 Plotting Available “Accelerator” bindkeys. 2/10/05 Virtuoso Analog Design Environment 4-14 Plotting (continued) Menu Bar Tool Bar Graph Title Legend Marker Grids Graph Area Status Bar Label Area Simulation Results Display Tools 4-15 Plotting (continued) ■ A graph created for the first time is displayed in a new Graph Display window. ■ If a Graph Display window is already open, the destination for the new graph must be specified. ■ Signals may be added to a selected graph. If the trace shares the same unit, it is assigned to the same Y-axis; otherwise, it is assigned to a new Y-axis. ■ If the selected graph window already has four Y-axes, WaveScan creates the new graph in a new subwindow. 2/10/05 Virtuoso Analog Design Environment 4-16 Data Ranging ■ Can plot a portion of a simulation run ■ Execute Settings—Select Data (or click “Select sweep dialog” icon: ) ■ Change time to desired scale Simulation Results Display Tools 4-17 Data Ranging The data ranging feature in WaveScan makes it easy to use a very large dataset efficiently by opening just the portion of the dataset that you need. ■ If you specify a particular time range in a transient analysis, then the dataset will plot the signals over just that range. ■ However, you cannot view anything outside the range you have chosen: the time must be reset to another range in order to see a different data range. ■ The WaveScan calculator can be used on data-ranged waveforms; however, it ignores the data ranging. 2/10/05 Virtuoso Analog Design Environment 4-18 Parametric Data ■ Can plot all parametric sweeps or selected sweeps ■ Plots both Virtuoso Analog Design Environment parametric data and Spectre “sweep” data ■ Can modify range data as well. Simulation Results Display Tools 4-19 Parametric Data A sweep analysis sweeps a specified parameter and executes the list of analyses for each value specified. You can then plot the signals for the selected sweep variables in WaveScan. You can also bring the signal information into the Calculator and apply a max function to it. In the example above, plotting max V(out) results in the maximum value of each trace on the Y-axis, and the vdd values used in the sweep on the X-axis. Each trace corresponds to a different temp value. 2/10/05 Virtuoso Analog Design Environment 4-20 Plotting Options ■ Layout can be quickly changed: Horizontal, Vertical, Strip, Card ■ Strip mode is available (scroll bar is automatically added if many strips are plotted) Simulation Results Display Tools 4-21 Plotting Options By making selections from the GRAPH pulldown menu, you may select a wide range of plotting and viewing options. ❑ Horizontal ❑ Vertical ❑ Strip ❑ Card Active plot windows will always be denoted by a highlighted indicator in the upper right of the plot window, or by trace highlights in the selected window. 2/10/05 Virtuoso Analog Design Environment 4-22 Plotting Options (continued) ■ Layout may be locked in; aspect ratio no longer the only way to set layout ■ When plotting many subwindows, you can change the view to “Card” Card view select Simulation Results Display Tools 4-23 Plotting Options (continued) Card view allows you to “stack” the graph view like a deck of cards, then select the desired view by clicking on a View Number in the upper right hand corner of the Graph Window. 2/10/05 Virtuoso Analog Design Environment 4-24 Tables (Tools—Table from Results Browser) ■ Tables can display a variety of information ■ Tables are data-specific; the above table shows bjt dcOp-Info, but tables can also show bjt, bsim3v3, capacitor, isource, resistor, vcvs, and vsource ■ Any waveform or calculator expression may be printed in a table ■ Table formatting options: transpose rows and columns, move columns, modify scale, modify significant digits, column headers, resize columns, hide columns, sort ■ Table saves data to pointer file; ascii save is available Simulation Results Display Tools 4-25 Tables ■ Tables may be created at the dataset or subcircuit level. ■ WaveScan generates a separate table for each primitive. ■ Display the table for a particular primitive by selecting the primitive from the cyclic field at the bottom center of the Report Table window. The instances in the dataset or subcircuit are displayed in rows, and the output parameters for each instance are displayed in columns. ❑ Instances: WaveScan displays the instance in a row and the output parameters in columns. ❑ Parameters: WaveScan displays the instance and parameter. ■ When creating a table for parametric scalar data, WaveScan displays the sweep points for all primitives. ■ A new table is opened each time; there is no way to add information to an existing table. Arrow keys scroll between different types of data (e.g., bjt, bsim3v3, resistor, etc.). 2/10/05 Virtuoso Analog Design Environment 4-26 Reloading Data ■ If you resimulate your design, WaveScan automatically reloads the data: ❏ No “Refresh” needed ❏ New graphs plotted with new data ❏ Existing graphs are not updated ■ File—Reload will update all unfrozen graphs with new data ■ Graphs can be “frozen” using Graph—Freeze On ❏ No new data will be allowed in subwindow ❏ All new plots go in a separate subwindow Simulation Results Display Tools 4-27 Reloading Data While resimulating your design, you can: Update the data directory— ❑ The Results Browser re-reads the data. You can thus look at results as the simulation is running. All new graphs you create display the updated data, which helps you in monitoring long simulations. Existing graphs are not updated. Reload the data directory— ❑ The Results Browser re-reads the data and updates all associated graphs except frozen graphs. To update a data directory, ❑ In the Results Browser window, choose the data directory from the Location pull-down. ❑ Click in either panel. ❑ Choose File—Open to open the data directory again. ❑ Click on a toolbar icon or menu option. To reload a data directory and update all associated graphs, ❑ Select the data directory and choose File—Reload. Note: If the Graph Window displays a graph of data that does not exist after the data directory is reloaded, the graph is erased unless it is frozen. 2/10/05 Virtuoso Analog Design Environment 4-28 Digital Signals ■ Digital signals are plotted at top of WaveScan window in strip mode Digital Analog ■ Create Bus—Select Traces, then Trace—Bus—Create (or click ) ■ Expand Bus—Select Bus, then Trace—Bus—Expand (or click ) ■ Mixed-signal plotting still available; analog appears below digital. Simulation Results Display Tools 4-29 Digital Signals The previous slide shows a Graph Window with mixed analog and digital signals. You can create a bus from digital signals or other buses; and you can expand a bus to view the component signals. Creating a Bus ❑ In the Graph Window, select the digital traces from which you want to create a bus. ❑ Select traces in order of significance (top to bottom) as shown in the figure below (most significant bit to least significant bit). ❑ Execute Trace—Bus—Create. The selected traces form a bus. The bus replaces the selected signals. To expand a bus: ❑ Select the bus you want to expand. ❑ Choose Trace—Bus—Expand. WaveScan displays the individual traces in the selected bus. 2/10/05 Virtuoso Analog Design Environment 4-30 Saving and Printing Graphs and Data You can save the entire waveform window or individual trace information: ■ File—Save to save the graph (saves current waveform window) ❏ Format is XML; file saved as *.grf ❏ Graphic formats supported: PNG, BMP, TIFF ■ You can save graph information to a file ❏ Saves a pointer to data file, no real data saved in file. ❏ Need to “save trace” to get ascii data (Trace—Save) ■ Open a saved graph by selecting: ❏ File—Open Graph—Open Graph as Plot... You can create “template” graph file so new graphs will have same attributes: ■ File—Open Graph—Open Graph as Template... ■ Current graph can become template: Graph—Template—Set Current You can print the graph or part of a graph, from the Graph Window: ■ File—Print: prints selected subwindow ■ File—Print All: prints all visible subwindows Simulation Results Display Tools 4-31 Saving and Printing Graphs and Data A saved graph saves the following information: ■ The location to the data (data directory, data set, and trace name); not the actual data. Therefore, if your simulation data changes between sessions, the graph reflects those changes. ■ Most graph attributes such as grids, background and foreground color, labels, and markers. Use Trace—Load for ascii files to compare “golden” data to current simulation run. Suffix line from .wsenv file: wavescan.graph fileSuffix string “grf” Important Save does not check to see if the file name exists. Make certain to use a unique file name when saving. 2/10/05 Virtuoso Analog Design Environment 4-32 Calculator ■ User interface is Java-based Menu Bar Analysis Mode Select Dataset Label Buffer Analysis Tabs Buffer Pulldown Functions Panel Status Bar Filters ■ RPN and algebraic mode available Simulation Results Display Tools 4-33 Calculator Open calculator in ADE by selecting Tools—Calculator or clicking on CIW, choose Tools—Analog Environment—Calculator or from the The Family checkbox is available only when the Select Mode checkbox is selected. When the Family checkbox is selected and you select a trace from a set of parametric leaf waveforms, WaveScan enters an expression for the entire family in the calculator buffer. Select Mode—Enables you to select signals; any signal you select is displayed in the calculator buffer. You can select signals from the ❑ Results Browser ❑ Graph Window ❑ Schematic window (only in ADE WaveScan) Buffer—Displays expressions or results. Plot Destination—Displays the available destinations for plotting the result of your expression. ❑ Append—adds the result to the selected Graph Display window ❑ Replace—replaces the selected graph (or subwindow) with the result of your expression ❑ New Subwin—plots the result in a new subwindow ❑ New Win—plots the result in a new window Note: You cannot perform simple arithmetic operations in the calculator if you open it without selecting a dataset or signal. 2/10/05 Virtuoso Analog Design Environment 4-34 Calculator Functions ■ Select Signal in Results Browser automatically seeds buffer ■ One window: no popup forms ■ Dynamically changes depending on what function is called Function Panel Simulation Results Display Tools 4-35 Cns (continued) Function Panel ■ Displays the list of available functions. The functions displayed depend on the selected category. When you select a single-parameter function, it is displayed in the calculator buffer. When you select a multi-parameter function, the parameter panel for the function appears. For example, when you select slewRate, the function panel displays the parameter list for slewrate. Default values for each optional field are displayed. If you want to return to the default values for the parameters after over-writing them, click Defaults. Filter Area ■ You can use the filter in the calculator to display a subset of the available functions. 2/10/05 Virtuoso Analog Design Environment 4-36 Calculator Functions (continued) Schematic Expression Buttons Buffer Pull Down ■ Hit “Eval” to evaluate buffer (RPN mode) ■ Can plot expressions that evaluate to a waveform ■ Selecting from the Select Mode tab prompts for a schematic input. Simulation Results Display Tools 4-37 Calculator Functions (continued) Schematic Expression Buttons The buttons allow you to enter data to the buffer by selecting objects in the Schematic window. The schematic expression buttons are available only in the ADE WaveScan calculator and are enabled only if the Select Mode checkbox is selected. Buffer Pull-down In the RPN mode, buffer pull-down displays the current stack. In the algebraic mode, buffer pull-down displays a list of previously evaluated expressions. 2/10/05 Virtuoso Analog Design Environment 4-38 Calculator Filtering ■ Functions may be filtered to be relevant to a particular data type: ❏ Frequency, General, Math, Modifier, Statistics, Transient, Trig, PoleZero ■ Functions available (see the Wavescan Users Guide for more details): ❏ 1/x, 10**x, abs, acos, acosh, angle, argmax, argmin, asin, asinh, atan, atanh, average, b1f, bw, ceil, cfft, clip, compression, compressionVRI, conj, convolve cos, cosh, cplx, cross, crosscorr, crosses, d2r (degrees-to-radians), db10, db20, dBm, delay, deltax, deriv, dft (Discrete Fourier Transform), dftbb, dutycycle, dutycycles, ex,p eyeDiagram, falltime, fft, flip, floor, foo, fourEval, freq, freq_jitter, ga, gac_freq, gac_gain, gainBwProd, gainmargin, getAsciiWave, gmax, gmin, gmsg, gp, gpc_freq, gpc_gain, groupdelay, gt, gumx, harmonic, harmonicFreq, histo, ifft, iinteg, im, imag, int, integ, ipn, ipnVRI, kf, ln, log10, lsb (Load Stability Circles), lshift (Left Shift), mag, max, min, mod, movingavg, nc_freq (Noise Circles - Sweep Frequency), nc_gain (Noise Circles - Sweep Level), nf, nfmin, overshoo,t period_jitter, phase, phaseMargin, phaseNoise, pow, pp (peak-to-peak), psd (Power Spectral Density), psdbb (Power Spectral Density Baseband), pzbode, pzfilter, r2d (radians-to-degrees), re, real, risetime, rms (root-mean-square), rmsNoise, rn, Rn, root, round, s11, s12, s21, s22, sample, settlingTime, sign, sin, sinh, slewrate, snr, spectralPower, sqrt, ssb, stathisto, stddev, tan, tangent (Tangent Line), tanh, thd (Total Harmonic Distortion), trim, value, window, x**2, xmax, xmin, xval, y**x, ymax, ymin, yval. Simulation Results Display Tools 4-39 Calculator Filtering Click in the Filter text frame and type the filter pattern. This pattern works with the value selected from the cyclic field. For example, assume you want display all math functions whose name begin with c. ■ First, select Math from the cyclic field next to the Filter field. ■ Type in the necessary information to display math functions starting with c: ❑ If using regular expression syntax, type c.* ❑ If using shell syntax, type c* ■ Click the check mark to the left of the type-in field or press the Enter key. ■ The functions meeting the filtering criteria you specified are displayed. 2/10/05 Virtuoso Analog Design Environment 4-40 The Waveform Window (AWD) Double-click on any item in the window to display an options form that controls it. Simulation Results Display Tools 4-41 The Waveform Window Use the left mouse button to double-click on any item in the Waveform Window to display a form that controls it. Additionally, many of the schematic editor features, such as bindkeys, selection, deletion, and drag to move an item, are supported within the Waveform Window. You can easily save and recall waveform setups. There is no limit on the number of curves that can be plotted, or on the number of subwindows into which a single Waveform Window can be split. Use the annotation features from the Virtuoso Analog Design Environment window to display such items as the temp = 25, beta = 100, and CAP = 500f labels in the Waveform Window selected. In addition, display the design name, temperature, scalar outputs, design variables, and simulation date. These labels are turned on in the Setting Plotting Options form, which are accessed by the Results—Printing/Plotting Options command in the simulation window. This is discussed more in the next module, Analyzing Simulation Results. 2/10/05 Virtuoso Analog Design Environment 4-42 Waveform Window Features 1 2 Layout of Window Independent Subwindows Strip Mode 3 4 AC Response B Gain (dB) A* Phase (deg) Labels Vertical and Horizontal Markers Crosshair Markers w/ On-Screen Display Select Letters A or B to Delete Markers Frequency A: (40.37M 270.6m) B: (2.946K 1.26) delta: (-40.08M 1.233) slope: 3.076u Simulation Results Display Tools 4-43 Waveform Window Features Place as many as many curves on a single strip as desired, and each subwindow can use a different window setup. Additionally, a single strip or composite window can have from 1 to 4 Y-axes, with user-assigned curves on each axis. Waveform curves can be selected and their colors and design styles can be changed with a simple options form, which modifies your Waveform Window to display X/Y Plots. Both vertical and horizontal markers are available. In addition, crosshair markers, which display information directly on the Waveform Window, can be used for quick measurements. To delete the A and B markers, select the letter (A or B) that labels the marker and note the asterisk that appears next to it. Next, click the Delete icon. Axes labels can be modified, and there is a main title along with separate subtitles that can be used on each subwindow. Add labels that use calculator expressions, which update with each successive simulation. Display multiple Waveform Windows at the same time. Use one window to display results from a previous simulation run, while a new window displays the current data. Use the Waveform Window interactively with the Calculator (discussed later). Pan and zoom in the window, too. 2/10/05 Virtuoso Analog Design Environment 4-44 Waveform Calculator The Waveform Calculator Tool is integrated into the Virtuoso Analog Design Environment as a part of AWD (Analog Waveform Display). In version 5.1.41, the WaveScan viewer is integrated into ADE as well and may be selected from the Options menu in the ADE main form. Simulation Results Display Tools 4-45 Waveform Calculator The Calculator displays numerical results of the simulation data. It also processes waveform data obtained from the schematic, the Waveform Window, or the Results Browser. 2/10/05 Virtuoso Analog Design Environment 4-46 The Waveform Calculator (AWD Shown) In the Simulation Environment, select Tools—Calculator. In the Waveform Window, select Tools—Calculator or click the Calculator Icon. In the CIW, select Tools—Analog Environment—Calculator. Calculator Buffer Menu Banner Selecting waveform data Printing and Plotting Special Functions Math Functions Enter data from schematic Numeric Keypad UserProgrammable Function Keys Simulation Results Display Tools 4-47 The Waveform Calculator Use the Waveform Calculator to: ■ Build, print, and plot expressions containing your simulation output data. ■ Build expressions to be used with labels in the Waveform Window. ■ Enter expressions (which can contain node voltages, port currents, operating points, model parameters, noise parameters, design variables, mathematical functions, and arithmetic operators) into a buffer. ■ Store the buffer contents into a memory and then recall the memory contents back into the buffer. ■ Save calculator memories to a file and load those memories back into the calculator. The Waveform Calculator User Guide has more instructions concerning calculator usage and functionality. This is available through the CDSDoc documentation library. 2/10/05 Virtuoso Analog Design Environment 4-48 Postprocessing Data with the Waveform Calculator There are four ways to enter data into the calculator: 1. Probe in the schematic window using the import buttons (vt, vf, it, and if). 2. Probe in a Waveform window using the wave button. 3. Use the Results Browser. 4. Type in a signal name or expression. ■ Plot results or evaluate buffer expressions. ■ Use the printvs button to print data tables to a file. ■ Special functions are available, including Discrete Fourier Transforms (DFTs), rise times, gain margin, phase margin, and slew rates. ■ Use the Calculator in Reverse Polish Notation (RPN) or Algebraic mode. ■ A special RF mode is available. Simulation Results Display Tools 4-49 Postprocessing Data with the Waveform Calculator Enter information into the calculator in four ways. Enter simulation output expressions (such as node voltages, port currents, operating points, model parameters, and noise parameters) into the buffer by probing in the schematic. Also select simulation output directly from Results Browser. The wave button selects signals in the Waveform windows, and imports it into the calculator buffer for processing. The Results Browser (discussed later in this module) locates the data file with signal information. A left click on the signal name enters the signal data into the buffer of the calculator. 2/10/05 Virtuoso Analog Design Environment 4-50 Waveform Calculator, Special Functions Key Press “Special Functions” to display waveform processing functions. Functions include: integral derivative dft delay eye diagram thd Simulation Results Display Tools 4-51 Waveform Calculator, Special Functions Key The Waveform Calculator is a special tool for analyzing simulation data, including waveform analysis. The “Special Functions” key provides preprogrammed operations that simplify the process. The 47 different functions include: ■ Discrete Fourier Transform ■ Total Harmonic Distortion ■ Bandwidth Measurement ■ Frequency ■ Automated Delay Measurement ■ The “eye-diagram” Use the special functions to simplify measurements of your simulation results. These functions are available for automated measurements using Corners, Monte Carlo, and with OCEAN scripts. 2/10/05 Virtuoso Analog Design Environment 4-52 Controlling Schematic Label Displays In the schematic window, execute Edit—Component Display. Modifies cdsTerm ( ) labels Modifies cdsParam ( ) labels Modifies Instance labels Simulation Results Display Tools 4-53 Controlling Schematic Label Displays This form controls the label displays at different levels: ■ Instance Level: Affects a selected instance ■ Cell Level: Affects all instances in the cellview with the same cell name as the selected instance. ■ Library Level: Affects all instances in the cellview from the same library as the selected instance. Save label display changes to a file. ■ Attach label displays to a library, so the latest settings appear when a design opens. ■ Label display changes at the instance level are always saved with the design. Modify these settings later on at the instance level only. In addition, terminal and instance labels can have different values in the simulation and schematic environments. This is due to design hierarchy. For example, if an instance of the amplifier cell is placed in a hierarchical design, an nmos transistor in the amplifier schematic might be named M2. In the final netlist, the transistor might appear with a name of xi0/m2. Similarly, a terminal can appear to be named net52 in the amplifier schematic, but might have a name of xi0/net52 in the final netlist. The schematic and simulation values of terminal and instance labels can be displayed, too. 2/10/05 Virtuoso Analog Design Environment 4-54 Annotating Simulation Information to the Schematic DC Operating Points Annotation labels appear near all components in the design window. ■ Display configurations can be saved and loaded again. ■ Unless explicitly saved, the database is overwritten or lost when exiting the Design Framework II session. ■ The Design Defaults command removes annotated simulation data and restore design information on the schematic. ■ Use Results—Print command and menus to print results to a file. Simulation Results Display Tools 4-55 Annotating Simulation Information to the Schematic Annotate simulation information to the schematic window with the Results—Annotate command and menu in the simulation window. Print the same data to a file using the Results—Print command and menu. The annotation is achieved through the interpreted labels on component symbols that serve as “placeholders” for the data to be displayed. Set the visibility and type of data by using the Label Display menu. Bring up the Label Display menu with the Edit—Label Display command in the schematic window. Apply changes to all cells in the design window, to all cells in the library of the selected instance, to the same cells as the selected instance, or to only the selected instance. The different types of interpreted labels are: ■ terminal or cdsTerm(pin_name) labels: Display net names, pin names, node voltages, port currents and node numbers (referenced to either the design environment or simulation netlist). ■ parameter or cdsParam() labels: Display component parameters, model parameters, transient data, and operating points. Hierarchical variables can be displayed literally or evaluated. ■ instance or cdsName() labels: Display instance or cell names (referenced to either the design environment or simulation netlist). Note: Show Parasitics and Hide Parasitics are activated only in out of context mode. 2/10/05 Virtuoso Analog Design Environment 4-56 Labs Lab 4-1 Displaying Results and Using the Calculator with WaveScan Lab 4-2 Saving the Simulation Session Lab 4-3 Displaying Interpreted Labels Near Schematic Components Lab 4-4 Annotating Simulation Results to the Schematic Window Lab 4-5 The Waveform Calculator Simulation Results Display Tools 4-57 Labs 2/10/05 Virtuoso Analog Design Environment 4-58 Lab Reference Material When using a command such as Outputs—To Be Plotted—Select On Schematic or Outputs—To Be Saved—Select On Schematic in the simulation environment, follow the prompts in the schematic window or CIW to graphically probe the design. When finished probing all desired nodes and terminals, press the Esc key with the cursor in the design entry window to cancel the select function. Failure to cancel the select function explicitly before starting a different one, might temporarily disable the system. If this condition occurs, the Nest Limit of the environment has been violated, and a warning appears in the CIW. Change the Nest Limit with the Options—User Preferences form through the CIW to get around this feature. Make sure to cancel each selection or probing function using the Esc key when done. Simulation Results Display Tools Lab Reference Material 4-59 2/10/05 Virtuoso Analog Design Environment 4-60 ® 5 Analyzing Simulation Results Module 5 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 5-2 Topics in this Module ■ The Print engine ■ Storing and managing simulation results ■ The Results Browser ■ Conditional search and display ■ Device Check in ADE ■ The Spectre sweep feature ■ Sensitivity Analysis ■ Stability Analysis Analyzing Simulation Results 5-3 Terms and Definitions Terms and Definitions evaluate buffer Command to evaluate data or expression of the calculator buffer. erplot Erase Waveform Window and plot data of calculator buffer. Print Engine Cadence software tool used for printing specified simulation data. Results Browser Cadence software tool used to browse and select simulation data. Circuit Conditions A feature that allows circuit conditions to be view on the schematic. Spectre Sweep A series of simulations viewed as a curve over a selected range. 2/10/05 Virtuoso Analog Design Environment 5-4 Print Engine ■ Printed results are displayed in a “smart” print window. ■ Examples of printed results: ❏ All Results—Print commands ❏ Print and Report commands from OCEAN ❏ Simple or parametric waveforms ❏ Generic tabular data (such as Monte Carlo data) ■ Tabular data can be further formatted using form-driven interface. (Move columns, sort, and expressions.) Analyzing Simulation Results 5-5 Print Engine The print engine works best for tables of numbers. For example: ■ The output of the calculator printvs command for several outputs over a set of transient time points is well suited for the print engine. All columns are related (all from the same time point) and functions like sorting, moving columns, and operating on the all data points in a column with expressions makes sense. ■ The output of the DC operating point on a transistor, however, is not well suited to the print engine, because it is described by several columns of unrelated numbers. For consistency, this function uses the Print Engine window to display results. However, no further manipulation on the data can be done because the columns are unrelated. 2/10/05 Virtuoso Analog Design Environment 5-6 Printing the Results Specify the results to print: ■ Run a simulation. ■ Then in the Simulation Window, select Results—Select. A Select Results window appears. This window lets you select other simulation results. (Make sure the schematic window for the selected design is open.) ■ To print the results, select Results—Print with one of the following options: ❏ DC Node Voltages or DC Operating Points ❏ Model Parameters ❏ Transient Node Voltages or Transient Operating Points ❏ S-Parameter ❏ Noise Parameters ❏ Noise Summary or PSS Noise Summary ❏ Sensitivities ■ Select a node or device in the schematic window. Analyzing Simulation Results 5-7 Printing the Results DC Operating Points: Choose Results—Print—DC Operating Points. Move your cursor into the schematic window. The CIW displays prompts to select instances for the operating point output. Click an instance. Transient Operating Points: Choose Results—Print—Transient Operating Points. Move your cursor into the schematic window. The CIW displays prompts to select instances for the transient operating point (OPT) output. Click an instance or node. Model Parameters: Choose Results—Print—Model Parameters. Move your cursor into the Schematic window. The CIW displays prompts to select instances for the model parameter output. Click an instance of a device. Noise Parameters: Choose Results—Print—Noise Parameters. Set a frequency in the Select Frequency Value form that appears. If the form does not appear, press the F3 key. The default frequency is 1K. Move your cursor into the schematic window. The CIW displays prompts to select instances for the VNP output. Click on an instance or node. DC Node Voltages: Choose Results—Print—DC Node Voltages. Move your cursor into the Schematic window and select nets for the VDC output. Click a node. Transient Voltages: Choose Results—Print—Transient Node Voltages. Enter a time in the Select Time Value form that appears. If the menu does not appear automatically, press the F3 key. The default time value is zero. Move your cursor into the Schematic window. The CIW displays prompts to select nets for the time value output. Click a node (net8, for example). Sensitivities: Choose Results—Print—Sensitivities. Move your cursor into the Schematic window and select nets for the output. Click on a net or port. 2/10/05 Virtuoso Analog Design Environment 5-8 Results Display Window After a simulation run, select printvs from the calculator window, and provide the printvs range. Pull-Down Menus Analyzing Simulation Results 5-9 Results Display Window The Results Display Window offers a comprehensive suite of tools to process simulation data. 2/10/05 Virtuoso Analog Design Environment 5-10 Run Data Storage Directories Subdirectories are created below the project directory to define a unique storage location for simulation results. ■ The project directory is specified in the Simulation environment. Hierarchy Level Project Directory/Cell_Name/Simulator_Name/Run_Name/Run_Data Example ~/simulation/ampTest/spectre/schematic/ (netlist/ or psf/) ■ Data storage directories can be managed with UNIX commands. ■ Numerical simulation data is written to a binary file in Parameter Storage Format (PSF), which is stored in the psf/ directory. ■ The final netlist and text files related to netlist generation are stored in the netlist/ directory. Analyzing Simulation Results 5-11 Run Data Storage Directories Run data is stored in this location: //// Names in brackets represent directories on the system as defined below: User-defined directory defined in the Simulation environment. Name of the simulated cell as it appears in the Library Manager. Name of the simulation engine used. Always /schematic unless the is moved by the user. The /schematic directory is overwritten on the next simulation. We discuss saving methods later. Run_Data contains two subdirectories. The /psf directory holds all the numerical run data. This includes waveform data, initial conditions, model parameters, and operating points. The /netlist directory contains textual run data, including the netlist and simulator output files. 2/10/05 Virtuoso Analog Design Environment 5-12 Backing Up Simulation Data Explicitly The /schematic directory is overwritten during subsequent simulation runs of the same design. To preserve simulation data, use the Results—Save command. Results—Save Analyzing Simulation Results 5-13 Backing Up Simulation Data Explicitly If automatic simulation results saving is disabled, then save the simulation results explicitly. To do this, copy the results data directories to user-defined locations. Attach comments to the data directories for use when selecting results in the Simulation environment. Use this command to back up an automatically saved run directory or save it with a more meaningful name. 2/10/05 Virtuoso Analog Design Environment 5-14 Selecting Results Load results from previous simulations. Results—Select... Analyzing Simulation Results 5-15 Selecting Results By specifying the location of a psf/ directory, past simulation data is linked to a schematic window. Probe the schematic to analyze older simulation results and compare them with current data. Use this feature when exiting the Virtuoso Analog Design Environment or logging out to retain the simulation data upon resuming work. Note: The schematic window used to generate the simulation data must be open when saving the results. Additionally, save the .artist_states used to create the simulation results. Important Never edit the schematic in a way that changes the topology. The saved data corresponds to the schematic at the time the simulation is run. If you must change the schematic, consider an alternate cell or view name. Otherwise, the simulation data linked to the edited schematic is not meaningful. Make a copy of the design, and edit the copy, leaving the original design to link simulation results in the future. Failing to follow this practice does not render the saved data useless, even if the topology changes; however, you can no longer click on an internal node of the schematic. Use the Results Browser to access the data for plotting and post-simulation analysis. Hints for Saving Simulation Data Copy the /schematic directory to a directory whose name contains the design name and date of last modification. This helps to keep the results pertinent to the proper design. PSF is an efficient storage format, and the files in the /psf directory can be compressed to further save disk space. When deleting files in the /netlist directory, use caution as some of the data may be needed later on. 2/10/05 Virtuoso Analog Design Environment 5-16 Setting Plotting Options Location and size of Waveform Window Results—Printing/Plotting Options Analyzing Simulation Results 5-17 Setting Plotting Options Plotting Options can be set with the following commands: ■ Auto Plot After Simulation: Instructs the software to automatically plot the selected signals and waveform expressions contained in the Outputs list box of the Simulation window, after the simulation ends. ■ Overlay Plots: This is part of the automatic plotting feature of the Virtuoso Analog Design Environment. If Overlay Plot is OFF (default), the Waveform Window is always erased before a new waveform is drawn. If Overlay Plots is ON, a new waveform is plotted on top of the old waveform. This is useful for comparing simulation results on the same design with parameter changes. ■ Direct Plots Done After: This refers to the Direct Plot commands. The default is to plot signals after All Selections Are Made. Change the setting so that the Waveform Window is updated immediately after Each Selection on the schematic. ■ Annotations: This feature displays information such as Design Name, Temperature, and other parameters shown above, in the Waveform Window. This makes simulation results more complete for archiving purposes. ■ Waveform Window options: These options affect the physical appearance of the Waveform Window. Turn the icons in the window on or off, change the font size used for labels, and change the size and location of the Waveform Window. These choices have the greatest impact on the Waveform Window that is generated with automatic plotting after the simulation ends. 2/10/05 Virtuoso Analog Design Environment 5-18 Annotating Data to the Waveform Window Annotation—Edit Waveform Window Build expressions in the Calculator and use them to create labels in the Waveform Window. Analyzing Simulation Results 5-19 Annotating Data to the Waveform Window Use the calculator to build expressions to use with labels in the Waveform Window. Use these labels to annotate important measurements to waveforms in datasheets or other documentation. 2/10/05 Virtuoso Analog Design Environment 5-20 Starting the Results Browser In the Simulation Environment or Waveform Window, select Tools—Results Browser. In the CIW, select Tools—Analog Environment—Results Browser. In the Calculator, click the Browser button. Specify a Project Directory. The Results Browser accesses data in the Project Directory and below. Examples of Project Directories ./simulation/ampTest/spectre Accesses all Spectre results for this design. ./simulation/ampTest Accesses all results for this design. Analyzing Simulation Results 5-21 Starting the Results Browser This Results Browser is a powerful simulation data management tool that is similar in appearance and functionality to a tree browser. Specify a project directory to display the Results Browser. The project directory is the highest directory the browser can access. Set this high enough to access required simulation data. Note, use the Results Browser to load in and view simulation data without having the schematic open or available. This is useful in sending simulation data between two or more locations of a design center in an efficient manner. 2/10/05 Virtuoso Analog Design Environment 5-22 The Results Browser The Results Browser is similar to the Library Manager. An object menu can manage or expand the data structure. Expanding the psf directory Interpretation of the PSF binary data ac-ac dcOp-dc schematic/ netlist/ psf/ Run1 Expand (L) Expand FS Plot (R) Expression dcOpInfo-info element-info finalTimeOP-info modelParameter-info outputParamer-info tran-tran variables /vin /out /net9 /I10/gnode /I10/net18 /vdd! Refresh Delete Rename... Properties... Categories of analysis data Waveform or numerical expressions Create ROF Right Mouse Button: Plot the signal Select Results Left Mouse Button: Paste signal expression into Calculator buffer Analyzing Simulation Results 5-23 The Results Browser The Results Browser Object Menu There is an Object Menu (OM) for the Results Browser. For a complete description, see CDSDoc. Unlike the Library Manager, the Results Browser OM does not change depending on the selected text. Expand is bound to the left mouse button as indicated by the (L) in the OM. Use this command at all levels of the Results browser. Plot is bound the right mouse button as indicated by the (R) in the OM. Move a data quantity such as a waveform, to the post processing tool with the Expression command. Use Delete or Rename for directories. The Create ROF command translates ASCII output data from a standalone simulation engine into the PSF format for use with the Waveform Window. Also Select Results from a data directory and link them to a schematic window if the simulation window is open. Postsimulation Data Structure Categories element-info contains component parameters for design circuit elements. modelParameters-info contains simulation model parameters. dcOp-dc contains the node voltages calculated from the DC operating point. dcOpInfo-dc contain operating point information for all of the component parameters in the design. tran-tran contains waveform data from the transient analysis. ac-ac contains waveform data for the AC analysis. 2/10/05 Virtuoso Analog Design Environment 5-24 Viewing Presimulation Text Data Click the names of text files with the right mouse button in the Results Browser to view their contents. Expanding the Netlist Directory Data from simulation runs Final Netlist OCEAN Scripts Analyzing Simulation Results 5-25 Viewing Presimulation Text Data At the schematic level, there can be more than one simulation, but each must have a distinct name from the others. There can then be a tree structure under each of these runs similar to the one shown above under schematic. Textual data includes netlists. Expand the textual data entries in the Results Browser as illustrated and click on the name of file for viewing. A window appears containing the text. 2/10/05 Virtuoso Analog Design Environment 5-26 Interactive Postprocessing Tools Schematic Editor 2 Window Edit Schematic Simulation Environment Waveform Window 2 Tools Window A Calculator B A+B Analyzing Simulation Results 5-27 Interactive Postprocessing Tools Take advantage of powerful interactive post processing tools in the Virtuoso Analog Design Environment. 2/10/05 Virtuoso Analog Design Environment 5-28 Conditional Search and Display ■ Form-driven search, probe, and print for specified device operating conditions. ■ Finds and displays breakdown conditions, MOSFETs in linear region, and saturated BJTs. ■ User-configurable search criteria ■ Includes multiple constraint (Boolean) searches. Analyzing Simulation Results 5-29 Conditional Search and Display After the simulation is finished, use this form to search through all operating point data for devices with certain conditions. Set up search conditions by using the Results: Circuit Conditions form. The boolean functions AND and OR are available to look for devices with multiple conditions. ■ For Spectre saturation, an instance is highlighted if: ❑ BJT: If the operating point parameter region=3 ❑ MOS/BSIM: If the operating point parameter region=2 ■ For cdsSpice saturation, an instance is highlighted if the operating point sat=0. ■ For Spectre breakdown in a BJT, an instance is highlighted if the operating point parameter region=4 ■ For cdsSpice breakdown, an instance is highlighted if the operating point bkdwn=0 ■ For the simulator to calculate breakdown or saturation, the appropriate model parameters need to be set. Currently, the conditional search capability only works for DC operating conditions. 2/10/05 Virtuoso Analog Design Environment 5-30 Setting Up a Conditional Search 1. Run a simulation or invoke Results—Select Results and choose other simulation results. This provides the results to search. 2. Choose Results—Circuit Conditions. 3. Select the Device Operating Conditions. 4. Set up the User-Defined Conditions. 5. View the Circuit Conditions results using the Place or Print buttons. Analyzing Simulation Results 5-31 Setting Up a Conditional Search 1. Run a simulation or choose which results to search using the Results—Select command. This feature only works when running a DC operating point analysis. 2. Choose Results—Circuit Conditions from the Simulation window to launch the Conditional Search form. 3. Choose device operating conditions to view components in the saturation (for BJT devices), linear (for MOS devices) or breakdown region. The appropriate model parameters must be set for the simulator to calculate these conditions. These features might not be available for simulators other than the Spectre or cdsSpice tools. 4. Set up the User Defined Conditions for cyclic and type-in fields to create custom search conditions . 5. To view the results of the conditions, click the Place button to highlight the instances that meet the specified conditions on the schematic. Click Print to print the values of instances that meet the specified conditions in a print window. 2/10/05 Virtuoso Analog Design Environment 5-32 The Circuit Conditions Form Analyzing Simulation Results 5-33 The Circuit Conditions Form The top left section provides buttons for turning the display of devices in the breakdown, saturation, and linear region on and off. Set the probe colors to help differentiate the conditions. The upper right section of the form is used to place and remove the graphical forms from the schematic. The lower portion of the form sets up the user-defined search criteria. 1. Pick a component type, such as bjt, mos, vsource, or resistor. 2. Choose the operating point parameter value from the cyclic field. 3. Set a lower and upper bound by typing a value on either side of the parameter. Leave either blank to set only one boundary. 4. Set the Boolean arguments to a condition. The options are: “none”, “and”, and “or”. When and is used, both conditions must be met for an instance to be highlighted. When or is used, either condition must be met for an instance to be highlighted. Both operators have the same precedence. 5. Set the probe colors. This field shows the color with which an instance that meets the condition will be highlighted. 6. Use the Enable field to turn a condition on or off without deleting it from the form. 7. Use the bottom buttons to Add, Delete, or Change an entry, or completely Clear the form. 2/10/05 Virtuoso Analog Design Environment 5-34 Device Check Interface to ADE ■ Allows the user to write custom characterization rules that check device, model, design parameters, or expressions against specified bounds. ■ Allows user to write rules that are complicated expressions in MDL syntax. ■ Checks the rules in DC, DC Sweep, and Transient analysis. ❏ Device Checking Setup ❏ Simulation Output ❏ Results Violation Display Analyzing Simulation Results 5-35 Device checking feature was introduced in spectre (standalone) in version 5.0.33 then integrated into 5.1.41. SOA—Safe Operating Area Spectre uses ‘assert’ statements to write these rules You can set checks for any of the following: ■ Top-level netlist parameter ■ Operating point parameter ■ Model parameter ■ Instance parameter ■ Expressions Spectre then prints messages either to a Spectre log file or to a dedicated violations file when rules are violated. Ability to control the checking of rules such as enable/disable, checking during a range of the independent variable of the analysis such as time. Currently not supported with advance analysis like Parametric, Monte Carlo, Corners. 2/10/05 Virtuoso Analog Design Environment 5-36 Device Checking Setup Simulation—Device Checking.... Analyzing Simulation Results 5-37 Device Checking Setup device checks before simulation Selections: ■ Select from schematic hierarchy ■ Check parameters, operating points. or expressions ■ Specify error level of check (Notice, Warning, Error) ■ Check-specific, custom messages ■ Enable/disable subset of checks ■ Checks can be part of model card, netlist, or any other file that is included for simulation as a part of the design. 2/10/05 Virtuoso Analog Design Environment 5-38 Device Checking Setup (continued) Simulation—Device Checking... invokes the following form, which is used to enter and manage asserts Analyzing Simulation Results 5-39 Device Checking Setup form Enable Device Checking is enabled by default. You can enter asserts using the graphical user interface to the netlist only when this button is enabled. list box field shows all the asserts that have been entered.ON/OFF under the Status column indicate whether the assert is enabled or disabled. Add brings up the Edit Device Check form which is used to add new asserts. Edit brings up the Edit Device Check form which is used to change a selected assert. Enable is used to enable one or more asserts selected in the list of asserts. The status of an assert is indicated by ON/OFF preceding the assert. Disable is used to disable one or more asserts selected in the list of asserts.This disables the assert for all analyses. Delete is used to delete one or more asserts (selected in the list of asserts). Up/Down are used to move a selected assert one position up or one position down. Options brings up a form where you can specify options such as start and stop times on the checklimit statement for transient analysis, severity for checklimit statements associated with dc and transient analyses. 2/10/05 Virtuoso Analog Design Environment 5-40 Editing Device Check Device/Model/Primitive Tab Analyzing Simulation Results 5-41 Edit Device Check : Device/Model/Primitive Tab You can create three types of asserts by selecting the type of check you want to create from the corresponding tab. Each tab contains fields applicable for that type of assert. The Name field allows you to specify names for an assert. These asserts apply to Instances, Models, or Primitives: The Subcircuit Master field is a boolean field. This field can be used to add sub=subckt to the assert statement. To the right side of this is a text entry field. This field becomes active only when the sub field in ON. Click on the Select button and select an instance in the schematic window. You get the subcircuit master name for that instance and put that name in this field. Below the Subcircuit Master field is a cyclic field from which you can select either Device, Model, or Primitive. If you select Device, the right side is a text entry field. Click on the Select button to select a device in the schematic. If you select Model or Primitive, the right side will be a cyclic field where you can select a model/primitive. assert0 assert sub=myAmp dev=M1 param=Vgs min=0.0 max=2.5 message=”Vgs exceeds bounds” assert1 assert sub=myAmp mod=trnmos modelparam=Vtho min=0.0 max=0.8 message=”Vgs exceeds bounds” assert2 assert sub=myAmp primitive=bsim3 param=Vgs min=0.0 max=2.5 message=”Vgs exceeds bounds” Below the Device, Model, or Primitive cyclic field is another pair of cyclic fields from which you can select Instant Parameter,Operating Point parameter, Model Parameter, Terminal Current, and Terminal Voltage. Under “Limits” section you can specify “min” and “max” values for the assert statement in their respective text fields. The Duration field is a text field that can be used to specify a duration for an assert for transient analysis. Under “Message Options” section, you can type in a message in the “Additional Message” text field (like “Vgs exceeds bounds”). This message will be printed when this assert statement is violated during simulation. From the “Severity” cyclic field, you can select “Notice”, “Warning”, “Error” or “None”. The tran, dcOp and dc sweep buttons are used to specify if the assert will be enabled during transient, dc, or dc sweep analysis. 2/10/05 Virtuoso Analog Design Environment 5-42 Editing Device Check (continued) Parameter Tab Analyzing Simulation Results 5-43 Edit Device Check: Parameter tab This is a cyclic field in which you can select a top-level netlist parameter whose value is to be checked. The choices for this cyclic field would be the design variables defined in ADE and the Spectre reserved parameters like temp, tnom, scale, scalem, freq, time, etc. asser3 assert param=cap min=2p max=5p message= “The capacitance exceeded bounds” 2/10/05 Virtuoso Analog Design Environment 5-44 Editing Device Check (continued) Expression Tab Analyzing Simulation Results 5-45 Edit Device Check: Expression Tab This tab can be used to specify the three types of asserts mentioned earlier. The expression field is a text entry field where you can enter an MDL expression. The select button is used to select a device in the schematic. When a device is selected, a form appears in which you can select one of the displayed parameters. The full simulator name for that instance followed by :paramname is appended to the existing text in the field. You can then add operators, functions, etc. to create an expression. assert4 assert expr=”(i1.x1:id - i2.x2:id)” min= - 0.001u max=0.001u duration=1n 2/10/05 Virtuoso Analog Design Environment 5-46 Device Checking Setup Options Click on “Options” button in the Device Checking Setup form gives following: ■ Settings go to checklimit statement ■ This severity setting overrides severity specified for individual assert Analyzing Simulation Results 5-47 Device Checking Setup Options This form is used to specify checklimit options such as start and stop times and severity of violations. Default values for severity is None. 2/10/05 Virtuoso Analog Design Environment 5-48 Simulation Output ■ Device Checking Options ❏ ADE: Simulation—Options—Analog ❏ Controls device checking ❏ Write violations to file (spectre.out), psf, or both ❏ checklimitfile written under netlist directory Analyzing Simulation Results 5-49 dochecklimit Check asserts in the netlist. Possible values are no or yes. This button controls whether you would like the simulator to do device checking or not. This button works with the “Enable Device Checking” button in the “Device Checking Setup” form. Note: The last setting wins regardless if it is in the “Simulator Options” or “Device Checking Setup” form. checklimitfile File to which assert violations will be written to. This file is written to a given file name under the netlist directory (i.e., /simulation/cellname/spectre/schematic/netlist). When a filename is given in this field, you will not get any assert violations in the log file. Instead, you will see a line in your log file like: All assert violations will be written to file ‘xyz’. checklimitdest=file Destination(s) where violations will be written to. Possible values are file, psf, or both. 2/10/05 Virtuoso Analog Design Environment 5-50 Device Check Violations Display After a successful Device Check simulation, Violations Display is highlighted Analyzing Simulation Results 5-51 Violations Display Results—Violations Display... menu command is highlighted after Device Check simulation results are available. This command will invoke the forms shown on the next page. You can highlight devices in violation in schematic. You can filter checks and view violations based on device name, device type, model name, device check, error level, and analysis. You can select schematic devices to display associated violations. You can get a textual results in the Results Display Window for one or multiple device checks and devices. 2/10/05 Virtuoso Analog Design Environment 5-52 Violations Display Analyzing Simulation Results 5-53 Violations Display The “Results—Violations Display...” gives the above forms depending upon your selection of “Basic Filter” or “Advanced Filters”. Select any (one, multiple, or all) device checks from the list: ■ Display Info—Prompts you to select a device in the schematic window and, after selecting it, prints out violations for chosen device check(s) for selected device(s). ■ Print—Prints all devices for a selected check(s). ■ Place—Highlights device in violations and Clear clears it. For Advanced Filters, there are extra buttons. ■ Mode—None, Exclusive or Inclusive In exclusive mode, any violations that match the current filter settings are ignored. For example, if the filter was set to “Device Type: bjt” then you would see all violations except those that were caused by instances of primitive “bjt”. In inclusive mode, you see only those violations that match the current filter settings. For example, if the filter was set to “Device Type: bjt” then you would see all violations caused by instances of primitive “bjt”. ■ Cyclic Field—Device Name, Device Type, Model Name, Device Check, Error Level, Analysis 2/10/05 Virtuoso Analog Design Environment 5-54 Violations Display (continued) Display Info Analyzing Simulation Results 5-55 Display Info—Prompts you to select a device in the schematic window and after selecting it, it prints out violations for chosen device check(s) for selected device(s). In the above window, we have selected “MN_5u” and “MN0” devices in the schematic. 2/10/05 Virtuoso Analog Design Environment 5-56 Violations Display (continued) Print Analyzing Simulation Results 5-57 Print—Prints result on all devices for a selected check(s). In the above window, we have selected “All_nmos_id_3u” device check from the violations display form and then clicked the “Print” button. 2/10/05 Virtuoso Analog Design Environment 5-58 Sensitivity Analysis Use the Sensitivity Analysis to: ■ View the parameters that most affect the specified outputs ■ Tune a design to increase or decrease certain goals ■ Determine what parameters to run in an Optimization analysis The Sensitivity Analysis requires a base analysis to be run first. ■ Only runs with AC and DC analysis at the present time. Analyzing Simulation Results 5-59 Sensitivity Analysis Sensitivity analysis allows a designer to see what parameters in the circuit most affect the specified outputs. It is typically used to tune a design to increase or decrease certain design goals. A designer many times will run a Sensitivity analysis to determine what parameters to optimize in the Optimizer. Sensitivity is a useful tool on its own but also has capabilities of tying in with other tools in the future. The Sensitivity Analysis project will provide a user interface to run the base Sensitivity Analysis provided by the Spectre tool. This will be created using the Virtuoso Analog Design Environment to add the Sensitivity analysis for the Spectre simulator. There will also be a user interface for printing the Sensitivity results. This will sort the sensitivity results with the most sensitive values being displayed first. The Sensitivity analysis currently runs with AC and DC analyses, only. The Spectre simulator generates model parameter sensitivities on a per model basis. If multiple devices in your circuit use the same model, the effect of changing a model parameter within that model is done on all those models at the same time. Optionally, treat each model as a separate entity per device, so when a model parameter is changed in the model on a device, it is only changed for that single device. To achieve this with the Spectre simulator, create multiples of the same model and place a different model on each device. This functionality will be simplified in future releases. 2/10/05 Virtuoso Analog Design Environment 5-60 Setting Up Sensitivity Analysis Select one of these and run the base analysis in addition to any selection here. Analyses—Choose Analyzing Simulation Results 5-61 Set Up Sensitivity Analysis Select Analyses—Choose in the Simulation window to display the Choosing Analyses form. Select sens, and click which base analysis (AC or DC) to run with the sensitivity algorithm. Also, set up a simulation for the specified base analysis for the Sensitivity Analysis to run. The form options are as follows: For base Select Outputs Delete Clear Enabled Select the base analysis to run for a sensitivity analysis. Default: none. Prompts to select nets or ports from the schematic. The schematic will appear in the foreground of the screen, so it must be open before selecting the outputs. Select only voltages and currents as outputs for Sensitivity analysis. Press Esc to end selection. Provides a List box of the selected outputs. Highlight one or more of these outputs using the mouse. Default: no outputs. Delete any of the highlighted outputs in the list box. Removes all outputs from the list box. Enables the Sensitivity Analysis in the Simulation window. 2/10/05 Virtuoso Analog Design Environment 5-62 Viewing Sensitivity Results Results—Print—Sensitivities Analyzing Simulation Results 5-63 Viewing Sensitivity Results To view the simulation results, select Results—Print—Sensitivities in the Simulation window. This is the only way to view Sensitivity simulation results. The results window displays the analysis results, sorted by the magnitude of the real components of the sensitivities (SensitivityReal). The results generated from Spectre are the actual sensitivity values. They have not been modified or normalized in any way. The sensitivities indicate the relative impact a change in a design parameter, such as trnpn:iss (the saturation current of the npn model file used to simulate the npn transistor) has on the output variable selected, the node out. This data displayed is valid for the AC analysis that was run in this example. The value of the frequency (SweepValue) at each measurement is displayed. The magnitude of the sensitivity is not as important as the relative value to other sensitivities. For example, a design parameter with a sensitivity of 4.05739e+12 will impact the output variable by four orders of magnitude greater than a parameter with a sensitivity of 4.05739e+8. The sensitivities are also important in regards to the base value of the parameter being changed. This can lead to giving Normalized Sensitivity as a possible addition to sensitivity results. There is a Sensitivity option used to specify the filename for the Spectre sensitivity results. Select Simulation—Options—Analog to display the Simulator Options form. Scroll down to the SENSITIVITY OPTIONS section. Optionally, set the value of sensfile, which has a default value of ./psf/sens.output. This file is displayed with data in a sorted format, as shown above. 2/10/05 Virtuoso Analog Design Environment 5-64 Spectre Sweep Feature Temperature Sweep (DC Analysis) Model Parameter Sweep (AC Analysis) Design Variable Sweep (AC Analysis) Analyzing Simulation Results 5-65 Spectre Sweep Feature The Spectre simulator interface offers a powerful yet simple way to sweep parameters. The following sweeps are available: ■ Frequency (ac, noise, xf (transfer), sp (s-parameter) analyses) ■ Design Variable (dc, ac, noise, xf, sp analysis) ■ Temperature (dc, ac, noise, xf, sp Analyses) ■ Component Parameters (dc, ac, noise, xf, sp analyses) ■ Model Parameters (dc, ac, noise, xf, sp analyses) For simple sweeps, the Spectre simulator provides a quick method of calculating and viewing data over a given range. 2/10/05 Virtuoso Analog Design Environment 5-66 Introduction to Stability Analysis ■ Stability analysis is a small-signal analysis that is available for Spectre only. ■ It can be used with Spectre standalone, or with the Virtuoso Analog Design Environment, to: ❏ Verify the stability of feedback circuits. ❏ Check circuit stability with margin information. ❏ Easily measure loop gain, phase margin, and gain margin. ■ Results can be printed in the Results Display Window and plotted in the Waveform Window. ■ Two algorithms are available depending on the probe parameter specified: loop-based and device-based. ❏ The loop-based algorithm produces accurate stability information for circuit design in which a critical wire can be identified to break all feedback loops. ❏ The device-based algorithm produces accurate stability information for a circuit design in which a critical controlled source can be identified such that nulling this source renders the whole network passive. Analyzing Simulation Results 5-67 Introduction to Stability Analysis Loop gain calculation for a specific feedback loop or active device at the given dc operating point. Gain Margin The gain margin is defined to be the amount of magnitude in decibels of the loop gain below the 0 dB level at the frequency for which the phase is 0 degrees. Loop Gain The loop gain, a function of frequency, is defined as the gain around the feedback loop when the loop is virtually broken at any point. It is the negative of Bode’s return ratio. Phase Margin The phase margin is defined to be the amount of phase in degrees of the loop gain above 0 degrees at the frequency for which the gain is 0 dB. Two algorithms: loop-based and device-based, are available in Spectre for small-signal stability analysis. Both algorithms are based on the calculation of Bode’s return ratio. Loop gain waveform, gain margin, and phase margin are the analysis output. 2/10/05 Virtuoso Analog Design Environment 5-68 Loop-Based Algorithm ■ Calculates the true loop gain. ■ Invoked when a probe parameter points to a current probe or zero-DC-valued voltage source. ■ Current probe or zero-DC-valued voltage source is placed on the feedback loop. ■ Provides accurate stability information for single loop circuits and for multiloop circuits with a critical wire. ■ Multiloop circuit can be stable if all individual loops have reasonable stability margins. ■ Determines the stability of the whole network as long as all nested loops are stable. Analyzing Simulation Results 5-69 Loop-Based Algorithm The probe parameter must be specified to perform stability analysis. When the probe parameter points to a current probe or voltage source instance, the loop-based algorithm is invoked; when it points to a supported active device instance, the device-based algorithm is invoked. The gain margin and phase margin are automatically determined from the loop gain waveform by detecting zero-crossing in the gain plot and phase plot. The loop-based algorithm requires a probe component—current probe or zero-DC-valued voltage source—being placed on the feedback loop to identify and characterize the particular loop of interest. The introduction of the probe component does not change any of the circuit characteristics. There is no special requirement on the polarity configuration of the probe component. The loop-based algorithm provides accurate stability information for single-loop and multiloop circuits, provided that a probe component can be placed on a critical wire to break all loops. For a general multiloop circuit, such a critical wire may not be available. The loop-based algorithm can be only performed on individual feedback loops to ensure they are stable. Although the stability of all feedback loops is a necessary condition for the whole circuit to be stable, the multiloop circuit tends to be stable if all individual loops are associated with reasonable stability margins. 2/10/05 Virtuoso Analog Design Environment 5-70 The Device-Based Algorithm ■ Calculates the loop gain around a particular active device. ■ Invoked when a probe parameter points to a supported active device instance. ■ Used for designs in which local feedback loops cannot be neglected. ■ Can be used to ensure all local loops are stable. ■ Local feedback loops are not accessible from the schematic or netlist level to insert the probe component. ■ Nulling dominant controlled source renders the active device to be passive. The supported active device and its dominant gain source are summarized below. The device-based algorithm produces accurate stability information for a circuit in which a critical active device can be identified such that nulling the dominant gain source of this device renders the whole network to be passive. Examples are multistage amplifier, single-transistor circuit, and S-parameter characterized microwave component. Analyzing Simulation Results 5-71 The Device-Based Algorithm Component Dominant Controlled Source Description b3soipd gm Common-source transconductance bjt gm Common-emitter transconductance bsim1,2,3,3v3 gm Common-source transconductance btasoi gm Common-source transconductance cccs gain Current gain ccvs rm Transresistance ekv gm Common-source transconductance gaas gm Common-source transconductance hbt dice_dvbe Intrinsic dIce/dVbe hvmos gm Common-source transconductance jfet gm Common-source transconductance mos0,1,2,3 gm Common-source transconductance tom2 gm Common-source transconductance vbic dic_dvbe Intrinsic dIc/dVbe vccs gm Transconductance vcvs gain Voltage gain 2/10/05 Virtuoso Analog Design Environment 5-72 Starting Stability Analysis In the simulation window, select: Analyses—Choose... . In the Choosing Analyses form select the stb button. Sweep variables allowed in stability analysis. Analyzing Simulation Results 5-73 Starting Stability Analysis Start the stability analysis from the simulation widow by clicking the Choose Analyses icon or selecting Analyses—Choose from the menu bar. When the Choosing Analyses form appears, select the stb button. The stability analysis is a small-signal ac analysis. As such, frequency is a sweep variable. In addition, design variables, temperature, and component parameters can be swept. 2/10/05 Virtuoso Analog Design Environment 5-74 Stability Analysis Results Results—Direct Plot—Main Form Results—Print—Stability Summary Analyzing Simulation Results 5-75 Stability Analysis Results After successful stability analysis, you can get a plot of loop gain by selecting Results—Direct Plot—Main Form... from simulation window and selecting “Loop Gain” button and clicking “Plot” button in the “Direct Plot Form”. In this form, click on “Add To Outputs” button to add any function or expression (Loop Gain, Phase Margin, Gain Margin, etc.) to “Outputs” section of the simulation window. You can use markers in the Waveform Window to manually verify your gain margin and phase margin results. After successful stb analysis, you can view stability summary by selecting Results—Print—Stability Summary... from the simulation window. A Results Display Window and Stability Summary window will open. In the Stability Summary window, choose “Phase Margin”, “Gain Margin”, or “Both” and click “Apply” or “OK”. This displays phase margin, gain margin, and the frequency values at which these values were measured. This information is very important to know if your circuit is stable or not. You can find out whether your circuit is stable or not by doing poles and zeroes analysis; however, poles and zeroes analysis will not provide the margin information that the stability analysis provides. 2/10/05 Virtuoso Analog Design Environment 5-76 Labs Lab 5-1 Managing Simulation Results Lab 5-2 Managing Simulation Data with the Results Browser Lab 5-3 Viewing Circuit Conditions Lab 5-4 Using the Spectre Sweep Features Lab 5-5 Stability Analysis Lab 5-6 Device Checking Interface to ADE Analyzing Simulation Results 5-77 Labs 2/10/05 Virtuoso Analog Design Environment 5-78 Lab Reference Materials Any import key in the calculator, such as vt, it, wave, when pressed will prompt to probe in the design entry window. When finished graphically probing, press the Esc key with the cursor in the design entry window to cancel the probing function. Failure to cancel the probing function before starting a different one, will temporarily disable the system. This can be solved by cancelling the current probing functions using the Esc key. This condition violates the Nest Limit of the environment, and a warning appears in the CIW. To avoid this, change the Nest Limit with the Options—User Preferences form through the CIW. Currently, the conditional search capability only works for DC operating conditions. Analyzing Simulation Results Lab Reference Materials 5-79 2/10/05 Virtuoso Analog Design Environment 5-80 ® 6 SKILL and OCEAN Module 6 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 6-2 Topics in this Module ■ Overview of SKILL and OCEAN ■ SKILL in the DFII Environment ■ Basic SKILL statements ■ Introduction to OCEAN ■ Types of commands ■ Sample OCEAN script ■ Data access commands ■ Plotting commands ■ Aliases ■ Running OCEAN interactively ■ Creating OCEAN scripts in the Virtuoso Analog Design Environment ■ Loading OCEAN scripts SKILL and OCEAN 6-3 Terms and Definitions Terms and Definitions OCEAN Acronym for Open Command Environment for ANalysis; Text-based command language for running simulations. setup commands Commands that control input data to the host simulator. run commands Commands that run the simulator. data access commands Commands that are used to get simulator results. OCEAN aliases Abbreviated text that activates specific OCEAN commands. 2/10/05 Virtuoso Analog Design Environment 6-4 Overview of SKILL and OCEAN Introduction This chapter provides some basic instruction in the use and applications of SKILL programming language. This chapter provides instruction on SKILL because: ■ SKILL is used as the fundamental program language of DFII and the Virtuoso Analog Design Environment. ■ The OCEAN Command Language is based on SKILL and many SKILL and OCEAN commands are similar and interchangeable. This chapter also provides basic instruction on the use and applications of the OCEAN Command Language. This information on OCEAN is used to: ■ Run long simulations in batch mode. ■ Run simulations from remote non-graphic terminals ■ Setup and run a large set of simulations, obtain data from the simulation runs, and evaluate the simulation data automatically. ■ Use the Virtuoso Analog Design Environment to create OCEAN scripts to run simulations at a later time. SKILL and OCEAN 6-5 Overview of SKILL and OCEAN In this chapter you will be introduced to the SKILL program language and to the OCEAN command language. The introduction to SKILL is to demonstrate that SKILL is the fundamental program language of the DFII Environment. Most of the user interface windows, features, and forms within DFII are written in SKILL. This chapter also provides instruction on using OCEAN. The OCEAN syntax is based on SKILL, and so many of the SKILL and OCEAN commands are identical. The OCEAN command language is included with the installation of Virtuoso Analog Design Environment. OCEAN provides an alternate method to set up simulations, run the simulation, access the simulation data, and then process the data. 2/10/05 Virtuoso Analog Design Environment 6-6 Introduction to SKILL ■ SKILL is a graphics-based program language based on Lisp. ■ DFII and most features and applications of Virtuoso Analog Design Environment are written in SKILL code. ■ Features of the Virtuoso Analog Design Environment and related tools can be customized using SKILL. ■ The OCEAN command language is based on SKILL. ■ Many SKILL and OCEAN commands are interchangeable between the two domains. ■ Training in SKILL is available from Cadence Education Services. ■ Both classroom and internet training (iLS) are available. ■ There are SKILL development tools available in your installation of Virtuoso Analog Design Environment. SKILL and OCEAN 6-7 Introduction to SKILL SKILL is a graphical base programming language with thousands of commands. DFII and most features and applications of Virtuoso Analog Design Environment are written in SKILL code. In the classroom environment for this class some students ask: ■ “How can I change this feature to do this or that?” or ■ “How do I change the appearance of the user interface?” Very often the answer to such questions is “SKILL”. SKILL Programming Language Class is taught by Cadence Education Services as a 5-day class. An Internet Learning Series (iLS) version of the class is also provided through Cadence Education Services. 2/10/05 Virtuoso Analog Design Environment 6-8 Using SKILL Commands There are numerous ways to execute SKILL commands and programs. ■ The command line of the CIW accepts SKILL commands. ■ The command line of the CIW executes SKILL programs. ■ The buffer of the Waveform Calculator will evaluate mathematical expression written in SKILL. ■ There is a SKILL environment that is started by typing “skill” in a unix window. SKILL support ■ The Finder utility is a SKILL dictionary for locating the syntax and usage SKILL commands. ❏ Start the Finder from the CIW by selecting: Tools—SKILL Development, then select the Finder button. ■ Other SKILL support features include SKILL Development Tool and CDSDoc. SKILL and OCEAN 6-9 Using SKILL Commands 2/10/05 Virtuoso Analog Design Environment 6-10 Basic SKILL Statements ■ SKILL commands can be entered into and evaluated on the command line of the Command Interpreter Window. ■ You can enter valid SKILL syntax into the CIW. For example, on the command line enter: 2+2 4 ... SKILL response ■ Now enter: pi=3.14159 3.14159 ... SKILL response then enter: x= 1/( 2 * pi * 1M * 1p ) ... the reactance of a 1pf capacitor at 1MHz 159155.1 ... SKILL response ■ SKILL evaluates the command line, assigns values to variables, and evaluates expressions. SKILL and OCEAN 6-11 Basic SKILL Statements SKILL easily handles setting of variables and expressions. SKILL can also be used to set up arrays. 2/10/05 Virtuoso Analog Design Environment 6-12 Parentheses and Double Quotes There are common SKILL syntax characters. These are also used in OCEAN scripts: ■ Parentheses [ () ] Example: path( "./simulation1/schematic/psf") No space! This very important. ■ Double quotes [ "" ] Example: path( "./simulation2/schematic/psf" ) SKILL and OCEAN 6-13 Parentheses and Double Quotes Parentheses Parentheses surround the arguments to the command. The command name is followed immediately by the left parenthesis, with no intervening space as in this example: path( "./simulation1/schematic/psf" "./simulation2/schematic/psf" ) This is correct. There is no space between the word path and the first parenthesis. path ( "./simulation1/schematic/psf" "./simulation2/schematic/psf" ) This example is incorrect. The space after the command name causes a syntax error. Double Quotes Use double quotes to surround string values. A string value is a sequence of characters, such as “abc”. In the following example, the directory names provided to the path command are strings, which must be surrounded by double quotes: path( "./simulation1/schematic/psf" "./simulation2/schematic/psf" ) In OCEAN, a SKILL convention indicates when an argument must be a string. For the prefix t_, substitute a string value (surrounded by double quotes) for the argument as in this example: desVar( t_desVar1 g_value1 t_desVar2 g_value2) This example includes two string values that must be supplied: t_desVar1 and t_desVar2. More information is in the OCEAN Reference manual. 2/10/05 Virtuoso Analog Design Environment 6-14 Single Quote and Question Mark ■ Single Quotes Example: analysis( ‘tran .... ) ■ Question Mark Example: analysis( ‘tran ?stop 1u) SKILL and OCEAN 6-15 Single Quote and Question Mark Single Quote A single quote indicates that an item is a symbol. Symbols in SKILL correspond to constant enumerated values in the C language. In the context of OCEAN, there are predefined symbols used to avoid errors. The simulator being used also has predefined symbols. In example below, tran is a predefined symbol and must be preceded by a single quote. Determine the valid symbols for a command by checking the valid values for the command’s arguments. analysis( 'tran .... ) Another example is the predefined save command. The 'v symbol indicates that the item to save is the voltage on a net. save( 'v "net1" ) In addition, use the selectResult(s_resultsName) command, where s_resultsName = ‘dc, ‘tran, or ‘ac. Question Mark A question mark indicates an optional keyword argument, which is the first part of a keyword parameter. For a keyword parameter, the first component is the keyword, which has a question mark in front of it. The second component is the value being passed, and immediately follows the keyword. In the example, analysis( 'tran ?stop 1u), all the keyword/value pair arguments to the analysis command are optional, except the ‘tran keyword. 2/10/05 Virtuoso Analog Design Environment 6-16 Introduction to OCEAN Open Command Environment for ANalysis ■ OCEAN is a product included in the Virtuoso Analog Design Environment. ■ Use OCEAN for the following tasks: ❏ To create scripts to run batch mode simulations. ❏ To run parametric, Corners, Monte Carlo, and Optimization analyses. ❏ To run long simulations without starting the graphical user interface. ❏ To run simulations from a non-graphical, remote terminal. ■ OCEAN is based on the SKILL programming language. Scripts are created automatically within the Virtuoso Analog Design Environment. These scripts can be saved, modified, and used to run batch simulations. ■ After the design has been debugged in the Virtuoso Analog Design Environment, use OCEAN to test your circuit under a variety of conditions. SKILL and OCEAN 6-17 Introduction to OCEAN The Open Command Environment for ANalysis (OCEAN) sets up, simulates, and analyzes circuit data. OCEAN is a text-based process that runs from a UNIX shell by starting the ocean executable, or from the Command Interpreter Window (CIW). Type in OCEAN commands in an interactive session, or create scripts containing your commands, then load those scripts into OCEAN. Use OCEAN with any simulator integrated into the Virtuoso Analog Design Environment software. Typically, you use ADE when creating your circuit (in the Virtuoso Schematic Editor software) and when interactively debugging the circuit. After the circuit has the required performance, use OCEAN to run your scripts and test the circuit under a variety of conditions. After making changes to your circuit, run your scripts again. Use OCEAN to: ■ Create scripts that can run repeatedly to verify circuit performance. ■ Run longer analyses such as parametric, Monte Carlo, Optimization, and Corners analyses more effectively. ■ Run long simulations in OCEAN without the graphics interface of the Virtuoso Analog Design Environment. ■ Run simulations from a nongraphic, remote terminal. OCEAN is based on the SKILL programming language and uses SKILL syntax. Use all the SKILL language commands in OCEAN. These commands include if statements, case statements, for loops, while loops, read commands, print commands, and so on. The most frequently used SKILL commands relevant to OCEAN are listed in the OCEAN Reference manual. 2/10/05 Virtuoso Analog Design Environment 6-18 Types of OCEAN Commands OCEAN Commands Purpose Simulation Setup Commands Specify the analyses to run. Specify the nets and currents to save. Specify the simulator option value. Specify the circuit stimulus. OCEAN scripts can contain all of these types of commands. Simulator Run Commands Run the simulator. Data Access Commands Perform calculations on the results. Print information. Plot waveforms. Hardcopy results. SKILL and OCEAN 6-19 Types of OCEAN Commands Create OCEAN scripts to accomplish the full suite of simulation and data access tasks that you can perform in the Virtuoso Analog Design Environment. An OCEAN script can contain three types of commands: ■ Simulation setup commands ■ Simulator run commands ■ Data access commands All the parameter storage format (PSF) information created by the simulator is accessible through the OCEAN data access commands. (The data access commands include all of the Virtuoso Analog Design Environment calculator functions.) 2/10/05 Virtuoso Analog Design Environment 6-20 Sample OCEAN Script simulator( 'spectre ) design("./simulation/ampTest/spectre/schematic/netlist/netlist") resultsDir( "./simulation/ampTest/spectre/schematic" ) modelFile( ( "./Models/myModels.scs" ““) ) analysis('ac ?start "100" ?stop "150M" ?dec "20" ) desVar( "CAP" .5p ) temp( 27 ) run() selectResult( 'ac ) plot(getData("/out") ) Note: Specify the resultsDir() to set the directory where simulation data is saved. In the example above, resultsDir() points to the default location. When using the default, the resultsDir() expression is not needed. SKILL and OCEAN 6-21 Sample OCEAN Script You can annotate the sample OCEAN script as follows: simulator( 'spectre ) ->Choose simulator. design("./simulation/ampTest/spectre/schematic/netlist/netlist") ->Specify schematic to be simulated. The netlist was created in Analog Design Environment. resultsDir( "./simulation/ampTest/spectre/schematic" ) ->Specify location of psf directory that holds simulation results. In this example, the default is specified as an argument to resultsDir(), so the command is not necessary. modelFile( ‘( "./Models/myModels.scs" ““)) ->Set Library Model File in Simulation Environment. analysis('ac ?start "100" ?stop "150M" ?dec "20" ) ->Specify AC Analysis. desVar( "CAP" .5p ) ->Set the value of the design variable, CAP. temp( 27 ) ->Set the simulation temperature. run() ->Run the simulation. selectResult( 'ac ) ->Select the AC analysis results. plot(getData("/out") ) -> Generic command to plot the data. Try using plot(vm("/out")) to plot the magnitude of the voltage at node “/out”. Note: There are “easy” commands available for common analyses. For example, enter tran(0 100n 1n) for a transient analysis, ac(1 10000 “linear” 100) for an AC analysis, and dc(“r1” “r” 0 5 1) for a DC analysis. See the OCEAN Reference Manual for more examples and the general form of these commands. 2/10/05 Virtuoso Analog Design Environment 6-22 OCEAN Help Online help is available for all the OCEAN commands. In an OCEAN session, type the following: ocnHelp( ‘commandName ) For example, enter: ocnHelp(‘analysis) An explanation of the command and examples of use are returned. For a list of all types of OCEAN commands, enter: ocnHelp() Additional help and samples of OCEAN scripts are located at: /tools/dfII/samples/artist/OCEAN Detailed documentation on OCEAN and OCEAN scripts is accessible through CDSDoc. SKILL and OCEAN 6-23 OCEAN Help Online help is available for OCEAN commands. Enter ocnHelp(‘analysis) and note: PROTOTYPEanalysis( s_analysisType [? g_analysisOptionValue1] ... [? g_analysisOptionValueN]) => undefined/nil DESCRIPTIONSpecifies the analysis to be simulated. Include as many analysis options as you want. Analysis options vary, depending on the simulator being used. To include an analysis option, replace with the name of the desired analysis option and include another argument to specify the value for the option. With an ac analysis, the first option/value pair might be [?from 0]. Note: Some simplified commands are available for basic SPICE analyses, See the ac, dc, tran, and noise commands. Use ocnhelp( `analysis ) for more information on the analysis types for the simulator choosen. EXAMPLE(S) analysis( 'ac ?start 1 ?stop 10000 ?lin 100 ) For the Spectre simulator, specifies that an ac analysis is to be performed. analysis( 'tran ?start 0 ?stop 1u ?step 10n ) Specifies that a transient analysis is to be performed. 2/10/05 Virtuoso Analog Design Environment 6-24 Data Access Commands Open simulation results and analyze data. ■ Simulation does not have to have been run in the current session. ■ Examples of data access commands include: openResults( “./simulation/opamp/spectre/schematic/psf” ) results() selectResult( ‘tran) ocnPrint( v( “/net56”)) i( “/R1” ) plot(v(“/out”)) pv( “/Q19” “ib”) ■ List of commands includes: dataTypes, getData, i, noiseSummary, ocnPrint, openResults, outputParams, outputs, pv, report, results, selectResults, sweepNames, sweepValues, v ■ Common arithmetic operators and all Calculator functions are available. SKILL and OCEAN 6-25 Data Access Commands There are special commands available in OCEAN that allow you to access data after a simulation is run. These include: dataTypes, getData, i, noiseSummary, ocnPrint, openResults, outputParams, outputs, pv, report, results, selectResults, sweepNames, sweepValues, and v. A full list of commands and their usage is found in the OCEAN Reference Manual. Some of these commands function as follows: openResults( “./simulation/opamp/spectre/schematic/psf” ) ❑ Opens simulation results stored in PSF format in psf directory. results() ❑ Returns a list of the type of results that can be selected. selectResult( ‘tran) ❑ Selects Transient results. ocnPrint( v( “/net56”)) ❑ Prints the text data of the waveform net56. i( “/R1” ) ❑ Returns the current through R1. plot(v(“/out”)) ❑ plots node ‘out” in a waveform window. pv( “Q19” “ib”) ❑ Returns the value of the ib parameter for the Q19 component. 2/10/05 Virtuoso Analog Design Environment 6-26 Plotting Commands Use any Waveform Window SKILL command for plotting in OCEAN. ■ By default, the Waveform Window is in overlay mode. Use the clearAll() command to erase the window. ■ Use graphicsOn() and graphicsOff() to turn plotting on and off. ■ Arithmetic operators and all Calculator functions are available. Original label New Label Examples: plot(getData("/out") ) SKILL and OCEAN plot(getData("/out") ?expr list( "Output Node") ) 6-27 Plotting Commands Use any Waveform Window SKILL command for plotting in OCEAN. Plot any data that is in PSF format. The graphicsOff() command disables the redrawing of the current Waveform Window. Use this command to freeze the Waveform Window display, send several plots to window, and then use graphicsOn() to unfreeze the window and display all of the plots at once. Plotting commands include: plot, newWindow, addSubwindow, clearSubwindow, clearAll, deleteSubwindow, deleteWaveform, displayMode, plotStyle, xLimit, yLimit, currentWindow, currentSubwindow, addWaveLabel, addWindowLabel, removeLabel, hardCopyOptions, and hardCopy. Details of plot commands are in the OCEAN Reference manual. The example above illustrates how to replace the command, plot(getData("/out"), with the following expression: plot(getData("/out") ?expr list("Output Node")) This expression gives a specific name to a waveform that is plotted in the Waveform Window. Also replace the expression with plot(vm("/out")). 2/10/05 Virtuoso Analog Design Environment 6-28 Available OCEAN Aliases Aliases are available in OCEAN to simplify your scripts. Alias vm vdb vp vr vim im ip ir iim Syntax mag( v( t_net)) db20( v (t_net)) phase( v(t_net)) real( v( t_net)) imag( v( t_net)) mag( i( t_component)) phase( i( t_component)) real( i( t_component)) imag( i( t_component)) Description Magnitude of voltage on the net Power gain in decibels from net “in” to net “out” Phase of voltage on net Real part of complex voltage Imaginary part of complex voltage Magnitude of AC current Phase of AC current Real part of complex number representing AC current Imaginary part of complex number representing AC current SKILL and OCEAN 6-29 Available OCEAN Aliases The aliases shown above provide shortcuts to commonly used pairs of commands. All of these aliases operate on results previously selected with selectResult. However, an alias can be used on a different set of results as follows: vm( t_net [?result s_resultName] ) where resultName is the name of the data type for the particular analysis required. Use an alias on results stored in a different directory as follows: vm( t_net [?Resultsdir t_resultsDir] [?result s_resultName] ) where resultsDir is the name of a different directory containing PSF results, and resultName is the name of a data type contained in that directory. (If specifying another directory with resultsDir, specify the particular results with resultName.) 2/10/05 Virtuoso Analog Design Environment 6-30 Running OCEAN Interactively Run OCEAN from a UNIX prompt or from the CIW. ■ In UNIX: Enter ocean from the UNIX prompt to start. This loads awd.exe and loads and reads the .oceanrc startup file. The .oceanrc file contains OCEAN commands that include alias definitions, and user-defined procedures and characterization scripts. An ocean> prompt appears in the UNIX window. Enter commands at the prompt. The .cdsinit file is not loaded. Type exit to quit OCEAN. ■ In the CIW, through the Virtuoso Analog Design Environment: ❏ Enter OCEAN commands at any time. ❏ The .oceanrc is not loaded automatically. If it exists, load it by entering: load “.oceanrc” SKILL and OCEAN 6-31 Running OCEAN Interactively Run OCEAN from a UNIX prompt or from the CIW. The primary method is to run it from a UNIX shell. When entering ocean at a UNIX prompt, a series of messages are printed. This includes a note that the awd.exe code is loaded. This code drives the Waveform Display tool that drives the Waveform Window. Other messages indicate that context files are loaded to activate the Simulation Environment. The .oceanrc file contains OCEAN commands that include alias definitions, and user-defined procedures and characterization scripts. For example, an .oceanrc file might contain: alias h ocnHelp alias d ocnDisplay alias sr selectResults alias op openResults alias p ocnPrint installDebugger() Once this file is loaded, you can enter: h( ‘commandName) instead of typing ocnHelp(‘commandName) Using OCEAN in the Virtuoso Analog Design Environment is straightforward, because commands are directly entered into the CIW. 2/10/05 Virtuoso Analog Design Environment 6-32 Creating OCEAN Scripts in ADE It is easy to create OCEAN scripts in the Virtuoso Analog Design Environment. ■ OCEAN commands of tasks performed in the Virtuoso Analog Design Environment are automatically saved in the ./simulation/design/simulator/schematic/netlist/simulatorX.ocn files. ■ In the Simulation Environment form, select Session—Save Script... ❏ Specify the file name of the script to create. ❏ Only enabled analyses are saved. ❏ The command saves the design, library model file, design variables, data directory, simulator options, plot set, etc. SKILL and OCEAN 6-33 Creating OCEAN Scripts in ADE Automatically create an OCEAN script within the Virtuoso Analog Design Environment. The following example illustrates the difference between the script that is automatically created in the ./simulation/design/simulator/schematic/netlist/simulatorX.ocn location, and the one created by the Session—Save Script... command. For example, walk through the following design flow: 1. Start the Virtuoso Analog Design Environment software. 2. Specify DC analysis. 3. Select nets on schematic to save. 4. Run simulation. 5. Turn off DC analysis. 6. Select transient analysis. 7. Run simulation. 8. Save OCEAN script. The simulatorX.ocn file in the netlist directory will contain the entire design session, including the DC analysis. The oceanScript.ocn (default name) will not have the DC analysis, because it was turned off before the script was created. 2/10/05 Virtuoso Analog Design Environment 6-34 Loading OCEAN Scripts Load OCEAN scripts from a UNIX window or from the CIW. ■ In UNIX: ocean> load( “script_name.ocn”) or load “script_name.ocn” ■ In UNIX, to run an OCEAN script and then have OCEAN quit, enter: unix> ocean < script_name.ocn ■ In the CIW, enter: load( “script_name.ocn”) or load “script_name.ocn” This command loads and runs the OCEAN script. SKILL and OCEAN 6-35 Loading OCEAN Scripts Once an OCEAN script exists, it is easy to load it and run it through the CIW or in a UNIX window. The netlist specified with the design command needs to have already been created. It is recommended to use the netlist generated from the Virtuoso Analog Design Environment. Use netlists from other sources as long as they are in the same format as those created by the ADE simulation environment. Any models, include files, stimulus files, or PWLF files must be in the locations set by the path command. The scripts that are created automatically in the ../simulation/design/simulator/ schematic/netlist/simulatorX.ocn location or with the Session—Save Ocean Script command have the proper syntax to run in OCEAN. 2/10/05 Virtuoso Analog Design Environment 6-36 Labs Lab 6-1 Using an OCEAN Script to Run a Simple Simulation Lab 6-2 Measuring PSRR and CMRR with OCEAN Lab 6-3 Introduction to SKILL Lab 6-4 SKILL Development Tools SKILL and OCEAN Labs 6-37 2/10/05 Virtuoso Analog Design Environment 6-38 ® 7 Parametric Analysis Module 7 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 7-2 Topics in this Module ■ Introduction to EDFM design tools ■ Parametric analysis flow and methodology ■ Parametric analysis environment ■ Parametric plots ■ Accessing data from parametric analysis ■ Model parameters ■ Running parametric analysis in OCEAN Parametric Analysis 7-3 Terms and Definitions Terms and Definitions parametric analysis Set of simulations sweeping one variable while stepping another. inclusion list A list of data points to be added to defined set. exclusion list A list of data points to be removed from a defined set. EDFM Electronic Design For Manufacturability PDF process description file PDK process design kit 2/10/05 Virtuoso Analog Design Environment 7-4 Introduction to EDFM Design Tools Parametric Analysis is one of set of software products called EDFM tools. Parametric Analysis 7-5 Introduction to EDFM Design Tools EDFM is a set of design tools used to develop manufacturable products. In general, a circuit simulator is a software design tool for running a single analysis. The simulator performs calculations using the device models to predict behavior at each step of the simulation run. The simulator performs these calculations as directed by the input files. A simulator is used to design circuits, but it is also used run experiments and verify lab results. Alternatively, EDFM tools are used to complete the design process. Instead of a single simulation run to verify circuit operation and performance at specific conditions, an EDFM analysis is a set of multiple simulations. The EDFM analysis verifies operation and performance over a specified range, or over multiple ranges, or over a set of specified of conditions. EDFM tools feature the following properties: ■ Multiple simulations. ■ A graphical user interface for setup. ■ An automated flow to alter the simulation input between runs. ■ Specified ranges for parameters or design variables. ■ Multiple pdf files. ■ Special post processing tools to display results. ■ EDFM tools are selected under the Tools menu of the Virtuoso Analog Design Environment. 2/10/05 Virtuoso Analog Design Environment 7-6 EDFM Tool Usage The following table provides on overview of the EDFM tool usage. The table shows the existing common usage for the EDFM tool set. The table also shows what is now considered the “best usage”. Note that each tool shows usage in more than one domain. Parametric analysis is suitable for design exploration and for problem detection. Table of Design Tool Usage EDFM Tool Circuit Optimizer Parametric Analysis Corners Monte Carlo Initial Design High Design Problem Exploration Detection Medium High High High Medium High Improve & Final Center Verification Medium High Medium Parametric Analysis 7-7 EDFM Tool Usage Important The Table of Design Usage is intended to show “Best Use” as well as the current usage. The Best Use is intended to show the best application of each tool. It is not a claim that the historical use or any use of a specific tool to a specific application is flawed! 2/10/05 Virtuoso Analog Design Environment 7-8 Overview of Parametric Analysis and Flow Open Design Start Simulation Environment Start Parametric tool with: Tools—Parametric Analysis Pick Sweep Variables Set Sweep Ranges Add Inclusion/Exclusion Lists Run Analysis Parametric Analysis 7-9 Overview of Parametric Analysis and Flow Parametric Analysis is a flow where multiple simulations are performed over specified ranges of design variables, device parameters, or circuit conditions. The Virtuoso Analog Design Environment Parametric Analysis Tool provides an easy-to-use interface to run multiple simulations. Note: The Parametric Analysis tool is somewhat analogous to a semiconductor parameter analyzer (SPA). The SPA is used to measure the device parameters, or device behavior as inputs are swept. The Parametric Analysis tool simulates device behavior as simulation inputs are swept. In the EDFM realm, Parametric Analysis is used to explore the design space. The flow diagram above shows the major steps for performing a Parametric Analysis. ■ Open the design ■ Start the simulation environment and verify proper circuit operation. ■ Start the Parametric Analysis tool. ■ Select the sweep variables. ■ Select sweep ranges and number of steps for the sweeps. ■ Add or delete specific points in the sweep. ■ Run the simulation and evaluate the results. 2/10/05 Virtuoso Analog Design Environment 7-10 Parametric Analysis Methodology 1. Set up the simulation environment. ❏ The environment remains fixed during parametric analysis. ❏ Limit output data if results storage space is limited. 2. Start the Parametric Analysis tool by selecting Tools—Parametric Analysis from the simulation environment. The tool behaves as a: ❏ Number list generator ❏ Simulation engine controller 3. Generate lists of design variable values. ❏ A simulation is run for each variable value or point. ❏ A parametric analysis on a variable is called a sweep. 4. Plot results by probing in the design window. ❏ A family of curves is displayed. Parametric Analysis 7-11 Parametric Analysis Methodology The Parametric Analysis tool runs a simulation many times while changing the value of design variables for each simulation. Set up the Simulation environment as if running a single simulation, then start the Parametric Analysis tool from the simulation environment. Open the Parametric Analysis tool and invoke the Design Variables form. Design variables must be declared on this form, before they can be selected for a sweep. Variables that are part of parameterized models can be added to the Parametric Analysis environment. The DC temperature variable (temp) is already available to be swept. For any variable, pick a starting and ending value then generate intermediate numbers. This is called a range of points. Any number of ranges can be generated and they can overlap. For any variable add and delete points in a range with inclusion and exclusion lists. Other features: ■ Select a multiple sweep feature ■ Pick multiple variables ■ Create independent ranges ■ Create inclusion and exclusion lists for each variable 2/10/05 Virtuoso Analog Design Environment 7-12 The Parametric Analysis Environment Tools—Parametric Analysis Parametric Analysis 7-13 The Parametric Analysis Environment In the Parametric Analysis form, define and view simulation data points, as well as save any parametric analysis settings in a file to load again at a later time. In addition, set up multiple variable sweeps, which are nested so that the value of the Nth variable is swept at every value of the (N-1)th variable where N is the position of the variable in the analysis. For example, take two swept variables, A and B, A will be set to an initial value, and simulations will be run for all values of B. Next, A will be changed to its next value, and simulations will be run again for all values of B. The process continues for all values of A and B. The Analysis pull-down menu commands provide start, pause, and continue of an analysis. Take note that interrupting a parametric analysis stops the analysis between simulations. When interrupting a standard simulation in the Simulation environment, the simulation is aborted. Additionally, delete some or all of the specifications in an analysis and then restore them after deletion. Generating Ranges Edit the sweep ranges for the different variables selected, or generate new ones. Choose to sweep any design variable(s) that are declared in the Design Variables form in the Simulation environment. Add multiple ranges which may overlap, and vary the steps in individual ranges. Add inclusion and exclusion fields to specify additional simulation data points or prohibit simulations at particular points. 2/10/05 Virtuoso Analog Design Environment 7-14 Parametric Plots ■ Curve identifiers match the curve colors. ■ Put your cursor on a curve to indicate the associated value(s) of variables. ■ Use the calculator to process families of curves. ■ Once plotted, each curve is independent for postprocessing. Parametric Analysis 7-15 Parametric Plots After Parametric Analysis has finished, families of curves are plotted for the selected signals in the Waveform Window. The Waveform Window displays multiple curves labeled with the design variable values for that simulation. Putting your cursor over a particular colored curve will show the value(s) of the swept variable(s) associated with that curve. Parametric analysis data is also available via the Results Browser. Access individual simulation data for each value of the swept variable by using this method. All functionality of the Results Browser is available for this data. Once plotted, the different colored curves are independent and can be moved, deleted, or analyzed separate from other curves in the “family.” 2/10/05 Virtuoso Analog Design Environment 7-16 Accessing the Parametric Analysis Data Structure Access data for specific variable values with the Results Browser. Parametric Analysis 7-17 Accessing the Parametric Analysis Data Structure It is possible to use the Results Browser to access data for any simulation run for a specific value of any number of swept variables. Use the Results Browser to plot the data or move it into the calculator buffer for postprocessing. 2/10/05 Virtuoso Analog Design Environment 7-18 Parametric Analysis on Model Parameters 1. Add model parameter as a Design Variable. model trnpn type=npn is=10e-15 bf=beta \ va=58.7 ik=5.63e-3 rb=665 rbm=86 re=3.2 \ cje=0.25e-12 pe=0.76 me=0.34 tf=249e-12 \ cjc=0.34e-12 pc=0.55 mc=0.35 ccs=2.4e-12 \ ms=0.35 ps=0.53 rc=169 2. Point to a model file that contains the new variable. 3. Start Parametric Analysis and choose the new sweep variable. Parametric Analysis Parametric Analysis on Model Parameters 7-19 2/10/05 Virtuoso Analog Design Environment 7-20 Parametric Analysis in OCEAN ■ The parametric analysis commands are not saved to the OCEAN script when selecting Session—Save Ocean Script. ■ Use Tool—Save Script to save the parametric analysis. ■ Nest parametric analyses for multiple variables, as shown in this example. Example paramAnalysis( “rl” ?start 200 ?stop 600 ?step 200 paramAnalysis( “rs” ?start 300 ?stop 700 ?step 200 )) paramRun() Runs a parametric analysis on rl for each value of rs, yielding a nested parametric analysis. Parametric Analysis 7-21 Parametric Analysis in OCEAN OCEAN scripts must be manually modified to run a parametric analysis. (This will be done automatically in future releases.) Remove or comment out the run() statement in your script, and add the paramAnalysis() and paramRun() commands. For example, add the following to your OCEAN script: paramAnalysis("CAP" ?start 0.1p ?stop 0.5p ?step 0.1p) paramRun() This example will run a parametric analysis on the CAP variable. Set up multiple parametric analyses, and only simulate the variables desired as in this example: paramAnalysis( "rs" ?start 200 ?stop 1000 ?step 200 ) paramAnalysis( “rl” ?start 200 ?stop 600 ?step 200 ) paramRun( ‘rs) This example runs a parametric analysis on the rs design variable only. Nest parametric analyses with multiple variables by setting up an OCEAN script with syntax similar to the following example: paramAnalysis( “rl” ?start 200 ?stop 600 ?step 200 paramAnalysis( “rs” ?start 300 ?stop 700 ?step 200 )) paramRun() This example runs a parametric analysis on rl for each value of rs, yielding a nested parametric analysis. 2/10/05 Virtuoso Analog Design Environment 7-22 Summary In this module we discussed: ■ An overview of EDFM tools, their uses and properties. ■ Parametric Analysis flow and methodology ■ The Parametric Analysis environment ■ Plotting results ■ Accessing data from Parametric Analysis ■ Model parameters ■ Running Parametric Analysis in OCEAN Parametric Analysis Summary 7-23 2/10/05 Virtuoso Analog Design Environment 7-24 Labs Lab 7-1 Running Parametric Analysis Parametric Analysis 7-25 Labs 2/10/05 Virtuoso Analog Design Environment 7-26 ® 8 Corners Analysis Module 8 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 8-2 Topics in this Module ■ Introduction to the Corners Analysis tool ■ Corners Analysis Window ■ Adding a new process ■ Modeling styles used for Corners Analysis ■ Results Corners Analysis 8-3 Terms and Definitions Terms and Definitions process corner Model parameters assumed for the extreme limits of a process. corner Selected set of model parameters and operating conditions. Corners Analysis Software tool to run multiple simulations at specified corners. pcf Process Customization File, defines corners for a given process. dcf Design Customization File, defines design variables. model style Method of compiling data to describing model variations. 2/10/05 Virtuoso Analog Design Environment 8-4 Corners Analysis Tool ■ The Corners Analysis tool provides useful performance information on a design by performing multiple simulations under specified conditions. ■ With the Corners Analysis tool, a design is simulated at specified “corners” where the process parameters, supply voltages, temperature, and other operating conditions are altered. ■ The Corners Analysis tool is one of five EDFM software tools that operate within the Virtuoso Analog Design Environment. ■ As an EDFM tool, the Corners Analysis is intended to automatically set up, run, and analyze multiple simulations. It is used to explore the design space and locate problem areas. Corners Analysis 8-5 Corners Analysis Tool In a theoretical manufacturing process, process variables can have exact values and these exact values can be used to calculate the yield for the process. However, in a real manufacturing process, process variables are subject to a manufacturing tolerance—they fluctuate randomly around their ideal values. The combined random variation for all the components results in an uncertain yield for the circuit as a whole. A design methodology that is used to guarantee both reliability and yield is to simulate the circuit under worst-case conditions. In actuality, there are numerous worst-case conditions. As such, circuit simulation is performed using worst-case device models at the specified limits of temperature, supply voltage, and frequency. The so called worst-case models, along with the worst-case design limits, are often called “the worst-case corners”. Hence the name used for this design tool. The fabrication process is often considered to occupy a specified region of multi-dimensional fabrication universe. Within this region, the process produces worst-case extremes of device parameters. These worst-case extremes are represented by worst-case models. For example, for typical CMOS process, the following table establishes the worst-case corners: process corner K’n K’p Vtn Vtp Ln Lp Vdd Temp worst-case slow min. min. max. max. max. max. min. max. worst-case fast max. max. min. min. min. min. max. min. worst-case one max. min. min. max. min. max. min. worst-case zero min. max. max. min. max. min. max. 2/10/05 Virtuoso Analog Design Environment 8-6 Corners Analysis Window Execute Tools—Corners from the Simulation window. Corners Analysis 8-7 Corners Analysis Window Corners Analysis looks at the performance outcomes generated from the most extreme variations expected in the process, voltage, and temperature values (the corners). With this information, the circuit performance specifications can be determined, even when the random process variations combine in their most unfavorable patterns. There are different kinds of files associated with setting up a Corners Analysis. ■ Process customization files (pcf’s) define processes, groups, variants, and corners that are shared by an entire organization. pcf’s are usually created by a process engineer or process group. ■ Design customization files (dcf’s) contain definitions that are used for a particular design or for several designs within a design group. dcf’s are usually created by designers, who use the dcf’s to add design-specific information to the general information provided in pcf’s. Use the Add Corner button, or select Edit—Add Corner from the menu to add a new process corner. Use the Add Variable button, or select Edit—Add Variable from the menu to add a new variable. Use the Add Measurement button, or select Edit—Add Measurement from the menu to add a new measurement. 2/10/05 Virtuoso Analog Design Environment 8-8 Adding a New Process Select Setup—Add Process from the Corners Window. Corners Analysis 8-9 Adding a New Process 2/10/05 Virtuoso Analog Design Environment 8-10 Implementing Modeling Styles Model styles are specified in a .scs file. There are several ways to implement models: ■ Single-Model Library Style ■ Multiple-Model Library Style ■ Single-Numeric Style ■ Multiple-Numeric Style ■ Multiple-Parametric Modeling Two additional types of files used are: ■ Process Customization File (pcf)—ends in .pcf Adds the name of a new process to the Corners tool and defines the basic set of corners ■ Design Customization File (dcf)—ends in .dcf Adds design specific variables and measurements to the Corners tool Load them explicitly, or with the .cdsinit file: loadPcf( "./CORNERS/multipleModelLib.dcf" ) loadPcf( "./CORNERS/singleModelLib.pcf" ) Corners Analysis 8-11 Implementing Modeling Styles There are different modeling styles for corners. 2/10/05 Virtuoso Analog Design Environment 8-12 Single-Model Library Style Recommended style: ■ All models for all corners are located in a single model file ■ The model file is located in the base directory and can have any name ■ Can also use the .LIB syntax for this style ■ Works with altergroup function in the Spectre simulator Path: ./models/fab6 Filename: mylibfile.scs library processA section slowslow model npn2 npn tf=120n model npn9 npn tf=320n model nmosR nmos tox=120n model nmos8 nmos tox=320n endsection section nom model npn2 npn tf=100n model npn9 npn tf=300n model nmosR nmos tox=100n model nmos8 nmos tox=300n endsection section fastfast model npn2 npn tf=80n model npn9 npn tf=380n model nmosR nmos tox=80n model nmos8 nmos tox=380n endsection endlibrary Corners Analysis 8-13 Single-Model Library Style The following code illustrates how you can refer to this modeling structure in a pcf. corAddProcess("fab6" "~lorenp/models/fab6/" ’singleModelLib) corSetModelFile("fab6" "mylibfile.scs") corAddProcessVar("fab6" "vdc") corAddCorner("fab6" "slowslow" ?runTemp 20 ?nomTemp 27 ?vars ’( ("vdc" 2) ) ) The Corners window produced by this pcf looks like this. 2/10/05 Virtuoso Analog Design Environment 8-14 Multiple-Model Library Style Similar to Single-Model Library Style Example: models might be located in the files: ./models/fab6/path1/npn.scs ./models/fab6/path3/nmos.scs Path: ~/john/models/fab6/path1 Filename: npn.scs library npn section slow model npn2 bjt tf=120n model npn8 bjt tf=80n endsection section nom model npn2 bjt tf=100n model npn8 bjt tf=60n endsection section fast model npn2 bjt tf=80n model npn8 bjt tf=50n endsection endlibrary Path: ~/john/models/fab6/path3 Filename: nmos.scs library nmos section slow model nmosR mos3 tox=120n model nmos2 mos3 tox=140n endsection section nom model nmosR mos3 tox=100n model nmos2 mos3 tox=115n endsection section fast model nmosR mos3 tox=80n model nmos2 mos3 tox=90n endsection endlibrary Corners Analysis 8-15 Multiple-Model Library Style The following code illustrates how to refer to this multiple-model library structure in a pcf. corAddProcess("fab6" "~john/models/fab6/" 'multipleModelLib) corAddModelFileAndSectionChoices("fab6" "path1/npn.scs" '( "slow" "nom" "fast") ) corAddModelFileAndSectionChoices("fab6" "path3/nmos.scs" '( "slow" "nom" "fast") ) corAddProcessVar("fab6" "vdc") corAddCorner("fab6" "slowslow" ?sections '( ("path1/npn.scs" "slow") ("path3/nmos.scs" "slow") ) ?runTemp 20 ?nomTemp -27 ?vars '( ("vdc" 2) ) ) corAddCorner("fab6" "nomnom" ?sections '( ("path1/npn.scs" "nom") ("path3/nmos.scs" "nom") ) ?runTemp 30 ?nomTemp 27 ?vars '( ("vdc" 3) ) ) corAddCorner("fab6" "fastfast" ?sections '(("path1/npn.scs" "fast") ("path3/nmos.scs" "fast") ) ?runTemp 40 ?nomTemp -27 ?vars '( ("vdc" 4) ) ) corAddCorner("fab6" "fastslow" ?sections '(("path1/npn.scs" "fast") ("path3/nmos.scs" "slow") ) ?runTemp 50 ?nomTemp -27 ?vars '( ("vdc" 4) ) ) The Corners window produced by this pcf looks like this: 2/10/05 Virtuoso Analog Design Environment 8-16 Other Styles Not recommended—provided for backward compatibility ■ Single Numeric Each corner is located in a separate file. If there are four corners, there are four model files with the same name. ■ Multiple Numeric Each model is defined in a separate file. All model parameters are defined with numeric values. ■ Multiple Parametric With this style, each model is defined in a separate file. There is a corresponding parameter file for every model associated with each corner. Corners Analysis 8-17 Other Styles (Single Numeric) Path ./models/fab6/allslow/ Filename models ./models/fab6/allnom/ models (Multiple Numeric) Path Filename ./models/fab6/npn/slow/ npn2.scs npn9.scs ./models/fab6/npn/nom/ npn2.scs npn9.scs (Multiple Parametric) Path Filename ./models/fab6/npn npn2.scs npn9.scs ./models/fab6/npn/slow/ npn2.param npn9.param File Contents .model npn2 npn tf=120n .model nmos8 nmos tox=320n .model npn2 npn tf=100n .model nmos8 nmos tox=300n File Contents model npn2 bjt tf=120n model npn9 bjt tf=320n model npn2 bjt tf=100n model npn9 bjt tf=300n File Contents include "npn2.param" model npn2 bjt tf=TF2 include "npn9.param" model npn9 bjt tf=TF9 parameter TF2=120n parameter TF9=320 This chart shows a partial list to the models associated with each of the above styles. 2/10/05 Virtuoso Analog Design Environment 8-18 Corners Results Corners Analysis 8-19 Corners Results When the analysis finishes, the Corners tool plots or lists the results according to choosing text or graphic outputs in the Performance Measurements pane. To view a different set of outputs from those selected before running the analysis, set up new outputs in the Performance Measurements section. Next, select Tools—Plot or Print Outputs from the menu or click the Plot/Print button. The Corners tool evaluates and displays the new measurements or plots, as long as the data needed for these new calculations was saved during simulation. There are two kinds of graphical output: ■ Residual plots for scalar data The residual plots (bar graphs) above shows that three of the corners fail for the Phase Margin specifications. This result implies that yield for the manufactured circuit will be less than 100 percent if the circuit is produced in its current form. For greater yield, the circuit designer might want to redesign the circuit so that it performs acceptably for all corners. ■ Family of curves for waveform data The plot above shows how the magnitude and phase vary as a function of frequency for each of the corners. All these features are also available in OCEAN. 2/10/05 Virtuoso Analog Design Environment 8-20 Corners Results Window Textual output Corners Analysis 8-21 Corners Results Window The window above shows the result of the request for Textual output for the Phase Margin measurement. It gives a clear indication of the successes and failures of this performance measurement with each corner. 2/10/05 Virtuoso Analog Design Environment 8-22 Labs Lab 8-1 Using the Corners Analysis Tool Corners Analysis Labs 8-23 2/10/05 Virtuoso Analog Design Environment 8-24 ® 9 Monte Carlo Analysis Module 9 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 9-2 Topics in this Module ■ Overview ■ The Monte Carlo tool ■ Statistical modeling ■ Process variation methodology ■ Setting up Monte Carlo analysis ■ Running Monte Carlo analysis ■ Filtering output data Monte Carlo Analysis 9-3 Terms and Definitions Terms and Definitions Monte Carlo Statistical analysis with multiple simulations using random number generation to synthesize process variations. process variations Variation of device parameters inherent in fabrication due to acceptable tolerances. mismatch Variation in device parameters within the same circuit. Contributes to input offset in opamps and comparators. output filtering Process by which data beyond expected statistical limits are eliminated. 2/10/05 Virtuoso Analog Design Environment 9-4 Overview of Monte Carlo Analysis The features of the Monte Carlo Analysis Tool include: ■ An EDFM analysis tool ■ Multiple simulation tool using a large number of samples ■ Uses a statistical approach to evaluate the performance of a design ■ Provides broad coverage in exploring the “Design Space” ■ Emulates the variations in model parameters due to process tolerances ■ Very useful in finding “problem areas” ■ Used to predict process yield The Monte Carlo Tool is based on the “Monte Carlo” analysis technique. This analysis uses the random selection of model parameters based on statistical distributions. Monte Carlo Analysis 9-5 Overview of MonteCarlo Analysis Background: The manufacturing variations in components affect the production yield of any design that includes them. Monte Carlo analyses these relationships in detail. Monte Carlo Analysis Monte Carlo is a specific type of statistical analysis in which variables are randomly selected and applied to the specific application, and the results are then evaluated. If applied properly, a Monte Carlo analysis can accurately predict the yield of a product fabricated with a specified process. EDFM Monte Carlo Analysis is one of the EDFM tools available with the Virtuoso Analog Design Environment. It is often used to detect problem areas within the design space. It can also be used to explore the design space. Multiple Simulation Tool Monte Carlo is a multiple simulation analysis tool. In Monte Carlo, the inputs to the simulation (process variables and mismatches) are automatically altered between simulation runs. These variables are altered randomly using random number generators. The Spectre® Direct simulator provides special features for running Monte Carlo Analysis that facilitate higher performance. 2/10/05 Virtuoso Analog Design Environment 9-6 Simulation Using Process Distributions N=N+1 Random Number Generator Model Files Select Value From Model Distribution Modify Parameter Value Run Simulation Append Results No Yes N = Number of Samples Exit Monte Carlo Analysis 9-7 Simulation Using Process Distributions Background Manufacturing always produces a distribution in model parameters. The distribution of each parameter is evaluated for mean, standard deviation, and type of distribution. The statistical properties are included in the model file. When the device is manufactured, process variations will occur. The actual device parameters are not known until fabrication has been completed. The outcome of a specific fabrication cycle cannot be predicted. However, over a large number of fabrication cycles, the distributions in device parameters will occur. Using the above flow, the analysis emulates the variation in the device parameters from processing many fabrication lots. 2/10/05 Virtuoso Analog Design Environment 9-8 Example of Monte Carlo Using Simple LPF Uniform Distribution Normal or Gaussian Distribution Monte Carlo Analysis 9-9 Example of Monte Carlo Using Simple LPF The circuit above is simulated using the Monte Carlo Analysis Tool. The capacitor C0 has a nominal capacitance value of 1.0pf. This is a simplified example of a low pass filter in which only the CAP value is altered between simulation runs. The histograms for C0 are obtained by executing Results—Plot—Histogram in the Analog Statistical Analysis user interface. The first simulation run is 1000 samples using a “unif” distribution for CAP in the model file spectreLib5.scs. The Spectre circuit simulator simulates the above circuit 1000 times in which the value for CAP is changed randomly with a uniform distribution. The second simulation run is 1000 samples using a “gauss” distribution for CAP in the model file spectreLib5.scs. The Spectre circuit simulator simulates the above circuit 1000 times in which the value for CAP is changed randomly with a normal distribution. 2/10/05 Virtuoso Analog Design Environment 9-10 Monte Carlo Analysis Environment Starts with outputs from the Simulation window (Spectre Only) wave, scalar, or unknown Select Tools—Monte Carlo in the Simulation Window. Setup, expression definition, and statistical analysis forms all in a single window. Monte Carlo Analysis 9-11 Monte Carlo Analysis Environment Number of Runs: Select the number of Monte Carlo runs (default = 100). Starting Run #: Select starting iteration # (default = 1). Define the starting seed of the statistical analysis that sets the first pseudo-random seed used in the random variation functions (i.e., gauss(), etc.). Consequently, to run several sets of analyses, collecting the results from all, each subsequent set should start with an iteration of the # of previous runs + 1. This is used in conjunction with the Append to Previous Scalar Data option. Analysis Variation: Select an Analysis Variation type (default = “Process Only”). The default choices for the Spectre® tool are (i) Process Only, (ii) Process and Mismatch, and (iii) Mismatch Only. Swept Parameter: Select a stepped/swept parameter (default = “None”). This selection determines if an inner loop is performed for each set of random variables (i.e., each iteration of Monte Carlo). The choices are: “None”, “Temperature”, or any one of the design variables in the design. Only one parameter may be swept. Append to Previous Scalar Data: Choose whether the scalar output data from the run should be appended to previously saved scalar data (default = “no”). Save Data Between Runs to Allow Family Plots: Choose whether the raw output data (PSF files) should be saved between iterations (default = “no”). Selecting this option plots families of waveforms representing variation of entire waveforms. Select specific nodes or terminal, rather than all voltages and currents, to save on the disk space usage. Perform Nominal Run to Check Expressions: Choose whether a nominal simulation is run, prior to starting the Monte Carlo process, to validate the expressions defined in the Outputs section (default = “no”). This option is highly recommended because it avoids the possibility of running the analysis and not getting the desired results. 2/10/05 Virtuoso Analog Design Environment 9-12 Support of Spectre Direct ■ Spectre includes commands for statistical modeling and Monte Carlo looping within the simulator. ■ Simplified methodology for specifying statistics, correlation, and mismatch. ■ All runs from a single netlist. ■ Online help available with the following command in an xterm window: spectre -h montecarlo Note: The following are only available in Spectre Direct Monte Carlo simulations: ■ Distributed processing ■ Save/plot any data or families of curves Monte Carlo Analysis 9-13 Support of Spectre Direct Monte Carlo with the Spectre Direct simulator runs from a single netlist. The statistical variations take place in the simulator, whereas in the socket mode, every single Monte Carlo run requires a new final netlist and a restart of the Spectre software. This is a huge time saver. 2/10/05 Virtuoso Analog Design Environment 9-14 Spectre Direct Statistical Modeling Several files are used for modeling of process variations: ■ Model file: Contains variables altered by other include files. ■ Variables include file: used to set global variables in prior versions, as in this example: simulator lang=spectre parameters PiRho=2500 PbRho=200 stat=1 npnbeta=145.5 pnpbeta=200 initstat=1 ■ Distribution include file: Defines statistical distributions for all variables. ❏ Contains statistics blocks for process and mismatch variations ❏ Types of distributions available: Gaussian, Uniform, Lognormal ❏ Specify process and mismatch correlations ❏ Support of altergroup statement in Spectre simulator Monte Carlo Analysis 9-15 Spectre Direct Statistical Modeling The Monte Carlo tool now works both in socket mode and in native Spectre (direct) mode. When you run Monte Carlo in Spectre Direct mode, the statistical variations are specified in several include files or a single file. Specifying the statistical expressions in the CDF is not currently supported in Spectre direct. Example using several files: simulator lang=spectre include "processSimple.scs" include "process.scs" statistics { process { vary RSHSP dist=gauss std=5 vary RSHPI dist=lnorm std=0.15 vary SPDW dist=gauss std=0.25 vary SNDW dist=gauss std=0.25 } correlate param=[RSHSP RSHPI] cc=0.6 mismatch { vary XISN dist=gauss std=1 vary XBFN dist=gauss std=1 vary XRSP dist=gauss std=1 } } File: monteProcess.scs // Provides the designer with "geometrical" device interface simulator lang=spectre // Call to the geometrical TNSA model inline subckt TNSA (C B E S) parameters WE=1u LE=1u MULT=1 dIS=0 dBF=0 TNSA (C B E S) TNSA_PR WE=WE LE=LE \ MULT=MULT dIS=dIS dBF=dBF // call TNSA_PR ends TNSA // Call to the geometrical RPLR model inline subckt RPLR (A B) parameters Rnom=1 WB=10u MULT=1 dR=0 RPLR (A B) RPLR_PR Rnom=Rnom WB=WB \ MULT=MULT dR=dR // call RPLR_PR ends RPLR File: process.scs In addition, there is a file that will contain the models for the “primitives” (TNSA_PR and RPLR_PR devices) that are used by the inline subcircuits in the process.scs file. The file monteProcess.scs is a distribution include file. 2/10/05 Virtuoso Analog Design Environment 9-16 Statistical Modeling simulator lang=spectre parameters PiRho=2500 PbRho=200 npnbeta=250 pnpbeta=80 CAP=.8p statistics { process { vary PbRho dist=lnorm std=40 vary npnbeta dist=gauss std=20 vary pnpbeta dist=gauss std=25 vary CAP dist=gauss std=30 percent=yes } mismatch { vary PbRho dist=lnorm std=3.75 vary npnbeta dist=gauss std=4 vary pnpbeta dist=gauss std=6 }} inline subckt trnpn (C B E) model npnstat bjt type=npn is=10e-15 bf=npnbeta \ va=58.7 ik=5.63e-3 rb=565 rbm=86 re=3.2 cje=1.3e-12 pe=0.76 \ me=0.34 tf=249e-12 cjc=0.8e-12 pc=0.55 mc=0.35 ccs=2.4e-12 \ ms=0.35 ps=0.53 rc=169 vsubfwd=10 trnpn (C B E) npnstat ends trnpn inline subckt trpnp (C B E) model pnpstat bjt type=pnp is=1.2e-16 bf=pnpbeta nf=1 vaf=60 ikf=4e-5 \ ne=1.5 br=80 nr=1 var=5 ikr=5e-5 isc=0 nc=1.5 rb=100 re=15 rc=30\ cje=30e-15 vje=.72 mje=.45 tf=5e-10 ptf=40 cjc=60e-15 vjc=.72\ mjc=.45 xcjc=.9 tr=5e-10 cjs=0 vjs=.99 mjs=.99 trpnp (C B E) pnpstat ends trpnp ...(continued) Monte Carlo Analysis 9-17 Statistical Modeling In the example above, the model names trnpn and trpnp were maintained so you do not need to change the names of the models on the devices in the schematic. Additional example of a Monte Carlo distribution include file: simulator lang=spectre statistics { process { vary vth0_nfet_x dist=gauss std=vth0_nfet_t vary u0_nfet dist=gauss std=u0_nfet_t vary rdsw_nfet dist=gauss std=rdsw_nfet_t vary cgso_nfet dist=gauss std=cgso_nfet_t vary cgdo_nfet dist=gauss std=cgdo_nfet_t vary cgsl_nfet dist=gauss std=cgsl_nfet_t vary cgdl_nfet dist=gauss std=cgdl_nfet_t } mismatch { vary stat dist=gauss std=0.1 } } 2/10/05 Virtuoso Analog Design Environment 9-18 Other Features in Monte Carlo ■ Save data between runs to plot families of curves for all iterations. This can consume lots of disk space, so select signals appropriately. ■ Outputs selected in Simulation window prior to starting the Monte Carlo tool are automatically placed in the Output Expressions section ❏ No need to manually re-enter data to be measured/saved ❏ Expressions can be added/edited/deleted ■ Can run specific iterations again ■ Can save the OCEAN script for batch processing ■ Can save and load Monte Carlo setups A nominal run not required prior to entering expressions. ■ Use the Check Expressions capability. This helps to determine whether the output expressions and signals—defined or selected—are valid. Monte Carlo Analysis 9-19 Other Features in Monte Carlo Previous versions of Monte Carlo analysis required you to run a nominal simulation prior to entering Monte Carlo expressions. This prerequisite has been removed and replaced by the Check Expressions function. Use Simulation—Check Expressions to validate the entries in the Outputs section. If data exists, Check Expressions will use this for the validation. If no data is currently available, a message box pops up. A nominal simulation will be run automatically by the Monte Carlo tool. With this feature, it is possible to use restored results with Check Expressions. 2/10/05 Virtuoso Analog Design Environment 9-20 Monte Carlo Results Analysis Monte Carlo Analysis 9-21 Monte Carlo Results Analysis The Monte Carlo environment provides many ways to evaluate the simulation results. ■ The graphical results as shown above and as demonstrated in the lab activity. ❑ Printed results ❑ Histograms ❑ Filtered data ❑ Scatter plots ❑ Yield 2/10/05 Virtuoso Analog Design Environment 9-22 Monte Carlo Results Analysis (continued) Monte Carlo Analysis 9-23 Monte Carlo Results Analysis (continued) The above figure shows a text window displaying iteration versus value and a scatter plot. The scatter plot shows correlation between the capvalue and beta parameters. 2/10/05 Virtuoso Analog Design Environment 9-24 Filtering Output Data Results — Filter Results—Specification Limits Monte Carlo Analysis Filtering Output Data 9-25 2/10/05 Virtuoso Analog Design Environment 9-26 Summary In this module we discussed: ■ Overview of Monte Carlo analysis ■ The Monte Carlo environment ■ Statistical modeling ■ Process variation methodology ■ Setting up Monte Carlo analysis ■ Running Monte Carlo analysis ■ Filtering output data Monte Carlo Analysis Summary 9-27 2/10/05 Virtuoso Analog Design Environment 9-28 Labs Lab 9-1 Monte Carlo Analysis Monte Carlo Analysis 9-29 2/10/05 Virtuoso Analog Design Environment 9-30 ® 10 Optimization Analysis Module 10 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 10-2 Topics in this Module ■ Introduction ■ Optimization design flow ■ Optimization computational flow ■ Optimization options form ■ Algorithms used in optimization ■ Adding goals ■ Curve fitting ■ Iteration history ■ Plotting options ■ Optimization using OCEAN Optimization Analysis 10-3 Terms and Definitions Terms and Definitions optimization goals LSQ CFSQP curve fitting Process to increase circuit or system performance by changing selected design parameters. A design target of circuit performance, such as bandwidth. Least Squares Fit. A model fit that minimizes the squared error of all data points. C version Feasible Sequential Quadratic Programming, an optimization algorithm. The optimization capability to define the target goals over a specified range. 2/10/05 Virtuoso Analog Design Environment 10-4 Introduction to the Circuit Optimizer Tool ■ The Cadence Analog Circuit Optimizer is a software design tool used to find the optimum values of circuit components. ■ The Optimizer is one of five EDFM design tools. As such, it is intended to set up and run multiple simulations. The Optimizer is unique in that the number of simulation runs is unknown. It is also unique in that the simulation input files are generated by the previous simulation results. The Optimizer is used to ❏ explore the design space, ❏ establish circuit component values used for the other EDFM tools, ❏ optimize circuit performance, and ❏ develop accurate behavioral models for the circuit. ■ Use the Optimizer to automatically determine component values based on design goals. ❏ The Optimizer eliminates the need for the tedious tasks of searching for component values to obtain specified performance (or to prove it is not feasible). Optimization Analysis 10-5 Introduction to the Circuit Optimizer Tool The Cadence Analog Circuit Optimizer is a design tool intended to eliminate the tedious tasks of searching for component values to obtain a specified performance. The Optimizer performs the repetitive tasks of opening the simulation output files, analyzing the simulation results, altering component values, and then submitting the next set of simulation runs. 2/10/05 Virtuoso Analog Design Environment 10-6 Optimization Analysis Flow Create Schematic Start Simulation Environment Tool — Optimization Goals — Add Variables — Add/Edit Optimizer — Run Analyze Results Optimization Analysis 10-7 Optimization Analysis Flow Apply optimization profitably in a wide range of activities. ■ When using a top-down design approach, optimize a circuit block so that its performance characteristics match the desired characteristics defined in an analog AHDL module. ■ Using the opposite approach, optimize a macro or behavioral module so that it accurately describes the behavior of a circuit block. Then, instead of simulating with the circuit block, simulate with the macro or behavioral model, which usually runs much faster. ■ Optimize model parameters so that they match measured device data under various conditions. ■ Use optimization to address radio frequency (RF) design problems, such as impedance matching. ■ To increase circuit yield, use optimization to achieve better design center values. ■ Use optimization to match the frequency response of a filter to the specifications for the filter. ■ Use optimization to balance design tradeoffs. The product is called the Resolve Optimizer. 2/10/05 Virtuoso Analog Design Environment 10-8 Optimization Computational Flow Initial Value Sensitivity Simulations (N) Trial Simulation Trial Solution Loop 2~3 simulations Is this acceptable? No If (f= than a certain value. The values for the Target and Acceptable fields are used by the algorithm to attach weights to the constraints. Also, specify the percentage (%) within the target. Enabled Turns on/off this goal during optimization. Use a functional goal to optimize in curve fitting applications. 2/10/05 Virtuoso Analog Design Environment 10-16 Design Variables Menu Variables—Add/Edit Optimization Analysis 10-17 Design Variables Menu After setting up the objectives/constraints form, specify which design variables to use. These are the variables that the optimizer can change in the process of meeting the design targets. Optimization design variables must be Simulation environment variables. Typical variables can be component parameters and device/model parameters. Name The name of the design variable in the design. Initial Value The initial value that the algorithm will use to start the optimization step. Minimum Value The minimum value for the design variable. Maximum Value The maximum value for the design variable. Enabled Turns on/off this design variable during optimization. 2/10/05 Virtuoso Analog Design Environment 10-18 Options Menu Sessions —Options ■ Algorithm Selection: Specify the optimization algorithm. ■ Percentage Finite Difference Perturbation: Set the step length. ■ Relative Design Variable and Function Value Tolerance: Specify the relative percentage change in values for the stopping criteria for LSQ. Note: These are expressed as absolute numbers rather than percentages (for instance, 0.05 is equivalent to 5%.) Optimization Analysis 10-19 Options Menu Algorithm Selection: Generally, there is no need to pick which algorithm to use for the problem. The optimizer decides which algorithm to use based on the type of optimization to be done. However, this option provides the ability to force the optimizer to use a particular algorithm. Percentage Finite Difference Perturbation: As is the case for algorithm selection, it is not necessary to set up the step: the optimizer uses its default value. This is suggested for most designers. For advanced designers who have better knowledge of the effect of the step length, the Finite Difference Perturbation field provides a way to specify the step length that is appropriate. Caution should be taken in using this because some problems are very sensitive to the step length used. Relative Design Variable Tolerance (LSQ Only) and Relative Function Value Tolerance: The Relative Design Variable Tolerance and Relative Function Value Tolerance fields are designed to stop the algorithm by specifying stopping criteria to use rather than using the default settings. These fields are entered as absolute numbers instead of percentages. For example, if 0.05 is specified in the Relative Design Variable Tolerance field, that means if the relative change in the design variables is smaller than 5 percent, the algorithm would stop. Likewise, if 0.05 is specified in the Relative Function Value Tolerance field, the algorithm will stop when the relative change in each function value is smaller than 5 percent. 2/10/05 Virtuoso Analog Design Environment 10-20 Curve Fitting ■ Optimizing circuit output to match a desired waveform (functional goal). ■ Waveform can be a waveform object or a file of x-y data. ■ Many applications ❏ Real circuit used to match an AHDL model ❏ Filter responses ❏ Impedance matching in RF applications ❏ Design scaling and migration ❏ Design centering in order to increase circuit yield ❏ Filter frequency response can be optimized to meet the required performance ❏ Balance design tradeoffs Optimization Analysis 10-21 Curve Fitting Curve Fitting is the capability to optimize a circuit behavior to a set of waveform targets and constraints. Each objective consists of multiple points generated by the simulation analysis. This kind of curve fitting is usually used to optimize device model parameters or to improve circuit performance. Examples: ■ Optimizing a circuit model to an AHDL module. In a top-down design, the final circuit parameters will be calculated based on the behavioral model performance. Place an AHDL instance as well as circuit instance and optimize the output from both. Select the output from AHDL instance as a target and from the circuit as an objective. ■ The opposite case is to create a macro or behavioral module from a circuit model. In this case, it is preferred to save the circuit behavior in a file and use it as a target for the behavioral model. This is useful because the circuit doesn’t have to be resimulated (which is usually much slower to simulate) for every new AHDL or macro model parameter set. ■ Device model parameters extraction. Model parameters are used as design variables that are optimized to produce device model characteristics that match measured device data at different conditions. Use this to migrate to a new device model that has better convergence characteristics, faster simulation time, and uses less memory. ■ RF applications such as impedance matching. ■ Design scaling and migration, and design centering in order to increase circuit yield. ■ Filter frequency response and balance design tradeoffs. 2/10/05 Virtuoso Analog Design Environment 10-22 Curve Fitting (continued) ■ When setting goals, use the Acceptable Percentage option: Acceptable 5 % within Target A scalar entry gives the same weight to all calculated points. ■ Use a table or a list to weight different parts of a curve to match. 10% 10% Acceptable% 2% 2% Calculated Acceptable List Target Sweep Parameter Target 1 4 9 16 25 Acceptable% 10 10 2 2 2 Calculated Acceptable 1.1 4.4 9.18 16.32 25.5 Optimization Analysis 10-23 Curve Fitting (continued) This feature allows the acceptable value to be a percentage of the Target field at each separate point in the curve. The percentage field is useful to keep final optimization results consistent at very small and very large numbers in the Target list. Specify the percentage change around the Target. For example, if the Objective is to be at least 99% of the Target, specify Acceptable as 1% within Target. The Acceptable field can be a scalar or a list. In the case of a list, each Target point will have its own Acceptable value. This will emphasize the importance of some areas in the curve over other less important regions. The closer the Acceptable to the Target, the higher the Objective weight is. This is because the optimizer is using the following scaling factor to evaluate the Objective with respect Target: (Objective - Target) / (Acceptable - Target) When using absolute values for the Acceptable field, these values are used directly. On the other hand, specify the Acceptable as a percentage of the target as shown in the table above. When specifying the Acceptable percentage field as scalar, all the points will have the same weight. But when defining an Acceptable percentage list, the resulting weighting will have the shape of the square wave shown above. 2/10/05 Virtuoso Analog Design Environment 10-24 Curve Fitting to User-Defined Waveforms Goals—Add Click the wave button in the calculator and select a waveform, or enter an expression or table object. Optimization Analysis 10-25 Curve Fitting to User-Defined Waveforms Define the target, goal, and acceptable waveforms. This data has to be converted to waveform variables to be used in conjunction with other tools and input forms. A file of x-y value pairs can be obtained through the print engine, a third party tool, or manually entered x-y data file. The expression for the waveform in the Target field above can be obtained from the calculator by clicking on the wave button and then the desired waveform. When running OCEAN, the waveform can be stored as a SKILL variable and then entered with the goals command. The source of these waveforms can be any of the following: ■ A user-defined SKILL list. ■ A calculator SKILL expression. ■ A tabular input data file. ■ A waveform generated from previous results. These variables will be used directly or in expressions and assigned to target, acceptable or constraints fields. 2/10/05 Virtuoso Analog Design Environment 10-26 Iteration History Optimization Analysis 10-27 Iteration History A Waveform Window appears during the optimization run that displays the history of the different values of the variables, as well as the goals that the simulator attempts to satisfy. After the simulation ends, the final values of the goals and design variables appear in the Optimization window. Specify which items to display in the Waveform Window during optimization. The options are shown in the graphic on the next page. 2/10/05 Virtuoso Analog Design Environment 10-28 Plotting Options Results—Set Plot Options Optimization Analysis 10-29 Plotting Options Specify to plot the Variables, Scalar Goals, and Functional Goals during the optimization run. ■ Variables: The values of the design variables that are modified during optimization ■ Scalar Goals: The values of the scalar goals set by the user ■ Functional Goals: The waveforms that are set as goals by the user The No. of Functional Iterations to Display field specifies how many iterations of the optimization loop are plotted in the Waveform Window. 2/10/05 Virtuoso Analog Design Environment 10-30 OCEAN Interface ■ Select Session—Save Ocean Script to create an OCEAN script for batch optimization jobs. ■ The following OCEAN commands have been added to allow optimization simulations: optimizeAlgoControl optimizeGoal optimizeRun optimizeVar optimizePlotOption Use ocnHelp() for more information on these commands. Optimization Analysis OCEAN Interface 10-31 2/10/05 Virtuoso Analog Design Environment 10-32 Labs Lab 10-1 Running Optimization Analysis Optimization Analysis Labs 10-33 2/10/05 Virtuoso Analog Design Environment 10-34 ® 11 Component Description Format (CDF) Module 11 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 11-2 Topics in this Module ■ Overview of CDF ■ Types of CDF and CDF levels ■ CDF user interface form ■ Editing a component’s parameters using CDF ■ Editing simulation information using CDF Component Description Format (CDF) 11-3 Terms and Definitions Terms and Definitions CDF Acronym for Component Description Format library CDF Defines component properties common to all cells in the library. cell CDF Defines component properties unique to the cell in the library. base-level CDF Lowest level CDF, always saved to memory. user-level CDF User-defined property that masks a base-level CDF when applied to schematic components. effective CDF Combination of user- and base-level CDF used for simulation. label display Labels attached to components in schematics. prompt A displayed text that indicates a value is to be entered. 2/10/05 Virtuoso Analog Design Environment 11-4 CDF Overview CDF is encoded and attached to design database objects. CDF defines component behavior within the SKILL language. Add Instance Schematic Editor Schematic Editor 2 Window Edit Schematic Simulation Environment CDF Skill Skill Skill DLE Label1 Label2 Label3 Layout Editor FrameworkLTaoyoolsutMask Layout3 Window Edit Mask Layout R: 5 Component Description Format (CDF) 11-5 CDF Overview CDFs are attached to components and libraries in the Design Framework II environment. It is a textual database written in the SKILL extension language. The Virtuoso Analog Design Environment references CDFs to gain information about design components. Some examples are: ■ The Add Instance form reads the CDF to display a component’s parameters. The CDF determines default value, type, and units. CDF can be used to limit available choices for component parameters (parameterization). ■ Label displays in the schematic editor are controlled by the CDF. In fact, the Label Display form works by indirectly editing CDF. ■ The simulation environment uses the CDF to generate the simulation netlist. ■ The Layout Editor references the CDF to translate schematic components into layout components with the proper dimensions and electrical characteristics. As changes are made in the schematic, the layout can be continually updated. 2/10/05 Virtuoso Analog Design Environment 11-6 Types of CDF CDF is a part of a library or cell and is always copied with the database object. CDF attached to a library is adopted by all cells in the library. CDF Example: Label Defaults Library CDF attached to a cell in a library is specific to the cell. Library NPN device Capacitor A Cell A Cell B Cell C CDF Capacitor C CDF CDF Cell CDF masks the Library CDF to produce an Effective result. + = Library Cell Effective Cell The Effective Cell CDF exists only in virtual memory. Component Description Format (CDF) 11-7 Types of CDF When attaching a CDF to a library, all components in the library inherit the description. When attaching a CDF to a component, the description is attached to the component’s cell. Library-level CDF data is shared by all cells in the library. Cell-level CDF data creates or overwrites library level data. Library CDF is the lowest level. Cell CDF overlaps the Library CDF to produce the Effective Cell CDF as illustrated. Note that Cell CDF overrides Library CDF adding additional quantities and redefining Library CDF quantities. Effective Cell CDF is the CDF used by the system. View Effective CDFs to see the combined Library and Cell CDFs. 2/10/05 Virtuoso Analog Design Environment 11-8 Levels of the CDF 1 Base 2 User 3 Effective Library Cell Instance 7 Base 4 User 5 6 Effective Base CDF is stored on disk. User CDF is a user-defined mask in virtual memory. The Effective CDF is the result of the user mask redefining the Base CDF. + = Base User Effective The highest Effective level of CDF is used by the system. The highest level of CDF is the overlapping summation of all the CDFs at lower levels. Component Description Format (CDF) 11-9 Levels of the CDF A dual hierarchy of CDF exists. Library and cell CDFs have another level of hierarchy to describe them. Base CDF is the lowest level. User CDF masks the Base CDF to produce the Effective CDF as illustrated. Note that User CDF overrides Base CDF adding additional quantities and redefining Base CDF quantities. Effective CDF is the overlapping sum of all the existing Base and User level CDFs beneath it. It is the CDF used by the system. The illustration shows the seven overlapping levels of CDF. The number indicates the precedence of the CDF. For an existing CDF, the highest numbered Effective CDF is the one used by the system. Instance CDF stores instance-specific quantities, like component parameter values or instance identifiers, and is always the highest level of CDF stored with the design database. Effective and User CDFs, by default, are not saved beyond the current design session. However, you can save these settings to a file and attach them to other schematic objects in the future. Write permission is not needed to attach user-level CDF information to an object. Instance CDF (level 7) is edited when updating an instance’s properties in the schematic window. It is saved permanently when the design is saved. Base CDF can be permanently saved to disk using the CDF user interface. The creator of a base-level CDF must have write permission to the object to which the description is being attached. We will discuss the CDF user interface next. The Label Display form updates User CDF implying labels must be explicitly saved if they are to be retrieved after the current design session. To make label display information on components permanent, update component labels using the Label Display form and immediately copy the Effective CDF to the Base CDF. Label display settings are then saved to disk as part of the component or library description. 2/10/05 Virtuoso Analog Design Environment 11-10 The CDF User Interface Form In the CIW, select Tools—CDF—Edit. NOTE: This is a long form that also includes entry fields for “Interpreted Labels Information” and “Other Information” Component Description Format (CDF) 11-11 The CDF User Interface Form Use the CDF user interface to create, view, or edit a CDF without having to write or edit a textual SKILL CDF. The CDF user interface form has header information, including the library and cell names. A CDF Type cyclic field selects the Base, User, or Effective CDF. This cyclic field is set to Effective when the form first appears. In this mode, the User-level CDF is generated indirectly when changing the effective results. A file saving feature saves the settings of the CDF forms, but not the CDF itself. Saved settings can also be loaded back into the CDF. However, the CDF is generated for a component, or edits take effect, only when clicking Apply or OK in the CDF user interface form. The four sections of the CDF appear below the header information. Under each section are relevant command buttons, such as Add, Edit, and Move in the first section, called Component Parameters. The remaining sections cover Simulation Information, Interpreted Labels Information, and Other Information. Avoid creating a CDF from scratch, since similar CDF information can be copied and edited from a sample component. To view or edit a textual CDF file, type the following in the CIW: cdfDump(“libName” “filename” ?cellName “cellName” ?level ‘ ?edit ) To write the CDF of the npn cell in analogLib to a file named “test” that opens for edit, type: cdfDump(“analogLib” “test” ?cellName “npn” ?level ‘base ?edit t) This file can be edited and loaded back into the CDF. See the online Component Description Format User Guide for more information. 2/10/05 Virtuoso Analog Design Environment 11-12 Editing Component Parameters in the CDF ■ Click Add to add new component parameters. ■ Click Move to change the order of listed parameters. Component Description Format (CDF) 11-13 Editing Component Parameters in the CDF A separate form is used to edit component parameters in the CDF. Each entry field has a complete definition in the Component Description Format User Guide. Here are some field definitions that highlight CDF capabilities: ■ Change the paramType field to make this component appear as a radio button, cyclic field, text field, etc. on any form that uses CDF. ■ For most analog applications, the parseAsCEL field should be yes, and the storeDefault field should be no. For details, refer to the Component Description Format User Guide. ■ If there were multiple choices for this parameter, they could be entered in the choices field. Examples would be the cyclic or radio parameter types. ■ The component parameter has a name and a prompt as it would appear on a form that uses CDF. For example, the Add Instance form. ■ Set a default parameter value in the defValue field. Some parameterized component types require a default value in the CDF. ■ The callback field contains the name of a SKILL routine loaded into ADE that can alter this component parameter’s values based on the values of the other component parameters. An example is size-dependent models, which will be modified in a layout or schematic based on a parameter passed to the placed instance. Callbacks are discussed in depth in the Component Description Format User Guide, and are not recommended for use with the Spectre Direct simulation environment. 2/10/05 Virtuoso Analog Design Environment 11-14 Editing Simulation Information in the CDF This is the Spectre simulation information for a 4-terminal NMOS with a model parameter area1 (in addition to others) that is passed to the model file. There is a Simulation Information section for each simulator. Component Description Format (CDF) 11-15 Editing Simulation Information in the CDF This illustration is an example of the CDF Simulation Information that you can edit. The parameters and their values are specific to the chosen simulator. In this case, the Choose Simulator cyclic field is set to spectre. 2/10/05 Virtuoso Analog Design Environment 11-16 Editing Simulation Information in the CDF (continued) Set the instParameters field for the Spectre simulator to pass information from the design to a parameterized model by the following: 1. Create a parameterized model file (inline subcircuit): inline subckt mynmos4 (d g s b) parameters area1 = 10 mynmos4 (d g s b) trnmos1 l=sqrt(area1)*1e-6 w=10*sqrt(area1)*1e-6 model trnmos1 mos2 type=n vto=(area1/100)*0.775 tox=400e-10 nsub=8e+15\ ... 2. Define CDF component parameters or add a User Property that passes to the model file. Example: area1 3. List the component parameters in the instParameters field of the Simulation Information Section. Example: instParameters =area1 4. Set the componentName=Model Name, OR set a value for the model component parameter and set otherParameters=model. Set or reset the model parameter value when placing a component instance. The netlister sets the value of each parameter for each instance that uses the model file. Component Description Format (CDF) 11-17 Editing Simulation Information in the CDF (continued) Edit the CDF Simulation Information section for every simulation engine integrated into your system. Consult the Component Description Format User Guide for details on form settings. Information in this form is used by the system for netlisting purposes. The examples in this book cover the use of the Spectre Direct simulator. The instParameters field can contain the names of a cell’s CDF parameters to be passed to the cell’s model file. To accomplish this, first write a model file (inline or standard subcircuit, or standard model file) that contains parameters, as in this example: inline subckt mynmos4 (d g s b) parameters area1 = 10 mynmos4 (d g s b) trnmos1 l=sqrt(area1)*1e-6 w=10*sqrt(area1)*1e-6 model trnmos1 mos2 type=n vto=(area1/100)*0.775 tox=400e-10 nsub=8e+15 \ ... The parameter area1 is set in the model. Next, add this component parameter to the CDF and to each parameter to be passed into a model. Finally edit the CDF simulation information and list the names of the component parameters in the instParameters field. In addition, set the componentName field to be the name of the model file (inline or standard subcircuit, or standard model file) to point to, or create, a component parameter named model. Set the value of model to the name of the model file. Consult the Component Description Format User Guide for details. Values for CDF component parameters are requested when the component is placed in a design, and can overwrite the default values set in the model file. Assign numbers or variables to the parameters. If choosing the latter, the model parameters can be swept in a parametric analysis. 2/10/05 Virtuoso Analog Design Environment 11-18 Summary In this module we discussed: ■ Overview of CDFs ■ That CDF information is used to provide data between DFII design tools ■ The types of CDFs and CDF Levels ■ How to use the CDF user interface form ■ Editing a component’s parameters using CDF ■ Editing simulation information using CDF Component Description Format (CDF) Summary 11-19 2/10/05 Virtuoso Analog Design Environment 11-20 Labs Lab 11-1 The CDF User Interface Lab 11-2 CDF Effects in Simulation Component Description Format (CDF) Labs 11-21 2/10/05 Virtuoso Analog Design Environment 11-22 ® 12 Macromodels, Subcircuits, and Inline Subcircuits Module 12 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 12-2 Topics in this Module ■ Overview of Macromodels, Subcircuits, and Inline Subcircuits ■ Macromodels ■ Subcircuits ■ Library requirements to use Subcircuits ■ Inline Subcircuits ■ Inline Subcircuit example: Parasitic Devices ■ Advantages of Inline Subcircuits ■ Generalized Binning Macromodels, Subcircuits, and Inline Subcircuits 12-3 Terms and Definitions Terms and Definitions macromodel A behavioral model using a simplified schematic or text file. subcircuit A behavioral model using a text file. inline subcircuit Special subcircuit with one component having the same name as the instantiated subcircuit. high-level description A simplified behavioral description replacing the schematic. generalized binning Process of modeling parameters into regions. 2/10/05 Virtuoso Analog Design Environment 12-4 Overview Macromodels and subcircuits provide high-level descriptions of a cell block. The macromodel is a behavioral representation of a circuit that is either a schematic or a text file. When the macromodel is described with a text file, it is called a subcircuit. Inline subcircuits are special-case subcircuits where one device has the same name as the instantiated subcircuit. Use inline subcircuits to: 1. Override model parameters based on the instance parameter. 2. Place virtual components such as a parasitic BJT. 3. Select a component based on instance parameter. Macromodels, Subcircuits, and Inline Subcircuits 12-5 Overview Macromodels and subcircuits provide a high-level description of a complex block or cell. The high level simulates faster than the transistor-level circuit description of the cell. As such, the macromodels or subcircuits are used to test functionality of circuit blocks within a hierarchy. This facilitates design and verification of the system with a top-down or with a mixed-hierarchy design methodology. The system or chip-level debug and verification proceeds rapidly using the high-level descriptions. The final transistor-level description, the schematic view, is used during final verification. The Inline subcircuit is a special feature of the Spectre® simulator. The inline subcircuit provides customization of component parameters within the subcircuit. 2/10/05 Virtuoso Analog Design Environment 12-6 Advantages of Inline Subcircuits Advantages of Inline Subcircuits versus a conditional if statement in the Spectre environment: ■ No need to redefine the instance name, such as mospar. ■ Component shows up in postprocessing tools (Results Browser) with its instantiated name, rather than a hierarchical name. ■ Allows annotation of operating points in the Virtuoso Analog Design Environment. ■ Supports binning of models. ■ Supports parasitic modeling. For example, add parasitics to a component by changing a model card to an inline subcircuit. Macromodels, Subcircuits, and Inline Subcircuits 12-7 Advantages of Inline Subcircuits Annotate operating points in the Virtuoso Analog Design Environment using inline subcircuits. (This cannot be done with regular subcircuits.) Separate models into bins, to take advantage of foundry database modeling. 2/10/05 Virtuoso Analog Design Environment 12-8 Macromodels and Subcircuits A graphic instance can be described by a schematic, a macromodel, or a user-defined text file called a subcircuit file. The file is a subcircuit description. IN+ Symbol Schematic View Macromodels Macromodel OUT IN- Schematic View Textual Macromodel parameters inputCap=500e-15 C1 (plus minus) capacitor c=inputCap E1 (aout 0 plus minus) vcvs gain=1e6 R3 (aout output) 100e-3 R4 (plus minus) 10e6 ends A macromodel description or subcircuit file in the final simulation netlist will simulate faster than the schematic circuit description. The parameter inputCap allows the capacitor C1 to have the value passed into the subcircuit when the symbol is instantiated in a schematic. Macromodels, Subcircuits, and Inline Subcircuits 12-9 Macromodels and Subcircuits Macromodeling is a procedure that describes the functionality of a component that is a combination of many primitive devices. An example is an operational amplifier. Within the Virtuoso Analog Design Environment, there are two ways to create a macromodel. 1. Describe the functionality of a component with a schematic. 2. Describe the functionality of a component with a text file called a subcircuit file. When creating macromodels, there are a number of things to keep in mind: ■ What will the symbolic graphic look like? ■ What special properties will the component need to use a subcircuit file? ■ Will parameters pass from the component in the design to the subcircuit file? ■ How is a subcircuit file created? 2/10/05 Virtuoso Analog Design Environment 12-10 Library Requirements to Use Subcircuits Cells referencing a user-defined subcircuit file require cellviews with: ■ A symbol view. Create this using the symbol editor. Add symbol pins and a shape. ■ A cellview identifying the cell as a primitive component. Copy the symbol cellview to one that has the name of the simulator you are using, such as Spectre, Spectre S, cdsSpice. ■ A cell CDF that contains the name of the subcircuit file and defines any parameters that are passed to the file. ■ Pins on the subcircuit text that correspond to those on the symbol. ■ Any other parameters to be defined. ■ A subcircuit file can be defined in the Library Model File. Macromodels, Subcircuits, and Inline Subcircuits 12-11 Library Requirements to Use Subcircuits Creating the Graphic Symbol Use the symbol editor to create any shape, which can have any number of input and output pins. When placing symbol pins on the graphic, name them and assign a direction. These names are important since references are made to them later when defining the CDF for the macromodel cell. Add interpreted labels to the symbol to provide annotation capability after simulation or display schematic information as labels. An operational amplifier can have a symbol resembling the following: IN+ OUT IN- cdsParam(1) cdsParam(2) Creating the Primitive Cellview Using the Library Manager, create a cellview for your cell that has the name of the target simulator. It is a copy of the symbol cellview. Edit the symbol view and save the information to a cellview named spectre, cdsSpice, or spectreS with a Save As command in the symbol editor. The simulator cellview tells your system that the cell is a primitive device that might use a subcircuit file to describe its behavior. 2/10/05 Virtuoso Analog Design Environment 12-12 Inline Subcircuits Inline subcircuits are an enhancement available only with the Spectre Direct simulator. ■ Customization of component parameters Allows access to model parameters from the instance line ■ Virtual Components Example: Parasitic BJT Example: Parasitic Estimation ■ Automatic selection of components based on any instance parameter Macromodels, Subcircuits, and Inline Subcircuits 12-13 Inline Subcircuits An inline subcircuit is a special case of a subcircuit where one of the devices instantiated within the subcircuit takes on the name of the instance instantiation. The “inline” component is denoted by giving it the same name as the inline subcircuit itself. When the subcircuit is flattened, the inline component does not take on a hierarchical name such as X1.M1, but rather takes on the name of the subckt call itself, such as X1. Any noninline components in the subckt take on the regular hierarchical name, just as if the concept of inline subckts never existed. Use inline subcircuits to override model parameters from the instance line. This is a nice alternative to CDF callbacks, because ADE capabilities like parametric analysis will recognize the change to the netlist. Also, if you implement complex subcircuits as single instances, you will not need to track the often cryptic hierarchical component names. Binning on any model parameter is also possible. The inline subcircuit also allows conditional binning. For more details, enter these commands in an xterm window: spectre -h subckt spectre -h if (for conditional binning) 2/10/05 Virtuoso Analog Design Environment 12-14 Inline Subcircuit Example: Parasitic Devices inline subckt bjtpar (c b e ) parameters we=10u le=10u // emitter width, length model npnmod bjt bf=1e3*(we*le/1e-10) is=1e-6*(we+le...) ... bjtpar (c b e s) npnmod // the inline component qpar (s c b) parpnp // parasitic device model parpnp bjt type=pnp.. // model for parasitic ends bjtpar // instantiate with: q0 (1 2 3) bjtpar we=5u le=2u Model parameters based on instance parameters Inline subckt masquerades as a simple BJT. Macromodels, Subcircuits, and Inline Subcircuits 12-15 Inline Subcircuit Example: Parasitic Devices This example of an inline subcircuit shows how a designer can model a parasitic bjt device. The parameters assignments within the subcircuit (we, le) can be overridden on the instance line, so that the model can be parameterized for each device. In the postprocessing tools, the inline component for element q0 will be known as q0 and the parasitic element as q0.qpar. In the traditional implementation of subcircuits, the instance is known by its full hierarchical name. With inlines, only the parasitic device is called by its hierarchical name. The parasitic model (parpnp) can be specified within the subcircuit (as it is in this case), or it can be included as any other model with the include syntax of the Spectre simulator. Important Points: Inline Subcircuits can promote model parameters to instance parameters, and can add parasitic devices to a component in a manner that is transparent to the user. 2/10/05 Virtuoso Analog Design Environment 12-16 Inline Subcircuit Example: Parasitic Estimation inline subckt mospar (d g s b) parameters mym=1 min=0 drainwidth=(0.4+0.25+0.3)*1e-6 +sourcewidth =(0.4+0.25+0.3)*1e-6 l=1u if (min==0) {mospar d g s b nch ad=mym*l*drainwidth as= mym*l*sourcewidth } else if (min==1) {mospar d g s b nch ad=mym*l*drainwidth as= l*sourcewidth } else {mospar d g s b nch ad=l*drainwidth as= mym*l*sourcewidth } model nch bsim3v3 ends mospar Geometry selection based on instance parameter Macromodels, Subcircuits, and Inline Subcircuits 12-17 Inline Subcircuit Example: Parasitic Estimation The above example calculates the area of a MOS source and drain according to flags that define how the device will appear in the physical design. In this case, there is a flag, mym, that defines the number of stripes, and a flag, min, that will minimize the source, the drain, or neither. 2/10/05 Virtuoso Analog Design Environment 12-18 Generalized Binning inline subckt NPNmod (c b e s) parameters area=5e-12 if ( area < 100e-12 ) { NPNmod (c b e s) npn10x10 } else if ( area < 400e-12 ) { Model selection based on Instance Parameter NPNmod (c b e s) npn20x20 } else { NPNmod (c b e s) npn_default } model npn_default bjt is=3.2e-16 va=59.8 model npn10x10 bjt is=3.5e-16 va=61.5 model npn20x20 bjt is=3.77e-16 va=60.5 ends NPNmod q1 (1 2 0 0) NPNmod area=350e-12 // gets npn20x20 model q2 (1 3 0 0) NPNmod area=25e-12 // gets npn10x10 model q3 (1 3 0 0) NPNmod area=1000e-12 // gets npn_default model Macromodels, Subcircuits, and Inline Subcircuits 12-19 Generalized Binning Model binning is selecting an appropriate model based on certain ranges of specified parameters. It is the process of partitioning a device with different sizes into different models. With Spectre, model binning can be based on any parameter, and for any device. Other simulators are only able to bin on wmin, wmax, lmin and lmax. See the warnings about conditional instantiation in the SpectreRF User Guide. Rules for General Purpose Model Binning Within the subckt NPNmod, the inline device “NPNmod” is referenced three times (each with a different model). Allowing multiple “instances” or “references” to the same-named device will only be possible under the following, strict topological conditions: ■ Reference to same-named device is only possible in a structural “if” statement which has both an “if” part and an “else” part. ■ Both the “if” part and the “else” part must either be a simple one-statement block, or another structural “if” statement to which these same rules apply. ■ Both the “if” part and the “else” part must evaluate to a single device instance, whose instance name, terminal list, and type of primitive are identical. For example, multiple references to the same-named device will only be possible if there can be one single instance of this device after all expressions have been evaluated. In addition, each instance must be connected to the same nodes, and represent the same device (no topology change). The only thing that can change as the conditional expression changes is the actual model bound to the device. 2/10/05 Virtuoso Analog Design Environment 12-20 Using Inlines with the Virtuoso Analog Design Environment To use inline subckts in the Virtuoso Analog Design Environment with a primitive device: ■ Write the text of the inline subckt. ■ Place the component in the schematic. ■ Do one of the following: ❏ Using the CDF editor, create a parameter called model. Set a default value for this parameter in the Edit Component CDF form or set the value at the time you place the component in a schematic. ❏ Set the base CDF Spectre simInfo field componentName to the name of the inline subckt. ❏ Add the model parameter as a User Property to the Edit Object Properties form with a value that is the name of the inline subckt. ■ Add any additional parameters needed as instanceParams in the simInfo section of the CDF. Macromodels, Subcircuits, and Inline Subcircuits 12-21 Using Inlines with the Virtuoso Analog Design Environment It is easy to use an inline subcircuit in the Virtuoso Analog Design Environment. The value of model is the name of the inline subcircuit model. There is additional information to the steps listed above in the following lecture on Macromodels and Subcircuits. Values for CDF component parameters are requested when the component is placed in a design, and can overwrite the default values set in the model file. Assign numbers or variables to the parameters. If choosing the latter, the model parameters can be swept in a parametric analysis. 2/10/05 Virtuoso Analog Design Environment 12-22 Labs Lab 12-1 Creating a Parasitic Transistor Model Lab 12-2 Using Subcircuit Cells Lab 12-3 Adding a Subcircuit Representation Macromodels, Subcircuits, and Inline Subcircuits Labs 12-23 2/10/05 Virtuoso Analog Design Environment 12-24 ® 13 The Hierarchy Editor Module 13 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 13-2 Topics in this Module ■ Applications of the Hierarchy Editor ■ Overview ■ Creating a configuration ■ The Hierarchy Editor window ■ Selecting views with the Hierarchy Editor ■ The tree view of a Hierarchy ■ Opening a configuration ■ Synchronizing a configured schematic The Hierarchy Editor 13-3 Terms and Definitions Terms and Definitions Hierarchy Editor A Cadence tool for viewing and editing a design hierarchy. configuration A specialized cell view for using the Hierarchy Editor. configured schematic The schematic of the configuration cell view. view found The cell view within hierarchy of the current configuration. view to use The cell view to use within the updated configuration. 2/10/05 Virtuoso Analog Design Environment 13-4 Applications for the Hierarchy Editor The Hierarchy Editor is used to select the view to be used within a system hierarchy. In the design of a circuit used within a system, there are numerous phases of the design flow. Each phase of the design has cell views associated to that step. The Hierarchy Editor is a tool that selects the corresponding cell view for display and for netlisting the design. The Hierarchy Editor is used extremely useful in system level design, mixed signal design, and for parasitic analysis. Front System Definition (ahdl) (veriloga) Behavioral Simulation (ahdl) (veriloga) Mixed-Hierarchy Design (schematic) (veriloga) Topology Selection (schem1) (schem2) Component Values & Optimization (schematic) Physical Design (schematic) (layout) Parasitic Analysis (schematic) (analog_extracted) FRONT-TO-BACK FLOW Back The Hierarchy Editor 13-5 Applications for the Hierarchy Editor As shown in the diagram above, the design of a structure within the hierarchy takes on numerous views. The Hierarchy Editor is used to select view for netlisting and simulation. ■ Initially, the design is behavioral to determine the specifications needed for the cell block to work. Here, the view is perhaps ahdl, veriloga, or spectre. ■ The design then progresses to mixed level or mixed-hierarchy design, where the cell view is perhaps a veriloga view with more specified behavior, or a schematic view using ideal components. The Hierarchy Editor is used to verify proper behavior and performance as the views are selected. ■ In topology selection, the view is schematic. However, the design sometimes requires some research to determine a feasible circuit topology. As such, numerous schematics with unique view names are used. The Hierarchy Editor is used to select between the available views (schem1, schem2, etc.). The performance of the various topologies can be compared. ■ The circuit schematic is then optimized using EDFM tools in the Virtuoso Analog Design Environment. ■ The circuit is then reduced to a physical design to produce a layout view. ■ The layout is extracted and the Hierarchy Editor is used to select the analog_extracted view for the parasitic analysis simulation. 2/10/05 Virtuoso Analog Design Environment 13-6 Overview of the Hierarchy Editor The Hierarchy Editor (HED) is a graphical tool for creating configurations. designLib schematic peakDetect layout config mixedConfig Root cell Directories that contain configuration files Design Framework II view pc.db sch.cdb pc.db layout.cdb expand.cfg expand.cfg UNIX view Configuration: A set of rules that defines how cellviews in a design are partitioned and netlisted. The Hierarchy Editor 13-7 Overview of the Hierarchy Editor Use the Hierarchy Editor to do the following: ■ Prepare and organize complex designs for netlisting. ■ Browse a design hierarchy by viewing the instance bindings. ■ Speed the navigation of a large hierarchical design to open a cellview in the context of a design hierarchy. ■ Facilitate copying a hierarchy by specifying a configuration. ■ Simplify debugging of a hierarchy (finding, controlling, removing incorrect views). ■ Run a simulation on a configuration. The configuration is contained in a file named expand.cfg for each config cellview. A cell can have different configuration files for different purposes, such as mixed-signal simulation netlisting, LVS netlisting, etc. Run the Hierarchy Editor on a standalone basis or through the Design Framework II environment. Because the Hierarchy Editor is a separate tool from Design Framework II, you should always save the changes to the configuration files and have your Design Framework II applications read in the information again to access the new information. 2/10/05 Virtuoso Analog Design Environment 13-8 Creating a Configuration 1 File—New—Cellview 4 Select simulator name for template desired. Select Spectre, then OK in form Set to Hierarchy-Editor 2 Change myView to schematic, OK the form. 3 Select template The Hierarchy Editor 13-9 Creating a Configuration Create a configuration file with the File—New—Cellview command. Set the Tool field to Hierarchy-Editor in the Create New File form. The New Hierarchy form appears in front of the Hierarchy Editor window. Set the Template Name field to the simulator that you are using. More information about the Hierarchy Editor and Configuration files can be found in CDSDoc. 2/10/05 Virtuoso Analog Design Environment 13-10 The Hierarchy Editor Window When this icon is RED, select it to incorporate the selections. View Lists can be replaced with a constant, such as $analog. The Hierarchy Editor 13-11 The Hierarchy Editor Window The table format is the default display structure for the HED. A tree structure is also available, and both are helpful in setting up the views for simulation. Define what views to include in the hierarchy at three different levels: 1. The global level, using a global view list and stop list. 2. The cell level, using cell bindings or Inherited View Lists, which affect the cell as well as structures below the cell in the hierarchy. 3. The instance level, using instance bindings or instance based Inherited View Lists, which affect the instance as well as structures below it in the hierarchy. Import the View List, Stop List, and all other Cell Bindings and Instance Bindings from another configuration to the current one that is open. 2/10/05 Virtuoso Analog Design Environment 13-12 Selecting Views with the HED The banner prompts to save the new configuration. Click the Update icon to put changes into effect. The new Cell Binding The Hierarchy Editor 13-13 Selecting Views with the HED Select the desired view for simulation for each cell in the design. When a change is made to the configuration file in the HED, the Save Needed message appears at the top of the configured schematic window. Select File—Save to save your changes, or respond to the dialog box that appears after you click the Update button. In addition, when a change is made to the configuration, the Update button will highlight in red in the HED. Click the Update button to put your changes to the configuration into effect. 2/10/05 Virtuoso Analog Design Environment 13-14 HED Tree Format View tree from here. The Hierarchy Editor 13-15 HED Tree Format Click the Show Tree icon or select View—Tree to display the Tree format. The Tree format shows the position of the cells and cellviews in the hierarchy. Cells and instances subject to inherited view lists appear in dark blue print. Cells and instances subject to cell and instance bindings appear in light blue print. Cells and instances without chosen views appear in red print. Use the tree format to display the current configuration. Also, use the tree format to change cell/instance bindings, and to change inherited view lists. 2/10/05 Virtuoso Analog Design Environment 13-16 Opening a Configured Schematic New Information in Schematic Title Bar Click Open Open a Configured Schematic: ■ From the Open button in the Hierarchy Editor ■ Using the File—Open command in the CIW as you open the config view. ■ Using the Library Manager when you open the config view. The Hierarchy Editor 13-17 Opening a Configured Schematic All applications that run based on configurations must be executed from a schematic window that was opened from the config file (referred as the configured schematic). This applies to Showing Views Found, Netlisting, and Simulation. It is necessary to start the Virtuoso Analog Design Environment from the configured schematic to use your configuration to set the partition and cell bindings for simulation. 2/10/05 Virtuoso Analog Design Environment 13-18 Synchronizing the Configured Schematic The configured schematic might not match the current configuration file. To synchronize the configuration schematic to the configured file: ■ Click the Update button after modifying the configuration. ■ Click OK in the Cellviews Need Saving form that appears. The Hierarchy Editor 13-19 Synchronizing the Configured Schematic The Hierarchy Editor is a separate tool from the Design Framework II environment. If changes are made in the HED, the configured schematic that was opened prior to the modifications will contain out of date information. The schematic window banner will have the “(out of date)” label. To synchronize the configured schematic to the updated configuration file, click the Update button and then click OK in the Cellviews Need Saving form that appears. 2/10/05 Virtuoso Analog Design Environment 13-20 Summary In this module we discussed: ■ Applications for using the Hierarchy Editor ■ Overview ■ How to create a configuration ■ Selecting views in the Hierarchy Editor and saving the new configuration ■ Opening the configuration to view the hierarchy ■ Running a simulation on the configured schematic The Hierarchy Editor Summary 13-21 2/10/05 Virtuoso Analog Design Environment 13-22 Labs Lab 13-1 Creating a Configuration File with the Hierarchy Editor Lab 13-2 Running a Simulation with Subcircuits Lab 13-3 Rerunning Simulation with the Schematic View The Hierarchy Editor Labs 13-23 2/10/05 Virtuoso Analog Design Environment 13-24 ® 14 Inherited Connections Module 14 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 14-2 Topics in this Module ■ Applications of inherited connections ■ Setting net expressions and using the netSet property ■ Netlist and Run with inherited connections Inherited Connections 14-3 Terms and Definitions Terms and Definitions inherited connection Selectable connection to a default or instantiated net. default connection A connection to a net when a connection is not instantiated. net expression A property added to a net that is programmable. netSet Property added to component to override a default connection. substrate connection A terminal of a component that is in contact to the substrate. library duplication A parallel design library required for different applications. global connection Connection to signal or supply node not requiring symbol pin. 2/10/05 Virtuoso Analog Design Environment 14-4 Applications of Inherited Connections Use inherited connections to: ■ Defer where a net is attached until a cell that contains that net is used in the design hierarchy. ■ Change the attach point on the fly by changing an instance property. ■ Affect many points down a hierarchy with the change of only one parameter. ■ Provide a programmable net capability. Inherited Connections enhances the link between the physical and logical tool flows. Inherited Connections help to solve: ■ Library Duplication—A cell can be designed with the power supplies left as inherited connections. ■ Substrate Connections—Inherited connections provides a solution that works in both the physical and logical design space. ■ Inherited Terminals—With inherited connections, add extra terminals to the layout views that are not hard coded. Inherited Connections 14-5 Applications of Inherited Connections With inherited connections, the circuit designer has the ability to defer where a net is attached until a cell that contains that net is used in the design hierarchy. The attachment point can be changed on the fly by changing an instance property. Because the capability works hierarchically, there is the ability to affect many points down a hierarchy with the change of only one parameter. The inherited connections concept is to provide a programmable net capability. Inherited connections enhances the link between the physical and logical tool flows. Inherited connections help to solve Library Duplication—A cell can be designed with the power supplies left as inherited connections. In the past, users would have multiple copies of the same cell, with the only difference being the connection of the power supplies. Substrate Connections—Prior to inherited connections, the problem of resolving substrate connections required ingenuity, patience, and a large effort on design resources. Inherited connections provides a unique solution to the problem that is easily incorporated into the design flow. Inherited Terminals—The physical implementation of a cell usually has more terminals than the logical implementation. Inherited connections can add extra terminals to the layout views that are not hard coded. There is no need to search for terminals in a layout and change them. 2/10/05 Virtuoso Analog Design Environment 14-6 Features of Inherited Connections ■ Inherited Connections allow you to create global signals and override their names for selected branches of the design hierarchy. ■ Inherited Connections enable you to: ❏ Use multiple power supplies in a design. ❏ Add overridable substrate connections. ❏ Parameterize power and ground symbols. ■ This override information can be accessed by other Cadence® tools across the design flow. ■ Sample library and tutorial /tools/dfII/samples/tutorials/inhconn ■ You may also access a tutorial and database at http://sourcelink.cadence.com Inherited Connections 14-7 Features of Inherited Connections The inherited connections solution provides a long-needed answer to the problem of multiple power supplies. To implement separate power supplies (analog and digital, for example, or +3V and +5V) in a hierarchical design, assign net expressions to those global signals whose defaults will be overridden, and then use netSet properties to specify the new values of the signals. (Global signals are electrical signals that pass through more than one level of a multilevel design, at the same power level and with the same name.) Net expressions assigned to signal names can be overridden with the specifications of global signals. The netSet properties redefine the value of the property assigned to a signal or terminal. Redefining the signal eliminates the problem of global nets being merged into a single, electrically equivalent signal, which occurs when the signal traverses the design hierarchy. In summary, inherited connections allow global signals to be inherited through a design hierarchy. Override default values by setting netSet properties on instances where a net expression has been assigned to the signal at the level above. In this way, the netSet property values filter down through the hierarchy below that instance. 2/10/05 Virtuoso Analog Design Environment 14-8 Defining Inherited Connections ■ Add a net expression label to either a pin or a wire to define an inherited connection. ■ The net expression defines a default global signal name for the connection and the name of the property overrides the global signal name. Example Net Expression [@power:%:vdd!] Add—Net Expression Property name Default global signal name Example Net Expression Labels [@gnd:%:gnd!] [@vdd:%:vdd!] Symbol pin with a net expression Schematic wire with a net expression ■ The basic library contains sample power and ground symbols. Inherited Connections 14-9 Defining Inherited Connections The default global signal name specifies what the pin or wire is connected to by default. When a net expression is attached to a wire, the default name in the expression names the net. When a net expression is attached to a pin, the default name in the expression names the signal that the pin will be connected to by default. Net expressions associated with symbol pins do not name the pin. The inherited terminal is created when the net expression is associated with the pin in the symbol editor. The schematic extractor processes expressions associated with symbol pins only when the extractor encounters an instance of the symbol in a schematic. Check the schematic, and the Net Expression from the symbol pin is propagated into the schematic. Basic Library Samples The basic library contains sample parameterized power and ground supply symbols called vcc_inherit, vdd_inherit, gnd_inherit, and vss_inherit. Inherited Supply Symbol basic vcc_inherit symbol basic vdd_inherit symbol basic gnd_inherit symbol basic vss_inherit symbol Net Expressions [@vcc:%:vcc!] [@vdd:%:vdd!] [@gnd:%:gnd!] [@vss:%:vss!] 2/10/05 Virtuoso Analog Design Environment 14-10 Setting a Net Expression Select the wire. Add—Net Expression Inherited Connections 14-11 Setting a Net Expression The Default Net Name in a net expression must denote a scalar, global name, such as vdd! or mygnd!. 2/10/05 Virtuoso Analog Design Environment 14-12 Override Default with the netSet Property All override global names must be assigned at the level of hierarchy where used. 3.3V! mygnd! 1 2 Portion of I5 schematic 3.3V! 3 4 Inherited Connections 14-13 Override Default with the netSet Property Override the default Net Expression setting with the netSet property. To add the netSet property: 1. In the schematic window, click on an instance and select Edit — Properties — Objects. The Edit Object Properties form appears. 2. Click the Add button, and fill in the Add Property form as follows: ❑ Set the Type to netSet. ❑ Enter a Name and Value. ❑ OK the form. 3. Set the visibility of the new property in the Edit Object Properties form to both, and OK the form. When using inherited connections, assign all the override global names at each level of the hierarchy, because the net expression evaluator looks up one level for its connections. In this case, the globals used are 3.3V! and mygnd!. The schematic updates and displays the label for your property. Check and Save your schematic for the property to go into effect. 4. Descend into the cell for which you added a netSet property. The new value is displayed. 2/10/05 Virtuoso Analog Design Environment 14-14 Netlisting with Inherited Connections [@p1:%:vdd1!] A Y [@p2:%:vss1!] Cellview A1 Cellview with Inherited Connections When netlisted, two pseudo ports are created, because it has two inherited connections for the supplies. Pport [@p1:%:vdd1!] Pport [@p2:%:vss1!] Rport A Rport = “Real” port Pport = “Pseudo” port Cellview A1 Rport Y Inherited Connections 14-15 Netlisting with Inherited Connections Rport denotes a “real” port, which is a physical pin on the symbol cellview. Pport denotes a “pseudo” port that is created by the netlister. The name of the pseudo port is the net expression of the inherited connection. Below is an example of how the nand3 gate shown in previous slides appears in the Spectre® direct netlist. In this example, all pseudo-ports begin with the inh_ prefix. ... // Library name: InhConn // Cell name: nand3 // View name: cmos_sch // Inherited view list: schematic symbol cmos_sch verilog behavioral subckt nand3 A B C Y inh_n3gnd inh_nsub inh_psub inh_n3vdd M8 (net37 C inh_n3gnd inh_nsub) nmos w=nw l=nl M6 (Y A net34 inh_nsub) nmos w=nw l=nl M7 (net34 B net37 inh_nsub) nmos w=nw l=nl M3 (Y A inh_n3vdd inh_psub) pmos w=pw l=pl M0 (Y C inh_n3vdd inh_psub) pmos w=pw l=pl M4 (Y B inh_n3vdd inh_psub) pmos w=pw l=pl ends nand3 // End of subcircuit definition. ... I5 (net2 net18 CLK net5 mygnd! inh_nsub inh_psub 6) nand3 The I5 statement denotes the instantiation of the nand3 gate in the netlist. 2/10/05 Virtuoso Analog Design Environment 14-16 Evaluating Net Expressions netSet property value = new net name found not found Default net name specified in the net expression No instance found that has a matching property name. Cellview containing the net expression System searches up the hierarchy for a specified property. Note: Place the netSet property on any instances at any level above the cellviews with net expressions. Inherited Connections 14-17 Evaluating Net Expressions Net expressions are evaluated for each hierarchical path. The system uses the property name specified in the net expression to search upward from the cellview containing the net expression (one instance at a time) to the top of the design. The first instance that is found that has a matching property name terminates the search. If the property is of type netSet and is a legal net name, then its value is used as the connecting net rather than the default net name specified in the expression. The netSet property can be placed on any instance and it will affect all net expressions with matching property names at all levels below that instance unless overridden by another netSet property in a lower-level instance. 2/10/05 Virtuoso Analog Design Environment 14-18 Labs Lab 14-1 Inherited Connections Lab 14-2 Using Inherited Connections with the ampTest Design Inherited Connections Labs 14-19 2/10/05 Virtuoso Analog Design Environment 14-20 ® 15 Overview of Parasitic Simulation Module 15 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 15-2 Topics in this Module ■ Background of parasitic simulation ■ Brief overview ■ Design flow ■ Supported layout software ■ Diva and Assura ■ What happens in parasitic simulation ■ An actual parasitic simulation flow ■ Summary Overview of Parasitic Simulation 15-3 Terms and Definitions Terms and Definitions CDF Component Description Format is information stored on a cell that defines parameters, simulation rules, and display information. Selected Parasitic Simulation Selected parasitic simulation limits the nets that are simulated with parasitic information. Source/Loads Components in the schematic that are for simulation purposes only. LVS Layout versus schematic checking is used to verify that the layout matches the schematic. Test Fixture Schematic A schematic containing a symbol representing the design schematic with all required simulation sources and loads attached to I/O pins of the symbol. “LVS-able” block A subblock with a layout and a schematic in the same cell that can be verified with LVS. 2/10/05 Virtuoso Analog Design Environment 15-4 Background In previous chapters, a large amount of time and effort is applied to designing a circuit that realizes specific design goals. During the design phase of the circuit, there was no allowance for the parasitic capacitance and for the resistance of interconnecting the components of the schematic. Such “interconnect parasitics” typically cause a 10 to 20 percent increase in the delay times of a circuit and a corresponding reduction in bandwidth. To ensure the product meets the specific design goals, the following options are available: ■ “Over design” or “guard band” the design by using larger devices and increasing power consumption. ■ Carefully measure and analyze the interconnect parasitics after layout has been completed and resimulate the design. ■ Run a parasitic extraction simulation on the layout and resimulate the design. The first and second options have disadvantages. The first consumes more power and is at risk for not meeting the design goals. The second option is work intensive, and is also at risk for errors to occur. Parasitic extraction requires less time, effort, and is more reliable. Overview of Parasitic Simulation 15-5 Background Most semiconductor devices must be interconnected using conductive materials such as metal, polysilicon, salicided polysilicon, and so on. The conductive interconnect has some resistance. In addition, the conductive material often must traverse over a substrate, or power bus. As such, capacitance exists to a power supply potential. In addition, the interconnect sometimes must cross over other signals, which creates a “point to point” capacitance. As such, a circuit design that has been simulated prior to layout must be significantly altered after layout. Such conditions increase delay and reduce bandwidth. Bandwidth can be increased by increasing the transconductance of the devices in the circuit. However, this requires additional power. As such, using a “guardband” in the design comes at a cost of larger devices, increased power consumption, and risk. The layout of the circuit can be evaluated by carefully measuring the area and the effective number of squares of the interconnect. The measurements can then be converted into parasitic resistors and capacitors elements. These elements can then be added back into the schematic and the circuit simulated again. This methodology requires both time and effort. In addition, this methodology has a high risk of error for large circuits. The layout parasitic extraction simulation with extracted circuit simulation is faster, often more accurate, and generally a more reliable method to verify the physical design. 2/10/05 Virtuoso Analog Design Environment 15-6 Overview of Parasitic Analysis Why Is Parasitic Extraction and Simulation Needed? Original Circuit Design Submitted to Layout Fabricated Circuit, Fails to Operate at Specified Frequency! delay = 1ns Simulation without parasitics delay = 3ns Simulation with parasitics Overview of Parasitic Simulation 15-7 Overview of Parasitic Analysis A circuit design and simulation often includes the device parasitics such as the junction area and sidewall capacitance. To obtain high-frequency performance in a circuit, you simulate the circuit over corners, and use Monte Carlo Analysis and optimization. However, the circuit was designed without knowing the interconnect parasitics. Since the circuit must be captured in layout, the parasitics are unknown until the layout is completed. If the circuit is fabricated without simulating with interconnect parasitics, then the circuit may not operate as expected from the design simulations. In the simulations shown above, a circuit was designed to have a delay less than 1ns. However, the fabricated device failed to operated at the specified maximum frequency. When the fabricated device was simulated using parasitics, the circuit had a significant increase in delay. At high frequency, the interconnect parasitics become more dominate in the overall delay of the circuit. 2/10/05 Virtuoso Analog Design Environment 15-8 Supported Layout Software The Virtuoso Analog Design Environment, version 5.1.41, supports parasitic extraction and simulation for: ■ Assura, which is documented in Module 16. ■ Diva, which is documented in Appendix A Background Prior to IC 4.4.6, only Diva layout extraction and parasitic simulation was supported. ■ Diva is now associated for the layout of small circuits. ■ Assura is now replacing Diva in more and more design flows for large circuits. ■ There is a genuine need for parasitic extraction and simulation tool. Overview of Parasitic Simulation 15-9 Supported Layout Software Parasitic extraction and simulation are supported in the Virtuoso Analog Design Environment using both Diva and Assura. ■ The Assura flow is covered in Module 16 of this class. ■ The Diva flow is covered in Appendix A of this class ■ Only one of the two flows (Diva or Assura) shall be presented in the lecture. ■ Only one of the two flows (Diva or Assura) shall be performed in the lab. ■ The instructor will inform you which flow is used for the lecture and lab. 2/10/05 Virtuoso Analog Design Environment 15-10 What Happens in Parasitic Simulation? extracted layout parasitic “netlist” 3 3 1 design schematic 2 4 test fixture schematic Overview of Parasitic Simulation 15-11 What Happens in Parasitic Simulation? The numbers in the illustration above correspond to the following: 1. Run LVS to make the comparison between the schematic and extracted representations of the design, verifying that the two are logically equivalent. As a result, the system maps equivalent device terminals (pins) in the extracted and schematic views. 2. Create a simulation test fixture schematic that includes a symbol of the design. When running the simulation, the netlist used is actually combined from two sources: a circuit with stimulus and loads, and the parasitic devices. 3. The circuit and parasitic devices that are selected in the schematic come from the extracted netlist. 4. Sources and other components (loads) are used as defined in the top-level test fixture schematic. 2/10/05 Virtuoso Analog Design Environment 15-12 An Actual Parasitic Simulation Flow 1 Create schematic for design 2 Create layout for design 3 Extract & Run LVS on design (or subblocks) 4 Create analog_extracted view of design Backannotate Parasitic Probe optional 5 Create test fixture schematic & configuration 6 Choose views in configuration (Netlist with or without Parasitics) 7 Run Simulation 8 Schematic Waveform Analysis Extracted Waveform Analysis Overview of Parasitic Simulation 15-13 An Actual Parasitic Simulation Flow 1. Start with the schematic for the design. This can be a flat schematic or a hierarchical schematic. The design must be able to run LVS on any portion of the design that will be simulated with parasitics. 2. Create the layout for the design. For any subblock of the design for which the parasitic simulation is run, the hierarchy of the layout must correspond to the hierarchy of the schematic. 3. Extract and run LVS on the portion of the design to simulate with parasitics. 4. Create an analog_extracted view of the parasitic portion of the design. At this point additional parasitic information, using Show Parasitics or Probing, is available for simulation. 5. Create a test fixture that includes a symbol for your design and the appropriate sources and loads to run simulation. Create a config view of the design for use with the Hierarchy Editor. 6. Using the Hierarchy Editor, choose which views will be netlisted for simulation. Simulate with parasitics by choosing analog_extracted for the design or subblocks of the design. For parasitic simulation, the view must be analog_extracted. 7. Run Simulation. The netlist will use parasitic information as specified in your configuration. 8. Any net of the layout or schematic can be selected and then graphically plotted for waveform analysis. 2/10/05 Virtuoso Analog Design Environment 15-14 Summary Topics in this module ■ Background of parasitic simulation ■ Brief overview ■ Design flow ■ Supported layout software ■ Diva and Assura ■ What happens in parasitic simulation ■ An actual parasitic simulation flow Overview of Parasitic Simulation 15-15 Summary This module presented an overview of parasitic simulation and its value. Both the Diva and Assura layout tools are supported in ADE 5.1.41. The parasitic flow was presented. 2/10/05 Virtuoso Analog Design Environment 15-16 Labs Lab 15-1 Simulating a Schematic Without Parasitics Overview of Parasitic Simulation Labs 15-17 2/10/05 Virtuoso Analog Design Environment 15-18 ® 16 Assura Parasitic Simulation Flow Module 16 February 10, 2005 2/10/05 Virtuoso Analog Design Environment 16-2 Topics in this Module ■ Overview and background to Assura parasitic simulation ■ Introduction to Assura ■ Schematic requirements ■ LVS requirements and results ■ Parasitic simulation messages and options ■ Selective parasitic simulation Assura Parasitic Simulation Flow Terms and Definitions Terms and Definitions CDF Selected Parasitic Simulation Source/Loads LVS Test Fixture Schematic “LVS-able” block 16-3 Component Description Format is information stored on a cell that defines parameters, simulation rules, and display information. Selected parasitic simulation limits the nets that are simulated with parasitic information. Components in the schematic that are for simulation purposes only. Layout versus schematic checking is used to verify that the layout matches the schematic. A schematic containing a symbol representing the design schematic with all required simulation sources and loads attached to I/O pins of the symbol. A subblock with a layout and a schematic in the same cell that can be verified with LVS. 2/10/05 Virtuoso Analog Design Environment 16-4 Assura in ADE What is the Assura? ■ Cadence’s next-generation physical verification tool ■ Very similar in concept to Diva ■ Documentation: Chapter 4 of the Virtuoso Parasitic Simulation User Guide Why is it needed? ■ Allows extraction of designs that are too large for Diva to extract in a reasonable amount of time ■ Will support AMS Designer and be the primary extraction tool Assura Parasitic Simulation Flow 16-5 Assura Integration in ADE Customers are creating circuit designs that are too large for Diva to extract in a reasonable time. Assura Physical Verification is a next-generation connectivity extraction tool capable of handling the largest customer circuit designs. Assura RCX integration Integrating Assura into the ADE flow provides improved capacity, performance, and accuracy over Diva. Assura RCX allows the recognition and extraction of parasitic resistance and capacitance for the largest circuit designs with greater speed and accuracy. 2/10/05 Virtuoso Analog Design Environment 16-6 What’s New in Assura 5.1.41 ■ Increased accuracy of resistance backannotation ❏ Calculated from power calculation based on DC simulation ■ Can drive backannotation from schematic ❏ No need to open extracted view ■ Ability to backannotate node voltages out of context ❏ Can annotate voltages in schematic after a simulation ■ Hierarchical extracted view support ■ Do not need Assura in your path ■ Now reports on R, decoupled C, coupled C, L, and K, ■ Provides the option of reporting parasitics on a single Net, Net to Net, Terminal to Terminal, and All Nets Assura Parasitic Simulation Flow 16-7 Accurate resistance backannotation: ■ Previously, resistance values backannotated to schematic nets were simple sums of all parasitic resistors associated with the net. In 5.1.41, the method used is based on measuring power dissipated across the parasitic resistors to return accurate effective values that are more accurate. Note: This power calculation method is based on DC simulation results, and so the flow associated with this feature has changed. The accurate values are reported for backannotation as well as in point to point probing reports. Ability to backannotate node voltages out of context: ■ In past releases, it was not possible to backannotate voltages on a schematic after a simulation of that block as an extracted view. This limitation has been removed in 5.1.41. Hierarchical extracted view support: ■ The MSPS (mixed signal parasitic simulation) flow now supports Assura 3.1.x’s hierarchical extracted view feature. You may use hierarchical extracted views in your designs, taking advantage of the simulation speed improvements when using hierarchical simulators such as UltraSim, while maintaining the ability to probe and backannotate simulation results for these blocks. Parasitic reporting procedures have been expanded and improved upon in this release of MSPS, which now reports on R, decoupled C, coupled C, L, and K, and provides the option of reporting parasitics on a single Net, Net to Net, Terminal to Terminal, and All Nets. 2/10/05 Virtuoso Analog Design Environment 16-8 Assura Flow in Virtuoso Analog Design Environment The ADE flow using Assura is very similar to the current Diva-driven flow, except that, instead of Diva, Assura is used to perform layout connectivity, parasitic extraction, and extracted view creation. ■ Once the av_extracted view has been created, you can access the Parasitics menu to create Refined Views or annotate parasitic information. ■ This menu allows you to specify the library, cell, and view for both the schematic and extracted views. Once these fields are set, you can perform the same functions found in the Diva flow: Backannotate, Refine View (Build Analog). ■ The functionality is the same as the current Diva-based flow; however, the underlying callbacks have been changed to operate on the Assura-generated extracted view. ■ In addition, the av_analog_extracted and av_extracted views resulting from the Refine Extracted View allows configured simulation using different parasitics. Aside from the existence of this new property, the primary difference is that the Assura-generated extracted view will use mapped algorithmically hierarchical schematic names for instances and nets. Assura Parasitic Simulation Flow 16-9 Assura Flow in Virtuoso Analog Design Environment Creating an av_extracted view using “all nets” eliminates the need for an av_analog_extracted view. 2/10/05 Virtuoso Analog Design Environment 16-10 Menu Changes for Assura A “Parasitics” pulldown is available in schematic and av_extracted views. Note: This function was formerly known as Parasitic Probing. ■ Schematic pulldown: Setup, Options, Show/Hide Parasitics, Report Parasitics, Refine Extracted View ■ Layout pulldown: Setup, Options, Report Parasitics, Refine Extracted View Assura Parasitic Simulation Flow 16-11 The mixed signal parasitic simulator is accessible by executing Tools—Parasitics, which adds a Parasitics menu to the Virtuoso Schematic Editor and Virtuoso Layout Editor menu bars. ■ The Mixed Signal Parasitic Simulation form has been replaced by a selection of menu items available under the Parasitics menu banner: ❑ Setup—Lib, Cell, Name, Extracted Cell View ❑ Options—To set options for back annotation, font, size ❑ Show Parasitics—Toggles with Hide Parasitics ❑ Report Parasitics—Select Net, Net-to-Net, Terminal-to-Terminal to show/save. ❑ Refine Extracted View—Builds the Analog Extracted View with none/selected/all nets from the schematic. Note: In previous releases, the Parasitics—Report Parasitics function was known as Parasitic Probing. 2/10/05 Virtuoso Analog Design Environment 16-12 Parasitic Show/Hide within ADE Note: Must be “out of context” for these Annotate options to activate. Assura Parasitic Simulation Flow 16-13 Being out of context is defined as: “Descending into a cellview that is different from the one used in your simulation.” For instance, if you descend into a lower-level block of a schematic that you simulated using an av_analog_extracted view, you will be out of context. 2/10/05 Virtuoso Analog Design Environment 16-14 Accurate Assura Backannotation Values for R are not available until after simulation. Important To obtain r values, you must perform a dc simulation. Assura Parasitic Simulation Flow 16-15 Resistance: All resistors have the value NA (Not Available). In order to provide resistance values, simulation results must be acquired. The only way that you can now get backannotated resistances is from within a config view of a design that has valid dc simulation results. Capacitance: Backannotated capacitance values are prefaced by a Sigma character. This indicates that these values are simple sums. Because most capacitors come out of extraction tools in a parallel configuration, this is often an accurate enough report. Note: This is identical to the way capacitance values were calculated in previous releases. 2/10/05 Virtuoso Analog Design Environment 16-16 Total R Values Not Shown Until After DC Simulation From Schematic View Post Simulation Parasitic Report Report from the av_extracted view Assura Parasitic Simulation Flow Important Values for R are not available unless a valid DC simulation has been performed. 16-17 2/10/05 Virtuoso Analog Design Environment 16-18 Assura Design Flow 1 Create schematic for design 2 Create layout for design 3 Assura 3.1 Run Assura LVS 3.2 Run Assura RCX 4 Parasitics Backannotate Probe 5 Create test fixture schematic & configuration 6 Choose views in configuration (Netlist with or without Parasitics) 7 Run Simulation 8 Schematic Waveform Analysis Extracted Waveform Analysis Assura Parasitic Simulation Flow 16-19 Assura Design Flow 1. Start with the schematic for the design. This can be a flat schematic or a hierarchical schematic. The design must be able to run LVS on any portion of the design that will be simulated with parasitics. 2. From the layout view of the design, select Tools—Assura. For any subblock of the design for which the parasitic simulation runs, the hierarchy of the layout must correspond to the hierarchy of the schematic. 3. In Assura, run LVS and RCX on the portion of the design to be simulated with parasitics. 4. Assura creates an av_extracted view of the parasitic portion of the design. 5. Create a test fixture that includes a symbol for your design and the appropriate sources and loads to run simulation. Create a config view of the design for use with the Hierarchy Editor. 6. Using the Hierarchy Editor, choose which views will be netlisted for simulation. Simulate with parasitics by choosing av_extracted for the design or subblocks of the design. 7. Run the simulation. The netlist will use parasitic information as specified in your configuration. 8. Any net of the layout or schematic can be selected and then graphically plotted for waveform analysis. 2/10/05 Virtuoso Analog Design Environment 16-20 Design Schematic 1 Create schematic for design design schematic inv schematic Assura Parasitic Simulation Flow 16-21 Design Schematic The design schematic can be flat or hierarchical, and cannot have sources or loads in this schematic. It must contain only those elements that will correspond directly to elements in the design layout. If the design schematic is hierarchical, parasitic simulation can be run on specific subblocks of the design if corresponding layout exist for each subblock. Each analog primitive used in the design needs: ■ a symbol view. ■ a schematic view. ■ a layout view and corresponding extraction rules. ■ a simulation model. ■ an auLvs view. ■ auLvs simulation information in the cell CDF. 2/10/05 Virtuoso Analog Design Environment 16-22 Design Layout 2 Create layout for design inv layout design layout Assura Parasitic Simulation Flow 16-23 Design Layout Capture a layout for the design schematic using the Assura Design Tool. The design layout can be flat or hierarchical. 2/10/05 Virtuoso Analog Design Environment 16-24 Accessing the Assura Commands 2 Create layout for design You are here! 3 Assura 3.1 Run Assura LVS 3.2 Run Assura RCX Assura pull-down menu Run LVS... Starts the Assura Run LVS form Run RCX... is enabled only after completing LVS Assura Parasitic Simulation Flow 16-25 Accessing the Assura Commands At this point in the Assura Parasitic Simulation flow, the layout for the design has been captured. You are now ready to begin the extraction process, or Block 3 in the flow. 2/10/05 Virtuoso Analog Design Environment 16-26 LVS in Assura 3 Assura 3.1 Run Assura LVS 3.2 Run Assura RCX Assura—Run LVS... Assura Parasitic Simulation Flow 16-27 LVS in Assura Assura requires the extraction files and schematics to perform the Assura LVS. Select Run LVS from the Assura pulldown menu to perform LVS for the target layout and schematic. When LVS is successful, the Run RCX field will become enabled. 2/10/05 Virtuoso Analog Design Environment 16-28 Run RCX in Assura 3 Assura 3.1 Run Assura LVS 3.2 Run Assura RCX Assura Parasitic Simulation Flow 16-29 Run RCX in Assura The Assura 3.1.3 generated extracted view does not have layout polygons present; it uses the CDBA “group” mechanism to tag the parasitic resistor sub-nets, and a new property “extractionCreatedBy” set to “Assura” is now present to distinguish the Assura generated extracted view from the Diva generated extracted view. Most significantly, the Assura extracted view uses algorithmically mapped hierarchical schematic names. 2/10/05 Virtuoso Analog Design Environment 16-30 Assura RCX Output 3 Assura 3.1 Run Assura LVS 3.2 Run Assura RCX extracted view Run Assura RCX design layout Assura Parasitic Simulation Flow 16-31 Assura RCX Output Running Assura RCX builds an extraction of the layout called av_extracted that has connectivity, designed devices, and parasitic information. This step in the flow requires the layout to be completed, and LVS must be completed successfully. In addition, Assura extraction rules files must also exist. 2/10/05 Virtuoso Analog Design Environment 16-32 Creating av_analog_extracted 4 Parasitics 4.1 Layout/Schematic 4.2 Refine Extracted View av_analog_extracted created Backannotate The Parasitics menu becomes available by executing Tools—Parasitics from the Layout or Schematic window. Probe Parasitics—Refine Extracted View Assura Parasitic Simulation Flow 16-33 Building av_analog_extracted Create the Assura av_analog_extracted view by selecting Parasitics—Refine Extracted View from the Assura pulldown menu. Select the OK once you have set the Extracted Parasitics choice. ■ By default, the analog extracted view is called “av_analog_extracted” ■ The av_analog_extracted view is basically a copy of the av_extracted view ❑ Some or all of the parasitics can be removed ❑ Nets ending with “!” are recognized as global signals 2/10/05 Virtuoso Analog Design Environment 16-34 Create Test Fixture Schematic and Configuration 5 Create test fixture schematic & configuration design schematic test fixture schematic Assura Parasitic Simulation Flow 16-35 Create Test Fixture Schematic and Configuration 1. Create a schematic cellview. ❑ Use a symbol for the design and appropriate sources and loads for simulation. 2. Create a config cellview. ❑ Use the template for the simulator you are using. ❑ Use the test fixture schematic as the top cell. 2/10/05 Virtuoso Analog Design Environment 16-36 Choose Views in Configuration 6 Choose views in configuration (Netlist with or without Parasitics) Netlist without parasitics Netlist with parasitics Assura Parasitic Simulation Flow 16-37 Choose Views in Configuration Choose to use parasitic information for: ■ The entire design. ■ Specific subblocks at any point in the hierarchy of the design. ■ A specific net in a specific subblock. Use the selective simulation components to indicate which net and then use the Hierarchy Editor to choose the subblock view. To set the views for the design: 1. In the Hierarchy Editor, use the “tree” icon to expand the hierarchy. 2. For each block that you wish to simulate with parasitics, set the view to av_analog_extracted (or just to av_extracted if you did the extraction using “all nets”). 3. Click Update and then save the changes. 2/10/05 Virtuoso Analog Design Environment 16-38 Running Simulation 7 Run Simulation 1. Open the configured schematic from the HED. 2. Start ADE from the configured schematic and run the simulation. delay = 1ns delay = 3ns Simulation without parasitics Assura Parasitic Simulation Flow Simulation with parasitics 16-39 Running Simulation To run simulation using the views defined in the configuration, open the design from the config view. When opening a config view, the default is to open the schematic view in a window without actually opening the config view. However, all netlisting is being controlled by the config. For running parasitic simulation, open the config view as well as the schematic view to easily change the configuration views as needed. Important When using the Hierarchy Editor to switch configuration views being fed to the Virtuoso Analog Design Environment, ALWAYS select Netlist and Run from the toolbar or menus. Failing to do this will prevent a new netlist from being created for the selected configuration view. 2/10/05 Virtuoso Analog Design Environment 16-40 Waveform Analysis 8 Schematic Waveform Analysis Extracted Waveform Analysis You can choose waveforms in either the schematic or extracted layout: Assura Parasitic Simulation Flow 16-41 Waveform Analysis In parasitic simulation, the netlist is derived based on the views chosen in the configuration. When descending into an instance from the test fixture schematic, choose from a list of views to descend into. By default, the first view offered will be the one defined for simulation in the configuration. 2/10/05 Virtuoso Analog Design Environment 16-42 Labs Lab 16-1 Parasitic Simulation Flow Lab 16-2 Running a Simulation without Parasitics Lab 16-3 Running Simulation with Parasitics Lab 16-4 Improved Bus Probing Assura Parasitic Simulation Flow Labs 16-43 2/10/05 Virtuoso Analog Design Environment 16-44 ® A Diva Parasitic Simulation Flow Module A February 10, 2005 2/10/05 Virtuoso Analog Design Environment A-2 Topics in this Module ■ Overview ■ Design flow ■ Schematic requirements ■ LVS requirements and results ■ Parasitic simulation messages and options ■ Selective parasitic simulation Diva Parasitic Simulation Flow A-3 Terms and Definitions Terms and Definitions CDF Component Description Format is information stored on a cell that defines parameters, simulation rules, and display information. Selected Parasitic Simulation Selected parasitic simulation limits the nets that are simulated with parasitic information. Source/Loads Components in the schematic that are for simulation purposes only. LVS Layout versus schematic checking is used to verify that the layout matches the schematic. Test Fixture Schematic A schematic containing a symbol representing the design schematic with all required simulation sources and loads attached to I/O pins of the symbol. “LVS-able” block A subblock with a layout and a schematic in the same cell that can be verified with LVS. 2/10/05 Virtuoso Analog Design Environment A-4 Diva Parasitic Extraction The Diva flow for parasitic extraction is also supported by the Virtuoso Analog Design Environment. This module is included for the following reasons: ■ For those facilities where Diva is used and Assura is not installed. ■ For classes at the customer sites where Diva is used. ■ For classes at customer sites where Diva is specifically requested. ■ For special circumstances, such as when the class is presented by an instructor who is not familiar with the Assura tool. All versions of the Virtuoso Analog Design Environment as well as the previous versions of the Analog Artist environment support parasitic simulation using Diva. The Diva and Assura parasitic simulation flows have only minor differences. Diva Parasitic Simulation Flow A-5 Diva Parasitic Extraction The Diva and Assura flows are similar. 2/10/05 Virtuoso Analog Design Environment A-6 Diva Design Flow with Parasitic Simulation 1 Create schematic for design 2 Create layout for design 3 Extract & Run LVS on design (or subblocks) 4 Build analog_extracted view of design Backannotate Parasitic Probe optional 5 Create test fixture schematic & configuration 6 Choose views in configuration (Netlist with or without Parasitics) 7 Run Simulation 8 Schematic Waveform Analysis Extracted Waveform Analysis Diva Parasitic Simulation Flow A-7 Diva Design Flow with Parasitic Simulation 1. Start with the schematic for the design. This can be a flat schematic or a hierarchical schematic. The design must be able to run LVS on any portion of the design that will be simulated with parasitics. 2. Create the layout for the design. For any subblock of the design for which runs the parasitic simulation, the hierarchy of the layout must correspond to the hierarchy of the schematic. 3. Extract and run LVS on the portion of the design to simulate with parasitics. 4. Build an analog_extracted view of the parasitic portion of the design. At this point additional parasitic information, using Backannotation or Parasitic Probing, is available for simulation. 5. Create a test fixture that includes a symbol for your design and the appropriate sources and loads to run simulation. Create a config view of the design for use with the Hierarchy Editor. 6. Using the Hierarchy Editor, choose which views will be netlisted for simulation. Simulate with parasitics by choosing analog_extracted for the design or subblocks of the design. For parasitic simulation, the view must be analog_extracted. 7. Run Simulation. The netlist will use parasitic information as specified in your configuration. 8. Any net of the layout or schematic can be selected and then graphically plotted for waveform analysis. 2/10/05 Virtuoso Analog Design Environment A-8 Design Schematic 1 Create schematic for design design schematic inv schematic Diva Parasitic Simulation Flow A-9 Design Schematic The design schematic can be flat or hierarchical, and cannot have sources or loads in this schematic. It must contain only those elements that will correspond directly to elements in the design layout. If the design schematic is hierarchical, parasitic simulation can be run on specific subblocks of the design if corresponding layout exist for each subblock. Each analog primitive used in the design needs: ■ a symbol view. ■ a schematic view. ■ a layout view and corresponding extraction rules. ■ a simulation model. ■ an auLvs view. ■ auLvs simulation information in the cell CDF. 2/10/05 Virtuoso Analog Design Environment A-10 Design Layout 2 Create layout for design inv layout design layout Diva Parasitic Simulation Flow A-11 Design Layout The design layout can be flat or hierarchical. 2/10/05 Virtuoso Analog Design Environment A-12 Extraction and LVS 3 Extract & Run LVS on design (or subblocks) design schematic extracted design layout LVS inv schematic LVS extracted inv layout Diva Parasitic Simulation Flow A-13 Extraction and LVS Use extraction to build a view of the layout that has connectivity, designed devices, and parasitic information for simulation netlisting. The design must pass LVS with the netlists matching using selective parasitics or waveform selection from the schematic. 1. Extract the layout without parasitic devices. Device extraction must include measurement of any device parameters used in simulation. 2. Run LVS between the schematic and extracted layout to verify the design is correct. 3. Extract the layout including parasitic devices. Parasitic cells require: ❑ symbol and auLvs views. ❑ CDF component parameters for resistance and capacitance. The parameter names must be r and c for the parasitic probing and backannotation commands to work. ❑ CDF simulation information for auLvs. The symbols can have any name but the componentName in the auLvs simulation information must be pcapacitor, presistor, pinductor, or pdiode for the comparison programs to recognize them as parasitic components. Examples can be found in the analogLib library at: /tools/dfII/etc/cdslib/artist 4. Rerun LVS between the schematic and extracted layout with parasitics to establish a mapping between the designs. During LVS with parasitics, information about the parasitics being removed is displayed. This means that the parasitics are removed for the purposes of the LVS netlist comparison. The parasitics are still available for simulation. 2/10/05 Virtuoso Analog Design Environment A-14 Building analog_extracted 4 Build analog_extracted view of design Backannotate Parasitic Probe Do not close the LVS form, but you can iconify it. Bottom of LVS form: Diva Parasitic Simulation Flow A-15 Building analog_extracted Select which parasitics will be used for simulation by defining how the analog_extracted view will be built. ■ enable all will copy all of the parasitics found during extraction to the analog_extracted view. This will result in the greatest accuracy during simulation but also the slowest run time. ■ disable all will copy only the designed devices found during extraction to the analog_extracted view. Choose to use this option to simulate the devices as they were actually built in the layout, using measured device sizes. ■ set from sch selects which parasitics will be copied to the analog_extracted view by placing special symbols on nets in the schematic view. 2/10/05 Virtuoso Analog Design Environment A-16 Selective Parasitic Simulation ■ Nets are identified in the schematic using sbaLib components: Cap to gnd Cap between nets Series resistor ■ Enabled by set from sch button on Build analog_extracted View form all parasitics selected parasitics Diva Parasitic Simulation Flow A-17 Selective Parasitic Simulation In many cases, only the parasitics on a few critical nets are used during simulation. To use selective parasitics, put special components on specific schematic nets to tell the program to keep the parasitics on these nets. This can significantly reduce the time needed to run a parasitic simulation while keeping the critical information. The components are available in a library called sbaLib, or create your own. A single terminal component with the componentName spresistor can be attached to nets to keep parasitic resistors. Note that parasitic resistors are components that have been defined as presistors in the CDF. A presistor component can include capacitance information as well as resistance information. The other sbaLib components are spcapacitor, spcapacitor2, and spinductor. The components spcapacitor and spinductor work just like spresistor, while spcapacitor2 is a two-pin component that tells the program to keep all parasitic capacitors between two specific nets. Find sbaLib in this directory: /tools/dfII/etc/cdslib/artist 2/10/05 Virtuoso Analog Design Environment A-18 Backannotation 4 Build analog_extracted view of design Backannotate Parasitic Probe Diva Parasitic Simulation Flow A-19 Backannotation Parasitic backannotation can be invoked anytime after successfully completing LVS. During extraction, the system determines that parasitic devices exist between pins in the layout. During backannotation, the system sums all the parasitic quantities of parasitic networks between pins in the extracted layout view. It then labels the corresponding wires in the schematic window with the total resistance and capacitance between those points. Backannotation gives instance specific results for hierarchical designs. To see the parasitics for a specific cell, push into it and add the parasitics for that particular instance. Since the information is taken from the extracted view, it is possible for different instances of the same cell to have different parasitics. Caution Backannotation is for documentation purposes only. The resistance and capacitance values that are shown above are lumped values for the entire net. This is useful for finding excessive parasitics on critical signals in the schematic design without being familiar with the physical design. To see the effects of the parasitics on circuit performance, use parasitic simulation. 2/10/05 Virtuoso Analog Design Environment A-20 Parasitic Probing 4 Build analog_extracted view of design Backannotate Parasitic Probe Bottom of LVS form: extracted layout Diva Parasitic Simulation Flow A-21 Parasitic Probing Use parasitic probing to get detailed information about the parasitics. ■ Whole Net reports all of the parasitic elements found on a single net. ■ Point to Point reports all of the parasitic elements found between two points on a net. ■ Net to Net reports all of the parasitic elements found between two nets (typically capacitors). Choose the net in either the schematic or extracted layout, whichever is the current window invoking one of the parasitic probing commands. The net probe is highlighted in that window. Click on an instance in the parasitic probing report form; it is highlighted in the extracted layout. To execute another parasitic probe, close the current report window. 2/10/05 Virtuoso Analog Design Environment A-22 Create Test Fixture Schematic and Configuration 5 Create test fixture schematic & configuration design schematic test fixture schematic Diva Parasitic Simulation Flow A-23 Create Test Fixture Schematic and Configuration 1. Create a schematic cellview, using a symbol for the design and appropriate sources and loads for simulation. 2. Create a config cellview. ❑ Use the template for the simulator you are using. ❑ Use the test fixture schematic as the top cell. 2/10/05 Virtuoso Analog Design Environment A-24 Choose Views in Configuration 6 Choose views in configuration (Netlist with or without Parasitics) Diva Parasitic Simulation Flow A-25 Choose Views in Configuration Choose to use parasitic information for: ■ The entire design. ■ Specific subblocks at any point in the hierarchy of the design. ■ A specific net in a specific subblock. Use the selective simulation components to indicate which net and then use the Hierarchy Editor to choose the subblock view. To set the views for the design: 1. In the Hierarchy Editor, use the “tree” icon to expand the hierarchy. 2. For each block that you wish to simulate with parasitics, set the view to analog_extracted. 3. Click Update and then save the changes. 2/10/05 Virtuoso Analog Design Environment A-26 Running Simulation 7 Run Simulation 1. Open config view of test fixture. 2. Run simulation from the configured schematic view. delay = 1ns delay = 3ns Simulation without parasitics Diva Parasitic Simulation Flow Simulation with parasitics A-27 Running Simulation To run a simulation using the views defined in the configuration, open the design from the config view. When opening a config view, the default is to open the schematic view in a window without actually opening the config view. However, all netlisting is being controlled by the config. For running parasitic simulation, open the config view as well as the schematic view to easily change the configuration views as needed. Start simulation from the schematic window. Also, start simulation from the CIW, selecting Tools—Mixed Signal Environment—Simulation. 2/10/05 Virtuoso Analog Design Environment A-28 Waveform Analysis 8 Schematic Waveform Analysis Extracted Waveform Analysis You can choose waveforms in either the schematic or extracted layout: Diva Parasitic Simulation Flow A-29 Waveform Analysis In parasitic simulation, the netlist is derived based on the views chosen in the configuration. When descending into an instance from the test fixture schematic, choose from a list of views to descend into. By default, the first view offered will be the one defined for simulation in the configuration. 2/10/05 Virtuoso Analog Design Environment A-30 Layout Waveform Analysis 8 Schematic Waveform Analysis Extracted Waveform Analysis Probed net in extracted view yields waveform. poly1 shape not probed Probe pins or nets in the extracted layout: Choose pins or layer shapes for which parasitic devices were not extracted. Diva Parasitic Simulation Flow A-31 Layout Waveform Analysis Because the parasitic simulation is usually derived from an analog_extracted view, this is typically the first view offered when descending into an instance to probe for waveform information. This view is often conceptually easier to use for designers familiar with the physical layout. The simulation netlist is mostly generated from the physical layout so points in the extracted layout view map directly to the final simulation netlist. Nodes in the extracted layout represent nodes in the final simulation netlist. Probe only points that have corresponding net or pin information in the simulation netlist. If extracted resistances exist, the shapes that were converted to resistor networks no longer have any connectivity information associated with them. These shapes will not yield any waveform information. Probe pins or vias attached to these shapes. In this design, resistance was extracted for shapes on layer poly1, so those shapes cannot be probed. Probe shapes on layers metal1, ndiff or pdiff because resistance was not extracted for those shapes. 2/10/05 Virtuoso Analog Design Environment A-32 Schematic Waveform Analysis 8 Schematic Waveform Analysis Extracted Waveform Analysis Use the schematic as a representation of the final netlist: + Pin1 Pin2 Click on a wire close to a terminal (not on the terminal) An X in the schematic indicates the corresponding node probed in the final netlist: + Pin1 Pin2 Node referenced in the final simulation netlist: Diva Parasitic Simulation Flow A-33 Schematic Waveform Analysis In parasitic simulation, the netlist is mostly derived from the extracted layout view, but can use the schematic window to probe nodes in the final netlist. For designers not familiar with the physical layout, it is often more relevant to simulate a parasitic netlist and probe in the schematic window, rather than trying to find and probe signals in an unfamiliar layout. In this case, when descending, choose the schematic view instead of the analog_extracted view. When probing in a hierarchical design, probe at any level, as long as the probe is very close to a pin that has a corresponding pin in the extracted layout. In the schematic, probe on wires very close to terminals of devices which have corresponding pins in the extracted layout. An “X” appears on the terminal of the device attached to that net in the schematic. The net also highlights as it would for analysis without parasitic devices. To observe the effect of parasitic devices on a signal across a net, choose another point on the same net close to a terminal of another device. The new device must also have a corresponding pin in the extracted layout. To probe a pin that has a corresponding pin in the extracted layout, descend to lower levels of hierarchy. When plotting the selected signals using commands in the simulation environment window, waveforms are displayed for the corresponding nodes in the final simulation netlist. Any differences in signals probed at either end of a net in the schematic are attributable to parasitic devices inserted in the final simulation netlist. 2/10/05 Virtuoso Analog Design Environment A-34 Labs Lab A-1 Simulating a Schematic with Parasitics Using the Diva Layout Flow Diva Parasitic Simulation Flow Labs A-35 2/10/05 Virtuoso Analog Design Environment A-36 ® B Match Analysis, dcmatch Module B February 10, 2005 2/10/05 Virtuoso Analog Design Environment B-2 Topics in this Module ■ Special modeling requirements ■ Introduction to device mismatch ■ Effects of device mismatch on analog circuits ■ Design considerations ■ Layout matching ■ dcmatch analysis flow Match Analysis, dcmatch B-3 Terms and Definitions Terms and Definitions device mismatch offset error input offset common centroid implant shadowing DNL INL ADC DAC dcmatch A physical limitation, no two devices have identical electrical properties. Mismatch error that requires additional voltage or current to correct. Mismatch error measured at the inputs of opamps and comparators. A geometric layout technique to reduce errors from process gradients. In fabrication, mask layer forms a shadow to an angled ion beam. Differential non-linearity, error between steps in ADCs and DACs. Integral non-linearity. Total error across all codes in ADCs and DACs Analog-to-Digital converter, processes an analog input to digital codes. Digital-to-Analog converter, processes digital codes to an analog output. A type of analysis to evaluate the effects of using matched devices. 2/10/05 Virtuoso Analog Design Environment B-4 Overview of Device Mismatch ■ Two devices “replicated” on the same chip are never identical. To some degree, differences in the electrical properties of the two devices always occurs. ■ In a large array of devices replicated on the same chip, no device is identical to any of the other device. Again, the electrical properties will be different. ■ Mismatches are produced by random processes, and produce the following effects: ❏ Undesired effects in analog circuits. ❏ Offset errors in comparators and amplifiers ❏ Voltage distributions in band-gap reference ❏ DNL and INL in DACs and ADCs. ■ In simulation, devices are often modeled using identical numerical values and expressions for the electrical behavior. ■ Simulations often fail to include the effects of mismatch. ■ Precise values of mismatch cannot be predicted. ■ Statistical methods are used to analyze mismatch. Match Analysis, dcmatch B-5 Overview of Device Mismatch Random effects during fabrication produce distributions in the physical structures and electrical properties of electronic devices. Some of these random processes include lattice defects, surface defects, optical errors, mechanical vibrations, edge effects, and localized impurities. As such, the device parameters or electrical properties of replicated components are not identical. Mismatched devices produce numerous undesirable effects in analog circuits. Mismatch contributes to input offset on operational amplifiers and comparators. The mismatch also reduces CMRR. In many band-gap circuits, the mismatch produces a large distribution in output voltage. In DACs and ADCs, the mismatch produces DNL and INL errors. Circuit simulators use device models to describe electrical behavior. The models use equations and often have identical numerical values for replicated devices. Often the simulation results do not show the effects of device mismatches because the mismatch was never modeled. 2/10/05 Virtuoso Analog Design Environment B-6 Design Considerations Numerous factors either increase or reduce mismatch errors. These include: ■ Layout dimensions (width and length) ■ Matched physical layout ■ Orientation (rotation, mirror image, misalignment, etc.) ■ Spatial separation (distance between replicated devices) ■ Proximity effects (how close are other unrelated devices) ■ Common centroid techniques (1 and 2 dimensional arrays) ■ Dummy devices ■ Contact resistance ■ Package stress and “edge effects” Important These effects shall also influence the model extraction for the mismatch analysis. Match Analysis, dcmatch B-7 Design Considerations Many design considerations influence device mismatch. Many of the considerations involve the device geometries. Capacitors, resistors and transistors are produced by a series of geometric shapes. Any inconsistencies in duplicating these shapes contributes to device mismatches. The width and length of capacitors, resistors, and transistors are altered by these replication errors. A geometric replication error has a mean and variance. A small design length is proportionally more sensitive to such an error than a larger design length, (Lerror/L). By increasing the width and length, the error on W/L or L/W ratios become proportionally smaller and the W/L ratios become more accurate. Where device matching is required, it is important to actually match the device geometries. Such devices should not be rotated or misaligned. The use of a “mirror layout” between two devices will sometimes improve the matching. However, a mirror layout is sensitive to processes with “implant shadowing.” If you are not certain if implant shadowing occurs in the process, avoid mirror devices where matching is required. The devices should also see the same geometric conditions in all directions. For this reason dummy devices are often where critical matching is needed. Fabrication often produces process gradients across the chip. A process gradient is a condition where model parameters tend to increase or decrease in a specific direction. To reduce the device mismatches due to process gradients, the spatial distances between matched devices should be small. Another design technique used to reduce the effects of gradients is called common centroid. Common centroid is a geometric arrangement where each of the “matched devices” comprises an array of components. The array is then used so that the gradients have equal and opposite effects on the components. Common centroid reduces mismatch for first order gradients. For second order gradients the common centroid design shall increase the mismatch. Important These factors influence the model extraction for mismatch analysis. All of these factors should be properly modeled if used where device matching is needed. 2/10/05 Virtuoso Analog Design Environment B-8 Layout Matching Match Analysis, dcmatch Matched W and L Matched layout Matched orientation Aligned in Y Matched W and L Matched layout Mirror orientation! Aligned in Y Matched W and L Matched layout Rotated orientation! Matched W and L Matched layout Matched orientation Misalignment X and Y! Matched W and L Unmatched layout! Matched orientation Aligned in Y DU 1300 ohms 1B Gradient 1200 ohms 2B 1100 ohms 2A 1000 ohms 1A DL The 1-Dimensional Array Common Centroid Design The 2-Dimensional Array DU DU 3B 4B 1B 2B 2A 1A 4A 3A DL DL B-9 Layout Matching The diagram shows both the matched and the unmatched layout examples. For best modeling of device mismatch, each example should have a corresponding mismatch model. The 1-dimensional common centroid shows values for the resistor elements and the proper sequence for adding the elements. In this example, a vertical process gradient occurs in the sheet resistance. In this example: R1 = R1A + R1B = 1000 ohms + 1300 ohms = 2300 ohms R2 = R2A + R2B = 1100 ohms + 1200 ohms = 2300 ohms The 2-dimensional common centroid has process gradients of sheet resistance in both x and y directions. Each resistor element in the increasing x direction is 100 ohms smaller. Each resistor element in the increasing y direction is 100 ohms larger. R1 = R1A + R1B = 1.0K + 1.2K = 2.2K R2 = R2A + R2B = 1.1K + 1.1K = 2.2K R3 = R3A + R3B = 0.9K + 1.3K = 2.2K R4 = R4A + R4B = 1.0K + 1.2K = 2.2K Important Common Centroid is used in DACs and ADCs to reduce INL or integral non-linearity error. In the case of current sources comprising MOS transistors, the 2-dimensional sequence shown is also used. 2/10/05 Virtuoso Analog Design Environment B-10 Special Modeling Requirements for dcmatch The dcmatch analysis has been added to the Choosing Analysis form. It is important to know that this new analysis has special model requirements. The dcmatch analysis works with bsim3v3, bsim4, res, vbic. The lab activity for this module uses bsim3v3. You will be instructed to view the model file. The mismatch model parameters shown have been extracted for a specified process. The model extraction for these parameters is unique to that process only. The dcmatch parameters are unique to a specific process. To work properly, the dcmatch model parameters must be properly extracted for the process used. When this manual was written very few fabrication facilities supported extraction of these model parameters. In addition to the statistical properties of the fabrication facility, the geometric conditions discussed must be included with the model extraction. Using different geometric conditions shall alter NMOS and PMOS mismatch model parameters. Match Analysis, dcmatch B-11 Special Modeling Requirements for dcmatch Special consideration must be used when dcmatch analysis: ■ The use of dcmatch analysis requires special models. ■ The model parameters must be properly extracted. ■ The model parameters are unique to a specific foundry. ■ The model parameters are geometry dependent. 2/10/05 Virtuoso Analog Design Environment B-12 Starting the dcmatch Analysis From the simulation window, select: Analyses—Choose... The Choosing Analyses form appears. In the form select dcmatch. 1. Select this button! 2. The form changes to allow input of dcmatch information. 3. Use these buttons to select nodes on the schematic. 4. For a dc sweep select one of these buttons. Match Analysis, dcmatch Starting the dcmatch Analysis B-13 2/10/05 Virtuoso Analog Design Environment B-14 dcmatch Analysis Selection Select OK or Apply in the Choosing Analysis form. Then verify the dcmatch analysis appears in the Analyses field of the simulation window. Match Analysis, dcmatch dcmatch Analysis Selection B-15 2/10/05 Virtuoso Analog Design Environment B-16 Labs Lab B-1 dcmatch Match Analysis, dcmatch Labs B-17 2/10/05 Virtuoso Analog Design Environment B-18 ® C Advanced Topics in ADE Module C February 10, 2005 2/10/05 Virtuoso Analog Design Environment C-2 Topics in this Module ■ Overview of advanced topics ■ Introduction to Verilog-A ■ Introduction to the Mixed Signal Design Environment Advanced Topics in ADE C-3 Terms and Definitions Terms and Definitions Verilog-A veriloga Modelwriter MSDE IPC An HDL language used for describing analog behavior or structure. View name for a netlistable module written Verilog-A. A Cadence tool for generating Verilog-A code for selected modules. Mixed Signal Design Environment. Inter Process Communication, a special program used in MSDE. 2/10/05 Virtuoso Analog Design Environment C-4 Overview of Advanced Topics This optional module provides instruction on the advanced features of the Virtuoso Analog Design Environment. The covered topics include: ■ Introduction to Verilog-A ■ Introduction to Mixed Signal Design Environment Note that the Virtuoso Analog Design Environment is a gateway to using Verilog-A and the Mixed Signal Design Environment. ■ Classes are provided by Cadence Education Services. Advanced Topics in ADE C-5 Overview of Advanced Topics The Virtuoso Analog Design Environment is a gateway to using other Cadence design tools. These other tools and advanced features of the Virtuoso Analog Design Environment are discussed in this special module. Completion of this module is not required. 2/10/05 Virtuoso Analog Design Environment C-6 Introduction to Verilog-A The Verilog®-A Language ■ Is an extension of the Verilog language (with many HDL constructs from the Verilog language) used to describe analog/mixed signal models, and is an Open Verilog International (OVI) standard. ■ Is a multidiscipline language that models electrical, mechanical, fluid dynamic, and thermodynamic systems. ■ Is used with the Virtuoso Spectre Circuit Simulator in the Virtuoso Analog Design Environment, in the Analog Workbench (AWB), AMS Designer, or in a standalone mode. ■ Supported simulators in the Virtuoso Analog Design Environment: ❏ Spectre—known as Spectre Direct simulator ❏ Spectre Verilog—mixed Spectre Direct and Verilog-XL simulators ❏ Spectre S—socketed Spectre simulator ❏ Spectre S Verilog—socketed Spectre and Verilog-XL simulators ■ Supports top-down design ❏ Easy to learn and use ❏ Easy to transition from abstract to detailed models Advanced Topics in ADE C-7 Introduction to Verilog-A The Verilog-A software is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. Verilog-A is extremely useful in: ■ Defining a system architecture. ■ Verifying the feasibility of a system design. ■ Developing interface specifications, and completing chip level simulations. In addition, Verilog-A simplifies the design process in a front to back design flow. Verilog-A can describe a wide range of conservative systems and signal-flow systems, such as electrical, mechanical, fluid dynamic, and thermodynamic systems. Cadence provides numerous models in all these disciplines that can be used as a starting point for specific model applications. For consistency, Verilog-A uses many constructs found in the Verilog and C programming languages. These languages use modules, which are the fundamental user-defined primitives. To describe a system, specify both the structure of the system and the behavior of its components at different levels. At the highest level, use Verilog-A to define the overall system as a structural model. At lower levels, use Verilog-A to define the internal modules as structural or behavioral models, thus defining the interconnections among submodules. 2/10/05 Virtuoso Analog Design Environment C-8 The Verilog-A Module A code example of a behavioral Verilog-A module Include natures, disciplines, & constants Interface Declarations `include "constants.h" `include "disciplines.h" module res1(p, n); inout p, n; electrical p, n; parameter real r=1 from (0:inf); parameter real tc=1.5m from [0:3m); Module Scope Behavioral Description real reff; analog begin @(initial_step) begin reff = r*(1+tc*$temperature); end I(p, n) <+ V(p, n)/reff ; end endmodule Advanced Topics in ADE C-9 The Verilog-A Module A Verilog-A module is a text file that is accessible as a veriloga view of a cell from the Library Manager tool. The text file comprises lines of code using the Verilog-A language syntax. This text file has `include statements that access the constants.h and the disciplines.h files, which are required for all behavioral modules. In addition this text file includes interface declarations and a module scope. To use the veriloga view for a simulation, just create a corresponding symbol view and and instantiate that symbol view into a schematic. 2/10/05 Virtuoso Analog Design Environment C-10 Advantages of Verilog-A ■ Verilog-A is a behavioral language that simulates faster than structural. ■ Can be used to simulate almost anything in Spectre, including: ❏ Mechanical structures ❏ Fluid dynamic systems ❏ Thermodynamic ❏ Magnetic and electromagnetic structures ■ Verilog-A is a modeling language that is easy to learn. Cadence Educational Services provides both classroom and internet training. ■ Verilog-A modules are very easy to use. ■ Extensive Library support /tools/dfII/samples/artist/ahdlLib /tools/dfII/samples/artist/rfLib /tools/dfII/samples/artist/spectreHDL/Verilog-A The libraries contain hundreds of samples of predesigned Verilog-A modules for common circuit structures. ■ Development tools include Modelwriter and AHDL Debugger Advanced Topics in ADE C-11 Advantages of Verilog-A Verilog-A simulates must faster than circuit structures because behavioral descriptions are used. Behavior reduces the size of the solution matrix and the number of iterations to solve the solution matrix. Verilog-A is a multidiscipline language. It can be used to solve electrical circuits, as well as mechanical, thermodynamic, magnetic and fluid dynamic problems. Almost anything can be simulated using Verilog-A and the Spectre Circuit Simulator. Verilog-A is very easy to use. The Modelwriter tool will write models for preselected circuits. These Verilog-A models are automatically written with assigned ports and with user-specified parameters. Cadence Educational Services provides both public and private classroom instruction in Analog Modeling with Verilog-A. The classroom course is taught in two just days. Topics include writing Verilog-A modules, capturing a system hierarchy, system modeling, and running simulations. The class also covers language syntax, model disciplines, formatting output, and filtering signals. A lab activity is included in each module. The course is also available using the Cadence Internet Learning Series (iLS). This class covers the same topics presented in the classroom. There are also downloadable lab activities. The iLS class offers the advantage of “Anytime - Anywhere” learning. Once you obtain an iLS account, you can use the internet and browser of your choice to access the class material. 2/10/05 Virtuoso Analog Design Environment C-12 Introduction to Mixed Signal Design Environment Mixed Signal Design Environment Analog Design Environment Spectre Circuit Simulator IPC Verilog-XL Logic Simulator (LDV) Simulation Output Database The above diagram shows a conceptual overview of the Mixed Signal Design Environment. MSDE is actually a software extension of the Virtuoso Analog Design Environment. When LDV is installed along with a valid LDV license file, then the MSDE extension of Virtuoso Analog Design Environment is enabled. Advanced Topics in ADE C-13 Introduction to Mixed Signal Design Environment The Mixed Signal Design Environment combines the Spectre Circuit Simulator with the Verilog-XL simulator from LDV. The mixed signal environment also provides an Inter Process Control to interrupt the Spectre Circuit Simulator whenever digital events need to be processed in the Verilog-XL simulation. MSDE is a true mixed-signal simulation environment. The two simulators operate together passing the needed analog and digital data back and forth. Each simulator operates within its specific domain. When signals connect from analog to the digital domain, or from digital to analog domain, then interfaces element do the signal conversion between the domains. 2/10/05 Virtuoso Analog Design Environment C-14 Advantages of Mixed Signal Design Environment 1. True mixed signal simulation and waveforms. 2. Mixed Signal Parasitic Simulation. 3. Backannotation. 4. Works with Verilog-A. Advanced Topics in ADE Advantages of Mixed Signal Design Environment C-15 2/10/05 Virtuoso Analog Design Environment C-16 Mixed Signal Design Environment and Verilog-A Analog Design Environment (IC) Design Verilog HDL Schematic Spectre Verilog-A Netlist Netlist Verilog-A & SpectreHDL Behavioral Models Behavior IPC Verilog-XL (LDV) Spectre Circuit Simulator (IC) Spectre/ SPICE Primitives Advanced Topics in ADE C-17 Mixed Signal Design Environment and Verilog-A The Mixed Signal Design Environment is compatible with Verilog-A. The diagram above shows a conceptual overview of how netlisting is realized. The above diagram is also used to conceptualize a design flow using the Virtuoso Analog Design Environment, the Mixed Signal Design Environment, and Verilog-A. 2/10/05 Virtuoso Analog Design Environment C-18 Labs Lab C-1 Verilog-A Overview Advanced Topics in ADE Labs C-19 2/10/05 Virtuoso Analog Design Environment C-20
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$(function(){ var appid = $(".select li a").data("channel"); $(".select li a").click(function(){ var appid = $(this).data("channel"); $('.select dt').html($(this).html()); $('#channel').val(appid); }) })