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    数模混仿例子,8bit DA转换

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    ECE 128 – VerilogA Lab: Creating & simulating an 8-bit D-A Converter (DAC) Adapted for GWU by: Thomas Farmer Objectives: • To create a sample 8-bit DAC in VerilogA for use with 8-bit CPU Project • Simulate an 8-bit DAC using SpectreVerilog • Use verilog to drive a mixed signal simulation Assumptions: • Student has successfully completed ECE 128 Lab 8 VerilogA ADC. Note: • This tutorial was created using Cadence 5.41, but it has been tested and works properly in Cadence 6.1. There are some basic menu differences, but if a student is familiar with Cadence 6.1, this should be no problem for the student. SECTION I: Creating the DAC 1. Log into a Sun Workstation. 2. Start Cadence by typing these commands: $ cd cadence $ virtuoso & 3. In the library created for the ADC: Create a new “verilogA” cell entitled: ece128_lab_8 dac_8bit 4. When the emacs editor opens, delete the existing lines of text and copy & paste this code for an 8-bit DAC converter below: // FUNCTION: Digital to Analog Converter // VERSION: $Revision: 2.8 $ // AUTHOR: Cadence Design Systems, Inc. // // GENERATED BY: Cadence Modelwriter 2.31 // ON: Fri Mar 07 09:43:02 EST 2008 // // Description: Ideal Digital to Analog Converter // // This model is an example, provided "as is" without express or // implied warranty and with no claim as to its suitability for // any purpose. // // PARAMETERS: // slack = Smallest time unit considered negligible for clock // threshold cross event [S] // tconv = Delay from clock edge to new output voltage [S] // tfall = Output fall time for new output voltage [S] // trise = Output rise time for new output voltage [S] // vmax = Full scale analog output voltage [V] // vmin = Zero scale analog output voltage [V] // vth = Digital Input and Clock Logic Threshold [V] // `include "discipline.h" `include "constants.h" `define NUM_DAC_BITS 8 module dac_8bit (clk, data, vout); input [`NUM_DAC_BITS-1:0] data; electrical [`NUM_DAC_BITS-1:0] data; input clk; electrical clk; output vout; electrical vout; parameter real vmax = 5; parameter real vmin = 0; parameter real vth = 2.5; parameter real trise = 0.1n from (0:inf); parameter real tfall = 0.1n from (0:inf); parameter real tconv = 0.1n from [0:inf); parameter real slack = 0.1n from (0:inf); parameter integer traceflag = 1; real lsb, voffset, new_vout; integer decimal_value; analog begin @(initial_step or initial_step("dc","ac","tran","xf")) begin voffset = vmin; decimal_value = 0; lsb = (vmax - vmin) / (1 << `NUM_DAC_BITS) ; if (traceflag) begin $display("%M DAC range ( %g v ) / %d bits = lsb %g volts.\n", vmax - vmin, `NUM_DAC_BITS, lsb ); $display(" offset %g volts.\n", voffset ); end end @(cross ( V(clk)-vth, 1, slack, clk.potential.abstol)) begin decimal_value=0; generate i (`NUM_DAC_BITS-1, 0) begin decimal_value = decimal_value + (( V(data[i]) > vth ) ? 1 << i : 0 ); end new_vout = decimal_value * lsb + voffset; if(traceflag) $strobe("%M at %g sec. digital in: %d vout: %g", $abstime, decimal_value, (decimal_value * lsb) + voffset ); end V(vout) <+ transition ( new_vout, tconv, trise, tfall ); end endmodule `undef NUM_DAC_BITS 5. You will be prompted to create a symbol for this device, answer yes and save the symbol. SECTION II: Creating the DAC Verilog Driver The DAC requires digital input. Instead of 8 analog pulses, we can use verilog to create the test digital input signal for a DAC. We will create a digital driver for our DAC using verilog. 1. Create a new cell entitled: dac_8bit_driver, use the View Name: functional Tool: Verilog-Editor (NOT verilogA) 2. When the editor comes up, type in the following verilog test bench behavioral code: //Verilog HDL for "ece128_lab8", "dac_8bit_driver" "verilog" `timescale 10ns/1ns module dac_8bit_tb_driver ( data ); output [7:0] data; reg [7:0] data; initial begin data = 8'b00000000; #400 $finish; end always #5 data = data + 1'b1; endmodule 3. Understand the following statement: `timescale 10ns/1ns This statement indicates the amount of time # statement will represent. As an example: #1 variable = 1’b0; The #1 will be worth 10 nanoseconds. So for the above statement: always #5 data = data + 1'b1; The value of “data” will change every: 5 x 10ns or 50ns. The second portion of the timescale directive: / 1ns, indicates the level of precision we wish the simulator to store information. So the precision on a simvision waveform graph will be in segments of 1ns per tic mark 4. Total Simulation Time: In the verilog code the line: #400 $finish; Indicates that the simulation will require: 400 x 10ns or 4us to complete. Note: you will be required to alter the value of the timescale directive above later on in this lab. 5. Save and close the editor, view any errors or warnings, and allow symbol to be generated from your code. a. Note: you may see an ncvlog warning regarding hdl.var, this can be safely ignored b. Notice that the “NC Verilog” compiler is used, so far in this course we’ve used VerilogXL. SECTION III: Creating the DAC Test Bench 1. Create a new cell entitled: dac_8bit_tb, and create the following schematic: a. Instance your verilog driver, veriloga DAC, a vpulse, and a resistor b. Use a wide wire for the bus c. Label the bus wire as we did for the ADC 2. Save the schematic and close it after you have set it up, there should be no warnings SECTION IV: Configuring the Hierarchy To simulate our DAC with the driver, we need to setup a mixed-signal simulation using the cadence 'hierarchy editor.' 1. Create a new cell view called "dac_8bit_tb" View Name "config" Tool "Hierarchy-Editor" 2. From the New Configuration Window: a. Click the “Use Template…” button, choose: spectreVerilog b. When returned to the New Configuration Window, set: i. View = schematic (this is case sensitive) ii. Library List: ece128_lab8 3. Ensure all the views listed in the cell bindings exist in your design. a. From the menu choose View->Update b. Save and exit the hierarchy editor SECTION IV: Simulating the DAC 1. Open the “config” view for the dac_8bit_tb in the library manager. 2. Choose to open both the schematic and the hierarchy configuration: • If things worked properly, when you open the “config” view, both the hierarchy editor will appear AND the amp’s schematic will open at the same time, this is essential. 3. Launch-ADE L Simulator, change the simulator to spectreVerilog: 4. Click OK. Once the simulator has changed over to spectreVerilog, keep the simulation window open, but return to the schematic window. From the schematic window select: Verimix->Interface Elements->Library a. Change the Model IO to: input b. Set the a2d_tx to 1p c. Set a2d_v0 to 2.45 d. Set a2d-v1 to 2.5 e. Change the Model IO to: output f. Set the parameters as shown below: • That window allowed us to specify the delay, & threshold voltage for logic 1 and 0 for the A to D conversion. 5. Back in the ADE Simulator Setup window, setup a transient simulation for 4u s. a. Notice this time MUST be the same amount of time as specified by your verilog test bench. If you change the value of the `timescale, you must change this value as well. b. And you must set the $finish directive to end at the same time as the transient simulation 6. Copy the variables from the cell view a. It is up to you to determine an appropriate clock cycle time for the clock variables. This depends upon the `timescale directive in your verilog test bench. b. You must set these values before you can perform a simulation or move on in the lab 7. Choose to plot the signals: VOUT, CLK, DATA <7:0> When you get all the variables configured appropriately you should be able to see the following plot: Notice the 2nd waveform (that's vout), it the output of the D2A converter. It is just the upward slope of a sine wave. 8. Homework a. Alter dac_8bit_driver to give the stimulus necessary to show the downward slope of a sine wave. b. Hand in a picture of your simulation once the sine wave is achieved c. Also, find the fastest clock speed that this DAC can be run at (shrinking the clock pulse, see if proper data output is still on the vout line) d. Challenge: What is the fastest & slowest common clock speed that both the ADC (from the ADC portion of this lab), and the DAC can successfully operate at. You do not have to put the two together (unless you’d like to try that). But find the common speed so you can have these two components ready for integration with your CPU and its common clock speed. Hand in spectre graphed output for each. SECTION V: Observations This lab is important for various reasons. This is the first Cadence simulation you have performed where a verilog test bench (the ‘driver’) ran the simulation. A clock pulse was used, but the main driver was your verilog code. This will be a critical feature for integration with your CPU project. You will use a “driver,” similar to the verilog test bench file: cpu_test.v, to load memory, and ultimately direct the CPU (via memory instructions) to sample and output data from your sensors. SECTION VI: References This tutorial was adapted from the “Cadence Mixed-Signal Tutorial” from the electrical and computer engineering department of Southern Illinois University. Originally found at the following URL: http://www.ee.siue.edu/~cdsadmin/tutorials/cadence_mixed-signal/ams_tutorial.html

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