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    英文STM32F101xx, STM32F102xx、STM32F103xx、STM32F105xx 和STM32F107xx

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    RM0008 Reference manual STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced ARM®-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as STM32F10xxx throughout the document, unless otherwise specified. The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx connectivity line datasheet. For information on programming, erasing and protection of the internal Flash memory please refer to: • PM0075, the Flash programming manual for low-, medium- high-density and connectivity line STM32F10xxx devices • PM0068, the Flash programming manual for XL-density STM32F10xxx devices. For information on the ARM® Cortex®-M3 core, please refer to the STM32F10xxx Cortex®M3 programming manual (PM0056). Related documents Available from www.st.com: • STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx/STM32F107xx and datasheets • STM32F10xxx Cortex®-M3 programming manual (PM0056) • STM32F10xxx Flash programming manual (PM0075) • STM32F10xxx XL-density Flash programming manual (PM0068) June 2014 DocID13902 Rev 15 1/1128 www.st.com RM0008 Contents Contents 1 Overview of the manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.1 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.3.2 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 CRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.1 CRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4.4 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.1.1 Independent A/D and D/A converter supply and reference voltage . . . . 68 5.1.2 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.2.1 Power on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 70 DocID13902 Rev 15 2/1128 26 Contents RM0008 5.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3.6 Auto-wakeup (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . . 77 5.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 79 5.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6 Backup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1 BKP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.2 BKP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3 BKP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.1 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.2 RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4 BKP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) . . . . . . . . . . . . . . . . . . . 83 6.4.2 RTC clock calibration register (BKP_RTCCR) . . . . . . . . . . . . . . . . . . . . 83 6.4.3 Backup control register (BKP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.4 Backup control/status register (BKP_CSR) . . . . . . . . . . . . . . . . . . . . . . 84 6.4.5 BKP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7 Low-, medium-, high- and XL-density reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3/1128 DocID13902 Rev 15 RM0008 Contents 7.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 101 7.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 106 7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 109 7.3.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 111 7.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 112 7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 115 7.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 118 7.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.3.11 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8 Connectivity line devices: reset and clock control (RCC) . . . . . . . . . 123 8.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.2.3 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 8.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 DocID13902 Rev 15 4/1128 26 Contents RM0008 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 134 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 141 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 142 AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . 145 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 146 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 148 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 150 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 AHB peripheral clock reset register (RCC_AHBRSTR) . . . . . . . . . . . . 153 Clock configuration register2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 154 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 9 General-purpose and alternate-function I/Os (GPIOs and AFIOs) . . 159 9.1 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.1.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9.1.2 Atomic bit set or reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9.1.3 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . 162 9.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 9.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 9.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.1.10 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.1.11 GPIO configurations for device peripherals . . . . . . . . . . . . . . . . . . . . . 166 9.2 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . . . . . . . . 171 9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . . . . . . . 172 9.2.3 Port input data register (GPIOx_IDR) (x=A..G) . . . . . . . . . . . . . . . . . . 172 9.2.4 Port output data register (GPIOx_ODR) (x=A..G) . . . . . . . . . . . . . . . . 173 9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . . . . . . . . . . . . 173 9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) . . . . . . . . . . . . . . . . . . . 174 9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . . . . . . . 174 9.3 Alternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . 175 9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . 175 5/1128 DocID13902 Rev 15 RM0008 Contents 9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . . . . . . . 175 9.3.3 CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 9.3.4 CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 9.3.5 JTAG/SWD alternate function remapping . . . . . . . . . . . . . . . . . . . . . . 176 9.3.6 ADC alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 9.3.7 Timer alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 9.3.8 USART alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . 180 9.3.9 I2C1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 9.3.10 SPI1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 9.3.11 SPI3/I2S3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . 181 9.3.12 Ethernet alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . 181 9.4 AFIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.4.1 Event control register (AFIO_EVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) . . . . . . 184 9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) . . . . . . . . 191 9.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) . . . . . . . . 191 9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) . . . . . . . . 192 9.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) . . . . . . . . 192 9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2) . . . . 193 9.5 GPIO and AFIO register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 196 10.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 10.2 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 205 10.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 10.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 10.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 10.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 10.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 208 10.3 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 10.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 10.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 10.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 211 10.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 211 10.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . . 212 DocID13902 Rev 15 6/1128 26 Contents RM0008 10.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 10.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 11 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 11.1 ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 11.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 11.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 11.3.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 11.3.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 11.3.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 11.3.4 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 11.3.5 Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 11.3.6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 11.3.7 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 11.3.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 11.3.9 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 11.3.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 11.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 11.5 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 11.6 Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 224 11.7 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 11.8 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 11.9 Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 11.9.1 Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 11.9.2 Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 11.9.3 Fast interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 11.9.4 Slow interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 11.9.5 Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 11.9.6 Independent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 11.9.7 Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 232 11.9.8 Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 232 11.9.9 Combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . . 233 11.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 11.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 11.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 11.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 7/1128 DocID13902 Rev 15 RM0008 Contents 11.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 11.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 11.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 243 11.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 244 11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . 244 11.12.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 245 11.12.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 245 11.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 246 11.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 247 11.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 248 11.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 249 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 250 11.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 250 11.12.15 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 12 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 12.1 DAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 12.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 12.3 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 12.3.1 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 12.3.2 DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 12.3.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 12.3.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 12.3.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 12.3.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 12.3.7 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 12.3.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 12.3.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 12.4 Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 12.4.1 Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 260 12.4.2 Independent trigger with same LFSR generation . . . . . . . . . . . . . . . . 261 12.4.3 Independent trigger with different LFSR generation . . . . . . . . . . . . . . 261 12.4.4 Independent trigger with same triangle generation . . . . . . . . . . . . . . . 261 12.4.5 Independent trigger with different triangle generation . . . . . . . . . . . . . 262 12.4.6 Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 12.4.7 Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 262 12.4.8 Simultaneous trigger with same LFSR generation . . . . . . . . . . . . . . . 263 DocID13902 Rev 15 8/1128 26 Contents RM0008 12.5 12.4.9 Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 263 12.4.10 Simultaneous trigger with same triangle generation . . . . . . . . . . . . . . 263 12.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 264 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 12.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 12.5.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 267 12.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 12.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 12.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 12.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 12.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 12.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 271 12.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 271 12.5.14 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 273 13.1 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 13.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 13.3 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 13.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 13.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 13.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 13.3.4 Programmable data width, data alignment and endians . . . . . . . . . . . 278 13.3.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 13.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 13.3.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 9/1128 DocID13902 Rev 15 RM0008 Contents 13.4 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 13.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 284 13.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 285 13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7), where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7), where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7), where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 13.4.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 14 Advanced-control timers (TIM1&TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 292 14.1 TIM1&TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 14.2 TIM1&TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 14.3 TIM1&TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 14.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 14.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 14.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 14.3.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 14.3.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 14.3.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 14.3.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 14.3.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 14.3.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 14.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 14.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 317 14.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 14.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 321 14.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 14.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 14.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 14.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 14.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 14.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 329 14.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 14.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 DocID13902 Rev 15 10/1128 26 Contents RM0008 14.4 TIM1&TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 333 14.4.2 TIM1&TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 334 14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 337 14.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . 339 14.4.5 TIM1&TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 341 14.4.6 TIM1&TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 342 14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . 344 14.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . 347 14.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . 348 14.4.10 TIM1&TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 14.4.11 TIM1&TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 14.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 351 14.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . 352 14.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . 352 14.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . 353 14.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . 353 14.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . 354 14.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . 354 14.4.19 TIM1&TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . 356 14.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . 357 14.4.21 TIM1&TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 15 General-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 360 15.1 TIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 15.2 TIMx main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 15.3 TIMx functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 15.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 15.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 15.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 15.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 15.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 15.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 15.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 15.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 15.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 11/1128 DocID13902 Rev 15 RM0008 Contents 15.4 15.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 384 15.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 15.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 15.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 388 15.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 15.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 TIMx2 to TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 15.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 397 15.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 399 15.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 400 15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 402 15.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 15.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 405 15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 406 15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 409 15.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 410 15.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 15.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 15.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 412 15.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 412 15.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 413 15.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 413 15.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 413 15.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 414 15.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 414 15.4.19 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 16 General-purpose timers (TIM9 to TIM14) . . . . . . . . . . . . . . . . . . . . . . . 418 16.1 TIM9 to TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 16.2 TIM9 to TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 16.2.1 TIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 16.2.2 TIM10/TIM11 and TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . 420 16.3 TIM9 to TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 16.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 16.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 16.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 16.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 DocID13902 Rev 15 12/1128 26 Contents RM0008 16.4 16.5 16.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 16.3.6 PWM input mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 429 16.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 16.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 16.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 16.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 16.3.11 TIM9/12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 434 16.3.12 Timer synchronization (TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 16.3.13 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 TIM9 and TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 16.4.1 TIM9/12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 437 16.4.2 9/12TIM9/12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 439 16.4.3 TIM9/12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . 440 16.4.4 TIM9/12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 16.4.5 TIM9/12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . 442 16.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . 444 16.4.7 TIM9/12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . 447 16.4.8 TIM9/12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 16.4.9 TIM9/12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 16.4.10 TIM9/12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 448 16.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 449 16.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 449 16.4.13 TIM9/12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 TIM10/11/13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 16.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 452 16.5.2 TIM10/11/13/14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . 453 16.5.3 TIM10/11/13/14 event generation register (TIMx_EGR) . . . . . . . . . . . 453 16.5.4 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 16.5.5 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 16.5.6 TIM10/11/13/14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 458 16.5.7 TIM10/11/13/14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 458 16.5.8 TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . 458 16.5.9 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . 459 16.5.10 TIM10/11/13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 13/1128 DocID13902 Rev 15 RM0008 Contents 17 Basic timers (TIM6&TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 17.1 TIM6&TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 17.2 TIM6&TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 17.3 TIM6&TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 17.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 17.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 17.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 17.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 17.4 TIM6&TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 17.4.1 TIM6&TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 467 17.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 469 17.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . 469 17.4.4 TIM6&TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 470 17.4.5 TIM6&TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 470 17.4.6 TIM6&TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 17.4.7 TIM6&TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 471 17.4.9 TIM6&TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 18 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 18.1 RTC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 18.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 18.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 18.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 18.3.2 Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.3.3 Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.3.4 Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.3.5 RTC flag assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 18.4 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 18.4.1 RTC control register high (RTC_CRH) . . . . . . . . . . . . . . . . . . . . . . . . 478 18.4.2 RTC control register low (RTC_CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 479 18.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) . . . . . . . . . . . 480 18.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . . . . . . . 481 18.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) . . . . . . . . . . . . . . . . 482 18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . . . . . . . . . . . 483 18.4.7 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 DocID13902 Rev 15 14/1128 26 Contents RM0008 19 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 19.1 IWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 19.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 19.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 19.3.1 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 19.3.2 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 19.3.3 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 19.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 19.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 19.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 19.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 19.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 19.4.5 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 20 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.1 WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 20.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 493 20.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 20.6 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 20.6.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 20.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 496 20.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 20.6.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 21 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 498 21.1 FSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 21.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 21.3 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 21.3.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 501 21.4 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 21.4.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 21.4.2 NAND/PC Card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 21.5 NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 15/1128 DocID13902 Rev 15 RM0008 Contents 21.6 21.5.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 21.5.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 506 21.5.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 21.5.4 NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 508 21.5.5 Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 21.5.6 NOR/PSRAM control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 NAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 21.6.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 21.6.2 NAND Flash / PC Card supported memories and transactions . . . . . . 541 21.6.3 Timing diagrams for NAND and PC Card . . . . . . . . . . . . . . . . . . . . . . 541 21.6.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 21.6.5 NAND Flash pre-wait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 21.6.6 Computation of the error correction code (ECC) in NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 21.6.7 PC Card/CompactFlash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 21.6.8 NAND Flash/PC Card control registers . . . . . . . . . . . . . . . . . . . . . . . . 547 21.6.9 FSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 22 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . 556 22.1 SDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 22.2 SDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 22.3 SDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 22.3.1 SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 22.3.2 SDIO AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 22.4 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 22.4.1 Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 22.4.2 Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 22.4.3 Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 22.4.4 Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 22.4.5 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 22.4.6 Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 22.4.7 Stream access, stream write and stream read (MultiMediaCard only) 574 22.4.8 Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . 576 22.4.9 Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 22.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 22.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 22.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 DocID13902 Rev 15 16/1128 26 Contents RM0008 22.5 22.6 22.7 22.8 22.9 22.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 22.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 22.5.1 R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 22.5.2 R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 22.5.3 R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 22.5.4 R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 22.5.5 R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 22.5.6 R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 22.5.7 R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 22.5.8 R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 22.6.1 SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . . 595 22.6.2 SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . . 595 22.6.3 SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 22.6.4 SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 CE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 22.7.1 Command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 596 22.7.2 Command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 596 22.7.3 CE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 22.7.4 Aborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 SDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 22.9.1 SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . . 598 22.9.2 SDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . . . 598 22.9.3 SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . . 599 22.9.4 SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . . 600 22.9.5 SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . . 601 22.9.6 SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . . 601 22.9.7 SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . . 602 22.9.8 SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . . 602 22.9.9 SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . . 603 22.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 604 22.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 22.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 606 22.9.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 17/1128 DocID13902 Rev 15 RM0008 Contents 22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . . 610 22.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . 611 22.9.16 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 23 Universal serial bus full-speed device interface (USB) . . . . . . . . . . . 613 23.1 USB introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 23.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 23.3 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 23.3.1 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 23.4 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 23.4.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 23.4.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 23.4.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 23.4.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 23.4.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 23.5 USB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 23.5.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 23.5.2 Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 23.5.3 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 23.5.4 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 24 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 24.1 bxCAN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 24.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 24.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 24.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 24.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 647 24.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 24.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 24.4 bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 24.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 24.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 24.4.3 Sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 24.5 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 24.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 24.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 DocID13902 Rev 15 18/1128 26 Contents RM0008 24.6 24.7 24.8 24.9 24.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 651 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 24.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 24.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 654 24.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 24.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 24.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 24.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 24.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 24.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 24.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 24.9.3 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 24.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 24.9.5 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 25.1 SPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 25.2 SPI and I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 25.2.1 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 25.2.2 I2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 25.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 25.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 25.3.2 Configuring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 25.3.3 Configuring the SPI in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 698 25.3.4 Configuring the SPI for half-duplex communication . . . . . . . . . . . . . . . 699 25.3.5 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 699 25.3.6 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 25.3.7 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 25.3.8 Disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 25.3.9 SPI communication using DMA (direct memory addressing) . . . . . . . 710 25.3.10 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 25.3.11 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 25.4 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 19/1128 DocID13902 Rev 15 RM0008 Contents 25.5 25.4.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 25.4.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 25.4.3 25.4.4 25.4.5 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 25.4.6 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 25.4.7 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 25.4.8 I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 25.4.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 25.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 733 25.5.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 25.5.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 25.5.4 25.5.5 25.5.6 25.5.7 25.5.8 25.5.9 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode) . . . . . . 738 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode) . . . . . . 738 SPI_I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 739 SPI_I2S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 740 25.5.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 26 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 743 26.1 I2C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 26.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 26.3 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 26.3.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 26.3.2 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 26.3.3 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 26.3.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 26.3.5 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 26.3.6 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 26.3.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 26.4 26.5 26.3.8 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 I2C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 26.6 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 DocID13902 Rev 15 20/1128 26 Contents RM0008 26.6.1 26.6.2 26.6.3 26.6.4 26.6.5 26.6.6 26.6.7 26.6.8 26.6.9 I2C Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 I2C Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 I2C Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 769 I2C Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 769 I2C Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 I2C Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 I2C Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 I2C Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 775 I2C TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 26.6.10 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 27 Universal synchronous asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 27.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 27.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 27.3 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780 27.3.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 27.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 27.3.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 27.3.4 Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 27.3.5 USART receiver’s tolerance to clock deviation . . . . . . . . . . . . . . . . . . 793 27.3.6 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 27.3.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 27.3.8 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 796 27.3.9 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 27.3.10 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 800 27.3.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 27.3.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 27.3.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 805 27.3.14 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 27.4 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 27.5 USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 27.6 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 27.6.1 Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 27.6.2 Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 27.6.3 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 27.6.4 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 21/1128 DocID13902 Rev 15 RM0008 Contents 27.6.5 27.6.6 27.6.7 27.6.8 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 819 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 28 USB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . 821 28.1 OTG_FS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821 28.2 OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 28.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 28.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 28.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 28.3 OTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 28.3.1 OTG full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 28.3.2 Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 28.4 OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 28.4.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 28.4.2 HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 28.4.3 SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 28.5 USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 28.5.1 SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 28.5.2 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 28.5.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 28.6 USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 28.6.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 28.6.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 28.6.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 28.6.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 28.7 SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 28.7.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 28.7.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 28.8 Power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837 28.9 Dynamic update of the OTG_FS_HFIR register . . . . . . . . . . . . . . . . . . . 838 28.10 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 28.11 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 28.11.1 Peripheral Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 28.11.2 Peripheral Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 DocID13902 Rev 15 22/1128 26 Contents RM0008 28.12 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 28.12.1 Host Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 28.12.2 Host Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 28.13 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 28.13.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 28.13.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 28.14 USB system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 28.15 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843 28.16 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 28.16.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 28.16.2 OTG_FS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 28.16.3 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 28.16.4 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882 28.16.5 OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904 28.16.6 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 28.17 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912 28.17.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912 28.17.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 28.17.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 28.17.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 28.17.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 28.17.6 Operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933 28.17.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 28.17.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 29 Ethernet (ETH): media access control (MAC) with DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 29.1 Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 29.2 Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958 29.2.1 MAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959 29.2.2 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 29.2.3 PTP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960 29.3 Ethernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961 29.4 Ethernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . . 962 29.4.1 Station management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 23/1128 DocID13902 Rev 15 RM0008 Contents 29.5 29.6 29.7 29.8 29.4.2 Media-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 29.4.3 Reduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . . 968 29.4.4 MII/RMII selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 Ethernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . . 970 29.5.1 MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970 29.5.2 MAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974 29.5.3 MAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 29.5.4 MAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987 29.5.5 MAC filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987 29.5.6 MAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990 29.5.7 MAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . 990 29.5.8 Power management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 29.5.9 Precision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . . 994 Ethernet functional description: DMA controller operation . . . . . . . . . . 1000 29.6.1 Initialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . 1001 29.6.2 Host bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001 29.6.3 Host data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 29.6.4 Buffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 29.6.5 DMA arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 29.6.6 Error response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 29.6.7 Tx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003 29.6.8 Rx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012 29.6.9 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 Ethernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 29.8.1 MAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022 29.8.2 MMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039 29.8.3 IEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044 29.8.4 DMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048 29.8.5 Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061 30 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065 30.1 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065 30.1.1 Flash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065 30.2 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 31 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068 DocID13902 Rev 15 24/1128 26 Contents RM0008 31.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068 31.2 Reference ARM® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 31.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1070 31.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1071 31.4 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 31.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072 31.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072 31.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1073 31.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . 1074 31.5 STM32F10xxx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . 1074 31.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076 31.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076 31.6.2 31.6.3 31.6.4 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 Cortex®-M3 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 Cortex®-M3 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 31.7 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 31.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080 31.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080 31.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080 31.8.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1081 31.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082 31.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082 31.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 31.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 31.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 31.11 Capability of the debugger host to connect under system reset . . . . . 1086 31.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086 31.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087 31.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1087 31.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087 31.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 1087 31.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 31.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 31.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 31.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 25/1128 DocID13902 Rev 15 RM0008 Contents 31.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090 31.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1090 31.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1090 31.16.2 Debug support for timers, watchdog, bxCAN and I2C . . . . . . . . . . . . 1091 31.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091 31.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093 31.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093 31.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095 31.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 31.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1097 31.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 1097 31.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097 31.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 31.17.8 TRACECLKIN connection inside the STM32F10xxx . . . . . . . . . . . . . 1098 31.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 31.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099 31.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101 DocID13902 Rev 15 26/1128 26 List of tables List of tables RM0008 Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Sections related to each STM32F10xxx product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Sections related to each peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Flash module organization (low-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Flash module organization (medium-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Flash module organization (high-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Flash module organization (connectivity line devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 XL-density Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 CRC calculation unit register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 BKP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Output MODE bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Advanced timers TIM1/TIM8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 General-purpose timers TIM2/3/4/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 BxCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 OTG_FS pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 FSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Other IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Debug interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Debug port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 ADC1 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 177 ADC1 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 177 ADC2 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 177 ADC2 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 178 TIM5 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 TIM4 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 TIM3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 TIM2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 TIM1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 TIM9 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 TIM10 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 27/1128 DocID13902 Rev 15 RM0008 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. TIM11 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 TIM13 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 TIM14 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 USART3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 USART2 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 USART1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 I2C1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SPI1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SPI3/I2S3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 ETH remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 AFIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Vector table for connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Vector table for XL-density devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Vector table for other STM32F10xxx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 213 ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 External trigger for regular channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . . 224 External trigger for injected channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . 225 External trigger for regular channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 External trigger for injected channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 278 DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Summary of DMA1 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Summary of DMA2 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Output control bits for complementary OCx and OCxN channels with break feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 TIM1&TIM8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 TIM9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 TIM10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 TIM6&TIM7 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Min/max IWDG timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Min-max timeout value @36 MHz (fPCLK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 DocID13902 Rev 15 28/1128 31 List of tables RM0008 Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 Memory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 NAND bank selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 Nonmultiplexed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 Multiplexed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 Nonmultiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 NOR Flash/PSRAM controller: example of supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 FSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 FSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 FSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 Programmable NAND/PC Card access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 16-bit PC-Card signals and access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 FSMC register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 SDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 Long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 29/1128 DocID13902 Rev 15 RM0008 List of tables Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. Table 195. Table 197. Table 198. Table 199. Table 200. Table 201. Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 Response type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 Audio-frequency precision using standard 8 MHz HSE (high-density and XL-density devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725 Audio-frequency precision using standard 14.7456 MHz and PLL3 (connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 SMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 Error calculation for programmed baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 USART receiver’s tolerance when DIV_Fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793 USART receiver’s tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . 793 Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 DocID13902 Rev 15 30/1128 31 List of tables RM0008 Table 202. Table 203. Table 204. Table 205. Table 206. Table 207. Table 208. Table 209. Table 210. Table 211. Table 212. Table 213. Table 214. Table 215. Table 216. Table 217. Table 218. Table 219. Table 220. Table 221. Table 222. Table 223. Table 224. Table 225. Table 226. Table 227. Table 228. Table 229. Table 230. Table 231. Table 232. Table 233. Table 234. Table 235. Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884 OTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 Ethernet pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961 Management frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 Clock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 TX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 RX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 Frame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 Destination address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989 Source address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990 Receive descriptor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 Ethernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 1080 Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082 Cortex®-M3 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088 Main ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095 Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095 Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096 Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098 DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101 31/1128 DocID13902 Rev 15 RM0008 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. System architecture (low-, medium-, XL-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . 48 System architecture in connectivity line devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Basic structure of a standard I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 ADC / DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Calibration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Right alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Left alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Dual ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Injected simultaneous mode on 4 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Regular simultaneous mode on 16 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Fast interleaved mode on 1 channel in continuous conversion mode . . . . . . . . . . . . . . . 230 Slow interleaved mode on 1 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Alternate trigger: injected channel group of each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Alternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . . . . . . . . 232 Alternate + Regular simultaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Interleaved single channel with injected sequence CH11, CH12 . . . . . . . . . . . . . . . . . . . 233 Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 234 DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 257 DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 259 DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 260 DMA block diagram in connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 DocID13902 Rev 15 32/1128 39 List of figures RM0008 Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. DMA block diagram in low-, medium- high- and XL-density devices . . . . . . . . . . . . . . . . 275 DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 296 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 296 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 298 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 302 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 303 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 304 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 304 Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 305 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 306 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 309 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 310 Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 310 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 317 Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 318 Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 326 Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 326 Example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 33/1128 DocID13902 Rev 15 RM0008 List of figures Figure 99. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Figure 100. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Figure 101. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 363 Figure 102. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 364 Figure 103. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Figure 104. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Figure 105. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Figure 106. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 366 Figure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 367 Figure 109. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Figure 110. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Figure 111. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Figure 112. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Figure 113. Counter timing diagram, Update event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Figure 114. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 370 Figure 115. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Figure 116. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 371 Figure 117. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 372 Figure 119. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 372 Figure 120. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 373 Figure 121. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Figure 122. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Figure 123. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Figure 124. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Figure 125. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 375 Figure 126. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Figure 127. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 376 Figure 128. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Figure 129. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Figure 130. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Figure 131. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 Figure 132. Example of one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Figure 133. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Figure 134. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 387 Figure 135. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 387 Figure 136. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Figure 137. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Figure 138. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Figure 139. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 391 Figure 140. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 Figure 141. Gating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Figure 142. Gating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 Figure 143. Triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Figure 144. Triggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Figure 145. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 Figure 146. General-purpose timer block diagram (TIM9 and TIM12) . . . . . . . . . . . . . . . . . . . . . . . . 419 Figure 147. General-purpose timer block diagram (TIM10/11/13/14) . . . . . . . . . . . . . . . . . . . . . . . . 420 Figure 148. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 422 Figure 149. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 422 Figure 150. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 DocID13902 Rev 15 34/1128 39 List of figures RM0008 Figure 151. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Figure 152. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 Figure 153. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 Figure 154. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 Figure 155. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Figure 156. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 426 Figure 157. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 Figure 158. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Figure 159. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 427 Figure 160. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Figure 161. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Figure 162. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 Figure 163. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 Figure 164. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Figure 165. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Figure 166. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Figure 167. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Figure 168. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Figure 169. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 Figure 170. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 463 Figure 171. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 463 Figure 172. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 Figure 173. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Figure 174. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Figure 175. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Figure 176. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Figure 177. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 Figure 178. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 467 Figure 179. RTC simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 Figure 180. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . 477 Figure 181. RTC Overflow waveform example with PR=0003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 Figure 182. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 Figure 183. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Figure 184. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 Figure 185. FSMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 Figure 186. FSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 Figure 187. Mode1 read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 Figure 188. Mode1 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 Figure 189. ModeA read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 Figure 190. ModeA write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 Figure 191. Mode2 and mode B read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 Figure 192. Mode2 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 Figure 193. Mode B write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 Figure 194. Mode C read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 Figure 195. Mode C write accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Figure 196. Mode D read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Figure 197. Multiplexed read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 Figure 198. Multiplexed write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 35/1128 DocID13902 Rev 15 RM0008 List of figures Figure 199. Asynchronous wait during a read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 Figure 200. Asynchronous wait during a write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 Figure 201. Wait configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 Figure 202. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . 528 Figure 203. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 530 Figure 204. NAND/PC Card controller timing for common memory access . . . . . . . . . . . . . . . . . . . 542 Figure 205. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 Figure 206. SDIO “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Figure 207. SDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Figure 208. SDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 Figure 209. SDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 Figure 210. SDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 Figure 211. SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 Figure 212. SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Figure 213. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 Figure 214. SDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 Figure 215. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 Figure 216. SDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 Figure 217. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Figure 218. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 Figure 219. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614 Figure 220. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 618 Figure 221. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 Figure 222. Dual CAN block diagram (connectivity devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 Figure 223. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 Figure 224. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 Figure 225. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 Figure 226. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 Figure 227. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 Figure 228. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 Figure 229. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 Figure 230. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 Figure 231. Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 Figure 232. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 Figure 233. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 Figure 234. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 Figure 235. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 Figure 236. RX and TX mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 Figure 237. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 Figure 238. Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694 Figure 239. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 Figure 240. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 Figure 241. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702 Figure 242. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 Figure 243. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 Figure 244. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 Figure 245. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in the case of DocID13902 Rev 15 36/1128 39 List of figures RM0008 discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 Figure 246. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 Figure 247. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 Figure 248. I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 Figure 249. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 716 Figure 250. I2S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 716 Figure 251. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Figure 252. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 Figure 253. I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 717 Figure 254. Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 Figure 255. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 718 Figure 256. MSB Justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 Figure 257. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . 719 Figure 258. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 719 Figure 259. LSB Justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Figure 260. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Figure 261. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Figure 262. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 721 Figure 263. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . 721 Figure 264. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 Figure 265. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 722 Figure 266. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 Figure 267. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 Figure 268. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 Figure 269. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 Figure 270. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 Figure 271. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Figure 272. Transfer sequence diagram for master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 Figure 273. Method 1: transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . 754 Figure 274. Method 2: transfer sequence diagram for master receiver when N>2 . . . . . . . . . . . . . . . 755 Figure 275. Method 2: transfer sequence diagram for master receiver when N=2 . . . . . . . . . . . . . . . 756 Figure 276. Method 2: transfer sequence diagram for master receiver when N=1 . . . . . . . . . . . . . . . 757 Figure 277. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 Figure 278. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 Figure 279. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 Figure 280. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 Figure 281. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 Figure 282. Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 Figure 283. Data sampling for noise detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 Figure 284. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794 Figure 285. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795 Figure 286. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 797 Figure 287. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 798 Figure 288. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 Figure 289. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 Figure 290. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 Figure 291. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 Figure 292. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 Figure 293. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 Figure 294. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 Figure 295. IrDA data modulation (3/16) -normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 Figure 296. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 37/1128 DocID13902 Rev 15 RM0008 List of figures Figure 297. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 Figure 298. Hardware flow control between two USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 Figure 299. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 Figure 300. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 Figure 301. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 Figure 302. OTG full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 Figure 303. OTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 Figure 304. USB peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 Figure 305. USB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 Figure 306. SOF connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 Figure 307. Updating OTG_FS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 Figure 308. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . 839 Figure 309. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . . 840 Figure 310. Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 Figure 311. CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 Figure 312. Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 Figure 313. Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916 Figure 314. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . . 918 Figure 315. Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921 Figure 316. Normal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 Figure 317. Normal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 Figure 318. Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 Figure 319. Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936 Figure 320. Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942 Figure 321. TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 Figure 322. A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 Figure 323. B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 Figure 324. A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954 Figure 325. B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956 Figure 326. ETH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962 Figure 327. SMI interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963 Figure 328. MDIO timing and frame structure - Write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964 Figure 329. MDIO timing and frame structure - Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965 Figure 330. Media independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966 Figure 331. MII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 Figure 332. Reduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968 Figure 333. RMII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 Figure 334. Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969 Figure 335. Address field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971 Figure 336. MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 Figure 337. Tagged MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973 Figure 338. Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 Figure 339. Transmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980 Figure 340. Transmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 Figure 341. Frame transmission in MMI and RMII modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981 Figure 342. Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 Figure 343. Reception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 Figure 344. Reception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 Figure 345. Reception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 Figure 346. MAC core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987 Figure 347. Wakeup frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992 Figure 348. Networked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995 DocID13902 Rev 15 38/1128 39 List of figures RM0008 Figure 349. System time update using the Fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . . 997 Figure 350. PTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999 Figure 351. PPS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 Figure 352. Descriptor ring and chain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001 Figure 353. TxDMA operation in Default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005 Figure 354. TxDMA operation in OSF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007 Figure 355. ransmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 Figure 356. Receive DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014 Figure 357. Rx DMA descriptor structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016 Figure 358. Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021 Figure 359. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . . . . . . . . 1031 Figure 360. Block diagram of STM32 MCU and Cortex®-M3-level debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069 Figure 361. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070 Figure 362. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 Figure 363. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094 39/1128 DocID13902 Rev 15 RM0008 1 Overview of the manual Overview of the manual Legend for Table 1: The section in each row applies to products in columns marked with “•" Table 1. Sections related to each STM32F10xxx product Low-density STM32F101xx Medium-density STM32F101xx High and XL-density STM32F101x Low-density STM32F102xx Medium-density STM32F102xx Low-density STM32F103xx Medium-density STM32F103xx High and XL-density STM32F103xx STM32F105xx STM32F107xx Section 2: Documentation conventions •• • • • • • • • • Section 3: Memory and bus architecture •• • • • • • • • • Section 4: CRC calculation unit •• • • • • • • • • Section 5: Power control (PWR) •• • • • • • • • • Section 6: Backup registers (BKP) •• • • • • • • • • Section 7: Low-, medium-, high- and XL-density reset • • • • • • • • and clock control (RCC) Section 8: Connectivity line devices: reset and clock control (RCC) •• Section 9: General- purpose and alternatefunction I/Os (GPIOs and •• • • • • • • • • AFIOs) Section 10: Interrupts and events •• • • • • • • • • Section 13: Direct memory access controller (DMA) • • • • • • • • • • DocID13902 Rev 15 40/1128 46 Overview of the manual Table 1. Sections related to each STM32F10xxx product (continued) RM0008 Low-density STM32F101xx Medium-density STM32F101xx High and XL-density STM32F101x Low-density STM32F102xx Medium-density STM32F102xx Low-density STM32F103xx Medium-density STM32F103xx High and XL-density STM32F103xx STM32F105xx STM32F107xx Section 11: Analog-todigital converter (ADC) •• • • • • • • • • Section 12: Digital-toanalog converter (DAC) • ••• Section 14: Advanced- control timers • (TIM1&TIM8) ••••• Section 15: General- purpose timers (TIM2 to •• • • • • • • • • TIM5) Section 16: General- purpose timers (TIM9 to • (1) • (1) TIM14) Section 17: Basic timers (TIM6&TIM7) • ••• Section 18: Real-time clock (RTC) •• • • • • • • • • Section 19: Independent watchdog (IWDG) •• • • • • • • • • Section 20: Window watchdog (WWDG) •• • • • • • • • • Section 21: Flexible static memory controller (FSMC) · · Section 1: Secure digital input/output interface · · (SDIO) Section 23: Universal serial bus full-speed device interface (USB) · · · · · 41/1128 DocID13902 Rev 15 RM0008 Overview of the manual Table 1. Sections related to each STM32F10xxx product (continued) Low-density STM32F101xx Medium-density STM32F101xx High and XL-density STM32F101x Low-density STM32F102xx Medium-density STM32F102xx Low-density STM32F103xx Medium-density STM32F103xx High and XL-density STM32F103xx STM32F105xx STM32F107xx Section 24: Controller area network (bxCAN) · · · · · Section 25: Serial peripheral interface (SPI) •• • • • • • • • • Section 26: Interintegrated circuit (I2C) interface •• • • • • • • • • Section 27: Universal synchronous asynchronous receiver transmitter (USART) •• • • • • • • • • Section 28: USB on-thego full-speed (OTG_FS) · · Section 29: Ethernet (ETH): media access control (MAC) with DMA · controller Section 30: Device electronic signature •• • • • • • • • • Section 31: Debug support (DBG) •• • • • • • • • • Note: Available only on XL-density devices. DocID13902 Rev 15 42/1128 46 Overview of the manual RM0008 Legend for Table 2: • The section in this row must be read when using the peripherals in columns marked with “•"  The section in this row can optionally be read when using the peripherals in columns marked with “" Table 2. Sections related to each peripheral Backup registers (BKP) General-purpose I/Os (GPIOs) Analog-to-digital converter (ADC) Digital-to-analog converter (DAC) Advanced-control timers (TIM1&TIM8) General-purpose timers (TIM2 to TIM5) General-purpose timers (TIM9 to TIM14) Basic timers (TIM6&TIM7) Real-time clock (RTC) Independent watchdog (IWDG) Window watchdog (WWDG) Flexible static memory controller (FSMC) Secure digital input/output interface (SDIO) USB full-speed device (USB) Controller area network (bxCAN) Serial peripheral interface (SPI) Inter-integrated circuit (I2C) interface USART USB on-the-go full-speed (OTG_FS) Ethernet (ETH) Section 2: Documentation conventions •• • • • • • • • Section 3: Memory and bus architecture •• • • • • • • • Section 4: CRC calculation unit Section 5: Power control (PWR) •• •• •• •• • Section 6: Backup registers (BKP) •  Section 7: Low-, medium-, high- and XLdensity reset and clock • • • • • • • • • control (RCC) Section 8: Connectivity line devices: reset and • • • • • • • • • clock control (RCC) • •• • • • • • • • • • •• • • • • • • • • • • •• •• •• •• · • •• • • • • • • • • • •• • • • • • • • • 43/1128 DocID13902 Rev 15 RM0008 Overview of the manual Table 2. Sections related to each peripheral (continued) Backup registers (BKP) General-purpose I/Os (GPIOs) Analog-to-digital converter (ADC) Digital-to-analog converter (DAC) Advanced-control timers (TIM1&TIM8) General-purpose timers (TIM2 to TIM5) General-purpose timers (TIM9 to TIM14) Basic timers (TIM6&TIM7) Real-time clock (RTC) Independent watchdog (IWDG) Window watchdog (WWDG) Flexible static memory controller (FSMC) Secure digital input/output interface (SDIO) USB full-speed device (USB) Controller area network (bxCAN) Serial peripheral interface (SPI) Inter-integrated circuit (I2C) interface USART USB on-the-go full-speed (OTG_FS) Ethernet (ETH) Section 9: General- purpose and alternatefunction I/Os (GPIOs • • • • • • and AFIOs) à • •• • • • • • • • • Section 10: Interrupts and events   Section 13: Direct memory access controller (DMA)     Section 11: Analog-todigital converter (ADC) · Section 12: Digital-toanalog converter (DAC) · Section 14: Advancedcontrol timers (TIM1&TIM8) · Section 15: Generalpurpose timers (TIM2 to TIM5) à · Section 16: General- purpose timers (TIM9 to · TIM14) Section 17: Basic timers (TIM6&TIM7)  · Section 18: Real-time clock (RTC) · · DocID13902 Rev 15 44/1128 46 Overview of the manual Table 2. Sections related to each peripheral (continued) Section 19: Independent watchdog (IWDG) Section 20: Window watchdog (WWDG) Section 21: Flexible static memory controller (FSMC) Section 1: Secure digital input/output interface (SDIO) Section 23: Universal serial bus full-speed device interface (USB) Section 24: Controller area network (bxCAN) Section 25: Serial peripheral interface (SPI) Section 26: Interintegrated circuit (I2C) interface Section 27: Universal synchronous asynchronous receiver transmitter (USART) 45/1128 · · · · · · · · · DocID13902 Rev 15 Backup registers (BKP) General-purpose I/Os (GPIOs) Analog-to-digital converter (ADC) Digital-to-analog converter (DAC) Advanced-control timers (TIM1&TIM8) General-purpose timers (TIM2 to TIM5) General-purpose timers (TIM9 to TIM14) Basic timers (TIM6&TIM7) Real-time clock (RTC) Independent watchdog (IWDG) Window watchdog (WWDG) Flexible static memory controller (FSMC) Secure digital input/output interface (SDIO) USB full-speed device (USB) Controller area network (bxCAN) Serial peripheral interface (SPI) Inter-integrated circuit (I2C) interface USART USB on-the-go full-speed (OTG_FS) Ethernet (ETH) RM0008 RM0008 Section 28: USB onthe-go full-speed (OTG_FS) Section 29: Ethernet (ETH): media access control (MAC) with DMA controller Section 30: Device electronic signature Section 31: Debug support (DBG) Overview of the manual Table 2. Sections related to each peripheral (continued) · ·  DocID13902 Rev 15 Backup registers (BKP) General-purpose I/Os (GPIOs) Analog-to-digital converter (ADC) Digital-to-analog converter (DAC) Advanced-control timers (TIM1&TIM8) General-purpose timers (TIM2 to TIM5) General-purpose timers (TIM9 to TIM14) Basic timers (TIM6&TIM7) Real-time clock (RTC) Independent watchdog (IWDG) Window watchdog (WWDG) Flexible static memory controller (FSMC) Secure digital input/output interface (SDIO) USB full-speed device (USB) Controller area network (bxCAN) Serial peripheral interface (SPI) Inter-integrated circuit (I2C) interface USART USB on-the-go full-speed (OTG_FS) Ethernet (ETH) 46/1128 46 Documentation conventions 2 Documentation conventions RM0008 2.1 List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) read-only (r) write-only (w) read/clear (rc_w1) read/clear (rc_w0) read/clear by read (rc_r) read/set (rs) read-only write trigger (rt_w) toggle (t) Reserved (Res.) Software can read and write to these bits. Software can only read these bits. Software can only write to this bit. Reading the bit returns the reset value. Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value. Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no effect on the bit value. Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value. Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on the bit value. Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect. Reserved bit, must be kept at reset value. 2.2 Glossary • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. • Word: data of 32-bit length. • Half-word: data of 16-bit length. • Byte: data of 8-bit length. 2.3 Peripheral availability For peripheral availability and number across all STM32F10xxx sales types, please refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the connectivity line devices, STM32F105xx/STM32F107xx. 47/1128 DocID13902 Rev 15 RM0008 3 Memory and bus architecture Memory and bus architecture 3.1 System architecture In low-, medium-, high- and XL-density devices, the main system consists of: • Four masters: – Cortex®-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) • Four slaves: – Internal SRAM – Internal Flash memory – FSMC – AHB to APBx (APB1 or APB2), which connect all the APB peripherals These are interconnected using a multilayer AHB bus architecture as shown in Figure 1: Figure 1. System architecture (low-, medium-, XL-density devices) Co r t ex -M3 DMA1 Ch.1 Ch.2 Ch.7 DMA2 Ch.1 Ch.2 ICode DCode FLITF Flash DMA Bus matrix Sys tem DMA FSMC SDIO SRAM AHB system bus Reset & clock control (RCC) DMA Request Bridge 2 Bridge 1 ADC1 ADC2 ADC3 USART1 SPI1 TIM1 TIM8 GPIOA GPIOB APB2 GPIOC GPIOD GPIOE GPIOF GPIOG EXTI AFIO APB 1 DAC SPI3/I2S PWR SPI2/I2S BKP IWDG bxCAN WWDG USB RTC I2C2 TIM7 I2C1 TIM6 UART5 TIM5 UART4 TIM4 USART3 TIM3 USART2 TIM2 Ch.5 DMA request ai14800c DocID13902 Rev 15 48/1128 63 Memory and bus architecture RM0008 In connectivity line devices the main system consists of: • Five masters: – Cortex®-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) – Ethernet DMA • Three slaves: – Internal SRAM – Internal Flash memory – AHB to APB bridges (AHB to APBx), which connect all the APB peripherals These are interconnected using a multilayer AHB bus architecture as shown in Figure 2: Figure 2. System architecture in connectivity line devices Co r t ex -M3 DMA1 ICode DCode FLITF Sys tem DMA Reset & clock control (RCC) Flash SRAM DMA Bus matrix Ch.1 Ch.2 Ch.7 DMA2 Ch.1 Ch.2 Ch.5 DMA AHB system bus Bridge 2 Bridge 1 APB2 APB 1 DMA request ADC1 ADC2 USART1 SPI1 TIM1 GPIOA GPIOB GPIOC GPIOD GPIOE EXTI AFIO DAC SPI3/I2S PWR SPI2/I2S BKP IWDG CAN1 WWDG CAN2 RTC I2C2 TIM7 I2C1 TIM6 UART5 TIM5 UART4 TIM4 USART3 TIM3 USART2 TIM2 DMA request Ethernet MAC USB OTG FS ai15810 ICode bus This bus connects the Instruction bus of the Cortex®-M3 core to the Flash memory instruction interface. Prefetching is performed on this bus. 49/1128 DocID13902 Rev 15 RM0008 Memory and bus architecture Note: DCode bus This bus connects the DCode bus (literal load and debug access) of the Cortex®-M3 core to the Flash memory Data interface. System bus This bus connects the system bus of the Cortex®-M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA. DMA bus This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU DCode and DMA to SRAM, Flash memory and peripherals. BusMatrix The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1 and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices, the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges). AHB peripherals are connected on system bus through a BusMatrix to allow DMA access. AHB/APB bridges (APB) The two AHB/APB bridges provide full synchronous connections between the AHB and the 2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz depending on the device). Refer to Table 3 on page 51 for the address mapping of the peripherals connected to each bridge. After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register. When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector. 3.2 Memory organization Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. For the detailed mapping of peripheral registers, please refer to the related chapters. The addressable memory space is divided into 8 main blocks, each of 512 MB. All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”). Refer to the Memory map figure in the corresponding product datasheet. DocID13902 Rev 15 50/1128 63 Memory and bus architecture RM0008 3.3 Memory map See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 3 gives the boundary addresses of the peripherals available in all STM32F10xxx devices. Boundary address 0xA000 0000 - 0xA000 0FFF 0x5000 0000 - 0x5003 FFFF 0x4003 0000 - 0x4FFF FFFF 0x4002 8000 - 0x4002 9FFF 0x4002 3400 - 0x4002 7FFF 0x4002 3000 - 0x4002 33FF 0x4002 2000 - 0x4002 23FF 0x4002 1400 - 0x4002 1FFF 0x4002 1000 - 0x4002 13FF 0x4002 0800 - 0x4002 0FFF 0x4002 0400 - 0x4002 07FF 0x4002 0000 - 0x4002 03FF 0x4001 8400 - 0x4001 FFFF 0x4001 8000 - 0x4001 83FF Table 3. Register boundary addresses Peripheral Bus Register map FSMC USB OTG FS Section 21.6.9 on page 554 Section 28.16.6 on page 905 Reserved Ethernet Reserved CRC Flash memory interface Reserved Reset and clock control RCC Reserved DMA2 Section 29.8.5 on page 1061 Section 4.4.4 on page 66 AHB Section 7.3.11 on page 121 Section 13.4.7 on page 289 DMA1 Section 13.4.7 on page 289 Reserved SDIO Section 1.9.16 on page 656 51/1128 DocID13902 Rev 15 RM0008 Memory and bus architecture Table 3. Register boundary addresses (continued) Boundary address Peripheral Bus Register map 0x4001 5800 - 0x4001 7FFF Reserved 0x4001 5400 - 0x4001 57FF TIM11 timer Section 16.5.10 on page 459 0x4001 5000 - 0x4001 53FF TIM10 timer Section 16.5.10 on page 459 0x4001 4C00 - 0x4001 4FFF TIM9 timer Section 16.4.13 on page 449 0x4001 4000 - 0x4001 4BFF Reserved 0x4001 3C00 - 0x4001 3FFF ADC3 Section 11.12.15 on page 251 0x4001 3800 - 0x4001 3BFF USART1 Section 27.6.8 on page 820 0x4001 3400 - 0x4001 37FF TIM8 timer Section 14.4.21 on page 358 0x4001 3000 - 0x4001 33FF SPI1 Section 25.5 on page 733 0x4001 2C00 - 0x4001 2FFF TIM1 timer Section 14.4.21 on page 358 0x4001 2800 - 0x4001 2BFF ADC2 APB2 Section 11.12.15 on page 251 0x4001 2400 - 0x4001 27FF ADC1 Section 11.12.15 on page 251 0x4001 2000 - 0x4001 23FF GPIO Port G Section 9.5 on page 194 0x4001 1C00 - 0x4001 1FFF GPIO Port F Section 9.5 on page 194 0x4001 1800 - 0x4001 1BFF GPIO Port E Section 9.5 on page 194 0x4001 1400 - 0x4001 17FF GPIO Port D Section 9.5 on page 194 0x4001 1000 - 0x4001 13FF GPIO Port C Section 9.5 on page 194 0x4001 0C00 - 0x4001 0FFF GPIO Port B Section 9.5 on page 194 0x4001 0800 - 0x4001 0BFF GPIO Port A Section 9.5 on page 194 0x4001 0400 - 0x4001 07FF EXTI Section 10.3.7 on page 213 0x4001 0000 - 0x4001 03FF AFIO Section 9.5 on page 194 DocID13902 Rev 15 52/1128 63 Memory and bus architecture RM0008 Table 3. Register boundary addresses (continued) Boundary address Peripheral Bus Register map 0x4000 7800 - 0x4000 FFFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF Power control PWR 0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) 0x4000 6400 - 0x4000 67FF bxCAN1 0x4000 6800 - 0x4000 6BFF bxCAN2 0x4000 6000(1) - 0x4000 63FF Shared USB/CAN SRAM 512 bytes 0x4000 5C00 - 0x4000 5FFF USB device FS registers 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF Reserved Section 12.5.14 on page 272 Section 5.4.3 on page 80 Section 6.4.5 on page 85 Section 24.9.5 on page 686 Section 24.9.5 on page 686 Section 23.5.4 on page 643 Section 26.6.10 on page 777 Section 26.6.10 on page 777 Section 27.6.8 on page 820 Section 27.6.8 on page 820 Section 27.6.8 on page 820 Section 27.6.8 on page 820 0x4000 3C00 - 0x4000 3FFF 0x4000 3800 - 0x4000 3BFF 0x4000 3400 - 0x4000 37FF 0x4000 3000 - 0x4000 33FF 0x4000 2C00 - 0x4000 2FFF 0x4000 2800 - 0x4000 2BFF 0x4000 2400 - 0x4000 27FF 0x4000 2000 - 0x4000 23FF 0x4000 1C00 - 0x4000 1FFF SPI3/I2S SPI2/I2S Reserved Independent watchdog (IWDG) Window watchdog (WWDG) RTC Reserved TIM14 timer TIM13 timer APB1 Section 25.5 on page 733 Section 25.5 on page 733 Section 19.4.5 on page 490 Section 20.6.4 on page 497 Section 18.4.7 on page 484 Section 16.5.10 on page 459 Section 16.5.10 on page 459 0x4000 1800 - 0x4000 1BFF 0x4000 1400 - 0x4000 17FF 0x4000 1000 - 0x4000 13FF 0x4000 0C00 - 0x4000 0FFF 0x4000 0800 - 0x4000 0BFF 0x4000 0400 - 0x4000 07FF 0x4000 0000 - 0x4000 03FF TIM12 timer TIM7 timer TIM6 timer TIM5 timer TIM4 timer TIM3 timer TIM2 timer Section 16.4.13 on page 449 Section 17.4.9 on page 472 Section 17.4.9 on page 472 Section 15.4.19 on page 416 Section 15.4.19 on page 416 Section 15.4.19 on page 416 Section 15.4.19 on page 416 1. This shared SRAM can be fully accessed only in low-, medium-, high- and XL-density devices, not in connectivity line devices. 53/1128 DocID13902 Rev 15 RM0008 Memory and bus architecture 3.3.1 3.3.2 Embedded SRAM The STM32F10xxx features up to 96 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000. Bit banding The Cortex®-M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region. In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region. This allows single bit-band write and read operations to be performed. The operations are only available for Cortex®-M3 accesses, not from other bus masters (e.g. DMA). A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4) where: bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. bit_band_base is the starting address of the alias region byte_offset is the number of the byte in the bit-band region that contains the targeted bit bit_number is the bit position (0-7) of the targeted bit. Example: The following example shows how to map bit 2 of the byte located at SRAM address 0x20000300 in the alias region: 0x22006008 = 0x22000000 + (0x300*32) + (2*4). Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM address 0x20000300. Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset). For more information on Bit-Banding, please refer to the Cortex®-M3 Technical Reference Manual. DocID13902 Rev 15 54/1128 63 Memory and bus architecture RM0008 3.3.3 Embedded Flash memory The high-performance Flash memory module has the following key features: • For XL-density devices: density of up to 1 Mbyte with dual bank architecture for read- while-write (RWW) capability: – bank 1: fixed size of 512 Kbytes – bank 2: up to 512 Kbytes • For other devices: density of up to 512 Kbytes • Memory organization: the Flash memory is organized as a main block and an information block: – Main memory block of size: up to 128 Kbytes × 64 bits divided into 512 pages of 2 Kbytes each (see Table 8) for XL-density devices up to 4 Kb × 64 bits divided into 32 pages of 1 Kbyte each for low-density devices (see Table 4) up to 16 Kb × 64 bits divided into 128 pages of 1 Kbyte each for medium-density devices (see Table 5) up to 64 Kb × 64 bits divided into 256 pages of 2 Kbytes each (see Table 6) for high-density devices up to 32 Kbit × 64 bits divided into 128 pages of 2 Kbytes each (see Table 7) for connectivity line devices – Information block of size: 770 × 64 bits for XL-density devices (see Table 8) 2360 × 64 bits for connectivity line devices (see Table 7) 258 × 64 bits for other devices (see Table 4, Table 5 and Table 6) The Flash memory interface (FLITF) features: • Read interface with prefetch buffer (2x64-bit words) • Option byte Loader • Flash Program / Erase operation • Read / Write protection Table 4. Flash module organization (low-density devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte Main memory Page 3 Page 4 0x0800 0C00 - 0x0800 0FFF 0x0800 1000 - 0x0800 13FF 1 Kbyte 1 Kbyte . . . . . . . . . Page 31 0x0800 7C00 - 0x0800 7FFF 1 Kbyte 55/1128 DocID13902 Rev 15 RM0008 Memory and bus architecture Table 4. Flash module organization (low-density devices) (continued) Block Name Base addresses Size (bytes) Information block System memory Option Bytes 0x1FFF F000 - 0x1FFF F7FF 0x1FFF F800 - 0x1FFF F80F 2 Kbytes 16 FLASH_ACR 0x4002 2000 - 0x4002 2003 4 FLASH_KEYR 0x4002 2004 - 0x4002 2007 4 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4 Flash memory interface registers FLASH_SR FLASH_CR FLASH_AR 0x4002 200C - 0x4002 200F 4 0x4002 2010 - 0x4002 2013 4 0x4002 2014 - 0x4002 2017 4 Reserved 0x4002 2018 - 0x4002 201B 4 FLASH_OBR 0x4002 201C - 0x4002 201F 4 FLASH_WRPR 0x4002 2020 - 0x4002 2023 4 Table 5. Flash module organization (medium-density devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte Main memory Page 2 Page 3 Page 4 . . . 0x0800 0800 - 0x0800 0BFF 0x0800 0C00 - 0x0800 0FFF 0x0800 1000 - 0x0800 13FF . . . 1 Kbyte 1 Kbyte 1 Kbyte . . . Information block Page 127 System memory Option Bytes FLASH_ACR 0x0801 FC00 - 0x0801 FFFF 0x1FFF F000 - 0x1FFF F7FF 0x1FFF F800 - 0x1FFF F80F 0x4002 2000 - 0x4002 2003 1 Kbyte 2 Kbytes 16 4 Flash memory interface registers FLASH_KEYR 0x4002 2004 - 0x4002 2007 4 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4 FLASH_SR 0x4002 200C - 0x4002 200F 4 FLASH_CR 0x4002 2010 - 0x4002 2013 4 FLASH_AR 0x4002 2014 - 0x4002 2017 4 Reserved FLASH_OBR FLASH_WRPR 0x4002 2018 - 0x4002 201B 4 0x4002 201C - 0x4002 201F 4 0x4002 2020 - 0x4002 2023 4 DocID13902 Rev 15 56/1128 63 Memory and bus architecture RM0008 Table 6. Flash module organization (high-density devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes Main memory Page 1 Page 2 Page 3 . . . 0x0800 0800 - 0x0800 0FFF 0x0800 1000 - 0x0800 17FF 0x0800 1800 - 0x0800 1FFF . . . 2 Kbytes 2 Kbytes 2 Kbytes . . . Information block Page 255 System memory Option Bytes FLASH_ACR 0x0807 F800 - 0x0807 FFFF 0x1FFF F000 - 0x1FFF F7FF 0x1FFF F800 - 0x1FFF F80F 0x4002 2000 - 0x4002 2003 2 Kbytes 2 Kbytes 16 4 FLASH_KEYR 0x4002 2004 - 0x4002 2007 4 Flash memory interface registers FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4 FLASH_SR 0x4002 200C - 0x4002 200F 4 FLASH_CR 0x4002 2010 - 0x4002 2013 4 FLASH_AR 0x4002 2014 - 0x4002 2017 4 Reserved FLASH_OBR FLASH_WRPR 0x4002 2018 - 0x4002 201B 4 0x4002 201C - 0x4002 201F 4 0x4002 2020 - 0x4002 2023 4 Table 7. Flash module organization (connectivity line devices) Block Name Base addresses Size (bytes) Main memory Information block Page 0 Page 1 Page 2 Page 3 . . . Page 127 System memory Option Bytes 0x0800 0000 - 0x0800 07FF 0x0800 0800 - 0x0800 0FFF 0x0800 1000 - 0x0800 17FF 0x0800 1800 - 0x0800 1FFF . . . 0x0803 F800 - 0x0803 FFFF 0x1FFF B000 - 0x1FFF F7FF 0x1FFF F800 - 0x1FFF F80F 2 Kbytes 2 Kbytes 2 Kbytes 2 Kbytes . . . 2 Kbytes 18 Kbytes 16 57/1128 DocID13902 Rev 15 RM0008 Memory and bus architecture Table 7. Flash module organization (connectivity line devices) (continued) Block Name Base addresses Size (bytes) FLASH_ACR 0x4002 2000 - 0x4002 2003 4 FLASH_KEYR 0x4002 2004 - 0x4002 2007 4 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4 Flash memory interface registers FLASH_SR FLASH_CR FLASH_AR 0x4002 200C - 0x4002 200F 4 0x4002 2010 - 0x4002 2013 4 0x4002 2014 - 0x4002 2017 4 Reserved 0x4002 2018 - 0x4002 201B 4 FLASH_OBR 0x4002 201C - 0x4002 201F 4 FLASH_WRPR 0x4002 2020 - 0x4002 2023 4 Table 8. XL-density Flash module organization Block Name Base addresses Bank 1 Main memory Page 0 Page 1 ... Page 255 Page 256 Page 257 0x0800 0000 - 0x0800 07FF 0x0800 0800 - 0x0800 0FFF ... 0x0807 F800 - 0x0807 FFFF 0x0808 0000 - 0x0808 07FF 0x0808 0800 - 0x0808 0FFF Bank 2 Information block . . . Page 511 System memory Option bytes . . . 0x080F F800 - 0x080F FFFF 0x1FFF E000 - 0x1FFF F7FF 0x1FFF F800 - 0x1FFF F80F Size (bytes) 2 Kbytes 2 Kbytes ... 2 Kbytes 2 Kbytes 2 Kbytes . . . 2 Kbytes 6 Kbytes 16 DocID13902 Rev 15 58/1128 63 Memory and bus architecture RM0008 Table 8. XL-density Flash module organization (continued) Block Name Base addresses Size (bytes) FLASH_ACR 0x4002 2000 - 0x4002 2003 4 FLASH_KEYR 0x4002 2004 - 0x4002 2007 4 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4 FLASH_SR 0x4002 200C - 0x4002 200F 4 FLASH_CR 0x4002 2010 - 0x4002 2013 4 FLASH_AR 0x4002 2014 - 0x4002 2017 4 Reserved 0x4002 2018 - 0x4002 201B 4 Flash memory interface registers FLASH_OBR 0x4002 201C - 0x4002 201F 4 FLASH_WRPR 0x4002 2020 - 0x4002 2023 4 Reserved 0x4002 2024 - 0x4002 2043 32 FLASH_KEYR2 0x4002 2044 - 0x4002 2047 4 Reserved 0x4002 2048 - 0x4002 204B 4 FLASH_SR2 0x4002 204C - 0x4002 204F 4 FLASH_CR2 0x4002 2050 - 0x4002 2053 4 FLASH_AR2 0x4002 2054 - 0x4002 2057 4 Note: Note: For further information on the Flash memory interface registers, please refer to the: “STM32F10xxx XL-density Flash programming manual” (PM0068) for XL-density devices “STM32F10xxx Flash programming manual” (PM0075) for other devices Reading the Flash memory Flash memory instructions and data access are performed through the AHB bus. The prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed in the Flash memory interface, and priority is given to data access on the DCode bus. Read accesses can be performed with the following configuration options: • Latency: number of wait states for a read operation programmed on-the-fly • Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be replaced with a single read from the Flash memory as the size of the block matches the bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is possible as the CPU fetches one word at a time with the next word readily available in the prefetch buffer • Half cycle: for power optimization These options should be used in accordance with the Flash memory access time. The wait states represent the ratio of the SYSCLK (system clock) period to the Flash memory access time: zero wait state, if 0 < SYSCLK ≤ 24 MHz one wait state, if 24 MHz < SYSCLK ≤ 48 MHz two wait states, if 48 MHz < SYSCLK ≤ 72 MHz Half cycle configuration is not available in combination with a prescaler on the AHB. The system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be 59/1128 DocID13902 Rev 15 RM0008 Memory and bus architecture used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or the HSE but not from the PLL. The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz and no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch buffer is usually switched on/off during the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator. Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode instructions. The DMA provides one free cycle after each transfer. Some instructions can be performed together with DMA transfer. Programming and erasing the Flash memory The Flash memory can be programmed 16 bits (half words) at a time. For write and erase operations on the Flash memory (write/erase), the internal RC oscillator (HSI) must be ON. The Flash memory erase operation can be performed at page level or on the whole Flash area (mass-erase). The mass-erase does not affect the information blocks. To ensure that there is no over-programming, the Flash Programming and Erase Controller blocks are clocked by a fixed clock. The End of write operation (programming or erasing) can trigger an interrupt. This interrupt can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the interrupt is served only after an exit from WFI. The FLASH_ACR register is used to enable/disable prefetch and half cycle access, and to control the Flash memory access time according to the CPU frequency. The tables below provide the bit map and bit descriptions for this register. For complete information on Flash memory operations and register configurations, please refer to the STM32F10xxx Flash programming manual (PM0075) or to the XL STM32F10xxx Flash programming manual (PM0068). DocID13902 Rev 15 60/1128 63 Memory and bus architecture RM0008 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PRFTBS PRFTBE HLFCYA r rw rw LATENCY rw rw rw Bits 31:6 Reserved, must be kept at reset value. Bit 5 PRFTBS: Prefetch buffer status This bit provides the status of the prefetch buffer. 0: Prefetch buffer is disabled 1: Prefetch buffer is enabled Bit 4 PRFTBE: Prefetch buffer enable 0: Prefetch is disabled 1: Prefetch is enabled Bit 3 HLFCYA: Flash half cycle access enable 0: Half cycle is disabled 1: Half cycle is enabled Bits 2:0 LATENCY: Latency These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time. 000 Zero wait state, if 0 < SYSCLK≤ 24 MHz 001 One wait state, if 24 MHz < SYSCLK ≤ 48 MHz 010 Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz 3.4 Boot configuration In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as shown in Table 9. Boot mode selection pins BOOT1 x 0 1 BOOT0 0 1 1 Table 9. Boot modes Boot mode Aliasing Main Flash memory System memory Embedded SRAM Main Flash memory is selected as boot space System memory is selected as boot space Embedded SRAM is selected as boot space 61/1128 DocID13902 Rev 15 RM0008 Memory and bus architecture Note: Note: The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot mode. The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004. Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address 0x2000 0000 (accessed through the system bus). The Cortex®-M3 CPU always fetches the reset vector on the ICode bus, which implies to have the boot space available only in the code area (typically, Flash memory). STM32F10xxx microcontrollers implement a special mechanism to be able to boot also from SRAM and not only from main Flash memory and System memory. Depending on the selected boot mode, main Flash memory, system memory or SRAM is accessible as follows: • Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x800 0000. • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in connectivity line devices, 0x1FFF F000 in other devices). • Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000. When booting from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register. For XL-density devices, when booting from the main Flash memory, you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by clearing the BFB2 bit in the user option bytes. When this bit is cleared and the boot pins are in the boot from main Flash memory configuration, the device boots from system memory, and the boot loader jumps to execute the user application programmed in Flash memory bank 2. For further details, please refer to AN2606. When booting from Bank2 in the applications initialization code, relocate the vector table to the Bank2 base address. (0x0808 0000) using the NVIC exception table and offset register. Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory with one of the available serial interfaces: • In low-, medium- and high-density devices the bootoader is activated through the USART1 interface. • In XL-density devices the boot loader is activated through the following interfaces: USART1 or USART2 (remapped). • In connectivity line devices the boot loader can be activated through one of the following interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in Device mode (DFU: device firmware upgrade). DocID13902 Rev 15 62/1128 63 Memory and bus architecture RM0008 Note: The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present. For further details, please refer to AN2606. 63/1128 DocID13902 Rev 15 RM0008 4 CRC calculation unit CRC calculation unit Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. 4.1 CRC introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 4.2 CRC main features • Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 – X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1 • Single input/output 32-bit data register • CRC computation done in 4 AHB clock cycles (HCLK) • General-purpose 8-bit register (can be used for temporary storage) The block diagram is shown in Figure 3. Figure 3. CRC calculation unit block diagram AHB bus 32-bit (read access) Data register (output) CRC computation (polynomial: 0x4C11DB7) 32-bit (write access) Data register (input) ai14968 DocID13902 Rev 15 64/1128 66 CRC calculation unit RM0008 4.3 CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: • is used as an input register to enter new data in the CRC calculator (when writing into the register) • holds the result of the previous CRC calculation (when reading the register) Each write operation into the data register creates a combination of the previous CRC value and the new one (CRC computation is done on the whole 32-bit data word, and not byte per byte). The write operation is stalled until the end of the CRC computation, thus allowing back-toback write accesses or consecutive write and read accesses. The CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the CRC_CR register. This operation does not affect the contents of the CRC_IDR register. 4.4 4.4.1 CRC registers The CRC calculation unit contains two data registers and a control register.The peripheral The CRC registers have to be accessed by words (32 bits). Data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DR [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR [15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 Data register bits Used as an input register when writing new data into the CRC calculator. Holds the previous CRC calculation result when it is read. 4.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IDR[7:0] rw rw rw rw rw rw rw rw 65/1128 DocID13902 Rev 15 RM0008 CRC calculation unit Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register. 4.4.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Reserved Bits 31:1 Reserved, must be kept at reset value. Bit 0 RESET bit Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF. This bit can only be set, it is automatically cleared by hardware. 17 16 1 0 RESET w 4.4.4 CRC register map The following table the CRC register map and reset values. Table 10. CRC calculation unit register map and reset values Offset Register 31-24 23-16 15-8 7 6 5 4 3 2 1 0x00 CRC_DR Reset value Data register 0xFFFF FFFF 0x04 CRC_IDR Reset value Reserved Independent data register 0x00 0x08 CRC_CR Reset value Reserved 0 RESET 0 DocID13902 Rev 15 66/1128 66 Power control (PWR) 5 Power control (PWR) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F101xx family, unless otherwise specified. 5.1 Power supplies The device requires a 2.0-to-3.6 V operating voltage supply (VDD). An embedded regulator is used to supply the internal 1.8 V digital power. The real-time clock (RTC) and backup registers can be powered from the VBAT voltage when the main VDD supply is powered off. 67/1128 DocID13902 Rev 15 RM0008 Power control (PWR) Figure 4. Power supply overview (VSSA) VREF(from 2.4 V up to VDDA)VREF+ (VDD) VDDA (VSS) VSSA VDDA domain A/D converter D/A converter Temp. sensor Reset block PLL VDD domain 1.8 V domain I/O Ring VSS Core Standby circuitry Memories VDD (Wakeup logic, digital IWDG) peripherals Voltage Regulator VBAT Low voltage detector Backup domain LSE crystal 32K osc BKP registers RCC BDCR register RTC 5.1.1 1. VDDA and VSSA must be connected to VDD and VSS, respectively. Independent A/D and D/A converter supply and reference voltage To improve conversion accuracy, the ADC and the DAC have an independent power supply which can be separately filtered and shielded from noise on the PCB. • The ADC and DAC voltage supply input is available on a separate VDDA pin. • An isolated supply ground connection is provided on pin VSSA. When available (according to package), VREF- must be tied to VSSA. On 100-pin and 144-pin packages To ensure a better accuracy on low-voltage inputs and outputs, the user can connect a separate external reference voltage on VREF+. VREF+ is the highest voltage, represented by the full scale value, for an analog input (ADC) or output (DAC) signal. The voltage on VREF+ can range from 2.4 V to VDDA. On 64-pin packages and packages with less pins The VREF+ and VREF- pins are not available, they are internally connected to the ADC voltage supply (VDDA) and ground (VSSA). DocID13902 Rev 15 68/1128 80 Power control (PWR) RM0008 5.1.2 Battery backup domain To retain the content of the Backup registers and supply the RTC function when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing the RTC to operate even when the main digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the Power Down Reset embedded in the Reset block. Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR is detected, the power switch between VBAT and VDD remains connected to VBAT. During the startup phase, if VDD is established in less than tRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO) and VDD > VBAT + 0.6 V, a current may be injected into VBAT through an internal diode connected between VDD and the power switch (VBAT). If the power supply/battery connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the VBAT pin. Note: If no external battery is used in the application, it is recommended to connect VBAT externally to VDD with a 100 nF external ceramic decoupling capacitor (for more details refer to AN2586). When the backup domain is supplied by VDD (analog switch connected to VDD), the following functions are available: • PC14 and PC15 can be used as either GPIO or LSE pins • PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or second output (refer to Section 6: Backup registers (BKP) on page 81) Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). When the backup domain is supplied by VBAT (analog switch connected to VBAT because VDD is not present), the following functions are available: • PC14 and PC15 can be used as LSE pins only • PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to section Section 6.4.2: RTC clock calibration register (BKP_RTCCR) on page 83). 69/1128 DocID13902 Rev 15 RM0008 Power control (PWR) 5.1.3 Voltage regulator The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes. • In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals). • In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving contents of registers and SRAM • In Standby Mode, the regulator is powered off. The contents of the registers and SRAM are lost except for the Standby circuitry and the Backup Domain. 5.2 5.2.1 Power supply supervisor Power on reset (POR)/power down reset (PDR) The device has an integrated POR/PDR circuitry that allows proper operation starting from/down to 2 V. The device remains in Reset mode when VDD/VDDA is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. For more details concerning the power on/power down reset threshold, refer to the electrical characteristics of the datasheet. Figure 5. Power on reset/power down reset waveform VDD/VDDA POR 40 mV hysteresis PDR Temporization tRSTTEMPO Reset 5.2.2 Programmable voltage detector (PVD) You can use the PVD to monitor the VDD/VDDA power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR). The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The DocID13902 Rev 15 70/1128 80 Power control (PWR) RM0008 PVD output interrupt can be generated when VDD/VDDA drops below the PVD threshold and/or when VDD/VDDA rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. VDD/VDDA Figure 6. PVD thresholds PVD threshold 100 mV hysteresis PVD output 71/1128 DocID13902 Rev 15 RM0008 Power control (PWR) 5.3 Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several lowpower modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources. The STM32F10xxx devices feature three low-power modes: • Sleep mode (CPU clock off, all peripherals including Cortex®-M3 core peripherals like NVIC, SysTick, etc. are kept running) • Stop mode (all clocks are stopped) • Standby mode (1.8V domain powered-off) In addition, the power consumption in Run mode can be reduce by one of the following means: • Slowing down the system clocks • Gating the clocks to the APB and AHB peripherals when they are unused. Table 11. Low-power mode summary Mode name Entry wakeup Effect on 1.8V domain clocks Effect on VDD domain clocks Voltage regulator Sleep (Sleep now or Sleep-on exit) WFI WFE Any interrupt CPU clock OFF Wakeup event no effect on other clocks or analog None ON clock sources Stop Standby PDDS and LPDS bits + SLEEPDEEP bit + WFI or WFE PDDS bit + SLEEPDEEP bit + WFI or WFE Any EXTI line (configured in the EXTI registers) WKUP pin rising edge, RTC alarm, external reset in NRST pin, IWDG reset All 1.8V domain clocks OFF ON or in lowpower mode (depends on Power control HSI and register HSE (PWR_CR)) oscillators OFF OFF 5.3.1 Slowing down system clocks In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode. For more details refer to Section 7.3.2: Clock configuration register (RCC_CFGR). DocID13902 Rev 15 72/1128 80 Power control (PWR) RM0008 5.3.2 5.3.3 Peripheral clock gating In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. Peripheral clock gating is controlled by the AHB peripheral clock enable register (RCC_AHBENR), APB1 peripheral clock enable register (RCC_APB1ENR) and APB2 peripheral clock enable register (RCC_APB2ENR). Sleep mode Entering Sleep mode The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions. Two options are available to select the Sleep mode entry mechanism, depending on the SLEEPONEXIT bit in the Cortex®-M3 System Control register: • Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed. • Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as it exits the lowest priority ISR. In the Sleep mode, all I/O pins keep the same state as in the Run mode. Refer to Table 12 and Table 13 for details on how to enter Sleep mode. Exiting Sleep mode If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as an event occurs. The wakeup event can be generated either by: • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex®-M3 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. • or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit. Refer to Table 12 and Table 13 for more details on how to exit Sleep mode. 73/1128 DocID13902 Rev 15 RM0008 Power control (PWR) Sleep-now mode Mode entry Mode exit Wakeup latency Table 12. Sleep-now Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 0 Refer to the Cortex®-M3 System Control register. If WFI was used for entry: Interrupt: Refer to Section 10.1.2: Interrupt and exception vectors on page 197 If WFE was used for entry Wakeup event: Refer to Section 10.2.3: Wakeup event management None Sleep-on-exit Mode entry Mode exit Wakeup latency Table 13. Sleep-on-exit Description WFI (wait for interrupt) while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 Refer to the Cortex®-M3 System Control register. Interrupt: refer to Section 10.1.2: Interrupt and exception vectors on page 197. None 5.3.4 Stop mode The Stop mode is based on the Cortex®-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved. In the Stop mode, all I/O pins keep the same state as in the Run mode. Entering Stop mode Refer to Table 14 for details on how to enter the Stop mode. To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPDS bit of the Power control register (PWR_CR). If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished. If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished. In Stop mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See DocID13902 Rev 15 74/1128 80 Power control (PWR) RM0008 Note: Section 19.3: IWDG functional description in Section 19: Independent watchdog (IWDG). • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR). The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0. If the application needs to disable the external clock before entering Stop mode, the HSEON bit must first be disabled and the system clock switched to HSI. Otherwise, if the HSEON bit remains enabled and the external clock (external oscillator) is removed when entering Stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering stop mode. Exiting Stop mode Refer to Table 14 for more details on how to exit Stop mode. When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock. When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced. Stop mode Mode entry Mode exit Wakeup latency Table 14. Stop mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP bit in Cortex®-M3 System Control register – Clear PDDS bit in Power Control register (PWR_CR) – Select the voltage regulator mode by configuring LPDS bit in PWR_CR Note: To enter Stop mode, all EXTI Line pending bits (in Pending register (EXTI_PR)), all peripheral interrupt pending bits, and RTC Alarm flag must be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues. If WFI was used for entry: Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). Refer to Section 10.1.2: Interrupt and exception vectors on page 197. If WFE was used for entry: Any EXTI Line configured in event mode. Refer to Section 10.2.3: Wakeup event management on page 206 HSI RC wakeup time + regulator wakeup time from Low-power mode 75/1128 DocID13902 Rev 15 RM0008 Power control (PWR) 5.3.5 Standby mode The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex®-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry (see Figure 4). Entering Standby mode Refer to Table 15 for more details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 19.3: IWDG functional description in Section 19: Independent watchdog (IWDG). • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR). • External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR) Exiting Standby mode The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or the rising edge of an RTC alarm occurs (see Figure 179: RTC simplified block diagram). All registers are reset after wakeup from Standby except for Power control/status register (PWR_CSR). After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power control/status register (PWR_CSR) indicates that the MCU was in Standby mode. Refer to Table 15 for more details on how to exit Standby mode. Standby mode Mode entry Mode exit Wakeup latency Table 15. Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – Set SLEEPDEEP in Cortex®-M3 System Control register – Set PDDS bit in Power Control register (PWR_CR) – Clear WUF bit in Power Control/Status register (PWR_CSR) WKUP pin rising edge, RTC alarm event’s rising edge, external Reset in NRST pin, IWDG Reset. Reset phase DocID13902 Rev 15 76/1128 80 Power control (PWR) RM0008 5.3.6 I/O states in Standby mode In Standby mode, all I/O pins are high impedance except: • Reset pad (still available) • TAMPER pin if configured for tamper or calibration out • WKUP pin, if enabled Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex®-M3 core is no longer clocked. However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 31.16.1: Debug support for low-power modes. Auto-wakeup (AWU) from low-power mode The RTC can be used to wakeup the MCU from low-power mode without depending on an external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR): • Low-power 32.768 kHz external crystal oscillator (LSE OSC). This clock source provides a precise time base with very low-power consumption (less than 1µA added consumption in typical conditions) • Low-power internal RC Oscillator (LSI RC) This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to add minimum power consumption. To wakeup from Stop mode with an RTC alarm event, it is necessary to: • Configure the EXTI Line 17 to be sensitive to rising edge • Configure the RTC to generate the RTC alarm To wakeup from Standby mode, there is no need to configure the EXTI Line 17. 5.4 5.4.1 Power control registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). Power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 Reserved 9 8 7 6 5 4 3 2 1 0 DBP PLS[2:0] PVDE CSBF CWUF PDDS LPDS rw rw rw rw rw rc_w1 rc_w1 rw rw 77/1128 DocID13902 Rev 15 RM0008 Power control (PWR) Bits 31:9 Reserved, must be kept at reset value.. Bit 8 DBP: Disable backup domain write protection. In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1. Bits 7:5 PLS[2:0]: PVD level selection. These bits are written by software to select the voltage threshold detected by the Power Voltage Detector 000: 2.2V 001: 2.3V 010: 2.4V 011: 2.5V 100: 2.6V 101: 2.7V 110: 2.8V 111: 2.9V Note: Refer to the electrical characteristics of the datasheet for more details. Bit 4 PVDE: Power voltage detector enable. This bit is set and cleared by software. 0: PVD disabled 1: PVD enabled Bit 3 CSBF: Clear standby flag. This bit is always read as 0. 0: No effect 1: Clear the SBF Standby Flag (write). Bit 2 CWUF: Clear wakeup flag. This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write) Bit 1 PDDS: Power down deepsleep. This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the LPDS bit. 1: Enter Standby mode when the CPU enters Deepsleep. Bit 0 LPDS: Low-power deepsleep. This bit is set and cleared by software. It works together with the PDDS bit. 0: Voltage regulator on during Stop mode 1: Voltage regulator in low-power mode during Stop mode DocID13902 Rev 15 78/1128 80 Power control (PWR) RM0008 5.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 Reserved 9 8 7 EWUP rw 6 5 4 Reserved 3 2 1 0 PVDO SBF WUF r r r Bits 31:9 Reserved, must be kept at reset value. Bit 8 EWUP: Enable WKUP pin This bit is set and cleared by software. 0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the device from Standby mode. 1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin wakes-up the system from Standby mode). Note: This bit is reset by a system Reset. Bits 7:3 Reserved, must be kept at reset value. Bit 2 PVDO: PVD output This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. 0: VDD/VDDA is higher than the PVD threshold selected with the PLS[2:0] bits. 1: VDD/VDDA is lower than the PVD threshold selected with the PLS[2:0] bits. Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set. Bit 1 SBF: Standby flag This bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset) or by setting the CSBF bit in the Power control register (PWR_CR) 0: Device has not been in Standby mode 1: Device has been in Standby mode Bit 0 WUF: Wakeup flag This bit is set by hardware and cleared by hardware, by a system reset or by setting the CWUF bit in the Power control register (PWR_CR) 0: No wakeup event occurred 1: A wakeup event was received from the WKUP pin or from the RTC alarm Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high. 79/1128 DocID13902 Rev 15 0 RM0008 5.4.3 PWR register map The following table summarizes the PWR registers. Table 16. PWR register map and reset values Power control (PWR) Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x000 PWR_CR Reset value 0x004 PWR_CSR Reset value Reserved Reserved EWUP DBP LPDS PDDS PVDO CWUF CSBF PVDE PLS [2:0] 000000000 WUF SBF Reserved 0 000 Refer to Table 3 on page 51 for the register boundary addresses. DocID13902 Rev 15 80/1128 80 Backup registers (BKP) 6 Backup registers (BKP) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F101xx family, unless otherwise specified. 6.1 BKP introduction The backup registers are forty two 16-bit registers for storing 84 bytes of user application data. They are implemented in the backup domain that remains powered on by VBAT when the VDD power is switched off. They are not reset when the device wakes up from Standby mode or by a system reset or power reset. In addition, the BKP control registers are used to manage the Tamper detection feature and RTC calibration. After reset, access to the Backup registers and RTC is disabled and the Backup domain (BKP) is protected against possible parasitic write access. To enable access to the Backup registers and the RTC, proceed as follows: • enable the power and backup interface clocks by setting the PWREN and BKPEN bits in the RCC_APB1ENR register • set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup registers and RTC. 6.2 BKP main features • 20-byte data registers (in medium-density and low-density devices) or 84-byte data registers (in high-density, XL-density and connectivity line devices) • Status/control register for managing tamper detection with interrupt capability • Calibration register for storing the RTC calibration value • Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on TAMPER pin PC13 (when this pin is not used for tamper detection) 81/1128 DocID13902 Rev 15 RM0008 Backup registers (BKP) 6.3 6.3.1 Note: 6.3.2 BKP functional description Tamper detection The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper detection event resets all data backup registers. However to avoid losing Tamper events, the signal used for edge detection is logically ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before the TAMPER pin is enabled. • When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while there was no rising edge on the TAMPER pin after TPE was set) • When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the TPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while there was no falling edge on the TAMPER pin after TPE was set) By setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper detection event occurs. After a Tamper event has been detected and cleared, the TAMPER pin should be disabled and then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again. This prevents software from writing to the backup data registers (BKP_DRx), while the TAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection on the TAMPER pin. Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting of the data backup registers, the TAMPER pin should be externally tied to the correct level. RTC calibration For measurement purposes, the RTC clock with a frequency divided by 64 can be output on the TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register (BKP_RTCCR). The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits. For more details about RTC calibration and how to use it to improve timekeeping accuracy, please refer to AN2604 "STM32F101xx and STM32F103xx RTC calibration”. DocID13902 Rev 15 82/1128 89 Backup registers (BKP) RM0008 6.4 BKP registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 D[15:0] Backup data These bits can be written with user data. Note: The BKP_DRx registers are not reset by a System reset or Power reset or when the device wakes up from Standby mode. They are reset by a Backup Domain reset or by a TAMPER pin event (if the TAMPER pin function is activated). 6.4.2 RTC clock calibration register (BKP_RTCCR) Address offset: 0x2C Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ASOS ASOE CCO CAL[6:0] rw rw rw rw rw rw rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bit 9 ASOS: Alarm or second output selection When the ASOE bit is set, the ASOS bit can be used to select whether the signal output on the TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal: 0: RTC Alarm pulse output selected 1: RTC Second pulse output selected Note: This bit is reset only by a Backup domain reset. 83/1128 DocID13902 Rev 15 RM0008 Backup registers (BKP) Bit 8 ASOE: Alarm or second output enable Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit. The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the ASOE bit is set. Note: This bit is reset only by a Backup domain reset. Bit 7 CCO: Calibration clock output 0: No effect 1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin. The TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted Tamper detection. Note: This bit is reset when the VDD supply is powered off. Bit 6:0 CAL[6:0]: Calibration value This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses. This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20 PPM. The clock of the RTC can be slowed down from 0 to 121PPM. 6.4.3 Backup control register (BKP_CR) Address offset: 0x30 Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TPAL TPE rw rw Bits 15:2 Reserved, must be kept at reset value. Bit 1 TPAL: TAMPER pin active level 0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set). 1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set). Bit 0 TPE: TAMPER pin enable 0: The TAMPER pin is free for general purpose I/O 1: Tamper alternate I/O function is activated. Note: 6.4.4 Setting the TPAL and TPE bits at the same time is always safe, however resetting both at the same time can generate a spurious Tamper event. For this reason it is recommended to change the TPAL bit only when the TPE bit is reset. Backup control/status register (BKP_CSR) Address offset: 0x34 Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 Reserved TIF TEF r r 6 5 4 Reserved 3 2 1 0 TPIE CTI CTE rw w w DocID13902 Rev 15 84/1128 89 Backup registers (BKP) RM0008 Bits 15:10 Reserved, must be kept at reset value. Bit 9 TIF: Tamper interrupt flag This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is reset. 0: No Tamper interrupt 1: A Tamper interrupt occurred Note: This bit is reset only by a system reset and wakeup from Standby mode. Bit 8 TEF: Tamper event flag This bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the CTE bit. 0: No Tamper event 1: A Tamper event occurred Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the TEF bit is set. If a write to the BKP_DRx registers is performed while this bit is set, the value will not be stored. Bits 7:3 Reserved, must be kept at reset value. Bit 2 TPIE: TAMPER pin interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register Note: A Tamper interrupt does not wake up the core from low-power modes. This bit is reset only by a system reset and wakeup from Standby mode. Bit 1 CTI: Clear tamper interrupt This bit is write only, and is always read as 0. 0: No effect 1: Clear the Tamper interrupt and the TIF Tamper interrupt flag. Bit 0 CTE: Clear tamper event This bit is write only, and is always read as 0. 0: No effect 1: Reset the TEF Tamper event flag (and the Tamper detector) 6.4.5 BKP register map BKP registers are mapped as 16-bit addressable registers as described in the table below: Table 17. BKP register map and reset values Offset Register 0x00 0x04 BKP_DR1 Reset value Reserved Reserved D[15:0] 0000000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 85/1128 DocID13902 Rev 15 RM0008 Backup registers (BKP) Table 17. BKP register map and reset values (continued) Offset Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2 0x30 0x34 0x38 BKP_DR2 Reset value BKP_DR3 Reset value BKP_DR4 Reset value BKP_DR5 Reset value BKP_DR6 Reset value BKP_DR7 Reset value BKP_DR8 Reset value BKP_DR9 Reset value BKP_DR10 Reset value BKP_RTCCR Reset value BKP_CR Reset value BKP_CSR Reset value 0x3C 0x40 BKP_DR11 Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ASOS ASOE D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 CAL[6:0] 0000000000 CCO TPE TPAL Reserved 00 CTE CTI TPIE TEF TIF Reserved Reserved Reserved 00 Reserved 000 Reserved D[15:0] 0000000000000000 DocID13902 Rev 15 86/1128 89 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Backup registers (BKP) Table 17. BKP register map and reset values (continued) Offset Register RM0008 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 BKP_DR12 Reset value BKP_DR13 Reset value BKP_DR14 Reset value BKP_DR15 Reset value BKP_DR16 Reset value BKP_DR17 Reset value BKP_DR18 Reset value BKP_DR19 Reset value BKP_DR20 Reset value BKP_DR21 Reset value BKP_DR22 Reset value BKP_DR23 Reset value BKP_DR24 Reset value BKP_DR25 Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 87/1128 DocID13902 Rev 15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0008 Backup registers (BKP) Table 17. BKP register map and reset values (continued) Offset Register 0x7C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 BKP_DR26 Reset value BKP_DR27 Reset value BKP_DR28 Reset value BKP_DR29 Reset value BKP_DR30 Reset value BKP_DR31 Reset value BKP_DR32 Reset value BKP_DR33 Reset value BKP_DR34 Reset value BKP_DR35 Reset value BKP_DR36 Reset value BKP_DR37 Reset value BKP_DR38 Reset value BKP_DR39 Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 DocID13902 Rev 15 88/1128 89 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Backup registers (BKP) Table 17. BKP register map and reset values (continued) Offset Register RM0008 0xB4 0xB8 0xBC BKP_DR40 Reset value BKP_DR41 Reset value BKP_DR42 Reset value Reserved Reserved Reserved D[15:0] 0000000000000000 D[15:0] 0000000000000000 D[15:0] 0000000000000000 Refer to Table 3 on page 51 for the register boundary addresses. 89/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7 Low-, medium-, high- and XL-density reset and clock control (RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to low-, medium-, high- and XL-density STM32F10xxx devices. Connectivity line devices are discussed in a separate section (refer to Connectivity line devices: reset and clock control (RCC) on page 123). 7.1 7.1.1 Reset There are three types of reset, defined as system reset, power reset and backup domain reset. System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 4). A system reset is generated when one of the following events occurs: 1. A low level on the NRST pin (external reset) 2. Window watchdog end of count condition (WWDG reset) 3. Independent watchdog end of count condition (IWDG reset) 4. A software reset (SW reset) (see Software reset) 5. Low-power management reset (see Low-power management reset) The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 7.3.10: Control/status register (RCC_CSR)). Software reset The SYSRESETREQ bit in Cortex®-M3 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex®-M3 programming manual (see Related documents on page 1) for more details. DocID13902 Rev 15 90/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.1.2 Low-power management reset There are two ways to generate a low-power management reset: 1. Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode. 2. Reset when entering Stop mode: This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode. For further information on the User Option Bytes, refer to the STM32F10xxx Flash programming manual. Power reset A power reset is generated when one of the following events occurs: 1. Power-on/power-down reset (POR/PDR reset) 2. When exiting Standby mode A power reset sets all registers to their reset values except the Backup domain (see Figure 4) These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each reset source (external or internal reset). In case of an external reset, the reset pulse is generated while the NRST pin is asserted low. Figure 7. Simplified diagram of the reset circuit 9''9''$ ([WHUQDO UHVHW 1567 538 )LOWHU 6\VWHPUHVHW 3XOVH JHQHUDWRU PLQ—V ::'*UHVHW ,:'*UHVHW 3RZHUUHVHW 6RIWZDUHUHVHW /RZSRZHUPDQDJHPHQWUHVHW DLF 91/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.1.3 Backup domain reset The backup domain has two specific resets that affect only the backup domain (see Figure 4). A backup domain reset is generated when one of the following events occurs: 1. Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). 2. VDD or VBAT power on, if both supplies have previously been powered off. 7.2 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): • HSI oscillator clock • HSE oscillator clock • PLL clock The devices have the following two secondary clock sources: • 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode. • 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real- time clock (RTCCLK) Each clock source can be switched on or off independently when it is not used, to optimize power consumption. DocID13902 Rev 15 92/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 /3#?/54 /3#?). /3#?). /3#?/54 Figure 8. Clock tree &,)4&#,+ TO&LASHPROGRAMMINGINTERFACE 53" 0RESCALER   -(Z 53"#,+ TO53"INTERFACE )3#,+ TO)3 0ERIPHERALCLOCK ENABLE )3#,+ TO)3 -(Z (3)2# (3)  0,,32# 0,,-5,  X X X X 0,, 0ERIPHERALCLOCK ENABLE 0ERIPHERALCLOCK ENABLE 0ERIPHERALCLOCK ENABLE -(ZMAX #LOCK %NABLE 37  (3) 0,,#,+ (3% 393#,+ !(" -(Z MAX 0RESCALER   !0" 0RESCALER      3$)/#,+ TO3$)/ &3-##,+ TO&3-# (#,+ TO!("BUS CORE MEMORYAND$-! TO#ORTEX3YSTEMTIMER &#,+#ORTEX FREERUNNINGCLOCK -(ZMAX 0#,+ TO!0" 0ERIPHERAL#LOCK PERIPHERALS %NABLE #33 4)-         )F!0"PRESCALER X ELSEX TO4)-         4)-8#,+ 0ERIPHERAL#LOCK %NABLE  -(Z (3%/3# 0,,8402%  ,3%/3# K(Z  ,3% TO24# 24##,+ !0" 0RESCALER      -(ZMAX 0#,+ PERIPHERALSTO!0" 0ERIPHERAL#LOCK %NABLE 4)-    TIMERS )F!0"PRESCALER X ELSEX TO4)-   AND 4)-X#,+ 0ERIPHERAL#LOCK !$# %NABLE TO!$# OR 0RESCALER     !$##,+-(ZMAX ,3)2# K(Z 24#3%,;= ,3) TO)NDEPENDENT7ATCHDOG)7$' )7$'#,+  (#,+ 4O 3$)/!("INTERFACE 0ERIPHERALCLOCK ENABLE -#/ -AIN  #LOCK/UTPUT -#/ 0,,#,+ (3) (3% 393#,+ ,EGEND (3%(IGH SPEEDEXTERNALCLOCKSIGNAL (3) (IGH SPEEDINTERNALCLOCKSIGNAL ,3),OW SPEEDINTERNALCLOCKSIGNAL ,3%,OW SPEEDEXTERNALCLOCKSIGNAL AIE 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet. Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz. The SDIO AHB interface is clocked with a fixed frequency equal to HCLK/2 The RCC feeds the Cortex® System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex® clock (HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8. The Flash memory programming interface clock (FLITFCLK) is always the HSI clock. 93/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.2.1 The timer clock frequencies are automatically fixed by hardware. There are two cases: 1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected. FCLK acts as Cortex®-M3’s free-running clock. For more details refer to the ARM® Cortex™-M3 r1p1 Technical Reference Manual (TRM). HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. Clock source Figure 9. HSE/ LSE clock sources Hardware configuration External clock OSC_OUT External source (HiZ) Crystal/Ceramic resonators OSC_IN OSC_OUT CL1 CL2 Load capacitors DocID13902 Rev 15 94/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.2.2 External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 25 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 9. External crystal/ceramic resonator (HSE crystal) The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 9. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). The HSE Crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR). HSI clock The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input. The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator. Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at TA=25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control register (RCC_CR). If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the Clock control register (RCC_CR). The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware. The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 97. 95/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.2.3 7.2.4 7.2.5 Note: PLL The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock frequency. Refer to Figure 8 and Clock control register (RCC_CR). The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL enabled, these parameters cannot be changed. An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt register (RCC_CIR). If the USB interface is used in the application, the PLL must be programmed to output 48 or 72 MHz. This is needed to provide a 48 MHz USBCLK. LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. The LSE crystal is switched on and off using the LSEON bit in Backup domain control register (RCC_BDCR). The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z. See Figure 9. LSI clock The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets. The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR). The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). LSI calibration is only available on high-density, XL-density and connectivity line devices. DocID13902 Rev 15 96/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.2.6 7.2.7 Note: LSI calibration The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy. This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout. Use the following procedure to calibrate the LSI: 1. Enable TIM5 timer and configure channel4 in input capture mode 2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose. 3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or interrupt. 4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout. System clock (SYSCLK) selection After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as system clock. Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock failure event is sent to the break input of the advanced-control timers (TIM1 and TIM8) and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex®-M3 NMI (Non-Maskable Interrupt) exception vector. Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too. 97/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.2.8 7.2.9 7.2.10 RTC clock The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain. The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: • If LSE is selected as RTC clock: – The RTC continues to work even if the VDD supply is switched off, provided the VBAT supply is maintained. • If LSI is selected as Auto-Wakeup unit (AWU) clock: – The AWU state is not guaranteed if the VDD supply is powered off. Refer to Section 7.2.5: LSI clock on page 96 for more details on LSI calibration. • If the HSE clock divided by 128 is used as the RTC clock: – The RTC state is not guaranteed if the VDD supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain). – The DPB bit (disable backup domain write protection) in the Power controller register must be set to 1 (refer to Section 5.4.1: Power control register (PWR_CR)). Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 4 clock signals can be selected as the MCO clock. • SYSCLK • HSI • HSE • PLL clock divided by 2 The selection is controlled by the MCO[2:0] bits of the Clock configuration register (RCC_CFGR). DocID13902 Rev 15 98/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3 7.3.1 RCC registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLL RDY r PLLON rw Reserved CSS ON rw HSE BYP rw HSE RDY r HSE ON rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSICAL[7:0] HSITRIM[4:0] Res. HSI RDY HSION r r r r r r r r rw rw rw rw rw r rw Bits 31:26 Reserved, must be kept at reset value. Bit 25 PLLRDY: PLL clock ready flag Set by hardware to indicate that the PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: PLL enable Set and cleared by software to enable PLL. Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. 0: PLL OFF 1: PLL ON Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. 0: Clock detector OFF 1: Clock detector ON (Clock detector ON if the HSE oscillator is ready , OFF if not). Bit 18 HSEBYP: External high-speed clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0: external 4-16 MHz oscillator not bypassed 1: external 4-16 MHz oscillator bypassed with external clock Bit 17 HSERDY: External high-speed clock ready flag Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE oscillator clock to fall down after HSEON reset. 0: HSE oscillator not ready 1: HSE oscillator ready 99/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration These bits are initialized automatically at startup. Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC. The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ± 1%. The trimming step (Fhsitrim) is around 40 kHz between two consecutive HSICAL steps. Bit 2 Reserved, must be kept at reset value. Bit 1 HSIRDY: Internal high-speed clock ready flag Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles. 0: internal 8 MHz RC oscillator not ready 1: internal 8 MHz RC oscillator ready Bit 0 HSION: Internal high-speed clock enable Set and cleared by software. Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby mode or in case of failure of the external 4-16 MHz oscillator used directly or indirectly as system clock. This bit cannot be reset if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock. 0: internal 8 MHz RC oscillator OFF 1: internal 8 MHz RC oscillator ON DocID13902 Rev 15 100/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. 31 30 29 28 27 Reserved 15 14 ADCPRE[1:0] rw rw 13 12 11 PPRE2[2:0] rw rw rw 26 25 24 MCO[2:0] rw rw rw 10 9 8 PPRE1[2:0] rw rw rw 23 Res. 7 rw 22 21 USB PRE rw rw 6 5 HPRE[3:0] rw rw 20 19 18 PLLMUL[3:0] rw rw rw 4 3 2 SWS[1:0] rw r r 17 16 PLL PLL XTPRE SRC rw rw 1 0 SW[1:0] rw rw Bits 31:27 Reserved, must be kept at reset value. Bits 26:24 MCO: Microcontroller clock output Set and cleared by software. 0xx: No clock 100: System clock (SYSCLK) selected 101: HSI clock selected 110: HSE clock selected 111: PLL clock divided by 2 selected Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. When the System Clock is selected to output to the MCO pin, make sure that this clock does not exceed 50 MHz (the maximum IO speed). Bit 22 USBPRE: USB prescaler Set and cleared by software to generate 48 MHz USB clock. This bit must be valid before enabling the USB clock in the RCC_APB1ENR register. This bit can’t be reset if the USB clock is enabled. 0: PLL clock is divided by 1.5 1: PLL clock is not divided 101/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bits 21:18 PLLMUL: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 72 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4 0011: PLL input clock x 5 0100: PLL input clock x 6 0101: PLL input clock x 7 0110: PLL input clock x 8 0111: PLL input clock x 9 1000: PLL input clock x 10 1001: PLL input clock x 11 1010: PLL input clock x 12 1011: PLL input clock x 13 1100: PLL input clock x 14 1101: PLL input clock x 15 1110: PLL input clock x 16 1111: PLL input clock x 16 Bit 17 PLLXTPRE: HSE divider for PLL entry Set and cleared by software to divide HSE before PLL entry. This bit can be written only when PLL is disabled. 0: HSE clock not divided 1: HSE clock divided by 2 Bit 16 PLLSRC: PLL entry clock source Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled. 0: HSI oscillator clock / 2 selected as PLL input clock 1: HSE oscillator clock selected as PLL input clock Bits 15:14 ADCPRE: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PCLK2 divided by 2 01: PCLK2 divided by 4 10: PCLK2 divided by 6 11: PCLK2 divided by 8 Bits 13:11 PPRE2: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB high-speed clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 DocID13902 Rev 15 102/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bits 10:8 PPRE1: APB low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB low-speed clock (PCLK1). Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain. 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 7:4 HPRE: AHB prescaler Set and cleared by software to control the division factor of the AHB clock. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. Refer to Reading the Flash memory on page 59 section for more details. Bits 3:2 SWS: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: HSI oscillator used as system clock 01: HSE oscillator used as system clock 10: PLL used as system clock 11: not applicable Bits 1:0 SW: System clock switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). 00: HSI selected as system clock 01: HSE selected as system clock 10: PLL selected as system clock 11: not allowed 103/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.3.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 15 14 13 Reserved 28 27 26 25 24 23 Reserved 12 11 10 PLL HSE HSI RDYIE RDYIE RDYIE rw rw rw 9 LSE RDYIE rw 8 LSI RDYIE rw CSSC w 7 CSSF r 22 21 Reserved 6 5 Reserved 20 PLL RDYC w 4 PLL RDYF r 19 HSE RDYC w 3 HSE RDYF r 18 HSI RDYC w 2 HSI RDYF r 17 LSE RDYC w 1 LSE RDYF r 16 LSI RDYC w 0 LSI RDYF r Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bits 22:21 Reserved, must be kept at reset value. Bit 20 PLLRDYC: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 0: No effect 1: PLLRDYF cleared Bit 19 HSERDYC: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0: No effect 1: HSERDYF cleared Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set software to clear the HSIRDYF flag. 0: No effect 1: HSIRDYF cleared Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 16 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: LSIRDYF cleared Bits 15:13 Reserved, must be kept at reset value. Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled DocID13902 Rev 15 104/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 4-16 MHz oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 8 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the external 4-16 MHz oscillator. Cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bits 6:5 Reserved, must be kept at reset value. Bit 4 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. Cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit3 HSERDYF: HSE ready interrupt flag Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set. Cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the external 4-16 MHz oscillator 1: Clock ready interrupt caused by the external 4-16 MHz oscillator 105/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set. Cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the external 32 kHz oscillator 1: Clock ready interrupt caused by the external 32 kHz oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set. Cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the internal RC 40 kHz oscillator 1: Clock ready interrupt caused by the internal RC 40 kHz oscillator 7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 15 ADC3 RST rw 14 USART1 RST rw 13 TIM8 RST rw 28 12 SPI1 RST rw 27 26 25 Reserved 11 TIM1 RST rw 10 ADC2 RST rw 9 ADC1 RST rw 24 8 IOPG RST rw 23 7 IOPF RST rw 22 6 IOPE RST rw 21 TIM11 RST 20 TIM10 RST rw rw 5 4 IOPD IOPC RST RST rw rw 19 TIM9 RST rw 3 IOPB RST rw 18 17 16 Reserved 2 IOPA RST rw 1 Res. Res. 0 AFIO RST rw Bits 31:22 Reserved, must be kept at reset value. Bit 21 TIM11RST: TIM11 timer reset Set and cleared by software. 0: No effect 1: Reset TIM11 timer Bit 20 TIM10RST: TIM10 timer reset Set and cleared by software. 0: No effect 1: Reset TIM10 timer Bit 19 TIM9RST: TIM9 timer reset Set and cleared by software. 0: No effect 1: Reset TIM9 timer Bits 18:16 Reserved, always read as 0. DocID13902 Rev 15 106/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 15 ADC3RST: ADC3 interface reset Set and cleared by software. 0: No effect 1: Reset ADC3 interface Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 TIM8RST: TIM8 timer reset Set and cleared by software. 0: No effect 1: Reset TIM8 timer Bit 12 SPI1RST: SPI1 reset Set and cleared by software. 0: No effect 1: Reset SPI1 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bit 10 ADC2RST: ADC 2 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 2 interface Bit 9 ADC1RST: ADC 1 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 1 interface Bit 8 IOPGRST: IO port G reset Set and cleared by software. 0: No effect 1: Reset IO port G Bit 7 IOPFRST: IO port F reset Set and cleared by software. 0: No effect 1: Reset IO port F Bit 6 IOPERST: IO port E reset Set and cleared by software. 0: No effect 1: Reset IO port E Bit 5 IOPDRST: IO port D reset Set and cleared by software. 0: No effect 1: Reset IO port D 107/1128 DocID13902 Rev 15 RM0008 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset IO port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset IO port B Bit 2 IOPARST: IO port A reset Set and cleared by software. 0: No effect 1: Reset IO port A Bit 1 Reserved, must be kept at reset value. Bit 0 AFIORST: Alternate function IO reset Set and cleared by software. 0: No effect 1: Reset Alternate Function DocID13902 Rev 15 108/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 Reserved 15 SPI3 RST rw 14 SPI2 RST rw 29 28 27 26 25 DAC PWR BKP RST RST RST Res. CAN RST rw rw 13 12 Reserved rw 11 WWDG RST rw rw 10 9 Reserved 24 Res. 8 TIM14 RST rw 23 22 USB RST I2C2 RST rw rw 7 6 TIM13 TIM12 RST RST rw rw 21 I2C1 RST rw 5 TIM7 RST rw 20 19 18 17 UART5 UART4 USART 3 USART 2 RST RST RST RST rw rw rw rw 4 3 2 1 TIM6 TIM5 RST RST TIM4 RST TIM3 RST rw rw rw rw 16 Res. 0 TIM2 RST rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACRST: DAC interface reset Set and cleared by software. 0: No effect 1: Reset DAC interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset power interface Bit 27 BKPRST: Backup interface reset Set and cleared by software. 0: No effect 1: Reset backup interface Bit 26 Reserved, must be kept at reset value. Bit 25 CANRST: CAN reset Set and cleared by software. 0: No effect 1: Reset CAN Bit 24 Reserved, always read as 0. Bit 23 USBRST: USB reset Set and cleared by software. 0: No effect 1: Reset USB Bit 22 I2C2RST: I2C2 reset Set and cleared by software. 0: No effect 1: Reset I2C2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C1 109/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 20 UART5RST: USART5 reset Set and cleared by software. 0: No effect 1: Reset USART5 Bit 19 UART4RST: USART4 reset Set and cleared by software. 0: No effect 1: Reset USART4 Bit 18 USART3RST: USART3 reset Set and cleared by software. 0: No effect 1: Reset USART3 Bit 17 USART2RST: USART2 reset Set and cleared by software. 0: No effect 1: Reset USART2 Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:9 Reserved, must be kept at reset value. Bit 8 TIM14RST: TIM14 timer reset Set and cleared by software. 0: No effect 1: Reset TIM14 Bit 7 TIM13RST: TIM13 timer reset Set and cleared by software. 0: No effect 1: Reset TIM13 Bit 6 TIM12RST: TIM12 timer reset Set and cleared by software. 0: No effect 1: Reset TIM12 DocID13902 Rev 15 110/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 5 TIM7RST: TIM7 timer reset Set and cleared by software. 0: No effect 1: Reset TIM7 Bit 4 TIM6RST: TIM6 timer reset Set and cleared by software. 0: No effect 1: Reset TIM6 Bit 3 TIM5RST: TIM5 timer reset Set and cleared by software. 0: No effect 1: Reset TIM5 Bit 2 TIM4RST: TIM4 timer reset Set and cleared by software. 0: No effect 1: Reset TIM4 Bit 1 TIM3RST: TIM3 timer reset Set and cleared by software. 0: No effect 1: Reset TIM3 Bit 0 TIM2RST: TIM2 timer reset Set and cleared by software. 0: No effect 1: Reset TIM2 7.3.6 Note: AHB peripheral clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SDIO EN rw Res. FSMC EN rw Res. CRCE N rw Res. FLITF EN rw Res. SRAM EN rw DMA2 EN rw DMA1 EN rw Bits 31:11 Reserved, must be kept at reset value. Bit 10 SDIOEN: SDIO clock enable Set and cleared by software. 0: SDIO clock disabled 1: SDIO clock enabled Bits 9 Reserved, always read as 0. 111/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 8 FSMCEN: FSMC clock enable Set and cleared by software. 0: FSMC clock disabled 1: FSMC clock enabled Bit 7 Reserved, always read as 0. Bit 6 CRCEN: CRC clock enable Set and cleared by software. 0: CRC clock disabled 1: CRC clock enabled Bit 5 Reserved, must be kept at reset value. Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during Sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode Bit 3 Reserved, must be kept at reset value. Bit 2 SRAMEN: SRAM interface clock enable Set and cleared by software to disable/enable SRAM interface clock during Sleep mode. 0: SRAM interface clock disabled during Sleep mode. 1: SRAM interface clock enabled during Sleep mode Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disabled 1: DMA2 clock enabled Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled 7.3.7 Note: APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished. When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DocID13902 Rev 15 112/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 15 14 13 ADC3 USART TIM8 EN 1EN EN rw rw rw 12 SPI1 EN rw Reserved 11 TIM1 EN rw 10 ADC2 EN rw 9 ADC1 EN rw 8 IOPG EN rw 7 IOPF EN rw 6 IOPE EN rw TIM11 TIM10 EN EN rw rw 5 4 IOPD IOPC EN EN rw rw TIM9 EN rw 3 IOPB EN rw Reserved 2 IOPA EN rw 1 Res. 0 AFIO EN rw Bits 31:22 Reserved, must be kept at reset value. Bit 21 TIM11EN: TIM11 timer clock enable Set and cleared by software. 0: TIM11 timer clock disabled 1: TIM11 timer clock enabled Bit 20 TIM10EN: TIM10 timer clock enable Set and cleared by software. 0: TIM10 timer clock disabled 1: TIM10 timer clock enabled Bit 19 TIM9EN: TIM9 timer clock enable Set and cleared by software. 0: TIM9 timer clock disabled 1: TIM9 timer clock enabled Bits 18:16 Reserved, always read as 0. Bit 15 ADC3EN: ADC3 interface clock enable Set and cleared by software. 0: ADC3 interface clock disabled 1: ADC3 interface clock enabled Bit 14 USART1EN: USART1 clock enable Set and cleared by software. 0: USART1 clock disabled 1: USART1 clock enabled Bit 13 TIM8EN: TIM8 Timer clock enable Set and cleared by software. 0: TIM8 timer clock disabled 1: TIM8 timer clock enabled Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bit 11 TIM1EN: TIM1 timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled 113/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bit 8 IOPGEN: IO port G clock enable Set and cleared by software. 0: IO port G clock disabled 1: IO port G clock enabled Bit 7 IOPFEN: IO port F clock enable Set and cleared by software. 0: IO port F clock disabled 1: IO port F clock enabled Bit 6 IOPEEN: IO port E clock enable Set and cleared by software. 0: IO port E clock disabled 1: IO port E clock enabled Bit 5 IOPDEN: IO port D clock enable Set and cleared by software. 0: IO port D clock disabled 1: IO port D clock enabled Bit 4 IOPCEN: IO port C clock enable Set and cleared by software. 0: IO port C clock disabled 1: IO port C clock enabled Bit 3 IOPBEN: IO port B clock enable Set and cleared by software. 0: IO port B clock disabled 1: IO port B clock enabled Bit 2 IOPAEN: IO port A clock enable Set and cleared by software. 0: IO port A clock disabled 1: IO port A clock enabled Bit 1 Reserved, must be kept at reset value. Bit 0 AFIOEN: Alternate function IO clock enable Set and cleared by software. 0: Alternate Function IO clock disabled 1: Alternate Function IO clock enabled DocID13902 Rev 15 114/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3.8 Note: APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished. When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 Reserved 15 SPI3 EN rw 14 SPI2 EN rw 29 DAC EN rw 13 28 PWR EN rw 12 Reserved 27 BKP EN rw 11 WWD GEN rw 26 Res. 10 25 CAN EN rw 9 Reserved 24 Res. 8 TIM14 EN rw 23 22 USB I2C2 EN EN rw rw 7 6 TIM13 TIM12 EN EN rw rw 21 I2C1 EN rw 5 TIM7 EN rw 20 19 18 17 UART5E UART4E USART3 USART2 N N EN EN rw rw rw rw 4 3 2 1 TIM6 EN TIM5 EN TIM4 EN TIM3 EN rw rw rw rw 16 Res. 0 TIM2 EN rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACEN: DAC interface clock enable Set and cleared by software. 0: DAC interface clock disabled 1: DAC interface clock enable Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enable Bit 27 BKPEN: Backup interface clock enable Set and cleared by software. 0: Backup interface clock disabled 1: Backup interface clock enabled Bit 26 Reserved, must be kept at reset value. Bit 25 CANEN: CAN clock enable Set and cleared by software. 0: CAN clock disabled 1: CAN clock enabled Bit 24 Reserved, always read as 0. Bit 23 USBEN: USB clock enable Set and cleared by software. 0: USB clock disabled 1: USB clock enabled 115/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 22 I2C2EN: I2C2 clock enable Set and cleared by software. 0: I2C2 clock disabled 1: I2C2 clock enabled Bit 21 I2C1EN: I2C1 clock enable Set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled Bit 20 UART5EN: USART5 clock enable Set and cleared by software. 0: USART5 clock disabled 1: USART5 clock enabled Bit 19 UART4EN: USART4 clock enable Set and cleared by software. 0: USART4 clock disabled 1: USART4 clock enabled Bit 18 USART3EN: USART3 clock enable Set and cleared by software. 0: USART3 clock disabled 1: USART3 clock enabled Bit 17 USART2EN: USART2 clock enable Set and cleared by software. 0: USART2 clock disabled 1: USART2 clock enabled Bits 16 Reserved, always read as 0. Bit 15 SPI3EN: SPI 3 clock enable Set and cleared by software. 0: SPI 3 clock disabled 1: SPI 3 clock enabled Bit 14 SPI2EN: SPI2 clock enable Set and cleared by software. 0: SPI2 clock disabled 1: SPI2 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bits 10:9 Reserved, must be kept at reset value. Bit 8 TIM14EN: TIM14 timer clock enable Set and cleared by software. 0: TIM14 clock disabled 1: TIM14 clock enabled DocID13902 Rev 15 116/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 7 TIM13EN: TIM13 timer clock enable Set and cleared by software. 0: TIM13 clock disabled 1: TIM13 clock enabled Bit 6 TIM12EN: TIM12 timer clock enable Set and cleared by software. 0: TIM12 clock disabled 1: TIM12 clock enabled Bit 5 TIM7EN: TIM7 timer clock enable Set and cleared by software. 0: TIM7 clock disabled 1: TIM7 clock enabled Bit 4 TIM6EN: TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled Bit 3 TIM5EN: TIM5 timer clock enable Set and cleared by software. 0: TIM5 clock disabled 1: TIM5 clock enabled Bit 2 TIM4EN: TIM4 timer clock enable Set and cleared by software. 0: TIM4 clock disabled 1: TIM4 clock enabled Bit 1 TIM3EN: TIM3 timer clock enable Set and cleared by software. 0: TIM3 clock disabled 1: TIM3 clock enabled Bit 0 TIM2EN: TIM2 timer clock enable Set and cleared by software. 0: TIM2 clock disabled 1: TIM2 clock enabled RM0008 117/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.3.9 Note: Backup domain control register (RCC_BDCR) Address offset: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. The LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are writeprotected and the DBP bit in the Power control register (PWR_CR) has to be set before these can be modified. Refer to Section 5 on page 44 for further information. These bits are only reset after a Backup domain Reset (see Section 7.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BDRST rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC EN rw Reserved RTCSEL[1:0] rw rw Reserved LSE BYP rw LSE RDY r LSEON rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, must be kept at reset value. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset them. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by 128 used as RTC clock Bits 7:3 Reserved, must be kept at reset value. DocID13902 Rev 15 118/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 2 LSEBYP: External low-speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles. 0: External 32 kHz oscillator not ready 1: External 32 kHz oscillator ready Bit 0 LSEON: External low-speed oscillator enable Set and cleared by software. 0: External 32 kHz oscillator OFF 1: External 32 kHz oscillator ON 7.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR WWDG IWDG RSTF RSTF RSTF rw rw rw SFT RSTF rw POR RSTF rw PIN RSTF rw Res. RMVF rw Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LSI RDY r LSION rw 119/1128 DocID13902 Rev 15 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a Low-power management reset occurs. Cleared by writing to the RMVF bit. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Low-power management reset. Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent watchdog reset flag Set by hardware when an independent watchdog reset from VDD domain occurs. Cleared by writing to the RMVF bit. 0: No watchdog reset occurred 1: Watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs. Cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 Reserved, must be kept at reset value. Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: Internal low-speed oscillator ready Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 internal RC 40 kHz oscillator clock cycles. 0: Internal RC 40 kHz oscillator not ready 1: Internal RC 40 kHz oscillator ready Bit 0 LSION: Internal low-speed oscillator enable Set and cleared by software. 0: Internal RC 40 kHz oscillator OFF 1: Internal RC 40 kHz oscillator ON DocID13902 Rev 15 120/1128 122 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.3.11 Offset Register 0x00 0x04 0x08 RCC register map The following table gives the RCC register map and the reset values. Table 18. RCC register map and reset values RCC_CR Reset value RCC_CFGR Reset value RCC_CIR Reset value RCC_APB2RSTR 0x0C Reset value RCC_APB1RSTR 0x010 0x14 Reset value RCC_AHBENR Reset value RCC_APB2ENR 0x18 Reset value RCC_APB1ENR 0x1C Reset value 0x20 121/1128 RCC_BDCR Reset value Reserved Reserved 31 30 Reserved Reserved Reserved Reserved 00 MCO [2:0] 000 Reserved PLLMUL[3:0 ] HSICAL[7:0] 00000000000010000 ADC PRE [1:0] PPRE2 [2:0] 00000000000000000000000 000 0 0000000 00 000 DACEN DACRST 29 PWREN PWRRST 28 Reserved BKPEN BKPRST 27 Reserved Reserved 26 00000 000 Reserved 000 0 0000000 00 Reserved CANEN CANRST PLL RDY 25 Reserved Reserved PLL ON 24 USBEN USBRST 0 CSSC Reserved 23 DocID13902 Rev 15 I2C2EN I2C1EN TIM11 EN I2C2RST I2C1RST TIM11RST Reserved USBPRE 22 21 UART5EN TIM10 EN UART5RST TIM10RST PLLRDYC 20 UART4EN TIM9 EN UART4RST TIM9RST HSERDYC CSSON 19 Reserve d USART3EN USART3RST HSIRDYC HSEBYP 18 USART2EN USART2RST Reserved LSERDYC PLLXTPRE HSERDY 17 00 BDRST Reserved Reserved LSIRDYC PLLSRC HSEON 16 PPRE1 [2:0] 000000 00000000000000 0 HSITRIM[4:0] SWS SW HPRE[3:0] [1:0] [1:0] RM0008 00000 000000000 0 0 0 1 100 00000000000000 0 RTCEN SPI3EN ADC3EN SPI3RST ADC3RST 15 SPI2EN USART1EN SPI2RST USART1RST Reserved 14 Reserved Reserved TIM8EN Reserved TIM8RST 13 SPI1EN SPI1RST PLLRDYIE 12 0 0 WWDGEN TIM1EN WWDGRST TIM1RST HSERDYIE 11 Rese rved Reserved ADC2EN SDIOEN ADC2RST HSIRDYIE 10 ADC1EN Reserved ADC1RST LSERDYIE 9 RTC SEL [1:0] 00 000000000 TIM14EN IOPGEN FSMCEN TIM14RST IOPGRST LSIRDYIE 8 Reserved TIM13EN IOPFEN Reserved TIM13RST IOPFRST CSSF 7 TIM12EN IOPEEN CRCEN TIM12RST IOPERST Reserved 6 TIM7EN IOPDEN Reserved TM7RST IOPDRST 5 TIM6EN IOPCEN FLITFEN TM6RST IOPCRST PLLRDYF 4 TIM5EN IOPBEN Reserved TM5RST IOPBRST HSERDYF 3 11 000 LSEBYP TIM4EN IOPAEN SRAMEN TIM4RST IOPARST HSIRDYF Reserved 2 LSERDY TIM3EN Reserved DM2AEN TIM3RST Reserved LSERDYF HSIRDY 1 LSEON TIM2EN AFIOEN DM1AEN TIM2RST AFIORST LSIRDYF HSION 0 0 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Table 18. RCC register map and reset values (continued) Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LSION LSIRDY RMVF Reserved PINRSTF PORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRSTF 0x24 RCC_CSR Reset value 0 0 0 0 1 1 0 Reserved 00 Refer to Table 1 on page 24 for the register boundary addresses. DocID13902 Rev 15 122/1128 122 Connectivity line devices: reset and clock control (RCC) RM0008 8 Connectivity line devices: reset and clock control (RCC) 8.1 8.1.1 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to all connectivity line devices, unless otherwise specified. Reset There are three types of reset, defined as system reset, power reset and backup domain reset. System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 4). A system reset is generated when one of the following events occurs: 1. A low level on the NRST pin (external reset) 2. Window watchdog end of count condition (WWDG reset) 3. Independent watchdog end of count condition (IWDG reset) 4. A software reset (SW reset) (see Software reset) 5. Low-power management reset (see Low-power management reset) The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 8.3.10: Control/status register (RCC_CSR)). Software reset The SYSRESETREQ bit in Cortex®-M3 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex®-M3 programming manual (see Related documents on page 1) for more details. 123/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) 8.1.2 Low-power management reset There are two ways to generate a low-power management reset: 1. Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode. 2. Reset when entering Stop mode: This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode. For further information on the User Option Bytes, refer to the STM32F10xxx Flash programming manual. Power reset A power reset is generated when one of the following events occurs: 1. Power-on/power-down reset (POR/PDR reset) 2. When exiting Standby mode A power reset sets all registers to their reset values except the Backup domain (see Figure 4) These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more details, refer to Table 63: Vector table for other STM32F10xxx devices on page 203. The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each reset source (external or internal reset). In case of an external reset, the reset pulse is generated while the NRST pin is asserted low. Figure 10. Simplified diagram of the reset circuit 9''9''$ ([WHUQDO UHVHW 1567 538 )LOWHU 6\VWHPUHVHW 3XOVH JHQHUDWRU PLQ—V ::'*UHVHW ,:'*UHVHW 3RZHUUHVHW 6RIWZDUHUHVHW /RZSRZHUPDQDJHPHQWUHVHW DLF DocID13902 Rev 15 124/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 8.1.3 Backup domain reset The backup domain has two specific resets that affect only the backup domain (see Figure 4). A backup domain reset is generated when one of the following events occurs: 1. Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). 2. VDD or VBAT power on, if both supplies have previously been powered off. 8.2 Clocks Three different clock sources can be used to drive the system clock (SYSCLK): • HSI oscillator clock • HSE oscillator clock • PLL clock The devices have the following two secondary clock sources: • 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode. • 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real- time clock (RTCCLK) Each clock source can be switched on or off independently when it is not used, to optimize power consumption. 125/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) Figure 11. Clock tree 40 kHz LSI RC OSC32_IN OSC32_OUT 32.768 kHz LSE OSC to independent watchdog IWDGCLK LSI to RTC LSE RTCCLK /128 RTCSEL[1:0] HSE CSS OSC_IN OSC_OUT XT1 to MCO 3-25 MHz HSE OSC to Flash prog. IF FLITFCLK 8 MHz HSI RC /2 /1,2,3.... ..../15, /16 PREDIV1 PLLSCR PREDIV1SCR HSI PLLMUL x4, x5,... x9, PLLCLK x6.5 SW PLLVCO (2 × PLLCLK) USB prescaler /2,3 SYSCLK system clock PREDIV2 PLL2MUL x8, x9,... x14, x16, x20 OTGFSCLK 48 MHz to USB OTG FS to I2S2 interface /1,2,3.... ..../15, /16 PLL3MUL PLL2CLK to MCO x8, x9,... x14, x16, x20 PLL3VCO (2 × PLL3CLK) to I2S3 interface PLL3CLK to MCO MCO Ethernet PHY ETH_MII_TX_CLK ETH_MII_RX_CLK MCO[3:0] HSE HSI PLLCLK/2 PLL2CLK PLL3CLK/2 PLL3CLK XT1 SYSCLK 72 MHz max. (see note1) AHB prescaler /1,/2 ../512 HCLK to AHB bus, core memory and DMA /8 APB1 prescaler /1, 2, 4, 8, 16 to Cortex System timer FCLK Cortex free running clock 36 MHz max Peripheral clock enable PCLK1 to APB1 peripherals TIM2,3,4,5,6,7 If(APB1 prescaler =1) x1 else x2 Peripheral clock enable to TIM2,3,4,5, 6&7 TIMxCLK APB2 prescaler /1, 2, 4, 8, 16 72 MHz max Peripheral clock enable PCLK2 to APB2 peripherals /2, /20 MACTXCLK MII_RMII_SEL in AFIO_MAPR MACRXCLK to Ethernet MAC MACRMIICLK TIM1 If(APB2 prescaler =1) x1 else x2 Peripheral clock enable to TIM1 TIMxCLK ADC prescaler ADCCLK /2, 4, 6, 8 14 MHz max to ADC1,2 ai15699d 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz. 2. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet. The advanced clock controller features 3 PLLs to provide a high degree of flexibility to the application in the choice of the external crystal or oscillator to run the core and peripherals at the highest frequency and guarantee the appropriate frequency for the Ethernet and USB OTG FS. A single 25 MHz crystal can clock the entire system and all peripherals including the Ethernet and USB OTG FS peripherals. In order to achieve high-quality audio performance, an audio crystal can be used. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy. For more details about clock configuration for applications requiring Ethernet, USB OTG FS and/or I2S (audio), please refer to "Appendix A Applicative block diagrams" in your connectivity line device datasheet. DocID13902 Rev 15 126/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 8.2.1 Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz. All peripheral clocks are derived from the system clock (SYSCLK) except: • The Flash memory programming interface clock (FLITFCLK) is always the HSI clock • The USB OTG FS 48 MHz clock which is derived from the PLL VCO clock (2 × PLLCLK), followed by a programmable prescaler (divide by 3 or 2). This selection is made through the OTGFSPRE bit in the RCC_CFGR register. For proper USB OTG FS operation, the PLL should be configured to output 72 MHz or 48 MHz. • The I2S2 and I2S3 clocks which can be derived from the system clock (SYSCLK) or the PLL3 VCO clock (2 × PLL3CLK). This selection is made through the I2SxSRC bit in the RCC_CFGR2 register. For more information on PLL3 and how to configure the I2S clock to achieve high-quality audio performance, please refer to Section 25.4.3: Clock generator. • The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external PHY. For further information on the Ethernet configuration, please refer to Section 29.4.4: MII/RMII selection. When the Ethernet is used, the AHB clock frequency must be at least 25 MHz. The RCC feeds the Cortex® System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex® clock (HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8. The timer clock frequencies are automatically fixed by hardware. There are two cases: 1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected. FCLK acts as Cortex®-M3’s free-running clock. For more details refer to the ARM Cortex™M3 r1p1 Technical Reference Manual (TRM). HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: • HSE external crystal/ceramic resonator • HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. 127/1128 DocID13902 Rev 15 RM0008 Clock source Connectivity line devices: reset and clock control (RCC) Figure 12. HSE/ LSE clock sources Hardware configuration External clock OSC_OUT External source (HiZ) 8.2.2 Crystal/ceramicr esonators OSC_IN OSC_OUT CL1 CL2 Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 50 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 12. External crystal/ceramic resonator (HSE crystal) The 3 to 25 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 12. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). The HSE crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR). HSI clock The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input. The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator. DocID13902 Rev 15 128/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 8.2.3 8.2.4 Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control register (RCC_CR). If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the Clock control register (RCC_CR). The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware. The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR). The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 8.2.7: Clock security system (CSS) on page 131. PLLs The main PLL provides a frequency multiplier starting from one of the following clock sources: • HSI clock divided by 2 • HSE or PLL2 clock through a configurable divider Refer to Figure 11 and Clock control register (RCC_CR). PLL2 and PLL3 are clocked by HSE through a specific configurable divider. Refer to Figure 11 and Clock configuration register2 (RCC_CFGR2) The configuration of each PLL (selection of clock source, predivision factor and multiplication factor) must be done before enabling the PLL. Each PLL should be enabled after its input clock becomes stable (ready flag). Once the PLL is enabled, these parameters can not be changed. When changing the entry clock source of the main PLL, the original clock source must be switched off only after the selection of the new clock source (done through bit PLLSRC in the Clock configuration register (RCC_CFGR)). An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt register (RCC_CIR). LSE clock The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. The LSE crystal is switched on and off using the LSEON bit in Backup domain control register (RCC_BDCR). The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). 129/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) 8.2.5 8.2.6 External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z. See Figure 12. LSI clock The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets. The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR). The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR). LSI calibration The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy. This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout. Use the following procedure to calibrate the LSI: 1. Enable TIM5 timer and configure channel4 in input capture mode 2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose. 3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or interrupt. 4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout. System clock (SYSCLK) selection After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as the system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as system clock. DocID13902 Rev 15 130/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 8.2.7 Note: 8.2.8 8.2.9 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. a failure is detected on the HSE clock, the HSE Oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex®-M3 NMI (Non-Maskable Interrupt) exception vector. Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR). If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock directly or through PLL2, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL (directly or through PLL2) used as system clock when the failure occurs, the PLL is disabled too. RTC clock The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR). This selection cannot be modified without resetting the Backup domain. The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: • If LSE is selected as RTC clock: – The RTC continues to work even if the VDD supply is switched off, provided the VBAT supply is maintained. • If LSI is selected as Auto-Wakeup unit (AWU) clock: – The AWU state is not guaranteed if the VDD supply is powered off. Refer to Section 8.2.5: LSI clock on page 130 for more details on LSI calibration. • If the HSE clock divided by 128 is used as RTC clock: – The RTC state is not guaranteed if the VDD supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain). – The DPB bit (Disable backup domain write protection) in the Power controller register must be set to 1 (refer to Section 5.4.1: Power control register (PWR_CR)). Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. 131/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) 8.2.10 Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 8 clock signals can be selected as the MCO clock. • SYSCLK • HSI • HSE • PLL clock divided by 2 selected • PLL2 clock selected • PLL3 clock divided by 2 selected • XT1 external 3-25 MHz oscillator clock selected (for Ethernet) • PLL3 clock selected (for Ethernet) The selected clock to output onto MCO must not exceed 50 MHz (the maximum I/O speed). The selection is controlled by the MCO[3:0] bits of the Clock configuration register (RCC_CFGR). 8.3 8.3.1 RCC registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access 31 30 Reserved 15 14 r r 29 28 27 26 25 24 23 PLL3 RDY PLL3 ON PLL2 RDY PLL2 ON PLLRD Y PLLON r rw r rw r rw 13 12 11 10 9 8 7 HSICAL[7:0] r r r r r r rw 22 21 20 Reserved 6 5 4 HSITRIM[4:0] rw rw rw 19 18 17 16 CSSON HSEBY P HSERDY HSEON rw rw r rw 3 2 1 0 HSIRDY HSION Res. rw r rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 PLL3RDY: PLL3 clock ready flag Set by hardware to indicate that the PLL3 is locked. 0: PLL3 unlocked 1: PLL3 locked Bit 28 PLL3ON: PLL3 enable Set and cleared by software to enable PLL3. Cleared by hardware when entering Stop or Standby mode. 0: PLL3 OFF 1: PLL3 ON DocID13902 Rev 15 132/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 27 PLL2RDY: PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked. 0: PLL2 unlocked 1: PLL2 locked Bit 26 PLL2ON: PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode. This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). 0: PLL2 OFF 1: PLL2 ON Bit 25 PLLRDY: PLL clock ready flag Set by hardware to indicate that the PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: PLL enable Set and cleared by software to enable PLL. Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. Software must disable the USB OTG FS clock before clearing this bit. 0: PLL OFF 1: PLL ON Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. 0: Clock detector OFF 1: Clock detector ON (Clock detector ON if the HSE oscillator is ready, OFF if not) Bit 18 HSEBYP: External high-speed clock bypass Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. 0: external 3-25 MHz oscillator not bypassed 1: external 3-25 MHz oscillator bypassed with external clock Bit 17 HSERDY: External high-speed clock ready flag Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE oscillator clock to fall down after HSEON reset. 0: HSE oscillator not ready 1: HSE oscillator ready Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration These bits are initialized automatically at startup. 133/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC. The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ± 1%. The trimming step (Fhsitrim) is around 40 kHz between two consecutive HSICAL steps. Bit 2 Reserved, must be kept at reset value. Bit 1 HSIRDY: Internal high-speed clock ready flag Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles. 0: Internal 8 MHz RC oscillator not ready 1: Internal 8 MHz RC oscillator ready Bit 0 HSION: Internal high-speed clock enable Set and cleared by software. Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby mode or in case of failure of the external 3-25 MHz oscillator used directly or indirectly as system clock. This bit can not be cleared if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock. 0: Internal 8 MHz RC oscillator OFF 1: Internal 8 MHz RC oscillator ON 8.3.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during a clock source switch. 31 30 29 28 27 Reserved rw 15 14 13 12 11 ADC PRE[1:0] PPRE2[2:0] rw rw rw rw rw 26 25 24 MCO[3:0] rw rw rw 10 9 8 PPRE1[2:0] rw rw rw 23 Res. 7 rw 22 21 OTGFS PRE rw rw 6 5 HPRE[3:0] rw rw 20 19 18 PLLMUL[3:0] rw rw rw 4 3 2 SWS[1:0] rw r r 17 16 PLL PLL XTPRE SRC rw rw 1 0 SW[1:0] rw rw DocID13902 Rev 15 134/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 31:27 Reserved, must be kept at reset value. Bits 26:24 MCO[3:0]: Microcontroller clock output Set and cleared by software. 00xx: No clock 0100: System clock (SYSCLK) selected 0101: HSI clock selected 0110: HSE clock selected 0111: PLL clock divided by 2 selected 1000: PLL2 clock selected 1001: PLL3 clock divided by 2 selected 1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet) 1011: PLL3 clock selected (for Ethernet) Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. The selected clock to output onto the MCO pin must not exceed 50 MHz (the maximum I/O speed). Bit 22 OTGFSPRE: USB OTG FS prescaler Set and cleared by software to generate the 48 MHz USB OTG FS clock. This bit must be valid before enabling the OTG FS clock in the RCC_APB1ENR register. This bit can not be cleared if the OTG FS clock is enabled. 0: PLL VCO (2 × PLLCLK) clock is divided by 3 (PLL must be configured to output 72 MHz) 1: PLL VCO (2 × PLLCLK) clock is divided by 2 (PLL must be configured to output 48 MHz) Bits 21:18 PLLMUL[3:0]: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. They can be written only when PLL is disabled. 000x: Reserved 0010: PLL input clock x 4 0011: PLL input clock x 5 0100: PLL input clock x 6 0101: PLL input clock x 7 0110: PLL input clock x 8 0111: PLL input clock x 9 10xx: Reserved 1100: Reserved 1101: PLL input clock x 6.5 111x: Reserved Caution: The PLL output frequency must not exceed 72 MHz. Bit 17 PLLXTPRE: LSB of division factor PREDIV1 Set and cleared by software to select the least significant bit of the PREDIV1 division factor. It is the same bit as bit(0) in the RCC_CFGR2 register, so modifying bit(0) in the RCC_CFGR2 register changes this bit accordingly. If bits[3:1] in register RCC_CFGR2 are not set, this bit controls if PREDIV1 divides its input clock by 2 (PLLXTPRE=1) or not (PLLXTPRE=0). This bit can be written only when PLL is disabled. 135/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 16 PLLSRC: PLL entry clock source Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled. 0: HSI oscillator clock / 2 selected as PLL input clock 1: Clock from PREDIV1 selected as PLL input clock Note: When changing the main PLL’s entry clock source, the original clock source must be switched off only after the selection of the new clock source. Bits 14:14 ADCPRE[1:0]: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PCLK2 divided by 2 01: PCLK2 divided by 4 10: PCLK2 divided by 6 11: PCLK2 divided by 8 Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB High speed clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 10:8 PPRE1[2:0]: APB Low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB Low speed clock (PCLK1). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Caution: Software must configure these bits ensure that the frequency in this domain does not exceed 36 MHz. DocID13902 Rev 15 136/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 7:4 HPRE[3:0]: AHB prescaler Set and cleared by software to control AHB clock division factor. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. Refer to the section Reading the Flash memory on page 59 for more details. Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used. Bits 3:2 SWS[1:0]: System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock. 00: HSI oscillator used as system clock 01: HSE oscillator used as system clock 10: PLL used as system clock 11: Not applicable Bits 1:0 SW[1:0]: System clock Switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). 00: HSI selected as system clock 01: HSE selected as system clock 10: PLL selected as system clock 11: Not allowed 8.3.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 15 Res. 30 29 28 27 26 Reserved 14 13 12 11 10 PLL3 PLL2 PLL HSE HSI RDYIE RDYIE RDYIE RDYIE RDYIE rw rw rw rw rw 25 9 LSE RDYIE rw 24 8 LSI RDYIE rw 23 CSSC w 7 CSSF r 22 PLL3 RDYC w 6 PLL3 RDYF r 21 PLL2 RDYC w 5 PLL2 RDYF r 20 PLL RDYC w 4 PLL RDYF r 19 HSE RDYC w 3 HSE RDYF r 18 HSI RDYC w 2 HSI RDYF r 17 LSE RDYC w 1 LSE RDYF r 16 LSI RDYC w 0 LSI RDYF r 137/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bit 22 PLL3RDYC: PLL3 Ready Interrupt Clear This bit is set by software to clear the PLL3RDYF flag. 0: No effect 1: Clear PLL3RDYF flag Bit 21 PLL2RDYC: PLL2 Ready Interrupt Clear This bit is set by software to clear the PLL2RDYF flag. 0: No effect 1: Clear PLL2RDYF flag Bit 20 PLLRDYC: PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag. 0: No effect 1: Clear PLLRDYF flag Bit 19 HSERDYC: HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag. 0: No effect 1: Clear HSERDYF flag Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set by software to clear the HSIRDYF flag. 0: No effect 1: Clear HSIRDYF flag Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: Clear LSERDYF flag Bit 16 LSIRDYC: LSI ready interrupt clear This bit is set by software to clear the LSIRDYF flag. 0: No effect 1: Clear LSIRDYF flag Bit 15 Reserved, must be kept at reset value. Bit 14 PLL3RDYIE: PLL3 Ready Interrupt Enable Set and cleared by software to enable/disable interrupt caused by PLL3 lock. 0: PLL3 lock interrupt disabled 1: PLL3 lock interrupt enabled Bit 13 PLL2RDYIE: PLL2 Ready Interrupt Enable Set and cleared by software to enable/disable interrupt caused by PLL2 lock. 0: PLL2 lock interrupt disabled 1: PLL2 lock interrupt enabled Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled DocID13902 Rev 15 138/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 3-25 MHz oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization. 0: HSI ready interrupt disabled 1: HSI ready interrupt enabled Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 8 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the external 3-25 MHz oscillator. It is cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bit 6 PLL3RDYF: PLL3 Ready Interrupt flag Set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software setting the PLL3RDYC bit. 0: No clock ready interrupt caused by PLL3 lock 1: Clock ready interrupt caused by PLL3 lock Bit 5 PLL2RDYF: PLL2 Ready Interrupt flag Set by hardware when the PLL2 locks and PLL2RDYDIE is set. It is cleared by software setting the PLL2RDYC bit. 0: No clock ready interrupt caused by PLL2 lock 1: Clock ready interrupt caused by PLL2 lock Bit 4 PLLRDYF: PLL ready interrupt flag Set by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by software setting the PLLRDYC bit. 0: No clock ready interrupt caused by PLL lock 1: Clock ready interrupt caused by PLL lock Bit3 HSERDYF: HSE ready interrupt flag Set by hardware when External High Speed clock becomes stable and HSERDYIE is set. It is cleared by software setting the HSERDYC bit. 0: No clock ready interrupt caused by the external 3-25 MHz oscillator 1: Clock ready interrupt caused by the external 3-25 MHz oscillator 139/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is set. It is cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYIE is set. It is cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the external 32 kHz oscillator 1: Clock ready interrupt caused by the external 32 kHz oscillator Bit 0 LSIRDYF: LSI ready interrupt flag Set by hardware when Internal Low Speed clock becomes stable and LSIRDYIE is set. It is cleared by software setting the LSIRDYC bit. 0: No clock ready interrupt caused by the internal RC 40 kHz oscillator 1: Clock ready interrupt caused by the internal RC 40 kHz oscillator DocID13902 Rev 15 140/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 8.3.4 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 15 Res. 14 13 USART1 RST rw Res. 12 SPI1 RST rw 11 TIM1 RST rw 10 ADC2 RST rw 9 ADC1 RST rw 24 23 Reserved 8 7 Reserved 22 21 20 19 18 17 16 6 IOPE RST rw 5 IOPD RST rw 4 IOPC RST rw 3 IOPB RST rw 2 IOPA RST rw 1 Res. 0 AFIO RST rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1RST: SPI 1 reset Set and cleared by software. 0: No effect 1: Reset SPI 1 Bit 11 TIM1RST: TIM1 timer reset Set and cleared by software. 0: No effect 1: Reset TIM1 timer Bit 10 ADC2RST: ADC 2 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 2 interface Bit 9 ADC1RST: ADC 1 interface reset Set and cleared by software. 0: No effect 1: Reset ADC 1 interface Bits 8:7 Reserved, must be kept at reset value. Bit 6 IOPERST: I/O port E reset Set and cleared by software. 0: No effect 1: Reset I:O port E Bit 5 IOPDRST: I/O port D reset Set and cleared by software. 0: No effect 1: Reset I/O port D 141/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset I/O port B Bit 2 IOPARST: I/O port A reset Set and cleared by software. 0: No effect 1: Reset I/O port A Bit 1 Reserved, must be kept at reset value. Bit 0 AFIORST: Alternate function I/O reset Set and cleared by software. 0: No effect 1: Reset Alternate Function 8.3.5 APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 Reserved 15 SPI3 RST rw 14 SPI2 RST rw 29 28 27 26 25 24 23 DAC PWR BKP CAN2 CAN1 RST RST RST RST RST Reserved rw rw rw rw 13 12 11 10 Reserved WWDG RST rw rw 9 8 7 Reserved 22 I2C2 RST rw 6 21 I2C1 RST rw 5 TIM7 RST rw 20 19 18 17 UART5 UART4 USART 3 USART 2 RST RST RST RST rw rw rw rw 4 3 2 1 TIM6 TIM5 RST RST TIM4 RST TIM3 RST rw rw rw rw 16 Res. 0 TIM2 RST rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACRST: DAC interface reset Set and cleared by software. 0: No effect 1: Reset DAC interface Bit 28 PWRRST: Power interface reset Set and cleared by software. 0: No effect 1: Reset power interface Bit 27 BKPRST: Backup interface reset Set and cleared by software. 0: No effect 1: Reset backup interface DocID13902 Rev 15 142/1128 158 Connectivity line devices: reset and clock control (RCC) Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: No effect 1: Reset CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software. 0: No effect 1: Reset CAN1 Bits 24:23 Reserved, must be kept at reset value. Bit 22 I2C2RST: I2C 2 reset Set and cleared by software. 0: No effect 1: Reset I2C 2 Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C 1 Bit 20 UART5RST: USART 5 reset Set and cleared by software. 0: No effect 1: Reset USART 5 Bit 19 UART4RST: USART 4 reset Set and cleared by software. 0: No effect 1: Reset USART 4 Bit 18 USART3RST: USART 3 reset Set and cleared by software. 0: No effect 1: Reset USART 3 Bit 17 USART2RST: USART 2 reset Set and cleared by software. 0: No effect 1: Reset USART 2 Bits 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI 3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 Bits 13:12 Reserved, must be kept at reset value. 143/1128 DocID13902 Rev 15 RM0008 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:6 Reserved, must be kept at reset value. Bit 5 TIM7RST: Timer 7 reset Set and cleared by software. 0: No effect 1: Reset timer 7 Bit 4 TIM6RST: Timer 6 reset Set and cleared by software. 0: No effect 1: Reset timer 6 Bit 3 TIM5RST: Timer 5 reset Set and cleared by software. 0: No effect 1: Reset timer 5 Bit 2 TIM4RST: Timer 4 reset Set and cleared by software. 0: No effect 1: Reset timer 4 Bit 1 TIM3RST: Timer 3 reset Set and cleared by software. 0: No effect 1: Reset timer 3 Bit 0 TIM2RST: Timer 2 reset Set and cleared by software. 0: No effect 1: Reset timer 2 DocID13902 Rev 15 144/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access 31 30 29 28 27 15 14 13 12 11 ETHM ACTXE N ETHM ACEN OTGFS Res. EN rw rw rw 26 25 24 23 Reserved 10 9 8 7 Reserved 22 21 6 5 CRCEN rw Res. 20 19 18 17 16 ETH MACRX EN rw 4 3 2 1 0 FLITFE N rw Res. SRAM DMA2 EN EN rw rw DMA1 EN rw Bits 31:17 Reserved, must be kept at reset value. Bit 16 ETHMACRXEN: Ethernet MAC RX clock enable Set and cleared by software. 0: Ethernet MAC RX clock disabled 1: Ethernet MAC RX clock enabled Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled. Bit 15 ETHMACTXEN: Ethernet MAC TX clock enable Set and cleared by software. 0: Ethernet MAC TX clock disabled 1: Ethernet MAC TX clock enabled Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled. Bit 14 ETHMACEN: Ethernet MAC clock enable Set and cleared by software. Selection of PHY interface (MII/RMII) must be done before enabling the MAC clock. 0: Ethernet MAC clock disabled 1: Ethernet MAC clock enabled Bit 13 Reserved, must be kept at reset value. Bit 12 OTGFSEN: USB OTG FS clock enable Set and cleared by software. 0: USB OTG FS clock disabled 1: USB OTG FS clock enabled Bits 11:7 Reserved, must be kept at reset value. Bit 6 CRCEN: CRC clock enable Set and cleared by software. 0: CRC clock disabled 1: CRC clock enabled Bit 5 Reserved, must be kept at reset value. 145/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode Bit 3 Reserved, must be kept at reset value. Bit 2 SRAMEN: SRAM interface clock enable Set and cleared by software to disable/enable SRAM interface clock during Sleep mode. 0: SRAM interface clock disabled during Sleep mode 1: SRAM interface clock enabled during Sleep mode Bit 1 DMA2EN: DMA2 clock enable Set and cleared by software. 0: DMA2 clock disabled 1: DMA2 clock enabled Bit 0 DMA1EN: DMA1 clock enable Set and cleared by software. 0: DMA1 clock disabled 1: DMA1 clock enabled 8.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x18 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished. 31 30 29 28 27 26 25 15 Res. 14 USART 1EN rw 13 Res. 12 SPI1 EN rw 11 TIM1 EN rw 10 ADC2 EN rw 9 ADC1 EN rw 24 23 Reserved 8 7 Reserved 22 21 20 19 18 17 16 6 IOPE EN rw 5 IOPD EN rw 4 IOPC EN rw 3 IOPB EN rw 2 IOPA EN rw 1 Res. 0 AFIO EN rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 USART1EN: USART1 clock enable Set and cleared by software. 0: USART1 clock disabled 1: USART1 clock enabled Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1EN: SPI 1 clock enable Set and cleared by software. 0: SPI 1 clock disabled 1: SPI 1 clock enabled DocID13902 Rev 15 146/1128 158 Connectivity line devices: reset and clock control (RCC) Bit 11 TIM1EN: TIM1 Timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bits 8:7 Reserved, must be kept at reset value. Bit 6 IOPEEN: I/O port E clock enable Set and cleared by software. 0: I/O port E clock disabled 1: I/O port E clock enabled Bit 5 IOPDEN: I/O port D clock enable Set and cleared by software. 0: I/O port D clock disabled 1: I/O port D clock enabled Bit 4 IOPCEN: I/O port C clock enable Set and cleared by software. 0: I/O port C clock disabled 1:I/O port C clock enabled Bit 3 IOPBEN: I/O port B clock enable Set and cleared by software. 0: I/O port B clock disabled 1:I/O port B clock enabled Bit 2 IOPAEN: I/O port A clock enable Set and cleared by software. 0: I/O port A clock disabled 1:I/O port A clock enabled Bit 1 Reserved, must be kept at reset value. Bit 0 AFIOEN: Alternate function I/O clock enable Set and cleared by software. 0: Alternate Function I/O clock disabled 1:Alternate Function I/O clock enabled 147/1128 DocID13902 Rev 15 RM0008 RM0008 Connectivity line devices: reset and clock control (RCC) 8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished. 31 30 Reserved 15 SPI3 EN rw 14 SPI2 EN rw 29 DAC EN rw 13 28 PWR EN rw 12 Reserved 27 BKP EN rw 11 WWD GEN rw 26 CAN2 EN rw 10 25 CAN1 EN rw 9 24 23 Reserved 8 7 Reserved 22 I2C2 EN rw 6 21 20 19 18 17 16 I2C1 EN rw UART5E UART4E USART3 USART2 N N EN EN rw rw rw rw Res. 5 4 3 2 1 0 TIM7 EN TIM6 EN TIM5 EN TIM4 EN TIM3 EN TIM2 EN rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bit 29 DACEN: DAC interface clock enable Set and cleared by software. 0: DAC interface clock disabled 1: DAC interface clock enable Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enable Bit 27 BKPEN: Backup interface clock enable Set and cleared by software. 0: Backup interface clock disabled 1: Backup interface clock enabled Bit 26 CAN2EN: CAN2 clock enable Set and cleared by software. 0: CAN2 clock disabled 1: CAN2 clock enabled Bit 25 CAN1EN: CAN1 clock enable Set and cleared by software. 0: CAN1 clock disabled 1: CAN1 clock enabled Bits 24:23 Reserved, must be kept at reset value. Bit 22 I2C2EN: I2C 2 clock enable Set and cleared by software. 0: I2C 2 clock disabled 1: I2C 2 clock enabled DocID13902 Rev 15 148/1128 158 Connectivity line devices: reset and clock control (RCC) Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: USART 5 clock enable Set and cleared by software. 0: USART 5 clock disabled 1: USART 5 clock enabled Bit 19 UART4EN: USART 4 clock enable Set and cleared by software. 0: USART 4 clock disabled 1: USART 4 clock enabled Bit 18 USART3EN: USART 3 clock enable Set and cleared by software. 0: USART 3 clock disabled 1: USART 3 clock enabled Bit 17 USART2EN: USART 2 clock enable Set and cleared by software. 0: USART 2 clock disabled 1: USART 2 clock enabled Bits 16 Reserved, must be kept at reset value. Bit 15 SPI3EN: SPI 3 clock enable Set and cleared by software. 0: SPI 3 clock disabled 1: SPI 3 clock enabled Bit 14 SPI2EN: SPI 2 clock enable Set and cleared by software. 0: SPI 2 clock disabled 1: SPI 2 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: Window watchdog clock enable Set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bits 10:6 Reserved, must be kept at reset value. Bit 5 TIM7EN: Timer 7 clock enable Set and cleared by software. 0: Timer 7 clock disabled 1: Timer 7 clock enabled Bit 4 TIM6EN: Timer 6 clock enable Set and cleared by software. 0: Timer 6 clock disabled 1: Timer 6 clock enabled 149/1128 DocID13902 Rev 15 RM0008 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled 1: Timer 5 clock enabled Bit 2 TIM4EN: Timer 4 clock enable Set and cleared by software. 0: Timer 4 clock disabled 1: Timer 4 clock enabled Bit 1 TIM3EN: Timer 3 clock enable Set and cleared by software. 0: Timer 3 clock disabled 1: Timer 3 clock enabled Bit 0 TIM2EN: Timer 2 clock enable Set and cleared by software. 0: Timer 2 clock disabled 1: Timer 2 clock enabled 8.3.9 Note: Backup domain control register (RCC_BDCR) Address: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in the case of successive accesses to this register. LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are writeprotected and the DBP bit in the Power control register (PWR_CR) has to be set before these can be modified. Refer to Section 6 on page 81 for further information. These bits are only reset after a Backup domain Reset (see Section 8.1.3: Backup domain reset). Any internal or external Reset will not have any effect on these bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BDRST rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC EN rw Reserved RTCSEL[1:0] rw rw Reserved LSE BYP rw LSE RDY r LSEON rw DocID13902 Rev 15 150/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 31:17 Reserved, must be kept at reset value. Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, must be kept at reset value. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset the RTCSEL[1:0] bits. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by 128 used as RTC clock Bits 7:3 Reserved, must be kept at reset value. Bit 2 LSEBYP: External Low Speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External Low Speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low speed oscillator clock cycles 0: External 32 kHz oscillator not ready 1: External 32 kHz oscillator ready Bit 0 LSEON: External Low Speed oscillator enable Set and cleared by software. 0: External 32 kHz oscillator OFF 1: External 32 kHz oscillator ON 151/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) 8.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in the case of successive accesses to this register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPWR WWDG IWDG RSTF RSTF RSTF rw rw rw SFT RSTF rw POR RSTF rw PIN RSTF rw Res. RMVF rw Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LSI RDY r LSION rw Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a Low-power management reset occurs. It is cleared by writing to the RMVF bit. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Section : Low-power management reset. Bit 30 WWDGRSTF: Window watchdog reset flag Set by hardware when a window watchdog reset occurs. It is cleared by writing to the RMVF bit. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent watchdog reset flag Set by hardware when an independent watchdog reset from VDD domain occurs. It is cleared by writing to the RMVF bit. 0: No watchdog reset occurred 1: Watchdog reset occurred Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. It is cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag Set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. It is cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 Reserved, must be kept at reset value. DocID13902 Rev 15 152/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: Internal low speed oscillator ready Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 internal 40 kHz RC oscillator clock cycles. 0: Internal RC 40 kHz oscillator not ready 1: Internal RC 40 kHz oscillator ready Bit 0 LSION: Internal low speed oscillator enable Set and cleared by software. 0: Internal RC 40 kHz oscillator OFF 1: Internal RC 40 kHz oscillator ON 8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR) Address offset: 0x28 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. ETHMAC RST rw Res. OTGFSR ST rw Reserved Bits 31:15 Reserved, must be kept at reset value. Bit 14 ETHMACRST Ethernet MAC reset Set and cleared by software. 0: No effect 1: Reset ETHERNET MAC Bit 13 Reserved, must be kept at reset value. Bit 12 OTGFSRST USB OTG FS reset Set and cleared by software. 0: No effect 1: Reset USB OTG FS Bits 11:0 Reserved, must be kept at reset value. 153/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) 8.3.12 Clock configuration register2 (RCC_CFGR2) Address offset: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 15 14 13 12 PLL3MUL[3:0] rw rw rw rw 27 26 25 24 Reserved 11 10 9 8 PLL2MUL[3:0] rw rw rw rw 23 22 21 20 7 6 5 4 PREDIV2[3:0] rw rw rw rw 19 18 17 16 I2S3SR I2S2SR PREDIV C C 1SRC rw rw rw 3 2 1 0 PREDIV1[3:0] rw rw rw rw 7 Bits 31:19 Reserved, must be kept at reset value. Bit 18 I2S3SRC: I2S3 clock source Set and cleared by software to select I2S3 clock source. This bit must be valid before enabling I2S3 clock. 0: System clock (SYSCLK) selected as I2S3 clock entry 1: PLL3 VCO clock selected as I2S3 clock entry Bit 17 I2S2SRC: I2S2 clock source Set and cleared by software to select I2S2 clock source. This bit must be valid before enabling I2S2 clock. 0: System clock (SYSCLK) selected as I2S2 clock entry 1: PLL3 VCO clock selected as I2S2 clock entry Bit 16 PREDIV1SRC: PREDIV1 entry clock source Set and cleared by software to select PREDIV1 clock source. This bit can be written only when PLL is disabled. 0: HSE oscillator clock selected as PREDIV1 clock entry 1: PLL2 selected as PREDIV1 clock entry Bits 15:12 PLL3MUL[3:0]: PLL3 Multiplication Factor Set and cleared by software to control PLL3 multiplication factor. These bits can be written only when PLL3 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL3 clock entry x 8 0111: PLL3 clock entry x 9 1000: PLL3 clock entry x 10 1001: PLL3 clock entry x 11 1010: PLL3 clock entry x 12 1011: PLL3 clock entry x 13 1100: PLL3 clock entry x 14 1101: Reserved 1110: PLL3 clock entry x 16 1111: PLL3 clock entry x 20 DocID13902 Rev 15 154/1128 158 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 11:8 PLL2MUL[3:0]: PLL2 Multiplication Factor Set and cleared by software to control PLL2 multiplication factor. These bits can be written only when PLL2 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL2 clock entry x 8 0111: PLL2 clock entry x 9 1000: PLL2 clock entry x 10 1001: PLL2 clock entry x 11 1010: PLL2 clock entry x 12 1011: PLL2 clock entry x 13 1100: PLL2 clock entry x 14 1101: Reserved 1110: PLL2 clock entry x 16 1111: PLL2 clock entry x 20 Bits 7:4 PREDIV2[3:0]: PREDIV2 division factor Set and cleared by software to select PREDIV2 division factor. These bits can be written only when both PLL2 and PLL3 are disabled. 0000: PREDIV2 input clock not divided 0001: PREDIV2 input clock divided by 2 0010: PREDIV2 input clock divided by 3 0011: PREDIV2 input clock divided by 4 0100: PREDIV2 input clock divided by 5 0101: PREDIV2 input clock divided by 6 0110: PREDIV2 input clock divided by 7 0111: PREDIV2 input clock divided by 8 1000: PREDIV2 input clock divided by 9 1001: PREDIV2 input clock divided by 10 1010: PREDIV2 input clock divided by 11 1011: PREDIV2 input clock divided by 12 1100: PREDIV2 input clock divided by 13 1101: PREDIV2 input clock divided by 14 1110: PREDIV2 input clock divided by 15 1111: PREDIV2 input clock divided by 16 155/1128 DocID13902 Rev 15 RM0008 Connectivity line devices: reset and clock control (RCC) Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor Set and cleared by software to select PREDIV1 division factor. These bits can be written only when PLL is disabled. Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the RCC_CFGR register changes Bit(0) accordingly. 0000: PREDIV1 input clock not divided 0001: PREDIV1 input clock divided by 2 0010: PREDIV1 input clock divided by 3 0011: PREDIV1 input clock divided by 4 0100: PREDIV1 input clock divided by 5 0101: PREDIV1 input clock divided by 6 0110: PREDIV1 input clock divided by 7 0111: PREDIV1 input clock divided by 8 1000: PREDIV1 input clock divided by 9 1001: PREDIV1 input clock divided by 10 1010: PREDIV1 input clock divided by 11 1011: PREDIV1 input clock divided by 12 1100: PREDIV1 input clock divided by 13 1101: PREDIV1 input clock divided by 14 1110: PREDIV1 input clock divided by 15 1111: PREDIV1 input clock divided by 16 8.3.13 RCC register map The following table gives the RCC register map and the reset values. Table 19. RCC register map and reset values Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 HSION HSIRDY Reserved HSEON HSERDY HSEBYP CSSON PLLON PLL RDY PLL2 ON PLL2 RDY PLL3 ON PLL3 RDY 0x000 0x004 RCC_CR Reset value RCC_CFGR Reset value Rese rved 000000 Reserved HSICAL[7:0] HSITRIM[4:0] 0000xxxxxxxx10000 11 PLLXTPRE OTGFSPRE Reserved MCO [3:0] 0000 Reserved PLLSRC PLLMUL [3:0] ADC PRE [1:0] PPRE2 [2:0] PPRE1 [2:0] SWS SW HPRE[3:0] [1:0] [1:0] 00000000000000000000000 LSIRDYF LSERDYF HSIRDYF HSERDYF PLLRDYF PLL2RDYF PLL3RDYF CSSF LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE PLLRDYIE PLL2RDYIE PLL3RDYIE Reserved LSIRDYC LSERDYC HSIRDYC HSERDYC PLLRDYC PLL2RDYC PLL3RDYC CSSC 0x008 RCC_CIR Reset value Reserved 00000000 000000000000000 0 DocID13902 Rev 15 156/1128 158 Connectivity line devices: reset and clock control (RCC) Table 19. RCC register map and reset values (continued) Offset Register RCC_APB2RSTR 0x00C Reset value RCC_APB1RSTR Rese 0x010 rved Reset value RCC_AHBENR 0x014 Reset value 0x018 RCC_APB2ENR Reset value 0x01C 0x020 0x024 0x028 157/1128 RCC_APB1ENR Rese rved Reset value RCC_BDCR Reset value RCC_CSR Reset value 0 0 0 0 1 1 0 RCC_AHBSTR Reset value LPWRSTF 31 WWDGRSTF 30 00000 00000 IWDGRSTF DACEN DACRST 29 SFTRSTF PWREN PWRRST 28 PORRSTF BKPEN BKPRST 27 PINRSTF CAN2EN CAN2RST 26 Reserved Reserved Reserved Reserved Reserved CAN1EN CAN1RST 25 Reserved RMVF Reserved Reserved 24 23 000000 00 000000 00 DocID13902 Rev 15 I2C2EN I2C2RST 22 I2C1EN I2C1RST 21 UART5EN UART5RST 20 UART4EN UART4RST 19 USART3EN USART3RST 18 USART2EN USART2RST 17 0 0000 000 0 00 BDRST Reserved ETHMACRXEN Reserved 16 RTCEN SPI3EN ETHMACTXEN SPI3RST 15 0 0000 Reserved Reserved 00 ETHMACRST SPI2EN USART1EN ETHMACEN SPI2RST USART1RST 14 Reserved OTGFSRST Reserved Reserved Reserved Reserved Reserved 13 SPI1EN OTGFSEN SPI1RST 12 0 WWDGEN TIM1EN 0 WWDGRST TIM1RST 11 Reserved ADC2EN ADC2RST 10 00 RTC SEL [1:0] Reserved ADC1EN Reserved IOPEEN CRCEN Reserved ADC1RST 9 Reserved 8 7 IOPERST 6 RM0008 00000 0 000000 0 1 100 00000 0 000000 Reserved Reserved TIM7EN IOPDEN Reserved TM7RST IOPDRST 5 TIM6EN IOPCEN FLITFEN TM6RST IOPCRST 4 TIM5EN IOPBEN Reserved TM5RST IOPBRST 3 000 LSEBYP TIM4EN IOPAEN SRAMEN TIM4RST IOPARST 2 00 LSIRDY LSERDY TIM3EN Reserved DM2AEN TIM3RST Reserved 1 LSION LSEON TIM2EN AFIOEN DM1AEN TIM2RST AFIORST 0 0 RM0008 Connectivity line devices: reset and clock control (RCC) Table 19. RCC register map and reset values (continued) Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PREDIV1SRC I2S2SRC I2S3SRC 0x02C RCC_CFGR2 Reset value Reserved PLL3MUL [3:0] PLL2MUL PREDIV2[3: PREDIV1[3: [3:0] 0] 0] 0000000000000000000 Refer to Table 3 on page 51 for the register boundary addresses. DocID13902 Rev 15 158/1128 158 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 9.1 GPIO functional description Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register (GPIOx_LCKR). Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes: • Input floating • Input pull-up • Input-pull-down • Analog • Output open-drain • Output push-pull • Alternate function push-pull • Alternate function open-drain Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words (half-word or byte accesses are not allowed). The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the modify access. Figure 13 shows the basic structure of an I/O Port bit. 159/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 13. Basic structure of a standard I/O port bit Bit set/reset registers Output data register Input data register To on-chip peripheral Read Write Analog Input Alternate Function Input on/off TTL Schmitt trigger Input driver Output driver Read/write From on-chip peripheral Alternate Function Output Output control VDD on/off on/off VSS VDD P-MOS N-MOS VSS Push-pull, open-drain or disabled VDD Protection diode I/O pin Protection diode VSS ai14781 Figure 14. Basic structure of a five-volt tolerant I/O port bit Bit set/reset registers Output data register Input data register To on-chip peripheral Read Write Analog Input Alternate Function Input on/off TTL Schmitt trigger Input driver Output driver Read/write From on-chip peripheral Alternate Function Output Output control VDD on/off on/off VSS VDD P-MOS N-MOS VSS Push-pull, open-drain or disabled 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. VDD_FT(1) I/O pin Protection diode VSS ai14782 DocID13902 Rev 15 160/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 20. Port bit configuration table Configuration mode CNF1 CNF0 MODE1 MODE0 General purpose output Alternate Function output Input Push-pull Open-drain Push-pull Open-drain Analog Input floating Input pull-down Input pull-up 0 0 1 0 1 1 0 0 1 1 0 01 10 11 see Table 21 00 PxODR register 0 or 1 0 or 1 don’t care don’t care don’t care don’t care 0 1 Table 21. Output MODE bits MODE[1:0] Meaning 00 Reserved 01 Max. output speed 10 MHz 10 Max. output speed 2 MHz 11 Max. output speed 50 MHz 9.1.1 9.1.2 General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and the I/O ports are configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b). The JTAG pins are in input PU/PD after reset: PA15: JTDI in PU PA14: JTCK in PD PA13: JTMS in PU PB4: NJTRST in PU When configured as output, the value written to the Output Data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in Push-Pull mode or Open-Drain mode (only the N-MOS is activated when outputting 0). The Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every APB2 clock cycle. All GPIO pins have an internal weak pull-up and weak pull-down which can be activated or not when configured as input. Atomic bit set or reset There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify only one or several bits in a single atomic APB2 write access. This is achieved by programming to ‘1’ the Bit Set/Reset Register (GPIOx_BSRR, 161/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.1.3 9.1.4 Note: 9.1.5 9.1.6 or for reset only GPIOx_BRR) to select the bits you want to modify. The unselected bits will not be modified. External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode. For more information on external interrupts, refer to: • Section 10.2: External interrupt/event controller (EXTI) on page 205 and • Section 10.2.3: Wakeup event management on page 206 Alternate functions (AF) It is necessary to program the Port Bit Configuration Register before using a default alternate function. • For alternate function inputs, the port must be configured in Input mode (floating, pull- up or pull-down) and the input pin must be driven externally. It is also possible to emulate the AFI input pin by software by programming the GPIO controller. In this case, the port should be configured in Alternate Function Output mode. And obviously, the corresponding port should not be driven externally as it will be driven by the software using the GPIO controller. • For alternate function outputs, the port must be configured in Alternate Function Output mode (Push-Pull or Open-Drain). • For bidirectional Alternate Functions, the port bit must be configured in Alternate Function Output mode (Push-Pull or Open-Drain). In this case the input driver is configured in input floating mode If you configure a port bit as Alternate Function Output, this disconnects the output register and connects the pin to the output signal of an on-chip peripheral. If software configures a GPIO pin as Alternate Function Output, but peripheral is not activated, its output is not specified. Software remapping of I/O alternate functions To optimize the number of peripheral I/O functions for different device packages, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the corresponding registers (refer to AFIO registers on page 183. In that case, the alternate functions are no longer mapped to their original assignations. GPIO locking mechanism The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence has been applied on a port bit, it is no longer possible to modify the value of the port bit until the next reset. DocID13902 Rev 15 162/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.1.7 Input configuration When the I/O Port is programmed as Input: • The Output Buffer is disabled • The Schmitt Trigger Input is activated • The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating): • The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle • A read access to the Input Data Register obtains the I/O State. The Figure 15 on page 163 shows the Input Configuration of the I/O Port bit. Figure 15. Input floating/pull up/pull down configurations Read Write Read/write Bit set/reset registers Output data register Input data register on TTL Schmitt trigger input driver output driver VDD on/off on/off VSS 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. VDD or VDD_FT(1) protection diode I/O pin protection diode VSS ai14783 163/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.1.8 Output configuration When the I/O Port is programmed as Output: • The Output Buffer is enabled: – Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register leaves the port in Hi-Z. (the P-MOS is never activated) – Push-Pull Mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register activates the P-MOS. • The Schmitt Trigger Input is activated. • The weak pull-up and pull-down resistors are disabled. • The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle • A read access to the Input Data Register gets the I/O state in open drain mode • A read access to the Output Data register gets the last written value in Push-Pull mode The Figure 16 on page 164 shows the Output configuration of the I/O Port bit. Figure 16. Output configuration Bit set/reset registers Output data register Input data register Read Write Read/write on TTL Schmitt trigger Input driver Output driver Output control VDD P-MOS N-MOS Push-pull or VSS Open-drain 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. VDD or VDD_FT(1) Protection diode I/O pin Protection diode VSS ai14784 DocID13902 Rev 15 164/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.1.9 Alternate function configuration When the I/O Port is programmed as Alternate Function: • The Output Buffer is turned on in Open Drain or Push-Pull configuration • The Output Buffer is driven by the signal coming from the peripheral (alternate function out) • The Schmitt Trigger Input is activated • The weak pull-up and pull-down resistors are disabled. • The data present on the I/O pin is sampled into the Input Data Register every APB2 clock cycle • A read access to the Input Data Register gets the I/O state in open drain mode • A read access to the Output Data register gets the last written value in Push-Pull mode The Figure 17 on page 165 shows the Alternate Function Configuration of the I/O Port bit. Also, refer to Section 9.4: AFIO registers on page 183 for further information. A set of Alternate Function I/O registers allow you to remap some alternate functions to different pins. Refer to Section 9.3: Alternate function I/O and debug configuration (AFIO). Figure 17. Alternate function configuration Bit set/reset registers Output data register Input data register To on-chip peripheral Alternate Function Input Read Write on TTL Schmitt trigger Input driver Output driver Read/write From on-chip peripheral Alternate Function Output Output control VDD P-MOS N-MOS VSS push-pull or open-drain 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. VDD or VDD_FT(1) Protection diode I/O pin Protection diode VSS ai14785 165/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.1.10 Analog configuration When the I/O Port is programmed as Analog configuration: • The Output Buffer is disabled. • The Schmitt Trigger Input is de-activated providing zero consumption for every analog value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0). • The weak pull-up and pull-down resistors are disabled. • Read access to the Input Data Register gets the value “0”. The Figure 18 on page 166 shows the high impedance-analog configuration of the I/O Port bit. Figure 18. High impedance-analog configuration Bit set/reset registers Output data register Input data register To on-chip peripheral Read Analog Input Write off 0 TTL Schmitt trigger Input driver Read/write VDD or VDD_FT(1) Protection diode I/O pin Protection diode VSS 9.1.11 From on-chip peripheral ai14786 GPIO configurations for device peripherals Table 22 to Table 33 give the GPIO configurations of the device peripherals. TIM1/8 pinout TIM1/8_CHx TIM1/8_CHxN TIM1/8_BKIN TIM1/8_ETR Table 22. Advanced timers TIM1/TIM8 Configuration GPIO configuration Input capture channel x Output compare channel x Complementary output channel x Break input External trigger timer input Input floating Alternate function push-pull Alternate function push-pull Input floating Input floating DocID13902 Rev 15 166/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 23. General-purpose timers TIM2/3/4/5 TIM2/3/4/5 pinout Configuration GPIO configuration TIM2/3/4/5_CHx TIM2/3/4/5_ETR Input capture channel x Output compare channel x External trigger timer input Input floating Alternate function push-pull Input floating USART pinout Table 24. USARTs Configuration GPIO configuration USARTx_TX(1) USARTx_RX USARTx_CK USARTx_RTS USARTx_CTS Full duplex Half duplex synchronous mode Full duplex Half duplex synchronous mode Synchronous mode Hardware flow control Hardware flow control Alternate function push-pull Alternate function push-pull Input floating / Input pull-up Not used. Can be used as a general IO Alternate function push-pull Alternate function push-pull Input floating/ Input pull-up 1. The USART_TX pin can also be configured as alternate function open drain. Table 25. SPI SPI pinout Configuration GPIO configuration Master SPIx_SCK Slave Alternate function push-pull Input floating Full duplex / master Alternate function push-pull Full duplex / slave Input floating / Input pull-up SPIx_MOSI Simplex bidirectional data wire / master Alternate function push-pull Simplex bidirectional data wire/ slave Not used. Can be used as a GPIO Full duplex / master Input floating / Input pull-up Full duplex / slave (point to point) Alternate function push-pull Full duplex / slave (multi-slave) Alternate function open drain SPIx_MISO Simplex bidirectional data wire / master Simplex bidirectional data wire/ slave (point to point) Not used. Can be used as a GPIO Alternate function push-pull Simplex bidirectional data wire/ slave (multi-slave) Alternate function open drain Hardware master /slave Input floating/ Input pull-up / Input pull-down SPIx_NSS Hardware master/ NSS output enabled Alternate function push-pull Software Not used. Can be used as a GPIO 167/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) I2S pinout I2Sx_ WS I2Sx_CK I2Sx_SD I2Sx_MCK Table 26. I2S Configuration GPIO configuration Master Alternate function push-pull Slave Master Input floating Alternate function push-pull Slave Input floating Transmitter Receiver Master Slave Alternate function push-pull Input floating/ Input pull-up/ Input pull-down Alternate function push-pull Not used. Can be used as a GPIO I2C pinout I2Cx_SCL I2Cx_SDA Table 27. I2C Configuration GPIO configuration I2C clock Alternate function open drain I2C Data I/O Alternate function open drain BxCAN pinout CAN_TX (Transmit data line) CAN_RX (Receive data line) Table 28. BxCAN GPIO configuration Alternate function push-pull Input floating / Input pull-up USB pinout Table 29. USB(1) GPIO configuration USB_DM / USB_DP As soon as the USB is enabled, these pins are connected to the USB internal transceiver automatically. 1. This table applies to low-, medium-, high and XL-density devices only. Table 30. OTG_FS pin configuration(1) OTG_FS pinout Configuration GPIO configuration OTG_FS_SOF OTG_FS_VBUS (2) Host Device OTG Host Device OTG AF push-pull, if used AF push-pull, if used AF push-pull, if used Input floating Input floating Input floating DocID13902 Rev 15 168/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 30. OTG_FS pin configuration(1) OTG_FS pinout Configuration GPIO configuration OTG_FS_ID OTG_FS_DM Host Device OTG Host Device No need if the Force host mode is selected by software (FHMOD set in the OTG_FS_GUSBCFG register) No need if the Force device mode is selected by software (FDMOD set in the OTG_FS_GUSBCFG register) Input pull-up Controlled automatically by the USB power-down Controlled automatically by the USB power-down OTG_FS_DP OTG Host Device Controlled automatically by the USB power-down Controlled automatically by the USB power-down Controlled automatically by the USB power-down OTG Controlled automatically by the USB power-down 1. This table applies to connectivity line devices only. 2. For the OTG_FS_VBUS pin (PA9) to be used by another shared peripheral or as a general-purpose IO, the PHY Power-down mode has to be active (clear bit 16 in the OTG_FS_GCCFG register). SDIO pinout SDIO_CK SDIO_CMD SDIO[D7:D0] Table 31. SDIO GPIO configuration Alternate function push-pull Alternate function push-pull Alternate function push-pull The GPIO configuration of the ADC inputs should be analog. ADC/DAC ADC/DAC pin Figure 19. ADC / DAC GPIO configuration Analog FSMC pinout FSMC_A[25:0] FSMC_D[15:0] FSMC_CK FSMC_NOE FSMC_NWE FSMC_NE[4:1] FSMC_NCE[3:2] FSMC_NCE4_1 FSMC_NCE4_2 Table 32. FSMC GPIO configuration Alternate function push-pull Alternate function push-pull Alternate function push-pull Alternate function push-pull 169/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 32. FSMC (continued) FSMC pinout GPIO configuration FSMC_NWAIT FSMC_CD Input floating/ Input pull-up FSMC_NIOS16, FSMC_INTR FSMC_INT[3:2] Input floating FSMC_NL FSMC_NBL[1:0] Alternate function push-pull FSMC_NIORD, FSMC_NIOWR FSMC_NREG Alternate function push-pull Pins TAMPER-RTC pin MCO EXTI input lines Table 33. Other IOs Alternate function GPIO configuration RTC output Tamper event input Clock output External input interrupts Forced by hardware when configuring the BKP_CR and BKP_RTCCR registers Alternate function push-pull Input floating / input pull-up / input pull-down DocID13902 Rev 15 170/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.2 9.2.1 GPIO registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). Port configuration register low (GPIOx_CRL) (x=A..G) Address offset: 0x00 Reset value: 0x4444 4444 31 30 CNF7[1:0] rw rw 15 14 CNF3[1:0] rw rw 29 28 MODE7[1:0] rw rw 13 12 MODE3[1:0] rw rw 27 26 CNF6[1:0] rw rw 11 10 CNF2[1:0] rw rw 25 24 MODE6[1:0] rw rw 9 8 MODE2[1:0] rw rw 23 22 CNF5[1:0] rw rw 7 6 CNF1[1:0] rw rw 21 20 MODE5[1:0] rw rw 5 4 MODE1[1:0] rw rw 19 18 CNF4[1:0] rw rw 3 2 CNF0[1:0] rw rw 17 16 MODE4[1:0] rw rw 1 0 MODE0[1:0] rw rw Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 0 .. 7) 23:22, 19:18, 15:14, These bits are written by software to configure the corresponding I/O port. 11:10, 7:6, 3:2 Refer to Table 20: Port bit configuration table on page 161. In input mode (MODE[1:0]=00): 00: Analog mode 01: Floating input (reset state) 10: Input with pull-up / pull-down 11: Reserved In output mode (MODE[1:0] > 00): 00: General purpose output push-pull 01: General purpose output Open-drain 10: Alternate function output Push-pull 11: Alternate function output Open-drain Bits 29:28, 25:24, MODEy[1:0]: Port x mode bits (y= 0 .. 7) 21:20, 17:16, 13:12, These bits are written by software to configure the corresponding I/O port. 9:8, 5:4, 1:0 Refer to Table 20: Port bit configuration table on page 161. 00: Input mode (reset state) 01: Output mode, max speed 10 MHz. 10: Output mode, max speed 2 MHz. 11: Output mode, max speed 50 MHz. 171/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) Address offset: 0x04 Reset value: 0x4444 4444 31 30 CNF15[1:0] rw rw 15 14 CNF11[1:0] rw rw 29 28 MODE15[1:0] rw rw 13 12 MODE11[1:0] rw rw 27 26 CNF14[1:0] rw rw 11 10 CNF10[1:0] rw rw 25 24 MODE14[1:0] rw rw 9 8 MODE10[1:0] rw rw 23 22 CNF13[1:0] rw rw 7 6 CNF9[1:0] rw rw 21 20 MODE13[1:0] rw rw 5 4 MODE9[1:0] rw rw 19 18 CNF12[1:0] rw rw 3 2 CNF8[1:0] rw rw 17 16 MODE12[1:0] rw rw 1 0 MODE8[1:0] rw rw Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 8 .. 15) 23:22, 19:18, 15:14, These bits are written by software to configure the corresponding I/O port. 11:10, 7:6, 3:2 Refer to Table 20: Port bit configuration table on page 161. In input mode (MODE[1:0]=00): 00: Analog mode 01: Floating input (reset state) 10: Input with pull-up / pull-down 11: Reserved In output mode (MODE[1:0] > 00): 00: General purpose output push-pull 01: General purpose output Open-drain 10: Alternate function output Push-pull 11: Alternate function output Open-drain Bits 29:28, 25:24, MODEy[1:0]: Port x mode bits (y= 8 .. 15) 21:20, 17:16, 13:12, These bits are written by software to configure the corresponding I/O port. 9:8, 5:4, 1:0 Refer to Table 20: Port bit configuration table on page 161. 00: Input mode (reset state) 01: Output mode, max speed 10 MHz. 10: Output mode, max speed 2 MHz. 11: Output mode, max speed 50 MHz. 9.2.3 Port input data register (GPIOx_IDR) (x=A..G) Address offset: 0x08h Reset value: 0x0000 XXXX 31 30 29 28 27 26 25 15 14 13 12 11 10 IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 r r r r r r 9 IDR9 r 24 23 Reserved 8 7 IDR8 IDR7 r r 22 6 IDR6 r 21 5 IDR5 r 20 4 IDR4 r 19 3 IDR3 r 18 2 IDR2 r 17 1 IDR1 r 16 0 IDR0 r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 IDRy: Port input data (y= 0 .. 15) These bits are read only and can be accessed in Word mode only. They contain the input value of the corresponding I/O port. DocID13902 Rev 15 172/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.2.4 Port output data register (GPIOx_ODR) (x=A..G) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 15 14 13 12 11 10 9 ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 rw rw rw rw rw rw rw 24 23 Reserved 8 7 ODR8 ODR7 rw rw 22 6 ODR6 rw 21 5 ODR5 rw 20 4 ODR4 rw 19 3 ODR3 rw 18 2 ODR2 rw 17 1 ODR1 rw 16 0 ODR0 rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ODRy: Port output data (y= 0 .. 15) These bits can be read and written by software and can be accessed in Word mode only. Note: For atomic bit set/reset, the ODR bits can be individually set and cleared by writing to the GPIOx_BSRR register (x = A .. G). 9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 w w w w w w w w w w w w w w w w Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. 0: No action on the corresponding ODRx bit 1: Reset the corresponding ODRx bit Note: If both BSx and BRx are set, BSx has priority. Bits 15:0 BSy: Port x Set bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. 0: No action on the corresponding ODRx bit 1: Set the corresponding ODRx bit 173/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only. 0: No action on the corresponding ODRx bit 1: Reset the corresponding ODRx bit 9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit it is no longer possible to modify the value of the port bit until the next reset. Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH). Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 15 14 13 12 11 10 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 rw rw rw rw rw rw 25 24 23 Reserved 9 LCK9 rw 8 LCK8 rw 7 LCK7 rw 22 6 LCK6 rw 21 5 LCK5 rw 20 4 LCK4 rw 19 3 LCK3 rw 18 2 LCK2 rw 17 1 LCK1 rw 16 LCKK rw 0 LCK0 rw DocID13902 Rev 15 174/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 31:17 Reserved Bit 16 LCKK[16]: Lock key This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. GPIOx_LCKR register is locked until an MCU reset occurs. LOCK key writing sequence: Write 1 Write 0 Write 1 Read 0 Read 1 (this read is optional but confirms that the lock is active) Note: During the LOCK Key Writing sequence, the value of LCK[15:0] must not change. Any error in the lock sequence will abort the lock. Bits 15:0 LCKy: Port x Lock bit y (y= 0 .. 15) These bits are read write but can only be written when the LCKK bit is 0. 0: Port configuration not locked 1: Port configuration locked. 9.3 9.3.1 Note: 9.3.2 Note: Alternate function I/O and debug configuration (AFIO) To optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin package, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the AF remap and debug I/O configuration register (AFIO_MAPR) on page 184. In this case, the alternate functions are no longer mapped to their original assignations. Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O PC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the GP IOs function. The PC14/PC15 GPIO functionality is lost when the 1.8 V domain is powered off (by entering standby mode) or when the backup domain is supplied by VBAT (VDD no more supplied). In this case the IOs are set in analog mode. Refer to the note on IO usage restrictions in Section 5.1.2 on page 69. Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1 by programming the PD01_REMAP bit in the AF remap and debug I/O configuration register (AFIO_MAPR). This remap is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping). The external interrupt/event function is not remapped. PD0 and PD1 cannot be used for external interrupt/event generation on 36-, 48- and 64-pin packages. 175/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.3.3 9.3.4 CAN1 alternate function remapping The CAN signals can be mapped on Port A, Port B or Port D as shown in Table 34. For port D, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages. Table 34. CAN1 alternate function remapping Alternate function(1) CAN_REMAP[1:0] = “00” CAN_REMAP[1:0] = “10” (2) CAN_REMAP[1:0] = “11”(3) CAN1_RX or CAN_RX PA11 PB8 PD0 CAN1_TX or CAN_RX PA12 PB9 PD1 1. CAN1_RX and CAN1_TX in connectivity line devices; CAN_RX and CAN_TX in other devices with a single CAN interface. 2. Remap not available on 36-pin package 3. This remapping is available only on 100-pin and 144-pin packages, when PD0 and PD1 are not remapped on OSC-IN and OSC-OUT. CAN2 alternate function remapping CAN2 is available in connectivity line devices. The external signal can be remapped as shown in Chapter Table 35. Table 35. CAN2 alternate function remapping Alternate function CAN2_REMAP = “0” CAN2_REMAP = “1” CAN2_RX PB12 PB5 CAN2_TX PB13 PB6 9.3.5 JTAG/SWD alternate function remapping The debug interface signals are mapped on the GPIO ports as shown in Table 36. Table 36. Debug interface signals Alternate function GPIO port JTMS / SWDIO JTCK / SWCLK PA13 PA14 JTDI JTDO / TRACESWO NJTRST TRACECK TRACED0 PA15 PB3 PB4 PE2 PE3 TRACED1 PE4 TRACED2 PE5 TRACED3 PE6 DocID13902 Rev 15 176/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.3.6 To optimize the number of free GPIOs during debugging, this mapping can be configured in different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O configuration register (AFIO_MAPR). Refer to Table 37 Table 37. Debug port mapping SWJ _CFG [2:0] Available debug ports SWJ I/O pin assigned PA13 / JTMS/ SWDIO PA14 / JTCK/S WCLK PA15 / JTDI PB3 / JTDO/ TRACE SWO PB4/ NJTRST 000 Full SWJ (JTAG-DP + SW-DP) (Reset state) X X X X X 001 Full SWJ (JTAG-DP + SW-DP) but without NJTRST X X X x free 010 JTAG-DP Disabled and SW-DP Enabled X X free free(1) free 100 JTAG-DP Disabled and SW-DP Disabled free free free free free Other Forbidden 1. Released only if not using asynchronous trace. ADC alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Table 38. ADC1 external trigger injected conversion alternate function remapping(1) Alternate function ADC1_ETRGINJ_REMAP = 0 ADC1_ETRGINJ_REMAP = 1 ADC1 external trigger injected conversion ADC1 external trigger injected conversion is connected to EXTI15 ADC1 external trigger injected conversion is connected to TIM8_CH4 1. Remap available only for high-density and XL-density devices. Table 39. ADC1 external trigger regular conversion alternate function remapping(1) Alternate function ADC1_ETRGREG_REMAP = 0 ADC1_ETRGREG_REMAP = 1 ADC1 external trigger regular conversion ADC1 external trigger regular conversion is connected to EXTI11 ADC1 external trigger regular conversion is connected to TIM8_TRGO 1. Remap available only for high-density and XL-density devices. Table 40. ADC2 external trigger injected conversion alternate function remapping(1) Alternate function ADC2_ETRGINJ_REMAP = 0 ADC2_ETRGINJ_REMAP = 1 ADC2 external trigger injected conversion ADC2 external trigger injected conversion is connected to EXTI 15 ADC2 external trigger injected conversion is connected to TIM8_CH4 1. Remap available only for high-density and XL-density devices. 177/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.3.7 Table 41. ADC2 external trigger regular conversion alternate function remapping(1) Alternate function ADC2_ETRGREG_REG = 0 ADC2_ETRGREG_REG = 1 ADC2 external trigger regular conversion ADC2 external trigger regular conversion is connected to EXTI11 ADC2 external trigger regular conversion is connected to TIM8_TRGO 1. Remap available only for high-density and XL-density devices. Timer alternate function remapping Timer 4 channels 1 to 4 can be remapped from Port B to Port D. Other timer remapping possibilities are listed in Table 44 to Table 46. Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Table 42. TIM5 alternate function remapping(1) Alternate function TIM5CH4_IREMAP = 0 TIM5CH4_IREMAP = 1 TIM5_CH4 TIM5 Channel4 is connected to PA3 LSI internal clock is connected to TIM5_CH4 input for calibration purpose. 1. Remap available only for high-density, XL-density and connectivity line devices. Table 43. TIM4 alternate function remapping Alternate function TIM4_REMAP = 0 TIM4_REMAP = 1(1) TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_CH4 PB6 PD12 PB7 PD13 PB8 PD14 PB9 PD15 1. Remap available only for 100-pin and for 144-pin package. Table 44. TIM3 alternate function remapping Alternate function TIM3_REMAP[1:0] = TIM3_REMAP[1:0] = TIM3_REMAP[1:0] = “00” (no remap) “10” (partial remap) “11” (full remap) (1) TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 PA6 PB4 PC6 PA7 PB5 PC7 PB0 PC8 PB1 PC9 1. Remap available only for 64-pin, 100-pin and 144-pin packages. DocID13902 Rev 15 178/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 45. TIM2 alternate function remapping TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: Alternate function 0] = “00” (no remap) 0] = “01” (partial 0] = “10” (partial remap) remap) (1) 0] = “11” (full remap) (1) TIM2_CH1_ETR(2) PA0 PA15 PA0 PA15 TIM2_CH2 PA1 PB3 PA1 PB3 TIM2_CH3 PA2 PB10 TIM2_CH4 PA3 PB11 1. Remap not available on 36-pin package. 2. TIM_CH1 and TIM_ETR share the same pin but cannot be used at the same time (which is why we have this notation: TIM2_CH1_ETR). Table 46. TIM1 alternate function remapping Alternate functions mapping TIM1_REMAP[1:0] = TIM1_REMAP[1:0] = TIM1_REMAP[1:0] = “00” (no remap) “01” (partial remap) “11” (full remap) (1) TIM1_ETR TIM1_CH1 TIM1_CH2 TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM1_CH1N TIM1_CH2N TIM1_CH3N PA12 PA8 PA9 PA10 PA11 PB12 (2) PA6 PB13 PB14 (2) PB15 (2) PA7 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15 PE8 PE10 PE12 1. Remap available only for 100-pin and 144-pin packages. 2. Remap not available on 36-pin package. Table 47. TIM9 remapping(1) Alternate function TIM9_REMAP = 0 TIM9_REMAP = 1 TIM9_CH1 PA2 PE5 TIM9_CH2 PA3 PE6 1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O configuration register2 (AFIO_MAPR2). Table 48. TIM10 remapping(1) Alternate function TIM10_REMAP = 0 TIM10_REMAP = 1 TIM10_CH1 PB8 PF6 1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O configuration register2 (AFIO_MAPR2). 179/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.3.8 Table 49. TIM11 remapping(1) Alternate function TIM11_REMAP = 0 TIM11_REMAP = 1 TIM11_CH1 PB9 PF7 1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O configuration register2 (AFIO_MAPR2). Table 50. TIM13 remapping(1) Alternate function TIM13_REMAP = 0 TIM13_REMAP = 1 TIM13_CH1 PA6 PF8 1. Refer to the AF remap and debug I/O configuration registerSection 9.4.7: AF remap and debug I/O configuration register2 (AFIO_MAPR2). Table 51. TIM14 remapping(1) Alternate function TIM14_REMAP = 0 TIM14_REMAP = 1 TIM14_CH1 PA7 PF9 1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O configuration register2 (AFIO_MAPR2). USART alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Table 52. USART3 remapping Alternate function USART3_REMAP[1:0] = “00” (no remap) USART3_REMAP[1:0] = “01” (partial remap) (1) USART3_REMAP[1:0] = “11” (full remap) (2) USART3_TX USART3_RX USART3_CK USART3_CTS USART3_RTS PB10 PB11 PB12 PB13 PB14 PC10 PC11 PC12 PD8 PD9 PD10 PD11 PD12 1. Remap available only for 64-pin, 100-pin and 144-pin packages 2. Remap available only for 100-pin and 144-pin packages. Table 53. USART2 remapping Alternate functions USART2_REMAP = 0 USART2_CTS PA0 USART2_RTS PA1 USART2_TX PA2 USART2_RX PA3 USART2_CK PA4 1. Remap available only for 100-pin and 144-pin packages. USART2_REMAP = 1(1) PD3 PD4 PD5 PD6 PD7 DocID13902 Rev 15 180/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 54. USART1 remapping Alternate function USART1_REMAP = 0 USART1_TX PA9 USART1_RX PA10 USART1_REMAP = 1 PB6 PB7 9.3.9 9.3.10 I2C1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 55. I2C1 remapping Alternate function I2C1_REMAP = 0 I2C1_SCL PB6 I2C1_SDA PB7 1. Remap not available on 36-pin package. I2C1_REMAP = 1(1) PB8 PB9 SPI1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Alternate function SPI1_NSS SPI1_SCK SPI1_MISO SPI1_MOSI Table 56. SPI1 remapping SPI1_REMAP = 0 PA4 PA5 PA6 PA7 SPI1_REMAP = 1 PA15 PB3 PB4 PB5 9.3.11 SPI3/I2S3 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR). This remap is available only in connectivity line devices. Table 57. SPI3/I2S3 remapping Alternate function SPI3_REMAP = 0 SPI3_NSS / I2S3_WS PA15 SPI3_SCK / I2S3_CK PB3 SPI3_MISO PB4 SPI3_MOSI / I2S3_SD PB5 SPI3_REMAP = 1 PA4 PC10 PC11 PC12 9.3.12 Ethernet alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR). Ethernet is available only in connectivity line devices. 181/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Alternate function RX_DV-CRS_DV RXD0 RXD1 RXD2 RXD3 Table 58. ETH remapping ETH_REMAP = 0 PA7 PC4 PC5 PB0 PB1 ETH_REMAP = 1 PD8 PD9 PD10 PD11 PD12 DocID13902 Rev 15 182/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.4 Note: AFIO registers Refer to Section 2.1 on page 47for a list of abbreviations used in register descriptions. To read/write the AFIO_EVCR, AFIO_MAPR and AFIO_EXTICRX registers, the AFIO clock should first be enabled. Refer to Section 7.3.7: APB2 peripheral clock enable register (RCC_APB2ENR). The peripheral registers have to be accessed by words (32-bit). 9.4.1 Event control register (AFIO_EVCR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EVOE PORT[2:0] PIN[3:0] rw rw rw rw rw rw rw rw Bits 31:8 Reserved Bit 7 EVOE: Event output enable Set and cleared by software. When set the EVENTOUT Cortex® output is connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits. Bits 6:4 PORT[2:0]: Port selection Set and cleared by software. Select the port used to output the Cortex® EVENTOUT signal. Note: The EVENTOUT signal output capability is not extended to ports PF and PG. 000: PA selected 001: PB selected 010: PC selected 011: PD selected 100: PE selected Bits 3:0 PIN[3:0]: Pin selection (x = A .. E) Set and cleared by software. Select the pin used to output the Cortex® EVENTOUT signal. 0000: Px0 selected 0001: Px1 selected 0010: Px2 selected 0011: Px3 selected ... 1111: Px15 selected 183/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) Address offset: 0x04 Reset value: 0x0000 0000 Memory map and bit definitions for low-, medium- high- and XL-density devices: 31 15 PD01_ REMA P rw 30 29 28 Reserved Reserved 14 13 CAN_REMAP [1:0] rw rw 12 TIM4_ REMA P rw 27 26 25 24 SWJ_ CFG[2:0] w w w SWJ_CFG[2:0] w w w 11 10 9 8 TIM3_REMAP TIM2_REMAP [1:0] [1:0] rw rw rw rw 23 22 21 20 19 18 17 16 Reserved ADC2_ ETRG REG_R EMAP ADC2_E TRGINJ_ REMAP ADC1_E TRGRE G_REMA P ADC1_ ETRGI NJ_RE MAP TIM5C H4_IRE MAP rw rw rw rw rw Reserved TIM5C H4_IRE MAP rw 7 6 5 4 3 2 1 0 TIM1_REMAP [1:0] USART3_ REMAP[1:0] USART2 USART1 I2C1_ SPI1_ _ _ REMA REMA REMAP REMAP P P rw rw rw rw rw rw rw rw Bits 31:27 Reserved Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration These bits are write-only (when read, the value is undefined). They are used to configure the SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex® debug port. The default state after reset is SWJ ON without trace. This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS / JTCK pin. 000: Full SWJ (JTAG-DP + SW-DP): Reset State 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST 010: JTAG-DP Disabled and SW-DP Enabled 100: JTAG-DP Disabled and SW-DP Disabled Other combinations: no effect Bits 23:21 Reserved. Bits 20 ADC2_ETRGREG_REMAP: ADC 2 external trigger regular conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger regular conversion. When this bit is reset, the ADC2 external trigger regular conversion is connected to EXTI11. When this bit is set, the ADC2 external event regular conversion is connected to TIM8_TRGO. Bits 19 ADC2_ETRGINJ_REMAP: ADC 2 external trigger injected conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC2 external trigger injected conversion. When this bit is reset, the ADC2 external trigger injected conversion is connected to EXTI15. When this bit is set, the ADC2 external event injected conversion is connected to TIM8_Channel4. Bits 18 ADC1_ETRGREG_REMAP: ADC 1 external trigger regular conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC1 External trigger regular conversion. When reset the ADC1 External trigger regular conversion is connected to EXTI11. When set the ADC1 External Event regular conversion is connected to TIM8 TRGO. DocID13902 Rev 15 184/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 17 ADC1_ETRGINJ_REMAP: ADC 1 External trigger injected conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC1 External trigger injected conversion. When reset the ADC1 External trigger injected conversion is connected to EXTI15. When set the ADC1 External Event injected conversion is connected to TIM8 Channel4. Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to TIM5_CH4 input for calibration purpose. Note: This bit is available only in high density value line devices. Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping). 0: No remapping of PD0 and PD1 1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT, Bits 14:13 CAN_REMAP[1:0]: CAN alternate function remapping These bits are set and cleared by software. They control the mapping of alternate functions CAN_RX and CAN_TX in devices with a single CAN interface. 00: CAN_RX mapped to PA11, CAN_TX mapped to PA12 01: Not used 10: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) 11: CAN_RX mapped to PD0, CAN_TX mapped to PD1 Bit 12 TIM4_REMAP: TIM4 remapping This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the GPIO ports. 0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) 1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) Note: TIM4_ETR on PE0 is not re-mapped. Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01: Not used 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) Note: TIM3_ETR on PE0 is not re-mapped. Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports. 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) 185/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports. 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 10: not used 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) Bits 5:4 USART3_REMAP[1:0]: USART3 remapping These bits are set and cleared by software. They control the mapping of USART3 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 10: not used 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) Bit 3 USART2_REMAP: USART2 remapping This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) Bit 2 USART1_REMAP: USART1 remapping This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports. 0: No remap (TX/PA9, RX/PA10) 1: Remap (TX/PB6, RX/PB7) Bit 1 I2C1_REMAP: I2C1 remapping This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate functions on the GPIO ports. 0: No remap (SCL/PB6, SDA/PB7) 1: Remap (SCL/PB8, SDA/PB9) Bit 0 SPI1_REMAP: SPI1 remapping This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) DocID13902 Rev 15 186/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Memory map and bit definitions for connectivity line devices: 31 30 29 28 27 26 25 24 23 22 21 20 Res. PTP_P PS_RE MAP TIM2IT R1_ IREMA P SPI3_ REMA P Res. SWJ_ CFG[2:0] MII_R MII_SE L CAN2_ REMA P ETH_R EMAP rw rw rw w w w rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 PD01_ REMA P CAN1_REMAP [1:0] TIM4_ REMA P TIM3_REMAP TIM2_REMAP [1:0] [1:0] TIM1_REMAP [1:0] USART3_ REMAP[1:0] rw rw rw rw rw rw rw rw rw rw rw rw 19 18 17 16 Reserved TIM5C H4_IRE MAP rw 3 2 1 0 USART2 USART1 I2C1_ SPI1_ _ _ REMA REMA REMAP REMAP P P rw rw rw rw Bit 31 Reserved, must be kept at reset value. Bit 30 PTP_PPS_REMAP: Ethernet PTP PPS remapping This bit is set and cleared by software. It enables the Ethernet MAC PPS_PTS to be output on the PB5 pin. 0: PTP_PPS not output on PB5 pin. 1: PTP_PPS is output on PB5 pin. Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 29 TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping This bit is set and cleared by software. It controls the TIM2_ITR1 internal mapping. 0: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. 1: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 28 SPI3_REMAP: SPI3/I2S3 remapping This bit is set and cleared by software. It controls the mapping of SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD alternate functions on the GPIO ports. 0: No remap (SPI_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5) 1: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 27 Reserved Bits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration These bits are write-only (when read, the value is undefined). They are used to configure the SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex® debug port. The default state after reset is SWJ ON without trace. This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS / JTCK pin. 000: Full SWJ (JTAG-DP + SW-DP): Reset State 001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST 010: JTAG-DP Disabled and SW-DP Enabled 100: JTAG-DP Disabled and SW-DP Disabled Other combinations: no effect 187/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 23 MII_RMII_SEL: MII or RMII selection This bit is set and cleared by software. It configures the Ethernet MAC internally for use with an external MII or RMII PHY. 0: Configure Ethernet MAC for connection with an MII PHY 1: Configure Ethernet MAC for connection with an RMII PHY Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 22 CAN2_REMAP: CAN2 I/O remapping This bit is set and cleared by software. It controls the CAN2_TX and CAN2_RX pins. 0: No remap (CAN2_RX/PB12, CAN2_TX/PB13) 1: Remap (CAN2_RX/PB5, CAN2_TX/PB6) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 21 ETH_REMAP: Ethernet MAC I/O remapping This bit is set and cleared by software. It controls the Ethernet MAC connections with the PHY. 0: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) 1: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bits 20:17 Reserved Bits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap Set and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset the timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to TIM5_CH4 input for calibration purpose. Bit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping). 0: No remapping of PD0 and PD1 1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT, Bits 14:13 CAN1_REMAP[1:0]: CAN1 alternate function remapping These bits are set and cleared by software. They control the mapping of alternate functions CAN1_RX and CAN1_TX. 00: CAN1_RX mapped to PA11, CAN1_TX mapped to PA12 01: Not used 10: CAN1_RX mapped to PB8, CAN1_TX mapped to PB9 (not available on 36-pin package) 11: CAN1_RX mapped to PD0, CAN1_TX mapped to PD1 Bit 12 TIM4_REMAP: TIM4 remapping This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the GPIO ports. 0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) 1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) Note: TIM4_ETR on PE0 is not re-mapped. DocID13902 Rev 15 188/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01: Not used 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) Note: TIM3_ETR on PE0 is not re-mapped. Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports. 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports. 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 10: not used 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) Bits 5:4 USART3_REMAP[1:0]: USART3 remapping These bits are set and cleared by software. They control the mapping of USART3 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 10: not used 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) Bit 3 USART2_REMAP: USART2 remapping This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports. 0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) 189/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 2 USART1_REMAP: USART1 remapping This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports. 0: No remap (TX/PA9, RX/PA10) 1: Remap (TX/PB6, RX/PB7) Bit 1 I2C1_REMAP: I2C1 remapping This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate functions on the GPIO ports. 0: No remap (SCL/PB6, SDA/PB7) 1: Remap (SCL/PB8, SDA/PB9) Bit 0 SPI1_REMAP: SPI1 remapping This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports. 0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) DocID13902 Rev 15 190/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) Address offset: 0x08 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3) These bits are written by software to select the source input for EXTIx external interrupt. Refer to Section 10.2.5: External interrupt/event line mapping on page 208 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 9.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) Address offset: 0x0C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 191/1128 DocID13902 Rev 15 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) Address offset: 0x10 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin 9.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) Address offset: 0x14 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PF[x] pin 0110: PG[x] pin DocID13902 Rev 15 192/1128 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 Reserved FSM TIM14_ TIM13_ TIM11_ TIM10_ C_NA REMA REMA REMA REMA DV P P P P TIM9_ REMA P rw rw rw rw rw rw 19 18 17 16 3 2 1 0 Reserved Bits 31:11 Reserved. Bit 10 FSMC_NADV: NADV connect/disconnect This bit is set and cleared by software. It controls the use of the optional FSMC_NADV signal. 0: The NADV signal is connected to the output (default) 1: The NADV signal is not connected. The I/O pin can be used by another peripheral. Bit 9 TIM14_REMAP: TIM14 remapping This bit is set and cleared by software. It controls the mapping of the TIM14_CH1 alternate function onto the GPIO ports. 0: No remap (PA7) 1: Remap (PF9) Bit 8 TIM13_REMAP: TIM13 remapping This bit is set and cleared by software. It controls the mapping of the TIM13_CH1 alternate function onto the GPIO ports. 0: No remap (PA6) 1: Remap (PF8) Bit 7 TIM11_REMAP: TIM11 remapping This bit is set and cleared by software. It controls the mapping of the TIM11_CH1 alternate function onto the GPIO ports. 0: No remap (PB9) 1: Remap (PF7) Bit 6 TIM10_REMAP: TIM10 remapping This bit is set and cleared by software. It controls the mapping of the TIM10_CH1 alternate function onto the GPIO ports. 0: No remap (PB8) 1: Remap (PF6) Bit 5 TIM9_REMAP: TIM9 remapping This bit is set and cleared by software. It controls the mapping of the TIM9_CH1 and TIM9_CH2 alternate functions onto the GPIO ports. 0: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3) 1: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6) Bits 4:0 Reserved. 193/1128 DocID13902 Rev 15 0 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.5 GPIO and AFIO register maps Refer to Table 3 on page 51 for the register boundary addresses. The following tables give the GPIO and AFIO register map and the reset values. Table 59. GPIO register map and reset values Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 14 13 15 16 20 19 18 17 21 24 23 22 25 27 26 28 29 30 31 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 GPIOx_CRL Reset value GPIOx_CRH Reset value CN F7 [1:0] 01 CN F 15 [1:0] 01 MODE 7 [1:0] 00 MODE 15 [1:0] 00 CN F6 [1:0] 01 CN F 14 [1:0] 01 MODE 6 [1:0] 00 MODE 14 [1:0] 00 CN F5 [1:0] 01 CN F 13 [1:0] 01 MODE 5 [1:0] 00 MODE 13 [1:0] 00 CNF 4 [1:0] 01 CNF 12 [1:0] 01 MODE 4 [1:0] 00 MODE 12 [1:0] 00 CN F3 [1:0] 01 CN F 11 [1:0] 01 MODE 3 [1:0] 00 MODE 11 [1:0] 00 CNF 2 [1:0] 01 CNF 10 [1:0] 01 MODE 2 [1:0] 00 MODE 10 [1:0] 00 CN F1 [1:0] 01 CN F 9 [1:0] 01 MOD E1 [1:0] 00 MOD E9 [1:0] 00 CNF 0 [1:0] 01 CNF 8 [1:0] 01 MOD E0 [1:0] 00 MOD E8 [1:0] 00 GPIOx_IDR Reset value Reserved IDRy 00 0 0 00 0 0 00 0 0 00 0 0 GPIOx_ODR Reset value Reserved ODRy 00 0 0 00 0 0 00 0 0 00 0 0 GPIOx_BSRR BR[15:0] BSR[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_BRR Reset value Reserved BR[15:0] 00 0 0 00 0 0 00 0 0 00 0 0 LCKK GPIOx_LCKR Reset value Reserved LCK[15:0] 0 00 0 0 00 0 0 00 0 0 00 0 0 Table 60. AFIO register map and reset values Offset Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 27 29 30 31 0x00 AFIO_EVCR Reset value Reserved EVOE PORT[2: 0] PIN[3:0] 0000000 SPI1_REMAP I2C1_REMAP USART1_REMAP USART2_REMAP USART3_REMAP[0] USART3_REMAP[1] TIM1_REMPAP[0] TIM1_REMPAP[1] TIM2_REMPAP[0] TIM2_REMPAP[1] TIM3_REMPAP[0] TIM3_REMPAP[1] TIM4_REMPAP CAN1_REMAP[0] CAN1_REMAP[1] PD01_REMAP TIM5CH4_IREMAP ADC1_ETRGINJ_REMAP ADC1_ETRGREG_REMAP ADC2_ETRGINJ_REMAP ADC2_ETRGREG_REMAP SWJ_CFG[0] SWJ_CFG[1] SWJ_CFG[2] 0x04 AFIO_MAPR low-, medium-, high- and XLdensity devices Reserved Reserve d Reset value 000 000000000000000000000 DocID13902 Rev 15 194/1128 195 0 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 60. AFIO register map and reset values (continued) Offset Register RM0008 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPI1_REMAP I2C1_REMAP USART1_REMAP USART2_REMAP USART3_REMAP[0] USART3_REMAP[1] TIM1_REMPAP[0] TIM1_REMPAP[1] TIM2_REMPAP[0] TIM2_REMPAP[1] TIM3_REMPAP[0] TIM3_REMPAP[1] TIM4_REMPAP CAN1_REMAP[0] CAN1_REMAP[1] PD01_REMAP TIM5CH4_IREMAP ETH_REMAP CAN2_REMAP MII_RMII_SEL SWJ_CFG[0] SWJ_CFG[1] SWJ_CFG[2] SPI3_REMAP TIM2ITR1_IREMAP PTP_PPS_REMAP Reserved Reserved 0x04 AFIO_MAPR connectivity line devices Reset value 000 000000 Reserved 00000000000000000 SPI1_REMAP I2C1_REMAP USART1_REMAP USART2_REMAP USART3_REMAP[1:0] TIM1_REMAP[1:0] TIM2_REMAP[1:0] TIM3_REMAP[1:0] TIM4_REMAP Reserved PD01_REMAP TIM5CH4_IREMAP 0x04 AFIO_MAPR Reserved SWJ_ CFG[2:0] Reserved 0x08 0x0C 0x10 0x14 Reset value AFIO_EXTICR1 Reset value AFIO_EXTICR2 Reset value AFIO_EXTICR3 Reset value AFIO_EXTICR4 Reset value 0x1C AFIO_MAPR2 Reset value 000 Reserved Reserved Reserved Reserved Reserved 00 0000000000000 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] 0000000000000000 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0] 0000000000000000 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] 0000000000000000 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] 0000000000000000 FSMC_NADV TIM14_REMAP TIM13_REMAP TIM11_REMAP TIM10_REMAP TIM9_REMAP Reserved 000000 MISC_ REMAP TIM12_REMAP TIM67_DAC_ DMA_ REMAP FSMC_NADV TIM14_REMAP TIM13_REMAP TIM1_DMA_REMAP CEC_REMAP TIM17_REMAP TIM16_REMAP TIM15_REMAP 0x1C AFIO_MAPR2 Reserved Res. Reset value 000000 Refer to Table 3 on page 51 for the register boundary addresses. 00000 195/1128 DocID13902 Rev 15 RM0008 10 Interrupts and events Interrupts and events Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to the whole STM32F10xxx family, unless otherwise specified. 10.1 10.1.1 Nested vectored interrupt controller (NVIC) Features • 68 (not including the sixteen Cortex®-M3 interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) • Low-latency exception and interrupt handling • Power management control • Implementation of System Control Registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to STM32F10xxx Cortex®-M3 programming manual (see Related documents on page 1). SysTick calibration value register The SysTick calibration value is set to 9000, which gives a reference time base of 1 ms with the SysTick clock set to 9 MHz (max HCLK/8). DocID13902 Rev 15 196/1128 213 Interrupts and events RM0008 10.1.2 Interrupt and exception vectors Table 61 and Table 63 are the vector tables for connectivity line and other STM32F10xxx devices, respectively. Table 61. Vector table for connectivity line devices Position Priority Type of priority Acronym Description Address - - - -3 fixed Reset -2 fixed NMI -1 fixed HardFault 0 settable MemManage 1 settable BusFault 2 settable UsageFault - - - 3 settable SVCall 4 settable Debug Monitor - - - 5 settable PendSV 6 settable SysTick 0 7 settable WWDG 1 8 settable PVD 2 9 settable TAMPER 3 10 settable RTC 4 11 settable FLASH 5 12 settable RCC 6 13 settable EXTI0 7 14 settable EXTI1 8 15 settable EXTI2 9 16 settable EXTI3 Reserved Reset Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. All class of fault Memory management Pre-fetch fault, memory access fault Undefined instruction or illegal state Reserved System service call via SWI instruction Debug Monitor Reserved Pendable request for system service System tick timer Window Watchdog interrupt PVD through EXTI Line detection interrupt Tamper interrupt RTC global interrupt Flash global interrupt RCC global interrupt EXTI Line0 interrupt EXTI Line1 interrupt EXTI Line2 interrupt EXTI Line3 interrupt 0x0000_0000 0x0000_0004 0x0000_0008 0x0000_000C 0x0000_0010 0x0000_0014 0x0000_0018 0x0000_001C 0x0000_002B 0x0000_002C 0x0000_0030 0x0000_0034 0x0000_0038 0x0000_003C 0x0000_0040 0x0000_0044 0x0000_0048 0x0000_004C 0x0000_0050 0x0000_0054 0x0000_0058 0x0000_005C 0x0000_0060 0x0000_0064 197/1128 DocID13902 Rev 15 RM0008 Interrupts and events Table 61. Vector table for connectivity line devices (continued) Position Priority Type of priority Acronym Description Address 10 17 settable EXTI4 11 18 settable DMA1_Channel1 12 19 settable DMA1_Channel2 13 20 settable DMA1_Channel3 14 21 settable DMA1_Channel4 15 22 settable DMA1_Channel5 16 23 settable DMA1_Channel6 17 24 settable DMA1_Channel7 18 25 settable ADC1_2 19 26 settable CAN1_TX 20 27 settable CAN1_RX0 21 28 settable CAN1_RX1 22 29 settable CAN1_SCE 23 30 settable EXTI9_5 24 31 settable TIM1_BRK 25 32 settable TIM1_UP 26 33 settable TIM1_TRG_COM 27 34 settable TIM1_CC 28 35 settable TIM2 29 36 settable TIM3 30 37 settable TIM4 31 38 settable I2C1_EV 32 39 settable I2C1_ER 33 40 settable I2C2_EV 34 41 settable I2C2_ER 35 42 settable SPI1 36 43 settable SPI2 37 44 settable USART1 38 45 settable USART2 EXTI Line4 interrupt DMA1 Channel1 global interrupt DMA1 Channel2 global interrupt DMA1 Channel3 global interrupt DMA1 Channel4 global interrupt DMA1 Channel5 global interrupt DMA1 Channel6 global interrupt DMA1 Channel7 global interrupt ADC1 and ADC2 global interrupt CAN1 TX interrupts CAN1 RX0 interrupts CAN1 RX1 interrupt CAN1 SCE interrupt EXTI Line[9:5] interrupts TIM1 Break interrupt TIM1 Update interrupt TIM1 Trigger and Commutation interrupts TIM1 Capture Compare interrupt TIM2 global interrupt TIM3 global interrupt TIM4 global interrupt I2C1 event interrupt I2C1 error interrupt I2C2 event interrupt I2C2 error interrupt SPI1 global interrupt SPI2 global interrupt USART1 global interrupt USART2 global interrupt 0x0000_0068 0x0000_006C 0x0000_0070 0x0000_0074 0x0000_0078 0x0000_007C 0x0000_0080 0x0000_0084 0x0000_0088 0x0000_008C 0x0000_0090 0x0000_0094 0x0000_0098 0x0000_009C 0x0000_00A0 0x0000_00A4 0x0000_00A8 0x0000_00AC 0x0000_00B0 0x0000_00B4 0x0000_00B8 0x0000_00BC 0x0000_00C0 0x0000_00C4 0x0000_00C8 0x0000_00CC 0x0000_00D0 0x0000_00D4 0x0000_00D8 DocID13902 Rev 15 198/1128 213 Interrupts and events RM0008 Table 61. Vector table for connectivity line devices (continued) Position Priority Type of priority Acronym Description Address 39 46 settable USART3 40 47 settable EXTI15_10 41 48 settable RTCAlarm 42 49 settable OTG_FS_WKUP -- - - 50 57 settable TIM5 51 58 settable SPI3 52 59 settable UART4 53 60 settable UART5 54 61 settable TIM6 55 62 settable TIM7 56 63 settable DMA2_Channel1 57 64 settable DMA2_Channel2 58 65 settable DMA2_Channel3 59 66 settable DMA2_Channel4 60 67 settable DMA2_Channel5 61 68 settable ETH 62 69 settable ETH_WKUP 63 70 settable CAN2_TX 64 71 settable CAN2_RX0 65 72 settable CAN2_RX1 66 73 settable CAN2_SCE 67 74 settable OTG_FS USART3 global interrupt EXTI Line[15:10] interrupts RTC alarm through EXTI line interrupt USB On-The-Go FS Wakeup through EXTI line interrupt Reserved TIM5 global interrupt SPI3 global interrupt UART4 global interrupt UART5 global interrupt TIM6 global interrupt TIM7 global interrupt DMA2 Channel1 global interrupt DMA2 Channel2 global interrupt DMA2 Channel3 global interrupt DMA2 Channel4 global interrupt DMA2 Channel5 global interrupt Ethernet global interrupt Ethernet Wakeup through EXTI line interrupt CAN2 TX interrupts CAN2 RX0 interrupts CAN2 RX1 interrupt CAN2 SCE interrupt USB On The Go FS global interrupt 0x0000_00DC 0x0000_00E0 0x0000_00E4 0x0000_00E8 0x0000_00EC 0x0000_0104 0x0000_0108 0x0000_010C 0x0000_0110 0x0000_0114 0x0000_0118 0x0000_011C 0x0000_0120 0x0000_0124 0x0000_0128 0x0000_012C 0x0000_0130 0x0000_0134 0x0000_0138 0x0000_013C 0x0000_0140 0x0000_0144 0x0000_0148 0x0000_014C 199/1128 DocID13902 Rev 15 RM0008 Interrupts and events Table 62. Vector table for XL-density devices Position Priority Type of priority Acronym Description Address --3 fixed Reset -2 fixed NMI -1 fixed HardFault 0 settable MemManage 1 settable BusFault 2 settable UsageFault -- - 3 settable SVCall 4 settable Debug Monitor -- - 5 settable PendSV 6 settable SysTick 0 7 settable WWDG 1 8 settable PVD 2 9 settable TAMPER 3 10 settable RTC 4 11 settable FLASH 5 12 settable RCC 6 13 settable EXTI0 7 14 settable EXTI1 8 15 settable EXTI2 9 16 settable EXTI3 10 17 settable EXTI4 11 18 settable DMA1_Channel1 12 19 settable DMA1_Channel2 13 20 settable DMA1_Channel3 Reserved 0x0000_0000 Reset 0x0000_0004 Nonmaskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. 0x0000_0008 All class of fault 0x0000_000C Memory management 0x0000_0010 Prefetch fault, memory access fault 0x0000_0014 Undefined instruction or illegal state 0x0000_0018 Reserved 0x0000_001C 0x0000_002B System service call via SWI instruction 0x0000_002C Debug monitor 0x0000_0030 Reserved 0x0000_0034 Pendable request for system service 0x0000_0038 Systick timer 0x0000_003C Window watchdog interrupt 0x0000_0040 PVD through EXTI Line detection interrupt 0x0000_0044 Tamper interrupt 0x0000_0048 RTC global interrupt 0x0000_004C Flash global interrupt 0x0000_0050 RCC global interrupt 0x0000_0054 EXTI Line0 interrupt 0x0000_0058 EXTI Line1 interrupt 0x0000_005C EXTI Line2 interrupt 0x0000_0060 EXTI Line3 interrupt 0x0000_0064 EXTI Line4 interrupt 0x0000_0068 DMA1 Channel1 global interrupt 0x0000_006C DMA1 Channel2 global interrupt 0x0000_0070 DMA1 Channel3 global interrupt 0x0000_0074 DocID13902 Rev 15 200/1128 213 Interrupts and events Table 62. Vector table for XL-density devices (continued) RM0008 Position Priority Type of priority Acronym Description Address 14 21 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078 15 22 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C 16 23 settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080 17 24 settable DMA1_Channel7 DMA1 Channel7 global interrupt 0x0000_0084 18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000_0088 19 26 settable USB_HP_CAN_TX USB high priority or CAN TX interrupts 0x0000_008C 20 27 settable USB_LP_CAN_RX0 USB low priority or CAN RX0 interrupts 0x0000_0090 21 28 settable CAN_RX1 CAN RX1 interrupt 0x0000_0094 22 29 settable CAN_SCE CAN SCE interrupt 0x0000_0098 23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C 24 31 settable TIM1_BRK_TIM9 TIM1 Break interrupt and TIM9 global interrupt 0x0000_00A0 25 32 settable TIM1_UP_TIM10 TIM1 Update interrupt and TIM10 global interrupt 0x0000_00A4 26 33 settable TIM1_TRG_COM_TIM11 TIM1 Trigger and Commutation interrupts and TIM11 global interrupt 0x0000_00A8 27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC 28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0 29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4 30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8 31 38 settable I2C1_EV I2C1 event interrupt 0x0000_00BC 32 39 settable I2C1_ER I2C1 error interrupt 0x0000_00C0 33 40 settable I2C2_EV I2C2 event interrupt 0x0000_00C4 34 41 settable I2C2_ER I2C2 error interrupt 0x0000_00C8 35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC 36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0 37 44 settable USART1 USART1 global interrupt 0x0000_00D4 38 45 settable USART2 USART2 global interrupt 0x0000_00D8 39 46 settable USART3 USART3 global interrupt 0x0000_00DC 40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0 201/1128 DocID13902 Rev 15 RM0008 Interrupts and events Table 62. Vector table for XL-density devices (continued) Position Priority Type of priority Acronym Description Address 41 48 settable RTCAlarm RTC alarm through EXTI line interrupt 0x0000_00E4 42 49 settable USBWakeUp USB wakeup from suspend through EXTI line interrupt 0x0000_00E8 43 50 settable TIM8_BRK_TIM12 TIM8 Break interrupt and TIM12 global interrupt 0x0000_00EC 44 51 settable TIM8_UP_TIM13 TIM8 Update interrupt and TIM13 global interrupt 0x0000_00F0 45 52 settable TIM8_TRG_COM_TIM14 TIM8 Trigger and Commutation interrupts and TIM14 global interrupt 0x0000_00F4 46 53 settable TIM8_CC TIM8 Capture Compare interrupt 0x0000_00F8 47 54 settable ADC3 ADC3 global interrupt 0x0000_00FC 48 55 settable FSMC FSMC global interrupt 0x0000_0100 49 56 settable SDIO SDIO global interrupt 0x0000_0104 50 57 settable TIM5 TIM5 global interrupt 0x0000_0108 51 58 settable SPI3 SPI3 global interrupt 0x0000_010C 52 59 settable UART4 UART4 global interrupt 0x0000_0110 53 60 settable UART5 UART5 global interrupt 0x0000_0114 54 61 settable TIM6 TIM6 global interrupt 0x0000_0118 55 62 settable TIM7 TIM7 global interrupt 0x0000_011C 56 63 settable DMA2_Channel1 DMA2 Channel1 global interrupt 0x0000_0120 57 64 settable DMA2_Channel2 DMA2 Channel2 global interrupt 0x0000_0124 58 65 settable DMA2_Channel3 DMA2 Channel3 global interrupt 0x0000_0128 59 66 settable DMA2_Channel4_5 DMA2 Channel4 and DMA2 Channel5 global interrupts 0x0000_012C DocID13902 Rev 15 202/1128 213 Interrupts and events Table 63. Vector table for other STM32F10xxx devices RM0008 Position Priority Type of priority Acronym Description Address - - - -3 fixed Reset -2 fixed NMI -1 fixed HardFault 0 settable MemManage 1 settable BusFault 2 settable UsageFault - - - 3 settable SVCall 4 settable Debug Monitor - - - 5 settable PendSV 6 settable SysTick 0 7 settable WWDG 1 8 settable PVD 2 9 settable TAMPER 3 10 settable RTC 4 11 settable FLASH 5 12 settable RCC 6 13 settable EXTI0 7 14 settable EXTI1 8 15 settable EXTI2 9 16 settable EXTI3 10 17 settable EXTI4 11 18 settable DMA1_Channel1 12 19 settable DMA1_Channel2 Reserved Reset Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. All class of fault Memory management Prefetch fault, memory access fault Undefined instruction or illegal state Reserved System service call via SWI instruction Debug Monitor Reserved Pendable request for system service System tick timer Window watchdog interrupt PVD through EXTI Line detection interrupt Tamper interrupt RTC global interrupt Flash global interrupt RCC global interrupt EXTI Line0 interrupt EXTI Line1 interrupt EXTI Line2 interrupt EXTI Line3 interrupt EXTI Line4 interrupt DMA1 Channel1 global interrupt DMA1 Channel2 global interrupt 0x0000_0000 0x0000_0004 0x0000_0008 0x0000_000C 0x0000_0010 0x0000_0014 0x0000_0018 0x0000_001C 0x0000_002B 0x0000_002C 0x0000_0030 0x0000_0034 0x0000_0038 0x0000_003C 0x0000_0040 0x0000_0044 0x0000_0048 0x0000_004C 0x0000_0050 0x0000_0054 0x0000_0058 0x0000_005C 0x0000_0060 0x0000_0064 0x0000_0068 0x0000_006C 0x0000_0070 203/1128 DocID13902 Rev 15 RM0008 Interrupts and events Table 63. Vector table for other STM32F10xxx devices (continued) Position Priority Type of priority Acronym Description Address 13 20 settable DMA1_Channel3 14 21 settable DMA1_Channel4 15 22 settable DMA1_Channel5 16 23 settable DMA1_Channel6 17 24 settable DMA1_Channel7 18 25 settable ADC1_2 19 26 settable USB_HP_CAN_ TX 20 27 settable USB_LP_CAN_ RX0 21 28 settable CAN_RX1 22 29 settable CAN_SCE 23 30 settable EXTI9_5 24 31 settable TIM1_BRK 25 32 settable TIM1_UP 26 33 settable TIM1_TRG_COM 27 34 settable TIM1_CC 28 35 settable TIM2 29 36 settable TIM3 30 37 settable TIM4 31 38 settable I2C1_EV 32 39 settable I2C1_ER 33 40 settable I2C2_EV 34 41 settable I2C2_ER 35 42 settable SPI1 36 43 settable SPI2 37 44 settable USART1 38 45 settable USART2 39 46 settable USART3 40 47 settable EXTI15_10 DMA1 Channel3 global interrupt DMA1 Channel4 global interrupt DMA1 Channel5 global interrupt DMA1 Channel6 global interrupt DMA1 Channel7 global interrupt ADC1 and ADC2 global interrupt USB High Priority or CAN TX interrupts USB Low Priority or CAN RX0 interrupts CAN RX1 interrupt CAN SCE interrupt EXTI Line[9:5] interrupts TIM1 Break interrupt TIM1 Update interrupt TIM1 Trigger and Commutation interrupts TIM1 Capture Compare interrupt TIM2 global interrupt TIM3 global interrupt TIM4 global interrupt I2C1 event interrupt I2C1 error interrupt I2C2 event interrupt I2C2 error interrupt SPI1 global interrupt SPI2 global interrupt USART1 global interrupt USART2 global interrupt USART3 global interrupt EXTI Line[15:10] interrupts 0x0000_0074 0x0000_0078 0x0000_007C 0x0000_0080 0x0000_0084 0x0000_0088 0x0000_008C 0x0000_0090 0x0000_0094 0x0000_0098 0x0000_009C 0x0000_00A0 0x0000_00A4 0x0000_00A8 0x0000_00AC 0x0000_00B0 0x0000_00B4 0x0000_00B8 0x0000_00BC 0x0000_00C0 0x0000_00C4 0x0000_00C8 0x0000_00CC 0x0000_00D0 0x0000_00D4 0x0000_00D8 0x0000_00DC 0x0000_00E0 DocID13902 Rev 15 204/1128 213 Interrupts and events RM0008 Table 63. Vector table for other STM32F10xxx devices (continued) Position Priority Type of priority Acronym Description Address 41 48 settable RTCAlarm RTC alarm through EXTI line interrupt 42 49 settable USBWakeup USB wakeup from suspend through EXTI line interrupt 43 50 settable TIM8_BRK TIM8 Break interrupt 44 51 settable TIM8_UP TIM8 Update interrupt 45 52 settable TIM8_TRG_COM TIM8 Trigger and Commutation interrupts 46 53 settable TIM8_CC TIM8 Capture Compare interrupt 47 54 settable ADC3 ADC3 global interrupt 48 55 settable FSMC FSMC global interrupt 49 56 settable SDIO SDIO global interrupt 50 57 settable TIM5 TIM5 global interrupt 51 58 settable SPI3 SPI3 global interrupt 52 59 settable UART4 UART4 global interrupt 53 60 settable UART5 UART5 global interrupt 54 61 settable TIM6 TIM6 global interrupt 55 62 settable TIM7 TIM7 global interrupt 56 63 settable DMA2_Channel1 DMA2 Channel1 global interrupt 57 64 settable DMA2_Channel2 DMA2 Channel2 global interrupt 58 65 settable DMA2_Channel3 DMA2 Channel3 global interrupt 59 66 settable DMA2_Channel4_5 DMA2 Channel4 and DMA2 Channel5 global interrupts 0x0000_00E4 0x0000_00E8 0x0000_00EC 0x0000_00F0 0x0000_00F4 0x0000_00F8 0x0000_00FC 0x0000_0100 0x0000_0104 0x0000_0108 0x0000_010C 0x0000_0110 0x0000_0114 0x0000_0118 0x0000_011C 0x0000_0120 0x0000_0124 0x0000_0128 0x0000_012C 10.2 External interrupt/event controller (EXTI) The external interrupt/event controller consists of up to 20 edge detectors in connectivity line devices, or 19 edge detectors in other devices for generating event/interrupt requests. Each input line can be independently configured to select the type (event or interrupt) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests 205/1128 DocID13902 Rev 15 RM0008 Interrupts and events 10.2.1 10.2.2 Main features The EXTI controller main features are the following: • Independent trigger and mask on each interrupt/event line • Dedicated status bit for each interrupt line • Generation of up to 20 software event/interrupt requests • Detection of external signal with pulse width lower than APB2 clock period. Refer to the electrical characteristics section of the datasheet for details on this parameter. Block diagram The block diagram is shown in Figure 20. Figure 20. External interrupt/event controller block diagram !-"! !0"BUS 0#,+ 0ERIPHERALINTERFACE      0ENDING REQUEST REGISTER )NTERRUPT MASK REGISTER 4O.6)#INTERRUPT  CONTROLLER  3OFTWARE INTERRUPT EVENT REGISTER  2ISING TRIGGER SELECTION REGISTER &ALLING TRIGGER SELECTION REGISTER   0ULSE  GENERATOR  %DGEDETECT )NPUT  CIRCUIT ,INE 10.2.3 (YHQW PDVN UHJLVWHU -36 Wakeup event management The STM32F10xxx is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex®-M3 System Control register. When the MCU DocID13902 Rev 15 206/1128 213 Interrupts and events RM0008 10.2.4 resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. • or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. In connectivity line devices, Ethernet wakeup events also have the WFE wakeup capability. To use an external line as a wakeup event, refer to Section 10.2.4: Functional description. Functional description To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a ‘1’ in the pending register. To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set An interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register. Hardware interrupt selection To configure the 20 lines as interrupt sources, use the following procedure: • Configure the mask bits of the 20 Interrupt lines (EXTI_IMR) • Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and EXTI_FTSR) • Configure the enable and mask bits that control the NVIC IRQ channel mapped to the External Interrupt Controller (EXTI) so that an interrupt coming from one of the 20 lines can be correctly acknowledged. Hardware event selection To configure the 20 lines as event sources, use the following procedure: • Configure the mask bits of the 20 Event lines (EXTI_EMR) • Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR) Software interrupt/event selection The 20 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt. • Configure the mask bits of the 20 Interrupt/Event lines (EXTI_IMR, EXTI_EMR) • Set the required bit of the software interrupt register (EXTI_SWIER) 207/1128 DocID13902 Rev 15 RM0008 Interrupts and events 10.2.5 External interrupt/event line mapping The 112 GPIOs are connected to the 16 external interrupt/event lines in the following manner: Figure 21. External interrupt/event GPIO mapping EXTI0[3:0] bits in AFIO_EXTICR1 register PA0 PB0 PC0 PD0 PE0 PF0 PG0 EXTI0 EXTI1[3:0] bits in AFIO_EXTICR1 register PA1 PB1 PC1 PD1 PE1 PF1 PG1 EXTI1 EXTI15[3:0] bits in AFIO_EXTICR4 register PA15 PB15 PC15 PD15 PE15 PF15 PG15 EXTI15 1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO clock should first be enabled. Refer to Section 7.3.7: APB2 peripheral clock enable register (RCC_APB2ENR) for low-, medium-, high- and XL-density devices and, to Section 8.3.7: APB2 peripheral clock enable register (RCC_APB2ENR) for connectivity line devices. DocID13902 Rev 15 208/1128 213 Interrupts and events RM0008 The four other EXTI lines are connected as follows: • EXTI line 16 is connected to the PVD output • EXTI line 17 is connected to the RTC Alarm event • EXTI line 18 is connected to the USB Wakeup event • EXTI line 19 is connected to the Ethernet Wakeup event (available only in connectivity line devices) 209/1128 DocID13902 Rev 15 RM0008 Interrupts and events 10.3 10.3.1 EXTI registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 Reserved 15 14 13 12 11 10 MR15 MR14 MR13 MR12 MR11 MR10 rw rw rw rw rw rw 9 MR9 rw 24 8 MR8 rw 23 7 MR7 rw 22 21 6 MR6 rw 5 MR5 rw 20 4 MR4 rw 19 MR19 rw 3 18 MR18 rw 2 17 MR17 rw 1 MR3 MR2 MR1 rw rw rw 16 MR16 rw 0 MR0 rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 MRx: Interrupt Mask on line x 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. 10.3.2 Event mask register (EXTI_EMR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 Reserved 15 14 13 12 11 10 MR15 MR14 MR13 MR12 MR11 MR10 rw rw rw rw rw rw 9 MR9 rw 24 8 MR8 rw 23 7 MR7 rw 22 21 6 MR6 rw 5 MR5 rw 20 4 MR4 rw 19 MR19 rw 3 18 MR18 rw 2 17 MR17 rw 1 MR3 MR2 MR1 rw rw rw 16 MR16 rw 0 MR0 rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 MRx: Event mask on line x 0: Event request from Line x is masked 1: Event request from Line x is not masked Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. DocID13902 Rev 15 210/1128 213 Interrupts and events RM0008 10.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TR19 TR18 rw rw TR17 rw TR16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line. Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. Note: 10.3.4 The external wakeup lines are edge triggered, no glitches must be generated on these lines. If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the pending bit will not be set. Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition. Falling trigger selection register (EXTI_FTSR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TR19 TR18 rw rw TR17 rw TR16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 TRx: Falling trigger event configuration bit of line x 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line. Note: Bit 19 used in connectivity line devices and is reserved otherwise. Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines. If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the pending bit will not be set. Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition. 211/1128 DocID13902 Rev 15 RM0008 Interrupts and events 10.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SWIER SWIER SWIER SWIER 19 18 17 16 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 SWIERx: Software interrupt on line x If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is set to '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit). Note: Bit 19 used in connectivity line devices and is reserved otherwise. 10.3.6 Pending register (EXTI_PR) Address offset: 0x14 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PR19 PR18 PR17 PR16 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 PRx: Pending bit 0: No trigger request occurred 1: selected trigger request occurred This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a ‘1’ into the bit. Note: Bit 19 is used in connectivity line devices only and is reserved otherwise. DocID13902 Rev 15 212/1128 213 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupts and events RM0008 10.3.7 EXTI register map The following table gives the EXTI register map and the reset values. Bits 19 in all registers, are used in connectivity line devices and is reserved otherwise. Table 64. External interrupt/event controller register map and reset values Offset Register 0x00 0x04 0x08 0x0C 0x10 0x14 EXTI_IMR Reset value EXTI_EMR Reset value EXTI_RTSR Reset value EXTI_FTSR Reset value EXTI_SWIER Reset value EXTI_PR Reset value Reserved Reserved Reserved Reserved Reserved Reserved MR[19:0] 00000000000000000000 MR[19:0] 00000000000000000000 TR[19:0] 00000000000000000000 TR[19:0] 00000000000000000000 SWIER[19:0] 00000000000000000000 PR[19:0] 00000000000000000000 Refer to Table 3 on page 51 for the register boundary addresses. 213/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11 Analog-to-digital converter (ADC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to the whole STM32F10xxx family, unless otherwise specified. 11.1 ADC introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it measure signals from 16 external and two internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register. The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined high or low thresholds. The ADC input clock is generated from the PCLK2 clock divided by a prescaler and it must not exceed 14 MHz, refer to Figure 8: Clock tree for low-, medium-, high- and XL-density devices, and to Figure 11: Clock tree for connectivity line devices. DocID13902 Rev 15 214/1128 252 Analog-to-digital converter (ADC) RM0008 11.2 Note: ADC main features • 12-bit resolution • Interrupt generation at End of Conversion, End of Injected conversion and Analog watchdog event • Single and continuous conversion modes • Scan mode for automatic conversion of channel 0 to channel ‘n’ • Self-calibration • Data alignment with in-built data coherency • Channel by channel programmable sampling time • External trigger option for both regular and injected conversion • Discontinuous mode • Dual mode (on devices with 2 ADCs or more) • ADC conversion time: – STM32F103xx performance line devices: 1 µs at 56 MHz (1.17 µs at 72 MHz) – STM32F101xx access line devices: 1 µs at 28 MHz (1.55 µs at 36 MHz) – STM32F102xx USB access line devices: 1.2 µs at 48 MHz – STM32F105xx and STM32F107xx devices: 1 µs at 56 MHz (1.17 µs at 72 MHz) • ADC supply requirement: 2.4 V to 3.6 V • ADC input range: VREF- ≤ VIN ≤ VREF+ • DMA request generation during regular channel conversion The block diagram of the ADC is shown in Figure 22. VREF-,if available (depending on package), must be tied to VSSA. 11.3 ADC functional description Figure 22 shows a single ADC block diagramand Table 65 gives the ADC pin description. 215/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) Figure 22. Single ADC block diagram Flags End of conversion EOC End of injected conversion JEOC Analog watchdog event AWD Interrupt enable bits EOCIE JEOCIE AWDIE Analog watchdog Compare Result High Threshold (12 bits) Low Threshold (12 bits) ADC Interrupt to NVIC Address/data bus VREF+ VREFVDDA VSSA ADCx_IN0 Analog MUX Injected data registers (4 x 16 bits) Regular data register (16 bits) DMA request ADCx_IN1 ADCx_IN15 GPIO Ports Temp. sensor VREFINT up to 4 up to 16 Injected channels Regular channels Analog to digital converter ADCCLK JEXTSEL[2:0] bits TIM1_TRGO TIM1_CH4 TIM2_TRGO TIM2_CH1 TIM3_CH4 TIM4_TRGO JEXTRIG bit Start trigger (injected group) From ADC prescaler EXTI_15 TIM8_CH4(2) ADCx-ETRGINJ_REMAP bit EXTRI G bit EXTSEL[2:0] bits TIM1_CH1 TIM1_CH2 TIM1_CH3 TIM2_CH2 TIM3_TRGO TIM4_CH4 Start trigger (regular group) EXTI_11 TIM8_TRGO(2) ADCx_ETRGREG_REMAP bit JEXTSEL[2:0] bits TIM1_TRGO TIM1_CH4 TIM4_CH3 TIM8_CH2 TIM8_CH4 TIM5_TRGO TIM5_CH4 JEXTRIG bit Start trigger (injected group) EXTSEL[2:0] bits TIM3_CH1 TIM2_CH3 TIM1_CH3 TIM8_CH1 TIM8_TRGO TIM5_CH1 TIM5_CH3 EXTRIG bit Start trigger (regular group) Triggers for ADC3(1) ai14802d 1. ADC3 has regular and injected conversion triggers different from those of ADC1 and ADC2. 2. TIM8_CH4 and TIM8_TRGO with their corresponding remap bits exist only in High-density and XL-density products. DocID13902 Rev 15 216/1128 252 Analog-to-digital converter (ADC) RM0008 Table 65. ADC pins Name Signal type Remarks VREF+ VDDA(1) VREFVSSA(1) ADCx_IN[15:0] Input, analog reference positive Input, analog supply Input, analog reference negative Input, analog supply ground Analog signals The higher/positive reference voltage for the ADC, 2.4 V ≤ VREF+ ≤ VDDA Analog power supply equal to VDD and 2.4 V ≤ VDDA ≤ 3.6 V The lower/negative reference voltage for the ADC, VREF- = VSSA Ground for analog power supply equal to VSS Up to 21 analog channels(2) 1. VDDA and VSSA have to be connected to VDD and VSS, respectively. 2. For full details about the ADC I/O pins, please refer to the “Pinouts and pin descriptions” section of the corresponding device datasheet. 217/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.3.1 11.3.2 11.3.3 Note: 11.3.4 ADC on-off control The ADC can be powered-on by setting the ADON bit in the ADC_CR2 register. When the ADON bit is set for the first time, it wakes up the ADC from Power Down mode. Conversion starts when ADON bit is set for a second time by software after ADC power-up time (tSTAB). You can stop conversion and put the ADC in power down mode by resetting the ADON bit. In this mode the ADC consumes almost no power (only a few µA). ADC clock The ADCCLK clock provided by the Clock Controller is synchronous with the PCLK2 (APB2 clock). The RCC controller has a dedicated programmable prescaler for the ADC clock (refer to Low-, medium-, high- and XL-density reset and clock control (RCC) on page 90for more details. Channel selection There are 16 multiplexed channels. It is possible to organize the conversions in two groups: regular and injected. A group consists of a sequence of conversions which can be done on any channel and in any order. For instance, it is possible to do the conversion in the following order: Ch3, Ch8, Ch2, Ch2, Ch0, Ch2, Ch2, Ch15. • The regular group is composed of up to 16 conversions. The regular channels and their order in the conversion sequence must be selected in the ADC_SQRx registers. The total number of conversions in the regular group must be written in the L[3:0] bits in the ADC_SQR1 register. • The injected group is composed of up to 4 conversions. The injected channels and their order in the conversion sequence must be selected in the ADC_JSQR register. The total number of conversions in the injected group must be written in the L[1:0] bits in the ADC_JSQR register. If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the ADC to convert the new chosen group. Temperature sensor/VREFINT internal channels The Temperature sensor is connected to channel ADCx_IN16 and the internal reference voltage VREFINT is connected to ADCx_IN17. These two internal channels can be selected and converted as injected or regular channels. The sensor and VREFINT are only available on the master ADC1 peripheral. Single conversion mode In Single conversion mode the ADC does one conversion. This mode is started either by setting the ADON bit in the ADC_CR2 register (for a regular channel only) or by external trigger (for a regular or injected channel), while the CONT bit is 0. DocID13902 Rev 15 218/1128 252 Analog-to-digital converter (ADC) RM0008 11.3.5 11.3.6 Once the conversion of the selected channel is complete: • If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set – and an interrupt is generated if the EOCIE is set. • If an injected channel was converted: – The converted data is stored in the 16-bit ADC_DRJ1 register – The JEOC (End Of Conversion Injected) flag is set – and an interrupt is generated if the JEOCIE bit is set. The ADC is then stopped. Continuous conversion mode In continuous conversion mode ADC starts another conversion as soon as it finishes one. This mode is started either by external trigger or by setting the ADON bit in the ADC_CR2 register, while the CONT bit is 1. After each conversion: • If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set – An interrupt is generated if the EOCIE is set. • If an injected channel was converted: – The converted data is stored in the 16-bit ADC_DRJ1 register – The JEOC (End Of Conversion Injected) flag is set – An interrupt is generated if the JEOCIE bit is set. Timing diagram As shown in Figure 23, the ADC needs a stabilization time of tSTAB before it starts converting accurately. After the start of ADC conversion and after 14 clock cycles, the EOC flag is set and the 16-bit ADC Data register contains the result of the conversion. Figure 23. Timing diagram ADC_CLK SET ADON ADC power on Start 1st conversion Start next conversion ADC EOC tSTAB ADC Conversion Conversion Time (total conv time) Next ADC Conversion Software resets EOC bit 219/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.3.7 Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by using the AWDIE bit in the ADC_CR1 register. The threshold value is independent of the alignment selected by the ALIGN bit in the ADC_CR2 register. The comparison is done before the alignment (see Section 11.5). The analog watchdog can be enabled on one or more channels by configuring the ADC_CR1 register as shown in Table 66. Figure 24. Analog watchdog guarded area Analog voltage High threshold Low threshold Guarded area HTR LTR 11.3.8 Table 66. Analog watchdog channel selection Channels to be guarded by analog watchdog ADC_CR1 register control bits (x = don’t care) AWDSGL bit AWDEN bit JAWDEN bit None x 0 0 All injected channels 0 0 1 All regular channels 0 1 0 All regular and injected channels 0 1 1 Single(1) injected channel 1 0 1 Single(1) regular channel 1 1 0 Single(1) regular or injected channel 1 1 1 1. Selected by AWDCH[4:0] bits Scan mode This mode is used to scan a group of analog channels. Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular channels) or in the ADC_JSQR (for injected channels). A single conversion is performed for each channel of the group. After each end of conversion the next channel of the group is converted automatically. If the CONT bit is set, conversion does not stop at the last selected group channel but continues again from the first selected group channel. When using scan mode, DMA bit must be set and the direct memory access controller is used to transfer the converted data of regular group channels to SRAM after each update of the ADC_DR register. The injected channel converted data is always stored in the ADC_JDRx registers. DocID13902 Rev 15 220/1128 252 Analog-to-digital converter (ADC) RM0008 11.3.9 Note: Note: Injected channel management Triggered injection To use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the ADC_CR1 register. 1. Start conversion of a group of regular channels either by external trigger or by setting the ADON bit in the ADC_CR2 register. 2. If an external injected trigger occurs during the regular group channel conversion, the current conversion is reset and the injected channel sequence is converted in Scan once mode. 3. Then, the regular group channel conversion is resumed from the last interrupted regular conversion. If a regular event occurs during an injected conversion, it doesn’t interrupt it but the regular sequence is executed at the end of the injected sequence. Figure 25 shows the timing diagram. When using triggered injection, the interval between trigger events must be longer than the injection sequence. For instance, if the sequence length is 28 ADC clock cycles (that is two conversions with a 1.5 clock-period sampling time), the minimum interval between triggers must be 29 ADC clock cycles. Auto-injection If the JAUTO bit is set, then the injected group channels are automatically converted after the regular group channels. This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRx and ADC_JSQR registers. In this mode, external trigger on injected channels must be disabled. If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected channels are continuously converted. For ADC clock prescalers ranging from 4 to 8, a delay of 1 ADC clock period is automatically inserted when switching from regular to injected sequence (respectively injected to regular). When the ADC clock prescaler is set to 2, the delay is 2 ADC clock periods. It is not possible to use both auto-injected and discontinuous modes simultaneously. Figure 25. Injected conversion latency ADC clock Inj. event Reset ADC SOC max latency(1) 1. The maximum latency value can be found in the electrical characteristics of the STM32F101xx and STM32F103xx datasheets. 221/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.3.10 Note: Note: Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n <=8) which is a part of the sequence of conversions selected in the ADC_SQRx registers. The value of n is specified by writing to the DISCNUM[2:0] bits in the ADC_CR1 register. When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx registers until all the conversions in the sequence are done. The total sequence length is defined by the L[3:0] bits in the ADC_SQR1 register. Example: n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion 2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each conversion 3rd trigger: sequence converted 9, 10. An EOC event is generated at each conversion 4th trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion When a regular group is converted in discontinuous mode, no rollover will occur. When all sub groups are converted, the next trigger starts conversion of the first sub-group. In the example above, the 4th trigger reconverts the 1st sub-group channels 0, 1 and 2. Injected group This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to convert the sequence selected in the ADC_JSQR register, channel by channel, after an external trigger event. When an external trigger occurs, it starts the next channel conversions selected in the ADC_JSQR registers until all the conversions in the sequence are done. The total sequence length is defined by the JL[1:0] bits in the ADC_JSQR register. Example: n = 1, channels to be converted = 1, 2, 3 1st trigger: channel 1 converted 2nd trigger: channel 2 converted 3rd trigger: channel 3 converted and EOC and JEOC events generated 4th trigger: channel 1 When all injected channels are converted, the next trigger starts the conversion of the first injected channel. In the example above, the 4th trigger reconverts the 1st injected channel 1. It is not possible to use both auto-injected and discontinuous modes simultaneously. The user must avoid setting discontinuous mode for both regular and injected groups together. Discontinuous mode must be enabled only for one group conversion. 11.4 Calibration The ADC has an built-in self calibration mode. Calibration significantly reduces accuracy errors due to internal capacitor bank variations. During calibration, an error-correction code DocID13902 Rev 15 222/1128 252 Analog-to-digital converter (ADC) RM0008 Note: (digital word) is calculated for each capacitor, and during all subsequent conversions, the error contribution of each capacitor is removed using this code. Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is over, the CAL bit is reset by hardware and normal conversion can be performed. It is recommended to calibrate the ADC once at power-on. The calibration codes are stored in the ADC_DR as soon as the calibration phase ends. It is recommended to perform a calibration after each power-up. Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’) for at least two ADC clock cycles. Figure 26. Calibration timing diagram CLK CAL ADC Conversion Calibration ongoing tCAL Calibration Reset by Hardware Normal ADC Conversion 11.5 Data alignment ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion. Data can be left or right aligned as shown in Figure 27. and Figure 28. The injected group channels converted data value is decreased by the user-defined offset written in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit is the extended sign value. For regular group channels no offset is subtracted so only twelve bits are significant. Figure 27. Right alignment of data Injected group SEXT SEXT SEXT SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Regular group 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 28. Left alignment of data Injected group SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 Regular group D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 00 223/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.6 Channel-by-channel programmable sample time ADC samples the input voltage for a number of ADC_CLK cycles which can be modified using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sample time. The total conversion time is calculated as follows: Tconv = Sampling time + 12.5 cycles Example: With an ADCCLK = 14 MHz and a sampling time of 1.5 cycles: Tconv = 1.5 + 12.5 = 14 cycles = 1 µs 11.7 Note: Conversion on external trigger Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXTTRIG control bit is set then external events are able to trigger a conversion. The EXTSEL[2:0] and JEXTSEL[2:0] control bits allow the application to select decide which out of 8 possible events can trigger conversion for the regular and injected groups. When an external trigger is selected for ADC regular or injected conversion, only the rising edge of the signal can start the conversion. Table 67. External trigger for regular channels for ADC1 and ADC2 Source Type EXTSEL[2:0] TIM1_CC1 event 000 TIM1_CC2 event TIM1_CC3 event TIM2_CC2 event TIM3_TRGO event TIM4_CC4 event EXTI line 11/TIM8_TRGO event(1)(2) SWSTART 001 Internal signal from on-chip 010 timers 011 100 101 External pin/Internal signal from on-chip timers 110 Software control bit 111 1. The TIM8_TRGO event exists only in high-density and XL-density devices. 2. The selection of the external trigger EXTI line11 or TIM8_TRGO event for regular channels is done through configuration bits ADC1_ETRGREG_REMAP and ADC2_ETRGREG_REMAP for ADC1 and ADC2, respectively. DocID13902 Rev 15 224/1128 252 Analog-to-digital converter (ADC) RM0008 Table 68. External trigger for injected channels for ADC1 and ADC2 Source Connection type JEXTSEL[2:0] TIM1_TRGO event TIM1_CC4 event TIM2_TRGO event TIM2_CC1 event TIM3_CC4 event TIM4_TRGO event EXTI line 15/TIM8_CC4 event(1)(2) JSWSTART 000 001 Internal signal from on-chip 010 timers 011 100 101 External pin/Internal signal from on-chip timers 110 Software control bit 111 1. The TIM8_CC4 event exists only in high-density and XL-density devices. 2. The selection of the external trigger EXTI line15 or TIM8_CC4 event for injected channels is done through configuration bits ADC1_ETRGINJ_REMAP and ADC2_ETRGINJ_REMAP for ADC1 and ADC2, respectively. Table 69. External trigger for regular channels for ADC3 Source Connection type EXTSEL[2:0] TIM3_CC1 event 000 TIM2_CC3 event 001 TIM1_CC3 event TIM8_CC1 event TIM8_TRGO event 010 Internal signal from on-chip timers 011 100 TIM5_CC1 event 101 TIM5_CC3 event 110 SWSTART Software control bit 111 Table 70. External trigger for injected channels for ADC3 Source Connection type JEXTSEL[2:0] TIM1_TRGO event 000 TIM1_CC4 event 001 TIM4_CC3 event TIM8_CC2 event TIM8_CC4 event 010 Internal signal from on-chip timers 011 100 TIM5_TRGO event 101 TIM5_CC4 event 110 JSWSTART Software control bit 111 225/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) The software source trigger events can be generated by setting a bit in a register (SWSTART and JSWSTART in ADC_CR2). A regular group conversion can be interrupted by an injected trigger. 11.8 Note: DMA request Since converted regular channels value are stored in a unique data register, it is necessary to use DMA for conversion of more than one regular channel. This avoids the loss of data already stored in the ADC_DR register. Only the end of conversion of a regular channel generates a DMA request, which allows the transfer of its converted data from the ADC_DR register to the destination location selected by the user. Only ADC1 and ADC3 have this DMA capability. ADC2-converted data can be transferred in dual ADC mode using DMA thanks to master ADC1. DocID13902 Rev 15 226/1128 252 Analog-to-digital converter (ADC) RM0008 11.9 Note: Note: Dual ADC mode In devices with two ADCs or more, dual ADC mode can be used (see Figure 29). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0] bits in the ADC1_CR1 register. In dual mode, when configuring conversion to be triggered by an external event, the user must set the trigger for the master only and set a software trigger for the slave to prevent spurious triggers to start unwanted slave conversion. However, external triggers must be enabled on both master and slave ADCs. The following six possible modes are implemented: – Injected simultaneous mode – Regular simultaneous mode – Fast interleaved mode – Slow interleaved mode – Alternate trigger mode – Independent mode It is also possible to use the previous modes combined in the following ways: – Injected simultaneous mode + Regular simultaneous mode – Regular simultaneous mode + Alternate trigger mode – Injected simultaneous mode + Interleaved mode In dual ADC mode, to read the slave converted data on the master data register, the DMA bit must be enabled even if it is not used to transfer converted regular channel data. 227/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) Figure 29. Dual ADC block diagram(1) Address/data bus Regular data register (1(216bibtsit)s) Injected data registers (4 x 16 bits) Regular channels injected channels ADC2 (Slave) internal triggers Regular data register (16 bits)(2) Injected data registers (4 x 16 bits) ADCx_IN0 ADCx_IN1 ADCx_IN15 GPIO Ports Temp. sensor VREFINT EXTI_11 Start trigger mux (regular group) Regular channels Injected channels Dual mode control ADC1 (Master) EXTI_15 Start trigger mux (injected group) 1. External triggers are present on ADC2 but are not shown for the purposes of this diagram. 2. In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted data over the entire 32 bits. DocID13902 Rev 15 228/1128 252 Analog-to-digital converter (ADC) RM0008 11.9.1 Note: Note: Injected simultaneous mode This mode converts an injected channel group. The source of external trigger comes from the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits in the ADC1_CR2 register). A simultaneous trigger is provided to ADC2. Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). At the end of conversion event on ADC1 or ADC2: • The converted data is stored in the ADC_JDRx registers of each ADC interface. • An JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the ADC1/ADC2 injected channels are all converted. In simultaneous mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and ADC2. Figure 30. Injected simultaneous mode on 4 channels ADC2 ADC1 CH0 CH3 Trigger CH1 CH2 CH2 CH1 CH3 CH0 Sampling Conversion End of injected conversion on ADC1 and ADC2 11.9.2 Note: Note: Regular simultaneous mode This mode is performed on a regular channel group. The source of the external trigger comes from the regular group mux of ADC1 (selected by the EXTSEL[2:0] bits in the ADC1_CR2 register). A simultaneous trigger is provided to the ADC2. Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel). At the end of conversion event on ADC1 or ADC2: • A 32-bit DMA transfer request is generated (if DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword. • An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when ADC1/ADC2 regular channels are all converted. In regular simultaneous mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and ADC2. 229/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) Figure 31. Regular simultaneous mode on 16 channels ADC1 ADC2 CH0 CH15 CH1 CH14 CH2 CH13 CH3 ... CH12 ... Trigger CH15 CH0 Sampling Conversion End of conversion on ADC1 and ADC2 11.9.3 Note: 11.9.4 Note: Fast interleaved mode This mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux of ADC1. After an external trigger occurs: • ADC2 starts immediately and • ADC1 starts after a delay of 7 ADC clock cycles. If CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are continuously converted. After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword. The maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap between ADC1 and ADC2 sampling phases in the event that they convert the same channel. Figure 32. Fast interleaved mode on 1 channel in continuous conversion mode ADC2 ADC1 End of conversion on ADC2 CH0 ... CH0 CH0 ... CH0 Trigger End of conversion on ADC1 7 ADCCLK cycles Sampling Conversion Slow interleaved mode This mode can be started only on a regular channel group (only one channel). The source of external trigger comes from regular channel mux of ADC1. After external trigger occurs: • ADC2 starts immediately and • ADC1 starts after a delay of 14 ADC clock cycles. • ADC2 starts after a second delay of 14 ADC cycles, and so on. The maximum sampling time allowed is <14 ADCCLK cycles to avoid an overlap with the next conversion. DocID13902 Rev 15 230/1128 252 Analog-to-digital converter (ADC) RM0008 Note: 11.9.5 After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword. A new ADC2 start is automatically generated after 28 ADC clock cycles CONT bit can not be set in the mode since it continuously converts the selected regular channel. The application must ensure that no external trigger for injected channel occurs when interleaved mode is enabled. Figure 33. Slow interleaved mode on 1 channel End of conversion on ADC2 ADC2 ADC1 Trigger CH0 CH0 CH0 CH0 End of conversion on ADC1 14 ADCCLK cycles 28 ADCCLK cycles Sampling Conversion Alternate trigger mode This mode can be started only on an injected channel group. The source of external trigger comes from the injected group mux of ADC1. • When the 1st trigger occurs, all injected group channels in ADC1 are converted. • When the 2nd trigger arrives, all injected group channels in ADC2 are converted • and so on. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are converted. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are converted. If another external trigger occurs after all injected group channels have been converted then the alternate trigger process restarts by converting ADC1 injected group channels. Figure 34. Alternate trigger: injected channel group of each ADC 1st trigger 3rd trigger EOC, JEOC EOC, JEOC on ADC1 on ADC1 (n)th trigger Sampling Conversion ADC1 ... ADC2 2nd trigger EOC, JEOC EOC, JEOC on ADC2 on ADC2 4th trigger (n+1)th trigger 231/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) If the injected discontinuous mode is enabled for both ADC1 and ADC2: • When the 1st trigger occurs, the first injected channel in ADC1 is converted. • When the 2nd trigger arrives, the first injected channel in ADC2 are converted • and so on.... A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are converted. A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are converted. If another external trigger occurs after all injected group channels have been converted then the alternate trigger process restarts. Figure 35. Alternate trigger: 4 injected channels (each ADC) in discontinuous model 1st trigger 3rd trigger 5th trigger 7th trigger JEOC on ADC1 Sampling Conversion ADC1 ADC2 2nd trigger 4th trigger 6th trigger JEOC on ADC2 8th trigger 11.9.6 11.9.7 Note: 11.9.8 Note: Independent mode In this mode the dual ADC synchronization is bypassed and each ADC interfaces works independently. Combined regular/injected simultaneous mode It is possible to interrupt simultaneous conversion of a regular group to start simultaneous conversion of an injected group. In combined regular/injected simultaneous mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and ADC2. Combined regular simultaneous + alternate trigger mode It is possible to interrupt regular group simultaneous conversion to start alternate trigger conversion of an injected group. Figure 36 shows the behavior of an alternate trigger interrupting a regular simultaneous conversion. The injected alternate conversion is immediately started after the injected event arrives. If regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of both (master/slave) ADCs is stopped and resumed synchronously at the end of the injected conversion. In combined regular simultaneous + alternate trigger mode, exactly the same sampling time should be configured for the two channels that will be sampled simultaneously by ACD1 and ADC2. DocID13902 Rev 15 232/1128 252 Analog-to-digital converter (ADC) Figure 36. Alternate + Regular simultaneous 1st trig RM0008 ADC1 reg ADC1 inj ADC2 reg ADC2 inj CH0 CH3 CH1 CH5 CH2 CH0 CH6 CH2 CH3 CH6 CH7 CH0 CH3 CH4 CH7 CH8 synchro not lost 2nd trig If a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored. Figure 37 shows the behavior in this case (2nd trig is ignored). Figure 37. Case of trigger occurring during injected conversion 1st trig 3rd trig 11.9.9 Note: ADC1 reg ADC1 inj ADC2 reg ADC2 inj CH0 CH3 CH1 CH5 CH2 CH0 CH6 2nd trig CH2 CH3 CH6 CH7 CH0 CH3 CH7 CH4 CH0 CH8 4th trig Combined injected simultaneous + interleaved It is possible to interrupt an interleaved conversion with an injected event. In this case the interleaved conversion is interrupted and the injected conversion starts, at the end of the injected sequence the interleaved conversion is resumed. Figure 38 shows the behavior using an example. When the ADC clock prescaler is set to 4, the interleaved mode does not recover with evenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6 ADC clock periods, instead of 7 clock periods followed by 7 clock periods. Figure 38. Interleaved single channel with injected sequence CH11, CH12 ADC1 ADC2 CH0 CH0 CH0 CH0 CH0 CH0 Trigger CH11 CH12 CH12 CH11 Sampling Conversion CH0 CH0 CH0 CH0 233/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.10 Note: Temperature sensor The temperature sensor can be used to measure the ambient temperature (TA) of the device. The temperature sensor is internally connected to the ADCx_IN16 input channel which is used to convert the sensor output voltage into a digital value. The recommended sampling time for the temperature sensor is 17.1 µs. The block diagram of the temperature sensor is shown in Figure 39. When not in use, this sensor can be put in power down mode. The TSVREFE bit must be set to enable both internal channels: ADCx_IN16 (temperature sensor) and ADCx_IN17 (VREFINT) conversion. The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to 45 °C from one chip to another). The internal temperature sensor is more suited to applications that detect temperature variations instead of absolute temperatures. If accurate temperature readings are needed, an external temperature sensor part should be used. Figure 39. Temperature sensor and VREFINT channel block diagram TSVREFE control bit Address/data bus TEMPERATURE SENSOR INTERNAL POWER BLOCK VSENSE VREFINT ADCx_IN16 ADC1 ADCx_IN17 converted data DocID13902 Rev 15 234/1128 252 Analog-to-digital converter (ADC) RM0008 Note: Reading the temperature To use the sensor: 1. Select the ADCx_IN16 input channel. 2. Select a sample time of 17.1 µs 3. Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the temperature sensor from power down mode. 4. Start the ADC conversion by setting the ADON bit (or by external trigger). 5. Read the resulting VSENSE data in the ADC data register 6. Obtain the temperature using the following formula: Temperature (in °C) = {(V25 - VSENSE) / Avg_Slope} + 25. Where, V25 = VSENSE value for 25° C and Avg_Slope = Average Slope for curve between Temperature vs. VSENSE (given in mV/° C or µV/ °C). Refer to the Electrical characteristics section for the actual values of V25 and Avg_Slope. The sensor has a startup time after waking from power down mode before it can output VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADON and TSVREFE bits should be set at the same time. 11.11 Note: ADC interrupts An interrupt can be produced on end of conversion for regular and injected groups and when the analog watchdog status bit is set. Separate interrupt enable bits are available for flexibility. ADC1 and ADC2 interrupts are mapped onto the same interrupt vector. ADC3 interrupts are mapped onto a separate interrupt vector. Two other flags are present in the ADC_SR register, but there is no interrupt associated with them: • JSTRT (Start of conversion for injected group channels) • STRT (Start of conversion for regular group channels) Table 71. ADC interrupts Interrupt event Event flag End of conversion regular group End of conversion injected group Analog watchdog status bit is set EOC JEOC AWD Enable Control bit EOCIE JEOCIE AWDIE 235/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.12 ADC registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 11.12.1 ADC status register (ADC_SR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved STRT JSTRT JEOC rc_w0 rc_w0 rc_w0 EOC rc_w0 AWD rc_w0 Bits 31:5 Reserved, must be kept at reset value. Bit 4 STRT: Regular channel Start flag This bit is set by hardware when regular channel conversion starts. It is cleared by software. 0: No regular channel conversion started 1: Regular channel conversion has started Bit 3 JSTRT: Injected channel Start flag This bit is set by hardware when injected channel group conversion starts. It is cleared by software. 0: No injected group conversion started 1: Injected group conversion has started Bit 2 JEOC: Injected channel end of conversion This bit is set by hardware at the end of all injected group channel conversion. It is cleared by software. 0: Conversion is not complete 1: Conversion complete Bit 1 EOC: End of conversion This bit is set by hardware at the end of a group channel conversion (regular or injected). It is cleared by software or by reading the ADC_DR. 0: Conversion is not complete 1: Conversion complete Bit 0 AWD: Analog watchdog flag This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software. 0: No Analog watchdog event occurred 1: Analog watchdog event occurred DocID13902 Rev 15 236/1128 252 Analog-to-digital converter (ADC) RM0008 11.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 15 14 13 DISCNUM[2:0] rw rw rw 28 27 26 25 Reserved 12 JDISCE N rw 11 DISC EN rw 10 JAUTO rw 9 AWD SGL rw 24 8 SCAN rw 23 AWDE N 22 JAWDE N rw rw 21 20 Reserved 7 6 5 4 JEOC IE AWDIE EOCIE rw rw rw rw 19 18 17 16 DUALMOD[3:0] rw rw rw rw 3 2 1 0 AWDCH[4:0] rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software. 0: Analog watchdog disabled on regular channels 1: Analog watchdog enabled on regular channels Bit 22 JAWDEN: Analog watchdog enable on injected channels This bit is set/reset by software. 0: Analog watchdog disabled on injected channels 1: Analog watchdog enabled on injected channels Bits 21:20 Reserved, must be kept at reset value. Bits 19:16 DUALMOD[3:0]: Dual mode selection These bits are written by software to select the operating mode. 0000: Independent mode. 0001: Combined regular simultaneous + injected simultaneous mode 0010: Combined regular simultaneous + alternate trigger mode 0011: Combined injected simultaneous + fast interleaved mode 0100: Combined injected simultaneous + slow Interleaved mode 0101: Injected simultaneous mode only 0110: Regular simultaneous mode only 0111: Fast interleaved mode only 1000: Slow interleaved mode only 1001: Alternate trigger mode only Note: These bits are reserved in ADC2 and ADC3. In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change. Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. 000: 1 channel 001: 2 channels ....... 111: 8 channels 237/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) Bit 12 JDISCEN: Discontinuous mode on injected channels This bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Bit 11 DISCEN: Discontinuous mode on regular channels This bit set and cleared by software to enable/disable Discontinuous mode on regular channels. 0: Discontinuous mode on regular channels disabled 1: Discontinuous mode on regular channels enabled Bit 10 JAUTO: Automatic Injected Group conversion This bit set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. 0: Automatic injected group conversion disabled 1: Automatic injected group conversion enabled Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode This bit set and cleared by software to enable/disable the analog watchdog on the channel identified by the AWDCH[4:0] bits. 0: Analog watchdog enabled on all channels 1: Analog watchdog enabled on a single channel Bit 8 SCAN: Scan mode This bit is set and cleared by software to enable/disable Scan mode. In Scan mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted. 0: Scan mode disabled 1: Scan mode enabled Note: An EOC or JEOC interrupt is generated only on the end of conversion of the last channel if the corresponding EOCIE or JEOCIE bit is set Bit 7 JEOCIE: Interrupt enable for injected channels This bit is set and cleared by software to enable/disable the end of conversion interrupt for injected channels. 0: JEOC interrupt disabled 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. DocID13902 Rev 15 238/1128 252 Analog-to-digital converter (ADC) RM0008 Bit 6 AWDIE: Analog watchdog interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. 0: Analog watchdog interrupt disabled 1: Analog watchdog interrupt enabled Bit 5 EOCIE: Interrupt enable for EOC This bit is set and cleared by software to enable/disable the End of Conversion interrupt. 0: EOC interrupt disabled 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set. Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits These bits are set and cleared by software. They select the input channel to be guarded by the Analog watchdog. 00000: ADC analog Channel0 00001: ADC analog Channel1 .... 01111: ADC analog Channel15 10000: ADC analog Channel16 10001: ADC analog Channel17 Other values reserved. Note: ADC1 analog Channel16 and Channel17 are internally connected to the temperature sensor and to VREFINT, respectively. ADC2 analog inputs Channel16 and Channel17 are internally connected to VSS. ADC3 analog inputs Channel9, Channel14, Channel15, Channel16 and Channel17 are connected to VSS. 11.12.3 ADC control register 2 (ADC_CR2) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 Reserved 15 JEXTT RIG rw 14 13 12 JEXTSEL[2:0] rw rw rw 11 ALIGN rw 10 9 Reserved Res. 24 8 DMA rw 23 22 21 20 TSVRE SWSTA JSWST EXTTR FE RT ART IG rw rw rw rw 7 6 5 4 Reserved 19 18 17 EXTSEL[2:0] rw 3 RST CAL rw rw rw 2 1 CAL CONT rw rw 16 Res. 0 ADON rw 239/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) Bits 31:24 Reserved, must be kept at reset value. Bit 23 TSVREFE: Temperature sensor and VREFINT enable This bit is set and cleared by software to enable/disable the temperature sensor and VREFINT channel. In devices with dual ADCs this bit is present only in ADC1. 0: Temperature sensor and VREFINT channel disabled 1: Temperature sensor and VREFINT channel enabled Bit 22 SWSTART: Start conversion of regular channels This bit is set by software to start conversion and cleared by hardware as soon as conversion starts. It starts a conversion of a group of regular channels if SWSTART is selected as trigger event by the EXTSEL[2:0] bits. 0: Reset state 1: Starts conversion of regular channels Bit 21 JSWSTART: Start conversion of injected channels This bit is set by software and cleared by software or by hardware as soon as the conversion starts. It starts a conversion of a group of injected channels (if JSWSTART is selected as trigger event by the JEXTSEL[2:0] bits. 0: Reset state 1: Starts conversion of injected channels Bit 20 EXTTRIG: External trigger conversion mode for regular channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 19:17 EXTSEL[2:0]: External event select for regular group These bits select the external event used to trigger the start of conversion of a regular group: For ADC1 and ADC2, the assigned triggers are: 000: Timer 1 CC1 event 001: Timer 1 CC2 event 010: Timer 1 CC3 event 011: Timer 2 CC2 event 100: Timer 3 TRGO event 101: Timer 4 CC4 event 110: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XLdensity devices) 111: SWSTART Bit 16 For ADC3, the assigned triggers are: 000: Timer 3 CC1 event 001: Timer 2 CC3 event 010: Timer 1 CC3 event 011: Timer 8 CC1 event 100: Timer 8 TRGO event 101: Timer 5 CC1 event 110: Timer 5 CC3 event 111: SWSTART Reserved, must be kept at reset value. DocID13902 Rev 15 240/1128 252 Analog-to-digital converter (ADC) RM0008 Bit 15 JEXTTRIG: External trigger conversion mode for injected channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of an injected channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 14:12 JEXTSEL[2:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected group: For ADC1 and ADC2 the assigned triggers are: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 2 TRGO event 011: Timer 2 CC1 event 100: Timer 3 CC4 event 101: Timer 4 TRGO event 110: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XLdensity devices) 111: JSWSTART For ADC3 the assigned triggers are: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 4 CC3 event 011: Timer 8 CC2 event 100: Timer 8 CC4 event 101: Timer 5 TRGO event 110: Timer 5 CC4 event 111: JSWSTART Bit 11 ALIGN: Data alignment This bit is set and cleared by software. Refer to Figure 27.and Figure 28. 0: Right Alignment 1: Left Alignment Bits 10:9 Reserved, must be kept at reset value. Bit 8 DMA: Direct memory access mode This bit is set and cleared by software. Refer to the DMA controller chapter for more details. 0: DMA mode disabled 1: DMA mode enabled Only ADC1 and ADC3 can generate a DMA request. Bits 7:4 Reserved, must be kept at reset value. Bit 3 RSTCAL: Reset calibration This bit is set by software and cleared by hardware. It is cleared after the calibration registers are initialized. 0: Calibration register initialized. 1: Initialize calibration register. Note: If RSTCAL is set when conversion is ongoing, additional cycles are required to clear the calibration registers. 241/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) Bit 2 CAL: A/D Calibration This bit is set by software to start the calibration. It is reset by hardware after calibration is complete. 0: Calibration completed 1: Enable calibration Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If set conversion takes place continuously till this bit is reset. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D converter ON / OFF This bit is set and cleared by software. If this bit holds a value of zero and a 1 is written to it then it wakes up the ADC from Power Down state. Conversion starts when this bit holds a value of 1 and a 1 is written to it. The application should allow a delay of tSTAB between power up and start of conversion. Refer to Figure 23. 0: Disable ADC conversion/calibration and go to power down mode. 1: Enable ADC and to start conversion Note: If any other bit in this register apart from ADON is changed at the same time, then conversion is not triggered. This is to prevent triggering an erroneous conversion. DocID13902 Rev 15 242/1128 252 Analog-to-digital converter (ADC) RM0008 11.12.4 ADC sample time register 1 (ADC_SMPR1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 Reserved 15 SMP 15_0 rw 14 13 12 SMP14[2:0] rw rw rw 11 10 9 SMP13[2:0] rw rw rw 24 23 22 21 20 19 18 17 16 SMP17[2:0] SMP16[2:0] SMP15[2:1] rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 SMP12[2:0] SMP11[2:0] SMP10[2:0] rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Note: ADC1 analog Channel16 and Channel 17 are internally connected to the temperature sensor and to VREFINT, respectively. ADC2 analog input Channel16 and Channel17 are internally connected to VSS. ADC3 analog inputs Channel14, Channel15, Channel16 and Channel17 are connected to VSS. 243/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.12.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 31 30 Reserved 29 28 27 SMP9[2:0] 26 25 24 SMP8[2:0] 23 22 21 SMP7[2:0] 20 19 18 SMP6[2:0] 17 16 SMP5[2:1] Res. rw rw 15 14 13 12 SMP 5_0 SMP4[2:0] rw rw rw 11 10 9 SMP3[2:0] rw rw rw 8 7 6 SMP2[2:0] rw rw rw 5 4 3 SMP1[2:0] rw rw rw 2 1 0 SMP0[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel. During sample cycles channel selection bits must remain unchanged. 000: 1.5 cycles 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles Note: ADC3 analog input Channel9 is connected to VSS. 11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) Address offset: 0x14-0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved JOFFSETx[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x These bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. The conversion result can be read from in the ADC_JDRx registers. DocID13902 Rev 15 244/1128 252 Analog-to-digital converter (ADC) RM0008 11.12.7 ADC watchdog high threshold register (ADC_HTR) Address offset: 0x24 Reset value: 0x0000 0FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HT[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 HT[11:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. 11.12.8 ADC watchdog low threshold register (ADC_LTR) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LT[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 LT[11:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. 245/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.12.9 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved L[3:0] SQ16[4:1] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQ16_0 SQ15[4:0] SQ14[4:0] SQ13[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions ..... 1111: 16 conversions Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 16th in the conversion sequence. Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence DocID13902 Rev 15 246/1128 252 Analog-to-digital converter (ADC) RM0008 11.12.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SQ12[4:0] SQ11[4:0] SQ10[4:1] Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQ10_ 0 SQ9[4:0] SQ8[4:0] SQ7[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 12th in the sequence to be converted. Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence 247/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SQ6[4:0] SQ5[4:0] SQ4[4:1] Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted. Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence DocID13902 Rev 15 248/1128 252 Analog-to-digital converter (ADC) RM0008 11.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved JL[1:0] JSQ4[4:1] rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JSQ4_0 JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. 00: 1 conversion 01: 2 conversions 10: 3 conversions 11: 4 conversions Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0] = 3)(1) These bits are written by software with the channel number (0..17) assigned as the 4th in the sequence to be converted. Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels are converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10 00011 00011 00111 00010 means that a scan conversion will convert the following channel sequence: 7, 3, 3. (not 2, 7, 3) Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0] = 3) Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0] = 3) Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0] = 3) 1. When JL=3 ( 4 injected conversions in the sequencer), the ADC converts the channels in this order: JSQ1[4:0] >> JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0] When JL=2 ( 3 injected conversions in the sequencer), the ADC converts the channels in this order: JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0] When JL=1 ( 2 injected conversions in the sequencer), the ADC converts the channels in this order: JSQ3[4:0] >> JSQ4[4:0] When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] channel 249/1128 DocID13902 Rev 15 RM0008 Analog-to-digital converter (ADC) 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JDATA[15:0] r r r r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 27 and Figure 28. 11.12.14 ADC regular data register (ADC_DR) Address offset: 0x4C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADC2DATA[15:0] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA[15:0] r r r r r r r r r r r r r r r r Bits 31:16 ADC2DATA[15:0]: ADC2 data In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to Section 11.9: Dual ADC mode. In ADC2 and ADC3: these bits are not used. Bits 15:0 DATA[15:0]: Regular data These bits are read only. They contain the conversion result from the regular channels. The data is left or right-aligned as shown in Figure 27 and Figure 28. DocID13902 Rev 15 250/1128 252 0 Analog-to-digital converter (ADC) 11.12.15 ADC register map The following table summarizes the ADC registers. Table 72. ADC register map and reset values Offset Register RM0008 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 AWD EOC JEOC JSTRT STRT 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 ADC_SR Reset value ADC_CR1 Reset value ADC_CR2 Reset value Reserved Reserved TSVREFE AWDEN JSWSTART Reserved 00 JAWDEN Reserved 00000 JEOC IE AWD SGL DISCEN JDISCEN DUALMOD [3:0] DISC NUM [2:0] JAUTO SCAN AWDIE EOCIE AWDCH[4:0] 00000000000000000000 ADON CONT CAL RSTCAL Reserved JEXTTRIG Reserved EXTTRIG SWSTART EXTSEL [2:0] JEXTSE L [2:0] ALIGN DMA Reserved 0000000 00000 0 0000 ADC_SMPR1 Sample time bits SMPx_x Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SMPR2 Sample time bits SMPx_x Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JOFR1 Reset value Reserved JOFFSET1[11:0] 000000000000 ADC_JOFR2 Reset value Reserved JOFFSET2[11:0] 000000000000 ADC_JOFR3 Reset value Reserved JOFFSET3[11:0] 000000000000 ADC_JOFR4 Reset value Reserved JOFFSET4[11:0] 000000000000 ADC_HTR Reset value Reserved HT[11:0] 000000000000 ADC_LTR Reset value Reserved LT[11:0] 000000000000 251/1128 DocID13902 Rev 15 0 RM0008 Analog-to-digital converter (ADC) Table 72. ADC register map and reset values (continued) Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C ADC_SQR1 Reset value ADC_SQR2 Reset value ADC_SQR3 Reset value ADC_JSQR Reset value ADC_JDR1 Reset value ADC_JDR2 Reset value ADC_JDR3 Reset value ADC_JDR4 Reset value ADC_DR Reset value Reserved SQ16[4:0] 16th SQ15[4:0] 15th SQ14[4:0] 14th SQ13[4:0] 13th Reserved L[3:0] conversion in regular sequence bits conversion in regular sequence bits conversion in regular sequence bits conversion in regular sequence bits 000000000000000000000000 SQ12[4:0] 12th SQ11[4:0] 11th SQ10[4:0] 10th SQ9[4:0] 9th SQ8[4:0] 8th SQ7[4:0] 7th conversion in conversion in conversion in conversion in conversion in conversion in regular regular regular regular regular regular sequence bits sequence bits sequence bits sequence bits sequence bits sequence bits 000000000000000000000000000000 SQ6[4:0] 6th SQ5[4:0] 5th SQ4[4:0] 4th SQ3[4:0] 3rd SQ2[4:0] 2nd SQ1[4:0] 1st conversion in conversion in conversion in conversion in conversion in conversion in regular regular regular regular regular regular sequence bits sequence bits sequence bits sequence bits sequence bits sequence bits 000000000000000000000000000000 JSQ4[4:0] 4th JSQ3[4:0] 3rd JSQ2[4:0] 2nd JSQ1[4:0] 1st JL[1: conversion in conversion in conversion in conversion in Reserved 0] injected injected injected injected sequence bits sequence bits sequence bits sequence bits 0000000000000000000000 Reserved Reserved JDATA[15:0] 0000000000000000 Reserved JDATA[15:0] 0000000000000000 Reserved JDATA[15:0] 0000000000000000 Reserved JDATA[15:0] 0000000000000000 ADC2DATA[15:0] Regular DATA[15:0] 00000000000000000000000000000000 Refer to Table 1 on page 24 for the register boundary addresses. DocID13902 Rev 15 252/1128 252 Digital-to-analog converter (DAC) 12 Digital-to-analog converter (DAC) RM0008 12.1 12.2 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to connectivity line, high-density and XL-density STM32F101xx and STM32F103xx devices only. DAC introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operation. An input reference pin VREF+ (shared with ADC) is available for better resolution. DAC main features • Two DAC converters: one output channel each • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Input voltage reference VREF+ The block diagram of a DAC channel is shown in Figure 40 and the pin description is given in Table 73. 253/1128 DocID13902 Rev 15 RM0008 Digital-to-analog converter (DAC) Figure 40. DAC channel block diagram Note: EXTI_9 Trigger selectorx SWTR IGx TIM2_T RGO TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO(1) TSELx[2:0] bits DAC control register DMAENx DHRx 12- bit Control logicx DM A req ue stx TENx LFSRx trianglex MAMPx[3:0] bits WAVENx[1:0] bits 12-bit VDDA VSSA VR EF+ DO Rx 12-bit Digital-to-analog converterx DAC_ OU Tx ai14708c 1. In connectivity line devices, the TIM8_TRGO trigger is replaced by TIM3_TRGO . Name VREF+ VDDA VSSA DAC_OUTx Table 73. DAC pins Signal type Remarks Input, analog reference The higher/positive reference voltage for the DAC, positive 2.4 V ≤ VREF+ ≤ VDDA (3.3 V) Input, analog supply Analog power supply Input, analog supply ground Ground for analog power supply Analog output signal DAC channelx analog output Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is automatically connected to the analog converter output (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN). DocID13902 Rev 15 254/1128 272 Digital-to-analog converter (DAC) RM0008 12.3 12.3.1 Note: 12.3.2 12.3.3 DAC functional description DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time tWAKEUP. The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset. DAC output buffer enable The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. Each DAC channel output buffer can be enabled and disabled using the corresponding BOFFx bit in the DAC_CR register. DAC data format Depending on the selected configuration mode, the data has to be written in the specified register as described below: • Single DAC channelx, there are three possibilities: – 8-bit right alignment: user has to load data into DAC_DHR8Rx [7:0] bits (stored into DHRx[11:4] bits) – 12-bit left alignment: user has to load data into DAC_DHR12Lx [15:4] bits (stored into DHRx[11:0] bits) – 12-bit right alignment: user has to load data into DAC_DHR12Rx [11:0] bits (stored into DHRx[11:0] bits) Depending on the loaded DAC_DHRyyyx register, the data written by the user will be shifted and stored into the DHRx (Data Holding Registerx, that are internal non-memory-mapped registers). The DHRx register will then be loaded into the DORx register either automatically, by software trigger or by an external event trigger. 255/1128 DocID13902 Rev 15 RM0008 Digital-to-analog converter (DAC) 12.3.4 Figure 41. Data registers in single DAC channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0] bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits) – 12-bit left alignment: data for DAC channel1 to be loaded into DAC_DHR12LD [15:4] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12LD [31:20] bits (stored into DHR2[11:0] bits) – 12-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR12RD [11:0] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12LD [27:16] bits (stored into DHR2[11:0] bits) Depending on the loaded DAC_DHRyyyD register, the data written by the user will be shifted and stored into the DHR1 and DHR2 (Data Holding Registers, that are internal nonmemory-mapped registers). The DHR1 and DHR2 registers will then be loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger. Figure 42. Data registers in dual DAC channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14709 DAC conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write on DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD). Data stored into the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later. When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time of tSETTLING that depends on the power supply voltage and the analog output load. DocID13902 Rev 15 256/1128 272 Digital-to-analog converter (DAC) RM0008 Figure 43. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK DHR 0x1AC DOR 0x1AC tSETTLING Output voltage available on DAC_OUT pin ai14711b 12.3.5 12.3.6 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+. The analog output voltages on each DAC channel pin are determined by the following equation: DACoutput = VREF × D-4---0-O---9--R-5-- DAC trigger selection If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possible events will trigger conversion as shown in Table 74. Source Timer 6 TRGO event Timer 3 TRGO event in connectivity line devices or Timer 8 TRGO in high-density and XL-density devices Timer 7 TRGO event Timer 5 TRGO event Timer 2 TRGO event Timer 4 TRGO event EXTI line9 SWTRIG Table 74. External triggers Type Internal signal from on-chip timers External pin Software control bit TSEL[2:0] 000 001 010 011 100 101 110 111 Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register is transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs. If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents. 257/1128 DocID13902 Rev 15 RM0008 Digital-to-analog converter (DAC) Note: 12.3.7 12.3.8 TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-toDAC_DORx register transfer. DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests. A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred to the DAC_DORx register. In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel. The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement of the last request, then the new request will not be serviced and no error is reported Noise generation In order to generate a variable-amplitude pseudonoise, a Linear Feedback Shift Register is available. The DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in the LFSR is 0xAAA. This register is updated, three APB1 clock cycles after each trigger event, following a specific calculation algorithm. Figure 44. DAC LFSR register calculation algorithm XOR X6 X4 X X0 X 12 11 10 9 8 7 6 5 4 3 2 1 0 12 NOR ai14713b The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register. If LFSR is 0x0000, a ‘1’ is injected into it (antilock-up mechanism). It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits. DocID13902 Rev 15 258/1128 272 Digital-to-analog converter (DAC) RM0008 Figure 45. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK DHR 0x00 DOR 0xAAA 0xD55 SWTRIG ai14714 Note: 12.3.9 DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register. The triangle counter is incremented while it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on. It is possible to reset triangle wave generation by resetting WAVEx[1:0] bits. Figure 46. DAC triangle wave generation -!-0X;=MAXAMPLITUDE $!#?$(2XBASEVALUE )NCREMENTATION $ECREMENTATION $!#?$(2XBASEVALUE  AIC 259/1128 DocID13902 Rev 15 RM0008 Digital-to-analog converter (DAC) Figure 47. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK DHR 0xABE DOR 0xABE 0xABF 0xAC0 Note: SWTRIG ai14714 DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed. 12.4 12.4.1 Dual DAC channel conversion To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time. Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed. All modes are described in the paragraphs below. Independent trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three APB1 clock cycles later). When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB1 clock cycles later). DocID13902 Rev 15 260/1128 272 Digital-to-analog converter (DAC) RM0008 12.4.2 12.4.3 12.4.4 Independent trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits • Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD or DHR8RD) When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated. Independent trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values in the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the LFSR1 counter is updated. When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the LFSR2 counter is updated. Independent trigger with same triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value in the MAMPx[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into 261/1128 DocID13902 Rev 15 RM0008 Digital-to-analog converter (DAC) 12.4.5 12.4.6 12.4.7 DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. Independent trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register part and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. Simultaneous software start To configure the DAC in this conversion mode, the following sequence is required: • Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively. Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively (after three APB1 clock cycles). DocID13902 Rev 15 262/1128 272 Digital-to-analog converter (DAC) RM0008 12.4.8 Simultaneous trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits • Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or DHR8RD) When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated. 12.4.9 Simultaneous trigger with different LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values using the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The LFSR2 counter is then updated. 12.4.10 Simultaneous trigger with same triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum amplitude value using the MAMPx[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is 263/1128 DocID13902 Rev 15 RM0008 Digital-to-analog converter (DAC) added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. 12.4.11 Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits • Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits • Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD) When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is updated. At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated. 12.5 DAC registers The peripheral registers have to be accessed by words (32-bit). 12.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Reserved DMA EN2 MAMP2[3:0] rw rw rw rw rw 15 14 13 12 11 10 9 8 Reserved DMA EN1 MAMP1[3:0] rw rw rw rw rw 23 22 WAVE2[1:0] rw rw 7 6 WAVE1[1:0] rw rw 21 20 19 TSEL2[2:0] rw rw rw 5 4 3 TSEL1[2:0] rw rw rw 18 17 16 TEN2 BOFF2 EN2 rw rw rw 2 1 0 TEN1 BOFF1 EN1 rw rw rw DocID13902 Rev 15 264/1128 272 Digital-to-analog converter (DAC) RM0008 Bits 31:29 Reserved. Bit 28 DMAEN2: DAC channel2 DMA enable This bit is set and cleared by software. 0: DAC channel2 DMA mode disabled 1: DAC channel2 DMA mode enabled Bit 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ Triangle Amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ Triangle Amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ Triangle Amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ Triangle Amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ Triangle Amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ Triangle Amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ Triangle Amplitude equal to 2047 ≥ 1011: Unmask bits[11:0] of LFSR/ Triangle Amplitude equal to 4095 Bit 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event 001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density and XL-density devices 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9 111: Software trigger Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) Bit 18 TEN2: DAC channel2 trigger enable This bit set and cleared by software to enable/disable DAC channel2 trigger 0: DAC channel2 trigger disabled and data written into DAC_DHRx register is transferred one APB1 clock cycle later to the DAC_DOR2 register. 1: DAC channel2 trigger enabled and data transfer from DAC_DHRx register is transferred three APB1 clock cycles later to the DAC_DOR2 register. Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to DAC_DOR2 register transfer. 265/1128 DocID13902 Rev 15 RM0008 Digital-to-analog converter (DAC) Bit 17 BOFF2: DAC channel2 output buffer disable This bit set and cleared by software to enable/disable DAC channel2 output buffer. 0: DAC channel2 output buffer enabled 1: DAC channel2 output buffer disabled Bit 16 EN2: DAC channel2 enable This bit set and cleared by software to enable/disable DAC channel2. 0: DAC channel2 disabled 1: DAC channel2 enabled Bits 15:13 Reserved. Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software. 0: DAC channel1 DMA mode disabled 1: DAC channel1 DMA mode enabled Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15 0100: Unmask bits[4:0] of LFSR/ Triangle Amplitude equal to 31 0101: Unmask bits[5:0] of LFSR/ Triangle Amplitude equal to 63 0110: Unmask bits[6:0] of LFSR/ Triangle Amplitude equal to 127 0111: Unmask bits[7:0] of LFSR/ Triangle Amplitude equal to 255 1000: Unmask bits[8:0] of LFSR/ Triangle Amplitude equal to 511 1001: Unmask bits[9:0] of LFSR/ Triangle Amplitude equal to 1023 1010: Unmask bits[10:0] of LFSR/ Triangle Amplitude equal to 2047 ≥ 1011: Unmask bits[11:0] of LFSR/ Triangle Amplitude equal to 4095 Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1 000: Timer 6 TRGO event 001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density and XL-density devices 010: Timer 7 TRGO event 011: Timer 5 TRGO event 100: Timer 2 TRGO event 101: Timer 4 TRGO event 110: External line9 111: Software trigger Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) DocID13902 Rev 15 266/1128 272 Digital-to-analog converter (DAC) RM0008 Bit 2 TEN1: DAC channel1 trigger enable This bit set and cleared by software to enable/disable DAC channel1 trigger 0: DAC channel1 trigger disabled and data written into DAC_DHRx register is transferred one APB1 clock cycle later to the DAC_DOR1 register. 1: DAC channel1 trigger enabled and data transfer from DAC_DHRx register is transferred three APB1 clock cycles later to the DAC_DOR1 register. Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to DAC_DOR1 register transfer. Bit 1 BOFF1: DAC channel1 output buffer disable This bit set and cleared by software to enable/disable DAC channel1 output buffer. 0: DAC channel1 output buffer enabled 1: DAC channel1 output buffer disabled Bit 0 EN1: DAC channel1 enable This bit set and cleared by software to enable/disable DAC channel1. 0: DAC channel1 disabled 1: DAC channel1 enabled 12.5.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SWTRI SWTRI G2 G1 w w Bits 31:2 Reserved. Bit 1 SWTRIG2: DAC channel2 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value is loaded to the DAC_DOR2 register. Bit 0 SWTRIG1: DAC channel1 software trigger This bit is set and cleared by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value is loaded to the DAC_DOR1 register. 267/1128 DocID13902 Rev 15 RM0008 Digital-to-analog converter (DAC) 12.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved. Bit 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel1. 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Reserved Bits 31:16 Reserved. Bit 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel1. Bits 3:0 Reserved. 12.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC1DHR[7:0] rw rw rw rw rw rw rw rw Bits 31:8 Reserved. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel1. DocID13902 Rev 15 268/1128 272 Digital-to-analog converter (DAC) RM0008 12.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 12.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Reserved Bits 31:16 Reserved. Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 3:0 Reserved. 12.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC2DHR[7:0] rw rw rw rw rw rw rw rw Bits 31:8 Reserved. Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel2. 269/1128 DocID13902 Rev 15 RM0008 Digital-to-analog converter (DAC) 12.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:28 Reserved. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 15:12 Reserved. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel1. 12.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DACC2DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC1DHR[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Reserved Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 19:16 Reserved. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel1. Bits 3:0 Reserved. DocID13902 Rev 15 270/1128 272 Digital-to-analog converter (DAC) RM0008 12.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC2DHR[7:0] DACC1DHR[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel2. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel1. 12.5.12 DAC channel1 data output register (DAC_DOR1) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC1DOR[11:0] r r r r r r r r r r r r Bits 31:12 Reserved. Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read only, they contain data output for DAC channel1. 12.5.13 DAC channel2 data output register (DAC_DOR2) Address offset: 0x30 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC2DOR[11:0] r r r r r r r r r r r r Bits 31:12 Reserved. Bit 11:0 DACC2DOR[11:0]: DAC channel2 data output These bits are read only, they contain data output for DAC channel2. 271/1128 DocID13902 Rev 15 0 RM0008 Digital-to-analog converter (DAC) 12.5.14 DAC register map The following table summarizes the DAC registers. Table 75. DAC register map Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DMAEN1 DMAEN2 0x00 DAC_CR Reset value Res. EN2 BOFF2 TEN2 MAMP2[3:0] WAV E2[2: 0] TSEL2[2: 0] 00000000 00000 Res. EN1 BOFF1 TEN1 WAV MAMP1[3:0] E1[2: 0] TSEL1 [2:0] 0000000000000 SWTRIG1 SWTRIG2 0x04 DAC_SWTRIGR Reserved 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 Reset value DAC_DHR12R1 Reset value DAC_DHR12L1 Reset value DAC_DHR8R1 Reset value DAC_DHR12R2 Reset value DAC_DHR12L2 Reset value DAC_DHR8R2 DAC_DHR12RD Reset value DAC_DHR12LD Reset value DAC_DHR8RD Reset value DAC_DOR1 Reset value DAC_DOR2 Reset value Reserved Reserved Reserved Reserved Reserved Reserved DACC2DHR[11:0] Reserved 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR[11:0] 00000000000 0 Reserved Reserved Reserved Reserved 00 DACC1DHR[11:0] 000000000000 DACC1DHR[11:0] 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DACC1DHR[7:0] 00000000 DACC2DHR[11:0] 000000000000 DACC2DHR[11:0] 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DACC2DHR[7:0] 0 00 0 00 0 0 DACC1DHR[11:0] Reserved 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR[11:0] 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DACC2DHR[7:0] DACC1DHR[7:0] 0000000000000000 DACC1DOR[11:0] 000000000000 DACC2DOR[11:0] 000000000000 Note: Refer to Table 3 on page 51 for the register boundary addresses. DocID13902 Rev 15 272/1128 272 Direct memory access controller (DMA) 13 Direct memory access controller (DMA) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 13.1 DMA introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests. 13.2 DMA main features • 12 independently configurable channels (requests): 7 for DMA1 and 5 for DMA2 • Each of the 12 channels is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. • Support for circular buffer management • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel • Memory-to-memory transfer • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers • Access to Flash, SRAM, APB1, APB2 and AHB peripherals as source and destination • Programmable number of data to be transferred: up to 65536 The block diagram is shown in Figure 48. 273/1128 DocID13902 Rev 15 RM0008 Direct memory access controller (DMA) Figure 48. DMA block diagram in connectivity line devices #O R T EX - $-! #H #H )#ODE $#ODE 3YS TEM &,)4& $-! 2ESETCLOCK CONTROL2## &LASH 32!- $-! "USMATRIX #H !RBITER !("3LAVE $-! #H #H $-!REQUEST $-!REQUEST "RIDGE  "RIDGE  !0" !0" !$# 53!24 30) 4)- $!#30))3 )# )# 30 )4))-3 5!24 4)- 53!24 4)- 53!24  4)- 4)- 4)- #H $-! !RBITER !("3LAVE %THERNET-!# 53"/4'&3 AIB DocID13902 Rev 15 274/1128 291 Direct memory access controller (DMA) RM0008 Figure 49. DMA block diagram in low-, medium- high- and XL-density devices Co r t ex -M3 ICode DCode Sys tem FLITF Flash SRAM DMA1 Ch.1 Ch.2 DMA FSMC SDIO DMA Bus matrix Ch.7 Arbiter AHB Slave DMA2 Ch.1 Ch.2 AHB System Bridge 2 Bridge 1 APB1 APB2 DMA request DMA request USART2 USART3 UART4 SPI/I2S2 SPI/I2S3 I2C1 I2C2 TIM2 TIM3 TIM 4 TIM5 TIM6 TIM7 USA RT1 SPI1 ADC1 ADC3 TIM1 TIM8 Ch.5 Arbiter DMA request AHB Slave Reset & clock control (RCC) ai14801b 1. The DMA2 controller is available only in high-density and XL-density devices. 1. ADC3, SPI/I2S3, UART4, SDIO, TIM5, TIM6, DAC, TIM7, TIM8 DMA requests are available only in high- density devices 13.3 13.3.1 DMA functional description The DMA controller performs direct memory transfer by sharing the system bus with the Cortex®-M3 core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU. DMA transactions After an event, the peripheral sends a request signal to the DMA Controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA Controller. The peripheral releases its request as soon as it gets the Acknowledge from the DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. 275/1128 DocID13902 Rev 15 RM0008 Direct memory access controller (DMA) 13.3.2 Note: 13.3.3 In summary, each DMA transfer consists of three operations: • The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register • The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register • The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed. Arbiter The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences. The priorities are managed in two stages: • Software: each channel priority can be configured in the DMA_CCRx register. There are four levels: – Very high priority – High priority – Medium priority – Low priority • Hardware: if 2 requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4. In high-density, XL-density and connectivity line devices, the DMA1 controller has priority over the DMA2 controller. DMA channels Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register which contains the amount of data items to be transferred is decremented after each transaction. Programmable data sizes Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE and MSIZE bits in the DMA_CCRx register. Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current DocID13902 Rev 15 276/1128 291 Direct memory access controller (DMA) RM0008 Note: transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in noncircular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled. If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers (DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase. In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx/DMA_CMARx registers. Channel configuration procedure The following sequence should be followed to configure a DMA channelx (where x is the channel number). 1. Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event. 2. Set the memory address in the DMA_CMARx register. The data will be written to or read from this memory after the peripheral event. 3. Configure the total number of data to be transferred in the DMA_CNDTRx register. After each peripheral event, this value will be decremented. 4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register 5. Configure data transfer direction, circular mode, peripheral & memory incremented mode, peripheral & memory data size, and interrupt after half and/or full transfer in the DMA_CCRx register 6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register. As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel. Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer Complete Interrupt Enable bit (TCIE) is set. Circular mode Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register. When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral. This mode is called Memory to Memory mode. If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx 277/1128 DocID13902 Rev 15 RM0008 Direct memory access controller (DMA) register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. 13.3.4 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 76: Programmable data width & endian behavior (when bits PINC = MINC = 1). Table 76. Programmable data width & endian behavior (when bits PINC = MINC = 1) Source port width Destination port width Number of data items to transfer (NDT) Source content: address / data Transfer operations Destination content: address / data 8 8 8 16 8 32 16 8 16 16 16 32 32 8 @0x0 / B0 4 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1 3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2 4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3 @0x0 / B0 4 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2 3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4 4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6 @0x0 / B0 4 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4 3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8 4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC @0x0 / B1B0 4 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1 3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2 4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3 @0x0 / B1B0 4 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2 3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4 4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6 @0x0 / B1B0 4 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4 3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8 4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC @0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0 4 @0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1 @0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2 @0xC / BFBEBDBC 4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 @0x0 / 00B0 @0x2 / 00B1 @0x4 / 00B2 @0x6 / 00B3 @0x0 / 000000B0 @0x4 / 000000B1 @0x8 / 000000B2 @0xC / 000000B3 @0x0 / B0 @0x1 / B2 @0x2 / B4 @0x3 / B6 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 @0x0 / 0000B1B0 @0x4 / 0000B3B2 @0x8 / 0000B5B4 @0xC / 0000B7B6 @0x0 / B0 @0x1 / B4 @0x2 / B8 @0x3 / BC DocID13902 Rev 15 278/1128 291 Direct memory access controller (DMA) RM0008 Table 76. Programmable data width & endian behavior (when bits PINC = MINC = 1) (continued) Source port width Destination port width Number of data items to transfer (NDT) Source content: address / data Transfer operations Destination content: address / data 32 16 32 32 @0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[7:0] @0x0 4 @0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[7:0] @0x1 @0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[7:0] @0x2 @0xC / BFBEBDBC 4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[7:0] @0x3 @0x0 / B1B0 @0x2 / B5B4 @0x4 / B9B8 @0x6 / BDBC @0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0 @0x0 / B3B2B1B0 4 @0x4 / B7B6B5B4 2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC 13.3.5 Addressing an AHB peripheral that does not support byte or halfword write operations When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: • To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord • To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with HSIZE = Byte Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit APB operation in the following manner: • an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0 • an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0 For instance, if you want to write the APB backup registers (16-bit registers aligned to a 32bit address boundary), you must configure the memory source size (MSIZE) to “16-bit” and the peripheral destination size (PSIZE) to “32-bit”. Error management A DMA transfer error can be generated by reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag (TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error interrupt enable bit (TEIE) in the DMA_CCRx register is set. 279/1128 DocID13902 Rev 15 RM0008 Direct memory access controller (DMA) 13.3.6 Interrupts An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility. Table 77. DMA interrupt requests Interrupt event Event flag Half-transfer Transfer complete HTIF TCIF Transfer error TEIF Enable Control bit HTIE TCIE TEIE Note: 13.3.7 In high-density and XL-density devices, DMA2 Channel4 and DMA2 Channel5 interrupts are mapped onto the same interrupt vector. In connectivity line devices, DMA2 Channel4 and DMA2 Channel5 interrupts have separate interrupt vectors. All other DMA1 and DMA2 Channel interrupts have their own interrupt vector. DMA request mapping DMA1 controller The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and USARTx[1,2,3]) are simply logically ORed before entering the DMA1, this means that only one request must be enabled at a time. Refer to Figure 50: DMA1 request mapping. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. DocID13902 Rev 15 280/1128 291 Direct memory access controller (DMA) RM0008 Peripheral request signals ADC1 TIM2_CH3 TIM4_CH1 USART3_TX TIM1_CH1 TIM2_UP TIM3_CH3 SPI1_RX USART3_RX TIM1_CH2 TIM3_CH4 TIM3_UP SPI1_TX USART1_TX TIM1_CH4 TIM1_TRIG TIM1_COM TIM4_CH2 SPI/I2S2_RX I2C2_TX USART1_RX TIM1_UP SPI/I2S2_TX TIM2_CH1 TIM4_CH3 I2C2_RX USART2_RX TIM1_CH3 TIM3_CH1 TIM3_TRIG I2C1_TX USART2_TX TIM2_CH2 TIM2_CH4 TIM4_UP I2C1_RX Figure 50. DMA1 request mapping Fixed hardware priority HW request 1 SW trigger (MEM2MEM bit) Channel 1 High priority Channel 1 EN bit HW request 2 Channel 2 SW trigger (MEM2MEM bit) Channel 2 EN bit HW request 3 Channel 3 SW trigger (MEM2MEM bit) Channel 3 EN bit HW request 4 SW trigger (MEM2MEM bit) Channel 4 internal DMA1 request Channel 4 EN bit HW request 5 SW trigger (MEM2MEM bit) Channel 5 Channel 5 EN bit HW REQUEST 6 SW TRIGGER (MEM2MEM bit) Channel 6 Channel 6 EN bit HW request 7 SW trigger (MEM2MEM bit) Channel 7 Low priority Channel 7 EN bit 281/1128 DocID13902 Rev 15 RM0008 Direct memory access controller (DMA) Table 78 lists the DMA requests for each channel. Table 78. Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 SPI/I2S USART I2C ADC1 - - - - - - - SPI1_RX SPI1_TX SPI2/I2S2_RX SPI2/I2S2_TX - - USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX - - I2C2_TX I2C2_RX I2C1_TX I2C1_RX TIM1 TIM2 TIM3 TIM4 TIM1_CH1 TIM2_CH3 TIM2_UP - TIM3_CH3 TIM4_CH1 - - TIM3_CH4 TIM3_UP - TIM1_CH4 TIM1_TRIG TIM1_COM - TIM4_CH2 TIM1_UP TIM2_CH1 - TIM4_CH3 TIM1_CH3 - TIM3_CH1 TIM3_TRIG - TIM2_CH2 TIM2_CH4 - TIM4_UP Note: DMA2 controller The 5 requests from the peripherals (TIMx[5,6,7,8], ADC3, SPI/I2S3, UART4, DAC_Channel[1,2] and SDIO) are simply logically ORed before entering the DMA2, this means that only one request must be enabled at a time. Refer to Figure 51: DMA2 request mapping. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. The DMA2 controller and its relative requests are available only in high-density, XL-density and connectivity line devices. DocID13902 Rev 15 282/1128 291 Direct memory access controller (DMA) RM0008 Figure 51. DMA2 request mapping Peripheral request signals Fixed hardware priority TIM5_CH4 TIM5_TRIG TIM8_CH3 TIM8_UP SPI/I2S3_RX TIM8_CH4 TIM8_TRIG TIM8_COM TIM5_CH3 TIM5_UP SPI/I2S3_TX TIM8_CH1 UART4_RX TIM6_UP/DAC_Channel1 TIM5_CH2 SDIO TIM7_UP/DAC_Channel2 HW request 1 SW trigger (MEM2MEM bit) HIGH PRIORITY Channel 1 Channel 1 EN bit HW request 2 Channel 2 SW trigger (MEM2MEM bit) Channel 2 EN bit HW request 3 Channel 3 SW trigger (MEM2MEM bit) Channel 3 EN bit HW request 4 Channel 4 SW trigger (MEM2MEM bit) internal DMA2 request ADC3 TIM8_CH2 TIM5_CH1 UART4_TX Channel 4 EN bit HW request 5 SW trigger (MEM2MEM bit) Channel 5 LOW PRIORITY Channel 5 EN bit Table 79 lists the DMA2 requests for each channel. Table 79. Summary of DMA2 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 ADC3(1) SPI/I2S3 SPI/I2S3_RX SPI/I2S3_TX UART4 SDIO(1) UART4_RX SDIO TIM5 TIM5_CH4 TIM5_TRIG TIM5_CH3 TIM5_UP TIM5_CH2 TIM6/ DAC_Channel1 TIM6_UP/ DAC_Channel 1 TIM7 TIM7_UP/ DAC_Channel 2 TIM8 TIM8_CH3 TIM8_UP TIM8_CH4 TIM8_TRIG TIM8_COM TIM8_CH1 Channel 5 ADC3 UART4_TX TIM5_CH1 TIM8_CH2 283/1128 DocID13902 Rev 15 RM0008 Direct memory access controller (DMA) 1. ADC3, SDIO and TIM8 DMA requests are available only in high-density and XL-density devices. 13.4 Note: 13.4.1 DMA registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. In the following registers, all bits related to channel6 and channel7 are not relevant for DMA2 since it has only 5 channels. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32bit). DMA interrupt status register (DMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 Reserved 15 TEIF4 r 14 HTIF4 r 13 TCIF4 r 12 GIF4 r 27 TEIF7 r 11 TEIF3 r 26 HTIF7 r 10 HTIF3 r 25 TCIF7 r 9 TCIF3 r 24 GIF7 r 8 GIF3 r 23 TEIF6 r 7 TEIF2 r 22 HTIF6 r 6 HTIF2 r 21 TCIF6 r 5 TCIF2 r 20 GIF6 r 4 GIF2 r 19 TEIF5 r 3 TEIF1 r 18 HTIF5 r 2 HTIF1 r 17 TCIF5 r 1 TCIF1 r 16 GIF5 r 0 GIF1 r Bits 31:28 Reserved, must be kept at reset value. Bits 27, 23, 19, 15, TEIFx: Channel x transfer error flag (x = 1 ..7) 11, 7, 3 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel x 1: A transfer error (TE) occurred on channel x Bits 26, 22, 18, 14, HTIFx: Channel x half transfer flag (x = 1 ..7) 10, 6, 2 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel x 1: A half transfer (HT) event occurred on channel x Bits 25, 21, 17, 13, TCIFx: Channel x transfer complete flag (x = 1 ..7) 9, 5, 1 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel x 1: A transfer complete (TC) event occurred on channel x Bits 24, 20, 16, 12, GIFx: Channel x global interrupt flag (x = 1 ..7) 8, 4, 0 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel x 1: A TE, HT or TC event occurred on channel x DocID13902 Rev 15 284/1128 291 Direct memory access controller (DMA) RM0008 13.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CTEIF 7 CHTIF 7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTEIF 4 CHTIF 4 CTCIF 4 CGIF4 CTEIF 3 CHTIF 3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 w w w w w w w w w w w w w w w w Bits 31:28 Reserved, must be kept at reset value. Bits 27, 23, 19, 15, CTEIFx: Channel x transfer error clear (x = 1 ..7) 11, 7, 3 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register Bits 26, 22, 18, 14, CHTIFx: Channel x half transfer clear (x = 1 ..7) 10, 6, 2 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register Bits 25, 21, 17, 13, CTCIFx: Channel x transfer complete clear (x = 1 ..7) 9, 5, 1 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register Bits 24, 20, 16, 12, CGIFx: Channel x global interrupt clear (x = 1 ..7) 8, 4, 0 This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register 285/1128 DocID13902 Rev 15 RM0008 Direct memory access controller (DMA) 13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 15 Res. 14 MEM2 MEM rw 13 12 PL[1:0] rw rw 27 26 11 10 MSIZE[1:0] rw rw 25 24 23 22 21 20 19 18 17 16 Reserved 9 8 7 6 5 4 3 2 1 0 PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN rw rw rw rw rw rw rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled Bits 13:12 PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high Bits 11:10 MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bits 9:8 PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bit 7 MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled Bit 6 PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled DocID13902 Rev 15 286/1128 291 Direct memory access controller (DMA) Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled Bit 1 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled Bit 0 EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled RM0008 13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7), where x = channel number) Address offset: 0x0C + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NDT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in autoreload mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 287/1128 DocID13902 Rev 15 RM0008 Direct memory access controller (DMA) 13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7), where x = channel number) Address offset: 0x10 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address. 13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7), where x = channel number) Address offset: 0x14 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MA rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address. DocID13902 Rev 15 288/1128 291 Direct memory access controller (DMA) 13.4.7 DMA register map The following table gives the DMA register map and the reset values. Table 80. DMA register map and reset values 9 Offset Register 8 7 6 5 4 3 2 1 RM0008 0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GIF1 TCIF1 HTIF1 TEIF1 GIF2 TCIF2 HTIF2 TEIF2 GIF3 TCIF3 HTIF3 TEIF3 GIF4 TCIF4 HTIF4 TEIF4 GIF5 TCIF5 HTIF5 TEIF5 GIF6 TCIF6 HTIF6 TEIF6 GIF7 TCIF7 HTIF7 TEIF7 CGIF1 EN MEM2MEM M SIZE [1:0] PSIZE [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN 0x000 DMA_ISR Reset value Reserved 0000000000000000000000000000 CTCIF1 CHTIF1 CTEIF1 CGIF2 CTCIF2 CHTIF2 CTEIF2 CGIF3 CTCIF3 CHTIF3 CTEIF3 CGIF4 CTCIF4 CHTIF4 CTEIF4 CGIF5 CTCIF5 CHTIF5 CTEIF5 CGIF6 CTCIF6 CHTIF6 CTEIF6 CGIF7 CTCIF7 CHTIF7 CTEIF7 0x004 DMA_IFCR Reset value Reserved 0000000000000000000000000000 PSIZE [1:0] M SIZE [1:0] MEM2MEM TCIE HTIE TEIE DIR CIRC PINC MINC 0x008 DMA_CCR1 Reserved PL [1:0] 0x00C 0x010 0x014 0x018 Reset value 000000000000000 DMA_CNDTR1 Reset value Reserved NDT[15:0] 0000000000000000 DMA_CPAR1 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR1 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0x01C DMA_CCR2 Reserved PL [1:0] 0x020 0x024 0x028 0x02C Reset value 000000000000000 DMA_CNDTR2 Reset value Reserved NDT[15:0] 0000000000000000 DMA_CPAR2 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR2 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0x030 DMA_CCR3 Reserved PL [1:0] 0x034 0x038 Reset value 000000000000000 DMA_CNDTR3 Reset value Reserved NDT[15:0] 0000000000000000 DMA_CPAR3 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 289/1128 DocID13902 Rev 15 MEM2MEM M SIZE [1:0] PSIZE [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN RM0008 Direct memory access controller (DMA) Table 80. DMA register map and reset values (continued) 1 2 3 4 5 6 7 8 9 Offset Register 0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EN MEM2MEM M SIZE [1:0] PSIZE [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN 0x03C 0x040 DMA_CMAR3 Reset value MA[31:0] 00000000000000000000000000000000 Reserved PSIZE [1:0] M SIZE [1:0] MEM2MEM TCIE HTIE TEIE DIR CIRC PINC MINC 0x044 DMA_CCR4 Reserved PL [1:0] 0x048 0x04C 0x050 0x054 Reset value 000000000000000 DMA_CNDTR4 Reset value Reserved NDT[15:0] 0000000000000000 DMA_CPAR4 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR4 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0x058 DMA_CCR5 Reserved PL [1:0] 0x05C 0x060 0x064 0x068 Reset value 000000000000000 DMA_CNDTR5 Reset value Reserved NDT[15:0] 0000000000000000 DMA_CPAR5 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR5 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0x06C DMA_CCR6 Reserved PL [1:0] 0x070 0x074 0x078 0x07C Reset value 000000000000000 DMA_CNDTR6 Reset value Reserved NDT[15:0] 0000000000000000 DMA_CPAR6 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR6 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved 0x080 DMA_CCR7 Reset value Reserved PL [1:0] 000000000000000 MEM2MEM M SIZE [1:0] PSIZE [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN MEM2MEM M SIZE [1:0] PSIZE [1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN DocID13902 Rev 15 290/1128 291 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direct memory access controller (DMA) Table 80. DMA register map and reset values (continued) Offset Register RM0008 0x084 0x088 0x08C 0x090 DMA_CNDTR7 Reset value Reserved NDT[15:0] 0000000000000000 DMA_CPAR7 PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR7 MA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Refer to Table 3 on page 51 for the register boundary addresses. 291/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) 14 Advanced-control timers (TIM1&TIM8) 14.1 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. Low- and medium-density STM32F103xx devices, and the STM32F105xx/STM32F107xx connectivity line devices, contain one advanced-control timer (TIM1) whereas high-density and XL-density STM32F103xx devices feature two advance-control timers (TIM1 and TIM8). TIM1&TIM8 introduction The advanced-control timers (TIM1&TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The advanced-control (TIM1&TIM8) and general-purpose (TIMx) timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 14.3.20. DocID13902 Rev 15 292/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.2 TIM1&TIM8 main features TIM1&TIM8 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. • Up to 4 independent channels for: – Input Capture – Output Compare – PWM generation (Edge and Center-aligned Mode) – One-pulse mode output • Complementary outputs with programmable dead-time • Synchronization circuit to control the timer with external signals and to interconnect several timers together. • Repetition counter to update the timer registers only after a given number of cycles of the counter. • Break input to put the timer’s output signals in reset state or in a known state. • Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare – Break input • Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes • Trigger input for external clock or cycle-by-cycle current management 293/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 52. Advanced-control timer block diagram TIMx_ETR Internal Clock (CK_INT) CK_TIM18 from RCC ETR ETRP Polarity Selection & Edge Detector & Prescaler Input Filter ITR0 ITR1 ITR2 ITR3 ITR TRC TI1F_ED ETRF Trigger Controller TGI TRGI Slave Mode Controller TRGO to other timers to DAC/ADC Reset, Enable, Up/Down, Count TIMx_CH1 TIMx_CH2 TIMx_CH3 TIMx_CH4 TIMx_BKIN XOR TI1 TI2 TI3 TI4 TI1FP1 TI2FP2 Encoder Interface U AutoReload Register Input Filter & Edge detector Input Filter & Edge detector Input Filter & Edge detector Input Filter & Edge detector Stop, Clear or Up/Down CK_PSC PSC Prescaler CK_CNT TI1FP1 TI1FP2 CC1I IC1 IC1PS U Prescaler +/- CNT COUNTER Capture/Compare 1 Register TRC CC2I TI2FP1 TI2FP2 TRC TI3FP3 TI3FP4 IC2 IC2PS U Prescaler CC3I IC3 IC3PS U Prescaler Capture/Compare 2 Register Capture/Compare 3 Register TRC CC4I TI4FP3 TI4FP4 TRC IC4 IC4PS U Prescaler Capture/Compare 4 Register REP Register UI Repetition counter U DTG[7:0] registers CC1I OC1REF DTG CC2I output OC1 control OC1N TIMx_CH1 TIMx_CH1N TIMx_CH2 OC2REF DTG CC3I output OC2 control TIMx_CH2N OC2N TIMx_CH3 OC3REF DTG CC4I OC4REF output OC3 control TIMx_CH3N OC3N output control OC4 TIMx_CH4 ETRF BRK Polarity Selection BI Clock failure event from clock controller CSS (Clock Security system Notes: Reg Preload registers transferred to active registers on U event according to control bit event interrupt & DMA output DocID13902 Rev 15 294/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.3 14.3.1 TIM1&TIM8 functional description Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter register (TIMx_CNT) • Prescaler register (TIMx_PSC) • Auto-reload register (TIMx_ARR) • Repetition counter register (TIMx_RCR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 53 and Figure 54 give some examples of the counter behavior when the prescaler ratio is changed on the fly: 295/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 53. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CEN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 02 03 Update event (UEV) Prescaler control register 0 1 Write a new value in TIMx_PSC Prescaler buffer 0 1 Prescaler counter 0 01 01 01 01 Figure 54. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CEN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 Update event (UEV) Prescaler control register 0 3 Write a new value in TIMx_PSC Prescaler buffer 0 3 Prescaler counter 0 01 23 01 23 14.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1). Else the update event is generated at each counter overflow. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the DocID13902 Rev 15 296/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register, • The auto-reload shadow register is updated with the preload value (TIMx_ARR), • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 55. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Figure 56. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0034 0035 0036 0000 0001 0002 0003 Update interrupt flag (UIF) 297/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 57. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0035 0036 0000 0001 Update interrupt flag (UIF) Figure 58. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register 1F 20 00 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 59. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC CEN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR DocID13902 Rev 15 298/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Figure 60. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CEN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Auto-reload preload register F5 36 Auto-reload shadow register F5 36 Write a new value in TIMx_ARR Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register plus one (TIMx_RCR+1). Else the update event is generated at each counter underflow. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one 299/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 61. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter underflow (cnt_udf) Update event (UEV) 05 04 03 02 01 00 36 35 34 33 32 31 30 2F Update interrupt flag (UIF) Figure 62. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0002 0001 0000 0036 0035 0034 0033 Update interrupt flag (UIF) Figure 63. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0001 0000 0036 0035 Update interrupt flag (UIF) DocID13902 Rev 15 300/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Figure 64. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register 20 1F 00 36 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 65. Counter timing diagram, update event when repetition counter is not used CK_PSC CEN Timer clock = CK_CNT Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11"). In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. 301/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The repetition counter is reloaded with the content of TIMx_RCR register • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. Figure 66. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03 Counter underflow Counter overflow Update event (UEV) Update interrupt flag (UIF) 1. Here, center-aligned mode 1 is used (for more details refer to Section 14.4: TIM1&TIM8 registers on page 333). DocID13902 Rev 15 302/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Figure 67. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0003 0002 0001 0000 0001 0002 0003 Update interrupt flag (UIF) Figure 68. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0034 0035 0036 0035 Update interrupt flag (UIF) 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 69. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register 20 1F 01 00 Counter underflow Update event (UEV) Update interrupt flag (UIF) 303/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 70. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC CEN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 06 05 04 03 02 01 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Auto-reload preload register FD 36 Write a new value in TIMx_ARR Auto-reload active register FD 36 Figure 71. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC CEN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register FD 36 Write a new value in TIMx_ARR Auto-reload active register FD 36 14.3.3 Repetition counter Section 14.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N+1 counter overflows or underflows, where N is the value in the TIMx_RCR repetition counter register. DocID13902 Rev 15 304/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is 2xTck, due to the symmetry of the pattern. The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 72). When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register. In center-aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was started. If the RCR was written before starting the counter, the UEV occurs on the overflow. If the RCR was written after starting the counter, the UEV occurs on the underflow. For example for RCR = 3, the UEV is generated on each 4th overflow or underflow event depending on when RCR was written. Figure 72. Update rate examples depending on mode and TIMx_RCR register settings Counter TIMx_CNT TIMx_RCR = 0 UEV Center-aligned mode Edge-aligned mode Upcounting Downcounting TIMx_RCR = 1 UEV TIMx_RCR = 2 UEV TIMx_RCR = 3 UEV TIMx_RCR = 3 and re-synchronization UEV (by SW) (by SW) (by SW) UEV Update Event: Preload registers transferred to active registers and update interrupt generated 305/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) 14.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Using one timer as prescaler for another for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 73 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 73. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN UG CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 74. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2 Filter DeEtdegcetor TI2F_Rising TI2F_Falling 0 1 ITRx or TI2F TI1F or or 0xx TI1_ED 100 TI1FP1 101 TRGI TI2FP2 110 ETRF 111 ETRF emnocdoeder external clock mode 1 CK_PSC emxotedrena2l clock ICF[3:0] TIMx_CCMR1 CC2P TIMx_CCER CK_INT (internal clock) imntoedrneal clock ECE SMS[2:0] TIMx_SMCR DocID13902 Rev 15 306/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Note: For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). 3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 75. Control circuit in external clock mode 1 TI2 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 Write TIF=0 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 76 gives an overview of the external trigger input block. Figure 76. External trigger input block ETR pin ETR 0 1 ETP TIMx_SMCR divider /1, /2, /4, /8 ETRP fDTS filter downcounter ETPS[1:0] TIMx_SMCR ETF[3:0] TIMx_SMCR or TI2F TI1F or or emnocdoeder TRGI external clock mode 1 CK_PSC ETRF emxotedrena2l clock CK_INT (internal clock) imntoedrenal clock ECE SMS[2:0] TIMx_SMCR 307/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 77. Control circuit in external clock mode 2 fCK_INT CNT_EN ETR ETRP ETRF Counter clock = CK_CNT = CK_PSC Counter register 34 35 36 14.3.5 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 78 to Figure 81 give an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). DocID13902 Rev 15 308/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Figure 78. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1 filter TI1F Edge TI1F_Rising 0 TI1FP1 fDTS downcounter Detector TI1F_Falling 1 TI2FP1 01 10 IC1 divider IC1PS /1, /2, /4, /8 ICF[3:0] TIMx_CCMR1 CC1P/CC1NP TIMx_CCER TI2F_rising 0 (from channel 2) TI2F_falling (from channel 2) 1 TRC (from slave mode 11 controller) CC1S[1:0] ICPS[1:0] TIMx_CCMR1 CC1E TIMx_CCER The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 79. Capture/compare channel 1 main circuit APB Bus read CCR1H S read CCR1L R CC1S[1] CC1S[0] IC1PS CC1E CC1G TIM1_EGR MCU-peripheral interface high (if 16-bit) low read_in_progress 8 8 write_in_progress Capture/compare preload register S write CCR1H R write CCR1L input mode capture_transfer compare_transfer output mode Capture/compare shadow register capture comparator CC1S[1] CC1S[0] OC1PE OC1PE UEV (from time TIM1_CCMR1 base unit) CNT>CCR1 Counter CNT=CCR1 309/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 80. Output stage of capture/compare channel (channel 1 to 3) ETR CNT>CCR1 Output mode OC1REF CNT=CCR1 controller To the master mode controller ‘0’ x0 01 OC1_DT 11 Dead-time generator OC1N_DT 11 10 ‘0’ 0x 0 1 CC1P TIM1_CCER Output enable circuit OC1 0 Output OC1N enable 1 circuit OC1CE OC1M[2:0] TIM1_CCMR1 DTG[7:0] TIM1_BDTR CC1NE CC1E TIM1_CCER CC1NE CC1E TIM1_CCER CC1NP MOEOSSI OSSR TIM1_BDTR TIM1_CCER Figure 81. Output stage of capture/compare channel (channel 4) ETR To the master mode controller CNT > CCR4 Output mode OC4 REF CNT = CCR4 controller 0 1 CC4P TIM1_CCER Output enable circuit OC4 14.3.6 OC2M[2:0] TIM1_CCMR2 CC4E TIM1_CCER MOEOSSI TIM1_BDTR OIS4 TIM1_CR2 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. DocID13902 Rev 15 310/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Note: 14.3.7 The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: • Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. • Program the input filter duration you need with respect to the signal you connect to the timer (by programming ICxF bits in the TIMx_CCMRx register if the input is a TIx input). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in the TIMx_CCER register (rising edge in this case). • Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). • Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. • If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. 311/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): • Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). • Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P bit to ‘0’ (active on rising edge). • Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). • Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active on falling edge). • Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). • Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. • Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 82. PWM input mode timing TI1 TIMx_CNT 0004 0000 0001 0002 0003 0004 0000 TIMx_CCR1 0004 TIMx_CCR2 0002 14.3.8 IC1 capture IC2 capture reset counter IC2 capture pulse width measurement IC1 capture period measurement ai15413 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. DocID13902 Rev 15 312/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.3.9 Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). • Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). • Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One Pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. Select the output mode. For example: – Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx – Write OCxPE = 0 to disable preload register – Write CCxP = 0 to select active high polarity – Write CCxE = 1 to enable the output 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 83. 313/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 83. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 TIM1_CCR1 003A 003B 003A oc1ref=OC1 B200 B201 B201 Match detected on CCR1 Interrupt generated if enabled 14.3.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction of the counter). The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. DocID13902 Rev 15 314/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section : Upcounting mode on page 296. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 84 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. Figure 84. Edge-aligned PWM waveforms (ARR=8) Counter register 0 1 2 3 4 5 6 7 8 0 1 OCXREF CCRx=4 CCxIF OCXREF CCRx=8 CCxIF OCXREF ‘1’ CCRx>8 CCxIF OCXREF ‘0’ CCRx=0 CCxIF • Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section : Downcounting mode on page 299 In PWM mode 1, the reference signal OCxRef is low as long as TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Section : Center-aligned mode (up/down counting) on page 301. Figure 85 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. 315/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 85. Center-aligned PWM waveforms (ARR=8) #OUNTERREGISTER                   /#X2%& ##2X ##X)& /#X2%& ##2X #-3 #-3 #-3 ##X)& #-3OR /#X2%& gg ##2X ##X)& /#X2%& gg ##2X #-3 #-3 #-3 ##X)& /#X2%& gg ##2X #-3 #-3 #-3 ##X)& #-3 #-3 #-3 AIB Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. • The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. DocID13902 Rev 15 316/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.3.11 Complementary outputs and dead-time insertion The advanced-control timers (TIM1&TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of levelshifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register. The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 83: Output control bits for complementary OCx and OCxN channels with break feature on page 350 for more details. In particular, the dead-time is activated when switching to the IDLE state (MOE falling down to 0). Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. DTG[7:0] bits of the TIMx_BDTR register are used to control the dead-time generation for all channels. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: • The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. • The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge. If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated. The following figures show the relationships between the output signals of the dead-time generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples) Figure 86. Complementary output with dead-time insertion. OCxREF OCx OCxN delay delay Figure 87. Dead-time waveforms with delay greater than the negative pulse. OCxREF OCx OCxN delay 317/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 88. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCx OCxN delay Note: The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 14.4.18: TIM1&TIM8 break and deadtime register (TIMx_BDTR) on page 354 for delay calculation. Re-directing OCxREF to OCx or OCxN In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register. This allows you to send a specific waveform (such as PWM or static active level) on one output while the complementary remains at its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time. When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low. 14.3.12 Using the break function When using the break function, the output enable signals and inactive levels are modified according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs cannot be set both to active level at a given time. Refer to Table 83: Output control bits for complementary OCx and OCxN channels with break feature on page 350 for more details. The break source can be either the break input pin or a clock failure event, generated by the Clock Security System (CSS), from the Reset Clock Controller. For further information on the Clock Security System, refer to Section 7.2.7: Clock security system (CSS) on page 97. When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable the break function by setting the BKE bit in the TIMx_BDTR register. The break input polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1 APB clock period to correctly read back the bit after the write operation. Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you DocID13902 Rev 15 318/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Note: must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. When a break occurs (selected level on the break input): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit). This feature functions even if the MCU oscillator is off. • Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable output else the enable output remains high. • When complementary outputs are used: – The outputs are first put in reset state inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer. – If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high. • The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set. • If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance. Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components. The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared. The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR Register. There are two solutions to generate a break: • By using the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR register • By software through the BG bit of the TIMx_EGR register. In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows you to freeze the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). You can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to Section 14.4.18: TIM1&TIM8 break and dead-time register (TIMx_BDTR) on page 354. The LOCK bits can be written only once after an MCU reset. Figure 89 shows an example of behavior of the outputs in response to a break. 319/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 89. Output behavior in response to a break. BREAK (MOE ) OCxREF OCx (OCxN not implemented, CCxP=0, OISx=1) OCx (OCxN not implemented, CCxP=0, OISx=0) OCx (OCxN not implemented, CCxP=1, OISx=1) OCx (OCxN not implemented, CCxP=1, OISx=0) OCx OCxN delay delay delay (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) OCx OCxN delay delay delay (CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1) OCx OCxN delay (CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1) OCx OCxN delay (CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0) OCx OCxN (CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1) DocID13902 Rev 15 320/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs. This function can only be used in output compare and PWM modes, and does not work in forced mode. For example, the ETR signal can be connected to the output of a comparator to be used for current handling. In this case, the ETR must be configured as follow: 1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’. 2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to ‘0’. 3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to the user needs. Figure 90 shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in PWM mode. Figure 90. Clearing TIMx OCxREF counter (CNT) (CCRx) ETRF OCxREF (OCxCE=’0’) OCxREF (OCxCE=’1’) ETRF becomes high ETRF still high 321/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) 14.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on TRGI rising edge). A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request (if the COMDE bit is set in the TIMx_DIER register). Figure 91 describes the behavior of the OCx and OCxN outputs when a COM event occurs, in 3 different examples of programmed configurations. Figure 91. 6-step generation, COM example (OSSR=1) counter (CNT) (CCRx) OCxREF Write COM to 1 COM event OCx Example 1 OCxN OCx Example 2 OCxN OCx Example 3 OCxN CCxE=1 CCxNE=0 write OCxM to 100 OCxM=100 (forced inactive) Write CCxNE to 1 CCxE=1 and OCxM to 101 CCxNE=0 OCxM=100 (forced inactive) CCxE=1 CCxNE=0 write CCxNE to 0 and OCxM to 100 OCxM=100 (forced inactive) CCxE=1 CCxNE=0 OCxM=100 CCxE=0 CCxNE=1 OCxM=101 CCxE=1 CCxNE=0 OCxM=100 ai14910 DocID13902 Rev 15 322/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx) • In downcounting: CNT > CCRx Figure 92. Example of one pulse mode. TI2 OC1REF OC1 Counter TIM1_ARR TIM1_CCR1 0 tDELAY tPULSE t For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: • Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register. • TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). 323/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable: In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 14.3.16 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’ if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, you can program the input filter as well. The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 81. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. in the same way, the capture, compare, prescaler, DocID13902 Rev 15 324/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. Table 81. Counting direction versus encoder signals Active edge Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) TI1FP1 signal Rising Falling TI2FP2 signal Rising Falling Counting on TI1 only High Low Down Up Up Down No Count No Count No Count No Count Counting on TI2 only High Low No Count No Count No Count No Count Up Down Down Up Counting on TI1 and TI2 High Low Down Up Up Down Up Down Down Up An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. Figure 93 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: • CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1). • CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2). • CC1P=’0’, and IC1F = ‘0000’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1). • CC2P=’0’, and IC2F = ‘0000’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2). • SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges). • CEN=’1’ (TIMx_CR1 register, Counter enabled). 325/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Figure 93. Example of counter operation in encoder interface mode. forward jitter backward jitter forward TI1 TI2 Counter up down up Figure 94 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 94. Example of encoder interface mode with TI1FP1 polarity inverted. forward jitter backward jitter forward TI1 TI2 Counter down up down The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a real-time clock. DocID13902 Rev 15 326/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture. An example of this feature used to interface Hall sensors is given in Section 14.3.18 below. 14.3.18 Interfacing with Hall sensors This is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to drive the motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as “interfacing timer” in Figure 95. The “interfacing timer” captures the 3 timer input pins (TIMx_CH1, TIMx_CH2, and TIMx_CH3) connected through a XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register). The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus, each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a time base triggered by any change on the Hall inputs. On the “interfacing timer”, capture/compare channel 1 is configured in capture mode, capture signal is TRC (see Figure 78: Capture/compare channel (example: channel 1 input stage) on page 309). The captured value, which corresponds to the time elapsed between 2 changes on the inputs, gives information about motor speed. The “interfacing timer” can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or PWM mode). This pulse is sent to the advanced-control timer (TIM1 or TIM8) through the TRGO output. Example: you want to change the PWM configuration of your advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, • Program the time base: write the TIMx_ARR to the max value (the counter must be cleared by the TI1 change. Set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors, • Program channel 1 in capture mode (TRC selected): write the CC1S bits in the TIMx_CCMR1 register to ‘11’. You can also program the digital filter if needed, • Program channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to ‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR1 register, • Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 register to ‘101’, In the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the timer is programmed to generate PWM signals, the capture/compare control signals are preloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the trigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are 327/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF). Figure 95 describes this example. Figure 95. Example of hall sensor interface Interfacing timer TIH1 TIH2 TIH3 counter (CNT) (CCR2) CCR1 TRGO=OC2REF C7A3 C7A8 C794 C7A5 C7AB C796 advanced-control timers (TIM1&TIM8) COM OC1 OC1N OC2 OC2N OC3 OC3N Write CCxE, CCxNE and OCxM for next step ai17335 DocID13902 Rev 15 328/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: • Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only). • Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. • Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 96. Control circuit in reset mode TI1 UG Counter clock = ck_cnt = ck_psc Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03 TIF 329/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. • Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 97. Control circuit in gated mode TI1 CNT_EN Counter clock = ck_cnt = ck_psc Counter register 30 31 32 33 34 TIF 35 36 37 38 Write TIF=0 DocID13902 Rev 15 330/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 98. Control circuit in trigger mode TI2 CNT_EN Counter clock = ck_cnt = ck_psc Counter register 34 TIF 35 36 37 38 Slave mode: external clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register. In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: 1. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS = 00: prescaler disabled – ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. 331/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) 2. Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01 in TIMx_CCMR1 register to select only the input capture source – CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge only). 3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. Figure 99. Control circuit in external clock mode 2 + trigger mode TI1 CEN/CNT_EN ETR Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 14.3.20 Timer synchronization The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 15.3.15: Timer synchronization on page 391 for details. 14.3.21 Debug mode When the microcontroller enters debug mode (Cortex®-M3 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. DocID13902 Rev 15 332/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.4 14.4.1 TIM1&TIM8 registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). TIM1&TIM8 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CKD[1:0] rw rw ARPE rw CMS[1:0] rw rw DIR OPM URS UDIS CEN rw rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD[1:0]: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS)used by the dead-time generators and the digital filters (ETR, TIx), 00: tDTS=tCK_INT 01: tDTS=2*tCK_INT 10: tDTS=4*tCK_INT 11: Reserved, do not program this value Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:5 CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 333/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. 14.4.2 TIM1&TIM8 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 Res. 14 OIS4 rw 13 OIS3N rw 12 OIS3 rw 11 OIS2N rw 10 OIS2 rw 9 OIS1N rw 8 OIS1 rw 7 TI1S rw 6 5 4 MMS[2:0] rw rw rw 3 CCDS rw 2 CCUS rw 1 Res. 0 CCPC rw Bit 15 Reserved, must be kept at reset value. Bit 14 OIS4: Output Idle state 4 (OC4 output) refer to OIS1 bit Bit 13 OIS3N: Output Idle state 3 (OC3N output) refer to OIS1N bit Bit 12 OIS3: Output Idle state 3 (OC3 output) refer to OIS1 bit Bit 11 OIS2N: Output Idle state 2 (OC2N output) refer to OIS1N bit DocID13902 Rev 15 334/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Bit 10 OIS2: Output Idle state 2 (OC2 output) refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Bit 8 OIS1: Output Idle state 1 (OC1 output) 0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[2:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enable. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO). 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Compare - OC3REF signal is used as trigger output (TRGO) 111: Compare - OC4REF signal is used as trigger output (TRGO) Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs 335/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output. Bit 1 Reserved, must be kept at reset value. Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when a commutation event (COM) occurs (COMG bit set or rising edge detected on TRGI, depending on the CCUS bit). Note: This bit acts only on channels that have a complementary output. DocID13902 Rev 15 336/1128 359 Advanced-control timers (TIM1&TIM8) 14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 RM0008 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] Res. SMS[2:0] rw rw rw rw rw rw rw rw rw rw rw rw Res. rw rw rw Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge. Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 337/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bit 7 MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. Bits 6:4 TS[2:0]: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) See Table 82: TIMx Internal trigger connection on page 339 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. DocID13902 Rev 15 338/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal clock. 001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Table 82. TIMx Internal trigger connection(1) Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM1 TIM8 TIM5 TIM1 TIM2 TIM2 TIM3 TIM4 TIM4 TIM5 1. When a timer is not present in the product, the corresponding trigger ITRx is not available. 14.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 TDE COMDE CC4DE CC3DE CC2DE CC1DE UDE BIE Res. rw rw rw rw rw rw rw rw 6 5 4 3 2 1 0 TIE COMIE CC4IE CC3IE CC2IE CC1IE UIE rw rw rw rw rw rw rw Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled 339/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Bit 5 COMIE: COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled Bit 4 CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled 1: CC4 interrupt enabled Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled DocID13902 Rev 15 340/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.4.5 TIM1&TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 Reserved 12 11 10 9 CC4OF CC3OF CC2OF CC1OF rc_w0 rc_w0 rc_w0 rc_w0 8 Res. Res. 7 BIF rc_w0 6 TIF rc_w0 5 4 COMIF CC4IF rc_w0 rc_w0 3 CC3IF rc_w0 2 CC2IF rc_w0 1 CC1IF rc_w0 0 UIF rc_w0 Bits 15:13 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF: Capture/Compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 Reserved, must be kept at reset value. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred. 1: An active level has been detected on the break input. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bit 5 COMIF: COM interrupt flag This flag is set by hardware on COM event (when Capture/compare Control bits - CCxE, CCxNE, OCxM - have been updated). It is cleared by software. 0: No COM event occurred. 1: COM interrupt pending. Bit 4 CC4IF: Capture/Compare 4 interrupt flag refer to CC1IF description Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description 341/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –At overflow or underflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. –When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. –When CNT is reinitialized by a trigger event (refer to Section 14.4.3: TIM1&TIM8 slave mode control register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register. 14.4.6 TIM1&TIM8 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 1 0 BG TG COMG CC4G CC3G CC2G CC1G UG w w w w w w w w Bits 15:8 Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled. DocID13902 Rev 15 342/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. Bit 5 COMG: Capture/Compare control update generation This bit can be set by software, it is automatically cleared by hardware 0: No action 1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits Note: This bit acts only on channels having a complementary output. Bit 4 CC4G: Capture/Compare 4 generation refer to CC1G description Bit 3 CC3G: Capture/Compare 3 generation refer to CC1G description Bit 2 CC2G: Capture/Compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 343/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) 14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 15 OC2 CE rw 14 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2 PE OC2 FE IC2PSC[1:0] rw rw 9 8 CC2S[1:0] rw rw 7 OC1 CE rw 6 5 4 OC1M[2:0] IC1F[3:0] rw rw rw 3 2 OC1 PE OC1 FE IC1PSC[1:0] rw rw 1 0 CC1S[1:0] rw rw Output compare mode: Bit 15 OC2CE: Output Compare 2 clear enable Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). Bit 7 OC1CE: Output Compare 1 clear enable OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF Input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input DocID13902 Rev 15 344/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=’1’). 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else inactive. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output Compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). 345/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER). Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER). DocID13902 Rev 15 346/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. 15 OC4 CE rw 14 13 12 OC4M[2:0] IC4F[3:0] rw rw rw 11 10 OC4 PE OC4 FE IC4PSC[1:0] rw rw 9 8 CC4S[1:0] rw rw 7 OC3 CE. rw 6 5 4 OC3M[2:0] IC3F[3:0] rw rw rw 3 2 OC3 PE OC3 FE IC3PSC[1:0] rw rw 1 0 CC3S[1:0] rw rw Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER). 347/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER). Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER). 14.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER) Address offset: 0x20 15 14 Reserved Reset value: 0x0000 13 12 11 10 9 CC4P CC4E CC3NP CC3NE CC3P rw rw rw rw rw 8 7 6 5 CC3E CC2NP CC2NE CC2P rw rw rw rw 4 3 2 1 CC2E CC1NP CC1NE CC1P rw rw rw rw 0 CC1E rw Bits 15:14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output polarity refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity refer to CC1NP description Bit 10 CC3NE: Capture/Compare 3 complementary output enable refer to CC1NE description Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description DocID13902 Rev 15 348/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high. 1: OC1N active low. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=”00” (the channel is configured in output). Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: This bit selects whether IC1 or IC1 is used for trigger or capture operations. 0: non-inverted: capture is done on a rising edge of IC1. When used as external trigger, IC1 is non-inverted. 1: inverted: capture is done on a falling edge of IC1. When used as external trigger, IC1 is inverted. Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. 349/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Table 83. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states(1) MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state 0 0 Output Disabled (not driven by Output Disabled (not driven by the 0 the timer) timer) OCx=0, OCx_EN=0 OCxN=0, OCxN_EN=0 0 0 1 Output Disabled (not driven by the timer) OCx=0, OCx_EN=0 OCxREF + Polarity OCxN=OCxREF xor CCxNP, OCxN_EN=1 0 1 OCxREF + Polarity 0 OCx=OCxREF xor CCxP, OCx_EN=1 Output Disabled (not driven by the timer) OCxN=0, OCxN_EN=0 0 1 1 X 1 0 1 OCREF + Polarity + dead-time OCx_EN=1 Complementary to OCREF (not OCREF) + Polarity + dead-time OCxN_EN=1 Output Disabled (not driven by Output Disabled (not driven by the 0 the timer) timer) OCx=CCxP, OCx_EN=0 OCxN=CCxNP, OCxN_EN=0 1 0 Off-State (output enabled with OCxREF + Polarity 1 inactive state) OCxN=OCxREF xor CCxNP, OCx=CCxP, OCx_EN=1 OCxN_EN=1 1 1 OCxREF + Polarity 0 OCx=OCxREF xor CCxP, OCx_EN=1 Off-State (output enabled with inactive state) OCxN=CCxNP, OCxN_EN=1 1 1 1 OCREF + Polarity + dead-time OCx_EN=1 Complementary to OCREF (not OCREF) + Polarity + dead-time OCxN_EN=1 0 0 0 0 0 1 0 1 0 1 X 0 1 0 1 1 1 1 0 Output Disabled (not driven by the timer) 1 Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP, 0 OCxN_EN=0 Then if the clock is present: OCx=OISx and OCxN=OISxN after a 1 dead-time, assuming that OISx and OISxN do not correspond to OCX 0 and OCxN both in active state. 1 Off-State (output enabled with inactive state) 0 Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP, OCxN_EN=1 Then if the clock is present: OCx=OISx and OCxN=OISxN after a 1 dead-time, assuming that OISx and OISxN do not correspond to OCX and OCxN both in active state 1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared. Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIOand AFIO registers. DocID13902 Rev 15 350/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 14.4.11 TIM1&TIM8 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”). 14.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to Section 14.3.1: Time-base unit on page 295 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 351/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) 14.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 1 0 REP[7:0] rw rw rw rw rw rw rw rw Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. Each time the REP_CNT related downcounter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken in account until the next repetition update event. It means in PWM mode (REP+1) corresponds to: – the number of PWM periods in edge-aligned mode – the number of half PWM period in center-aligned mode. 14.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). DocID13902 Rev 15 352/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR2[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 14.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR3[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR3[15:0]: Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). 353/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) 14.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR4[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. If channel CC4 is configured as input: CCR4 is the counter value transferred by the last input capture 4 event (IC4). 14.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR) Address offset: 0x44 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it can be necessary to configure all of them during the first write access to the TIMx_BDTR register. Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: OC and OCN outputs are disabled or forced to idle state. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register). See OC/OCN enable description for more details (Section 14.4.9: TIM1&TIM8 capture/compare enable register (TIMx_CCER) on page 348). Bit 14 AOE: Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if the break input is not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). DocID13902 Rev 15 354/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 12 BKE: Break enable 0: Break inputs (BRK and CSS clock failure event) disabled 1; Break inputs (BRK and CSS clock failure event) enabled Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels having a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details (Section 14.4.9: TIM1&TIM8 capture/compare enable register (TIMx_CCER) on page 348). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1 Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details (Section 14.4.9: TIM1&TIM8 capture/compare enable register (TIMx_CCER) on page 348). 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0). 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1) Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register). Bits 9:8 LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected. 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset. 355/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS. DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS. DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS. DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS. Example if TDTS=125ns (8MHz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 14.4.19 TIM1&TIM8 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 12 11 10 9 8 Reserved DBL[4:0] rw rw rw rw rw 7 6 5 Reserved 4 3 2 1 0 DBA[4:0] rw rw rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer detects a burst transfer when a read or a write access to the TIMx_DMAR register address is performed). the TIMx_DMAR address) 00000: 1 transfer 00001: 2 transfers 00010: 3 transfers ... 10001: 18 transfers Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. DocID13902 Rev 15 356/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 14.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAB[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). Note: Example of how to use the DMA burst feature In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. This is done in the following steps: 1. Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. – Number of data to transfer = 3 (See note below). – Circular mode disabled. 2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE. 3. Enable the TIMx update DMA request (set the UDE bit in the DIER register). 4. Enable TIMx 5. Enable the DMA channel This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4. 357/1128 DocID13902 Rev 15 RM0008 Advanced-control timers (TIM1&TIM8) CEN 0 14.4.21 TIM1&TIM8 register map TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Offset Register Table 84. TIM1&TIM8 register map and reset values UDIS 1 URS 2 OPM 3 4 5 6 ARPE 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x00 0x04 0x08 TIMx_CR1 Reset value TIMx_CR2 Reset value TIMx_SMCR Reset value 0x0C TIMx_DIER Reset value 0x10 TIMx_SR Reset value 0x14 0x18 0x1C TIMx_EGR Reset value TIMx_CCMR1 Output Compare mode Reset value TIMx_CCMR1 Input Capture mode Reset value TIMx_CCMR2 Output Compare mode Reset value TIMx_CCMR2 Input Capture mode Reset value 0x20 0x24 0x28 0x2C TIMx_CCER Reset value TIMx_CNT Reset value TIMx_PSC Reset value TIMx_ARR Reset value 0x30 TIMx_RCR Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved O24CE OC4PE OC4FE OC3CE OC3PE OC3FE OC2CE OC2PE OC2FE OC1CE OC1PE OC1FE ETP CC3IE Reserved CCDS DIR CKD [1:0] CMS [1:0] 0000000000 CCPC Reserved CCUS TI1S OIS1 OIS1N OIS2 OIS2N OIS3 OIS3N OIS4 MMS[2:0] 0000000000000 0 MSM ECE ETPS [1:0] ETF[3:0] TS[2:0] SMS[2:0] 000000000000 000 UIE CC1IE CC2IE CC4IE COMIE TIE BIE UDE CC1DE CC2DE CC3DE CC4DE COMDE TDE 000000000000000 UIF CC1G CC1IF CC2G CC2IF CC3G CC3IF CC4G CC4IF COMG COMIF TIF BIF Reserved CC1OF CC2OF CC3OF CC4OF 0000 00000000 UG TG BG 00000000 OC2M [2:0] CC2S [1:0] OC1M [2:0] CC1S [1:0] 0000 IC2F[3:0] 0000 00 IC2 PSC [1:0] 00 00 CC2S [1:0] 00 0000 IC1F[3:0] 0000 00 IC1 PSC [1:0] 00 00 CC1S [1:0] 00 OC4M [2:0] CC4S [1:0] OC3M [2:0] CC3S [1:0] 0000 IC4F[3:0] 0000 00 IC4 PSC [1:0] 00 00 CC4S [1:0] 00 0000 IC3F[3:0] 0000 00 IC3 PSC [1:0] 00 00 CC3S [1:0] 00 CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E 00000000000000 CNT[15:0] 0000000000000000 PSC[15:0] 0000000000000000 ARR[15:0] 0000000000000000 REP[7:0] 00000000 DocID13902 Rev 15 358/1128 359 Advanced-control timers (TIM1&TIM8) RM0008 0 Table 84. TIM1&TIM8 register map and reset values (continued) Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C TIMx_CCR1 Reset value TIMx_CCR2 Reset value TIMx_CCR3 Reset value TIMx_CCR4 Reset value TIMx_BDTR Reset value TIMx_DCR Reset value TIMx_DMAR Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved MOE CCR1[15:0] 0000000000000000 CCR2[15:0] 0000000000000000 CCR3[15:0] 0000000000000000 CCR4[15:0] 0000000000000000 OSSI OSSR BKE BKP AOE LOCK [1:0] DT[7:0] 0000000000000000 DBL[4:0] Reserved DBA[4:0] 00000 00000 DMAB[15:0] 0000000000000000 Refer to Table 3 on page 51 for the register boundary addresses. 359/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) 15 General-purpose timers (TIM2 to TIM5) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This Section applies to the whole STM32F10xxx family, unless otherwise specified. 15.1 TIM2 to TIM5 introduction The general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 15.3.15. DocID13902 Rev 15 360/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 15.2 TIMx main features General-purpose TIMx timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536. • Up to 4 independent channels for: – Input capture – Output compare – PWM generation (Edge- and Center-aligned modes) – One-pulse mode output • Synchronization circuit to control the timer with external signals and to interconnect several timers. • Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare • Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes • Trigger input for external clock or cycle-by-cycle current management 361/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) TIMx_ETR Figure 100. General-purpose timer block diagram Internal Clock (CK_INT) TIMxCLK from RCC ETR ETRP Polarity selection & edge detector & prescaler Input filter ITR0 ITR1 ITR2 ITR3 ITR TRC TI1F_ED ETRF TGI TRGI Trigger controller Slave mode controller TRGO to other timers to DAC/ADC Reset, enable, up/down, count, TI1FP1 TI2FP2 Encoder Interface TIMx_CH1 TIMx_CH2 TIMx_CH3 TIMx_CH4 XOR TI1 TI2 TI3 TI4 U Autoreload register Input filter & edge detector Input filter & edge detector Input filter & edge detector Input filter & edge detector Stop, clear or up/down CK_PSC PSC CK_CNT Prescaler TI1FP1 TI1FP2 CC1I IC1 IC1PS U Prescaler +/- CNT counter Capture/compare 1 register TRC CC2I TI2FP1 TI2FP2 TRC TI3FP3 TI3FP4 IC2 IC2PS U Prescaler CC3I IC3 IC3PS U Prescaler Capture/compare 2 register Capture/compare 3 register TRC CC4I TI4FP3 TI4FP4 TRC IC4 IC4PS U Prescaler Capture/compare 4 register ETRF UI U CC1I OC1REF output control OC1 CC2I OC2REF output control OC2 CC3I OC3REF output control OC3 CC4I OC4REF output control OC4 TIMx_CH1 TIMx_CH2 TIMx_CH3 TIMx_CH4 Notes: Reg Preload registers transferred to active registers on U event according to control bit event interrupt & DMA output 15.3 15.3.1 TIMx functional description Time-base unit The main block of the programmable timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC): • Auto-Reload Register (TIMx_ARR) DocID13902 Rev 15 362/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 101 and Figure 102 give some examples of the counter behavior when the prescaler ratio is changed on the fly: Figure 101. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 02 03 Update event (UEV) Prescaler control register 0 1 Write a new value in TIMx_PSC Prescaler buffer 0 1 Prescaler counter 0 01 01 01 01 363/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Figure 102. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 Update event (UEV) Prescaler control register 0 3 Write a new value in TIMx_PSC Prescaler buffer 0 3 Prescaler counter 0 01 23 01 23 15.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) • The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. DocID13902 Rev 15 364/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Figure 103. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Figure 104. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0034 0035 0036 0000 0001 0002 0003 Update interrupt flag (UIF) Figure 105. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0035 0036 0000 0001 Update interrupt flag (UIF) 365/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Figure 106. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register 1F 20 00 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR DocID13902 Rev 15 366/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Figure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register F5 36 Auto-reload shadow register F5 36 Write a new value in TIMx_ARR Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. 367/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Figure 109. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter underflow (cnt_udf) Update event (UEV) 05 04 03 02 01 00 36 35 34 33 32 31 30 2F Update interrupt flag (UIF) Figure 110. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0002 0001 0000 0036 0035 0034 0033 Update interrupt flag (UIF) Figure 111. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0001 0000 0036 0035 Update interrupt flag (UIF) DocID13902 Rev 15 368/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Figure 112. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register 20 1F 00 36 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 113. Counter timing diagram, Update event CK_INT CNT_EN Timer clock = CK_CNT Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11"). In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. 369/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. Figure 114. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter underflow Counter overflow Update event (UEV) 04 03 02 01 00 01 02 03 04 05 06 05 04 03 Update interrupt flag (UIF) 1. Here, center-aligned mode 1 is used (for more details refer to Section 15.4.1: TIMx control register 1 (TIMx_CR1) on page 397). DocID13902 Rev 15 370/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Figure 115. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN TImer clock = CK_CNT Counter register Counter underflow Update event (UEV) 0003 0002 0001 0000 0001 0002 0003 Update interrupt flag (UIF) Figure 116. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow (cnt_ovf) Update event (UEV) 0034 0035 0036 0035 Update interrupt flag (UIF) 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 117. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register 20 1F 01 00 Counter underflow Update event (UEV) Update interrupt flag (UIF) 371/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register FD 36 Write a new value in TIMx_ARR Auto-reload active register FD 36 Figure 119. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register FD 36 Write a new value in TIMx_ARR Auto-reload active register FD 36 15.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) • External clock mode2: external trigger input (ETR). • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer1 to act as a prescaler for Timer 2. Refer to : Using one timer as prescaler for another on page 391 for more details. DocID13902 Rev 15 372/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 120 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 120. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN UG CNT_INIT Counter clock = CK_CNT = CK_PSC COUNTER REGISTER 31 32 33 34 35 36 00 01 02 03 04 05 06 07 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 121. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2 Filter DeEtdegcetor ICF[3:0] TIMx_CCMR1 TI2F_Rising0 TI2F_Fallin1g ITRx or TI2F or TI1F or 001 TI1F_ED100 TI1FP1 101 TRGI TI2FP2 110 ETRF 111 ETRF emnocdoeder emxotedrena1l clock CK_PSC emxotedrena2l clock CC2P TIMx_CCER CK_INT (internal clock) imntoedrneal clock ECE SMS[2:0] TIMx_SMCR For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). 373/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Note: The capture prescaler is not used for triggering, so you don’t need to configure it. 3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 122. Control circuit in external clock mode 1 TI2 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 Write TIF=0 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 123 gives an overview of the external trigger input block. Figure 123. External trigger input block ETR pin ETR 0 1 ETP TIMx_SMCR divider ETRP /1, /2, /4, /8 CK_INT filter downcounter ETPS[1:0] TIMx_SMCR ETF[3:0] TIMx_SMCR or TI2F TI1F or or emnocdoeder TRGI emxotedrena1l clock CK_PSC ETRF external clock mode 2 CK_INT (internal clock) imntoedrenal clock ECE SMS[2:0] TIMx_SMCR For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: DocID13902 Rev 15 374/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 124. Control circuit in external clock mode 2 CK_INT CNT_EN ETR ETRP ETRF Counter clock = CK_CNT = CK_PSC Counter register 34 35 36 15.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). The following figure gives an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). Figure 125. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1 filter TI1F Edge TI1F_Rising 0 TI1FP1 fDTS downcounter Detector TI1F_Falling 1 TI2FP1 01 10 IC1 divider IC1PS /1, /2, /4, /8 ICF[3:0] TIMx_CCMR1 CC1P TIMx_CCER TI2F_rising 0 (from channel 2) TI2F_falling (from channel 2) 1 TRC (from slave mode 11 controller) CC1S[1:0] ICPS[1:0] TIMx_CCMR1 CC1E TIMx_CCER 375/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 126. Capture/compare channel 1 main circuit APB Bus read CCR1H S read CCR1L R CC1S[1] CC1S[0] IC1PS CC1E CC1G TIMx_EGR MCU-peripheral interface high (if 16-bit) low 8 8 read_in_progress write_in_progress Capture/Compare Preload Register S write CCR1H R write CCR1L input mode capture_transfer compare_transfer output mode Capture/Compare Shadow Register capture comparator CC1S[1] CC1S[0] OC1PE OC1PE UEV (from time TIMx_CCMR1 base unit) CNT>CCR1 Counter CNT=CCR1 Figure 127. Output stage of capture/compare channel (channel 1) KZ&ͺ>Z dZ& Ϭ KZ&ͺ>Zͺ/Ed ϭ K^ d/Ddžͺ^DZ EdхZϭ KƵƚƉƵƚŵŽĚĞ ŽĐϭƌĞĨ EdсZϭ ĐŽŶƚƌŽůůĞƌ dŽƚŚĞŵĂƐƚĞƌŵŽĚĞ ĐŽŶƚƌŽůůĞƌ Ϭ ϭ ϭW d/DdžͺZ KƵƚƉƵƚ Kϭ ŶĂďůĞ ŝƌĐƵŝƚ KϭD΀Ϯ͗Ϭ΁ d/DdžͺDZϭ ϭ d/DdžͺZ Ăŝϭϳϭϴϳ The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. DocID13902 Rev 15 376/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 15.3.5 Note: Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: • Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. • Program the input filter duration you need with respect to the signal you connect to the timer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of the TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. • Select the edge of the active transition on the TI1 channel by writing the CC1P bit to 0 in the TIMx_CCER register (rising edge in this case). • Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the TIMx_CCMR1 register). • Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. • If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. • A DMA request is generated depending on the CC1DE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. 377/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) 15.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): • Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). • Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ‘0’ (active on rising edge). • Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). • Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ (active on falling edge). • Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). • Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. • Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register. Figure 128. PWM input mode timing TI1 TIMx_CNT 0004 0000 0001 0002 0003 0004 0000 TIMx_CCR1 0004 TIMx_CCR2 0002 IC1 capture IC2 capture reset counter IC2 capture pulse width measurement IC1 capture period measurement ai15413 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. DocID13902 Rev 15 378/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 15.3.7 15.3.8 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. e.g.: CCxP=0 (OCx active high) => OCx is forced to high level. ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). • Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). • Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on ocxref and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated. 4. Select the output mode. For example, you must write OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high. 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. 379/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 129. Figure 129. Output compare mode, toggle on OC1 Write B201h in the CC1R register TIMx_CNT 0039 TIMx_CCR1 003A 003B 003A OC1REF=OC1 B200 B201 B201 15.3.9 Match detected on CCR1 Interrupt generated if enabled PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx≤ TIMx_CNT or TIMx_CNT≤ TIMx_CCRx (depending on the direction of the counter). However, to comply with the ETRF (OCREF can be cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: • When the result of the comparison changes, or • When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes (OCxM=‘110 or ‘111). DocID13902 Rev 15 380/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 This forces the PWM by software while the timer is running. The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section : Upcounting mode on page 364. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT 8 CCxIF OCxREF ‘0 CCRx=0 CCxIF Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section : Downcounting mode on page 367. In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Section : Center-aligned mode (up/down counting) on page 369. 381/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Figure 131 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. Figure 131. Center-aligned PWM waveforms (ARR=8) #OUNTERREGISTER                   /#X2%& ##2X ##X)& /#X2%& ##2X #-3 #-3 #-3 ##X)& #-3OR /#X2%& gg ##2X ##X)& /#X2%& gg ##2X #-3 #-3 #-3 ##X)& /#X2%& gg ##2X #-3 #-3 #-3 ##X)& #-3 #-3 #-3 AIB Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit DocID13902 Rev 15 382/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. • The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. 15.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: • In upcounting: CNTCCRx. Figure 132. Example of one-pulse mode TI2 OC1REF OC1 Counter TIM1_ARR TIM1_CCR1 0 tDELAY tPULSE t For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. 383/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register. • TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register (trigger mode). The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR + 1). • Let’s say you want to build a waveform with a transition from ‘0 to ‘1 when a compare match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0 in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable: In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 15.3.11 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to '1'). The OCxREF signal remains Low until the next update event, UEV, occurs. This function can only be used in output compare and PWM modes, and does not work in forced mode. For example, the ETR signal can be connected to the output of a comparator to be used for current handling. In this case, ETR must be configured as follows: DocID13902 Rev 15 384/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. 2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. 3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs. Figure 133 shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in PWM mode. Figure 133. Clearing TIMx OCxREF counter (CNT) (CCRx) ETRF OCxREF (OCxCE=0) OCxREF (OCxCE=1) ETRF becomes high ETRF still high 15.3.12 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, you can program the input filter as well. The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 85. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal. 385/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. Active edge Counting on TI1 only Counting on TI2 only Counting on TI1 and TI2 Table 85. Counting direction versus encoder signals Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) TI1FP1 signal Rising Falling TI2FP2 signal Rising Falling High Down Up No Count No Count Low Up Down No Count No Count High No Count No Count Up Down Low No Count No Count Down Up High Down Up Up Down Low Up Down Down Up An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. Figure 134 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: • CC1S= ‘01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1) • CC2S= ‘01’ (TIMx_CCMR2 register, TI2FP2 mapped on TI2) • CC1P= ‘0’, CC1NP = ‘0’, IC1F =’0000’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1) • CC2P= ‘0’, CC2NP = ‘0’, IC2F =’0000’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2) • SMS= ‘011’ (TIMx_SMCR register, both inputs are active on both rising and falling edges) • CEN = 1 (TIMx_CR1 register, Counter is enabled) DocID13902 Rev 15 386/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Figure 134. Example of counter operation in encoder interface mode forward jitter backward jitter forward TI1 TI2 Counter up down up Figure 135 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 135. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward TI1 TI2 Counter down up down The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a Real-Time clock. 387/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) 15.3.13 Timer input XOR function The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture. An example of this feature used to interface Hall sensors is given in Section 14.3.18 on page 327. 15.3.14 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: • Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only). • Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. • Start the counter by writing CEN=1 in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 136. Control circuit in reset mode TI1 UG Counter clock = CK_CNT = CK_PSC Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03 TIF DocID13902 Rev 15 388/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. • Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 137. Control circuit in gated mode TI1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 30 31 32 33 34 TIF Write TIF=0 35 36 37 38 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. CC2S bits are selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. 389/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Figure 138. Control circuit in trigger mode TI2 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 37 38 Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register. In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: 1. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS = 00: prescaler disabled – ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. 2. Configure the channel 1 as follows, to detect rising edges on TI: – IC1F = 0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S = 01 in TIMx_CCMR1 register to select only the input capture source – CC1P = 0 in TIMx_CCER register to validate the polarity (and detect rising edge only). 3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. DocID13902 Rev 15 390/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Figure 139. Control circuit in external clock mode 2 + trigger mode TI1 CEN/CNT_EN ETR Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 15.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode. Figure 140: Master/Slave timer example presents an overview of the trigger selection and the master mode selection blocks. Using one timer as prescaler for another Figure 140. Master/Slave timer example Clock Prescaler TIM1 UEV Counter MMS TIM2 TS SMS Master mode control TRGO1 ITR0 Slave mode control CK_PSC Prescaler Input trigger selection Counter Note: For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 140. To do this: • Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is output on TRGO1 each time an update event is generated. • To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in slave mode using ITR0 as internal trigger. You select this through the TS bits in the TIM2_SMCR register (writing TS=000). • Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow). • Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register). If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock the counter of timer 2. 391/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Note: Using one timer to enable another timer In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1. Refer to Figure 140 for connections. Timer 2 counts on the divided internal clock only when OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3). • Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register). • Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register). • Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). • Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register). • Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register). • Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register). The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2 counter enable signal. Figure 141. Gating timer 2 with OC1REF of timer 1 CK_INT TIMER1-OC1REF TIMER1-CNT TIMER2-CNT TIMER 2-TIF FC 3045 FD FE FF 3046 3047 00 01 3048 Write TIF=0 In the example in Figure 141, the Timer 2 counter and prescaler are not initialized before being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting Timer 1. You can then write any value you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both DocID13902 Rev 15 392/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 timers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1 register: • Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register). • Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register). • Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). • Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register). • Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register). • Reset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register). • Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL). • Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register). • Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register). • Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register). Figure 142. Gating timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT 75 00 01 02 TIMER2-CNT AB 00 E7 E8 E9 TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF Write TIF=0 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 140 for connections. Timer 2 starts counting from its current value (which can be nonzero) on the divided internal clock as soon as the update event is generated by Timer 1. When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3). • Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register). • Configure the Timer 1 period (TIM1_ARR registers). • Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). • Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register). • Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register). 393/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Figure 143. Triggering timer 2 with update of timer 1 CK_INT TIMER1-UEV TIMER1-CNT TIMER2-CNT TIMER2-CEN=CNT_EN FD FE FF 45 00 01 02 46 47 48 TIMER 2-TIF Write TIF=0 As in the previous example, you can initialize both counters before starting counting. Figure 144 shows the behavior with the same configuration as in Figure 141 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 144. Triggering timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT 75 TIMER2-CNT CD TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF 00 00 E7 01 02 E8 E9 EA Write TIF=0 DocID13902 Rev 15 394/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Note: Using one timer as prescaler for another timer For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 140 for connections. To do this: • Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register). then it outputs a periodic signal on each counter overflow. • Configure the Timer 1 period (TIM1_ARR registers). • Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). • Configure Timer 2 in external clock mode 1 (SMS=111 in TIM2_SMCR register). • Start Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register). • Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register). Starting 2 timers synchronously in response to an external trigger In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of Timer 2 with the enable of Timer 1. Refer to Figure 140 for connections. To ensure the counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): • Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register). • Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the TIM1_SMCR register). • Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register). • Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register). • Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR register). • Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register). When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on the internal clock and both TIF flags are set. In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0, but you can easily insert an offset between them by writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on timer 1. 395/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Figure 145. Triggering timer 1 and 2 with timer 1 TI1 input CK_INT TIMER 1-TI1 TIMER1-CEN=CNT_EN TIMER 1-CK_PSC TIMER1-CNT TIMER1-TIF TIMER2-CEN=CNT_EN TIMER 2-CK_PSC TIMER2-CNT TIMER2-TIF 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04 05 06 07 08 09 15.3.16 Debug mode When the microcontroller enters debug mode (Cortex®-M3 core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBGMCU module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. DocID13902 Rev 15 396/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 15.4 TIMx2 to TIM5 registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 15.4.1 TIMx control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Reserved CKD[1:0] rw rw ARPE rw 6 5 CMS rw rw 4 3 2 1 0 DIR OPM URS UDIS CEN rw rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 397/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. DocID13902 Rev 15 398/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 15.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 Reserved 8 7 TI1S rw 6 5 4 MMS[2:0] rw rw rw 3 CCDS rw 2 1 0 Reserved Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section 14.3.18: Interfacing with Hall sensors on page 327 Bits 6:4 MMS[2:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Compare - OC3REF signal is used as trigger output (TRGO) 111: Compare - OC4REF signal is used as trigger output (TRGO) Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bits 2:0 Reserved, must be kept at reset value. 399/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) 15.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 15 14 13 12 11 10 9 ETP ECE ETPS[1:0] ETF[3:0] rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 MSM TS[2:0] SMS[2:0] Res. rw rw rw rw rw rw rw rw Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. Bits 13:12 ETPS: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6 0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8 0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5 0011: fSAMPLING=fCK_INT, N=8²1011: fSAMPLING=fDTS/16, N=6 0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8 0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5 0110: fSAMPLING=fDTS/4, N=6²1110: fSAMPLING=fDTS/32, N=6 0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8 Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. DocID13902 Rev 15 400/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). 001: Internal Trigger 1 (ITR1). 010: Internal Trigger 2 (ITR2). 011: Internal Trigger 3 (ITR3). 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) See Table 86: TIMx Internal trigger connection on page 401for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level. 010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level. 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. Table 86. TIMx Internal trigger connection(1) Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM2 TIM3 TIM4 TIM5 TIM1 TIM1 TIM1 TIM2 TIM8 TIM2 TIM2 TIM3 TIM3 TIM5 TIM3 TIM4 TIM4 TIM4 TIM8 TIM8 1. When a timer is not present in the product, the corresponding trigger ITRx is not available. 401/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) 15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 TDE CC4DE CC3DE CC2DE CC1DE UDE TIE Res. Res Res. rw rw rw rw rw rw rw 5 4 3 2 1 0 CC4IE CC3IE CC2IE CC1IE UIE Res rw rw rw rw rw Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled. Bit 13 Reserved, always read as 0 Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled. Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bit 7 Reserved, must be kept at reset value. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bit 5 Reserved, must be kept at reset value. Bit 4 CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled. Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled. 1: CC3 interrupt enabled. DocID13902 Rev 15 402/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. 15.4.5 TIMx status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 Reserved 12 11 10 9 CC4OF CC3OF CC2OF CC1OF rc_w0 rc_w0 rc_w0 rc_w0 8 7 Reserved 6 5 4 3 2 1 0 TIF CC4IF CC3IF CC2IF CC1IF UIF Res rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bit 15:13 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8:7 Reserved, must be kept at reset value. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode, both edges in case gated mode is selected). It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bit 5 Reserved, must be kept at reset value. Bit 4 CC4IF: Capture/Compare 4 interrupt flag refer to CC1IF description Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description 403/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1 register. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity). Bit 0 UIF: Update interrupt flag – This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow or underflow and if the UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. DocID13902 Rev 15 404/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 15.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TG CC4G CC3G CC2G CC1G UG Res. w w w w w w Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. Bit 5 Reserved, must be kept at reset value. Bit 4 CC4G: Capture/compare 4 generation refer to CC1G description Bit 3 CC3G: Capture/compare 3 generation refer to CC1G description Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 405/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) 15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) 15 OC2CE rw Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 14 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2PE OC2FE IC2PSC[1:0] rw rw 9 8 CC2S[1:0] rw rw 7 OC1CE rw 6 5 4 OC1M[2:0] IC1F[3:0] rw rw rw 3 2 OC1PE OC1FE IC1PSC[1:0] rw rw 1 0 CC1S[1:0] rw rw Output compare mode Bit 15 OC2CE: Output compare 2 clear enable Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bit 7 OC1CE: Output compare 1 clear enable OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input DocID13902 Rev 15 406/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1 else active (OC1REF=1). 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else inactive. Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: 1: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in output). 2: The PWM mode can be used without validating the preload register only in onepulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 407/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). DocID13902 Rev 15 408/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) 15 OC4CE rw Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. 14 13 12 OC4M[2:0] IC4F[3:0] rw rw rw 11 10 OC4PE OC4FE IC4PSC[1:0] rw rw 9 8 CC4S[1:0] rw rw 7 OC3CE rw 6 5 4 OC3M[2:0] IC3F[3:0] rw rw rw 3 2 OC3PE OC3FE IC3PSC[1:0] rw rw 1 0 CC3S[1:0] rw rw Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 409/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 15.4.9 TIMx capture/compare enable register (TIMx_CCER) Address offset: 0x20 15 14 Reserved Reset value: 0x0000 13 12 11 10 CC4P CC4E rw rw Reserved 9 CC3P rw 8 CC3E rw 7 6 Reserved 5 CC2P rw 4 CC2E rw 3 2 Reserved 1 CC1P rw 0 CC1E rw Bits 15:14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output polarity refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable refer to CC1E description Bits 11:10 Reserved, must be kept at reset value. Bit 9 CC3P: Capture/Compare 3 output polarity refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable refer to CC1E description Bits 7:6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description DocID13902 Rev 15 410/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bits 3:2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low. CC1 channel configured as input: This bit selects whether IC1 or IC1 is used for trigger or capture operations. 0: non-inverted: capture is done on a rising edge of IC1. When used as external trigger, IC1 is non-inverted. 1: inverted: capture is done on a falling edge of IC1. When used as external trigger, IC1 is inverted. Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. 1: On - OC1 signal is output on the corresponding output pin. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. CCxE bit 0 1 Table 87. Output control bit for standard OCx channels OCx output state Output Disabled (OCx=0, OCx_EN=0) OCx=OCxREF + Polarity, OCx_EN=1 Note: The state of the external IO pins connected to the standard OCx channels depends on the OCx channel state and the GPIO and AFIO registers. 15.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 411/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) 15.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. 15.4.12 TIMx auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Prescaler value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 15.3.1: Time-base unit on page 362 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 15.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). DocID13902 Rev 15 412/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 15.4.14 TIMx capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR2[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 15.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR3[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR3[15:0]: Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC3 output. If channel CC3 is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). 15.4.16 TIMx capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR4[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 413/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) Bits 15:0 CCR4[15:0]: Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). 15.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 12 11 10 9 8 Reserved DBL[4:0] rw rw rw rw rw 7 6 5 Reserved 4 3 2 1 0 DBA[4:0] rw rw rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 15.4.18 TIMx DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAB[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw DocID13902 Rev 15 414/1128 417 General-purpose timers (TIM2 to TIM5) RM0008 Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). Note: Example of how to use the DMA burst feature In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. This is done in the following steps: 1. Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. – Number of data to transfer = 3 (See note below). – Circular mode disabled. 2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE. 3. Enable the TIMx update DMA request (set the UDE bit in the DIER register). 4. Enable TIMx 5. Enable the DMA channel This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4. 415/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM2 to TIM5) 15.4.19 TIMx register map TIMx registers are mapped as described in the table below: Table 88. TIMx register map and reset values Offset Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x00 0x04 0x08 TIMx_CR1 Reset value TIMx_CR2 Reset value TIMx_SMCR Reset value 0x0C TIMx_DIER Reset value 0x10 TIMx_SR Reset value 0x14 0x18 0x1C TIMx_EGR Reset value TIMx_CCMR1 Output Compare mode Reset value TIMx_CCMR1 Input Capture mode Reset value TIMx_CCMR2 Output Compare mode Reset value TIMx_CCMR2 Input Capture mode Reset value 0x20 TIMx_CCER Reset value 0x24 TIMx_CNT Reset value 0x28 TIMx_PSC Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved O24CE OC4PE OC4FE OC3CE OC3PE OC3FE OC2CE ETP CC3IE Reserved CCDS CEN UDIS URS OPM DIR ARPE CKD [1:0] CMS [1:0] 0 0000000 0 0 Reserved TI1S MMS [2:0] 00000 MSM ECE ETPS [1:0] ETF[3:0] TS[2:0] SMS[2:0] 000 000000000 000 UIE CC1IE CC2IE CC4IE Reserved Reserved Reserved TIE Reserved UDE CC1DE CC2DE CC3DE CC4DE COMDE TDE 00 00000 0 000 0 0 UIF CC1IF CC2IF CC3IF CC4IF TIF Reserved CC1OF CC2OF CC3OF CC4OF 0000 0 000 0 0 UG CC1G CC2G CC3G CC4G TG 0 000 0 0 OC1FE OC1PE OC1CE OC2FE OC2PE OC2M [2:0] CC2S [1:0] OC1M [2:0] CC1S [1:0] 000 0 IC2F[3:0] 000 0 00 IC2 PSC [1:0] 00 00 CC2S [1:0] 00 0000 IC1F[3:0] 0000 00 IC1 PSC [1:0] 00 00 CC1S [1:0] 00 OC4M [2:0] CC4S [1:0] OC3M [2:0] CC3S [1:0] 000 0 IC4F[3:0] 000 0 00 IC4 PSC [1:0] 00 00 CC4S [1:0] 00 0000 IC3F[3:0] 0000 00 IC3 PSC [1:0] 00 00 CC3S [1:0] 00 Reserved CC4P CC4E Reserved CC3P CC3E Reserved CC2P CC2E Reserved CC1P CC1E 00 00 00 00 CNT[15:0] 000 0000000000000 PSC[15:0] 000 0000000000000 DocID13902 Rev 15 416/1128 417 General-purpose timers (TIM2 to TIM5) Table 88. TIMx register map and reset values (continued) Offset Register RM0008 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x2C 0x30 TIMx_ARR Reset value 0x34 0x38 0x3C 0x40 0x44 TIMx_CCR1 Reset value TIMx_CCR2 Reset value TIMx_CCR3 Reset value TIMx_CCR4 Reset value 0x48 0x4C TIMx_DCR Reset value TIMx_DMAR Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved ARR[15:0] 000 0000000000000 Reserved CCR1[15:0] 000 0000000000000 CCR2[15:0] 000 0000000000000 CCR3[15:0] 000 0000000000000 CCR4[15:0] 000 0000000000000 Reserved Reserved DBL[4:0] DBA[4:0] 0 00 0 0 000 0 0 DMAB[15:0] 000 0000000000000 Refer to Table 3 on page 51 for the register boundary addresses. 417/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) 16 General-purpose timers (TIM9 to TIM14) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to XL-density devices only. 16.1 TIM9 to TIM14 introduction The TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The TIM9 to TIM14 timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 16.3.12. DocID13902 Rev 15 418/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.2 16.2.1 TIM9 to TIM14 main features TIM9/TIM12 main features The features of the TIM9 to TIM14 general-purpose timers include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65536 (can be changed “on the fly”) • Up to 2 independent channels for: – Input capture – Output compare – PWM generation (edge-aligned mode) – One-pulse mode output • Synchronization circuit to control the timer with external signals and to interconnect several timers together • Interrupt generation on the following events: – Update: counter overflow, counter initialization (by software or internal trigger) – Trigger event (counter start, stop, initialization or count by internal trigger) – Input capture – Output compare Figure 146. General-purpose timer block diagram (TIM9 and TIM12) Internal clock (CK_INT) ITR0 ITR1 ITR2 ITR3 ITR TI1F_ED TRC Trigger TGI controller TRGI Slave mode controller Reset, Enable, Count TI1FP1 TI2FP2 TIMx_CH1 TIMx_CH2 TI1 TI2 U Auto-reload register CK_PSC PSC Prescaler CK_CNT TI1FP1 Input filter & Edge detector TI1FP2 CC1I IC1 IC1PS U Prescaler TRC CC2I Input filter & Edge detector TI2FP1 TI2FP2 TRC IC2 IC2PS U Prescaler Stop, Clear +/- CNT COUNTER Capture/Compare 1 register Capture/Compare 2 register UI U CC1I OC1REF output control OC1 CC2I OC2REF output control OC2 TIMx_CH1 TIMx_CH2 419/1128 Notes: Reg Preload registers transferred to active registers on U event according to control bit event interrupt DocID13902 Rev 15 ai17190 RM0008 General-purpose timers (TIM9 to TIM14) 16.2.2 TIM10/TIM11 and TIM13/TIM14 main features The features of general-purpose timers TIM10/TIM11 and TIM13/TIM14 include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65536 (can be changed “on the fly”) • independent channel for: – Input capture – Output compare – PWM generation (edge-aligned mode) – One-pulse mode output • Interrupt generation on the following events: – Update: counter overflow, counter initialization (by software) – Input capture – Output compare Figure 147. General-purpose timer block diagram (TIM10/11/13/14) )NTERNALCLOCK#+?).4 4RIGGER #ONTROLLER %NABLE COUNTER 4)-X?#( 5 !UTORELOADREGISTER 5) 3TOP #LEAR 5 #+?03# 03# #+?#.4 PRESCALER  #.4 COUNTER ##) ##) 4) )NPUTFILTER EDGEDETECTOR 4)&0 )# 5 0RESCALER )#03 #APTURE#OMPAREREGISTER /#2%& OUTPUT /# CONTROL 4)-X?#( .OTES 2EG 0RELOADREGISTERSTRANSFERRED TOACTIVEREGISTERSON5EVENT ACCORDINGTOCONTROLBIT EVENT INTERRUPT$-!OUTPUT -36 DocID13902 Rev 15 420/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.3 16.3.1 TIM9 to TIM14 functional description Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter register (TIMx_CNT) • Prescaler register (TIMx_PSC) • Auto-reload register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in details for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 148 and Figure 149 give some examples of the counter behavior when the prescaler ratio is changed on the fly. 421/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Figure 148. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CEN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 02 03 Update event (UEV) Prescaler control register 0 1 Write a new value in TIMx_PSC Prescaler buffer 0 1 Prescaler counter 0 01 01 01 01 Figure 149. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CEN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 Update event (UEV) Prescaler control register 0 3 Write a new value in TIMx_PSC Prescaler buffer 0 3 Prescaler counter 0 01 23 01 23 16.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM9 and TIM12) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without DocID13902 Rev 15 422/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): • The auto-reload shadow register is updated with the preload value (TIMx_ARR), • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 150. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Figure 151. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0034 0035 0036 0000 0001 0002 0003 Update interrupt flag (UIF) 423/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Figure 152. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0035 0036 0000 0001 Update interrupt flag (UIF) Figure 153. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register 1F 20 00 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 154. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC CEN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR DocID13902 Rev 15 424/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 Figure 155. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CEN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) Auto-reload preload register F5 36 Auto-reload shadow register F5 36 16.3.3 Write a new value in TIMx_ARR Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1 (for TIM9 and TIM12): external input pin (TIx) • Internal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from another timer. Refer to Section : Using one timer as prescaler for another for more details. Internal clock source (CK_INT) The internal clock source is the default clock source for TIM10/TIM11 and TIM13/TIM14. For TIM9 and TIM12, the internal clock source is selected when the slave mode controller is disabled (SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR register are then used as control bits and can be changed only by software (except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the prescaler is clocked by the internal clock CK_INT. Figure 156 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. 425/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Figure 156. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN UG CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Note: External clock source mode 1(TIM9 and TIM12) This mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 157. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2 Filter ICF[3:0] DeEtdegcetor TI2F_Rising TI2F_Falling 0 1 CC2P ITRx or TI2F TI1F or or 0xx TI1_ED 100 TI1FP1 101 TRGI TI2FP2 110 emxotedrena1l clock CK_PSC CK_INT (internal clock) imntoedrneal clock TIMx_CCMR1 TIMx_CCER SMS[2:0] TIMx_SMCR For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=’0000’). 3. Select the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR register. 5. Select TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register. 6. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register. The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. DocID13902 Rev 15 426/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.3.4 Figure 158. Control circuit in external clock mode 1 TI2 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 34 TIF 35 36 Write TIF=0 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 159 to Figure 161 give an overview of one capture/compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). Figure 159. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1 filter TI1F Edge TI1F_Rising 0 TI1FP1 fDTS downcounter Detector TI1F_Falling 1 TI2FP1 01 10 IC1 divider IC1PS /1, /2, /4, /8 ICF[3:0] TIMx_CCMR1 CC1P/CC1NP TIMx_CCER TI2F_rising 0 (from channel 2) TI2F_falling (from channel 2) 1 TRC (from slave mode 11 controller) CC1S[1:0] ICPS[1:0] TIMx_CCMR1 CC1E TIMx_CCER The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. 427/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Figure 160. Capture/compare channel 1 main circuit APB Bus read CCR1H S read CCR1L R CC1S[1] CC1S[0] IC1PS CC1E CC1G TIM1_EGR MCU-peripheral interface high (if 16-bit) low read_in_progress 8 8 write_in_progress Capture/compare preload register S write CCR1H R write CCR1L input mode capture_transfer compare_transfer output mode Capture/compare shadow register capture comparator CC1S[1] CC1S[0] OC1PE OC1PE UEV (from time TIM1_CCMR1 base unit) Counter CNT>CCR1 CNT=CCR1 Figure 161. Output stage of capture/compare channel (channel 1) 4OTHEMASTERMODE CONTROLLER  /UTPUT /# ENABLE  CIRCUIT #.4##2 /UTPUTMODE /#?2%& #.4##2 CONTROLLER ##0 4)-X?##%2 16.3.5 /#-;= 4)-X?##-2 ##% 4)-X?##%2 AI The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be DocID13902 Rev 15 428/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 Note: 16.3.6 cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’, the channel is configured in input mode and the TIMx_CCR1 register becomes readonly. 2. Program the input filter duration you need with respect to the signal you connect to the timer (by programming the ICxF bits in the TIMx_CCMRx register if the input is one of the TIx inputs). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the TIMx_CCMR1 register. 3. Select the edge of the active transition on the TI1 channel by programming CC1P and CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case). 4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). 5. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register. When an input capture occurs: • The TIMx_CCR1 register gets the value of the counter on the active transition. • CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. • An interrupt is generated depending on the CC1IE bit. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. IC interrupt requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. PWM input mode (only for TIM9/12) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): 429/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) 1. Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). 2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). 3. Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1 register (TI1 selected). 4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the CC2P and CC2NP bits to ‘11’ (active on falling edge). 5. Select the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register (TI1FP1 selected). 6. Configure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the TIMx_SMCR register. 7. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. Figure 162. PWM input mode timing TI1 TIMx_CNT 0004 0000 0001 0002 0003 0004 0000 TIMx_CCR1 0004 TIMx_CCR2 0002 16.3.7 IC1 capture IC2 capture reset counter IC2 capture pulse width measurement IC1 capture period measurement ai15413 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. Forced output mode In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write ‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=’0’ (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in the output compare mode section below. DocID13902 Rev 15 430/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: 1. Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set active (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on match. 2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). 3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. Select the output mode. For example: – Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx – Write OCxPE = ‘0’ to disable preload register – Write CCxP = ‘0’ to select active high polarity – Write CCxE = ‘1’ to enable the output 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 163. 431/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Figure 163. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 TIM1_CCR1 003A 003B 003A oc1ref=OC1 B200 B201 B201 Match detected on CCR1 Interrupt generated if enabled 16.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. The OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CNT ≤ TIMx_CCRx. The timer is able to generate PWM in edge-aligned mode only since the counter is upcounting. PWM edge-aligned mode In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 164 shows some edgealigned PWM waveforms in an example where TIMx_ARR=8. DocID13902 Rev 15 432/1128 460 General-purpose timers (TIM9 to TIM14) Figure 164. Edge-aligned PWM waveforms (ARR=8) RM0008 Counter register 0 1 2 3 4 5 6 7 8 0 1 OCXREF CCRx=4 CCxIF OCXREF CCRx=8 CCxIF OCXREF CCRx>8 CCxIF OCXREF CCRx=0 CCxIF 16.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be as follows: CNT < CCRx≤ ARR (in particular, 0 < CCRx) Figure 165. Example of one pulse mode. TI2 OC1REF OC1 Counter TIM1_ARR TIM1_CCR1 0 tDELAY tPULSE t 433/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Use TI2FP2 as trigger 1: 1. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. 2. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER register. 3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register. 4. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The tDELAY is defined by the value written in the TIMx_CCR1 register. • The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1). • Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=’111’ in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. 16.3.11 TIM9/12 external trigger synchronization The TIM9/12 timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. DocID13902 Rev 15 434/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: 1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = ‘01’ in the TIMx_CCMR1 register. Program CC1P and CC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and detect rising edges only). 2. Configure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register. 3. Start the counter by writing CEN=’1’ in the TIMx_CR1 register. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if enabled (depending on the TIE bit in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 166. Control circuit in reset mode TI1 UG Counter clock = ck_cnt = ck_psc Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03 TIF Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: 1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=’01’ in TIMx_CCMR1 register. Program CC1P=’1’ and CC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register. Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register. 3. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=’0’, whatever is the trigger input level). 435/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 167. Control circuit in gated mode TI1 cnt_en Counter clock = ck_cnt = ck_psc Counter register 30 31 32 33 34 TIF 35 36 37 38 Write TIF=0 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: 1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=’01’ in TIMx_CCMR1 register. Program CC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register. Select TI2 as the input source by writing TS=’110’ in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 168. Control circuit in trigger mode TI2 cnt_en Counter clock = ck_cnt = ck_psc Counter register 34 TIF 35 36 37 38 DocID13902 Rev 15 436/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.3.12 Timer synchronization (TIM9/12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 15.3.15: Timer synchronization on page 391 for details. 16.3.13 Debug mode When the microcontroller enters debug mode (Cortex®-M3 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. 16.4 TIM9 and TIM12 registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 16.4.1 TIM9/12 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 Reserved CKD[1:0] rw rw ARPE rw Reserved 3 OPM rw 2 URS rw 1 UDIS rw 0 CEN rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped on the update event 1: Counter stops counting on the next update event (clearing the CEN bit). 437/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow – Setting the UG bit 1: Only counter overflow generates an update interrupt if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable update event (UEV) generation. 0: UEV enabled. An UEV is generated by one of the following events: – Counter overflow – Setting the UG bit Buffered registers are then loaded with their preload values. 1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled CEN is cleared automatically in one-pulse mode, when an update event occurs. DocID13902 Rev 15 438/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.4.2 9/12TIM9/12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TS[2:0] rw rw rw Res. SMS[2:0] rw rw rw Bits 6:4 TS: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2) 011: Internal Trigger 3 (ITR3) 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: Reserved. See Table 89: TIMx internal trigger connection on page 439 for more details on the meaning of ITRx for each timer. Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. Bits 2:0 SMS: Slave mode selection When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input control register and Control register descriptions. 000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock 001: Reserved 010: Reserved 011: Reserved 100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers 101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops are both controlled 110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled 111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the Gated mode checks the level of the trigger signal. Slave TIM TIM2 TIM3 Table 89. TIMx internal trigger connection ITR0 (TS =’ 000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ’011’) TIM1 TIM8 TIM3 TIM4 TIM1 TIM2 TIM5 TIM4 439/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Slave TIM TIM4 TIM5 TIM9 TIM12 Table 89. TIMx internal trigger connection ITR0 (TS =’ 000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ’011’) TIM1 TIM2 TIM3 TIM8 TIM2 TIM3 TIM4 TIM8 TIM2 TIM3 TIM10 TIM11 TIM4 TIM5 TIM13 TIM14 16.4.3 TIM9/12 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 Reserved TIE Res rw 3 2 1 0 CC2IE CC1IE UIE rw rw rw Bits 15:7 Reserved, must be kept at reset value. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bit 5:3 Reserved, must be kept at reset value. Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. DocID13902 Rev 15 440/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.4.4 TIM9/12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Reserved CC2OF CC1OF rc_w0 rc_w0 Reserved 6 TIF rc_w0 5 4 3 Reserved 2 CC2IF rc_w0 1 CC1IF rc_w0 0 UIF rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8:7 Reserved, must be kept at reset value. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bits 5:3 Reserved, must be kept at reset value. 441/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity). Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow and if UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. 16.4.5 TIM9/12 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 Reserved TG Reserved w 2 1 0 CC2G CC1G UG w w w Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled Bits 5:3 Reserved, must be kept at reset value. DocID13902 Rev 15 442/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled. If channel CC1 is configured as input: The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared. 443/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) 16.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) 15 OC2CE rw Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes. For a given bit, OCxx describes its function when the channel is configured in output mode, ICxx describes its function when the channel is configured in input mode. So you must take care that the same bit can have different meanings for the input stage and the output stage. 14 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2PE OC2FE IC2PSC[1:0] rw rw 9 8 CC2S[1:0] rw rw 7 OC1CE rw 6 5 4 OC1M[2:0] IC1F[3:0] rw rw rw 3 2 OC1PE OC1FE IC1PSC[1:0] rw rw 1 0 CC1S[1:0] rw rw Output compare mode Bit 15 OC2CE: Output compare 2 clear enable Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bit 7 OC1CE: Output compare 1 clear enable OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input DocID13902 Rev 15 444/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 001: Set channel 1 to active level on match. The OC1REF signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1 100: Force inactive level - OC1REF is forced low 101: Force active level - OC1REF is forced high 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNTTIMx_CCR1, else it is active (OC1REF=’1’) 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNTTIMx_CCR1 else it is inactive. Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in the TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles 1: An active edge on the trigger input acts like a compare match on the CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 445/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bits 7:4 IC1F: Input capture 1 filter This bitfield defines the frequency used to sample the TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6 0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8 0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5 0011: fSAMPLING=fCK_INT, N=8 1011: fSAMPLING=fDTS/16, N=6 0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8 0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5 0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6 0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). DocID13902 Rev 15 446/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.4.7 TIM9/12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 3 2 1 0 CC2NP Res. rw CC2P CC2E CC1NP Res. rw rw rw CC1P CC1E rw rw Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bits 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity CC1 channel configured as output: CC1NP must be kept cleared CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity (refer to CC1P description). Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low. CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. Note: 11: noninverted/both edges Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. Bit 0 CC1E: Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active. 1: On - OC1 signal is output on the corresponding output pin. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. 447/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) CCxE bit 0 1 Table 90. Output control bit for standard OCx channels OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers. 16.4.8 TIM9/12 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 16.4.9 TIM9/12 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. 16.4.10 TIM9/12 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded into the actual auto-reload register. Refer to the Section 16.3.1: Time-base unit on page 421 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID13902 Rev 15 448/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit). Else the preload value is copied into the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signaled on the OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 16.4.12 TIM9/12 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR2[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (OC2PE bit). Else the preload value is copied into the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signalled on the OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 16.4.13 TIM9/12 register map TIM9/12 registers are mapped as 16-bit addressable registers as described below: 449/1128 DocID13902 Rev 15 RM0008 Offset Register 0x00 0x08 0x0C TIMx_CR1 Reset value TIMx_SMCR Reset value TIMx_DIER Reset value 0x10 TIMx_SR Reset value 0x14 0x18 0x1C TIMx_EGR Reset value TIMx_CCMR1 Output Compare mode Reset value TIMx_CCMR1 Input Capture mode Reset value 0x20 0x24 0x28 0x2C 0x30 TIMx_CCER Reset value TIMx_CNT Reset value TIMx_PSC Reset value TIMx_ARR Reset value 0x34 TIMx_CCR1 Reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ARPE 7 6 5 4 OPM 3 URS 2 UDIS 1 CEN 0 General-purpose timers (TIM9 to TIM14) Table 91. TIM9/12 register map and reset values CC2IE CC1IE UIE CC2IF CC1IF UIF CC2G CC1G UG Reserved Reserved CKD [1:0] Reserved 000 0000 Reserved TS[2:0] SMS[2:0] 000 000 TIE Reserved Reserved 0 000 TIF CC2OF CC1OF Reserved Reserved 00 Reserved 0 000 TG Reserved Reserved Reserved Reserved Reserved 0 000 OC2PE OC2FE Reserved OC1PE OC1FE OC2M [2:0] CC2S [1:0] OC1M [2:0] CC1 S [1:0] 00 0000 0 00 00000 IC2F[3:0] IC2 PSC [1:0] CC2S [1:0] IC1F[3:0] IC1 PSC [1:0] CC1 S [1:0] 000 0000 000 0 0 0000 Reserved Reserved Reserved Reserved 0 000 00 CNT[15:0] 000 0000 000 0 0 0000 PSC[15:0] 000 0000 000 0 0 0000 ARR[15:0] 000 0000 000 0 0 0000 Reserved Reserved CCR1[15:0] 000 0000 000 0 0 0000 CC2NP Reserved CC2P CC2E CC1NP Reserved CC1P CC1E DocID13902 Rev 15 450/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Offset Table 91. TIM9/12 register map and reset values (continued) Register 0x38 0x3C to 0x4C TIMx_CCR2 Reset value Reserved CCR2[15:0] 000 0000 000 0 0 0000 Reserved Refer to Table 3 on page 51 for the register boundary addresses. 451/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) 16.5 TIM10/11/13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 16.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 Reserved CKD[1:0] rw rw ARPE rw 5 4 Reserved 3 2 1 0 URS UDIS CEN rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:3 Reserved, must be kept at reset value. Bit 2 URS: Update request source This bit is set and cleared by software to select the update interrupt (UEV) sources. 0: Any of the following events generate an UEV if enabled: – Counter overflow – Setting the UG bit 1: Only counter overflow generates an UEV if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable update interrupt (UEV) event generation. 0: UEV enabled. An UEV is generated by one of the following events: – Counter overflow – Setting the UG bit. Buffered registers are then loaded with their preload values. 1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled DocID13902 Rev 15 452/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.5.2 TIM10/11/13/14 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CC1OF rc_w0 Reserved CC1IF UIF rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8:2 Reserved, must be kept at reset value. Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity). Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow and if UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. 16.5.3 TIM10/11/13/14 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 Reserved 2 1 0 CC1G UG w w 453/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared. 16.5.4 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 15 14 13 12 11 10 9 Reserved Reserved 8 7 6 5 4 3 2 1 0 OC1M[2:0] IC1F[3:0] OC1PE OC1FE IC1PSC[1:0] CC1S[1:0] rw rw rw rw rw rw rw rw DocID13902 Rev 15 454/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived. OC1REF is active high whereas OC1 active level depends on CC1P bit. 000: Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive. 111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active. Note: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison changes or when the output compare mode switches from frozen to PWM mode. Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: The PWM mode can be used without validating the preload register only in one pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 455/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS1000: fSAMPLING=fDTS/8, N=6 0001: fSAMPLING=fCK_INT, N=21001: fSAMPLING=fDTS/8, N=8 0010: fSAMPLING=fCK_INT, N=41010: fSAMPLING=fDTS/16, N=5 0011: fSAMPLING=fCK_INT, N=81011: fSAMPLING=fDTS/16, N=6 0100: fSAMPLING=fDTS/2, N=61100: fSAMPLING=fDTS/16, N=8 0101: fSAMPLING=fDTS/2, N=81101: fSAMPLING=fDTS/32, N=5 0110: fSAMPLING=fDTS/4, N=61110: fSAMPLING=fDTS/32, N=6 0111: fSAMPLING=fDTS/4, N=81111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). DocID13902 Rev 15 456/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.5.5 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 Reserved 3 CC1NP rw 2 Res. 1 CC1P rw 0 CC1E rw Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description). Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: The CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TI1FP1 rising edge (capture mode), TI1FP1 is not inverted. 01: inverted/falling edge Circuit is sensitive to TI1FP1 falling edge (capture mode), TI1FP1 is inverted. 10: reserved, do not use this configuration. 11: noninverted/both edges Circuit is sensitive to both TI1FP1 rising and falling edges (capture mode), TI1FP1 is not inverted. Bit 0 CC1E: Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active 1: On - OC1 signal is output on the corresponding output pin CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled CCxE bit 0 1 Table 92. Output control bit for standard OCx channels OCx output state Output Disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The state of the external I/O pins connected to the standard OCx channels depends on the OCx channel state and the GPIO registers. 457/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) 16.5.6 TIM10/11/13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 16.5.7 TIM10/11/13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. 16.5.8 TIM10/11/13/14 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to Section 16.3.1: Time-base unit on page 421 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID13902 Rev 15 458/1128 460 General-purpose timers (TIM9 to TIM14) RM0008 16.5.9 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 16.5.10 TIM10/11/13/14 register map TIMx registers are mapped as 16-bit addressable registers as described in the tables below: Offset Register Table 93. TIM10/11/13/14 register map and reset values 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 ARPE 7 6 5 4 3 URS 2 UDIS 1 CEN 0 0x00 0x08 0x0C TIMx_CR1 Reset value TIMx_SMCR Reset value TIMx_DIER Reset value Reserved Reserved Reserved CKD [1:0] 000 Reserved 00 0 00 CC1IE UIE CC1IF UIF CC1OF 0x10 0x14 TIMx_SR Reset value TIMx_EGR Reset value Reserved Reserved Reserved 0 00 00 CC1G UG 459/1128 DocID13902 Rev 15 RM0008 General-purpose timers (TIM9 to TIM14) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 OC1PE 3 OC1FE 2 1 0 CC1NP Reserved CC1P CC1E Offset Table 93. TIM10/11/13/14 register map and reset values (continued) Register 0x18 0x1C TIMx_CCMR1 Output compare mode Reset value TIMx_CCMR1 Input capture mode Reset value Reserved Reserved Reserved OC1M [2:0] CC1S [1:0] 00000 0 0 IC1F[3:0] IC1 PSC [1:0] CC1S [1:0] 000000 0 0 0x20 0x24 0x28 0x2C 0x30 TIMx_CCER Reset value TIMx_CNT Reset value TIMx_PSC Reset value TIMx_ARR Reset value Reserved Reserved Reserved Reserved 0 00 CNT[15:0] 000 00000000000 0 0 PSC[15:0] 000 00000000000 0 0 ARR[15:0] 000 00000000000 0 0 Reserved 0x34 0x38 to 0x4C TIMx_CCR1 Reset value Reserved CCR1[15:0] 000 00000000000 0 0 Reserved Refer to Table 3 on page 51 for the register boundary addresses. DocID13902 Rev 15 460/1128 460 Basic timers (TIM6&TIM7) 17 Basic timers (TIM6&TIM7) RM0008 17.1 17.2 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to high-density and XL-density STM32F101xx and STM32F103xx devices, and to connectivity line devices only. TIM6&TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs. The timers are completely independent, and do not share any resources. TIM6&TIM7 main features Basic timer (TIM6&TIM7) features include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536 • Synchronization circuit to trigger the DAC • Interrupt/DMA generation on the update event: counter overflow 461/1128 DocID13902 Rev 15 RM0008 Basic timers (TIM6&TIM7) Figure 169. Basic timer block diagram Internal clock (CK_INT) TIMxCLK from RCC Trigger TRGO to DAC controller Controller Reset, Enable, Count, U Auto-reload Register UI Stop, Clear or up U CK_PSC PSC Prescaler CK_CNT ± CNT COUNTER Flag Preload registers transferred to active registers on U event according to control bit event interrupt & DMA output ai14749b 17.3 17.3.1 TIM6&TIM7 functional description Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: • Counter Register (TIMx_CNT) • Prescaler Register (TIMx_PSC) • Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set. Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. DocID13902 Rev 15 462/1128 472 Basic timers (TIM6&TIM7) RM0008 Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 170 and Figure 171 give some examples of the counter behavior when the prescaler ratio is changed on the fly. Figure 170. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 02 03 Update event (UEV) Prescaler control register 0 1 Write a new value in TIMx_PSC Prescaler buffer 0 1 Prescaler counter 0 01 01 01 01 Figure 171. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F7 F8 F9 FA FB FC 00 01 Update event (UEV) Prescaler control register 0 3 Write a new value in TIMx_PSC Prescaler buffer 0 3 Prescaler counter 0 01 23 01 23 463/1128 DocID13902 Rev 15 RM0008 Basic timers (TIM6&TIM7) 17.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent). When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit): • The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register) • The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36. Figure 172. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Update interrupt flag (UIF) DocID13902 Rev 15 464/1128 472 Basic timers (TIM6&TIM7) RM0008 Figure 173. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0034 0035 0036 0000 0001 0002 0003 Update interrupt flag (UIF) Figure 174. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT Counter register Counter overflow Update event (UEV) 0035 0036 0000 0001 Update interrupt flag (UIF) Figure 175. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register 1F 20 00 Counter overflow Update event (UEV) Update interrupt flag (UIF) 465/1128 DocID13902 Rev 15 RM0008 Basic timers (TIM6&TIM7) Figure 176. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register FF 36 Write a new value in TIMx_ARR Figure 177. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register F5 36 Auto-reload shadow register F5 36 17.3.3 Write a new value in TIMx_ARR Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 178 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. DocID13902 Rev 15 466/1128 472 Basic timers (TIM6&TIM7) RM0008 Figure 178. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN UG CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07 17.3.4 Debug mode When the microcontroller enters the debug mode (Cortex®-M3 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. 17.4 TIM6&TIM7 registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 17.4.1 TIM6&TIM7 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 Reserved 8 7 6 5 4 ARPE rw Reserved 3 OPM rw 2 URS rw 1 UDIS rw 0 CEN rw Bits 15:8 Reserved, must be kept at reset value. Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit). 467/1128 DocID13902 Rev 15 RM0008 Basic timers (TIM6&TIM7) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. DocID13902 Rev 15 468/1128 472 Basic timers (TIM6&TIM7) RM0008 17.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MMS[2:0] rw rw rw Reserved Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). 010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. Bits 3:0 Reserved, must be kept at reset value. 17.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Reserved UDE rw Reserved 1 0 UIE rw Bits 15:9 Reserved, must be kept at reset value. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bits 7:1 Reserved, must be kept at reset value. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. 469/1128 DocID13902 Rev 15 RM0008 Basic timers (TIM6&TIM7) 17.4.4 TIM6&TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UIF rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow or underflow and if UDIS = 0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 17.4.5 TIM6&TIM7 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UG Reserved w Bits 15:1 Reserved, must be kept at reset value. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). 17.4.6 TIM6&TIM7 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value DocID13902 Rev 15 470/1128 472 Basic timers (TIM6&TIM7) RM0008 17.4.7 TIM6&TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. 17.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 17.3.1: Time-base unit on page 462 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 471/1128 DocID13902 Rev 15 RM0008 Basic timers (TIM6&TIM7) CEN 0 UIE UIF 17.4.9 TIM6&TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Offset Register Table 94. TIM6&TIM7 register map and reset values 4 5 8 9 URS 2 UDIS 1 OPM 3 ARPE 7 6 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reserved 0x00 0x04 0x08 TIMx_CR1 Reset value TIMx_CR2 Reset value 0x0C 0x10 0x14 0x18 TIMx_DIER Reset value TIMx_SR Reset value TIMx_EGR Reset value 0x1C 0x20 0x24 0x28 0x2C TIMx_CNT Reset value TIMx_PSC Reset value TIMx_ARR Reset value Reserved Reserved Reserved 0 0000 Reserved MMS[2:0] 000 UDE Reserved Reserved 0 0 Reserved 0 Reserved Reserved Reserved Reserved 0 Reserved Reserved Reserved CNT[15:0] 0000000000000000 PSC[15:0] 0000000000000000 ARR[15:0] 0000000000000000 UG Refer to Table 3 on page 51 for the register boundary addresses. DocID13902 Rev 15 472/1128 472 Real-time clock (RTC) 18 Real-time clock (RTC) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 18.1 RTC introduction The real-time clock is an independent timer. The RTC provides a set of continuously running counters which can be used, with suitable software, to provide a clock-calendar function. The counter values can be written to set the current time/date of the system. The RTC core and clock configuration (RCC_BDCR register) are in the Backup domain, which means that RTC setting and time are kept after reset or wakeup from Standby mode. After reset, access to the Backup registers and RTC is disabled and the Backup domain (BKP) is protected against possible parasitic write access. To enable access to the Backup registers and the RTC, proceed as follows: • enable the power and backup interface clocks by setting the PWREN and BKPEN bits in the RCC_APB1ENR register • set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup registers and RTC. 473/1128 DocID13902 Rev 15 RM0008 Real-time clock (RTC) 18.2 RTC main features • Programmable prescaler: division factor up to 220 • 32-bit programmable counter for long-term measurement • Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least four times slower than the PCLK1 clock) • The RTC clock source could be any of the following ones: – HSE clock divided by 128 – LSE oscillator clock – LSI oscillator clock (refer to Section 7.2.8: RTC clock for details) • Two separate reset types: – The APB1 interface is reset by system reset – The RTC Core (Prescaler, Alarm, Counter and Divider) is reset only by a Backup domain reset (see Section 7.1.3: Backup domain reset on page 92). • Three dedicated maskable interrupt lines: – Alarm interrupt, for generating a software programmable alarm interrupt. – Seconds interrupt, for generating a periodic interrupt signal with a programmable period length (up to 1 second). – Overflow interrupt, to detect when the internal programmable counter rolls over to zero. DocID13902 Rev 15 474/1128 484 Real-time clock (RTC) RM0008 18.3 18.3.1 RTC functional description Overview The RTC consists of two main units (see Figure 179 on page 475). The first one (APB1 Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit registers accessible from the APB1 bus in read or write mode (for more information refer to Section 18.4: RTC registers on page 478). The APB1 interface is clocked by the APB1 bus clock in order to interface with the APB1 bus. The other unit (RTC Core) consists of a chain of programmable counters made of two main blocks. The first block is the RTC prescaler block, which generates the RTC time base TR_CLK that can be programmed to have a period of up to 1 second. It includes a 20-bit programmable divider (RTC Prescaler). Every TR_CLK period, the RTC generates an interrupt (Second Interrupt) if it is enabled in the RTC_CR register. The second block is a 32-bit programmable counter that can be initialized to the current system time. The system time is incremented at the TR_CLK rate and compared with a programmable date (stored in the RTC_ALR register) in order to generate an alarm interrupt, if enabled in the RTC_CR control register. Figure 179. RTC simplified block diagram PCLK1 APB1 bus APB1 interface not powered in Standby RTCCLK Backup domain RTC_PRL Reload RTC_DIV TR_CLK rising edge RTC prescaler 32-bit programmable counter RTC_CNT RTC_Second RTC_Overflow RTC_Alarm = RTC_ALR powered in Standby powered in Standby WKUP pin RTC_Alarm WKP_STDBY RTC_CR SECF SECIE OWF OWIE ALRF ALRIE not powered in Standby NVIC interrupt controller not powered in Standby exit Standby mode powered in Standby ai14969b 475/1128 DocID13902 Rev 15 RM0008 Real-time clock (RTC) 18.3.2 18.3.3 18.3.4 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset. Refer to Section 7.1.3 on page 92. Reading RTC registers The RTC core is completely independent from the RTC APB1 interface. Software accesses the RTC prescaler, counter and alarm values through the APB1 interface but the associated readable registers are internally updated at each rising edge of the RTC clock resynchronized by the RTC APB1 clock. This is also true for the RTC flags. This means that the first read to the RTC APB1 registers may be corrupted (generally read as 0) if the APB1 interface has previously been disabled and the read occurs immediately after the APB1 interface is enabled but before the first internal update of the registers. This can occur if: • A system reset or power reset has occurred • The MCU has just woken up from Standby mode (see Section 5.3: Low-power modes) • The MCU has just woken up from Stop mode (see Section 5.3: Low-power modes) In all the above cases, the RTC core has been kept running while the APB1 interface was disabled (reset, not clocked or unpowered). Consequently when reading the RTC registers, after having disabled the RTC APB1 interface, the software must first wait for the RSF bit (Register Synchronized Flag) in the RTC_CRL register to be set by hardware. Note that the RTC APB1 interface is not affected by WFI and WFE low-power modes. Configuring RTC registers To write in the RTC_PRL, RTC_CNT, RTC_ALR registers, the peripheral must enter Configuration Mode. This is done by setting the CNF bit in the RTC_CRL register. In addition, writing to any RTC register is only enabled if the previous write operation is finished. To enable the software to detect this situation, the RTOFF status bit is provided in the RTC_CR register to indicate that an update of the registers is in progress. A new value can be written to the RTC registers only when the RTOFF status bit value is ’1’. Configuration procedure: 1. Poll RTOFF, wait until its value goes to ‘1’ 2. Set the CNF bit to enter configuration mode 3. Write to one or more RTC registers 4. Clear the CNF bit to exit configuration mode 5. Poll RTOFF, wait until its value goes to ‘1’ to check the end of the write operation. The write operation only executes when the CNF bit is cleared; it takes at least three RTCCLK cycles to complete. DocID13902 Rev 15 476/1128 484 Real-time clock (RTC) RM0008 18.3.5 RTC flag assertion The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update of the RTC Counter. The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0000. The RTC_Alarm and RTC Alarm flag (ALRF) (see Figure 180) are asserted on the last RTC Core clock cycle before the counter reaches the RTC Alarm value stored in the Alarm register increased by one (RTC_ALR + 1). The write operation in the RTC Alarm and RTC Second flag must be synchronized by using one of the following sequences: • Use the RTC Alarm interrupt and inside the RTC interrupt routine, the RTC Alarm and/or RTC Counter registers are updated. • Wait for SECF bit to be set in the RTC Control register. Update the RTC Alarm and/or the RTC Counter register. Figure 180. RTC second and alarm waveform example with PR=0003, ALARM=00004 RTCCLK RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 RTC_Second RTC_CNT 0000 0001 0002 0003 0004 0005 RTC_ALARM ALRF (not powered in Standby) 1 RTCCLK can be cleared by software Figure 181. RTC Overflow waveform example with PR=0003 RTCCLK RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 RTC_Second RTC_CNT FFFFFFFB FFFFFFFC FFFFFFFD FFFFFFFE FFFFFFFF 0000 RTC_Overflow OWF (not powered in Standby) 1 RTCCLK can be cleared by software 477/1128 DocID13902 Rev 15 RM0008 Real-time clock (RTC) 18.4 18.4.1 RTC registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). RTC control register high (RTC_CRH) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OWIE ALRIE SECIE rw rw rw Bits 15:3 Reserved, forced by hardware to 0. Bit 2 OWIE: Overflow interrupt enable 0: Overflow interrupt is masked. 1: Overflow interrupt is enabled. Bit 1 ALRIE: Alarm interrupt enable 0: Alarm interrupt is masked. 1: Alarm interrupt is enabled. Bit 0 SECIE: Second interrupt enable 0: Second interrupt is masked. 1: Second interrupt is enabled. These bits are used to mask interrupt requests. Note that at reset all interrupts are disabled, so it is possible to write to the RTC registers to ensure that no interrupt requests are pending after initialization. It is not possible to write to the RTC_CRH register when the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 18.3.4 on page 476). The RTC functions are controlled by this control register. Some bits must be written using a specific configuration procedure (see Configuration procedure:). DocID13902 Rev 15 478/1128 484 Real-time clock (RTC) RM0008 18.4.2 RTC control register low (RTC_CRL) Address offset: 0x04 Reset value: 0x0020 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RTOFF r CNF rw RSF OWF ALRF SECF rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:6 Reserved, forced by hardware to 0. Bit 5 RTOFF: RTC operation OFF With this bit the RTC reports the status of the last write operation performed on its registers, indicating if it has been completed or not. If its value is ‘0’ then it is not possible to write to any of the RTC registers. This bit is read only. 0: Last write operation on RTC registers is still ongoing. 1: Last write operation on RTC registers terminated. Bit 4 CNF: Configuration flag This bit must be set by software to enter in configuration mode so as to allow new values to be written in the RTC_CNT, RTC_ALR or RTC_PRL registers. The write operation is only executed when the CNF bit is reset by software after has been set. 0: Exit configuration mode (start update of RTC registers). 1: Enter configuration mode. Bit 3 RSF: Registers synchronized flag This bit is set by hardware at each time the RTC_CNT and RTC_DIV registers are updated and cleared by software. Before any read operation after an APB1 reset or an APB1 clock stop, this bit must be cleared by software, and the user application must wait until it is set to be sure that the RTC_CNT, RTC_ALR or RTC_PRL registers are synchronized. 0: Registers not yet synchronized. 1: Registers synchronized. Bit 2 OWF: Overflow flag This bit is set by hardware when the 32-bit programmable counter overflows. An interrupt is generated if OWIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect. 0: Overflow not detected 1: 32-bit programmable counter overflow occurred. Bit 1 ALRF: Alarm flag This bit is set by hardware when the 32-bit programmable counter reaches the threshold set in the RTC_ALR register. An interrupt is generated if ALRIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect. 0: Alarm not detected 1: Alarm detected Bit 0 SECF: Second flag This bit is set by hardware when the 32-bit programmable prescaler overflows, thus incrementing the RTC counter. Hence this flag provides a periodic signal with a period corresponding to the resolution programmed for the RTC counter (usually one second). An interrupt is generated if SECIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect. 0: Second flag condition not met. 1: Second flag condition met. 479/1128 DocID13902 Rev 15 RM0008 Real-time clock (RTC) Note: 18.4.3 The functions of the RTC are controlled by this control register. It is not possible to write to the RTC_CR register while the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 18.3.4 on page 476). Any flag remains pending until the appropriate RTC_CR request bit is reset by software, indicating that the interrupt request has been granted. At reset the interrupts are disabled, no interrupt requests are pending and it is possible to write to the RTC registers. The OWF, ALRF, SECF and RSF bits are not updated when the APB1 clock is not running. The OWF, ALRF, SECF and RSF bits can only be set by hardware and only cleared by software. If ALRF = 1 and ALRIE = 1, the RTC global interrupt is enabled. If EXTI Line 17 is also enabled through the EXTI Controller, both the RTC global interrupt and the RTC Alarm interrupt are enabled. If ALRF = 1, the RTC Alarm interrupt is enabled if EXTI Line 17 is enabled through the EXTI Controller in interrupt mode. When the EXTI Line 17 is enabled in event mode, a pulse is generated on this line (no RTC Alarm interrupt generation). RTC prescaler load register (RTC_PRLH / RTC_PRLL) The Prescaler Load registers keep the period counting value of the RTC prescaler. They are write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. RTC prescaler load register high (RTC_PRLH) Address offset: 0x08 Write only (see Section 18.3.4 on page 476) Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PRL[19:16] w w w w Bits 15:4 Reserved, forced by hardware to 0. Bits 3:0 PRL[19:16]: RTC prescaler reload value high These bits are used to define the counter clock frequency according to the following formula: fTR_CLK = fRTCCLK/(PRL[19:0]+1) DocID13902 Rev 15 480/1128 484 Real-time clock (RTC) RM0008 RTC prescaler load register low (RTC_PRLL) Address offset: 0x0C Write only (see Section 18.3.4 on page 476) Reset value: 0x8000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRL[15:0] w w w w w w w w w w w w w w w w Bits 15:0 PRL[15:0]: RTC prescaler reload value low These bits are used to define the counter clock frequency according to the following formula: fTR_CLK = fRTCCLK/(PRL[19:0]+1) Caution: The zero value is not recommended. RTC interrupts and flags cannot be asserted correctly. Note: 18.4.4 If the input clock frequency (fRTCCLK) is 32.768 kHz, write 7FFFh in this register to get a signal period of 1 second. RTC prescaler divider register (RTC_DIVH / RTC_DIVL) During each period of TR_CLK, the counter inside the RTC prescaler is reloaded with the value stored in the RTC_PRL register. To get an accurate time measurement it is possible to read the current value of the prescaler counter, stored in the RTC_DIV register, without stopping it. This register is read-only and it is reloaded by hardware after any change in the RTC_PRL or RTC_CNT registers. RTC prescaler divider register high (RTC_DIVH) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RTC_DIV[19:16] r r r r Bits 15:4 Reserved Bits 3:0 RTC_DIV[19:16]: RTC clock divider high RTC prescaler divider register low (RTC_DIVL) Address offset: 0x14 Reset value: 0x8000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_DIV[15:0] r r r r r r r r r r r r r r r r Bits 15:0 RTC_DIV[15:0]: RTC clock divider low 481/1128 DocID13902 Rev 15 RM0008 Real-time clock (RTC) 18.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the TR_CLK time reference, generated by the prescaler. RTC_CNT registers keep the counting value of this counter. They are write-protected by bit RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. A write operation on the upper (RTC_CNTH) or lower (RTC_CNTL) registers directly loads the corresponding programmable counter and reloads the RTC Prescaler. When reading, the current value in the counter (system date) is returned. RTC counter register high (RTC_CNTH) Address offset: 0x18 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_CNT[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 RTC_CNT[31:16]: RTC counter high Reading the RTC_CNTH register, the current value of the high part of the RTC Counter register is returned. To write to this register it is necessary to enter configuration mode (see Section 18.3.4: Configuring RTC registers on page 476). RTC counter register low (RTC_CNTL) Address offset: 0x1C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 RTC_CNT[15:0]: RTC counter low Reading the RTC_CNTL register, the current value of the lower part of the RTC Counter register is returned. To write to this register it is necessary to enter configuration mode (see Section 18.3.4: Configuring RTC registers on page 476). DocID13902 Rev 15 482/1128 484 Real-time clock (RTC) RM0008 18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) When the programmable counter reaches the 32-bit value stored in the RTC_ALR register, an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. RTC alarm register high (RTC_ALRH) Address offset: 0x20 Write only (see Section 18.3.4 on page 476) Reset value: 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_ALR[31:16] w w w w w w w w w w w w w w w w Bits 15:0 RTC_ALR[31:16]: RTC alarm high The high part of the alarm time is written by software in this register. To write to this register it is necessary to enter configuration mode (see Section 18.3.4: Configuring RTC registers on page 476). RTC alarm register low (RTC_ALRL) Address offset: 0x24 Write only (see Section 18.3.4 on page 476) Reset value: 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_ALR[15:0] w w w w w w w w w w w w w w w w Bits 15:0 RTC_ALR[15:0]: RTC alarm low The low part of the alarm time is written by software in this register. To write to this register it is necessary to enter configuration mode (see Section 18.3.4: Configuring RTC registers on page 476). 483/1128 DocID13902 Rev 15 0 RM0008 Real-time clock (RTC) 18.4.7 RTC register map RTC registers are mapped as 16-bit addressable registers as described in the table below: Table 95. RTC register map and reset values Offset Register 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SECIE ALRIE OWIE 0x00 RTC_CRH Reset value 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 RTC_CRL Reset value RTC_PRLH Reset value RTC_PRLL Reset value RTC_DIVH Reset value RTC_DIVL Reset value RTC_CNTH Reset value RTC_CNTL Reset value RTC_ALRH Reset value RTC_ALRL Reset value Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 000 SECF ALRF OWF RSF CNF RTOFF Reserved 100000 Reserved PRL[19:16] 0000 PRL[15:0] 1000000000000000 DIV[31:16] 0000000000000000 DIV[15:0] 1000000000000000 CNT[13:16] 0000000000000000 CNT[15:0] 0000000000000000 ALR[31:16] 1111111111111111 ALR[15:0] 1111111111111111 Refer to Table 3 on page 51for the register boundary addresses. DocID13902 Rev 15 484/1128 484 Independent watchdog (IWDG) 19 Independent watchdog (IWDG) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 19.1 IWDG introduction The STM32F10xxx have two embedded watchdog peripherals which offer a combination of high safety level, timing accuracy and flexibility of use. Both watchdog peripherals (Independent and Window) serve to detect and resolve malfunctions due to software failure, and to trigger system reset or an interrupt (window watchdog only) when the counter reaches a given timeout value. The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. The window watchdog (WWDG) clock is prescaled from the APB1 clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior. The IWDG is best suited to applications which require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy constraints. The WWDG is best suited to applications which require the watchdog to react within an accurate timing window. For further information on the window watchdog, refer to Section 20 on page 491. 19.2 19.3 IWDG main features • Free-running downcounter • clocked from an independent RC oscillator (can operate in Standby and Stop modes) • Reset (if watchdog activated) when the downcounter value of 0x000 is reached IWDG functional description Figure 182 shows the functional blocks of the independent watchdog module. When the independent watchdog is started by writing the value 0xCCCC in the Key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). 485/1128 DocID13902 Rev 15 RM0008 Independent watchdog (IWDG) 19.3.1 19.3.2 19.3.3 Whenever the key value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and will generate a reset unless the Key register is written by the software before the counter reaches end of count. Register access protection Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you must first write the code 0x5555 in the IWDG_KR register. A write access to this register with a different value will break the sequence and register access will be protected again. This implies that it is the case of the reload operation (writing 0xAAAA). A status register is available to indicate that an update of the prescaler or the down-counter reload value is on going. Debug mode When the microcontroller enters debug mode (Cortex®-M3 core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. Figure 182. Independent watchdog block diagram Note: #/2% 0RESCALERREGISTER )7$'?02 3TATUSREGISTER )7$'?32 2ELOADREGISTER )7$'?2,2 +EYREGISTER )7$'?+2 ,3)  BIT K(Z PRESCALER 6$$VOLTAGEDOMAIN  BITRELOADVALUE  BITDOWNCOUNTER )7$'RESET -36 The watchdog function is implemented in the VDD voltage domain that is still functional in Stop and Standby modes. Table 96. Min/max IWDG timeout period at 40 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= 0x000 Max timeout (ms) RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 /16 2 0.4 819.2 1638.4 /32 3 0.8 /64 4 1.6 3276.8 6553.6 DocID13902 Rev 15 486/1128 490 Independent watchdog (IWDG) RM0008 Table 96. Min/max IWDG timeout period at 40 kHz (LSI)(1) (continued) Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= 0x000 Max timeout (ms) RL[11:0]= 0xFFF /128 5 3.2 /256 6 (or 7) 6.4 13107.2 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy. For more details refer to LSI clock on page 96. 19.4 IWDG registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 19.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved KEY[15:0] wwwwwww w ww w w ww w w Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 KEY[15:0]: Key value (write only, read 0000h) These bits must be written by software at regular intervals with the key value AAAAh, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers (see Section 19.3.2) Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected) 487/1128 DocID13902 Rev 15 RM0008 Independent watchdog (IWDG) 19.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PR[2:0] rw rw rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected seeSection 19.3.2. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. 000: divider /4 001: divider /8 010: divider /16 011: divider /32 100: divider /64 101: divider /128 110: divider /256 111: divider /256 Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset. 19.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RL[11:0] rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits11:0 RL[11:0]: Watchdog counter reload value These bits are write access protected see Section 19.3.2. They are written by software to define the value to be loaded in the watchdog counter each time the value AAAAh is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to Table 96. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on this register. For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset. 19.4.4 Status register (IWDG_SR) Address offset: 0x0C DocID13902 Rev 15 488/1128 490 Independent watchdog (IWDG) RM0008 Reset value: 0x0000 0000 (not reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RVU PVU rr Bits 31:2 Reserved, must be kept at reset value. Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset. Bit 0 PVU: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset. Note: If several reload values or prescaler values are used by application, it is mandatory to wait until RVU bit is reset before changing the reload value and to wait until PVU bit is reset before changing the prescaler value. However, after updating the prescaler and/or the reload value it is not necessary to wait until RVU or PVU is reset before continuing code execution (even in case of low-power mode entry, the write operation is taken into account and will complete) 489/1128 DocID13902 Rev 15 RM0008 Independent watchdog (IWDG) 0 19.4.5 IWDG register map The following table gives the IWDG register map and reset values. Offset Register Table 97. IWDG register map and reset values 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x00 0x04 0x08 0x0C IWDG_KR Reset value IWDG_PR Reset value IWDG_RLR Reset value IWDG_SR Reset value Reserved Reserved KEY[15:0] 0000000000000000 Reserved PR[2:0] 000 RL[11:0] 111111111111 RVU Reserved 00 PVU Refer to Table 3 on page 51 for the register boundary addresses. DocID13902 Rev 15 490/1128 490 Window watchdog (WWDG) 20 Window watchdog (WWDG) RM0008 Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F10xxx family, unless otherwise specified. 20.1 20.2 WWDG introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window. WWDG main features • Programmable free-running downcounter • Conditional reset – Reset (if watchdog activated) when the downcounter value becomes less than 0x40 – Reset (if watchdog activated) if the downcounter is reloaded outside the window (see Figure 184) • Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when the downcounter is equal to 0x40. 20.3 WWDG functional description If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the 7-bit downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T6 becomes cleared), it initiates a reset. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. 491/1128 DocID13902 Rev 15 RM0008 Window watchdog (WWDG) RESET Figure 183. Watchdog block diagram Watchdog configuration register (WWDG_CFR) - W6 W5 W4 W3 W2 W1 W0 comparator = 1 when T6:0 > W6:0 CMP Write WWDG_CR Watchdog control register (WWDG_CR) WDGA T6 PCLK1 (from RCC clock controller) T5 T4 T3 T2 T1 T0 6-bit downcounter (CNT) WDG prescaler (WDGTB) Note: The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0: Enabling the watchdog The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. Controlling the downcounter This downcounter is free-running: It counts down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register (see Figure 184).The Configuration register (WWDG_CFR) contains the high limit of the window: To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x3F. Figure 184 describes the window watchdog process. The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). Advanced watchdog interrupt feature The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value 0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device. In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this DocID13902 Rev 15 492/1128 497 Window watchdog (WWDG) RM0008 Note: case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions. The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task, the WWDG reset will eventually be generated. 20.4 How to program the watchdog timeout You can use the formula in Figure 184 to calculate the WWDG timeout. Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 184. Window watchdog timing diagram 4;=#.4DOWNCOUNTER 7;= X& 2EFRESHNOTALLOWED 2EFRESHALLOWED 4BIT 4IME 2%3%4 The formula to calculate the timeout value is given by: tWWDG = tPCLK1 × 4096 × 2WDGTB × (t[5:0] + 1) ( ms ) where: tWWDG: WWDG timeout tPCLK1: APB1 clock period measured in ms Refer to the table below for the minimum and maximum values of the TWWDG. AIB 493/1128 DocID13902 Rev 15 RM0008 Window watchdog (WWDG) Prescaler 1 2 4 8 Table 98. Min-max timeout value @36 MHz (fPCLK1) WDGTB Min timeout value Max timeout value 0 113 µs 1 227 µs 2 455 µs 3 910 µs 7.28 ms 14.56 ms 29.12 ms 58.25 ms 20.5 Debug mode When the microcontroller enters debug mode (Cortex®-M3 core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. DocID13902 Rev 15 494/1128 497 Window watchdog (WWDG) RM0008 20.6 20.6.1 WWDG registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WDGA rs T[6:0] rw Bits 31:8 Reserved, must be kept at reset value. Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB) PCLK1 cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6 becomes cleared). 495/1128 DocID13902 Rev 15 RM0008 Window watchdog (WWDG) 20.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWI WDGTB[1:0] rs rw W[6:0] rw Bit 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. Bits 8:7 WDGTB[1:0]: Timer base The time base of the prescaler can be modified as follows: 00: CK Counter Clock (PCLK1 div 4096) div 1 01: CK Counter Clock (PCLK1 div 4096) div 2 10: CK Counter Clock (PCLK1 div 4096) div 4 11: CK Counter Clock (PCLK1 div 4096) div 8 Bits 6:0 W[6:0]: 7-bit window value These bits contain the window value to be compared to the downcounter. 20.6.3 Status register (WWDG_SR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF rc_w0 Bits 31:1 Reserved, must be kept at reset value. Bit 0 EWIF: Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0. A write of ‘1 has no effect. This bit is also set if the interrupt is not enabled. DocID13902 Rev 15 496/1128 497 Window watchdog (WWDG) RM0008 20.6.4 WWDG register map The following table gives the WWDG register map and reset values. Offset Register Table 99. WWDG register map and reset values 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 WDGA 7 6 5 4 3 2 1 0 0x00 WWDG_CR Reset value 0x04 WWDG_CFR Reset value 0x08 WWDG_SR Reset value Reserved Reserved Reserved EWI WDGTB1 WDGTB0 T[6:0] 01111111 W[6:0] 0001111111 0 EWIF Refer to Table 3 on page 51 for the register boundary addresses. 497/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) 21 Flexible static memory controller (FSMC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to high-density and XL-density devices only. 21.1 FSMC main features The FSMC block is able to interface with synchronous and asynchronous memories and 16bit PC memory cards. Its main purpose is to: • Translate the AHB transactions into the appropriate external device protocol • Meet the access timing requirements of the external devices All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique chip select. The FSMC performs only one access at a time to an external device. DocID13902 Rev 15 498/1128 555 Flexible static memory controller (FSMC) RM0008 The FSMC has the following main features: • Interfaces with static memory-mapped devices including: – Static random access memory (SRAM) – NOR Flash memory – PSRAM (4 memory banks) • Two banks of NAND Flash with ECC hardware that checks up to 8 Kbytes of data • 16-bit PC Card compatible devices • Supports burst mode access to synchronous devices (NOR Flash and PSRAM) • 8- or 16-bit wide databus • Independent chip select control for each memory bank • Independent configuration for each memory bank • Programmable timings to support a wide range of devices, in particular: – Programmable wait states (up to 15) – Programmable bus turnaround cycles (up to 15) – Programmable output enable and write enable delays (up to 15) – Independent read and write timings and protocol, so as to support the widest variety of memories and timings • Write enable and byte lane select outputs for use with PSRAM and SRAM devices • Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to external 16-bit or 8-bit devices • A Write FIFO, 2-word long , each word is 32 bits wide, only stores data and not the address. Therefore, this FIFO only buffers AHB write burst transactions. This makes it possible to write to slow memories and free the AHB quickly for other operations. Only one burst at a time is buffered: if a new AHB burst or single transaction occurs while an operation is in progress, the FIFO is drained. The FSMC will insert wait states until the current memory access is complete. • External asynchronous wait control The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, it is possible to change the settings at any time. 21.2 Block diagram The FSMC consists of four main blocks: • The AHB interface (including the FSMC configuration registers) • The NOR Flash/PSRAM controller • The NAND Flash/PC Card controller • The external device interface The block diagram is shown in Figure 185. 499/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) Figure 185. FSMC block diagram &3-#INTERRUPTTO.6)# &ROMCLOCK CONTROLLER (#,+ ./2032!MEMORY CONTROLLER !("BUS #ONFIGURATION REGISTERS .!.$0##ARD MEMORY CONTROLLER &3-#?.%;= &3-#?.,OR.!$6 &3-#?.",;= &3-#?#,+ ./2032!SIGNALS &3-#?!;= &3-#?$;= &3-#?./% &3-#?.7% &3-#?.7!)4 &3-#?.#%;= &3-#?).4;= &3-#?).42 &3-#?.#%? &3-#?.#%? &3-#?.)/2$ &3-#?.)/72 &3-#?.)/3 &3-#?.2%' &3-#?#$ 3HARED SIGNALS .!.$ SIGNALS 0##ARD SIGNALS AID 21.3 AHB interface The AHB slave interface enables internal CPUs and other bus master peripherals to access the external static memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The Chip Select is kept low or toggles between the consecutive accesses when perfoming 32-bit aligned or 32-bit unaligned accesses respectively. The FSMC generates an AHB error in the following conditions: • When reading or writing to an FSMC bank which is not enabled • When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the FSMC_BCRx register. • When reading or writing to the PC Card banks while the input pin FSMC_CD (Card Presence Detection) is low. DocID13902 Rev 15 500/1128 555 Flexible static memory controller (FSMC) RM0008 21.3.1 The effect of this AHB error depends on the AHB master which has attempted the R/W access: • If it is the Cortex®-M3 CPU, a hard fault interrupt is generated • If is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled. The AHB clock (HCLK) is the reference clock for the FSMC. Supported memories and transactions General transaction rules The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers. Therefore, some simple transaction rules must be followed: • AHB transaction size and memory data size are equal There is no issue in this case. • AHB transaction size is greater than the memory size In this case, the FSMC splits the AHB transaction into smaller consecutive memory accesses in order to meet the external data width. • AHB transaction size is smaller than the memory size Asynchronous transfers may or not be consistent depending on the type of external device. – Asynchronous accesses to devices that have the byte select feature (SRAM, ROM, PSRAM). a) FSMC allows write transactions accessing the right data through its byte lanes NBL[1:0] b) Read transactions are allowed. All memory bytes are read and the useless ones are discarded. The NBL[1:0] are kept low during read transactions. – Asynchronous accesses to devices that do not have the byte select feature (NOR and NAND Flash 16-bit). This situation occurs when a byte access is requested to a 16-bit wide Flash memory. Clearly, the device cannot be accessed in byte mode (only 16-bit words can be read from/written to the Flash memory) therefore: a) Write transactions are not allowed b) Read transactions are allowed. All memory bytes are read and the useless ones are discarded. The NBL[1:0] are set to 0 during read transactions. Configuration registers The FSMC can be configured using a register set. See Section 21.5.6, for a detailed description of the NOR Flash/PSRAM control registers. See Section 21.6.8, for a detailed description of the NAND Flash/PC Card registers. 501/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) 21.4 External device address mapping From the FSMC point of view, the external memory is divided into 4 fixed-size banks of 256 Mbytes each (Refer to Figure 186): • Bank 1 used to address up to 4 NOR Flash or PSRAM memory devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows: – Bank 1 - NOR/PSRAM 1 – Bank 1 - NOR/PSRAM 2 – Bank 1 - NOR/PSRAM 3 – Bank 1 - NOR/PSRAM 4 • Banks 2 and 3 used to address NAND Flash devices (1 device per bank) • Bank 4 used to address a PC Card device For each bank the type of memory to be used is user-defined in the Configuration register. Figure 186. FSMC memory banks A ddres s Banks Supported memory type 21.4.1 6000 0000h 6FF F FFF Fh Bank 1 4 × 64 MB NOR / PSRAM 7000 0000h 7FF F FFF Fh 8000 0000h 8FF F FFF Fh Bank 2 4 × 64 MB Bank 3 4 × 64 MB NAND Flash 9000 0000h 9FF F FFF Fh Bank 4 4 × 64 MB PC Card ai14719 NOR/PSRAM address mapping HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 100. Table 100. NOR/PSRAM bank selection HADDR[27:26](1) Selected bank 00 Bank 1 - NOR/PSRAM 1 01 Bank 1 - NOR/PSRAM 2 DocID13902 Rev 15 502/1128 555 Flexible static memory controller (FSMC) RM0008 21.4.2 Table 100. NOR/PSRAM bank selection (continued) HADDR[27:26](1) Selected bank 10 Bank 1 - NOR/PSRAM 3 11 Bank 1 - NOR/PSRAM 4 1. HADDR are internal AHB address lines that are translated to external memory. HADDR[25:0] contain the external memory address. Since HADDR is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the following table. Memory width(1) Table 101. External memory address Data address issued to the memory Maximum memory capacity (bits) 8-bit 16-bit HADDR[25:0] HADDR[25:1] >> 1 64 Mbytes x 8 = 512 Mbit 64 Mbytes/2 x 16 = 512 Mbit 1. In case of a 16-bit external memory width, the FSMC will internally use HADDR[25:1] to generate the address for external memory FSMC_A[24:0]. Whatever the external memory width (16-bit or 8-bit), FSMC_A[0] should be connected to external memory address A[0]. Wrap support for NOR Flash/PSRAM Wrap burst mode for synchronous memories is not supported. The memories must be configured in linear burst mode of undefined length. NAND/PC Card address mapping In this case, three banks are available, each of them divided into memory spaces as indicated in Table 102. Table 102. Memory mapping and timing registers Start address End address FSMC Bank Memory space Timing register 0x9C00 0000 0x9FFF FFFF I/O FSMC_PIO4 (0xB0) 0x9800 0000 0x9BFF FFFF Bank 4 - PC card Attribute FSMC_PATT4 (0xAC) 0x9000 0000 0x93FF FFFF Common FSMC_PMEM4 (0xA8) 0x8800 0000 0x8000 0000 0x8BFF FFFF Attribute Bank 3 - NAND Flash 0x83FF FFFF Common FSMC_PATT3 (0x8C) FSMC_PMEM3 (0x88) 0x7800 0000 0x7000 0000 0x7BFF FFFF Attribute Bank 2- NAND Flash 0x73FF FFFF Common FSMC_PATT2 (0x6C) FSMC_PMEM2 (0x68) For NAND Flash memory, the common and attribute memory spaces are subdivided into three sections (see in Table 103 below) located in the lower 256 Kbytes: • Data section (first 64 Kbytes in the common/attribute memory space) • Command section (second 64 Kbytes in the common / attribute memory space) • Address section (next 128 Kbytes in the common / attribute memory space) 503/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) Section name Address section Command section Data section Table 103. NAND bank selections HADDR[17:16] Address range 1X 0x020000-0x03FFFF 01 0x010000-0x01FFFF 00 0x000000-0x0FFFF The application software uses the 3 sections to access the NAND Flash memory: • To send a command to NAND Flash memory: the software must write the command value to any memory location in the command section. • To specify the NAND Flash address that must be read or written: the software must write the address value to any memory location in the address section. Since an address can be 4 or 5 bytes long (depending on the actual memory size), several consecutive writes to the address section are needed to specify the full address. • To read or write data: the software reads or writes the data value from or to any memory location in the data section. Since the NAND Flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations. 21.5 NOR Flash/PSRAM controller The FSMC generates the appropriate signal timings to drive the following types of memories: • Asynchronous SRAM and ROM – 8-bit – 16-bit – 32-bit • PSRAM (Cellular RAM) – Asynchronous mode – Burst mode for synchronous accesses • NOR Flash – Asynchronous mode – Burst mode for synchronous accesses – Multiplexed or nonmultiplexed The FSMC outputs a unique chip select signal NE[4:1] per bank. All the other signals (addresses, data and control) are shared. For synchronous accesses, the FSMC issues the clock (CLK) to the selected external device only during the read/write transactions. This clock is a submultiple of the HCLK clock. The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured by means of dedicated registers (see Section 21.5.6). The programmable memory parameters include access timings (see Table 104) and support for wait management (for PSRAM and NOR Flash accessed in burst mode). DocID13902 Rev 15 504/1128 555 Flexible static memory controller (FSMC) RM0008 Table 104. Programmable NOR/PSRAM access parameters Parameter Function Access mode Unit Min. Address setup Address hold Data setup Duration of the address setup phase Asynchronous Duration of the address hold Asynchronous, phase muxed I/Os Duration of the data setup phase Asynchronous AHB clock cycle (HCLK) 1 AHB clock cycle (HCLK) 2 AHB clock cycle (HCLK) 2 Bust turn Duration of the bus turnaround phase Asynchronous and AHB clock cycle synchronous read (HCLK) 1 Clock divide ratio Data latency Number of AHB clock cycles (HCLK) to build one memory Synchronous clock cycle (CLK) Number of clock cycles to issue to the memory before the first data of the burst Synchronous AHB clock cycle (HCLK) 2 Memory clock cycle (CLK) 2 Max. 16 16 256 16 16 17 21.5.1 Note: External memory interface signals Table 105, Table 106 and Table 107 list the signals that are typically used to interface NOR Flash, SRAM and PSRAM. Prefix “N”. specifies the associated signal as active low. NOR Flash, nonmultiplexed I/Os Table 105. Nonmultiplexed I/O NOR Flash FSMC signal name I/O Function CLK O Clock (for synchronous access) A[25:0] O Address bus D[15:0] I/O Bidirectional data bus NE[x] O Chip select, x = 1..4 NOE O Output enable NWE O Write enable NL(=NADV) O Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) NWAIT I NOR Flash wait input signal to the FSMC NOR Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines). 505/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) NOR Flash, multiplexed I/Os Table 106. Multiplexed I/O NOR Flash FSMC signal name I/O Function CLK O Clock (for synchronous access) A[25:16] O Address bus AD[15:0] NE[x] NOE NWE I/O 16-bit multiplexed, bidirectional address/data bus O Chip select, x = 1..4 O Output enable O Write enable NL(=NADV) NWAIT O Latch enable (this signal is called address valid, NADV, by some NOR Flash devices) I NOR Flash wait input signal to the FSMC NOR-Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines). PSRAM/SRAM Table 107. Nonmultiplexed I/Os PSRAM/SRAM FSMC signal name I/O Function CLK O Clock (only for PSRAM synchronous access) A[25:0] D[15:0] NE[x] NOE O Address bus I/O Data bidirectional bus O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM)) O Output enable NWE O Write enable NL(= NADV) NWAIT NBL[1] NBL[0] O Address valid only for PSRAM input (memory signal name: NADV) I PSRAM wait input signal to the FSMC O Upper byte enable (memory signal name: NUB) O Lowed byte enable (memory signal name: NLB) 21.5.2 PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines). Supported memories and transactions Table 108 below displays an example of the supported devices, access modes and transactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM. Transactions not allowed (or not supported) by the FSMC in this example appear in gray. DocID13902 Rev 15 506/1128 555 Flexible static memory controller (FSMC) RM0008 Table 108. NOR Flash/PSRAM controller: example of supported memories and transactions Device Mode R/W AHB data size Memory data size Allowed/ not allowed Comments Asynchronous R 8 16 Y Asynchronous W 8 16 N Asynchronous R 16 16 Y Asynchronous W 16 16 NOR Flash Asynchronous R 32 16 (muxed I/Os and nonmuxed Asynchronous W 32 16 I/Os) Asynchronous page R - 16 Y Y Split into 2 FSMC accesses Y Split into 2 FSMC accesses N Mode is not supported Synchronous R 8 16 N Synchronous R 16 16 Y Synchronous R 32 16 Y Asynchronous R 8 16 Y Asynchronous W 8 16 Y Use of byte lanes NBL[1:0] Asynchronous R 16 16 Y Asynchronous W 16 16 Y Asynchronous R 32 16 PSRAM (multiplexed Asynchronous W 32 16 I/Os and nonmultiplexed Asynchronous page R - 16 I/Os) Synchronous R 8 16 Y Split into 2 FSMC accesses Y Split into 2 FSMC accesses N Mode is not supported N Synchronous R 16 16 Y Synchronous R 32 16 Y Synchronous W 8 16 Y Use of byte lanes NBL[1:0] Synchronous W 16/32 16 Y Asynchronous R 8 / 16 16 Y SRAM and ROM Asynchronous W 8 / 16 16 Asynchronous R 32 16 Asynchronous W 32 16 Y Use of byte lanes NBL[1:0] Y Split into 2 FSMC accesses Split into 2 FSMC Y accesses. Use of byte lanes NBL[1:0] 507/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) 21.5.3 21.5.4 General timing rules Signals synchronization • All controller output signals change on the rising edge of the internal clock (HCLK) • In synchronous mode (read or write), all output signals change on the rising edge of HCLK. Whatever the CLKDIV value, all outputs change as follows: – NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the falling edge of FSMC_CLK clock. – NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising edge of FSMC_CLK clock. NOR Flash/PSRAM controller asynchronous transactions Asynchronous static memories (NOR Flash memory, PSRAM, SRAM) • Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory • The FSMC always samples the data before de-asserting the chip select signal NE. This guarantees that the memory data-hold timing constraint is met (chip enable high to data transition, usually 0 ns min.) • If the extended mode is enabled (EXTMOD bit is set in the FSMC_BCRx register), up to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D modes for read and write operations. For example, read operation can be performed in mode A and write in mode B. • If the extended mode is disabled (EXTMOD bit is reset in the FSMC_BCRx register), the FSMC can operate in Mode1 or Mode2 as follows: – Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01 in the FSMC_BCRx register) – Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in the FSMC_BCRx register). Mode 1 - SRAM/PSRAM (CRAM) The next figures show the read and write transactions for the supported modes followed by the required configuration of FSMC _BCRx, and FSMC_BTRx/FSMC_BWTRx registers. DocID13902 Rev 15 508/1128 555 Flexible static memory controller (FSMC) A[25:0] Figure 187. Mode1 read accesses Memory transaction NBL[1:0] RM0008 NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK HCLK cycles cycles Data sampled Data strobe 1. NBL[1:0] are driven low during read access. Figure 188. Mode1 write accesses Memory transaction A[25:0] ai14720c NBL[1:0] NEx NOE NWE 1HCLK D[15:0] data driven by FSMC (ADDSET +1) HCLK cycles (DATAST + 1) HCLK cycles ai14721c The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the DATAST value must be greater than zero (DATAST > 0). 509/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) Table 109. FSMC_BCRx bit fields Bit number Bit name Value to set 31-20 Reserved 0x000 19 CBURSTRW 0x0 (no effect on asynchronous mode) 18:16 Reserved 0x0 15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0. 14 EXTMOD 0x0 13 WAITEN 0x0 (no effect on asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Don’t care 5-4 MWID As needed 3-2 MTYP As needed, exclude 0x2 (NOR Flash) 1 MUXE 0x0 0 MBKEN 0x1 Bit number 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Table 110. FSMC_BTRx bit fields Bit name Value to set Reserved ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0x0 Don’t care Don’t care Don’t care Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST+3 HCLK cycles for read accesses). This value cannot be 0 (minimum is 1). Don’t care Duration of the first access phase (ADDSET+1 HCLK cycles). DocID13902 Rev 15 510/1128 555 Flexible static memory controller (FSMC) Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 189. ModeA read accesses Memory transaction A[25:0] NBL[1:0] RM0008 NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK HCLK cycles cycles Data sampled Data strobe ai14722c 1. NBL[1:0] are driven low during read access. Figure 190. ModeA write accesses Memory transaction A[25:0] NBL[1:0] NEx NOE NWE 1HCLK D[15:0] (ADDSET +1) HCLK cycles data driven by FSMC (DATAST + 1) HCLK cycles ai14721c 511/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) The differences compared with mode1 are the toggling of NOE and the independent read and write timings. Table 111. FSMC_BCRx bit fields Bit number Bit name Value to set 31-20 Reserved 0x000 19 18:16 15 14 13 12 CBURSTRW Reserved ASYNCWAIT EXTMOD WAITEN WREN 0x0 (no effect on asynchronous mode) 0x0 Set to 1 if the memory supports this feature. Otherwise keep at 0. 0x1 0x0 (no effect on asynchronous mode) As needed 11 WAITCFG Don’t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN Don’t care 5-4 MWID As needed 3-2 MTYP As needed, exclude 0x2 (NOR Flash) 1 MUXEN 0x0 0 MBKEN 0x1 Bit number 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Table 112. FSMC_BTRx bit fields Bit name Value to set Reserved ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0x0 0x0 Don’t care Don’t care Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+3 HCLK cycles) for read accesses. This value cannot be 0 (minimum is 1). Don’t care Duration of the first access phase (ADDSET+1 HCLK cycles) for read accesses. DocID13902 Rev 15 512/1128 555 Flexible static memory controller (FSMC) RM0008 Bit number 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Table 113. FSMC_BWTRx bit fields Bit name Value to set Reserved ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0x0 0x0 Don’t care Don’t care Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST+3 HCLK cycles for read accesses). This value cannot be 0 (minimum is 1). Don’t care Duration of the first access phase (ADDSET+1 HCLK cycles) for write accesses. Mode 2/B - NOR Flash Figure 191. Mode2 and mode B read accesses Memory transaction A[25:0] NADV NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK HCLK cycles cycles Data sampled Data strobe ai14724c 513/1128 DocID13902 Rev 15 RM0008 A[25:0] NADV NEx NOE NWE Flexible static memory controller (FSMC) Figure 192. Mode2 write accesses Memory transaction 1HCLK D[15:0] A[25:0] NADV NEx NOE NWE (ADDSET +1) HCLK cycles data driven by FSMC (DATAST + 1) HCLK cycles Figure 193. Mode B write accesses Memory transaction ai14723b 1HCLK D[15:0] (ADDSET +1) HCLK cycles data driven by FSMC (DATAST + 1) HCLK cycles ai15110b The differences with mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B). DocID13902 Rev 15 514/1128 555 Flexible static memory controller (FSMC) RM0008 Table 114. FSMC_BCRx bit fields Bit number Bit name Value to set 31-20 Reserved 0x000 19 CBURSTRW 0x0 (no effect on asynchronous mode) 18:16 Reserved 0x0 15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0. 14 EXTMOD 0x1 for mode B, 0x0 for mode 2 13 WAITEN 0x0 (no effect on asynchronous mode) 12 WREN As needed 11 WAITCFG Don’t care 10 WRAPMOD 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 Reserved 0x1 6 FACCEN 0x1 5-4 MWID As needed 3-2 MTYP 0x2 (NOR Flash memory) 1 MUXEN 0x0 0 MBKEN 0x1 Bit number 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Table 115. FSMC_BTRx bit fields Bit name Value to set Reserved ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0x0 0x1 Don’t care Don’t care Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+3 HCLK cycles) for read accesses. This value cannot be 0 (minimum is 1). Don’t care Duration of the first access phase (ADDSET+1 HCLK cycles) for read accesses. 515/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) Note: Bit number 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Table 116. FSMC_BWTRx bit fields Bit name Value to set Reserved ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0x0 0x1 Don’t care Don’t care Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST+3 HCLK cycles for write accesses). This value cannot be 0 (minimum is 1). Don’t care Duration of the first access phase (ADDSET+1 HCLK cycles) for write accesses. The FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its content is don’t care. Mode C - NOR Flash - OE toggling Figure 194. Mode C read accesses Memory transaction A[25:0] NADV NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK HCLK cycles cycles Data sampled Data strobe ai14725c DocID13902 Rev 15 516/1128 555 Flexible static memory controller (FSMC) A[25:0] Figure 195. Mode C write accesses Memory transaction NADV NEx NOE NWE 1HCLK RM0008 D[15:0] data driven by FSMC (ADDSET +1) HCLK cycles (DATAST + 1) HCLK cycles ai14723b The differences compared with mode1 are the toggling of NOE and the independent read and write timings. Bit No. 31-20 19 18:16 15 14 13 12 11 10 9 8 7 6 5-4 3-2 Table 117. FSMC_BCRx bit fields Bit name Value to set Reserved CBURSTRW Reserved ASYNCWAIT EXTMOD WAITEN 0x000 0x0 (no effect on asynchronous mode) 0x0 Set to 1 if the memory supports this feature. Otherwise keep at 0. 0x1 0x0 (no effect on asynchronous mode) WREN As needed WAITCFG WRAPMOD WAITPOL BURSTEN Don’t care 0x0 Meaningful only if bit 15 is 1 0x0 Reserved FACCEN MWID MTYP 0x1 0x1 As needed 0x2 (NOR Flash memory) 517/1128 DocID13902 Rev 15 RM0008 Bit No. 1 0 Bit number 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Bit number 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Flexible static memory controller (FSMC) Table 117. FSMC_BCRx bit fields (continued) Bit name Value to set MUXEN 0x0 MBKEN 0x1 Table 118. FSMC_BTRx bit fields Bit name Value to set Reserved ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0x0 0x2 0x0 0x0 Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+3 HCLK cycles) for read accesses. This value cannot be 0 (minimum is 1). Don’t care Duration of the first access phase (ADDSET+1 HCLK cycles) for read accesses. Table 119. FSMC_BWTRx bit fields Bit name Value to set Reserved ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0x0 0x2 Don’t care Don’t care Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST+3 HCLK cycles for write accesses). This value cannot be 0 (minimum is 1). Don’t care Duration of the first access phase (ADDSET+1 HCLK cycles) for write accesses. DocID13902 Rev 15 518/1128 555 Flexible static memory controller (FSMC) Mode D - asynchronous access with extended address Figure 196. Mode D read accesses Memory transaction A[25:0] NADV RM0008 NEx NOE NWE High D[15:0] (ADDSET +1) HCLK cycles data driven by memory (DATAST + 1) 2 HCLK (ADDHLD + 1) HCLK cycles cycles HCLK cycles Data sampled Data strobe ai14726c Mode D write accessesThe differences with mode1 are the toggling of NOE that goes on Memory transaction A[25:0] NADV NEx NOE NWE 1HCLK D[15:0] data driven by FSMC (ADDSET +1) HCLK cycles (ADDHLD + 1) HCLK cycles (DATAST + 1) HCLK cycles toggling after NADV changes and the independent read and write timings. ai14727c 519/1128 DocID13902 Rev 15 RM0008 Bit No. 31-20 19 18:16 15 14 13 12 11 10 9 8 7 6 5-4 3-2 1 0 Bit No. 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Flexible static memory controller (FSMC) Table 120. FSMC_BCRx bit fields Bit name Value to set Reserved 0x000 CBURSTRW Reserved ASYNCWAIT EXTMOD WAITEN WREN 0x0 (no effect on asynchronous mode) 0x0 Set to 1 if the memory supports this feature. Otherwise keep at 0. 0x1 0x0 (no effect on asynchronous mode) As needed WAITCFG Don’t care WRAPMOD WAITPOL BURSTEN Reserved 0x0 Meaningful only if bit 15 is 1 0x0 0x1 FACCEN MWID MTYP MUXEN Set according to memory support As needed As needed 0x0 MBKEN 0x1 Table 121. FSMC_BTRx bit fields Bit name Value to set Reserved 0x0 ACCMOD 0x3 DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET Don’t care Don’t care Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+3 HCLK cycles) for read accesses. This value cannot be 0 (minimum is 1) Duration of the middle phase of the read access (ADDHLD+1 HCLK cycles) Duration of the first access phase (ADDSET+1 HCLK cycles) for read accesses. DocID13902 Rev 15 520/1128 555 Flexible static memory controller (FSMC) RM0008 Bit No. 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Table 122. FSMC_BWTRx bit fields Bit name Value to set Reserved 0x0 ACCMOD DATLAT CLKDIV BUSTURN 0x3 0x0 0x0 Time between NEx high to NEx low (BUSTURN HCLK) DATAST ADDHLD ADDSET Duration of the second access phase (DATAST+3 HCLK cycles) for write accesses. This value cannot be 0 (minimum is 1) Duration of the middle phase of the write access (ADDHLD+1 HCLK cycles) Duration of the first access phase (ADDSET+1 HCLK cycles) for write accesses. Muxed mode - multiplexed asynchronous access to NOR Flash memory Figure 197. Multiplexed read accesses Memory transaction A[25:16] NADV NEx NOE NWE High AD[15:0] Lower address 1HCLK cycle data driven by memory (ADDSET +1) HCLK cycles (DATAST + 1) 2 HCLK (BUSTURN + 1)(1) HCLK cycles cycles HCLK cycles (ADDHLD + 1) HCLK cycles Data sampled Data strobe ai14728c 1. The bus turnaround delay (BUSTURN + 1) and the delay between side-by-side transactions overlap, so BUSTURN ≤ 5 has not impact. 521/1128 DocID13902 Rev 15 RM0008 A[25:16] NADV Flexible static memory controller (FSMC) Figure 198. Multiplexed write accesses Memory transaction NEx NOE NWE 1HCLK AD[15:0] Lower address data driven by FSMC (ADDSET +1) ADDHLD HCLK cycles HCLK cycles (DATAST + 2) HCLK cycles ai14729c The difference with mode D is the drive of the lower address byte(s) on the databus. Bit No. 31-21 19 18:16 15 14 13 12 11 10 9 8 7 6 5-4 3-2 Table 123. FSMC_BCRx bit fields Bit name Value to set Reserved 0x000 CBURSTRW Reserved ASYNCWAIT EXTMOD WAITEN WREN 0x0 (no effect on asynchronous mode) 0x0 Set to 1 if the memory supports this feature. Otherwise keep at 0. 0x0 0x0 (no effect on asynchronous mode) As needed WAITCFG WRAPMOD WAITPOL BURSTEN Reserved Don’t care 0x0 Meaningful only if bit 15 is 1 0x0 0x1 FACCEN MWID MTYP 0x1 As needed 0x2 (NOR Flash memory) DocID13902 Rev 15 522/1128 555 Flexible static memory controller (FSMC) Bit No. 1 0 Table 123. FSMC_BCRx bit fields (continued) Bit name Value to set MUXEN 0x1 MBKEN 0x1 RM0008 Bit No. 31:30 29-28 27-24 23-20 19-16 15-8 7-4 3-0 Table 124. FSMC_BTRx bit fields Bit name Value to set Reserved 0x0 ACCMOD 0x0 DATLAT CLKDIV BUSTURN Don’t care Don’t care Duration of the last phase of the access (BUSTURN+1 HCLK) DATAST ADDHLD ADDSET Duration of the second access phase (DATAST+3 HCLK cycles for read accesses and DATAST+1 HCLK cycles for write accesses). This value cannot be 0 (minimum is 1) Duration of the middle phase of the access (ADDHLD+1 HCLK cycles).This value cannot be 0 (minimum is 1). Duration of the first access phase (ADDSET+1 HCLK cycles). WAIT management in asynchronous accesses If the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register. If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase) programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT sensitive and so they are not prolonged. The data setup phase (DATAST in FSMC_BTRx register) must be programmed so that the WAIT signal meets the following conditions: • For read accesses: WAIT can be detected 4 HCLK cycles before data is being sampled or 6 HCLK cycles before NOE is deasserted (refer to Figure 199: Asynchronous wait during a read access). • For write accesses: WAIT can be detected 4 HCLK cycles before NWE deassertion (refer to Figure 200: Asynchronous wait during a write access). 523/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) 1. Memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ (4 × HCLK) + max_wait_assertion_time 2. Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): if max_wait_assertion_time > address_phase + hold_phase then DATAST ≥ (4 × HCLK) + (max_wait_assertion_time – address_phase – hold_phase) otherwise DATAST ≥ 4 × HCLK where max_wait_assertion_time is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low. Figure 199 and Figure 200 show the number of HCLK clock cycles that are added to the memory access after WAIT is released by the asynchronous memory (independently of the above cases). Figure 199. Asynchronous wait during a read access $>@ 1([ 0HPRU\WUDQVDFWLRQ DGGUHVVSKDVH GDWDVHWXSSKDVH 1:$,7 12( GRQ¶WFDUH GRQ¶WFDUH '>@ GDWDGULYHQE\PHPRU\ +&/. +&/. 'DWDVDPSOHG 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. DLF DocID13902 Rev 15 524/1128 555 Flexible static memory controller (FSMC) Figure 200. Asynchronous wait during a write access -EMORYTRANSACTION !;= .%X ADDRESSPHASE DATASETUPPHASE .7!)4 .7% DONTCARE DONTCARE (#,+ $;= DATADRIVENBY&3-# (#,+ 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. RM0008 AIC 525/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) 21.5.5 Caution: Synchronous transactions The memory clock, CLK, is a submultiple of HCLK according to the value of parameter CLKDIV. NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FSMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse. Data latency versus NOR Flash latency The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR Flash configuration register. The FSMC does not include the clock cycle when NADV is low in the data latency count. Some NOR Flash memories include the NADV Low cycle in the data latency count, so the exact relation between the NOR Flash latency and the FMSC DATLAT parameter can be either of: • NOR Flash latency = (DATLAT + 2) CLK clock cycles • NOR Flash latency = (DATLAT + 3) CLK clock cycles Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FSMC samples the data and waits long enough to evaluate if the data are valid. Thus the FSMC detects when the memory exits latency and real data are taken. Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FSMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access. Single-burst transfer When the selected bank is configured in burst mode for synchronous accesses, if for example an AHB single-burst transaction is requested on 16-bit memories, the FSMC performs a burst transaction of length 1 (if the AHB transfer is 16-bit), or length 2 (if the AHB transfer is 32-bit) and de-assert the chip select signal when the last data is strobed. Clearly, such a transfer is not the most efficient in terms of cycles (compared to an asynchronous read). Nevertheless, a random asynchronous access would first require to reprogram the memory access mode, which would altogether last longer. Wait management For synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency period, (DATLAT+2) CLK clock cycles. If NWAIT is sensed active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is sensed inactive (high level when WAITPOL = 0, low level when WAITPOL = 1). When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0). DocID13902 Rev 15 526/1128 555 Flexible static memory controller (FSMC) RM0008 During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid, and does not consider the data valid. There are two timing configurations for the NOR Flash NWAIT signal in burst mode: • Flash memory asserts the NWAIT signal one data cycle before the wait state (default after reset) • Flash memory asserts the NWAIT signal during the wait state These two NOR Flash wait state configurations are supported by the FSMC, individually for each chip select, thanks to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3). Figure 201. Wait configurations -EMORYTRANSACTIONBURSTOFHALFWORDS (#,+ #,+ !;= ADDR;= .!$6 .7!)4 7!)4#&' .7!)4 7!)4#&' !$;= AADDR;= INSERTEDWAITSTATE DATA DATA DATA AIB 527/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) Figure 202. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) -EMORYTRANSACTIONBURSTOFHALFWORDS (#,+ #,+ !;= ADDR;= .%X ./% .7% (IGH .!$6 .7!)4 7!)4#&' !$;= $!4,!4  #,+CYCLES !DDR;= INSERTEDWAITSTATE DATA DATA DATA DATA CLOCK CLOCK CYCLE CYCLE $ATASTROBES $ATASTROBES AID 1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. 2. NWAIT polarity is set to 0. Bit No. Table 125. FSMC_BCRx bit fields Bit name Value to set 31-20 19 18-16 15 14 13 12 11 Reserved CBURSTRW Reserved ASCYCWAIT EXTMOD WAITEN WREN WAITCFG 0x000 No effect on synchronous read 0x0 0x0 0x0 Set to 1 if the memory supports this feature, otherwise keep at 0. no effect on synchronous read to be set according to memory DocID13902 Rev 15 528/1128 555 Flexible static memory controller (FSMC) RM0008 Bit No. 10 9 8 7 6 5-4 3-2 1 0 Table 125. FSMC_BCRx bit fields (continued) Bit name Value to set WRAPMOD 0x0 WAITPOL to be set according to memory BURSTEN 0x1 Reserved 0x1 FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP 0x1 or 0x2 MUXEN As needed MBKEN 0x1 Bit No. 31:30 29:28 27-24 23-20 19-16 15-8 7-4 3-0 Bit name Reserved ACCMOD DATLAT CLKDIV Table 126. FSMC_BTRx bit fields Value to set 0x0 0x0 Data latency 0x0 to get CLK = HCLK (not supported) 0x1 to get CLK = 2 × HCLK BUSTURN DATAST ADDHLD ADDSET no effect Don’t care Don’t care Don’t care 529/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) Figure 203. Synchronous multiplexed write mode - PSRAM (CRAM) -EMORYTRANSACTIONBURSTOFHALFWORDS (#,+ #,+ !;= ADDR;= .%X (I : ./% .7% .!$6 .7!)4 7!)4#&' !$;= $!4,!4  #,+CYCLES !DDR;= INSERTEDWAITSTATE DATA DATA CLOCK CLOCK AIF 1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. NWAIT polarity is set to 0. 3. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Bit No. 31-20 19 18-16 15 14 13 12 11 10 Table 127. FSMC_BCRx bit fields Bit name Value to set Reserved 0x000 CBURSTRW 0x1 Reserved ASCYCWAIT EXTMOD WAITEN 0x0 0x0 0x0 Set to 1 if the memory supports this feature, otherwise keep at 0. WREN 0x1 WAITCFG 0x0 WRAPMOD 0x0 DocID13902 Rev 15 530/1128 555 Flexible static memory controller (FSMC) Bit No. 9 8 7 6 5-4 3-2 1 0 Table 127. FSMC_BCRx bit fields (continued) Bit name Value to set WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved 0x1 FACCEN Set according to memory support MWID As needed MTYP 0x1 MUXEN As needed MBKEN 0x1 RM0008 Bit No. 31:30 29:28 27-24 23-20 19-16 15-8 7-4 3-0 Table 128. FSMC_BTRx bit fields Bit name Value to set Reserved ACCMOD DATLAT CLKDIV 0x0 0x0 Data latency 0x0 to get CLK = HCLK (not supported) 0x1 to get CLK = 2 × HCLK BUSTURN DATAST ADDHLD ADDSET Time between NEx high to NEx low (BUSTURN HCLK) Don’t care Don’t care Don’t care 531/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) 21.5.6 NOR/PSRAM control registers The NOR/PSRAM control registers have to be accessed by words (32 bits). SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBURSTRW ASCYCWAIT EXTMOD WAITEN WREN WAITCFG WRAPMOD WAITPOL BURSTEN Reserved FACCEN MWID MTYP MUXEN MBKEN Reserved Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31: 20 Reserved, must be kept at reset value. Bit 19 CBURSTRW: Write burst enable. For Cellular RAM (PSRAM) memories, this bit enables the synchronous burst protocol during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FSMC_BCRx register. 0: Write operations are always performed in asynchronous mode 1: Write operations are performed in synchronous mode. Bits 18: 16 Reserved, must be kept at reset value. Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers This bit enables/disables the FSMC to use the wait signal even during an asynchronous protocol. 0: NWAIT signal is not taken into account when running an asynchronous protocol (default after reset) 1: NWAIT signal is taken into account when running an asynchronous protocol Bit 14 EXTMOD: Extended mode enable. This bit enables the FSMC to program the write timings for asynchronous accesses inside the FSMC_BWTR register, thus resulting in different timings for read and write operations. 0: values inside FSMC_BWTR register are not taken into account (default after reset) 1: values inside FSMC_BWTR register are taken into account Note: When the extended mode is disabled, the FSMC can operate in Mode1 or Mode2 as follows: – Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) – Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10). DocID13902 Rev 15 532/1128 555 Flexible static memory controller (FSMC) RM0008 Bit 13 WAITEN: Wait enable bit. This bit enables/disables wait-state insertion via the NWAIT signal when accessing the Flash memory in synchronous mode. 0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period) 1: NWAIT signal is enabled (its level is taken into account after the programmed Flash latency period to insert wait states if asserted) (default after reset) Bit 12 WREN: Write enable bit. This bit indicates whether write operations are enabled/disabled in the bank by the FSMC: 0: Write operations are disabled in the bank by the FSMC, an AHB error is reported, 1: Write operations are enabled for the bank by the FSMC (default after reset). Bit 11 WAITCFG: Wait timing configuration. The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the Flash memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 0: NWAIT signal is active one data cycle before wait state (default after reset), 1: NWAIT signal is active during wait state (not used for PRAM). Bit 10 WRAPMOD: Wrapped burst mode support. Defines whether the controller will or not split an AHB burst wrap access into two linear accesses. Valid only when accessing memories in burst mode 0: Direct wrapped burst is not enabled (default after reset), 1: Direct wrapped burst is enabled. Note: This bit has no effect as the CPU and DMA cannot generate wrapping burst transfers. Bit 9 WAITPOL: Wait signal polarity bit. Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode: 0: NWAIT active low (default after reset), 1: NWAIT active high. Bit 8 BURSTEN: Burst enable bit. This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode: 0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. 1: Burst mode enable. Read accesses are performed in synchronous mode. Bit 7 Reserved, must be kept at reset value. Bit 6 FACCEN: Flash access enable Enables NOR Flash memory access operations. 0: Corresponding NOR Flash memory access is disabled 1: Corresponding NOR Flash memory access is enabled (default after reset) Bits 5:4 MWID: Memory databus width. Defines the external memory device width, valid for all type of memories. 00: 8 bits, 01: 16 bits (default after reset), 10: reserved, do not use, 11: reserved, do not use. 533/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) Bits 3:2 MTYP: Memory type. Defines the type of external memory attached to the corresponding memory bank: 00: SRAM (default after reset for Bank 2...4) 01: PSRAM (CRAM) 10: NOR Flash(default after reset for Bank 1) 11: reserved Bit 1 MUXEN: Address/data multiplexing enable bit. When this bit is set, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories: 0: Address/Data nonmultiplexed 1: Address/Data multiplexed on databus (default after reset) Bit 0 MBKEN: Memory bank enable bit. Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus. 0: Corresponding memory bank is disabled 1: Corresponding memory bank is enabled DocID13902 Rev 15 534/1128 555 Flexible static memory controller (FSMC) RM0008 SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) Address offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FSMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FSMC_BWTRx registers). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 ACCMOD: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D Bits 27:24 DATLAT: Data latency for synchronous NOR Flash memory (see note below bit description table) For synchronous NOR Flash memory with burst mode enabled, defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data. This timing parameter is not expressed in HCLK periods, but in FSMC_CLK periods. In case of PSRAM (CRAM), this field must be set to 0. In asynchronous NOR Flash or SRAM or PSRAM , this value is don't care. 0000: Data latency of 2 CLK clock cycles for first burst access 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) Bits 23:20 CLKDIV: Clock divide ratio (for FSMC_CLK signal) Defines the period of FSMC_CLK clock output signal, expressed in number of HCLK cycles: 0000: Reserved 0001: FSMC_CLK period = 2 × HCLK periods 0010: FSMC_CLK period = 3 × HCLK periods 1111: FSMC_CLK period = 16 × HCLK periods (default value after reset) In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care. Bits 19:16 BUSTURN: Bus turnaround phase duration These bits are written by software to insert the bus turnaround delay after a read access only from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the databus in Hi-Z state. 0000: BUSTURN phase duration = 1 HCLK clock cycle added ... 1111: BUSTURN phase duration = 16 × HCLK clock cycles (default value after reset) 535/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) Bits 15:8 DATAST: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 187 to Figure 198), used in asynchronous accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 2 × HCLK clock cycles 0000 0010: DATAST phase duration = 3 × HCLK clock cycles ... 1111 1111: DATAST phase duration = 256 × HCLK clock cycles (default value after reset) For each memory type and access mode data-phase duration, please refer to the respective figure (Figure 187 to Figure 198). Example: Mode1, read access, DATAST=1: Data-phase duration= DATAST+3 = 4 HCLK clock cycles. Note: In synchronous accesses, this value is don't care. Bits 7:4 ADDHLD: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 196 to Figure 198), used in mode D and multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration = 2 × HCLK clock cycle 0010: ADDHLD phase duration = 3 × HCLK clock cycle ... 1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset) For each access mode address-hold phase duration, please refer to the respective figure (Figure 196 to Figure 198). Example: ModeD, read access, ADDHLD=1: Address-hold phase duration = ADDHLD + 1 =2 HCLK clock cycles. Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. Bits 3:0 ADDSET: Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure 187 to Figure 198), used in SRAMs, ROMs and asynchronous NOR Flash accesses: 0000: ADDSET phase duration = 1 × HCLK clock cycle ... 1111: ADDSET phase duration = × HCLK clock cycles (default value after reset) For each access mode address setup phase duration, please refer to the respective figure (refer to Figure 187 to Figure 198). Example: Mode2, read access, ADDSET=1: Address setup phase duration = ADDSET + 1 = 2 HCLK clock cycles. Note: In synchronous accesses, this value is don’t care. Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to prolong the latency as needed. With PSRAMs (CRAMs) the DATLAT field must be set to 0, so that the FSMC exits its latency phase soon and starts sampling NWAIT from memory, then starts to read or write when the memory is ready. This method can be used also with the latest generation of synchronous Flash memories that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the specific Flash memory being used). DocID13902 Rev 15 536/1128 555 Flexible static memory controller (FSMC) RM0008 SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) Address offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, PSRAMs and NOR Flash memories. This register is active for write asynchronous access only when the EXTMOD bit is set in the FSMC_BCRx register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. ACCM OD rw rw Reserved BUSTURN DATAST ADDHLD ADDSET rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 ACCMOD: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D Bits 27:20 Reserved, must be kept at reset value. Bits 19:16 BUSTURN: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) HCLK period ≥ tEHELmin. 0000: BUSTURN phase duration = 1 HCLK clock cycle added ... 1111: BUSTURN phase duration = 16 HCLK clock cycles added (default value after reset) 537/1128 DocID13902 Rev 15 RM0008 Flexible static memory controller (FSMC) Bits 15:8 DATAST: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 187 to Figure 198), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 2 × HCLK clock cycles 0000 0010: DATAST phase duration = 3 × HCLK clock cycles ... 1111 1111: DATAST phase duration = 16 × HCLK clock cycles (default value after reset) Note: In synchronous accesses, this value is don't care. Bits 7:4 ADDHLD: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 196 to Figure 198), used in asynchronous multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration = 2 × HCLK clock cycle 0010: ADDHLD phase duration = 3 × HCLK clock cycle ... 1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset) Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. Bits 3:0 ADDSET: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 196 to Figure 198), used in asynchronous accessed: 0000: ADDSET phase duration = 1 × HCLK clock cycle ... 1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset) Note: In synchronous NOR Flash accesses, this value is don’t care. 21.6 NAND Flash/PC Card controller The FSMC generates the appropriate signal timings to drive the following types of device: • NAND Flash – 8-bit – 16-bit • 16-bit PC Card compatible devices The NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support NAND Flash devices. Bank 4 supports PC Card devices. Each bank is configured by means of dedicated registers (Section 21.6.8). The programmable memory parameters include access timings (shown in Table 129) and ECC configuration. DocID13902 Rev 15 538/1128 555 Flexible static memory controller (FSMC) RM0008 Table 129. Programmable NAND/PC Card access parameters Parameter Function Access mode Unit Min. Max. Memory setup time Number of clock cycles (HCLK) to set up the address before the command assertion Read/Write AHB clock cycle (HCLK) 1 256 Memory wait Minimum duration (HCLK clock cycles) of the command assertion Read/Write AHB clock cycle (HCLK) 2 256 Number of clock cycles (HCLK) Memory hold to hold the address (and the data in case of a write access) after Read/Write AHB clock cycle (HCLK) 1 255 the command de-assertion Memory databus high-Z Number of clock cycles (HCLK) during which the databus is kept in high-Z state after the start of a write access Write AHB clock cycle (HCLK) 0 255 21.6.1 Caution: Note: External memory interface signals The following tables list the signals that are typically used to interface NAND Flash and PC Card. When using a PC Card or a CompactFlash in I/O mode, the NIOS16 input pin must remain at ground level during the whole operation, otherwise the FSMC may not operate properly. This means that the NIOS16 input pin must not be connected to the card, but direct