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MSP430x2xx Family User's Guide(讲义)

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MSP430x2xx Family User's Guide Literature Number: SLAU144J December 2004 – Revised July 2013 Contents Preface ...................................................................................................................................... 21 1 Introduction ...................................................................................................................... 23 1.1 Architecture ................................................................................................................. 24 1.2 Flexible Clock System .................................................................................................... 24 1.3 Embedded Emulation ..................................................................................................... 25 1.4 Address Space ............................................................................................................. 25 1.4.1 Flash/ROM ........................................................................................................ 25 1.4.2 RAM ................................................................................................................ 26 1.4.3 Peripheral Modules ............................................................................................... 26 1.4.4 Special Function Registers (SFRs) ............................................................................ 26 1.4.5 Memory Organization ............................................................................................ 26 1.5 MSP430x2xx Family Enhancements .................................................................................... 27 2 System Resets, Interrupts, and Operating Modes .................................................................. 28 2.1 System Reset and Initialization .......................................................................................... 29 2.1.1 Brownout Reset (BOR) .......................................................................................... 29 2.1.2 Device Initial Conditions After System Reset ................................................................. 30 2.2 Interrupts .................................................................................................................... 31 2.2.1 (Non)-Maskable Interrupts (NMI) ............................................................................... 31 2.2.2 Maskable Interrupts .............................................................................................. 34 2.2.3 Interrupt Processing .............................................................................................. 35 2.2.4 Interrupt Vectors .................................................................................................. 37 2.3 Operating Modes .......................................................................................................... 38 2.3.1 Entering and Exiting Low-Power Modes ...................................................................... 40 2.4 Principles for Low-Power Applications .................................................................................. 40 2.5 Connection of Unused Pins .............................................................................................. 41 3 CPU ................................................................................................................................. 42 3.1 CPU Introduction .......................................................................................................... 43 3.2 CPU Registers ............................................................................................................. 44 3.2.1 Program Counter (PC) ........................................................................................... 44 3.2.2 Stack Pointer (SP) ................................................................................................ 45 3.2.3 Status Register (SR) ............................................................................................. 45 3.2.4 Constant Generator Registers CG1 and CG2 ................................................................ 46 3.2.5 General-Purpose Registers R4 to R15 ........................................................................ 47 3.3 Addressing Modes ......................................................................................................... 47 3.3.1 Register Mode .................................................................................................... 49 3.3.2 Indexed Mode ..................................................................................................... 50 3.3.3 Symbolic Mode ................................................................................................... 51 3.3.4 Absolute Mode .................................................................................................... 52 3.3.5 Indirect Register Mode ........................................................................................... 53 3.3.6 Indirect Autoincrement Mode ................................................................................... 54 3.3.7 Immediate Mode .................................................................................................. 55 3.4 Instruction Set .............................................................................................................. 56 3.4.1 Double-Operand (Format I) Instructions ....................................................................... 57 3.4.2 Single-Operand (Format II) Instructions ....................................................................... 58 3.4.3 Jumps .............................................................................................................. 59 2 Contents SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.4 Instruction Cycles and Lengths ................................................................................. 60 3.4.5 Instruction Set Description ...................................................................................... 62 3.4.6 Instruction Set Details ............................................................................................ 64 4 CPUX .............................................................................................................................. 115 4.1 CPU Introduction ......................................................................................................... 116 4.2 Interrupts .................................................................................................................. 118 4.3 CPU Registers ............................................................................................................ 119 4.3.1 Program Counter (PC) ......................................................................................... 119 4.3.2 Stack Pointer (SP) .............................................................................................. 119 4.3.3 Status Register (SR) ............................................................................................ 121 4.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 122 4.3.5 General-Purpose Registers (R4 to R15) ..................................................................... 123 4.4 Addressing Modes ....................................................................................................... 125 4.4.1 Register Mode ................................................................................................... 126 4.4.2 Indexed Mode ................................................................................................... 127 4.4.3 Symbolic Mode .................................................................................................. 131 4.4.4 Absolute Mode .................................................................................................. 136 4.4.5 Indirect Register Mode ......................................................................................... 138 4.4.6 Indirect Autoincrement Mode .................................................................................. 139 4.4.7 Immediate Mode ................................................................................................ 140 4.5 MSP430 and MSP430X Instructions .................................................................................. 142 4.5.1 MSP430 Instructions ............................................................................................ 142 4.5.2 MSP430X Extended Instructions .............................................................................. 147 4.6 Instruction Set Description .............................................................................................. 160 4.6.1 Extended Instruction Binary Descriptions .................................................................... 161 4.6.2 MSP430 Instructions ............................................................................................ 163 4.6.3 MSP430X Extended Instructions .............................................................................. 215 4.6.4 MSP430X Address Instructions ............................................................................... 257 5 Basic Clock Module+ ........................................................................................................ 272 5.1 Basic Clock Module+ Introduction ..................................................................................... 273 5.2 Basic Clock Module+ Operation ....................................................................................... 275 5.2.1 Basic Clock Module+ Features for Low-Power Applications .............................................. 276 5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ............................................... 276 5.2.3 LFXT1 Oscillator ................................................................................................ 276 5.2.4 XT2 Oscillator ................................................................................................... 277 5.2.5 Digitally-Controlled Oscillator (DCO) ......................................................................... 277 5.2.6 DCO Modulator .................................................................................................. 279 5.2.7 Basic Clock Module+ Fail-Safe Operation ................................................................... 279 5.2.8 Synchronization of Clock Signals ............................................................................. 280 5.3 Basic Clock Module+ Registers ........................................................................................ 282 5.3.1 DCOCTL, DCO Control Register ............................................................................. 283 5.3.2 BCSCTL1, Basic Clock System Control Register 1 ........................................................ 283 5.3.3 BCSCTL2, Basic Clock System Control Register 2 ........................................................ 284 5.3.4 BCSCTL3, Basic Clock System Control Register 3 ........................................................ 285 5.3.5 IE1, Interrupt Enable Register 1 .............................................................................. 286 5.3.6 IFG1, Interrupt Flag Register 1 ................................................................................ 286 6 DMA Controller ................................................................................................................ 287 6.1 DMA Introduction ......................................................................................................... 288 6.2 DMA Operation ........................................................................................................... 290 6.2.1 DMA Addressing Modes ....................................................................................... 290 6.2.2 DMA Transfer Modes ........................................................................................... 291 6.2.3 Initiating DMA Transfers ....................................................................................... 297 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Contents 3 www.ti.com 6.2.4 Stopping DMA Transfers ....................................................................................... 298 6.2.5 DMA Channel Priorities ........................................................................................ 299 6.2.6 DMA Transfer Cycle Time ..................................................................................... 299 6.2.7 Using DMA With System Interrupts ........................................................................... 299 6.2.8 DMA Controller Interrupts ...................................................................................... 300 6.2.9 Using the USCI_B I2C Module with the DMA Controller ................................................... 300 6.2.10 Using ADC12 with the DMA Controller ...................................................................... 301 6.2.11 Using DAC12 With the DMA Controller ..................................................................... 301 6.2.12 Writing to Flash With the DMA Controller .................................................................. 301 6.3 DMA Registers ........................................................................................................... 302 6.3.1 DMACTL0, DMA Control Register 0 .......................................................................... 303 6.3.2 DMACTL1, DMA Control Register 1 .......................................................................... 303 6.3.3 DMAxCTL, DMA Channel x Control Register ............................................................... 304 6.3.4 DMAxSA, DMA Source Address Register ................................................................... 305 6.3.5 DMAxDA, DMA Destination Address Register .............................................................. 306 6.3.6 DMAxSZ, DMA Size Address Register ....................................................................... 306 6.3.7 DMAIV, DMA Interrupt Vector Register ...................................................................... 307 7 Flash Memory Controller .................................................................................................. 308 7.1 Flash Memory Introduction ............................................................................................. 309 7.2 Flash Memory Segmentation ........................................................................................... 309 7.2.1 SegmentA ........................................................................................................ 310 7.3 Flash Memory Operation ................................................................................................ 311 7.3.1 Flash Memory Timing Generator ............................................................................. 311 7.3.2 Erasing Flash Memory ......................................................................................... 312 7.3.3 Writing Flash Memory .......................................................................................... 315 7.3.4 Flash Memory Access During Write or Erase ............................................................... 320 7.3.5 Stopping a Write or Erase Cycle .............................................................................. 321 7.3.6 Marginal Read Mode ........................................................................................... 321 7.3.7 Configuring and Accessing the Flash Memory Controller ................................................. 321 7.3.8 Flash Memory Controller Interrupts ........................................................................... 321 7.3.9 Programming Flash Memory Devices ........................................................................ 321 7.4 Flash Memory Registers ................................................................................................ 323 7.4.1 FCTL1, Flash Memory Control Register ..................................................................... 324 7.4.2 FCTL2, Flash Memory Control Register ..................................................................... 324 7.4.3 FCTL3, Flash Memory Control Register ..................................................................... 325 7.4.4 FCTL4, Flash Memory Control Register ..................................................................... 326 7.4.5 IE1, Interrupt Enable Register 1 .............................................................................. 326 8 Digital I/O ........................................................................................................................ 327 8.1 Digital I/O Introduction ................................................................................................... 328 8.2 Digital I/O Operation ..................................................................................................... 328 8.2.1 Input Register PxIN ............................................................................................. 328 8.2.2 Output Registers PxOUT ....................................................................................... 328 8.2.3 Direction Registers PxDIR ..................................................................................... 329 8.2.4 Pullup/Pulldown Resistor Enable Registers PxREN ........................................................ 329 8.2.5 Function Select Registers PxSEL and PxSEL2 ............................................................. 329 8.2.6 Pin Oscillator ..................................................................................................... 330 8.2.7 P1 and P2 Interrupts ............................................................................................ 331 8.2.8 Configuring Unused Port Pins ................................................................................. 332 8.3 Digital I/O Registers ..................................................................................................... 333 9 Supply Voltage Supervisor (SVS) ....................................................................................... 335 9.1 Supply Voltage Supervisor (SVS) Introduction ....................................................................... 336 9.2 SVS Operation ........................................................................................................... 337 9.2.1 Configuring the SVS ............................................................................................ 337 4 Contents SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 9.2.2 SVS Comparator Operation ................................................................................... 337 9.2.3 Changing the VLDx Bits ........................................................................................ 337 9.2.4 SVS Operating Range .......................................................................................... 338 9.3 SVS Registers ............................................................................................................ 339 9.3.1 SVSCTL, SVS Control Register ............................................................................... 340 10 Watchdog Timer+ (WDT+) ................................................................................................. 341 10.1 Watchdog Timer+ (WDT+) Introduction ............................................................................... 342 10.2 Watchdog Timer+ Operation ........................................................................................... 344 10.2.1 Watchdog Timer+ Counter .................................................................................... 344 10.2.2 Watchdog Mode ................................................................................................ 344 10.2.3 Interval Timer Mode ........................................................................................... 344 10.2.4 Watchdog Timer+ Interrupts .................................................................................. 344 10.2.5 Watchdog Timer+ Clock Fail-Safe Operation .............................................................. 345 10.2.6 Operation in Low-Power Modes ............................................................................. 345 10.2.7 Software Examples ............................................................................................ 345 10.3 Watchdog Timer+ Registers ............................................................................................ 346 10.3.1 WDTCTL, Watchdog Timer+ Register ...................................................................... 347 10.3.2 IE1, Interrupt Enable Register 1 ............................................................................. 348 10.3.3 IFG1, Interrupt Flag Register 1 ............................................................................... 348 11 Hardware Multiplier .......................................................................................................... 349 11.1 Hardware Multiplier Introduction ....................................................................................... 350 11.2 Hardware Multiplier Operation .......................................................................................... 350 11.2.1 Operand Registers ............................................................................................. 351 11.2.2 Result Registers ................................................................................................ 351 11.2.3 Software Examples ............................................................................................ 352 11.2.4 Indirect Addressing of RESLO ............................................................................... 353 11.2.5 Using Interrupts ................................................................................................ 353 11.3 Hardware Multiplier Registers .......................................................................................... 354 12 Timer_A .......................................................................................................................... 355 12.1 Timer_A Introduction .................................................................................................... 356 12.2 Timer_A Operation ....................................................................................................... 357 12.2.1 16-Bit Timer Counter .......................................................................................... 357 12.2.2 Starting the Timer .............................................................................................. 358 12.2.3 Timer Mode Control ........................................................................................... 358 12.2.4 Capture/Compare Blocks ..................................................................................... 362 12.2.5 Output Unit ...................................................................................................... 363 12.2.6 Timer_A Interrupts ............................................................................................. 367 12.3 Timer_A Registers ....................................................................................................... 369 12.3.1 TACTL, Timer_A Control Register ........................................................................... 370 12.3.2 TAR, Timer_A Register ....................................................................................... 371 12.3.3 TACCRx, Timer_A Capture/Compare Register x .......................................................... 371 12.3.4 TACCTLx, Capture/Compare Control Register ............................................................ 372 12.3.5 TAIV, Timer_A Interrupt Vector Register ................................................................... 373 13 Timer_B .......................................................................................................................... 374 13.1 Timer_B Introduction .................................................................................................... 375 13.1.1 Similarities and Differences From Timer_A ................................................................ 375 13.2 Timer_B Operation ....................................................................................................... 377 13.2.1 16-Bit Timer Counter .......................................................................................... 377 13.2.2 Starting the Timer .............................................................................................. 377 13.2.3 Timer Mode Control ........................................................................................... 377 13.2.4 Capture/Compare Blocks ..................................................................................... 381 13.2.5 Output Unit ...................................................................................................... 384 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Contents 5 www.ti.com 13.2.6 Timer_B Interrupts ............................................................................................. 388 13.3 Timer_B Registers ....................................................................................................... 390 13.3.1 Timer_B Control Register TBCTL ........................................................................... 391 13.3.2 TBR, Timer_B Register ....................................................................................... 392 13.3.3 TBCCRx, Timer_B Capture/Compare Register x .......................................................... 392 13.3.4 TBCCTLx, Capture/Compare Control Register ............................................................ 393 13.3.5 TBIV, Timer_B Interrupt Vector Register ................................................................... 394 14 Universal Serial Interface (USI) .......................................................................................... 395 14.1 USI Introduction .......................................................................................................... 396 14.2 USI Operation ............................................................................................................ 399 14.2.1 USI Initialization ................................................................................................ 399 14.2.2 USI Clock Generation ......................................................................................... 399 14.2.3 SPI Mode ....................................................................................................... 400 14.2.4 I2C Mode ........................................................................................................ 402 14.3 USI Registers ............................................................................................................. 405 14.3.1 USICTL0, USI Control Register 0 ............................................................................ 406 14.3.2 USICTL1, USI Control Register 1 ............................................................................ 407 14.3.3 USICKCTL, USI Clock Control Register .................................................................... 408 14.3.4 USICNT, USI Bit Counter Register .......................................................................... 408 14.3.5 USISRL, USI Low Byte Shift Register ....................................................................... 409 14.3.6 USISRH, USI High Byte Shift Register ...................................................................... 409 15 Universal Serial Communication Interface, UART Mode ........................................................ 410 15.1 USCI Overview ........................................................................................................... 411 15.2 USCI Introduction: UART Mode ........................................................................................ 411 15.3 USCI Operation: UART Mode .......................................................................................... 413 15.3.1 USCI Initialization and Reset ................................................................................. 413 15.3.2 Character Format .............................................................................................. 413 15.3.3 Asynchronous Communication Formats .................................................................... 413 15.3.4 Automatic Baud Rate Detection .............................................................................. 416 15.3.5 IrDA Encoding and Decoding ................................................................................ 417 15.3.6 Automatic Error Detection .................................................................................... 418 15.3.7 USCI Receive Enable ......................................................................................... 418 15.3.8 USCI Transmit Enable ........................................................................................ 419 15.3.9 UART Baud Rate Generation ................................................................................ 419 15.3.10 Setting a Baud Rate .......................................................................................... 421 15.3.11 Transmit Bit Timing ........................................................................................... 422 15.3.12 Receive Bit Timing ........................................................................................... 422 15.3.13 Typical Baud Rates and Errors ............................................................................. 424 15.3.14 Using the USCI Module in UART Mode with Low Power Modes ...................................... 426 15.3.15 USCI Interrupts ............................................................................................... 426 15.4 USCI Registers: UART Mode .......................................................................................... 428 15.4.1 UCAxCTL0, USCI_Ax Control Register 0 .................................................................. 429 15.4.2 UCAxCTL1, USCI_Ax Control Register 1 .................................................................. 430 15.4.3 UCAxBR0, USCI_Ax Baud Rate Control Register 0 ...................................................... 430 15.4.4 UCAxBR1, USCI_Ax Baud Rate Control Register 1 ...................................................... 430 15.4.5 UCAxMCTL, USCI_Ax Modulation Control Register ...................................................... 431 15.4.6 UCAxSTAT, USCI_Ax Status Register ..................................................................... 431 15.4.7 UCAxRXBUF, USCI_Ax Receive Buffer Register ......................................................... 432 15.4.8 UCAxTXBUF, USCI_Ax Transmit Buffer Register ......................................................... 432 15.4.9 UCAxIRTCTL, USCI_Ax IrDA Transmit Control Register ................................................ 432 15.4.10 UCAxIRRCTL, USCI_Ax IrDA Receive Control Register ............................................... 432 15.4.11 UCAxABCTL, USCI_Ax Auto Baud Rate Control Register ............................................. 433 15.4.12 IE2, Interrupt Enable Register 2 ............................................................................ 433 6 Contents SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.4.13 IFG2, Interrupt Flag Register 2 ............................................................................. 433 15.4.14 UC1IE, USCI_A1 Interrupt Enable Register .............................................................. 434 15.4.15 UC1IFG, USCI_A1 Interrupt Flag Register ............................................................... 434 16 Universal Serial Communication Interface, SPI Mode ........................................................... 435 16.1 USCI Overview ........................................................................................................... 436 16.2 USCI Introduction: SPI Mode ........................................................................................... 436 16.3 USCI Operation: SPI Mode ............................................................................................. 438 16.3.1 USCI Initialization and Reset ................................................................................. 438 16.3.2 Character Format .............................................................................................. 439 16.3.3 Master Mode .................................................................................................... 439 16.3.4 Slave Mode ..................................................................................................... 440 16.3.5 SPI Enable ...................................................................................................... 441 16.3.6 Serial Clock Control ........................................................................................... 441 16.3.7 Using the SPI Mode With Low-Power Modes .............................................................. 442 16.3.8 SPI Interrupts ................................................................................................... 442 16.4 USCI Registers: SPI Mode ............................................................................................. 444 16.4.1 UCAxCTL0, USCI_Ax Control Register 0, UCBxCTL0, USCI_Bx Control Register 0 ................ 445 16.4.2 UCAxCTL1, USCI_Ax Control Register 1, UCBxCTL1, USCI_Bx Control Register 1 ................ 445 16.4.3 UCAxBR0, USCI_Ax Bit Rate Control Register 0, UCBxBR0, USCI_Bx Bit Rate Control Register 0 ................................................................................................................... 446 16.4.4 UCAxBR1, USCI_Ax Bit Rate Control Register 1, UCBxBR1, USCI_Bx Bit Rate Control Register 1 ................................................................................................................... 446 16.4.5 UCAxSTAT, USCI_Ax Status Register, UCBxSTAT, USCI_Bx Status Register ...................... 446 16.4.6 UCAxRXBUF, USCI_Ax Receive Buffer Register, UCBxRXBUF, USCI_Bx Receive Buffer Register .......................................................................................................... 446 16.4.7 UCAxTXBUF, USCI_Ax Transmit Buffer Register, UCBxTXBUF, USCI_Bx Transmit Buffer Register .......................................................................................................... 447 16.4.8 IE2, Interrupt Enable Register 2 ............................................................................. 447 16.4.9 IFG2, Interrupt Flag Register 2 ............................................................................... 447 16.4.10 UC1IE, USCI_A1/USCI_B1 Interrupt Enable Register .................................................. 448 16.4.11 UC1IFG, USCI_A1/USCI_B1 Interrupt Flag Register ................................................... 448 17 Universal Serial Communication Interface, I2C Mode ............................................................ 449 17.1 USCI Overview ........................................................................................................... 450 17.2 USCI Introduction: I2C Mode ........................................................................................... 450 17.3 USCI Operation: I2C Mode .............................................................................................. 451 17.3.1 USCI Initialization and Reset ................................................................................. 452 17.3.2 I2C Serial Data .................................................................................................. 452 17.3.3 I2C Addressing Modes ......................................................................................... 453 17.3.4 I2C Module Operating Modes ................................................................................. 454 17.3.5 I2C Clock Generation and Synchronization ................................................................. 464 17.3.6 Using the USCI Module in I2C Mode with Low-Power Modes ........................................... 465 17.3.7 USCI Interrupts in I2C Mode .................................................................................. 465 17.4 USCI Registers: I2C Mode .............................................................................................. 467 17.4.1 UCBxCTL0, USCI_Bx Control Register 0 .................................................................. 468 17.4.2 UCBxCTL1, USCI_Bx Control Register 1 .................................................................. 469 17.4.3 UCBxBR0, USCI_Bx Baud Rate Control Register 0 ...................................................... 469 17.4.4 UCBxBR1, USCI_Bx Baud Rate Control Register 1 ...................................................... 469 17.4.5 UCBxSTAT, USCI_Bx Status Register ..................................................................... 470 17.4.6 UCBxRXBUF, USCI_Bx Receive Buffer Register ......................................................... 470 17.4.7 UCBxTXBUF, USCI_Bx Transmit Buffer Register ......................................................... 470 17.4.8 UCBxI2COA, USCIBx I2C Own Address Register ......................................................... 471 17.4.9 UCBxI2CSA, USCI_Bx I2C Slave Address Register ...................................................... 471 17.4.10 UCBxI2CIE, USCI_Bx I2C Interrupt Enable Register .................................................... 471 17.4.11 IE2, Interrupt Enable Register 2 ............................................................................ 472 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Contents 7 www.ti.com 17.4.12 IFG2, Interrupt Flag Register 2 ............................................................................. 472 17.4.13 UC1IE, USCI_B1 Interrupt Enable Register .............................................................. 472 17.4.14 UC1IFG, USCI_B1 Interrupt Flag Register ............................................................... 473 18 USART Peripheral Interface, UART Mode ............................................................................ 474 18.1 USART Introduction: UART Mode ..................................................................................... 475 18.2 USART Operation: UART Mode ....................................................................................... 476 18.2.1 USART Initialization and Reset .............................................................................. 476 18.2.2 Character Format .............................................................................................. 477 18.2.3 Asynchronous Communication Formats .................................................................... 477 18.2.4 USART Receive Enable ...................................................................................... 480 18.2.5 USART Transmit Enable ...................................................................................... 480 18.2.6 USART Baud Rate Generation .............................................................................. 481 18.2.7 USART Interrupts .............................................................................................. 487 18.3 USART Registers: UART Mode ........................................................................................ 490 18.3.1 UxCTL, USART Control Register ............................................................................ 491 18.3.2 UxTCTL, USART Transmit Control Register ............................................................... 492 18.3.3 UxRCTL, USART Receive Control Register ............................................................... 493 18.3.4 UxBR0, USART Baud Rate Control Register 0 ............................................................ 493 18.3.5 UxBR1, USART Baud Rate Control Register 1 ............................................................ 493 18.3.6 UxMCTL, USART Modulation Control Register ............................................................ 494 18.3.7 UxRXBUF, USART Receive Buffer Register ............................................................... 494 18.3.8 UxTXBUF, USART Transmit Buffer Register .............................................................. 494 18.3.9 IE1, Interrupt Enable Register 1 ............................................................................. 495 18.3.10 IE2, Interrupt Enable Register 2 ............................................................................ 495 18.3.11 IFG1, Interrupt Flag Register 1 ............................................................................. 495 18.3.12 IFG2, Interrupt Flag Register 2 ............................................................................. 496 19 USART Peripheral Interface, SPI Mode ............................................................................... 497 19.1 USART Introduction: SPI Mode ........................................................................................ 498 19.2 USART Operation: SPI Mode .......................................................................................... 499 19.2.1 USART Initialization and Reset .............................................................................. 499 19.2.2 Master Mode .................................................................................................... 500 19.2.3 Slave Mode ..................................................................................................... 500 19.2.4 SPI Enable ...................................................................................................... 501 19.2.5 Serial Clock Control ........................................................................................... 502 19.2.6 SPI Interrupts ................................................................................................... 504 19.3 USART Registers: SPI Mode ........................................................................................... 506 19.3.1 UxCTL, USART Control Register ............................................................................ 507 19.3.2 UxTCTL, USART Transmit Control Register ............................................................... 507 19.3.3 UxRCTL, USART Receive Control Register ............................................................... 508 19.3.4 UxBR0, USART Baud Rate Control Register 0 ............................................................ 508 19.3.5 UxBR1, USART Baud Rate Control Register 1 ............................................................ 508 19.3.6 UxMCTL, USART Modulation Control Register ............................................................ 508 19.3.7 UxRXBUF, USART Receive Buffer Register ............................................................... 508 19.3.8 UxTXBUF, USART Transmit Buffer Register .............................................................. 509 19.3.9 ME1, Module Enable Register 1 ............................................................................. 509 19.3.10 ME2, Module Enable Register 2 ............................................................................ 509 19.3.11 IE1, Interrupt Enable Register 1 ............................................................................ 509 19.3.12 IE2, Interrupt Enable Register 2 ............................................................................ 510 19.3.13 IFG1, Interrupt Flag Register 1 ............................................................................. 510 19.3.14 IFG2, Interrupt Flag Register 2 ............................................................................. 510 20 OA ................................................................................................................................. 511 20.1 OA Introduction ........................................................................................................... 512 8 Contents SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 20.2 OA Operation ............................................................................................................. 513 20.2.1 OA Amplifier .................................................................................................... 514 20.2.2 OA Input ......................................................................................................... 514 20.2.3 OA Output and Feedback Routing ........................................................................... 514 20.2.4 OA Configurations ............................................................................................. 514 20.3 OA Registers ............................................................................................................. 520 20.3.1 OAxCTL0, Opamp Control Register 0 ...................................................................... 521 20.3.2 OAxCTL1, Opamp Control Register 1 ...................................................................... 522 21 Comparator_A+ ............................................................................................................... 523 21.1 Comparator_A+ Introduction ........................................................................................... 524 21.2 Comparator_A+ Operation .............................................................................................. 525 21.2.1 Comparator ..................................................................................................... 525 21.2.2 Input Analog Switches ......................................................................................... 525 21.2.3 Input Short Switch ............................................................................................. 526 21.2.4 Output Filter .................................................................................................... 526 21.2.5 Voltage Reference Generator ................................................................................ 527 21.2.6 Comparator_A+, Port Disable Register CAPD ............................................................. 527 21.2.7 Comparator_A+ Interrupts .................................................................................... 528 21.2.8 Comparator_A+ Used to Measure Resistive Elements ................................................... 528 21.3 Comparator_A+ Registers .............................................................................................. 530 21.3.1 CACTL1, Comparator_A+ Control Register 1 .............................................................. 531 21.3.2 CACTL2, Comparator_A+, Control Register ............................................................... 532 21.3.3 CAPD, Comparator_A+, Port Disable Register ............................................................ 532 22 ADC10 ............................................................................................................................ 533 22.1 ADC10 Introduction ...................................................................................................... 534 22.2 ADC10 Operation ........................................................................................................ 536 22.2.1 10-Bit ADC Core ............................................................................................... 536 22.2.2 ADC10 Inputs and Multiplexer ............................................................................... 536 22.2.3 Voltage Reference Generator ................................................................................ 537 22.2.4 Auto Power-Down .............................................................................................. 537 22.2.5 Sample and Conversion Timing .............................................................................. 538 22.2.6 Conversion Modes ............................................................................................. 539 22.2.7 ADC10 Data Transfer Controller ............................................................................. 544 22.2.8 Using the Integrated Temperature Sensor ................................................................. 549 22.2.9 ADC10 Grounding and Noise Considerations ............................................................. 550 22.2.10 ADC10 Interrupts ............................................................................................. 551 22.3 ADC10 Registers ......................................................................................................... 552 22.3.1 ADC10CTL0, ADC10 Control Register 0 ................................................................... 553 22.3.2 ADC10CTL1, ADC10 Control Register 1 ................................................................... 555 22.3.3 ADC10AE0, Analog (Input) Enable Control Register 0 ................................................... 556 22.3.4 ADC10AE1, Analog (Input) Enable Control Register 1 (MSP430F22xx only) ......................... 556 22.3.5 ADC10MEM, Conversion-Memory Register, Binary Format ............................................. 556 22.3.6 ADC10MEM, Conversion-Memory Register, 2s Complement Format .................................. 557 22.3.7 ADC10DTC0, Data Transfer Control Register 0 ........................................................... 557 22.3.8 ADC10DTC1, Data Transfer Control Register 1 ........................................................... 557 22.3.9 ADC10SA, Start Address Register for Data Transfer ..................................................... 558 23 ADC12 ............................................................................................................................ 559 23.1 ADC12 Introduction ...................................................................................................... 560 23.2 ADC12 Operation ........................................................................................................ 562 23.2.1 12-Bit ADC Core ............................................................................................... 562 23.2.2 ADC12 Inputs and Multiplexer ............................................................................... 562 23.2.3 Voltage Reference Generator ................................................................................ 563 23.2.4 Sample and Conversion Timing .............................................................................. 563 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Contents 9 www.ti.com 23.2.5 Conversion Memory ........................................................................................... 565 23.2.6 ADC12 Conversion Modes ................................................................................... 565 23.2.7 Using the Integrated Temperature Sensor ................................................................. 570 23.2.8 ADC12 Grounding and Noise Considerations ............................................................. 571 23.2.9 ADC12 Interrupts .............................................................................................. 572 23.3 ADC12 Registers ......................................................................................................... 574 23.3.1 ADC12CTL0, ADC12 Control Register 0 ................................................................... 575 23.3.2 ADC12CTL1, ADC12 Control Register 1 ................................................................... 577 23.3.3 ADC12MEMx, ADC12 Conversion Memory Registers .................................................... 578 23.3.4 ADC12MCTLx, ADC12 Conversion Memory Control Registers ......................................... 578 23.3.5 ADC12IE, ADC12 Interrupt Enable Register ............................................................... 579 23.3.6 ADC12IFG, ADC12 Interrupt Flag Register ................................................................ 579 23.3.7 ADC12IV, ADC12 Interrupt Vector Register ................................................................ 580 24 TLV Structure .................................................................................................................. 581 24.1 TLV Introduction .......................................................................................................... 582 24.2 Supported Tags .......................................................................................................... 583 24.2.1 DCO Calibration TLV Structure .............................................................................. 583 24.2.2 TAG_ADC12_1 Calibration TLV Structure ................................................................. 584 24.3 Checking Integrity of SegmentA ....................................................................................... 586 24.4 Parsing TLV Structure of Segment A .................................................................................. 586 25 DAC12 ............................................................................................................................ 588 25.1 DAC12 Introduction ...................................................................................................... 589 25.2 DAC12 Operation ........................................................................................................ 591 25.2.1 DAC12 Core .................................................................................................... 591 25.2.2 DAC12 Reference ............................................................................................. 591 25.2.3 Updating the DAC12 Voltage Output ........................................................................ 591 25.2.4 DAC12_xDAT Data Format ................................................................................... 592 25.2.5 DAC12 Output Amplifier Offset Calibration ................................................................. 592 25.2.6 Grouping Multiple DAC12 Modules .......................................................................... 593 25.2.7 DAC12 Interrupts .............................................................................................. 594 25.3 DAC12 Registers ......................................................................................................... 595 25.3.1 DAC12_xCTL, DAC12 Control Register .................................................................... 596 25.3.2 DAC12_xDAT, DAC12 Data Register ....................................................................... 597 26 SD16_A ........................................................................................................................... 598 26.1 SD16_A Introduction ..................................................................................................... 599 26.2 SD16_A Operation ....................................................................................................... 601 26.2.1 ADC Core ....................................................................................................... 601 26.2.2 Analog Input Range and PGA ................................................................................ 601 26.2.3 Voltage Reference Generator ................................................................................ 601 26.2.4 Auto Power-Down .............................................................................................. 601 26.2.5 Analog Input Pair Selection ................................................................................... 601 26.2.6 Analog Input Characteristics .................................................................................. 602 26.2.7 Digital Filter ..................................................................................................... 603 26.2.8 Conversion Memory Register: SD16MEM0 ................................................................ 607 26.2.9 Conversion Modes ............................................................................................. 608 26.2.10 Using the Integrated Temperature Sensor ................................................................ 608 26.2.11 Interrupt Handling ............................................................................................ 609 26.3 SD16_A Registers ....................................................................................................... 611 26.3.1 SD16CTL, SD16_A Control Register ........................................................................ 612 26.3.2 SD16CCTL0, SD16_A Control Register 0 .................................................................. 613 26.3.3 SD16INCTL0, SD16_A Input Control Register ............................................................. 614 26.3.4 SD16MEM0, SD16_A Conversion Memory Register ..................................................... 615 10 Contents SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 26.3.5 SD16AE, SD16_A Analog Input Enable Register ......................................................... 615 26.3.6 SD16IV, SD16_A Interrupt Vector Register ................................................................ 615 27 SD24_A ........................................................................................................................... 616 27.1 SD24_A Introduction ..................................................................................................... 617 27.2 SD24_A Operation ....................................................................................................... 619 27.2.1 ADC Core ....................................................................................................... 619 27.2.2 Analog Input Range and PGA ................................................................................ 619 27.2.3 Voltage Reference Generator ................................................................................ 619 27.2.4 Auto Power-Down .............................................................................................. 619 27.2.5 Analog Input Pair Selection ................................................................................... 619 27.2.6 Analog Input Characteristics .................................................................................. 620 27.2.7 Digital Filter ..................................................................................................... 621 27.2.8 Conversion Memory Register: SD24MEMx ................................................................ 625 27.2.9 Conversion Modes ............................................................................................. 626 27.2.10 Conversion Operation Using Preload ...................................................................... 628 27.2.11 Using the Integrated Temperature Sensor ................................................................ 629 27.2.12 Interrupt Handling ............................................................................................ 630 27.3 SD24_A Registers ....................................................................................................... 632 27.3.1 SD24CTL, SD24_A Control Register ........................................................................ 633 27.3.2 SD24CCTLx, SD24_A Channel x Control Register ....................................................... 634 27.3.3 SD24INCTLx, SD24_A Channel x Input Control Register ................................................ 635 27.3.4 SD24MEMx, SD24_A Channel x Conversion Memory Register ......................................... 636 27.3.5 SD24PREx, SD24_A Channel x Preload Register ........................................................ 636 27.3.6 SD24AE, SD24_A Analog Input Enable Register ......................................................... 636 27.3.7 SD24IV, SD24_A Interrupt Vector Register ................................................................ 637 28 Embedded Emulation Module (EEM) .................................................................................. 638 28.1 EEM Introduction ......................................................................................................... 639 28.2 EEM Building Blocks .................................................................................................... 641 28.2.1 Triggers ......................................................................................................... 641 28.2.2 Trigger Sequencer ............................................................................................. 641 28.2.3 State Storage (Internal Trace Buffer) ........................................................................ 641 28.2.4 Clock Control ................................................................................................... 641 28.3 EEM Configurations ..................................................................................................... 642 Revision History ....................................................................................................................... 643 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Contents 11 www.ti.com List of Figures 1-1. MSP430 Architecture ..................................................................................................... 24 1-2. Memory Map ............................................................................................................... 25 1-3. Bits, Bytes, and Words in a Byte-Organized Memory ................................................................ 26 2-1. Power-On Reset and Power-Up Clear Schematic .................................................................... 29 2-2. Brownout Timing........................................................................................................... 30 2-3. Interrupt Priority............................................................................................................ 31 2-4. Block Diagram of (Non)-Maskable Interrupt Sources................................................................. 32 2-5. NMI Interrupt Handler ..................................................................................................... 34 2-6. Interrupt Processing....................................................................................................... 35 2-7. Return From Interrupt ..................................................................................................... 36 2-8. Typical Current Consumption of 'F21x1 Devices vs Operating Modes............................................. 38 2-9. Operating Modes For Basic Clock System............................................................................. 39 3-1. CPU Block Diagram....................................................................................................... 44 3-2. Program Counter .......................................................................................................... 44 3-3. Stack Counter.............................................................................................................. 45 3-4. Stack Usage................................................................................................................ 45 3-5. PUSH SP - POP SP Sequence ......................................................................................... 45 3-6. Status Register Bits ....................................................................................................... 46 3-7. Register-Byte/Byte-Register Operations................................................................................ 47 3-8. Operand Fetch Operation ................................................................................................ 54 3-9. Double Operand Instruction Format .................................................................................... 57 3-10. Single Operand Instruction Format...................................................................................... 58 3-11. Jump Instruction Format.................................................................................................. 59 3-12. Core Instruction Map...................................................................................................... 62 3-13. Decrement Overlap........................................................................................................ 80 3-14. Main Program Interrupt.................................................................................................. 100 3-15. Destination Operand – Arithmetic Shift Left .......................................................................... 101 3-16. Destination Operand - Carry Left Shift ................................................................................ 102 3-17. Destination Operand – Arithmetic Right Shift ........................................................................ 103 3-18. Destination Operand - Carry Right Shift .............................................................................. 104 3-19. Destination Operand - Byte Swap ..................................................................................... 111 3-20. Destination Operand - Sign Extension ................................................................................ 112 4-1. MSP430X CPU Block Diagram ........................................................................................ 117 4-2. PC Storage on the Stack for Interrupts ............................................................................... 118 4-3. Program Counter......................................................................................................... 119 4-4. PC Storage on the Stack for CALLA .................................................................................. 119 4-5. Stack Pointer ............................................................................................................. 120 4-6. Stack Usage .............................................................................................................. 120 4-7. PUSHX.A Format on the Stack ........................................................................................ 120 4-8. PUSH SP, POP SP Sequence ......................................................................................... 120 4-9. SR Bits .................................................................................................................... 121 4-10. Register-Byte/Byte-Register Operation ............................................................................... 123 4-11. Register-Word Operation ............................................................................................... 123 4-12. Word-Register Operation ............................................................................................... 124 4-13. Register – Address-Word Operation .................................................................................. 124 4-14. Address-Word – Register Operation .................................................................................. 125 4-15. Indexed Mode in Lower 64KB.......................................................................................... 127 12 List of Figures SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4-16. Indexed Mode in Upper Memory....................................................................................... 128 4-17. Overflow and Underflow for Indexed Mode........................................................................... 129 4-18. Symbolic Mode Running in Lower 64KB.............................................................................. 132 4-19. Symbolic Mode Running in Upper Memory .......................................................................... 133 4-20. Overflow and Underflow for Symbolic Mode ......................................................................... 134 4-21. MSP430 Double-Operand Instruction Format........................................................................ 142 4-22. MSP430 Single-Operand Instructions................................................................................. 143 4-23. Format of Conditional Jump Instructions.............................................................................. 144 4-24. Extension Word for Register Modes................................................................................... 147 4-25. Extension Word for Non-Register Modes............................................................................. 149 4-26. Example for Extended Register/Register Instruction ................................................................ 150 4-27. Example for Extended Immediate/Indexed Instruction.............................................................. 150 4-28. Extended Format I Instruction Formats ............................................................................... 152 4-29. 20-Bit Addresses in Memory ........................................................................................... 152 4-30. Extended Format II Instruction Format................................................................................ 153 4-31. PUSHM/POPM Instruction Format .................................................................................... 154 4-32. RRCM, RRAM, RRUM, and RLAM Instruction Format ............................................................. 154 4-33. BRA Instruction Format ................................................................................................. 154 4-34. CALLA Instruction Format .............................................................................................. 154 4-35. Decrement Overlap ...................................................................................................... 180 4-36. Stack After a RET Instruction .......................................................................................... 199 4-37. Destination Operand—Arithmetic Shift Left .......................................................................... 201 4-38. Destination Operand—Carry Left Shift ................................................................................ 202 4-39. Rotate Right Arithmetically RRA.B and RRA.W ..................................................................... 203 4-40. Rotate Right Through Carry RRC.B and RRC.W.................................................................... 204 4-41. Swap Bytes in Memory.................................................................................................. 211 4-42. Swap Bytes in a Register ............................................................................................... 211 4-43. Rotate Left Arithmetically—RLAM[.W] and RLAM.A ................................................................ 238 4-44. Destination Operand-Arithmetic Shift Left ............................................................................ 239 4-45. Destination Operand-Carry Left Shift.................................................................................. 240 4-46. Rotate Right Arithmetically RRAM[.W] and RRAM.A ............................................................... 241 4-47. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode ......................................................... 243 4-48. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode ................................................... 243 4-49. Rotate Right Through Carry RRCM[.W] and RRCM.A.............................................................. 244 4-50. Rotate Right Through Carry RRCX(.B,.A) – Register Mode ....................................................... 246 4-51. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode ................................................. 246 4-52. Rotate Right Unsigned RRUM[.W] and RRUM.A.................................................................... 247 4-53. Rotate Right Unsigned RRUX(.B,.A) – Register Mode ............................................................. 248 4-54. Swap Bytes SWPBX.A Register Mode................................................................................ 252 4-55. Swap Bytes SWPBX.A In Memory .................................................................................... 252 4-56. Swap Bytes SWPBX[.W] Register Mode ............................................................................. 253 4-57. Swap Bytes SWPBX[.W] In Memory .................................................................................. 253 4-58. Sign Extend SXTX.A .................................................................................................... 254 4-59. Sign Extend SXTX[.W] .................................................................................................. 254 5-1. Basic Clock Module+ Block Diagram − MSP430F2xx .............................................................. 274 5-2. Basic Clock Module+ Block Diagram − MSP430AFE2xx........................................................... 275 5-3. Off Signals for the LFXT1 Oscillator................................................................................... 277 5-4. Off Signals for Oscillator XT2 .......................................................................................... 277 5-5. On/Off Control of DCO .................................................................................................. 278 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated List of Figures 13 www.ti.com 5-6. Typical DCOx Range and RSELx Steps.............................................................................. 278 5-7. Modulator Patterns....................................................................................................... 279 5-8. Oscillator-Fault Logic .................................................................................................... 280 5-9. Switch MCLK from DCOCLK to LFXT1CLK.......................................................................... 281 6-1. DMA Controller Block Diagram......................................................................................... 289 6-2. DMA Addressing Modes ................................................................................................ 290 6-3. DMA Single Transfer State Diagram .................................................................................. 292 6-4. DMA Block Transfer State Diagram ................................................................................... 294 6-5. DMA Burst-Block Transfer State Diagram ............................................................................ 296 7-1. Flash Memory Module Block Diagram ................................................................................ 309 7-2. Flash Memory Segments, 32-KB Example ........................................................................... 310 7-3. Flash Memory Timing Generator Block Diagram .................................................................... 311 7-4. Erase Cycle Timing ...................................................................................................... 312 7-5. Erase Cycle from Within Flash Memory .............................................................................. 313 7-6. Erase Cycle from Within RAM.......................................................................................... 314 7-7. Byte or Word Write Timing.............................................................................................. 315 7-8. Initiating a Byte or Word Write From Flash........................................................................... 316 7-9. Initiating a Byte or Word Write from RAM ............................................................................ 317 7-10. Block-Write Cycle Timing ............................................................................................... 318 7-11. Block Write Flow ......................................................................................................... 319 7-12. User-Developed Programming Solution .............................................................................. 322 8-1. Example Circuitry and Configuration using the Pin Oscillator...................................................... 330 8-2. Typical Pin-Oscillation Frequency ..................................................................................... 331 9-1. SVS Block Diagram...................................................................................................... 336 9-2. Operating Levels for SVS and Brownout/Reset Circuit ............................................................. 338 10-1. Watchdog Timer+ Block Diagram...................................................................................... 343 11-1. Hardware Multiplier Block Diagram.................................................................................... 350 12-1. Timer_A Block Diagram................................................................................................. 357 12-2. Up Mode .................................................................................................................. 358 12-3. Up Mode Flag Setting ................................................................................................... 359 12-4. Continuous Mode ........................................................................................................ 359 12-5. Continuous Mode Flag Setting ......................................................................................... 359 12-6. Continuous Mode Time Intervals ...................................................................................... 360 12-7. Up/Down Mode........................................................................................................... 360 12-8. Up/Down Mode Flag Setting............................................................................................ 361 12-9. Output Unit in Up/Down Mode ......................................................................................... 362 12-10. Capture Signal (SCS = 1)............................................................................................... 362 12-11. Capture Cycle ............................................................................................................ 363 12-12. Output Example—Timer in Up Mode.................................................................................. 364 12-13. Output Example—Timer in Continuous Mode........................................................................ 365 12-14. Output Example—Timer in Up/Down Mode .......................................................................... 366 12-15. Capture/Compare TACCR0 Interrupt Flag............................................................................ 367 13-1. Timer_B Block Diagram................................................................................................. 376 13-2. Up Mode .................................................................................................................. 378 13-3. Up Mode Flag Setting ................................................................................................... 378 13-4. Continuous Mode ........................................................................................................ 378 13-5. Continuous Mode Flag Setting ......................................................................................... 379 13-6. Continuous Mode Time Intervals ...................................................................................... 379 13-7. Up/Down Mode........................................................................................................... 380 14 List of Figures SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13-8. Up/Down Mode Flag Setting............................................................................................ 380 13-9. Output Unit in Up/Down Mode ......................................................................................... 381 13-10. Capture Signal (SCS = 1)............................................................................................... 381 13-11. Capture Cycle ............................................................................................................ 382 13-12. Output Example, Timer in Up Mode ................................................................................... 385 13-13. Output Example, Timer in Continuous Mode......................................................................... 386 13-14. Output Example, Timer in Up/Down Mode ........................................................................... 387 13-15. Capture/Compare TBCCR0 Interrupt Flag............................................................................ 388 14-1. USI Block Diagram: SPI Mode ......................................................................................... 397 14-2. USI Block Diagram: I2C Mode .......................................................................................... 398 14-3. SPI Timing ................................................................................................................ 400 14-4. Data Adjustments for 7-Bit SPI Data .................................................................................. 401 15-1. USCI_Ax Block Diagram: UART Mode (UCSYNC = 0)............................................................. 412 15-2. Character Format ........................................................................................................ 413 15-3. Idle-Line Format.......................................................................................................... 414 15-4. Address-Bit Multiprocessor Format.................................................................................... 415 15-5. Auto Baud Rate Detection - Break/Synch Sequence ............................................................... 416 15-6. Auto Baud Rate Detection - Synch Field ............................................................................. 416 15-7. UART vs IrDA Data Format............................................................................................. 417 15-8. Glitch Suppression, USCI Receive Not Started...................................................................... 419 15-9. Glitch Suppression, USCI Activated................................................................................... 419 15-10. BITCLK Baud Rate Timing With UCOS16 = 0 ....................................................................... 420 15-11. Receive Error ............................................................................................................. 423 16-1. USCI Block Diagram: SPI Mode ....................................................................................... 437 16-2. USCI Master and External Slave ...................................................................................... 439 16-3. USCI Slave and External Master ...................................................................................... 440 16-4. USCI SPI Timing with UCMSB = 1 .................................................................................... 442 17-1. USCI Block Diagram: I2C Mode ........................................................................................ 451 17-2. I2C Bus Connection Diagram ........................................................................................... 452 17-3. I2C Module Data Transfer ............................................................................................... 452 17-4. Bit Transfer on the I2C Bus ............................................................................................. 453 17-5. I2C Module 7-Bit Addressing Format ................................................................................. 453 17-6. I2C Module 10-Bit Addressing Format................................................................................. 453 17-7. I2C Module Addressing Format with Repeated START Condition................................................. 454 17-8. I2C Time Line Legend ................................................................................................... 454 17-9. I2C Slave Transmitter Mode ............................................................................................ 455 17-10. I2C Slave Receiver Mode ............................................................................................... 457 17-11. I2C Slave 10-bit Addressing Mode ..................................................................................... 458 17-12. I2C Master Transmitter Mode ........................................................................................... 460 17-13. I2C Master Receiver Mode .............................................................................................. 462 17-14. I2C Master 10-bit Addressing Mode ................................................................................... 463 17-15. Arbitration Procedure Between Two Master Transmitters .......................................................... 463 17-16. Synchronization of Two I2C Clock Generators During Arbitration ................................................. 464 18-1. USART Block Diagram: UART Mode ................................................................................. 476 18-2. Character Format ........................................................................................................ 477 18-3. Idle-Line Format.......................................................................................................... 478 18-4. Address-Bit Multiprocessor Format.................................................................................... 479 18-5. State Diagram of Receiver Enable .................................................................................... 480 18-6. State Diagram of Transmitter Enable ................................................................................. 481 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated List of Figures 15 www.ti.com 18-7. MSP430 Baud Rate Generator......................................................................................... 481 18-8. BITCLK Baud Rate Timing ............................................................................................. 482 18-9. Receive Error ............................................................................................................. 485 18-10. Transmit Interrupt Operation ........................................................................................... 487 18-11. Receive Interrupt Operation ............................................................................................ 487 18-12. Glitch Suppression, USART Receive Not Started ................................................................... 489 18-13. Glitch Suppression, USART Activated ................................................................................ 489 19-1. USART Block Diagram: SPI Mode .................................................................................... 498 19-2. USART Master and External Slave.................................................................................... 500 19-3. USART Slave and External Master.................................................................................... 501 19-4. Master Transmit Enable State Diagram............................................................................... 501 19-5. Slave Transmit Enable State Diagram ................................................................................ 502 19-6. SPI Master Receive-Enable State Diagram .......................................................................... 502 19-7. SPI Slave Receive-Enable State Diagram............................................................................ 502 19-8. SPI Baud Rate Generator............................................................................................... 503 19-9. USART SPI Timing ...................................................................................................... 503 19-10. Transmit Interrupt Operation ........................................................................................... 504 19-11. Receive Interrupt Operation ............................................................................................ 505 19-12. Receive Interrupt State Diagram....................................................................................... 505 20-1. OA Block Diagram ....................................................................................................... 513 20-2. Two-Opamp Differential Amplifier...................................................................................... 516 20-3. Two-Opamp Differential Amplifier OAx Interconnections ........................................................... 517 20-4. Three-Opamp Differential Amplifier.................................................................................... 518 20-5. Three-Opamp Differential Amplifier OAx Interconnections ......................................................... 519 21-1. Comparator_A+ Block Diagram ........................................................................................ 524 21-2. Comparator_A+ Sample-And-Hold .................................................................................... 526 21-3. RC-Filter Response at the Output of the Comparator............................................................... 527 21-4. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer ...................................... 527 21-5. Comparator_A+ Interrupt System...................................................................................... 528 21-6. Temperature Measurement System ................................................................................... 528 21-7. Timing for Temperature Measurement Systems..................................................................... 529 22-1. ADC10 Block Diagram .................................................................................................. 535 22-2. Analog Multiplexer ....................................................................................................... 536 22-3. Sample Timing ........................................................................................................... 538 22-4. Analog Input Equivalent Circuit ........................................................................................ 538 22-5. Single-Channel Single-Conversion Mode............................................................................. 540 22-6. Sequence-of-Channels Mode .......................................................................................... 541 22-7. Repeat-Single-Channel Mode .......................................................................................... 542 22-8. Repeat-Sequence-of-Channels Mode................................................................................. 543 22-9. One-Block Transfer ...................................................................................................... 545 22-10. State Diagram for Data Transfer Control in One-Block Transfer Mode........................................... 546 22-11. Two-Block Transfer ...................................................................................................... 547 22-12. State Diagram for Data Transfer Control in Two-Block Transfer Mode........................................... 548 22-13. Typical Temperature Sensor Transfer Function ..................................................................... 550 22-14. ADC10 Grounding and Noise Considerations (Internal VREF) ...................................................... 550 22-15. ADC10 Grounding and Noise Considerations (External VREF) ..................................................... 551 22-16. ADC10 Interrupt System ................................................................................................ 551 23-1. ADC12 Block Diagram .................................................................................................. 561 23-2. Analog Multiplexer ....................................................................................................... 562 16 List of Figures SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 23-3. Extended Sample Mode................................................................................................. 564 23-4. Pulse Sample Mode ..................................................................................................... 564 23-5. Analog Input Equivalent Circuit ........................................................................................ 565 23-6. Single-Channel, Single-Conversion Mode ............................................................................ 566 23-7. Sequence-of-Channels Mode .......................................................................................... 567 23-8. Repeat-Single-Channel Mode .......................................................................................... 568 23-9. Repeat-Sequence-of-Channels Mode................................................................................. 569 23-10. Typical Temperature Sensor Transfer Function ..................................................................... 571 23-11. ADC12 Grounding and Noise Considerations........................................................................ 572 25-1. DAC12 Block Diagram .................................................................................................. 590 25-2. Output Voltage vs DAC12 Data, 12-Bit, Straight Binary Mode .................................................... 592 25-3. Output Voltage vs DAC12 Data, 12-Bit, 2s-Compliment Mode .................................................... 592 25-4. Negative Offset........................................................................................................... 593 25-5. Positive Offset ............................................................................................................ 593 25-6. DAC12 Group Update Example, Timer_A3 Trigger ................................................................. 594 26-1. SD16_A Block Diagram ................................................................................................. 600 26-2. Analog Input Equivalent Circuit ........................................................................................ 602 26-3. Comb Filter Frequency Response With OSR = 32 .................................................................. 603 26-4. Digital Filter Step Response and Conversion Points................................................................ 604 26-5. Used Bits of Digital Filter Output....................................................................................... 606 26-6. Input Voltage vs Digital Output......................................................................................... 607 26-7. Single Channel Operation .............................................................................................. 608 26-8. Typical Temperature Sensor Transfer Function ..................................................................... 609 27-1. Block Diagram of the SD24_A ......................................................................................... 618 27-2. Analog Input Equivalent Circuit ........................................................................................ 620 27-3. Comb Filter Frequency Response With OSR = 32 .................................................................. 622 27-4. Digital Filter Step Response and Conversion Points................................................................ 622 27-5. Used Bits of Digital Filter Output....................................................................................... 624 27-6. Input Voltage vs Digital Output......................................................................................... 625 27-7. Single Channel Operation - Example ................................................................................. 626 27-8. Grouped Channel Operation - Example .............................................................................. 627 27-9. Conversion Delay Using Preload - Example ......................................................................... 628 27-10. Start of Conversion Using Preload - Example ....................................................................... 628 27-11. Preload and Channel Synchronization ................................................................................ 629 27-12. Typical Temperature Sensor Transfer Function ..................................................................... 629 28-1. Large Implementation of the Embedded Emulation Module (EEM) ............................................... 640 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated List of Figures 17 www.ti.com List of Tables 1-1. MSP430x2xx Family Enhancements.................................................................................... 27 2-1. Interrupt Sources, Flags, and Vectors .................................................................................. 37 2-2. Operating Modes For Basic Clock System............................................................................. 39 2-3. Connection of Unused Pins .............................................................................................. 41 3-1. Description of Status Register Bits...................................................................................... 46 3-2. Values of Constant Generators CG1, CG2 ............................................................................ 46 3-3. Source/Destination Operand Addressing Modes...................................................................... 48 3-4. Register Mode Description ............................................................................................... 49 3-5. Indexed Mode Description ............................................................................................... 50 3-6. Symbolic Mode Description .............................................................................................. 51 3-7. Absolute Mode Description............................................................................................... 52 3-8. Indirect Mode Description ................................................................................................ 53 3-9. Indirect Autoincrement Mode Description .............................................................................. 54 3-10. Immediate Mode Description............................................................................................. 55 3-11. Double Operand Instructions ............................................................................................ 57 3-12. Single Operand Instructions.............................................................................................. 58 3-13. Jump Instructions.......................................................................................................... 59 3-14. Interrupt and Reset Cycles............................................................................................... 60 3-15. Format-II Instruction Cycles and Lengths .............................................................................. 60 3-16. Format 1 Instruction Cycles and Lengths .............................................................................. 61 3-17. MSP430 Instruction Set .................................................................................................. 62 4-1. SR Bit Description ....................................................................................................... 121 4-2. Values of Constant Generators CG1, CG2........................................................................... 122 4-3. Source/Destination Addressing ........................................................................................ 125 4-4. MSP430 Double-Operand Instructions................................................................................ 143 4-5. MSP430 Single-Operand Instructions................................................................................. 143 4-6. Conditional Jump Instructions .......................................................................................... 144 4-7. Emulated Instructions ................................................................................................... 144 4-8. Interrupt, Return, and Reset Cycles and Length..................................................................... 145 4-9. MSP430 Format II Instruction Cycles and Length ................................................................... 145 4-10. MSP430 Format I Instructions Cycles and Length .................................................................. 146 4-11. Description of the Extension Word Bits for Register Mode......................................................... 147 4-12. Description of Extension Word Bits for Non-Register Modes ...................................................... 149 4-13. Extended Double-Operand Instructions............................................................................... 151 4-14. Extended Single-Operand Instructions................................................................................ 153 4-15. Extended Emulated Instructions ....................................................................................... 155 4-16. Address Instructions, Operate on 20-Bit Register Data............................................................. 156 4-17. MSP430X Format II Instruction Cycles and Length ................................................................. 157 4-18. MSP430X Format I Instruction Cycles and Length .................................................................. 158 4-19. Address Instruction Cycles and Length ............................................................................... 159 4-20. Instruction Map of MSP430X ........................................................................................... 160 5-1. Basic Clock Module+ Registers ........................................................................................ 282 6-1. DMA Transfer Modes.................................................................................................... 291 6-2. DMA Trigger Operation ................................................................................................. 297 6-3. Channel Priorities ........................................................................................................ 299 6-4. Maximum Single-Transfer DMA Cycle Time ......................................................................... 299 6-5. DMA Registers ........................................................................................................... 302 18 List of Tables SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7-1. Erase Modes.............................................................................................................. 312 7-2. Write Modes .............................................................................................................. 315 7-3. Flash Access While BUSY = 1 ......................................................................................... 320 7-4. Flash Memory Registers ................................................................................................ 323 8-1. PxSEL and PxSEL2 ..................................................................................................... 329 8-2. Digital I/O Registers ..................................................................................................... 333 9-1. SVS Registers............................................................................................................ 339 10-1. Watchdog Timer+ Registers............................................................................................ 346 11-1. OP1 Addresses........................................................................................................... 351 11-2. RESHI Contents.......................................................................................................... 351 11-3. SUMEXT Contents....................................................................................................... 351 11-4. Hardware Multiplier Registers .......................................................................................... 354 12-1. Timer Modes.............................................................................................................. 358 12-2. Output Modes ............................................................................................................ 364 12-3. Timer_A3 Registers...................................................................................................... 369 13-1. Timer Modes.............................................................................................................. 377 13-2. TBCLx Load Events ..................................................................................................... 383 13-3. Compare Latch Operating Modes ..................................................................................... 383 13-4. Output Modes ............................................................................................................ 384 13-5. Timer_B Registers ....................................................................................................... 390 14-1. USI Registers............................................................................................................. 405 14-2. Word Access to USI Registers ......................................................................................... 405 15-1. Receive Error Conditions ............................................................................................... 418 15-2. BITCLK Modulation Pattern ............................................................................................ 420 15-3. BITCLK16 Modulation Pattern ......................................................................................... 421 15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 ................................................ 424 15-5. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1 ................................................ 425 15-6. USCI_A0 Control and Status Registers............................................................................... 428 15-7. USCI_A1 Control and Status Registers............................................................................... 428 16-1. UCxSTE Operation ...................................................................................................... 438 16-2. USCI_A0 and USCI_B0 Control and Status Registers ............................................................. 444 16-3. USCI_A1 and USCI_B1 Control and Status Registers ............................................................. 444 17-1. State Change Interrupt Flags........................................................................................... 465 17-2. USCI_B0 Control and Status Registers............................................................................... 467 17-3. USCI_B1 Control and Status Registers............................................................................... 467 18-1. Receive Error Conditions ............................................................................................... 480 18-2. Commonly Used Baud Rates, Baud Rate Data, and Errors ....................................................... 486 18-3. USART0 Control and Status Registers ............................................................................... 490 18-4. USART1 Control and Status Registers ............................................................................... 490 19-1. USART0 Control and Status Registers ............................................................................... 506 19-2. USART1 Control and Status Registers ............................................................................... 506 20-1. OA Output Configurations .............................................................................................. 514 20-2. OA Mode Select.......................................................................................................... 514 20-3. Two-Opamp Differential Amplifier Control Register Settings....................................................... 516 20-4. Two-Opamp Differential Amplifier Gain Settings..................................................................... 516 20-5. Three-Opamp Differential Amplifier Control Register Settings..................................................... 518 20-6. Three-Opamp Differential Amplifier Gain Settings................................................................... 518 20-7. OA Registers ............................................................................................................. 520 21-1. Comparator_A+ Registers .............................................................................................. 530 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated List of Tables 19 www.ti.com 22-1. Conversion Mode Summary ............................................................................................ 539 22-2. Maximum DTC Cycle Time ............................................................................................. 549 22-3. ADC10 Registers......................................................................................................... 552 23-1. Conversion Mode Summary ............................................................................................ 565 23-2. ADC12 Registers......................................................................................................... 574 24-1. Example SegmentA Structure.......................................................................................... 582 24-2. Supported Tags (Device Specific) ..................................................................................... 583 24-3. DCO Calibration Data (Device Specific) .............................................................................. 583 24-4. TAG_ADC12_1 Calibration Data (Device Specific) ................................................................. 584 25-1. DAC12 Full-Scale Range (VREF = VeREF+ or VREF+) .................................................................... 591 25-2. DAC12 Registers......................................................................................................... 595 26-1. High Input Impedance Buffer ........................................................................................... 602 26-2. Sampling Capacitance .................................................................................................. 603 26-3. Data Format .............................................................................................................. 607 26-4. Conversion Mode Summary ............................................................................................ 608 26-5. SD16_A Registers ....................................................................................................... 611 27-1. High Input Impedance Buffer ........................................................................................... 620 27-2. Sampling Capacitance .................................................................................................. 621 27-3. Data Format .............................................................................................................. 625 27-4. Conversion Mode Summary ............................................................................................ 626 27-5. SD24_A Registers ....................................................................................................... 632 28-1. 2xx EEM Configurations ................................................................................................ 642 20 List of Tables SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Preface SLAU144J – December 2004 – Revised July 2013 Read This First About This Manual This manual discusses modules and peripherals of the MSP430x2xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family. Pin functions, internal signal connections, and operational paramenters differ from device to device. The user should consult the device-specific datasheet for these details. Related Documentation From Texas Instruments For related documentation see the web site http://www.ti.com/msp430. FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Notational Conventions Program examples, are shown in a special typeface. Glossary ACLK ADC BOR BSL CPU DAC DCO dst FLL GIE INT(N/2) I/O ISR LSB LSD LPM MAB MCLK Auxiliary Clock Analog-to-Digital Converter Brown-Out Reset Bootstrap Loader Central Processing Unit Digital-to-Analog Converter Digitally Controlled Oscillator Destination Frequency Locked Loop General Interrupt Enable Integer portion of N/2 Input/Output Interrupt Service Routine Least-Significant Bit Least-Significant Digit Low-Power Mode Memory Address Bus Master Clock See Basic Clock Module See System Resets, Interrupts, and Operating Modes See www.ti.com/msp430for application reports See RISC 16-Bit CPU See Basic Clock Module See RISC 16-Bit CPU See FLL+in MSP430x4xx Family User’s Guide See System Resets, Interrupts, and Operating Modes See Digital I/O See System Resets, Interrupts, and Operating Modes See Basic Clock Module SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Read This First 21 Register Bit Conventions MDB MSB MSD NMI PC POR PUC RAM SCG SFR SMCLK SP SR src TOS WDT Memory Data Bus Most-Significant Bit Most-Significant Digit (Non)-Maskable Interrupt Program Counter Power-On Reset Power-Up Clear Random Access Memory System Clock Generator Special Function Register Sub-System Master Clock Stack Pointer Status Register Source Top-of-Stack Watchdog Timer www.ti.com See System Resets, Interrupts, and Operating Modes See RISC 16-Bit CPU See System Resets, Interrupts, and Operating Modes See System Resets, Interrupts, and Operating Modes See System Resets, Interrupts, and Operating Modes See Basic Clock Module See RISC 16-Bit CPU See RISC 16-Bit CPU See RISC 16-Bit CPU See RISC 16-Bit CPU See Watchdog Timer Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition Key rw r r0 r1 w w0 w1 (w) h0 h1 -0,-1 -(0),-(1) Bit Accessibility Read/write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0. Cleared by hardware Set by hardware Condition after PUC Condition after POR 22 Read This First SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 1 SLAU144J – December 2004 – Revised July 2013 Introduction This chapter describes the architecture of the MSP430. Topic ........................................................................................................................... Page 1.1 Architecture ...................................................................................................... 24 1.2 Flexible Clock System ........................................................................................ 24 1.3 Embedded Emulation ......................................................................................... 25 1.4 Address Space .................................................................................................. 25 1.5 MSP430x2xx Family Enhancements ..................................................................... 27 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Introduction 23 Architecture www.ti.com 1.1 Architecture The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clock system that interconnect using a von-Neumann common memory address bus (MAB) and memory data bus (MDB) (see Figure 11). Partnering a modern CPU with modular memory-mapped analog and digital peripherals, the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x2xx family include: • Ultralow-power architecture extends battery life – 0.1 µA RAM retention – 0.8 µA real-time clock mode – 250 µA/MIPS active • High-performance analog ideal for precision measurement – Comparator-gated timers for measuring resistive elements • 16-bit RISC CPU enables new applications at a fraction of the code size. – Large register file eliminates working file bottleneck – Compact core design reduces power consumption and cost – Optimized for modern high-level programming – Only 27 core instructions and seven addressing modes – Extensive vectored-interrupt capability • In-system programmable Flash permits flexible code changes, field upgrades and data logging Clock ACLK Flash/ System SMCLK ROM MCLK RAM Peripheral Peripheral Peripheral JTAG/Debug RISC CPU 16-Bit MAB 16-Bit JTAG MDB 16-Bit Bus Conv. MDB 8-Bit ACLK SMCLK Watchdog Peripheral Peripheral Peripheral Peripheral Figure 1-1. MSP430 Architecture 1.2 Flexible Clock System The clock system is designed specifically for battery-powered applications. A low-frequency auxiliary clock (ACLK) is driven directly from a common 32-kHz watch crystal. The ACLK can be used for a background real-time clock self wake-up function. An integrated high-speed digitally controlled oscillator (DCO) can source the master clock (MCLK) used by the CPU and high-speed peripherals. By design, the DCO is active and stable in less than 2 µs at 1 MHz. MSP430-based solutions effectively use the highperformance 16-bit RISC CPU in very short bursts. • Low-frequency auxiliary clock = Ultralow-power stand-by mode • High-speed master clock = High performance signal processing 24 Introduction SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Embedded Emulation 1.3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources. The benefits of embedded emulation include: • Unobtrusive development and debug with full-speed execution, breakpoints, and single-steps in an application are supported. • Development is in-system subject to the same characteristics as the final application. • Mixed-signal integrity is preserved and not subject to cabling interference. 1.4 Address Space The MSP430 von-Neumann architecture has one address space shared with special function registers (SFRs), peripherals, RAM, and Flash/ROM memory as shown in Figure 1-2. See the device-specific data sheets for specific memory maps. Code access are always performed on even addresses. Data can be accessed as bytes or words. The addressable memory space is currently 128 KB. Access 1FFFFh 10000h 0FFFFh 0FFE0h 0FFDFh Flash/ROM Interrupt Vector Table Flash/ROM Word/Byte Word/Byte Word/Byte 0200h 01FFh 0100h 0FFh 010h 0Fh 0h RAM Word/Byte 16-Bit Peripheral Modules Word 8-Bit Peripheral Modules Byte Special Function Registers Byte Figure 1-2. Memory Map 1.4.1 Flash/ROM The start address of Flash/ROM depends on the amount of Flash/ROM present and varies by device. The end address for Flash/ROM is 0x0FFFF for devices with less that 60KB of Flash/ROM. Flash can be used for both code and data. Word or byte tables can be stored and used in Flash/ROM without the need to copy the tables to RAM before using them. The interrupt vector table is mapped into the upper 16 words of Flash/ROM address space, with the highest priority interrupt vector at the highest Flash/ROM word address (0x0FFFE). SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Introduction 25 Address Space www.ti.com 1.4.2 RAM RAM starts at 0200h. The end address of RAM depends on the amount of RAM present and varies by device. RAM can be used for both code and data. 1.4.3 Peripheral Modules Peripheral modules are mapped into the address space. The address space from 0100 to 01FFh is reserved for 16-bit peripheral modules. These modules should be accessed with word instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always 0. The address space from 010h to 0FFh is reserved for 8-bit peripheral modules. These modules should be accessed with byte instructions. Read access of byte modules using word instructions results in unpredictable data in the high byte. If word data is written to a byte module only the low byte is written into the peripheral register, ignoring the high byte. 1.4.4 Special Function Registers (SFRs) Some peripheral functions are configured in the SFRs. The SFRs are located in the lower 16 bytes of the address space, and are organized by byte. SFRs must be accessed using byte instructions only. See the device-specific data sheets for applicable SFR bits. 1.4.5 Memory Organization Bytes are located at even or odd addresses. Words are only located at even addresses as shown in Figure 1-3. When using word instructions, only even addresses may be used. The low byte of a word is always an even address. The high byte is at the next odd address. For example, if a data word is located at address xxx4h, then the low byte of that data word is located at address xxx4h, and the high byte of that word is located at address xxx5h. xxxAh 15 14 . . Bits . . 9 8 xxx9h 7 6 . . Bits . . 1 0 xxx8h Byte Byte xxx7h xxx6h Word (High Byte) Word (Low Byte) xxx5h xxx4h xxx3h Figure 1-3. Bits, Bytes, and Words in a Byte-Organized Memory 26 Introduction SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430x2xx Family Enhancements 1.5 MSP430x2xx Family Enhancements Table 1-1 highlights enhancements made to the MSP430x2xx family. The enhancements are discussed fully in the following chapters, or in the case of improved device parameters, shown in the device-specific data sheet. Subject Reset Watchdog Timer Basic Clock System Flash Memory Digital I/O Comparator_A Low Power Operating frequency BSL Table 1-1. MSP430x2xx Family Enhancements Enhancement • Brownout reset is included on all MSP430x2xx devices. • PORIFG and RSTIFG flags have been added to IFG1 to indicate the cause of a reset. • An instruction fetch from the address range 0x0000 - 0x01FF will reset the device. • All MSP430x2xx devices integrate the Watchdog Timer+ module (WDT+). The WDT+ ensures the clock source for the timer is never disabled. • The LFXT1 oscillator has selectable load capacitors in LF mode. • The LFXT1 supports up to 16-MHz crystals in HF mode. • The LFXT1 includes oscillator fault detection in LF mode. • The XIN and XOUT pins are shared function pins on 20- and 28-pin devices. • The external R OSCfeature of the DCO not supported on some devices. Software should not set the LSB of the BCSCTL2 register in this case. See the device-specific data sheet for details. • The DCO operating frequency has been significantly increased. • The DCO temperature stability has been significantly improved. • The information memory has 4 segments of 64 bytes each. • SegmentA is individually locked with the LOCKA bit. • All information if protected from mass erase with the LOCKA bit. • Segment erases can be interrupted by an interrupt. • Flash updates can be aborted by an interrupt. • Flash programming voltage has been lowered to 2.2 V • Program/erase time has been reduced. • Clock failure aborts a flash update. • All ports have integrated pullup/pulldown resistors. • P2.6 and P2.7 functions have been added to 20- and 28- pin devices. These are shared functions with XIN and XOUT. Software must not clear the P2SELx bits for these pins if crystal operation is required. • Comparator_A has expanded input capability with a new input multiplexer. • Typical LPM3 current consumption has been reduced almost 50% at 3 V. DCO startup time has been significantly reduced. • The maximum operating frequency is 16 MHz at 3.3 V. • An incorrect password causes a mass erase. • BSL entry sequence is more robust to prevent accidental entry and erasure. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Introduction 27 Chapter 2 SLAU144J – December 2004 – Revised July 2013 System Resets, Interrupts, and Operating Modes This chapter describes the MSP430x2xx system resets, interrupts, and operating modes. Topic ........................................................................................................................... Page 2.1 System Reset and Initialization ........................................................................... 29 2.2 Interrupts ......................................................................................................... 31 2.3 Operating Modes ............................................................................................... 38 2.4 Principles for Low-Power Applications ................................................................ 40 2.5 Connection of Unused Pins ................................................................................ 41 28 System Resets, Interrupts, and Operating Modes SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com System Reset and Initialization 2.1 System Reset and Initialization The system reset circuitry shown in Figure 2-1 sources both a power-on reset (POR) and a power-up clear (PUC) signal. Different events trigger these reset signals and different initial conditions exist depending on which signal was generated. VCC Brownout Reset 0V SVS_POR‡ RST/NMI WDTNMI† WDTTMSEL WDTQn† WDTIFG† ~50 µs Resetwd1 EQU† KEYV (from flash module) Resetwd2 Invalid instruction fetch † From watchdog timer peripheral module ‡ Devices with SVS only POR S Latch R Delay S S PUC S Latch S S R MCLK POR PUC Figure 2-1. Power-On Reset and Power-Up Clear Schematic A POR is a device reset. A POR is only generated by the following three events: • Powering up the device • A low signal on the RST/NMI pin when configured in the reset mode • An SVS low condition when PORON = 1. A PUC is always generated when a POR is generated, but a POR is not generated by a PUC. The following events trigger a PUC: • A POR signal • Watchdog timer expiration when in watchdog mode only • Watchdog timer security key violation • A Flash memory security key violation • A CPU instruction fetch from the peripheral address range 0h to 01FFh 2.1.1 Brownout Reset (BOR) The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the VCC terminal. The brownout reset circuit resets the device by triggering a POR signal when power is applied or removed. The operating levels are shown in Figure 2-2. The POR signal becomes active when VCC crosses the VCC(start) level. It remains active until VCC crosses the V(B_IT+) threshold and the delay t(BOR) elapses. The delay t(BOR) is adaptive being longer for a slow ramping VCC. The hysteresis Vhys(B_ IT-) ensures that the supply voltage must drop below V(B_IT-) to generate another POR signal from the brownout reset circuitry. SLAU144J – December 2004 – Revised July 2013 System Resets, Interrupts, and Operating Modes 29 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated System Reset and Initialization V(B_IT+) V(B_IT−) Vhys(B_IT−) VCC(start) VCC www.ti.com Set Signal for POR circuitry t (BOR) Figure 2-2. Brownout Timing As the V(B_IT-) level is significantly above the Vmin level of the POR circuit, the BOR provides a reset for power failures where VCC does not fall below Vmin. See device-specific data sheet for parameters. 2.1.2 Device Initial Conditions After System Reset After a POR, the initial MSP430 conditions are: • The RST/NMI pin is configured in the reset mode. • I/O pins are switched to input mode as described in the Digital I/O chapter. • Other peripheral modules and registers are initialized as described in their respective chapters in this manual. • Status register (SR) is reset. • The watchdog timer powers up active in watchdog mode. • Program counter (PC) is loaded with address contained at reset vector location (0FFFEh). If the reset vectors content is 0FFFFh the device will be disabled for minimum power consumption. 2.1.2.1 Software Initialization After a system reset, user software must initialize the MSP430 for the application requirements. The following must occur: • Initialize the SP, typically to the top of RAM. • Initialize the watchdog to the requirements of the application. • Configure peripheral modules to the requirements of the application. Additionally, the watchdog timer, oscillator fault, and flash memory flags can be evaluated to determine the source of the reset. 30 System Resets, Interrupts, and Operating Modes SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Interrupts 2.2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2-3. The nearer a module is to the CPU/NMIRS, the higher the priority. Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously. There are three types of interrupts: • System reset • (Non)-maskable NMI • Maskable Priority High Low CPU GMIRS GIE NMIRS Module Module 1 2 12 12 WDT Timer Module Module m n 12 12 1 PUC PUC Circuit OSCfault Flash ACCV Reset/NMI Bus Grant WDT Security Key Flash Security Key MAB − 5LSBs Figure 2-3. Interrupt Priority 2.2.1 (Non)-Maskable Interrupts (NMI) (Non)-maskable NMI interrupts are not masked by the general interrupt enable bit (GIE), but are enabled by individual interrupt enable bits (NMIIE, ACCVIE, OFIE). When a NMI interrupt is accepted, all NMI interrupt enable bits are automatically reset. Program execution begins at the address stored in the (non)maskable interrupt vector, 0FFFCh. User software must set the required NMI interrupt enable bits for the interrupt to be re-enabled. The block diagram for NMI sources is shown in Figure 2-4. A (non)-maskable NMI interrupt can be generated by three sources: • An edge on the RST/NMI pin when configured in NMI mode • An oscillator fault occurs • An access violation to the flash memory SLAU144J – December 2004 – Revised July 2013 System Resets, Interrupts, and Operating Modes 31 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Interrupts www.ti.com ACCV FCTL3.2 ACCVIFG S ACCVIE IE1.5 Clear PUC RST/NMI POR S IFG1.2 PORIFG Flash Module IFG1.3 S Clear RSTIFG POR POR PUC KEYV SVS_POR BOR System Reset Generator PUC POR NMIIFG S IFG1.4 Clear WDTTMSEL WDTNMIES WDTNMI WDTQn NMIRS EQU PUC POR PUC NMIIE IE1.4 Clear PUC OSCFault OFIFG S IFG1.1 OFIE IE1.1 PUC Clear NMI_IRQA WDTIFG S IR IFG1.0 Q Clear Counter WDT POR IRQA WDTTMSEL WDTIE IE1.0 Clear IRQA: Interrupt Request Accepted Watchdog Timer Module PUC Figure 2-4. Block Diagram of (Non)-Maskable Interrupt Sources 32 System Resets, Interrupts, and Operating Modes SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Interrupts 2.2.1.1 Reset/NMI Pin At power-up, the RST/NMI pin is configured in the reset mode. The function of the RST/NMI pins is selected in the watchdog control register WDTCTL. If the RST/NMI pin is set to the reset function, the CPU is held in the reset state as long as the RST/NMI pin is held low. After the input changes to a high state, the CPU starts program execution at the word address stored in the reset vector, 0FFFEh, and the RSTIFG flag is set. If the RST/NMI pin is configured by user software to the NMI function, a signal edge selected by the WDTNMIES bit generates an NMI interrupt if the NMIIE bit is set. The RST/NMI flag NMIIFG is also set. NOTE: Holding RST/NMI Low When configured in the NMI mode, a signal generating an NMI event should not hold the RST/NMI pin low. If a PUC occurs from a different source while the NMI signal is low, the device will be held in the reset state because a PUC changes the RST/NMI pin to the reset function. NOTE: Modifying WDTNMIES When NMI mode is selected and the WDTNMIES bit is changed, an NMI can be generated, depending on the actual level at the RST/NMI pin. When the NMI edge select bit is changed before selecting the NMI mode, no NMI is generated. 2.2.1.2 Flash Access Violation The flash ACCVIFG flag is set when a flash access violation occurs. The flash access violation can be enabled to generate an NMI interrupt by setting the ACCVIE bit. The ACCVIFG flag can then be tested by the NMI interrupt service routine to determine if the NMI was caused by a flash access violation. 2.2.1.3 Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator. The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit. The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault. A PUC signal can trigger an oscillator fault, because the PUC switches the LFXT1 to LF mode, therefore switching off the HF mode. The PUC signal also switches off the XT2 oscillator. SLAU144J – December 2004 – Revised July 2013 System Resets, Interrupts, and Operating Modes 33 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Interrupts www.ti.com 2.2.1.4 Example of an NMI Interrupt Handler The NMI interrupt is a multiple-source interrupt. An NMI interrupt automatically resets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMI service routine resets the interrupt flags and re-enables the interrupt-enable bits according to the application needs as shown in Figure 2-5. Start of NMI Interrupt Handler Reset by HW: OFIE, NMIIE, ACCVIE OFIFG=1 no no ACCVIFG=1 yes yes Reset OFIFG Reset ACCVIFG no NMIIFG=1 yes Reset NMIIFG User’s Software, Oscillator Fault Handler Optional User’s Software, Flash Access Violation Handler User’s Software, External NMI Handler RETI End of NMI Interrupt Handler Figure 2-5. NMI Interrupt Handler NOTE: Enabling NMI Interrupts with ACCVIE, NMIIE, and OFIE To prevent nested NMI interrupts, the ACCVIE, NMIIE, and OFIE enable bits should not be set inside of an NMI interrupt service routine. 2.2.2 Maskable Interrupts Maskable interrupts are caused by peripherals with interrupt capability including the watchdog timer overflow in interval-timer mode. Each maskable interrupt source can be disabled individually by an interrupt enable bit, or all maskable interrupts can be disabled by the general interrupt enable (GIE) bit in the status register (SR). Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual. 34 System Resets, Interrupts, and Operating Modes SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Interrupts 2.2.3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)maskable interrupts to be requested. 2.2.3.1 Interrupt Acceptance The interrupt latency is 5 cycles (CPUx) or 6 cycles (CPU), starting with the acceptance of an interrupt request and lasting until the start of execution of the first instruction of the interrupt-service routine, as shown in Figure 2-6. The interrupt logic executes the following: 1. Any currently executing instruction is completed. 2. The PC, which points to the next instruction, is pushed onto the stack. 3. The SR is pushed onto the stack. 4. The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service. 5. The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set for servicing by software. 6. The SR is cleared. This terminates any low-power mode. Because the GIE bit is cleared, further interrupts are disabled. 7. The content of the interrupt vector is loaded into the PC: the program continues with the interrupt service routine at that address. Before Interrupt After Interrupt Item1 Item1 SP Item2 TOS Item2 PC SP SR TOS Figure 2-6. Interrupt Processing SLAU144J – December 2004 – Revised July 2013 System Resets, Interrupts, and Operating Modes 35 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Interrupts www.ti.com 2.2.3.2 Return From Interrupt The interrupt handling routine terminates with the instruction: RETI (return from an interrupt service routine) The return from the interrupt takes 5 cycles (CPU) or 3 cycles (CPUx) to execute the following actions and is illustrated in Figure 2-7. 1. The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are now in effect, regardless of the settings used during the interrupt service routine. 2. The PC pops from the stack and begins execution at the point where it was interrupted. Before After Return From Interrupt Item1 Item1 Item2 SP Item2 TOS PC PC SP SR TOS SR Figure 2-7. Return From Interrupt 2.2.3.3 Interrupt Nesting Interrupt nesting is enabled if the GIE bit is set inside an interrupt service routine. When interrupt nesting is enabled, any interrupt occurring during an interrupt service routine will interrupt the routine, regardless of the interrupt priorities. 36 System Resets, Interrupts, and Operating Modes SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Interrupts 2.2.4 Interrupt Vectors The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h, as described in Table 2-1. A vector is programmed by the user with the 16-bit address of the corresponding interrupt service routine. See the device-specific data sheet for the complete interrupt vector list. It is recommended to provide an interrupt service routine for each interrupt vector that is assigned to a module. A dummy interrupt service routine can consist of just the RETI instruction and several interrupt vectors can point to it. Unassigned interrupt vectors can be used for regular program code if necessary. Some module enable bits, interrupt enable bits, and interrupt flags are located in the SFRs. The SFRs are located in the lower address range and are implemented in byte format. SFRs must be accessed using byte instructions. See the device-specific data sheet for the SFR configuration. Table 2-1. Interrupt Sources, Flags, and Vectors Interrupt Source Power-up, external reset, watchdog, flash password, illegal instruction fetch NMI, oscillator fault, flash memory access violation device-specific device-specific device-specific Watchdog timer device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific device-specific Interrupt Flag PORIFG RSTIFG WDTIFG KEYV NMIIFG OFIFG ACCVIFG WDTIFG System Interrupt Reset (non)-maskable (non)-maskable (non)-maskable maskable Word Address 0FFFEh 0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h 0FFDEh 0FFDCh 0FFDAh 0FFD8h 0FFD6h 0FFD4h 0FFD2h 0FFD0h 0FFCEh 0FFCCh 0FFCAh 0FFC8h 0FFC6h 0FFC4h 0FFC2h 0FFC0h Priority 31, highest 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0, lowest SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback System Resets, Interrupts, and Operating Modes 37 Copyright © 2004–2013, Texas Instruments Incorporated Operating Modes www.ti.com 2.3 Operating Modes The MSP430 family is designed for ultralow-power applications and uses different operating modes shown in Figure 2-9. The operating modes take into account three different needs: • Ultralow-power • Speed and data throughput • Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2-8. ICC/µA at 1 MHz 300 315 270 225 200 180 135 90 55 32 45 0 AM LPM0 VCC = 3 V VCC = 2.2 V 17 11 0.9 0.7 LPM2 LPM3 Operating Modes 0.1 0.1 LPM4 Figure 2-8. Typical Current Consumption of 'F21x1 Devices vs Operating Modes The low-power modes 0 to 4 are configured with the CPUOFF, OSCOFF, SCG0, and SCG1 bits in the status register The advantage of including the CPUOFF, OSCOFF, SCG0, and SCG1 mode-control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine. Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine. Program flow can be returned to a different operating mode by manipulating the saved SR value on the stack inside of the interrupt service routine. The mode-control bits and the stack can be accessed with any instruction. When setting any of the mode-control bits, the selected operating mode takes effect immediately (see Figure 2-9). Peripherals operating with any disabled clock are disabled until the clock becomes active. The peripherals may also be disabled with their individual control register settings. All I/O port pins and RAM/registers are unchanged. Wake up is possible through all enabled interrupts. 38 System Resets, Interrupts, and Operating Modes SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Operating Modes RST/NMI Reset Active SVS_POR WDT Time Expired, Overflow WDT Active, Security Key Violation WDTIFG = 1 WDTIFG = 1 POR WDTIFG = 0 PUC RST/NMI is Reset Pin WDT is Active RST/NMI NMI Active CPUOFF = 1 SCG0 = 0 SCG1 = 0 LPM0 CPU Off, MCLK Off, SMCLK On, ACLK On CPUOFF = 1 SCG0 = 1 SCG1 = 0 LPM1 CPU Off, MCLK Off, DCO off, SMCLK On, ACLK On DC Generator Off if DCO not used for SMCLK Active Mode CPU Is Active Peripheral Modules Are Active CPUOFF = 1 OSCOFF = 1 SCG0 = 1 SCG1 = 1 LPM4 CPU Off, MCLK Off, DCO Off, SMCLK Off, ACLK Off CPUOFF = 1 DC Generator Off CPUOFF = 1 SCG0 = 1 SCG0 = 0 SCG1 = 1 SCG1 = 1 LPM3 CPU Off, MCLK Off, SMCLK LPM2 Off, DCO Off, ACLK On CPU Off, MCLK Off, SMCLK Off, DCO Off, ACLK On DC Generator Off Figure 2-9. Operating Modes For Basic Clock System SCG1 0 0 0 1 1 1 SCG0 0 0 1 0 1 1 Table 2-2. Operating Modes For Basic Clock System OSCOFF 0 0 0 CPUOFF 0 1 1 0 1 0 1 1 1 Mode Active LPM0 LPM1 LPM2 LPM3 LPM4 CPU and Clocks Status CPU is active, all enabled clocks are active CPU, MCLK are disabled, SMCLK, ACLK are active CPU, MCLK are disabled. DCO and DC generator are disabled if the DCO is not used for SMCLK. ACLK is active. CPU, MCLK, SMCLK, DCO are disabled. DC generator remains enabled. ACLK is active. CPU, MCLK, SMCLK, DCO are disabled. DC generator disabled. ACLK is active. CPU and all clocks disabled SLAU144J – December 2004 – Revised July 2013 System Resets, Interrupts, and Operating Modes 39 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Principles for Low-Power Applications www.ti.com 2.3.1 Entering and Exiting Low-Power Modes An enabled interrupt event wakes the MSP430 from any of the low-power operating modes. The program flow is: • Enter interrupt service routine: – The PC and SR are stored on the stack – The CPUOFF, SCG1, and OSCOFF bits are automatically reset • Options for returning from the interrupt service routine: – The original SR is popped from the stack, restoring the previous operating mode. – The SR bits stored on the stack can be modified within the interrupt service routine returning to a different operating mode when the RETI instruction is executed. ; Enter LPM0 Example BIS #GIE+CPUOFF,SR ; Enter LPM0 ; ... ; Program stops here ; ; Exit LPM0 Interrupt Service Routine BIC #CPUOFF,0(SP) ; Exit LPM0 on RETI RETI ; Enter LPM3 Example BIS #GIE+CPUOFF+SCG1+SCG0,SR ; Enter LPM3 ; ... ; Program stops here ; ; Exit LPM3 Interrupt Service Routine BIC #CPUOFF+SCG1+SCG0,0(SP) ; Exit LPM3 on RETI RETI 2.4 Principles for Low-Power Applications Often, the most important factor for reducing power consumption is using the MSP430 clock system to maximize the time in LPM3. LPM3 power consumption is less than 2 µA typical with both a real-time clock function and all interrupts active. A 32-kHz watch crystal is used for the ACLK and the CPU is clocked from the DCO (normally off) which has a 1-µs wake-up. • Use interrupts to wake the processor and control program flow. • Peripherals should be switched on only when needed. • Use low-power integrated peripheral modules in place of software driven functions. For example Timer_A and Timer_B can automatically generate PWM and capture external timing, with no CPU resources. • Calculated branching and fast table look-ups should be used in place of flag polling and long software calculations. • Avoid frequent subroutine and function calls due to overhead. • For longer software routines, single-cycle CPU registers should be used. 40 System Resets, Interrupts, and Operating Modes SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 2.5 Connection of Unused Pins The correct termination of all unused pins is listed in Table 2-3. Connection of Unused Pins Table 2-3. Connection of Unused Pins Pin Potential Comment AVCC AVSS VREF+ VeREF+ VREF-/VeREF- XIN DVCC DVSS Open DVSS DVSS DVCC For dedicated XIN pins only. XIN pins with shared GPIO functions should be programmed to GPIO and follow Px.0 to Px.7 recomendations. XOUT Open For dedicated XOUT pins only. XOUT pins with shared GPIO functions should be programmed to GPIO and follow Px.0 to Px.7 recomendations. XT2IN DVSS For dedicated X2IN pins only. X2IN pins with shared GPIO functions should be programmed to GPIO and follow Px.0 to Px.7 recomendations. XT2OUT Open For dedicated X2OUT pins only. X2OUT pins with shared GPIO functions should be programmed to GPIO and follow Px.0 to Px.7 recomendations. Px.0 to Px.7 Open Switched to port function, output direction or input with pullup/pulldown enabled RST/NMI DVCC or VCC 47 kΩ pullup with 10 nF (2.2 nF(1)) pulldown Test Open 20xx, 21xx, 22xx devices TDO Open TDI Open TMS Open TCK Open (1) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4wire JTAG mode with TI tools like FET interfaces or GANG programmers. SLAU144J – December 2004 – Revised July 2013 System Resets, Interrupts, and Operating Modes 41 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Chapter 3 SLAU144J – December 2004 – Revised July 2013 CPU This chapter describes the MSP430 CPU, addressing modes, and instruction set. Topic ........................................................................................................................... Page 3.1 CPU Introduction ............................................................................................... 43 3.2 CPU Registers .................................................................................................. 44 3.3 Addressing Modes ............................................................................................ 47 3.4 Instruction Set .................................................................................................. 56 42 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com CPU Introduction 3.1 CPU Introduction The CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing, and the use of high-level languages such as C. The CPU can address the complete address range without paging. The CPU features include: • RISC architecture with 27 instructions and 7 addressing modes. • Orthogonal architecture with every instruction usable with every addressing mode. • Full register access including program counter, status registers, and stack pointer. • Single-cycle register operations. • Large 16-bit register file reduces fetches to memory. • 16-bit address bus allows direct access and branching throughout entire memory range. • 16-bit data bus allows direct manipulation of word-wide arguments. • Constant generator provides six most used immediate values and reduces code size. • Direct memory-to-memory transfers without intermediate register holding. • Word and byte addressing and instruction formats. The block diagram of the CPU is shown in Figure 3-1. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 43 CPU Registers MDB − Memory Data Bus Memory Address Bus − MAB 15 0 R0/PC Program Counter 0 R1/SP Stack Pointer 0 R2/SR/CG1 Status R3/CG2 Constant Generator R4 General Purpose R5 General Purpose R6 General Purpose R7 General Purpose R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14 General Purpose R15 General Purpose 16 Zero, Z Carry, C Overflow, V dst src 16−bit ALU Negative, N 16 MCLK www.ti.com Figure 3-1. CPU Block Diagram 3.2 CPU Registers The CPU incorporates sixteen 16-bit registers. R0, R1, R2, and R3 have dedicated functions. R4 to R15 are working registers for general use. 3.2.1 Program Counter (PC) The 16-bit program counter (PC/R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (two, four, or six), and the PC is incremented accordingly. Instruction accesses in the 64-KB address space are performed on word boundaries, and the PC is aligned to even addresses. Figure 3-2 shows the program counter. Figure 3-2. Program Counter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Program Counter Bits 15 to 1 0 44 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com The PC can be addressed with all instructions and addressing modes. A few examples: MOV #LABEL,PC MOV LABEL,PC MOV @R14,PC ; Branch to address LABEL ; Branch to address contained in LABEL ; Branch indirect to address in R14 CPU Registers 3.2.2 Stack Pointer (SP) The stack pointer (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes. Figure 3-3 shows the SP. The SP is initialized into RAM by the user, and is aligned to even addresses. Figure 3-4 shows stack usage. Figure 3-3. Stack Counter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Stack Pointer Bits 15 to 1 0 MOV MOV PUSH POP 2(SP),R6 R7,0(SP) #0123h R8 ; Item I2 -> R6 ; Overwrite TOS with R7 ; Put 0123h onto TOS ; R8 = 0123h Address PUSH #0123h POP R8 0xxxh I1 0xxxh − 2 I2 0xxxh − 4 I3 0xxxh − 6 0xxxh − 8 I1 I2 SP I3 0123h I1 I2 I3 SP SP 0123h Figure 3-4. Stack Usage The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 3-5. PUSH SP POP SP SPold SP1 SP1 SP2 SP1 The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction. instruction. The POP SP instruction places SP1 into the stack pointer SP (SP2=SP1) Figure 3-5. PUSH SP - POP SP Sequence 3.2.3 Status Register (SR) The status register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator. Figure 3-6 shows the SR bits. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 45 CPU Registers 15 14 13 12 11 Reserved rw-0 www.ti.com Figure 3-6. Status Register Bits 10 9 8 7 6 5 4 3 2 1 0 V SCG1 SCG0 OSC OFF CPU OFF GIE N Z C rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table 3-1 describes the status register bits. Bit V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C Table 3-1. Description of Status Register Bits Description Overflow bit. This bit is set when the result of an arithmetic operation overflows the signed-variable range. ADD(.B),ADDC(.B) Set when: Positive + Positive = Negative Negative + Negative = Positive Otherwise reset SUB(.B),SUBC(.B),CMP(.B) Set when: Positive – Negative = Negative Negative – Positive = Positive Otherwise reset System clock generator 1. When set, turns off the SMCLK. System clock generator 0. When set, turns off the DCO dc generator, if DCOCLK is not used for MCLK or SMCLK. Oscillator Off. When set, turns off the LFXT1 crystal oscillator, when LFXT1CLK is not use for MCLK or SMCLK. CPU off. When set, turns off the CPU. General interrupt enable. When set, enables maskable interrupts. When reset, all maskable interrupts are disabled. Negative bit. Set when the result of a byte or word operation is negative and cleared when the result is not negative. Word operation: N is set to the value of bit 15 of the result. Byte operation: N is set to the value of bit 7 of the result. Zero bit. Set when the result of a byte or word operation is 0 and cleared when the result is not 0. Carry bit. Set when the result of a byte or word operation produced a carry and cleared when no carry occurred. 3.2.4 Constant Generator Registers CG1 and CG2 Six commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constants are selected with the source-register addressing modes (As), as described in Table 3-2. Register R2 R2 R2 R2 R3 R3 R3 R3 Table 3-2. Values of Constant Generators CG1, CG2 As Constant 00 ––––– 01 (0) 10 00004h 11 00008h 00 00000h 01 00001h 10 00002h 11 0FFFFh Remarks Register mode Absolute address mode +4, bit processing +8, bit processing 0, word processing +1 +2, bit processing -1, word processing The constant generator advantages are: • No special instructions required • No additional code word for the six constants • No code memory access required to retrieve the constant 46 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as source-only registers. 3.2.4.1 Constant Generator - Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions. However, the constant generator allows the MSP430 assembler to support 24 additional, emulated instructions. For example, the single-operand instruction CLR dst is emulated by the double-operand instruction with the same length: MOV R3,dst where the #0 is replaced by the assembler, and R3 is used with As=00. INC dst is replaced by: ADD 0(R3),dst 3.2.5 General-Purpose Registers R4 to R15 The twelve registers, R4-R15, are general-purpose registers. All of these registers can be used as data registers, address pointers, or index values and can be accessed with byte or word instructions as shown in Figure 3-7. Register-Byte Operation Byte-Register Operation High Byte Unused Low Byte Register High Byte Low Byte Byte Memory Byte Memory 0h Register Figure 3-7. Register-Byte/Byte-Register Operations Example Register-Byte Operation R5 = 0A28Fh R6 = 0203h Mem(0203h) = 012h ADD.B R5,0(R6) 08Fh + 012h 0A1h Mem (0203h) = 0A1h C = 0, Z = 0, N = 1 (Low byte of register) + (Addressed byte) ->(Addressed byte) Example Byte-Register Operation R5 = 01202h R6 = 0223h Mem(0223h) = 05Fh ADD.B @R6,R5 05Fh + 002h 00061h R5 = 00061h C = 0, Z = 0, N = 0 (Addressed byte) + (Low byte of register) ->(Low byte of register, zero to High byte) 3.3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. The bit numbers in Table 3-3 describe the contents of the As (source) and Ad (destination) mode bits. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 47 Addressing Modes As/Ad 00/0 01/1 01/1 01/1 10/11/11/- www.ti.com Table 3-3. Source/Destination Operand Addressing Modes Addressing Mode Register mode Indexed mode Symbolic mode Absolute mode Indirect register mode Indirect autoincrement Immediate mode Syntax Rn X(Rn) ADDR &ADDR @Rn @Rn+ #N Description Register contents are operand (Rn + X) points to the operand. X is stored in the next word. (PC + X) points to the operand. X is stored in the next word. Indexed mode X(PC) is used. The word following the instruction contains the absolute address. X is stored in the next word. Indexed mode X(SR) is used. Rn is used as a pointer to the operand. Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for .B instructions and by 2 for .W instructions. The word following the instruction contains the immediate constant N. Indirect autoincrement mode @PC+ is used. The seven addressing modes are explained in detail in the following sections. Most of the examples show the same addressing mode for the source and destination, but any valid combination of source and destination addressing modes is possible in an instruction. NOTE: Use of Labels EDE, TONI, TOM, and LEO Throughout MSP430 documentation EDE, TONI, TOM, and LEO are used as generic labels. They are only labels. They have no special meaning. 48 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.3.1 Register Mode The register mode is described in Table 3-4. Table 3-4. Register Mode Description Assembler Code MOV R10,R11 Content of ROM MOV R10,R11 Length: Operation: Comment: Example: One or two words Move the content of R10 to R11. R10 is not affected. Valid for source and destination MOV R10,R11 Before: R10 0A023h After: R10 0A023h Addressing Modes R11 0FA15h R11 0A023h PC PCold PC PCold + 2 NOTE: Data in Registers The data in the register can be accessed using word or byte instructions. If byte instructions are used, the high byte is always 0 in the result. The status bits are handled according to the result of the byte instructions. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 49 Addressing Modes 3.3.2 Indexed Mode The indexed mode is described in Table 3-5. Table 3-5. Indexed Mode Description Assembler Code MOV 2(R5),6(R6) Content of ROM MOV X(R5),Y(R6) X=2 Y=6 www.ti.com Length: Operation: Comment: Example: Two or three words Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6). The source and destination registers (R5 and R6) are not affected. In indexed mode, the program counter is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV 2(R5),6(R6); Before: Address Space Register 0FF16h 0FF14h 0FF12h 00006h 00002h 04596h R5 R6 PC 01080h 0108Ch After: Address Space 0xxxxh 0FF16h 00006h 0FF14h 00002h 0FF12h 04596h Register PC R5 01080h R6 0108Ch 01094h 01092h 01090h 0xxxxh 05555h 0xxxxh 0108Ch +0006h 01092h 01094h 01092h 01090h 0xxxxh 01234h 0xxxxh 01084h 01082h 01080h 0xxxxh 01234h 0xxxxh 01080h +0002h 01082h 01084h 01082h 01080h 0xxxxh 01234h 0xxxxh 50 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.3.3 Symbolic Mode The symbolic mode is described in Table 3-6. Table 3-6. Symbolic Mode Description Assembler Code MOV EDE,TONI Content of ROM MOV X(PC),Y(PC) X = EDE – PC Y = TONI – PC Addressing Modes Length: Operation: Comment: Example: Two or three words Move the contents of the source address EDE (contents of PC + X) to the destination address TONI (contents of PC + Y). The words after the instruction contain the differences between the PC and the source or destination addresses. The assembler computes and inserts offsets X and Y automatically. With symbolic mode, the program counter (PC) is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV EDE,TONI ;Source address EDE = 0F016h ;Dest. address TONI = 01114h Before: Address Space Register 0FF16h 0FF14h 0FF12h 011FEh 0F102h 04090h PC After: 0FF16h 0FF14h 0FF12h Address Space 0xxxxh 011FEh 0F102h 04090h Register PC 0F018h 0F016h 0F014h 0xxxxh 0A123h 0xxxxh 0FF14h +0F102h 0F016h 0F018h 0F016h 0F014h 0xxxxh 0A123h 0xxxxh 01116h 01114h 01112h 0xxxxh 05555h 0xxxxh 0FF16h +011FEh 01114h 01116h 01114h 01112h 0xxxxh 0A123h 0xxxxh SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 51 Addressing Modes 3.3.4 Absolute Mode The absolute mode is described in Table 3-7. Table 3-7. Absolute Mode Description Assembler Code MOV &EDE,&TONI Content of ROM MOV X(0),Y(0) X = EDE Y = TONI www.ti.com Length: Operation: Comment: Example: Two or three words Move the contents of the source address EDE to the destination address TONI. The words after the instruction contain the absolute address of the source and destination addresses. With absolute mode, the PC is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV &EDE,&TONI ;Source address EDE = 0F016h ;Dest. address TONI = 01114h Before: Address Space Register 0FF16h 0FF14h 0FF12h 01114h 0F016h 04292h PC After: Address Register Space 0xxxxh PC 0FF16h 01114h 0FF14h 0F016h 0FF12h 04292h 0F018h 0F016h 0F014h 0xxxxh 0A123h 0xxxxh 0F018h 0F016h 0F014h 0xxxxh 0A123h 0xxxxh 01116h 01114h 01112h 0xxxxh 01234h 0xxxxh 01116h 01114h 01112h 0xxxxh 0A123h 0xxxxh This address mode is mainly for hardware peripheral modules that are located at an absolute, fixed address. These are addressed with absolute mode to ensure software transportability (for example, position-independent code). 52 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.3.5 Indirect Register Mode The indirect register mode is described in Table 3-8. Table 3-8. Indirect Mode Description Assembler Code MOV @R10,0(R11) Content of ROM MOV @R10,0(R11) Addressing Modes Length: Operation: Comment: Example: One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11). The registers are not modified. Valid only for source operand. The substitute for destination operand is 0(Rd). MOV.B @R10,0(R11) Before: Address Space 0xxxxh 0FF16 0000h 0FF14hh 04AEBh 0FF12h 0xxxxh Register R10 0FA33h PC R11 002A7h After: Address Space 0xxxxh 0FF16h 0000h 0FF14h 04AEBh 0FF12h 0xxxxh Register PC R10 0FA33h R11 002A7h 0FA34h 0FA32h 0FA30h 0xxxxh 05BC1h 0xxxxh 0FA34h 0xxxxh 0FA32h 05BC1h 0FA30h 0xxxxh 002A8h 002A7h 002A6h 0xxh 012h 0xxh 002A8h 002A7h 002A6h 0xxh 05Bh 0xxh SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 53 Addressing Modes 3.3.6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 3-9. Table 3-9. Indirect Autoincrement Mode Description Assembler Code MOV @R10+,0(R11) Content of ROM MOV @R10+,0(R11) www.ti.com Length: Operation: Comment: Example: One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11). Register R10 is incremented by 1 for a byte operation, or 2 for a word operation after the fetch; it points to the next address without any overhead. This is useful for table processing. Valid only for source operand. The substitute for destination operand is 0(Rd) plus second instruction INCD Rd. MOV @R10+,0(R11) Before: Address Space After: Register Address Space Register 0FF18h 0xxxxh 0FF16h 00000h 0FF14h 04ABBh 0FF12h 0xxxxh R10 PC R11 0FA32h 010A8h 0FF18h 0xxxxh PC 0FF16h 00000h R10 0FA34h 0FF14h 04ABBh R11 010A8h 0FF12h 0xxxxh 0FA34h 0FA32h 0FA30h 0xxxxh 05BC1h 0xxxxh 0FA34h 0xxxxh 0FA32h 05BC1h 0FA30h 0xxxxh 010AAh 010A8h 010A6h 0xxxxh 01234h 0xxxxh 010AAh 0xxxxh 010A8h 05BC1h 010A6h 0xxxxh The auto-incrementing of the register contents occurs after the operand is fetched. This is shown in Figure 3-8. Instruction Address Operand +1/ +2 Figure 3-8. Operand Fetch Operation 54 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.3.7 Immediate Mode The immediate mode is described in Table 3-10. Table 3-10. Immediate Mode Description Assembler Code MOV #45h,TONI Content of ROM MOV @PC+,X(PC) 45 X = TONI – PC Addressing Modes Length: Operation: Comment: Example: Two or three words It is one word less if a constant of CG1 or CG2 can be used. Move the immediate constant 45h, which is contained in the word following the instruction, to destination address TONI. When fetching the source, the program counter points to the word following the instruction and moves the contents to the destination. Valid only for a source operand. MOV #45h,TONI Before: Address Space 0FF16h 0FF14h 0FF12h 01192h 00045h 040B0h PC Register After: 0FF18h 0FF16h 0FF14h 0FF12h Address Space 0xxxxh 01192h 00045h 040B0h Register PC 010AAh 010A8h 010A6h 0xxxxh 01234h 0xxxxh 0FF16h +01192h 010A8h 010AAh 010A8h 010A6h 0xxxxh 00045h 0xxxxh SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 55 Instruction Set www.ti.com 3.4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions. The core instructions are instructions that have unique op-codes decoded by the CPU. The emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automatically by the assembler with an equivalent core instruction. There is no code or performance penalty for using emulated instruction. There are three core-instruction formats: • Dual-operand • Single-operand • Jump All single-operand and dual-operand instructions can be byte or word instructions by using .B or .W extensions. Byte instructions are used to access byte data or byte peripherals. Word instructions are used to access word data or word peripherals. If no extension is used, the instruction is a word instruction. The source and destination of an instruction are defined by the following fields: src dst As S-reg Ad D-reg B/W The source operand defined by As and S-reg The destination operand defined by Ad and D-reg The addressing bits responsible for the addressing mode used for the source (src) The working register used for the source (src) The addressing bits responsible for the addressing mode used for the destination (dst) The working register used for the destination (dst) Byte or word operation: 0: word operation 1: byte operation NOTE: Destination Address Destination addresses are valid anywhere in the memory map. However, when using an instruction that modifies the contents of the destination, the user must ensure the destination address is writable. For example, a masked-ROM location would be a valid destination address, but the contents are not modifiable, so the results of the instruction would be lost. 56 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.1 Double-Operand (Format I) Instructions Figure 3-9 illustrates the double-operand instruction format. Instruction Set 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Op-code S-Reg Ad B/W As D-Reg Figure 3-9. Double Operand Instruction Format Table 3-11 lists and describes the double operand instructions. Mnemonic MOV(.B) ADD(.B) ADDC(.B) SUB(.B) SUBC(.B) CMP(.B) DADD(.B) BIT(.B) BIC(.B) BIS(.B) XOR(.B) AND(.B) Table 3-11. Double Operand Instructions S-Reg, D-Reg src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst Operation src → dst src + dst → dst src + dst + C → dst dst + .not.src + 1 → dst dst + .not.src + C → dst dst - src src + dst + C → dst (decimally) src .and. dst not.src .and. dst → dst src .or. dst → dst src .xor. dst → dst src .and. dst → dst Status Bits V N Z C - - - - * * * * * * * * * * * * * * * * * * * * * * * * 0 * * * - - - - - - - - * * * * 0 * * * * The status bit is affected – The status bit is not affected 0 The status bit is cleared 1 The status bit is set NOTE: Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result. The same is true for the BIT and AND instructions. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 57 Instruction Set 3.4.2 Single-Operand (Format II) Instructions Figure 3-10 illustrates the single-operand instruction format. 15 14 13 12 11 10 9 8 7 6 5 4 3 Op-code B/W Ad Figure 3-10. Single Operand Instruction Format Table 3-12 lists and describes the single operand instructions. Mnemonic RRC(.B) RRA(.B) PUSH(.B) SWPB CALL RETI SXT S-Reg, D-Reg dst dst src dst dst dst Table 3-12. Single Operand Instructions Operation V C → MSB →.......LSB → C * MSB → MSB →....LSB → C 0 SP – 2 → SP, src → @SP - Swap bytes - SP – 2 → SP, PC+2 → @SP - dst → PC TOS → SR, SP + 2 → SP * TOS → PC,SP + 2 → SP Bit 7 → Bit 8........Bit 15 0 www.ti.com 2 1 0 D/S-Reg Status Bits N Z C * * * * * * - - - - - - - - - * * * * * * * The status bit is affected – The status bit is not affected 0 The status bit is cleared 1 The status bit is set All addressing modes are possible for the CALL instruction. If the symbolic mode (ADDRESS), the immediate mode (#N), the absolute mode (&EDE) or the indexed mode x(RN) is used, the word that follows contains the address information. 58 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.3 Jumps Figure 3-11 shows the conditional-jump instruction format. 15 14 13 12 11 10 9 8 7 6 5 4 3 Op-code C 10-Bit PC Offset Figure 3-11. Jump Instruction Format Table 3-13 lists and describes the jump instructions Mnemonic JEQ/JZ JNE/JNZ JC JNC JN JGE JL JMP Table 3-13. Jump Instructions S-Reg, D-Reg Label Label Label Label Label Label Label Label Operation Jump to label if zero bit is set Jump to label if zero bit is reset Jump to label if carry bit is set Jump to label if carry bit is reset Jump to label if negative bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally Instruction Set 2 1 0 Conditional jumps support program branching relative to the PC and do not affect the status bits. The possible jump range is from –511 to +512 words relative to the PC value at the jump instruction. The 10bit program-counter offset is treated as a signed 10-bit value that is doubled and added to the program counter: PCnew = PCold + 2 + PCoffset × 2 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 59 Instruction Set www.ti.com 3.4.4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK. 3.4.4.1 Interrupt and Reset Cycles Table 3-14 lists the CPU cycles for interrupt overhead and reset. Table 3-14. Interrupt and Reset Cycles Action Return from interrupt (RETI) Interrupt accepted WDT reset Reset (RST/NMI) No. of Cycles 5 6 4 4 Length of Instruction 1 - 3.4.4.2 Format-II (Single Operand) Instruction Cycles and Lengths Table 3-15 lists the length and CPU cycles for all addressing modes of format-II instructions. Addressing Mode Rn @Rn @Rn+ #N X(Rn) EDE &EDE Table 3-15. Format-II Instruction Cycles and Lengths RRA, RRC SWPB, SXT 1 3 3 (See note) 4 4 4 No. of Cycles PUSH 3 4 5 4 5 5 5 CALL 4 4 5 5 5 5 5 Length of Instruction 1 1 1 2 2 2 2 Example SWPB R5 RRC @R9 SWPB @R10+ CALL #0F000h CALL 2(R7) PUSH EDE SXT &EDE NOTE: Instruction Format II Immediate Mode Do not use instruction RRA, RRC, SWPB, and SXT with the immediate mode in the destination field. Use of these in the immediate mode results in an unpredictable program operation. 3.4.4.3 Format-III (Jump) Instruction Cycles and Lengths All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not. 60 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Instruction Set 3.4.4.4 Format-I (Double Operand) Instruction Cycles and Lengths Table 3-16 lists the length and CPU cycles for all addressing modes of format-I instructions. Table 3-16. Format 1 Instruction Cycles and Lengths Rn @Rn @Rn+ #N x(Rn) EDE &EDE Addressing Mode Src Dst Rm PC x(Rm) EDE &EDE Rm PC x(Rm) EDE &EDE Rm PC x(Rm) EDE &EDE Rm PC x(Rm) EDE &EDE Rm PC TONI x(Rm) &TONI Rm PC TONI x(Rm) &TONI Rm PC TONI x(Rm) &TONI No. of Cycles 1 2 4 4 4 2 2 5 5 5 2 3 5 5 5 2 3 5 5 5 3 3 6 6 6 3 3 6 6 6 3 3 6 6 6 Length of Instruction 1 MOV 1 BR 2 ADD 2 XOR 2 MOV 1 AND 1 BR 2 XOR 2 MOV 2 XOR 1 ADD 1 BR 2 XOR 2 MOV 2 MOV 2 MOV 2 BR 3 MOV 3 ADD 3 ADD 2 MOV 2 BR 3 MOV 3 ADD 3 MOV 2 AND 2 BR 3 CMP 3 MOV 3 MOV 2 MOV 2 BRA 3 MOV 3 MOV 3 MOV Example R5,R8 R9 R5,4(R6) R8,EDE R5,&EDE @R4,R5 @R8 @R5,8(R6) @R5,EDE @R5,&EDE @R5+,R6 @R9+ @R5,8(R6) @R9+,EDE @R9+,&EDE #20,R9 #2AEh #0300h,0(SP) #33,EDE #33,&EDE 2(R5),R7 2(R6) 4(R7),TONI 4(R4),6(R9) 2(R4),&TONI EDE,R6 EDE EDE,TONI EDE,0(SP) EDE,&TONI &EDE,R8 &EDE &EDE,TONI &EDE,0(SP) &EDE,&TONI SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 61 Instruction Set www.ti.com 3.4.5 Instruction Set Description The instruction map is shown in Figure 3-12 and the complete instruction set is summarized in Table 3-17. 000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0 0xxx 4xxx 8xxx Cxxx 1xxx 14xx RRC RRC.B SWPB RRA RRA.B SXT PUSH PUSH.B CALL RETI 18xx 1Cxx 20xx 24xx 28xx JNE/JNZ JEQ/JZ JNC 2Cxx JC 30xx JN 34xx 38xx 3Cxx JGE JL JMP 4xxx MOV, MOV.B 5xxx 6xxx ADD, ADD.B ADDC, ADDC.B 7xxx SUBC, SUBC.B 8xxx 9xxx Axxx SUB, SUB.B CMP, CMP.B DADD, DADD.B Bxxx BIT, BIT.B Cxxx Dxxx Exxx Fxxx BIC, BIC.B BIS, BIS.B XOR, XOR.B AND, AND.B Figure 3-12. Core Instruction Map Mnemonic ADC(.B) (1) dst ADD(.B) src,dst ADDC(.B) src,dst AND(.B) src,dst BIC(.B) src,dst BIS(.B) src,dst BIT(.B) BR (1) src,dst dst CALL CLR(.B) (1) CLRC (1) CLRN (1) CLRZ (1) dst dst CMP(.B) DADC(.B) (1) src,dst dst DADD(.B) DEC(.B) (1) src,dst dst (1) Emulated Instruction 62 CPU Table 3-17. MSP430 Instruction Set Description VNZC Add C to destination dst + C → dst * * * * Add source to destination src + dst → dst * * * * Add source and C to destination src + dst + C → dst * * * * AND source and destination src .and. dst → dst 0 * * * Clear bits in destination not.src .and. dst → dst - - - - Set bits in destination src .or. dst → dst - - - - Test bits in destination src .and. dst 0 * * * Branch to destination dst → PC - - - - Call destination PC+2 → stack, dst → PC - - - - Clear destination 0 → dst - - - - Clear C 0→C - - - 0 Clear N 0→N - 0 - - Clear Z 0→Z - - 0 - Compare source and destination dst - src * * * * Add C decimally to destination dst + C → dst (decimally) * * * * Add source and C decimally to dst src + dst + C → dst (decimally) * * * * Decrement destination dst - 1 → dst * * * * SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com Mnemonic DECD(.B) (1) dst DINT (1) EINT (1) INC(.B) (1) dst INCD(.B) (1) dst INV(.B) (1) dst JC/JHS label JEQ/JZ label JGE label JL label JMP label JN label JNC/JLO label JNE/JNZ label MOV(.B) NOP (2) POP(.B) (2) src,dst dst PUSH(.B) src RET (2) RETI RLA(.B) (2) dst RLC(.B) (2) dst RRA(.B) dst RRC(.B) SBC(.B) (2) SETC (2) SETN (2) SETZ (2) dst dst SUB(.B) src,dst SUBC(.B) src,dst SWPB dst SXT dst TST(.B) (2) dst XOR(.B) src,dst (2) Emulated Instruction Table 3-17. MSP430 Instruction Set (continued) Description Double-decrement destination dst - 2 → dst Disable interrupts 0 → GIE Enable interrupts 1 → GIE Increment destination dst +1 → dst Double-increment destination dst+2 → dst Invert destination .not.dst → dst Jump if C set/Jump if higher or same Jump if equal/Jump if Z set Jump if greater or equal Jump if less Jump PC + 2 × offset → PC Jump if N set Jump if C not set/Jump if lower Jump if not equal/Jump if Z not set Move source to destination src → dst No operation Pop item from stack to destination @SP → dst, SP+2 → SP Push source onto stack SP - 2 → SP, src → @SP Return from subroutine @SP → PC, SP + 2 → SP Return from interrupt Rotate left arithmetically Rotate left through C Rotate right arithmetically Rotate right through C Subtract not(C) from destination dst + 0FFFFh + C → dst Set C 1→C Set N 1→N Set Z 1→Z Subtract source from destination dst + .not.src + 1 → dst Subtract source and not(C) from dst dst + .not.src + C → dst Swap bytes Extend sign Test destination dst + 0FFFFh + 1 Exclusive OR source and destination src .xor. dst → dst Instruction Set VNZC * * * * - - - - - - - - * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * 0 * * * * * * * * * * * - - - 1 - 1 - - - - 1 - * * * * * * * * - - - - 0 * * * 0* *1 * * * * SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 63 Instruction Set 3.4.6 Instruction Set Details 3.4.6.1 ADC www.ti.com *ADC[.W] *ADC.B Syntax Operation Emulation Description Status Bit Mode Bits Example Example Add carry to destination Add carry to destination ADC dst or ADC.W dst ADC.B dst dst + C → dst ADDC #0,dst ADDC.B #0,dst The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if dst was incremented from 0FFFFh to 0000, reset otherwise Set if dst was incremented from 0FFh to 00, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. The 16-bit counter pointed to by R13 is added to a 32-bit counter pointed to by R12. ADD @R13,0(R12) ; Add LSDs ADC 2(R12) ; Add carry to MSD The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ; Add LSDs ADC.B 1(R12) ; Add carry to MSD 64 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.2 ADD ADD[.W] ADD.B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Add source to destination Add source to destination ADD src,dst or ADD.W src,dst ADD.B src,dst src + dst → dst The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the result, cleared if not V:Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. R5 is increased by 10. The jump to TONI is performed on a carry. ADD #10,R5 JC TONI ...... ; Carry occurred ; No carry R5 is increased by 10. The jump to TONI is performed on a carry. ADD.B #10,R5 JC TONI ...... ; Add 10 to Lowbyte of R5 ; Carry occurred, if (R5) ≥ 246 [0Ah+0F6h] ; No carry SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 65 Instruction Set 3.4.6.3 ADDC www.ti.com ADDC[.W] ADDC.B Syntax Operation Description Status Bits Mode Bits Example Example Add source and carry to destination Add source and carry to destination ADDC src,dst or ADDC.W src,dst ADDC.B src,dst src + dst + C → dst The source operand and the carry bit (C) are added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. The 32-bit counter pointed to by R13 is added to a 32-bit counter, eleven words (20/2 + 2/2) above the pointer in R13. ADD ADDC ... @R13+,20(R13) @R13+,20(R13) ; ADD LSDs with no carry in ; ADD MSDs with carry ; resulting from the LSDs The 24-bit counter pointed to by R13 is added to a 24-bit counter, eleven words above the pointer in R13. ADD.B ADDC.B ADDC.B ... @R13+,10(R13) @R13+,10(R13) @R13+,10(R13) ; ADD LSDs with no carry in ; ADD medium Bits with carry ; ADD MSDs with carry ; resulting from the LSDs 66 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.4 AND AND[.W] AND.B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Source AND destination Source AND destination AND src,dst or AND.W src,dst AND.B src,dst src .AND. dst → dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. N: Set if result MSB is set, reset if not set Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The bits set in R5 are used as a mask (#0AA55h) for the word addressed by TOM. If the result is zero, a branch is taken to label TONI. MOV AND JZ ...... ; ; ; or ; ; AND JZ #0AA55h,R5 R5,TOM TONI #0AA55h,TOM TONI ; Load mask into register R5 ; mask word addressed by TOM with R5 ; ; Result is not zero The bits of mask #0A5h are logically ANDed with the low byte TOM. If the result is zero, a branch is taken to label TONI. AND.B #0A5h,TOM JZ TONI ...... ; mask Lowbyte TOM with 0A5h ; ; Result is not zero SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 67 Instruction Set 3.4.6.5 BIC BIC[.W] BIC.B Syntax Operation Description Status Bits Mode Bits Example Example www.ti.com Clear bits in destination Clear bits in destination BIC src,dst or BIC.W src,dst BIC.B src,dst .NOT.src .AND. dst → dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The six MSBs of the RAM word LEO are cleared. BIC #0FC00h,LEO ; Clear 6 MSBs in MEM(LEO) The five MSBs of the RAM byte LEO are cleared. BIC.B #0F8h,LEO ; Clear 5 MSBs in Ram location LEO 68 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.6 BIS BIS[.W] BIS.B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Set bits in destination Set bits in destination BIS src,dst or BIS.W src,dst BIS.B src,dst src .OR. dst → dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The six LSBs of the RAM word TOM are set. BIS #003Fh,TOM ; set the six LSBs in RAM location TOM The three MSBs of RAM byte TOM are set. BIS.B #0E0h,TOM ; set the 3 MSBs in RAM location TOM SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 69 Instruction Set 3.4.6.7 BIT BIT[.W] BIT.B Syntax Operation Description Status Bits Mode Bits Example Example Example www.ti.com Test bits in destination Test bits in destination BIT src,dst or BIT.W src,dst src .AND. dst The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected. N: Set if MSB of result is set, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT. Zero) V: Reset OSCOFF, CPUOFF, and GIE are not affected. If bit 9 of R8 is set, a branch is taken to label TOM. BIT #0200h,R8 ; bit 9 of R8 set? JNZ TOM ; Yes, branch to TOM ... ; No, proceed If bit 3 of R8 is set, a branch is taken to label TOM. BIT.B #8,R8 JC TOM A serial communication receive bit (RCV) is tested. Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit, the carry bit is used by the subsequent instruction; the read information is shifted into register RECBUF. ; ; Serial communication with LSB is shifted first: ; xxxx xxxx xxxx xxxx BIT.B #RCV,RCCTL ; Bit info into carry RRC RECBUF ; Carry -> MSB of RECBUF ; cxxx xxxx ...... ; repeat previous two instructions ...... ; 8 times ; cccc cccc ;^ ^ ; MSB LSB ; Serial communication with MSB shifted first: BIT.B #RCV,RCCTL ; Bit info into carry RLC.B RECBUF ; Carry -> LSB of RECBUF ; xxxx xxxc ...... ; repeat previous two instructions ...... ; 8 times ; cccc cccc ;| ; MSB LSB 70 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.8 BR, BRANCH Instruction Set *BR, BRANCH Syntax Operation Emulation Description Status Bits Example Branch to .......... destination BR dst dst → PC MOV dst,PC An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. BR #EXEC ; Branch to label EXEC or direct branch (e.g. #0A4h) ; Core instruction MOV @PC+,PC BR EXEC ; Branch to the address contained in EXEC ; Core instruction MOV X(PC),PC ; Indirect address BR &EXEC ; Branch to the address contained in absolute ; address EXEC ; Core instruction MOV X(0),PC ; Indirect address BR R5 ; Branch to the address contained in R5 ; Core instruction MOV R5,PC ; Indirect R5 BR @R5 ; Branch to the address contained in the word ; pointed to by R5. ; Core instruction MOV @R5+,PC ; Indirect, indirect R5 BR @R5+ ; Branch to the address contained in the word pointed ; to by R5 and increment pointer in R5 afterwards. ; The next time--S/W flow uses R5 pointer--it can ; alter program execution due to access to ; next address in a table pointed to by R5 ; Core instruction MOV @R5,PC ; Indirect, indirect R5 with autoincrement BR X(R5) ; Branch to the address contained in the address ; pointed to by R5 + X (e.g. table with address ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 71 Instruction Set 3.4.6.9 CALL www.ti.com CALL Syntax Operation Description Status Bits Example Subroutine CALL dst dst → tmp dst is evaluated and stored SP - 2 → SP PC → @SP PC updated to TOS tmp → PC dst saved to PC A subroutine call is made to an address anywhere in the 64K address space. All addressing modes can be used. The return address (the address of the following instruction) is stored on the stack. The call instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. CALL CALL CALL CALL CALL CALL CALL #EXEC EXEC &EXEC R5 @R5 @R5+ X(R5) ; Call on label EXEC or immediate address (e.g. #0A4h) ; SP-2 -> SP, PC+2 -> @SP, @PC+ -> PC ; Call on the address contained in EXEC ; SP-2 -> SP, PC+2 ->SP, X(PC) -> PC ; Indirect address ; Call on the address contained in absolute address ; EXEC ; SP-2 -> SP, PC+2 -> @SP, X(0) -> PC ; Indirect address ; Call on the address contained in R5 ; SP-2 -> SP, PC+2 -> @SP, R5 -> PC ; Indirect R5 ; Call on the address contained in the word ; pointed to by R5 ; SP-2 -> SP, PC+2 -> @SP, @R5 -> PC ; Indirect, indirect R5 ; Call on the address contained in the word ; pointed to by R5 and increment pointer in R5. ; The next time S/W flow uses R5 pointer ; it can alter the program execution due to ; access to next address in a table pointed to by R5 ; SP-2 -> SP, PC+2 -> @SP, @R5 -> PC ; Indirect, indirect R5 with autoincrement ; Call on the address contained in the address pointed ; to by R5 + X (e.g. table with address starting at X) ; X can be an address or a label ; SP-2 -> SP, PC+2 -> @SP, X(R5) -> PC ; Indirect, indirect R5 + X 72 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.10 CLR *CLR[.W] *CLR.B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destination CLR dst or CLR.W dst CLR.B dst 0 → dst MOV #0,dst MOV.B #0,dst The destination operand is cleared. Status bits are not affected. RAM word TONI is cleared. CLR TONI ; 0 -> TONI Register R5 is cleared. CLR R5 RAM byte TONI is cleared. CLR.B TONI ; 0 -> TONI Instruction Set SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 73 Instruction Set 3.4.6.11 CLRC www.ti.com *CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Clear carry bit CLRC 0→C BIC #1,SR The carry bit (C) is cleared. The clear carry instruction is a word instruction. N: Not affected Z: Not affected C: Cleared V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12. CLRC DADD DADC @R13,0(R12) 2(R12) ; C=0: defines start ; add 16=bit counter to low word of 32=bit counter ; add carry to high word of 32=bit counter 74 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.12 CLRN Instruction Set *CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example Clear negative bit CLRN 0→N or (.NOT.src .AND. dst → dst) BIC #4,SR The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction. N: Reset to 0 Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The Negative bit in the status register is cleared. This avoids special treatment with negative numbers of the subroutine called. SUBR SUBRET CLRN CALL SUBR ...... ...... JN SUBRET ...... ...... ...... RET ; If input is negative: do nothing and return SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 75 Instruction Set 3.4.6.13 CLRZ www.ti.com *CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Clear zero bit CLRZ 0→Z or (.NOT.src .AND. dst → dst) BIC #2,SR The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. N: Not affected Z: Reset to 0 C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The zero bit in the status register is cleared. CLRZ 76 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.14 CMP Instruction Set CMP[.W] CMP.B Syntax Operation Description Status Bits Mode Bits Example Example Example Compare source and destination Compare source and destination CMP src,dst or CMP.W src,dst CMP.B src,dst dst + .NOT.src + 1 or (dst - src) The source operand is subtracted from the destination operand. This is accomplished by adding the 1s complement of the source operand plus 1. The two operands are not affected and the result is not stored; only the status bits are affected. N: Set if result is negative, reset if positive (src ≥ dst) Z: Set if result is zero, reset otherwise (src = dst) C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. R5 and R6 are compared. If they are equal, the program continues at the label EQUAL. CMP R5,R6 ; R5 = R6? JEQ EQUAL ; YES, JUMP Two RAM blocks are compared. If they are not equal, the program branches to the label ERROR. MOV #NUM,R5 MOV #BLOCK1,R6 MOV #BLOCK2,R7 L$1 CMP @R6+,0(R7) JNZ ERROR INCD R7 DEC R5 JNZ L$1 ; number of words to be compared ; BLOCK1 start address in R6 ; BLOCK2 start address in R7 ; Are Words equal? R6 increments ; No, branch to ERROR ; Increment R7 pointer ; Are all words compared? ; No, another compare The RAM bytes addressed by EDE and TONI are compared. If they are equal, the program continues at the label EQUAL. CMP.B EDE,TONI ; MEM(EDE) = MEM(TONI)? JEQ EQUAL ; YES, JUMP SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 77 Instruction Set 3.4.6.15 DADC www.ti.com *DADC[.W] *DADC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Add carry decimally to destination Add carry decimally to destination DADC dst or DADC.W src,dst DADC.B dst dst + C → dst (decimally) DADD #0,dst DADD.B #0,dst The carry bit (C) is added decimally to the destination. N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise C: Set if destination increments from 9999 to 0000, reset otherwise Set if destination increments from 99 to 00, reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The four-digit decimal number contained in R5 is added to an eight-digit decimal number pointed to by R8. CLRC DADD DADC R5,0(R8) 2(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSD The two-digit decimal number contained in R5 is added to a four-digit decimal number pointed to by R8. CLRC DADD.B DADC.B R5,0(R8) 1(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSDs 78 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.16 DADD Instruction Set DADD[.W] DADD.B Syntax Operation Description Status Bits Mode Bits Example Example Source and carry added decimally to destination Source and carry added decimally to destination DADD src,dst or DADD.W src,dst DADD.B src,dst src + dst + C → dst (decimally) The source operand and the destination operand are treated as four binary coded decimals (BCD) with positive signs. The source operand and the carry bit (C)are added decimally to the destination operand. The source operand is not affected. The previous contents of the destination are lost. The result is not defined for non-BCD numbers. N: Set if the MSB is 1, reset otherwise Z: Set if result is zero, reset otherwise C: Set if the result is greater than 9999 Set if the result is greater than 99 V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The eight-digit BCD number contained in R5 and R6 is added decimally to an eight-digit BCD number contained in R3 and R4 (R6 and R4 contain the MSDs). CLRC DADD DADD JC R5,R3 R6,R4 OVERFLOW ; clear carry ; add LSDs ; add MSDs with carry ; If carry occurs go to error handling routine The two-digit decimal counter in the RAM byte CNT is incremented by one. CLRC DADD.B #1,CNT ; clear carry or SETC DADD.B #0,CNT ; equivalent to DADC.B CNT SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 79 Instruction Set 3.4.6.17 DEC *DEC[.W] *DEC.B Syntax Operation Emulation Description Status Bits Mode Bits Example www.ti.com Decrement destination Decrement destination DEC dst or DEC.W dst DEC.B dst dst - 1 → dst SUB #1,dst SUB.B #1,dst The destination operand is decremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08000h, otherwise reset. Set if initial value of destination was 080h, otherwise reset. OSCOFF, CPUOFF,and GIE are not affected. R10 is decremented by 1. DEC R10 ; Decrement R10 ; Move a block of 255 bytes from memory location starting with EDE to memory location starting with ; TONI. Tables should not overlap: start of destination address TONI must not be within the range EDE ; to EDE+0FEh MOV MOV L$1 MOV.B DEC JNZ #EDE,R6 #255,R10 @R6+,TONI-EDE-1(R6) R10 L$1 Do not transfer tables using the routine above with the overlap shown in Figure 3-13. EDE 80 CPU EDE+254 TONI TONI+254 Figure 3-13. Decrement Overlap SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.18 DECD Instruction Set *DECD[.W] *DECD.B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example Double-decrement destination Double-decrement destination DECD dst or DECD.W dst DECD.B dst dst - 2 → dst SUB #2,dst SUB.B #2,dst The destination operand is decremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08001 or 08000h, otherwise reset. Set if initial value of destination was 081 or 080h, otherwise reset. OSCOFF, CPUOFF, and GIE are not affected. R10 is decremented by 2. DECD R10 ; Decrement R10 by two ; Move a block of 255 words from memory location starting with EDE to ; memory location starting with TONI ; Tables should not overlap: start of destination address TONI must not be ; within the range EDE to EDE+0FEh MOV #EDE,R6 MOV #510,R10 L$1 MOV @R6+,TONI-EDE-2(R6) DECD R10 JNZ L$1 Memory at location LEO is decremented by two. DECD.B LEO ; Decrement MEM(LEO) Decrement status byte STATUS by two. DECD.B STATUS SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 81 Instruction Set 3.4.6.19 DINT www.ti.com *DINT Syntax Operation Emulation Description Status Bits Mode Bits Example Disable (general) interrupts DINT 0 → GIE or (0FFF7h .AND. SR → SR / .NOT.src .AND. dst → dst) BIC #8,SR All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR. Status bits are not affected. GIE is reset. OSCOFF and CPUOFF are not affected. The general interrupt enable (GIE) bit in the status register is cleared to allow a nondisrupted move of a 32-bit counter. This ensures that the counter is not modified during the move by any interrupt. DINT NOP MOV MOV EINT COUNTHI,R5 COUNTLO,R6 ; All interrupt events using the GIE bit are disabled ; Copy counter ; All interrupt events using the GIE bit are enabled NOTE: Disable Interrupt If any code sequence needs to be protected from interruption, the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence, or should be followed by a NOP instruction. 82 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.20 EINT Instruction Set *EINT Syntax Operation Emulation Description Status Bits Mode Bits Example Enable (general) interrupts EINT 1 → GIE or (0008h .OR. SR → SR / .src .OR. dst → dst) BIS #8,SR All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR. Status bits are not affected. GIE is set. OSCOFF and CPUOFF are not affected. The general interrupt enable (GIE) bit in the status register is set. ; Interrupt routine of ports P1.2 to P1.7 ; P1IN is the address of the register where all port bits are read. P1IFG is ; the address of the register where all interrupt events are latched. MaskOK PUSH.B BIC.B EINT BIT JEQ ...... BIC ...... INCD RETI &P1IN @SP,&P1IFG #Mask,@SP MaskOK #Mask,@SP SP ; Reset only accepted flags ; Preset port 1 interrupt flags stored on stack ; other interrupts are allowed ; Flags are present identically to mask: jump ; Housekeeping: inverse to PUSH instruction ; at the start of interrupt subroutine. Corrects ; the stack pointer. NOTE: Enable Interrupt The instruction following the enable interrupt instruction (EINT) is always executed, even if an interrupt service request is pending when the interrupts are enable. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 83 Instruction Set 3.4.6.21 INC *INC[.W] *INC.B Syntax Operation Emulation Description Status Bits Mode Bits Example www.ti.com Increment destination Increment destination INC dst or INC.W dst INC.B dst dst + 1 → dst ADD #1,dst The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The status byte, STATUS, of a process is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B CMP.B JEQ STATUS #11,STATUS OVFL 84 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.22 INCD Instruction Set *INCD[.W] *INCD.B Syntax Operation Emulation Example Status Bits Mode Bits Example Example Double-increment destination Double-increment destination INCD dst or INCD.W dst INCD.B dst dst + 2 → dst ADD #2,dst ADD.B #2,dst The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The item on the top of the stack (TOS) is removed without using a register. PUSH R5 ; R5 is the result of a calculation, which is stored ; in the system stack INCD SP ; Remove TOS by double-increment from stack ; Do not use INCD.B, SP is a word-aligned register RET The byte on the top of the stack is incremented by two. INCD.B 0(SP) ; Byte on TOS is increment by two SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 85 Instruction Set 3.4.6.23 INV *INV[.W] *INV.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Invert destination Invert destination INV dst INV.B dst .NOT.dst → dst XOR #0FFFFh,dst XOR.B #0FFh,dst The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. Content of R5 is negated (twos complement). MOV #00AEh,R5 ; INV R5 ; Invert R5, INC R5 ; R5 is now negated, R5 = 000AEh R5 = 0FF51h R5 = 0FF52h Content of memory byte LEO is negated. MOV.B #0AEh,LEO ; MEM(LEO) = 0AEh INV.B LEO ; Invert LEO, MEM(LEO) = 051h INC.B LEO ; MEM(LEO) is negated, MEM(LEO) = 052h www.ti.com 86 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.24 JC, JHS Instruction Set JC JHS Syntax Operation Description Status Bits Example Example Jump if carry set Jump if higher or same JC label JHS label If C = 1: PC + 2 offset → PC If C = 0: execute following instruction The status register carry bit (C) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is reset, the next instruction following the jump is executed. JC (jump if carry/higher or same) is used for the comparison of unsigned numbers (0 to 65536). Status bits are not affected. The P1IN.1 signal is used to define or control the program flow. BIT.B #02h,&P1IN JC PROGA ...... ; State of signal -> Carry ; If carry=1 then execute program routine A ; Carry=0, execute program here R5 is compared to 15. If the content is higher or the same, branch to LABEL. CMP #15,R5 JHS LABEL ...... ; Jump is taken if R5 >= 15 ; Continue here if R5 < 15 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 87 Instruction Set 3.4.6.25 JEQ, JZ www.ti.com JEQ, JZ Syntax Operation Description Status Bits Example Example Example Jump if equal, jump if zero JEQ label JZ label If Z = 1: PC + 2 offset → PC If Z = 0: execute following instruction The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is not set, the instruction following the jump is executed. Status bits are not affected. Jump to address TONI if R7 contains zero. TST R7 JZ TONI ; Test R7 ; if zero: JUMP Jump to address LEO if R6 is equal to the table contents. CMP R6,Table(R5) JEQ LEO ...... ; Compare content of R6 with content of ; MEM (table address + content of R5) ; Jump if both data are equal ; No, data are not equal, continue here Branch to LABEL if R5 is 0. TST R5 JZ LABEL ...... 88 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.26 JGE JGE Syntax Operation Description Status Bits Example Instruction Set Jump if greater or equal JGE label If (N .XOR. V) = 0 then jump to label: PC + 2 P offset → PC If (N .XOR. V) = 1 then execute the following instruction The status register negative bit (N) and overflow bit (V) are tested. If both N and V are set or reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If only one is set, the instruction following the jump is executed. This allows comparison of signed integers. Status bits are not affected. When the content of R6 is greater or equal to the memory pointed to by R7, the program continues at label EDE. CMP @R7,R6 JGE EDE ...... ...... ...... ; R6 >= (R7)?, compare on signed numbers ; Yes, R6 >= (R7) ; No, proceed SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 89 Instruction Set 3.4.6.27 JL JL Syntax Operation Description Status Bits Example www.ti.com Jump if less JL label If (N .XOR. V) = 1 then jump to label: PC + 2 offset → PC If (N .XOR. V) = 0 then execute following instruction The status register negative bit (N) and overflow bit (V) are tested. If only one is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If both N and V are set or reset, the instruction following the jump is executed. This allows comparison of signed integers. Status bits are not affected. When the content of R6 is less than the memory pointed to by R7, the program continues at label EDE. CMP @R7,R6 JL EDE ...... ...... ...... ; R6 < (R7)?, compare on signed numbers ; Yes, R6 < (R7) ; No, proceed 90 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.28 JMP JMP Syntax Operation Description Status Bits Hint Instruction Set Jump unconditionally JMP label PC + 2 × offset → PC The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status bits are not affected. This one-word instruction replaces the BRANCH instruction in the range of –511 to +512 words relative to the current program counter. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 91 Instruction Set 3.4.6.29 JN JN Syntax Operation Description Status Bits Example www.ti.com Jump if negative JN label if N = 1: PC + 2 ×offset → PC if N = 0: execute following instruction The negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If N is reset, the next instruction following the jump is executed. Status bits are not affected. The result of a computation in R5 is to be subtracted from COUNT. If the result is negative, COUNT is to be cleared and the program continues execution in another path. SUB R5,COUNT ; COUNT - R5 -> COUNT JN L$1 ; If negative continue with COUNT=0 at PC=L$1 ...... ; Continue with COUNT>=0 ...... ...... ...... L$1 CLR COUNT ...... ...... ...... 92 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.30 JNC, JLO Instruction Set JNC JLO Syntax Operation Description Status Bits Example Example Jump if carry not set Jump if lower JNC label JLO label if C = 0: PC + 2 offset → PC if C = 1: execute following instruction The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is set, the next instruction following the jump is executed. JNC (jump if no carry/lower) is used for the comparison of unsigned numbers (0 to 65536). Status bits are not affected. The result in R6 is added in BUFFER. If an overflow occurs, an error handling routine at address ERROR is used. ERROR CONT ADD JNC ...... ...... ...... ...... ...... ...... ...... R6,BUFFER CONT ; BUFFER + R6 -> BUFFER ; No carry, jump to CONT ; Error handler start ; Continue with normal program flow Branch to STL2 if byte STATUS contains 1 or 0. CMP.B #2,STATUS JLO STL 2 ...... ; STATUS < 2 ; STATUS >= 2, continue here SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 93 Instruction Set 3.4.6.31 JNE, JNZ www.ti.com JNE JNZ Syntax Operation Description Status Bits Example Jump if not equal Jump if not zero JNE label JNZ label If Z = 0: PC + 2 a offset → PC If Z = 1: execute following instruction The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is set, the next instruction following the jump is executed. Status bits are not affected. Jump to address TONI if R7 and R8 have different contents. CMP R7,R8 JNE TONI ...... ; COMPARE R7 WITH R8 ; if different: jump ; if equal, continue 94 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.32 MOV Instruction Set MOV[.W] MOV.B Syntax Operation Description Status Bits Mode Bits Example Example Move source to destination Move source to destination MOV src,dst or MOV.W src,dst MOV.B src,dst src → dst The source operand is moved to the destination. The source operand is not affected. The previous contents of the destination are lost. Status bits are not affected. OSCOFF, CPUOFF,and GIE are not affected. The contents of table EDE (word data) are copied to table TOM. The length of the tables must be 020h locations. Loop MOV #EDE,R10 MOV #020h,R9 MOV @R10+,TOM-EDE-2(R10) DEC R9 JNZ Loop ...... ...... ...... ; Prepare pointer ; Prepare counter ; Use pointer in R10 for both tables ; Decrement counter ; Counter not 0, continue copying ; Copying completed The contents of table EDE (byte data) are copied to table TOM. The length of the tables should be 020h locations Loop MOV MOV MOV.B #EDE,R10 #020h,R9 @R10+,TOM-EDE-1(R10) DEC R9 JNZ Loop ...... ...... ...... ; Prepare pointer ; Prepare counter ; Use pointer in R10 for ; both tables ; Decrement counter ; Counter not 0, continue ; copying ; Copying completed SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 95 Instruction Set 3.4.6.33 NOP www.ti.com *NOP Syntax Operation Emulation Description Status Bits No operation NOP None MOV #0, R3 No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status bits are not affected. The NOP instruction is mainly used for two purposes: • To fill one, two, or three memory words • To adjust software timing NOTE: Emulating No-Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words. Some examples are: MOV #0,R3 ; 1 cycle, 1 word MOV 0(R4),0(R4) ; 6 cycles, 3 words MOV @R4,0(R4) ; 5 cycles, 2 words BIC #0,EDE(R4) ; 4 cycles, 2 words JMP $+2 ; 2 cycles, 1 word BIC #0,R5 ; 1 cycle, 1 word However, care should be taken when using these examples to prevent unintended results. For example, if MOV 0(R4), 0(R4) is used and the value in R4 is 120h, then a security violation occurs with the watchdog timer (address 120h), because the security key was not used. 96 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.34 POP *POP[.W] *POP.B Syntax Operation Emulation Description Status Bits Example Example Example Example Instruction Set Pop word from stack to destination Pop byte from stack to destination POP dst POP.B dst @SP → temp SP + 2 → SP temp → dst MOV @SP+,dst or MOV.W @SP+,dst MOV.B @SP+,dst The stack location pointed to by the stack pointer (TOS) is moved to the destination. The stack pointer is incremented by two afterwards. Status bits are not affected. The contents of R7 and the status register are restored from the stack. POP R7 POP SR ; Restore R7 ; Restore status register The contents of RAM byte LEO is restored from the stack. POP.B LEO ; The low byte of the stack is moved to LEO. The contents of R7 is restored from the stack. POP.B R7 ; The low byte of the stack is moved to R7, ; the high byte of R7 is 00h The contents of the memory pointed to by R7 and the status register are restored from the stack. POP.B POP 0(R7) SR ; The low byte of the stack is moved to the ; the byte which is pointed to by R7 ; Example: R7 = 203h ; Mem(R7) = low byte of system stack ; Example: R7 = 20Ah ; Mem(R7) = low byte of system stack ; Last word on stack moved to the SR NOTE: The System Stack Pointer The system stack pinter (SP) is always incremented by two, independent of the byte suffix. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 97 Instruction Set 3.4.6.35 PUSH www.ti.com PUSH[.W] PUSH.B Syntax Operation Description Status Bits Mode Bits Example Example Push word onto stack Push byte onto stack PUSH src or PUSH.W src PUSH.B src SP - 2 → SP src → @SP The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS). Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The contents of the status register and R8 are saved on the stack. PUSH SR PUSH R8 ; save status register ; save R8 The contents of the peripheral TCDAT is saved on the stack. PUSH.B &TCDAT ; save data from 8-bit peripheral module, ; address TCDAT, onto stack NOTE: System Stack Pointer The System stack pointer (SP) is always decremented by two, independent of the byte suffix. 98 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.36 RET *RET Syntax Operation Emulation Description Status Bits Instruction Set Return from subroutine RET @SP → PC SP + 2 → SP MOV @SP+,PC The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call. Status bits are not affected. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 99 Instruction Set 3.4.6.37 RETI www.ti.com RETI Syntax Operation Description Status Bits Mode Bits Example Return from interrupt RETI TOS → SR SP + 2 → SP TOS → PC SP + 2 → SP The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two. The program counter is restored to the value at the beginning of interrupt service. This is the consecutive step after the interrupted program flow. Restoration is performed by replacing the present PC contents with the TOS memory contents. The stack pointer (SP) is incremented. N: Restored from system stack Z: Restored from system stack C: Restored from system stack V: Restored from system stack OSCOFF, CPUOFF, and GIE are restored from system stack. Figure 3-14 illustrates the main program interrupt. PC −6 PC −4 PC −2 PC PC +2 PC +4 PC +6 PC +8 Interrupt Request Interrupt Accepted PC+2 is Stored Onto Stack PC = PCi PCi +2 PCi +4 PCi +n−4 PCi +n−2 PCi +n RETI Figure 3-14. Main Program Interrupt 100 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.38 RLA Instruction Set *RLA[.W] *RLA.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Rotate left arithmetically Rotate left arithmetically RLA dst or RLA.W dst RLA.B dst C <- MSB <- MSB-1 .... LSB+1 <- LSB <- 0 ADD dst,dst ADD.B dst,dst The destination operand is shifted left one position as shown in Figure 3-15. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2. An overflow occurs if dst ≥ 04000h and dst < 0C000h before operation is performed: the result has changed sign. Word 15 C Byte 7 0 0 0 Figure 3-15. Destination Operand – Arithmetic Shift Left An overflow occurs if dst ≥ 040h and dst < 0C0h before the operation is performed: the result has changed sign. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF,and GIE are not affected. R7 is multiplied by 2. RLA R7 ; Shift left R7 (x 2) The low byte of R7 is multiplied by 4. RLA.B R7 ; Shift left low byte of R7 (x 2) RLA.B R7 ; Shift left low byte of R7 (x 4) NOTE: RLA Substitution The assembler does not recognize the instruction: RLA @R5+, RLA.B @R5+, or RLA(.B) @R5 It must be substituted by: ADD @R5+,-2(R5), ADD.B @R5+,-1(R5), or ADD(.B) @R5 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 101 Instruction Set 3.4.6.39 RLC *RLC[.W] *RLC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Example www.ti.com Rotate left through carry Rotate left through carry RLC dst or RLC.W dst RLC.B dst C <- MSB <- MSB-1 .... LSB+1 <- LSB <- C ADDC dst,dst The destination operand is shifted left one position as shown in Figure 3-16. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C). Word 15 0 C Byte 7 0 Figure 3-16. Destination Operand - Carry Left Shift N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R5 is shifted left one position. RLC R5 ; (R5 x 2) + C -> R5 The input P1IN.1 information is shifted into the LSB of R5. BIT.B #2,&P1IN ; Information -> Carry RLC R5 ; Carry=P0in.1 -> LSB of R5 The MEM(LEO) content is shifted left one position. RLC.B LEO ; Mem(LEO) x 2 + C -> Mem(LEO) NOTE: RLC and RLC.B Substitution The assembler does not recognize the instruction: RLC @R5+, RLC @R5, or RLC(.B) @R5 It must be substitued by: ADDC @R5+,-2(R5), ADDC.B @R5+,-1(R5), or ADDC(.B) @R5 102 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.40 RRA Instruction Set RRA[.W] RRA.B Syntax Operation Description Status Bits Mode Bits Example Example Rotate right arithmetically Rotate right arithmetically RRA dst or RRA.W dst RRA.B dst MSB → MSB, MSB → MSB-1, ... LSB+1 → LSB, LSB → C The destination operand is shifted right one position as shown in Figure 3-17. The MSB is shifted into the MSB, the MSB is shifted into the MSB-1, and the LSB+1 is shifted into the LSB. Word 15 0 C Byte 7 0 Figure 3-17. Destination Operand – Arithmetic Right Shift N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. R5 is shifted right one position. The MSB retains the old value. It operates equal to an arithmetic division by 2. RRA R5 ; R5/2 -> R5 ; The value in R5 is multiplied by 0.75 (0.5 + 0.25). ; PUSH R5 ; Hold R5 temporarily using stack RRA R5 ; R5 x 0.5 -> R5 ADD @SP+,R5 ; R5 x 0.5 + R5 = 1.5 x R5 -> R5 RRA R5 ; (1.5 x R5) x 0.5 = 0.75 x R5 -> R5 ...... The low byte of R5 is shifted right one position. The MSB retains the old value. It operates equal to an arithmetic division by 2. RRA.B PUSH.B RRA.B ADD.B ...... R5 R5 @SP @SP+,R5 ; R5/2 -> R5: operation is on low byte only ; High byte of R5 is reset ; R5 x 0.5 -> TOS ; TOS x 0.5 = 0.5 x R5 x 0.5 = 0.25 x R5 -> TOS ; R5 x 0.5 + R5 x 0.25 = 0.75 x R5 -> R5 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 103 Instruction Set 3.4.6.41 RRC www.ti.com RRC[.W] RRC.B Syntax Operation Description Status Bits Mode Bits Example Example Rotate right through carry Rotate right through carry RRC dst or RRC.W dst RRC dst C → MSB → MSB-1 .... LSB+1 → LSB → C The destination operand is shifted right one position as shown in Figure 3-18. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C). Word 15 0 C Byte 7 0 Figure 3-18. Destination Operand - Carry Right Shift N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIEare not affected. R5 is shifted right one position. The MSB is loaded with 1. SETC RRC ; Prepare carry for MSB R5 ; R5/2 + 8000h -> R5 R5 is shifted right one position. The MSB is loaded with 1. SETC ; Prepare carry for MSB RRC.B R5 ; R5/2 + 80h -> R5; low byte of R5 is used 104 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.42 SBC *SBC[.W] *SBC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Subtract source and borrow/.NOT. carry from destination Subtract source and borrow/.NOT. carry from destination SBC dst or SBC.W dst SBC.B dst dst + 0FFFFh + C → dst dst + 0FFh + C → dst SUBC #0,dst SUBC.B #0,dst The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, reset otherwise. OSCOFF, CPUOFF,and GIE are not affected. The 16-bit counter pointed to by R13 is subtracted from a 32-bit counter pointed to by R12. SUB @R13,0(R12) ; Subtract LSDs SBC 2(R12) ; Subtract carry from MSD The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUB.B @R13,0(R12) ; Subtract LSDs SBC.B 1(R12) ; Subtract carry from MSD NOTE: Borrow Implementation The borrow is treated as a .NOT. carry: Borrow Yes No Carry bit 0 1 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 105 Instruction Set 3.4.6.43 SETC www.ti.com *SETC Syntax Operation Emulation Description Status Bits Mode Bits Example Set carry bit SETC 1→C BIS #1,SR The carry bit (C) is set. N: Not affected Z: Not affected C: Set V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Emulation of the decimal subtraction: Subtract R5 from R6 decimally Assume that R5 = 03987h and R6 = 04137h DSUB ADD INV SETC DADD #06666h,R5 R5 R5,R6 ; Move content R5 from 0-9 to 6-0Fh ; R5 = 03987h + 06666h = 09FEDh ; Invert this (result back to 0-9) ; R5 = .NOT. R5 = 06012h ; Prepare carry = 1 ; Emulate subtraction by addition of: ; (010000h - R5 - 1) ; R6 = R6 + R5 + 1 ; R6 = 0150h 106 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.44 SETN *SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1→N BIS #4,SR The negative bit (N) is set. N: Set Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Instruction Set SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 107 Instruction Set 3.4.6.45 SETZ *SETZ Syntax Operation Emulation Description Status Bits Mode Bits Set zero bit SETZ 1→Z BIS #2,SR The zero bit (Z) is set. N: Not affected Z: Set C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. www.ti.com 108 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.46 SUB SUB[.W] SUB.B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Subtract source from destination Subtract source from destination SUB src,dst or SUB.W src,dst SUB.B src,dst dst + .NOT.src + 1 → dst or [(dst - src → dst)] The source operand is subtracted from the destination operand by adding the source operand's 1s complement and the constant 1. The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. See example at the SBC instruction. See example at the SBC.B instruction. NOTE: Borrow Is Treated as a .NOT. The borrow is treated as a .NOT. carry: Borrow Yes No Carry bit 0 1 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 109 Instruction Set 3.4.6.47 SUBC, SBB www.ti.com SUBC[.W], SBB[.W] SUBC.B, SBB.B Syntax Operation Description Status Bits Mode Bits Example Example Subtract source and borrow/.NOT. carry from destination Subtract source and borrow/.NOT. carry from destination SUBC src,dst or SUBC.W src,dst or SBB src,dst or SBB.W src,dst SUBC.B src,dst or SBB.B src,dst dst + .NOT.src + C → dst or (dst - src - 1 + C → dst) The source operand is subtracted from the destination operand by adding the source operand's 1s complement and the carry bit (C). The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive. Z: Set if result is zero, reset otherwise. C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, reset otherwise. OSCOFF, CPUOFF, and GIE are not affected. Two floating point mantissas (24 bits) are subtracted. LSBs are in R13 and R10, MSBs are in R12 and R9. SUB.W R13,R10 SUBC.B R12,R9 ; 16-bit part, LSBs ; 8-bit part, MSBs The 16-bit counter pointed to by R13 is subtracted from a 16-bit counter in R10 and R11(MSD). SUB.B SUBC.B ... @R13+,R10 @R13,R11 ; Subtract LSDs without carry ; Subtract MSDs with carry ; resulting from the LSDs NOTE: Borrow Implementation The borrow is treated as a .NOT. carry: Borrow Yes No Carry bit 0 1 110 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.48 SWPB Instruction Set SWPB Syntax Operation Description Mode Bits Swap bytes SWPB dst Bits 15 to 8 ↔ bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure 3-19. OSCOFF, CPUOFF, and GIE are not affected. 15 87 0 Example Example Figure 3-19. Destination Operand - Byte Swap MOV #040BFh,R7 ; 0100000010111111 -> R7 SWPB R7 ; 1011111101000000 in R7 The value in R5 is multiplied by 256. The result is stored in R5,R4. SWPB MOV BIC BIC R5 R5,R4 #0FF00h,R5 #00FFh,R4 ; ; Copy the swapped value to R4 ; Correct the result ; Correct the result SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 111 Instruction Set 3.4.6.49 SXT SXT Syntax Operation Description Status Bits Mode Bits www.ti.com Extend Sign SXT dst Bit 7 → Bit 8 ......... Bit 15 The sign of the low byte is extended into the high byte as shown in Figure 3-20. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (.NOT. Zero) V: Reset OSCOFF, CPUOFF, and GIE are not affected. 15 87 0 Example Figure 3-20. Destination Operand - Sign Extension R7 is loaded with the P1IN value. The operation of the sign-extend instruction expands bit 8 to bit 15 with the value of bit 7. R7 is then added to R6. MOV.B &P1IN,R7 ; P1IN = 080h: SXT R7 ; R7 = 0FF80h: .... .... 1000 0000 1111 1111 1000 0000 112 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.4.6.50 TST *TST[.W] *TST.B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Test destination Test destination TST dst or TST.W dst TST.B dst dst + 0FFFFh + 1 dst + 0FFh + 1 CMP #0,dst CMP.B #0,dst The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TST JN JZ ...... ...... ...... R7 R7NEG R7ZERO ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TST.B JN JZ ...... ..... ...... R7 R7NEG R7ZERO ; Test low byte of R7 ; Low byte of R7 is negative ; Low byte of R7 is zero ; Low byte of R7 is positive but not zero ; Low byte of R7 is negative ; Low byte of R7 is zero SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPU 113 Instruction Set 3.4.6.51 XOR www.ti.com XOR[.W] XOR.B Syntax Operation Description Status Bits Mode Bits Example Example Example Exclusive OR of source with destination Exclusive OR of source with destination XOR src,dst or XOR.W src,dst XOR.B src,dst src .XOR. dst → dst The source and destination operands are exclusive ORed. The result is placed into the destination. The source operand is not affected. N: Set if result MSB is set, reset if not set Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if both operands are negative OSCOFF, CPUOFF,and GIE are not affected. The bits set in R6 toggle the bits in the RAM word TONI. XOR R6,TONI ; Toggle bits of word TONI on the bits set in R6 The bits set in R6 toggle the bits in the RAM byte TONI. XOR.B R6,TONI ; Toggle bits of byte TONI on the bits set in ; low byte of R6 Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE. XOR.B EDE,R7 ; Set different bit to "1s" INV.B R7 ; Invert Lowbyte, Highbyte is 0h 114 CPU SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 4 SLAU144J – December 2004 – Revised July 2013 CPUX This chapter describes the extended MSP430X 16-bit RISC CPU with 1-MB memory access, its addressing modes, and instruction set. The MSP430X CPU is implemented in all MSP430 devices that exceed 64-KB of address space. Topic ........................................................................................................................... Page 4.1 CPU Introduction ............................................................................................. 116 4.2 Interrupts ........................................................................................................ 118 4.3 CPU Registers ................................................................................................. 119 4.4 Addressing Modes ........................................................................................... 125 4.5 MSP430 and MSP430X Instructions ................................................................... 142 4.6 Instruction Set Description ............................................................................... 160 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 115 CPU Introduction www.ti.com 4.1 CPU Introduction The MSP430X CPU incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as C. The MSP430X CPU can address a 1-MB address range without paging. In addition, the MSP430X CPU has fewer interrupt overhead cycles and fewer instruction cycles in some cases than the MSP430 CPU, while maintaining the same or better code density than the MSP430 CPU. The MSP430X CPU is backward compatible with the MSP430 CPU. The MSP430X CPU features include: • RISC architecture • Orthogonal architecture • Full register access including program counter, status register and stack pointer • Single-cycle register operations • Large register file reduces fetches to memory • 20-bit address bus allows direct access and branching throughout the entire memory range without paging • 16-bit data bus allows direct manipulation of word-wide arguments • Constant generator provides the six most often used immediate values and reduces code size • Direct memory-to-memory transfers without intermediate register holding • Byte, word, and 20-bit address-word addressing The block diagram of the MSP430X CPU is shown in Figure 4-1. 116 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MDB - Memor y Data Bus Memory Address Bus - MAB 19 16 15 0 R0/PC Program Counter 0 R1/SP Pointer Stack 0 R2/SR Status Register R3/CG2 Constant Generator R4 General Purpose R5 General Purpose R6 General Purpose R7 General Purpose R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14 General Purpose R15 General Purpose 16 Zero, Z Carry, C Overflow,V dst src 16/20-bit ALU Negative,N 20 MCLK Figure 4-1. MSP430X CPU Block Diagram CPU Introduction SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 117 Interrupts www.ti.com 4.2 Interrupts The MSP430X uses the same interrupt structure as the MSP430: • Vectored interrupts with no polling necessary • Interrupt vectors are located downward from address 0FFFEh Interrupt operation for both MSP430 and MSP430X CPUs is described in Chapter 2 System Resets, Interrupts, and Operating modes, Section 2 Interrupts. The interrupt vectors contain 16-bit addresses that point into the lower 64-KB memory. This means all interrupt handlers must start in the lower 64-KB memory, even in MSP430X devices. During an interrupt, the program counter and the status register are pushed onto the stack as shown in Figure 4-2. The MSP430X architecture efficiently stores the complete 20-bit PC value by automatically appending the PC bits 19:16 to the stored SR value on the stack. When the RETI instruction is executed, the full 20-bit PC is restored making return from interrupt to any address in the memory range possible. SP old SP Item n-1 PC.15:0 PC.19:16 SR.11:0 Figure 4-2. PC Storage on the Stack for Interrupts 118 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com CPU Registers 4.3 CPU Registers The CPU incorporates 16 registers (R0 through R15). Registers R0, R1, R2, and R3 have dedicated functions. Registers R4 through R15 are working registers for general use. 4.3.1 Program Counter (PC) The 20-bit PC (PC/R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (2, 4, 6, or 8 bytes), and the PC is incremented accordingly. Instruction accesses are performed on word boundaries, and the PC is aligned to even addresses. Figure 4-3 shows the PC. 19 16 15 10 Program Counter Bits 19 to 1 0 Figure 4-3. Program Counter The PC can be addressed with all instructions and addressing modes. A few examples: MOV.W #LABEL,PC ; Branch to address LABEL (lower 64KB) MOVA #LABEL,PC ; Branch to address LABEL (1MB memory) MOV.W LABEL,PC ; Branch to address in word LABEL ; (lower 64KB) MOV.W @R14,PC ; Branch indirect to address in ; R14 (lower 64KB) ADDA #4,PC ; Skip two words (1MB memory) The BR and CALL instructions reset the upper four PC bits to 0. Only addresses in the lower 64-KB address range can be reached with the BR or CALL instruction. When branching or calling, addresses beyond the lower 64-KB range can only be reached using the BRA or CALLA instructions. Also, any instruction to directly modify the PC does so according to the used addressing mode. For example, MOV.W #value,PC clears the upper four bits of the PC, because it is a .W instruction. The PC is automatically stored on the stack with CALL (or CALLA) instructions and during an interrupt service routine. Figure 4-4 shows the storage of the PC with the return address after a CALLA instruction. A CALL instruction stores only bits 15:0 of the PC. SP old SP Item n PC.19:16 PC.15:0 Figure 4-4. PC Storage on the Stack for CALLA The RETA instruction restores bits 19:0 of the PC and adds 4 to the stack pointer (SP). The RET instruction restores bits 15:0 to the PC and adds 2 to the SP. 4.3.2 Stack Pointer (SP) The 20-bit SP (SP/R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes. Figure 4-5 shows the SP. The SP is initialized into RAM by the user, and is always aligned to even addresses. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 119 CPU Registers www.ti.com Figure 4-6 shows the stack usage. Figure 4-7 shows the stack usage when 20-bit address words are pushed. 19 10 Stack Pointer Bits 19 to 1 0 MOV.W MOV.W PUSH POP 2(SP),R6 R7,0(SP) #0123h R8 ; Copy Item I2 to R6 ; Overwrite TOS with R7 ; Put 0123h on stack ; R8 = 0123h Figure 4-5. Stack Pointer Address PUSH #0123h POP R8 0xxxh I1 I1 I1 0xxxh - 2 I2 I2 I2 0xxxh - 4 I3 SP I3 I3 SP 0xxxh - 6 0123h SP 0xxxh - 8 Figure 4-6. Stack Usage SP old SP Item n-1 Item.19:16 Item.15:0 Figure 4-7. PUSHX.A Format on the Stack The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 4-8. PUSH SP POP SP SPold SP1 SPold SP2 SP1 The stack pointer is changed after a PUSH SP instruction. The stack pointer is not changed after a POP SP instruction. The POP SP instruction places SP1 into the stack pointer SP (SP2 = SP1) Figure 4-8. PUSH SP, POP SP Sequence 120 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com CPU Registers 4.3.3 Status Register (SR) The 16-bit SR (SR/R2), used as a source or destination register, can only be used in register mode addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator. Figure 4-9 shows the SR bits. Do not write 20-bit values to the SR. Unpredictable operation can result. 15 Reserved 98 7 0 OSC CPU V SCG1 SCG0 OFF OFF GIE N Z C rw-0 Figure 4-9. SR Bits Table 4-1 describes the SR bits. Table 4-1. SR Bit Description Bit Reserved V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C Description Reserved Overflow. This bit is set when the result of an arithmetic operation overflows the signed-variable range. ADD(.B), ADDX(.B,.A), ADDC(.B), ADDCX(.B.A), ADDA Set when: positive + positive = negative negative + negative = positive otherwise reset SUB(.B), SUBX(.B,.A), SUBC(.B), SUBCX(.B,.A), SUBA, CMP(.B), CMPX(.B,.A), CMPA Set when: positive – negative = negative negative – positive = positive otherwise reset System clock generator 1. This bit may be to enable/disable functions in the clock system depending on the device family; for example, DCO bias enable/disable System clock generator 0. This bit may be used to enable/disable functions in the clock system depending on the device family; for example, FLL disable/enable Oscillator off. This bit, when set, turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or SMCLK. CPU off. This bit, when set, turns off the CPU. General interrupt enable. This bit, when set, enables maskable interrupts. When reset, all maskable interrupts are disabled. Negative. This bit is set when the result of an operation is negative and cleared when the result is positive. Zero. This bit is set when the result of an operation is 0 and cleared when the result is not 0. Carry. This bit is set when the result of an operation produced a carry and cleared when no carry occurred. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 121 CPU Registers www.ti.com 4.3.4 Constant Generator Registers (CG1 and CG2) Six commonly-used constants are generated with the constant generator registers R2 (CG1) and R3 (CG2), without requiring an additional 16-bit word of program code. The constants are selected with the source register addressing modes (As), as described in Table 4-2. Table 4-2. Values of Constant Generators CG1, CG2 Register As R2 00 R2 01 R2 10 R2 11 R3 00 R3 01 R3 10 R3 11 Constant – (0) 00004h 00008h 00000h 00001h 00002h FFh, FFFFh, FFFFFh Remarks Register mode Absolute address mode +4, bit processing +8, bit processing 0, word processing +1 +2, bit processing –1, word processing The constant generator advantages are: • No special instructions required • No additional code word for the six constants • No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as source-only registers. 4.3.4.1 Constant Generator – Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions. However, the constant generator allows the MSP430 assembler to support 24 additional emulated instructions. For example, the single-operand instruction: CLR dst is emulated by the double-operand instruction with the same length: MOV R3,dst where the #0 is replaced by the assembler, and R3 is used with As = 00. INC dst is replaced by: ADD #1,dst 122 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com CPU Registers 4.3.5 General-Purpose Registers (R4 to R15) The 12 CPU registers (R4 to R15) contain 8-bit, 16-bit, or 20-bit values. Any byte-write to a CPU register clears bits 19:8. Any word-write to a register clears bits 19:16. The only exception is the SXT instruction. The SXT instruction extends the sign through the complete 20-bit register. The following figures show the handling of byte, word, and address-word data. Note the reset of the leading most significant bits (MSBs) if a register is the destination of a byte or word instruction. Figure 4-10 shows byte handling (8-bit data, .B suffix). The handling is shown for a source register and a destination memory byte and for a source memory byte and a destination register. Register-Byte Operation High Byte Low Byte 19 16 15 87 0 Unused Unused Register Byte-Register Operation High Byte Low Byte Memory Memory 19 16 15 87 Un- Unused used 0 Register Operation Operation Memory 0 0 Register Figure 4-10. Register-Byte/Byte-Register Operation Figure 4-11 and Figure 4-12 show 16-bit word handling (.W suffix). The handling is shown for a source register and a destination memory word and for a source memory word and a destination register. Register-Word Operation High Byte Low Byte 19 16 15 87 0 Unused Register Memory Operation Memory Figure 4-11. Register-Word Operation SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 123 CPU Registers Word-Register Operation High Byte Low Byte Memory 19 16 15 87 Un- used 0 Register Operation www.ti.com 0 Register Figure 4-12. Word-Register Operation Figure 4-13 and Figure 4-14 show 20-bit address-word handling (.A suffix). The handling is shown for a source register and a destination memory address-word and for a source memory address-word and a destination register. Register - Ad dress-Word Operation High Byte Low Byte 19 16 15 87 0 Register Memory +2 Unused Memory Operation Memory +2 0 Memory Figure 4-13. Register – Address-Word Operation 124 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Memory +2 Address-Word - Register Operation High Byte Low Byte 19 16 15 87 0 Unused Memory Addressing Modes Register Operation Register Figure 4-14. Address-Word – Register Operation 4.4 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand use 16-bit or 20-bit addresses (see Table 4-3). The MSP430 and MSP430X instructions are usable throughout the entire 1MB memory range. As/Ad Addressing Mode 00/0 Register 01/1 Indexed 01/1 Symbolic 01/1 Absolute 10/– Indirect Register 11/– Indirect Autoincrement 11/– Immediate Table 4-3. Source/Destination Addressing Syntax Rn X(Rn) ADDR &ADDR @Rn @Rn+ #N Description Register contents are operand. (Rn + X) points to the operand. X is stored in the next word, or stored in combination of the preceding extension word and the next word. (PC + X) points to the operand. X is stored in the next word, or stored in combination of the preceding extension word and the next word. Indexed mode X(PC) is used. The word following the instruction contains the absolute address. X is stored in the next word, or stored in combination of the preceding extension word and the next word. Indexed mode X(SR) is used. Rn is used as a pointer to the operand. Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for .B instructions. by 2 for .W instructions, and by 4 for .A instructions. N is stored in the next word, or stored in combination of the preceding extension word and the next word. Indirect autoincrement mode @PC+ is used. The seven addressing modes are explained in detail in the following sections. Most of the examples show the same addressing mode for the source and destination, but any valid combination of source and destination addressing modes is possible in an instruction. NOTE: Use of Labels EDE, TONI, TOM, and LEO Throughout MSP430 documentation, EDE, TONI, TOM, and LEO are used as generic labels. They are only labels and have no special meaning. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 125 Addressing Modes 4.4.1 Register Mode www.ti.com Operation: Length: Comment: Byte operation: Word operation: Address-word operation: SXT exception: Example: The operand is the 8-, 16-, or 20-bit content of the used CPU register. One, two, or three words Valid for source and destination Byte operation reads only the eight least significant bits (LSBs) of the source register Rsrc and writes the result to the eight LSBs of the destination register Rdst. The bits Rdst.19:8 are cleared. The register Rsrc is not modified. Word operation reads the 16 LSBs of the source register Rsrc and writes the result to the 16 LSBs of the destination register Rdst. The bits Rdst.19:16 are cleared. The register Rsrc is not modified. Address-word operation reads the 20 bits of the source register Rsrc and writes the result to the 20 bits of the destination register Rdst. The register Rsrc is not modified The SXT instruction is the only exception for register operation. The sign of the low byte in bit 7 is extended to the bits Rdst.19:8. BIS.W R5,R6 ; This instruction logically ORs the 16-bit data contained in R5 with the 16-bit contents of R6. R6.19:16 is cleared. Before: Address Space Register After: Address Space Register 21036h xxxxh R5 AA550h 21034h D506h PC R6 11111h 21036h 21034h xxxxh D506h PC R5 AA550h R6 0B551h Example: BISX.A R5,R6 ; A550h.or.1111h = B551h This instruction logically ORs the 20-bit data contained in R5 with the 20-bit contents of R6. The extension word contains the A/L bit for 20-bit data. The instruction word uses byte mode with bits A/L:B/W = 01. The result of the instruction is: Before: Address Space Register After: Address Space Register 21036h xxxxh R5 AA550h 21034h D546h R6 11111h 21032h 1800h PC 21036h xxxxh 21034h D546h 21032h 1800h PC R5 AA550h R6 BB551h AA550h.or.11111h = BB551h 126 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes 4.4.2 Indexed Mode The Indexed mode calculates the address of the operand by adding the signed index to a CPU register. The Indexed mode has three addressing possibilities: • Indexed mode in lower 64-KB memory • MSP430 instruction with Indexed mode addressing memory above the lower 64-KB memory • MSP430X instruction with Indexed mode 4.4.2.1 Indexed Mode in Lower 64-KB Memory If the CPU register Rn points to an address in the lower 64KB of the memory range, the calculated memory address bits 19:16 are cleared after the addition of the CPU register Rn and the signed 16-bit index. This means the calculated memory address is always located in the lower 64KB and does not overflow or underflow out of the lower 64-KB memory space. The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4-15. FFFFF Lower 64 KB Rn.19:16 = 0 19 16 15 0 0 CPU Register Rn 10000 0FFFF Rn.19:0 S 16-bit byte index 16-bit signed index 16-bit signed add Lower 64KB 00000 0 Memory address Figure 4-15. Indexed Mode in Lower 64KB Length: Operation: Comment: Example: Source: Destination: Two or three words The signed 16-bit index is located in the next word after the instruction and is added to the CPU register Rn. The resulting bits 19:16 are cleared giving a truncated 16-bit memory address, which points to an operand address in the range 00000h to 0FFFFh. The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the register index and inserts it. ADD.B 1000h(R5),0F000h(R6); This instruction adds the 8-bit data contained in source byte 1000h(R5) and the destination byte 0F000h(R6) and places the result into the destination byte. Source and destination bytes are both located in the lower 64KB due to the cleared bits 19:16 of registers R5 and R6. The byte pointed to by R5 + 1000h results in address 0479Ch + 1000h = 0579Ch after truncation to a 16-bit address. The byte pointed to by R6 + F000h results in address 01778h + F000h = 00778h after truncation to a 16-bit address. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 127 Addressing Modes Before: Address Space Register After: Address Space Register 1103Ah 11038h 11036h 11034h xxxxh F000h 1000h 55D6h R5 0479Ch R6 01778h PC 1103Ah 11038h 11036h 11034h xxxxh F000h 1000h 55D6h PC R5 0479Ch R6 01778h 0077Ah 00778h xxxxh xx45h 01778h +F000h 00778h 0077Ah 00778h xxxxh xx77h 32h +45h 77h src dst Sum www.ti.com 0579Eh 0579Ch xxxxh xx32h 0479Ch +1000h 0579Ch 0579Eh 0579Ch xxxxh xx32h 4.4.2.2 MSP430 Instruction With Indexed Mode in Upper Memory If the CPU register Rn points to an address above the lower 64-KB memory, the Rn bits 19:16 are used for the address calculation of the operand. The operand may be located in memory in the range Rn ±32KB, because the index, X, is a signed 16-bit value. In this case, the address of the operand can overflow or underflow into the lower 64-KB memory space (see Figure 4-16 and Figure 4-17). FFFFF Upper Memory Rn.19:16 > 0 19 16 15 1 ... 15 0 CPU Register Rn Rn.19:0 Rn ± 32 KB 10000 0FFFF S S 16-bit byte index 16-bit signed index (sign extended to 20 bits) 20-bit signed add Lower 64 KB 00000 Memory address Figure 4-16. Indexed Mode in Upper Memory 128 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes FFFFF Rn.19:0 Rn.19:0 ±32 KB ±32 KB Lower 64 KB 10000 0,FFFF Rn.19:0 Rn.19:0 0000C Figure 4-17. Overflow and Underflow for Indexed Mode Length: Operation: Comment: Example: Source: Destination: Two or three words The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the CPU register Rn. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh. The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the register index and inserts it. ADD.W 8346h(R5),2100h(R6) ; This instruction adds the 16-bit data contained in the source and the destination addresses and places the 16-bit result into the destination. Source and destination operand can be located in the entire address range. The word pointed to by R5 + 8346h. The negative index 8346h is sign extended, which results in address 23456h + F8346h = 1B79Ch. The word pointed to by R6 + 2100h results in address 15678h + 2100h = 17778h. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 129 Addressing Modes Before: Address Space Register After: Address Space Register 1103Ah 11038h 11036h 11034h xxxxh 2100h 8346h 5596h R5 23456h R6 15678h PC 1103Ah 11038h 11036h 11034h xxxxh 2100h 8346h 5596h PC R5 23456h R6 15678h 1777Ah 17778h xxxxh 2345h 15678h +02100h 17778h 1777Ah 17778h xxxxh 7777h 05432h +02345h 07777h src dst Sum www.ti.com 1B79Eh 1B79Ch xxxxh 5432h 23456h +F8346h 1B79Ch 1B79Eh 1B79Ch xxxxh 5432h 4.4.2.3 MSP430X Instruction With Indexed Mode When using an MSP430X instruction with Indexed mode, the operand can be located anywhere in the range of Rn + 19 bits. Length: Operation: Comment: Example: Source: Destination: Three or four words The operand address is the sum of the 20-bit CPU register content and the 20-bit index. The 4 MSBs of the index are contained in the extension word; the 16 LSBs are contained in the word following the instruction. The CPU register is not modified Valid for source and destination. The assembler calculates the register index and inserts it. ADDX.A 12346h(R5),32100h(R6) ; This instruction adds the 20-bit data contained in the source and the destination addresses and places the result into the destination. Two words pointed to by R5 + 12346h which results in address 23456h + 12346h = 3579Ch. Two words pointed to by R6 + 32100h which results in address 45678h + 32100h = 77778h. 130 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes The extension word contains the MSBs of the source index and of the destination index and the A/L bit for 20-bit data. The instruction word uses byte mode due to the 20-bit data length with bits A/L:B/W = 01. Before: Address Space Register After: Address Space Register 2103Ah 21038h 21036h 21034h 21032h xxxxh 2100h 2346h 55D6h 1883h R5 23456h R6 45678h PC 2103Ah 21038h 21036h 21034h 21032h xxxxh 2100h 2346h 55D6h 1883h PC R5 23456h R6 45678h 7777Ah 77778h 0001h 2345h 45678h +32100h 77778h 7777Ah 77778h 0007h 7777h 65432h +12345h 77777h src dst Sum 3579Eh 3579Ch 0006h 5432h 23456h +12346h 3579Ch 3579Eh 3579Ch 0006h 5432h 4.4.3 Symbolic Mode The Symbolic mode calculates the address of the operand by adding the signed index to the PC. The Symbolic mode has three addressing possibilities: • Symbolic mode in lower 64-KB memory • MSP430 instruction with Symbolic mode addressing memory above the lower 64-KB memory. • MSP430X instruction with Symbolic mode 4.4.3.1 Symbolic Mode in Lower 64KB If the PC points to an address in the lower 64KB of the memory range, the calculated memory address bits 19:16 are cleared after the addition of the PC and the signed 16-bit index. This means the calculated memory address is always located in the lower 64KB and does not overflow or underflow out of the lower 64-KB memory space. The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4-18. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 131 Addressing Modes FFFFF Lower 64 KB PC.19:16 = 0 19 16 15 0 0 Program counter PC www.ti.com 10000 0FFFF PC.19:0 S 16-bit byte index 16-bit signed PC index 16-bit signed add Lower 64 KB 00000 0 Memory address Figure 4-18. Symbolic Mode Running in Lower 64KB Operation: Length: Comment: Example: Source: Destination: The signed 16-bit index in the next word after the instruction is added temporarily to the PC. The resulting bits 19:16 are cleared giving a truncated 16-bit memory address, which points to an operand address in the range 00000h to 0FFFFh. The operand is the content of the addressed memory location. Two or three words Valid for source and destination. The assembler calculates the PC index and inserts it. ADD.B EDE,TONI ; This instruction adds the 8-bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI. Bytes EDE and TONI and the program are located in the lower 64KB. Byte EDE located at address 0579Ch, pointed to by PC + 4766h, where the PC index 4766h is the result of 0579Ch – 01036h = 04766h. Address 01036h is the location of the index for this example. Byte TONI located at address 00778h, pointed to by PC + F740h, is the truncated 16-bit result of 00778h – 1038h = FF740h. Address 01038h is the location of the index for this example. 132 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Before: Address Space 0103Ah 01038h 01036h 01034h xxxxh F740h 4766h 05D0h PC After: Address Space 0103Ah 01038h 01036h 01034h xxxxh PC F740h 4766h 50D0h Addressing Modes 0077Ah 00778h xxxxh xx45h 01038h +0F740h 00778h 0077Ah 00778h xxxxh xx77h 32h +45h 77h src dst Sum 0579Eh 0579Ch xxxxh xx32h 01036h +04766h 0579Ch 0579Eh 0579Ch xxxxh xx32h 4.4.3.2 MSP430 Instruction With Symbolic Mode in Upper Memory If the PC points to an address above the lower 64-KB memory, the PC bits 19:16 are used for the address calculation of the operand. The operand may be located in memory in the range PC ± 32KB, because the index, X, is a signed 16-bit value. In this case, the address of the operand can overflow or underflow into the lower 64-KB memory space as shown in Figure 4-19 and Figure 4-20. FFFFF Upper Memory PC.19:16 > 0 19 16 15 1 ... 15 0 Program counter PC PC.19:0 PC ±32 KB 10000 0FFFF S S 16-bit byte index 16-bit signed PC index (sign extended to 20 bits) 20-bit signed add Lower 64 KB 00000 Memory address Figure 4-19. Symbolic Mode Running in Upper Memory SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 133 Addressing Modes www.ti.com FFFFF PC.19:0 ±32 KB PC.19:0 ±32 KB Lower 64 KB 10000 0FFFF PC.19:0 PC.19:0 0000C Figure 4-20. Overflow and Underflow for Symbolic Mode Length: Operation: Comment: Example: Source: Destination: Two or three words The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the PC. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh. The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the PC index and inserts it ADD.W EDE,&TONI ; This instruction adds the 16-bit data contained in source word EDE and destination word TONI and places the 16-bit result into the destination word TONI. For this example, the instruction is located at address 2F034h. Word EDE at address 3379Ch, pointed to by PC + 4766h, which is the 16-bit result of 3379Ch – 2F036h = 04766h. Address 2F036h is the location of the index for this example. Word TONI located at address 00778h pointed to by the absolute address 00778h 134 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Before: Address Space 2F03Ah 2F038h 2F036h 2F034h xxxxh 0778h 4766h 5092h PC After: Address Space 2F03Ah 2F038h 2F036h 2F034h xxxxh PC 0778h 4766h 5092h 3379Eh 3379Ch xxxxh 5432h 2F036h +04766h 3379Ch 3379Eh 3379Ch xxxxh 5432h Addressing Modes 0077Ah 00778h xxxxh 2345h 0077Ah 00778h xxxxh 7777h 5432h +2345h 7777h src dst Sum 4.4.3.3 MSP430X Instruction With Symbolic Mode When using an MSP430X instruction with Symbolic mode, the operand can be located anywhere in the range of PC + 19 bits. Length: Operation: Comment: Example: Source: Destination: Three or four words The operand address is the sum of the 20-bit PC and the 20-bit index. The 4 MSBs of the index are contained in the extension word; the 16 LSBs are contained in the word following the instruction. Valid for source and destination. The assembler calculates the register index and inserts it. ADDX.B EDE,TONI ; This instruction adds the 8-bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI. Byte EDE located at address 3579Ch, pointed to by PC + 14766h, is the 20-bit result of 3579Ch – 21036h = 14766h. Address 21036h is the address of the index in this example. Byte TONI located at address 77778h, pointed to by PC + 56740h, is the 20-bit result of 77778h – 21038h = 56740h. Address 21038h is the address of the index in this example. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 135 Addressing Modes Before: Address Space 2103Ah 21038h 21036h 21034h 21032h xxxxh 6740h 4766h 50D0h 18C5h PC After: Address Space 2103Ah xxxxh PC 21038h 6740h 21036h 4766h 21034h 50D0h 21032h 18C5h 7777Ah 77778h xxxxh xx45h 21038h +56740h 77778h 7777Ah 77778h xxxxh xx77h 32h +45h 77h src dst Sum www.ti.com 3579Eh 3579Ch xxxxh xx32h 21036h +14766h 3579Ch 3579Eh 3579Ch xxxxh xx32h 4.4.4 Absolute Mode The Absolute mode uses the contents of the word following the instruction as the address of the operand. The Absolute mode has two addressing possibilities: • Absolute mode in lower 64-KB memory • MSP430X instruction with Absolute mode 4.4.4.1 Absolute Mode in Lower 64KB If an MSP430 instruction is used with Absolute addressing mode, the absolute address is a 16-bit value and, therefore, points to an address in the lower 64KB of the memory range. The address is calculated as an index from 0 and is stored in the word following the instruction The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications. Length: Operation: Comment: Example: Source: Destination: Two or three words The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the index from 0 and inserts it. ADD.W &EDE,&TONI ; This instruction adds the 16-bit data contained in the absolute source and destination addresses and places the result into the destination. Word at address EDE Word at address TONI 136 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Before: Address Space 2103Ah 21038h 21036h 21034h xxxxh 7778h 579Ch 5292h PC 0777Ah 07778h xxxxh 2345h After: Address Space 2103Ah 21038h 21036h 21034h xxxxh PC 7778h 579Ch 5292h Addressing Modes 0777Ah 07778h xxxxh 7777h 5432h +2345h 7777h src dst Sum 0579Eh 0579Ch xxxxh 5432h 0579Eh 0579Ch xxxxh 5432h 4.4.4.2 MSP430X Instruction With Absolute Mode If an MSP430X instruction is used with Absolute addressing mode, the absolute address is a 20-bit value and, therefore, points to any address in the memory range. The address value is calculated as an index from 0. The 4 MSBs of the index are contained in the extension word, and the 16 LSBs are contained in the word following the instruction. Length: Operation: Comment: Example: Source: Destination: Three or four words The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the index from 0 and inserts it. ADDX.A &EDE,&TONI ; This instruction adds the 20-bit data contained in the absolute source and destination addresses and places the result into the destination. Two words beginning with address EDE Two words beginning with address TONI SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 137 Addressing Modes Before: Address Space 2103Ah 21038h 21036h 21034h 21032h xxxxh 7778h 579Ch 52D2h 1987h PC 7777Ah 77778h 0001h 2345h After: Address Space 2103Ah xxxxh PC 21038h 7778h 21036h 579Ch 21034h 52D2h 21032h 1987h 7777Ah 77778h 0007h 7777h 65432h +12345h 77777h src dst Sum www.ti.com 3579Eh 3579Ch 0006h 5432h 3579Eh 3579Ch 0006h 5432h 4.4.5 Indirect Register Mode The Indirect Register mode uses the contents of the CPU register Rsrc as the source operand. The Indirect Register mode always uses a 20-bit address. Length: Operation: Comment: Example: Source: Destination: One, two, or three words The operand is the content the addressed memory location. The source register Rsrc is not modified. Valid only for the source operand. The substitute for the destination operand is 0(Rdst). ADDX.W @R5,2100h(R6) This instruction adds the two 16-bit operands contained in the source and the destination addresses and places the result into the destination. Word pointed to by R5. R5 contains address 3579Ch for this example. Word pointed to by R6 + 2100h, which results in address 45678h + 2100h = 7778h 138 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes Before: Address Space Register After: Address Space Register 21038h 21036h 21034h xxxxh 2100h 55A6h R5 R6 PC 3579Ch 45678h 21038h 21036h 21034h xxxxh 2100h 55A6h PC R5 3579Ch R6 45678h 4777Ah 47778h xxxxh 2345h 45678h +02100h 47778h 4777Ah 47778h xxxxh 7777h 5432h +2345h 7777h src dst Sum 3579Eh 3579Ch xxxxh 5432h R5 3579Eh 3579Ch xxxxh 5432h R5 4.4.6 Indirect Autoincrement Mode The Indirect Autoincrement mode uses the contents of the CPU register Rsrc as the source operand. Rsrc is then automatically incremented by 1 for byte instructions, by 2 for word instructions, and by 4 for address-word instructions immediately after accessing the source operand. If the same register is used for source and destination, it contains the incremented address for the destination access. Indirect Autoincrement mode always uses 20-bit addresses. Length: Operation: Comment: Example: Source: Destination: One, two, or three words The operand is the content of the addressed memory location. Valid only for the source operand ADD.B @R5+,0(R6) This instruction adds the 8-bit data contained in the source and the destination addresses and places the result into the destination. Byte pointed to by R5. R5 contains address 3579Ch for this example. Byte pointed to by R6 + 0h, which results in address 0778h for this example SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 139 Addressing Modes Before: Address Space Register After: Address Space Register 21038h 21036h 21034h xxxxh 0000h 55F6h R5 R6 PC 3579Ch 00778h 21038h 21036h 21034h xxxxh 0000h 55F6h PC R5 3579Dh R6 00778h www.ti.com 0077Ah 00778h xxxxh xx45h 00778h +0000h 00778h 0077Ah 00778h xxxxh xx77h 32h +45h 77h src dst Sum 3579Dh 3579Ch xxh 32h R5 3579Dh 3579Ch xxh R5 xx32h 4.4.7 Immediate Mode The Immediate mode allows accessing constants as operands by including the constant in the memory location following the instruction. The PC is used with the Indirect Autoincrement mode. The PC points to the immediate value contained in the next word. After the fetching of the immediate operand, the PC is incremented by 2 for byte, word, or address-word instructions. The Immediate mode has two addressing possibilities: • 8-bit or 16-bit constants with MSP430 instructions • 20-bit constants with MSP430X instruction 4.4.7.1 MSP430 Instructions With Immediate Mode If an MSP430 instruction is used with Immediate addressing mode, the constant is an 8- or 16-bit value and is stored in the word following the instruction. Length: Operation: Comment: Example: Source: Destination: Two or three words. One word less if a constant of the constant generator can be used for the immediate operand. The 16-bit immediate source operand is used together with the 16-bit destination operand. Valid only for the source operand ADD #3456h,&TONI This instruction adds the 16-bit immediate operand 3456h to the data in the destination address TONI. 16-bit immediate value 3456h Word at address TONI 140 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Before: Address Space 2103Ah xxxxh 21038h 0778h 21036h 3456h 21034h 50B2h PC 0077Ah 00778h xxxxh 2345h After: Address Space 2103Ah xxxxh PC 21038h 0778h 21036h 3456h 21034h 50B2h Addressing Modes 0077Ah 00778h xxxxh 579Bh 3456h +2345h 579Bh src dst Sum 4.4.7.2 MSP430X Instructions With Immediate Mode If an MSP430X instruction is used with Immediate addressing mode, the constant is a 20-bit value. The 4 MSBs of the constant are stored in the extension word, and the 16 LSBs of the constant are stored in the word following the instruction. Length: Operation: Comment: Example: Source: Destination: Three or four words. One word less if a constant of the constant generator can be used for the immediate operand. The 20-bit immediate source operand is used together with the 20-bit destination operand. Valid only for the source operand ADDX.A #23456h,&TONI ; This instruction adds the 20-bit immediate operand 23456h to the data in the destination address TONI. 20-bit immediate value 23456h Two words beginning with address TONI Before: Address Space After: Address Space 2103Ah 21038h 21036h 21034h 21032h xxxxh 7778h 3456h 50F2h 1907h PC 2103Ah xxxxh PC 21038h 7778h 21036h 3456h 21034h 50F2h 21032h 1907h 7777Ah 77778h 0001h 2345h 7777Ah 77778h 0003h 579Bh 23456h +12345h 3579Bh src dst Sum SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 141 MSP430 and MSP430X Instructions www.ti.com 4.5 MSP430 and MSP430X Instructions MSP430 instructions are the 27 implemented instructions of the MSP430 CPU. These instructions are used throughout the 1MB memory range unless their 16-bit capability is exceeded. The MSP430X instructions are used when the addressing of the operands, or the data length exceeds the 16-bit capability of the MSP430 instructions. There are three possibilities when choosing between an MSP430 and MSP430X instruction: • To use only the MSP430 instructions – The only exceptions are the CALLA and the RETA instruction. This can be done if a few, simple rules are met: – Placement of all constants, variables, arrays, tables, and data in the lower 64KB. This allows the use of MSP430 instructions with 16-bit addressing for all data accesses. No pointers with 20-bit addresses are needed. – Placement of subroutine constants immediately after the subroutine code. This allows the use of the symbolic addressing mode with its 16-bit index to reach addresses within the range of PC + 32KB. • To use only MSP430X instructions – The disadvantages of this method are the reduced speed due to the additional CPU cycles and the increased program space due to the necessary extension word for any double operand instruction. • Use the best fitting instruction where needed. The following sections list and describe the MSP430 and MSP430X instructions. 4.5.1 MSP430 Instructions The MSP430 instructions can be used, regardless if the program resides in the lower 64KB or beyond it. The only exceptions are the instructions CALL and RET, which are limited to the lower 64-KB address range. CALLA and RETA instructions have been added to the MSP430X CPU to handle subroutines in the entire address range with no code size overhead. 4.5.1.1 MSP430 Double-Operand (Format I) Instructions Figure 4-21 shows the format of the MSP430 double-operand instructions. Source and destination words are appended for the Indexed, Symbolic, Absolute, and Immediate modes. Table 4-4 lists the 12 MSP430 double-operand instructions. 15 12 11 87654 0 Op-code Rsrc Ad B/W As Rdst Source or Destination 15:0 Destination 15:0 Figure 4-21. MSP430 Double-Operand Instruction Format 142 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions Table 4-4. MSP430 Double-Operand Instructions Mnemonic S-Reg, DReg Operation MOV(.B) src,dst src → dst ADD(.B) src,dst src + dst → dst ADDC(.B) src,dst src + dst + C → dst SUB(.B) src,dst dst + .not.src + 1 → dst SUBC(.B) src,dst dst + .not.src + C → dst CMP(.B) src,dst dst → src DADD(.B) src,dst src + dst + C → dst (decimally) BIT(.B) src,dst src .and. dst BIC(.B) src,dst .not.src .and. dst → dst BIS(.B) src,dst src .or. dst → dst XOR(.B) src,dst src .xor. dst → dst AND(.B) src,dst src .and. dst → dst (1) * = Status bit is affected. - = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. Status Bits(1) V N Z C - - - - * * * * * * * * * * * * * * * * * * * * * * * * 0 * * Z - - - - - - - - * * * Z 0 * * Z 4.5.1.2 MSP430 Single-Operand (Format II) Instructions Figure 4-22 shows the format for MSP430 single-operand instructions, except RETI. The destination word is appended for the Indexed, Symbolic, Absolute, and Immediate modes. Table 4-5 lists the seven singleoperand instructions. 15 7654 0 Op-code B/W Ad Rdst Destination 15:0 Figure 4-22. MSP430 Single-Operand Instructions Table 4-5. MSP430 Single-Operand Instructions Mnemonic S-Reg, DReg Operation RRC(.B) dst C → MSB →.......LSB → C RRA(.B) dst MSB → MSB →....LSB → C PUSH(.B) src SP - 2 → SP, src → SP SWPB dst bit 15...bit 8 ↔ bit 7...bit 0 CALL dst Call subroutine in lower 64KB RETI TOS → SR, SP + 2 → SP TOS → PC,SP + 2 → SP SXT dst Register mode: bit 7 → bit 8...bit 19 Other modes: bit 7 → bit 8...bit 15 (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. Status Bits (1) V N Z C * * * * 0 * * * – – – – – – – – – – – – * * * * 0 * * Z SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 143 MSP430 and MSP430X Instructions www.ti.com 4.5.1.3 Jump Instructions Figure 4-23 shows the format for MSP430 and MSP430X jump instructions. The signed 10-bit word offset of the jump instruction is multiplied by two, sign-extended to a 20-bit address, and added to the 20-bit PC. This allows jumps in a range of –511 to +512 words relative to the PC in the full 20-bit address space. Jumps do not affect the status bits. Table 4-6 lists and describes the eight jump instructions. 15 13 12 10 9 8 0 Op-Code Condition S 10-Bit Signed PC Offset Figure 4-23. Format of Conditional Jump Instructions Mnemonic JEQ/JZ JNE/JNZ JC JNC JN JGE JL JMP Table 4-6. Conditional Jump Instructions S-Reg, D-Reg Label Label Label Label Label Label Label Label Operation Jump to label if zero bit is set Jump to label if zero bit is reset Jump to label if carry bit is set Jump to label if carry bit is reset Jump to label if negative bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally 4.5.1.4 Emulated Instructions In addition to the MSP430 and MSP430X instructions, emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves. Instead, they are replaced automatically by the assembler with a core instruction. There is no code or performance penalty for using emulated instructions. The emulated instructions are listed in Table 4-7. Table 4-7. Emulated Instructions Instruction ADC(.B) dst Explanation Add Carry to dst Emulation Status Bits (1) V N Z C ADDC(.B) #0,dst * * * * BR dst Branch indirectly dst MOV dst,PC – – – – CLR(.B) dst CLRC Clear dst Clear Carry bit MOV(.B) #0,dst – – – – BIC #1,SR – – – 0 CLRN Clear Negative bit BIC #4,SR – 0 – – CLRZ Clear Zero bit BIC #2,SR – – 0 – DADC(.B) dst DEC(.B) dst DECD(.B) dst Add Carry to dst decimally Decrement dst by 1 Decrement dst by 2 DADD(.B) #0,dst * * * * SUB(.B) #1,dst * * * * SUB(.B) #2,dst * * * * DINT Disable interrupt BIC #8,SR – – – – EINT Enable interrupt BIS #8,SR – – – – INC(.B) dst INCD(.B) dst Increment dst by 1 Increment dst by 2 ADD(.B) #1,dst * * * * ADD(.B) #2,dst * * * * (1) * = Status bit is affected; – = Status bit is not affected; 0 = Status bit is cleared; 1 = Status bit is set. 144 CPUX SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com Instruction INV(.B) dst NOP POP dst RET RLA(.B) dst RLC(.B) dst SBC(.B) dst SETC SETN SETZ TST(.B) dst MSP430 and MSP430X Instructions Table 4-7. Emulated Instructions (continued) Explanation Emulation Status Bits (1) V N Z C Invert dst XOR(.B) #–1,dst * * * * No operation MOV R3,R3 – – – – Pop operand from stack MOV @SP+,dst – – – – Return from subroutine MOV @SP+,PC – – – – Shift left dst arithmetically ADD(.B) dst,dst * * * * Shift left dst logically through Carry ADDC(.B) dst,dst * * * * Subtract Carry from dst SUBC(.B) #0,dst * * * * Set Carry bit BIS #1,SR – – – 1 Set Negative bit BIS #4,SR – 1 – – Set Zero bit BIS #2,SR – – 1 – Test dst (compare with 0) CMP(.B) #0,dst 0 * * 1 4.5.1.5 MSP430 Instruction Execution The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used – not the instruction itself. The number of clock cycles refers to MCLK. 4.5.1.5.1 Instruction Cycles and Length for Interrupt, Reset, and Subroutines Table 4-8 lists the length and the CPU cycles for reset, interrupts, and subroutines. Table 4-8. Interrupt, Return, and Reset Cycles and Length Action Return from interrupt RETI Return from subroutine RET Interrupt request service (cycles needed before first instruction) WDT reset Reset ( RST/NMI) (1) The cycle count in MSP430 CPU is 5. (2) The cycle count in MSP430 CPU is 6. Execution Time (MCLK Cycles) 3 (1) 3 5 (2) 4 4 Length of Instruction (Words) 1 1 – – – 4.5.1.5.2 Format II (Single-Operand) Instruction Cycles and Lengths Table 4-9 lists the length and the CPU cycles for all addressing modes of the MSP430 single-operand instructions. Table 4-9. MSP430 Format II Instruction Cycles and Length Addressing Mode Rn @Rn @Rn+ No. of Cycles RRA, RRC SWPB, SXT PUSH 1 3 3 3 (1) 3 3 (1) CALL 3 (1) 4 4 (2) Length of Instruction 1 1 1 Example SWPB R5 RRC @R9 SWPB @R10+ (1) The cycle count in MSP430 CPU is 4. (2) The cycle count in MSP430 CPU is 5. Also, the cycle count is 5 for X(Rn) addressing mode, when Rn = SP. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 145 MSP430 and MSP430X Instructions Table 4-9. MSP430 Format II Instruction Cycles and Length (continued) Addressing Mode #N X(Rn) EDE &EDE No. of Cycles RRA, RRC SWPB, SXT PUSH N/A 3 (1) 4 4 (2) 4 4 (2) 4 4 (2) CALL 4 (2) 4 (2) 4 (2) 4 (2) Length of Instruction 2 2 2 2 Example CALL #LABEL CALL 2(R7) PUSH EDE SXT &EDE www.ti.com 4.5.1.5.3 Jump Instructions Cycles and Lengths All jump instructions require one code word and take two CPU cycles to execute, regardless of whether the jump is taken or not. 4.5.1.5.4 Format I (Double-Operand) Instruction Cycles and Lengths Table 4-10 lists the length and CPU cycles for all addressing modes of the MSP430 Format I instructions. Table 4-10. MSP430 Format I Instructions Cycles and Length Addressing Mode Src Dst Rm PC Rn x(Rm) EDE &EDE Rm PC @Rn x(Rm) EDE &EDE Rm PC @Rn+ x(Rm) EDE &EDE Rm PC #N x(Rm) EDE &EDE Rm PC x(Rn) TONI x(Rm) &TONI No. of Cycles 1 2 4 (1) 4 (1) 4 (1) 2 3 5 (1) 5 (1) 5 (1) 2 3 5 (1) 5 (1) 5 (1) 2 3 5 (1) 5 (1) 5 (1) 3 3 6 (1) 6 (1) 6 (1) Length of Instruction 1 1 2 2 2 1 1 2 2 2 1 1 2 2 2 2 2 3 3 3 2 2 3 3 3 MOV BR ADD XOR MOV AND BR XOR MOV XOR ADD BR XOR MOV MOV MOV BR MOV ADD ADD MOV BR MOV ADD MOV Example R5,R8 R9 R5,4(R6) R8,EDE R5,&EDE @R4,R5 @R8 @R5,8(R6) @R5,EDE @R5,&EDE @R5+,R6 @R9+ @R5,8(R6) @R9+,EDE @R9+,&EDE #20,R9 #2AEh #0300h,0(SP) #33,EDE #33,&EDE 2(R5),R7 2(R6) 4(R7),TONI 4(R4),6(R9) 2(R4),&TONI (1) MOV, BIT, and CMP instructions execute in one fewer cycle. 146 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions Table 4-10. MSP430 Format I Instructions Cycles and Length (continued) Addressing Mode Src Dst Rm PC EDE TONI x(Rm) &TONI Rm PC &EDE TONI x(Rm) &TONI No. of Cycles 3 3 6 (1) 6 (1) 6 (1) 3 3 6 (1) 6 (1) 6 (1) Length of Instruction 2 2 3 3 3 2 2 3 3 3 AND BR CMP MOV MOV MOV BR MOV MOV MOV Example EDE,R6 EDE EDE,TONI EDE,0(SP) EDE,&TONI &EDE,R8 &EDE &EDE,TONI &EDE,0(SP) &EDE,&TONI 4.5.2 MSP430X Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space. Most MSP430X instructions require an additional word of op-code called the extension word. Some extended instructions do not require an additional word and are noted in the instruction description. All addresses, indexes, and immediate numbers have 20-bit values when preceded by the extension word. There are two types of extension words: • Register/register mode for Format I instructions and register mode for Format II instructions • Extension word for all other address mode combinations 4.5.2.1 Register Mode Extension Word The register mode extension word is shown in Figure 4-24 and described in Table 4-11. An example is shown in Figure 4-26. 15 12 11 10 9 8 7 6 5 4 3 0 0001 1 00 ZC # A/L 0 0 (n-1)/Rn Figure 4-24. Extension Word for Register Modes Bit 15:11 10:9 ZC # Table 4-11. Description of the Extension Word Bits for Register Mode Description Extension word op-code. Op-codes 1800h to 1FFFh are extension words. Reserved Zero carry 0 The executed instruction uses the status of the carry bit C. 1 The executed instruction uses the carry bit as 0. The carry bit is defined by the result of the final operation after instruction execution. Repetition 0 The number of instruction repetitions is set by extension word bits 3:0. 1 The number of instruction repetitions is defined by the value of the four LSBs of Rn. See description for bits 3:0. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 147 MSP430 and MSP430X Instructions www.ti.com Table 4-11. Description of the Extension Word Bits for Register Mode (continued) Bit Description A/L Data length extension. Together with the B/W bits of the following MSP430 instruction, the AL bit defines the used data length of the instruction. A/L B/W Comment 0 0 Reserved 0 1 20-bit address word 1 0 16-bit word 1 1 8-bit byte 5:4 Reserved 3:0 Repetition count # = 0 These four bits set the repetition count n. These bits contain n – 1. # = 1 These four bits define the CPU register whose bits 3:0 set the number of repetitions. Rn.3:0 contain n – 1. 148 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 4.5.2.2 Non-Register Mode Extension Word The extension word for non-register modes is shown in Figure 4-25 and described in Table 4-12. An example is shown in Figure 4-27. 15 12 11 10 76543 0 0 0 0 1 1 Source bits 19:16 A/L 0 0 Destination bits 19:16 Figure 4-25. Extension Word for Non-Register Modes Table 4-12. Description of Extension Word Bits for Non-Register Modes Bit Description 15:11 Extension word op-code. Op-codes 1800h to 1FFFh are extension words. Source Bits The four MSBs of the 20-bit source. Depending on the source addressing mode, these four MSBs may belong to an 19:16 immediate operand, an index or to an absolute address. A/L Data length extension. Together with the B/W bits of the following MSP430 instruction, the AL bit defines the used data length of the instruction. A/L B/W Comment 0 0 Reserved 0 1 20-bit address word 1 0 16-bit word 1 1 8-bit byte 5:4 Reserved Destination The four MSBs of the 20-bit destination. Depending on the destination addressing mode, these four MSBs may Bits 19:16 belong to an index or to an absolute address. NOTE: B/W and A/L bit settings for SWPBX and SXTX A/L B/W 0 0 SWPBX.A, SXTX.A 0 1 N/A 1 0 SWPB.W, SXTX.W 1 1 N/A SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 149 MSP430 and MSP430X Instructions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00011 00 ZC # A/L Rsvd (n-1)/Rn Op-code Rsrc Ad B/W As Rdst XORX.A R9,R8 1: Repetition count in bits 3:0 0: Use Carry 01:Address word 00011 0 000 0 0 14(XOR) 9 01 0 8(R8) XORX instruction Source R9 Destination R8 Destination register mode Source register mode Figure 4-26. Example for Extended Register/Register Instruction 15 14 13 12 11 10 9 8 7 6 5 4 00011 Source 19:16 A/L Rsvd 3210 Destination 19:16 Op-code Rsrc Ad B/W As Rdst Source 15:0 Destination 15:0 XORX.A #12345h, 45678h(R15) 18xx extension word 00011 X(Rn) 01: Address word 12345h 1 0 0 @PC+ 4 14 (XOR) 0 (PC) 11 3 15 (R15) Immediate operand LSBs: 2345h Index destination LSBs: 5678h Figure 4-27. Example for Extended Immediate/Indexed Instruction www.ti.com 150 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 4.5.2.3 Extended Double-Operand (Format I) Instructions All 12 double-operand instructions have extended versions as listed in Table 4-13. Table 4-13. Extended Double-Operand Instructions Mnemonic Operands Operation Status Bits (1) V N Z C MOVX(.B,.A) src,dst src → dst – – – – ADDX(.B,.A) src,dst src + dst → dst * * * * ADDCX(.B,.A) src,dst src + dst + C → dst * * * * SUBX(.B,.A) src,dst dst + .not.src + 1 → dst * * * * SUBCX(.B,.A) src,dst dst + .not.src + C → dst * * * * CMPX(.B,.A) src,dst dst – src * * * * DADDX(.B,.A) src,dst src + dst + C → dst (decimal) * * * * BITX(.B,.A) src,dst src .and. dst 0 * * Z BICX(.B,.A) src,dst .not.src .and. dst → dst – – – – BISX(.B,.A) src,dst src .or. dst → dst – – – – XORX(.B,.A) src,dst src .xor. dst → dst * * * Z ANDX(.B,.A) src,dst src .and. dst → dst 0 * * Z (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 151 MSP430 and MSP430X Instructions www.ti.com The four possible addressing combinations for the extension word for Format I instructions are shown in Figure 4-28. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn Op-code src 0 B/W 0 0 dst 0 0 01 1 Op-code src.19:16 A/L 0 0 0 0 0 0 src Ad B/W As dst src.15:0 0 0 0 1 1 0 0 0 0 A/L 0 0 Op-code src Ad B/W As dst.15:0 dst.19:16 dst 0 0 01 1 Op-code src.19:16 A/L 0 0 src Ad B/W As src.15:0 dst.15:0 dst.19:16 dst Figure 4-28. Extended Format I Instruction Formats If the 20-bit address of a source or destination operand is located in memory, not in a CPU register, then two words are used for this operand as shown in Figure 4-29. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address+2 0 .......................................................................................0 19:16 Address Operand LSBs 15:0 Figure 4-29. 20-Bit Addresses in Memory 152 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.5.2.4 Extended Single-Operand (Format II) Instructions Extended MSP430X Format II instructions are listed in Table 4-14. MSP430 and MSP430X Instructions Table 4-14. Extended Single-Operand Instructions Mnemonic Operands Operation CALLA dst POPM.A #n,Rdst POPM.W #n,Rdst PUSHM.A #n,Rsrc PUSHM.W #n,Rsrc PUSHX(.B,.A) src RRCM(.A) #n,Rdst RRUM(.A) #n,Rdst RRAM(.A) #n,Rdst RLAM(.A) #n,Rdst RRCX(.B,.A) dst RRUX(.B,.A) Rdst RRAX(.B,.A) dst SWPBX(.A) dst SXTX(.A) Rdst SXTX(.A) dst (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. Call indirect to subroutine (20-bit address) Pop n 20-bit registers from stack Pop n 16-bit registers from stack Push n 20-bit registers to stack Push n 16-bit registers to stack Push 8/16/20-bit source to stack Rotate right Rdst n bits through carry (16-/20-bit register) Rotate right Rdst n bits unsigned (16-/20-bit register) Rotate right Rdst n bits arithmetically (16-/20-bit register) Rotate left Rdst n bits arithmetically (16-/20-bit register) Rotate right dst through carry (8-/16-/20-bit data) Rotate right dst unsigned (8-/16-/20-bit) Rotate right dst arithmetically Exchange low byte with high byte Bit7 → bit8 ... bit19 Bit7 → bit8 ... MSB n 1 to 16 1 to 16 1 to 16 1 to 16 1 to 4 1 to 4 1 to 4 1 to 4 1 1 1 1 1 1 Status Bits (1) VNZC –––– –––– –––– –––– –––– –––– 0* * * 0* * * **** **** 0* * * 0* * * **** –––– 0* * * 0* * * The three possible addressing mode combinations for Format II instructions are shown in Figure 4-30. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn Op-code B/W 0 0 dst 0 0 0 1 1 0 0 0 0 A/L 0 0 0 0 0 0 Op-code B/W 1 x dst 0 0 0 1 1 0 0 0 0 A/L 0 0 Op-code B/W x 1 dst.15:0 dst.19:16 dst Figure 4-30. Extended Format II Instruction Format SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 153 MSP430 and MSP430X Instructions www.ti.com 4.5.2.4.1 Extended Format II Instruction Format Exceptions Exceptions for the Format II instruction formats are shown in Figure 4-31 through Figure 4-34. 15 87 43 0 Op-code n-1 Rdst - n+1 Figure 4-31. PUSHM/POPM Instruction Format 15 12 11 10 9 C n-1 Op-code 43 0 Rdst Figure 4-32. RRCM, RRAM, RRUM, and RLAM Instruction Format 15 12 11 87 43 0 C Rsrc Op-code 0(PC) C #imm/abs19:16 Op-code #imm15:0 / &abs15:0 0(PC) C 15 Rsrc Op-code index15:0 0(PC) Figure 4-33. BRA Instruction Format Op-code 43 0 Rdst Op-code index15:0 Rdst Op-code #imm15:0 / index15:0 / &abs15:0 #imm/ix/abs19:16 Figure 4-34. CALLA Instruction Format 154 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 4.5.2.5 Extended Emulated Instructions The extended instructions together with the constant generator form the extended emulated instructions. Table 4-15 lists the emulated instructions. Instruction ADCX(.B,.A) dst BRA dst RETA CLRA Rdst CLRX(.B,.A) dst DADCX(.B,.A) dst DECX(.B,.A) dst DECDA Rdst DECDX(.B,.A) dst INCX(.B,.A) dst INCDA Rdst INCDX(.B,.A) dst INVX(.B,.A) dst RLAX(.B,.A) dst RLCX(.B,.A) dst SBCX(.B,.A) dst TSTA Rdst TSTX(.B,.A) dst POPX dst Table 4-15. Extended Emulated Instructions Explanation Add carry to dst Branch indirect dst Return from subroutine Clear Rdst Clear dst Add carry to dst decimally Decrement dst by 1 Decrement Rdst by 2 Decrement dst by 2 Increment dst by 1 Increment Rdst by 2 Increment dst by 2 Invert dst Shift left dst arithmetically Shift left dst logically through carry Subtract carry from dst Test Rdst (compare with 0) Test dst (compare with 0) Pop to dst Emulation ADDCX(.B,.A) #0,dst MOVA dst,PC MOVA @SP+,PC MOV #0,Rdst MOVX(.B,.A) #0,dst DADDX(.B,.A) #0,dst SUBX(.B,.A) #1,dst SUBA #2,Rdst SUBX(.B,.A) #2,dst ADDX(.B,.A) #1,dst ADDA #2,Rdst ADDX(.B,.A) #2,dst XORX(.B,.A) #-1,dst ADDX(.B,.A) dst,dst ADDCX(.B,.A) dst,dst SUBCX(.B,.A) #0,dst CMPA #0,Rdst CMPX(.B,.A) #0,dst MOVX(.B, .A) @SP+,dst SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 155 MSP430 and MSP430X Instructions www.ti.com 4.5.2.6 MSP430X Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode, except for the MOVA instruction as listed in Table 4-16. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time. Address instructions should be used any time an MSP430X instruction is needed with the corresponding restricted addressing mode. Table 4-16. Address Instructions, Operate on 20-Bit Register Data Mnemonic Operands ADDA Rsrc,Rdst #imm20,Rdst Rsrc,Rdst #imm20,Rdst z16(Rsrc),Rdst EDE,Rdst MOVA &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,z16(Rdst) Rsrc,&abs20 CMPA Rsrc,Rdst #imm20,Rdst SUBA Rsrc,Rdst #imm20,Rdst (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. Operation Add source to destination register Status Bits (1) VNZC **** Move source to destination –––– Compare source to destination register * * * * Subtract source from destination register * * * * 156 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 4.5.2.7 MSP430X Instruction Execution The number of CPU clock cycles required for an MSP430X instruction depends on the instruction format and the addressing modes used, not the instruction itself. The number of clock cycles refers to MCLK. 4.5.2.7.1 MSP430X Format II (Single-Operand) Instruction Cycles and Lengths Table 4-17 lists the length and the CPU cycles for all addressing modes of the MSP430X extended singleoperand instructions. Table 4-17. MSP430X Format II Instruction Cycles and Length Instruction Rn RRAM n/1 RRCM n/1 RRUM n/1 RLAM n/1 PUSHM 2+n/1 PUSHM.A 2+2n/1 POPM 2+n/1 POPM.A 2+2n/1 CALLA 4/1 RRAX(.B) 1+n/2 RRAX.A 1+n/2 RRCX(.B) 1+n/2 RRCX.A 1+n/2 PUSHX(.B) 4/2 PUSHX.A 5/2 POPX(.B) 3/2 POPX.A 4/2 (1) Add one cycle when Rn = SP Execution Cycles/Length of Instruction (Words) @Rn @Rn+ #N X(Rn) EDE – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 5/1 5/1 4/2 6 (1)/2 6/2 4/2 4/2 – 5/3 5/3 6/2 6/2 – 7/3 7/3 4/2 4/2 – 5/3 5/3 6/2 6/2 – 7/3 7/3 4/2 4/2 4/3 5 (1)/3 5/3 6/2 6/2 6/3 7 (1)/3 7/3 – – – 5/3 5/3 – – – 7/3 7/3 &EDE – – – – – – – – 6/2 5/3 7/3 5/3 7/3 5/3 7/3 5/3 7/3 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 157 MSP430 and MSP430X Instructions www.ti.com 4.5.2.7.2 MSP430X Format I (Double-Operand) Instruction Cycles and Lengths Table 4-18 lists the length and CPU cycles for all addressing modes of the MSP430X extended Format I instructions. Table 4-18. MSP430X Format I Instruction Cycles and Length Addressing Mode No. of Cycles Length of Instruction Examples Source Destination .B/.W .A .B/.W/.A Rn Rm (1) 2 2 2 BITX.B R5,R8 PC 3 3 2 ADDX R9,PC X(Rm) 5 (2) 7 (3) 3 ANDX.A R5,4(R6) EDE 5 (2) 7 (3) 3 XORX R8,EDE &EDE 5 (2) 7 (3) 3 BITX.W R5,&EDE @Rn Rm 3 4 2 BITX @R5,R8 PC 3 4 2 ADDX @R9,PC X(Rm) 6 (2) 9 (3) 3 ANDX.A @R5,4(R6) EDE 6 (2) 9 (3) 3 XORX @R8,EDE &EDE 6 (2) 9 (3) 3 BITX.B @R5,&EDE @Rn+ Rm 3 4 2 BITX @R5+,R8 PC 4 5 2 ADDX.A @R9+,PC X(Rm) 6 (2) 9 (3) 3 ANDX @R5+,4(R6) EDE 6 (2) 9 (3) 3 XORX.B @R8+,EDE &EDE 6 (2) 9 (3) 3 BITX @R5+,&EDE #N Rm 3 3 3 BITX #20,R8 PC (4) 4 4 3 ADDX.A #FE000h,PC X(Rm) 6 (2) 8 (3) 4 ANDX #1234,4(R6) EDE 6 (2) 8 (3) 4 XORX #A5A5h,EDE &EDE 6 (2) 8 (3) 4 BITX.B #12,&EDE X(Rn) Rm 4 5 3 BITX 2(R5),R8 PC (4) 5 6 3 SUBX.A 2(R6),PC X(Rm) 7 (2) 10 (3) 4 ANDX 4(R7),4(R6) EDE 7 (2) 10 (3) 4 XORX.B 2(R6),EDE &EDE 7 (2) 10 (3) 4 BITX 8(SP),&EDE EDE Rm 4 5 3 BITX.B EDE,R8 PC (4) 5 6 3 ADDX.A EDE,PC X(Rm) 7 (2) 10 (3) 4 ANDX EDE,4(R6) EDE 7 (2) 10 (3) 4 ANDX EDE,TONI &TONI 7 (2) 10 (3) 4 BITX EDE,&TONI &EDE Rm 4 5 3 BITX &EDE,R8 PC (4) 5 6 3 ADDX.A &EDE,PC X(Rm) 7 (2) 10 (3) 4 ANDX.B &EDE,4(R6) TONI 7 (2) 10 (3) 4 XORX &EDE,TONI &TONI 7 (2) 10 (3) 4 BITX &EDE,&TONI (1) Repeat instructions require n + 1 cycles, where n is the number of times the instruction is executed. (2) Reduce the cycle count by one for MOV, BIT, and CMP instructions. (3) Reduce the cycle count by two for MOV, BIT, and CMP instructions. (4) Reduce the cycle count by one for MOV, ADD, and SUB instructions. 158 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 4.5.2.7.3 MSP430X Address Instruction Cycles and Lengths Table 4-19 lists the length and the CPU cycles for all addressing modes of the MSP430X address instructions. Addressing Mode Source Rn @Rn @Rn+ #N x(Rn) EDE &EDE Destination Rn PC x(Rm) EDE &EDE Rm PC Rm PC Rm PC Rm PC Rm PC Rm PC Table 4-19. Address Instruction Cycles and Length Execution Time (MCLK Cycles) MOVA BRA CMPA ADDA SUBA 1 1 2 2 4 – 4 – 4 – 3 – 3 – 3 – 3 – 2 3 3 3 4 – 4 – 4 – 4 – 4 – 4 – Length of Instruction (Words) MOVA CMPA ADDA SUBA 1 1 1 1 2 – 2 – 2 – 1 – 1 – 1 – 1 – 2 2 2 2 2 – 2 – 2 – 2 – 2 – 2 – Example CMPA R5,R8 SUBA R9,PC MOVA R5,4(R6) MOVA R8,EDE MOVA R5,&EDE MOVA @R5,R8 MOVA @R9,PC MOVA @R5+,R8 MOVA @R9+,PC CMPA #20,R8 SUBA #FE000h,PC MOVA 2(R5),R8 MOVA 2(R6),PC MOVA EDE,R8 MOVA EDE,PC MOVA &EDE,R8 MOVA &EDE,PC SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 159 Instruction Set Description 4.6 Instruction Set Description Table 4-20 shows all available instructions: www.ti.com Table 4-20. Instruction Map of MSP430X 000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0 0xxx MOVA, CMPA, ADDA, SUBA, RRCM, RRAM, RLAM, RRUM 10xx RRC RRC.B SWPB RRA RRA.B SXT PUSH PUSH. B CALL RETI CALL A 14xx PUSHM.A, POPM.A, PUSHM.W, POPM.W 18xx 1Cxx Extension word for Format I and Format II instructions 20xx JNE/JNZ 24xx JEQ/JZ 28xx JNC 2Cxx JC 30xx JN 34xx JGE 38xx JL 3Cxx JMP 4xxx MOV, MOV.B 5xxx ADD, ADD.B 6xxx ADDC, ADDC.B 7xxx SUBC, SUBC.B 8xxx SUB, SUB.B 9xxx CMP, CMP.B Axxx DADD, DADD.B Bxxx BIT, BIT.B Cxxx BIC, BIC.B Dxxx BIS, BIS.B Exxx XOR, XOR.B Fxxx AND, AND.B 160 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Instruction Set Description 4.6.1 Extended Instruction Binary Descriptions Detailed MSP430X instruction binary descriptions are shown in the following tables. Instruction MOVA CMPA ADDA SUBA MOVA CMPA ADDA SUBA Instruction Group src or data.19:16 Instruction Identifier 15 12 11 87 4 0000 src 0000 0000 src 0001 0000 &abs.19:16 0010 &abs.15:0 0000 src 0011 x.15:0 0000 src 0110 &abs.15:0 0000 src 0111 x.15:0 0000 imm.19:16 1000 imm.15:0 0000 imm.19:16 1001 imm.15:0 0000 imm.19:16 1010 imm.15:0 0000 imm.19:16 1011 imm.15:0 0000 src 1100 0000 src 1101 0000 src 1110 0000 src 1111 dst 3 0 dst MOVA @Rsrc,Rdst dst MOVA @Rsrc+,Rdst dst MOVA &abs20,Rdst dst &abs.19:16 MOVA x(Rsrc),Rdst ±15-bit index x MOVA Rsrc,&abs20 dst MOVA Rsrc,X(Rdst) ±15-bit index x dst MOVA #imm20,Rdst dst CMPA #imm20,Rdst dst ADDA #imm20,Rdst dst SUBA #imm20,Rdst dst MOVA Rsrc,Rdst dst CMPA Rsrc,Rdst dst ADDA Rsrc,Rdst dst SUBA Rsrc,Rdst Instruction RRCM.A RRAM.A RLAM.A RRUM.A RRCM.W RRAM.W RLAM.W RRUM.W Instruction Group Bit Loc. Inst. ID Instruction Identifier dst 15 12 11 10 9 8 7 43 0 0 0 0 0 n–1 0 0 0 1 0 0 dst RRCM.A #n,Rdst 0 0 0 0 n–1 0 1 0 1 0 0 dst RRAM.A #n,Rdst 0 0 0 0 n–1 1 0 0 1 0 0 dst RLAM.A #n,Rdst 0 0 0 0 n–1 1 1 0 1 0 0 dst RRUM.A #n,Rdst 0 0 0 0 n–1 0 0 0 1 0 1 dst RRCM.W #n,Rdst 0 0 0 0 n–1 0 1 0 1 0 1 dst RRAM.W #n,Rdst 0 0 0 0 n–1 1 0 0 1 0 1 dst RLAM.W #n,Rdst 0 0 0 0 n–1 1 1 0 1 0 1 dst RRUM.W #n,Rdst SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 161 Instruction Set Description www.ti.com Instruction RETI CALLA Reserved Reserved PUSHM.A PUSHM.W POPM.A POPM.W Instruction Identifier dst 15 12 11 876543 0 0001001100000000 000100110100 dst CALLA Rdst 000100110101 dst CALLA x(Rdst) x.15:0 000100110110 dst CALLA @Rdst 000100110111 dst CALLA @Rdst+ 000100111000 &abs.19:16 CALLA &abs20 &abs.15:0 000100111001 x.19:16 CALLA EDE x.15:0 CALLA x(PC) 000100111011 imm.19:16 CALLA #imm20 imm.15:0 000100111010xxxx 0001001111xxxxxx 00010100 n–1 dst PUSHM.A #n,Rdst 00010101 n–1 dst PUSHM.W #n,Rdst 00010110 n–1 dst – n + 1 POPM.A #n,Rdst 00010111 n–1 dst – n + 1 POPM.W #n,Rdst 162 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Instruction Set Description 4.6.2 MSP430 Instructions The MSP430 instructions are described in the following sections. See Section 4.6.3 for MSP430X extended instructions and Section 4.6.4 for MSP430X address instructions. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 163 Instruction Set Description 4.6.2.1 ADC www.ti.com * ADC[.W] * ADC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Add carry to destination Add carry to destination ADC dst or ADC.W dst ADC.B dst dst + C → dst ADDC #0,dst ADDC.B #0,dst The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if dst was incremented from 0FFFFh to 0000, reset otherwise Set if dst was incremented from 0FFh to 00, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. The 16-bit counter pointed to by R13 is added to a 32-bit counter pointed to by R12. ADD @R13,0(R12) ADC 2(R12) ; Add LSDs ; Add carry to MSD Example The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ADC.B 1(R12) ; Add LSDs ; Add carry to MSD 164 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.2 ADD Instruction Set Description ADD[.W] ADD.B Syntax Operation Description Status Bits Mode Bits Example Add source word to destination word Add source byte to destination byte ADD src,dst or ADD.W src,dst ADD.B src,dst src + dst → dst The source operand is added to the destination operand. The previous content of the destination is lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Ten is added to the 16-bit counter CNTR located in lower 64KB. ADD.W #10,&CNTR ; Add 10 to 16-bit counter Example A table word pointed to by R5 (20-bit address in R5) is added to R6. The jump to label TONI is performed on a carry. ADD.W JC ... @R5,R6 TONI ; Add table word to R6. R6.19:16 = 0 ; Jump if carry ; No carry Example A table byte pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. R6.19:8 = 0 ADD.B JNC ... @R5+,R6 TONI ; Add byte to R6. R5 + 1. R6: 000xxh ; Jump if no carry ; Carry occurred SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 165 Instruction Set Description 4.6.2.3 ADDC www.ti.com ADDC[.W] ADDC.B Syntax Operation Description Status Bits Mode Bits Example Add source word and carry to destination word Add source byte and carry to destination byte ADDC src,dst or ADDC.W src,dst ADDC.B src,dst src + dst + C → dst The source operand and the carry bit C are added to the destination operand. The previous content of the destination is lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Constant value 15 and the carry of the previous instruction are added to the 16-bit counter CNTR located in lower 64KB. ADDC.W #15,&CNTR ; Add 15 + C to 16-bit CNTR Example A table word pointed to by R5 (20-bit address) and the carry C are added to R6. The jump to label TONI is performed on a carry. R6.19:16 = 0 ADDC.W JC ... @R5,R6 TONI ; Add table word + C to R6 ; Jump if carry ; No carry Example A table byte pointed to by R5 (20-bit address) and the carry bit C are added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. R6.19:8 = 0 ADDC.B JNC ... @R5+,R6 TONI ; Add table byte + C to R6. R5 + 1 ; Jump if no carry ; Carry occurred 166 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.4 AND Instruction Set Description AND[.W] AND.B Syntax Operation Description Status Bits Mode Bits Example Logical AND of source word with destination word Logical AND of source byte with destination byte AND src,dst or AND.W src,dst AND.B src,dst src .and. dst → dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The bits set in R5 (16-bit data) are used as a mask (AA55h) for the word TOM located in the lower 64KB. If the result is zero, a branch is taken to label TONI. R5.19:16 = 0 MOV #AA55h,R5 ; Load 16-bit mask to R5 AND R5,&TOM ; TOM .and. R5 -> TOM JZ TONI ; Jump if result 0 ... ; Result > 0 or shorter: AND #AA55h,&TOM ; TOM .and. AA55h -> TOM JZ TONI ; Jump if result 0 Example A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R5 is incremented by 1 after the fetching of the byte. R6.19:8 = 0 AND.B @R5+,R6 ; AND table byte with R6. R5 + 1 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 167 Instruction Set Description 4.6.2.5 BIC www.ti.com BIC[.W] BIC.B Syntax Operation Description Status Bits Mode Bits Example Clear bits set in source word in destination word Clear bits set in source byte in destination byte BIC src,dst or BIC.W src,dst BIC.B src,dst (.not. src) .and. dst → dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The bits 15:14 of R5 (16-bit data) are cleared. R5.19:16 = 0 BIC #0C000h,R5 ; Clear R5.19:14 bits Example A table word pointed to by R5 (20-bit address) is used to clear bits in R7. R7.19:16 = 0 BIC.W @R5,R7 ; Clear bits in R7 set in @R5 Example A table byte pointed to by R5 (20-bit address) is used to clear bits in Port1. BIC.B @R5,&P1OUT ; Clear I/O port P1 bits set in @R5 168 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.6 BIS Instruction Set Description BIS[.W] BIS.B Syntax Operation Description Status Bits Mode Bits Example Set bits set in source word in destination word Set bits set in source byte in destination byte BIS src,dst or BIS.W src,dst BIS.B src,dst src .or. dst → dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Bits 15 and 13 of R5 (16-bit data) are set to one. R5.19:16 = 0 BIS #A000h,R5 ; Set R5 bits Example A table word pointed to by R5 (20-bit address) is used to set bits in R7. R7.19:16 = 0 BIS.W @R5,R7 ; Set bits in R7 Example A table byte pointed to by R5 (20-bit address) is used to set bits in Port1. R5 is incremented by 1 afterwards. BIS.B @R5+,&P1OUT ; Set I/O port P1 bits. R5 + 1 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 169 Instruction Set Description 4.6.2.7 BIT www.ti.com BIT[.W] BIT.B Syntax Operation Description Status Bits Mode Bits Example Test bits set in source word in destination word Test bits set in source byte in destination byte BIT src,dst or BIT.W src,dst BIT.B src,dst src .and. dst The source operand and the destination operand are logically ANDed. The result affects only the status bits in SR. Register mode: the register bits Rdst.19:16 (.W) resp. Rdst. 19:8 (.B) are not cleared! N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. Test if one (or both) of bits 15 and 14 of R5 (16-bit data) is set. Jump to label TONI if this is the case. R5.19:16 are not affected. BIT #C000h,R5 JNZ TONI ... ; Test R5.15:14 bits ; At least one bit is set in R5 ; Both bits are reset Example A table word pointed to by R5 (20-bit address) is used to test bits in R7. Jump to label TONI if at least one bit is set. R7.19:16 are not affected. BIT.W JC ... @R5,R7 TONI ; Test bits in R7 ; At least one bit is set ; Both are reset Example A table byte pointed to by R5 (20-bit address) is used to test bits in output Port1. Jump to label TONI if no bit is set. The next table byte is addressed. BIT.B JNC ... @R5+,&P1OUT TONI ; Test I/O port P1 bits. R5 + 1 ; No corresponding bit is set ; At least one bit is set 170 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.8 BR, BRANCH Instruction Set Description * BR, BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination in lower 64K address space BR dst dst → PC MOV dst,PC An unconditional branch is taken to an address anywhere in the lower 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. BR #EXEC ; Branch to label EXEC or direct branch (e.g. #0A4h) ; Core instruction MOV @PC+,PC BR EXEC ; Branch to the address contained in EXEC ; Core instruction MOV X(PC),PC ; Indirect address BR &EXEC ; Branch to the address contained in absolute ; address EXEC ; Core instruction MOV X(0),PC ; Indirect address BR R5 ; Branch to the address contained in R5 ; Core instruction MOV R5,PC ; Indirect R5 BR @R5 ; Branch to the address contained in the word ; pointed to by R5. ; Core instruction MOV @R5,PC ; Indirect, indirect R5 BR @R5+ ; Branch to the address contained in the word pointed ; to by R5 and increment pointer in R5 afterwards. ; The next time-S/W flow uses R5 pointer-it can ; alter program execution due to access to ; next address in a table pointed to by R5 ; Core instruction MOV @R5,PC ; Indirect, indirect R5 with autoincrement BR X(R5) ; Branch to the address contained in the address ; pointed to by R5 + X (e.g. table with address ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 171 Instruction Set Description 4.6.2.9 CALL www.ti.com CALL Syntax Operation Description Status Bits Mode Bits Examples Call a subroutine in lower 64KB CALL dst dst → PC 16-bit dst is evaluated and stored SP – 2 → SP PC → @SP updated PC with return address to TOS tmp → PC saved 16-bit dst to PC A subroutine call is made from an address in the lower 64KB to a subroutine address in the lower 64KB. All seven source addressing modes can be used. The call instruction is a word instruction. The return is made with the RET instruction. Status bits are not affected. PC.19:16 cleared (address in lower 64KB) OSCOFF, CPUOFF, and GIE are not affected. Examples for all addressing modes are given. Immediate Mode: Call a subroutine at label EXEC (lower 64KB) or call directly to address. CALL #EXEC CALL #0AA04h ; Start address EXEC ; Start address 0AA04h Symbolic Mode: Call a subroutine at the 16-bit address contained in address EXEC. EXEC is located at the address (PC + X) where X is within PC + 32 K. CALL EXEC ; Start address at @EXEC. z16(PC) Absolute Mode: Call a subroutine at the 16-bit address contained in absolute address EXEC in the lower 64KB. CALL &EXEC ; Start address at @EXEC Register mode: Call a subroutine at the 16-bit address contained in register R5.15:0. CALL R5 ; Start address at R5 Indirect Mode: Call a subroutine at the 16-bit address contained in the word pointed to by register R5 (20-bit address). CALL @R5 ; Start address at @R5 172 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.10 CLR * CLR[.W] * CLR.B Syntax Operation Emulation Description Status Bits Example Clear destination Clear destination CLR dst or CLR.B dst CLR.W dst 0 → dst MOV #0,dst MOV.B #0,dst The destination operand is cleared. Status bits are not affected. RAM word TONI is cleared. CLR TONI ; 0 -> TONI Example Register R5 is cleared. CLR R5 Example RAM byte TONI is cleared. CLR.B TONI ; 0 -> TONI Instruction Set Description SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 173 Instruction Set Description 4.6.2.11 CLRC www.ti.com * CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Clear carry bit CLRC 0→C BIC #1,SR The carry bit (C) is cleared. The clear carry instruction is a word instruction. N: Not affected Z: Not affected C: Cleared V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12. CLRC DADD DADC @R13,0(R12) 2(R12) ; C=0: defines start ; add 16-bit counter to low word of 32-bit counter ; add carry to high word of 32-bit counter 174 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.12 CLRN Instruction Set Description * CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example Clear negative bit CLRN 0→N or (.NOT.src .AND. dst → dst) BIC #4,SR The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction. N: Reset to 0 Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The negative bit in the SR is cleared. This avoids special treatment with negative numbers of the subroutine called. SUBR SUBRET CLRN CALL ... ... JN ... ... ... RET SUBR SUBRET ; If input is negative: do nothing and return SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 175 Instruction Set Description 4.6.2.13 CLRZ www.ti.com * CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Clear zero bit CLRZ 0→Z or (.NOT.src .AND. dst → dst) BIC #2,SR The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. N: Not affected Z: Reset to 0 C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The zero bit in the SR is cleared. CLRZ Indirect, Auto-Increment mode: Call a subroutine at the 16-bit address contained in the word pointed to by register R5 (20-bit address) and increment the 16-bit address in R5 afterwards by 2. The next time the software uses R5 as a pointer, it can alter the program execution due to access to the next word address in the table pointed to by R5. CALL @R5+ ; Start address at @R5. R5 + 2 Indexed mode: Call a subroutine at the 16-bit address contained in the 20-bit address pointed to by register (R5 + X), for example, a table with addresses starting at X. The address is within the lower 64KB. X is within +32KB. CALL X(R5) ; Start address at @(R5+X). z16(R5) 176 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.14 CMP Instruction Set Description CMP[.W] CMP.B Syntax Operation Emulation Description Status Bits Mode Bits Example Compare source word and destination word Compare source byte and destination byte CMP src,dst or CMP.W src,dst CMP.B src,dst (.not.src) + 1 + dst or dst – src BIC #2,SR The source operand is subtracted from the destination operand. This is made by adding the 1s complement of the source + 1 to the destination. The result affects only the status bits in SR. Register mode: the register bits Rdst.19:16 (.W) resp. Rdst. 19:8 (.B) are not cleared. N: Set if result is negative (src > dst), reset if positive (src = dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. Compare word EDE with a 16-bit constant 1800h. Jump to label TONI if EDE equals the constant. The address of EDE is within PC + 32 K. CMP #01800h,EDE ; Compare word EDE with 1800h JEQ TONI ; EDE contains 1800h ... ; Not equal Example A table word pointed to by (R5 + 10) is compared with R7. Jump to label TONI if R7 contains a lower, signed 16-bit number. R7.19:16 is not cleared. The address of the source operand is a 20-bit address in full memory range. CMP.W JL ... 10(R5),R7 TONI ; Compare two signed numbers ; R7 < 10(R5) ; R7 >= 10(R5) Example A table byte pointed to by R5 (20-bit address) is compared to the value in output Port1. Jump to label TONI if values are equal. The next table byte is addressed. CMP.B JEQ ... @R5+,&P1OUT TONI ; Compare P1 bits with table. R5 + 1 ; Equal contents ; Not equal SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 177 Instruction Set Description 4.6.2.15 DADC www.ti.com * DADC[.W] * DADC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Add carry decimally to destination Add carry decimally to destination DADC dst or DADC.W dst DADC.B dst dst + C → dst (decimally) DADD #0,dst DADD.B #0,dst The carry bit (C) is added decimally to the destination. N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise C: Set if destination increments from 9999 to 0000, reset otherwise Set if destination increments from 99 to 00, reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The four-digit decimal number contained in R5 is added to an eight-digit decimal number pointed to by R8. CLRC DADD R5,0(R8) DADC 2(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSD Example The two-digit decimal number contained in R5 is added to a four-digit decimal number pointed to by R8. CLRC DADD.B R5,0(R8) DADC 1(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSDs 178 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.16 DADD Instruction Set Description * DADD[.W] * DADD.B Syntax Operation Description Status Bits Mode Bits Example Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADD src,dst or DADD.W src,dst DADD.B src,dst src + dst + C → dst (decimally) The source operand and the destination operand are treated as two (.B) or four (.W) binary coded decimals (BCD) with positive signs. The source operand and the carry bit C are added decimally to the destination operand. The source operand is not affected. The previous content of the destination is lost. The result is not defined for non-BCD numbers. N: Set if MSB of result is 1 (word > 7999h, byte > 79h), reset if MSB is 0 Z: Set if result is zero, reset otherwise C: Set if the BCD result is too large (word > 9999h, byte > 99h), reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. Decimal 10 is added to the 16-bit BCD counter DECCNTR. DADD #10h,&DECCNTR ; Add 10 to 4-digit BCD counter Example The eight-digit BCD number contained in 16-bit RAM addresses BCD and BCD+2 is added decimally to an eight-digit BCD number contained in R4 and R5 (BCD+2 and R5 contain the MSDs). The carry C is added, and cleared. CLRC DADD.W DADD.W JC ... &BCD,R4 &BCD+2,R5 OVERFLOW ; Clear carry ; Add LSDs. R4.19:16 = 0 ; Add MSDs with carry. R5.19:16 = 0 ; Result >9999,9999: go to error routine ; Result ok Example The two-digit BCD number contained in word BCD (16-bit address) is added decimally to a two-digit BCD number contained in R4. The carry C is added, also. R4.19:8 = 0CLRC ; Clear carryDADD.B &BCD,R4 ; Add BCD to R4 decimally. R4: 0,00ddh CLRC DADD.B &BCD,R4 ; Clear carry ; Add BCD to R4 decimally. R4: 0,00ddh SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 179 Instruction Set Description 4.6.2.17 DEC www.ti.com * DEC[.W] * DEC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Decrement destination Decrement destination DEC dst or DEC.W dst DEC.B dst dst – 1 → dst SUB #1,dst SUB.B #1,dst The destination operand is decremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08000h, otherwise reset. Set if initial value of destination was 080h, otherwise reset. OSCOFF, CPUOFF, and GIE are not affected. R10 is decremented by 1. DEC R10 ; Decrement R10 ; Move a block of 255 bytes from memory location starting with EDE to ; memory location starting with TONI. Tables should not overlap: start of ; destination address TONI must not be within the range EDE to EDE+0FEh MOV MOV L$1 MOV DEC JNZ #EDE,R6 #510,R10 @R6+,TONI-EDE-1(R6) R10 L$1 Do not transfer tables using the routine above with the overlap shown in Figure 4-35. EDE EDE+254 TONI TONI+254 Figure 4-35. Decrement Overlap 180 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.18 DECD Instruction Set Description * DECD[.W] * DECD.B Syntax Operation Emulation Description Status Bits Mode Bits Example Double-decrement destination Double-decrement destination DECD dst or DECD.W dst DECD.B dst dst – 2 → dst SUB #2,dst SUB.B #2,dst The destination operand is decremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset Set if initial value of destination was 08001 or 08000h, otherwise reset Set if initial value of destination was 081 or 080h, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. R10 is decremented by 2. DECD R10 ; Decrement R10 by two ; Move a block of 255 bytes from memory location starting with EDE to ; memory location starting with TONI. ; Tables should not overlap: start of destination address TONI must not ; be within the range EDE to EDE+0FEh MOV #EDE,R6 MOV #255,R10 L$1 MOV.B @R6+,TONI-EDE-2(R6) DECD R10 JNZ L$1 Example Memory at location LEO is decremented by two. DECD.B LEO ; Decrement MEM(LEO) Decrement status byte STATUS by two DECD.B STATUS SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 181 Instruction Set Description 4.6.2.19 DINT www.ti.com * DINT Syntax Operation Emulation Description Status Bits Mode Bits Example Disable (general) interrupts DINT 0 → GIE or (0FFF7h .AND. SR → SR / .NOT. src .AND. dst → dst) BIC #8,SR All interrupts are disabled. The constant 08h is inverted and logically ANDed with the SR. The result is placed into the SR. Status bits are not affected. GIE is reset. OSCOFF and CPUOFF are not affected. The general interrupt enable (GIE) bit in the SR is cleared to allow a nondisrupted move of a 32-bit counter. This ensures that the counter is not modified during the move by any interrupt. DINT NOP MOV MOV EINT COUNTHI,R5 COUNTLO,R6 ; All interrupt events using the GIE bit are disabled ; Copy counter ; All interrupt events using the GIE bit are enabled NOTE: Disable interrupt If any code sequence needs to be protected from interruption, DINT should be executed at least one instruction before the beginning of the uninterruptible sequence, or it should be followed by a NOP instruction. 182 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.20 EINT Instruction Set Description * EINT Syntax Operation Emulation Description Status Bits Mode Bits Example Enable (general) interrupts EINT 1 → GIE or (0008h .OR. SR → SR / .src .OR. dst → dst) BIS #8,SR All interrupts are enabled. The constant #08h and the SR are logically ORed. The result is placed into the SR. Status bits are not affected. GIE is set. OSCOFF and CPUOFF are not affected. The general interrupt enable (GIE) bit in the SR is set. ; Interrupt routine of ports P1.2 to P1.7 ; P1IN is the address of the register where all port bits are read. ; P1IFG is the address of the register where all interrupt events are latched. MaskOK PUSH.B BIC.B EINT BIT JEQ ... ... BIC ... ... INCD RETI &P1IN @SP,&P1IFG #Mask,@SP MaskOK ; Reset only accepted flags ; Preset port 1 interrupt flags stored on stack ; other interrupts are allowed ; Flags are present identically to mask: jump #Mask,@SP SP ; Housekeeping: inverse to PUSH instruction ; at the start of interrupt subroutine. Corrects ; the stack pointer. NOTE: Enable interrupt The instruction following the enable interrupt instruction (EINT) is always executed, even if an interrupt service request is pending when the interrupts are enabled. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 183 Instruction Set Description 4.6.2.21 INC www.ti.com * INC[.W] * INC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Increment destination Increment destination INC dst or INC.W dst INC.B dst dst + 1 → dst ADD #1,dst The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The status byte, STATUS, of a process is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B CMP.B JEQ STATUS #11,STATUS OVFL 184 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.22 INCD Instruction Set Description * INCD[.W] * INCD.B Syntax Operation Emulation Description Status Bits Mode Bits Example Double-increment destination Double-increment destination INCD dst or INCD.W dst INCD.B dst dst + 2 → dst ADD #2,dst ADD.B #2,dst The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The item on the top of the stack (TOS) is removed without using a register. ....... PUSH R5 INCD SP RET ; R5 is the result of a calculation, which is stored ; in the system stack ; Remove TOS by double-increment from stack ; Do not use INCD.B, SP is a word-aligned register Example The byte on the top of the stack is incremented by two. INCD.B 0(SP) ; Byte on TOS is increment by two SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 185 Instruction Set Description 4.6.2.23 INV * INV[.W] * INV.B Syntax Operation Emulation Description Status Bits Mode Bits Example Invert destination Invert destination INV dst or INV.W dst INV.B dst .not.dst → dst XOR #0FFFFh,dst XOR.B #0FFh,dst The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. Content of R5 is negated (2s complement). MOV #00AEh,R5 ; R5 = 000AEh INV R5 ; Invert R5, R5 = 0FF51h INC R5 ; R5 is now negated, R5 = 0FF52h Example Content of memory byte LEO is negated. MOV.B INV.B INC.B #0AEh,LEO LEO LEO ; MEM(LEO) = 0AEh ; Invert LEO, MEM(LEO) = 051h ; MEM(LEO) is negated, MEM(LEO) = 052h www.ti.com 186 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.24 JC, JHS Instruction Set Description JC JHS Syntax Operation Description Status Bits Mode Bits Example Jump if carry Jump if higher or same (unsigned) JC label JHS label If C = 1: PC + (2 × Offset) → PC If C = 0: execute the following instruction The carry bit C in the SR is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range. If C is reset, the instruction after the jump is executed. JC is used for the test of the carry bit C. JHS is used for the comparison of unsigned numbers. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected. The state of the port 1 pin P1IN.1 bit defines the program flow. BIT.B JC ... #2,&P1IN Label1 ; Port 1, bit 1 set? Bit -> C ; Yes, proceed at Label1 ; No, continue Example If R5 ≥ R6 (unsigned), the program continues at Label2. CMP R6,R 5 JHS Label2 ... ; Is R5 >= R6? Info to C ; Yes, C = 1 ; No, R5 < R6. Continue Example If R5 ≥ 12345h (unsigned operands), the program continues at Label2. CMPA JHS ... #12345h,R5 Label2 ; Is R5 >= 12345h? Info to C ; Yes, 12344h < R5 <= F,FFFFh. C = 1 ; No, R5 < 12345h. Continue SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 187 Instruction Set Description 4.6.2.25 JEQ, JZ www.ti.com JEQ JZ Syntax Operation Description Status Bits Mode Bits Example Jump if equal Jump if zero JEQ label JZ label If Z = 1: PC + (2 × Offset) → PC If Z = 0: execute following instruction The zero bit Z in the SR is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range. If Z is reset, the instruction after the jump is executed. JZ is used for the test of the zero bit Z. JEQ is used for the comparison of operands. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected. The state of the P2IN.0 bit defines the program flow. BIT.B JZ ... #1,&P2IN Label1 ; Port 2, bit 0 reset? ; Yes, proceed at Label1 ; No, set, continue Example If R5 = 15000h (20-bit data), the program continues at Label2. CMPA JEQ ... #15000h,R5 Label2 ; Is R5 = 15000h? Info to SR ; Yes, R5 = 15000h. Z = 1 ; No, R5 not equal 15000h. Continue Example R7 (20-bit counter) is incremented. If its content is zero, the program continues at Label4. ADDA JZ ... #1,R7 Label4 ; Increment R7 ; Zero reached: Go to Label4 ; R7 not equal 0. Continue here. 188 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.26 JGE Instruction Set Description JGE Syntax Operation Description Status Bits Mode Bits Example Jump if greater or equal (signed) JGE label If (N .xor. V) = 0: PC + (2 × Offset) → PC If (N .xor. V) = 1: execute following instruction The negative bit N and the overflow bit V in the SR are tested. If both bits are set or both are reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range -511 to +512 words relative to the PC in full Memory range. If only one bit is set, the instruction after the jump is executed. JGE is used for the comparison of signed operands: also for incorrect results due to overflow, the decision made by the JGE instruction is correct. Note: JGE emulates the nonimplemented JP (jump if positive) instruction if used after the instructions AND, BIT, RRA, SXTX, and TST. These instructions clear the V bit. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. If byte EDE (lower 64KB) contains positive data, go to Label1. Software can run in the full memory range. TST.B JGE ... &EDE Label1 ; Is EDE positive? V <- 0 ; Yes, JGE emulates JP ; No, 80h <= EDE <= FFh Example If the content of R6 is greater than or equal to the memory pointed to by R7, the program continues a Label5. Signed data. Data and program in full memory range. CMP @R7,R6 JGE Label5 ... ; Is R6 >= @R7? ; Yes, go to Label5 ; No, continue here Example If R5 ≥ 12345h (signed operands), the program continues at Label2. Program in full memory range. CMPA JGE ... #12345h,R5 Label2 ; Is R5 >= 12345h? ; Yes, 12344h < R5 <= 7FFFFh ; No, 80000h <= R5 < 12345h SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 189 Instruction Set Description 4.6.2.27 JL www.ti.com JL Syntax Operation Description Status Bits Mode Bits Example Jump if less (signed) JL label If (N .xor. V) = 1: PC + (2 × Offset) → PC If (N .xor. V) = 0: execute following instruction The negative bit N and the overflow bit V in the SR are tested. If only one is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in full memory range. If both bits N and V are set or both are reset, the instruction after the jump is executed. JL is used for the comparison of signed operands: also for incorrect results due to overflow, the decision made by the JL instruction is correct. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. If byte EDE contains a smaller, signed operand than byte TONI, continue at Label1. The address EDE is within PC ± 32 K. CMP.B JL ... &TONI,EDE Label1 ; Is EDE < TONI ; Yes ; No, TONI <= EDE Example If the signed content of R6 is less than the memory pointed to by R7 (20-bit address), the program continues at Label5. Data and program in full memory range. CMP @R7,R6 JL Label5 ... ; Is R6 < @R7? ; Yes, go to Label5 ; No, continue here Example If R5 < 12345h (signed operands), the program continues at Label2. Data and program in full memory range. CMPA JL ... #12345h,R5 Label2 ; Is R5 < 12345h? ; Yes, 80000h =< R5 < 12345h ; No, 12344h < R5 <= 7FFFFh 190 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.28 JMP Instruction Set Description JMP Syntax Operation Description Status Bits Mode Bits Example Jump unconditionally JMP label PC + (2 × Offset) → PC The signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means an unconditional jump in the range –511 to +512 words relative to the PC in the full memory. The JMP instruction may be used as a BR or BRA instruction within its limited range relative to the PC. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected. The byte STATUS is set to 10. Then a jump to label MAINLOOP is made. Data in lower 64KB, program in full memory range. MOV.B #10,&STATUS JMP MAINLOOP ; Set STATUS to 10 ; Go to main loop Example The interrupt vector TAIV of Timer_A3 is read and used for the program flow. Program in full memory range, but interrupt handlers always starts in lower 64KB. ADD RETI JMP JMP RETI &TAIV,PC IHCCR1 IHCCR2 ; Add Timer_A interrupt vector to PC ; No Timer_A interrupt pending ; Timer block 1 caused interrupt ; Timer block 2 caused interrupt ; No legal interrupt, return SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 191 Instruction Set Description 4.6.2.29 JN www.ti.com JN Syntax Operation Description Status Bits Mode Bits Example Jump if negative JN label If N = 1: PC + (2 × Offset) → PC If N = 0: execute following instruction The negative bit N in the SR is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program PC. This means a jump in the range -511 to +512 words relative to the PC in the full memory range. If N is reset, the instruction after the jump is executed. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The byte COUNT is tested. If it is negative, program execution continues at Label0. Data in lower 64KB, program in full memory range. TST.B JN ... &COUNT Label0 ; Is byte COUNT negative? ; Yes, proceed at Label0 ; COUNT >= 0 Example R6 is subtracted from R5. If the result is negative, program continues at Label2. Program in full memory range. SUB R6,R5 ; R5 - R6 -> R5 JN Label2 ; R5 is negative: R6 > R5 (N = 1) ... ; R5 >= 0. Continue here. Example R7 (20-bit counter) is decremented. If its content is below zero, the program continues at Label4. Program in full memory range. SUBA JN ... #1,R7 Label4 ; Decrement R7 ; R7 < 0: Go to Label4 ; R7 >= 0. Continue here. 192 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.30 JNC, JLO Instruction Set Description JNC JLO Syntax Operation Description Status Bits Mode Bits Example Jump if no carry Jump if lower (unsigned) JNC label JLO label If C = 0: PC + (2 × Offset) → PC If C = 1: execute following instruction The carry bit C in the SR is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range. If C is set, the instruction after the jump is executed. JNC is used for the test of the carry bit C. JLO is used for the comparison of unsigned numbers. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. If byte EDE < 15, the program continues at Label2. Unsigned data. Data in lower 64KB, program in full memory range. CMP.B JLO ... #15,&EDE Label2 ; Is EDE < 15? Info to C ; Yes, EDE < 15. C = 0 ; No, EDE >= 15. Continue Example The word TONI is added to R5. If no carry occurs, continue at Label0. The address of TONI is within PC ± 32 K. ADD TONI,R5 JNC Label0 ... ; TONI + R5 -> R5. Carry -> C ; No carry ; Carry = 1: continue here SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 193 Instruction Set Description 4.6.2.31 JNZ, JNE www.ti.com JNZ JNE Syntax Operation Description Status Bits Mode Bits Example Jump if not zero Jump if not equal JNZ label JNE label If Z = 0: PC + (2 × Offset) → PC If Z = 1: execute following instruction The zero bit Z in the SR is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range. If Z is set, the instruction after the jump is executed. JNZ is used for the test of the zero bit Z. JNE is used for the comparison of operands. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The byte STATUS is tested. If it is not zero, the program continues at Label3. The address of STATUS is within PC ± 32 K. TST.B JNZ ... STATUS Label3 ; Is STATUS = 0? ; No, proceed at Label3 ; Yes, continue here Example If word EDE ≠ 1500, the program continues at Label2. Data in lower 64KB, program in full memory range. CMP #1500,&EDE ; Is EDE = 1500? Info to SR JNE Label2 ; No, EDE not equal 1500. ... ; Yes, R5 = 1500. Continue Example R7 (20-bit counter) is decremented. If its content is not zero, the program continues at Label4. Program in full memory range. SUBA JNZ ... #1,R7 Label4 ; Decrement R7 ; Zero not reached: Go to Label4 ; Yes, R7 = 0. Continue here. 194 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.32 MOV Instruction Set Description MOV[.W] MOV.B Syntax Operation Description Status Bits Mode Bits Example Move source word to destination word Move source byte to destination byte MOV src,dst or MOV.W src,dst MOV.B src,dst src → dst The source operand is copied to the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Move a 16-bit constant 1800h to absolute address-word EDE (lower 64KB) MOV #01800h,&EDE ; Move 1800h to EDE Example The contents of table EDE (word data, 16-bit addresses) are copied to table TOM. The length of the tables is 030h words. Both tables reside in the lower 64KB. MOV Loop MOV CMP JLO ... #EDE,R10 @R10+,TOM-EDE-2(R10) #EDE+60h,R10 Loop ; Prepare pointer (16-bit address) ; R10 points to both tables. ; R10+2 ; End of table reached? ; Not yet ; Copy completed Example The contents of table EDE (byte data, 16-bit addresses) are copied to table TOM. The length of the tables is 020h bytes. Both tables may reside in full memory range, but must be within R10 ± 32 K. Loop MOVA MOV MOV.B DEC JNZ ... #EDE,R10 #20h,R9 @R10+,TOM-EDE-1(R10) R9 Loop ; Prepare pointer (20-bit) ; Prepare counter ; R10 points to both tables. ; R10+1 ; Decrement counter ; Not yet done ; Copy completed SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 195 Instruction Set Description 4.6.2.33 NOP www.ti.com * NOP Syntax Operation Emulation Description Status Bits No operation NOP None MOV #0, R3 No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status bits are not affected. 196 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.34 POP Instruction Set Description * POP[.W] * POP.B Syntax Operation Emulation Description Status Bits Example Pop word from stack to destination Pop byte from stack to destination POP dst POP.B dst @SP → temp SP + 2 → SP temp → dst MOV @SP+,dst or MOV.W @SP+,dst MOV.B @SP+,dst The stack location pointed to by the SP (TOS) is moved to the destination. The SP is incremented by two afterwards. Status bits are not affected. The contents of R7 and the SR are restored from the stack. POP R7 POP SR ; Restore R7 ; Restore status register Example The contents of RAM byte LEO is restored from the stack. POP.B LEO ; The low byte of the stack is moved to LEO. Example The contents of R7 is restored from the stack. POP.B R7 ; The low byte of the stack is moved to R7, ; the high byte of R7 is 00h Example The contents of the memory pointed to by R7 and the SR are restored from the stack. POP.B POP 0(R7) SR ; The low byte of the stack is moved to the ; the byte which is pointed to by R7 : Example: R7 = 203h ; Mem(R7) = low byte of system stack : Example: R7 = 20Ah ; Mem(R7) = low byte of system stack ; Last word on stack moved to the SR NOTE: System stack pointer The system SP is always incremented by two, independent of the byte suffix. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 197 Instruction Set Description 4.6.2.35 PUSH www.ti.com PUSH[.W] PUSH.B Syntax Operation Description Status Bits Mode Bits Example Save a word on the stack Save a byte on the stack PUSH dst or PUSH.W dst PUSH.B dst SP – 2 → SP dst → @SP The 20-bit SP SP is decremented by two. The operand is then copied to the RAM word addressed by the SP. A pushed byte is stored in the low byte; the high byte is not affected. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Save the two 16-bit registers R9 and R10 on the stack PUSH R9 PUSH R10 ; Save R9 and R10 XXXXh ; YYYYh Example Save the two bytes EDE and TONI on the stack. The addresses EDE and TONI are within PC ± 32 K. PUSH.B EDE PUSH.B TONI ; Save EDE xxXXh ; Save TONI xxYYh 198 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.36 RET Instruction Set Description RET Syntax Operation Description Status Bits Mode Bits Example Return from subroutine RET @SP →PC.15:0 Saved PC to PC.15:0. PC.19:16 ← 0 SP + 2 → SP The 16-bit return address (lower 64KB), pushed onto the stack by a CALL instruction is restored to the PC. The program continues at the address following the subroutine call. The four MSBs of the PC.19:16 are cleared. Status bits are not affected. PC.19:16: Cleared OSCOFF, CPUOFF, and GIE are not affected. Call a subroutine SUBR in the lower 64KB and return to the address in the lower 64KB after the CALL. SUBR CALL ... PUSH ... POP RET #SUBR R14 R14 ; Call subroutine starting at SUBR ; Return by RET to here ; Save R14 (16 bit data) ; Subroutine code ; Restore R14 ; Return to lower 64KB Item n SP PC Return SP Item n Stack before RET instruction Stack after RET instruction Figure 4-36. Stack After a RET Instruction SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 199 Instruction Set Description 4.6.2.37 RETI www.ti.com RETI Syntax Operation Description Status Bits Mode Bits Example Return from interrupt RETI @SP → SR.15:0 SP + 2 → SP @SP → PC.15:0 SP + 2 → SP Restore saved SR with PC.19:16 Restore saved PC.15:0 Housekeeping The SR is restored to the value at the beginning of the interrupt service routine. This includes the four MSBs of the PC.19:16. The SP is incremented by two afterward. The 20-bit PC is restored from PC.19:16 (from same stack location as the status bits) and PC.15:0. The 20-bit PC is restored to the value at the beginning of the interrupt service routine. The program continues at the address following the last executed instruction when the interrupt was granted. The SP is incremented by two afterward. N: Restored from stack C: Restored from stack Z: Restored from stack V: Restored from stack OSCOFF, CPUOFF, and GIE are restored from stack. Interrupt handler in the lower 64KB. A 20-bit return address is stored on the stack. INTRPT PUSHM.A ... POPM.A RETI #2,R14 #2,R14 ; Save R14 and R13 (20-bit data) ; Interrupt handler code ; Restore R13 and R14 (20-bit data) ; Return to 20-bit address in full memory range 200 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.38 RLA Instruction Set Description * RLA[.W] * RLA.B Syntax Operation Emulation Description Rotate left arithmetically Rotate left arithmetically RLA dst or RLA.W dst RLA.B dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 ADD dst,dst ADD.B dst,dst The destination operand is shifted left one position as shown in Figure 4-37. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2. An overflow occurs if dst ≥ 04000h and dst < 0C000h before operation is performed; the result has changed sign. Word 15 0 C 0 Byte 7 0 Figure 4-37. Destination Operand—Arithmetic Shift Left Status Bits Mode Bits Example An overflow occurs if dst ≥ 040h and dst < 0C0h before the operation is performed; the result has changed sign. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs; the initial value is 04000h ≤ dst < 0C000h, reset otherwise Set if an arithmetic overflow occurs; the initial value is 040h ≤ dst < 0C0h, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R7 is multiplied by 2. RLA R7 ; Shift left R7 (x 2) Example The low byte of R7 is multiplied by 4. RLA.B R7 RLA.B R7 ; Shift left low byte of R7 (x 2) ; Shift left low byte of R7 (x 4) NOTE: RLA substitution The assembler does not recognize the instructions: RLA @R5+ RLA.B @R5+ They must be substituted by: ADD @R5+,-2(R5) ADD.B @R5+,-1(R5) RLA(.B) @R5 ADD(.B) @R5 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 201 Instruction Set Description 4.6.2.39 RLC www.ti.com * RLC[.W] * RLC.B Syntax Operation Emulation Description Rotate left through carry Rotate left through carry RLC dst or RLC.W dst RLC.B dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← C ADDC dst,dst The destination operand is shifted left one position as shown in Figure 4-38. The carry bit (C) is shifted into the LSB, and the MSB is shifted into the carry bit (C). Word 15 0 C Byte 7 0 Status Bits Mode Bits Example Figure 4-38. Destination Operand—Carry Left Shift N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs; the initial value is 04000h ≤ dst < 0C000h, reset otherwise Set if an arithmetic overflow occurs; the initial value is 040h ≤ dst < 0C0h, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R5 is shifted left one position. RLC R5 ; (R5 x 2) + C -> R5 Example The input P1IN.1 information is shifted into the LSB of R5. BIT.B #2,&P1IN RLC R5 ; Information -> Carry ; Carry=P0in.1 -> LSB of R5 Example The MEM(LEO) content is shifted left one position. RLC.B LEO ; Mem(LEO) x 2 + C -> Mem(LEO) NOTE: RLA substitution The assembler does not recognize the instructions: RLC @R5+ RLC.B @R5+ They must be substituted by: ADDC @R5+,-2(R5) ADDC.B @R5+,-1(R5) RLC(.B) @R5 ADDC(.B) @R5 202 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.40 RRA Instruction Set Description RRA[.W] RRA.B Syntax Operation Description Status Bits Mode Bits Example Rotate right arithmetically destination word Rotate right arithmetically destination byte RRA.B dst or RRA.W dst MSB → MSB → MSB–1 → ... LSB+1 → LSB → C The destination operand is shifted right arithmetically by one bit position as shown in Figure 4-39. The MSB retains its value (sign). RRA operates equal to a signed division by 2. The MSB is retained and shifted into the MSB–1. The LSB+1 is shifted into the LSB. The previous LSB is shifted into the carry bit C. N: Set if result is negative (MSB = 1), reset otherwise (MSB = 0) Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 16-bit number in R5 is shifted arithmetically right one position. RRA R5 ; R5/2 -> R5 Example The signed RAM byte EDE is shifted arithmetically right one position. RRA.B EDE ; EDE/2 -> EDE 19 15 7 0 C 0 0 0 0 0 0 0 0 0 0 0 0 MSB LSB 19 15 C 0 0 0 0 MSB 0 LSB Figure 4-39. Rotate Right Arithmetically RRA.B and RRA.W SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 203 Instruction Set Description 4.6.2.41 RRC www.ti.com RRC[.W] RRC.B Syntax Operation Description Status Bits Mode Bits Example Rotate right through carry destination word Rotate right through carry destination byte RRC dst or RRC.W dst RRC.B dst C → MSB → MSB–1 → ... LSB+1 → LSB → C The destination operand is shifted right by one bit position as shown in Figure 4-40. The carry bit C is shifted into the MSB and the LSB is shifted into the carry bit C. N: Set if result is negative (MSB = 1), reset otherwise (MSB = 0) Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. RAM word EDE is shifted right one bit position. The MSB is loaded with 1. SETC RRC EDE ; Prepare carry for MSB ; EDE = EDE >> 1 + 8000h 19 15 7 0 C 0 0 0 0 0 0 0 0 0 0 0 0 MSB LSB 19 15 C 0 0 0 0 MSB 0 LSB Figure 4-40. Rotate Right Through Carry RRC.B and RRC.W 204 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.42 SBC Instruction Set Description * SBC[.W] * SBC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Subtract borrow (.NOT. carry) from destination Subtract borrow (.NOT. carry) from destination SBC dst or SBC.W dst SBC.B dst dst + 0FFFFh + C → dst dst + 0FFh + C → dst SUBC #0,dst SUBC.B #0,dst The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise Set to 1 if no borrow, reset if borrow V: Set if an arithmetic overflow occurs, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 16-bit counter pointed to by R13 is subtracted from a 32-bit counter pointed to by R12. SUB @R13,0(R12) ; Subtract LSDs SBC 2(R12) ; Subtract carry from MSD Example The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUB.B @R13,0(R12) SBC.B 1(R12) ; Subtract LSDs ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Yes No Carry Bit 0 1 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 205 Instruction Set Description 4.6.2.43 SETC * SETC Syntax Operation Emulation Description Status Bits Mode Bits Example Set carry bit SETC 1→C BIS #1,SR The carry bit (C) is set. N: Not affected Z: Not affected C: Set V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Emulation of the decimal subtraction: Subtract R5 from R6 decimally. Assume that R5 = 03987h and R6 = 04137h. DSUB ADD #06666h,R5 INV R5 SETC DADD R5,R6 ; Move content R5 from 0-9 to 6-0Fh ; R5 = 03987h + 06666h = 09FEDh ; Invert this (result back to 0-9) ; R5 = .NOT. R5 = 06012h ; Prepare carry = 1 ; Emulate subtraction by addition of: ; (010000h - R5 - 1) ; R6 = R6 + R5 + 1 ; R6 = 0150h www.ti.com 206 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.44 SETN * SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1→N BIS #4,SR The negative bit (N) is set. N: Set Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Instruction Set Description SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 207 Instruction Set Description 4.6.2.45 SETZ * SETZ Syntax Operation Emulation Description Status Bits Mode Bits Set zero bit SETZ 1→N BIS #2,SR The zero bit (Z) is set. N: Not affected Z: Set C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. www.ti.com 208 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.46 SUB Instruction Set Description SUB[.W] SUB.B Syntax Operation Description Status Bits Mode Bits Example Subtract source word from destination word Subtract source byte from destination byte SUB src,dst or SUB.W src,dst SUB.B src,dst (.not.src) + 1 + dst → dst or dst – src → dst The source operand is subtracted from the destination operand. This is made by adding the 1s complement of the source + 1 to the destination. The source operand is not affected, the result is written to the destination operand. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. A 16-bit constant 7654h is subtracted from RAM word EDE. SUB #7654h,&EDE ; Subtract 7654h from EDE Example A table word pointed to by R5 (20-bit address) is subtracted from R7. Afterwards, if R7 contains zero, jump to label TONI. R5 is then auto-incremented by 2. R7.19:16 = 0. SUB @R5+,R7 JZ TONI ... ; Subtract table number from R7. R5 + 2 ; R7 = @R5 (before subtraction) ; R7 <> @R5 (before subtraction) Example Byte CNT is subtracted from byte R12 points to. The address of CNT is within PC ± 32K. The address R12 points to is in full memory range. SUB.B CNT,0(R12) ; Subtract CNT from @R12 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 209 Instruction Set Description 4.6.2.47 SUBC www.ti.com SUBC[.W] SUBC.B Syntax Operation Description Status Bits Mode Bits Example Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBC src,dst or SUBC.W src,dst SUBC.B src,dst (.not.src) + C + dst → dst or dst – (src – 1) + C → dst The source operand is subtracted from the destination operand. This is done by adding the 1s complement of the source + carry to the destination. The source operand is not affected, the result is written to the destination operand. Used for 32, 48, and 64-bit operands. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. A 16-bit constant 7654h is subtracted from R5 with the carry from the previous instruction. R5.19:16 = 0 SUBC.W #7654h,R5 ; Subtract 7654h + C from R5 Example A 48-bit number (3 words) pointed to by R5 (20-bit address) is subtracted from a 48-bit counter in RAM, pointed to by R7. R5 points to the next 48-bit number afterwards. The address R7 points to is in full memory range. SUB SUBC SUBC @R5+,0(R7) @R5+,2(R7) @R5+,4(R7) ; Subtract LSBs. R5 + 2 ; Subtract MIDs with C. R5 + 2 ; Subtract MSBs with C. R5 + 2 Example Byte CNT is subtracted from the byte, R12 points to. The carry of the previous instruction is used. The address of CNT is in lower 64KB. SUBC.B &CNT,0(R12) ; Subtract byte CNT from @R12 210 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.48 SWPB Instruction Set Description SWPB Syntax Operation Description Status Bits Mode Bits Example Swap bytes SWPB dst dst.15:8 ↔ dst.7:0 The high and the low byte of the operand are exchanged. PC.19:16 bits are cleared in register mode. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected. Exchange the bytes of RAM word EDE (lower 64KB) MOV #1234h,&EDE SWPB &EDE ; 1234h -> EDE ; 3412h -> EDE Before SWPB 15 87 0 High Byte Low Byte After SWPB 15 Low Byte 87 0 High Byte Figure 4-41. Swap Bytes in Memory Before SWPB 19 16 15 87 0 x High Byte Low Byte After SWPB 19 16 15 87 0 0 ... 0 Low Byte High Byte Figure 4-42. Swap Bytes in a Register SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 211 Instruction Set Description 4.6.2.49 SXT www.ti.com SXT Syntax Operation Description Status Bits Mode Bits Example Extend sign SXT dst dst.7 → dst.15:8, dst.7 → dst.19:8 (register mode) Register mode: the sign of the low byte of the operand is extended into the bits Rdst.19:8. Rdst.7 = 0: Rdst.19:8 = 000h afterwards Rdst.7 = 1: Rdst.19:8 = FFFh afterwards Other modes: the sign of the low byte of the operand is extended into the high byte. dst.7 = 0: high byte = 00h afterwards dst.7 = 1: high byte = FFh afterwards N: Set if result is negative, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (C = .not.Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 8-bit data in EDE (lower 64KB) is sign extended and added to the 16-bit signed data in R7. MOV.B SXT ADD &EDE,R5 R5 R5,R7 ; EDE -> R5. 00XXh ; Sign extend low byte to R5.19:8 ; Add signed 16-bit values Example The signed 8-bit data in EDE (PC +32 K) is sign extended and added to the 20-bit data in R7. MOV.B SXT ADDA EDE,R5 R5 R5,R7 ; EDE -> R5. 00XXh ; Sign extend low byte to R5.19:8 ; Add signed 20-bit values 212 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.2.50 TST Instruction Set Description * TST[.W] * TST.B Syntax Operation Emulation Description Status Bits Mode Bits Example Test destination Test destination TST dst or TST.W dst TST.B dst dst + 0FFFFh + 1 dst + 0FFh + 1 CMP #0,dst CMP.B #0,dst The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TST JN JZ ...... ...... ...... R7 R7NEG R7ZERO ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero Example The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TST.B JN JZ ...... ..... ...... R7 R7NEG R7ZERO ; Test low byte of R7 ; Low byte of R7 is negative ; Low byte of R7 is zero ; Low byte of R7 is positive but not zero ; Low byte of R7 is negative ; Low byte of R7 is zero SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 213 Instruction Set Description 4.6.2.51 XOR www.ti.com XOR[.W] XOR.B Syntax Operation Description Status Bits Mode Bits Example Exclusive OR source word with destination word Exclusive OR source byte with destination byte XOR src,dst or XOR.W src,dst XOR.B src,dst src .xor. dst → dst The source and destination operands are exclusively ORed. The result is placed into the destination. The source operand is not affected. The previous content of the destination is lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (C = .not. Z) V: Set if both operands are negative before execution, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Toggle bits in word CNTR (16-bit data) with information (bit = 1) in address-word TONI. Both operands are located in lower 64KB. XOR &TONI,&CNTR ; Toggle bits in CNTR Example A table word pointed to by R5 (20-bit address) is used to toggle bits in R6. R6.19:16 = 0. XOR @R5,R6 ; Toggle bits in R6 Example Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE. R7.19:8 = 0. The address of EDE is within PC ± 32 K. XOR.B EDE,R7 INV.B R7 ; Set different bits to 1 in R7. ; Invert low byte of R7, high byte is 0h 214 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Instruction Set Description 4.6.3 MSP430X Extended Instructions The MSP430X extended instructions give the MSP430X CPU full access to its 20-bit address space. MSP430X instructions require an additional word of op-code called the extension word. All addresses, indexes, and immediate numbers have 20-bit values when preceded by the extension word. The MSP430X extended instructions are described in the following sections. For MSP430X instructions that do not require the extension word, it is noted in the instruction description. See Section 4.6.2 for standard MSP430 instructions and Section 4.6.4 for MSP430X address instructions. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 215 Instruction Set Description 4.6.3.1 ADCX www.ti.com * ADCX.A * ADCX.[W] * ADCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Add carry to destination address-word Add carry to destination word Add carry to destination byte ADCX.A dst ADCX dst or ADCX.W dst ADCX.B dst dst + C → dst ADDCX.A #0,dst ADDCX #0,dst ADDCX.B #0,dst The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 40-bit counter, pointed to by R12 and R13, is incremented. INCX.A @R12 ADCX.A @R13 ; Increment lower 20 bits ; Add carry to upper 20 bits 216 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.2 ADDX Instruction Set Description ADDX.A ADDX.[W] ADDX.B Syntax Operation Description Status Bits Mode Bits Example Add source address-word to destination address-word Add source word to destination word Add source byte to destination byte ADDX.A src,dst ADDX src,dst or ADDX.W src,dst ADDX.B src,dst src + dst → dst The source operand is added to the destination operand. The previous contents of the destination are lost. Both operands can be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Ten is added to the 20-bit pointer CNTR located in two words CNTR (LSBs) and CNTR+2 (MSBs). ADDX.A #10,CNTR ; Add 10 to 20-bit pointer Example A table word (16-bit) pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is performed on a carry. ADDX.W JC ... @R5,R6 TONI ; Add table word to R6 ; Jump if carry ; No carry Example A table byte pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. ADDX.B JNC ... @R5+,R6 TONI ; Add table byte to R6. R5 + 1. R6: 000xxh ; Jump if no carry ; Carry occurred Note: Use ADDA for the following two cases for better code density and execution. ADDX.A Rsrc,Rdst ADDX.A #imm20,Rdst SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 217 Instruction Set Description 4.6.3.3 ADDCX www.ti.com ADDCX.A ADDCX.[W] ADDCX.B Syntax Operation Description Status Bits Mode Bits Example Add source address-word and carry to destination address-word Add source word and carry to destination word Add source byte and carry to destination byte ADDCX.A src,dst ADDCX src,dst or ADDCX.W src,dst ADDCX.B src,dst src + dst + C → dst The source operand and the carry bit C are added to the destination operand. The previous contents of the destination are lost. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Constant 15 and the carry of the previous instruction are added to the 20-bit counter CNTR located in two words. ADDCX.A #15,&CNTR ; Add 15 + C to 20-bit CNTR Example A table word pointed to by R5 (20-bit address) and the carry C are added to R6. The jump to label TONI is performed on a carry. ADDCX.W JC ... @R5,R6 TONI ; Add table word + C to R6 ; Jump if carry ; No carry Example A table byte pointed to by R5 (20-bit address) and the carry bit C are added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. ADDCX.B JNC ... @R5+,R6 TONI ; Add table byte + C to R6. R5 + 1 ; Jump if no carry ; Carry occurred 218 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.4 ANDX Instruction Set Description ANDX.A ANDX.[W] ANDX.B Syntax Operation Description Status Bits Mode Bits Example Logical AND of source address-word with destination address-word Logical AND of source word with destination word Logical AND of source byte with destination byte ANDX.A src,dst ANDX src,dst or ANDX.W src,dst ANDX.B src,dst src .and. dst → dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The bits set in R5 (20-bit data) are used as a mask (AAA55h) for the address-word TOM located in two words. If the result is zero, a branch is taken to label TONI. MOVA ANDX.A JZ ... #AAA55h,R5 R5,TOM TONI ; Load 20-bit mask to R5 ; TOM .and. R5 -> TOM ; Jump if result 0 ; Result > 0 or shorter: ANDX.A #AAA55h,TOM JZ TONI ; TOM .and. AAA55h -> TOM ; Jump if result 0 Example A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R6.19:8 = 0. The table pointer is auto-incremented by 1. ANDX.B @R5+,R6 ; AND table byte with R6. R5 + 1 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 219 Instruction Set Description 4.6.3.5 BICX www.ti.com BICX.A BICX.[W] BICX.B Syntax Operation Description Status Bits Mode Bits Example Clear bits set in source address-word in destination address-word Clear bits set in source word in destination word Clear bits set in source byte in destination byte BICX.A src,dst BICX src,dst or BICX.W src,dst BICX.B src,dst (.not. src) .and. dst → dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Both operands may be located in the full address space. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The bits 19:15 of R5 (20-bit data) are cleared. BICX.A #0F8000h,R5 ; Clear R5.19:15 bits Example A table word pointed to by R5 (20-bit address) is used to clear bits in R7. R7.19:16 = 0. BICX.W @R5,R7 ; Clear bits in R7 Example A table byte pointed to by R5 (20-bit address) is used to clear bits in output Port1. BICX.B @R5,&P1OUT ; Clear I/O port P1 bits 220 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.6 BISX Instruction Set Description BISX.A BISX.[W] BISX.B Syntax Operation Description Status Bits Mode Bits Example Set bits set in source address-word in destination address-word Set bits set in source word in destination word Set bits set in source byte in destination byte BISX.A src,dst BISX src,dst or BISX.W src,dst BISX.B src,dst src .or. dst → dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Both operands may be located in the full address space. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Bits 16 and 15 of R5 (20-bit data) are set to one. BISX.A #018000h,R5 ; Set R5.16:15 bits Example A table word pointed to by R5 (20-bit address) is used to set bits in R7. BISX.W @R5,R7 ; Set bits in R7 Example A table byte pointed to by R5 (20-bit address) is used to set bits in output Port1. BISX.B @R5,&P1OUT ; Set I/O port P1 bits SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 221 Instruction Set Description 4.6.3.7 BITX www.ti.com BITX.A BITX.[W] BITX.B Syntax Operation Description Status Bits Mode Bits Example Test bits set in source address-word in destination address-word Test bits set in source word in destination word Test bits set in source byte in destination byte BITX.A src,dst BITX src,dst or BITX.W src,dst BITX.B src,dst src .and. dst → dst The source operand and the destination operand are logically ANDed. The result affects only the status bits. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. Test if bit 16 or 15 of R5 (20-bit data) is set. Jump to label TONI if so. BITX.A JNZ ... #018000h,R5 TONI ; Test R5.16:15 bits ; At least one bit is set ; Both are reset Example A table word pointed to by R5 (20-bit address) is used to test bits in R7. Jump to label TONI if at least one bit is set. BITX.W JC ... @R5,R7 TONI ; Test bits in R7: C = .not.Z ; At least one is set ; Both are reset Example A table byte pointed to by R5 (20-bit address) is used to test bits in input Port1. Jump to label TONI if no bit is set. The next table byte is addressed. BITX.B JNC ... @R5+,&P1IN TONI ; Test input P1 bits. R5 + 1 ; No corresponding input bit is set ; At least one bit is set 222 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.8 CLRX * CLRX.A * CLRX.[W] * CLRX.B Syntax Operation Emulation Description Status Bits Example Clear destination address-word Clear destination word Clear destination byte CLRX.A dst CLRX dst or CLRX.W dst CLRX.B dst 0 → dst MOVX.A #0,dst MOVX #0,dst MOVX.B #0,dst The destination operand is cleared. Status bits are not affected. RAM address-word TONI is cleared. CLRX.A TONI ; 0 -> TONI Instruction Set Description SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 223 Instruction Set Description 4.6.3.9 CMPX www.ti.com CMPX.A CMPX.[W] CMPX.B Syntax Operation Description Status Bits Mode Bits Example Compare source address-word and destination address-word Compare source word and destination word Compare source byte and destination byte CMPX.A src,dst CMPX src,dst or CMPX.W src,dst CMPX.B src,dst (.not. src) + 1 + dst or dst – src The source operand is subtracted from the destination operand by adding the 1s complement of the source + 1 to the destination. The result affects only the status bits. Both operands may be located in the full address space. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. Compare EDE with a 20-bit constant 18000h. Jump to label TONI if EDE equals the constant. CMPX.A JEQ ... #018000h,EDE TONI ; Compare EDE with 18000h ; EDE contains 18000h ; Not equal Example A table word pointed to by R5 (20-bit address) is compared with R7. Jump to label TONI if R7 contains a lower, signed, 16-bit number. CMPX.W JL ... @R5,R7 TONI ; Compare two signed numbers ; R7 < @R5 ; R7 >= @R5 Example A table byte pointed to by R5 (20-bit address) is compared to the input in I/O Port1. Jump to label TONI if the values are equal. The next table byte is addressed. CMPX.B JEQ ... @R5+,&P1IN TONI ; Compare P1 bits with table. R5 + 1 ; Equal contents ; Not equal Note: Use CMPA for the following two cases for better density and execution. CMPA CMPA Rsrc,Rdst #imm20,Rdst 224 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.10 DADCX Instruction Set Description * DADCX.A * DADCX.[W] * DADCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Add carry decimally to destination address-word Add carry decimally to destination word Add carry decimally to destination byte DADCX.A dst DADCX dst or DADCX.W dst DADCX.B dst dst + C → dst (decimally) DADDX.A #0,dst DADDX #0,dst DADDX.B #0,dst The carry bit (C) is added decimally to the destination. N: Set if MSB of result is 1 (address-word > 79999h, word > 7999h, byte > 79h), reset if MSB is 0 Z: Set if result is zero, reset otherwise C: Set if the BCD result is too large (address-word > 99999h, word > 9999h, byte > 99h), reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The 40-bit counter, pointed to by R12 and R13, is incremented decimally. DADDX.A #1,0(R12) DADCX.A 0(R13) ; Increment lower 20 bits ; Add carry to upper 20 bits SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 225 Instruction Set Description 4.6.3.11 DADDX www.ti.com DADDX.A DADDX.[W] DADDX.B Syntax Operation Description Status Bits Mode Bits Example Add source address-word and carry decimally to destination address-word Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADDX.A src,dst DADDX src,dst or DADDX.W src,dst DADDX.B src,dst src + dst + C → dst (decimally) The source operand and the destination operand are treated as two (.B), four (.W), or five (.A) binary coded decimals (BCD) with positive signs. The source operand and the carry bit C are added decimally to the destination operand. The source operand is not affected. The previous contents of the destination are lost. The result is not defined for non-BCD numbers. Both operands may be located in the full address space. N: Set if MSB of result is 1 (address-word > 79999h, word > 7999h, byte > 79h), reset if MSB is 0. Z: Set if result is zero, reset otherwise C: Set if the BCD result is too large (address-word > 99999h, word > 9999h, byte > 99h), reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. Decimal 10 is added to the 20-bit BCD counter DECCNTR located in two words. DADDX.A #10h,&DECCNTR ; Add 10 to 20-bit BCD counter Example The eight-digit BCD number contained in 20-bit addresses BCD and BCD+2 is added decimally to an eight-digit BCD number contained in R4 and R5 (BCD+2 and R5 contain the MSDs). CLRC DADDX.W DADDX.W JC ... BCD,R4 BCD+2,R5 OVERFLOW ; Clear carry ; Add LSDs ; Add MSDs with carry ; Result >99999999: go to error routine ; Result ok Example The two-digit BCD number contained in 20-bit address BCD is added decimally to a twodigit BCD number contained in R4. CLRC DADDX.B BCD,R4 ; Clear carry ; Add BCD to R4 decimally. ; R4: 000ddh 226 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.12 DECX Instruction Set Description * DECX.A * DECX.[W] * DECX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Decrement destination address-word Decrement destination word Decrement destination byte DECX.A dst DECX dst or DECX.W dst DECX.B dst dst – 1 → dst SUBX.A #1,dst SUBX #1,dst SUBX.B #1,dst The destination operand is decremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. RAM address-word TONI is decremented by one. DECX.A TONI ; Decrement TONI SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 227 Instruction Set Description 4.6.3.13 DECDX www.ti.com * DECDX.A * DECDX.[W] * DECDX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Double-decrement destination address-word Double-decrement destination word Double-decrement destination byte DECDX.A dst DECDX dst or DECDX.W dst DECDX.B dst dst – 2 → dst SUBX.A #2,dst SUBX #2,dst SUBX.B #2,dst The destination operand is decremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. RAM address-word TONI is decremented by two. DECDX.A TONI ; Decrement TONI 228 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.14 INCX Instruction Set Description * INCX.A * INCX.[W] * INCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Increment destination address-word Increment destination word Increment destination byte INCX.A dst INCX dst or INCX.W dst INCX.B dst dst + 1 → dst ADDX.A #1,dst ADDX #1,dst ADDX.B #1,dst The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFFh, reset otherwise Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFFh, reset otherwise Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. RAM address-word TONI is incremented by one. INCX.A TONI ; Increment TONI (20-bits) SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 229 Instruction Set Description 4.6.3.15 INCDX www.ti.com * INCDX.A * INCDX.[W] * INCDX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Double-increment destination address-word Double-increment destination word Double-increment destination byte INCDX.A dst INCDX dst or INCDX.W dst INCDX.B dst dst + 2 → dst ADDX.A #2,dst ADDX #2,dst ADDX.B #2,dst The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFEh, reset otherwise Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFFEh or 0FFFFFh, reset otherwise Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFFEh or 07FFFFh, reset otherwise Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. RAM byte LEO is incremented by two; PC points to upper memory. INCDX.B LEO ; Increment LEO by two 230 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.16 INVX Instruction Set Description * INVX.A * INVX.[W] * INVX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Invert destination Invert destination Invert destination INVX.A dst INVX dst or INVX.W dst INVX.B dst .NOT.dst → dst XORX.A #0FFFFFh,dst XORX #0FFFFh,dst XORX.B #0FFh,dst The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFFh, reset otherwise Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. 20-bit content of R5 is negated (2s complement). INVX.A R5 INCX.A R5 ; Invert R5 ; R5 is now negated Example Content of memory byte LEO is negated. PC is pointing to upper memory. INVX.B LEO INCX.B LEO ; Invert LEO ; MEM(LEO) is negated SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 231 Instruction Set Description 4.6.3.17 MOVX www.ti.com MOVX.A MOVX.[W] MOVX.B Syntax Operation Description Status Bits Mode Bits Example Move source address-word to destination address-word Move source word to destination word Move source byte to destination byte MOVX.A src,dst MOVX src,dst or MOVX.W src,dst MOVX.B src,dst src → dst The source operand is copied to the destination. The source operand is not affected. Both operands may be located in the full address space. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Move a 20-bit constant 18000h to absolute address-word EDE MOVX.A #018000h,&EDE ; Move 18000h to EDE Example The contents of table EDE (word data, 20-bit addresses) are copied to table TOM. The length of the table is 030h words. MOVA Loop MOVX.W CMPA JLO ... #EDE,R10 @R10+,TOM-EDE-2(R10) #EDE+60h,R10 Loop ; Prepare pointer (20-bit address) ; R10 points to both tables. ; R10+2 ; End of table reached? ; Not yet ; Copy completed Example The contents of table EDE (byte data, 20-bit addresses) are copied to table TOM. The length of the table is 020h bytes. MOVA MOV Loop MOVX.W DEC JNZ ... #EDE,R10 #20h,R9 @R10+,TOM-EDE-2(R10) R9 Loop ; Prepare pointer (20-bit) ; Prepare counter ; R10 points to both tables. ; R10+1 ; Decrement counter ; Not yet done ; Copy completed Ten of the 28 possible addressing combinations of the MOVX.A instruction can use the MOVA instruction. This saves two bytes and code cycles. Examples for the addressing combinations are: MOVX.A MOVX.A MOVX.A MOVX.A MOVX.A MOVX.A Rsrc,Rdst #imm20,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,&abs20 MOVA MOVA MOVA MOVA MOVA MOVA Rsrc,Rdst #imm20,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,&abs20 ; Reg/Reg ; Immediate/Reg ; Absolute/Reg ; Indirect/Reg ; Indirect,Auto/Reg ; Reg/Absolute 232 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Instruction Set Description The next four replacements are possible only if 16-bit indexes are sufficient for the addressing: MOVX.A MOVX.A MOVX.A MOVX.A z20(Rsrc),Rdst Rsrc,z20(Rdst) symb20,Rdst Rsrc,symb20 MOVA MOVA MOVA MOVA z16(Rsrc),Rdst Rsrc,z16(Rdst) symb16,Rdst Rsrc,symb16 ; Indexed/Reg ; Reg/Indexed ; Symbolic/Reg ; Reg/Symbolic SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 233 Instruction Set Description 4.6.3.18 POPM www.ti.com POPM.A POPM.[W] Syntax Operation Description Status Bits Mode Bits Example Restore n CPU registers (20-bit data) from the stack Restore n CPU registers (16-bit data) from the stack POPM.A #n,Rdst 1 ≤ n ≤ 16 POPM.W #n,Rdst or POPM #n,Rdst 1 ≤ n ≤ 16 POPM.A: Restore the register values from stack to the specified CPU registers. The SP is incremented by four for each register restored from stack. The 20-bit values from stack (two words per register) are restored to the registers. POPM.W: Restore the 16-bit register values from stack to the specified CPU registers. The SP is incremented by two for each register restored from stack. The 16-bit values from stack (one word per register) are restored to the CPU registers. Note : This instruction does not use the extension word. POPM.A: The CPU registers pushed on the stack are moved to the extended CPU registers, starting with the CPU register (Rdst – n + 1). The SP is incremented by (n × 4) after the operation. POPM.W: The 16-bit registers pushed on the stack are moved back to the CPU registers, starting with CPU register (Rdst – n + 1). The SP is incremented by (n × 2) after the instruction. The MSBs (Rdst.19:16) of the restored CPU registers are cleared. Status bits are not affected, except SR is included in the operation. OSCOFF, CPUOFF, and GIE are not affected. Restore the 20-bit registers R9, R10, R11, R12, R13 from the stack POPM.A #5,R13 ; Restore R9, R10, R11, R12, R13 Example Restore the 16-bit registers R9, R10, R11, R12, R13 from the stack. POPM.W #5,R13 ; Restore R9, R10, R11, R12, R13 234 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.19 PUSHM Instruction Set Description PUSHM.A PUSHM.[W] Syntax Operation Description Status Bits Mode Bits Example Save n CPU registers (20-bit data) on the stack Save n CPU registers (16-bit words) on the stack PUSHM.A #n,Rdst 1 ≤ n ≤ 16 PUSHM.W #n,Rdst or PUSHM #n,Rdst 1 ≤ n ≤ 16 PUSHM.A: Save the 20-bit CPU register values on the stack. The SP is decremented by four for each register stored on the stack. The MSBs are stored first (higher address). PUSHM.W: Save the 16-bit CPU register values on the stack. The SP is decremented by two for each register stored on the stack. PUSHM.A: The n CPU registers, starting with Rdst backwards, are stored on the stack. The SP is decremented by (n × 4) after the operation. The data (Rn.19:0) of the pushed CPU registers is not affected. PUSHM.W: The n registers, starting with Rdst backwards, are stored on the stack. The SP is decremented by (n × 2) after the operation. The data (Rn.19:0) of the pushed CPU registers is not affected. Note : This instruction does not use the extension word. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Save the five 20-bit registers R9, R10, R11, R12, R13 on the stack PUSHM.A #5,R13 ; Save R13, R12, R11, R10, R9 Example Save the five 16-bit registers R9, R10, R11, R12, R13 on the stack PUSHM.W #5,R13 ; Save R13, R12, R11, R10, R9 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 235 Instruction Set Description 4.6.3.20 POPX www.ti.com * POPX.A * POPX.[W] * POPX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Restore single address-word from the stack Restore single word from the stack Restore single byte from the stack POPX.A dst POPX dst or POPX.W dst POPX.B dst Restore the 8-/16-/20-bit value from the stack to the destination. 20-bit addresses are possible. The SP is incremented by two (byte and word operands) and by four (address-word operand). MOVX(.B,.A) @SP+,dst The item on TOS is written to the destination operand. Register mode, Indexed mode, Symbolic mode, and Absolute mode are possible. The SP is incremented by two or four. Note: The SP is incremented by two also for byte operations. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Write the 16-bit value on TOS to the 20-bit address &EDE POPX.W &EDE ; Write word to address EDE Example Write the 20-bit value on TOS to R9 POPX.A R9 ; Write address-word to R9 236 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.21 PUSHX Instruction Set Description PUSHX.A PUSHX.[W] PUSHX.B Syntax Operation Description Status Bits Mode Bits Example Save single address-word to the stack Save single word to the stack Save single byte to the stack PUSHX.A src PUSHX src or PUSHX.W src PUSHX.B src Save the 8-/16-/20-bit value of the source operand on the TOS. 20-bit addresses are possible. The SP is decremented by two (byte and word operands) or by four (addressword operand) before the write operation. The SP is decremented by two (byte and word operands) or by four (address-word operand). Then the source operand is written to the TOS. All seven addressing modes are possible for the source operand. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Save the byte at the 20-bit address &EDE on the stack PUSHX.B &EDE ; Save byte at address EDE Example Save the 20-bit value in R9 on the stack. PUSHX.A R9 ; Save address-word in R9 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 237 Instruction Set Description 4.6.3.22 RLAM www.ti.com RLAM.A RLAM.[W] Syntax Operation Description Status Bits Mode Bits Example Rotate left arithmetically the 20-bit CPU register content Rotate left arithmetically the 16-bit CPU register content RLAM.A #n,Rdst 1≤n≤4 RLAM.W #n,Rdst or RLAM #n,Rdst 1≤n≤4 C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 The destination operand is shifted arithmetically left one, two, three, or four positions as shown in Figure 4-43. RLAM works as a multiplication (signed and unsigned) with 2, 4, 8, or 16. The word instruction RLAM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the MSB (n = 1), MSB-1 (n = 2), MSB-2 (n = 3), MSB-3 (n = 4) V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The 20-bit operand in R5 is shifted left by three positions. It operates equal to an arithmetic multiplication by 8. RLAM.A #3,R5 ; R5 = R5 x 8 19 16 15 C 0000 MSB 0 LSB 0 19 C MSB 0 LSB 0 Figure 4-43. Rotate Left Arithmetically—RLAM[.W] and RLAM.A 238 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.23 RLAX Instruction Set Description * RLAX.A * RLAX.[W] * RLAX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Rotate left arithmetically address-word Rotate left arithmetically word Rotate left arithmetically byte RLAX.A dst RLAX dst or RLAX.W dst RLAX.B dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 ADDX.A dst,dst ADDX dst,dst ADDX.B dst,dst The destination operand is shifted left one position as shown in Figure 4-44. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLAX instruction acts as a signed multiplication by 2. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs: the initial value is 040000h ≤ dst < 0C0000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R7 is multiplied by 2 RLAX.A R7 ; Shift left R7 (20-bit) 0 C MSB LSB 0 Figure 4-44. Destination Operand-Arithmetic Shift Left SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 239 Instruction Set Description 4.6.3.24 RLCX www.ti.com * RLCX.A * RLCX.[W] * RLCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Rotate left through carry address-word Rotate left through carry word Rotate left through carry byte RLCX.A dst RLCX dst or RLCX.W dst RLCX.B dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← C ADDCX.A dst,dst ADDCX dst,dst ADDCX.B dst,dst The destination operand is shifted left one position as shown in Figure 4-45. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C). N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs: the initial value is 040000h ≤ dst < 0C0000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is shifted left one position. RLCX.A R5 ; (R5 x 2) + C -> R5 Example The RAM byte LEO is shifted left one position. PC is pointing to upper memory. RLCX.B LEO ; RAM(LEO) x 2 + C -> RAM(LEO) 0 C MSB LSB Figure 4-45. Destination Operand-Carry Left Shift 240 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.25 RRAM Instruction Set Description RRAM.A RRAM.[W] Syntax Operation Description Status Bits Mode Bits Example Rotate right arithmetically the 20-bit CPU register content Rotate right arithmetically the 16-bit CPU register content RRAM.A #n,Rdst 1≤n≤4 RRAM.W #n,Rdst or RRAM #n,Rdst 1≤n≤4 MSB → MSB → MSB–1 ... LSB+1 → LSB → C The destination operand is shifted right arithmetically by one, two, three, or four bit positions as shown in Figure 4-46. The MSB retains its value (sign). RRAM operates equal to a signed division by 2/4/8/16. The MSB is retained and shifted into MSB-1. The LSB+1 is shifted into the LSB, and the LSB is shifted into the carry bit C. The word instruction RRAM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 20-bit number in R5 is shifted arithmetically right two positions. RRAM.A #2,R5 ; R5/4 -> R5 Example The signed 20-bit value in R15 is multiplied by 0.75. (0.5 + 0.25) × R15. PUSHM.A RRAM.A ADDX.A RRAM.A #1,R15 #1,R15 @SP+,R15 #1,R15 19 16 C 0000 ; Save extended R15 on stack ; R15 y 0.5 -> R15 ; R15 y 0.5 + R15 = 1.5 y R15 -> R15 ; (1.5 y R15) y 0.5 = 0.75 y R15 -> R15 15 0 MSB LSB 19 C MSB 0 LSB Figure 4-46. Rotate Right Arithmetically RRAM[.W] and RRAM.A SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 241 Instruction Set Description 4.6.3.26 RRAX www.ti.com RRAX.A RRAX.[W] RRAX.B Syntax Operation Description Status Bits Mode Bits Example Rotate right arithmetically the 20-bit operand Rotate right arithmetically the 16-bit operand Rotate right arithmetically the 8-bit operand RRAX.A Rdst RRAX.W Rdst RRAX Rdst RRAX.B Rdst RRAX.A dst RRAX dst or RRAX.W dst RRAX.B dst MSB → MSB → MSB–1 ... LSB+1 → LSB → C Register mode for the destination: the destination operand is shifted right by one bit position as shown in Figure 4-47. The MSB retains its value (sign). The word instruction RRAX.W clears the bits Rdst.19:16, the byte instruction RRAX.B clears the bits Rdst.19:8. The MSB retains its value (sign), the LSB is shifted into the carry bit. RRAX here operates equal to a signed division by 2. All other modes for the destination: the destination operand is shifted right arithmetically by one bit position as shown in Figure 4-48. The MSB retains its value (sign), the LSB is shifted into the carry bit. RRAX here operates equal to a signed division by 2. All addressing modes, with the exception of the Immediate mode, are possible in the full memory. N: Set if result is negative, reset if positive .A: dst.19 = 1, reset if dst.19 = 0 .W: dst.15 = 1, reset if dst.15 = 0 .B: dst.7 = 1, reset if dst.7 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 20-bit number in R5 is shifted arithmetically right four positions. RPT #4 RRAX.A R5 ; R5/16 -> R5 242 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Example The signed 8-bit value in EDE is multiplied by 0.5. RRAX.B &EDE ; EDE/2 -> EDE 19 C 0 8 7 0 MSB Instruction Set Description 0 LSB 19 16 C 0000 15 MSB 0 LSB 19 C MSB 0 LSB Figure 4-47. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode 7 0 C MSB LSB 15 C MSB 0 LSB 31 0 19 C MSB 20 0 0 LSB Figure 4-48. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 243 Instruction Set Description 4.6.3.27 RRCM www.ti.com RRCM.A RRCM.[W] Syntax Operation Description Status Bits Mode Bits Example Rotate right through carry the 20-bit CPU register content Rotate right through carry the 16-bit CPU register content RRCM.A #n,Rdst 1≤n≤4 RRCM.W #n,Rdst or RRCM #n,Rdst 1≤n≤4 C → MSB → MSB–1 ... LSB+1 → LSB → C The destination operand is shifted right by one, two, three, or four bit positions as shown in Figure 4-49. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. The word instruction RRCM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The address-word in R5 is shifted right by three positions. The MSB–2 is loaded with 1. SETC RRCM.A #3,R5 ; Prepare carry for MSB-2 ; R5 = R5 » 3 + 20000h Example The word in R6 is shifted right by two positions. The MSB is loaded with the LSB. The MSB–1 is loaded with the contents of the carry flag. RRCM.W #2,R6 ; R6 = R6 » 2. R6.19:16 = 0 19 16 15 0 C 0 MSB LSB 19 C MSB 0 LSB Figure 4-49. Rotate Right Through Carry RRCM[.W] and RRCM.A 244 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.28 RRCX Instruction Set Description RRCX.A RRCX.[W] RRCX.B Syntax Operation Description Status Bits Mode Bits Example Rotate right through carry the 20-bit operand Rotate right through carry the 16-bit operand Rotate right through carry the 8-bit operand RRCX.A Rdst RRCX.W Rdst RRCX Rdst RRCX.B Rdst RRCX.A dst RRCX dst or RRCX.W dst RRCX.B dst C → MSB → MSB–1 ... LSB+1 → LSB → C Register mode for the destination: the destination operand is shifted right by one bit position as shown in Figure 4-50. The word instruction RRCX.W clears the bits Rdst.19:16, the byte instruction RRCX.B clears the bits Rdst.19:8. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. All other modes for the destination: the destination operand is shifted right by one bit position as shown in Figure 4-51. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. All addressing modes, with the exception of the Immediate mode, are possible in the full memory. N: Set if result is negative .A: dst.19 = 1, reset if dst.19 = 0 .W: dst.15 = 1, reset if dst.15 = 0 .B: dst.7 = 1, reset if dst.7 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The 20-bit operand at address EDE is shifted right by one position. The MSB is loaded with 1. SETC RRCX.A EDE ; Prepare carry for MSB ; EDE = EDE » 1 + 80000h SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 245 Instruction Set Description Example The word in R6 is shifted right by 12 positions. RPT #12 RRCX.W R6 ; R6 = R6 » 12. R6.19:16 = 0 19 C 0--------------------0 87 MSB 19 16 15 C 0 0 0 0 MSB www.ti.com 0 LSB 0 LSB 19 C MSB 0 LSB Figure 4-50. Rotate Right Through Carry RRCX(.B,.A) – Register Mode 7 0 C MSB LSB C 31 0 19 C MSB 15 MSB 0 LSB 20 0 0 LSB Figure 4-51. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode 246 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.29 RRUM Instruction Set Description RRUM.A RRUM.[W] Syntax Operation Description Status Bits Mode Bits Example Rotate right through carry the 20-bit CPU register content Rotate right through carry the 16-bit CPU register content RRUM.A #n,Rdst 1≤n≤4 RRUM.W #n,Rdst or RRUM #n,Rdst 1≤n≤4 0 → MSB → MSB–1 ... LSB+1 → LSB → C The destination operand is shifted right by one, two, three, or four bit positions as shown in Figure 4-52. Zero is shifted into the MSB, the LSB is shifted into the carry bit. RRUM works like an unsigned division by 2, 4, 8, or 16. The word instruction RRUM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The unsigned address-word in R5 is divided by 16. RRUM.A #4,R5 ; R5 = R5 » 4. R5/16 Example The word in R6 is shifted right by one bit. The MSB R6.15 is loaded with 0. RRUM.W #1,R6 ; R6 = R6/2. R6.19:15 = 0 19 16 15 0 C 0000 MSB LSB 0 C0 19 MSB 0 LSB Figure 4-52. Rotate Right Unsigned RRUM[.W] and RRUM.A SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 247 Instruction Set Description 4.6.3.30 RRUX www.ti.com RRUX.A RRUX.[W] RRUX.B Syntax Operation Description Status Bits Mode Bits Example Shift right unsigned the 20-bit CPU register content Shift right unsigned the 16-bit CPU register content Shift right unsigned the 8-bit CPU register content RRUX.A Rdst RRUX.W Rdst RRUX Rdst RRUX.B Rdst C=0 → MSB → MSB–1 ... LSB+1 → LSB → C RRUX is valid for register mode only: the destination operand is shifted right by one bit position as shown in Figure 4-53. The word instruction RRUX.W clears the bits Rdst.19:16. The byte instruction RRUX.B clears the bits Rdst.19:8. Zero is shifted into the MSB, the LSB is shifted into the carry bit. N: Set if result is negative .A: dst.19 = 1, reset if dst.19 = 0 .W: dst.15 = 1, reset if dst.15 = 0 .B: dst.7 = 1, reset if dst.7 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The word in R6 is shifted right by 12 positions. RPT #12 RRUX.W R6 ; R6 = R6 » 12. R6.19:16 = 0 19 87 0 C 0--------------------0 MSB LSB 0 19 16 15 C 0 0 0 0 MSB 0 LSB 0 C0 19 MSB 0 LSB Figure 4-53. Rotate Right Unsigned RRUX(.B,.A) – Register Mode 248 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.31 SBCX Instruction Set Description * SBCX.A * SBCX.[W] * SBCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Subtract borrow (.NOT. carry) from destination address-word Subtract borrow (.NOT. carry) from destination word Subtract borrow (.NOT. carry) from destination byte SBCX.A dst SBCX dst or SBCX.W dst SBCX.B dst dst + 0FFFFFh + C → dst dst + 0FFFFh + C → dst dst + 0FFh + C → dst SBCX.A #0,dst SBCX #0,dst SBCX.B #0,dst The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise Set to 1 if no borrow, reset if borrow V: Set if an arithmetic overflow occurs, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUBX.B @R13,0(R12) SBCX.B 1(R12) ; Subtract LSDs ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Yes No Carry Bit 0 1 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 249 Instruction Set Description 4.6.3.32 SUBX www.ti.com SUBX.A SUBX.[W] SUBX.B Syntax Operation Description Status Bits Mode Bits Example Subtract source address-word from destination address-word Subtract source word from destination word Subtract source byte from destination byte SUBX.A src,dst SUBX src,dst or SUBX.W src,dst SUBX.B src,dst (.not. src) + 1 + dst → dst or dst – src → dst The source operand is subtracted from the destination operand. This is done by adding the 1s complement of the source + 1 to the destination. The source operand is not affected. The result is written to the destination operand. Both operands may be located in the full address space. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. A 20-bit constant 87654h is subtracted from EDE (LSBs) and EDE+2 (MSBs). SUBX.A #87654h,EDE ; Subtract 87654h from EDE+2|EDE Example A table word pointed to by R5 (20-bit address) is subtracted from R7. Jump to label TONI if R7 contains zero after the instruction. R5 is auto-incremented by two. R7.19:16 = 0. SUBX.W JZ ... @R5+,R7 TONI ; Subtract table number from R7. R5 + 2 ; R7 = @R5 (before subtraction) ; R7 <> @R5 (before subtraction) Example Byte CNT is subtracted from the byte R12 points to in the full address space. Address of CNT is within PC ± 512 K. SUBX.B CNT,0(R12) ; Subtract CNT from @R12 Note: Use SUBA for the following two cases for better density and execution. SUBX.A Rsrc,Rdst SUBX.A #imm20,Rdst 250 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.33 SUBCX Instruction Set Description SUBCX.A SUBCX.[W] SUBCX.B Syntax Operation Description Status Bits Mode Bits Example Subtract source address-word with carry from destination address-word Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBCX.A src,dst SUBCX src,dst or SUBCX.W src,dst SUBCX.B src,dst (.not. src) + C + dst → dst or dst – (src – 1) + C → dst The source operand is subtracted from the destination operand. This is made by adding the 1s complement of the source + carry to the destination. The source operand is not affected, the result is written to the destination operand. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. A 20-bit constant 87654h is subtracted from R5 with the carry from the previous instruction. SUBCX.A #87654h,R5 ; Subtract 87654h + C from R5 Example A 48-bit number (3 words) pointed to by R5 (20-bit address) is subtracted from a 48-bit counter in RAM, pointed to by R7. R5 auto-increments to point to the next 48-bit number. SUBX.W SUBCX.W SUBCX.W @R5+,0(R7) @R5+,2(R7) @R5+,4(R7) ; Subtract LSBs. R5 + 2 ; Subtract MIDs with C. R5 + 2 ; Subtract MSBs with C. R5 + 2 Example Byte CNT is subtracted from the byte R12 points to. The carry of the previous instruction is used. 20-bit addresses. SUBCX.B &CNT,0(R12) ; Subtract byte CNT from @R12 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 251 Instruction Set Description 4.6.3.34 SWPBX www.ti.com SWPBX.A SWPBX.[W] Syntax Operation Description Status Bits Mode Bits Example Swap bytes of lower word Swap bytes of word SWPBX.A dst SWPBX dst or SWPBX.W dst dst.15:8 ↔ dst.7:0 Register mode: Rn.15:8 are swapped with Rn.7:0. When the .A extension is used, Rn.19:16 are unchanged. When the .W extension is used, Rn.19:16 are cleared. Other modes: When the .A extension is used, bits 31:20 of the destination address are cleared, bits 19:16 are left unchanged, and bits 15:8 are swapped with bits 7:0. When the .W extension is used, bits 15:8 are swapped with bits 7:0 of the addressed word. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Exchange the bytes of RAM address-word EDE MOVX.A #23456h,&EDE SWPBX.A EDE ; 23456h -> EDE ; 25634h -> EDE Example Exchange the bytes of R5 MOVA #23456h,R5 SWPBX.W R5 ; 23456h -> R5 ; 05634h -> R5 Before SWPBX.A 19 16 15 87 0 X High Byte Low Byte After SWPBX.A 19 16 15 87 0 X Low Byte High Byte Figure 4-54. Swap Bytes SWPBX.A Register Mode Before SWPBX.A 31 20 19 16 15 X X High Byte 87 0 Low Byte After SWPBX.A 31 20 19 16 15 0 X Low Byte 87 0 High Byte Figure 4-55. Swap Bytes SWPBX.A In Memory 252 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Before SWPBX 19 16 15 X High Byte 87 Low Byte Instruction Set Description 0 After SWPBX 19 16 15 87 0 0 Low Byte High Byte Figure 4-56. Swap Bytes SWPBX[.W] Register Mode Before SWPBX 15 87 0 High Byte Low Byte After SWPBX 15 87 0 Low Byte High Byte Figure 4-57. Swap Bytes SWPBX[.W] In Memory SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 253 Instruction Set Description 4.6.3.35 SXTX www.ti.com SXTX.A SXTX.[W] Syntax Operation Description Status Bits Mode Bits Example Extend sign of lower byte to address-word Extend sign of lower byte to word SXTX.A dst SXTX dst or SXTX.W dst dst.7 → dst.15:8, Rdst.7 → Rdst.19:8 (Register mode) Register mode: The sign of the low byte of the operand (Rdst.7) is extended into the bits Rdst.19:8. Other modes: SXTX.A: the sign of the low byte of the operand (dst.7) is extended into dst.19:8. The bits dst.31:20 are cleared. SXTX[.W]: the sign of the low byte of the operand (dst.7) is extended into dst.15:8. N: Set if result is negative, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (C = .not.Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 8-bit data in EDE.7:0 is sign extended to 20 bits: EDE.19:8. Bits 31:20 located in EDE+2 are cleared. SXTX.A &EDE SXTX.A Rdst ; Sign extended EDE -> EDE+2/EDE 19 16 15 876 0 S SXTX.A dst 31 0 ...... 20 19 0 16 15 876 0 S Figure 4-58. Sign Extend SXTX.A SXTX[.W] Rdst 19 16 15 876 0 S SXTX[.W] dst 15 876 0 S Figure 4-59. Sign Extend SXTX[.W] 254 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.3.36 TSTX Instruction Set Description * TSTX.A * TSTX.[W] * TSTX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Test destination address-word Test destination word Test destination byte TSTX.A dst TSTX dst or TSTX.W dst TSTX.B dst dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 CMPX.A #0,dst CMPX #0,dst CMPX.B #0,dst The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. RAM byte LEO is tested; PC is pointing to upper memory. If it is negative, continue at LEONEG; if it is positive but not zero, continue at LEOPOS. LEOPOS LEONEG LEOZERO TSTX.B JN JZ ...... ...... ...... LEO LEONEG LEOZERO ; Test LEO ; LEO is negative ; LEO is zero ; LEO is positive but not zero ; LEO is negative ; LEO is zero SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 255 Instruction Set Description 4.6.3.37 XORX www.ti.com XORX.A XORX.[W] XORX.B Syntax Operation Description Status Bits Mode Bits Example Exclusive OR source address-word with destination address-word Exclusive OR source word with destination word Exclusive OR source byte with destination byte XORX.A src,dst XORX src,dst or XORX.W src,dst XORX.B src,dst src .xor. dst → dst The source and destination operands are exclusively ORed. The result is placed into the destination. The source operand is not affected. The previous contents of the destination are lost. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (carry = .not. Zero) V: Set if both operands are negative (before execution), reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Toggle bits in address-word CNTR (20-bit data) with information in address-word TONI (20-bit address) XORX.A TONI,&CNTR ; Toggle bits in CNTR Example A table word pointed to by R5 (20-bit address) is used to toggle bits in R6. XORX.W @R5,R6 ; Toggle bits in R6. R6.19:16 = 0 Example Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE (20-bit address) XORX.B EDE,R7 INV.B R7 ; Set different bits to 1 in R7 ; Invert low byte of R7. R7.19:8 = 0. 256 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Instruction Set Description 4.6.4 MSP430X Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode, except for the MOVA instruction. Restricting the addressing modes removes the need for the additional extension-word op-code, which improves code density and execution time. The MSP430X address instructions are described in the following sections. See Section 4.6.3 for MSP430X extended instructions and Section 4.6.2 for standard MSP430 instructions. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 257 Instruction Set Description 4.6.4.1 ADDA www.ti.com ADDA Syntax Operation Description Status Bits Mode Bits Example Add 20-bit source to a 20-bit destination register ADDA Rsrc,Rdst ADDA #imm20,Rdst src + Rdst → Rdst The 20-bit source operand is added to the 20-bit destination CPU register. The previous contents of the destination are lost. The source operand is not affected. N: Set if result is negative (Rdst.19 = 1), reset if positive (Rdst.19 = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the 20-bit result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R5 is increased by 0A4320h. The jump to TONI is performed if a carry occurs. ADDA JC ... #0A4320h,R5 TONI ; Add A4320h to 20-bit R5 ; Jump on carry ; No carry occurred 258 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.4.2 BRA Instruction Set Description * BRA Syntax Operation Emulation Description Status Bits Mode Bits Examples Branch to destination BRA dst dst → PC MOVA dst,PC An unconditional branch is taken to a 20-bit address anywhere in the full address space. All seven source addressing modes can be used. The branch instruction is an address-word instruction. If the destination address is contained in a memory location X, it is contained in two ascending words: X (LSBs) and (X + 2) (MSBs). N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Examples for all addressing modes are given. Immediate mode: Branch to label EDE located anywhere in the 20-bit address space or branch directly to address. BRA #EDE ; MOVA #imm20,PC BRA #01AA04h Symbolic mode: Branch to the 20-bit address contained in addresses EXEC (LSBs) and EXEC+2 (MSBs). EXEC is located at the address (PC + X) where X is within +32 K. Indirect addressing. BRA EXEC ; MOVA z16(PC),PC Note: If the 16-bit index is not sufficient, a 20-bit index may be used with the following instruction. MOVX.A EXEC,PC ; 1M byte range with 20-bit index Absolute mode: Branch to the 20-bit address contained in absolute addresses EXEC (LSBs) and EXEC+2 (MSBs). Indirect addressing. BRA &EXEC ; MOVA &abs20,PC Register mode: Branch to the 20-bit address contained in register R5. Indirect R5. BRA R5 ; MOVA R5,PC Indirect mode: Branch to the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. BRA @R5 ; MOVA @R5,PC SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 259 Instruction Set Description www.ti.com Indirect, Auto-Increment mode: Branch to the 20-bit address contained in the words pointed to by register R5 and increment the address in R5 afterwards by 4. The next time the S/W flow uses R5 as a pointer, it can alter the program execution due to access to the next address in the table pointed to by R5. Indirect, indirect R5. BRA @R5+ ; MOVA @R5+,PC. R5 + 4 Indexed mode: Branch to the 20-bit address contained in the address pointed to by register (R5 + X) (for example, a table with addresses starting at X). (R5 + X) points to the LSBs, (R5 + X + 2) points to the MSBs of the address. X is within R5 + 32 K. Indirect, indirect (R5 + X). BRA X(R5) ; MOVA z16(R5),PC Note: If the 16-bit index is not sufficient, a 20-bit index X may be used with the following instruction: MOVX.A X(R5),PC ; 1M byte range with 20-bit index 260 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.4.3 CALLA Instruction Set Description CALLA Syntax Operation Description Status Bits Mode Bits Examples Call a subroutine CALLA dst dst → tmp 20-bit dst is evaluated and stored SP – 2 → SP PC.19:16 → @SP updated PC with return address to TOS (MSBs) SP – 2 → SP PC.15:0 → @SP updated PC to TOS (LSBs) tmp → PC saved 20-bit dst to PC A subroutine call is made to a 20-bit address anywhere in the full address space. All seven source addressing modes can be used. The call instruction is an address-word instruction. If the destination address is contained in a memory location X, it is contained in two ascending words, X (LSBs) and (X + 2) (MSBs). Two words on the stack are needed for the return address. The return is made with the instruction RETA. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Examples for all addressing modes are given. Immediate mode: Call a subroutine at label EXEC or call directly an address. CALLA #EXEC CALLA #01AA04h ; Start address EXEC ; Start address 01AA04h Symbolic mode: Call a subroutine at the 20-bit address contained in addresses EXEC (LSBs) and EXEC+2 (MSBs). EXEC is located at the address (PC + X) where X is within +32 K. Indirect addressing. CALLA EXEC ; Start address at @EXEC. z16(PC) Absolute mode: Call a subroutine at the 20-bit address contained in absolute addresses EXEC (LSBs) and EXEC+2 (MSBs). Indirect addressing. CALLA &EXEC ; Start address at @EXEC Register mode: Call a subroutine at the 20-bit address contained in register R5. Indirect R5. CALLA R5 ; Start address at @R5 Indirect mode: Call a subroutine at the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. CALLA @R5 ; Start address at @R5 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 261 Instruction Set Description www.ti.com Indirect, Auto-Increment mode: Call a subroutine at the 20-bit address contained in the words pointed to by register R5 and increment the 20-bit address in R5 afterwards by 4. The next time the S/W flow uses R5 as a pointer, it can alter the program execution due to access to the next word address in the table pointed to by R5. Indirect, indirect R5. CALLA @R5+ ; Start address at @R5. R5 + 4 Indexed mode: Call a subroutine at the 20-bit address contained in the address pointed to by register (R5 + X); for example, a table with addresses starting at X. (R5 + X) points to the LSBs, (R5 + X + 2) points to the MSBs of the word address. X is within R5 + 32 K. Indirect, indirect (R5 + X). CALLA X(R5) ; Start address at @(R5+X). z16(R5) 262 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.4.4 CLRA * CLRA Syntax Operation Emulation Description Status Bits Example Clear 20-bit destination register CLRA Rdst 0 → Rdst MOVA #0,Rdst The destination register is cleared. Status bits are not affected. The 20-bit value in R10 is cleared. CLRA R10 ; 0 -> R10 Instruction Set Description SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 263 Instruction Set Description 4.6.4.5 CMPA www.ti.com CMPA Syntax Operation Description Status Bits Mode Bits Example Compare the 20-bit source with a 20-bit destination register CMPA Rsrc,Rdst CMPA #imm20,Rdst (.not. src) + 1 + Rdst or Rdst – src The 20-bit source operand is subtracted from the 20-bit destination CPU register. This is made by adding the 1s complement of the source + 1 to the destination register. The result affects only the status bits. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. A 20-bit immediate operand and R6 are compared. If they are equal, the program continues at label EQUAL. CMPA JEQ ... #12345h,R6 EQUAL ; Compare R6 with 12345h ; R5 = 12345h ; Not equal Example The 20-bit values in R5 and R6 are compared. If R5 is greater than (signed) or equal to R6, the program continues at label GRE. CMPA JGE ... R6,R5 GRE ; Compare R6 with R5 (R5 - R6) ; R5 >= R6 ; R5 < R6 264 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.4.6 DECDA Instruction Set Description * DECDA Syntax Operation Emulation Description Status Bits Mode Bits Example Double-decrement 20-bit destination register DECDA Rdst Rdst – 2 → Rdst SUBA #2,Rdst The destination register is decremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if Rdst contained 2, reset otherwise C: Reset if Rdst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is decremented by 2. DECDA R5 ; Decrement R5 by two SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 265 Instruction Set Description 4.6.4.7 INCDA www.ti.com * INCDA Syntax Operation Emulation Description Status Bits Mode Bits Example Double-increment 20-bit destination register INCDA Rdst Rdst + 2 → Rdst ADDA #2,Rdst The destination register is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if Rdst contained 0FFFFEh, reset otherwise Set if Rdst contained 0FFFEh, reset otherwise Set if Rdst contained 0FEh, reset otherwise C: Set if Rdst contained 0FFFFEh or 0FFFFFh, reset otherwise Set if Rdst contained 0FFFEh or 0FFFFh, reset otherwise Set if Rdst contained 0FEh or 0FFh, reset otherwise V: Set if Rdst contained 07FFFEh or 07FFFFh, reset otherwise Set if Rdst contained 07FFEh or 07FFFh, reset otherwise Set if Rdst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is incremented by two. INCDA R5 ; Increment R5 by two 266 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.4.8 MOVA Instruction Set Description MOVA Syntax Operation Description Status Bits Mode Bits Examples Move the 20-bit source to the 20-bit destination MOVA Rsrc,Rdst MOVA #imm20,Rdst MOVA z16(Rsrc),Rdst MOVA EDE,Rdst MOVA &abs20,Rdst MOVA @Rsrc,Rdst MOVA @Rsrc+,Rdst MOVA Rsrc,z16(Rdst) MOVA Rsrc,&abs20 src → Rdst Rsrc → dst The 20-bit source operand is moved to the 20-bit destination. The source operand is not affected. The previous content of the destination is lost. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Copy 20-bit value in R9 to R8 MOVA R9,R8 ; R9 -> R8 Write 20-bit immediate value 12345h to R12 MOVA #12345h,R12 ; 12345h -> R12 Copy 20-bit value addressed by (R9 + 100h) to R8. Source operand in addresses (R9 + 100h) LSBs and (R9 + 102h) MSBs. MOVA 100h(R9),R8 ; Index: + 32 K. 2 words transferred Move 20-bit value in 20-bit absolute addresses EDE (LSBs) and EDE+2 (MSBs) to R12 MOVA &EDE,R12 ; &EDE -> R12. 2 words transferred Move 20-bit value in 20-bit addresses EDE (LSBs) and EDE+2 (MSBs) to R12. PC index ± 32 K. MOVA EDE,R12 ; EDE -> R12. 2 words transferred Copy 20-bit value R9 points to (20 bit address) to R8. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9,R8 ; @R9 -> R8. 2 words transferred SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 267 Instruction Set Description www.ti.com Copy 20-bit value R9 points to (20 bit address) to R8. R9 is incremented by four afterwards. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9+,R8 ; @R9 -> R8. R9 + 4. 2 words transferred. Copy 20-bit value in R8 to destination addressed by (R9 + 100h). Destination operand in addresses @(R9 + 100h) LSBs and @(R9 + 102h) MSBs. MOVA R8,100h(R9) ; Index: +- 32 K. 2 words transferred Move 20-bit value in R13 to 20-bit absolute addresses EDE (LSBs) and EDE+2 (MSBs) MOVA R13,&EDE ; R13 -> EDE. 2 words transferred Move 20-bit value in R13 to 20-bit addresses EDE (LSBs) and EDE+2 (MSBs). PC index ± 32 K. MOVA R13,EDE ; R13 -> EDE. 2 words transferred 268 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.4.9 RETA Instruction Set Description * RETA Syntax Operation Emulation Description Status Bits Mode Bits Example Return from subroutine RETA @SP → PC.15:0 LSBs (15:0) of saved PC to PC.15:0 SP + 2 → SP @SP → PC.19:16 MSBs (19:16) of saved PC to PC.19:16 SP + 2 → SP MOVA @SP+,PC The 20-bit return address information, pushed onto the stack by a CALLA instruction, is restored to the PC. The program continues at the address following the subroutine call. The SR bits SR.11:0 are not affected. This allows the transfer of information with these bits. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Call a subroutine SUBR from anywhere in the 20-bit address space and return to the address after the CALLA SUBR CALLA ... PUSHM.A ... POPM.A RETA #SUBR #2,R14 #2,R14 ; Call subroutine starting at SUBR ; Return by RETA to here ; Save R14 and R13 (20 bit data) ; Subroutine code ; Restore R13 and R14 (20 bit data) ; Return (to full address space) SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 269 Instruction Set Description 4.6.4.10 TSTA www.ti.com * TSTA Syntax Operation Emulation Description Status Bits Mode Bits Example Test 20-bit destination register TSTA Rdst dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 CMPA #0,Rdst The destination register is compared with zero. The status bits are set according to the result. The destination register is not affected. N: Set if destination register is negative, reset if positive Z: Set if destination register contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TSTA R7 JN R7NEG JZ R7ZERO ...... ...... ...... ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero 270 CPUX SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.6.4.11 SUBA Instruction Set Description SUBA Syntax Operation Description Status Bits Mode Bits Example Subtract 20-bit source from 20-bit destination register SUBA Rsrc,Rdst SUBA #imm20,Rdst (.not.src) + 1 + Rdst → Rdst or Rdst – src → Rdst The 20-bit source operand is subtracted from the 20-bit destination register. This is made by adding the 1s complement of the source + 1 to the destination. The result is written to the destination register, the source is not affected. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB (Rdst.19), reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is subtracted from R6. If a carry occurs, the program continues at label TONI. SUBA R5,R6 JC TONI ... ; R6 - R5 -> R6 ; Carry occurred ; No carry SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated CPUX 271 Chapter 5 SLAU144J – December 2004 – Revised July 2013 Basic Clock Module+ The basic clock module+ provides the clocks for MSP430x2xx devices. This chapter describes the operation of the basic clock module+ of the MSP430x2xx device family. Topic ........................................................................................................................... Page 5.1 Basic Clock Module+ Introduction ..................................................................... 273 5.2 Basic Clock Module+ Operation ........................................................................ 275 5.3 Basic Clock Module+ Registers ......................................................................... 282 272 Basic Clock Module+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Basic Clock Module+ Introduction 5.1 Basic Clock Module+ Introduction The basic clock module+ supports low system cost and ultralow power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The basic clock module+ can be configured to operate without any external components, with one external resistor, with one or two external crystals, or with resonators, under full software control. The basic clock module+ includes two, three or four clock sources: • LFXT1CLK: Low-frequency/high-frequency oscillator that can be used with low-frequency watch crystals or external clock sources of 32768 Hz or with standard crystals, resonators, or external clock sources in the 400-kHz to 16-MHz range. • XT2CLK: Optional high-frequency oscillator that can be used with standard crystals, resonators, or external clock sources in the 400-kHz to 16-MHz range. • DCOCLK: Internal digitally controlled oscillator (DCO). • VLOCLK: Internal very low power, low frequency oscillator with 12-kHz typical frequency. Three clock signals are available from the basic clock module+: • ACLK: Auxiliary clock. ACLK is software selectable as LFXT1CLK or VLOCLK. ACLK is divided by 1, 2, 4, or 8. ACLK is software selectable for individual peripheral modules. • MCLK: Master clock. MCLK is software selectable as LFXT1CLK, VLOCLK, XT2CLK (if available onchip), or DCOCLK. MCLK is divided by 1, 2, 4, or 8. MCLK is used by the CPU and system. • SMCLK: Sub-main clock. SMCLK is software selectable as LFXT1CLK, VLOCLK, XT2CLK (if available on-chip), or DCOCLK. SMCLK is divided by 1, 2, 4, or 8. SMCLK is software selectable for individual peripheral modules. The block diagram of the basic clock module+ in the MSP430F2xx devices is shown in Figure 5-1. The block diagram of the basic clock module+ in the MSP430AFE2xx devices is shown in Figure 5-2. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Basic Clock Module+ 273 Basic Clock Module+ Introduction www.ti.com Internal VLOCLK LP/LF Oscillator† 10 Min. Pulse LFXT1CLK Filter else OSCOFF LFXT1Sx XTS DIVAx Divider /1/2/4/8 ACLK Auxillary Clock XIN XOUT 0V LF XT† LFOff XT1Off 0V XCAPx LFXT1 Oscillator XT2IN XT2OFF XT2S XT Min. Pulse Filter Connected only when XT2 not present on−chip SELMx 00 01 10 11 DIVMx CPUOFF Divider /1/2/4/8 0 1 MCLK Main System Clock XT2OUT XT2 Oscillator MODx VCC DCOR SCG0 RSELx 0 1 Rosc off DC Generator DCOx n DCO n+1 Modulator SELS 0 1 Min. Puls Filter DCOCLK 0 1 DIVSx Divider /1/2/4/8 SCG1 0 1 SMCLK Sub System Clock Figure 5-1. Basic Clock Module+ Block Diagram − MSP430F2xx NOTE: † Device-Specific Clock Variations Not all clock features are available on all MSP430x2xx devices: MSP430G22x0: LFXT1 is not present, XT2 is not present, ROSC is not supported. MSP430F20xx, MSP430G2xx1, MSP430G2xx2, MSP430G2xx3: LFXT1 does not support HF mode, XT2 is not present, ROSC is not supported. MSP430x21x1: Internal LP/LF oscillator is not present, XT2 is not present, ROSC is not supported. MSP430x21x2: XT2 is not present. MSP430F22xx, MSP430x23x0: XT2 is not present. 274 Basic Clock Module+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Internal VLOCLK 10 LP/LF else OSCOFF LFXT1Sx XT2IN XT2OFF XT2Sx XT XT2OUT XT2 Oscillator Min. Pulse Filter MODx Basic Clock Module+ Operation DIVAx Divider /1/2/4/8 ACLK Auxillary Clock SELMx 00 01 10 11 DIVMx CPUOFF Divider /1/2/4/8 0 1 MCLK Main System Clock VCC SCG0 RSELx off DC Generator DCOx n DCO n+1 Modulator 0 Min. Puls 1 Filter DCOCLK SELS 0 1 DIVSx SCG1 Divider /1/2/4/8 0 1 SMCLK Sub System Clock Figure 5-2. Basic Clock Module+ Block Diagram − MSP430AFE2xx NOTE: LFXT1 is not present in MSP430AFE2xx devices. 5.2 Basic Clock Module+ Operation After a PUC, MCLK and SMCLK are sourced from DCOCLK at ~1.1 MHz (see the device-specific data sheet for parameters) and ACLK is sourced from LFXT1CLK in LF mode with an internal load capacitance of 6 pF. Status register control bits SCG0, SCG1, OSCOFF, and CPUOFF configure the MSP430 operating modes and enable or disable portions of the basic clock module+ (see the System Resets, Interrupts and Operating Modes chapter). The DCOCTL, BCSCTL1, BCSCTL2, and BCSCTL3 registers configure the basic clock module+. The basic clock module+ can be configured or reconfigured by software at any time during program execution, for example: CLR.B BIS.B BIS.B &DCOCTL #RSEL2+RSEL1+RSEL0,&BCSCTL1 #DCO2+DCO1+DCO0,&DCOCTL ; Select lowest DCOx ; and MODx settings ; Select range 7 ; Select max DCO tap SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Basic Clock Module+ 275 Basic Clock Module+ Operation www.ti.com 5.2.1 Basic Clock Module+ Features for Low-Power Applications Conflicting requirements typically exist in battery-powered applications: • Low clock frequency for energy conservation and time keeping • High clock frequency for fast reaction to events and fast burst processing capability • Clock stability over operating temperature and supply voltage The basic clock module+ addresses the above conflicting requirements by allowing the user to select from the three available clock signals: ACLK, MCLK, and SMCLK. For optimal low-power performance, ACLK can be sourced from a low-power 32768-Hz watch crystal (if available), providing a stable time base for the system and low-power standby operation, or from the internal low-frequency oscillator when crystalaccurate time keeping is not required. The MCLK can be configured to operate from the on-chip DCO that can be activated when requested by interrupt-driven events. The SMCLK can be configured to operate from a crystal or the DCO, depending on peripheral requirements. A flexible clock distribution and divider system is provided to fine tune the individual clock requirements. 5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) The internal very-low-power low-frequency oscillator (VLO) provides a typical frequency of 12 kHz (see device-specific data sheet for parameters) without requiring a crystal. VLOCLK source is selected by setting LFXT1Sx = 10 when XTS = 0. The OSCOFF bit disables the VLO for LPM4. The LFXT1 crystal oscillators are disabled when the VLO is selected reducing current consumption. The VLO consumes no power when not being used. Devices without LFXT1 (for example, the MSP430G22x0) should be configured to use the VLO as ACLK. 5.2.3 LFXT1 Oscillator The LFXT1 oscillator is not implemented in the MSP430G22x0 device family. The LFXT1 oscillator supports ultra-low current consumption using a 32768-Hz watch crystal in LF mode (XTS = 0). A watch crystal connects to XIN and XOUT without any other external components. The software-selectable XCAPx bits configure the internally provided load capacitance for the LFXT1 crystal in LF mode. This capacitance can be selected as 1 pF, 6 pF, 10 pF, or 12.5 pF typical. Additional external capacitors can be added if necessary. The LFXT1 oscillator also supports high-speed crystals or resonators when in HF mode (XTS = 1, XCAPx = 00). The high-speed crystal or resonator connects to XIN and XOUT and requires external capacitors on both terminals. These capacitors should be sized according to the crystal or resonator specifications. When LFXT1 is in HF mode, the LFXT1Sx bits select the range of operation. LFXT1 may be used with an external clock signal on the XIN pin in either LF or HF mode when LFXT1Sx = 11, OSCOFF = 0, and XCAPx = 00. When used with an external signal, the external frequency must meet the data sheet parameters for the chosen mode. When the input frequency is below the specified lower limit, the LFXT1OF bit may be set preventing the CPU from being clocked with LFXT1CLK. Software can disable LFXT1 by setting OSCOFF, if LFXT1CLK does not source SMCLK or MCLK, as shown in Figure 5-3. 276 Basic Clock Module+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com XTS ACLK_request OSCOFF MCLK_request CPUOFF SELM0 XSELM1 XT2 Basic Clock Module+ Operation LFXT1Off LFOff XT1Off SMCLK_request SCG1 SELS XT2 is an Internal Signal XT2 = 0: Devices without XT2 oscillator XT2 = 1: Devices with XT2 oscillator Figure 5-3. Off Signals for the LFXT1 Oscillator NOTE: LFXT1 Oscillator Characteristics Low-frequency crystals often require hundreds of milliseconds to start up, depending on the crystal. Ultralow-power oscillators such as the LFXT1 in LF mode should be guarded from noise coupling from other sources. The crystal should be placed as close as possible to the MSP430 with the crystal housing grounded and the crystal traces guarded with ground traces. 5.2.4 XT2 Oscillator Some devices have a second crystal oscillator, XT2. XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode. The XT2Sx bits select the range of operation of XT2. The XT2OFF bit disables the XT2 oscillator if XT2CLK is not used for MCLK or SMCLK as shown in Figure 5-4. XT2 may be used with external clock signals on the XT2IN pin when XT2Sx = 11 and XT2OFF = 0. When used with an external signal, the external frequency must meet the data sheet parameters for XT2. When the input frequency is below the specified lower limit, the XT2OF bit may be set to prevent the CPU from being clocked with XT2CLK. XT2OFF MCLK_request CPUOFF SELM0 XSELM1 XT2off (Internal Signal) SMCLK_request SCG1 SELS Figure 5-4. Off Signals for Oscillator XT2 5.2.5 Digitally-Controlled Oscillator (DCO) The DCO is an integrated digitally controlled oscillator. The DCO frequency can be adjusted by software using the DCOx, MODx, and RSELx bits. 5.2.5.1 Disabling the DCO Software can disable DCOCLK by setting SCG0 when it is not used to source SMCLK or MCLK in active mode, as shown in Figure 5-5. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Basic Clock Module+ 277 Basic Clock Module+ Operation MCLK_request CPUOFF XSELM1 SMCLK_request SCG1 DQ SELS DCOCLK XT2CLK SYNC DCOCLK SCG0 Figure 5-5. On/Off Control of DCO www.ti.com DCOCLK_on 1: on 0: off DCO_Gen_on 1: on 0: off 5.2.5.2 Adjusting the DCO Frequency After a PUC, RSELx = 7 and DCOx = 3, allowing the DCO to start at a mid-range frequency. MCLK and SMCLK are sourced from DCOCLK. Because the CPU executes code from MCLK, which is sourced from the fast-starting DCO, code execution typically begins from PUC in less than 2 µs. The typical DCOx and RSELx ranges and steps are shown in Figure 5-6. The frequency of DCOCLK is set by the following functions: • The four RSELx bits select one of sixteen nominal frequency ranges for the DCO. These ranges are defined for an individual device in the device-specific data sheet. • The three DCOx bits divide the DCO range selected by the RSELx bits into 8 frequency steps, separated by approximately 10%. • The five MODx bits, switch between the frequency selected by the DCOx bits and the next higher frequency set by DCOx+1. When DCOx = 07h, the MODx bits have no effect because the DCO is already at the highest setting for the selected RSELx range. fDCO 20000 kHz RSEL = 15 1000 kHz 100 kHz RSEL = 7 RSEL=0 DCO=0 DCO=1 DCO=2 DCO=3 DCO=4 DCO=5 DCO=6 DCO=7 Figure 5-6. Typical DCOx Range and RSELx Steps Each MSP430F2xx device (and most MSP430G2xx devices; see device-specific data sheets) has calibrated DCOCTL and BCSCTL1 register settings for specific frequencies stored in information memory segment A. To use the calibrated settings, the information is copied into the DCOCTL and BCSCTL1 registers. The calibrated settings affect the DCOx, MODx, and RSELx bits, and clear all other bits, except XT2OFF which remains set. The remaining bits of BCSCTL1 can be set or cleared as needed with BIS.B or BIC.B instructions. ; Set DCO to 1 MHz: CLR.B &DCOCTL ; Select lowest DCOx ; and MODx settings 278 Basic Clock Module+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MOV.B MOV.B &CALBC1_1MHZ,&BCSCTL1 &CALDCO_1MHZ,&DCOCTL ; Set range ; Set DCO step + modulation Basic Clock Module+ Operation 5.2.5.3 Using an External Resistor (ROSC) for the DCO Some MSP430F2xx devices provide the option to source the DCO current through an external resistor, ROSC, tied to DVCC, when DCOR = 1. In this case, the DCO has the same characteristics as MSP430x1xx devices, and the RSELx setting is limited to 0 to 7 with the RSEL3 ignored. This option provides an additional method to tune the DCO frequency by varying the resistor value. See the device-specific data sheet for parameters. 5.2.6 DCO Modulator The modulator mixes two DCO frequencies, fDCO and fDCO+1 to produce an intermediate effective frequency between fDCO and fDCO+1 and spread the clock energy, reducing electromagnetic interference (EMI). The modulator mixes fDCO and fDCO+1 for 32 DCOCLK clock cycles and is configured with the MODx bits. When MODx = 0 the modulator is off. The modulator mixing formula is: t = (32 – MODx) × tDCO + MODx × tDCO+1 Because fDCO is lower than the effective frequency and fDCO+1 is higher than the effective frequency, the error of the effective frequency integrates to zero. It does not accumulate. The error of the effective frequency is zero every 32 DCOCLK cycles. Figure 5-7 shows the modulator operation. The modulator settings and DCO control are configured with software. The DCOCLK can be compared to a stable frequency of known value and adjusted with the DCOx, RSELx, and MODx bits. See http://www.msp430.com for application notes and example code on configuring the DCO. MODx 31 24 16 15 5 4 3 2 Lower DCO Tap Frequency fDCO 1 0 Upper DCO Tap Frequency fDCO+1 Figure 5-7. Modulator Patterns 5.2.7 Basic Clock Module+ Fail-Safe Operation The basic clock module+ incorporates an oscillator-fault fail-safe feature. This feature detects an oscillator fault for LFXT1 and XT2 as shown in Figure 5-8. The available fault conditions are: • Low-frequency oscillator fault (LFXT1OF) for LFXT1 in LF mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Basic Clock Module+ 279 Basic Clock Module+ Operation www.ti.com • High-frequency oscillator fault (LFXT1OF) for LFXT1 in HF mode • High-frequency oscillator fault (XT2OF) for XT2 The crystal oscillator fault bits LFXT1OF, and XT2OF are set if the corresponding crystal oscillator is turned on and not operating properly. The fault bits remain set as long as the fault condition exists and are automatically cleared if the enabled oscillators function normally. The OFIFG oscillator-fault flag is set and latched at POR or when an oscillator fault (LFXT1OF, or XT2OF) is detected. When OFIFG is set, MCLK is sourced from the DCO, and if OFIE is set, the OFIFG requests an NMI interrupt. When the interrupt is granted, the OFIE is reset automatically. The OFIFG flag must be cleared by software. The source of the fault can be identified by checking the individual fault bits. If a fault is detected for the crystal oscillator sourcing the MCLK, the MCLK is automatically switched to the DCO for its clock source. This does not change the SELMx bit settings. This condition must be handled by user software. LF_OscFault XTS LFXT1OF XT1_OscFault XT2_OscFault XT2OF Figure 5-8. Oscillator-Fault Logic Set OFIFG Flag 5.2.7.1 Sourcing MCLK from a Crystal After a PUC, the basic clock module+ uses DCOCLK for MCLK. If required, MCLK may be sourced from LFXT1 or XT2 - if available. The sequence to switch the MCLK source from the DCO clock to the crystal clock (LFXT1CLK or XT2CLK) is: 1. Turn on the crystal oscillator and select the appropriate mode 2. Clear the OFIFG flag 3. Wait at least 50 µs 4. Test OFIFG, and repeat steps 2 through 4 until OFIFG remains cleared. ; Select LFXT1 (HF mode) for MCLK BIC.W #OSCOFF,SR BIS.B #XTS,&BCSCTL1 MOV.B #LFXT1S0,&BCSCTL3 L1 BIC.B #OFIFG,&IFG1 MOV.W #0FFh,R15 L2 DEC.W R15 JNZ L2 BIT.B #OFIFG,&IFG1 JNZ L1 BIS.B #SELM1+SELM0,&BCSCTL2 ; Turn on osc. ; HF mode ; 1-3MHz Crystal ; Clear OFIFG ; Delay ; ; ; Re-test OFIFG ; Repeat test if needed ; Select LFXT1CLK 5.2.8 Synchronization of Clock Signals When switching MCLK or SMCLK from one clock source to another, the switch is synchronized to avoid critical race conditions as shown in Figure 5-9: • The current clock cycle continues until the next rising edge. • The clock remains high until the next rising edge of the new clock. • The new clock source is selected and continues with a full high period. 280 Basic Clock Module+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DCOCLK Select LFXT1CLK Basic Clock Module+ Operation LFXT1CLK MCLK DCOCLK Wait for LFXT1CLK LFXT1CLK Figure 5-9. Switch MCLK from DCOCLK to LFXT1CLK SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Basic Clock Module+ 281 Basic Clock Module+ Registers 5.3 Basic Clock Module+ Registers The basic clock module+ registers are listed in Table 5-1. Table 5-1. Basic Clock Module+ Registers Register Short Form Register Type DCO control register DCOCTL Read/write Basic clock system control 1 BCSCTL1 Read/write Basic clock system control 2 BCSCTL2 Read/write Basic clock system control 3 BCSCTL3 Read/write SFR interrupt enable register 1 IE1 Read/write SFR interrupt flag register 1 IFG1 Read/write (1) Some of the register bits are also PUC initialized (see Section 5.3.2). (2) The initial state of BCSCTL3 is 000h in the MSP430AFE2xx devices. Address 056h 057h 058h 053h 000h 002h www.ti.com Initial State 060h with PUC 087h with POR(1) Reset with PUC 005h with PUC(2) Reset with PUC Reset with PUC 282 Basic Clock Module+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5.3.1 DCOCTL, DCO Control Register Basic Clock Module+ Registers 7 rw-0 DCOx MODx 6 5 4 3 2 1 0 DCOx MODx rw-1 rw-1 rw-0 rw-0 rw-0 rw-0 rw-0 Bits 7-5 Bits 4-0 DCO frequency select. These bits select which of the eight discrete DCO frequencies within the range defined by the RSELx setting is selected. Modulator selection. These bits define how often the f DCO+1 frequency is used within a period of 32 DCOCLK cycles. During the remaining clock cycles (32-MOD) the f DCO frequency is used. Not useable when DCOx = 7. 5.3.2 BCSCTL1, Basic Clock System Control Register 1 7 XT2OFF rw-(1) 6 XTS(1) (2) rw-(0) 5 rw-(0) DIVAx 4 rw-(0) 3 rw-0 2 1 RSELx rw-1 rw-1 0 rw-1 XT2OFF XTS DIVAx RSELx Bit 7 Bit 6 Bits 5-4 Bits 3-0 XT2 off. This bit turns off the XT2 oscillator 0 XT2 is on 1 XT2 is off if it is not used for MCLK or SMCLK. LFXT1 mode select. 0 Low-frequency mode 1 High-frequency mode Divider for ACLK 00 /1 01 /2 10 /4 11 /8 Range select. Sixteen different frequency ranges are available. The lowest frequency range is selected by setting RSELx = 0. RSEL3 is ignored when DCOR = 1. (1) XTS = 1 is not supported in MSP430x20xx and MSP430G2xx devices (see Figure 5-1 and Figure 5-2 for details on supported settings for all devices). (2) This bit is reserved in the MSP430AFE2xx devices. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Basic Clock Module+ 283 Basic Clock Module+ Registers 5.3.3 BCSCTL2, Basic Clock System Control Register 2 www.ti.com 7 6 SELMx rw-0 rw-0 5 4 DIVMx rw-0 rw-0 3 SELS rw-0 2 1 DIVSx rw-0 rw-0 0 DCOR (1) (2) rw-0 SELMx DIVMx SELS DIVSx DCOR Bits 7-6 Bits 5-4 Bit 3 Bits 2-1 Bit 0 Select MCLK. These bits select the MCLK source. 00 DCOCLK 01 DCOCLK 10 XT2CLK when XT2 oscillator present on-chip. LFXT1CLK or VLOCLK when XT2 oscillator not present on-chip. 11 LFXT1CLK or VLOCLK Divider for MCLK 00 /1 01 /2 10 /4 11 /8 Select SMCLK. This bit selects the SMCLK source. 0 DCOCLK 1 XT2CLK when XT2 oscillator present. LFXT1CLK or VLOCLK when XT2 oscillator not present Divider for SMCLK 00 /1 01 /2 10 /4 11 /8 DCO resistor select. Not available in all devices. See the device-specific data sheet. 0 Internal resistor 1 External resistor (1) Does not apply to MSP430x20xx or MSP430x21xx devices. (2) This bit is reserved in the MSP430AFE2xx devices. 284 Basic Clock Module+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5.3.4 BCSCTL3, Basic Clock System Control Register 3 Basic Clock Module+ Registers 7 6 XT2Sx rw-0 rw-0 5 4 LFXT1Sx (1) rw-0 rw-0 3 2 XCAPx (2) rw-0 rw-1 1 XT2OF (3) r0 0 LFXT1OF (2) r-(1) XT2Sx LFXT1Sx XCAPx XT2OF LFXT1OF Bits 7-6 Bits 5-4 Bits 3-2 Bit 1 Bit 0 XT2 range select. These bits select the frequency range for XT2. 00 0.4- to 1-MHz crystal or resonator 01 1- to 3-MHz crystal or resonator 10 3- to 16-MHz crystal or resonator 11 Digital external 0.4- to 16-MHz clock source Low-frequency clock select and LFXT1 range select. These bits select between LFXT1 and VLO when XTS = 0, and select the frequency range for LFXT1 when XTS = 1. When XTS = 0: 00 32768-Hz crystal on LFXT1 01 Reserved 10 VLOCLK (Reserved in MSP430F21x1 devices) 11 Digital external clock source When XTS = 1 (Not applicable for MSP430x20xx devices, MSP430G2xx1/2/3) 00 0.4- to 1-MHz crystal or resonator 01 1- to 3-MHz crystal or resonator 10 3- to 16-MHz crystal or resonator 11 Digital external 0.4- to 16-MHz clock source LFXT1Sx definition for MSP430AFE2xx devices: 00 Reserved 01 Reserved 10 VLOCLK 11 Reserved Oscillator capacitor selection. These bits select the effective capacitance seen by the LFXT1 crystal when XTS = 0. If XTS = 1 or if LFXT1Sx = 11 XCAPx should be 00. 00 ~1 pF 01 ~6 pF 10 ~10 pF 11 ~12.5 pF XT2 oscillator fault 0 No fault condition present 1 Fault condition present LFXT1 oscillator fault 0 No fault condition present 1 Fault condition present (1) MSP430G22x0: The LFXT1Sx bits should be programmed to 10b during the initialization and start-up code to select VLOCLK (for more details refer to Digital I/O chapter). The other bits are reserved and should not be altered. (2) This bit is reserved in the MSP430AFE2xx devices. (3) Does not apply to MSP430x2xx, MSP430x21xx, or MSP430x22xx devices. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Basic Clock Module+ 285 Basic Clock Module+ Registers 5.3.5 IE1, Interrupt Enable Register 1 www.ti.com 7 6 5 4 3 2 1 0 OFIE (1) rw-0 OFIE Bits 7-2 Bit 1 Bits 0 These bits may be used by other modules. See device-specific data sheet. Oscillator fault interrupt enable. This bit enables the OFIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled This bit may be used by other modules. See device-specific data sheet. (1) MSP430G22x0: This bit should not be set. 5.3.6 IFG1, Interrupt Flag Register 1 7 6 5 4 3 2 1 0 OFIFG (1) rw-1 Bits 7-2 These bits may be used by other modules. See device-specific data sheet. OFIFG Bit 1 Oscillator fault interrupt flag. Because other bits in IFG1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 No interrupt pending 1 Interrupt pending Bits 0 This bit may be used by other modules. See device-specific data sheet. (1) MSP430G22x0: The LFXT1 oscillator pins are not available in this device. The oscillator fault flag will always be set by hardware. The interrupt enable bit should not be set. 286 Basic Clock Module+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 6 SLAU144J – December 2004 – Revised July 2013 DMA Controller The DMA controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller of the MSP430x2xx device family. Topic ........................................................................................................................... Page 6.1 DMA Introduction ............................................................................................ 288 6.2 DMA Operation ................................................................................................ 290 6.3 DMA Registers ................................................................................................ 302 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 287 DMA Introduction www.ti.com 6.1 DMA Introduction The direct memory access (DMA) controller transfers data from one address to another, without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC12 conversion memory to RAM. Devices that contain a DMA controller may have one, two, or three DMA channels available. Therefore, depending on the number of DMA channels available, some features described in this chapter are not applicable to all devices. Using the DMA controller can increase the throughput of peripheral modules. It can also reduce system power consumption by allowing the CPU to remain in a low-power mode without having to awaken to move data to or from a peripheral. The DMA controller features include: • Up to three independent transfer channels • Configurable DMA channel priorities • Requires only two MCLK clock cycles per transfer • Byte or word and mixed byte/word transfer capability • Block sizes up to 65535 bytes or words • Configurable transfer trigger selections • Selectable edge or level-triggered transfer • Four addressing modes • Single, block, or burst-block transfer modes The DMA controller block diagram is shown in Figure 6-1. 288 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA0TSELx 4 DMAREQ 0000 TACCR2_CCIFG TBCCR2_CCIFG 0001 0010 USCI A0 data receive 0011 USCI A0 data transmit 0100 DAC12_0IFG ADC12_IFGx 0101 0110 TACCR0_CCIFG 0111 TBCCR0_CCIFG 1000 USCI A1 data Rx 1001 Halt USCI A1 data Tx Multiplier ready 1010 1011 USCI B0 data receive 1100 USCI B0 data transmit 1101 DMA2IFG 1110 DMAE0 1111 DMA1TSELx 4 DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USCI A0 data receive USCI A0 data transmit DAC12_0IFG ADC12_IFGx TACCR0_CCIFG TBCCR0_CCIFG USCI A1 data Rx USCI A1 data Tx Multiplier ready USCI B0 data receive USCI B0 data transmit DMA0IFG DMAE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DMA2TSEL 4 DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USCI A0 data receive USCI A0 data transmit DAC12_0IFG ADC12_IFGx TACCR0_CCIFG TBCCR0_CCIFG USCI A1 data Rx USCI A1 data Tx Multiplier ready USCI B0 data receive USCI B0 data transmit DMA1IFG DMAE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DMA Priority And Controll JTAG Active ROUNDROBIN NMI Interrupt Request ENNMI DMADSTINCRx DMADTx 2 DMADSTBYTE 3 DMA Channel 0 DMA0SA DT DMA0DA DMA0SZ 2 DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx DMADSTBYTE 2 3 DMA Channel 1 DMA1SA DT DMA1DA DMA1SZ 2 DMASRSBYTE DMASRCINCRx DMAEN Address Space DMADSTINCRx DMADTx 2 DMADSTBYTE 3 DMA Channel 2 DMA2SA DT DMA2DA DMA2SZ 2 DMASRSBYTE DMASRCINCRx DMAEN DMAONFETCH Halt CPU Figure 6-1. DMA Controller Block Diagram DMA Introduction SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 289 DMA Operation www.ti.com 6.2 DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 6.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable. For example, channel 0 may transfer between two fixed addresses, while channel 1 transfers between two blocks of addresses. The addressing modes are shown in Figure 6-2. The addressing modes are: • Fixed address to fixed address • Fixed address to block of addresses • Block of addresses to fixed address • Block of addresses to block of addresses The addressing modes are configured with the DMASRCINCRx and DMADSTINCRx control bits. The DMASRCINCRx bits select if the source address is incremented, decremented, or unchanged after each transfer. The DMADSTINCRx bits select if the destination address is incremented, decremented, or unchanged after each transfer. Transfers may be byte-to-byte, word-to-word, byte-to-word, or word-to-byte. When transferring word-tobyte, only the lower byte of the source-word transfers. When transferring byte-to-word, the upper byte of the destination-word is cleared when the transfer occurs. DMA Controller Address Space DMA Controller Address Space Fixed Address To Fixed Address Fixed Address To Block Of Addresses DMA Controller Address Space DMA Controller Address Space Block Of Addresses To Fixed Address Block Of Addresses To Block Of Addresses Figure 6-2. DMA Addressing Modes 290 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation 6.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 6-1. Each channel is individually configurable for its transfer mode. For example, channel 0 may be configured in single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates in repeated block mode. The transfer mode is configured independently from the addressing mode. Any addressing mode can be used with any transfer mode. Two types of data can be transferred selectable by the DMAxCTL DSTBYTE and SRCBYTE fields. The source and/or destination location can be either byte or word data. It is also possible to transfer byte to byte, word to word or any combination. DMADTx 000 001 010, 011 100 101 110, 111 Table 6-1. DMA Transfer Modes Transfer Mode Single transfer Block transfer Burst-block transfer Repeated single transfer Repeated block transfer Repeated burst-block transfer Description Each transfer requires a trigger. DMAEN is automatically cleared when DMAxSZ transfers have been made. A complete block is transferred with one trigger. DMAEN is automatically cleared at the end of the block transfer. CPU activity is interleaved with a block transfer. DMAEN is automatically cleared at the end of the burst-block transfer. Each transfer requires a trigger. DMAEN remains enabled. A complete block is transferred with one trigger. DMAEN remains enabled. CPU activity is interleaved with a block transfer. DMAEN remains enabled. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 291 DMA Operation www.ti.com 6.2.2.1 Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state diagram is shown in Figure 6-3. The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer. The DMAxSZ register is decremented after each transfer. When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set. When DMADTx = 0, the DMAEN bit is cleared automatically when DMAxSZ decrements to zero and must be set again for another transfer to occur. In repeated single transfer mode, the DMA controller remains enabled with DMAEN = 1, and a transfer occurs every time a trigger occurs. DMAEN = 0 Reset DMAEN = 0 DMAREQ = 0 DMAEN = 1 T_Size → DMAxSZ [ DMADTx = 0 AND DMAxSZ = 0] DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd OR DMAEN = 0 DMAABORT = 1 DMAEN = 0 Idle DMAABORT=0 DMAREQ = 0 Wait for Trigger DMAxSZ > 0 AND DMAEN = 1 2 x MCLK [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] [ENNMI = 1 AND NMI event] OR [DMALEVEL = 1 AND Trigger = 0] Hold CPU, Transfer one word/byte T_Size → DMAxSZ DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMADTx = 4 AND DMAxSZ = 0 AND DMAEN = 1 Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd Figure 6-3. DMA Single Transfer State Diagram 292 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation 6.2.2.2 Block Transfers In block transfer mode, a transfer of a complete block of data occurs after one trigger. When DMADTx = 1, the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered. After a block transfer has been triggered, further trigger signals occurring during the block transfer are ignored. The block transfer state diagram is shown in Figure 6-4. The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer of the block. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block. The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block. When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set. During a block transfer, the CPU is halted until the complete block has been transferred. The block transfer takes 2 x MCLK x DMAxSZ clock cycles to complete. CPU execution resumes with its previous state after the block transfer is complete. In repeated block transfer mode, the DMAEN bit remains set after completion of the block transfer. The next trigger after the completion of a repeated block transfer triggers another block transfer. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 293 DMA Operation www.ti.com DMAEN = 0 DMAEN = 0 DMAREQ = 0 T_Size → DMAxSZ Reset DMAEN = 1 [DMADTx = 1 AND DMAxSZ = 0] OR DMAEN = 0 DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMAABORT = 1 DMAEN = 0 Idle DMAABORT=0 DMAREQ = 0 T_Size → DMAxSZ DMAxSA → T_SourceAdd DMAxDA → T_DestAdd Wait for Trigger 2 x MCLK [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] DMADTx = 5 AND DMAxSZ = 0 AND DMAEN = 1 [ENNMI = 1 AND NMI event] OR [DMALEVEL = 1 AND Trigger = 0] Hold CPU, Transfer one word/byte Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd DMAxSZ > 0 Figure 6-4. DMA Block Transfer State Diagram 294 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation 6.2.2.3 Burst-Block Transfers In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes 2 MCLK cycles after every four byte/word transfers of the block resulting in 20% CPU execution capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared. DMAEN must be set again before another burst-block transfer can be triggered. After a burst-block transfer has been triggered, further trigger signals occurring during the burst-block transfer are ignored. The burstblock transfer state diagram is shown in Figure 6-5. The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer of the block. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block. The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block. When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set. In repeated burst-block mode the DMAEN bit remains set after completion of the burst-block transfer and no further trigger signals are required to initiate another burst-block transfer. Another burst-block transfer begins immediately after completion of a burst-block transfer. In this case, the transfers must be stopped by clearing the DMAEN bit, or by an NMI interrupt when ENNMI is set. In repeated burst-block mode the CPU executes at 20% capacity continuously until the repeated burst-block transfer is stopped. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 295 DMA Operation DMAEN = 0 DMAEN = 0 DMAREQ = 0 T_Size → DMAxSZ Reset DMAEN = 1 DMAEN = 0 [DMADTx = {2, 3} AND DMAxSZ = 0] OR DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMAEN = 0 DMAABORT = 1 Idle www.ti.com DMAABORT=0 Wait for Trigger 2 x MCLK [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] [ENNMI = 1 AND NMI event] OR [DMALEVEL = 1 AND Trigger = 0] Hold CPU, Transfer one word/byte Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd T_Size → DMAxSZ DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMAxSZ > 0 DMAxSZ > 0 AND a multiple of 4 words/bytes were transferred 2 x MCLK Burst State (release CPU for 2xMCLK) DMAxSZ > 0 [DMADTx = {6, 7} AND DMAxSZ = 0] Figure 6-5. DMA Burst-Block Transfer State Diagram 296 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation 6.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in Table 6-2. The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur. When selecting the trigger, the trigger must not have already occurred, or the transfer will not take place. For example, if the TACCR2 CCIFG bit is selected as a trigger, and it is already set, no transfer will occur until the next time the TACCR2 CCIFG bit is set. 6.2.3.1 Edge-Sensitive Triggers When DMALEVEL = 0, edge-sensitive triggers are used and the rising edge of the trigger signal initiates the transfer. In single-transfer mode, each transfer requires its own trigger. When using block or burstblock modes, only one trigger is required to initiate the block or burst-block transfer. 6.2.3.2 Level-Sensitive Triggers When DMALEVEL = 1, level-sensitive triggers are used. For proper operation, level-sensitive triggers can only be used when external trigger DMAE0 is selected as the trigger. DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set. The trigger signal must remain high for a block or burst-block transfer to complete. If the trigger signal goes low during a block or burst-block transfer, the DMA controller is held in its current state until the trigger goes back high or until the DMA registers are modified by software. If the DMA registers are not modified by software, when the trigger signal goes high again, the transfer resumes from where it was when the trigger signal went low. When DMALEVEL = 1, transfer modes selected when DMADTx = {0, 1, 2, 3} are recommended because the DMAEN bit is automatically reset after the configured transfer. 6.2.3.3 Halting Executing Instructions for DMA Transfers The DMAONFETCH bit controls when the CPU is halted for a DMA transfer. When DMAONFETCH = 0, the CPU is halted immediately and the transfer begins when a trigger is received. When DMAONFETCH = 1, the CPU finishes the currently executing instruction before the DMA controller halts the CPU and the transfer begins. NOTE: DMAONFETCH Must Be Used When The DMA Writes To Flash If the DMA controller is used to write to flash memory, the DMAONFETCH bit must be set. Otherwise, unpredictable operation can result. DMAxTSELx 0000 0001 0010 0011 0100 Table 6-2. DMA Trigger Operation Operation A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer starts A transfer is triggered when the TACCR2 CCIFG flag is set. The TACCR2 CCIFG flag is automatically reset when the transfer starts. If the TACCR2 CCIE bit is set, the TACCR2 CCIFG flag will not trigger a transfer. A transfer is triggered when the TBCCR2 CCIFG flag is set. The TBCCR2 CCIFG flag is automatically reset when the transfer starts. If the TBCCR2 CCIE bit is set, the TBCCR2 CCIFG flag will not trigger a transfer. A transfer is triggered when serial interface receives new data. Devices with USCI_A0 module: A transfer is triggered when USCI_A0 receives new data. UCA0RXIFG is automatically reset when the transfer starts. If UCA0RXIE is set, the UCA0RXIFG flag will not trigger a transfer. A transfer is triggered when serial interface is ready to transmit new data. Devices with USCI_A0 module: A transfer is triggered when USCI_A0 is ready to transmit new data. UCA0TXIFG is automatically reset when the transfer starts. If UCA0TXIE is set, the UCA0TXIFG flag will not trigger a transfer. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 297 DMA Operation www.ti.com DMAxTSELx 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 6-2. DMA Trigger Operation (continued) Operation A transfer is triggered when the DAC12_0CTL DAC12IFG flag is set. The DAC12_0CTL DAC12IFG flag is automatically cleared when the transfer starts. If the DAC12_0CTL DAC12IE bit is set, the DAC12_0CTL DAC12IFG flag will not trigger a transfer. A transfer is triggered by an ADC12IFGx flag. When single-channel conversions are performed, the corresponding ADC12IFGx is the trigger. When sequences are used, the ADC12IFGx for the last conversion in the sequence is the trigger. A transfer is triggered when the conversion is completed and the ADC12IFGx is set. Setting the ADC12IFGx with software will not trigger a transfer. All ADC12IFGx flags are automatically reset when the associated ADC12MEMx register is accessed by the DMA controller. A transfer is triggered when the TACCR0 CCIFG flag is set. The TACCR0 CCIFG flag is automatically reset when the transfer starts. If the TACCR0 CCIE bit is set, the TACCR0 CCIFG flag will not trigger a transfer. A transfer is triggered when the TBCCR0 CCIFG flag is set. The TBCCR0 CCIFG flag is automatically reset when the transfer starts. If the TBCCR0 CCIE bit is set, the TBCCR0 CCIFG flag will not trigger a transfer. A transfer is triggered when the UCA1RXIFG flag is set. UCA1RXIFG is automatically reset when the transfer starts. If URXIE1 is set, the UCA1RXIFG flag will not trigger a transfer. A transfer is triggered when the UCA1TXIFG flag is set. UCA1TXIFG is automatically reset when the transfer starts. If UTXIE1 is set, the UCA1TXIFG flag will not trigger a transfer. A transfer is triggered when the hardware multiplier is ready for a new operand. No transfer is triggered. Devices with USCI_B0 module: A transfer is triggered when USCI_B0 receives new data. UCB0RXIFG is automatically reset when the transfer starts. If UCB0RXIE is set, the UCB0RXIFG flag will not trigger a transfer. No transfer is triggered. Devices with USCI_B0 module: A transfer is triggered when USCI_B0 is ready to transmit new data. UCB0TXIFG is automatically reset when the transfer starts. If UCB0TXIE is set, the UCB0TXIFG flag will not trigger a transfer. A transfer is triggered when the DMAxIFG flag is set. DMA0IFG triggers channel 1, DMA1IFG triggers channel 2, and DMA2IFG triggers channel 0. None of the DMAxIFG flags are automatically reset when the transfer starts. A transfer is triggered by the external trigger DMAE0. 6.2.4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress: • A single, block, or burst-block transfer may be stopped with an NMI interrupt, if the ENNMI bit is set in register DMACTL1. • A burst-block transfer may be stopped by clearing the DMAEN bit. 298 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation 6.2.5 DMA Channel Priorities The default DMA channel priorities are DMA0-DMA1-DMA2. If two or three triggers happen simultaneously or are pending, the channel with the highest priority completes its transfer (single, block or burst-block transfer) first, then the second priority channel, then the third priority channel. Transfers in progress are not halted if a higher priority channel is triggered. The higher priority channel waits until the transfer in progress completes before starting. The DMA channel priorities are configurable with the ROUNDROBIN bit. When the ROUNDROBIN bit is set, the channel that completes a transfer becomes the lowest priority. The order of the priority of the channels always stays the same, DMA0-DMA1-DMA2 (see Table 6-3). DMA Priority DMA0 - DMA1 - DMA2 DMA2 - DMA0 - DMA1 DMA0 - DMA1 - DMA2 Table 6-3. Channel Priorities Transfer Occurs DMA1 DMA2 DMA0 New DMA Priority DMA2 - DMA0 - DMA1 DMA0 - DMA1 - DMA2 DMA1 - DMA2 - DMA0 When the ROUNDROBIN bit is cleared the channel priority returns to the default priority. 6.2.6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after synchronization, and one cycle of wait time after the transfer. Because the DMA controller uses MCLK, the DMA cycle time is dependent on the MSP430 operating mode and clock system setup. If the MCLK source is active, but the CPU is off, the DMA controller will use the MCLK source for each transfer, without re-enabling the CPU. If the MCLK source is off, the DMA controller will temporarily restart MCLK, sourced with DCOCLK, for the single transfer or complete block or burst-block transfer. The CPU remains off, and after the transfer completes, MCLK is turned off. The maximum DMA cycle time for all operating modes is shown in Table 6-4. Table 6-4. Maximum Single-Transfer DMA Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time Active mode MCLK = DCOCLK 4 MCLK cycles Active mode MCLK = LFXT1CLK 4 MCLK cycles Low-power mode LPM0/1 MCLK = DCOCLK 5 MCLK cycles Low-power mode LPM3/4 MCLK = DCOCLK 5 MCLK cycles + 6 µs(1) Low-power mode LPM0/1 MCLK = LFXT1CLK 5 MCLK cycles Low-power mode LPM3 MCLK = LFXT1CLK 5 MCLK cycles Low-power mode LPM4 MCLK = LFXT1CLK 5 MCLK cycles + 6 µs(1) (1) The additional 6 µs are needed to start the DCOCLK. It is the t(LPMx) parameter in the data sheet. 6.2.7 Using DMA With System Interrupts DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the completion of the transfer. NMI interrupts can interrupt the DMA controller if the ENNMI bit is set. System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine or other routine must execute with no interruptions, the DMA controller should be disabled prior to executing the routine. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 299 DMA Operation www.ti.com 6.2.8 DMA Controller Interrupts Each DMA channel has its own DMAIFG flag. Each DMAIFG flag is set in any mode, when the corresponding DMAxSZ register counts to zero. If the corresponding DMAIE and GIE bits are set, an interrupt request is generated. All DMAIFG flags source only one DMA controller interrupt vector and, on some devices, the interrupt vector may be shared with other modules. Please refer to the device specific datasheet for further details. For these devices, software must check the DMAIFG and respective module flags to determine the source of the interrupt. The DMAIFG flags are not reset automatically and must be reset by software. Additionally, some devices utilize the DMAIV register. All DMAIFG flags are prioritized, with DMA0IFG being the highest, and combined to source a single interrupt vector. The highest priority enabled interrupt generates a number in the DMAIV register. This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled DMA interrupts do not affect the DMAIV value. Any access, read or write, of the DMAIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. For example, assume that DMA0 has the highest priority. If the DMA0IFG and DMA2IFG flags are set when the interrupt service routine accesses the DMAIV register, DMA0IFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the DMA2IFG will generate another interrupt. The following software example shows the recommended use of DMAIV and the handling overhead. The DMAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. Example 6-1. DMAIV Software Example ;Interrupt handler for DMA0IFG, DMA1IFG, DMA2IFG Cycles DMA_HND ... ; Interrupt latency 6 ADD &DMAIV,PC ; Add offset to Jump table 3 RETI ; Vector 0: No interrupt 5 JMP DMA0_HND ; Vector 2: DMA channel 0 2 JMP DMA1_HND ; Vector 4: DMA channel 1 2 JMP DMA2_HND ; Vector 6: DMA channel 2 2 RETI ; Vector 8: Reserved 5 RETI ; Vector 10: Reserved 5 RETI ; Vector 12: Reserved 5 RETI ; Vector 14: Reserved 5 DMA2_HND ... RETI ; Vector 6: DMA channel 2 ; Task starts here ; Back to main program 5 DMA1_HND ... RETI ; Vector 4: DMA channel 1 ; Task starts here ; Back to main program 5 DMA0_HND ... RETI ; Vector 2: DMA channel 0 ; Task starts here ; Back to main program 5 6.2.9 Using the USCI_B I2C Module with the DMA Controller The USCI_B I2C module provides two trigger sources for the DMA controller. The USCI_B I2C module can trigger a transfer when new I2C data is received and when data is needed for transmit. A transfer is triggered if UCB0RXIFG is set. The UCB0RXIFG is cleared automatically when the DMA controller acknowledges the transfer. If UCB0RXIE is set, UCB0RXIFG will not trigger a transfer. 300 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation A transfer is triggered if UCB0TXIFG is set. The UCB0TXIFG is cleared automatically when the DMA controller acknowledges the transfer. If UCB0TXIE is set, UCB0TXIFG will not trigger a transfer. 6.2.10 Using ADC12 with the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from any ADC12MEMx register to another location. DMA transfers are done without CPU intervention and independently of any low-power modes. The DMA controller increases throughput of the ADC12 module, and enhances lowpower applications allowing the CPU to remain off while data transfers occur. DMA transfers can be triggered from any ADC12IFGx flag. When CONSEQx = {0,2} the ADC12IFGx flag for the ADC12MEMx used for the conversion can trigger a DMA transfer. When CONSEQx = {1,3}, the ADC12IFGx flag for the last ADC12MEMx in the sequence can trigger a DMA transfer. Any ADC12IFGx flag is automatically cleared when the DMA controller accesses the corresponding ADC12MEMx. 6.2.11 Using DAC12 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the DAC12_xDAT register. DMA transfers are done without CPU intervention and independently of any low-power modes. The DMA controller increases throughput to the DAC12 module, and enhances low-power applications allowing the CPU to remain off while data transfers occur. Applications requiring periodic waveform generation can benefit from using the DMA controller with the DAC12. For example, an application that produces a sinusoidal waveform may store the sinusoid values in a table. The DMA controller can continuously and automatically transfer the values to the DAC12 at specific intervals creating the sinusoid with zero CPU execution. The DAC12_xCTL DAC12IFG flag is automatically cleared when the DMA controller accesses the DAC12_xDAT register. 6.2.12 Writing to Flash With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the Flash memory. DMA transfers are done without CPU intervention and independent of any low-power modes. The DMA controller performs the move of the data word/byte to the Flash. The write timing control is done by the Flash controller. Write transfers to the Flash memory succeed if the Flash controller is set up prior to the DMA transfer and if the Flash is not busy. To set up the Flash controller for write accesses, see the Flash Memory Controller chapter. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 301 DMA Registers 6.3 DMA Registers The DMA registers are listed in Table 6-5. Register DMA control 0 DMA control 1 DMA interrupt vector DMA channel 0 control DMA channel 0 source address DMA channel 0 destination address DMA channel 0 transfer size DMA channel 1 control DMA channel 1 source address DMA channel 1 destination address DMA channel 1 transfer size DMA channel 2 control DMA channel 2 source address DMA channel 2 destination address DMA-channel 2 transfer size Table 6-5. DMA Registers Short Form DMACTL0 DMACTL1 DMAIV DMA0CTL DMA0SA DMA0DA DMA0SZ DMA1CTL DMA1SA DMA1DA DMA1SZ DMA2CTL DMA2SA DMA2DA DMA2SZ Register Type Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write www.ti.com Address 0122h 0124h 0126h 01D0h 01D2h 01D6h 01DAh 01DCh 01DEh 01E2h 01E6h 01E8h 01EAh 01EEh 01F2h Initial State Reset with POR Reset with POR Reset with POR Reset with POR Unchanged Unchanged Unchanged Reset with POR Unchanged Unchanged Unchanged Reset with POR Unchanged Unchanged Unchanged 302 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.3.1 DMACTL0, DMA Control Register 0 15 rw-(0) 7 rw-(0) Reserved DMA2TSELx DMA1TSELx DMA0TSELx 14 13 Reserved rw-(0) rw-(0) 12 rw-(0) 11 rw-(0) 10 9 DMA2TSELx rw-(0) rw-(0) 6 5 DMA1TSELx rw-(0) rw-(0) 4 rw-(0) 3 rw-(0) 2 1 DMA0TSELx rw-(0) rw-(0) Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0 Reserved DMA trigger select. These bits select the DMA transfer trigger. 0000 DMAREQ bit (software trigger) 0001 TACCR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 Serial data received UCA0RXIFG 0100 Serial data transmit ready UCA0TXIFG 0101 DAC12_0CTL DAC12IFG bit 0110 ADC12 ADC12IFGx bit 0111 TACCR0 CCIFG bit 1000 TBCCR0 CCIFG bit 1001 Serial data received UCA1RXIFG 1010 Serial data transmit ready UCA1TXIFG 1011 Multiplier ready 1100 Serial data received UCB0RXIFG 1101 Serial data transmit ready UCB0TXIFG 1110 DMA0IFG bit triggers DMA channel 1 DMA1IFG bit triggers DMA channel 2 DMA2IFG bit triggers DMA channel 0 1111 External trigger DMAE0 Same as DMA2TSELx Same as DMA2TSELx DMA Registers 8 rw-(0) 0 rw-(0) 6.3.2 DMACTL1, DMA Control Register 1 15 0 r0 7 0 r0 Reserved DMAONFETCH ROUNDROBIN ENNMI 14 0 r0 6 0 r0 Bits 15-3 Bit 2 Bit 1 Bit 0 13 12 11 10 9 8 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 5 4 3 2 1 0 0 0 0 DMAON ROUND ENNMI FETCH ROBIN r0 r0 r0 rw-(0) rw-(0) rw-(0) Reserved. Read only. Always read as 0. DMA on fetch 0 The DMA transfer occurs immediately. 1 The DMA transfer occurs on next instruction fetch after the trigger. Round robin. This bit enables the round-robin DMA channel priorities. 0 DMA channel priority is DMA0 - DMA1 - DMA2 1 DMA channel priority changes with each transfer Enable NMI. This bit enables the interruption of a DMA transfer by an NMI interrupt. When an NMI interrupts a DMA transfer, the current transfer is completed normally, further transfers are stopped, and DMAABORT is set. 0 NMI interrupt does not interrupt DMA transfer 1 NMI interrupt interrupts a DMA transfer SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 303 DMA Registers 6.3.3 DMAxCTL, DMA Channel x Control Register www.ti.com 15 Reserved rw-(0) 7 DMADST BYTE rw-(0) Reserved DMADTx DMADSTINCRx DMASRCINCRx DMADSTBYTE DMASRCBYTE DMALEVEL DMAEN DMAIFG DMAIE 14 rw-(0) 13 DMADTx rw-(0) 12 rw-(0) 11 10 DMADSTINCRx rw-(0) rw-(0) 9 8 DMASRCINCRx rw-(0) rw-(0) 6 5 4 3 2 1 0 DMASRC BYTE DMALEVEL DMAEN DMAIFG DMAIE DMAABORT DMAREQ rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Bit 15 Reserved Bits 14-12 DMA Transfer mode. 000 Single transfer 001 Block transfer 010 Burst-block transfer 011 Burst-block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst-block transfer 111 Repeated burst-block transfer Bits 11-10 DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer. When DMADSTBYTE = 1, the destination address increments/decrements by one. When DMADSTBYTE = 0, the destination address increments/decrements by two. The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented. DMAxDA is not incremented or decremented. 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented Bits 9-8 DMA source increment. This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer. When DMASRCBYTE = 1, the source address increments/decrements by one. When DMASRCBYTE = 0, the source address increments/decrements by two. The DMAxSA is copied into a temporary register and the temporary register is incremented or decremented. DMAxSA is not incremented or decremented. 00 Source address is unchanged 01 Source address is unchanged 10 Source address is decremented 11 Source address is incremented Bit 7 DMA destination byte. This bit selects the destination as a byte or word. 0 Word 1 Byte Bit 6 DMA source byte. This bit selects the source as a byte or word. 0 Word 1 Byte Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive triggers. 0 Edge sensitive (rising edge) 1 Level sensitive (high level) Bit 4 DMA enable 0 Disabled 1 Enabled Bit 3 DMA interrupt flag 0 No interrupt pending 1 Interrupt pending Bit 2 DMA interrupt enable 0 Disabled 1 Enabled 304 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMAABORT DMAREQ Bit 1 Bit 0 DMA Registers DMA Abort. This bit indicates if a DMA transfer was interrupt by an NMI. 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0 No DMA start 1 Start DMA 6.3.4 DMAxSA, DMA Source Address Register 15 r0 7 r0 15 rw 7 rw DMAxSA 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 6 5 4 3 2 1 0 Reserved DMAxSAx r0 r0 r0 rw rw rw rw 14 13 12 11 10 9 8 DMAxSAx rw rw rw rw rw rw rw 6 5 4 3 2 1 0 DMAxSAx rw rw rw rw rw rw rw Bits 15-0 DMA source address The source address register points to the DMA source address for single transfers or the first source address for block transfers. The source address register remains unchanged during block and burst-block transfers. Devices that have addressable memory range 64 KB or below contain a single word for the DMAxSA. The upper word is automatically cleared when writing using word operations. Reads from this location are always read as zero. Devices that have addressable memory range beyond 64 KB contain an additional word for the source address. Bits 15-4 of this additional word are reserved and always read as zero. When writing to DMAxSA with word formats, this additional word is automatically cleared. Reads of this additional word using word formats, are always read as zero. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 305 DMA Registers 6.3.5 DMAxDA, DMA Destination Address Register www.ti.com 15 r0 7 r0 15 rw 7 rw DMAxDA 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 6 5 4 3 2 1 0 Reserved DMAxDAx r0 r0 r0 rw rw rw rw 14 13 12 11 10 9 8 DMAxDAx rw rw rw rw rw rw rw 6 5 4 3 2 1 0 DMAxDAx rw rw rw rw rw rw rw Bits 15-0 DMA destination address The destination address register points to the DMA destination address for single transfers or the first destination address for block transfers. The destination address register remains unchanged during block and burst-block transfers. Devices that have addressable memory range 64 KB or below contain a single word for the DMAxDA. Devices that have addressable memory range beyond 64 KB contain an additional word for the destination address. Bits 15-4 of this additional word are reserved and always read as zero. When writing to DMAxDA with word formats, this additional word is automatically cleared. Reads of this additional word using word formats, are always read as zero. 6.3.6 DMAxSZ, DMA Size Address Register 15 rw 7 rw DMAxSZx 14 rw 6 rw Bits 15-0 13 12 11 10 9 8 DMAxSZx rw rw rw rw rw rw 5 4 3 2 1 0 DMAxSZx rw rw rw rw rw rw DMA size. The DMA size register defines the number of byte/word data per block transfer. DMAxSZ register decrements with each word or byte transfer. When DMAxSZ decrements to 0, it is immediately and automatically reloaded with its previously initialized value. 00000h Transfer is disabled 00001h One byte or word to be transferred 00002h Two bytes or words have to be transferred ⋮ 0FFFFh 65535 bytes or words have to be transferred 306 DMA Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.3.7 DMAIV, DMA Interrupt Vector Register 15 0 r0 7 0 r0 DMAIVx DMAIV Contents 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 14 13 12 0 0 0 r0 r0 r0 6 5 4 0 0 0 r0 r0 r0 Bits 15-0 DMA interrupt vector value Interrupt Source Interrupt Flag No interrupt pending DMA channel 0 DMA channel 1 DMA channel 2 Reserved Reserved Reserved Reserved DMA0IFG DMA1IFG DMA2IFG - 11 0 r0 3 r--(0) Interrupt Priority Highest Lowest 10 0 r0 2 DMAIVx r--(0) DMA Registers 9 8 0 0 r0 r0 1 0 0 r--(0) r0 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated DMA Controller 307 Chapter 7 SLAU144J – December 2004 – Revised July 2013 Flash Memory Controller This chapter describes the operation of the MSP430x2xx flash memory controller. Topic ........................................................................................................................... Page 7.1 Flash Memory Introduction ............................................................................... 309 7.2 Flash Memory Segmentation ............................................................................. 309 7.3 Flash Memory Operation .................................................................................. 311 7.4 Flash Memory Registers ................................................................................... 323 308 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Introduction 7.1 Flash Memory Introduction The MSP430 flash memory is bit-, byte-, and word-addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations. The controller has four registers, a timing generator, and a voltage generator to supply program and erase voltages. MSP430 flash memory features include: • Internal programming voltage generation • Bit, byte, or word programmable • Ultralow-power operation • Segment erase and mass erase • Marginal 0 and marginal 1 read mode (optional, see the device-specific data sheet) Figure 7-1 shows the block diagram of the flash memory and controller. NOTE: Minimum VCC during flash write or erase The minimum VCC voltage during a flash write or erase operation is 2.2 V. If VCC falls below 2.2 V during write or erase, the result of the write or erase is unpredictable. MAB FCTL1 MDB Address Latch Data Latch FCTL2 FCTL3 FCTL4 Enable Address Latch Flash Memory Array Timing Generator Enable Data Latch Programming Voltage Generator Figure 7-1. Flash Memory Module Block Diagram 7.2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments. Single bits, bytes, or words can be written to flash memory, but the segment is the smallest size of flash memory that can be erased. The flash memory is partitioned into main and information memory sections. There is no difference in the operation of the main and information memory sections. Code or data can be located in either section. The differences between the two sections are the segment size and the physical addresses. The information memory has four 64-byte segments. The main memory has one or more 512-byte segments. See the device-specific data sheet for the complete memory map of a device. The segments are further divided into blocks. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Flash Memory Controller 309 Flash Memory Segmentation www.ti.com Figure 7-2 shows the flash segmentation using an example of 32-KB flash that has eight main segments and four information segments. 0x0FFFF 0x0F000 0x010FF 0x01000 32-kbyte Flash Main Memory 512-byte Flash Information Memory 0x0FFFF 0x0FE00 0x0FDFF 0x0FC00 Segment 0 Segment 1 Segment 2 Segment 61 Segment 62 Segment 63 0x08000 0x010FF Segment A 0x0FFFF 0x0FFC0 0x0FFBF 0x0FF80 0x0FF7F 0x0FF40 0x0FF3F 0x0FF00 0x0FFFF 0x0FEC0 0x0FEBF 0x0FE80 0x0FE7F 0x0FE40 0x0FE3F 0x0FE00 Block Block Block Block Block Block Block Block Segment B Segment C Segment D 0x01000 Figure 7-2. Flash Memory Segments, 32-KB Example 7.2.1 SegmentA SegmentA of the information memory is locked separately from all other segments with the LOCKA bit. When LOCKA = 1, SegmentA cannot be written or erased and all information memory is protected from erasure during a mass erase or production programming. When LOCKA = 0, SegmentA can be erased and written as any other flash memory segment, and all information memory is erased during a mass erase or production programming. The state of the LOCKA bit is toggled when a 1 is written to it. Writing a 0 to LOCKA has no effect. This allows existing flash programming routines to be used unchanged. ; Unlock SegmentA BIT #LOCKA,&FCTL3 JZ SEGA_UNLOCKED MOV #FWKEY+LOCKA,&FCTL3 SEGA_UNLOCKED ; SegmentA is unlocked ; Test LOCKA ; Already unlocked? ; No, unlock SegmentA ; Yes, continue ; Lock SegmentA BIT #LOCKA,&FCTL3 JNZ SEGA_LOCKED MOV #FWKEY+LOCKA,&FCTL3 SEGA_LOCKED ; SegmentA is locked ; Test LOCKA ; Already locked? ; No, lock SegmentA ; Yes, continue 310 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Operation 7.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are off, and the memory operates identically to ROM. MSP430 flash memory is in-system programmable (ISP) without the need for additional external voltage. The CPU can program its own flash memory. The flash memory write and erase modes are selected with the BLKWRT, WRT, MERAS, and ERASE bits and are: • Byte or word write • Block write • Segment erase • Mass erase (all main memory segments) • All erase (all segments) Reading from or writing to flash memory while it is being programmed or erased is prohibited. If CPU execution is required during the write or erase, the code to be executed must be in RAM. Any flash update can be initiated from within flash memory or RAM. 7.3.1 Flash Memory Timing Generator Write and erase operations are controlled by the flash timing generator shown in Figure 7-3. The flash timing generator operating frequency, fFTG, must be in the range from approximately 257 kHz to approximately 476 kHz (see device-specific data sheet). FSSELx FN5 ........... FN0 PUC EMEX ACLK 00 MCLK 01 SMCLK 10 SMCLK 11 fFTG Divider, 1−64 Reset Flash Timing Generator BUSY WAIT Figure 7-3. Flash Memory Timing Generator Block Diagram 7.3.1.1 Flash Timing Generator Clock Selection The flash timing generator can be sourced from ACLK, SMCLK, or MCLK. The selected clock source should be divided using the FNx bits to meet the frequency requirements for fFTG. If the fFTG frequency deviates from the specification during the write or erase operation, the result of the write or erase may be unpredictable, or the flash memory may be stressed above the limits of reliable operation. If a clock failure is detected during a write or erase operation, the operation is aborted, the FAIL flag is set, and the result of the operation is unpredictable. While a write or erase operation is active the selected clock source can not be disabled by putting the MSP430 into a low-power mode. The selected clock source remains active until the operation is completed before being disabled. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Flash Memory Controller 311 Flash Memory Operation www.ti.com 7.3.2 Erasing Flash Memory The erased level of a flash memory bit is 1. Each bit can be programmed from 1 to 0 individually but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is a segment. There are three erase modes selected with the ERASE and MERAS bits listed in Table 7-1. MERAS 0 1 1 ERASE 1 0 1 Table 7-1. Erase Modes Erase Mode Segment erase Mass erase (all main memory segments) LOCKA = 0: Erase main and information flash memory. LOCKA = 1: Erase only main flash memory. Any erase is initiated by a dummy write into the address range to be erased. The dummy write starts the flash timing generator and the erase operation. Figure 7-4 shows the erase cycle timing. The BUSY bit is set immediately after the dummy write and remains set throughout the erase cycle. BUSY, MERAS, and ERASE are automatically cleared when the cycle completes. The erase cycle timing is not dependent on the amount of flash memory present on a device. Erase cycle times are equivalent for all MSP430F2xx and MSP430G2xx devices. Generate Programming Voltage Erase Operation Active Remove Programming Voltage Erase Time, VCC Current Consumption is Increased BUSY tmass erase = 10593/fFTG, tsegment erase = 4819/fFTG Figure 7-4. Erase Cycle Timing A dummy write to an address not in the range to be erased does not start the erase cycle, does not affect the flash memory, and is not flagged in any way. This errant dummy write is ignored. 312 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Operation 7.3.2.1 Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM. When a flash segment erase operation is initiated from within flash memory, all timing is controlled by the flash controller, and the CPU is held while the erase cycle completes. After the erase cycle completes, the CPU resumes code execution with the instruction following the dummy write. When initiating an erase cycle from within flash memory, it is possible to erase the code needed for execution after the erase. If this occurs, CPU execution is unpredictable after the erase cycle. The flow to initiate an erase from flash is shown in Figure 7-5. Disable watchdog Setup flash controller and erase mode Dummy write Set LOCK=1, re-enable watchdog Figure 7-5. Erase Cycle from Within Flash Memory ; Segment Erase from flash. 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2 MOV #FWKEY, &FCTL3 ; Clear LOCK MOV #FWKEY+ERASE, &FCTL1 ; Enable segment erase CLR &0FC10h ; Dummy write, erase S1 MOV #FWKEY+LOCK, &FCTL3 ; Done, set LOCK ... ; Re-enable WDT? SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Flash Memory Controller 313 Flash Memory Operation www.ti.com 7.3.2.2 Initiating an Erase from RAM Any erase cycle may be initiated from RAM. In this case, the CPU is not held and can continue to execute code from RAM. The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again. If a flash access occurs while BUSY = 1, it is an access violation, ACCVIFG is set, and the erase results are unpredictable. The flow to initiate an erase from flash from RAM is shown in Figure 7-6. Disable watchdog yes BUSY = 1 Setup flash controller and erase mode Dummy write yes BUSY = 1 Set LOCK = 1, re-enable watchdog Figure 7-6. Erase Cycle from Within RAM ; Segment Erase from RAM. 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY, &FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWKEY+FSSEL1+FN0, &FCTL2 ; SMCLK/2 MOV #FWKEY&FCTL3 ; Clear LOCK MOV #FWKEY+ERASE, &FCTL1 ; Enable erase CLR &0FC10h ; Dummy write, erase S1 L2 BIT #BUSY, &FCTL3 ; Test BUSY JNZ L2 ; Loop while busy MOV #FWKEY+LOCK&FCTL3 ; Done, set LOCK ... ; Re-enable WDT? 314 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.3.3 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed in Table 7-2. Flash Memory Operation BLKWRT 0 1 Table 7-2. Write Modes WRT 1 1 Write Mode Byte or word write Block write Both write modes use a sequence of individual write instructions, but using the block write mode is approximately twice as fast as byte or word mode, because the voltage generator remains on for the complete block write. Any instruction that modifies a destination can be used to modify a flash location in either byte or word write mode or block write mode. A flash word (low and high bytes) must not be written more than twice between erasures. Otherwise, damage can occur. The BUSY bit is set while a write operation is active and cleared when the operation completes. If the write operation is initiated from RAM, the CPU must not access flash while BUSY = 1. Otherwise, an access violation occurs, ACCVIFG is set, and the flash write is unpredictable. 7.3.3.1 Byte or Word Write A byte or word write operation can be initiated from within flash memory or from RAM. When initiating from within flash memory, all timing is controlled by the flash controller, and the CPU is held while the write completes. After the write completes, the CPU resumes code execution with the instruction following the write. The byte or word write timing is shown in Figure 7-7. Generate Programming Voltage Programming Operation Active Remove Programming Voltage Programming Time, VCC Current Consumption is Increased BUSY tWord Write = 30/fFTG Figure 7-7. Byte or Word Write Timing When a byte or word write is executed from RAM, the CPU continues to execute code from RAM. The BUSY bit must be zero before the CPU accesses flash again, otherwise an access violation occurs, ACCVIFG is set, and the write result is unpredictable. In byte or word mode, the internally-generated programming voltage is applied to the complete 64-byte block, each time a byte or word is written, for 27 of the 30 fFTG cycles. With each byte or word write, the amount of time the block is subjected to the programming voltage accumulates. The cumulative programming time, tCPT, must not be exceeded for any block. If the cumulative programming time is met, the block must be erased before performing any further writes to any address within the block. See the device-specific data sheet for specifications. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Flash Memory Controller 315 Flash Memory Operation 7.3.3.2 Initiating a Byte or Word Write From Within Flash Memory The flow to initiate a byte or word write from flash is shown in Figure 7-8. Disable watchdog Setup flash controller and set WRT=1 Write byte or word Set WRT=0, LOCK=1, re-enable watchdog Figure 7-8. Initiating a Byte or Word Write From Flash ; Byte/word write from flash. 514 kHz < SMCLK < 952 kHz ; Assumes 0FF1Eh is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2 MOV #FWKEY,&FCTL3 ; Clear LOCK MOV #FWKEY+WRT,&FCTL1 ; Enable write MOV #0123h,&0FF1Eh ; 0123h -> 0FF1Eh MOV #FWKEY,&FCTL1 ; Done. Clear WRT MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT? www.ti.com 316 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.3.3.3 Initiating a Byte or Word Write From RAM The flow to initiate a byte or word write from RAM is shown in Figure 7-9. Disable watchdog Flash Memory Operation yes BUSY = 1 Setup flash controller and set WRT=1 Write byte or word yes BUSY = 1 Set WRT=0, LOCK = 1 re-enable watchdog Figure 7-9. Initiating a Byte or Word Write from RAM ; Byte/word write from RAM. 514 kHz < SMCLK < 952 kHz ; Assumes 0FF1Eh is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2 MOV #FWKEY,&FCTL3 ; Clear LOCK MOV #FWKEY+WRT,&FCTL1 ; Enable write MOV #0123h,&0FF1Eh ; 0123h -> 0FF1Eh L2 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L2 ; Loop while busy MOV #FWKEY,&FCTL1 ; Clear WRT MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT? SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Flash Memory Controller 317 Flash Memory Operation www.ti.com 7.3.3.4 Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 64-byte block. The cumulative programming time tCPT must not be exceeded for any block during a block write. A block write cannot be initiated from within flash memory. The block write must be initiated from RAM only. The BUSY bit remains set throughout the duration of the block write. The WAIT bit must be checked between writing each byte or word in the block. When WAIT is set the next byte or word of the block can be written. When writing successive blocks, the BLKWRT bit must be cleared after the current block is complete. BLKWRT can be set initiating the next block write after the required flash recovery time given by tend. BUSY is cleared following each block write completion indicating the next block can be written. Figure 7-10 shows the block write timing. BLKWRT bit Write to flash e.g., MOV#123h, &Flash Generate Programming Voltage Programming Operation Active Remove Programming Voltage BUSY Cumulative Programming Time tCPT ∼=< 4ms, VCC Current Consumption is Increased WAIT tBlock, 0 = 25/fFTG tBlock, 1-63 = 18/fFTG tBlock, 1-63 = 18/fFTG tend = 6/fFTG Figure 7-10. Block-Write Cycle Timing 318 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.3.3.5 Block Write Flow and Example A block write flow is shown in Figure 7-11 and the following example. Disable watchdog yes BUSY = 1 Setup flash controller Set BLKWRT=WRT=1 Write byte or word yes WAIT=0? no Block Border? Set BLKWRT=0 yes BUSY = 1 yes Another Block? Set WRT=0, LOCK=1 re-enable WDT Figure 7-11. Block Write Flow Flash Memory Operation SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Flash Memory Controller 319 Flash Memory Operation ; Write one block starting at 0F000h. ; Must be executed from RAM, Assumes Flash is already erased. ; 514 kHz < SMCLK < 952 kHz ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #32,R5 ; Use as write counter MOV #0F000h,R6 ; Write pointer MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2 MOV #FWKEY,&FCTL3 ; Clear LOCK MOV #FWKEY+BLKWRT+WRT,&FCTL1 ; Enable block write L2 MOV Write_Value,0(R6) ; Write location L3 BIT #WAIT,&FCTL3 ; Test WAIT JZ L3 ; Loop while WAIT = 0 INCD R6 ; Point to next word DEC R5 ; Decrement write counter JNZ L2 ; End of block? MOV #FWKEY,&FCTL1 ; Clear WRT,BLKWRT L4 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L4 ; Loop while busy MOV #FWKEY+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT if needed www.ti.com 7.3.4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY = 1, the CPU may not read or write to or from any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable. Also if a write to flash is attempted with WRT = 0, the ACCVIFG interrupt flag is set, and the flash memory is unaffected. When a byte or word write or any erase operation is initiated from within flash memory, the flash controller returns op-code 03FFFh to the CPU at the next instruction fetch. Op-code 03FFFh is the JMP PC instruction. This causes the CPU to loop until the flash operation is finished. When the operation is finished and BUSY = 0, the flash controller allows the CPU to fetch the proper op-code and program execution resumes. The flash access conditions while BUSY = 1 are listed in Table 7-3. Flash Operation Any erase, or byte or word write Block write Table 7-3. Flash Access While BUSY = 1 Flash Access Read Write Instruction fetch Any Read Write Instruction fetch WAIT 0 0 0 0 1 1 1 Result ACCVIFG = 0. 03FFFh is the value read. ACCVIFG = 1. Write is ignored. ACCVIFG = 0. CPU fetches 03FFFh. This is the JMP PC instruction. ACCVIFG = 1, LOCK = 1 ACCVIFG = 0. 03FFFh is the value read. ACCVIFG = 0. Write is written. ACCVIFG = 1, LOCK = 1 Interrupts are automatically disabled during any flash operation when EEI = 0 and EEIEX = 0 and on MSP430x20xx and MSP430G2xx devices where EEI and EEIEX are not present. After the flash operation has completed, interrupts are automatically re-enabled. Any interrupt that occurred during the operation has its associated flag set and generates an interrupt request when re-enabled. When EEIEX = 1 and GIE = 1, an interrupt immediately aborts any flash operation and the FAIL flag is set. When EEI = 1, GIE = 1, and EEIEX = 0, a segment erase is interrupted by a pending interrupt every 32 fFTG cycles. After servicing the interrupt, the segment erase is continued for at least 32 fFTG cycles or until it is complete. During the servicing of the interrupt, the BUSY bit remains set but the flash memory can be accessed by the CPU without causing an access violation occurs. Nested interrupts and using the RETI instruction inside interrupt service routines are not supported. 320 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Operation The watchdog timer (in watchdog mode) should be disabled before a flash erase cycle. A reset aborts the erase and the results are unpredictable. After the erase cycle has completed, the watchdog may be reenabled. 7.3.5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation immediately and stops the flash controller. All flash operations cease, the flash returns to read mode, and all bits in the FCTL1 register are reset. The result of the intended operation is unpredictable. 7.3.6 Marginal Read Mode The marginal read mode can be used to verify the integrity of the flash memory contents. This feature is implemented in selected 2xx devices; see the device-specific data sheet for availability. During marginal read mode marginally programmed flash memory bit locations can be detected. Events that could produce this situation include improper fFTG settings, or violation of minimum VCC during erase or program operations. One method for identifying such memory locations would be to periodically perform a checksum calculation over a section of flash memory (for example, a flash segment) and repeating this procedure with the marginal read mode enabled. If they do not match, it could indicate an insufficiently programmed flash memory location. It is possible to refresh the affected Flash memory segment by disabling marginal read mode, copying to RAM, erasing the flash segment, and writing back to it from RAM. The program checking the flash memory contents must be executed from RAM. Executing code from flash automatically disables the marginal read mode. The marginal read modes are controlled by the MRG0 and MRG1 register bits. Setting MRG1 is used to detect insufficiently programmed flash cells containing a 1 (erased bits). Setting MRG0 is used to detect insufficiently programmed flash cells containing a 0 (programmed bits). Only one of these bits should be set at a time. Therefore, a full marginal read check requires two passes of checking the flash memory content's integrity. During marginal read mode, the flash access speed (MCLK) must be limited to 1 MHz (see the device-specific data sheet). 7.3.7 Configuring and Accessing the Flash Memory Controller The FCTLx registers are 16-bit password-protected read/write registers. Any read or write access must use word instructions and write accesses must include the write password 0A5h in the upper byte. Any write to any FCTLx register with any value other than 0A5h in the upper byte is a security key violation, sets the KEYV flag and triggers a PUC system reset. Any read of any FCTLx registers reads 096h in the upper byte. Any write to FCTL1 during an erase or byte or word write operation is an access violation and sets ACCVIFG. Writing to FCTL1 is allowed in block write mode when WAIT = 1, but writing to FCTL1 in block write mode when WAIT = 0 is an access violation and sets ACCVIFG. Any write to FCTL2 when the BUSY = 1 is an access violation. Any FCTLx register may be read when BUSY = 1. A read does not cause an access violation. 7.3.8 Flash Memory Controller Interrupts The flash controller has two interrupt sources, KEYV, and ACCVIFG. ACCVIFG is set when an access violation occurs. When the ACCVIE bit is re-enabled after a flash write or erase, a set ACCVIFG flag generates an interrupt request. ACCVIFG sources the NMI interrupt vector, so it is not necessary for GIE to be set for ACCVIFG to request an interrupt. ACCVIFG may also be checked by software to determine if an access violation occurred. ACCVIFG must be reset by software. The key violation flag KEYV is set when any of the flash control registers are written with an incorrect password. When this occurs, a PUC is generated immediately resetting the device. 7.3.9 Programming Flash Memory Devices There are three options for programming an MSP430 flash device. All options support in-system programming: SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Flash Memory Controller 321 Flash Memory Operation • Program via JTAG • Program via the bootstrap loader • Program via a custom solution www.ti.com 7.3.9.1 Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port. The JTAG interface requires four signals (five signals on 20- and 28-pin devices), ground and, optionally, VCC and RST/NMI. The JTAG port is protected with a fuse. Blowing the fuse completely disables the JTAG port and is not reversible. Further access to the device via JTAG is not possible. For details, see the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320). 7.3.9.2 Programming Flash Memory via the Bootstrap Loader (BSL) Most MSP430 flash devices contain a bootstrap loader. See the device-specific data sheet for implementation details. The BSL enables users to read or program the flash memory or RAM using a UART serial interface. Access to the MSP430 flash memory via the BSL is protected by a 256-bit userdefined password. For more details see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319). 7.3.9.3 Programming Flash Memory via a Custom Solution The ability of the MSP430 CPU to write to its own flash memory allows for in-system and external custom programming solutions as shown in Figure 7-12. The user can choose to provide data to the MSP430 through any means available (UART, SPI, etc.). User-developed software can receive the data and program the flash memory. Since this type of solution is developed by the user, it can be completely customized to fit the application needs for programming, erasing, or updating the flash memory. Host MSP430 Commands, data, etc. Flash Memory UART, Px.x, SPI, etc. CPU executes user software Read/write flash memory Figure 7-12. User-Developed Programming Solution 322 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.4 Flash Memory Registers The flash memory registers are listed in Table 7-4. Table 7-4. Flash Memory Registers Register Short Form Flash memory control register 1 FCTL1 Flash memory control register 2 FCTL2 Flash memory control register 3 FCTL3 Flash memory control register 4(2) FCTL4 Interrupt Enable 1 IE1 Interrupt Flag 1 IFG1 (1) KEYV is reset with POR. (2) Not present in all devices. See device-specific data sheet. Register Type Read/write Read/write Read/write Read/write Read/write Read/write Flash Memory Registers Address 0x0128 0x012A 0x012C 0x01BE 0x0000 0x0002 Initial State 0x9600 with PUC 0x9642 with PUC 0x9658 with PUC(1) 0x0000 with PUC Reset with PUC SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Flash Memory Controller 323 Flash Memory Registers 7.4.1 FCTL1, Flash Memory Control Register www.ti.com 15 14 13 12 11 10 9 8 FRKEY, Read as 096h FWKEY, Must be written as 0A5h 7 BLKWRT rw-0 6 WRT rw-0 5 Reserved r0 4 EEIEX (1) rw-0 3 EEI (1) rw-0 2 MERAS rw-0 1 ERASE rw-0 0 Reserved r0 FRKEY FWKEY BLKWRT WRT Reserved EEIEX EEI MERAS ERASE MERAS 0 0 1 1 Reserved Bits 15-8 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC. Bit 7 Bit 6 Bit 5 Bit 4 Bits 3 Bit 2 Bit 1 ERASE 0 1 0 1 Bit 0 Block write mode. WRT must also be set for block write mode. BLKWRT is automatically reset when EMEX is set. 0 Block-write mode is off 1 Block-write mode is on Write. This bit is used to select any write mode. WRT is automatically reset when EMEX is set. 0 Write mode is off 1 Write mode is on Reserved. Always read as 0. Enable Emergency Interrupt Exit. Setting this bit enables an interrupt to cause an emergency exit from a flash operation when GIE = 1. EEIEX is automatically reset when EMEX is set. 0 Exit interrupt disabled. 1 Exit on interrupt enabled. Enable Erase Interrupts. Setting this bit allows a segment erase to be interrupted by an interrupt request. After the interrupt is serviced the erase cycle is resumed. 0 Interrupts during segment erase disabled. 1 Interrupts during segment erase enabled. Mass erase and erase. These bits are used together to select the erase mode. MERAS and ERASE are automatically reset when EMEX is set. Erase Cycle No erase Erase individual segment only Erase all main memory segments LOCKA = 0: Erase main and information flash memory. LOCKA = 1: Erase only main flash memory. Reserved. Always read as 0. (1) Not present on MSP430x20xx and MSP430G2xx devices. 7.4.2 FCTL2, Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 7 6 5 4 3 2 1 0 FSSELx FNx rw-0 rw-1 rw-0 rw-0 rw-0 rw-0 rw-1 rw-0 FWKEYx FSSELx FNx Bits 15-8 Bits 7-6 Bits 5-0 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC. Flash controller clock source select 00 ACLK 01 MCLK 10 SMCLK 11 SMCLK Flash controller clock divider. These six bits select the divider for the flash controller clock. The divisor value is FNx + 1. For example, when FNx = 00h, the divisor is 1. When FNx = 03Fh, the divisor is 64. 324 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.4.3 FCTL3, Flash Memory Control Register Flash Memory Registers 15 7 FAIL r(w)-0 FWKEYx FAIL LOCKA EMEX LOCK WAIT ACCVIFG KEYV BUSY 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 6 LOCKA r(w)-1 5 EMEX rw-0 4 LOCK rw-1 3 WAIT r-1 2 ACCVIFG rw-0 1 KEYV rw-(0) 0 BUSY r(w)-0 Bits 15-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC. Operation failure. This bit is set if the fFTG clock source fails, or a flash operation is aborted from an interrupt when EEIEX = 1. FAIL must be reset with software. 0 No failure 1 Failure SegmentA and Info lock. Write a 1 to this bit to change its state. Writing 0 has no effect. 0 Segment A unlocked and all information memory is erased during a mass erase. 1 Segment A locked and all information memory is protected from erasure during a mass erase. Emergency exit 0 No emergency exit 1 Emergency exit Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit can be set any time during a byte or word write or erase operation, and the operation completes normally. In the block write mode if the LOCK bit is set while BLKWRT = WAIT = 1, then BLKWRT and WAIT are reset and the mode ends normally. 0 Unlocked 1 Locked Wait. Indicates the flash memory is being written to. 0 The flash memory is not ready for the next byte/word write 1 The flash memory is ready for the next byte/word write Access violation interrupt flag 0 No interrupt pending 1 Interrupt pending Flash security key violation. This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set. KEYV must be reset with software. 0 FCTLx password was written correctly 1 FCTLx password was written incorrectly Busy. This bit indicates the status of the flash timing generator. 0 Not Busy 1 Busy SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Flash Memory Controller 325 Flash Memory Registers 7.4.4 FCTL4, Flash Memory Control Register This register is not available in all devices. See the device-specific data sheet for details. www.ti.com 15 7 r-0 FWKEYx Reserved MRG1 MRG0 Reserved 14 13 12 11 10 9 8 FWKEYx, Read as 096h Must be written as 0A5h 6 r-0 Bits 15-8 Bits 7-6 Bit 5 Bit 4 Bits 3-0 5 4 3 2 1 0 MRG1 MRG0 rw-0 rw-0 r-0 r-0 r-0 r-0 FCTLx password. Always reads as 096h. Must be written as 0A5h. Writing any other value generates a PUC. Reserved. Always read as 0. Marginal read 1 mode. This bit enables the marginal 1 read mode. The marginal read 1 bit is cleared if the CPU starts execution from the flash memory. If both MRG1 and MRG0 are set MRG1 is active and MRG0 is ignored. 0 Marginal 1 read mode is disabled. 1 Marginal 1 read mode is enabled. Marginal read 0 mode. This bit enables the marginal 0 read mode. The marginal mode 0 is cleared if the CPU starts execution from the flash memory. If both MRG1 and MRG0 are set MRG1 is active and MRG0 is ignored. 0 Marginal 0 read mode is disabled. 1 Marginal 0 read mode is enabled. Reserved. Always read as 0. 7.4.5 IE1, Interrupt Enable Register 1 7 ACCVIE 6 Bits 7-6 Bit 5 Bits 4-0 5 4 3 2 1 0 ACCVIE rw-0 These bits may be used by other modules. See the device-specific data sheet. Flash memory access violation interrupt enable. This bit enables the ACCVIFG interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See the device-specific data sheet. 326 Flash Memory Controller SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 8 SLAU144J – December 2004 – Revised July 2013 Digital I/O This chapter describes the operation of the digital I/O ports. Topic ........................................................................................................................... Page 8.1 Digital I/O Introduction ..................................................................................... 328 8.2 Digital I/O Operation ......................................................................................... 328 8.3 Digital I/O Registers ......................................................................................... 333 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Digital I/O 327 Digital I/O Introduction www.ti.com 8.1 Digital I/O Introduction MSP430 devices have up to eight digital I/O ports implemented, P1 to P8. Each port has up to eight I/O pins. Every I/O pin is individually configurable for input or output direction, and each I/O line can be individually read or written to. Ports P1 and P2 have interrupt capability. Each interrupt for the P1 and P2 I/O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal. All P1 I/O lines source a single interrupt vector, and all P2 I/O lines source a different, single interrupt vector. The digital I/O features include: • Independently programmable individual I/Os • Any combination of input or output • Individually configurable P1 and P2 interrupts • Independent input and output data registers • Individually configurable pullup or pulldown resistors • Individually configurable pin-oscillator function (some MSP430 devices) NOTE: MSP430G22x0 : These devices feature digital I/O pins P1.2, P1.5, P1.6 and P1.7. The GPIOs P1.0, P1.1, P1.3, P1.4, P2.6, and P2.7 are implemented on this device but not available on the device pin-out. To avoid floating inputs, these GPIOs, these digital I/Os should be properly initialized by running a start-up code. See initialization code below: mov.b #0x1B, P1REN; ; Terminate unavailable Port1 pins properly ; Config as Input with pulldown enabled xor.b #0x20, BCSCTL3; ; Select VLO as low freq clock The initialization code configures GPIOs P1.0, P1.1, P1.3, and P1.4 as inputs with pull-down resistor enabled (that is, P1REN.x = 1) and GPIOs P2.6 and P2.7 are terminated by selecting VLOCLK as ACLK – see the Basic Clock System chapter for details. The register bits of P1.0, P1.1, P1.3, and P1.4 in registers P1OUT, P1DIR, P1IFG, P1IE, P1IES, P1SEL and P1REN should not be altered after the initialization code is executed. Also, all Port2 registers are should not be altered. 8.2 Digital I/O Operation The digital I/O is configured with user software. The setup and operation of the digital I/O is discussed in the following sections. 8.2.1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at the corresponding I/O pin when the pin is configured as I/O function. Bit = 0: The input is low Bit = 1: The input is high NOTE: Writing to Read-Only Registers PxIN Writing to these read-only registers results in increased current consumption while the write attempt is active. 8.2.2 Output Registers PxOUT Each bit in each PxOUT register is the value to be output on the corresponding I/O pin when the pin is configured as I/O function, output direction, and the pullup/down resistor is disabled. Bit = 0: The output is low Bit = 1: The output is high 328 Digital I/O SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Digital I/O Operation If the pin's pullup/pulldown resistor is enabled, the corresponding bit in the PxOUT register selects pullup or pulldown. Bit = 0: The pin is pulled down Bit = 1: The pin is pulled up 8.2.3 Direction Registers PxDIR Each bit in each PxDIR register selects the direction of the corresponding I/O pin, regardless of the selected function for the pin. PxDIR bits for I/O pins that are selected for other functions must be set as required by the other function. Bit = 0: The port pin is switched to input direction Bit = 1: The port pin is switched to output direction 8.2.4 Pullup/Pulldown Resistor Enable Registers PxREN Each bit in each PxREN register enables or disables the pullup/pulldown resistor of the corresponding I/O pin. The corresponding bit in the PxOUT register selects if the pin is pulled up or pulled down. Bit = 0: Pullup/pulldown resistor disabled Bit = 1: Pullup/pulldown resistor enabled 8.2.5 Function Select Registers PxSEL and PxSEL2 Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet to determine pin functions. Each PxSEL and PxSEL2 bit is used to select the pin function - I/O port or peripheral module function. Table 8-1. PxSEL and PxSEL2 PxSEL2 0 0 1 1 PxSEL 0 1 0 1 Pin Function I/O function is selected. Primary peripheral module function is selected. Reserved. See device-specific data sheet. Secondary peripheral module function is selected. Setting PxSELx = 1 does not automatically set the pin direction. Other peripheral module functions may require the PxDIRx bits to be configured according to the direction needed for the module function. See the pin schematics in the device-specific data sheet. NOTE: Setting PxREN = 1 When PxSEL = 1 On some I/O ports on the MSP430F261x and MSP430F2416/7/8/9, enabling the pullup/pulldown resistor (PxREN = 1) while the module function is selected (PxSEL = 1) does not disable the logic output driver. This combination is not recommended and may result in unwanted current flow through the internal resistor. See the device-specific data sheet pin schematics for more information. ;Output ACLK on P2.0 on MSP430F21x1 BIS.B #01h,&P2SEL ; Select ACLK function for pin BIS.B #01h,&P2DIR ; Set direction to output *Required* NOTE: P1 and P2 Interrupts Are Disabled When PxSEL = 1 When any P1SELx or P2SELx bit is set, the corresponding pin's interrupt function is disabled. Therefore, signals on these pins will not generate P1 or P2 interrupts, regardless of the state of the corresponding P1IE or P2IE bit. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Digital I/O 329 Digital I/O Operation www.ti.com When a port pin is selected as an input to a peripheral, the input signal to the peripheral is a latched representation of the signal at the device pin. While PxSELx = 1, the internal input signal follows the signal at the pin. However, if the PxSELx = 0, the input to the peripheral maintains the value of the input signal at the device pin before the PxSELx bit was reset. 8.2.6 Pin Oscillator Some MSP430 devices have a pin oscillator function built-in to some pins. The pin oscillator function may be used in capacitive touch sensing applications to eliminate external passive components. Additionally, the pin oscillator may be used in sensor applications. No external components to create the oscillation Capacitive sensors can be connected directly to MSP430 pin Robust, typical built-in hysteresis of ~0.7 V When the pin oscillator function is enabled, other pin configurations are overwritten. The output driver is turned off while the weak pullup/pulldown is enabled and controlled by the voltage level on the pin itself. The voltage on the I/O is fed into the Schmitt trigger of the pin and then routed to a timer. The connection to the timer is device specific and, thus, defined in the device-specific data sheet. The Schmitt-trigger output is inverted and then decides if the pullup or the pulldown is enabled. Due to the inversion, the pin starts to oscillate as soon as the pin oscillator pin configuration is selected. Some of the pin-oscillator outputs are combined by a logical OR before routing to a timer clock input or timer capture channel. Therefore, only one pin oscillator should be enabled at a time. The oscillation frequency of each pin is defined by the load on the pin and by the I/O type. I/Os with analog functions typically show a lower oscillation frequency than pure digital I/Os. See the device-specific data sheet for details. Pins without external load show typical oscillation frequencies of 1 MHz to 3 MHz. Pin oscillator in a cap touch application A typical touch pad application using the pin oscilator is shown in Figure 8-1. Part of Digital I/OPx.y DVSS 0 DVCC 1 PAD TAxCLK 1 TASSELx 0 1 2 3 ID.x Divider 1/2/4/8 Part of Timer_A 16-bit Timer TAR Capture Register CCRx Figure 8-1. Example Circuitry and Configuration using the Pin Oscillator A change of the capacitance of the touch pad (external capacitive load) has an effect on the pin oscillator frequency. An approaching finger tip increases the capacitance of the touch pad thus leads to a lower selfoscillation frequency due to the longer charging time. The oscillation frequency can directly be captured in a built-in Timer channel. The typical sensitivity of a pin is shown in Figure 8-2. 330 Digital I/O SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Fosc − Typical Oscillation Frequency − MHz 1.50 1.35 VCC = 3.0 V 1.20 1.05 0.90 0.75 0.60 0.45 0.30 0.15 0.00 10 50 100 CLOAD − External Capacitance − pF Figure 8-2. Typical Pin-Oscillation Frequency Digital I/O Operation 8.2.7 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector, and all P2 pins source a different single interrupt vector. The PxIFG register can be tested to determine the source of a P1 or P2 interrupt. 8.2.7.1 Interrupt Flag Registers P1IFG, P2IFG Each PxIFGx bit is the interrupt flag for its corresponding I/O pin and is set when the selected input signal edge occurs at the pin. All PxIFGx interrupt flags request an interrupt when their corresponding PxIE bit and the GIE bit are set. Each PxIFG flag must be reset with software. Software can also set each PxIFG flag, providing a way to generate a software initiated interrupt. Bit = 0: No interrupt is pending Bit = 1: An interrupt is pending Only transitions, not static levels, cause interrupts. If any PxIFGx flag becomes set during a Px interrupt service routine, or is set after the RETI instruction of a Px interrupt service routine is executed, the set PxIFGx flag generates another interrupt. This ensures that each transition is acknowledged. NOTE: PxIFG Flags When Changing PxOUT or PxDIR Writing to P1OUT, P1DIR, P2OUT, or P2DIR can result in setting the corresponding P1IFG or P2IFG flags. 8.2.7.2 Interrupt Edge Select Registers P1IES, P2IES Each PxIES bit selects the interrupt edge for the corresponding I/O pin. Bit = 0: The PxIFGx flag is set with a low-to-high transition Bit = 1: The PxIFGx flag is set with a high-to-low transition SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Digital I/O 331 Digital I/O Operation NOTE: Writing to PxIESx Writing to P1IES, or P2IES can result in setting the corresponding interrupt flags. PxIESx 0→1 0→1 1→0 1→0 PxINx 0 1 0 1 PxIFGx May be set Unchanged Unchanged May be set www.ti.com 8.2.7.3 Interrupt Enable P1IE, P2IE Each PxIE bit enables the associated PxIFG interrupt flag. Bit = 0: The interrupt is disabled. Bit = 1: The interrupt is enabled. 8.2.8 Configuring Unused Port Pins Unused I/O pins should be configured as I/O function, output direction, and left unconnected on the PC board, to prevent a floating input and reduce power consumption. The value of the PxOUT bit is irrelevant, since the pin is unconnected. Alternatively, the integrated pullup/pulldown resistor can be enabled by setting the PxREN bit of the unused pin to prevent the floating input. See the System Resets, Interrupts, and Operating Modes chapter for termination of unused pins. 332 Digital I/O SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 8.3 Digital I/O Registers The digital I/O registers are listed in Table 8-2. Port P1 P2 P3 P4 P5 P6 Register Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Port Select 2 Resistor Enable Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Table 8-2. Digital I/O Registers Short Form P1IN P1OUT P1DIR P1IFG P1IES P1IE P1SEL P1SEL2 P1REN P2IN P2OUT P2DIR P2IFG P2IES P2IE P2SEL P2SEL2 P2REN P3IN P3OUT P3DIR P3SEL P3SEL2 P3REN P4IN P4OUT P4DIR P4SEL P4SEL2 P4REN P5IN P5OUT P5DIR P5SEL P5SEL2 P5REN P6IN P6OUT P6DIR P6SEL P6SEL2 P6REN Address 020h 021h 022h 023h 024h 025h 026h 041h 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 042h 02Fh 018h 019h 01Ah 01Bh 043h 010h 01Ch 01Dh 01Eh 01Fh 044h 011h 030h 031h 032h 033h 045h 012h 034h 035h 036h 037h 046h 013h Register Type Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write Digital I/O Registers Initial State - Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC 0C0h with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Digital I/O 333 Digital I/O Registers Table 8-2. Digital I/O Registers (continued) Port P7 P8 Register Input Output Direction Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Short Form P7IN P7OUT P7DIR P7SEL P7SEL2 P7REN P8IN P8OUT P8DIR P8SEL P8SEL2 P8REN Address 038h 03Ah 03Ch 03Eh 047h 014h 039h 03Bh 03Dh 03Fh 048h 015h Register Type Read only Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write www.ti.com Initial State - Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC 334 Digital I/O SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 9 SLAU144J – December 2004 – Revised July 2013 Supply Voltage Supervisor (SVS) This chapter describes the operation of the SVS. The SVS is implemented in selected MSP430x2xx devices. Topic ........................................................................................................................... Page 9.1 Supply Voltage Supervisor (SVS) Introduction .................................................... 336 9.2 SVS Operation ................................................................................................. 337 9.3 SVS Registers ................................................................................................. 339 SLAU144J – December 2004 – Revised July 2013 Supply Voltage Supervisor (SVS) 335 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Supply Voltage Supervisor (SVS) Introduction www.ti.com 9.1 Supply Voltage Supervisor (SVS) Introduction The SVS is used to monitor the AVCC supply voltage or an external voltage. The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a userselected threshold. The SVS features include: • AVCC monitoring • Selectable generation of POR • Output of SVS comparator accessible by software • Low-voltage condition latched and accessible by software • 14 selectable threshold levels • External channel to monitor external voltage The SVS block diagram is shown in Figure 9-1. AVCC VCC AVCC D GS Brownout Reset SVSIN 1111 0001 0010 1011 1100 1101 ~ 50us − + 1.2V D GS SVS_POR tReset ~ 50us SVSOUT Set SVSFG Reset VLD PORON SVSON SVSOP SVSFG SVSCTL Bits Figure 9-1. SVS Block Diagram 336 Supply Voltage Supervisor (SVS) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com SVS Operation 9.2 SVS Operation The SVS detects if the AVCC voltage drops below a selectable level. It can be configured to provide a POR or set a flag, when a low-voltage condition occurs. The SVS is disabled after a brownout reset to conserve current consumption. 9.2.1 Configuring the SVS The VLDx bits are used to enable/disable the SVS and select one of 14 threshold levels (V(SVS_IT-)) for comparison with AVCC. The SVS is off when VLDx = 0 and on when VLDx > 0. The SVSON bit does not turn on the SVS. Instead, it reflects the on/off state of the SVS and can be used to determine when the SVS is on. When VLDx = 1111, the external SVSIN channel is selected. The voltage on SVSIN is compared to an internal level of approximately 1.25 V. 9.2.2 SVS Comparator Operation A low-voltage condition exists when AVCC drops below the selected threshold or when the external voltage drops below its 1.25-V threshold. Any low-voltage condition sets the SVSFG bit. The PORON bit enables or disables the device-reset function of the SVS. If PORON = 1, a POR is generated when SVSFG is set. If PORON = 0, a low-voltage condition sets SVSFG, but does not generate a POR. The SVSFG bit is latched. This allows user software to determine if a low-voltage condition occurred previously. The SVSFG bit must be reset by user software. If the low-voltage condition is still present when SVSFG is reset, it will be immediately set again by the SVS. 9.2.3 Changing the VLDx Bits When the VLDx bits are changed from zero to any non-zero value there is a automatic settling delay td(SVSon) implemented that allows the SVS circuitry to settle. The td(SVSon) delay is approximately 50 µs. During this delay, the SVS will not flag a low-voltage condition or reset the device, and the SVSON bit is cleared. Software can test the SVSON bit to determine when the delay has elapsed and the SVS is monitoring the voltage properly. Writing to SVSCTL while SVSON = 0 will abort the SVS automatic settling delay, td(SVSon), and switch the SVS to active mode immediately. In doing so, the SVS circuitry might not be settled, resulting in unpredictable behavior. When the VLDx bits are changed from any non-zero value to any other non-zero value the circuitry requires the time tsettle to settle. The settling time tsettle is a maximum of ~12 µs. See the device-specific data sheet. There is no automatic delay implemented that prevents SVSFG to be set or to prevent a reset of the device. The recommended flow to switch between levels is shown in the following code. ; Enable SVS for the first time: MOV.B #080h,&SVSCTL ; Level 2.8V, do not cause POR ; ... ; Change SVS level MOV.B #000h,&SVSCTL ; Temporarily disable SVS MOV.B #018h,&SVSCTL ; Level 1.9V, cause POR ; ... SLAU144J – December 2004 – Revised July 2013 Supply Voltage Supervisor (SVS) 337 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated SVS Operation www.ti.com 9.2.4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AVCC is close to the threshold. The SVS operation and SVS/Brownout interoperation are shown in Figure 9-2. AV CC V(SVS_IT−) V(SVSstart) V(B_IT−) VCC(start) Brownout 1 Vhys(SVS_IT−) Vhys(B_IT−) Brownout Region Software Sets VLD>0 BrownOut Region 0 SVSOUT 1 t d(BOR) SVS Circuit Active t d(BOR) 0 Set SVS_POR 1 td(SVSon) td(SVSR) 0 undefined Figure 9-2. Operating Levels for SVS and Brownout/Reset Circuit 338 Supply Voltage Supervisor (SVS) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 9.3 SVS Registers The SVS registers are listed in Table 9-1. Register SVS Control Register Table 9-1. SVS Registers Short Form SVSCTL Register Type Read/write SVS Registers Address 055h Initial State Reset with BOR SLAU144J – December 2004 – Revised July 2013 Supply Voltage Supervisor (SVS) 339 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated SVS Registers 9.3.1 SVSCTL, SVS Control Register www.ti.com 7 rw-0 (1) 6 rw-0 (1) VLDx 5 rw-0 (1) 4 rw-0 (1) 3 PORON rw-0 (1) 2 SVSON r (1) 1 SVSOP r (1) 0 SVSFG rw-0 (1) VLDx PORON SVSON SVSOP SVSFG Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Voltage level detect. These bits turn on the SVS and select the nominal SVS threshold voltage level. See the device-specific data sheet for parameters. 0000 SVS is off 0001 1.9 V 0010 2.1 V 0011 2.2 V 0100 2.3 V 0101 2.4 V 0110 2.5 V 0111 2.65 V 1000 2.8 V 1001 2.9 V 1010 3.05 V 1011 3.2 V 1100 3.35 V 1101 3.5 V 1110 3.7 V 1111 Compares external input voltage SVSIN to 1.25 V. POR on. This bit enables the SVSFG flag to cause a POR device reset. 0 SVSFG does not cause a POR 1 SVSFG causes a POR SVS on. This bit reflects the status of SVS operation. This bit DOES NOT turn on the SVS. The SVS is turned on by setting VLDx > 0. 0 SVS is Off 1 SVS is On SVS output. This bit reflects the output value of the SVS comparator. 0 SVS comparator output is low 1 SVS comparator output is high SVS flag. This bit indicates a low voltage condition. SVSFG remains set after a low voltage condition until reset by software. 0 No low voltage condition occurred 1 A low condition is present or has occurred (1) Reset by a brownout reset only, not by a POR or PUC. 340 Supply Voltage Supervisor (SVS) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 10 SLAU144J – December 2004 – Revised July 2013 Watchdog Timer+ (WDT+) The watchdog timer+ (WDT+) is a 16-bit timer that can be used as a watchdog or as an interval timer. This chapter describes the WDT+ The WDT+ is implemented in all MSP430x2xx devices. Topic ........................................................................................................................... Page 10.1 Watchdog Timer+ (WDT+) Introduction ............................................................... 342 10.2 Watchdog Timer+ Operation ............................................................................. 344 10.3 Watchdog Timer+ Registers .............................................................................. 346 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Watchdog Timer+ (WDT+) 341 Watchdog Timer+ (WDT+) Introduction www.ti.com 10.1 Watchdog Timer+ (WDT+) Introduction The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. Features of the watchdog timer+ module include: • Four software-selectable time intervals • Watchdog mode • Interval mode • Access to WDT+ control register is password protected • Control of RST/NMI pin function • Selectable clock source • Can be stopped to conserve power • Clock fail-safe feature The WDT+ block diagram is shown in Figure 10-1. NOTE: Watchdog Timer+ Powers Up Active After a PUC, the WDT+ module is automatically configured in the watchdog mode with an initial 32768 clock cycle reset interval using the DCOCLK. The user must setup or halt the WDT+ prior to the expiration of the initial reset interval. 342 Watchdog Timer+ (WDT+) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Int. Flag WDTQn Y Pulse Generator A B PUC MCLK Q6 3 0 Q9 2 1 Q13 1 0 Q15 0 16−bit 1 Counter 1 0 Clear 1 (Asyn) CLK 0 Fail-Safe Logic EQU Watchdog Timer+ (WDT+) Introduction WDTCTL MSB MDB Password Compare 16−bit EQU Write Enable Low Byte R/W SMCLK ACLK 1 1 A EN WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTIS1 WDTIS0 LSB Clock Request Logic Figure 10-1. Watchdog Timer+ Block Diagram MCLK Active SMCLK Active ACLK Active SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Watchdog Timer+ (WDT+) 343 Watchdog Timer+ Operation www.ti.com 10.2 Watchdog Timer+ Operation The WDT+ module can be configured as either a watchdog or interval timer with the WDTCTL register. The WDTCTL register also contains control bits to configure the RST/NMI pin. WDTCTL is a 16-bit, password-protected, read/write register. Any read or write access must use word instructions and write accesses must include the write password 05Ah in the upper byte. Any write to WDTCTL with any value other than 05Ah in the upper byte is a security key violation and triggers a PUC system reset regardless of timer mode. Any read of WDTCTL reads 069h in the upper byte. The WDT+ counter clock should be slower or equal than the system (MCLK) frequency. 10.2.1 Watchdog Timer+ Counter The watchdog timer+ counter (WDTCNT) is a 16-bit up-counter that is not directly accessible by software. The WDTCNT is controlled and time intervals selected through the watchdog timer+ control register WDTCTL. The WDTCNT can be sourced from ACLK or SMCLK. The clock source is selected with the WDTSSEL bit. 10.2.2 Watchdog Mode After a PUC condition, the WDT+ module is configured in the watchdog mode with an initial 32768 cycle reset interval using the DCOCLK. The user must setup, halt, or clear the WDT+ prior to the expiration of the initial reset interval or another PUC will be generated. When the WDT+ is configured to operate in watchdog mode, either writing to WDTCTL with an incorrect password, or expiration of the selected time interval triggers a PUC. A PUC resets the WDT+ to its default condition and configures the RST/NMI pin to reset mode. 10.2.3 Interval Timer Mode Setting the WDTTMSEL bit to 1 selects the interval timer mode. This mode can be used to provide periodic interrupts. In interval timer mode, the WDTIFG flag is set at the expiration of the selected time interval. A PUC is not generated in interval timer mode at expiration of the selected timer interval and the WDTIFG enable bit WDTIE remains unchanged. When the WDTIE bit and the GIE bit are set, the WDTIFG flag requests an interrupt. The WDTIFG interrupt flag is automatically reset when its interrupt request is serviced, or may be reset by software. The interrupt vector address in interval timer mode is different from that in watchdog mode. NOTE: Modifying the Watchdog Timer+ The WDT+ interval should be changed together with WDTCNTCL = 1 in a single instruction to avoid an unexpected immediate PUC or interrupt. The WDT+ should be halted before changing the clock source to avoid a possible incorrect interval. 10.2.4 Watchdog Timer+ Interrupts The WDT+ uses two bits in the SFRs for interrupt control. • The WDT+ interrupt flag, WDTIFG, located in IFG1.0 • The WDT+ interrupt enable, WDTIE, located in IE1.0 When using the WDT+ in the watchdog mode, the WDTIFG flag sources a reset vector interrupt. The WDTIFG can be used by the reset interrupt service routine to determine if the watchdog caused the device to reset. If the flag is set, then the watchdog timer+ initiated the reset condition either by timing out or by a security key violation. If WDTIFG is cleared, the reset was caused by a different source. When using the WDT+ in interval timer mode, the WDTIFG flag is set after the selected time interval and requests a WDT+ interval timer interrupt if the WDTIE and the GIE bits are set. The interval timer interrupt vector is different from the reset vector used in watchdog mode. In interval timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced, or can be reset with software. 344 Watchdog Timer+ (WDT+) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Watchdog Timer+ Operation 10.2.5 Watchdog Timer+ Clock Fail-Safe Operation The WDT+ module provides a fail-safe clocking feature assuring the clock to the WDT+ cannot be disabled while in watchdog mode. This means the low-power modes may be affected by the choice for the WDT+ clock. For example, if ACLK is the WDT+ clock source, LPM4 will not be available, because the WDT+ will prevent ACLK from being disabled. Also, if ACLK or SMCLK fail while sourcing the WDT+, the WDT+ clock source is automatically switched to MCLK. In this case, if MCLK is sourced from a crystal, and the crystal has failed, the fail-safe feature will activate the DCO and use it as the source for MCLK. When the WDT+ module is used in interval timer mode, there is no fail-safe feature for the clock source. 10.2.6 Operation in Low-Power Modes The MSP430 devices have several low-power modes. Different clock signals are available in different lowpower modes. The requirements of the user’s application and the type of clocking used determine how the WDT+ should be configured. For example, the WDT+ should not be configured in watchdog mode with SMCLK as its clock source if the user wants to use low-power mode 3 because the WDT+ will keep SMCLK enabled for its clock source, increasing the current consumption of LPM3. When the watchdog timer+ is not required, the WDTHOLD bit can be used to hold the WDTCNT, reducing power consumption. 10.2.7 Software Examples Any write operation to WDTCTL must be a word operation with 05Ah (WDTPW) in the upper byte: ; Periodically clear an active watchdog MOV #WDTPW+WDTCNTCL,&WDTCTL ; ; Change watchdog timer+ interval MOV #WDTPW+WDTCNTL+WDTSSEL,&WDTCTL ; ; Stop the watchdog MOV #WDTPW+WDTHOLD,&WDTCTL ; ; Change WDT+ to interval timer mode, clock/8192 interval MOV #WDTPW+WDTCNTCL+WDTTMSEL+WDTIS0,&WDTCTL SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Watchdog Timer+ (WDT+) 345 Watchdog Timer+ Registers 10.3 Watchdog Timer+ Registers The WDT+ registers are listed in Table 10-1. Register Watchdog timer+ control register SFR interrupt enable register 1 SFR interrupt flag register 1 (1) WDTIFG is reset with POR. Table 10-1. Watchdog Timer+ Registers Short Form WDTCTL IE1 IFG1 Register Type Read/write Read/write Read/write Address 0120h 0000h 0002h www.ti.com Initial State 06900h with PUC Reset with PUC Reset with PUC (1) 346 Watchdog Timer+ (WDT+) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 10.3.1 WDTCTL, Watchdog Timer+ Register Watchdog Timer+ Registers 15 7 WDTHOLD rw-0 WDTPW WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx 14 13 12 11 10 9 8 WDTPW, Read as 069h Must be written as 05Ah 6 WDTNMIES rw-0 5 WDTNMI rw-0 4 WDTTMSEL rw-0 3 WDTCNTCL r0(w) 2 WDTSSEL rw-0 1 0 WDTISx rw-0 rw-0 Bits 15-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bits 1-0 Watchdog timer+ password. Always read as 069h. Must be written as 05Ah, or a PUC is generated. Watchdog timer+ hold. This bit stops the watchdog timer+. Setting WDTHOLD = 1 when the WDT+ is not in use conserves power. 0 Watchdog timer+ is not stopped 1 Watchdog timer+ is stopped Watchdog timer+ NMI edge select. This bit selects the interrupt edge for the NMI interrupt when WDTNMI = 1. Modifying this bit can trigger an NMI. Modify this bit when WDTIE = 0 to avoid triggering an accidental NMI. 0 NMI on rising edge 1 NMI on falling edge Watchdog timer+ NMI select. This bit selects the function for the RST/NMI pin. 0 Reset function 1 NMI function Watchdog timer+ mode select 0 Watchdog mode 1 Interval timer mode Watchdog timer+ counter clear. Setting WDTCNTCL = 1 clears the count value to 0000h. WDTCNTCL is automatically reset. 0 No action 1 WDTCNT = 0000h Watchdog timer+ clock source select 0 SMCLK 1 ACLK Watchdog timer+ interval select. These bits select the watchdog timer+ interval to set the WDTIFG flag and/or generate a PUC. 00 Watchdog clock source /32768 01 Watchdog clock source /8192 10 Watchdog clock source /512 11 Watchdog clock source /64 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Watchdog Timer+ (WDT+) 347 Watchdog Timer+ Registers 10.3.2 IE1, Interrupt Enable Register 1 www.ti.com 7 NMIIE WDTIE 6 Bits 7-5 Bit 4 Bits 3-1 Bit 0 5 4 3 2 1 0 NMIIE WDTIE rw-0 These bits may be used by other modules. See device-specific data sheet. NMI interrupt enable. This bit enables the NMI interrupt. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. Watchdog timer+ interrupt enable. This bit enables the WDTIFG interrupt for interval timer mode. It is not necessary to set this bit for watchdog mode. Because other bits in IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 Interrupt not enabled 1 Interrupt enabled 10.3.3 IFG1, Interrupt Flag Register 1 7 NMIIFG WDTIFG 6 Bits 7-5 Bit 4 Bits 3-1 Bit 0 5 4 3 2 1 0 NMIIFG WDTIFG rw-0 rw-(0) These bits may be used by other modules. See device-specific data sheet. NMI interrupt flag. NMIIFG must be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear NMIIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. Watchdog timer+ interrupt flag. In watchdog mode, WDTIFG remains set until reset by software. In interval mode, WDTIFG is reset automatically by servicing the interrupt, or can be reset by software. Because other bits in IFG1 may be used for other modules, it is recommended to clear WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0 No interrupt pending 1 Interrupt pending 348 Watchdog Timer+ (WDT+) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 11 SLAU144J – December 2004 – Revised July 2013 Hardware Multiplier This chapter describes the hardware multiplier. The hardware multiplier is implemented in some MSP430x2xx devices. Topic ........................................................................................................................... Page 11.1 Hardware Multiplier Introduction ....................................................................... 350 11.2 Hardware Multiplier Operation ........................................................................... 350 11.3 Hardware Multiplier Registers ........................................................................... 354 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Hardware Multiplier 349 Hardware Multiplier Introduction www.ti.com 11.1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU. This means, its activities do not interfere with the CPU activities. The multiplier registers are peripheral registers that are loaded and read with CPU instructions. The hardware multiplier supports: • Unsigned multiply • Signed multiply • Unsigned multiply accumulate • Signed multiply accumulate • 16x16 bits, 16x8 bits, 8x16 bits, 8x8 bits The hardware multiplier block diagram is shown in Figure 11-1. 15 rw 0 MPY 130h MPYS 132h MAC 134h OP1 15 rw 0 OP2 138h MACS 136h 16 x 16 Multipiler Accessible Register MPY = 0000 MACS MPYS MAC Multiplexer 32−bit Adder MPY, MPYS 32−bit Multiplexer MAC, MACS SUMEXT 13Eh 15 r C 0 S RESHI 13Ch 31 rw RESLO 13Ah rw 0 Figure 11-1. Hardware Multiplier Block Diagram 11.2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and signed multiply accumulate operations. The type of operation is selected by the address the first operand is written to. The hardware multiplier has two 16-bit operand registers, OP1 and OP2, and three result registers, RESLO, RESHI, and SUMEXT. RESLO stores the low word of the result, RESHI stores the high word of the result, and SUMEXT stores information about the result. The result is ready in three MCLK cycles and can be read with the next instruction after writing to OP2, except when using an indirect addressing mode to access the result. When using indirect addressing for the result, a NOP is required before the result is ready. 350 Hardware Multiplier SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Hardware Multiplier Operation 11.2.1 Operand Registers The operand one register OP1 has four addresses, shown in Table 11-1, used to select the multiply mode. Writing the first operand to the desired address selects the type of multiply operation but does not start any operation. Writing the second operand to the operand two register OP2 initiates the multiply operation. Writing OP2 starts the selected operation with the values stored in OP1 and OP2. The result is written into the three result registers RESLO, RESHI, and SUMEXT. Repeated multiply operations may be performed without reloading OP1 if the OP1 value is used for successive operations. It is not necessary to re-write the OP1 value to perform the operations. OP1 Address 0130h 0132h 0134h 0136h Table 11-1. OP1 Addresses Register Name MPY MPYS MAC MACS Operation Unsigned multiply Signed multiply Unsigned multiply accumulate Signed multiply accumulate 11.2.2 Result Registers The result low register RESLO holds the lower 16-bits of the calculation result. The result high register RESHI contents depend on the multiply operation and are listed in Table 11-2. Mode MPY MPYS MAC MACS Table 11-2. RESHI Contents RESHI Contents Upper 16-bits of the result The MSB is the sign of the result. The remaining bits are the upper 15-bits of the result. Two's complement notation is used for the result. Upper 16-bits of the result Upper 16-bits of the result. Two's complement notation is used for the result. The sum extension registers SUMEXT contents depend on the multiply operation and are listed in Table 11-3. Mode MPY MPYS MAC MACS Table 11-3. SUMEXT Contents SUMEXT SUMEXT is always 0000h SUMEXT contains the extended sign of the result 00000h = Result was positive or zero 0FFFFh = Result was negative SUMEXT contains the carry of the result 0000h = No carry for result 0001h = Result has a carry SUMEXT contains the extended sign of the result 00000h = Result was positive or zero 0FFFFh = Result was negative SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Hardware Multiplier 351 Hardware Multiplier Operation www.ti.com 11.2.2.1 MACS Underflow and Overflow The multiplier does not automatically detect underflow or overflow in the MACS mode. The accumulator range for positive numbers is 0 to 7FFF FFFFh and for negative numbers is 0FFFF FFFFh to 8000 0000h. An underflow occurs when the sum of two negative numbers yields a result that is in the range for a positive number. An overflow occurs when the sum of two positive numbers yields a result that is in the range for a negative number. In both of these cases, the SUMEXT register contains the sign of the result, 0FFFFh for overflow and 0000h for underflow. User software must detect and handle these conditions appropriately. 11.2.3 Software Examples Examples for all multiplier modes follow. All 8x8 modes use the absolute address for the registers because the assembler will not allow .B access to word registers when using the labels from the standard definitions file. There is no sign extension necessary in software. Accessing the multiplier with a byte instruction during a signed operation will automatically cause a sign extension of the byte within the multiplier module. ; 16x16 Unsigned Multiply MOV #01234h,&MPY ; Load first operand MOV #05678h,&OP2 ; Load second operand ; ... ; Process results ; 8x8 Unsigned Multiply. Absolute addressing. MOV.B #012h,&0130h ; Load first operand MOV.B #034h,&0138h ; Load 2nd operand ; ... ; Process results ; 16x16 Signed Multiply MOV #01234h,&MPYS MOV #05678h,&OP2 ; ... ; Load first operand ; Load 2nd operand ; Process results ; 8x8 Signed Multiply. Absolute addressing. MOV.B #012h,&0132h ; Load first operand MOV.B #034h,&0138h ; Load 2nd operand ; ... ; Process results ; 16x16 Unsigned Multiply Accumulate MOV #01234h,&MAC ; Load first operand MOV #05678h,&OP2 ; Load 2nd operand ; ... ; Process results ; 8x8 Unsigned Multiply Accumulate. Absolute addressing MOV.B #012h,&0134h ; Load first operand MOV.B #034h,&0138h ; Load 2nd operand ; ... ; Process results ; 16x16 Signed Multiply Accumulate MOV #01234h,&MACS ; Load first operand MOV #05678h,&OP2 ; Load 2nd operand ; ... ; Process results ; 8x8 Signed Multiply Accumulate. Absolute addressing MOV.B #012h,&0136h ; Load first operand MOV.B #034h,R5 ; Temp. location for 2nd operand MOV R5,&OP2 ; Load 2nd operand ; ... ; Process results 352 Hardware Multiplier SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Hardware Multiplier Operation 11.2.4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers, At least one instruction is needed between loading the second operand and accessing one of the result registers: ; Access multiplier results with indirect addressing MOV #RESLO,R5 ; RESLO address in R5 for indirect MOV &OPER1,&MPY ; Load 1st operand MOV &OPER2,&OP2 ; Load 2nd operand NOP ; Need one cycle MOV @R5+,&xxx ; Move RESLO MOV @R5,&xxx ; Move RESHI 11.2.5 Using Interrupts If an interrupt occurs after writing OP1, but before writing OP2, and the multiplier is used in servicing that interrupt, the original multiplier mode selection is lost and the results are unpredictable. To avoid this, disable interrupts before using the hardware multiplier or do not use the multiplier in interrupt service routines. ; Disable interrupts before using the hardware multiplier DINT ; Disable interrupts NOP ; Required for DINT MOV #xxh,&MPY ; Load 1st operand MOV #xxh,&OP2 ; Load 2nd operand EINT ; Interrupts may be enable before ; Process results SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Hardware Multiplier 353 Hardware Multiplier Registers 11.3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 11-4. Table 11-4. Hardware Multiplier Registers Register Operand one - multiply Operand one - signed multiply Operand one - multiply accumulate Operand one - signed multiply accumulate Operand two Result low word Result high word Sum extension register Short Form MPY MPYS MAC MACS OP2 RESLO RESHI SUMEXT Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read Address 0130h 0132h 0134h 0136h 0138h 013Ah 013Ch 013Eh www.ti.com Initial State Unchanged Unchanged Unchanged Unchanged Unchanged Undefined Undefined Undefined 354 Hardware Multiplier SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 12 SLAU144J – December 2004 – Revised July 2013 Timer_A Timer_A is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes the operation of the Timer_A of the MSP430x2xx device family. Topic ........................................................................................................................... Page 12.1 Timer_A Introduction ....................................................................................... 356 12.2 Timer_A Operation ........................................................................................... 357 12.3 Timer_A Registers ........................................................................................... 369 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 355 Timer_A Introduction www.ti.com 12.1 Timer_A Introduction Timer_A is a 16-bit timer/counter with three capture/compare registers. Timer_A can support multiple capture/compares, PWM outputs, and interval timing. Timer_A also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A features include: • Asynchronous 16-bit timer/counter with four operating modes • Selectable and configurable clock source • Two or three configurable capture/compare registers • Configurable outputs with PWM capability • Asynchronous input and output latching • Interrupt vector register for fast decoding of all Timer_A interrupts The block diagram of Timer_A is shown in Figure 12-1. NOTE: Use of the Word Count Count is used throughout this chapter. It means the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then an associated action will not take place. 356 Timer_A SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_A Operation TASSELx TACLK 00 ACLK 01 SMCLK 10 INCLK 11 Timer Clock IDx 15 Divider 1/2/4/8 Clear TACLR 16−bit Timer TAR CCISx CMx CCI2A CCI2B GND VCC 00 Capture 01 Mode 10 Timer Clock 11 CCI logic COV SCS 0 Sync 1 SCCI Y A EN MCx Timer Block 0 Count Mode EQU0 RC Set TAIFG CCR0 CCR1 CCR2 15 0 TACCR2 Comparator 2 EQU2 CAP 0 Set TACCR2 1 CCIFG EQU0 Output Unit2 OUT Timer Clock D Set Q Reset OUT2 Signal OUTMODx POR Figure 12-1. Timer_A Block Diagram 12.2 Timer_A Operation The Timer_A module is configured with user software. The setup and operation of Timer_A is discussed in the following sections. 12.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TAR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TAR can be read or written with software. Additionally, the timer can generate an interrupt when it overflows. TAR may be cleared by setting the TACLR bit. Setting TACLR also clears the clock divider and count direction for up/down mode. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 357 Timer_A Operation www.ti.com NOTE: Modifying Timer_A Registers It is recommended to stop the timer before modifying its operation (with exception of the interrupt enable, and interrupt flag) to avoid errant operating conditions. When the timer clock is asynchronous to the CPU clock, any read from TAR should occur while the timer is not operating or the results may be unpredictable. Alternatively, the timer may be read multiple times while operating, and a majority vote taken in software to determine the correct reading. Any write to TAR will take effect immediately. 12.2.1.1 Clock Source Select and Divider The timer clock can be sourced from ACLK, SMCLK, or externally via TACLK or INCLK. The clock source is selected with the TASSELx bits. The selected clock source may be passed directly to the timer or divided by 2, 4, or 8, using the IDx bits. The timer clock divider is reset when TACLR is set. 12.2.2 Starting the Timer The timer may be started, or restarted in the following ways: • The timer counts when MCx > 0 and the clock source is active. • When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TACCR0. The timer may then be restarted by writing a nonzero value to TACCR0. In this scenario, the timer starts incrementing in the up direction from zero. 12.2.3 Timer Mode Control The timer has four modes of operation as described in Table 12-1: stop, up, continuous, and up/down. The operating mode is selected with the MCx bits. MCx 00 01 10 11 Mode Stop Up Continuous Up/down Table 12-1. Timer Modes Description The timer is halted. The timer repeatedly counts from zero to the value of TACCR0. The timer repeatedly counts from zero to 0FFFFh. The timer repeatedly counts from zero up to the value of TACCR0 and back down to zero. 12.2.3.1 Up Mode The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly counts up to the value of compare register TACCR0, which defines the period, as shown in Figure 12-2. The number of timer counts in the period is TACCR0+1. When the timer value equals TACCR0 the timer restarts counting from zero. If up mode is selected when the timer value is greater than TACCR0, the timer immediately restarts counting from zero. 0FFFFh TACCR0 0h Figure 12-2. Up Mode The TACCR0 CCIFG interrupt flag is set when the timer counts to the TACCR0 value. The TAIFG interrupt flag is set when the timer counts from TACCR0 to zero. Figure 12-3 shows the flag set cycle. 358 Timer_A SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_A Operation Timer Clock Timer Set TAIFG Set TACCR0 CCIFG CCR0−1 CCR0 0h 1h CCR0−1 CCR0 0h Figure 12-3. Up Mode Flag Setting 12.2.3.2 Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, if the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period. If the new period is less than the current count value, the timer rolls to zero. However, one additional count may occur before the counter rolls to zero. 12.2.3.3 Continuous Mode In the continuous mode, the timer repeatedly counts up to 0FFFFh and restarts from zero as shown in Figure 12-4. The capture/compare register TACCR0 works the same way as the other capture/compare registers. 0FFFFh 0h Figure 12-4. Continuous Mode The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero. Figure 12-5 shows the flag set cycle. Timer Clock Timer FFFEh FFFFh 0h 1h Set TAIFG FFFEh FFFFh 0h Figure 12-5. Continuous Mode Flag Setting 12.2.3.4 Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TACCRx register in the interrupt service routine. Figure 12-6 shows two separate time intervals t0 and t1 being added to the capture/compare registers. In this usage, the time interval is controlled by hardware, not software, without impact from interrupt latency. Up to three independent time intervals or output frequencies can be generated using all three capture/compare registers. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 359 Timer_A Operation 0FFFFh TACCR1b TACCR0b TACCR1a TACCR0a TACCR1c TACCR0c TACCR0d TACCR1d www.ti.com t0 t0 t0 t1 t1 t1 Figure 12-6. Continuous Mode Time Intervals Time intervals can be produced with other modes as well, where TACCR0 is used as the period register. Their handling is more complex since the sum of the old TACCRx data and the new period can be higher than the TACCR0 value. When the previous TACCRx value plus tx is greater than the TACCR0 data, TACCR0 + 1 must be subtracted to obtain the correct time interval. 12.2.3.5 Up/Down Mode The up/down mode is used if the timer period must be different from 0FFFFh counts, and if a symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare register TACCR0 and back down to zero, as shown in Figure 12-7. The period is twice the value in TACCR0. 0FFFFh TACCR0 0h Figure 12-7. Up/Down Mode The count direction is latched. This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped. If this is not desired, the TACLR bit must be set to clear the direction. The TACLR bit also clears the TAR value and the timer clock divider. In up/down mode, the TACCR0 CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a period, separated by 1/2 the timer period. The TACCR0 CCIFG interrupt flag is set when the timer counts from TACCR0 – 1 to TACCR0, and TAIFG is set when the timer completes counting down from 0001h to 0000h. Figure 12-8 shows the flag set cycle. 360 Timer_A SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer Clock Timer Up/Down Set TAIFG Set TACCR0 CCIFG CCR0−1 CCR0 CCR0−1 CCR0−2 Timer_A Operation 1h 0h Figure 12-8. Up/Down Mode Flag Setting 12.2.3.6 Changing the Period Register TACCR0 When changing TACCR0 while the timer is running, and counting in the down direction, the timer continues its descent until it reaches zero. The value in TACCR0 is latched into TACL0 immediately, however the new period takes effect after the counter counts down to zero. When the timer is counting in the up direction, and the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period before counting down. When the timer is counting in the up direction, and the new period is less than the current count value, the timer begins counting down. However, one additional count may occur before the counter begins counting down. 12.2.3.7 Use of the Up/Down Mode The up/down mode supports applications that require dead times between output signals (See section Timer_A Output Unit). For example, to avoid overload conditions, two outputs driving an H-bridge must never be in a high state simultaneously. In the example shown in Figure 12-9 the tdead is: tdead = ttimer (TACCR1 – TACCR2) Where, tdead = Time during which both outputs need to be inactive ttimer = Cycle time of the timer clock TACCRx = Content of capture/compare register x The TACCRx registers are not buffered. They update immediately when written to. Therefore, any required dead time will not be maintained automatically. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 361 Timer_A Operation www.ti.com 0FFFFh TACCR0 TACCR1 TACCR2 0h Dead Time Output Mode 6:Toggle/Set Output Mode 2:Toggle/Reset TAIFG EQU1 EQU1 EQU0 TAIFG EQU1 EQU1 EQU0 EQU2 EQU2 EQU2 EQU2 Interrupt Events Figure 12-9. Output Unit in Up/Down Mode 12.2.4 Capture/Compare Blocks Two or three identical capture/compare blocks, TACCRx, are present in Timer_A. Any of the blocks may be used to capture the timer data, or to generate time intervals. Capture Mode The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits. The CMx bits select the capture edge of the input signal as rising, falling, or both. A capture occurs on the selected edge of the input signal. If a capture occurs: • The timer value is copied into the TACCRx register • The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit. MSP430x2xx family devices may have different signals connected to CCIxA and CCIxB. See the device-specific data sheet for the connections of these signals. The capture signal can be asynchronous to the timer clock and cause a race condition. Setting the SCS bit will synchronize the capture with the next timer clock. Setting the SCS bit to synchronize the capture signal with the timer clock is recommended. This is illustrated in Figure 12-10. Timer Clock Timer CCI Capture Set TACCRx CCIFG n−2 n−1 n n+1 n+2 n+3 n+4 Figure 12-10. Capture Signal (SCS = 1) Overflow logic is provided in each capture/compare register to indicate if a second capture was performed before the value from the first capture was read. Bit COV is set when this occurs as shown in Figure 1211. COV must be reset with software. 362 Timer_A SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com No Capture Taken Capture Timer_A Operation Idle Capture Read Capture Taken Capture Read Taken Capture Capture Read and No Capture Clear Bit COV in Register TACCTLx Capture Second Capture Idle Taken COV = 1 Capture Figure 12-11. Capture Cycle 12.2.4.1 Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then sets CCIS1 = 1 and toggles bit CCIS0 to switch the capture signal between VCC and GND, initiating a capture each time CCIS0 changes state: MOV #CAP+SCS+CCIS1+CM_3,&TACCTLx ; Setup TACCTLx XOR #CCIS0,&TACCTLx ; TACCTLx = TAR 12.2.4.2 Compare Mode The compare mode is selected when CAP = 0. The compare mode is used to generate PWM output signals or interrupts at specific time intervals. When TAR counts to the value in a TACCRx: • Interrupt flag CCIFG is set • Internal signal EQUx = 1 • EQUx affects the output according to the output mode • The input signal CCI is latched into SCCI 12.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. 12.2.5.1 Output Modes The output modes are defined by the OUTMODx bits and are described in Table 12-2. The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0, because EQUx = EQU0. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 363 Timer_A Operation OUTMODx 000 001 010 011 100 101 110 111 Mode Output Set Toggle/Reset Set/Reset Toggle Reset Toggle/Set Reset/Set www.ti.com Table 12-2. Output Modes Description The output signal OUTx is defined by the OUTx bit. The OUTx signal updates immediately when OUTx is updated. The output is set when the timer counts to the TACCRx value. It remains set until a reset of the timer, or until another output mode is selected and affects the output. The output is toggled when the timer counts to the TACCRx value. It is reset when the timer counts to the TACCR0 value. The output is set when the timer counts to the TACCRx value. It is reset when the timer counts to the TACCR0 value. The output is toggled when the timer counts to the TACCRx value. The output period is double the timer period. The output is reset when the timer counts to the TACCRx value. It remains reset until another output mode is selected and affects the output. The output is toggled when the timer counts to the TACCRx value. It is set when the timer counts to the TACCR0 value. The output is reset when the timer counts to the TACCRx value. It is set when the timer counts to the TACCR0 value. 12.2.5.2 Output Example — Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from TACCR0 to zero, depending on the output mode. An example is shown in Figure 12-12 using TACCR0 and TACCR1. 0FFFFh TACCR0 TACCR1 0h Output Mode 1: Set Output Mode 2:Toggle/Reset Output Mode 3: Set/Reset Output Mode 4:Toggle Output Mode 5: Reset Output Mode 6:Toggle/Set Output Mode 7: Reset/Set EQU0 TAIFG EQU1 EQU0 TAIFG EQU1 EQU0 TAIFG Interrupt Events Figure 12-12. Output Example—Timer in Up Mode 364 Timer_A SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_A Operation 12.2.5.3 Output Example — Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCR0 values, depending on the output mode. An example is shown in Figure 12-13 using TACCR0 and TACCR1. 0FFFFh TACCR0 TACCR1 0h Output Mode 1: Set Output Mode 2:Toggle/Reset Output Mode 3: Set/Reset Output Mode 4:Toggle Output Mode 5: Reset Output Mode 6:Toggle/Set Output Mode 7: Reset/Set TAIFG EQU1 EQU0 TAIFG EQU1 EQU0 Interrupt Events Figure 12-13. Output Example—Timer in Continuous Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 365 Timer_A Operation www.ti.com 12.2.5.4 Output Example — Timer in Up/Down Mode The OUTx signal changes when the timer equals TACCRx in either count direction and when the timer equals TACCR0, depending on the output mode. An example is shown in Figure 12-14 using TACCR0 and TACCR2. 0FFFFh TACCR0 TACCR2 0h Output Mode 1: Set Output Mode 2:Toggle/Reset Output Mode 3: Set/Reset Output Mode 4:Toggle Output Mode 5: Reset Output Mode 6:Toggle/Set Output Mode 7: Reset/Set EQU2 EQU2 EQU2 EQU2 TAIFG EQU0 TAIFG EQU0 Interrupt Events Figure 12-14. Output Example—Timer in Up/Down Mode NOTE: Switching Between Output Modes When switching between output modes, one of the OUTMODx bits should remain set during the transition, unless switching to mode 0. Otherwise, output glitching can occur because a NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: BIS #OUTMOD_7,&TACCTLx ; Set output mode=7 BIC #OUTMODx, &TACCTLx ; Clear unwanted bits 366 Timer_A SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_A Operation 12.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: • TACCR0 interrupt vector for TACCR0 CCIFG • TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register. In compare mode, any CCIFG flag is set if TAR counts to the associated TACCRx value. Software may also set or clear any CCIFG flag. All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set. 12.2.6.1 TACCR0 Interrupt The TACCR0 CCIFG flag has the highest Timer_A interrupt priority and has a dedicated interrupt vector as shown in Figure 12-15. The TACCR0 CCIFG flag is automatically reset when the TACCR0 interrupt request is serviced. Capture EQU0 CAP Timer Clock Set CCIE D Q Reset IRQ, Interrupt Service Requested POR IRACC, Interrupt RequestAccepted Figure 12-15. Capture/Compare TACCR0 Interrupt Flag 12.2.6.2 TAIV, Interrupt Vector Generator The TACCR1 CCIFG, TACCR2 CCIFG, and TAIFG flags are prioritized and combined to source a single interrupt vector. The interrupt vector register TAIV is used to determine which flag requested an interrupt. The highest priority enabled interrupt generates a number in the TAIV register (see register description). This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled Timer_A interrupts do not affect the TAIV value. Any access, read or write, of the TAIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. For example, if the TACCR1 and TACCR2 CCIFG flags are set when the interrupt service routine accesses the TAIV register, TACCR1 CCIFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the TACCR2 CCIFG flag will generate another interrupt. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 367 Timer_A Operation www.ti.com 12.2.6.3 TAIV Software Example The following software example shows the recommended use of TAIV and the handling overhead. The TAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. The latencies are: • Capture/compare block TACCR0: 11 cycles • Capture/compare blocks TACCR1, TACCR2: 16 cycles • Timer overflow TAIFG: 14 cycles ; Interrupt handler for TACCR0 CCIFG CCIFG_0_HND ; ... ; Start of handler Interrupt latency RETI Cycles 6 5 ; Interrupt handler for TAIFG, TACCR1 and TACCR2 CCIFG TA_HND ... ; Interrupt latency 6 ADD &TAIV,PC ; Add offset to Jump table 3 RETI ; Vector 0: No interrupt 5 JMP CCIFG_1_HND ; Vector 2: TACCR1 2 JMP CCIFG_2_HND ; Vector 4: TACCR2 2 RETI ; Vector 6: Reserved 5 RETI ; Vector 8: Reserved 5 TAIFG_HND ... RETI ; Vector 10: TAIFG Flag ; Task starts here 5 CCIFG_2_HND ... RETI ; Vector 4: TACCR2 ; Task starts here ; Back to main program 5 CCIFG_1_HND ... RETI ; Vector 2: TACCR1 ; Task starts here ; Back to main program 5 368 Timer_A SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 12.3 Timer_A Registers The Timer_A registers are listed in Table 12-3. Table 12-3. Timer_A3 Registers Register Short Form Register Type Timer_A control TACTL Read/write Timer_A counter TAR Read/write Timer_A capture/compare control 0 TACCTL0 Read/write Timer_A capture/compare 0 TACCR0 Read/write Timer_A capture/compare control 1 TACCTL1 Read/write Timer_A capture/compare 1 TACCR1 Read/write Timer_A capture/compare control 2 TACCTL2 (1) Read/write Timer_A capture/compare 2 TACCR2 (1) Read/write Timer_A interrupt vector TAIV Read only (1) Not present on MSP430 devices with Timer_A2 like MSP430F20xx and other devices. Address 0160h 0170h 0162h 0172h 0164h 0174h 0166h 0176h 012Eh Timer_A Registers Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 369 Timer_A Registers 12.3.1 TACTL, Timer_A Control Register www.ti.com 15 rw-(0) 7 rw-(0) Unused TASSELx IDx MCx Unused TACLR TAIE TAIFG 14 rw-(0) 13 12 Unused rw-(0) rw-(0) 11 rw-(0) 10 rw-(0) 9 8 TASSELx rw-(0) rw-(0) 6 IDx rw-(0) 5 rw-(0) MCx 4 rw-(0) 3 Unused rw-(0) 2 TACLR rw-(0) 1 TAIE rw-(0) 0 TAIFG rw-(0) Bits 15-10 Bits 9-8 Bits 7-6 Bits 5-4 Bit 3 Bit 2 Bit 1 Bit 0 Unused Timer_A clock source select 00 TACLK 01 ACLK 10 SMCLK 11 INCLK (INCLK is device-specific and is often assigned to the inverted TBCLK) (see the device- specific data sheet) Input divider. These bits select the divider for the input clock. 00 /1 01 /2 10 /4 11 /8 Mode control. Setting MCx = 00h when Timer_A is not in use conserves power. 00 Stop mode: the timer is halted. 01 Up mode: the timer counts up to TACCR0. 10 Continuous mode: the timer counts up to 0FFFFh. 11 Up/down mode: the timer counts up to TACCR0 then down to 0000h. Unused Timer_A clear. Setting this bit resets TAR, the clock divider, and the count direction. The TACLR bit is automatically reset and is always read as zero. Timer_A interrupt enable. This bit enables the TAIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled Timer_A interrupt flag 0 No interrupt pending 1 Interrupt pending 370 Timer_A SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 12.3.2 TAR, Timer_A Register 15 rw-(0) 7 rw-(0) TARx 14 rw-(0) 13 rw-(0) 12 rw-(0) TARx 11 rw-(0) 10 rw-(0) 6 rw-(0) 5 rw-(0) 4 rw-(0) TARx 3 rw-(0) 2 rw-(0) Bits 15-0 Timer_A register. The TAR register is the count of Timer_A. Timer_A Registers 9 rw-(0) 1 rw-(0) 8 rw-(0) 0 rw-(0) 12.3.3 TACCRx, Timer_A Capture/Compare Register x 15 rw-(0) 7 rw-(0) TACCRx 14 rw-(0) 13 rw-(0) 12 11 TACCRx rw-(0) rw-(0) 10 rw-(0) 9 rw-(0) 8 rw-(0) 6 rw-(0) Bits 15-0 5 4 3 2 1 0 TACCRx rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Timer_A capture/compare register. Compare mode: TACCRx holds the data for the comparison to the timer value in the Timer_A Register, TAR. Capture mode: The Timer_A Register, TAR, is copied into the TACCRx register when a capture is performed. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 371 Timer_A Registers 12.3.4 TACCTLx, Capture/Compare Control Register www.ti.com 15 rw-(0) 7 rw-(0) CMx CCISx SCS SCCI Unused CAP OUTMODx CCIE CCI OUT COV CCIFG CMx 14 rw-(0) 13 rw-(0) CCISx 12 rw-(0) 11 SCS rw-(0) 10 SCCI r 9 Unused r0 8 CAP rw-(0) 6 5 4 3 2 1 0 OUTMODx CCIE CCI OUT COV CCIFG rw-(0) rw-(0) rw-(0) r rw-(0) rw-(0) rw-(0) Bit 15-14 Bit 13-12 Bit 11 Bit 10 Bit 9 Bit 8 Bits 7-5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture/compare input select. These bits select the TACCRx input signal. See the device-specific data sheet for specific signal connections. 00 CCIxA 01 CCIxB 10 GND 11 VCC Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0 Asynchronous capture 1 Synchronous capture Synchronized capture/compare input. The selected CCI input signal is latched with the EQUx signal and can be read via this bit Unused. Read only. Always read as 0. Capture mode 0 Compare mode 1 Capture mode Output mode. Modes 2, 3, 6, and 7 are not useful for TACCR0, because EQUx = EQU0. 000 OUT bit value 001 Set 010 Toggle/reset 011 Set/reset 100 Toggle 101 Reset 110 Toggle/set 111 Reset/set Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled Capture/compare input. The selected input signal can be read by this bit. Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0 No capture overflow occurred 1 Capture overflow occurred Capture/compare interrupt flag 0 No interrupt pending 1 Interrupt pending 372 Timer_A SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 12.3.5 TAIV, Timer_A Interrupt Vector Register 15 14 13 12 0 0 0 0 r0 r0 r0 r0 7 6 5 4 0 0 0 0 r0 r0 r0 r0 TAIVx Bits 15-0 Timer_A interrupt vector value TAIV Contents Interrupt Source 00h No interrupt pending 02h Capture/compare 1 04h Capture/compare 2(1) 06h Reserved 08h Reserved 0Ah Timer overflow 0Ch Reserved 0Eh Reserved (1) Not implemented in MSP430x20xx devices Interrupt Flag TACCR1 CCIFG TACCR2 CCIFG TAIFG - 11 10 0 0 r0 r0 3 2 TAIVx r-(0) r-(0) Interrupt Priority Highest Lowest Timer_A Registers 9 8 0 0 r0 r0 1 0 0 r-(0) r0 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_A 373 Chapter 13 SLAU144J – December 2004 – Revised July 2013 Timer_B Timer_B is a 16-bit timer/counter with multiple capture/compare registers. This chapter describes the operation of the Timer_B of the MSP430x2xx device family. Topic ........................................................................................................................... Page 13.1 Timer_B Introduction ....................................................................................... 375 13.2 Timer_B Operation ........................................................................................... 377 13.3 Timer_B Registers ........................................................................................... 390 374 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_B Introduction 13.1 Timer_B Introduction Timer_B is a 16-bit timer/counter with three or seven capture/compare registers. Timer_B can support multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_B features include : • Asynchronous 16-bit timer/counter with four operating modes and four selectable lengths • Selectable and configurable clock source • Three or seven configurable capture/compare registers • Configurable outputs with PWM capability • Double-buffered compare latches with synchronized loading • Interrupt vector register for fast decoding of all Timer_B interrupts The block diagram of Timer_B is shown in Figure 13-1. NOTE: Use of the Word Count Count is used throughout this chapter. It means the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then an associated action does not take place. 13.1.1 Similarities and Differences From Timer_A Timer_B is identical to Timer_A with the following exceptions: • The length of Timer_B is programmable to be 8, 10, 12, or 16 bits. • Timer_B TBCCRx registers are double-buffered and can be grouped. • All Timer_B outputs can be put into a high-impedance state. • The SCCI bit function is not implemented in Timer_B. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 375 Timer_B Introduction www.ti.com TBCLK ACLK SMCLK INCLK TBSSELx Timer Clock IDx 15 00 Divider 01 1/2/4/8 10 11 TBCLGRPx Clear TBCLR Group Load Logic 0 16−bit Timer TBR RC 8 10 12 16 MCx Timer Block Count Mode CNTLx EQU0 00 01 Set TBIFG 10 11 CCISx CMx CCI6A CCI6B GND VCC 00 Capture 01 Mode 10 Timer Clock 11 CLLDx CCI VCC 00 TBR=0 01 EQU0 10 UP/DOWN 11 logic COV SCS 0 Sync 1 Group Load Logic CCR5 CCR4 CCR1 CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 15 0 TBCCR6 Load Compare Latch TBCL6 Comparator 6 EQU6 CAP 0 Set TBCCR6 1 CCIFG EQU0 Output Unit6 OUT Timer Clock D Set Q Reset OUT6 Signal OUTMODx POR NOTE: INCLK is device-specific, often assigned to the inverted TBCLK, refer to device-specific data sheet. Figure 13-1. Timer_B Block Diagram 376 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_B Operation 13.2 Timer_B Operation The Timer_B module is configured with user software. The setup and operation of Timer_B is discussed in the following sections. 13.2.1 16-Bit Timer Counter The 16-bit timer/counter register, TBR, increments or decrements (depending on mode of operation) with each rising edge of the clock signal. TBR can be read or written with software. Additionally, the timer can generate an interrupt when it overflows. TBR may be cleared by setting the TBCLR bit. Setting TBCLR also clears the clock divider and count direction for up/down mode. NOTE: Modifying Timer_B Registers It is recommended to stop the timer before modifying its operation (with exception of the interrupt enable, interrupt flag, and TBCLR) to avoid errant operating conditions. When the timer clock is asynchronous to the CPU clock, any read from TBR should occur while the timer is not operating or the results may be unpredictable. Alternatively, the timer may be read multiple times while operating, and a majority vote taken in software to determine the correct reading. Any write to TBR will take effect immediately. 13.2.1.1 TBR Length Timer_B is configurable to operate as an 8-, 10-, 12-, or 16-bit timer with the CNTLx bits. The maximum count value, TBR(max), for the selectable lengths is 0FFh, 03FFh, 0FFFh, and 0FFFFh, respectively. Data written to the TBR register in 8-, 10-, and 12-bit mode is right-justified with leading zeros. 13.2.1.2 Clock Source Select and Divider The timer clock can be sourced from ACLK, SMCLK, or externally via TBCLK or INCLK (INCLK is devicespecific, often assigned to the inverted TBCLK, refer to device-specific data sheet). The clock source is selected with the TBSSELx bits. The selected clock source may be passed directly to the timer or divided by 2,4, or 8, using the IDx bits. The clock divider is reset when TBCLR is set. 13.2.2 Starting the Timer The timer may be started or restarted in the following ways: • The timer counts when MCx > 0 and the clock source is active. • When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBCL0. The timer may then be restarted by loading a nonzero value to TBCL0. In this scenario, the timer starts incrementing in the up direction from zero. 13.2.3 Timer Mode Control The timer has four modes of operation as described in Table 13-1: stop, up, continuous, and up/down. The operating mode is selected with the MCx bits. MCx 00 01 10 11 Mode Stop Up Continuous Up/down Table 13-1. Timer Modes Description The timer is halted. The timer repeatedly counts from zero to the value of compare register TBCL0. The timer repeatedly counts from zero to the value selected by the CNTLx bits. The timer repeatedly counts from zero up to the value of TBCL0 and then back down to zero. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 377 Timer_B Operation www.ti.com 13.2.3.1 Up Mode The up mode is used if the timer period must be different from TBR(max) counts. The timer repeatedly counts up to the value of compare latch TBCL0, which defines the period, as shown in Figure 13-2. The number of timer counts in the period is TBCL0+1. When the timer value equals TBCL0 the timer restarts counting from zero. If up mode is selected when the timer value is greater than TBCL0, the timer immediately restarts counting from zero. TBR(max) TBCL0 0h Figure 13-2. Up Mode The TBCCR0 CCIFG interrupt flag is set when the timer counts to the TBCL0 value. The TBIFG interrupt flag is set when the timer counts from TBCL0 to zero. Figure 13-3 shows the flag set cycle. Timer Clock Timer TBCL0−1 TBCL0 0h 1h Set TBIFG Set TBCCR0 CCIFG TBCL0−1 TBCL0 0h Figure 13-3. Up Mode Flag Setting 13.2.3.2 Changing the Period Register TBCL0 When changing TBCL0 while the timer is running and when the TBCL0 load event is immediate, CLLD0 = 00, if the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period. If the new period is less than the current count value, the timer rolls to zero. However, one additional count may occur before the counter rolls to zero. 13.2.3.3 Continuous Mode In continuous mode the timer repeatedly counts up to TBR(max) and restarts from zero as shown in Figure 13-4. The compare latch TBCL0 works the same way as the other capture/compare registers. TBR(max) 0h Figure 13-4. Continuous Mode The TBIFG interrupt flag is set when the timer counts from TBR(max) to zero. Figure 13-5 shows the flag set cycle. 378 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_B Operation Timer Clock Timer TBR (max−) 1 TBR (max) 0h 1h Set TBIFG TBR (max−)1 TBR (max) 0h Figure 13-5. Continuous Mode Flag Setting 13.2.3.4 Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies. Each time an interval is completed, an interrupt is generated. The next time interval is added to the TBCLx latch in the interrupt service routine. Figure 13-6 shows two separate time intervals t0 and t1 being added to the capture/compare registers. The time interval is controlled by hardware, not software, without impact from interrupt latency. Up to three (Timer_B3) or 7 (Timer_B7) independent time intervals or output frequencies can be generated using capture/compare registers. TBR(max) TBCL1b TBCL0b TBCL1c TBCL0c TBCL0d TBCL1a TBCL0a TBCL1d 0h EQU0 Interrupt t0 t0 t0 EQU1 Interrupt t1 t1 t1 Figure 13-6. Continuous Mode Time Intervals Time intervals can be produced with other modes as well, where TBCL0 is used as the period register. Their handling is more complex since the sum of the old TBCLx data and the new period can be higher than the TBCL0 value. When the sum of the previous TBCLx value plus tx is greater than the TBCL0 data, TBCL0 + 1 must be subtracted to obtain the correct time interval. 13.2.3.5 Up/Down Mode The up/down mode is used if the timer period must be different from TBR(max) counts, and if a symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare latch TBCL0, and back down to zero, as shown in Figure 13-7. The period is twice the value in TBCL0. NOTE: TBCL0 > TBR(max) If TBCL0 > TBR(max), the counter operates as if it were configured for continuous mode. It does not count down from TBR(max) to zero. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 379 Timer_B Operation TBCL0 www.ti.com 0h Figure 13-7. Up/Down Mode The count direction is latched. This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped. If this is not desired, the TBCLR bit must be used to clear the direction. The TBCLR bit also clears the TBR value and the clock divider. In up/down mode, the TBCCR0 CCIFG interrupt flag and the TBIFG interrupt flag are set only once during the period, separated by 1/2 the timer period. The TBCCR0 CCIFG interrupt flag is set when the timer counts from TBCL0-1 to TBCL0, and TBIFG is set when the timer completes counting down from 0001h to 0000h. Figure 13-8 shows the flag set cycle. Timer Clock Timer Up/Down Set TBIFG Set TBCCR0 CCIFG TBCL0−1 TBCL0 TBCL0−1 TBCL0−2 1h 0h 1h Figure 13-8. Up/Down Mode Flag Setting 13.2.3.6 Changing the Value of Period Register TBCL0 When changing TBCL0 while the timer is running, and counting in the down direction, and when the TBCL0 load event is immediate, the timer continues its descent until it reaches zero. The value in TBCCR0 is latched into TBCL0 immediately; however, the new period takes effect after the counter counts down to zero. If the timer is counting in the up direction when the new period is latched into TBCL0, and the new period is greater than or equal to the old period, or greater than the current count value, the timer counts up to the new period before counting down. When the timer is counting in the up direction, and the new period is less than the current count value when TBCL0 is loaded, the timer begins counting down. However, one additional count may occur before the counter begins counting down. 13.2.3.7 Use of the Up/Down Mode The up/down mode supports applications that require dead times between output signals (see section Timer_B Output Unit). For example, to avoid overload conditions, two outputs driving an H-bridge must never be in a high state simultaneously. In the example shown in Figure 13-9 the tdead is: tdead = ttimer× (TBCL1 - TBCL3) Where, tdead = Time during which both outputs need to be inactive ttimer = Cycle time of the timer clock TBCLx = Content of compare latch x 380 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com The ability to simultaneously load grouped compare latches assures the dead times. Timer_B Operation TBR(max) TBCL0 TBCL1 TBCL3 0h Dead Time Output Mode 6:Toggle/Set Output Mode 2:Toggle/Reset TBIFG EQU1 EQU1 EQU0 TBIFG EQU1 EQU1 EQU0 EQU3 EQU3 EQU3 EQU3 Interrupt Events Figure 13-9. Output Unit in Up/Down Mode 13.2.4 Capture/Compare Blocks Three or seven identical capture/compare blocks, TBCCRx, are present in Timer_B. Any of the blocks may be used to capture the timer data or to generate time intervals. 13.2.4.1 Capture Mode The capture mode is selected when CAP = 1. Capture mode is used to record time events. It can be used for speed computations or time measurements. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits. The CMx bits select the capture edge of the input signal as rising, falling, or both. A capture occurs on the selected edge of the input signal. If a capture is performed: • The timer value is copied into the TBCCRx register • The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit. MSP430x2xx family devices may have different signals connected to CCIxA and CCIxB. Refer to the device-specific data sheet for the connections of these signals. The capture signal can be asynchronous to the timer clock and cause a race condition. Setting the SCS bit will synchronize the capture with the next timer clock. Setting the SCS bit to synchronize the capture signal with the timer clock is recommended. This is illustrated in Figure 13-10. Timer Clock Timer CCI Capture Set TBCCRx CCIFG n−2 n−1 n n+1 n+2 n+3 n+4 Figure 13-10. Capture Signal (SCS = 1) SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 381 Timer_B Operation www.ti.com Overflow logic is provided in each capture/compare register to indicate if a second capture was performed before the value from the first capture was read. Bit COV is set when this occurs as shown in Figure 1311. COV must be reset with software. Idle Capture Capture Read No Capture Taken Capture Taken Read Taken Capture Capture Capture Read and No Capture Clear Bit COV in Register TBCCTLx Capture Second Capture Idle Taken COV = 1 Capture Figure 13-11. Capture Cycle 13.2.4.1.1 Capture Initiated by Software Captures can be initiated by software. The CMx bits can be set for capture on both edges. Software then sets bit CCIS1=1 and toggles bit CCIS0 to switch the capture signal between VCC and GND, initiating a capture each time CCIS0 changes state: MOV #CAP+SCS+CCIS1+CM_3,&TBCCTLx ; Setup TBCCTLx XOR #CCIS0, &TBCCTLx ; TBCCTLx = TBR 382 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_B Operation 13.2.4.2 Compare Mode The compare mode is selected when CAP = 0. Compare mode is used to generate PWM output signals or interrupts at specific time intervals. When TBR counts to the value in a TBCLx: • Interrupt flag CCIFG is set • Internal signal EQUx = 1 • EQUx affects the output according to the output mode 13.2.4.2.1 Compare Latch TBCLx The TBCCRx compare latch, TBCLx, holds the data for the comparison to the timer value in compare mode. TBCLx is buffered by TBCCRx. The buffered compare latch gives the user control over when a compare period updates. The user cannot directly access TBCLx. Compare data is written to each TBCCRx and automatically transferred to TBCLx. The timing of the transfer from TBCCRx to TBCLx is user-selectable with the CLLDx bits as described in Table 13-2. CLLDx 00 01 10 11 Table 13-2. TBCLx Load Events Description New data is transferred from TBCCRx to TBCLx immediately when TBCCRx is written to. New data is transferred from TBCCRx to TBCLx when TBR counts to 0 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 for up and continuous modes. New data is transferred to from TBCCRx to TBCLx when TBR counts to the old TBCL0 value or to 0 for up/down mode New data is transferred from TBCCRx to TBCLx when TBR counts to the old TBCLx value. 13.2.4.2.2 Grouping Compare Latches Multiple compare latches may be grouped together for simultaneous updates with the TBCLGRPx bits. When using groups, the CLLDx bits of the lowest numbered TBCCRx in the group determine the load event for each compare latch of the group, except when TBCLGRP = 3, as shown in Table 13-3. The CLLDx bits of the controlling TBCCRx must not be set to zero. When the CLLDx bits of the controlling TBCCRx are set to zero, all compare latches update immediately when their corresponding TBCCRx is written; no compare latches are grouped. Two conditions must exist for the compare latches to be loaded when grouped. First, all TBCCRx registers of the group must be updated, even when new TBCCRx data = old TBCCRx data. Second, the load event must occur. TBCLGRPx 00 01 10 11 Table 13-3. Compare Latch Operating Modes Grouping None TBCL1+TBCL2 TBCL3+TBCL4 TBCL5+TBCL6 TBCL1+TBCL2+TBCL3 TBCL4+TBCL5+TBCL6 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6 Update Control Individual TBCCR1 TBCCR3 TBCCR5 TBCCR1 TBCCR4 TBCCR1 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 383 Timer_B Operation www.ti.com 13.2.5 Output Unit Each capture/compare block contains an output unit. The output unit is used to generate output signals such as PWM signals. Each output unit has eight operating modes that generate signals based on the EQU0 and EQUx signals. The TBOUTH pin function can be used to put all Timer_B outputs into a highimpedance state. When the TBOUTH pin function is selected for the pin, and when the pin is pulled high, all Timer_B outputs are in a high-impedance state. 13.2.5.1 Output Modes The output modes are defined by the OUTMODx bits and are described in Table 13-4. The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0 because EQUx = EQU0. OUTMODx 000 001 010 011 100 101 110 111 Table 13-4. Output Modes Mode Output Set Toggle/Reset Set/Reset Toggle Reset Toggle/Set Reset/Set Description The output signal OUTx is defined by the OUTx bit. The OUTx signal updates immediately when OUTx is updated. The output is set when the timer counts to the TBCLx value. It remains set until a reset of the timer, or until another output mode is selected and affects the output. The output is toggled when the timer counts to the TBCLx value. It is reset when the timer counts to the TBCL0 value. The output is set when the timer counts to the TBCLx value. It is reset when the timer counts to the TBCL0 value. The output is toggled when the timer counts to the TBCLx value. The output period is double the timer period. The output is reset when the timer counts to the TBCLx value. It remains reset until another output mode is selected and affects the output. The output is toggled when the timer counts to the TBCLx value. It is set when the timer counts to the TBCL0 value. The output is reset when the timer counts to the TBCLx value. It is set when the timer counts to the TBCL0 value. 384 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_B Operation 13.2.5.1.1 Output Example, Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode. An example is shown in Figure 13-12 using TBCL0 and TBCL1. TBR(max) TBCL0 TBCL1 0h Output Mode 1: Set Output Mode 2:Toggle/Reset Output Mode 3: Set/Reset Output Mode 4:Toggle Output Mode 5: Reset Output Mode 6:Toggle/Set Output Mode 7: Reset/Set EQU0 TBIFG EQU1 EQU0 TBIFG EQU1 EQU0 TBIFG Interrupt Events Figure 13-12. Output Example, Timer in Up Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 385 Timer_B Operation www.ti.com 13.2.5.1.2 Output Example, Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, An example is shown in Figure 13-13 using TBCL0 and TBCL1. TBR(max) TBCL0 TBCL1 0h Output Mode 1: Set Output Mode 2:Toggle/Reset Output Mode 3: Set/Reset Output Mode 4:Toggle Output Mode 5: Reset Output Mode 6:Toggle/Set Output Mode 7: Reset/Set TBIFG EQU1 EQU0 TBIFG EQU1 EQU0 Interrupt Events Figure 13-13. Output Example, Timer in Continuous Mode 386 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Timer_B Operation 13.2.5.1.3 Output Example, Timer in Up/Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode. An example is shown in Figure 13-14 using TBCL0 and TBCL3. TBR(max) TBCL0 TBCL3 0h Output Mode 1: Set Output Mode 2:Toggle/Reset Output Mode 3: Set/Reset Output Mode 4:Toggle Output Mode 5: Reset Output Mode 6:Toggle/Set Output Mode 7: Reset/Set EQU3 EQU3 EQU3 EQU3 TBIFG EQU0 TBIFG EQU0 Interrupt Events Figure 13-14. Output Example, Timer in Up/Down Mode NOTE: Switching Between Output Modes When switching between output modes, one of the OUTMODx bits should remain set during the transition, unless switching to mode 0. Otherwise, output glitching can occur because a NOR gate decodes output mode 0. A safe method for switching between output modes is to use output mode 7 as a transition state: BIS #OUTMOD_7,&TBCCTLx ; Set output mode=7 BIC #OUTMODx, &TBCCTLx ; Clear unwanted bits SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 387 Timer_B Operation www.ti.com 13.2.6 Timer_B Interrupts Two interrupt vectors are associated with the 16-bit Timer_B module: • TBCCR0 interrupt vector for TBCCR0 CCIFG • TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode, any CCIFG flag is set when a timer value is captured in the associated TBCCRx register. In compare mode, any CCIFG flag is set when TBR counts to the associated TBCLx value. Software may also set or clear any CCIFG flag. All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set. 13.2.6.1 TBCCR0 Interrupt Vector The TBCCR0 CCIFG flag has the highest Timer_B interrupt priority and has a dedicated interrupt vector as shown in Figure 13-15. The TBCCR0 CCIFG flag is automatically reset when the TBCCR0 interrupt request is serviced. Capture EQU0 CAP Timer Clock Set CCIE D Q Reset IRQ, Interrupt Service Requested POR IRACC, Interrupt RequestAccepted Figure 13-15. Capture/Compare TBCCR0 Interrupt Flag 13.2.6.2 TBIV, Interrupt Vector Generator The TBIFG flag and TBCCRx CCIFG flags (excluding TBCCR0 CCIFG) are prioritized and combined to source a single interrupt vector. The interrupt vector register TBIV is used to determine which flag requested an interrupt. The highest priority enabled interrupt (excluding TBCCR0 CCIFG) generates a number in the TBIV register (see register description). This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled Timer_B interrupts do not affect the TBIV value. Any access, read or write, of the TBIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. For example, if the TBCCR1 and TBCCR2 CCIFG flags are set when the interrupt service routine accesses the TBIV register, TBCCR1 CCIFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the TBCCR2 CCIFG flag will generate another interrupt. 13.2.6.3 TBIV, Interrupt Handler Examples The following software example shows the recommended use of TBIV and the handling overhead. The TBIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU clock cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. The latencies are: • Capture/compare block CCR0: 11 cycles • Capture/compare blocks CCR1 to CCR6: 16 cycles • Timer overflow TBIFG: 14 cycles Example 13-1 shows the recommended use of TBIV for Timer_B3. 388 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Example 13-1. Recommended Use of TBIV ; Interrupt handler for TBCCR0 CCIFG. CCIFG_0_HND ... ; Start of handler Interrupt latency RETI Cycles 6 5 ; Interrupt handler for TBIFG, TBCCR1 and TBCCR2 CCIFG. TB_HND ... ; Interrupt latency 6 ADD &TBIV,PC ; Add offset to Jump table 3 RETI ; Vector 0: No interrupt 5 JMP CCIFG_1_HND ; Vector 2: Module 1 2 JMP CCIFG_2_HND ; Vector 4: Module 2 2 RETI ; Vector 6 RETI ; Vector 8 RETI ; Vector 10 RETI ; Vector 12 TBIFG_HND ... RETI ; Vector 14: TIMOV Flag ; Task starts here 5 CCIFG_2_HND ... RETI ; Vector 4: Module 2 ; Task starts here ; Back to main program 5 ; The Module 1 handler shows a way to look if any other ; interrupt is pending: 5 cycles have to be spent, but ; 9 cycles may be saved if another interrupt is pending CCIFG_1_HND ; Vector 6: Module 3 ... ; Task starts here JMP TB_HND ; Look for pending ints 2 Timer_B Operation SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 389 Timer_B Registers 13.3 Timer_B Registers The Timer_B registers are listed in Table 13-5: Register Timer_B control Timer_B counter Timer_B capture/compare control 0 Timer_B capture/compare 0 Timer_B capture/compare control 1 Timer_B capture/compare 1 Timer_B capture/compare control 2 Timer_B capture/compare 2 Timer_B capture/compare control 3 Timer_B capture/compare 3 Timer_B capture/compare control 4 Timer_B capture/compare 4 Timer_B capture/compare control 5 Timer_B capture/compare 5 Timer_B capture/compare control 6 Timer_B capture/compare 6 Timer_B interrupt vector Table 13-5. Timer_B Registers Short Form TBCTL TBR TBCCTL0 TBCCR0 TBCCTL1 TBCCR1 TBCCTL2 TBCCR2 TBCCTL3 TBCCR3 TBCCTL4 TBCCR4 TBCCTL5 TBCCR5 TBCCTL6 TBCCR6 TBIV Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Address 0180h 0190h 0182h 0192h 0184h 0194h 0186h 0196h 0188h 0198h 018Ah 019Ah 018Ch 019Ch 018Eh 019Eh 011Eh www.ti.com Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR 390 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.3.1 Timer_B Control Register TBCTL Timer_B Registers 15 Unused rw-(0) 14 13 TBCLGRPx rw-(0) rw-(0) 12 11 CNTLx rw-(0) rw-(0) 10 Unused rw-(0) 9 8 TBSSELx rw-(0) rw-(0) 7 6 IDx rw-(0) rw-(0) 5 rw-(0) MCx 4 rw-(0) 3 Unused rw-(0) 2 TBCLR w-(0) 1 TBIE rw-(0) 0 TBIFG rw-(0) Unused TBCLGRP CNTLx Unused TBSSELx IDx MCx Unused TBCLR TBIE TBIFG Bit 15 Bit 14-13 Bits 12-11 Bit 10 Bits 9-8 Bits 7-6 Bits 5-4 Bit 3 Bit 2 Bit 1 Bit 0 Unused TBCLx group 00 Each TBCLx latch loads independently 01 TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update) TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update) TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update) TBCL0 independent 10 TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update) TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update) TBCL0 independent 11 TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6 (TBCCR1 CLLDx bits control the update) Counter length 00 16-bit, TBR(max) = 0FFFFh 01 12-bit, TBR(max) = 0FFFh 10 10-bit, TBR(max) = 03FFh 11 8-bit, TBR(max) = 0FFh Unused Timer_B clock source select. 00 TBCLK 01 ACLK 10 SMCLK 11 INCLK (INCLK is device-specific and is often assigned to the inverted TBCLK) (see the device- specific data sheet) Input divider. These bits select the divider for the input clock.00 /101 /210 /411 /8 Mode control. Setting MCx = 00h when Timer_B is not in use conserves power. 00 Stop mode: the timer is halted 01 Up mode: the timer counts up to TBCL0 10 Continuous mode: the timer counts up to the value set by CNTLx 11 Up/down mode: the timer counts up to TBCL0 and down to 0000h Unused Timer_B clear. Setting this bit resets TBR, the clock divider, and the count direction. The TBCLR bit is automatically reset and is always read as zero. Timer_B interrupt enable. This bit enables the TBIFG interrupt request. 0 Interrupt disabled 1 Interrupt enabled Timer_B interrupt flag. 0 No interrupt pending 1 Interrupt pending SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 391 Timer_B Registers 13.3.2 TBR, Timer_B Register 15 rw-(0) 7 rw-(0) TBRx 14 rw-(0) 13 rw-(0) 12 rw-(0) TBRx 11 rw-(0) 10 rw-(0) 6 rw-(0) 5 rw-(0) 4 rw-(0) TBRx 3 rw-(0) 2 rw-(0) Bits 15-0 Timer_B register. The TBR register is the count of Timer_B. www.ti.com 9 rw-(0) 1 rw-(0) 8 rw-(0) 0 rw-(0) 13.3.3 TBCCRx, Timer_B Capture/Compare Register x 15 rw-(0) 7 rw-(0) TBCCRx 14 rw-(0) 13 rw-(0) 12 11 TBCCRx rw-(0) rw-(0) 10 rw-(0) 9 rw-(0) 8 rw-(0) 6 rw-(0) 5 rw-(0) 4 3 TBCCRx rw-(0) rw-(0) 2 rw-(0) 1 rw-(0) 0 rw-(0) Bits 15-0 Timer_B capture/compare register. Compare mode: Compare data is written to each TBCCRx and automatically transferred to TBCLx. TBCLx holds the data for the comparison to the timer value in the Timer_B Register, TBR. Capture mode: The Timer_B Register, TBR, is copied into the TBCCRx register when a capture is performed. 392 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 13.3.4 TBCCTLx, Capture/Compare Control Register Timer_B Registers 15 rw-(0) 7 rw-(0) CMx CCISx SCS CLLDx CAP OUTMODx CCIE CCI OUT COV CCIFG CMx 14 rw-(0) 13 rw-(0) CCISx 12 rw-(0) 11 SCS rw-(0) 10 9 CLLDx rw-(0) r-(0) 8 CAP rw-(0) 6 5 4 3 2 1 0 OUTMODx CCIE CCI OUT COV CCIFG rw-(0) rw-(0) rw-(0) r rw-(0) rw-(0) rw-(0) Bit 15-14 Bit 13-12 Bit 11 Bit 10-9 Bit 8 Bits 7-5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture/compare input select. These bits select the TBCCRx input signal. See the device-specific data sheet for specific signal connections. 00 CCIxA 01 CCIxB 10 GND 11 VCC Synchronize capture source. This bit is used to synchronize the capture input signal with the timer clock. 0 Asynchronous capture 1 Synchronous capture Compare latch load. These bits select the compare latch load event. 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBCLx loads when TBR countsto 0 (up or continuous mode) TBCLx loads when TBR countsto TBCL0 or to 0 (up/down mode) 11 TBCLx loads when TBR countsto TBCLx Capture mode 0 Compare mode 1 Capture mode Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx = EQU0. 000 OUT bit value 001 Set 010 Toggle/reset 011 Set/reset 100 Toggle 101 Reset 110 Toggle/set 111 Reset/set Capture/compare interrupt enable. This bit enables the interrupt request of the corresponding CCIFG flag. 0 Interrupt disabled 1 Interrupt enabled Capture/compare input. The selected input signal can be read by this bit. Output. For output mode 0, this bit directly controls the state of the output. 0 Output low 1 Output high Capture overflow. This bit indicates a capture overflow occurred. COV must be reset with software. 0 No capture overflow occurred 1 Capture overflow occurred Capture/compare interrupt flag 0 No interrupt pending 1 Interrupt pending SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Timer_B 393 Timer_B Registers 13.3.5 TBIV, Timer_B Interrupt Vector Register 15 14 13 12 0 0 0 0 r0 r0 r0 r0 7 6 5 4 0 0 0 0 r0 r0 r0 r0 TBIVx Bits 15-0 Timer_B interrupt vector value TBIV Contents Interrupt Source 00h No interrupt pending 02h Capture/compare 1 04h Capture/compare 2 06h Capture/compare 3(1) 08h Capture/compare 4(1) 0Ah Capture/compare 5(1) 0Ch Capture/compare 6(1) 0Eh Timer overflow (1) Not available on all devices Interrupt Flag TBCCR1 CCIFG TBCCR2 CCIFG TBCCR3 CCIFG TBCCR4 CCIFG TBCCR5 CCIFG TBCCR6 CCIFG TBIFG 11 10 0 0 r0 r0 3 2 TBIVx r-(0) r-(0) Interrupt Priority Highest Lowest www.ti.com 9 8 0 0 r0 r0 1 0 0 r-(0) r0 394 Timer_B SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 14 SLAU144J – December 2004 – Revised July 2013 Universal Serial Interface (USI) The Universal Serial Interface (USI) module provides SPI and I2C serial communication with one hardware module. This chapter discusses both modes. Topic ........................................................................................................................... Page 14.1 USI Introduction .............................................................................................. 396 14.2 USI Operation .................................................................................................. 399 14.3 USI Registers .................................................................................................. 405 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Universal Serial Interface (USI) 395 USI Introduction www.ti.com 14.1 USI Introduction The USI module provides the basic functionality to support synchronous serial communication. In its simplest form, it is an 8- or 16-bit shift register that can be used to output data streams, or when combined with minimal software, can implement serial communication. In addition, the USI includes built-in hardware functionality to ease the implementation of SPI and I2C communication. The USI module also includes interrupts to further reduce the necessary software overhead for serial communication and to maintain the ultra-low-power capabilities of the MSP430. The USI module features include: • Three-wire SPI mode support • I2C mode support • Variable data length • Slave operation in LPM4; no internal clock required • Selectable MSB or LSB data order • START and STOP detection for I2C mode with automatic SCL control • Arbitration lost detection in master mode • Programmable clock generation • Selectable clock polarity and phase control Figure 14-1 shows the USI module in SPI mode. Figure 14-2 shows the USI module in I2C mode. 396 Universal Serial Interface (USI) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USII2C = 0 USISWRST USIGE USI16B USILSB 8/16 Bit Shift Register EN USISR USICNTx USIIFGCC Bit Counter EN Set USIIFG USI Introduction USIOE USIPE6 DQ G SDO USIPE7 SDI USICKPH USICKPL Shift Clock 1 0 USISSELx SCLK ACLK SMCLK SMCLK USISWCLK TA 0 TA 1 TA 2 000 USIDIVx 001 010 011 Clock Divider /1/2/4/8... /128 100 HOLD 101 110 111 USIMST 1 USICLK 0 USIIFG Figure 14-1. USI Block Diagram: SPI Mode USIPE5 SCLK SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Universal Serial Interface (USI) 397 USI Introduction USII2C = 1 USICKPL = 1 USICKPH = 0 USILSB = 0 USI16B = 0 USIOE USIGE DQ G USISWRST MSB LSB 8−Bit Shift Register EN USISRL USICNTx USIIFGCC Bit Counter EN Set USIIFG USICKPH USICKPL Shift Clock 1 0 www.ti.com DQ Set USIAL, Clear USIOE USIPE7 SDA START Detect STOP Detect Set USISTTIFG Set USISTP USIPE6 SCL USISTTIFG USIIFG SCL Hold USISSELx USISCLREL USIMST SCLK 000 ACLK 001 SMCLK 010 SMCLK 011 SWCLK 100 TA 0 101 TA 1 110 TA 2 111 USIDIVx HOLD Clock Divider /1/2/4/8... /128 1 0 USICLK Figure 14-2. USI Block Diagram: I2C Mode 398 Universal Serial Interface (USI) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USI Operation 14.2 USI Operation The USI module is a shift register and bit counter that includes logic to support SPI and I2C communication. The USI shift register (USISR) is directly accessible by software and contains the data to be transmitted or the data that has been received. The bit counter counts the number of sampled bits and sets the USI interrupt flag USIIFG when the USICNTx value becomes zero, either by decrementing or by directly writing zero to the USICNTx bits. Writing USICNTx with a value > 0 automatically clears USIIFG when USIIFGCC = 0, otherwise USIIFG is not affected. The USICNTx bits stop decrementing when they become 0. They will not underflow to 0FFh. Both the counter and the shift register are driven by the same shift clock. On a rising shift clock edge, USICNTx decrements and USISR samples the next bit input. The latch connected to the shift register’s output delays the change of the output to the falling edge of shift clock. It can be made transparent by setting the USIGE bit. This setting will immediately output the MSB or LSB of USISR to the SDO pin, depending on the USILSB bit. 14.2.1 USI Initialization While the USI software reset bit, USISWRST, is set, the flags USIIFG, USISTTIFG, USISTP, and USIAL will be held in their reset state. USISR and USICNTx are not clocked and their contents are not affected. In I2C mode, the SCL line is also released to the idle state by the USI hardware. To activate USI port functionality the corresponding USIPEx bits in the USI control register must be set. This will select the USI function for the pin and maintains the PxIN and PxIFG functions for the pin as well. With this feature, the port input levels can be read via the PxIN register by software and the incoming data stream can generate port interrupts on data transitions. This is useful, for example, to generate a port interrupt on a START edge. 14.2.2 USI Clock Generation The USI clock generator contains a clock selection multiplexer, a divider, and the ability to select the clock polarity as shown in the block diagrams Figure 14-1 and Figure 14-2. The clock source can be selected from the internal clocks ACLK or SMCLK, from an external clock SCLK, as well as from the capture/compare outputs of Timer_A. In addition, it is possible to clock the module by software using the USISWCLK bit when USISSELx = 100. The USIDIVx bits can be used to divide the selected clock by a power of 2 up to 128. The generated clock, USICLK, is stopped when USIIFG = 1 or when the module operates in slave mode. The USICKPL bit is used to select the polarity of USICLK. When USICKPL = 0, the inactive level of USICLK is low. When USICKPL = 1 the inactive level of USICLK is high. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Universal Serial Interface (USI) 399 USI Operation www.ti.com 14.2.3 SPI Mode The USI module is configured in SPI mode when USII2C = 0. Control bit USICKPL selects the inactive level of the SPI clock while USICKPH selects the clock edge on which SDO is updated and SDI is sampled. Figure 14-3 shows the clock/data relationship for an 8-bit, MSB-first transfer. USIPE5, USIPE6, and USIPE7 must be set to enable the SCLK, SDO, and SDI port functions. USI USI USICNTx 0 8 7 6 5 4 3 2 1 0 CKPH CKPL 00 SCLK 01 SCLK 10 SCLK 11 SCLK 0 X SDO/SDI MSB LSB 1 X SDO/SDI MSB LSB Load USICNTx USIIFG Figure 14-3. SPI Timing 14.2.3.1 SPI Master Mode The USI module is configured as SPI master by setting the master bit USIMST and clearing the I2C bit USII2C. Since the master provides the clock to the slave(s) an appropriate clock source needs to be selected and SCLK configured as output. When USIPE5 = 1, SCLK is automatically configured as an output. When USIIFG = 0 and USICNTx > 0, clock generation is enabled and the master will begin clocking in/out data using USISR. Received data must be read from the shift register before new data is written into it for transmission. In a typical application, the USI software will read received data from USISR, write new data to be transmitted to USISR, and enable the module for the next transfer by writing the number of bits to be transferred to USICNTx. 14.2.3.2 SPI Slave Mode The USI module is configured as SPI slave by clearing the USIMST and the USII2C bits. In this mode, when USIPE5 = 1 SCLK is automatically configured as an input and the USI receives the clock externally from the master. If the USI is to transmit data, the shift register must be loaded with the data before the master provides the first clock edge. The output must be enabled by setting USIOE. When USICKPH = 1, the MSB will be visible on SDO immediately after loading the shift register. The SDO pin can be disabled by clearing the USIOE bit. This is useful if the slave is not addressed in an environment with multiple slaves on the bus. Once all bits are received, the data must be read from USISR and new data loaded into USISR before the next clock edge from the master. In a typical application, after receiving data, the USI software will read the USISR register, write new data to USISR to be transmitted, and enable the USI module for the next transfer by writing the number of bits to be transferred to USICNTx. 400 Universal Serial Interface (USI) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USI Operation 14.2.3.3 USISR Operation The 16-bit USISR is made up of two 8-bit registers, USISRL and USISRH. Control bit USI16B selects the number of bits of USISR that are used for data transmit and receive. When USI16B = 0, only the lower 8 bits, USISRL, are used. To transfer < 8 bits, the data must be loaded into USISRL such that unused bits are not shifted out. The data must be MSB- or LSB-aligned depending on USILSB. Figure 14-4 shows an example of 7-bit data handling. 7-bit SPI Mode, MSB first Transmit data in memory 7-bit SPI Mode, LSB first Transmit data in memory 7-bit Data 7-bit Data Shift with software TX USISRL Move TX USISRL USISRL RX RX USISRL Move Shift with software 7-bit Data Received data in memory 7-bit Data Received data in memory Figure 14-4. Data Adjustments for 7-Bit SPI Data When USI16B = 1, all 16 bits are used for data handling. When using USISR to access both USISRL and USISRH, the data needs to be properly adjusted when < 16 bits are used in the same manner as shown in Figure 14-4. 14.2.3.4 SPI Interrupts There is one interrupt vector associated with the USI module, and one interrupt flag, USIIFG, relevant for SPI operation. When USIIE and the GIE bit are set, the interrupt flag will generate an interrupt request. USIIFG is set when USICNTx becomes zero, either by counting or by directly writing 0 to the USICNTx bits. USIIFG is cleared by writing a value > 0 to the USICNTx bits when USIIFGCC = 0, or directly by software. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Universal Serial Interface (USI) 401 USI Operation www.ti.com 14.2.4 I2C Mode The USI module is configured in I2C mode when USII2C =1, USICKPL = 1, and USICKPH = 0. For I2C data compatibility, USILSB and USI16B must be cleared. USIPE6 and USIPE7 must be set to enable the SCL and SDA port functions. 14.2.4.1 I2C Master Mode To configure the USI module as an I2C master the USIMST bit must be set. In master mode, clocks are generated by the USI module and output to the SCL line while USIIFG = 0. When USIIFG = 1, the SCL will stop at the idle, or high, level. Multi-master operation is supported as described in the Arbitration section. The master supports slaves that are holding the SCL line low only when USIDIVx > 0. When USIDIVx is set to /1 clock division (USIDIVx = 0), connected slaves must not hold the SCL line low during data transmission. Otherwise the communication may fail. 14.2.4.2 I2C Slave Mode To configure the USI module as an I2C slave the USIMST bit must be cleared. In slave mode, SCL is held low if USIIFG = 1, USISTTIFG = 1 or if USICNTx = 0. USISTTIFG must be cleared by software after the slave is setup and ready to receive the slave address from a master. 14.2.4.3 I2C Transmitter In transmitter mode, data is first loaded into USISRL. The output is enabled by setting USIOE and the transmission is started by writing 8 into USICNTx. This clears USIIFG and SCL is generated in master mode or released from being held low in slave mode. After the transmission of all 8 bits, USIIFG is set, and the clock signal on SCL is stopped in master mode or held low at the next low phase in slave mode. To receive the I2C acknowledgment bit, the USIOE bit is cleared with software and USICNTx is loaded with 1. This clears USIIFG and one bit is received into USISRL. When USIIFG becomes set again, the LSB of USISRL is the received acknowledge bit and can be tested in software. ; Receive ACK/NACK BIC.B #USIOE,&USICTL0 MOV.B #01h,&USICNT TEST_USIIFG BIT.B #USIIFG,&USICTL1 JZ TEST_USIIFG BIT.B #01h,&USISRL JNZ HANDLE_NACK ...Else, handle ACK ; SDA input ; USICNTx = 1 ; Test USIIFG ; Test received ACK bit ; Handle if NACK 402 Universal Serial Interface (USI) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USI Operation 14.2.4.4 I2C Receiver In I2C receiver mode the output must be disabled by clearing USIOE and the USI module is prepared for reception by writing 8 into USICNTx. This clears USIIFG and SCL is generated in master mode or released from being held low in slave mode. The USIIFG bit will be set after 8 clocks. This stops the clock signal on SCL in master mode or holds SCL low at the next low phase in slave mode. To transmit an acknowledge or no-acknowledge bit, the MSB of the shift register is loaded with 0 or 1, the USIOE bit is set with software to enable the output, and 1 is written to the USICNTx bits. As soon as the MSB bit is shifted out, USIIFG will be become set and the module can be prepared for the reception of the next I2C data byte. ; Generate ACK BIS.B #USIOE,&USICTL0 MOV.B #00h,&USISRL MOV.B #01h,&USICNT TEST_USIIFG BIT.B #USIIFG,&USICTL1 JZ TEST_USIIFG ...continue... ; SDA output ; MSB = 0 ; USICNTx = 1 ; Test USIIFG ; Generate NACK BIS.B #USIOE,&USICTL0 MOV.B #0FFh,&USISRL MOV.B #01h,&USICNT TEST_USIIFG BIT.B #USIIFG,&USICTL1 JZ TEST_USIIFG ...continue... ; SDA output ; MSB = 1 ; USICNTx = 1 ; Test USIIFG 14.2.4.5 START Condition A START condition is a high-to-low transition on SDA while SCL is high. The START condition can be generated by setting the MSB of the shift register to 0. Setting the USIGE and USIOE bits makes the output latch transparent and the MSB of the shift register is immediately presented to SDA and pulls the line low. Clearing USIGE resumes the clocked-latch function and holds the 0 on SDA until data is shifted out with SCL. ; Generate START MOV.B #000h,&USISRL BIS.B #USIGE+USIOE,&USICTL0 BIC.B #USIGE,&USICTL0 ...continue... ; MSB = 0 ; Latch/SDA output enabled ; Latch disabled 14.2.4.6 STOP Condition A STOP condition is a low-to-high transition on SDA while SCL is high. To finish the acknowledgment bit and pull SDA low to prepare the STOP condition generation requires clearing the MSB in the shift register and loading 1 into USICNTx. This will generate a low pulse on SCL and during the low phase SDA is pulled low. SCL stops in the idle, or high, state since the module is in master mode. To generate the lowto-high transition, the MSB is set in the shift register and USICNTx is loaded with 1. Setting the USIGE and USIOE bits makes the output latch transparent and the MSB of USISRL releases SDA to the idle state. Clearing USIGE stores the MSB in the output latch and the output is disabled by clearing USIOE. SDA remains high until a START condition is generated because of the external pullup. ; Generate STOP BIS.B #USIOE,&USICTL0 ; SDA=output MOV.B #000h,&USISRL ; MSB = 0 MOV.B #001h,&USICNT ; USICNT = 1 for one clock TEST_USIIFG BIT.B #USIIFG,&USICTL1 ; Test USIIFG JZ test_USIIFG ; MOV.B #0FFh,&USISRL ; USISRL = 1 to drive SDA high BIS.B #USIGE,&USICTL0 ; Transparent latch enabled BIC.B #USIGE+USIOE,&USICTL; Latch/SDA output disabled ...continue... SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Universal Serial Interface (USI) 403 USI Operation www.ti.com 14.2.4.7 Releasing SCL Setting the USISCLREL bit will release SCL if it is being held low by the USI module without requiring USIIFG to be cleared. The USISCLREL bit will be cleared automatically if a START condition is received and the SCL line will be held low on the next clock. In slave operation this bit should be used to prevent SCL from being held low when the slave has detected that it was not addressed by the master. On the next START condition USISCLREL will be cleared and the USISTTIFG will be set. 14.2.4.8 Arbitration The USI module can detect a lost arbitration condition in multi-master I2C systems. The I2C arbitration procedure uses the data presented on SDA by the competing transmitters. The first master transmitter that generates a logic high loses arbitration to the opposing master generating a logic low. The loss of arbitration is detected in the USI module by comparing the value presented to the bus and the value read from the bus. If the values are not equal arbitration is lost and the arbitration lost flag, USIAL, is set. This also clears the output enable bit USIOE and the USI module no longer drives the bus. In this case, user software must check the USIAL flag together with USIIFG and configure the USI to slave receiver when arbitration is lost. The USIAL flag must be cleared by software. To prevent other faster masters from generating clocks during the arbitration procedure SCL is held low if another master on the bus drives SCL low and USIIFG or USISTTIFG is set, or if USICNTx = 0. 14.2.4.9 I2C Interrupts There is one interrupt vector associated with the USI module with two interrupt flags relevant for I2C operation, USIIFG and USISTTIFG. Each interrupt flag has its own interrupt enable bit, USIIE and USISTTIE. When an interrupt is enabled, and the GIE bit is set, a set interrupt flag will generate an interrupt request. USIIFG is set when USICNTx becomes zero, either by counting or by directly writing 0 to the USICNTx bits. USIIFG is cleared by writing a value > 0 to the USICNTx bits when USIIFGCC = 0, or directly by software. USISTTIFG is set when a START condition is detected. The USISTTIFG flag must be cleared by software. The reception of a STOP condition is indicated with the USISTP flag but there is no interrupt function associated with the USISTP flag. USISTP is cleared by writing a value > 0 to the USICNTx bits when USIIFGCC = 0 or directly by software. 404 Universal Serial Interface (USI) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 14.3 USI Registers The USI registers are listed in Table 14-1. Register USI control register 0 USI control register 1 USI clock control USI bit counter USI low byte shift register USI high byte shift register Table 14-1. USI Registers Short Form USICTL0 USICTL1 USICKCTL USICNT USISRL USISRH Register Type Read/write Read/write Read/write Read/write Read/write Read/write Address 078h 079h 07Ah 07Bh 07Ch 07Dh USI Registers Initial State 01h with PUC 01h with PUC Reset with PUC Reset with PUC Unchanged Unchanged The USI registers can be accessed with word instructions as shown in Table 14-2. Table 14-2. Word Access to USI Registers Register USI control register USI clock and counter control register USI shift register Short Form USICTL USICCTL USISR High-Byte Register Low-Byte Register USICTL1 USICTL0 USICNT USICKCTL USISRH USISRL Address 078h 07Ah 07Ch SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Universal Serial Interface (USI) 405 USI Registers 14.3.1 USICTL0, USI Control Register 0 www.ti.com 7 USIPE7 rw-0 USIPE7 USIPE6 USIPE5 USILSB USIMST USIGE USIOE USISWRST 6 USIPE6 rw-0 5 USIPE5 rw-0 4 USILSB rw-0 3 USIMST rw-0 2 USIGE rw-0 1 USIOE rw-0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 USI SDI/SDA port enable. Input in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled USI SDO/SCL port enable. Output in SPI mode, input or open drain output in I2C mode. 0 USI function disabled 1 USI function enabled USI SCLK port enable. Input in SPI slave mode, or I2C mode, output in SPI master mode. 0 USI function disabled 1 USI function enabled LSB first select. This bit controls the direction of the receive and transmit shift register. 0 MSB first 1 LSB first Master select 0 Slave mode 1 Master mode Output latch control 0 Output latch enable depends on shift clock 1 Output latch always enabled and transparent Data output enable 0 Output disabled 1 Output enabled USI software reset 0 USI released for operation. 1 USI logic held in reset state. 0 USISWRST rw-1 406 Universal Serial Interface (USI) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 14.3.2 USICTL1, USI Control Register 1 USI Registers 7 USICKPH rw-0 USICKPH USII2C USISTTIE USIIE USIAL USISTP USISTTIFG USIIFG 6 USII2C rw-0 5 USISTTIE rw-0 4 USIIE rw-0 3 USIAL rw-0 2 USISTP rw-0 1 USISTTIFG rw-0 0 USIIFG rw-1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Clock phase select 0 Data is changed on the first SCLK edge and captured on the following edge. 1 Data is captured on the first SCLK edge and changed on the following edge. I2C mode enable 0 I2C mode disabled 1 I2C mode enabled START condition interrupt-enable 0 Interrupt on START condition disabled 1 Interrupt on START condition enabled USI counter interrupt enable 0 Interrupt disabled 1 Interrupt enabled Arbitration lost 0 No arbitration lost condition 1 Arbitration lost STOP condition received. USISTP is automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No STOP condition received 1 STOP condition received START condition interrupt flag 0 No START condition received. No interrupt pending. 1 START condition received. Interrupt pending. USI counter interrupt flag. Set when the USICNTx = 0. Automatically cleared if USICNTx is loaded with a value > 0 when USIIFGCC = 0. 0 No interrupt pending 1 Interrupt pending SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Universal Serial Interface (USI) 407 USI Registers 14.3.3 USICKCTL, USI Clock Control Register 7 6 5 USIDIVx rw-0 rw-0 rw-0 4 3 2 USISSELx rw-0 rw-0 rw-0 USIDIVx USISSELx USICKPL USISWCLK Bits 7-5 Bits 4-2 Bit 1 Bit 0 Clock divider select 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 Clock source select. Not used in slave mode. 000 SCLK (Not used in SPI mode) 001 ACLK 010 SMCLK 011 SMCLK 100 USISWCLK bit 101 TACCR0 110 TACCR1 111 TACCR2 (Reserved on MSP430F20xx devices) Clock polarity select 0 Inactive state is low 1 Inactive state is high Software clock 0 Input clock is low 1 Input clock is high www.ti.com 1 USICKPL rw-0 0 USISWCLK rw-0 14.3.4 USICNT, USI Bit Counter Register 7 USISCLREL rw-0 USISCLREL USI16B USIIFGCC USICNTx 6 5 4 3 2 1 0 USI16B USIIFGCC USICNTx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit 7 Bit 6 Bit 5 Bits 4-0 SCL release. The SCL line is released from low to idle. USISCLREL is cleared if a START condition is detected. 0 SCL line is held low if USIIFG is set 1 SCL line is released 16-bit shift register enable 0 8-bit shift register mode. Low byte register USISRL is used. 1 16-bit shift register mode. Both high and low byte registers USISRL and USISRH are used. USISR addresses all 16 bits simultaneously. USI interrupt flag clear control. When USIIFGCC = 1 the USIIFG will not be cleared automatically when USICNTx is written with a value > 0. 0 USIIFG automatically cleared on USICNTx update 1 USIIFG is not cleared automatically USI bit count. The USICNTx bits set the number of bits to be received or transmitted. 408 Universal Serial Interface (USI) SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 14.3.5 USISRL, USI Low Byte Shift Register 7 6 5 4 3 2 USISRLx rw rw rw rw rw rw USISRLx Bits 7-0 Contents of the USI low byte shift register 14.3.6 USISRH, USI High Byte Shift Register 7 rw USISRHx 6 rw Bits 7-0 5 4 3 2 USISRHx rw rw rw rw Contents of the USI high byte shift register. Ignored when USI16B = 0. USI Registers 1 0 rw rw 1 0 rw rw SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Universal Serial Interface (USI) 409 Chapter 15 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. Topic ........................................................................................................................... Page 15.1 USCI Overview ................................................................................................ 411 15.2 USCI Introduction: UART Mode ......................................................................... 411 15.3 USCI Operation: UART Mode ............................................................................. 413 15.4 USCI Registers: UART Mode ............................................................................. 428 410 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Overview 15.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers. For example, if one device has two USCI_A modules, they are named USCI_A0 and USCI_A1. See the device-specific data sheet to determine which USCI modules, if any, are implemented on which devices. The USCI_Ax modules support: • UART mode • Pulse shaping for IrDA communications • Automatic baud rate detection for LIN communications • SPI mode The USCI_Bx modules support: • I2C mode • SPI mode 15.2 USCI Introduction: UART Mode In asynchronous mode, the USCI_Ax modules connect the MSP430 to an external system via two external pins, UCAxRXD and UCAxTXD. UART mode is selected when the UCSYNC bit is cleared. UART mode features include: • 7- or 8-bit data with odd, even, or non-parity • Independent transmit and receive shift registers • Separate transmit and receive buffer registers • LSB-first or MSB-first data transmit and receive • Built-in idle-line and address-bit communication protocols for multiprocessor systems • Receiver start-edge detection for auto-wake up from LPMx modes • Programmable baud rate with modulation for fractional baud rate support • Status flags for error detection and suppression • Status flags for address detection • Independent interrupt capability for receive and transmit Figure 15-1 shows the USCI_Ax when configured for UART mode. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 411 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Introduction: UART Mode www.ti.com UCMODEx UCSPB UCDORM 2 Receive State Machine UCRXEIE UCRXBRKIE Error Flags Set Flags Set RXIFG UCRXERR UCPE UCFE UCOE Set UC0RXIFG Set UCBRK Set UCADDR/UCIDLE Receive Buffer UC 0RXBUF Receive Shift Register UCIRRXPL UCIRRXFLx UCIRRXFE UCIREN 6 UCLISTEN 1 IrDA Decoder 1 0 UC0RX 0 0 1 UCPEN UCPAR UCMSB UC7BIT UCABEN UCSSELx Receive Baudrate Generator UC0CLK ACLK SMCLK UC0BRx 00 01 10 BRCLK 16 Prescaler/Divider SMCLK 11 Modulator 4 3 UCBRFx UCBRSx UCOS16 Receive Clock Transmit Clock UCPEN UCPAR UCMSB UC7BIT UCIREN Transmit Shift Register 0 Transmit Buffer UC 0TXBUF 1 IrDA Encoder 6 UCIRTXPLx Transmit State Machine Set UC0TXIFG UCTXBRK UCTXADDR 2 UCMODEx UCSPB Figure 15-1. USCI_Ax Block Diagram: UART Mode (UCSYNC = 0) UC0TX 412 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: UART Mode 15.3 USCI Operation: UART Mode In UART mode, the USCI transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USCI. The transmit and receive functions use the same baud rate frequency. 15.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition. When set, the UCSWRST bit resets the UCAxRXIE, UCAxTXIE, UCAxRXIFG, UCRXERR, UCBRK, UCPE, UCOE, UCFE, UCSTOE and UCBTOE bits and sets the UCAxTXIFG bit. Clearing UCSWRST releases the USCI for operation. NOTE: Initializing or Re-Configuring the USCI Module The recommended USCI initialization/re-configuration process is: 1. Set UCSWRST (BIS.B #UCSWRST,&UCAxCTL1) 2. Initialize all USCI registers with UCSWRST = 1 (including UCAxCTL1) 3. Configure ports. 4. Clear UCSWRST via software (BIC.B #UCSWRST,&UCAxCTL1) 5. Enable interrupts (optional) via UCAxRXIE and/or UCAxTXIE 15.3.2 Character Format The UART character format, shown in Figure 15-2, consists of a start bit, seven or eight data bits, an even/odd/no parity bit, an address bit (address-bit mode), and one or two stop bits. The UCMSB bit controls the direction of the transfer and selects LSB or MSB first. LSB-first is typically required for UART communication. ST D0 D6 D7 AD PA SP SP Mark Space [Optional Bit, Condition] [2nd Stop Bit, UCSPB = 1] [Parity Bit, UCPEN = 1] [Address Bit, UCMODEx = 10] [8th Data Bit, UC7BIT = 0] Figure 15-2. Character Format 15.3.3 Asynchronous Communication Formats When two devices communicate asynchronously, no multiprocessor format is required for the protocol. When three or more devices communicate, the USCI supports the idle-line and address-bit multiprocessor communication formats. 15.3.3.1 Idle-Line Multiprocessor Format When UCMODEx = 01, the idle-line multiprocessor format is selected. Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 15-3. An idle receive line is detectedwhen 10 or more continuous ones (marks) are received after the one or two stop bits of a character. The baud rate generator is switched off after reception of an idle line until the next start edge is detected. When an idle line is detected the UCIDLE bit is set. The first character received after an idle period is an address character. The UCIDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 413 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: UART Mode UCAxTXD/RXD UCAxTXD/RXD Expanded Blocks of Characters Idle Periods of 10 Bits or More www.ti.com UCAxTXD/RXD ST Address SP ST Data SP ST Data SP First Character Within Block Is Address. It Follows Idle Period of 10 Bits or More Character Within Block Character Within Block Idle Period Less Than 10 Bits Figure 15-3. Idle-Line Format The UCDORM bit is used to control data reception in the idle-line multiprocessor format. When UCDORM = 1, all non-address characters are assembled but not transferred into the UCAxRXBUF, and interrupts are not generated. When an address character is received, the character is transferred into UCAxRXBUF, UCAxRXIFG is set, and any applicable error flag is set when UCRXEIE = 1. When UCRXEIE = 0 and an address character is received but has a framing error or parity error, the character is not transferred into UCAxRXBUF and UCAxRXIFG is not set. If an address is received, user software can validate the address and must reset UCDORM to continue receiving data. If UCDORM remains set, only address characters will be received. When UCDORM is cleared during the reception of a character the receive interrupt flag will be set after the reception completed. The UCDORM bit is not modified by the USCI hardware automatically. For address transmission in idle-line multiprocessor format, a precise idle period can be generated by the USCI to generate address character identifiers on UCAxTXD. The double-buffered UCTXADDR flag indicates if the next character loaded into UCAxTXBUF is preceded by an idle line of 11 bits. UCTXADDR is automatically cleared when the start bit is generated. 15.3.3.2 Transmitting an Idle Frame The following procedure sends out an idle frame to indicate an address character followed by associated data: 1. Set UCTXADDR, then write the address character to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). This generates an idle period of exactly 11 bits followed by the address character. UCTXADDR is reset automatically when the address character is transferred from UCAxTXBUF into the shift register. 2. Write desired data characters to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). The data written to UCAxTXBUF is transferred to the shift register and transmitted as soon as the shift register is ready for new data. The idle-line time must not be exceeded between address and data transmission or between data transmissions. Otherwise, the transmitted data will be misinterpreted as an address. 414 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: UART Mode 15.3.3.3 Address-Bit Multiprocessor Format When UCMODEx = 10, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 15-4. The first character in a block of characters carries a set address bit which indicates that the character is an address. The USCI UCADDR bit is set when a received character has its address bit set and is transferred to UCAxRXBUF. The UCDORM bit is used to control data reception in the address-bit multiprocessor format. When UCDORM is set, data characters with address bit = 0 are assembled by the receiver but are not transferred to UCAxRXBUF and no interrupts are generated. When a character containing a set address bit is received, the character is transferred into UCAxRXBUF, UCAxRXIFG is set, and any applicable error flag is set when UCRXEIE = 1. When UCRXEIE = 0 and a character containing a set address bit is received, but has a framing error or parity error, the character is not transferred into UCAxRXBUF and UCAxRXIFG is not set. If an address is received, user software can validate the address and must reset UCDORM to continue receiving data. If UCDORM remains set, only address characters with address bit = 1 will be received. The UCDORM bit is not modified by the USCI hardware automatically. When UCDORM = 0 all received characters will set the receive interrupt flag UCAxRXIFG. If UCDORM is cleared during the reception of a character the receive interrupt flag will be set after the reception is completed. For address transmission in address-bit multiprocessor mode, the address bit of a character is controlled by the UCTXADDR bit. The value of the UCTXADDR bit is loaded into the address bit of the character transferred from UCAxTXBUF to the transmit shift register. UCTXADDR is automatically cleared when the start bit is generated. Blocks of Characters UCAxTXD/UCAxRXD UCAxTXD/UCAxRXD Expanded Idle Periods of No Significance UCAxTXD/UCAxRXD ST Address 1 SP ST Data 0 SP ST Data 0 SP First Character Within Block Is an Address. AD Bit Is 1 AD Bit Is 0 for Data Within Block. Idle Time Is of No Significance Figure 15-4. Address-Bit Multiprocessor Format 15.3.3.4 Break Reception and Generation When UCMODEx = 00, 01, or 10 the receiver detects a break when all data, parity, and stop bits are low, regardless of the parity, address mode, or other character settings. When a break is detected, the UCBRK bit is set. If the break interrupt enable bit, UCBRKIE, is set, the receive interrupt flag UCAxRXIFG will also be set. In this case, the value in UCAxRXBUF is 0h since all data bits were zero. To transmit a break set the UCTXBRK bit, then write 0h to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). This generates a break with all bits low. UCTXBRK is automatically cleared when the start bit is generated. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 415 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: UART Mode www.ti.com 15.3.4 Automatic Baud Rate Detection When UCMODEx = 11 UART mode with automatic baud rate detection is selected. For automatic baud rate detection, a data frame is preceded by a synchronization sequence that consists of a break and a synch field. A break is detected when 11 or more continuous zeros (spaces) are received. If the length of the break exceeds 22 bit times the break timeout error flag UCBTOE is set. The synch field follows the break as shown in Figure 15-5. Break Delimiter Synch Figure 15-5. Auto Baud Rate Detection - Break/Synch Sequence For LIN conformance the character format should be set to 8 data bits, LSB first, no parity and one stop bit. No address bit is available. The synch field consists of the data 055h inside a byte field as shown in Figure 15-6. The synchronization is based on the time measurement between the first falling edge and the last falling edge of the pattern. The transmit baud rate generator is used for the measurement if automatic baud rate detection is enabled by setting UCABDEN. Otherwise, the pattern is received but not measured. The result of the measurement is transferred into the baud rate control registers UCAxBR0, UCAxBR1, and UCAxMCTL. If the length of the synch field exceeds the measurable time the synch timeout error flag UCSTOE is set. Synch 8 Bit Times Start Bit 0 1 2 3 4 5 6 7 Stop Bit Figure 15-6. Auto Baud Rate Detection - Synch Field The UCDORM bit is used to control data reception in this mode. When UCDORM is set, all characters are received but not transferred into the UCAxRXBUF, and interrupts are not generated. When a break/synch field is detected the UCBRK flag is set. The character following the break/synch field is transferred into UCAxRXBUF and the UCAxRXIFG interrupt flag is set. Any applicable error flag is also set. If the UCBRKIE bit is set, reception of the break/synch sets the UCAxRXIFG. The UCBRK bit is reset by user software or by reading the receive buffer UCAxRXBUF. When a break/synch field is received, user software must reset UCDORM to continue receiving data. If UCDORM remains set, only the character after the next reception of a break/synch field will be received. The UCDORM bit is not modified by the USCI hardware automatically. When UCDORM = 0 all received characters will set the receive interrupt flag UCAxRXIFG. If UCDORM is cleared during the reception of a character the receive interrupt flag will be set after the reception is complete. The automatic baud rate detection mode can be used in a full-duplex communication system with some restrictions. The USCI can not transmit data while receiving the break/sync field and if a 0h byte with framing error is received any data transmitted during this time gets corrupted. The latter case can be discovered by checking the received data and the UCFE bit. 416 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: UART Mode 15.3.4.1 Transmitting a Break/Synch Field The following procedure transmits a break/synch field: • Set UCTXBRK with UMODEx = 11. • Write 055h to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). This generates a break field of 13 bits followed by a break delimiter and the synch character. The length of the break delimiter is controlled with the UCDELIMx bits. UCTXBRK is reset automatically when the synch character is transferred from UCAxTXBUF into the shift register. • Write desired data characters to UCAxTXBUF. UCAxTXBUF must be ready for new data (UCAxTXIFG = 1). The data written to UCAxTXBUF is transferred to the shift register and transmitted as soon as the shift register is ready for new data. 15.3.5 IrDA Encoding and Decoding When UCIREN is set the IrDA encoder and decoder are enabled and provide hardware bit shaping for IrDA communication. 15.3.5.1 IrDA Encoding The encoder sends a pulse for every zero bit in the transmit bit stream coming from the UART as shown in Figure 15-7. The pulse duration is defined by UCIRTXPLx bits specifying the number of half clock periods of the clock selected by UCIRTXCLK. Start Bit Data Bits Stop Bit UART IrDA Figure 15-7. UART vs IrDA Data Format To set the pulse time of 3/16 bit period required by the IrDA standard the BITCLK16 clock is selected with UCIRTXCLK = 1 and the pulse length is set to 6 half clock cycles with UCIRTXPLx = 6 – 1 = 5. When UCIRTXCLK = 0, the pulse length tPULSE is based on BRCLK and is calculated as follows: UCIRTXPLx = tPULSE × 2 × fBRCLK − 1 When the pulse length is based on BRCLK the prescaler UCBRx must to be set to a value greater or equal to 5. 15.3.5.2 IrDA Decoding The decoder detects high pulses when UCIRRXPL = 0. Otherwise it detects low pulses. In addition to the analog deglitch filter an additional programmable digital filter stage can be enabled by setting UCIRRXFE. When UCIRRXFE is set, only pulses longer than the programmed filter length are passed. Shorter pulses are discarded. The equation to program the filter length UCIRRXFLx is: UCIRRXFLx = (tPULSE − tWAKE) × 2 × fBRCLK − 4 Where, tPULSE = Minimum receive pulse width tWAKE = Wake time from any low power mode. Zero when MSP430 is in active mode. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 417 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: UART Mode www.ti.com 15.3.6 Automatic Error Detection Glitch suppression prevents the USCI from being accidentally started. Any pulse on UCAxRXD shorter than the deglitch time tτ (approximately 150 ns) will be ignored. See the device-specific data sheet for parameters. When a low period on UCAxRXD exceeds tτ a majority vote is taken for the start bit. If the majority vote fails to detect a valid start bit the USCI halts character reception and waits for the next low period on UCAxRXD. The majority vote is also used for each bit in a character to prevent bit errors. The USCI module automatically detects framing errors, parity errors, overrun errors, and break conditions when receiving characters. The bits UCFE, UCPE, UCOE, and UCBRK are set when their respective condition is detected. When the error flags UCFE, UCPE or UCOE are set, UCRXERR is also set. The error conditions are described in Table 15-1. Error Condition Framing error Parity error Receive overrun Break condition Error Flag UCFE UCPE UCOE UCBRK Table 15-1. Receive Error Conditions Description A framing error occurs when a low stop bit is detected. When two stop bits are used, both stop bits are checked for framing error. When a framing error is detected, the UCFE bit is set. A parity error is a mismatch between the number of 1s in a character and the value of the parity bit. When an address bit is included in the character, it is included in the parity calculation. When a parity error is detected, the UCPE bit is set. An overrun error occurs when a character is loaded into UCAxRXBUF before the prior character has been read. When an overrun occurs, the UCOE bit is set. When not using automatic baud rate detection, a break is detected when all data, parity, and stop bits are low. When a break condition is detected, the UCBRK bit is set. A break condition can also set the interrupt flag UCAxRXIFG if the break interrupt enable UCBRKIE bit is set. When UCRXEIE = 0 and a framing error, or parity error is detected, no character is received into UCAxRXBUF. When UCRXEIE = 1, characters are received into UCAxRXBUF and any applicable error bit is set. When UCFE, UCPE, UCOE, UCBRK, or UCRXERR is set, the bit remains set until user software resets it or UCAxRXBUF is read. UCOE must be reset by reading UCAxRXBUF. Otherwise it will not function properly. To detect overflows reliably, the following flow is recommended. After a character is received and UCAxRXIFG is set, first read UCAxSTAT to check the error flags including the overflow flag UCOE. Read UCAxRXBUF next. This will clear all error flags except UCOE, if UCAxRXBUF was overwritten between the read access to UCAxSTAT and to UCAxRXBUF. The UCOE flag should be checked after reading UCAxRXBUF to detect this condition. Note that, in this case, the UCRXERR flag is not set. 15.3.7 USCI Receive Enable The USCI module is enabled by clearing the UCSWRST bit and the receiver is ready and in an idle state. The receive baud rate generator is in a ready state but is not clocked nor producing any clocks. The falling edge of the start bit enables the baud rate generator and the UART state machine checks for a valid start bit. If no valid start bit is detected the UART state machine returns to its idle state and the baud rate generator is turned off again. If a valid start bit is detected a character will be received. When the idle-line multiprocessor mode is selected with UCMODEx = 01 the UART state machine checks for an idle line after receiving a character. If a start bit is detected another character is received. Otherwise the UCIDLE flag is set after 10 ones are received and the UART state machine returns to its idle state and the baud rate generator is turned off. 418 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: UART Mode 15.3.7.1 Receive Data Glitch Suppression Glitch suppression prevents the USCI from being accidentally started. Any glitch on UCAxRXD shorter than the deglitch time tτ (approximately 150 ns) will be ignored by the USCI and further action will be initiated as shown in Figure 15-8. See the device-specific data sheet for parameters. URXDx URXS tτ Figure 15-8. Glitch Suppression, USCI Receive Not Started When a glitch is longer than tτ or a valid start bit occurs on UCAxRXD, the USCI receive operation is started and a majority vote is taken as shown in Figure 15-9. If the majority vote fails to detect a start bit the USCI halts character reception. Majority Vote Taken URXDx URXS tτ Figure 15-9. Glitch Suppression, USCI Activated 15.3.8 USCI Transmit Enable The USCI module is enabled by clearing the UCSWRST bit and the transmitter is ready and in an idle state. The transmit baud rate generator is ready but is not clocked nor producing any clocks. A transmission is initiated by writing data to UCAxTXBUF. When this occurs, the baud rate generator is enabled and the data in UCAxTXBUF is moved to the transmit shift register on the next BITCLK after the transmit shift register is empty. UCAxTXIFG is set when new data can be written into UCAxTXBUF. Transmission continues as long as new data is available in UCAxTXBUF at the end of the previous byte transmission. If new data is not in UCAxTXBUF when the previous byte has transmitted, the transmitter returns to its idle state and the baud rate generator is turned off. 15.3.9 UART Baud Rate Generation The USCI baud rate generator is capable of producing standard baud rates from non-standard source frequencies. It provides two modes of operation selected by the UCOS16 bit. 15.3.9.1 Low-Frequency Baud Rate Generation The low-frequency mode is selected when UCOS16 = 0. This mode allows generation of baud rates from low frequency clock sources (for example, 9600 baud from a 32768-Hz crystal). By using a lower input frequency the power consumption of the module is reduced. Using this mode with higher frequencies and higher prescaler settings will cause the majority votes to be taken in an increasingly smaller window and thus decrease the benefit of the majority vote. In low-frequency mode the baud rate generator uses one prescaler and one modulator to generate bit clock timing. This combination supports fractional divisors for baud rate generation. In this mode, the maximum USCI baud rate is one-third the UART source clock frequency BRCLK. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 419 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: UART Mode www.ti.com Timing for each bit is shown in Figure 15-10. For each bit received, a majority vote is taken to determine the bit value. These samples occur at the N/2 - 1/2, N/2, and N/2 + 1/2 BRCLK periods, where N is the number of BRCLKs per BITCLK. Bit Start Majority Vote: (m= 0) (m= 1) BRCLK Counter N/2 N/2−1 N/2−2 1 N/2 N/2−1 N/2−2 1 0 N/2 N/2−1 1 N/2 N/2−1 1 0 N/2 BITCLK INT(N/2) + m(= 0) INT(N/2) + m(= 1) NEVEN: INT(N/2) NODD : INT(N/2) + R(= 1) m: corresponding modulation bit R: Remainder from N/2 division Bit Period Figure 15-10. BITCLK Baud Rate Timing With UCOS16 = 0 Modulation is based on the UCBRSx setting as shown in Table 15-2. A 1 in the table indicates that m = 1 and the corresponding BITCLK period is one BRCLK period longer than a BITCLK period with m = 0. The modulation wraps around after 8 bits but restarts with each new start bit. UCBRSx 0 1 2 3 4 5 6 7 Bit 0 (Start Bit) 0 0 0 0 0 0 0 0 Table 15-2. BITCLK Modulation Pattern Bit 1 0 1 1 1 1 1 1 1 Bit 2 0 0 0 0 0 1 1 1 Bit 3 0 0 0 1 1 1 1 1 Bit 4 0 0 0 0 0 0 0 1 Bit 5 0 0 1 1 1 1 1 1 Bit 6 0 0 0 0 0 0 1 1 Bit 7 0 0 0 0 1 1 1 1 15.3.9.2 Oversampling Baud Rate Generation The oversampling mode is selected when UCOS16 = 1. This mode supports sampling a UART bit stream with higher input clock frequencies. This results in majority votes that are always 1/16 of a bit clock period apart. This mode also easily supports IrDA pulses with a 3/16 bit-time when the IrDA encoder and decoder are enabled. This mode uses one prescaler and one modulator to generate the BITCLK16 clock that is 16 times faster than the BITCLK. An additional divider and modulator stage generates BITCLK from BITCLK16. This combination supports fractional divisions of both BITCLK16 and BITCLK for baud rate generation. In this mode, the maximum USCI baud rate is 1/16 the UART source clock frequency BRCLK. When UCBRx is set to 0 or 1 the first prescaler and modulator stage is bypassed and BRCLK is equal to BITCLK16. Modulation for BITCLK16 is based on the UCBRFx setting as shown in Table 15-3. A 1 in the table indicates that the corresponding BITCLK16 period is one BRCLK period longer than the periods m=0. The modulation restarts with each new bit timing. Modulation for BITCLK is based on the UCBRSx setting as shown in Table 15-2 as previously described. 420 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: UART Mode Table 15-3. BITCLK16 Modulation Pattern No. of BITCLK16 Clocks After Last Falling BITCLK Edge UCBRFx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 00h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 02h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 03h 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 04h 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 05h 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 06h 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 07h 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 08h 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 09h 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0Ah 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0Bh 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0Ch 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0Dh 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0Eh 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0Fh 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15.3.10 Setting a Baud Rate For a given BRCLK clock source, the baud rate used determines the required division factor N: N = fBRCLK Baud rate The division factor N is often a non-integer value thus at least one divider and one modulator stage is used to meet the factor as closely as possible. If N is equal or greater than 16 the oversampling baud rate generation mode can be chosen by setting UCOS16. 15.3.10.1 Low-Frequency Baud Rate Mode Setting In the low-frequency mode, the integer portion of the divisor is realized by the prescaler: UCBRx = INT(N) and the fractional portion is realized by the modulator with the following nominal formula: UCBRSx = round( ( N – INT(N) ) × 8 ) Incrementing or decrementing the UCBRSx setting by one count may give a lower maximum bit error for any given bit. To determine if this is the case, a detailed error calculation must be performed for each bit for each UCBRSx setting. 15.3.10.2 Oversampling Baud Rate Mode Setting In the oversampling mode the prescaler is set to: UCBRx = INT( N ) 16 and the first stage modulator is set to: UCBRFx = round ( ( N – INT( N ) ) × 16 ) 16 16 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 421 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: UART Mode www.ti.com When greater accuracy is required, the UCBRSx modulator can also be implemented with values from 0 to 7. To find the setting that gives the lowest maximum bit error rate for any given bit, a detailed error calculation must be performed for all settings of UCBRSx from 0 to 7 with the initial UCBRFx setting and with the UCBRFx setting incremented and decremented by one. 15.3.11 Transmit Bit Timing The timing for each character is the sum of the individual bit timings. Using the modulation features of the baud rate generator reduces the cumulative bit error. The individual bit error can be calculated using the following steps. 15.3.11.1 Low-Frequency Baud Rate Mode Bit Timing In low-frequency mode, calculate the length of bit i Tbit,TX[i] based on the UCBRx and UCBRSx settings: Tbit,TX[i] = 1 fBRCLK (UCBRx + mUCBRSx[i]) Where, mUCBRSx[i] = Modulation of bit i from Table 15-2 15.3.11.2 Oversampling Baud Rate Mode Bit Timing In oversampling baud rate mode calculate the length of bit i Tbit,TX[i] based on the baud rate generator UCBRx, UCBRFx and UCBRSx settings: Tbit,TX[i] = 1 fBRCLK å æ ç ç (16 + mUCBRSx [i]) × UCBRx + 15 ö mUCBRFx [j] ÷ ÷ çè j=0 ÷ø Where, 15 å mUCBRFx [j] j=0 = Sum of ones from the corresponding row in Table 15-3 mUCBRSx[i] = Modulation of bit i from Table 15-2 This results in an end-of-bit time tbit,TX[i] equal to the sum of all previous and the current bit times: i å tbit,TX[i] = Tbit,TX[j] j=0 To calculate bit error, this time is compared to the ideal bit time tbit,ideal,TX[i]: tbit,ideal,TX[i] = 1 Baud rate (i + 1) This results in an error normalized to one ideal bit time (1/baudrate): ErrorTX[i] = (tbit,TX[i] – tbit,ideal,TX[i]) × Baudrate × 100% 15.3.12 Receive Bit Timing Receive timing error consists of two error sources. The first is the bit-to-bit timing error similar to the transmit bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USCI module. Figure 15-11 shows the asynchronous timing errors between data on the UCAxRXD pin and the internal baud-rate clock. This results in an additional synchronization error. The synchronization error tSYNC is between -0.5 BRCLKs and +0.5 BRCLKs independent of the selected baud rate generation mode. 422 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: UART Mode i tideal BRCLK 0 1 2 t0 t1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 UCAxRXD ST D0 D1 RXD synch. ST D0 D1 tactual t0 t1 t2 Synchronization Error ± 0.5x BRCLK Sample RXD synch. Majority Vote Taken Majority Vote Taken Figure 15-11. Receive Error Majority Vote Taken The ideal sampling time is in the middle of a bit period: tbit,ideal,RX[i] = 1 Baud rate (i + 0.5) The real sampling time is equal to the sum of all previous bits according to the formulas shown in the transmit timing section, plus one half BITCLK for the current bit i, plus the synchronization error tSYNC. This results in the following for the low-frequency baud rate mode: åi-1 tbit,RX[i] = tSYNC + Tbit,RX[j] + j=0 1 fBRCLK æ ççèINT æ çè 1 2 UCBRx ö ÷ø + ö mUCBRSx [i] ÷÷ø Where, Tbit,RX[i] = 1 fBRCLK (UCBRx + mUCBRSx[i]) mUCBRSx[i] = Modulation of bit i from Table 15-2 For the oversampling baud rate mode the sampling time of bit i is calculated by: åi-1 tbit,RX[i] = tSYNC + Tbit,RX[j] + j=0 1 fBRCLK ( ) å æ ç ç 8 + mUCBRSx [i] × UCBRx + 7+mUCBRSx [i] mUCBRFx [j] ö ÷ ÷ çè j=0 ÷ø Where, Tbit,RX[i] = 1 fBRCLK å æ ç ççè (16 + mUCBRSx [i]) × UCBRx + 15 j=0 mUCBRFx [j] ö ÷ ÷÷ø 7+mUCBRSx [i] å mUCBRFx[j] j=0 = Sum of ones from columns 0 - from the corresponding row in Table 15-3 mUCBRSx[i] = Modulation of bit i from Table 15-2 This results in an error normalized to one ideal bit time (1/baudrate) according to the following formula: ErrorRX[i] = (tbit,RX[i] − tbit,ideal,RX[i]) × Baudrate × 100% SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 423 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: UART Mode www.ti.com 15.3.13 Typical Baud Rates and Errors Standard baud rate data for UCBRx, UCBRSx and UCBRFx are listed in Table 15-4 and Table 15-5 for a 32768-Hz crystal sourcing ACLK and typical SMCLK frequencies. Ensure that the selected BRCLK frequency does not exceed the device-specific maximum USCI input frequency (see the device-specific data sheet). The receive error is the accumulated time versus the ideal scanning time in the middle of each bit. The worst case error is given for the reception of an 8-bit character with parity and one stop bit including synchronization error. The transmit error is the accumulated timing error versus the ideal time of the bit period. The worst case error is given for the transmission of an 8-bit character with parity and stop bit. Table 15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 BRCLK Frequency [Hz] 32,768 32,768 32,768 32,768 1,048,576 1,048,576 1,048,576 1,048,576 1,048,576 1,048,576 1,048,576 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 4,000,000 4,000,000 4,000,000 4,000,000 4,000,000 4,000,000 4,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 12,000,000 12,000,000 12,000,000 12,000,000 Baud Rate [Baud] 1200 2400 4800 9600 9600 19200 38400 56000 115200 128000 256000 9600 19200 38400 56000 115200 128000 256000 9600 19200 38400 56000 115200 128000 256000 9600 19200 38400 56000 115200 128000 256000 9600 19200 38400 56000 UCBRx 27 13 6 3 109 54 27 18 9 8 4 104 52 26 17 8 7 3 416 208 104 71 34 31 15 833 416 208 142 69 62 31 1250 625 312 214 UCBRSx 2 6 7 3 2 5 2 6 1 1 1 1 0 0 7 6 7 7 6 3 1 4 6 2 5 2 6 3 7 4 4 2 0 0 4 2 UCBRFx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Maximum TX Error [%] -2.8 1.4 -4.8 6.0 -12.1 5.7 -21.1 15.2 -0.2 0.7 -1.1 1.0 -2.8 1.4 -3.9 1.1 -1.1 10.7 -8.9 7.5 -2.3 25.4 -0.5 0.6 -1.8 0 -1.8 0 -4.8 0.8 -7.8 6.4 -10.4 6.4 -29.6 0 -0.2 0.2 -0.2 0.5 -0.5 0.6 -0.6 1.0 -2.1 0.6 -0.8 1.6 -4.0 3.2 -0.1 0 -0.2 0.2 -0.2 0.5 -0.6 0.1 -0.6 0.8 -0.8 0 -0.8 1.6 0 0 0 0 -0.2 0 -0.3 0.2 Maximum RX Error [%] -5.9 2.0 -9.7 8.3 -13.4 19.0 -44.3 21.3 -1.0 0.8 -1.5 2.5 -5.9 2.0 -4.6 5.7 -11.5 11.3 -13.8 14.8 -13.4 38.8 -0.9 1.2 -2.6 0.9 -3.6 1.8 -8.0 3.2 -9.7 16.1 -18.0 11.6 -43.6 5.2 -0.2 0.4 -0.3 0.8 -0.9 1.2 -1.7 1.3 -2.5 3.1 -3.6 2.0 -8.4 5.2 -0.2 0.1 -0.2 0.4 -0.3 0.8 -0.7 0.8 -1.8 1.1 -1.2 1.2 -3.6 2.0 -0.05 0.05 -0.2 0 -0.2 0.2 -0.4 0.5 424 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USCI Operation: UART Mode Table 15-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 (continued) BRCLK Frequency [Hz] 12,000,000 12,000,000 12,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 Baud Rate [Baud] 115200 128000 256000 9600 19200 38400 56000 115200 128000 256000 UCBRx 104 93 46 1666 833 416 285 138 125 62 UCBRSx 1 6 7 6 2 6 6 7 0 4 UCBRFx 0 0 0 0 0 0 0 0 0 0 Maximum TX Error [%] -0.5 0.6 -0.8 0 -1.9 0 -0.05 0.05 -0.1 0.05 -0.2 0.2 -0.3 0.1 -0.7 0 0 0 -0.8 0 Maximum RX Error [%] -0.9 1.2 -1.5 0.4 -2.0 2.0 -0.05 0.1 -0.2 0.1 -0.2 0.4 -0.5 0.2 -0.8 0.6 -0.8 0 -1.2 1.2 Table 15-5. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1 BRCLK Frequency [Hz] 1,048,576 1,048,576 1,000,000 1,000,000 1,000,000 4,000,000 4,000,000 4,000,000 4,000,000 4,000,000 4,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 8,000,000 12,000,000 12,000,000 12,000,000 12,000,000 12,000,000 12,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 16,000,000 Baud Rate [Baud] 9600 19200 9600 19200 57600 9600 19200 38400 57600 115200 230400 9600 19200 38400 57600 115200 230400 460800 9600 19200 38400 57600 115200 230400 9600 19200 38400 57600 115200 230400 460800 UCBRx 6 3 6 3 1 26 13 6 4 2 1 52 26 13 8 4 2 1 78 39 19 13 6 3 104 52 26 17 8 4 2 UCBRSx 0 1 0 0 7 0 0 0 5 3 7 0 0 0 0 5 3 7 0 0 0 0 0 0 0 0 0 0 0 5 3 UCBRFx 13 6 8 4 0 1 0 8 3 2 0 1 1 0 11 3 2 0 2 1 8 0 8 4 3 1 1 6 11 3 2 Maximum TX Error [%] -2.3 0 -4.6 3.2 -1.8 0 -1.8 0 -34.4 0 0 0.9 -1.8 0 -1.8 0 -3.5 3.2 -2.1 4.8 -34.4 0 -0.4 0 0 0.9 -1.8 0 0 0.88 -3.5 3.2 -2.1 4.8 -34.4 0 0 0 0 0 -1.8 0 -1.8 0 -1.8 0 -1.8 0 0 0.2 -0.4 0 0 0.9 0 0.9 0 0.9 -3.5 3.2 -2.1 4.8 Maximum RX Error [%] -2.2 0.8 -5.0 4.7 -2.2 0.4 -2.6 0.9 -33.4 0 0 1.1 -1.9 0.2 -2.2 0.4 -1.8 6.4 -2.5 7.3 -33.4 0 -0.4 0.1 0 1.1 -1.9 0.2 0 1.6 -1.8 6.4 -2.5 7.3 -33.4 0 -0.05 0.05 0 0.2 -1.8 0.1 -1.9 0.2 -2.2 0.4 -2.6 0.9 0 0.3 -0.4 0.1 0 1.1 -0.1 1.0 0 1.6 -1.8 6.4 -2.5 7.3 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Universal Serial Communication Interface, UART Mode 425 Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: UART Mode www.ti.com 15.3.14 Using the USCI Module in UART Mode with Low Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition. After the USCI module returns to the idle condition, control of the clock source reverts to the settings of its control bits. Automatic clock activation is not provided for ACLK. When the USCI module activates an inactive clock source, the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected. For example, a timer using SMCLK will increment while the USCI module forces SMCLK active. 15.3.15 USCI Interrupts The USCI has one interrupt vector for transmission and one interrupt vector for reception. 15.3.15.1 USCI Transmit Interrupt Operation The UCAxTXIFG interrupt flag is set by the transmitter to indicate that UCAxTXBUF is ready to accept another character. An interrupt request is generated if UCAxTXIE and GIE are also set. UCAxTXIFG is automatically reset if a character is written to UCAxTXBUF. UCAxTXIFG is set after a PUC or when UCSWRST = 1. UCAxTXIE is reset after a PUC or when UCSWRST = 1. 15.3.15.2 USCI Receive Interrupt Operation The UCAxRXIFG interrupt flag is set each time a character is received and loaded into UCAxRXBUF. An interrupt request is generated if UCAxRXIE and GIE are also set. UCAxRXIFG and UCAxRXIE are reset by a system reset PUC signal or when UCSWRST = 1. UCAxRXIFG is automatically reset when UCAxRXBUF is read. Additional interrupt control features include: • When UCAxRXEIE = 0 erroneous characters will not set UCAxRXIFG. • When UCDORM = 1, non-address characters will not set UCAxRXIFG in multiprocessor modes. In plain UART mode, no characters will set UCAxRXIFG. • When UCBRKIE = 1 a break condition will set the UCBRK bit and the UCAxRXIFG flag. 15.3.15.3 USCI Interrupt Usage USCI_Ax and USCI_Bx share the same interrupt vectors. The receive interrupt flags UCAxRXIFG and UCBxRXIFG are routed to one interrupt vector, the transmit interrupt flags UCAxTXIFG and UCBxTXIFG share another interrupt vector. Example 15-1 shows an extract of an interrupt service routine to handle data receive interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode. Example 15-1. Shared Interrupt Vectors Software Example, Data Receive USCIA0_RX_USCIB0_RX_ISR BIT.B #UCA0RXIFG, &IFG2 ; USCI_A0 Receive Interrupt? JNZ USCIA0_RX_ISR USCIB0_RX_ISR? ; Read UCB0RXBUF (clears UCB0RXIFG) ... RETI USCIA0_RX_ISR ; Read UCA0RXBUF (clears UCA0RXIFG) ... RETI 426 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: UART Mode Example 15-2 shows an extract of an interrupt service routine to handle data transmit interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode. Example 15-2. Shared Interrupt Vectors Software Example, Data Transmit USCIA0_TX_USCIB0_TX_ISR BIT.B #UCA0TXIFG, &IFG2 ; USCI_A0 Transmit Interrupt? JNZ USCIA0_TX_ISR USCIB0_TX_ISR ; Write UCB0TXBUF (clears UCB0TXIFG) ... RETI USCIA0_TX_ISR ; Write UCA0TXBUF (clears UCA0TXIFG) ... RETI SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 427 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: UART Mode 15.4 USCI Registers: UART Mode The USCI registers applicable in UART mode are listed in Table 15-6 and Table 15-7. Table 15-6. USCI_A0 Control and Status Registers Register USCI_A0 control register 0 USCI_A0 control register 1 USCI_A0 Baud rate control register 0 USCI_A0 baud rate control register 1 USCI_A0 modulation control register USCI_A0 status register USCI_A0 receive buffer register USCI_A0 transmit buffer register USCI_A0 Auto baud control register USCI_A0 IrDA transmit control register USCI_A0 IrDA receive control register SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form UCA0CTL0 UCA0CTL1 UCA0BR0 UCA0BR1 UCA0MCTL UCA0STAT UCA0RXBUF UCA0TXBUF UCA0ABCTL UCA0IRTCTL UCA0IRRCTL IE2 IFG2 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Read/write Read/write Read/write Address 060h 061h 062h 063h 064h 065h 066h 067h 05Dh 05Eh 05Fh 001h 003h www.ti.com Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC NOTE: Modifying SFR bits To avoid modifying control bits of other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. Table 15-7. USCI_A1 Control and Status Registers Register USCI_A1 control register 0 USCI_A1 control register 1 USCI_A1 baud rate control register 0 USCI_A1 baud rate control register 1 USCI_A1 modulation control register USCI_A1 status register USCI_A1 receive buffer register USCI_A1 transmit buffer register USCI_A1 auto baud control register USCI_A1 IrDA transmit control register USCI_A1 IrDA receive control register USCI_A1/B1 interrupt enable register USCI_A1/B1 interrupt flag register Short Form UCA1CTL0 UCA1CTL1 UCA1BR0 UCA1BR1 UCA1MCTL UCA1STAT UCA1RXBUF UCA1TXBUF UCA1ABCTL UCA1IRTCTL UCA1IRRCTL UC1IE UC1IFG Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Read/write Read/write Read/write Address 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0CDh 0CEh 0CFh 006h 007h Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC 428 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.4.1 UCAxCTL0, USCI_Ax Control Register 0 USCI Registers: UART Mode 7 UCPEN rw-0 UCPEN UCPAR UCMSB UC7BIT UCSPB UCMODEx UCSYNC 6 UCPAR rw-0 5 UCMSB rw-0 4 UC7BIT rw-0 3 UCSPB rw-0 2 1 UCMODEx rw-0 rw-0 0 UCSYNC rw-0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bits 2-1 Bit 0 Parity enable 0 Parity disabled. 1 Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation. Parity select. UCPAR is not used when parity is disabled. 0 Odd parity 1 Even parity MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data Stop bit select. Number of stop bits. 0 One stop bit 1 Two stop bits USCI mode. The UCMODEx bits select the asynchronous mode when UCSYNC = 0. 00 UART mode 01 Idle-line multiprocessor mode 10 Address-bit multiprocessor mode 11 UART mode with automatic baud rate detection Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 429 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: UART Mode 15.4.2 UCAxCTL1, USCI_Ax Control Register 1 www.ti.com 7 6 UCSSELx rw-0 rw-0 UCSSELx Bits 7-6 UCRXEIE Bit 5 UCBRKIE Bit 4 UCDORM Bit 3 UCTXADDR Bit 2 UCTXBRK Bit 1 UCSWRST Bit 0 5 UCRXEIE rw-0 4 UCBRKIE rw-0 3 UCDORM rw-0 2 UCTXADDR rw-0 1 UCTXBRK rw-0 0 UCSWRST rw-1 USCI clock source select. These bits select the BRCLK source clock. 00 UCLK 01 ACLK 10 SMCLK 11 SMCLK Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and UCAxRXIFG is not set 1 Erroneous characters received will set UCAxRXIFG Receive break character interrupt-enable 0 Received break characters do not set UCAxRXIFG. 1 Received break characters set UCAxRXIFG. Dormant. Puts USCI into sleep mode. 0 Not dormant. All received characters will set UCAxRXIFG. 1 Dormant. Only characters that are preceded by an idle-line or with address bit set will set UCAxRXIFG. In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG. Transmit address. Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode. 0 Next frame transmitted is data 1 Next frame transmitted is an address Transmit break. Transmits a break with the next write to the transmit buffer. In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break/synch fields. Otherwise 0h must be written into the transmit buffer. 0 Next frame transmitted is not a break 1 Next frame transmitted is a break or a break/synch Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state. 15.4.3 UCAxBR0, USCI_Ax Baud Rate Control Register 0 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw 15.4.4 UCAxBR1, USCI_Ax Baud Rate Control Register 1 7 rw UCBRx 6 rw 7-0 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw Clock prescaler setting of the Baud rate generator. The 16-bit value of (UCAxBR0 + UCAxBR1 × 256) forms the prescaler value. 430 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.4.5 UCAxMCTL, USCI_Ax Modulation Control Register USCI Registers: UART Mode 7 rw-0 UCBRFx UCBRSx UCOS16 6 5 4 3 2 1 0 UCBRFx UCBRSx UCOS16 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bits 7-4 Bits 3-1 Bit 0 First modulation stage select. These bits determine the modulation pattern for BITCLK16 when UCOS16 = 1. Ignored with UCOS16 = 0. Table 15-3 shows the modulation pattern. Second modulation stage select. These bits determine the modulation pattern for BITCLK. Table 15-2 shows the modulation pattern. Oversampling mode enabled 0 Disabled 1 Enabled 15.4.6 UCAxSTAT, USCI_Ax Status Register 7 UCLISTEN rw-0 UCLISTEN UCFE UCOE UCPE UCBRK UCRXERR UCADDR UCIDLE UCBUSY 6 UCFE rw-0 5 UCOE rw-0 4 UCPE rw-0 3 UCBRK rw-0 2 UCRXERR rw-0 1 UCADDR UCIDLE rw-0 0 UCBUSY r-0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UCAxTXD is internally fed back to the receiver. Framing error flag 0 No error 1 Character received with low stop bit Overrun error flag. This bit is set when a character is transferred into UCAxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred Parity error flag. When UCPEN = 0, UCPE is read as 0. 0 No error 1 Character received with parity error Break detect flag 0 No break condition 1 Break condition occurred Receive error flag. This bit indicates a character was received with error(s). When UCRXERR = 1, on or more error flags (UCFE, UCPE, UCOE) is also set. UCRXERR is cleared when UCAxRXBUF is read. 0 No receive errors detected 1 Receive error detected Address received in address-bit multiprocessor mode. 0 Received character is data 1 Received character is an address Idle line detected in idle-line multiprocessor mode. 0 No idle line detected 1 Idle line detected USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 431 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: UART Mode 15.4.7 UCAxRXBUF, USCI_Ax Receive Buffer Register www.ti.com 7 rw UCRXBUFx 6 rw Bits 7-0 5 4 3 2 1 0 UCRXBUFx rw rw rw rw rw rw The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCAxRXBUF resets the receive-error bits, the UCADDR or UCIDLE bit, and UCAxRXIFG. In 7-bit data mode, UCAxRXBUF is LSB justified and the MSB is always reset. 15.4.8 UCAxTXBUF, USCI_Ax Transmit Buffer Register 7 rw UCTXBUFx 6 rw Bits 7-0 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UCAxTXD. Writing to the transmit data buffer clears UCAxTXIFG. The MSB of UCAxTXBUF is not used for 7-bit data and is reset. 15.4.9 UCAxIRTCTL, USCI_Ax IrDA Transmit Control Register 7 rw-0 UCIRTXPLx UCIRTXCLK UCIREN 6 rw-0 Bits 7-2 Bit 1 Bit 0 5 4 3 2 1 UCIRTXPLx UCIRTXCLK rw-0 rw-0 rw-0 rw-0 rw-0 Transmit pulse length. Pulse length tPULSE = (UCIRTXPLx + 1) / (2 × fIRTXCLK) IrDA transmit pulse clock select 0 BRCLK 1 BITCLK16 when UCOS16 = 1. Otherwise, BRCLK IrDA encoder/decoder enable. 0 IrDA encoder/decoder disabled 1 IrDA encoder/decoder enabled 0 UCIREN rw-0 15.4.10 UCAxIRRCTL, USCI_Ax IrDA Receive Control Register 7 rw-0 UCIRRXFLx UCIRRXPL UCIRRXFE 6 rw-0 Bits 7-2 Bit 1 Bit 0 5 4 3 2 1 0 UCIRRXFLx UCIRRXPL UCIRRXFE rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Receive filter length. The minimum pulse length for receive is given by: tMIN = (UCIRRXFLx + 4) / (2 × fIRTXCLK) IrDA receive input UCAxRXD polarity 0 IrDA transceiver delivers a high pulse when a light pulse is seen 1 IrDA transceiver delivers a low pulse when a light pulse is seen IrDA receive filter enabled 0 Receive filter disabled 1 Receive filter enabled 432 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.4.11 UCAxABCTL, USCI_Ax Auto Baud Rate Control Register USCI Registers: UART Mode 7 6 Reserved r-0 r-0 Reserved UCDELIMx Bits 7-6 Bits 5-4 UCSTOE Bit 3 UCBTOE Bit 2 Reserved UCABDEN Bit 1 Bit 0 5 4 UCDELIMx rw-0 rw-0 3 UCSTOE rw-0 2 UCBTOE rw-0 1 Reserved r-0 0 UCABDEN rw-0 Reserved Break/synch delimiter length 00 1 bit time 01 2 bit times 10 3 bit times 11 4 bit times Synch field time out error 0 No error 1 Length of synch field exceeded measurable time. Break time out error 0 No error 1 Length of break field exceeded 22 bit times. Reserved Automatic baud rate detect enable 0 Baud rate detection disabled. Length of break and synch field is not measured. 1 Baud rate detection enabled. Length of break and synch field is measured and baud rate settings are changed accordingly. 15.4.12 IE2, Interrupt Enable Register 2 7 UCA0TXIE UCA0RXIE 6 Bits 7-2 Bit 1 Bit 0 5 4 3 2 1 UCA0TXIE rw-0 These bits may be used by other modules (see the device-specific data sheet). USCI_A0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled 0 UCA0RXIE rw-0 15.4.13 IFG2, Interrupt Flag Register 2 7 UCA0TXIFG UCA0RXIFG 6 Bits 7-2 Bit 1 Bit 0 5 4 3 2 1 0 UCA0TXIFG UCA0RXIFG rw-1 rw-0 These bits may be used by other modules (see the device-specific data sheet). USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, UART Mode 433 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: UART Mode 15.4.14 UC1IE, USCI_A1 Interrupt Enable Register 7 rw-0 Unused UCA1TXIE UCA1RXIE 6 5 4 3 Unused rw-0 rw-0 rw-0 2 1 UCA1TXIE rw-0 Bits 7-4 Bits 3-2 Bit 1 Bit 0 Unused These bits may be used by other USCI modules (see the device-specific data sheet). USCI_A1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled www.ti.com 0 UCA1RXIE rw-0 15.4.15 UC1IFG, USCI_A1 Interrupt Flag Register 7 rw-0 Unused UCA1TXIFG UCA1RXIFG 6 5 4 3 Unused rw-0 rw-0 rw-0 2 1 0 UCA1TXIFG UCA1RXIFG rw-1 rw-0 Bits 7-4 Bits 3-2 Bit 1 Bit 0 Unused These bits may be used by other USCI modules (see the device-specific data sheet). USCI_A1 transmit interrupt flag. UCA1TXIFG is set when UCA1TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_A1 receive interrupt flag. UCA1RXIFG is set when UCA1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending 434 Universal Serial Communication Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 16 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, SPI Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. Topic ........................................................................................................................... Page 16.1 USCI Overview ................................................................................................ 436 16.2 USCI Introduction: SPI Mode ............................................................................. 436 16.3 USCI Operation: SPI Mode ................................................................................ 438 16.4 USCI Registers: SPI Mode ................................................................................ 444 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, SPI Mode 435 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Overview www.ti.com 16.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter (for example, USCI_A is different from USCI_B). If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers. For example, if one device has two USCI_A modules, they are named USCI_A0 and USCI_A1. See the device-specific data sheet to determine which USCI modules, if any, are implemented on each device. The USCI_Ax modules support: • UART mode • Pulse shaping for IrDA communications • Automatic baud rate detection for LIN communications • SPI mode The USCI_Bx modules support: • I2C mode • SPI mode 16.2 USCI Introduction: SPI Mode In synchronous mode, the USCI connects the MSP430 to an external system via three or four pins: UCxSIMO, UCxSOMI, UCxCLK, and UCxSTE. SPI mode is selected when the UCSYNC bit is set and SPI mode (3-pin or 4-pin) is selected with the UCMODEx bits. SPI mode features include: • 7- or 8-bit data length • LSB-first or MSB-first data transmit and receive • 3-pin and 4-pin SPI operation • Master or slave modes • Independent transmit and receive shift registers • Separate transmit and receive buffer registers • Continuous transmit and receive operation • Selectable clock polarity and phase control • Programmable clock frequency in master mode • Independent interrupt capability for receive and transmit • Slave operation in LPM4 Figure 16-1 shows the USCI when configured for SPI mode. 436 Universal Serial Communication Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Receive State Machine Receive Buffer UC xRXBUF Receive Shift Register UCMSB UC7BIT USCI Introduction: SPI Mode Set UCOE Set UCxRXIFG UCLISTEN UCMST UCxSOMI 1 0 0 1 UCSSELx Bit Clock Generator N/A ACLK SMCLK SMCLK UCxBRx 00 01 10 BRCLK 16 Prescaler/Divider 11 UCCKPH UCCKPL Clock Direction, Phase and Polarity UCxCLK UCMSB UC7BIT Transmit Shift Register Transmit Buffer UC xTXBUF Transmit State Machine UCMODEx 2 Transmit Enable Control Figure 16-1. USCI Block Diagram: SPI Mode UCxSIMO UCxSTE Set UCFE Set UCxTXIFG SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, SPI Mode 437 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: SPI Mode www.ti.com 16.3 USCI Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, UCxSTE, is provided to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: • UCxSIMO: Slave in, master out – Master mode: UCxSIMO is the data output line. – Slave mode: UCxSIMO is the data input line. • UCxSOMI: Slave out, master in – Master mode: UCxSOMI is the data input line. – Slave mode: UCxSOMI is the data output line. • UCxCLK: USCI SPI clock – Master mode: UCxCLK is an output. – Slave mode: UCxCLK is an input. • UCxSTE: Slave transmit enable Used in 4-pin mode to allow multiple masters on a single bus. Not used in 3-pin mode. Table 16-1 describes the UCxSTE operation. UCMODEx 01 10 Table 16-1. UCxSTE Operation UCxSTE Active State High Low UCxSTE 0 1 0 1 Slave Inactive Active Active Inactive Master Active Inactive Inactive Active 16.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition. When set, the UCSWRST bit resets the UCxRXIE, UCxTXIE, UCxRXIFG, UCOE, and UCFE bits and sets the UCxTXIFG flag. Clearing UCSWRST releases the USCI for operation. NOTE: Initializing or Re-Configuring the USCI Module The recommended USCI initialization/re-configuration process is: 1. Set UCSWRST (BIS.B #UCSWRST,&UCxCTL1) 2. Initialize all USCI registers with UCSWRST=1 (including UCxCTL1) 3. Configure ports 4. Clear UCSWRST via software (BIC.B #UCSWRST,&UCxCTL1) 5. Enable interrupts (optional) via UCxRXIE and/or UCxTXIE 438 Universal Serial Communication Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: SPI Mode 16.3.2 Character Format The USCI module in SPI mode supports 7-bit and 8-bit character lengths selected by the UC7BIT bit. In 7bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. The UCMSB bit controls the direction of the transfer and selects LSB or MSB first. NOTE: Default Character Format The default SPI character transmission is LSB first. For communication with other SPI interfaces it MSB-first mode may be required. NOTE: Character Format for Figures Figures throughout this chapter use MSB first format. 16.3.3 Master Mode Figure 16-2 shows the USCI as a master in both 3-pin and 4-pin configurations. The USCI initiates data transfer when data is moved to the transmit data buffer UCxTXBUF. The UCxTXBUF data is moved to the TX shift register when the TX shift register is empty, initiating data transfer on UCxSIMO starting with either the most-significant or least-significant bit depending on the UCMSB setting. Data on UCxSOMI is shifted into the receive shift register on the opposite clock edge. When the character is received, the receive data is moved from the RX shift register to the received data buffer UCxRXBUF and the receive interrupt flag, UCxRXIFG, is set, indicating the RX/TX operation is complete. MASTER UCxSIMO SIMO SLAVE Receive Buffer UCxRXBUF Receive Shift Register Transmit Buffer UCxTXBUF Px.x UCxSTE Transmit Shift Register UCx SOMI SPI Receive Buffer STE SS Port.x SOMI Data Shift Register (DSR) MSP430 USCI UCxCLK SCLK COMMON SPI Figure 16-2. USCI Master and External Slave A set transmit interrupt flag, UCxTXIFG, indicates that data has moved from UCxTXBUF to the TX shift register and UCxTXBUF is ready for new data. It does not indicate RX/TX completion. To receive data into the USCI in master mode, data must be written to UCxTXBUF because receive and transmit operations operate concurrently. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, SPI Mode 439 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: SPI Mode www.ti.com 16.3.3.1 Four-Pin SPI Master Mode In 4-pin master mode, UCxSTE is used to prevent conflicts with another master and controls the master as described in Table 16-1. When UCxSTE is in the master-inactive state: • UCxSIMO and UCxCLK are set to inputs and no longer drive the bus • The error bit UCFE is set indicating a communication integrity violation to be handled by the user. • The internal state machines are reset and the shift operation is aborted. If data is written into UCxTXBUF while the master is held inactive by UCxSTE, it will be transmitted as soon as UCxSTE transitions to the master-active state. If an active transfer is aborted by UCxSTE transitioning to the master-inactive state, the data must be re-written into UCxTXBUF to be transferred when UCxSTE transitions back to the master-active state. The UCxSTE input signal is not used in 3-pin master mode. 16.3.4 Slave Mode Figure 16-3 shows the USCI as a slave in both 3-pin and 4-pin configurations. UCxCLK is used as the input for the SPI clock and must be supplied by the external master. The data-transfer rate is determined by this clock and not by the internal bit clock generator. Data written to UCxTXBUF and moved to the TX shift register before the start of UCxCLK is transmitted on UCxSOMI. Data on UCxSIMO is shifted into the receive shift register on the opposite edge of UCxCLK and moved to UCxRXBUF when the set number of bits are received. When data is moved from the RX shift register to UCxRXBUF, the UCxRXIFG interrupt flag is set, indicating that data has been received. The overrun error bit, UCOE, is set when the previously received data is not read from UCxRXBUF before new data is moved to UCxRXBUF. MASTER SIMO UCxSIMO SLAVE SPI Receive Buffer Px.x STE SOMI Data Shift Register DSR Transmit Buffer UCxTXBUF UCxSTE SS Port.x UCx SOMI Transmit Shift Register Receive Buffer UCxRXBUF Receive Shift Register SCLK COMMON SPI UCxCLK MSP430 USCI Figure 16-3. USCI Slave and External Master 16.3.4.1 Four-Pin SPI Slave Mode In 4-pin slave mode, UCxSTE is used by the slave to enable the transmit and receive operations and is provided by the SPI master. When UCxSTE is in the slave-active state, the slave operates normally. When UCxSTE is in the slave- inactive state: • Any receive operation in progress on UCxSIMO is halted • UCxSOMI is set to the input direction • The shift operation is halted until the UCxSTE line transitions into the slave transmit active state. The UCxSTE input signal is not used in 3-pin slave mode. 440 Universal Serial Communication Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: SPI Mode 16.3.5 SPI Enable When the USCI module is enabled by clearing the UCSWRST bit it is ready to receive and transmit. In master mode the bit clock generator is ready, but is not clocked nor producing any clocks. In slave mode the bit clock generator is disabled and the clock is provided by the master. A transmit or receive operation is indicated by UCBUSY = 1. A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated. 16.3.5.1 Transmit Enable In master mode, writing to UCxTXBUF activates the bit clock generator and the data will begin to transmit. In slave mode, transmission begins when a master provides a clock and, in 4-pin mode, when the UCxSTE is in the slave-active state. 16.3.5.2 Receive Enable The SPI receives data when a transmission is active. Receive and transmit operations operate concurrently. 16.3.6 Serial Clock Control UCxCLK is provided by the master on the SPI bus. When UCMST = 1, the bit clock is provided by the USCI bit clock generator on the UCxCLK pin. The clock used to generate the bit clock is selected with the UCSSELx bits. When UCMST = 0, the USCI clock is provided on the UCxCLK pin by the master, the bit clock generator is not used, and the UCSSELx bits are don’t care. The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer. The 16-bit value of UCBRx in the bit rate control registers UCxxBR1 and UCxxBR0 is the division factor of the USCI clock source, BRCLK. The maximum bit clock that can be generated in master mode is BRCLK. Modulation is not used in SPI mode and UCAxMCTL should be cleared when using SPI mode for USCI_A. The UCAxCLK/UCBxCLK frequency is given by: fBitClock = fBRCLK UCBRx SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, SPI Mode 441 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: SPI Mode www.ti.com 16.3.6.1 Serial Clock Polarity and Phase The polarity and phase of UCxCLK are independently configured via the UCCKPL and UCCKPH control bits of the USCI. Timing for each case is shown in Figure 16-4. UC UC CKPH CKPL Cycle# 1 2 3 4 5 6 7 8 0 0 UCxCLK 0 1 UCxCLK 1 0 UCxCLK 1 1 UCxCLK UCxSTE 0 X UCxSIMO UCxSOMI 1 X UCxSIMO UCxSOMI Move to UCxTXBUF TX Data Shifted Out MSB MSB LSB LSB RX Sample Points Figure 16-4. USCI SPI Timing with UCMSB = 1 16.3.7 Using the SPI Mode With Low-Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition. After the USCI module returns to the idle condition, control of the clock source reverts to the settings of its control bits. Automatic clock activation is not provided for ACLK. When the USCI module activates an inactive clock source, the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected. For example, a timer using SMCLK increments while the USCI module forces SMCLK active. In SPI slave mode, no internal clock source is required because the clock is provided by the external master. It is possible to operate the USCI in SPI slave mode while the device is in LPM4 and all clock sources are disabled. The receive or transmit interrupt can wake up the CPU from any low power mode. 16.3.8 SPI Interrupts The USCI has one interrupt vector for transmission and one interrupt vector for reception. 16.3.8.1 SPI Transmit Interrupt Operation The UCxTXIFG interrupt flag is set by the transmitter to indicate that UCxTXBUF is ready to accept another character. An interrupt request is generated if UCxTXIE and GIE are also set. UCxTXIFG is automatically reset if a character is written to UCxTXBUF. UCxTXIFG is set after a PUC or when UCSWRST = 1. UCxTXIE is reset after a PUC or when UCSWRST = 1. NOTE: Writing to UCxTXBUF in SPI Mode Data written to UCxTXBUF when UCxTXIFG = 0 may result in erroneous data transmission. 442 Universal Serial Communication Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USCI Operation: SPI Mode 16.3.8.2 SPI Receive Interrupt Operation The UCxRXIFG interrupt flag is set each time a character is received and loaded into UCxRXBUF. An interrupt request is generated if UCxRXIE and GIE are also set. UCxRXIFG and UCxRXIE are reset by a system reset PUC signal or when UCSWRST = 1. UCxRXIFG is automatically reset when UCxRXBUF is read. 16.3.8.3 USCI Interrupt Usage USCI_Ax and USCI_Bx share the same interrupt vectors. The receive interrupt flags UCAxRXIFG and UCBxRXIFG are routed to one interrupt vector, the transmit interrupt flags UCAxTXIFG and UCBxTXIFG share another interrupt vector. Example 16-1 shows an extract of an interrupt service routine to handle data receive interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode. Example 16-1. Shared Receive Interrupt Vectors Software Example USCIA0_RX_USCIB0_RX_ISR BIT.B #UCA0RXIFG, &IFG2 ; USCI_A0 Receive Interrupt? JNZ USCIA0_RX_ISR USCIB0_RX_ISR? ; Read UCB0RXBUF (clears UCB0RXIFG) ... RETI USCIA0_RX_ISR ; Read UCA0RXBUF (clears UCA0RXIFG) ... RETI Example 16-2 shows an extract of an interrupt service routine to handle data transmit interrupts from USCI_A0 in either UART or SPI mode and USCI_B0 in SPI mode. Example 16-2. Shared Transmit Interrupt Vectors Software Example USCIA0_TX_USCIB0_TX_ISR BIT.B #UCA0TXIFG, &IFG2 ; USCI_A0 Transmit Interrupt? JNZ USCIA0_TX_ISR USCIB0_TX_ISR ; Write UCB0TXBUF (clears UCB0TXIFG) ... RETI USCIA0_TX_ISR ; Write UCA0TXBUF (clears UCA0TXIFG) ... RETI SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, SPI Mode 443 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: SPI Mode www.ti.com 16.4 USCI Registers: SPI Mode The USCI registers applicable in SPI mode for USCI_A0 and USCI_B0 are listed in Table 16-2. Registers applicable in SPI mode for USCI_A1 and USCI_B1 are listed in Table 16-3. Table 16-2. USCI_A0 and USCI_B0 Control and Status Registers Register USCI_A0 control register 0 USCI_A0 control register 1 USCI_A0 baud rate control register 0 USCI_A0 baud rate control register 1 USCI_A0 modulation control register USCI_A0 status register USCI_A0 receive buffer register USCI_A0 transmit buffer register USCI_B0 control register 0 USCI_B0 control register 1 USCI_B0 bit rate control register 0 USCI_B0 bit rate control register 1 USCI_B0 status register USCI_B0 receive buffer register USCI_B0 transmit buffer register SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form UCA0CTL0 UCA0CTL1 UCA0BR0 UCA0BR1 UCA0MCTL UCA0STAT UCA0RXBUF UCA0TXBUF UCB0CTL0 UCB0CTL1 UCB0BR0 UCB0BR1 UCB0STAT UCB0RXBUF UCB0TXBUF IE2 IFG2 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Address 060h 061h 062h 063h 064h 065h 066h 067h 068h 069h 06Ah 06Bh 06Dh 06Eh 06Fh 001h 003h Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 001h with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC NOTE: Modifying SFR bits To avoid modifying control bits of other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. Table 16-3. USCI_A1 and USCI_B1 Control and Status Registers Register USCI_A1 control register 0 USCI_A1 control register 1 USCI_A1 baud rate control register 0 USCI_A1 baud rate control register 1 USCI_A1 modulation control register USCI_A1 status register USCI_A1 receive buffer register USCI_A1 transmit buffer register USCI_B1 control register 0 USCI_B1 control register 1 USCI_B1 bit rate control register 0 USCI_B1 bit rate control register 1 USCI_B1 status register USCI_B1 receive buffer register USCI_B1 transmit buffer register USCI_A1/B1 interrupt enable register USCI_A1/B1 interrupt flag register Short Form UCA1CTL0 UCA1CTL1 UCA1BR0 UCA1BR1 UCA10MCTL UCA1STAT UCA1RXBUF UCA1TXBUF UCB1CTL0 UCB1CTL1 UCB1BR0 UCB1BR1 UCB1STAT UCB1RXBUF UCB1TXBUF UC1IE UC1IFG Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Address 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0D8h 0D9h 0DAh 0DBh 0DDh 0DEh 0DFh 006h 007h Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 001h with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC 444 Universal Serial Communication Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com 16.4.1 UCAxCTL0, USCI_Ax Control Register 0, UCBxCTL0, USCI_Bx Control Register 0 USCI Registers: SPI Mode 7 UCCKPH rw-0 UCCKPH UCCKPL UCMSB UC7BIT UCMST UCMODEx UCSYNC 6 UCCKPL rw-0 5 UCMSB rw-0 4 UC7BIT rw-0 3 UCMST rw-0 2 1 UCMODEx rw-0 rw-0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bits 2-1 Bit 0 Clock phase select. 0 Data is changed on the first UCLK edge and captured on the following edge. 1 Data is captured on the first UCLK edge and changed on the following edge. Clock polarity select. 0 The inactive state is low. 1 The inactive state is high. MSB first select. Controls the direction of the receive and transmit shift register. 0 LSB first 1 MSB first Character length. Selects 7-bit or 8-bit character length. 0 8-bit data 1 7-bit data Master mode select 0 Slave mode 1 Master mode USCI mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-pin SPI 01 4-pin SPI with UCxSTE active high: slave enabled when UCxSTE = 1 10 4-pin SPI with UCxSTE active low: slave enabled when UCxSTE = 0 11 I2C mode Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode 0 UCSYNC=1 16.4.2 UCAxCTL1, USCI_Ax Control Register 1, UCBxCTL1, USCI_Bx Control Register 1 7 6 UCSSELx rw-0 rw-0 UCSSELx Bits 7-6 Unused UCSWRST Bits 5-1 Bit 0 (1) UCAxCTL1 (USCI_Ax) (2) UCBxCTL1 (USCI_Bx) 5 rw-0 (1) r0 (2) 4 3 2 Unused rw-0 rw-0 rw-0 1 0 UCSWRST rw-0 rw-1 USCI clock source select. These bits select the BRCLK source clock in master mode. UCxCLK is always used in slave mode. 00 NA 01 ACLK 10 SMCLK 11 SMCLK Unused Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, SPI Mode 445 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: SPI Mode 16.4.3 UCAxBR0, USCI_Ax Bit Rate Control Register 0, UCBxBR0, USCI_Bx Bit Rate Control Register 0 7 6 5 4 3 2 UCBRx - low byte rw rw rw rw rw rw www.ti.com 1 0 rw rw 16.4.4 UCAxBR1, USCI_Ax Bit Rate Control Register 1, UCBxBR1, USCI_Bx Bit Rate Control Register 1 7 rw UCBRx 6 5 4 3 2 1 0 UCBRx - high byte rw rw rw rw rw rw rw Bit clock prescaler setting. The 16-bit value of (UCxxBR0 + UCxxBR1 × 256) forms the prescaler value. 16.4.5 UCAxSTAT, USCI_Ax Status Register, UCBxSTAT, USCI_Bx Status Register 7 UCLISTEN rw-0 6 UCFE rw-0 5 UCOE rw-0 4 rw-0 (1) r0 (2) 3 2 Unused rw-0 rw-0 1 0 UCBUSY rw-0 r-0 UCLISTEN UCFE UCOE Unused UCBUSY Bit 7 Bit 6 Bit 5 Bits 4-1 Bit 0 Listen enable. The UCLISTEN bit selects loopback mode. 0 Disabled 1 Enabled. The transmitter output is internally fed back to the receiver. Framing error flag. This bit indicates a bus conflict in 4-wire master mode. UCFE is not used in 3-wire master or any slave mode. 0 No error 1 Bus conflict occurred Overrun error flag. This bit is set when a character is transferred into UCxRXBUF before the previous character was read. UCOE is cleared automatically when UCxRXBUF is read, and must not be cleared by software. Otherwise, it will not function correctly. 0 No error 1 Overrun error occurred Unused USCI busy. This bit indicates if a transmit or receive operation is in progress. 0 USCI inactive 1 USCI transmitting or receiving (1) UCAxSTAT (USCI_Ax) (2) UCBxSTAT (USCI_Bx) 16.4.6 UCAxRXBUF, USCI_Ax Receive Buffer Register, UCBxRXBUF, USCI_Bx Receive Buffer Register 7 r UCRXBUFx 6 r Bits 7-0 5 4 3 2 1 0 UCRXBUFx r r r r r r The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCxRXBUF resets the receive-error bits, and UCxRXIFG. In 7-bit data mode, UCxRXBUF is LSB justified and the MSB is always reset. 446 Universal Serial Communication Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 16.4.7 UCAxTXBUF, USCI_Ax Transmit Buffer Register, UCBxTXBUF, USCI_Bx Transmit Buffer Register USCI Registers: SPI Mode 7 rw UCTXBUFx 6 rw Bits 7-0 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted. Writing to the transmit data buffer clears UCxTXIFG. The MSB of UCxTXBUF is not used for 7-bit data and is reset. 16.4.8 IE2, Interrupt Enable Register 2 7 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE 6 Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 UCB0TXIE UCB0RXIE UCA0TXIE rw-0 rw-0 rw-0 These bits may be used by other modules (see the device-specific data sheet). USCI_B0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled 0 UCA0RXIE rw-0 16.4.9 IFG2, Interrupt Flag Register 2 7 UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG 6 Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG rw-1 rw-0 rw-1 rw-0 These bits may be used by other modules (see the device-specific data sheet). USCI_B0 transmit interrupt flag. UCB0TXIFG is set when UCB0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_B0 receive interrupt flag. UCB0RXIFG is set when UCB0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending USCI_A0 transmit interrupt flag. UCA0TXIFG is set when UCA0TXBUF empty. 0 No interrupt pending 1 Interrupt pending USCI_A0 receive interrupt flag. UCA0RXIFG is set when UCA0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, SPI Mode 447 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: SPI Mode 16.4.10 UC1IE, USCI_A1/USCI_B1 Interrupt Enable Register 7 rw-0 Unused UCB1TXIE UCB1RXIE UCA1TXIE UCA1RXIE 6 5 4 Unused rw-0 rw-0 rw-0 Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Unused USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled 3 UCB1TXIE rw-0 2 UCB1RXIE rw-0 1 UCA1TXIE rw-0 www.ti.com 0 UCA1RXIE rw-0 16.4.11 UC1IFG, USCI_A1/USCI_B1 Interrupt Flag Register 7 rw-0 Unused UCB1TXIFG UCB1RXIFG UCA1TXIFG UCA1RXIFG 6 5 Unused rw-0 rw-0 4 3 2 1 0 UCB1TXIFG UCB1RXIFG UCA1TXIFG UCA1RXIFG rw-0 rw-1 rw-0 rw-1 rw-0 Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Unused USCI_B1 transmit interrupt flag. UCB1TXIFG is set when UCB1TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_B1 receive interrupt flag. UCB1RXIFG is set when UCB1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending USCI_A1 transmit interrupt flag. UCA1TXIFG is set when UCA1TXBUF empty. 0 No interrupt pending 1 Interrupt pending USCI_A1 receive interrupt flag. UCA1RXIFG is set when UCA1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending 448 Universal Serial Communication Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 17 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module. This chapter discusses the operation of the I2C mode. Topic ........................................................................................................................... Page 17.1 USCI Overview ................................................................................................ 450 17.2 USCI Introduction: I2C Mode .............................................................................. 450 17.3 USCI Operation: I2C Mode ................................................................................. 451 17.4 USCI Registers: I2C Mode ................................................................................. 467 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 449 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Overview www.ti.com 17.1 USCI Overview The universal serial communication interface (USCI) modules support multiple serial communication modes. Different USCI modules support different modes. Each different USCI module is named with a different letter. For example, USCI_A is different from USCI_B, etc. If more than one identical USCI module is implemented on one device, those modules are named with incrementing numbers. For example, if one device has two USCI_A modules, they are named USCI_A0 and USCI_A1. See the device-specific data sheet to determine which USCI modules, if any, are implemented on which devices. The USCI_Ax modules support: • UART mode • Pulse shaping for IrDA communications • Automatic baud rate detection for LIN communications • SPI mode The USCI_Bx modules support: • I2C mode • SPI mode 17.2 USCI Introduction: I2C Mode In I2C mode, the USCI module provides an interface between the MSP430 and I2C-compatible devices connected by way of the two-wire I2C serial bus. External components attached to the I2C bus serially transmit and/or receive serial data to/from the USCI module through the 2-wire I2C interface. The I2C mode features include: • Compliance to the Philips Semiconductor I2C specification v2.1 – 7-bit and 10-bit device addressing modes – General call – START/RESTART/STOP – Multi-master transmitter/receiver mode – Slave receiver/transmitter mode – Standard mode up to 100 kbps and fast mode up to 400 kbps support • Programmable UCxCLK frequency in master mode • Designed for low power • Slave receiver START detection for auto-wake up from LPMx modes • Slave operation in LPM4 Figure 17-1 shows the USCI when configured in I2C mode. 450 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com UCA10 UCGCEN Own Address UC1OA Receive Shift Register Receive Buffer UC1RXBUF I2C State Machine USCI Operation: I2C Mode UCxSDA Transmit Buffer UC 1TXBUF Transmit Shift Register Slave Address UC 1SA UCSLA10 UCSSELx Bit Clock Generator UC1CLK ACLK SMCLK UCxBRx 00 01 10 BRCLK 16 Prescaler/Divider SMCLK 11 UCMST Figure 17-1. USCI Block Diagram: I2C Mode UCxSCL 17.3 USCI Operation: I2C Mode The I2C mode supports any slave or master I2C-compatible device. Figure 17-2 shows an example of an I2C bus. Each I2C device is recognized by a unique address and can operate as either a transmitter or a receiver. A device connected to the I2C bus can be considered as the master or the slave when performing data transfers. A master initiates a data transfer and generates the clock signal SCL. Any device addressed by a master is considered a slave. I2C data is communicated using the serial data pin (SDA) and the serial clock pin (SCL). Both SDA and SCL are bidirectional, and must be connected to a positive supply voltage using a pullup resistor. NOTE: SDA and SCL Levels The MSP430 SDA and SCL pins must not be pulled up above the MSP430 VCC level. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 451 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: I2C Mode Serial Data (SDA) Serial Clock (SCL) VCC MSP430 Device A www.ti.com Device B Device C Figure 17-2. I2C Bus Connection Diagram 17.3.1 USCI Initialization and Reset The USCI is reset by a PUC or by setting the UCSWRST bit. After a PUC, the UCSWRST bit is automatically set, keeping the USCI in a reset condition. To select I2C operation the UCMODEx bits must be set to 11. After module initialization, it is ready for transmit or receive operation. Clearing UCSWRST releases the USCI for operation. Configuring and reconfiguring the USCI module should be done when UCSWRST is set to avoid unpredictable behavior. Setting UCSWRST in I2C mode has the following effects: • I2C communication stops • SDA and SCL are high impedance • UCBxI2CSTAT, bits 6-0 are cleared • UCBxTXIE and UCBxRXIE are cleared • UCBxTXIFG and UCBxRXIFG are cleared • All other bits and registers remain unchanged. NOTE: Initializing or Reconfiguring the USCI Module The recommended USCI initialization or reconfiguration process is: 1. Set UCSWRST (BIS.B #UCSWRST,&UCxCTL1) 2. Initialize all USCI registers with UCSWRST=1 (including UCxCTL1) 3. Configure ports. 4. Clear UCSWRST via software (BIC.B #UCSWRST,&UCxCTL1) 5. Enable interrupts (optional) via UCxRXIE and/or UCxTXIE 17.3.2 I2C Serial Data One clock pulse is generated by the master device for each data bit transferred. The I2C mode operates with byte data. Data is transferred most significant bit first as shown in Figure 17-3. The first byte after a START condition consists of a 7-bit slave address and the R/W bit. When R/W = 0, the master transmits data to a slave. When R/W = 1, the master receives data from a slave. The ACK bit is sent from the receiver after each byte on the 9th SCL clock. SDA MSB SCL START 1 Condition (S) Acknowledgement Signal From Receiver Acknowledgement Signal From Receiver 2 789 12 R/W ACK Figure 17-3. I2C Module Data Transfer 89 STOP ACK Condition (P) 452 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USCI Operation: I2C Mode START and STOP conditions are generated by the master and are shown in Figure 17-3. A START condition is a high-to-low transition on the SDA line while SCL is high. A STOP condition is a low-to-high transition on the SDA line while SCL is high. The bus busy bit, UCBBUSY, is set after a START and cleared after a STOP. Data on SDA must be stable during the high period of SCL as shown in Figure 17-4. The high and low state of SDA can only change when SCL is low, otherwise START or STOP conditions will be generated. SDA Data Line Stable Data SCL Change of Data Allowed Figure 17-4. Bit Transfer on the I2C Bus 17.3.3 I2C Addressing Modes The I2C mode supports 7-bit and 10-bit addressing modes. 17.3.3.1 7-Bit Addressing In the 7-bit addressing format, shown in Figure 17-5, the first byte is the 7-bit slave address and the R/W bit. The ACK bit is sent from the receiver after each byte. 1 7 1 1 S Slave Address R/W ACK 8 Data 1 ACK 8 Data 11 ACK P Figure 17-5. I2C Module 7-Bit Addressing Format 17.3.3.2 10-Bit Addressing In the 10-bit addressing format, shown in Figure 17-6, the first byte is made up of 11110b plus the two MSBs of the 10-bit slave address and the R/W bit. The ACK bit is sent from the receiver after each byte. The next byte is the remaining 8 bits of the 10-bit slave address, followed by the ACK bit and the 8-bit data. 1 7 1 1 8 1 S Slave Address 1st byte R/W ACK Slave Address 2nd byte ACK 1 1 1 1 0XX 8 Data 11 ACK P Figure 17-6. I2C Module 10-Bit Addressing Format 17.3.3.3 Repeated Start Conditions The direction of data flow on SDA can be changed by the master, without first stopping a transfer, by issuing a repeated START condition. This is called a RESTART. After a RESTART is issued, the slave address is again sent out with the new data direction specified by the R/W bit. The RESTART condition is shown in Figure 17-7. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 453 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: I2C Mode www.ti.com 1 7 11 8 11 7 11 8 11 S Slave Address R/W ACK Data ACK S Slave Address R/W ACK Data ACK P 1 Any Number 1 Any Number Figure 17-7. I2C Module Addressing Format with Repeated START Condition 17.3.4 I2C Module Operating Modes In I2C mode the USCI module can operate in master transmitter, master receiver, slave transmitter, or slave receiver mode. The modes are discussed in the following sections. Time lines are used to illustrate the modes. Figure 17-8 shows how to interpret the time line figures. Data transmitted by the master is represented by grey rectangles, data transmitted by the slave by white rectangles. Data transmitted by the USCI module, either as master or slave, is shown by rectangles that are taller than the others. Actions taken by the USCI module are shown in grey rectangles with an arrow indicating where in the data stream the action occurs. Actions that must be handled with software are indicated with white rectangles with an arrow pointing to where in the data stream the action must take place. Other Master Other Slave USCI Master USCI Slave ... Bits set or reset by software ... Bits set or reset by hardware Figure 17-8. I2C Time Line Legend 17.3.4.1 Slave Mode The USCI module is configured as an I2C slave by selecting the I2C mode with UCMODEx = 11 and UCSYNC = 1 and clearing the UCMST bit. Initially the USCI module must to be configured in receiver mode by clearing the UCTR bit to receive the I2C address. Afterwards, transmit and receive operations are controlled automatically depending on the R/W bit received together with the slave address. The USCI slave address is programmed with the UCBxI2COA register. When UCA10 = 0, 7-bit addressing is selected. When UCA10 = 1, 10-bit addressing is selected. The UCGCEN bit selects if the slave responds to a general call. When a START condition is detected on the bus, the USCI module will receive the transmitted address and compare it against its own address stored in UCBxI2COA. The UCSTTIFG flag is set when address received matches the USCI slave address. 454 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USCI Operation: I2C Mode 17.3.4.1.1 I2C Slave Transmitter Mode Slave transmitter mode is entered when the slave address transmitted by the master is identical to its own address with a set R/W bit. The slave transmitter shifts the serial data out on SDA with the clock pulses that are generated by the master device. The slave device does not generate the clock, but it will hold SCL low while intervention of the CPU is required after a byte has been transmitted. If the master requests data from the slave the USCI module is automatically configured as a transmitter and UCTR and UCBxTXIFG become set. The SCL line is held low until the first data to be sent is written into the transmit buffer UCBxTXBUF. Then the address is acknowledged, the UCSTTIFG flag is cleared, and the data is transmitted. As soon as the data is transferred into the shift register the UCBxTXIFG is set again. After the data is acknowledged by the master the next data byte written into UCBxTXBUF is transmitted or if the buffer is empty the bus is stalled during the acknowledge cycle by holding SCL low until new data is written into UCBxTXBUF. If the master sends a NACK succeeded by a STOP condition the UCSTPIFG flag is set. If the NACK is succeeded by a repeated START condition the USCI I2C state machine returns to its address-reception state. Figure 17-9 shows the slave transmitter operation. Reception of own S address and transmission of data SLA/R bytes UCTR=1 (Transmitter) UCSTTIFG=1 UCBxTXIFG=1 UCSTPIFG=?0 UCBxTXBUF discarded A DATA A DATA A DATA AP Write data to UCBxTXBUF UCBxTXIFG=1 UCBxTXIFG=0 UCSTPIFG=1 UCSTTIFG=0 Bus stalled (SCL held low) until data available Write data to UCBxTXBUF Repeated start − continue as slave transmitter DATA A S SLA/R UCBxTXIFG=0 UCTR=1 (Transmitter) UCSTTIFG=1 UCBxTXIFG=1 UCBxTXBUF discarded Repeated start − continue as slave receiver Arbitration lost as master and addressed as slave DATA A S SLA/W UCBxTXIFG=0 A UCTR=0 (Receiver) UCSTTIFG=1 UCALIFG=1 UCMST=0 UCTR=1 (Transmitter) UCSTTIFG=1 UCBxTXIFG=1 UCSTPIFG=0 Figure 17-9. I2C Slave Transmitter Mode SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 455 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: I2C Mode www.ti.com 17.3.4.1.2 I2C Slave Receiver Mode Slave receiver mode is entered when the slave address transmitted by the master is identical to its own address and a cleared R/W bit is received. In slave receiver mode, serial data bits received on SDA are shifted in with the clock pulses that are generated by the master device. The slave device does not generate the clock, but it can hold SCL low if intervention of the CPU is required after a byte has been received. If the slave should receive data from the master the USCI module is automatically configured as a receiver and UCTR is cleared. After the first data byte is received the receive interrupt flag UCBxRXIFG is set. The USCI module automatically acknowledges the received data and can receive the next data byte. If the previous data was not read from the receive buffer UCBxRXBUF at the end of a reception, the bus is stalled by holding SCL low. As soon as UCBxRXBUF is read the new data is transferred into UCBxRXBUF, an acknowledge is sent to the master, and the next data can be received. Setting the UCTXNACK bit causes a NACK to be transmitted to the master during the next acknowledgment cycle. A NACK is sent even if UCBxRXBUF is not ready to receive the latest data. If the UCTXNACK bit is set while SCL is held low the bus will be released, a NACK is transmitted immediately, and UCBxRXBUF is loaded with the last received data. Since the previous data was not read that data will be lost. To avoid loss of data the UCBxRXBUF needs to be read before UCTXNACK is set. When the master generates a STOP condition the UCSTPIFG flag is set. If the master generates a repeated START condition the USCI I2C state machine returns to its address reception state. Figure 17-10 shows the I2C slave receiver operation. 456 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USCI Operation: I2C Mode Reception of own address and data bytes. All are acknowledged. S SLA/W A UCTR=0 (Receiver) UCSTTIFG=1 UCSTPIFG=0 DATA A DATA A UCBxRXIFG=1 Bus stalled (SCL held low) if UCBxRXBUF not read Read data from UCBxRXBUF DATA A P or S Refer to: ”Slave Transmitter” Timing Diagram Last byte is not acknowledged. Reception of the general call address. Gen Call A UCTR=0 (Receiver) UCSTTIFG=1 UCGC=1 DATA A P or S UCTXNACK=1 Bus not stalled even if UCBxRXBUF not read UCTXNACK=0 Arbitration lost as master and addressed as slave A UCALIFG=1 UCMST=0 UCTR=0 (Receiver) UCSTTIFG=1 (UCGC=1 if general call) UCBxTXIFG=0 UCSTPIFG=0 Figure 17-10. I2C Slave Receiver Mode SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 457 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: I2C Mode www.ti.com 17.3.4.1.3 I2C Slave 10-bit Addressing Mode The 10-bit addressing mode is selected when UCA10 = 1 and is as shown in Figure 17-11. In 10-bit addressing mode, the slave is in receive mode after the full address is received. The USCI module indicates this by setting the UCSTTIFG flag while the UCTR bit is cleared. To switch the slave into transmitter mode the master sends a repeated START condition together with the first byte of the address but with the R/W bit set. This will set the UCSTTIFG flag if it was previously cleared by software and the USCI modules switches to transmitter mode with UCTR = 1. Slave Receiver Reception of own address and data bytes. All are acknowledged. S 11110 xx/W A SLA (2.) A UCTR=0 (Receiver) UCSTTIFG=1 UCSTPIFG=0 DATA A DATA UCBxRXIFG=1 A P or S Reception of the general call address. Gen Call A UCTR=0 (Receiver) UCSTTIFG=1 UCGC=1 DATA A DATA UCBxRXIFG=1 A P or S Slave Transmitter Reception of own address and S 11110 xx/W A SLA (2.) transmission of data bytes UCTR=0 (Receiver) UCSTTIFG=1 UCSTPIFG=0 A S 11110 xx/R A DATA A P or S UCSTTIFG=0 UCTR=1 (Transmitter) UCSTTIFG=1 UCBxTXIFG=1 UCSTPIFG=0 Figure 17-11. I2C Slave 10-bit Addressing Mode 458 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USCI Operation: I2C Mode 17.3.4.2 Master Mode The USCI module is configured as an I2C master by selecting the I2C mode with UCMODEx = 11 and UCSYNC = 1 and setting the UCMST bit. When the master is part of a multi-master system, UCMM must be set and its own address must be programmed into the UCBxI2COA register. When UCA10 = 0, 7-bit addressing is selected. When UCA10 = 1, 10-bit addressing is selected. The UCGCEN bit selects if the USCI module responds to a general call. 17.3.4.2.1 I2C Master Transmitter Mode After initialization, master transmitter mode is initiated by writing the desired slave address to the UCBxI2CSA register, selecting the size of the slave address with the UCSLA10 bit, setting UCTR for transmitter mode, and setting UCTXSTT to generate a START condition. The USCI module checks if the bus is available, generates the START condition, and transmits the slave address. The UCBxTXIFG bit is set when the START condition is generated and the first data to be transmitted can be written into UCBxTXBUF. As soon as the slave acknowledges the address the UCTXSTT bit is cleared. The data written into UCBxTXBUF is transmitted if arbitration is not lost during transmission of the slave address. UCBxTXIFG is set again as soon as the data is transferred from the buffer into the shift register. If there is no data loaded to UCBxTXBUF before the acknowledge cycle, the bus is held during the acknowledge cycle with SCL low until data is written into UCBxTXBUF. Data is transmitted or the bus is held as long as the UCTXSTP bit or UCTXSTT bit is not set. Setting UCTXSTP will generate a STOP condition after the next acknowledge from the slave. If UCTXSTP is set during the transmission of the slave’s address or while the USCI module waits for data to be written into UCBxTXBUF, a STOP condition is generated even if no data was transmitted to the slave. When transmitting a single byte of data, the UCTXSTP bit must be set while the byte is being transmitted, or anytime after transmission begins, without writing new data into UCBxTXBUF. Otherwise, only the address will be transmitted. When the data is transferred from the buffer to the shift register, UCBxTXIFG will become set indicating data transmission has begun and the UCTXSTP bit may be set. Setting UCTXSTT will generate a repeated START condition. In this case, UCTR may be set or cleared to configure transmitter or receiver, and a different slave address may be written into UCBxI2CSA if desired. If the slave does not acknowledge the transmitted data the not-acknowledge interrupt flag UCNACKIFG is set. The master must react with either a STOP condition or a repeated START condition. If data was already written into UCBxTXBUF it will be discarded. If this data should be transmitted after a repeated START it must be written into UCBxTXBUF again. Any set UCTXSTT is discarded, too. To trigger a repeated start UCTXSTT needs to be set again. Figure 17-12 shows the I2C master transmitter operation. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 459 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: I2C Mode www.ti.com Successful transmission to a slave receiver S SLA/W A 1) UCTR=1 (Transmitter) 2) UCTXSTT=1 UCBxTXIFG=1 UCBxTXBUF discarded Next transfer started with a repeated start condition DATA A DATA UCTXSTT=0 UCBxTXIFG=1 Bus stalled (SCL held low) until data available Write data to UCBxTXBUF A DATA AP UCTXSTP=0 UCTXSTP=1 UCBxTXIFG=0 DATA A S SLA/W 1) UCTR=1 (Transmitter) 2) UCTXSTT=1 Not acknowledge received after slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave UCTXSTT=0 UCNACKIFG=1 UCBxTXIFG=0 UCBxTXBUF discarded UCTXSTP=1 DATA A S SLA/R 1) UCTR=0 (Receiver) 2) UCTXSTT=1 3) UCBxTXIFG=0 A P UCTXSTP=0 S SLA/W 1) UCTR=1 (Transmitter) 2) UCTXSTT=1 UCBxTXIFG=1 UCBxTXBUF discarded A S SLA/R UCNACKIFG=1 UCBxTXIFG=0 UCBxTXBUF discarded 1) UCTR=0 (Receiver) 2) UCTXSTT=1 Other master continues Other master continues UCALIFG=1 UCMST=0 (UCSTTIFG=0) UCALIFG=1 UCMST=0 (UCSTTIFG=0) A Other master continues UCALIFG=1 UCMST=0 UCTR=0 (Receiver) UCSTTIFG=1 (UCGC=1 if general call) UCBxTXIFG=0 UCSTPIFG=0 USCI continues as Slave Receiver Figure 17-12. I2C Master Transmitter Mode 460 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USCI Operation: I2C Mode 17.3.4.2.2 I2C Master Receiver Mode After initialization, master receiver mode is initiated by writing the desired slave address to the UCBxI2CSA register, selecting the size of the slave address with the UCSLA10 bit, clearing UCTR for receiver mode, and setting UCTXSTT to generate a START condition. The USCI module checks if the bus is available, generates the START condition, and transmits the slave address. As soon as the slave acknowledges the address the UCTXSTT bit is cleared. After the acknowledge of the address from the slave the first data byte from the slave is received and acknowledged and the UCBxRXIFG flag is set. Data is received from the slave ss long as UCTXSTP or UCTXSTT is not set. If UCBxRXBUF is not read the master holds the bus during reception of the last data bit and until the UCBxRXBUF is read. If the slave does not acknowledge the transmitted address the not-acknowledge interrupt flag UCNACKIFG is set. The master must react with either a STOP condition or a repeated START condition. Setting the UCTXSTP bit will generate a STOP condition. After setting UCTXSTP, a NACK followed by a STOP condition is generated after reception of the data from the slave, or immediately if the USCI module is currently waiting for UCBxRXBUF to be read. If a master wants to receive a single byte only, the UCTXSTP bit must be set while the byte is being received. For this case, the UCTXSTT may be polled to determine when it is cleared: POLL_STT BIS.B BIT.B JC BIS.B #UCTXSTT,&UCBOCTL1 #UCTXSTT,&UCBOCTL1 POLL_STT #UCTXSTP,&UCB0CTL1 ;Transmit START cond. ;Poll UCTXSTT bit ;When cleared, ;transmit STOP cond. Setting UCTXSTT will generate a repeated START condition. In this case, UCTR may be set or cleared to configure transmitter or receiver, and a different slave address may be written into UCBxI2CSA if desired. Figure 17-13 shows the I2C master receiver operation. NOTE: Consecutive Master Transactions Without Repeated Start When performing multiple consecutive I2C master transactions without the repeated start feature, the current transaction must be completed before the next one is initiated. This can be done by ensuring that the transmit stop condition flag UCTXSTP is cleared before the next I2C transaction is initiated with setting UCTXSTT = 1. Otherwise, the current transaction might be affected. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 461 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: I2C Mode Successful reception from a slave transmitter S SLA/R A DATA A DATA A 1) UCTR=0 (Receiver) 2) UCTXSTT=1 UCTXSTT=0 UCBxRXIFG=1 DATA AP UCTXSTP=1 UCTXSTP=0 www.ti.com Next transfer started with a repeated start condition Not acknowledge received after slave address Arbitration lost in slave address or data byte Arbitration lost and addressed as slave A UCTXSTT=0 UCNACKIFG=1 DATA A S SLA/W 1) UCTR=1 (Transmitter) 2) UCTXSTT=1 DATA A S SLA/R UCTXSTP=1 1) UCTR=0 (Receiver) 2) UCTXSTT=1 P UCTXSTP=0 S SLA/W S SLA/R 1) UCTR=1 (Transmitter) 2) UCTXSTT=1 UCBxTXIFG=1 1) UCTR=0 (Receiver) 2) UCTXSTT=1 Other master continues Other master continues UCALIFG=1 UCMST=0 (UCSTTIFG=0) UCALIFG=1 UCMST=0 (UCSTTIFG=0) A Other master continues UCALIFG=1 UCMST=0 UCTR=1 (Transmitter) UCSTTIFG=1 UCBxTXIFG=1 UCSTPIFG=0 USCI continues as Slave Transmitter Figure 17-13. I2C Master Receiver Mode 462 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USCI Operation: I2C Mode 17.3.4.2.3 I2C Master 10-Bit Addressing Mode The 10-bit addressing mode is selected when UCSLA10 = 1 and is shown in Figure 17-14. Master Transmitter Successful transmission to a slave receiver S 11110 xx/W A SLA (2.) A DATA A 1) UCTR=1 (Transmitter) 2) UCTXSTT=1 UCBxTXIFG=1 UCTXSTT=0 UCBxTXIFG=1 DATA AP UCTXSTP=1 UCTXSTP=0 Master Receiver Successful reception from a slave transmitter S 11110 xx/W A SLA (2.) A S 11110 xx/R A DATA A DATA AP 1) UCTR=0 (Receiver) 2) UCTXSTT=1 UCTXSTT=0 UCBxRXIFG=1 UCTXSTP=1 Figure 17-14. I2C Master 10-bit Addressing Mode UCTXSTP=0 17.3.4.2.4 Arbitration If two or more master transmitters simultaneously start a transmission on the bus, an arbitration procedure is invoked. Figure 17-15 shows the arbitration procedure between two devices. The arbitration procedure uses the data presented on SDA by the competing transmitters. The first master transmitter that generates a logic high is overruled by the opposing master generating a logic low. The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value. The master transmitter that lost arbitration switches to the slave receiver mode, and sets the arbitration lost flag UCALIFG. If two or more devices send identical first bytes, arbitration continues on the subsequent bytes. Bus Line SCL Data From Device 1 Data From Device 2 Bus Line SDA n 1 0 1 0 1 Device 1 Lost Arbitration and Switches Off 0 0 1 1 0 0 1 1 Figure 17-15. Arbitration Procedure Between Two Master Transmitters If the arbitration procedure is in progress when a repeated START condition or STOP condition is transmitted on SDA, the master transmitters involved in arbitration must send the repeated START condition or STOP condition at the same position in the format frame. Arbitration is not allowed between: • A repeated START condition and a data bit • A STOP condition and a data bit • A repeated START condition and a STOP condition SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 463 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: I2C Mode www.ti.com 17.3.5 I2C Clock Generation and Synchronization The I2C clock SCL is provided by the master on the I2C bus. When the USCI is in master mode, BITCLK is provided by the USCI bit clock generator and the clock source is selected with the UCSSELx bits. In slave mode the bit clock generator is not used and the UCSSELx bits are don’t care. The 16-bit value of UCBRx in registers UCBxBR1 and UCBxBR0 is the division factor of the USCI clock source, BRCLK. The maximum bit clock that can be used in single master mode is fBRCLK/4. In multi-master mode the maximum bit clock is fBRCLK/8. The BITCLK frequency is given by: fBitClock = fBRCLK UCBRx The minimum high and low periods of the generated SCL are UCBRx / 2 tLOW,MIN = tHIGH,MIN = fBRCLK when UCBRx is even and tLOW,MIN = tHIGH,MIN = (UCBRx – 1) / 2 fBRCLK when UCBRx is odd. The USCI clock source frequency and the prescaler setting UCBRx must to be chosen such that the minimum low and high period times of the I2C specification are met. During the arbitration procedure the clocks from the different masters must be synchronized. A device that first generates a low period on SCL overrules the other devices forcing them to start their own low periods. SCL is then held low by the device with the longest low period. The other devices must wait for SCL to be released before starting their high periods. Figure 17-16 shows the clock synchronization. This allows a slow slave to slow down a fast master. Wait State Start HIGH Period SCL From Device 1 SCL From Device 2 Bus Line SCL Figure 17-16. Synchronization of Two I2C Clock Generators During Arbitration 17.3.5.1 Clock Stretching The USCI module supports clock stretching and also makes use of this feature as described in the operation mode sections. The UCSCLLOW bit can be used to observe if another device pulls SCL low while the USCI module already released SCL due to the following conditions: • USCI is acting as master and a connected slave drives SCL low. • USCI is acting as master and another master drives SCL low during arbitration. The UCSCLLOW bit is also active if the USCI holds SCL low because it is waiting as transmitter for data being written into UCBxTXBUF or as receiver for the data being read from UCBxRXBUF. The UCSCLLOW bit might get set for a short time with each rising SCL edge because the logic observes the external SCL and compares it to the internally generated SCL. 464 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USCI Operation: I2C Mode 17.3.6 Using the USCI Module in I2C Mode with Low-Power Modes The USCI module provides automatic clock activation for SMCLK for use with low-power modes. When SMCLK is the USCI clock source, and is inactive because the device is in a low-power mode, the USCI module automatically activates it when needed, regardless of the control-bit settings for the clock source. The clock remains active until the USCI module returns to its idle condition. After the USCI module returns to the idle condition, control of the clock source reverts to the settings of its control bits. Automatic clock activation is not provided for ACLK. When the USCI module activates an inactive clock source, the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected. For example, a timer using SMCLK will increment while the USCI module forces SMCLK active. In I2C slave mode no internal clock source is required because the clock is provided by the external master. It is possible to operate the USCI in I2C slave mode while the device is in LPM4 and all internal clock sources are disabled. The receive or transmit interrupts can wake up the CPU from any low power mode. 17.3.7 USCI Interrupts in I2C Mode There are two interrupt vectors for the USCI module in I2C mode. One interrupt vector is associated with the transmit and receive interrupt flags. The other interrupt vector is associated with the four state change interrupt flags. Each interrupt flag has its own interrupt enable bit. When an interrupt is enabled, and the GIE bit is set, the interrupt flag will generate an interrupt request. DMA transfers are controlled by the UCBxTXIFG and UCBxRXIFG flags on devices with a DMA controller. 17.3.7.1 I2C Transmit Interrupt Operation The UCBxTXIFG interrupt flag is set by the transmitter to indicate that UCBxTXBUF is ready to accept another character. An interrupt request is generated if UCBxTXIE and GIE are also set. UCBxTXIFG is automatically reset if a character is written to UCBxTXBUF or if a NACK is received. UCBxTXIFG is set when UCSWRST = 1 and the I2C mode is selected. UCBxTXIE is reset after a PUC or when UCSWRST = 1. 17.3.7.2 I2C Receive Interrupt Operation The UCBxRXIFG interrupt flag is set when a character is received and loaded into UCBxRXBUF. An interrupt request is generated if UCBxRXIE and GIE are also set. UCBxRXIFG and UCBxRXIE are reset after a PUC signal or when UCSWRST = 1. UCxRXIFG is automatically reset when UCxRXBUF is read. 17.3.7.3 I2C State Change Interrupt Operation Table 17-1 describes the I2C state change interrupt flags. Interrupt Flag UCALIFG UCNACKIFG UCSTTIFG UCSTPIFG Table 17-1. State Change Interrupt Flags Interrupt Condition Arbitration-lost. Arbitration can be lost when two or more transmitters start a transmission simultaneously, or when the USCI operates as master but is addressed as a slave by another master in the system. The UCALIFG flag is set when arbitration is lost. When UCALIFG is set the UCMST bit is cleared and the I2C controller becomes a slave. Not-acknowledge interrupt. This flag is set when an acknowledge is expected but is not received. UCNACKIFG is automatically cleared when a START condition is received. Start condition detected interrupt. This flag is set when the I2C module detects a START condition together with its own address while in slave mode. UCSTTIFG is used in slave mode only and is automatically cleared when a STOP condition is received. Stop condition detected interrupt. This flag is set when the I2C module detects a STOP condition while in slave mode. UCSTPIFG is used in slave mode only and is automatically cleared when a START condition is received. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Universal Serial Communication Interface, I2C Mode 465 Copyright © 2004–2013, Texas Instruments Incorporated USCI Operation: I2C Mode www.ti.com 17.3.7.4 Interrupt Vector Assignment USCI_Ax and USCI_Bx share the same interrupt vectors. In I2C mode the state change interrupt flags UCSTTIFG, UCSTPIFG, UCNACKIFG, UCALIFG from USCI_Bx and UCAxRXIFG from USCI_Ax are routed to one interrupt vector. The I2C transmit and receive interrupt flags UCBxTXIFG and UCBxRXIFG from USCI_Bx and UCAxTXIFG from USCI_Ax share another interrupt vector. Example 17-1 shows an extract of the interrupt service routine to handle data receive interrupts from USCI_A0 in either UART or SPI mode and state change interrupts from USCI_B0 in I2C mode. Example 17-1. Shared Receive Interrupt Vectors Software Example USCIA0_RX_USCIB0_I2C_STATE_ISR BIT.B #UCA0RXIFG, &IFG2 ; USCI_A0 Receive Interrupt? JNZ USCIA0_RX_ISR USCIB0_I2C_STATE_ISR ; Decode I2C state changes ... ; Decode I2C state changes ... ... RETI USCIA0_RX_ISR ; Read UCA0RXBUF ... - clears UCA0RXIFG ... RETI Example 17-2 shows an extract of the interrupt service routine that handles data transmit interrupts from USCI_A0 in either UART or SPI mode and the data transfer interrupts from USCI_B0 in I2C mode. Example 17-2. Shared Transmit Interrupt Vectors Software Example USCIA0_TX_USCIB0_I2C_DATA_ISR BIT.B #UCA0TXIFG, &IFG2 ; USCI_A0 Transmit Interrupt? JNZ USCIA0_TX_ISR USCIB0_I2C_DATA_ISR BIT.B #UCB0RXIFG, &IFG2 JNZ USCIB0_I2C_RX USCIB0_I2C_TX ; Write UCB0TXBUF... - clears UCB0TXIFG ... RETI USCIB0_I2C_RX ; Read UCB0RXBUF... - clears UCB0RXIFG ... RETI USCIA0_TX_ISR ; Write UCA0TXBUF ... - clears UCA0TXIFG ... RETI 466 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USCI Registers: I2C Mode 17.4 USCI Registers: I2C Mode The USCI registers applicable in I2C mode for USCI_B0 are listed in Table 17-2, and for USCI_B1 in Table 17-3. Table 17-2. USCI_B0 Control and Status Registers Register USCI_B0 control register 0 USCI_B0 control register 1 USCI_B0 bit rate control register 0 USCI_B0 bit rate control register 1 USCI_B0 I2C interrupt enable register USCI_B0 status register USCI_B0 receive buffer register USCI_B0 transmit buffer register USCI_B0 I2C own address register USCI_B0 I2C slave address register SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form UCB0CTL0 UCB0CTL1 UCB0BR0 UCB0BR1 UCB0I2CIE UCB0STAT UCB0RXBUF UCB0TXBUF UCB0I2COA UCB0I2CSA IE2 IFG2 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Read/write Read/write Address 068h 069h 06Ah 06Bh 06Ch 06Dh 06Eh 06Fh 0118h 011Ah 001h 003h Initial State 001h with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC NOTE: Modifying SFR bits To avoid modifying control bits of other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. Table 17-3. USCI_B1 Control and Status Registers Register USCI_B1 control register 0 USCI_B1 control register 1 USCI_B1 baud rate control register 0 USCI_B1 baud rate control register 1 USCI_B1 I2C interrupt enable register USCI_B1 status register USCI_B1 receive buffer register USCI_B1 transmit buffer register USCI_B1 I2C own address register USCI_B1 I2C slave address register USCI_A1/B1 interrupt enable register USCI_A1/B1 interrupt flag register Short Form UCB1CTL0 UCB1CTL1 UCB1BR0 UCB1BR1 UCB1I2CIE UCB1STAT UCB1RXBUF UCB1TXBUF UCB1I2COA UCB1I2CSA UC1IE UC1IFG Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Read/write Read/write Address 0D8h 0D9h 0DAh 0DBh 0DCh 0DDh 0DEh 0DFh 017Ch 017Eh 006h 007h Initial State Reset with PUC 001h with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC Reset with PUC 00Ah with PUC SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 467 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: I2C Mode 17.4.1 UCBxCTL0, USCI_Bx Control Register 0 www.ti.com 7 UCA10 rw-0 UCA10 UCSLA10 UCMM Unused UCMST UCMODEx UCSYNC 6 UCSLA10 rw-0 5 UCMM rw-0 4 Unused rw-0 3 UCMST rw-0 2 1 UCMODEx=11 rw-0 rw-0 0 UCSYNC=1 r-1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bits 2-1 Bit 0 Own addressing mode select 0 Own address is a 7-bit address 1 Own address is a 10-bit address Slave addressing mode select 0 Address slave with 7-bit address 1 Address slave with 10-bit address Multi-master environment select 0 Single master environment. There is no other master in the system. The address compare unit is disabled. 1 Multi-master environment Unused Master mode select. When a master loses arbitration in a multi-master environment (UCMM = 1) the UCMST bit is automatically cleared and the module acts as slave. 0 Slave mode 1 Master mode USCI Mode. The UCMODEx bits select the synchronous mode when UCSYNC = 1. 00 3-pin SPI 01 4-pin SPI (master/slave enabled if STE = 1) 10 4-pin SPI (master/slave enabled if STE = 0) 11 I2C mode Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode 468 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com 17.4.2 UCBxCTL1, USCI_Bx Control Register 1 USCI Registers: I2C Mode 7 6 UCSSELx rw-0 rw-0 UCSSELx Bits 7-6 Unused UCTR Bit 5 Bit 4 UCTXNACK Bit 3 UCTXSTP Bit 2 UCTXSTT Bit 1 UCSWRST Bit 0 5 Unused r0 4 UCTR rw-0 3 UCTXNACK rw-0 2 UCTXSTP rw-0 1 UCTXSTT rw-0 0 UCSWRST rw-1 USCI clock source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK Unused Transmitter/receiver 0 Receiver 1 Transmitter Transmit a NACK. UCTXNACK is automatically cleared after a NACK is transmitted. 0 Acknowledge normally 1 Generate NACK Transmit STOP condition in master mode. Ignored in slave mode. In master receiver mode the STOP condition is preceded by a NACK. UCTXSTP is automatically cleared after STOP is generated. 0 No STOP generated 1 Generate STOP Transmit START condition in master mode. Ignored in slave mode. In master receiver mode a repeated START condition is preceded by a NACK. UCTXSTT is automatically cleared after START condition and address information is transmitted. Ignored in slave mode. 0 Do not generate START condition 1 Generate START condition Software reset enable 0 Disabled. USCI reset released for operation. 1 Enabled. USCI logic held in reset state. 17.4.3 UCBxBR0, USCI_Bx Baud Rate Control Register 0 7 6 5 4 3 2 1 0 UCBRx - low byte rw rw rw rw rw rw rw rw 17.4.4 UCBxBR1, USCI_Bx Baud Rate Control Register 1 7 rw UCBRx 6 5 4 3 2 1 0 UCBRx - high byte rw rw rw rw rw rw rw Bit clock prescaler setting. The 16-bit value of (UCBxBR0 + UCBxBR1 × 256) forms the prescaler value. SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 469 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: I2C Mode 17.4.5 UCBxSTAT, USCI_Bx Status Register www.ti.com 7 Unused rw-0 Unused UCSCLLOW UCGC UCBBUSY UCNACKIFG UCSTPIFG UCSTTIFG UCALIFG 6 UCSCLLOW r-0 5 UCGC rw-0 4 UCBBUSY r-0 3 UCNACKIFG rw-0 2 UCSTPIFG rw-0 1 UCSTTIFG rw-0 0 UCALIFG rw-0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unused. SCL low 0 SCL is not held low 1 SCL is held low General call address received. UCGC is automatically cleared when a START condition is received. 0 No general call address received 1 General call address received Bus busy 0 Bus inactive 1 Bus busy Not-acknowledge received interrupt flag. UCNACKIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending Stop condition interrupt flag. UCSTPIFG is automatically cleared when a START condition is received. 0 No interrupt pending 1 Interrupt pending Start condition interrupt flag. UCSTTIFG is automatically cleared if a STOP condition is received. 0 No interrupt pending 1 Interrupt pending Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending 17.4.6 UCBxRXBUF, USCI_Bx Receive Buffer Register 7 r UCRXBUFx 6 r Bits 7-0 5 4 3 2 1 0 UCRXBUFx r r r r r r The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UCBxRXBUF resets UCBxRXIFG. 17.4.7 UCBxTXBUF, USCI_Bx Transmit Buffer Register 7 rw UCTXBUFx 6 rw Bits 7-0 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted. Writing to the transmit data buffer clears UCBxTXIFG. 470 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com 17.4.8 UCBxI2COA, USCIBx I2C Own Address Register USCI Registers: I2C Mode 15 UCGCEN rw-0 7 rw-0 UCGCEN I2COAx 14 0 r0 6 rw-0 Bit 15 Bits 9-0 13 12 11 10 9 8 0 0 0 0 I2COAx r0 r0 r0 r0 rw-0 rw-0 5 4 3 2 1 0 I2COAx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 General call response enable 0 Do not respond to a general call 1 Respond to a general call I2C own address. The I2COAx bits contain the local address of the USCI_Bx I2C controller. The address is right-justified. In 7-bit addressing mode, bit 6 is the MSB, and bits 9-7 are ignored. In 10-bit addressing mode, bit 9 is the MSB. 17.4.9 UCBxI2CSA, USCI_Bx I2C Slave Address Register 15 0 r0 7 rw-0 I2CSAx 14 13 12 11 10 9 8 0 0 0 0 0 I2CSAx r0 r0 r0 r0 r0 rw-0 rw-0 6 rw-0 Bits 9-0 5 4 3 2 1 0 I2CSAx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 I2C slave address. The I2CSAx bits contain the slave address of the external device to be addressed by the USCI_Bx module. It is only used in master mode. The address is right-justified. In 7-bit slave addressing mode, bit 6 is the MSB, and bits 9-7 are ignored. In 10-bit slave addressing mode, bit 9 is the MSB. 17.4.10 UCBxI2CIE, USCI_Bx I2C Interrupt Enable Register 7 rw-0 Reserved UCNACKIE UCSTPIE UCSTTIE UCALIE 6 5 4 Reserved rw-0 rw-0 rw-0 Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Not-acknowledge interrupt enable 0 Interrupt disabled 1 Interrupt enabled Stop condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled Start condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled Arbitration lost interrupt enable 0 Interrupt disabled 1 Interrupt enabled 3 UCNACKIE rw-0 2 UCSTPIE rw-0 1 UCSTTIE rw-0 0 UCALIE rw-0 SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 471 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USCI Registers: I2C Mode 17.4.11 IE2, Interrupt Enable Register 2 7 UCB0TXIE UCB0RXIE 6 Bits 7-4 Bit 3 Bit 2 Bits 1-0 5 4 3 2 1 UCB0TXIE UCB0RXIE rw-0 rw-0 These bits may be used by other modules (see the device-specific data sheet). USCI_B0 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B0 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled These bits may be used by other modules (see the device-specific data sheet). www.ti.com 0 17.4.12 IFG2, Interrupt Flag Register 2 7 UCB0TXIFG UCB0RXIFG 6 Bits 7-4 Bit 3 Bit 2 Bits 1-0 5 4 3 2 1 0 UCB0TXIFG UCB0RXIFG rw-1 rw-0 These bits may be used by other modules (see the device-specific data sheet). USCI_B0 transmit interrupt flag. UCB0TXIFG is set when UCB0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_B0 receive interrupt flag. UCB0RXIFG is set when UCB0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules (see the device-specific data sheet). 17.4.13 UC1IE, USCI_B1 Interrupt Enable Register 7 6 5 4 3 2 1 0 Unused UCB1TXIE UCB1RXIE rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Unused UCB1TXIE UCB1RXIE Bits 7-4 Bit 3 Bit 2 Bits 1-0 Unused USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled These bits may be used by other USCI modules (see the device-specific data sheet). 472 Universal Serial Communication Interface, I2C Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com 17.4.14 UC1IFG, USCI_B1 Interrupt Flag Register USCI Registers: I2C Mode 7 rw-0 Unused UCB1TXIFG UCB1RXIFG 6 5 4 3 2 1 0 Unused UCB1TXIFG UCB1RXIFG rw-0 rw-0 rw-0 rw-1 rw-0 Bits 7-4 Bit 3 Bit 2 Bits 1-0 Unused. USCI_B1 transmit interrupt flag. UCB1TXIFG is set when UCB1TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USCI_B1 receive interrupt flag. UCB1RXIFG is set when UCB1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules (see the device-specific data sheet). SLAU144J – December 2004 – Revised July 2013 Universal Serial Communication Interface, I2C Mode 473 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Chapter 18 SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the asynchronous UART mode. USART0 is implemented on the MSP430AFE2xx devices. Topic ........................................................................................................................... Page 18.1 USART Introduction: UART Mode ...................................................................... 475 18.2 USART Operation: UART Mode ......................................................................... 476 18.3 USART Registers: UART Mode .......................................................................... 490 474 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Introduction: UART Mode 18.1 USART Introduction: UART Mode In asynchronous mode, the USART connects the MSP430 to an external system via two external pins, URXD and UTXD. UART mode is selected when the SYNC bit is cleared. UART mode features include: • 7- or 8-bit data with odd parity, even parity, or non-parity • Independent transmit and receive shift registers • Separate transmit and receive buffer registers • LSB-first data transmit and receive • Built-in idle-line and address-bit communication protocols for multiprocessor systems • Receiver start-edge detection for auto-wake up from LPMx modes • Programmable baud rate with modulation for fractional baud rate support • Status flags for error detection and suppression and address detection • Independent interrupt capability for receive and transmit Figure 18-1 shows the USART when configured for UART mode. SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 475 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: UART Mode FE PE OE BRK SWRST URXEx* URXEIE URXWIE Receive Control URXIFGx* www.ti.com SYNC= 0 Receive Status Receiver Buffer UxRXBUF RXERR RXWAKE Receiver Shift Register SSEL1 SSEL0 SPB CHAR PEV PENA UCLKI 00 ACLK 01 SMCLK 10 SMCLK 11 Baud−Rate Generator Prescaler/Divider UxBRx Modulator UxMCTL UCLKS SPB CHAR PEV PENA LISTEN 0 1 MM SYNC 1 1 SOMI 0 0 1 URXD 0 STE UTXD WUT Transmit Shift Register TXWAKE Transmit Buffer UxTXBUF 1 1 0 0 SIMO UTXIFGx* Transmit Control SWRST UTXEx* TXEPT UCLKI STC SYNC CKPH CKPL Clock Phase and Polarity UCLK * See the device-specific data sheet for SFR locations. Figure 18-1. USART Block Diagram: UART Mode 18.2 USART Operation: UART Mode In UART mode, the USART transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USART. The transmit and receive functions use the same baud rate frequency. 18.2.1 USART Initialization and Reset The USART is reset by a PUC or by setting the SWRST bit. After a PUC, the SWRST bit is automatically set, keeping the USART in a reset condition. When set, the SWRST bit resets the URXIEx, UTXIEx, URXIFGx, RXWAKE, TXWAKE, RXERR, BRK, PE, OE, and FE bits and sets the UTXIFGx and TXEPT bits. The receive and transmit enable flags, URXEx and UTXEx, are not altered by SWRST. Clearing SWRST releases the USART for operation. See also chapter USART Module, I2C mode for USART0 when reconfiguring from I2C mode to UART mode. 476 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: UART Mode NOTE: Initializing or Reconfiguring the USART Module The required USART initialization/reconfiguration process is: 1. Set SWRST (BIS.B #SWRST,&UxCTL) 2. Initialize all USART registers with SWRST = 1 (including UxCTL) 3. Enable USART module via the MEx SFRs (URXEx and/or UTXEx) 4. Clear SWRST via software (BIC.B #SWRST,&UxCTL) 5. Enable interrupts (optional) via the IEx SFRs (URXIEx and/or UTXIEx) Failure to follow this process may result in unpredictable USART behavior. 18.2.2 Character Format The UART character format, shown in Figure 18-2, consists of a start bit, seven or eight data bits, an even/odd/no parity bit, an address bit (address-bit mode), and one or two stop bits. The bit period is defined by the selected clock source and setup of the baud rate registers. ST D0 D6 D7 AD PA SP SP Mark Space [Optional Bit, Condition] [2nd Stop Bit, SPB = 1] [Parity Bit, PENA = 1] [Address Bit, MM = 1] [8th Data Bit, CHAR = 1] Figure 18-2. Character Format 18.2.3 Asynchronous Communication Formats When two devices communicate asynchronously, the idle-line format is used for the protocol. When three or more devices communicate, the USART supports the idle-line and address-bit multiprocessor communication formats. 18.2.3.1 Idle-Line Multiprocessor Format When MM = 0, the idle-line multiprocessor format is selected. Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 18-3. An idle receive line is detectedwhen 10 or more continuous ones (marks) are received after the first stop bit of a character. When two stop bits are used for the idle line the second stop bit is counted as the first mark bit of the idle period. The first character received after an idle period is an address character. The RXWAKE bit is used as an address tag for each block of characters. In the idle-line multiprocessor format, this bit is set when a received character is an address and is transferred to UxRXBUF. SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 477 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: UART Mode UTXDx/URXDx UTXDx/URXDx Expanded Blocks of Characters Idle Periods of 10 Bits or More www.ti.com UTXDx/URXDx ST Address SP ST Data SP ST Data SP First Character Within Block Is Address. It Follows Idle Period of 10 Bits or More Character Within Block Character Within Block Idle Period Less Than 10 Bits Figure 18-3. Idle-Line Format The URXWIE bit is used to control data reception in the idle-line multiprocessor format. When the URXWIE bit is set, all non-address characters are assembled but not transferred into the UxRXBUF, and interrupts are not generated. When an address character is received, the receiver is temporarily activated to transfer the character to UxRXBUF and sets the URXIFGx interrupt flag. Any applicable error flag is also set. The user can then validate the received address. If an address is received, user software can validate the address and must reset URXWIE to continue receiving data. If URXWIE remains set, only address characters are received. The URXWIE bit is not modified by the USART hardware automatically. For address transmission in idle-line multiprocessor format, a precise idle period can be generated by the USART to generate address character identifiers on UTXDx. The wake-up temporary (WUT) flag is an internal flag double-buffered with the user-accessible TXWAKE bit. When the transmitter is loaded from UxTXBUF, WUT is also loaded from TXWAKE resetting the TXWAKE bit. The following procedure sends out an idle frame to indicate an address character follows: 1. Set TXWAKE, then write any character to UxTXBUF. UxTXBUF must be ready for new data (UTXIFGx = 1). The TXWAKE value is shifted to WUT and the contents of UxTXBUF are shifted to the transmit shift register when the shift register is ready for new data. This sets WUT, which suppresses the start, data, and parity bits of a normal transmission, then transmits an idle period of exactly 11 bits. When two stop bits are used for the idle line, the second stop bit is counted as the first mark bit of the idle period. TXWAKE is reset automatically. 2. Write desired address character to UxTXBUF. UxTXBUF must be ready for new data (UTXIFGx = 1). The new character representing the specified address is shifted out following the address-identifying idle period on UTXDx. Writing the first "don't care" character to UxTXBUF is necessary in order to shift the TXWAKE bit to WUT and generate an idle-line condition. This data is discarded and does not appear on UTXDx. 18.2.3.2 Address-Bit Multiprocessor Format When MM = 1, the address-bit multiprocessor format is selected. Each processed character contains an extra bit used as an address indicator shown in Figure 18-4. The first character in a block of characters carries a set address bit which indicates that the character is an address. The USART RXWAKE bit is set when a received character is a valid address character and is transferred to UxRXBUF. 478 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: UART Mode The URXWIE bit is used to control data reception in the address-bit multiprocessor format. If URXWIE is set, data characters (address bit = 0) are assembled by the receiver but are not transferred to UxRXBUF and no interrupts are generated. When a character containing a set address bit is received, the receiver is temporarily activated to transfer the character to UxRXBUF and set URXIFGx. All applicable error status flags are also set. If an address is received, user software must reset URXWIE to continue receiving data. If URXWIE remains set, only address characters (address bit = 1) are received. The URXWIE bit is not modified by the USART hardware automatically. Blocks of Characters UTXDx/URXDx UTXDx/URXDx Expanded Idle Periods of No Significance UTXDx/URXDx ST Address 1 SP ST Data 0 SP ST Data 0 SP First Character Within Block Is an Address. AD Bit Is 1 AD Bit Is 0 for Data Within Block. Idle Time Is of No Significance Figure 18-4. Address-Bit Multiprocessor Format For address transmission in address-bit multiprocessor mode, the address bit of a character can be controlled by writing to the TXWAKE bit. The value of the TXWAKE bit is loaded into the address bit of the character transferred from UxTXBUF to the transmit shift register, automatically clearing the TXWAKE bit. TXWAKE must not be cleared by software. It is cleared by USART hardware after it is transferred to WUT or by setting SWRST. 18.2.3.3 Automatic Error Detection Glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time tτ (approximately 300 ns) is ignored. See the device-specific data sheet for parameters. When a low period on URXDx exceeds tτ a majority vote is taken for the start bit. If the majority vote fails to detect a valid start bit the USART halts character reception and waits for the next low period on URXDx. The majority vote is also used for each bit in a character to prevent bit errors. The USART module automatically detects framing errors, parity errors, overrun errors, and break conditions when receiving characters. The bits FE, PE, OE, and BRK are set when their respective condition is detected. When any of these error flags are set, RXERR is also set. The error conditions are described in Table 18-1. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback USART Peripheral Interface, UART Mode 479 Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: UART Mode Error Condition Framing error Parity error Receive overrun error Break condition www.ti.com Table 18-1. Receive Error Conditions Description A framing error occurs when a low stop bit is detected. When two stop bits are used, only the first stop bit is checked for framing error. When a framing error is detected, the FE bit is set. A parity error is a mismatch between the number of 1s in a character and the value of the parity bit. When an address bit is included in the character, it is included in the parity calculation. When a parity error is detected, the PE bit is set. An overrun error occurs when a character is loaded into UxRXBUF before the prior character has been read. When an overrun occurs, the OE bit is set. A break condition is a period of 10 or more low bits received on URXDx after a missing stop bit. When a break condition is detected, the BRK bit is set. A break condition can also set the interrupt flag URXIFGx when URXEIE = 0. When URXEIE = 0 and a framing error, parity error, or break condition is detected, no character is received into UxRXBUF. When URXEIE = 1, characters are received into UxRXBUF and any applicable error bit is set. When any of the FE, PE, OE, BRK, or RXERR bits are set, the bit remains set until user software resets it or UxRXBUF is read. 18.2.4 USART Receive Enable The receive enable bit, URXEx, enables or disables data reception on URXDx as shown in Figure 18-5. Disabling the USART receiver stops the receive operation following completion of any character currently being received or immediately if no receive operation is active. The receive-data buffer, UxRXBUF, contains the character moved from the RX shift register after the character is received. URXEx = 0 No Valid Start Bit Not Completed Receive Disable URXEx = 1 URXEx = 0 Idle State (Receiver Enabled) URXEx = 1 Valid Start Bit URXEx = 1 URXEx = 0 Receiver Collects Character Handle Interrupt Conditions Character Received Figure 18-5. State Diagram of Receiver Enable NOTE: Re-Enabling the Receiver (Setting URXEx): UART Mode When the receiver is disabled (URXEx = 0), re-enabling the receiver (URXEx = 1) is asynchronous to any data stream that may be present on URXDx at the time. Synchronization can be performed by testing for an idle line condition before receiving a valid character (see URXWIE). 18.2.5 USART Transmit Enable When UTXEx is set, the UART transmitter is enabled. Transmission is initiated by writing data to UxTXBUF. The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty, and transmission begins. This process is shown in Figure 18-6. When the UTXEx bit is reset the transmitter is stopped. Any data moved to UxTXBUF and any active transmission of data currently in the transmit shift register prior to clearing UTXEx continue until all data transmission is completed. 480 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: UART Mode UTXEx = 0 Transmit Disable UTXEx = 1 UTXEx = 0 No Data Written to Transmit Buffer Idle State (Transmitter Enabled) UTXEx = 1 Data Written to Transmit Buffer Not Completed Transmission Active Handle Interrupt Conditions UTXEx = 1 Character Transmitted UTXEx = 0 And Last Buffer Entry Is Transmitted Figure 18-6. State Diagram of Transmitter Enable When the transmitter is enabled (UTXEx = 1), data should not be written to UxTXBUF unless it is ready for new data indicated by UTXIFGx = 1. Violation can result in an erroneous transmission if data in UxTXBUF is modified as it is being moved into the TX shift register. It is recommended that the transmitter be disabled (UTXEx = 0) only after any active transmission is complete. This is indicated by a set transmitter empty bit (TXEPT = 1). Any data written to UxTXBUF while the transmitter is disabled are held in the buffer but are not moved to the transmit shift register or transmitted. Once UTXEx is set, the data in the transmit buffer is immediately loaded into the transmit shift register and character transmission resumes. 18.2.6 USART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non-standard source frequencies. The baud rate generator uses one prescaler/divider and a modulator as shown in Figure 187. This combination supports fractional divisors for baud rate generation. The maximum USART baud rate is one-third the UART source clock frequency BRCLK. SSEL1 SSEL0 N = 215 ... 28 27 ... 20 UCLKI ACLK SMCLK SMCLK 00 01 BRCLK 10 11 UxBR1 UxBR0 8 8 16−Bit Counter R Q15 ............ Q0 +0 or 1 Compare (0 or 1) Toggle FF R BITCLK Modulation Data Shift Register R (LSB first) mX m7 8 m0 UxMCTL Bit Start Figure 18-7. MSP430 Baud Rate Generator Timing for each bit is shown in Figure 18-8. For each bit received, a majority vote is taken to determine the bit value. These samples occur at the N/2-1, N/2, and N/2+1 BRCLK periods, where N is the number of BRCLKs per BITCLK. SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 481 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: UART Mode www.ti.com Bit Start BRCLK Counter BITCLK Majority Vote: (m= 0) (m= 1) N/2 N/2−1 N/2−2 1 N/2 N/2−1 N/2−2 1 0 N/2 N/2−1 1 N/2 N/2−1 1 0 N/2 INT(N/2) + m(= 0) INT(N/2) + m(= 1) NEVEN: INT(N/2) NODD : INT(N/2) + R(= 1) m: corresponding modulation bit R: Remainder from N/2 division Bit Period Figure 18-8. BITCLK Baud Rate Timing 18.2.6.1 Baud Rate Bit Timing The first stage of the baud rate generator is the 16-bit counter and comparator. At the beginning of each bit transmitted or received, the counter is loaded with INT(N/2) where N is the value stored in the combination of UxBR0 and UxBR1. The counter reloads INT(N/2) for each bit period half-cycle, giving a total bit period of N BRCLKs. For a given BRCLK clock source, the baud rate used determines the required division factor N: BRCLK N= Baud Rate The division factor N is often a non-integer value of which the integer portion can be realized by the prescaler/divider. The second stage of the baud rate generator, the modulator, is used to meet the fractional part as closely as possible. The factor N is then defined as: n–1 å 1 N = UxBR + n mi i=0 Where, N = Target division factor UxBR = 16-bit representation of registers UxBR0 and UxBR1 i = Bit position in the character n = Total number of bits in the character mi = Data of each corresponding modulation bit (1 or 0) BRCLK BRCLK Baud rate = + N n–1 å 1 UxBR + n mi i=0 The BITCLK can be adjusted from bit to bit with the modulator to meet timing requirements when a noninteger divisor is needed. Timing of each bit is expanded by one BRCLK clock cycle if the modulator bit mi is set. Each time a bit is received or transmitted, the next bit in the modulation control register determines the timing for that bit. A set modulation bit increases the division factor by one while a cleared modulation bit maintains the division factor given by UxBR. The timing for the start bit is determined by UxBR plus m0, the next bit is determined by UxBR plus m1, and so on. The modulation sequence begins with the LSB. When the character is greater than 8 bits, the modulation sequence restarts with m0 and continues until all bits are processed. 482 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: UART Mode 18.2.6.2 Determining the Modulation Value Determining the modulation value is an interactive process. Using the timing error formula provided, beginning with the start bit , the individual bit errors are calculated with the corresponding modulator bit set and cleared. The modulation bit setting with the lower error is selected and the next bit error is calculated. This process is continued until all bit errors are minimized. When a character contains more than 8 bits, the modulation bits repeat. For example, the ninth bit of a character uses modulation bit 0. 18.2.6.3 Transmit Bit Timing The timing for each character is the sum of the individual bit timings. By modulating each bit, the cumulative bit error is reduced. The individual bit error can be calculated by: å ì é jù ü Error [%] = ï í baud rate îï BRCLK × êê(j + 1) × UxBR + êë mi ú ú i=0 úû ï – (j + 1)ý þï × 100% Where, baud rate = Desired baud rate BRCLK = Input frequency - UCLKI, ACLK, or SMCLK j = Bit position - 0 for the start bit, 1 for data bit D0, and so on UxBR = Division factor in registers UxBR1 and UxBR0 For example, the transmit errors for the following conditions are calculated: Baud rate = 2400 BRCLK = 32 768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.65 UxMCTL = 6Bh: m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1, and m0 = 1. The LSB of UxMCTL is used first. SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 483 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: UART Mode ( ) Start bit Error [%]= bBaRudCrLaKte×((0+1)×UxBR+1)–1 ×100%=2.54% ( ) Data bit D0 Error [%]= bBaRudCrLaKte×((1+1)×UxBR+2)–2 ×100%=5.08% ( ) Data bit D1 Error [%]= bBaRudCrLaKte×((2+1)×UxBR+2)–3 ×100%=0.29% ( ) Data bit D2 Error [%]= bBaRudCrLaKte×((3+1)×UxBR+3)–4 ×100%=2.83% ( ) Data bit D3 Error [%]= bBaRudCrLaKte×((4+1)×UxBR+3)–5 ×100%=-1.95% ( ) Data bit D4 Error [%]= bBaRudCrLaKte×((5+1)×UxBR+4)–6 ×100%=0.59% ( ) Data bit D5 Error [%]= bBaRudCrLaKte×((6+1)×UxBR+5)–7 ×100%=3.13% ( ) Data bit D6 Error [%]= bBaRudCrLaKte×((7+1)×UxBR+5)–8 ×100%=-1.66% ( ) Data bit D7 Error [%]= bBaRudCrLaKte×((8+1)×UxBR+6)–9 ×100%=0.88% ( ) Parity bit Error [%]= bBaRudCrLaKte×((9+1)×UxBR+7)–10 ×100%=3.42% ( ) Stop bit 1 Error [%]= bBaRudCrLaKte×((10+1)×UxBR+7)–11 ×100%=-1.37% The results show the maximum per-bit error to be 5.08% of a BITCLK period. www.ti.com 484 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: UART Mode 18.2.6.4 Receive Bit Timing Receive timing is subject to two error sources. The first is the bit-to-bit timing error. The second is the error between a start edge occurring and the start edge being accepted by the USART. Figure 18-9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud-rate clock. i tideal BRCLK 0 1 2 t0 t1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 URXDx ST D0 D1 URXDS ST D0 D1 tactual t0 t1 t2 Synchronization Error ± 0.5x BRCLK Sample URXDS Int(UxBR/2)+m0 = Int (13/2)+1 = 6+1 = 7 UxBR +m1 = 13+1 = 14 UxBR +m2 = 13+0 = 13 Majority Vote Taken Majority Vote Taken Majority Vote Taken Figure 18-9. Receive Error The ideal start bit timing tideal(0) is half the baud-rate timing tbaudrate, because the bit is tested in the middle of its period. The ideal baud-rate timing tideal(i) for the remaining character bits is the baud rate timing tbaudrate. The individual bit errors can be calculated by: å Error [%] = ì ï í baud rate ï BRCLK î × æ ç ç2 × çè é êm0 ë + æ int çè UxBR 2 öù ÷øúû + é êêi × UxBR + êë j i=1 mi ù ú ú úû ö ÷ ÷ ÷ø ü ï – 1 – jý ï þ × 100% Where, baud rate = the required baud rate BRCLK = the input frequency; selected for UCLK, ACLK, or SMCLK j = 0 for the start bit, 1 for data bit D0, and so on UxBR = the division factor in registers UxBR1 and UxBR0 For example, the receive errors for the following conditions are calculated: Baud rate = 2400 BRCLK = 32 768 Hz (ACLK) UxBR = 13, since the ideal division factor is 13.65 UxMCTL = 6B: m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1 and m0 = 1. The LSB of UxMCTL is used first. SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 485 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: UART Mode ( ) Data bit D1 Error [%]= bBaRudCrLaKte×[2x(1+6)+2×UxBR+1]-1-2 ×100%=0.29% www.ti.com ( ) Data bit D2 Error [%]= bBaRudCrLaKte×[2x(1+6)+3×UxBR+2]-1-3 ×100%=2.83% ( ) Data bit D3 Error [%]= bBaRudCrLaKte×[2x(1+6)+4×UxBR+2]-1-4 ×100%=-1.95% ( ) Data bit D4 Error [%]= bBaRudCrLaKte×[2x(1+6)+5×UxBR+3]-1-5 ×100%=0.59% ( ) Data bit D5 Error [%]= bBaRudCrLaKte×[2x(1+6)+6×UxBR+4]-1-6 ×100%=3.13% ( ) Data bit D6 Error [%]= bBaRudCrLaKte×[2x(1+6)+7×UxBR+4]-1-7 ×100%=-1.66% ( ) Data bit D7 Error [%]= bBaRudCrLaKte×[2x(1+6)+8×UxBR+5]-1-8 ×100%=0.88% ( ) Parity bit Error [%]= bBaRudCrLaKte×[2x(1+6)+9×UxBR+6]-1-9 ×100%=3.42% ( ) Stop bit 1 Error [%]= bBaRudCrLaKte×[2x(1+6)+10×UxBR+6]-1-10 ×100%=-1.37% ( ) Start bit Error [%]= bBaRudCrLaKte×[2x(1+6)+0×UxBR+0]-1-0 ×100%=2.54% ( ) Data bit D0 Error [%]= bBaRudCrLaKte×[2x(1+6)+1×UxBR+1]-1-1 ×100%=5.08% The results show the maximum per-bit error to be 5.08% of a BITCLK period. 18.2.6.5 Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in Table 18-2 for a 32 768-Hz watch crystal (ACLK) and a typical 1 048 576-Hz SMCLK. The receive error is the accumulated time versus the ideal scanning time in the middle of each bit. The transmit error is the accumulated timing error versus the ideal time of the bit period. Baud Rate 1200 2400 4800 9600 19 200 38 400 76 800 115 200 Table 18-2. Commonly Used Baud Rates, Baud Rate Data, and Errors Divide by A: B: 27.31 13.65 6.83 3.41 873.81 436.91 218.45 109.23 54.61 27.31 13.65 9.1 UxBR1 0 0 0 0 A: BRCLK = 32 768 Hz UxBR0 UxMCTL Max TX Error % Max RX Error % 1B 03 -4/3 -4/3 0D 6B -6/3 -6/3 06 6F -9/11 -9/11 03 4A -21/12 -21/12 Synch RX Error % ±2 ±4 ±7 ±15 UxBR1 03 01 0 0 0 0 0 0 B: BRCLK = 1 048 576 Hz UxBR0 UxMCTL Max TX Error % 69 FF 0/0.3 B4 FF 0/0.3 DA 55 0/0.4 6D 03 -0.4/1 36 6B -0.2/2 1B 03 -4/3 0D 6B -6/3 09 08 -5/7 Max RX Error % ±2 ±2 ±2 ±2 ±2 ±2 ±4 ±7 486 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated www.ti.com USART Operation: UART Mode 18.2.7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. 18.2.7.1 USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF. UTXIFGx is set after a PUC or when SWRST = 1. UTXIEx is reset after a PUC or when SWRST = 1. The operation is shown is Figure 18-10. UTXIEx Q Clear PUC or SWRST VCC Character Moved From Buffer to Shift Register Set DQ UTXIFGx Clear SWRST Interrupt Service Requested Data written to UxTXBUF IRQA Figure 18-10. Transmit Interrupt Operation 18.2.7.2 USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1. URXIFGx is automatically reset if the pending interrupt is served (when URXSE = 0) or when UxRXBUF is read. The operation is shown in Figure 18-11. SYNC Valid Start Bit Receiver Collects Character From URXD URXSE τ Erroneous Character Rejection PE FE BRK URXEIE URXS S Clear URXIEx S URXIFGx Interrupt Service Requested URXWIE RXWAKE Non-Address Character Rejection Clear Character Received or Break Detected Figure 18-11. Receive Interrupt Operation SWRST PUC UxRXBUF Read URXSE IRQA SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 487 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: UART Mode www.ti.com URXEIE is used to enable or disable erroneous characters from setting URXIFGx. When using multiprocessor addressing modes, URXWIE is used to auto-detect valid address characters and reject unwanted data characters. Two types of characters do not set URXIFGx: • Erroneous characters when URXEIE = 0 • Non-address characters when URXWIE = 1 When URXEIE = 1 a break condition sets the BRK bit and the URXIFGx flag. 18.2.7.3 Receive-Start Edge Detect Operation The URXSE bit enables the receive start-edge detection feature. The recommended usage of the receivestart edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low-power mode operation. The ultra-fast turn-on of the DCO allows character reception after the start edge detection. When URXSE, URXIEx and GIE are set and a start edge occurs on URXDx, the internal signal URXS is set. When URXS is set, a receive interrupt request is generated but URXIFGx is not set. User software in the receive interrupt service routine can test URXIFGx to determine the source of the interrupt. When URXIFGx = 0 a start edge was detected, and when URXIFGx = 1 a valid character (or break) was received. When the ISR determines the interrupt request was from a start edge, user software toggles URXSE, and must enable the BRCLK source by returning from the ISR to active mode or to a low-power mode where the source is active. If the ISR returns to a low-power mode where the BRCLK source is inactive, the character is not received. Toggling URXSE clears the URXS signal and re-enables the start edge detect feature for future characters. See chapter System Resets, Interrupts, and Operating Modes for information on entering and exiting low-power modes. The now active BRCLK allows the USART to receive the balance of the character. After the full character is received and moved to UxRXBUF, URXIFGx is set and an interrupt service is again requested. Upon ISR entry, URXIFGx = 1 indicating a character was received. The URXIFGx flag is cleared when user software reads UxRXBUF. ; Interrupt handler for start condition and ; Character receive. BRCLK = DCO. U0RX_Int BIT.B JZ MOV.B ... RETI #URXIFG0,&IFG1 ST_COND &UxRXBUF,dst ; Test URXIFGx to determine ; If start or character ; Read buffer ; ; ST_COND BIC.B BIS.B BIC RETI #URXSE,&U0TCTL #URXSE,&U0TCTL #SCG0+SCG1,0(SP) ; Clear URXS signal ; Re-enable edge detect ; Enable BRCLK = DCO ; NOTE: Break Detect With Halted UART Clock When using the receive start-edge detect feature, a break condition cannot be detected when the BRCLK source is off. 488 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: UART Mode 18.2.7.4 Receive-Start Edge Detect Conditions When URXSE = 1, glitch suppression prevents the USART from being accidentally started. Any low-level on URXDx shorter than the deglitch time tτ (approximately 300 ns) is ignored by the USART and no interrupt request is generated (see Figure 18-12). See the device-specific data sheet for parameters. URXDx URXS tτ Figure 18-12. Glitch Suppression, USART Receive Not Started When a glitch is longer than tτ or a valid start bit occurs on URXDx, the USART receive operation is started and a majority vote is taken as shown in Figure 18-13. If the majority vote fails to detect a start bit, the USART halts character reception. If character reception is halted, an active BRCLK is not necessary. A time-out period longer than the character receive duration can be used by software to indicate that a character was not received in the expected time, and the software can disable BRCLK. Majority Vote Taken URXDx URXS tτ Figure 18-13. Glitch Suppression, USART Activated SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 489 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Registers: UART Mode www.ti.com 18.3 USART Registers: UART Mode Table 18-3 lists the registers for all devices implementing a USART module. Table 18-4 applies only to devices with a second USART module, USART1. Table 18-3. USART0 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0 Baud rate control register 1 Receive buffer register Transmit buffer register SFR interrupt enable register 1 SFR interrupt flag register 1 Short Form U0CTL U0TCTL U0RCTL U0MCTL U0BR0 U0BR1 U0RXBUF U0TXBUF IE1 IFG1 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Address 070h 071h 072h 073h 074h 075h 076h 077h 000h 002h Initial State 001h with PUC 001h with PUC 000h with PUC Unchanged Unchanged Unchanged Unchanged Unchanged 000h with PUC 082h with PUC Table 18-4. USART1 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0 Baud rate control register 1 Receive buffer register Transmit buffer register SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form U1CTL U1TCTL U1RCTL U1MCTL U1BR0 U1BR1 U1RXBUF U1TXBUF IE2 IFG2 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Address 078h 079h 07Ah 07Bh 07Ch 07Dh 07Eh 07Fh 001h 003h Initial State 001h with PUC 001h with PUC 000h with PUC Unchanged Unchanged Unchanged Unchanged Unchanged 000h with PUC 020h with PUC NOTE: Modifying SFR bits To avoid modifying control bits of other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 490 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 18.3.1 UxCTL, USART Control Register USART Registers: UART Mode 7 PENA rw-0 PENA PEV SPB CHAR LISTEN SYNC MM SWRST 6 PEV rw-0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 SPB rw-0 4 CHAR rw-0 3 LISTEN rw-0 2 SYNC rw-0 1 0 MM SWRST rw-0 rw-1 Parity enable 0 Parity disabled 1 Parity enabled. Parity bit is generated (UTXDx) and expected (URXDx). In address-bit multiprocessor mode, the address bit is included in the parity calculation. Parity select. PEV is not used when parity is disabled. 0 Odd parity 1 Even parity Stop bit select. Number of stop bits transmitted. The receiver always checks for one stop bit. 0 One stop bit 1 Two stop bits Character length. Selects 7-bit or 8-bit character length. 0 7-bit data 1 8-bit data Listen enable. The LISTEN bit selects loopback mode. 0 Disabled 1 Enabled. UTXDx is internally fed back to the receiver. Synchronous mode enable 0 UART mode 1 SPI mode Multiprocessor mode select 0 Idle-line multiprocessor protocol 1 Address-bit multiprocessor protocol Software reset enable 0 Disabled. USART reset released for operation 1 Enabled. USART logic held in reset state SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 491 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Registers: UART Mode 18.3.2 UxTCTL, USART Transmit Control Register 7 Unused rw-0 Unused CKPL SSELx URXSE TXWAKE Unused TXEPT 6 CKPL rw-0 5 4 SSELx rw-0 rw-0 3 URXSE rw-0 2 TXWAKE rw-0 1 Unused rw-0 Bit 7 Bit 6 Bits 5-4 Bit 3 Bit 2 Bit 1 Bit 0 Unused Clock polarity select 0 UCLKI = UCLK 1 UCLKI = inverted UCLK Source select. These bits select the BRCLK source clock. 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK UART receive start-edge. The bit enables the UART receive start-edge feature. 0 Disabled 1 Enabled Transmitter wake 0 Next frame transmitted is data 1 Next frame transmitted is an address Unused Transmitter empty flag 0 UART is transmitting data and/or data is waiting in UxTXBUF 1 Transmitter shift register and UxTXBUF are empty or SWRST = 1 www.ti.com 0 TXEPT rw-1 492 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 18.3.3 UxRCTL, USART Receive Control Register USART Registers: UART Mode 7 FE rw-0 FE PE OE BRK URXEIE URXWIE RXWAKE RXERR 6 PE rw-0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 OE BRK URXEIE URXWIE RXWAKE RXERR rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Framing error flag 0 No error 1 Character received with low stop bit Parity error flag. When PENA = 0, PE is read as 0. 0 No error 1 Character received with parity error Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous character was read. 0 No error 1 Overrun error occurred Break detect flag 0 No break condition 1 Break condition occurred Receive erroneous-character interrupt-enable 0 Erroneous characters rejected and URXIFGx is not set 1 Erroneous characters received set URXIFGx Receive wake-up interrupt-enable. This bit enables URXIFGx to be set when an address character is received. When URXEIE = 0, an address character does not set URXIFGx if it is received with errors. 0 All received characters set URXIFGx 1 Only received address characters set URXIFGx Receive wake-up flag 0 Received character is data 1 Received character is an address Receive error flag. This bit indicates a character was received with error(s). When RXERR = 1, on or more error flags (FE, PE, OE, BRK) is also set. RXERR is cleared when UxRXBUF is read. 0 No receive errors detected 1 Receive error detected 18.3.4 UxBR0, USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw 18.3.5 UxBR1, USART Baud Rate Control Register 1 7 215 rw UxBRx 6 5 4 3 2 1 0 214 213 212 211 210 29 28 rw rw rw rw rw rw rw The valid baud-rate control range is 3 ≤ UxBR ≤ 0FFFFh, where UxBR = (UxBR1 + UxBR0). Unpredictable receive and transmit timing occurs if UxBR < 3. SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 493 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Registers: UART Mode 18.3.6 UxMCTL, USART Modulation Control Register 7 m7 rw UxMCTLx 6 5 4 3 2 m6 m5 m4 m3 m2 rw rw rw rw rw Modulation bits. These bits select the modulation for BRCLK. www.ti.com 1 0 m1 m0 rw rw 18.3.7 UxRXBUF, USART Receive Buffer Register 7 27 r UxRXBUFx 6 26 r Bits 7-0 5 4 3 2 1 0 25 24 23 22 21 20 r r r r r r The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UxRXBUF resets the receive-error bits, the RXWAKE bit, and URXIFGx. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset. 18.3.8 UxTXBUF, USART Transmit Buffer Register 7 27 rw UxTXBUFx 6 26 rw Bits 7-0 5 4 3 2 1 0 25 24 23 22 21 20 rw rw rw rw rw rw The transmit data buffer is user accessible and holds the data waiting to be moved into the transmit shift register and transmitted on UTXDx. Writing to the transmit data buffer clears UTXIFGx. The MSB of UxTXBUF is not used for 7-bit data and is reset. 494 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 18.3.9 IE1, Interrupt Enable Register 1 USART Registers: UART Mode 7 6 5 4 3 2 1 0 UTXIE0 URXIE0 rw-0 rw-0 UTXIE0 URXIE0 Bit 7 Bit 6 Bits 5-0 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. 18.3.10 IE2, Interrupt Enable Register 2 7 6 5 4 3 2 1 0 UTXIE1 URXIE1 rw-0 rw-0 UTXIE1 URXIE1 Bits 7-6 Bit 5 Bit 4 Bits 3-0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. 18.3.11 IFG1, Interrupt Flag Register 1 7 UTXIFG0 rw-1 UTXIFG0 URXIFG0 6 5 4 3 2 1 0 URXIFG0 rw-0 Bit 7 Bit 6 Bits 5-0 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, UART Mode 495 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Registers: UART Mode 18.3.12 IFG2, Interrupt Flag Register 2 www.ti.com 7 UTXIFG1 URXIFG1 6 Bits 7-6 Bit 5 Bit 4 Bits 3-0 5 4 3 2 1 0 UTXIFG1 URXIFG1 rw-1 rw-0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF empty. 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. 496 USART Peripheral Interface, UART Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 19 SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, SPI Mode The universal synchronous/asynchronous receive/transmit (USART) peripheral interface supports two serial modes with one hardware module. This chapter discusses the operation of the synchronous peripheral interface or SPI mode. USART0 is implemented on the MSP430AFE2xx devices. Topic ........................................................................................................................... Page 19.1 USART Introduction: SPI Mode .......................................................................... 498 19.2 USART Operation: SPI Mode ............................................................................. 499 19.3 USART Registers: SPI Mode ............................................................................. 506 SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, SPI Mode 497 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Introduction: SPI Mode www.ti.com 19.1 USART Introduction: SPI Mode In synchronous mode, the USART connects the MSP430 to an external system via three or four pins: SIMO, SOMI, UCLK, and STE. SPI mode is selected when the SYNC bit is set and the I2C bit is cleared. SPI mode features include: • 7-bit or 8-bit data length • 3-pin and 4-pin SPI operation • Master or slave modes • Independent transmit and receive shift registers • Separate transmit and receive buffer registers • Selectable UCLK polarity and phase control • Programmable UCLK frequency in master mode • Independent interrupt capability for receive and transmit Figure 19-1 shows the USART when configured for SPI mode. FE PE OE BRK SWRST USPIEx* URXEIE URXWIE Receive Control URXIFGx* SYNC= 1 Receive Status Receiver Buffer UxRXBUF RXERR RXWAKE Receiver Shift Register SSEL1 SSEL0 SPB CHAR PEV PENA UCLKI 00 ACLK 01 SMCLK 10 SMCLK 11 Baud−Rate Generator Prescaler/Divider UxBRx Modulator UxMCTL UCLKS SPB CHAR PEV PENA LISTEN 0 1 MM SYNC 1 1 SOMI 0 0 1 URXD 0 STE UTXD WUT Transmit Shift Register TXWAKE Transmit Buffer UxTXBUF 1 1 0 0 SIMO UTXIFGx* Transmit Control SWRST USPIEx* TXEPT UCLKI STC SYNC CKPH CKPL Clock Phase and Polarity UCLK * See the device-specific data sheet for SFR locations. Figure 19-1. USART Block Diagram: SPI Mode 498 USART Peripheral Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: SPI Mode 19.2 USART Operation: SPI Mode In SPI mode, serial data is transmitted and received by multiple devices using a shared clock provided by the master. An additional pin, STE, is provided as to enable a device to receive and transmit data and is controlled by the master. Three or four signals are used for SPI data exchange: • SIMO: Slave in, master out – Master mode: SIMO is the data output line. – Slave mode: SIMO is the data input line. • SOMI: Slave out, master in – Master mode: SOMI is the data input line. – Slave mode: SOMI is the data output line. • UCLK: USART SPI clock – Master mode: UCLK is an output. – Slave mode: UCLK is an input. • STE: Slave transmit enable. Used in 4-pin mode to allow multiple masters on a single bus. Not used in 3-pin mode. – 4-pin master mode: • When STE is high, SIMO and UCLK operate normally. • When STE is low, SIMO and UCLK are set to the input direction. – 4-pin slave mode: • When STE is high, RX/TX operation of the slave is disabled and SOMI is forced to the input direction. • When STE is low, RX/TX operation of the slave is enabled and SOMI operates normally. 19.2.1 USART Initialization and Reset The USART is reset by a PUC or by the SWRST bit. After a PUC, the SWRST bit is automatically set, keeping the USART in a reset condition. When set, the SWRST bit resets the URXIEx, UTXIEx, URXIFGx, OE, and FE bits and sets the UTXIFGx flag. The USPIEx bit is not altered by SWRST. Clearing SWRST releases the USART for operation. NOTE: Initializing or Reconfiguring the USART Module The required USART initialization/reconfiguration process is: 1. Set SWRST (BIS.B #SWRST,&UxCTL) 2. Initialize all USART registers with SWRST=1 (including UxCTL) 3. Enable USART module via the MEx SFRs (USPIEx) 4. Clear SWRST via software (BIC.B #SWRST,&UxCTL) 5. Enable interrupts (optional) via the IEx SFRs (URXIEx and/or UTXIEx) Failure to follow this process may result in unpredictable USART behavior. SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, SPI Mode 499 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: SPI Mode www.ti.com 19.2.2 Master Mode Figure 19-2 shows the USART as a master in both 3-pin and 4-pin configurations. The USART initiates a data transfer when data is moved to the transmit data buffer UxTXBUF. The UxTXBUF data is moved to the TX shift register when the TX shift register is empty, initiating data transfer on SIMO starting with the most significant bit. Data on SOMI is shifted into the receive shift register on the opposite clock edge, starting with the most significant bit. When the character is received, the receive data is moved from the RX shift register to the received data buffer UxRXBUF and the receive interrupt flag, URXIFGx, is set, indicating the RX/TX operation is complete. MASTER SIMO SIMO SLAVE Receive Buffer UxRXBUF Transmit Buffer UxTXBUF Px.x STE Receive Shift Register SOMI Transmit Shift Register MSB LSB MSB MSP430 USART LSB UCLK SPI Receive Buffer STE SS Port.x SOMI Data Shift Register (DSR) MSB SCLK LSB COMMON SPI Figure 19-2. USART Master and External Slave A set transmit interrupt flag, UTXIFGx, indicates that data has moved from UxTXBUF to the TX shift register and UxTXBUF is ready for new data. It does not indicate RX/TX completion. In master mode, the completion of an active transmission is indicated by a set transmitter empty bit TXEPT = 1. To receive data into the USART in master mode, data must be written to UxTXBUF because receive and transmit operations operate concurrently. 19.2.2.1 Four-Pin SPI Master Mode In 4-pin master mode, STE is used to prevent conflicts with another master. The master operates normally when STE is high. When STE is low: • SIMO and UCLK are set to inputs and no longer drive the bus • The error bit FE is set indicating a communication integrity violation to be handled by the user A low STE signal does not reset the USART module. The STE input signal is not used in 3-pin master mode. 19.2.3 Slave Mode Figure 19-3 shows the USART as a slave in both 3-pin and 4-pin configurations. UCLK is used as the input for the SPI clock and must be supplied by the external master. The data transfer rate is determined by this clock and not by the internal baud rate generator. Data written to UxTXBUF and moved to the TX shift register before the start of UCLK is transmitted on SOMI. Data on SIMO is shifted into the receive shift register on the opposite edge of UCLK and moved to UxRXBUF when the set number of bits are received. When data is moved from the RX shift register to UxRXBUF, the URXIFGx interrupt flag is set, indicating that data has been received. The overrun error bit, OE, is set when the previously received data is not read from UxRXBUF before new data is moved to UxRXBUF. 500 USART Peripheral Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: SPI Mode MASTER SIMO SIMO SLAVE SPI Receive Buffer Px.x STE SOMI Data Shift Register DSR MSB LSB SCLK COMMON SPI Transmit Buffer UxTXBUF Receive Buffer UxRXBUF STE SS Port.x SOMI Transmit Shift Register Receive Shift Register MSB UCLK LSB MSB LSB MSP430 USART Figure 19-3. USART Slave and External Master 19.2.3.1 Four-Pin SPI Slave Mode In 4-pin slave mode, STE is used by the slave to enable the transmit and receive operations and is provided by the SPI master. When STE is low, the slave operates normally. When STE is high: • Any receive operation in progress on SIMO is halted • SOMI is set to the input direction A high STE signal does not reset the USART module. The STE input signal is not used in 3-pin slave mode. 19.2.4 SPI Enable The SPI transmit/receive enable bit USPIEx enables or disables the USART in SPI mode. When USPIEx = 0, the USART stops operation after the current transfer completes, or immediately if no operation is active. A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated. 19.2.4.1 Transmit Enable When USPIEx = 0, any further write to UxTXBUF does not transmit. Data written to UxTXBUF begin to transmit when USPIEx = 1 and the BRCLK source is active. Figure 19-4 and Figure 19-5 show the transmit enable state diagrams. USPIEx = 0 Transmit Disable USPIEx = 1 USPIEx = 0 PUC SWRST USPIEx = 0 And Last Buffer Entry Is Transmitted No Data Written to Transfer Buffer Not Completed Idle State (Transmitter Enabled) USPIEx = 1, Data Written to Transmit Buffer Transmission Active Handle Interrupt Conditions USPIEx = 1 Character Transmitted USPIEx = 0 Figure 19-4. Master Transmit Enable State Diagram SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, SPI Mode 501 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: SPI Mode USPIEx = 0 No Clock at UCLK Not Completed www.ti.com Transmit Disable USPIEx = 1 USPIEx = 0 Idle State (Transmitter Enabled) USPIEx = 1 External Clock Present Transmission Active PUC SWRST USPIEx = 0 USPIEx = 1 Handle Interrupt Conditions Character Transmitted Figure 19-5. Slave Transmit Enable State Diagram 19.2.4.2 Receive Enable The SPI receive enable state diagrams are shown in Figure 19-6 and Figure 19-7. When USPIEx = 0, UCLK is disabled from shifting data into the RX shift register. USPIEx = 0 No Data Written to UxTXBUF Not Completed Receive Disable USPIEx = 1 USPIEx = 0 PUC SWRST Idle State (Receiver Enabled) USPIEx = 1 Data Written to UxTXBUF Receiver Collects Character USPIEx = 1 USPIEx = 0 Handle Interrupt Conditions Character Received Figure 19-6. SPI Master Receive-Enable State Diagram USPIEx = 0 No Clock at UCLK Not Completed Receive Disable USPIEx = 1 USPIEx = 0 PUC SWRST Idle State (Receive Enabled) USPIEx = 1 External Clock Present USPIEx = 1 USPIEx = 0 Receiver Collects Character Handle Interrupt Conditions Character Received Figure 19-7. SPI Slave Receive-Enable State Diagram 19.2.5 Serial Clock Control UCLK is provided by the master on the SPI bus. When MM = 1, BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Figure 19-8. When MM = 0, the USART clock is provided on the UCLK pin by the master and, the baud rate generator is not used and the SSELx bits are “don’t care”. The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer. 502 USART Peripheral Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: SPI Mode SSEL1 SSEL0 N = 215 ... 28 27 ... 20 UCLKI ACLK SMCLK SMCLK 00 01 BRCLK 10 11 UxBR1 UxBR0 8 8 16−Bit Counter R Q15 ............ Q0 Compare (0 or 1) Modulation Data Shift Register R (LSB first) Toggle FF R mX m7 8 m0 UxMCTL Bit Start BITCLK Figure 19-8. SPI Baud Rate Generator The 16-bit value of UxBR0+UxBR1 is the division factor of the USART clock source, BRCLK. The maximum baud rate that can be generated in master mode is BRCLK/2. The maximum baud rate that can be generated in slave mode is BRCLK The modulator in the USART baud rate generator is not used for SPI mode and is recommended to be set to 000h. The UCLK frequency is given by: Baud rate = BRCLK with UxBR= [UxBR1, UxBR0] UxBR 19.2.5.1 Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART. Timing for each case is shown in Figure 19-9. CKPH CKPL Cycle# 1 2 3 4 5 6 7 8 00 UCLK 01 UCLK 10 UCLK 11 UCLK STE 0 X SIMO/ SOMI 1 X SIMO/ SOMI Move to UxTXBUF TX Data Shifted Out MSB MSB LSB LSB RX Sample Points Figure 19-9. USART SPI Timing SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, SPI Mode 503 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Operation: SPI Mode 19.2.6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception. www.ti.com 19.2.6.1 SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UxTXBUF is ready to accept another character. An interrupt request is generated if UTXIEx and GIE are also set. UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UxTXBUF. UTXIFGx is set after a PUC or when SWRST = 1. UTXIEx is reset after a PUC or when SWRST = 1. The operation is shown is Figure 19-10. UTXIEx Q SYNC = 1 Clear PUC or SWRST VCC Character Moved From Buffer to Shift Register Set UTXIFGx DQ Clear SWRST Interrupt Service Requested Data moved to UxTXBUF IRQA Figure 19-10. Transmit Interrupt Operation NOTE: Writing to UxTXBUF in SPI Mode Data written to UxTXBUF when UTXIFGx = 0 and USPIEx = 1 may result in erroneous data transmission. 504 USART Peripheral Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com USART Operation: SPI Mode 19.2.6.2 SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UxRXBUF as shown in Figure 19-11 and Figure 19-12. An interrupt request is generated if URXIEx and GIE are also set. URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST = 1. URXIFGx is automatically reset if the pending interrupt is served or when UxRXBUF is read. SYNC Valid Start Bit Receiver Collects Character From URXD URXSE τ URXS Clear SYNC = 1 PE FE BRK URXEIE URXWIE RXWAKE URXIEx Interrupt Service Requested (S) URXIFGx Clear Character Received Figure 19-11. Receive Interrupt Operation SWRST PUC UxRXBUF Read URXSE IRQA SWRST = 1 Wait For Next Start Receive Character USPIEx = 0 URXIFGx = 0 URXIEx = 0 PUC Receive Character Completed USPIEx = 1 SWRST = 1 USPIEx = 0 URXIFGx = 1 USPIEx = 1 and URXIEx = 1 and GIE = 1 and Priority Priority Valid Too GIE = 0 Low Interrupt Service Started, GIE = 0 URXIFGx = 0 Figure 19-12. Receive Interrupt State Diagram SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, SPI Mode 505 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Registers: SPI Mode www.ti.com 19.3 USART Registers: SPI Mode Table 19-1 lists the registers for all devices implementing a USART module. Table 19-2 applies only to devices with a second USART module, USART1. Table 19-1. USART0 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0 Baud rate control register 1 Receive buffer register Transmit buffer register SFR module enable register 1 SFR interrupt enable register 1 SFR interrupt flag register 1 Short Form U0CTL U0TCTL U0RCTL U0MCTL U0BR0 U0BR1 U0RXBUF U0TXBUF ME1 IE1 IFG1 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Read/write Address 070h 071h 072h 073h 074h 075h 076h 077h 004h 000h 002h Initial State 001h with PUC 001h with PUC 000h with PUC Unchanged Unchanged Unchanged Unchanged Unchanged 000h with PUC 000h with PUC 082h with PUC Table 19-2. USART1 Control and Status Registers Register USART control register Transmit control register Receive control register Modulation control register Baud rate control register 0 Baud rate control register 1 Receive buffer register Transmit buffer register SFR module enable register 2 SFR interrupt enable register 2 SFR interrupt flag register 2 Short Form U1CTL U1TCTL U1RCTL U1MCTL U1BR0 U1BR1 U1RXBUF U1TXBUF ME2 IE2 IFG2 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Read/write Address 078h 079h 07Ah 07Bh 07Ch 07Dh 07Eh 07Fh 005h 001h 003h Initial State 001h with PUC 001h with PUC 000h with PUC Unchanged Unchanged Unchanged Unchanged Unchanged 000h with PUC 000h with PUC 020h with PUC NOTE: Modifying the SFR bits To avoid modifying control bits for other modules, it is recommended to set or clear the IEx and IFGx bits using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 506 USART Peripheral Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 19.3.1 UxCTL, USART Control Register USART Registers: SPI Mode 7 6 Unused rw-0 rw-0 5 4 3 2 1 I2C CHAR LISTEN SYNC MM rw-0 rw-0 rw-0 rw-0 rw-0 Unused I2C CHAR LISTEN SYNC MM SWRST Bits 7-6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unused I2C mode enable. This bit selects I2C or SPI operation when SYNC = 1. 0 SPI mode 1 I2C mode Character length 0 7-bit data 1 8-bit data Listen enable. The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled. The transmit signal is internally fed back to the receiver. Synchronous mode enable 0 UART mode 1 SPI mode Master mode 0 USART is slave 1 USART is master Software reset enable 0 Disabled. USART reset released for operation. 1 Enabled. USART logic held in reset state. 0 SWRST rw-1 19.3.2 UxTCTL, USART Transmit Control Register 7 CKPH rw-0 CKPH CKPL SSELx Unused STC TXEPT 6 CKPL rw-0 5 4 SSELx rw-0 rw-0 3 2 Unused rw-0 rw-0 1 STC rw-0 Bit 7 Bit 6 Bits 5-4 Bits 3-2 Bit 1 Bit 0 Clock phase select. 0 Data is changed on the first UCLK edge and captured on the following edge. 1 Data is captured on the first UCLK edge and changed on the following edge. Clock polarity select 0 The inactive state is low. 1 The inactive state is high. Source select. These bits select the BRCLK source clock. 00 External UCLK (valid for slave mode only) 01 ACLK (valid for master mode only) 10 SMCLK (valid for master mode only) 11 SMCLK (valid for master mode only) Unused Slave transmit control. 0 4-pin SPI mode: STE enabled. 1 3-pin SPI mode: STE disabled. Transmitter empty flag. The TXEPT flag is not used in slave mode. 0 Transmission active and/or data waiting in UxTXBUF 1 UxTXBUF and TX shift register are empty 0 TXEPT rw-1 SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, SPI Mode 507 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Registers: SPI Mode 19.3.3 UxRCTL, USART Receive Control Register www.ti.com 7 FE rw-0 FE Unused OE Unused 6 5 4 3 2 1 0 Unused OE Unused rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit 7 Bit 6 Bit 5 Bits 4-0 Framing error flag. This bit indicates a bus conflict when MM = 1 and STC = 0. FE is unused in slave mode. 0 No conflict detected 1 A negative edge occurred on STE, indicating bus conflict Unused Overrun error flag. This bit is set when a character is transferred into UxRXBUF before the previous character was read. OE is automatically reset when UxRXBUF is read, when SWRST = 1, or can be reset by software. 0 No error 1 Overrun error occurred Unused 19.3.4 UxBR0, USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 27 26 25 24 23 22 21 20 rw rw rw rw rw rw rw rw 19.3.5 UxBR1, USART Baud Rate Control Register 1 7 215 rw UxBRx 6 5 4 3 2 1 0 214 213 212 211 210 29 28 rw rw rw rw rw rw rw The baud-rate generator uses the content of {UxBR1+UxBR0} to set the baud rate. Unpredictable SPI operation occurs if UxBR < 2. 19.3.6 UxMCTL, USART Modulation Control Register 7 6 5 4 3 2 1 0 m7 m6 m5 m4 m3 m2 m1 m0 rw rw rw rw rw rw rw rw UxMCTLx Bits 7-0 The modulation control register is not used for SPI mode and should be set to 000h. 19.3.7 UxRXBUF, USART Receive Buffer Register 7 27 r UxRXBUFx 6 26 r Bits 7-0 5 4 3 2 1 0 25 24 23 22 21 20 r r r r r r The receive-data buffer is user accessible and contains the last received character from the receive shift register. Reading UxRXBUF resets the OE bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and the MSB is always reset. 508 USART Peripheral Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 19.3.8 UxTXBUF, USART Transmit Buffer Register USART Registers: SPI Mode 7 27 rw UxTXBUFx 6 26 rw Bits 7-0 5 4 3 2 1 0 25 24 23 22 21 20 rw rw rw rw rw rw The transmit data buffer is user accessible and contains current data to be transmitted. When seven-bit character-length is used, the data should be MSB justified before being moved into UxTXBUF. Data is transmitted MSB first. Writing to UxTXBUF clears UTXIFGx. 19.3.9 ME1, Module Enable Register 1 7 6 5 4 3 2 1 0 USPIE0 rw-0 USPIE0 Bit 7 Bit 6 Bits 5-0 This bit may be used by other modules. See device-specific data sheet. USART0 SPI enable. This bit enables the SPI mode for USART0. 0 Module not enabled 1 Module enabled These bits may be used by other modules. See device-specific data sheet. 19.3.10 ME2, Module Enable Register 2 7 6 5 4 3 2 1 0 USPIE1 rw-0 USPIE1 Bits 7-5 Bit 4 Bits 3-0 These bits may be used by other modules. See device-specific data sheet. USART1 SPI enable. This bit enables the SPI mode for USART1. 0 Module not enabled 1 Module enabled These bits may be used by other modules. See device-specific data sheet. 19.3.11 IE1, Interrupt Enable Register 1 7 6 5 4 3 2 1 0 UTXIE0 URXIE0 rw-0 rw-0 UTXIE0 URXIE0 Bit 7 Bit 6 Bits 5-0 USART0 transmit interrupt enable. This bit enables the UTXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART0 receive interrupt enable. This bit enables the URXIFG0 interrupt. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. SLAU144J – December 2004 – Revised July 2013 USART Peripheral Interface, SPI Mode 509 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated USART Registers: SPI Mode 19.3.12 IE2, Interrupt Enable Register 2 7 UTXIE1 URXIE1 6 5 4 3 2 1 UTXIE1 URXIE1 rw-0 rw-0 Bits 7-6 Bit 5 Bit 4 Bits 3-0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt enable. This bit enables the UTXIFG1 interrupt. 0 Interrupt not enabled 1 Interrupt enabled USART1 receive interrupt enable. This bit enables the URXIFG1 interrupt. 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules. See device-specific data sheet. www.ti.com 0 19.3.13 IFG1, Interrupt Flag Register 1 7 UTXIFG0 rw-1 UTXIFG0 URXIFG0 6 5 4 3 2 1 0 URXIFG0 rw-0 Bit 7 Bit 6 Bits 5-0 USART0 transmit interrupt flag. UTXIFG0 is set when U0TXBUF is empty. 0 No interrupt pending 1 Interrupt pending USART0 receive interrupt flag. URXIFG0 is set when U0RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. 19.3.14 IFG2, Interrupt Flag Register 2 7 UTXIFG1 URXIFG1 6 Bits 7-6 Bit 5 Bit 4 Bits 3-0 5 4 3 2 1 0 UTXIFG1 URXIFG1 rw-1 rw-0 These bits may be used by other modules. See device-specific data sheet. USART1 transmit interrupt flag. UTXIFG1 is set when U1TXBUF empty. 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag. URXIFG1 is set when U1RXBUF has received a complete character. 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules. See device-specific data sheet. 510 USART Peripheral Interface, SPI Mode SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 20 SLAU144J – December 2004 – Revised July 2013 OA The OA is a general purpose operational amplifier. This chapter describes the OA. Two OA modules are implemented in the MSP430x22x4 devices. Topic ........................................................................................................................... Page 20.1 OA Introduction ............................................................................................... 512 20.2 OA Operation .................................................................................................. 513 20.3 OA Registers ................................................................................................... 520 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated OA 511 OA Introduction www.ti.com 20.1 OA Introduction The OA operational amplifiers support front-end analog signal conditioning prior to analog-to-digital conversion. Features of the OA include: • Single supply, low-current operation • Rail-to-rail output • Programmable settling time vs. power consumption • Software selectable configurations • Software selectable feedback resistor ladder for PGA implementations NOTE: Multiple OA Modules Some devices may integrate more than one OA module. If more than one OA is present on a device, the multiple OA modules operate identically. Throughout this chapter, nomenclature appears such as OAxCTL0 to describe register names. When this occurs, the x is used to indicate which OA module is being discussed. In cases where operation is identical, the register is simply referred to as OAxCTL0. The block diagram of the OA module is shown in Figure 20-1. 512 OA SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com OA Operation OAPx OAPx = 3 OAxI0 00 OAFCx = 6 OA0I1 01 OANx = 3 OAxIA 10 OA1TAP (OA0) 0 OAxIB OA2OUT (OA0) 11 0 OA2TAP (OA1) 1 OA0TAP (OA2) OA0OUT (OA1) 1 OA1OUT (OA2) OAFCx = 6 OAFCx = 5 OANx OANEXT OAPMx + OAx − OAxI0 00 OAxI1 01 OAxIA 10 OAxIB 11 OARRIP AV CC 0 1 1 0 OA1RBOTTOM OA2RBOTTOM OA0RBOTTOM (OA0) (OA1) (OA2) OAFBRx > 0 1 OANx OAxI0 00 OAxI1 01 OAxIA 10 OA2OUT (OA0) 11 OA0OUT (OA1) OA1OUT (OA2) 1 000 OAFCx OAxRBOTTOM 001 else 3 000 001 OAFBRx 010 3 011 OAxRTOP 000 100 4R 101 001 4R 110 010 111 2R 011 2R 3 100 R 101 000 R 110 001 R 010 111 R 011 100 OAxTAP OAxRBOTTOM 101 110 111 OAxFB Figure 20-1. OA Block Diagram Feeback Switch Matrix A1 (OA0) A3 (OA1) A5 (OA2) A1/OA0O A3/OA1O A5/OA2O A12 (OA0) A13 (OA1) A14 (OA2) A12/OA0O A13/OA1O A14/OA2O OAxOUT 2 OAADCx OAFCx = 0 20.2 OA Operation The OA module is configured with user software. The setup and operation of the OA is discussed in the following sections. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated OA 513 OA Operation www.ti.com 20.2.1 OA Amplifier The OA is a configurable, low-current, rail-to-rail output operational amplifier. It can be configured as an inverting amplifier, or a non-inverting amplifier, or can be combined with other OA modules to form differential amplifiers. The output slew rate of the OA can be configured for optimized settling time vs power consumption with the OAPMx bits. When OAPMx = 00 the OA is off and the output is highimpedance. When OAPMx > 0, the OA is on. See the device-specific data sheet for parameters. 20.2.2 OA Input The OA has configurable input selection. The signals for the + and - inputs are individually selected with the OANx and OAPx bits and can be selected as external signals or internal signals. OAxI0 and OAxI1 are external signals provided for each OA module. OA0I1 provides a non-inverting input that is tied together internally for all OA modules. OAxIA and OAxIB provide device-dependent inputs. See the device data sheet for signal connections. When the external inverting input is not needed for a mode, setting the OANEXT bit makes the internal inverting input externally available. 20.2.3 OA Output and Feedback Routing The OA has configurable output selection controlled by the OAADCx bits and the OAFCx bits. The OA output signals can be routed to ADC inputs A12 (OA0), A13 (OA1), or A14 (OA2) internally, or can be routed to these ADC inputs and their external pins. The OA output signals can also be routed to ADC inputs A1 (OA0), A3 (OA1), or A5 (OA2) and the corresponding external pin. The OA output is also connected to an internal R-ladder with the OAFCx bits. The R-ladder tap is selected with the OAFBRx bits to provide programmable gain amplifier functionality. Table 20-1 shows the OA output and feedback routing configurations. When OAFCx = 0 the OA is in general-purpose mode and feedback is achieved externally to the device. When OAFCx > 0 and when OAADCx = 00 or 11, the output of the OA is kept internal to the device. When OAFCx > 0 and OAADCx = 01 or 10, the OA output is routed both internally and externally. OAFCx =0 =0 >0 >0 >0 >0 OAADCx x0 x1 00 01 10 11 Table 20-1. OA Output Configurations OA Output and Feedback Routing OAxOUT connected to external pins and ADC input A1, A3, or A5. OAxOUT connected to external pins and ADC input A12, A13, or A14. OAxOUT used for internal routing only. OAxOUT connected to external pins and ADC input A12, A13, or A14. OAxOUT connected to external pins and ADC input A1, A3, or A5. OAxOUT connected internally to ADC input A12, A13 , or A14. External A12, A13, or A14 pin connections are disconnected from the ADC. 20.2.4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits as listed in Table 20-2. OAFCx 000 001 010 011 100 101 110 111 Table 20-2. OA Mode Select OA Mode General-purpose opamp Unity gain buffer for three-opamp differential amplifier Unity gain buffer Comparator Non-inverting PGA amplifier Cascaded non-inverting PGA amplifier Inverting PGA amplifier Differential amplifier 514 OA SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com OA Operation 20.2.4.1 General Purpose Opamp Mode In this mode the feedback resistor ladder is isolated from the OAx and the OAxCTL0 bits define the signal routing. The OAx inputs are selected with the OAPx and OANx bits. The OAx output is connected to the ADC input channel as selected by the OAxCTL0 bits. 20.2.4.2 Unity Gain Mode for Differential Amplifier In this mode the output of the OAx is connected to the inverting input of the OAx providing a unity gain buffer. The non-inverting input is selected by the OAPx bits. The external connection for the inverting input is disabled and the OANx bits are don’t care. The output of the OAx is also routed through the resistor ladder as part of the three-opamp differential amplifier. This mode is only for construction of the threeopamp differential amplifier. 20.2.4.3 Unity Gain Mode In this mode the output of the OAx is connected to the inverting input of the OAx providing a unity gain buffer. The non-inverting input is selected by the OAPx bits. The external connection for the inverting input is disabled and the OANx bits are don’t care. The OAx output is connected to the ADC input channel as selected by the OAxCTL0 bits. 20.2.4.4 Comparator Mode In this mode the output of the OAx is isolated from the resistor ladder. RTOP is connected to AVSS and RBOTTOM is connected to AVCC when OARRIP = 0. When OARRIP = 1, the connection of the resistor ladder is reversed. RTOP is connected to AVCC and RBOTTOM is connected to AVSS. The OAxTAP signal is connected to the inverting input of the OAx providing a comparator with a programmable threshold voltage selected by the OAFBRx bits. The non-inverting input is selected by the OAPx bits. Hysteresis can be added by an external positive feedback resistor. The external connection for the inverting input is disabled and the OANx bits are don’t care. The OAx output is connected to the ADC input channel as selected by the OAxCTL0 bits. 20.2.4.5 Non-Inverting PGA Mode In this mode the output of the OAx is connected to RTOP and RBOTTOM is connected to AVSS. The OAxTAP signal is connected to the inverting input of the OAx providing a non-inverting amplifier configuration with a programmable gain of [1+OAxTAP ratio]. The OAxTAP ratio is selected by the OAFBRx bits. If the OAFBRx bits = 0, the gain is unity. The non-inverting input is selected by the OAPx bits. The external connection for the inverting input is disabled and the OANx bits are don’t care. The OAx output is connected to the ADC input channel as selected by the OAxCTL0 bits. 20.2.4.6 Cascaded Non-Inverting PGA Mode This mode allows internal routing of the OA signals to cascade two or three OA in non-inverting mode. In this mode the non-inverting input of the OAx is connected to OA2OUT (OA0), OA0OUT (OA1), or OA1OUT (OA2) when OAPx = 11. The OAx outputs are connected to the ADC input channel as selected by the OAxCTL0 bits. 20.2.4.7 Inverting PGA Mode In this mode the output of the OAx is connected to RTOP and RBOTTOM is connected to an analog multiplexer that multiplexes the OAxI0, OAxI1, OAxIA, or the output of one of the remaining OAs, selected with the OANx bits. The OAxTAP signal is connected to the inverting input of the OAx providing an inverting amplifier with a gain of -OAxTAP ratio. The OAxTAP ratio is selected by the OAFBRx bits. The noninverting input is selected by the OAPx bits. The OAx output is connected to the ADC input channel as selected by the OAxCTL0 bits. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated OA 515 OA Operation NOTE: Using OAx Negative Input Simultaneously as ADC Input When the pin connected to the negative input multiplexer is also used as an input to the ADC, conversion errors up to 5 mV may be observed due to internal wiring voltage drops. www.ti.com 20.2.4.8 Differential Amplifier Mode This mode allows internal routing of the OA signals for a two-opamp or three-opamp instrumentation amplifier. Figure 20-2 shows a two-opamp configuration with OA0 and OA1. In this mode the output of the OAx is connected to RTOP by routing through another OAx in the Inverting PGA mode. RBOTTOM is unconnected providing a unity gain buffer. This buffer is combined with one or two remaining OAx to form the differential amplifier. The OAx output is connected to the ADC input channel as selected by the OAxCTL0 bits. Figure 20-2 shows an example of a two-opamp differential amplifier using OA0 and OA1. The control register settings and are shown in Table 20-3. The gain for the amplifier is selected by the OAFBRx bits for OA1 and is shown in Table 20-4. The OAx interconnections are shown in Figure 20-3. Table 20-3. Two-Opamp Differential Amplifier Control Register Settings Register OA0CTL0 OA0CTL1 OA1CTL0 OA1CTL1 Settings (binary) xx xx xx 0 0 000 111 0 x 11 xx xx x x xxx 110 0 x Table 20-4. Two-Opamp Differential Amplifier Gain Settings OA1 OAFBRx 000 001 010 011 100 101 110 111 Gain 0 1/3 1 1 2/3 3 4 1/3 7 15 V2 V1 + OA0 − + OA1 − R1 R2 (V2 − V1) × R2 Vdiff = R1 Figure 20-2. Two-Opamp Differential Amplifier 516 OA SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com OAxI0 OA0I1 OAxIA OAxIB OAPx 00 01 10 11 0 1 OAxI0 OA0I1 OAxIA OAxIB OAPx 00 01 10 0 11 1 0 1 OAPMx + OA0 − 000 000 001 001 010 OAxRTOP else 011 000 100 101 001 110 010 111 011 100 101 110 111 00 01 10 11 OA Operation 0 OAPMx 1 + OA1 − 000 001 else 000 001 OAFBRx 010 3 011 OAxRTOP 000 100 4R 101 001 4R 110 010 111 2R 011 2R 3 100 R 101 000 R 110 001 R 010 111 R 011 100 101 110 111 2 OAADCx OAxFB Figure 20-3. Two-Opamp Differential Amplifier OAx Interconnections SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated OA 517 OA Operation www.ti.com Figure 20-4 shows an example of a three-opamp differential amplifier using OA0, OA1 and OA2 (Three opamps are not available on all devices. See device-specific data sheet for implementation.). The control register settings are shown in Table 20-5. The gain for the amplifier is selected by the OAFBRx bits of OA0 and OA2. The OAFBRx settings for both OA0 and OA2 must be equal. The gain settings are shown in Table 20-6. The OAx interconnections are shown in Figure 20-5. Table 20-5. Three-Opamp Differential Amplifier Control Register Settings Register OA0CTL0 OA0CTL1 OA1CTL0 OA1CTL1 OA2CTL0 OA2CTL1 Settings (binary) xx xx xx 0 0 xxx 001 0 x xx xx xx 0 0 000 111 0 x 11 11 xx x x xxx 110 0 x Table 20-6. Three-Opamp Differential Amplifier Gain Settings OA0/OA2 OAFBRx 000 001 010 011 100 101 110 111 Gain 0 1/3 1 1 2/3 3 4 1/3 7 15 V2 + R1 R2 OA0 − + V1 + OA2 − (V2 − V1) × R2 Vdiff = R1 OA1 − R1 R2 Figure 20-4. Three-Opamp Differential Amplifier 518 OA SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com OA Operation OAxI0 OA0I1 OAxIA OAxIB 0 1 OAPx 00 01 10 11 OAPx OAxI0 00 OA0I1 01 OAxIA 10 OAxIB 11 0 1 OAPMx 0 1 000 001 OAFBRx 010 3 000 011 000 001 100 4R else 101 4R 001 110 010 111 2R 011 2R 100 R 101 000 R 110 001 R 010 111 R 011 100 101 110 111 + OA0 − 0 OA0TAP (OA2) 1 000 OAFBRx 000 001 3 001 010 011 OAxRTOP 000 else 100 4R 001 101 4R 110 2R 010 111 011 2R 100 R 000 R 101 001 110 010 R 111 011 R 100 00 101 01 110 10 11 111 OAxFB 000 001 010 OAxRTOP 011 000 100 101 001 110 010 111 011 0 1 OAPMx + 000 OA1 001 − else 100 101 110 111 OAPMx + OA2 − 2 OAADCx Figure 20-5. Three-Opamp Differential Amplifier OAx Interconnections SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated OA 519 OA Registers 20.3 OA Registers The OA registers are listed in Table 20-7. Register OA0 control register 0 OA0 control register 1 OA1 control register 0 OA1 control register 1 OA2 control register 0 OA2 control register 1 Table 20-7. OA Registers Short Form OA0CTL0 OA0CTL1 OA1CTL0 OA1CTL1 OA2CTL0 OA2CTL1 Register Type Read/write Read/write Read/write Read/write Read/write Read/write www.ti.com Address 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR 520 OA SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 20.3.1 OAxCTL0, Opamp Control Register 0 OA Registers 7 rw-0 OANx OAPx OAPMx OAADCx 6 OANx rw-0 Bits 7-6 Bits 5-4 Bits 3-2 Bits 1-0 5 4 OAPx rw-0 rw-0 3 2 OAPMx rw-0 rw-0 1 0 OAADCx rw-0 rw-0 Inverting input select. These bits select the input signal for the OA inverting input. 00 OAxI0 01 OAxI1 10 OAxIA (see the device-specific data sheet for connected signal) 11 OAxIB (see the device-specific data sheet for connected signal) Non-inverting input select. These bits select the input signal for the OA non-inverting input. 00 OAxI0 01 OA0I1 10 OAxIA (see the device-specific data sheet for connected signal) 11 OAxIB (see the device-specific data sheet for connected signal) Slew rate select. These bits select the slew rate vs. current consumption for the OA. 00 Off, output high Z 01 Slow 10 Medium 11 Fast OA output select. These bits, together with the OAFCx bits, control the routing of the OAx output when OAPMx > 0. When OAFCx = 0: 00 OAxOUT connected to external pins and ADC input A1, A3, or A5 01 OAxOUT connected to external pins and ADC input A12, A13, or A14 10 OAxOUT connected to external pins and ADC input A1, A3, or A5 11 OAxOUT connected to external pins and ADC input A12, A13, or A14 When OAFCx > 0: 00 OAxOUT used for internal routing only 01 OAxOUT connected to external pins and ADC input A12, A13, or A14 10 OAxOUT connected to external pins and ADC input A1, A3, or A5 11 OAxOUT connected internally to ADC input A12, A13 , or A14. External A12, A13, or A14 pin connections are disconnected from the ADC. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated OA 521 OA Registers 20.3.2 OAxCTL1, Opamp Control Register 1 www.ti.com 7 rw-0 OAFBRx OAFCx OANEXT OARRIP 6 5 OAFBRx rw-0 rw-0 4 3 2 1 0 OAFCx OANEXT OARRIP rw-0 rw-0 rw-0 rw-0 rw-0 Bits 7-5 Bits 4-2 Bit 1 Bit 0 OAx feedback resistor select 000 Tap 0 - 0R/16R 001 Tap 1 - 4R/12R 010 Tap 2 - 8R/8R 011 Tap 3 - 10R/6R 100 Tap 4 - 12R/4R 101 Tap 5 - 13R/3R 110 Tap 6 - 14R/2R 111 Tap 7 - 15R/1R OAx function control. This bit selects the function of OAx 000 General purpose opamp 001 Unity gain buffer for three-opamp differential amplifier 010 Unity gain buffer 011 Comparator 100 Non-inverting PGA amplifier 101 Cascaded non-inverting PGA amplifier 110 Inverting PGA amplifier 111 Differential amplifier OAx inverting input externally available. This bit, when set, connects the inverting OAx input to the external pin when the integrated resistor network is used. 0 OAx inverting input not externally available 1 OAx inverting input externally available OAx reverse resistor connection in comparator mode 0 RTOP is connected to AVSS and RBOTTOM is connected to AVCC when OAFCx = 3 1 RTOP is connected to AVCC and RBOTTOM is connected to AVSS when OAFCx = 3. 522 OA SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 21 SLAU144J – December 2004 – Revised July 2013 Comparator_A+ Comparator_A+ is an analog voltage comparator. This chapter describes the operation of the Comparator_A+ of the 2xx family. Topic ........................................................................................................................... Page 21.1 Comparator_A+ Introduction ............................................................................. 524 21.2 Comparator_A+ Operation ................................................................................ 525 21.3 Comparator_A+ Registers ................................................................................. 530 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Comparator_A+ 523 Comparator_A+ Introduction www.ti.com 21.1 Comparator_A+ Introduction The Comparator_A+ module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals. Features of Comparator_A+ include: • Inverting and non-inverting terminal input multiplexer • Software selectable RC-filter for the comparator output • Output provided to Timer_A capture input • Software control of the port input buffer • Interrupt capability • Selectable reference voltage generator • Comparator and reference generator can be powered down • Input Multiplexer The Comparator_A+ block diagram is shown in Figure 21-1. P2CA4 P2CA0 00 CA0 01 CA1 10 CA2 11 VCC 0V CAEX 10 CAON CASHORT 000 CA1 001 CA2 010 CA3 011 CA4 100 CA5 101 CA6 110 CA7 111 P2CA3 P2CA2 P2CA1 0 1 ++ −− 0 1 CAREFx CARSEL 00 0 VCAREF 01 1 10 11 CAF 0 0 1 1 Tau ~ 2.0ns 0V 10 D G S 0.5xVCC 0.25xVCC CCI1B CAOUT Set_CAIFG Figure 21-1. Comparator_A+ Block Diagram NOTE: MSP430G2210: Channels 2, 5, 6, and 7 are available. Other channels should not be enabled. 524 Comparator_A+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Comparator_A+ Operation 21.2 Comparator_A+ Operation The Comparator_A+ module is configured with user software. The setup and operation of Comparator_A+ is discussed in the following sections. 21.2.1 Comparator The comparator compares the analog voltages at the + and - input terminals. If the + terminal is more positive than the - terminal, the comparator output CAOUT is high. The comparator can be switched on or off using control bit CAON. The comparator should be switched off when not in use to reduce current consumption. When the comparator is switched off, the CAOUT is always low. 21.2.2 Input Analog Switches The analog input switches connect or disconnect the two comparator input terminals to associated port pins using the P2CAx bits. Both comparator terminal inputs can be controlled individually. The P2CAx bits allow: • Application of an external signal to the + and - terminals of the comparator • Routing of an internal reference voltage to an associated output port pin Internally, the input switch is constructed as a T-switch to suppress distortion in the signal path. NOTE: Comparator Input Connection When the comparator is on, the input terminals should be connected to a signal, power, or ground. Otherwise, floating levels may cause unexpected interrupts and increased current consumption. NOTE: MSP430G2210: Comparator channels 0, 1, 3, and 4 are implemented but not available at the device pins. To avoid floating inputs, these comparator inputs should not be enabled. The CAEX bit controls the input multiplexer, exchanging which input signals are connected to the comparator’s + and - terminals. Additionally, when the comparator terminals are exchanged, the output signal from the comparator is inverted. This allows the user to determine or compensate for the comparator input offset voltage. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Comparator_A+ 525 Comparator_A+ Operation www.ti.com 21.2.3 Input Short Switch The CASHORT bit shorts the comparator_A+ inputs. This can be used to build a simple sample-and-hold for the comparator as shown in Figure 21-2. Sampling Capacitor, Cs CASHORT Analog Inputs Figure 21-2. Comparator_A+ Sample-And-Hold The required sampling time is proportional to the size of the sampling capacitor (CS), the resistance of the input switches in series with the short switch (Ri), and the resistance of the external source (RS). The total internal resistance (RI) is typically in the range of 2 to 10 kΩ. The sampling capacitor CS should be greater than 100 pF. The time constant, Tau, to charge the sampling capacitor CS can be calculated with the following equation: Tau = (RI + RS) x CS Depending on the required accuracy 3 to 10 Tau should be used as a sampling time. With 3 Tau the sampling capacitor is charged to approximately 95% of the input signals voltage level, with 5 Tau it is charge to more than 99% and with 10 Tau the sampled voltage is sufficient for 12-bit accuracy. 21.2.4 Output Filter The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an on-chip RC-filter. Any comparator output oscillates if the voltage difference across the input terminals is small. Internal and external parasitic effects and cross coupling on and between signal lines, power supply lines, and other parts of the system are responsible for this behavior as shown in Figure 21-3. The comparator output oscillation reduces accuracy and resolution of the comparison result. Selecting the output filter can reduce errors associated with comparator oscillation. 526 Comparator_A+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com + Terminal − Terminal Comparator_A+ Operation Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT Figure 21-3. RC-Filter Response at the Output of the Comparator 21.2.5 Voltage Reference Generator The voltage reference generator is used to generate VCAREF,which can be applied to either comparator input terminal. The CAREFx bits control the output of the voltage generator. The CARSEL bit selects the comparator terminal to which VCAREF is applied. If external signals are applied to both comparator input terminals, the internal reference generator should be turned off to reduce current consumption. The voltage reference generator can generate a fraction of the device’s VCC or a fixed transistor threshold voltage of ~0.55 V. 21.2.6 Comparator_A+, Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I/O port pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption. The CAPDx bits, when set, disable the corresponding pin input and output buffers as shown in Figure 214. When current consumption is critical, any port pin connected to analog signals should be disabled with its CAPDx bit. Selecting an input pin to the comparator multiplexer with the P2CAx bits automatically disables the input and output buffers for that pin, regardless of the state of the associated CAPDx bit. VCC VI VO ICC ICC VCC VI 0 VCC CAPD.x = 1 VSS Figure 21-4. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer NOTE: MSP430G2210:The channels 0, 1, 3, an 4 are implemented by not available at pins. To avoid floating inputs these inputs should not be used. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Comparator_A+ 527 Comparator_A+ Operation www.ti.com 21.2.7 Comparator_A+ Interrupts One interrupt flag and one interrupt vector are associated with the Comparator_A+ as shown in Figure 215. The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output, selected by the CAIES bit. If both the CAIE and the GIE bits are set, then the CAIFG flag generates an interrupt request. The CAIFG flag is automatically reset when the interrupt request is serviced or may be reset with software. SET_CAIFG VCC CAIES 0 D CAIE Q Reset 1 POR IRQ, Interrupt Service Requested IRACC, Interrupt RequestAccepted Figure 21-5. Comparator_A+ Interrupt System 21.2.8 Comparator_A+ Used to Measure Resistive Elements The Comparator_A+ can be optimized to precisely measure resistive elements using single slope analogto-digital conversion. For example, temperature can be converted into digital data using a thermistor, by comparing the thermistor’s capacitor discharge time to that of a reference resistor as shown in Figure 216. A reference resister Rref is compared to Rmeas. Rref Px.x Rmeas Px.y CA0 ++ −− CCI1B Capture Input Of Timer_A 0.25xVCC Figure 21-6. Temperature Measurement System The MSP430 resources used to calculate the temperature sensed by Rmeas are: • Two digital I/O pins to charge and discharge the capacitor. • I/O set to output high (VCC) to charge capacitor, reset to discharge. • I/O switched to high-impedance input with CAPDx set when not in use. • One output charges and discharges the capacitor via Rref. • One output discharges capacitor via Rmeas. • The + terminal is connected to the positive terminal of the capacitor. • The - terminal is connected to a reference level, for example 0.25 x VCC. • The output filter should be used to minimize switching noise. • CAOUT used to gate Timer_A CCI1B, capturing capacitor discharge time. More than one resistive element can be measured. Additional elements are connected to CA0 with available I/O pins and switched to high impedance when not being measured. 528 Comparator_A+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Comparator_A+ Operation The thermistor measurement is based on a ratiometric conversion principle. The ratio of two capacitor discharge times is calculated as shown in Figure 21-7. VC VCC 0.25 × VCC Rmeas Rref Phase I: Charge Phase II: Discharge Phase III: Phase IV: t Charge Discharge tref tmeas Figure 21-7. Timing for Temperature Measurement Systems The VCC voltage and the capacitor value should remain constant during the conversion, but are not critical since they cancel in the ratio: Nmeas = –Rmeas × C × ln Vref VCC Nref –Rref × C × ln Vref VCC Nmeas = Rmeas Nref Rref Rmeas = Rref × Nmeas Nref SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Comparator_A+ 529 Comparator_A+ Registers 21.3 Comparator_A+ Registers The Comparator_A+ registers are listed in Table 21-1. Register Comparator_A+ control register 1 Comparator_A+ control register 2 Comparator_A+ port disable Table 21-1. Comparator_A+ Registers Short Form CACTL1 CACTL2 CAPD Register Type Read/write Read/write Read/write Address 059h 05Ah 05Bh www.ti.com Initial State Reset with POR Reset with POR Reset with POR 530 Comparator_A+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 21.3.1 CACTL1, Comparator_A+ Control Register 1 Comparator_A+ Registers 7 CAEX rw-(0) CAEX CARSEL CAREF CAON CAIES CAIE CAIFG 6 CARSEL rw-(0) 5 4 CAREFx rw-(0) rw-(0) 3 CAON rw-(0) 2 CAIES rw-(0) 1 CAIE rw-(0) 0 CAIFG rw-(0) Bit 7 Bit 6 Bits 5-4 Bit 3 Bit 2 Bit 1 Bit 0 Comparator_A+ exchange. This bit exchanges the comparator inputs and inverts the comparator output. Comparator_A+ reference select. This bit selects which terminal the VCAREF is applied to. When CAEX = 0: 0 VCAREF is applied to the + terminal 1 VCAREF is applied to the - terminal When CAEX = 1: 0 VCAREF is applied to the - terminal 1 VCAREF is applied to the + terminal Comparator_A+ reference. These bits select the reference voltage VCAREF. 00 Internal reference off. An external reference can be applied. 01 0.25 × VCC 10 0.50 × VCC 11 Diode reference is selected Comparator_A+ on. This bit turns on the comparator. When the comparator is off it consumes no current. The reference circuitry is enabled or disabled independently. 0 Off 1 On Comparator_A+ interrupt edge select 0 Rising edge 1 Falling edge Comparator_A+ interrupt enable 0 Disabled 1 Enabled The Comparator_A+ interrupt flag 0 No interrupt pending 1 Interrupt pending SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated Comparator_A+ 531 Comparator_A+ Registers 21.3.2 CACTL2, Comparator_A+, Control Register www.ti.com 7 CASHORT rw-(0) 6 P2CA4 rw-(0) 5 P2CA3 rw-(0) 4 P2CA2 rw-(0) 3 P2CA1 rw-(0) 2 P2CA0 rw-(0) 1 CAF rw-(0) 0 CAOUT r-(0) CASHORT P2CA4 P2CA3 (1) P2CA2 P2CA1 P2CA0 CAF CAOUT Bit 7 Bit 6 Bits 5-3 Bit 2 Bit 1 Bit 0 Input short. This bit shorts the + and - input terminals. 0 Inputs not shorted 1 Inputs shorted Input select. This bit together with P2CA0 selects the + terminal input when CAEX = 0 and the - terminal input when CAEX = 1. Input select. These bits select the - terminal input when CAEX = 0 and the + terminal input when CAEX = 1. 000 No connection 001 CA1 010 CA2 011 CA3 100 CA4 101 CA5 110 CA6 111 CA7 Input select. This bit, together with P2CA4, selects the + terminal input when CAEX = 0 and the - terminal input when CAEX = 1. 00 No connection 01 CA0 10 CA1 11 CA2 Comparator_A+ output filter 0 Comparator_A+ output is not filtered 1 Comparator_A+ output is filtered Comparator_A+ output. This bit reflects the value of the comparator output. Writing this bit has no effect. (1) MSP430G2210: Only channels 2, 5, 6, and 7 are available. Other channels should not be selected. 21.3.3 CAPD, Comparator_A+, Port Disable Register 7 CAPD7 rw-(0) 6 CAPD6 rw-(0) 5 CAPD5 rw-(0) 4 CAPD4 rw-(0) 3 CAPD3 rw-(0) 2 CAPD2 rw-(0) 1 CAPD1 rw-(0) 0 CAPD0 rw-(0) CAPDx (1) Bits 7-0 Comparator_A+ port disable. These bits individually disable the input buffer for the pins of the port associated with Comparator_A+. For example, if CA0 is on pin P2.3, the CAPDx bits can be used to individually enable or disable each P2.x pin buffer. CAPD0 disables P2.0, CAPD1 disables P2.1, etc. 0 The input buffer is enabled. 1 The input buffer is disabled. (1) MSP430G2210: Channels 2, 5, 6, and 7 are available. Other channels should not be disabled. 532 Comparator_A+ SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 22 SLAU144J – December 2004 – Revised July 2013 ADC10 The ADC10 module is a high-performance 10-bit analog-to-digital converter. This chapter describes the operation of the ADC10 module of the 2xx family in general. There are device with less than eight external input channels. Topic ........................................................................................................................... Page 22.1 ADC10 Introduction ......................................................................................... 534 22.2 ADC10 Operation ............................................................................................. 536 22.3 ADC10 Registers ............................................................................................. 552 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 533 ADC10 Introduction www.ti.com 22.1 ADC10 Introduction The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC). The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention. The module can be configured with user software to support a variety of applications. ADC10 features include: • Greater than 200-ksps maximum conversion rate • Monotonic 10-bit converter with no missing codes • Sample-and-hold with programmable sample periods • Conversion initiation by software or Timer_A • Software selectable on-chip reference voltage generation (1.5 V or 2.5 V) • Software selectable internal or external reference • Up to eight external input channels (twelve on MSP430F22xx devices) • Conversion channels for internal temperature sensor, VCC, and external references • Selectable conversion clock source • Single-channel, repeated single-channel, sequence, and repeated sequence conversion modes • ADC core and reference voltage can be powered down separately • Data transfer controller for automatic storage of conversion results The block diagram of ADC10 is shown in Figure 22-1. 534 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC10 Introduction A0† A1† A2† A3† A4† A5† A6† A7† A12† A13† A14† A15† Ve REF+ REFOUT SREF1 0 VREF+ 1 REFBURST ADC10SR VREF−/VeREF− INCHx 4 Auto CONSEQx AVCC 11 10 01 00 AVSS 2_5V 1 on 0 1.5V or 2.5V Reference Ref_x REFON INCHx=0Ah AVCC SREF1 SREF0 ADC10OSC 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AVCC SREF2 10 ADC10ON ADC10SSELx ADC10DIVx Sample and Hold S/H VR− VR+ 10−bit SAR Convert BUSY Divider /1 .. /8 ADC10CLK ISSH SAMPCON Sample Timer SHI 0 /4/8/16/64 1 ADC10DF ADC10SHTx MSC 00 01 ACLK 10 MCLK 11 SMCLK ENC Sync SHSx 00 01 10 11 ADC10SC TA1 TA0 TA2‡ INCHx=0Bh Ref_x ADC10MEM R Data Transfer Controller n RAM, Flash, Peripherials ADC10SA R AVSS ADC10CT ADC10TB ADC10B1 †Channels A12-A15 are available in MSP430F22xx devices only. Channels A12-A15 tied to channel A11 in other devices. Not all channels are available in all devices. ‡TA1 on MSP430F20x2, MSP430G2x31, and MSP430G2x30 devices Figure 22-1. ADC10 Block Diagram SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 535 ADC10 Operation www.ti.com 22.2 ADC10 Operation The ADC10 module is configured with user software. The setup and operation of the ADC10 is discussed in the following sections. 22.2.1 10-Bit ADC Core The ADC core converts an analog input to its 10-bit digital representation and stores the result in the ADC10MEM register. The core uses two programmable/selectable voltage levels (VR+ and VR-) to define the upper and lower limits of the conversion. The digital output (NADC) is full scale (03FFh) when the input signal is equal to or higher than VR+, and zero when the input signal is equal to or lower than VR-. The input channel and the reference voltage levels (VR+ and VR-) are defined in the conversion-control memory. Conversion results may be in straight binary format or 2s-complement format. The conversion formula for the ADC result when using straight binary format is: NADC = 1023 × VIN – VR– VR+ – VR– The ADC10 core is configured by two control registers, ADC10CTL0 and ADC10CTL1. The core is enabled with the ADC10ON bit. With few exceptions the ADC10 control bits can only be modified when ENC = 0. ENC must be set to 1 before any conversion can take place. 22.2.1.1 Conversion Clock Selection The ADC10CLK is used both as the conversion clock and to generate the sampling period. The ADC10 source clock is selected using the ADC10SSELx bits and can be divided from 1 to 8 using the ADC10DIVx bits. Possible ADC10CLK sources are SMCLK, MCLK, ACLK, and internal oscillator ADC10OSC . The ADC10OSC, generated internally, is in the 5-MHz range, but varies with individual devices, supply voltage, and temperature. See the device-specific data sheet for the ADC10OSC specification. The user must ensure that the clock chosen for ADC10CLK remains active until the end of a conversion. If the clock is removed during a conversion, the operation does not complete, and any result is invalid. 22.2.2 ADC10 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection that can result from channel switching (see Figure 22-2). The input multiplexer is also a T-switch to minimize the coupling between channels. Channels that are not selected are isolated from the A/D, and the intermediate node is connected to analog ground (VSS) so that the stray capacitance is grounded to help eliminate crosstalk. The ADC10 uses the charge redistribution method. When the inputs are internally switched, the switching action may cause transients on the input signal. These transients decay and settle before causing errant conversion. R ~ 100Ohm INCHx Input Ax ESD Protection Figure 22-2. Analog Multiplexer 536 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC10 Operation 22.2.2.1 Analog Port Selection The ADC10 external inputs Ax, VeREF+,and VREF- share terminals with general purpose I/O ports, which are digital CMOS gates (see the device-specific data sheet). When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption. The ADC10AEx bits provide the ability to disable the port pin input and output buffers. ; P2.3 on MSP430F22xx device configured for analog input BIS.B #08h,&ADC10AE0 ; P2.3 ADC10 function and enable Devices which don’t have all the ADC10 external inputs channels Ax or VeREF+/VREF+ and VeREF-/VREFavailable at device pins must not alter the default register bit configuration of the not available pins. See device specific data sheet. 22.2.3 Voltage Reference Generator The ADC10 module contains a built-in voltage reference with two selectable voltage levels. Setting REFON = 1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V. When REF2_5V = 0, the reference is 1.5 V. The internal reference voltage may be used internally (REFOUT = 0) and, when REFOUT = 1, externally on pin VREF+. REFOUT = 1 should only be used if the pins VREF+and VREF- are available as device pins. External references may be supplied for VR+ and VR- through pins A4 and A3 respectively. When external references are used, or when VCC is used as the reference, the internal reference may be turned off to save power. An external positive reference VeREF+ can be buffered by setting SREF0 = 1 and SREF1 = 1 (only devices with VeREF+ pin). This allows using an external reference with a large internal resistance at the cost of the buffer current. When REFBURST = 1 the increased current consumption is limited to the sample and conversion period. External storage capacitance is not required for the ADC10 reference source as on the ADC12. 22.2.3.1 Internal Reference Low-Power Features The ADC10 internal reference generator is designed for low power applications. The reference generator includes a band-gap voltage source and a separate buffer. The current consumption of each is specified separately in the device-specific data sheet. When REFON = 1, both are enabled and when REFON = 0 both are disabled. The total settling time when REFON becomes set is approximately 30 µs. When REFON = 1, but no conversion is active, the buffer is automatically disabled and automatically reenabled when needed. When the buffer is disabled, it consumes no current. In this case, the bandgap voltage source remains enabled. When REFOUT = 1, the REFBURST bit controls the operation of the internal reference buffer. When REFBURST = 0, the buffer is on continuously, allowing the reference voltage to be present outside the device continuously. When REFBURST = 1, the buffer is automatically disabled when the ADC10 is not actively converting and is automatically re-enabled when needed. The internal reference buffer also has selectable speed versus power settings. When the maximum conversion rate is below 50 ksps, setting ADC10SR = 1 reduces the current consumption of the buffer approximately 50%. 22.2.4 Auto Power-Down The ADC10 is designed for low power applications. When the ADC10 is not actively converting, the core is automatically disabled and is automatically re-enabled when needed. The ADC10OSC is also automatically enabled when needed and disabled when not needed. When the core or oscillator is disabled, it consumes no current. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 537 ADC10 Operation www.ti.com 22.2.5 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following: • The ADC10SC bit • The Timer_A Output Unit 1 • The Timer_A Output Unit 0 • The Timer_A Output Unit 2 The polarity of the SHI signal source can be inverted with the ISSH bit. The SHTx bits select the sample period tsample to be 4, 8, 16, or 64 ADC10CLK cycles. The sampling timer sets SAMPCON high for the selected sample period after synchronization with ADC10CLK.Total sampling time is tsample plus tsync.The high-to-low SAMPCON transition starts the analog-to-digital conversion, which requires 13 ADC10CLK cycles as shown in Figure 22-3. Start Sampling Stop Start Sampling Conversion Conversion Complete SHI SAMPCON ADC10CLK tsync tsample 13 x ADC10CLKs tconvert Figure 22-3. Sample Timing 22.2.5.1 Sample Timing Considerations When SAMPCON = 0 all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time tsample, as shown in Figure 22-4. An internal MUX-on input resistance RI (2 kΩ maximum) in series with capacitor CI (27 pF maximum) is seen by the source. The capacitor CI voltage VC must be charged to within ½ LSB of the source voltage VS for an accurate 10-bit conversion. MSP430 VS RS VI RI VC CI VI = Input voltage at pin Ax VS = External source voltage RS = External source resistance RI = Internal MUX-on input resistance CI = Input capacitance VC = Capacitance-charging voltage Figure 22-4. Analog Input Equivalent Circuit The resistance of the source RS and RI affect tsample.The following equations can be used to calculate the minimum sampling time for a 10-bit conversion. tsample > (RS + RI) × ln(211) × CI Substituting the values for RI and CI given above, the equation becomes: tsample > (RS + 2 kΩ) × 7.625 × 27 pF 538 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC10 Operation For example, if RS is 10 kΩ, tsample must be greater than 2.47 µs. When the reference buffer is used in burst mode, the sampling time must be greater than the sampling time calculated and the settling time of the buffer, tREFBURST: { tsample > (RS + RI) × ln(211) × CI tREFBURST For example, if VRef is 1.5 V and RS is 10 kΩ, tsample must be greater than 2.47 µs when ADC10SR = 0, or 2.5 µs when ADC10SR = 1. See the device-specific data sheet for parameters. To calculate the buffer settling time when using an external reference, the formula is: tREFBURST = SR × VRef − 0.5 µs Where: SR = Buffer slew rate (~1 µs/V when ADC10SR = 0 and ~2 µs/V when ADC10SR = 1) VRef = External reference voltage 22.2.6 Conversion Modes The ADC10 has four operating modes selected by the CONSEQx bits as discussed in Table 22-1. CONSEQx 00 01 10 11 Table 22-1. Conversion Mode Summary Mode Single channel single-conversion Sequence-of-channels Repeat single channel Repeat sequence-of-channels Operation A single channel is converted once. A sequence of channels is converted once. A single channel is converted repeatedly. A sequence of channels is converted repeatedly. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 539 ADC10 Operation www.ti.com 22.2.6.1 Single-Channel Single-Conversion Mode A single channel selected by INCHx is sampled and converted once. The ADC result is written to ADC10MEM. Figure 22-5 shows the flow of the single-channel, single-conversion mode. When ADC10SC triggers a conversion, successive conversions can be triggered by the ADC10SC bit. When any other trigger source is used, ENC must be toggled between each conversion. CONSEQx = 00 ADC10 Off ADC10ON = 1 ENC = x = INCHx Wait for Enable ENC = SHS = 0 and ENC = ENC = 1 or and ADC10SC = Wait for Trigger ENC = 0 SAMPCON = (4/8/16/64) x ADC10CLK ENC = 0† Sample, Input Channel ENC = 0† Convert 12 x ADC10CLK 1 x ADC10CLK Conversion Completed, Result to ADC10MEM, ADC10IFG is Set x = input channel Ax † Conversion result is unpredictable Figure 22-5. Single-Channel Single-Conversion Mode 540 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC10 Operation 22.2.6.2 Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence stops after conversion of channel A0. Figure 22-6 shows the sequence-of-channels mode. When ADC10SC triggers a sequence, successive sequences can be triggered by the ADC10SC bit. When any other trigger source is used, ENC must be toggled between each sequence. CONSEQx = 01 ADC10 Off ADC10ON = 1 ENC = x = INCHx Wait for Enable ENC = SHS = 0 and ENC = ENC = 1 or and ADC10SC = Wait for Trigger If x > 0 then x = x −1 SAMPCON = x=0 (4/8/16/64) x ADC10CLK Sample, Input Channel Ax If x > 0 then x = x −1 MSC = 1 and x≠0 Convert 12 x ADC10CLK 1 x ADC10CLK Conversion Completed, Result to ADC10MEM, ADC10IFG is Set MSC = 0 and x ≠0 x = input channel Ax Figure 22-6. Sequence-of-Channels Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 541 ADC10 Operation www.ti.com 22.2.6.3 Repeat-Single-Channel Mode A single channel selected by INCHx is sampled and converted continuously. Each ADC result is written to ADC10MEM. Figure 22-7 shows the repeat-single-channel mode. CONSEQx = 10 ADC10 Off ADC10ON = 1 ENC = x = INCHx Wait for Enable ENC = SHS = 0 and ENC = ENC = 1 or and ADC10SC = Wait for Trigger SAMPCON = Sample, Input Channel Ax (4/8/16/64) × ADC10CLK ENC = 0 MSC = 1 and ENC = 1 Convert 12 x ADC10CLK 1 x ADC10CLK Conversion Completed, Result to ADC10MEM, ADC10IFG is Set MSC = 0 and ENC = 1 x = input channel Ax Figure 22-7. Repeat-Single-Channel Mode 542 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC10 Operation 22.2.6.4 Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The sequence begins with the channel selected by INCHx and decrements to channel A0. Each ADC result is written to ADC10MEM. The sequence ends after conversion of channel A0, and the next trigger signal re-starts the sequence. Figure 22-8 shows the repeat-sequence-of-channels mode. CONSEQx = 11 ADC10 Off ADC10ON = 1 ENC = x = INCHx Wait for Enable ENC = SHS = 0 and ENC = ENC = 1 or and ADC10SC = Wait for Trigger SAMPCON = Sample Input Channel Ax (4/8/16/64) x ADC10CLK If x = 0 then x = INCH else x = x −1 If x = 0 then x = INCH else x = x −1 12 x ADC10CLK MSC = 1 and (ENC = 1 or x ≠ 0) Convert 1 x ADC10CLK Conversion Completed, Result to ADC10MEM, ADC10IFG is Set MSC = 0 and (ENC = 1 or x ≠ 0) ENC = 0 and x=0 x = input channel Ax Figure 22-8. Repeat-Sequence-of-Channels Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 543 ADC10 Operation www.ti.com 22.2.6.5 Using the MSC Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1 and CONSEQx > 0, the first rising edge of the SHI signal triggers the first conversion. Successive conversions are triggered automatically as soon as the prior conversion is completed. Additional rising edges on SHI are ignored until the sequence is completed in the single-sequence mode or until the ENC bit is toggled in repeat-single-channel, or repeated-sequence modes. The function of the ENC bit is unchanged when using the MSC bit. 22.2.6.6 Stopping Conversions Stopping ADC10 activity depends on the mode of operation. The recommended ways to stop an active conversion or conversion sequence are: • Resetting ENC in single-channel single-conversion mode stops a conversion immediately and the results are unpredictable. For correct results, poll the ADC10BUSY bit until reset before clearing ENC. • Resetting ENC during repeat-single-channel operation stops the converter at the end of the current conversion. • Resetting ENC during a sequence or repeat sequence mode stops the converter at the end of the sequence. • Any conversion mode may be stopped immediately by setting the CONSEQx = 0 and resetting the ENC bit. Conversion data is unreliable. 22.2.7 ADC10 Data Transfer Controller The ADC10 includes a data transfer controller (DTC) to automatically transfer conversion results from ADC10MEM to other on-chip memory locations. The DTC is enabled by setting the ADC10DTC1 register to a nonzero value. When the DTC is enabled, each time the ADC10 completes a conversion and loads the result to ADC10MEM, a data transfer is triggered. No software intervention is required to manage the ADC10 until the predefined amount of conversion data has been transferred. Each DTC transfer requires one CPU MCLK. To avoid any bus contention during the DTC transfer, the CPU is halted, if active, for the one MCLK required for the transfer. A DTC transfer must not be initiated while the ADC10 is busy. Software must ensure that no active conversion or sequence is in progress when the DTC is configured: ; ADC10 activity test BIC.W #ENC,&ADC10CTL0 ; busy_test BIT.W #BUSY,&ADC10CTL1 ; JNZ busy_test ; MOV.W #xxx,&ADC10SA ; Safe MOV.B #xx,&ADC10DTC1 ; ; continue setup 544 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC10 Operation 22.2.7.1 One-Block Transfer Mode The one-block mode is selected if the ADC10TB is reset. The value n in ADC10DTC1 defines the total number of transfers for a block. The block start address is defined anywhere in the MSP430 address range using the 16-bit register ADC10SA. The block ends at ADC10SA + 2n – 2. The one-block transfer mode is shown in Figure 22-9. TB=0 DTC ’n’th transfer ADC10SA+2n−2 ADC10SA+2n−4 2nd transfer 1st transfer ADC10SA+2 ADC10SA Figure 22-9. One-Block Transfer The internal address pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to 'n'. The internal pointer and counter are not visible to software. The DTC transfers the word-value of ADC10MEM to the address pointer ADC10SA. After each DTC transfer, the internal address pointer is incremented by two and the internal transfer counter is decremented by one. The DTC transfers continue with each loading of ADC10MEM, until the internal transfer counter becomes equal to zero. No additional DTC transfers occur until a write to ADC10SA. When using the DTC in the one-block mode, the ADC10IFG flag is set only after a complete block has been transferred. Figure 22-10 shows a state diagram of the one-block mode. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 545 ADC10 Operation www.ti.com n=0 (ADC10DTC1) DTC reset n=0 n ≠0 Wait for write to ADC10SA DTC init Initialize Start Address in ADC10SA Write to ADC10SA x=n AD = SA n is latched in counter ’x’ Write to ADC10SA or n=0 Wait until ADC10MEM is written DTC idle Prepare DTC Write to ADC10SA Write to ADC10MEM completed Wait for CPU ready Synchronize with MCLK x>0 Write to ADC10SA 1 x MCLK cycle DTC operation Transfer data to Address AD AD = AD + 2 x=x−1 x=0 ADC10IFG=1 ADC10TB = 0 and ADC10CT = 1 ADC10TB = 0 and ADC10CT = 0 Figure 22-10. State Diagram for Data Transfer Control in One-Block Transfer Mode 546 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC10 Operation 22.2.7.2 Two-Block Transfer Mode The two-block mode is selected if the ADC10TB bit is set. The value n in ADC10DTC1 defines the number of transfers for one block. The address range of the first block is defined anywhere in the MSP430 address range with the 16-bit register ADC10SA. The first block ends at ADC10SA+2n-2. The address range for the second block is defined as SA+2n to SA+4n-2. The two-block transfer mode is shown in Figure 22-11. TB=1 2 x ’n’th transfer ADC10SA+4n−2 ADC10SA+4n−4 DTC ’n’th transfer ADC10SA+2n−2 ADC10SA+2n−4 2nd transfer 1st transfer ADC10SA+2 ADC10SA Figure 22-11. Two-Block Transfer The internal address pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to 'n'. The internal pointer and counter are not visible to software. The DTC transfers the word-value of ADC10MEM to the address pointer ADC10SA. After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one. The DTC transfers continue, with each loading of ADC10MEM, until the internal transfer counter becomes equal to zero. At this point, block one is full and both the ADC10IFG flag the ADC10B1 bit are set. The user can test the ADC10B1 bit to determine that block one is full. The DTC continues with block two. The internal transfer counter is automatically reloaded with 'n'. At the next load of the ADC10MEM, the DTC begins transferring conversion results to block two. After n transfers have completed, block two is full. The ADC10IFG flag is set and the ADC10B1 bit is cleared. User software can test the cleared ADC10B1 bit to determine that block two is full. Figure 22-12 shows a state diagram of the two-block mode. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 547 ADC10 Operation www.ti.com n=0 (ADC10DTC1) DTC reset ADC10B1 = 0 ADC10TB = 1 n=0 n≠0 Wait for write to ADC10SA DTC init Initialize Start Address in ADC10SA Prepare DTC Write to ADC10SA x=n If ADC10B1 = 0 then AD = SA n is latched in counter ’x’ Write to ADC10SA or n=0 Wait until ADC10MEM is written DTC idle Write to ADC10SA Write to ADC10MEM completed Wait for Synchronize CPU ready with MCLK x>0 Write to ADC10SA 1 x MCLK cycle DTC operation Transfer data to Address AD AD = AD + 2 x=x−1 x=0 ADC10IFG=1 Toggle ADC10B1 ADC10B1 = 1 or ADC10CT=1 ADC10CT = 0 and ADC10B1 = 0 Figure 22-12. State Diagram for Data Transfer Control in Two-Block Transfer Mode 548 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC10 Operation 22.2.7.3 Continuous Transfer A continuous transfer is selected if ADC10CT bit is set. The DTC does not stop after block one (in oneblock mode) or block two (in two-block mode) has been transferred. The internal address pointer and transfer counter are set equal to ADC10SA and n respectively. Transfers continue starting in block one. If the ADC10CT bit is reset, DTC transfers cease after the current completion of transfers into block one (in one-block mode) or block two (in two-block mode) have been transferred. 22.2.7.4 DTC Transfer Cycle Time For each ADC10MEM transfer, the DTC requires one or two MCLK clock cycles to synchronize, one for the actual transfer (while the CPU is halted), and one cycle of wait time. Because the DTC uses MCLK, the DTC cycle time is dependent on the MSP430 operating mode and clock system setup. If the MCLK source is active but the CPU is off, the DTC uses the MCLK source for each transfer, without re-enabling the CPU. If the MCLK source is off, the DTC temporarily restarts MCLK, sourced with DCOCLK, only during a transfer. The CPU remains off, and MCLK is again turned off after the DTC transfer. The maximum DTC cycle time for all operating modes is show in Table 22-2. Table 22-2. Maximum DTC Cycle Time CPU Operating Mode Clock Source Maximum DTC Cycle Time Active mode MCLK = DCOCLK 3 MCLK cycles Active mode MCLK = LFXT1CLK 3 MCLK cycles Low-power mode LPM0/1 MCLK = DCOCLK 4 MCLK cycles Low-power mode LPM3/4 MCLK = DCOCLK 4 MCLK cycles + 2 µs(1) Low-power mode LPM0/1 MCLK = LFXT1CLK 4 MCLK cycles Low-power mode LPM3 MCLK = LFXT1CLK 4 MCLK cycles Low-power mode LPM4 MCLK = LFXT1CLK 4 MCLK cycles + 2 µs(1) (1) The additional 2 µs are needed to start the DCOCLK. See the device-specific data sheet for parameters. 22.2.8 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, select the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversionmemory selection, etc. The typical temperature sensor transfer function is shown in Figure 22-13. When using the temperature sensor, the sample period must be greater than 30 µs. The temperature sensor offset error is large. Deriving absolute temperature values in the application requires calibration. See the device-specific data sheet for the parameters. See Section 24.2.2.1 for the calibration equations. Selecting the temperature sensor automatically turns on the on-chip reference generator as a voltage source for the temperature sensor. However, it does not enable the VREF+ output or affect the reference selections for the conversion. The reference choices for converting the temperature sensor are the same as with any other channel. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 549 ADC10 Operation Volts 1.300 www.ti.com 1.200 1.100 1.000 0.900 0.800 VTEMP=0.00355(TEMPC)+0.986 0.700 −50 0 Celsius 50 100 Figure 22-13. Typical Temperature Sensor Transfer Function 22.2.9 ADC10 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small, unwanted offset voltages that can add to or subtract from the reference or input voltages of the A/D converter. The connections shown in Figure 22-14 and Figure 22-15 help avoid this. In addition to grounding, ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result. A noise-free design is important to achieve high accuracy. Digital Power Supply Decoupling 10uF 100nF Analog Power Supply Decoupling (if available) 10uF 100nF DVCC DVSS AVCC AVSS Figure 22-14. ADC10 Grounding and Noise Considerations (Internal VREF) 550 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC10 Operation Digital Power Supply Decoupling 10uF Analog Power Supply Decoupling (if available) 100nF 10uF 100nF Using an External Positive Reference Using an External Negative Reference DVCC DVSS AVCC AVSS VREF+ /VeREF+ VREF- /VeREF- Figure 22-15. ADC10 Grounding and Noise Considerations (External VREF) 22.2.10 ADC10 Interrupts One interrupt and one interrupt vector are associated with the ADC10 as shown in Figure 22-16. When the DTC is not used (ADC10DTC1 = 0), ADC10IFG is set when conversion results are loaded into ADC10MEM. When DTC is used (ADC10DTC1 > 0), ADC10IFG is set when a block transfer completes and the internal transfer counter n = 0. If both the ADC10IE and the GIE bits are set, then the ADC10IFG flag generates an interrupt request. The ADC10IFG flag is automatically reset when the interrupt request is serviced, or it may be reset by software. ADC10IE Set ADC10IFG ’n’ = 0 ADC10CLK D Q Reset IRQ, Interrupt Service Requested POR IRACC, Interrupt RequestAccepted Figure 22-16. ADC10 Interrupt System SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 551 ADC10 Registers 22.3 ADC10 Registers The ADC10 registers are listed in Table 22-3. Register ADC10 input enable register 0 ADC10 input enable register 1 ADC10 control register 0 ADC10 control register 1 ADC10 memory ADC10 data transfer control register 0 ADC10 data transfer control register 1 ADC10 data transfer start address Table 22-3. ADC10 Registers Short Form ADC10AE0 ADC10AE1 ADC10CTL0 ADC10CTL1 ADC10MEM ADC10DTC0 ADC10DTC1 ADC10SA Register Type Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Address 04Ah 04Bh 01B0h 01B2h 01B4h 048h 049h 01BCh www.ti.com Initial State Reset with POR Reset with POR Reset with POR Reset with POR Unchanged Reset with POR Reset with POR 0200h with POR 552 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 22.3.1 ADC10CTL0, ADC10 Control Register 0 ADC10 Registers 15 rw-(0) 7 MSC rw-(0) SREFx ADC10SHTx ADC10SR REFOUT REFBURST MSC REF2_5V REFON ADC10ON ADC10IE 14 SREFx rw-(0) 13 rw-(0) 12 11 ADC10SHTx rw-(0) rw-(0) 6 REF2_5V rw-(0) 5 REFON rw-(0) 4 ADC10ON rw-(0) 3 ADC10IE rw-(0) Can be modified only when ENC = 0 10 ADC10SR rw-(0) 2 ADC10IFG rw-(0) 9 REFOUT rw-(0) 1 ENC rw-(0) 8 REFBURST rw-(0) 0 ADC10SC rw-(0) Bits 15-13 Bits 12-11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Select reference. 000 VR+ = VCC and VR- = VSS 001 VR+ = VREF+ and VR- = VSS 010 VR+ = VeREF+ and VR- = VSS. Devices with VeREF+ only. 011 VR+ = Buffered VeREF+ and VR- = VSS. Devices with VeREF+ pin only. 100 VR+ = VCC and VR- = VREF-/ VeREF-. Devices with VeREF- pin only. 101 VR+ = VREF+ and VR- = VREF-/ VeREF-. Devices with VeREF+/- pins only. 110 VR+ = VeREF+ and VR- = VREF-/ VeREF-. Devices with VeREF+/- pins only. 111 VR+ = Buffered VeREF+ and VR- = VREF-/ VeREF-. Devices with VeREF+/- pins only. ADC10 sample-and-hold time 00 4 × ADC10CLKs 01 8 × ADC10CLKs 10 16 × ADC10CLKs 11 64 × ADC10CLKs ADC10 sampling rate. This bit selects the reference buffer drive capability for the maximum sampling rate. Setting ADC10SR reduces the current consumption of the reference buffer. 0 Reference buffer supports up to ~200 ksps 1 Reference buffer supports up to ~50 ksps Reference output 0 Reference output off 1 Reference output on. Devices with VeREF+ / VREF+ pin only. Reference burst. 0 Reference buffer on continuously 1 Reference buffer on only during sample-and-conversion Multiple sample and conversion. Valid only for sequence or repeated modes. 0 The sampling requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and- conversions are performed automatically as soon as the prior conversion is completed Reference-generator voltage. REFON must also be set. 0 1.5 V 1 2.5 V Reference generator on 0 Reference off 1 Reference on ADC10 on 0 ADC10 off 1 ADC10 on ADC10 interrupt enable 0 Interrupt disabled 1 Interrupt enabled SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 553 ADC10 Registers ADC10IFG Bit 2 ENC Bit 1 ADC10SC Bit 0 www.ti.com ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion result. It is automatically reset when the interrupt request is accepted, or it may be reset by software. When using the DTC this flag is set when a block of transfers is completed. 0 No interrupt pending 1 Interrupt pending Enable conversion 0 ADC10 disabled 1 ADC10 enabled Start conversion. Software-controlled sample-and-conversion start. ADC10SC and ENC may be set together with one instruction. ADC10SC is reset automatically. 0 No sample-and-conversion start 1 Start sample-and-conversion 554 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 22.3.2 ADC10CTL1, ADC10 Control Register 1 ADC10 Registers 15 rw-(0) 7 rw-(0) 14 rw-(0) INCHx 13 rw-(0) 6 ADC10DIVx rw-(0) 5 rw-(0) Can be modified only when ENC = 0 12 rw-(0) 11 rw-(0) SHSx 10 rw-(0) 9 ADC10DF rw-(0) 4 3 ADC10SSELx rw-(0) rw-(0) 2 1 CONSEQx rw-(0) rw-(0) 8 ISSH rw-(0) 0 ADC10BUSY r-0 INCHx Bits 15-12 Input channel select. These bits select the channel for a single-conversion or the highest channel for a sequence of conversions. Only available ADC channels should be selected. See device specific data sheet. 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 1001 1010 VeREF+ VREF-/VeREFTemperature sensor SHSx Bits 11-10 1011 (VCC - VSS) / 2 1100 (VCC - VSS) / 2, A12 on MSP430F22xx devices 1101 (VCC - VSS) / 2, A13 on MSP430F22xx devices 1110 (VCC - VSS) / 2, A14 on MSP430F22xx devices 1111 (VCC - VSS) / 2, A15 on MSP430F22xx devices Sample-and-hold source select. 00 ADC10SC bit 01 Timer_A.OUT1 (1) 10 Timer_A.OUT0 (1) 11 Timer_A.OUT2 (Timer_A.OUT1 on MSP430F20x0, MSP430G2x31, and MSP430G2x30 devices)(1) ADC10DF Bit 9 ADC10 data format 0 Straight binary 1 2s complement ISSH Bit 8 Invert signal sample-and-hold 0 The sample-input signal is not inverted. 1 The sample-input signal is inverted. ADC10DIVx Bits 7-5 ADC10 clock divider 000 /1 001 /2 010 /3 011 /4 100 /5 101 /6 110 /7 111 /8 ADC10SSELx Bits 4-3 ADC10 clock source select 00 ADC10OSC 01 ACLK 10 MCLK 11 SMCLK (1) Timer triggers are from Timer0_Ax if more than one timer module exists on the device. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 555 ADC10 Registers CONSEQx Bits 2-1 ADC10BUSY Bit 0 Conversion sequence mode select 00 Single-channel-single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels ADC10 busy. This bit indicates an active sample or conversion operation 0 No operation is active. 1 A sequence, sample, or conversion is active. www.ti.com 22.3.3 ADC10AE0, Analog (Input) Enable Control Register 0 7 rw-(0) ADC10AE0x 6 rw-(0) 5 rw-(0) 4 3 ADC10AE0x rw-(0) rw-(0) 2 rw-(0) 1 rw-(0) 0 rw-(0) Bits 7-0 ADC10 analog enable. These bits enable the corresponding pin for analog input. BIT0 corresponds to A0, BIT1 corresponds to A1, etc. The analog enable bit of not implemented channels should not be programmed to 1. 0 Analog input disabled 1 Analog input enabled 22.3.4 ADC10AE1, Analog (Input) Enable Control Register 1 (MSP430F22xx only) 7 rw-(0) ADC10AE1x Reserved 6 5 ADC10AE1x rw-(0) rw-(0) 4 rw-(0) 3 rw-(0) 2 1 Reserved rw-(0) rw-(0) 0 rw-(0) Bits 7-4 Bits 3-0 ADC10 analog enable. These bits enable the corresponding pin for analog input. BIT4 corresponds to A12, BIT5 corresponds to A13, BIT6 corresponds to A14, and BIT7 corresponds to A15. The analog enable bit of not implemented channels should not be programmed to 1. 0 Analog input disabled 1 Analog input enabled Reserved 22.3.5 ADC10MEM, Conversion-Memory Register, Binary Format 15 0 r0 7 r Conversion Results 14 0 r0 6 r Bits 15-0 13 12 11 10 9 8 0 0 0 0 Conversion Results r0 r0 r0 r0 r r 5 4 3 2 1 0 Conversion Results r r r r r r The 10-bit conversion results are right justified, straight-binary format. Bit 9 is the MSB. Bits 15-10 are always 0. 556 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 22.3.6 ADC10MEM, Conversion-Memory Register, 2s Complement Format ADC10 Registers 15 14 r r 7 6 Conversion Results r r Conversion Results Bits 15-0 13 12 11 10 9 8 Conversion Results r r r r r r 5 4 3 2 1 0 0 0 0 0 0 0 r0 r0 r0 r0 r0 r0 The 10-bit conversion results are left-justified, 2s complement format. Bit 15 is the MSB. Bits 5-0 are always 0. 22.3.7 ADC10DTC0, Data Transfer Control Register 0 7 r0 Reserved ADC10TB ADC10CT ADC10B1 ADC10FETCH 6 5 Reserved r0 r0 4 3 2 1 0 ADC10TB ADC10CT ADC10B1 ADC10FETCH r0 rw-(0) rw-(0) r-(0) rw-(0) Bits 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved. Always read as 0. ADC10 two-block mode 0 One-block transfer mode 1 Two-block transfer mode ADC10 continuous transfer 0 Data transfer stops when one block (one-block mode) or two blocks (two-block mode) have completed. 1 Data is transferred continuously. DTC operation is stopped only if ADC10CT cleared, or ADC10SA is written to. ADC10 block one. This bit indicates for two-block mode which block is filled with ADC10 conversion results. ADC10B1 is valid only after ADC10IFG has been set the first time during DTC operation. ADC10TB must also be set. 0 Block 2 is filled 1 Block 1 is filled This bit should normally be reset. 22.3.8 ADC10DTC1, Data Transfer Control Register 1 7 rw-(0) 6 rw-(0) 5 rw-(0) 4 3 DTC Transfers rw-(0) rw-(0) 2 rw-(0) DTC Transfers Bits 7-0 DTC transfers. These bits define the number of transfers in each block. 0 DTC is disabled 01h-0FFh Number of transfers per block 1 rw-(0) 0 rw-(0) SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC10 557 ADC10 Registers 22.3.9 ADC10SA, Start Address Register for Data Transfer www.ti.com 15 rw-(0) 7 rw-(0) ADC10SAx Unused 14 rw-(0) 13 rw-(0) 12 11 ADC10SAx rw-(0) rw-(0) 10 rw-(0) 9 rw-(0) 8 rw-(0) 6 5 4 3 2 1 0 ADC10SAx 0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r0 Bits 15-1 Bit 0 ADC10 start address. These bits are the start address for the DTC. A write to register ADC10SA is required to initiate DTC transfers. Unused, Read only. Always read as 0. 558 ADC10 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 23 SLAU144J – December 2004 – Revised July 2013 ADC12 The ADC12 module is a high-performance 12-bit analog-to-digital converter. This chapter describes the ADC12 of the MSP430x2xx device family. Topic ........................................................................................................................... Page 23.1 ADC12 Introduction ......................................................................................... 560 23.2 ADC12 Operation ............................................................................................. 562 23.3 ADC12 Registers ............................................................................................. 574 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 559 ADC12 Introduction www.ti.com 23.1 ADC12 Introduction The ADC12 module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. ADC12 features include: • Greater than 200-ksps maximum conversion rate • Monotonic 12-bit converter with no missing codes • Sample-and-hold with programmable sampling periods controlled by software or timers • Conversion initiation by software, Timer_A, or Timer_B • Software selectable on-chip reference voltage generation (1.5 V or 2.5 V) • Software selectable internal or external reference • Eight individually configurable external input channels • Conversion channels for internal temperature sensor, AVCC, and external references • Independent channel-selectable reference sources for both positive and negative references • Selectable conversion clock source • Single-channel, repeat-single-channel, sequence, and repeat-sequence conversion modes • ADC core and reference voltage can be powered down separately • Interrupt vector register for fast decoding of 18 ADC interrupts • 16 conversion-result storage registers The block diagram of ADC12 is shown in Figure 23-1. 560 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC12 Introduction A0 A1 A2 A3 A4 A5 A6 A7 Floating Floating Floating Floating VeREF+ VREF+ V /Ve REF− REF− REF2_5V on 1.5 V or 2.5 V Reference REFON INCHx=0Ah AVCC INCHx 4 AVCC 11 10 01 00 AVSS Ref_x SREF1 SREF0 ADC12OSC 0000 SREF2 10 ADC12ON ADC12SSELx 0001 0010 ADC12DIVx 0011 0100 0101 0110 0111 1000 1001 Sample and Hold S/H VR− VR+ 12-bit SAR Convert 00 Divider 01 /1 ... /8 10 11 ADC12CLK ACLK MCLK SMCLK 1010 1011 1100 1101 1110 1111 AVCC SHP 1 SAMPCON 0 BUSY SHT0x ISSH 4 Sample Timer SHI 0 /4 ... /1024 1 4 ENC Sync SHSx 00 01 10 11 SHT1x MSC INCHx=0Bh ADC12SC TA1 TB0 TB1 Ref_x R R AVSS CSTARTADDx CONSEQx ADC12MEM0 − 16 x 12 Memory Buffer − ADC12MEM15 Figure 23-1. ADC12 Block Diagram ADC12MCTL0 − 16 x 8 Memory Control − ADC12MCTL15 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 561 ADC12 Operation www.ti.com 23.2 ADC12 Operation The ADC12 module is configured with user software. The setup and operation of the ADC12 is discussed in the following sections. 23.2.1 12-Bit ADC Core The ADC core converts an analog input to its 12-bit digital representation and stores the result in conversion memory. The core uses two programmable/selectable voltage levels (VR+ and VR-) to define the upper and lower limits of the conversion. The digital output (NADC) is full scale (0FFFh) when the input signal is equal to or higher than VR+, and the digital output is zero when the input signal is equal to or lower than VR-. The input channel and the reference voltage levels (VR+ and VR-) are defined in the conversion-control memory. The conversion formula for the ADC result NADC is: NADC = 4095 × VIN - VRVR+ - VR- The ADC12 core is configured by two control registers, ADC12CTL0 and ADC12CTL1. The core is enabled with the ADC12ON bit. The ADC12 can be turned off when not in use to save power. With few exceptions, the ADC12 control bits can only be modified when ENC = 0. ENC must be set to 1 before any conversion can take place. 23.2.1.1 Conversion Clock Selection The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse sampling mode is selected. The ADC12 source clock is selected using the ADC12SSELx bits and can be divided from 1 through 8 using the ADC12DIVx bits. Possible ADC12CLK sources are SMCLK, MCLK, ACLK, and an internal oscillator ADC12OSC. The ADC12OSC is generated internally and is in the 5-MHz range, but the frequency varies with individual devices, supply voltage, and temperature. See the device-specific data sheet for the ADC12OSC specification. The application must ensure that the clock chosen for ADC12CLK remains active until the end of a conversion. If the clock is removed during a conversion, the operation does not complete and any result is invalid. 23.2.2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer. The input multiplexer is a break-before-make type to reduce input-to-input noise injection that can result from channel switching (see Figure 23-2). The input multiplexer is also a T-switch to minimize the coupling between channels. Channels that are not selected are isolated from the A/D, and the intermediate node is connected to analog ground (AVSS) so that the stray capacitance is grounded to help eliminate crosstalk. The ADC12 uses the charge redistribution method. When the inputs are internally switched, the switching action may cause transients on the input signal. These transients decay and settle before causing errant conversion. R ~ 100 Ohm ADC12MCTLx.0−3 Input Ax 562 ADC12 ESD Protection Figure 23-2. Analog Multiplexer SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC12 Operation 23.2.2.1 Analog Port Selection The ADC12 inputs are multiplexed with the port P6 pins, which are digital CMOS gates. When analog signals are applied to digital CMOS gates, parasitic current can flow from VCC to GND. This parasitic current occurs if the input voltage is near the transition level of the gate. Disabling the port pin buffer eliminates the parasitic current flow and, therefore, reduces overall current consumption. The P6SELx bits provide the ability to disable the port pin input and output buffers. ; P6.0 and P6.1 configured for analog input BIS.B #3h,&P6SEL ; P6.1 and P6.0 ADC12 function 23.2.3 Voltage Reference Generator The ADC12 module contains a built-in voltage reference with two selectable voltage levels, 1.5 V and 2.5 V. Either of these reference voltages may be used internally and externally on pin VREF+. Setting REFON = 1 enables the internal reference. When REF2_5V = 1, the internal reference is 2.5 V. When REF2_5V = 0, the reference is 1.5 V. The reference can be turned off to save power when not in use. For proper operation, the internal voltage reference generator must be supplied with storage capacitance across VREF+ and AVSS. The recommended storage capacitance is a parallel combination of 10-µF and 0.1µF capacitors. From turn-on, a maximum of 17 ms must be allowed for the voltage reference generator to bias the recommended storage capacitors. If the internal reference generator is not used for the conversion, the storage capacitors are not required. NOTE: Reference Decoupling Approximately 200 µA is required from any reference used by the ADC12 while the two LSBs are being resolved during a conversion. A parallel combination of 10-µF and 0.1-µF capacitors is recommended for any reference as shown in Figure 23-11. External references may be supplied for VR+ and VR- through pins VeREF+ and VREF-/VeREF- respectively. 23.2.4 Sample and Conversion Timing An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The source for SHI is selected with the SHSx bits and includes the following: • The ADC12SC bit • The Timer_A Output Unit 1 • The Timer_B Output Unit 0 • The Timer_B Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit. The SAMPCON signal controls the sample period and start of conversion. When SAMPCON is high, sampling is active. The high-to-low SAMPCON transition starts the analog-to-digital conversion, which requires 13 ADC12CLK cycles. Two different sample-timing methods are defined by control bit SHP, extended sample mode and pulse mode. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 563 ADC12 Operation www.ti.com 23.2.4.1 Extended Sample Mode The extended sample mode is selected when SHP = 0. The SHI signal directly controls SAMPCON and defines the length of the sample period tsample. When SAMPCON is high, sampling is active. The high-tolow SAMPCON transition starts the conversion after synchronization with ADC12CLK (see Figure 23-3). Start Sampling Stop Sampling Start Conversion Conversion Complete SHI SAMPCON ADC12CLK tsample t sync 13 x ADC12CLK tconvert Figure 23-3. Extended Sample Mode 23.2.4.2 Pulse Sample Mode The pulse sample mode is selected when SHP = 1. The SHI signal is used to trigger the sampling timer. The SHT0x and SHT1x bits in ADC12CTL0 control the interval of the sampling timer that defines the SAMPCON sample period tsample. The sampling timer keeps SAMPCON high after synchronization with AD12CLK for a programmed interval tsample. The total sampling time is tsample plus tsync (see Figure 23-4). The SHTx bits select the sampling time in 4x multiples of ADC12CLK. SHT0x selects the sampling time for ADC12MCTL0 to 7 and SHT1x selects the sampling time for ADC12MCTL8 to 15. Start Sampling Stop Start Sampling Conversion Conversion Complete SHI SAMPCON ADC12CLK tsync tsample 13 x ADC12CLK tconvert Figure 23-4. Pulse Sample Mode 564 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC12 Operation 23.2.4.3 Sample Timing Considerations When SAMPCON = 0, all Ax inputs are high impedance. When SAMPCON = 1, the selected Ax input can be modeled as an RC low-pass filter during the sampling time tsample, as shown in Figure 23-5. An internal MUX-on input resistance RI (maximum of 2 kΩ) in series with capacitor CI (maximum of 40 pF) is seen by the source. The capacitor CI voltage (VC) must be charged to within 1/2 LSB of the source voltage (VS) for an accurate 12-bit conversion. MSP430 VS RS VI RI VC CI VI = Input voltage at pin Ax VS = External source voltage RS = External source resistance RI = Internal MUX-on input resistance CI = Input capacitance VC = Capacitance-charging voltage Figure 23-5. Analog Input Equivalent Circuit The resistance of the source RS and RI affect tsample. The following equation can be used to calculate the minimum sampling time tsample for a 12-bit conversion: tsample > (RS + RI) × ln(213) × CI + 800 ns Substituting the values for RI and CI given above, the equation becomes: tsample > (RS + 2 kΩ) × 9.011 × 40 pF + 800 ns For example, if RS is 10 kΩ, tsample must be greater than 5.13 µs. 23.2.5 Conversion Memory There are 16 ADC12MEMx conversion memory registers to store conversion results. Each ADC12MEMx is configured with an associated ADC12MCTLx control register. The SREFx bits define the voltage reference and the INCHx bits select the input channel. The EOS bit defines the end of sequence when a sequential conversion mode is used. A sequence rolls over from ADC12MEM15 to ADC12MEM0 when the EOS bit in ADC12MCTL15 is not set. The CSTARTADDx bits define the first ADC12MCTLx used for any conversion. If the conversion mode is single-channel or repeat-single-channel the CSTARTADDx points to the single ADC12MCTLx to be used. If the conversion mode selected is either sequence-of-channels or repeat-sequence-of-channels, CSTARTADDx points to the first ADC12MCTLx location to be used in a sequence. A pointer, not visible to software, is incremented automatically to the next ADC12MCTLx in a sequence when each conversion completes. The sequence continues until an EOS bit in ADC12MCTLx is processed; this is the last control byte processed. When conversion results are written to a selected ADC12MEMx, the corresponding flag in the ADC12IFGx register is set. 23.2.6 ADC12 Conversion Modes The ADC12 has four operating modes selected by the CONSEQx bits as shown in Table 23-1. CONSEQx 00 01 10 11 Table 23-1. Conversion Mode Summary Mode Single channel single-conversion Sequence-of-channels Repeat-single-channel Repeat-sequence-of-channels Operation A single channel is converted once. A sequence of channels is converted once. A single channel is converted repeatedly. A sequence of channels is converted repeatedly. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 565 ADC12 Operation www.ti.com 23.2.6.1 Single-Channel Single-Conversion Mode A single channel is sampled and converted once. The ADC result is written to the ADC12MEMx defined by the CSTARTADDx bits. Figure 23-6 shows the flow of the single-channel, single-conversion mode. When ADC12SC triggers a conversion, successive conversions can be triggered by the ADC12SC bit. When any other trigger source is used, ENC must be toggled between each conversion. CONSEQx = 00 ADC12 off ADC12ON = 1 ENC = x = CSTARTADDx Wait for Enable ENC = SHSx = 0 and ENC = ENC = 1 or and ADC12SC = Wait for Trigger ENC = 0 ENC = 0† SAMPCON = Sample, Input Channel Defined in ADC12MCTLx SAMPCON = 1 SAMPCON = 12 x ADC12CLK ENC = 0† Convert 1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set x = pointer to ADC12MCTLx † Conversion result is unpredictable Figure 23-6. Single-Channel, Single-Conversion Mode 566 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC12 Operation 23.2.6.2 Sequence-of-Channels Mode A sequence of channels is sampled and converted once. The ADC results are written to the conversion memories starting with the ADCMEMx defined by the CSTARTADDx bits. The sequence stops after the measurement of the channel with a set EOS bit. Figure 23-7 shows the sequence-of-channels mode. When ADC12SC triggers a sequence, successive sequences can be triggered by the ADC12SC bit. When any other trigger source is used, ENC must be toggled between each sequence. CONSEQx = 01 ADC12 off ADC12ON = 1 ENC = x = CSTARTADDx Wait for Enable ENC = SHSx = 0 and ENC = ENC = 1 or and ADC12SC = Wait for Trigger SAMPCON = EOS.x = 1 If x < 15 then x = x + 1 else x = 0 Sample, Input Channel Defined in ADC12MCTLx SAMPCON = 1 If x < 15 then x = x + 1 else x = 0 SAMPCON = MSC = 1 and SHP = 1 and EOS.x = 0 Convert 12 x ADC12CLK 1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set (MSC = 0 or SHP = 0) and EOS.x = 0 x = pointer to ADC12MCTLx Figure 23-7. Sequence-of-Channels Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 567 ADC12 Operation www.ti.com 23.2.6.3 Repeat-Single-Channel Mode A single channel is sampled and converted continuously. The ADC results are written to the ADC12MEMx defined by the CSTARTADDx bits. It is necessary to read the result after the completed conversion, because only one ADC12MEMx memory is used and is overwritten by the next conversion. Figure 23-8 shows repeat-single-channel mode. CONSEQx = 10 ADC12 off ADC12ON = 1 ENC = x = CSTARTADDx Wait for Enable ENC = SHSx = 0 and ENC = ENC = 1 or and ADC12SC = Wait for Trigger SAMPCON = Sample, Input Channel Defined in ADC12MCTLx SAMPCON = 1 MSC = 1 and SHP = 1 and ENC = 1 SAMPCON = Convert 12 x ADC12CLK 1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set (MSC = 0 or SHP = 0) and ENC = 1 ENC = 0 x = pointer to ADC12MCTLx Figure 23-8. Repeat-Single-Channel Mode 568 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC12 Operation 23.2.6.4 Repeat-Sequence-of-Channels Mode A sequence of channels is sampled and converted repeatedly. The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDx bits. The sequence ends after the measurement of the channel with a set EOS bit, and the next trigger signal re-starts the sequence. Figure 23-9 shows the repeat-sequence-of-channels mode. CONSEQx = 11 ADC12 off ADC12ON = 1 ENC = x = CSTARTADDx Wait for Enable ENC = SHSx = 0 and ENC = ENC = 1 or and ADC12SC = Wait for Trigger SAMPCON = ENC = 0 and SAMPCON = 1 EOS.x = 1 Sample, Input Channel Defined in ADC12MCTLx If EOS.x = 1 then x = CSTARTADDx SAMPCON = else {if x < 15 then x = x + 1 else x = 0} If EOS.x = 1 then x = CSTARTADDx else {if x < 15 then x = x + 1 else x = 0} Convert 12 x ADC12CLK MSC = 1 and SHP = 1 and (ENC = 1 or EOS.x = 0) 1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set (MSC = 0 or SHP = 0) and (ENC = 1 or EOS.x = 0) x = pointer to ADC12MCTLx Figure 23-9. Repeat-Sequence-of-Channels Mode SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 569 ADC12 Operation www.ti.com 23.2.6.5 Using the Multiple Sample and Convert (MSC) Bit To configure the converter to perform successive conversions automatically and as quickly as possible, a multiple sample and convert function is available. When MSC = 1, CONSEQx > 0, and the sample timer is used, the first rising edge of the SHI signal triggers the first conversion. Successive conversions are triggered automatically as soon as the prior conversion is completed. Additional rising edges on SHI are ignored until the sequence is completed in the single-sequence mode or until the ENC bit is toggled in repeat-single-channel or repeated-sequence modes. The function of the ENC bit is unchanged when using the MSC bit. 23.2.6.6 Stopping Conversions Stopping ADC12 activity depends on the mode of operation. The recommended ways to stop an active conversion or conversion sequence are: • Resetting ENC in single-channel single-conversion mode stops a conversion immediately and the results are unpredictable. For correct results, poll the busy bit until it is reset before clearing ENC. • Resetting ENC during repeat-single-channel operation stops the converter at the end of the current conversion. • Resetting ENC during a sequence or repeat-sequence mode stops the converter at the end of the sequence. • Any conversion mode may be stopped immediately by setting the CONSEQx = 0 and resetting ENC bit. In this case, conversion data are unreliable. NOTE: No EOS Bit Set For Sequence If no EOS bit is set and a sequence mode is selected, resetting the ENC bit does not stop the sequence. To stop the sequence, first select a single-channel mode and then reset ENC. 23.2.7 Using the Integrated Temperature Sensor To use the on-chip temperature sensor, select the analog input channel INCHx = 1010. Any other configuration is done as if an external channel was selected, including reference selection, conversionmemory selection, etc. The typical temperature sensor transfer function is shown in Figure 23-10. When using the temperature sensor, the sample period must be greater than 30 µs. The temperature sensor offset error can be large and needs to be calibrated for most applications. See the device-specific data sheet for parameters. See Section 24.2.2.1 for the calibration equations. Selecting the temperature sensor automatically turns on the on-chip reference generator as a voltage source for the temperature sensor. However, it does not enable the VREF+ output or affect the reference selections for the conversion. The reference choices for converting the temperature sensor are the same as with any other channel. 570 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Volts 1.300 ADC12 Operation 1.200 1.100 1.000 0.900 0.800 VTEMP=0.00355(TEMPC)+0.986 0.700 −50 0 Celsius 50 100 Figure 23-10. Typical Temperature Sensor Transfer Function 23.2.8 ADC12 Grounding and Noise Considerations As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. Ground loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A/D converter. The connections shown in Figure 23-11 help avoid this. In addition to grounding, ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result. A noise-free design using separate analog and digital ground planes with a single-point connection is recommend to achieve high accuracy. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 571 ADC12 Operation www.ti.com Digital Power Supply + Decoupling 10 uF 100 nF Analog Power Supply Decoupling + 10 uF 100 nF DVCC DVSS AV CC AV SS Using an External + Positive Reference 10 uF 100 nF Ve REF+ Using the Internal + Reference Generator 10 uF 100 nF VREF+ Using an External + Negative Reference 10 uF 100 nF VREF− / Ve REF− Figure 23-11. ADC12 Grounding and Noise Considerations 23.2.9 ADC12 Interrupts The ADC12 has 18 interrupt sources: • ADC12IFG0 to ADC12IFG15 • ADC12OV, ADC12MEMx overflow • ADC12TOV, ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result. An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set. The ADC12OV condition occurs when a conversion result is written to any ADC12MEMx before its previous conversion result was read. The ADC12TOV condition is generated when another sample-andconversion is requested before the current conversion is completed. The DMA is triggered after the conversion in single channel modes or after the completion of a sequence-of-channel modes. 23.2.9.1 ADC12IV, Interrupt Vector Generator All ADC12 interrupt sources are prioritized and combined to source a single interrupt vector. The interrupt vector register ADC12IV is used to determine which enabled ADC12 interrupt source requested an interrupt. The highest priority enabled ADC12 interrupt generates a number in the ADC12IV register (see Section 23.3.7). This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled ADC12 interrupts do not affect the ADC12IV value. Any access (read or write) of the ADC12IV register automatically resets the ADC12OV condition or the ADC12TOV condition if either was the highest pending interrupt. Neither interrupt condition has an accessible interrupt flag. The ADC12IFGx flags are not reset by an ADC12IV access. ADC12IFGx bits are reset automatically by accessing their associated ADC12MEMx register or may be reset with software. If another interrupt is pending after servicing of an interrupt, another interrupt is generated. For example, if the ADC12OV and ADC12IFG3 interrupts are pending when the interrupt service routine accesses the ADC12IV register, the ADC12OV interrupt condition is reset automatically. After the RETI instruction of the interrupt service routine is executed, the ADC12IFG3 generates another interrupt. 572 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ADC12 Operation 23.2.9.2 ADC12 Interrupt Handling Software Example Example 23-1 shows the recommended use of ADC12IV and the handling overhead. The ADC12IV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. The latencies are: • ADC12IFG0 to ADC12IFG14, ADC12TOV, and ADC12OV: 16 cycles • ADC12IFG15: 14 cycles The interrupt handler for ADC12IFG15 shows a way to check immediately if a higher prioritized interrupt occurred during the processing of ADC12IFG15. This saves nine cycles if another ADC12 interrupt is pending. Example 23-1. Interrupt Handling ; Interrupt handler for ADC12. INT_ADC12 ; Enter Interrupt Service Routine 6 ADD &ADC12IV,PC ; Add offset to PC 3 RETI ; Vector 0: No interrupt 5 JMP ADOV ; Vector 2: ADC overflow 2 JMP ADTOV ; Vector 4: ADC timing overflow 2 JMP ADM0 ; Vector 6: ADC12IFG0 2 ... ; Vectors 8-32 2 JMP ADM14 ; Vector 34: ADC12IFG14 2 ; ; Handler for ADC12IFG15 starts here. No JMP required. ; ADM15 MOV &ADC12MEM15,xxx ; Move result, flag is reset ... ; Other instruction needed? JMP INT_ADC12 ; Check other int pending ; ; ADC12IFG14-ADC12IFG1 handlers go here ; ADM0 MOV &ADC12MEM0,xxx ; Move result, flag is reset ... ; Other instruction needed? RETI ; Return 5 ; ADTOV ... ; Handle Conv. time overflow RETI ; Return 5 ; ADOV ... ; Handle ADCMEMx overflow RETI ; Return 5 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 573 ADC12 Registers 23.3 ADC12 Registers The ADC12 registers are listed in Table 23-2. Register ADC12 control register 0 ADC12 control register 1 ADC12 interrupt flag register ADC12 interrupt enable register ADC12 interrupt vector word ADC12 memory 0 ADC12 memory 1 ADC12 memory 2 ADC12 memory 3 ADC12 memory 4 ADC12 memory 5 ADC12 memory 6 ADC12 memory 7 ADC12 memory 8 ADC12 memory 9 ADC12 memory 10 ADC12 memory 11 ADC12 memory 12 ADC12 memory 13 ADC12 memory 14 ADC12 memory 15 ADC12 memory control 0 ADC12 memory control 1 ADC12 memory control 2 ADC12 memory control 3 ADC12 memory control 4 ADC12 memory control 5 ADC12 memory control 6 ADC12 memory control 7 ADC12 memory control 8 ADC12 memory control 9 ADC12 memory control 10 ADC12 memory control 11 ADC12 memory control 12 ADC12 memory control 13 ADC12 memory control 14 ADC12 memory control 15 Table 23-2. ADC12 Registers Short Form ADC12CTL0 ADC12CTL1 ADC12IFG ADC12IE ADC12IV ADC12MEM0 ADC12MEM1 ADC12MEM2 ADC12MEM3 ADC12MEM4 ADC12MEM5 ADC12MEM6 ADC12MEM7 ADC12MEM8 ADC12MEM9 ADC12MEM10 ADC12MEM11 ADC12MEM12 ADC12MEM13 ADC12MEM14 ADC12MEM15 ADC12MCTL0 ADC12MCTL1 ADC12MCTL2 ADC12MCTL3 ADC12MCTL4 ADC12MCTL5 ADC12MCTL6 ADC12MCTL7 ADC12MCTL8 ADC12MCTL9 ADC12MCTL10 ADC12MCTL11 ADC12MCTL12 ADC12MCTL13 ADC12MCTL14 ADC12MCTL15 Register Type Read/write Read/write Read/write Read/write Read Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Address 01A0h 01A2h 01A4h 01A6h 01A8h 0140h 0142h 0144h 0146h 0148h 014Ah 014Ch 014Eh 0150h 0152h 0154h 0156h 0158h 015Ah 015Ch 015Eh 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh www.ti.com Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR 574 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 23.3.1 ADC12CTL0, ADC12 Control Register 0 ADC12 Registers 15 rw-(0) 7 MSC rw-(0) SHT1x SHT0x MSC REF2_5V 14 rw-(0) SHT1x 13 rw-(0) 12 rw-(0) 6 REF2_5V rw-(0) 5 REFON rw-(0) 4 ADC120N rw-(0) Can be modified only when ENC = 0 11 rw-(0) 3 ADC12OVIE rw-(0) 10 rw-(0) SHT0x 9 rw-(0) 2 ADC12TOVIE rw-(0) 1 ENC rw-(0) 8 rw-(0) 0 ADC12SC rw-(0) Bits 15-12 Bits 11-8 Bit 7 Bit 6 Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM8 to ADC12MEM15. 0000 4 ADC12CLK cycles 0001 8 ADC12CLK cycles 0010 16 ADC12CLK cycles 0011 32 ADC12CLK cycles 0100 64 ADC12CLK cycles 0101 96 ADC12CLK cycles 0110 128 ADC12CLK cycles 0111 192 ADC12CLK cycles 1000 256 ADC12CLK cycles 1001 384 ADC12CLK cycles 1010 512 ADC12CLK cycles 1011 768 ADC12CLK cycles 1100 1024 ADC12CLK cycles 1101 1024 ADC12CLK cycles 1110 1024 ADC12CLK cycles 1111 1024 ADC12CLK cycles Sample-and-hold time. These bits define the number of ADC12CLK cycles in the sampling period for registers ADC12MEM0 to ADC12MEM7. 0000 4 ADC12CLK cycles 0001 8 ADC12CLK cycles 0010 16 ADC12CLK cycles 0011 32 ADC12CLK cycles 0100 64 ADC12CLK cycles 0101 96 ADC12CLK cycles 0110 128 ADC12CLK cycles 0111 192 ADC12CLK cycles 1000 256 ADC12CLK cycles 1001 384 ADC12CLK cycles 1010 512 ADC12CLK cycles 1011 768 ADC12CLK cycles 1100 1024 ADC12CLK cycles 1101 1024 ADC12CLK cycles 1110 1024 ADC12CLK cycles 1111 1024 ADC12CLK cycles Multiple sample and conversion. Valid only for sequence or repeated modes. 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1 The first rising edge of the SHI signal triggers the sampling timer, but further sample-and- conversions are performed automatically as soon as the prior conversion is completed. Reference generator voltage. REFON must also be set. 0 1.5 V 1 2.5 V SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 575 ADC12 Registers REFON Bit 5 ADC12ON Bit 4 ADC12OVIE Bit 3 ADC12TOVIE Bit 2 ENC Bit 1 ADC12SC Bit 0 www.ti.com Reference generator on 0 Reference off 1 Reference on ADC12 on 0 ADC12 off 1 ADC12 on ADC12MEMx overflow-interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 conversion-time-overflow interrupt enable. The GIE bit must also be set to enable the interrupt. 0 Conversion time overflow interrupt disabled 1 Conversion time overflow interrupt enabled Enable conversion 0 ADC12 disabled 1 ADC12 enabled Start conversion. Software-controlled sample-and-conversion start. ADC12SC and ENC may be set together with one instruction. ADC12SC is reset automatically. 0 No sample-and-conversion-start 1 Start sample-and-conversion 576 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 23.3.2 ADC12CTL1, ADC12 Control Register 1 ADC12 Registers 15 rw-(0) 7 rw-(0) 14 13 CSTARTADDx rw-(0) rw-(0) 6 ADC12DIVx rw-(0) 5 rw-(0) Can be modified only when ENC = 0 12 rw-(0) 11 rw-(0) SHSx 10 rw-(0) 9 SHP rw-(0) 4 3 ADC12SSELx rw-(0) rw-(0) 2 1 CONSEQx rw-(0) rw-(0) 8 ISSH rw-(0) 0 ADC12BUSY rw-(0) CSTARTADDx SHSx SHP ISSH ADC12DIVx ADC12SSELx CONSEQx ADC12BUSY Bits 15-12 Bits 11-10 Bit 9 Bit 8 Bits 7-5 Bits 4-3 Bits 2-1 Bit 0 Conversion start address. These bits select which ADC12 conversion-memory register is used for a single conversion or for the first conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15. Sample-and-hold source select 00 ADC12SC bit 01 Timer_A.OUT1 10 Timer_B.OUT0 11 Timer_B.OUT1 Sample-and-hold pulse-mode select. This bit selects the source of the sampling signal (SAMPCON) to be either the output of the sampling timer or the sample-input signal directly. 0 SAMPCON signal is sourced from the sample-input signal. 1 SAMPCON signal is sourced from the sampling timer. Invert signal sample-and-hold 0 The sample-input signal is not inverted. 1 The sample-input signal is inverted. ADC12 clock divider 000 /1 001 /2 010 /3 011 /4 100 /5 101 /6 110 /7 111 /8 ADC12 clock source select 00 ADC12OSC 01 ACLK 10 MCLK 11 SMCLK Conversion sequence mode select 00 Single-channel, single-conversion 01 Sequence-of-channels 10 Repeat-single-channel 11 Repeat-sequence-of-channels ADC12 busy. This bit indicates an active sample or conversion operation. 0 No operation is active. 1 A sequence, sample, or conversion is active. SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 577 ADC12 Registers 23.3.3 ADC12MEMx, ADC12 Conversion Memory Registers www.ti.com 15 0 r0 7 rw Conversion Results 14 0 r0 6 rw Bits 15-0 13 12 11 10 9 8 0 0 Conversion Results r0 r0 rw rw rw rw 5 4 3 2 1 0 Conversion Results rw rw rw rw rw rw The 12-bit conversion results are right-justified. Bit 11 is the MSB. Bits 15-12 are always 0. Writing to the conversion memory registers corrupts the results. 23.3.4 ADC12MCTLx, ADC12 Conversion Memory Control Registers 7 EOS rw-(0) EOS SREFx INCHx 6 rw-(0) 5 SREFx rw-(0) Can be modified only when ENC = 0 4 rw-(0) 3 rw-(0) 2 rw-(0) INCHx 1 rw-(0) Bit 7 Bits 6-4 Bits 3-0 End of sequence. Indicates the last conversion in a sequence. 0 Not end of sequence 1 End of sequence Select reference 000 VR+ = AVCC and VR- = AVSS 001 VR+ = VREF+ and VR- = AVSS 010 VR+ = VeREF+ and VR- = AVSS 011 VR+ = VeREF+ and VR- = AVSS 100 VR+ = AVCC and VR- = VREF-/ VeREF- 101 VR+ = VREF+ and VR- = VREF-/ VeREF- 110 VR+ = VeREF+ and VR- = VREF-/ VeREF- 111 VR+ = VeREF+ and VR- = VREF-/ VeREF- Input channel select 0000 A0 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 1001 1010 VeREF+ VREF- /VeREFTemperature diode 1011 (AVCC - AVSS) / 2 1100 GND 1101 GND 1110 GND 1111 GND 0 rw-(0) 578 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 23.3.5 ADC12IE, ADC12 Interrupt Enable Register ADC12 Registers 15 ADC12IE15 rw-(0) 7 ADC12IE7 rw-(0) ADC12IEx 14 ADC12IE14 rw-(0) 13 ADC12IE13 rw-(0) 12 ADC12IE12 rw-(0) 11 ADC12IE11 rw-(0) 10 ADC12IE10 rw-(0) 9 ADC12IFG9 rw-(0) 6 ADC12IE6 rw-(0) 5 ADC12IE5 rw-(0) 4 ADC12IE4 rw-(0) 3 ADC12IE3 rw-(0) 2 ADC12IE2 rw-(0) 1 ADC12IE1 rw-(0) Bits 15-0 Interrupt enable. These bits enable or disable the interrupt request for the ADC12IFGx bits. 0 Interrupt disabled 1 Interrupt enabled 8 ADC12IE8 rw-(0) 0 ADC12IE0 rw-(0) 23.3.6 ADC12IFG, ADC12 Interrupt Flag Register 15 ADC12IFG15 rw-(0) 7 ADC12IFG7 rw-(0) ADC12IFGx 14 ADC12IFG14 rw-(0) 13 ADC12IFG13 rw-(0) 12 ADC12IFG12 rw-(0) 11 ADC12IFG11 rw-(0) 10 ADC12IFG10 rw-(0) 9 ADC12IFG9 rw-(0) 8 ADC12IFG8 rw-(0) 6 ADC12IFG6 rw-(0) 5 ADC12IFG5 rw-(0) 4 ADC12IFG4 rw-(0) 3 ADC12IFG3 rw-(0) 2 ADC12IFG2 rw-(0) 1 ADC12IFG1 rw-(0) 0 ADC12IFG0 rw-(0) Bits 15-0 ADC12MEMx Interrupt flag. These bits are set when corresponding ADC12MEMx is loaded with a conversion result. The ADC12IFGx bits are reset if the corresponding ADC12MEMx is accessed, or may be reset with software. 0 No interrupt pending 1 Interrupt pending SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated ADC12 579 ADC12 Registers 23.3.7 ADC12IV, ADC12 Interrupt Vector Register 15 0 r0 7 0 r0 ADC12IVx ADC12IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h 14 0 r0 6 0 r0 Bits 15-0 13 12 0 0 r0 r0 5 4 r-(0) r-(0) ADC12 interrupt vector value Interrupt Source No interrupt pending ADC12MEMx overflow Conversion time overflow ADC12MEM0 interrupt flag ADC12MEM1 interrupt flag ADC12MEM2 interrupt flag ADC12MEM3 interrupt flag ADC12MEM4 interrupt flag ADC12MEM5 interrupt flag ADC12MEM6 interrupt flag ADC12MEM7 interrupt flag ADC12MEM8 interrupt flag ADC12MEM9 interrupt flag ADC12MEM10 interrupt flag ADC12MEM11 interrupt flag ADC12MEM12 interrupt flag ADC12MEM13 interrupt flag ADC12MEM14 interrupt flag ADC12MEM15 interrupt flag 11 0 r0 3 ADC12IVx r-(0) Interrupt Flag ADC12IFG0 ADC12IFG1 ADC12IFG2 ADC12IFG3 ADC12IFG4 ADC12IFG5 ADC12IFG6 ADC12IFG7 ADC12IFG8 ADC12IFG9 ADC12IFG10 ADC12IFG11 ADC12IFG12 ADC12IFG13 ADC12IFG14 ADC12IFG15 10 9 0 0 r0 r0 2 1 r-(0) r-(0) Interrupt Priority Highest Lowest www.ti.com 8 0 r0 0 0 r0 580 ADC12 SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback Chapter 24 SLAU144J – December 2004 – Revised July 2013 TLV Structure The Tag-Length-Value (TLV) structure is used in selected MSP430x2xx devices to provide device-specific information in the device's flash memory SegmentA, such as calibration data. For the device-dependent implementation, see the device-specific data sheet. Topic ........................................................................................................................... Page 24.1 TLV Introduction .............................................................................................. 582 24.2 Supported Tags ............................................................................................... 583 24.3 Checking Integrity of SegmentA ........................................................................ 586 24.4 Parsing TLV Structure of Segment A .................................................................. 586 SLAU144J – December 2004 – Revised July 2013 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated TLV Structure 581 TLV Introduction www.ti.com 24.1 TLV Introduction The TLV structure stores device-specific data in SegmentA. The SegmentA content of an example device is shown in Table 24-1. Word Address 0x10FE 0x10FC 0x10FA 0x10F8 0x10F6 0x10F4 0x10F2 0x10F0 0x10EE 0x10EC 0x10EA 0x10E8 0x10E6 0x10E4 0x10E2 0x10E0 0x10DE 0x10DC 0x10DA 0x10D8 0x10D6 0x10D4 0x10D2 0x10D0 0x10CE 0x10CC 0x10CA 0x10C8 0x10C6 0x10C4 0x10C2 0x10C0 Table 24-1. Example SegmentA Structure Upper Byte Lower Byte CALBC1_1MHZ CALDCO_1MHZ CALBC1_8MHZ CALDCO_8MHZ CALBC1_12MHZ CALDCO_12MHZ CALBC1_16MHZ CALDCO_16MHZ 0x08 (LENGTH) TAG_DCO_30 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x08 (LENGTH) TAG_EMPTY CAL_ADC_25T85 CAL_ADC_25T30 CAL_ADC_25VREF_FACTOR CAL_ADC_15T85 CAL_ADC_15T30 CAL_ADC_15VREF_FACTOR CAL_ADC_OFFSET CAL_ADC_GAIN_FACTOR 0x10 (LENGTH) TAG_ADC12_1 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x16 (LENGTH) TAG_EMPTY 2s complement of bit-wise XOR Tag Address and Offset 0x10F6 + 0x0008 0x10F6 + 0x0006 0x10F6 + 0x0004 0x10F6 + 0x0002 0x10F6 0x10EC 0x10DA + 0x0010 0x10DA + 0x000E 0x10DA + 0x000C 0x10DA + 0x000A 0x10DA + 0x0008 0x10DA + 0x0006 0x10DA + 0x0004 0x10DA + 0x0002 0x10DA 0x10C2 0x10C0 The first two bytes of SegmentA (0x10C0 and 0x10C1) hold the checksum of the remainder of the segment (addresses 0x10C2 to 0x10FF). The first tag is located at address 0x10C2 and, in this example, is the TAG_EMPTY tag. The following byte (0x10C3) holds the length of the following structure. The length of this TAG_EMPTY structure is 0x16 and, therefore, the next tag, TAG_ADC12_1, is found at address 0x10DA. Again, the following byte holds the length of the TAG_ADC12_1 structure. The TLV structure maps the entire address range 0x10C2 to 0x10FF of the SegmentA. A program routine looking for tags starting at the SegmentA address 0x10C2 can extract all information even if it is stored at a different (device-specific) absolute address. 582 TLV Structure SLAU144J – December 2004 – Revised July 2013 Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Supported Tags 24.2 Supported Tags Each device contains a subset of the tags shown in Table 24-2. See the device-specific data sheet for details. Tag TAG_EMPTY TAG_DCO_30 TAG_ADC12_1 TAG_ADC10_1 Table 24-2. Supported Tags (Device Specific) Description Identifies an unused memory area Calibration values for the DCO at room temperature and DVCC = 3 V Calibration values for the ADC12 module Calibration values for the ADC10 module Value 0xFE 0x01 0x08 0x08 24.2.1 DCO Calibration TLV Structure For DCO calibration, the BCS+ registers (BCSCTL1 and DCOCTL) are used. The values stored in the flash information memory SegmentA are written to the BCS+ registers (see Table 24-3). Label CALBC1_1MHZ CALDCO_1MHZ CALBC1_8MHZ CALDCO_8MHZ CALBC1_12MHZ CALDCO_12MHZ CALBC1_16MHZ CALDCO_16MHZ Table 24-3. DCO Calibration Data (Device Specific) Description Value for the BCSCTL1 register for 1 MHz, TA = 25°C Value for the DCOCTL register for 1 MHz, TA = 25°C Value for the BCSCTL1 register for 8 MHz, TA = 25°C Value for the DCOCTL register for 8 MHz, TA = 25°C Value for the BCSCTL1 register for 12 MHz, TA = 25°C Value for the DCOCTL register for 12 MHz, TA = 25°C Value for the BCSCTL1 register for 16 MHz, TA = 25°C Value for the DCOCTL register for 16 MHz, TA = 25°C Offset 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 The calibration data for the DCO is available in all 2xx devices and is stored at the same absolute addresses. The device-specific SegmentA content is applied using the absolute addressing mode if the sample code shown in Example 24-1 is used. Example 24-1. Code Example Using Absolute Addressing Mode ; Calibrate the DCO to 1 MHz CLR.B &DCOCTL MOV.B &CALBC1_1MHZ,&BCSCTL1 MOV.B &CALDCO_1MHZ,&DCOCTL ; Select lowest DCOx ; and MODx settings ; Set RSELx ; Set DCOx and MODx The TLV structure allows use of the address of the TAG_DCO_30 tag to address the DCO registers. Example 24-2 shows how to address the DCO calibration data using the TAG_DCO_30 tag. Example 24-2. Code Example Using the TLV Structure ; Calibrate the DCO to 8 MHz ; It is assumed that R10 contains the address of the TAG_DCO_30 tag CLR.B &DCOCTL ; Select lowest DCOx and ; MODx