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Design of 26.5W Isolated Flyback Converter

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26.5W AC/DC Isolated Flyback Converter Design Designed by Sober Hu TASK : 26.5W 9-Outputs AC/DC Isolated Flyback Converter Design SPECIFICATION : Technical Specification on Sept 10, 2008 DATE : 15 Sept. 2008 Designed by Sober Hu Customer Specification fL := 100Hz fs := 100kHz Vo1 := 5.0V Io1_max := 2A Vo2 := 15.0V Vo3 := 15.0V Vo4 := 15.0V Vo5 := 24.0V Vo6 := 18.0V Vo7 := 18.0V Vo8 := 18.0V Vo9 := 18.0V Io2_max := 30mA Io3_max := 30mA Io4_max := 0.3A Io5_max := 0.1A Io6_max := 0.12A Io7_max := 0.12A Io8_max := 0.12A Io9_max := 0.12A Vr := 100mV ∆Vostep := 150mV ∆Io5V := Io1_max ⋅ 80% η := 0.70 Line frequency Switching frequency Main output voltage Main Nominal load current +5V Output ripple voltage +5VStep load output ripple voltage +5V Step load current amplitude Designed by Sober Hu Definition Of Symbols u(t) := Φ (t) mΩ := − 10 3Ω ms := − 10 3 s μs := − 10 6 s ns := − 10 9 s mW := − 10 3 W mJ := − 10 3 J μJ := − 10 6 J nC := − 10 9 C μm := − 10 6 m μo := 4 ⋅ π ⋅ − 10 7 H ⋅ − m 1 Unit step function Milliohm Millisecond Microsecond Nanosecond Milliwatts Millijoule Microjoule Nanocoulomb Micrometer Permeability of free space ρ ( θ) := 1.724[ 1 + 0.0042( θ − 20) ] − 10 6Ω ⋅ cm Resistivity of copper at θ degC Designed by Sober Hu Component Summary Primary FET - IRFBC30A - 600V, 3.6A, 2.2Ω ζirfbc30a := 1.7 Ronirfbc30a := 2.2Ω ⋅ ζirfbc30a Qgirfbc30a := 23nC VgMillerirfbc30a := 5.5V Vthirfbc30a := 4.5V Vdsirfbc30a := 25V Crssirfbc30a := 3.5pF Cissirfbc30a := 510pF Coss_effirfbc30a := 70pF Channel resistance elevation factor to 100 degC Channel resistance at 100 degC Total Gate charge at Vgs of 10V Gate Miller plateau from Gate Charge Curve Gate threshold voltage Vds test voltage for capacitance value Reverse transfer capacitance at Vds of 25V Input capacitance Effective output capacitance American Wire Gauge Table Formulae AWG := 10 , 11 .. 40 − AWG Dxbare (AWG) := 2.54 ⋅ 10 π 20 cm American wire gauge range Diameter of bare copper wire Dxinsulated (AWG) :=  Dxbare (AWG)  cm + 0.028 ⋅ Ax(AWG) := π ⋅ Dxbare ( 2 AWG) 4 Dxbare (AWG)  cm cm Diameter of wire with heavy insulation Bare copper cross section area Rx(θ , AWG) := ρ(θ) Ax ( AWG) Resistance per unit length of AWG Designed by Sober Hu Converter Parameters Ts := 1 fs Vgnom := 220V Vgmin := Vgnom ⋅ (1 − 20%) Vgmin = 176 V Vgmax := Vgnom ⋅ (1 + 20%) Vgmax = 264 V Converter period Nominal input voltage Minimum input voltage Maximum input voltage Pout1 := Vo1 ⋅ Io1_max + Vo2 ⋅ Io2_max + Vo3 ⋅ Io3_max Pout2 := Vo4 ⋅ Io4_max + Vo5 ⋅ Io5_max Pout3 := Vo6 ⋅ Io6_max + Vo7 ⋅ Io7_max + Vo8 ⋅ Io8_max + Vo9 ⋅ Io9_max Pout := Pout1 + Pout2 + Pout3 Pout = 26.44 W Designed by Sober Hu Input Capacitor and Minimum Input DC Voltage Cin := 3 μF W ⋅ Pout Cin = 79.32 ⋅ μF TC := 2ms Dch := TC ⋅ fL Cin := 100μF Estimated value Dch = 0.2 VMIN :=  ( ) 2 ⋅ Vgmin 2 − 2Pout ⋅ 1 − Dch η ⋅ Cin ⋅ fL VMIN = 236.45 V Minimum input DC voltage Cin := η ⋅ fL ⋅  2 ⋅ Pout Vgmin 2 − VMIN2 ⋅ asin   VMIN  2 ⋅ Vgmin Cin = 78.322 ⋅ μF Cin := 100μF VMAX := 2 ⋅ Vgmax VMAX = 373.352 V Dmax := 0.45 VRO := Dmax 1 − Dmax ⋅ VMIN VDS := VRO + VMAX Set maximum duty cycle at minimum input voltage VRO = 193.459 V VDS = 566.811 V Check Vds of primary MOSFET Designed by Sober Hu Primary Current Calculation IpAVG := Pout η ⋅ VMIN IpAVG = 0.16 A IP := 2 ⋅ Pout η ⋅ VMIN ⋅ Dmax IP = 0.71 A IpRMS := IP ⋅ Dmax 3 IpRMS = 0.275 A ( ) Lm := VMIN ⋅ Dmax 2 ⋅ η 2 ⋅ Pout ⋅ fs Lm = 1.499 ⋅ mH Lm := 2 ⋅ Pout η ⋅ 2 IP ⋅ fs Lm = 1.499 ⋅ mH Lm1 := VMIN ⋅ Dmax IP ⋅ fs Lm1 = 1.499 ⋅ mH Bm := 1500gauss KW := 0.15 Primary Inductance with Energy Transform Point Primary Inductance with Core Saturated Point Winding Utilized Factor KJ := 5 ⋅ A ⋅ − mm 2 AP :=     Bm ⋅ Lm1 ⋅ 2 IP KW ⋅ KJ ⋅  1.14  cm4   ⋅ 4 cm AP = 0.635 ⋅ cm4 AP3 :=   η ⋅ Bm ⋅ 1.6 ⋅ Pout fs ⋅ KW ⋅ KJ ⋅ 1.14 4 cm  ⋅ cm4 AP3 = 0.492 ⋅ 4 cm Designed by Sober Hu AP2 := η ⋅ Bm ⋅ 2 ⋅ Pout 3 ⋅ fs ⋅ KW ⋅ KJ Dmax 2 AP2 = 0.52 ⋅ cm4 AP4 := Lm ⋅ IP ⋅ IpRMS Bm ⋅ KW ⋅ KJ AP4 = 0.26 ⋅ 4 cm Power Transformer - EER28L/PC40 from TDK AeEER35 := 2 107mm AwEER35 := 2 152.7mm APEER35 := AeEER35 ⋅ AwEER35 APEER35 = 1.634 ⋅ 4 cm WtEER35 := 52g Effective cross section area Winding area base on BEER35-1112CPFR standard bobbin AeEE35 := 2 89.3mm AwEE35 := 2 88.7mm APEE35 := AeEE35 ⋅ AwEE35 APEE35 = 0.792 ⋅ 4 cm Effective cross section area Winding area base on BEE35-1112CPLFR standard bobbin WtEE35 := 57g AeEE32 := 2 83.2mm AwEE32 := 2 88.8mm APEE32 := AeEE32 ⋅ AwEE32 APEE32 = 0.739 ⋅ 4 cm WtEE32 := 32g AeEE30 := 2 109mm AwEE30 := 2 44.5mm APEE30 := AeEE30 ⋅ AwEE30 APEE30 = 0.485 ⋅ 4 cm WtEE30 := 32g AeEER28L := 81.4mm2 AwEER28L := 96.3mm2 APEER28L := AeEER28L ⋅ AwEER28L APEER28L = 0.784 ⋅ cm4 WtEER28L := 32g μiPC40 := 2300 VeEER28L := 3 6150mm Designed by Sober Hu Effective cross section area Winding area base on BEE33-1112CPLFR standard bobbin Effective cross section area Winding area base on BE30-1110CPFR standard bobbin Effective cross section area Winding area base on BEER28L-1110CPFR standard bobbin Initial permeability of PC40 core material Core volume leEER28L := 75.5mm ALEER28L_PC40 := 2520 ⋅ − 10 9H Tape := 0.06mm MLTEER28L := 2 ⋅ 3.14 ⋅ 7.0mm HwEER28L := 21.2 − 9.9 mm 2 BwEER28L := 2 ⋅ 12.53mm Kg2020 := 2 AeEER28L ⋅ AwEER28L MLTEER28L Designed by Sober Hu Effective path length Nominal inductance of ungapped core set Wrapping tape thickness Average length of turn Available winding height Available winding breadth Geometrical constant of core Designed by Sober Hu Power Transformer Flux Swing With EER28L-PC40 from TDK VF := 0.5V n := VRO Vo1 + VF Transformer primary to secondary turn ratio n = 35.174 Iplim := 1.35 ⋅ IP Iplim = 0.958 A BsPC40 := 3500gauss BrPC40 := 500gauss ( ) ∆BPC40 := 48% ⋅ BsPC40 − BrPC40 ∆BPC40 = 1.44 × 103 ⋅ gauss Npmin := Lm ⋅ Iplim AeEER28L ⋅ BsPC40 Npmin = 50.419 Npcal := VMIN ⋅ Dmax AeEER28L ⋅ ∆BPC40 ⋅ fs Npcal = 90.775 Np := 106 Select number of secondary turn Ns1cal := Np n Ns1cal = 3.014 Primary no of turns ( ) Ns1 := round Ns1cal Ns1 = 3 VF2 := 0.7V Vcc := 14V ( ) NVc := round Vcc + VF2 ⋅ Ns1 Vo1 + VF  ( ) Ns2 := round Vo2 + VF2 ⋅ Ns1 Vo1 + VF  ( ) Ns3 := round Vo3 + VF2 ⋅ Ns1 Vo1 + VF  ( ) Ns4 := round Vo4 + VF2 ⋅ Ns1 Vo1 + VF  ( ) Ns5 := round Vo5 + VF2 ⋅ Ns1 Vo1 + VF  ( ) Ns6 := round Vo6 + VF2 ⋅ Ns1 Vo1 + VF  ( ) Ns7 := round Vo7 + VF2 ⋅ Ns1 Vo1 + VF  ( ) Ns8 := round Vo8 + VF2 ⋅ Ns1 Vo1 + VF  ( ) Ns9 := round Vo9 + VF2 ⋅ Ns1 Vo1 + VF  NVc = 8 Ns2 = 9 Ns3 = 9 Ns4 = 9 Ns5 = 13 Ns6 = 10 Ns7 = 10 Ns8 = 10 Ns9 = 10 Designed by Sober Hu Verification of Design Parameters nact := Np Ns1 ( ) VROact := nact ⋅ Vo1 + VF VROact = 194.333 V Vdson := 0.5V ( ) D(Vg) := nact ⋅ Vo1 + VF ( ) nact ⋅ Vo1 + VF + Vg − Vdson Dmaxact := VROact VROact + VMIN − Vdson Dmaxact = 0.452 Dminact := VROact VROact + VMAX − Vdson Dminact = 0.343 Vdsact := VMAX + VROact Vdsact = 567.686 V lg := μo ⋅ AeEER28L ⋅   Np2 Lm − 1  ALEER28L_PC40  lg = 0.726 ⋅ mm Designed by Sober Hu Designed by Sober Hu Lmact := Np2 ⋅ μo ⋅ μiPC40 ⋅ AeEER28L leEER28L + μiPC40 ⋅ lg Lmact = 1.514 ⋅ mH Ipact := VMIN ⋅ Dmaxact Lmact ⋅ fs Bm := Lmact ⋅ Ipact Np ⋅ AeEER28L Ipact := VMAX ⋅ Dminact Lmact ⋅ fs Bm := Lmact ⋅ Ipact Np ⋅ AeEER28L Ipact = 0.705 A Bm = 0.124 T Ipact = 0.845 A Bm = 0.148 T Nom inductance with ungapped core set Bpp(Vg) := Vg ⋅ D(Vg) Np ⋅ AeEER28L ⋅ fs (( )) Bppmax := max Bpp Bpp VMAX VMIN   Bppmax = 0.148 T Check flux density of transformer Power Transformer Winding Current ip ( Vg) := Vg ⋅ D(Vg) Lmact ⋅ fs ( ) ip VMIN = 0.705 A Vout = Ls ⋅ Isp ⋅ fs Doff Isp ⋅ Doff Iout = 2 solve , Doff → 2 ⋅ Iout Isp Designed by Sober Hu D1off := 2 ⋅ Io1_max ⋅ Lmact ⋅ fs 2 nact ⋅ Vo1 I1sp := 2 ⋅ Io1_max D1off I1RMS := I1sp ⋅ D1off 3 D1off = 0.311 I1sp = 12.842 A I1RMS = 4.138 A I1AVG := 1 2 ⋅ I1sp ⋅ D1off I1AVG = 2 A Cp := 2 Number of switching pulse to display Imosfet (Vg , t) := d ← D(Vg) ip ← ip(Vg) ∑Cp−1 ip ⋅ fs ⋅ t − n  ⋅ ut − n  ⋅ u n + d − t  d  fs   fs   fs  n=0 Idiode (Vg , t) := d ← D(Vg) ip ← ip(Vg) ∑Cp−1 n=0 I+1s−pfDs..1⋅. Io1ffsp ⋅ t  − n+ fs d     u t   − n+ fs d  u 1 +   fs n − t   Designed by Sober Hu 10 ( ) Imosfet VMIN , t ( ) Idiode VMIN , t ( ) Imosfet VMAX , t ( ) Idiode VMAX , t 5 0 0 5×10− 6 D2off := 2 ⋅ Io2_max ⋅ Lmact ⋅ fs  Np Ns2 2  ⋅ Vo2 I2sp := 2 ⋅ Io2_max D2off I2RMS := I2sp ⋅ D2off 3 I2AVG := 1 2 ⋅ I2sp ⋅ D2off D3off := 2 ⋅ Io3_max ⋅ Lmact ⋅ fs  Np Ns3 2  ⋅ Vo3 I3sp := 2 ⋅ Io3_max D3off 1×10− 5 t 1.5×10− 5 2×10− 5 D2off = 0.066 I2sp = 0.908 A I2RMS = 0.135 A I2AVG = 0.03 A D3off = 0.066 I3sp = 0.908 A I3RMS := I3sp ⋅ D3off 3 D4off := 2 ⋅ Io4_max ⋅ Lmact ⋅ fs   Np Ns4 2  ⋅ Vo4 I4sp := 2 ⋅ Io4_max D4off I4RMS := I4sp ⋅ D4off 3 D5off := 2 ⋅ Io5_max ⋅ Lmact ⋅ fs   Np Ns5 2  ⋅ Vo5 I5sp := 2 ⋅ Io5_max D5off I5RMS := I5sp ⋅ D5off 3 D6off := 2 ⋅ Io6_max ⋅ Lmact ⋅ fs   Np Ns6 2  ⋅ Vo6 I6sp := 2 ⋅ Io6_max D6off I6RMS := I6sp ⋅ D6off 3 Designed by Sober Hu I3RMS = 0.135 A D4off = 0.209 I4sp = 2.872 A I4RMS = 0.758 A D5off = 0.138 I5sp = 1.452 A I5RMS = 0.311 A D6off = 0.134 I6sp = 1.791 A I6RMS = 0.378 A Designed by Sober Hu Evaluate Possible Wire Gauge Window area should be allocated according to the apparent current of individual winding IpRMS(Vg) := Vg ⋅ D(Vg) Lmact ⋅ fs ⋅ D ( Vg) 3 ( ) IpRMS VMIN = 0.274 A Kcutrf := 0.2 Sm := 2.5mm Aw := BwEER28L − 2 ⋅ Sm Aw = 20.06 ⋅ mm Window fill factor Safety creepage distance Available bobbin breadth Primary winding Np6 Axpri := Kcutrf ⋅ AwEER28L Np Axpri = 0.182 ⋅ mm2 ( ) KJP := IpRMS VMIN Ax ( 28) Dxp := Ax(28) ⋅ 4 π KJP = 3.363 ⋅ A 2 mm Dxp = 0.322 ⋅ mm turn_per_layerpri :=  floor Aw    Dxp  turn_per_layerpri = 62 Secondary winding Ns1 Axs1 := Kcutrf ⋅ AwEER28L Ns1 ⋅ 9 Axs1 = 0.713 ⋅ mm2 KJs1 := I1RMS Ax(28) ⋅ 12 Dxs1 := Ax(28) ⋅ 4 π KJs1 = 4.238 ⋅ A 2 mm Dxs1 = 0.322 ⋅ mm turn_per_layers1 :=  floor  Aw Dxs1 ⋅   12  turn_per_layers1 = 5 Secondary winding Ns4 Axs4 := Kcutrf ⋅ AwEER28L Ns4 ⋅ 9 Axs4 = 0.238 ⋅ mm2 KJs4 := I4RMS Ax(28) ⋅ 3 Dxs4 := Ax(28) ⋅ 4 π KJs4 = 3.105 ⋅ A 2 mm Dxs4 = 0.322 ⋅ mm turn_per_layers4 :=  floor  Aw Dxs4 ⋅   3 turn_per_layers4 = 20 Designed by Sober Hu Designed by Sober Hu Primary winding Np layerpri := round  Np   turn_per_layerpri  layerpri = 2 Secondary winding Ns1 layers1 := round  Ns1   turn_per_layers1  layers1 = 1 Secondary winding Ns4 layers4 :=  round Ns4  turn_per_layers4 +  0.05  layers4 = 1 ( ) StackUppri := layerpri ⋅ Dxp + Tape ( ) StackUpsec := 9 ⋅ layers1 ⋅ Dxs1 + Tape StackUppri = 0.764 ⋅ mm StackUpsec = 3.437 ⋅ mm TotalStackUpva := StackUppri + StackUpsec + 5 ⋅ Tape TotalStackUpva = 4.501 ⋅ mm Resistance per unit length at 100 degC Rwpri := Rx(100 , 28) Rwpri = 2.831 × − 10 3 ⋅ Ω ⋅ − cm 1 The dc resistance is then Rdcpri := MLTEER28L ⋅ Rwpri ⋅ Np Rdcpri = 1.319 ⋅ Ω Rws4 := Rx(100 , 28) Rws4 = 2.831 × − 10 3 ⋅ Ω ⋅ − cm 1 Rws1 := Rx(100 , 28) Rws1 = 2.831 × − 10 3 ⋅ Ω ⋅ − cm 1 Rdcs1 := MLTEER28L ⋅ Rws1 ⋅ Ns1 12 Rdcs1 = 3.111 ⋅ mΩ Designed by Sober Hu Rdcs4 := MLTEER28L ⋅ Rws4 ⋅ Ns4 3 Rdcs4 = 37.331 ⋅ mΩ The ac resistance is δskin := ρ ( 25) π ⋅ μo ⋅ fs δskin = 0.211 ⋅ mm Racpri := Dxbare (28) ⋅ Rdcpri δskin Racpri = 2.011 ⋅ Ω Racs1 := Dxbare (28) ⋅ Rdcs1 δskin Racs1 = 4.742 ⋅ mΩ Racs4 := Dxbare (28) ⋅ Rdcs4 δskin Racs4 = 56.905 ⋅ mΩ Transformer Copper Loss Pcutx(Vg) := IpRMS ← IpRMS( Vg) 2 IpRMS ⋅ Rdcpri + 2 IpRMS ⋅ Racpri + 2 I1RMS ⋅ Rdcs1 ⋅ 4 ... + 2 I1RMS ⋅ Racs1 ⋅ 4 ( ) Pcutx VMAX = 0.809 W ( ) Pcutx VMIN = 0.787 W Transformer Core Loss Estimation Core loss estimation based on empirical curve fit formula and fit parameters from TDK for PC40 material data within a frequency range of 100 to 200kHz, assumming transformer temperature of 100 degC. Designed by Sober Hu Cm := 0.928 x := 1.61 y := 2.68 Pcoretx ( Vg) := Cm ⋅  fs x  Hz  ⋅  Bpp(Vg)  2⋅T y  ⋅  W   3 m  ⋅ VeEER28L ( ) Pcoretx VMAX = 0.6 W Transformer core loss ( ) Pcoretx VMIN = 0.37 W Total Transformer Losses Ptx(Vg) := Pcutx(Vg) + Pcoretx(Vg) ( ) Ptx VMAX = 1.409 ⋅ W ( ) Ptx VMIN = 1.157 W Power transformer loss at high line, FL Loss at low line, FL 1.4 Ptx( Vg) 1.3 1.2 1.1 250 300 350 Vg Designed by Sober Hu Secondary Rectifier Stress Vs1diode := Vo1 + VMAX ⋅ Ns1 Np Vs2diode := Vo2 + VMAX ⋅ Ns2 Np Vs3diode := Vo3 + VMAX ⋅ Ns3 Np Vs4diode := Vo4 + VMAX ⋅ Ns4 Np Vs5diode := Vo5 + VMAX ⋅ Ns5 Np Vs6diode := Vo6 + VMAX ⋅ Ns6 Np Vs7diode := Vo7 + VMAX ⋅ Ns7 Np Vcdiode := Vcc + VMAX ⋅ NVc Np Vs1diode = 15.567 V Vs2diode = 46.7 V Vs3diode = 46.7 V Vs4diode = 46.7 V Vs5diode = 69.788 V Vs6diode = 53.222 V Vs7diode = 53.222 V Vcdiode = 42.178 V Pdrectifier := VF ⋅ Io1_max + VF2 ⋅ Io2_max + VF2 ⋅ Io3_max + VF2 ⋅ Io4_max + VF2 ⋅ Io5_max + 4 ⋅ VF2 ⋅ Io6_max Pdrectifier = 1.658 W Output Filtering Capacitance Stress Cout1 := 2200μF Cout2 := 220μF Cout3 := 220μF Cout4 := 440μF Cout5 := 220μF Cout6 := 220μF ESR1 := 5mΩ ESR2 := 20mΩ ESR3 := 20mΩ ESR4 := 10mΩ ESR5 := 20mΩ ESR6 := 20mΩ Is1cap := 2 I1RMS − 2 Io1_max ∆Vs1 := Io1_max ⋅ Dmax Cout1 ⋅ fs + I1sp ⋅ ESR1 Is2cap := 2 I2RMS − 2 Io2_max ∆Vs2 := Io2_max ⋅ Dmax Cout2 ⋅ fs + I2sp ⋅ ESR2 Is3cap := 2 I3RMS − 2 Io3_max Is1cap = 3.623 A ∆Vs1 = 0.068 V Is2cap = 0.131 A ∆Vs2 = 0.019 V Is3cap = 0.131 A ∆Vs3 := Io3_max ⋅ Dmax Cout3 ⋅ fs + I3sp ⋅ ESR3 Is4cap := 2 I4RMS − 2 Io4_max ∆Vs3 = 0.019 V Is4cap = 0.696 A ∆Vs4 := Io4_max ⋅ Dmax Cout4 ⋅ fs + I4sp ⋅ ESR4 Is5cap := 2 I5RMS − 2 Io5_max ∆Vs4 = 0.032 V Is5cap = 0.295 A Designed by Sober Hu Designed by Sober Hu ∆Vs5 := Io5_max ⋅ Dmax Cout5 ⋅ fs + I5sp ⋅ ESR5 Is6cap := 2 I6RMS − 2 Io6_max ∆Vs5 = 0.031 V Is6cap = 0.359 A ∆Vs6 := Io6_max ⋅ Dmax Cout6 ⋅ fs + I6sp ⋅ ESR6 ∆Vs6 = 0.038 V Capacitance requirement - Transient response dependence τ := 15 ⋅ Ts ∆Vocap = ∆Io ⋅ τ Co ∆Voesr = ∆Io ⋅ Resr ∆Vo = ∆Vocap + ∆Voesr ∆Vo = ∆Io ⋅ τ + ∆Io ⋅ Resr Co Co > τ ∆Vo − Resr ∆Io Assume delay time before converter response to a change in load current Capacitive voltage change due to load step Voltage change across esr due to a load step Output voltage change due to a load step ignoring effect of ESL Capacitance required for a voltage deviation of ∆Vo with say Resr no_of_cap := 1 Resr := ESR1 no_of_cap Resr = 5 ⋅ mΩ Select number of capacitor required Effective ESR with capacitor chosen Capacitor ripple current and effective current handling capacity ∆Icap := 2 I1RMS − 2 Io1_max AC rms current seen by cap ∆Icap = 3.623 A Designed by Sober Hu Output ripple voltage with selected capacitors ∆Vr := I1sp ⋅ ESR1 ∆Vr = 64.21 ⋅ mV Output ripple voltage due to esr Maximum output voltage ripple at room temperature At low temperature, esr of capacitor changes significantly Resrlotemp := Resr ⋅ 2 Resrlotemp = 0.01 Ω ∆Vrlotemp := ∆Icap ⋅ Resrlotemp ∆Vrlotemp = 0.036 V κripple := 1 − ∆Vrlotemp Vr κripple = 63.775 ⋅ % Maximum output ripple at low temperature Ripple voltage design margin at low temperature Step load ripple voltage Comin := no_of_cap ⋅ Cout1 ⋅ (1 − 10%)  ∆Vo := ∆Io5V ⋅ Resrlotemp + τ   Comin  ∆Vo = 0.137 ⋅ V Voltage change due to step load κstep := 1 − ∆Vo ∆Vostep κstep = 8.525 ⋅ % Estimate Power Loss In Capacitor ESR Pesr ( Vg) :=   ∆Icap ⋅ 2 1 2  ⋅ Resr 3 ( ) Pesr VMAX = 5.468 ⋅ mW Step response ripple deviation design margin at low temperature Designed by Sober Hu Design RCD Snubber Lpleak := Lmact ⋅ 0.2% Lpleak = 3.028 ⋅ μH Vsn := 220V KVsn := 5% Maximum snubber capacitor voltage VROact = 194.333 V PsnRES := 1 2 ⋅ Vsn ⋅ Ipact ⋅ fs ⋅ Lpleak Vsn − VROact ⋅ Ipact PsnRES = 0.926 W Rsn := Vsn2 PsnRES Csn := Vsn KVsn ⋅ Vsn ⋅ Rsn ⋅ fs Rsn = 52.244 ⋅ KΩ Csn = 3.828 ⋅ nF Primary FET Voltage Stress ( ) Vdsmax(Vg) := Vg + Vsn ⋅ 1 + KVsn 600 550 Vdsmax( Vg) 500 450 250 (( )) Vdsmax := max Vdsmax Vdsmax VMIN VMAX   300 350 Vg Vdsmax = 604.352 V Designed by Sober Hu Peak switch voltage stress at high line Designed by Sober Hu Primary Switch Current Main FET conducts the transformer primary current IQ(Vg , t) := Imosfet (Vg , t) Main switch current IQRMS( Vg) := Vg ⋅ D(Vg) Lmact ⋅ fs ⋅ D ( Vg) 3 IQpk(Vg) := Vg ⋅ D(Vg) Lmact ⋅ fs Main switch rms current Main switch peak current Primary FET Loss Estimation - IRFBC30A Gate drive loss Vgate := 10V Pgate := Vgate ⋅ Qgirfbc30a ⋅ fs Pgate = 0.023 W Saturation loss PQon ( Vg) := 2 IQRMS( Vg) ⋅ Ronirfbc30a ( ) PQon VMAX = 0.305 W ( ) PQon VMIN = 0.28 W Output capacitance loss Gate drive voltage Gate drive loss Saturation loss at high line, FL PQcap(Vg) := 1 2 ⋅ Coss_effirfbc30a ⋅ Vg2 ⋅ fs ( ) PQcap Vgmax = 0.244 W Output capacitance loss at high line Designed by Sober Hu Switch loss Vplt := VgMillerirfbc30a Vth := Vthirfbc30a Rgate := 5.6Ω ( ) Iga := Vgate − 0.5 ⋅ Vplt + Vth Rgate Iga = 0.893 A Igb := Vgate − Vplt Rgate Igb = 0.804 A Gate Miller plateau voltage Gate threshold voltage Gate series resistor Gate current that charges the input capacitance from from gate threshold to Vplt Gate current that discharge Miller capacitance Crss when drain voltage starts to fall to zero ton(Vg) := Cgd ← 2 ⋅ Crssirfbc30a ⋅ Vdsirfbc30a Vg Cissirfbc30a ⋅ Vplt − Vth Iga + Cgd ⋅ Vg 2 ⋅ Igb PQswitch_on (Vg) := ton ← ton(Vg) IQpk ← IQpk(Vg) 1 2 ⋅ Vg ⋅ IQpk ⋅ ton ⋅ fs ( ) PQswitch_on VMIN = 7.556 × − 10 3 W ( ) PQswitch_on VMAX = 0.016 W Assumming the same order of magnitude for the switch turn off lost with a fast turn off gate drive circuit, the total switch loss is, PQswitch ( Vg) := 2 ⋅ PQswitch_on(Vg) ( ) PQswitch VMIN = 0.015 W ( ) PQswitch VMAX = 0.031 W Total transitional loss at high line, FL Designed by Sober Hu Total Primary FET loss PQ( Vg) := Pgate + PQon(Vg) + PQcap(Vg) + PQswitch ( Vg) ( ) PQ VMIN = 0.514 W ( ) PQ VMAX = 0.847 W Primary switch losses at high line, FL Design Feeback Control Loop Bode Plot of Power Stage n := 0 , 1 .. 50 n 1+ f (n) := 10 10 Hz ω(n) := 2 ⋅ π ⋅ f (n) Gpwm := 1 2 ⋅ 2⋅2 2 + 750 ⋅ VMIN Gpwm = 0.797 ⋅ 1 V Small signal moel with feedfoward of UCC25706 Small signal model of DCM flyback converter operated in voltage mode control fz1 := 1 2π ⋅ Cout1 ⋅ ESR1  Np 2 ⋅ Vo1 ⋅ (1 − 2 D ( Vg) ) fz2(Vg) :=  Ns1  Io1_max 2π ⋅ Lmact ⋅ D(Vg) Np ⋅ (1 − D(Vg)) fo (Vg) := Ns1 2π ⋅ Lmact ⋅ Cout1 Np ⋅ Vo1 ⋅ (1 − D(Vg)) Ns1 Q(Vg) := Io1_max 2π ⋅ Lmact Cout1 fz1 = 14.469 ⋅ KHz ( ) fz2 VMIN = 218.443 ⋅ KHz ( ) fz2 VMAX = 413.81 ⋅ KHz ( ) fo VMIN = 1.69 ⋅ KHz ( ) fo VMAX = 2.026 ⋅ KHz Designed by Sober Hu Gdo(Vg) := Vg Np ⋅ (1 − D(Vg))2 Ns1 ( ) Tpwr (Vg , ω) :=  Gpwm ⋅ Gdo(Vg) ⋅ 1 +  1+ i⋅ω i⋅ 2π ω ⋅ fz1    ⋅  1  − 2π i⋅ω ⋅ fz2( Vg)    − ω2 2π ⋅ fo (Vg) ⋅ Q(Vg) 2π ⋅ fo (Vg) 2 ( ) Gpwr (Vg , ω) := 20 ⋅ log Tpwr (Vg , ω) ( ) Gpwrmin (ω) := Gpwr VMIN , ω ( ) Gpwrmax (ω) := Gpwr VMAX , ω ( ) Ppwr (Vg , ω) :=  180  π ⋅ arg Tpwr (Vg , ω) ( ) Ppwrmin (ω) := Ppwr VMIN , ω ( ) Ppwrmax (ω) := Ppwr VMAX , ω Gain - dB 50 38.75 27.5 16.25 5 − 6.25 − 17.5 − 28.75 − 40 10 Power Gain 100 1×103 1×104 1×105 1×106 Frequency Designed by Sober Hu Phase - Degrees 225 177.778 130.556 83.333 36.111 − 11.111 − 58.333 − 105.556 − 152.778 − 200 10 Power Stage Phase 100 1×103 1×104 1×105 1×106 Frequency Loop stability criteria How to arrange the crossover frequency? It is the best with as high as possible bandwidth. But the crossover frequency is limited by the parameters: 1. Sampling theory limit the crossover freqency not to over 1/2 operation frequency. 2. The effect fo right plane zero which is changed followed with input voltage, load, and filtering inductance. It can't be compensated. Therefore, the bandwidth shall be far away the right plane zero, 1/4--1/5 of RHZ. 3. The limitation of error amplifier bandwidth. 1/6-1/10 of operation frequency. ( ) fc := fz2 VMIN 30 fc = 7.281 ⋅ KHz fc := 3KHz ( ) Phase := −π +  atan fc   −  atan fc   ⋅ 180   fz1   fz2 VMIN  π Phase = −169.073 Designed by Sober Hu Because of LC resonant at the output, the phase big change and close to 180 degree. As a result, the compensation of type III will be used to boost the phase. Zero-pole arrangement: 1. 1st pole at the origin to boost the gain at the low frequencies. 2. 2 zeros at LC resonant point. 3. 2nd pole at the output capacitor esr zero. 4. 3nd pole at the RHZ. Bode Plot of Error Amplifier K-Factor Method: Pshift := 360 − ϕm Perrorpermitted := Pshift + Phase ϕm := 45 Pshift = 315 Perrorpermitted = 145.927 Kfac := tan 450  − Perrorpermitted 4 ⋅ π  180  fz3 := fc Kfac fz4 := fz3 fp2 := fc ⋅ Kfac fp3 := fp2 ( ) Gpwr.fc := Gpwr VMIN , 2π ⋅ fc Kfac = 4.016 fz3 = 0.747 ⋅ KHz fp2 = 12.049 ⋅ KHz Gpwr.fc = 18.471 Gerror.fz3 := −Gpwr.fc − 20 log fc   fz3  R3 C3 R1 Gerror.fz3 = −30.547 C2 C1 R2 Vref X1 Designed by Sober Hu R1 := 20KΩ −31.233 = 20 log R2   R1  solve , R2 → 0.54875690204124249564 ⋅ KΩ Gerror.fz3 R2 := R1 ⋅ 10 20 C2 := 1 2π ⋅ fp2 ⋅ R2 C1 := 1 2π ⋅ fz3 ⋅ R2 C3 := 1 2π ⋅ fz4 ⋅ R1 R3 := 1 2π ⋅ fp3 ⋅ C3 fp1 := 1 2π ⋅ R1 ⋅ C1 R2 = 0.594 ⋅ KΩ C2 = 0.022 ⋅ μF C1 = 0.359 ⋅ μF C3 = 0.011 ⋅ μF R3 = 1.24 ⋅ KΩ Designed by Sober Hu Tcomp (ω) := 1  + 2 i⋅ ⋅π ω ⋅ fz3   ⋅ 1  + 2 i⋅ ⋅π ω ⋅ fz4   i⋅ω 2 ⋅ π ⋅ fp1 ⋅  1 +  2 i⋅ ⋅π ω ⋅ fp2   ⋅  1  + 2 ⋅ i⋅ π ω ⋅ fp3   ( ) Gcomp (ω) := 20 ⋅ log Tcomp (ω) ( ) Pcomp (ω) :=  180  π ⋅ arg Tcomp (ω) Compensation Gain 5 −2 Gain - dB −9 − 16 − 23 − 30 10 100 1×103 1×104 1×105 1×106 Frequency Compensation Phase 50 Phase - Degrees 0 − 50 − 100 10 100 1×103 1×104 1×105 1×106 Frequency Gcompfc := Gcomp (2π ⋅ fc) Gcompfc = −18.471 Bode Plot of Closed-Loop ( ) ( ) Tloop Vin , ω := Tcomp (ω) ⋅ Tpwr Vin , ω ( ) ( ( ) ) Gloop Vin , ω := 20 ⋅ log Tloop Vin , ω ( ) Gmaxmax (ω) := Gloop VMAX , ω ( ) Pminmax(ω) := Ploop VMIN , ω Designed by Sober Hu ( ) ( ( )) Ploop Vin , ω :=  180 π  ⋅ arg Tloop Vin , ω ( ) Gminmax(ω) := Gloop VMIN , ω ( ) Pmaxmax (ω) := Ploop VMAX , ω Gain - dB 35 24.375 13.75 3.125 − 7.5 − 18.125 − 28.75 − 39.375 − 50 10 100 Min Vin Max Vin 0 dB Loop Gain 1×103 1×104 Frequency 1×105 1×106 Phase - Degrees 180 135 90 45 0 − 45 − 90 − 135 − 180 10 Loop Phase 100 1×103 1×104 1×105 1×106 Frequency Phaseloop := Phase + − π 2 + 2 atan fc    fz3  − atan fc    fp2  − atan fc    fp3  ⋅ 180 π Phaseloop = −135 Margin := 180 + Phaseloop Margin = 45 Designed by Sober Hu Designed by Sober Hu Designed by Sober Hu

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