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Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Abstract The phase shifted full bridge (PSFB) converter is used for DC-DC conversion in various applications, for example in telecom systems to convert a high voltage bus to an intermediate distribution voltage, typically closer to 48V. PSFB stage provides voltage translation as well as isolation from the line voltage, since this topology includes a transformer. This document presents the implementation details of a digitally controlled PSFB system implemented on the HVPSFB kit from Texas Instruments. This kit converts a 400V DC input to a regulated 12V DC output and is rated for operations up to 600W. Both peak current mode control (PCMC) and voltage mode control (VMC) implementations are described. These highly integrated microcontroller based realizations feature adaptive zero voltage switching (ZVS) and various synchronous rectification schemes, which are discussed here. Details for generating complex gate drive waveforms, required by these control schemes, and intelligent timing control, to optimize system performance under changing operating conditions, are provided. A step by step guide to run and get familiar with the HVPSFB project is also included. A constant high system efficiency above 10% rated load, novel PCMC waveform generation based on onchip hardware mechanisms, and simple system implementation are the highlights of this solution. NOTE: If you would like to quickly evaluate this kit without going through the implementation details, please follow the accompanying quick start guide (QSG-HVPSB-Rev1.1.pdf) instead of this document. An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 1 Copyright © 2014, Texas Instruments Incorporated General Texas Instruments High Voltage Evaluation (TI HV EVM) User Safety Guidelines www.ti.com WARNING Always follow TI’s setup and application instructions, including use of all interface components within their recommended electrical rated voltage and power limits. Always use electrical safety precautions to help ensure your personal safety and those working around you. Contact TI's Product Information Center http://support/ti./com for further information. Save all warnings and instructions for future reference. Failure to follow warnings and instructions may result in personal injury, property damage, or death due to electrical shock and burn hazards. The term TI HV EVM refers to an electronic device typically provided as an open framed, unenclosed printed circuit board assembly. It is intended strictly for use in development laboratory environments, solely for qualified professional users having training, expertise and knowledge of electrical safety risks in development and application of high voltage electrical circuits. Any other use and/or application are strictly prohibited by Texas Instruments. If you are not suitable qualified, you should immediately stop from further use of the HV EVM. 1. Work Area Safety (a) Keep work area clean and orderly. (b) Qualified observer(s) must be present anytime circuits are energized. (c) Effective barriers and signage must be present in the area where the TI HV EVM and its interface electronics are energized, indicating operation of accessible high voltages may be present, for the purpose of protecting inadvertent access. (d) All interface circuits, power supplies, evaluation modules, instruments, meters, scopes and other related apparatus used in a development environment exceeding 50Vrms/75VDC must be electrically located within a protected Emergency Power Off EPO protected power strip. (e) Use stable and nonconductive work surface. (f) Use adequately insulated clamps and wires to attach measurement probes and instruments. No freehand testing whenever possible. 2. Electrical Safety As a precautionary measure, it is always a good engineering practice to assume that the entire EVM may have fully accessible and active high voltages. (a) De-energize the TI HV EVM and all its inputs, outputs and electrical loads before performing any electrical or other diagnostic measurements. Revalidate that TI HV EVM power has been safely deenergized. (b) With the EVM confirmed de-energized, proceed with required electrical circuit configurations, wiring, measurement equipment connection, and other application needs, while still assuming the EVM circuit and measuring instruments are electrically live. (c) After EVM readiness is complete, energize the EVM as intended. WARNING: WHILE THE EVM IS ENERGIZED, NEVER TOUCH THE EVM OR ITS ELECTRICAL CIRCUITS AS THEY COULD BE AT HIGH VOLTAGES CAPABLE OF CAUSING ELECTRICAL SHOCK HAZARD. 3. Personal Safety (a) Wear personal protective equipment (for example, latex gloves or safety glasses with side shields) or protect EVM in an adequate lucent plastic box with interlocks to protect from accidental touch. Limitation for safe use: EVMs are not to be used as all or part of a production unit. 2 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Introduction 1 Introduction Phase shifted full bridge (PSFB) DC-DC converters are used frequently to step down high DC bus voltages and/or provide isolation in medium to high power applications like server power supplies, telecom rectifiers, battery charging systems, and renewable energy systems. Traditionally, micro-controllers have been restricted to only performing supervisory or communications tasks in these systems. With the availability of high performing micro-controller devices, it is now possible to use micro-controllers for closing control loops in these systems, in addition to handling the traditional micro-controller functions. The transition to digital power control means that functions that were previously implemented in hardware are now implemented in software. In addition to the flexibility this adds to the system, this simplifies the system considerably. These systems can implement advanced control strategies to optimally control the power stage under different conditions and also provide system level intelligence. A PSFB converter consists of four power electronic switches (like MOSFETs or IGBTs) that form a fullbridge on the primary side of the isolation transformer and diode rectifiers or MOSFET switches for synchronous rectification (SR) on the secondary side. This topology allows all the switching devices to switch with zero voltage switching (ZVS) resulting in lower switching losses and an efficient converter. In this work, ZVS for switches in the one leg of the full bridge and zero or low voltage or Low Voltage Switching for switches in the other leg is achieved across the complete load range, by changing deadtimes for primary side switches based on load conditions. For such an isolated topology, signal rectification is required on the secondary side. For systems with low output voltage and/or high output current ratings, implementing synchronous rectification instead of diode rectification achieves the best possible performance by avoiding diode rectification losses. In this work, current doubler synchronous rectification is implemented on the secondary side with different switching schemes to achieve optimum performance under varying load conditions. A DC-DC converter system can be controlled in various modes like voltage mode control (VMC), average current mode control (ACMC) or peak current mode control (PCMC). Implementing these different control modes for controlling the same power stage typically requires redesigning the control circuit along with some changes to the power stage sensing circuit. With a microcontroller based system, all these modes can be experimented with on the same design with minimal or no additional changes. Such a system is implemented here using VMC and PCMC control schemes. PCMC is a highly desired control scheme for power converters because of its inherent voltage feed forward, automatic cycle by cycle current limiting, flux balancing and other advantages. Implementing PCMC for a PSFB system requires complex PWM waveform generation with precise timing control. A new approach to this waveform generation is presented using TMS320F2802x and TMS320F2803x (Texas Instruments Piccolo series) microcontrollers without requiring any additional support circuitry. Unique programmable on-chip slope compensation hardware is used to provide appropriate slope compensation that guarantees open loop stability and eliminates/limits sub-harmonic oscillations at the output. For PCMC implementation with a micro-controller, the regulated output voltage is dependent on the amount of output voltage ripple, which in turn is dependent on the load. This relation is explained in detail and different solutions are suggested. Peak efficiency greater than 95% and efficiency greater than 90% down to 10% load is achieved with the 600W PSFB system used here. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 3 Copyright © 2014, Texas Instruments Incorporated Introduction www.ti.com 1.1 Basic Operation Figure 1 shows a simplified circuit of a phase shifted full bridge. MOSFET switches QA, QB, QC and QD form the full-bridge on the primary side of the transformer T1. QA and QB are switched at 50 % duty and 180 degree out of phase with each other. Similarly, QC and QD are switched at 50 % duty and 180 degree out of phase with each other. The PWM switching signals for leg QC – QD of the full bridge are phase shifted with respect to those for leg QA - QB. Amount of this phase shift decides the amount of overlap between diagonal switches, which in turn decides the amount of energy transferred. D1, D2 provide diode current doubler rectification on the secondary, while Lo and Co form the output filter. Inductor LR provides assistance to the transformer leakage inductance for resonance operation with MOSFET capacitance and facilitates Zero Voltage Switching (ZVS). Note the two different grounds G1 and G2 on the two sides of transformer T1. Figure 2 provides the switching waveforms for the system in Figure 1. Figure 1. A Phase-Shifted Full Bridge Circuit Figure 2. PSFB PWM Waveforms 4 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Introduction 1.2 PSFB Implementation on HVPSFB Board Figure 3 shows a simplified block diagram of the PSFB circuit implemented on the HVPSFB board. Switches QA, QB, QC and QD in Figure 3 correspond to switches Q1, Q4, Q2 and Q3 respectively. Switches Q5 and Q6 are used for synchronous rectification on the secondary. Figure 3. PSFB System Block Diagram The control algorithm is implemented on a C2000 microcontroller (MCU). The MCU interacts with the PSFB power stage by way of feedback signals and PWM outputs. The controller is placed on the secondary side on this design. Deciding on the placement of the controller with respect to the isolation boundary is a crucial step when designing an isolated DC-DC system. For systems that have multiple output rails or handle many signals and control loops on the secondary side or communicate with other systems in the application (on the secondary), placing the controller on the secondary side is more advantageous. Phase shift between PWM signals driving the two legs of the full bridge determines the amount of energy transferred to the load. This phase shift is the controlled parameter. MCU achieves DC – DC conversion by controlling this phase shift so as to regulate and maintain the output voltage at the commanded level. Controlling such a system in different operation modes requires generating complex PWM drive waveforms along with fast and efficient control loop calculations. This is made possible on C2000 microcontrollers by advanced on-chip control peripherals like PWM modules, analog comparators with DAC and slope compensation hardware and 12-bit high speed ADCs coupled with an efficient 32-bit CPU. A detailed description of the software algorithm is provided in the following chapters. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 5 Copyright © 2014, Texas Instruments Incorporated Introduction 1.3 Design Features • 400V DC input (370Vdc to 410Vdc operation), 12V DC output • Peak efficiency greater than 95%. Above 90% efficiency down to 10% load • 50 Amp (600 Watt) rated output • Phase Shifted Full-Bridge Circuit topology • 100 KHz switching frequency • Peak Current Mode Control (PCMC) with no external support circuitry for PCMC function • Multiple Synchronous Rectification (SR) switching schemes • Adaptive ZVS/LVS across the complete load range • Efficient GUI Interface that allows fast & easy system tuning for optimal performance • Fault protection: Input UV and OV, Over-current, Output UV (CC/CP mode) • Constant current (CC) and constant power (CP) functions • Optional Voltage Mode Control (VMC) www.ti.com 6 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com 1.4 Test Results Following provides some results obtained using this kit: HVPSFB 600W EVM - Efficiency 100 95 % Efficiency 90 85 PCMC VMC 80 75 70 65 60 2 6 12 18 24 30 37 43 49 55 61 67 73 79 85 91 98 % Load (1) Note that the auxiliary power is not included in the efficiency calculations. Figure 4. Efficiency Vs. Load (PCMC and VMC Implementations) Introduction A Load = 12A Figure 5. Active to Passive Leg Transitions (ZVS) Switching A Load = 12A Figure 7. Passive to Active Leg Transitions (LVS) Switching Figure 6. PCMC Transient Response (0% to 80% Load Step) Figure 8. PCMC Transient Response (80% to 0% Load Step) TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 7 Copyright © 2014, Texas Instruments Incorporated Introduction www.ti.com ZVS and/or LVS switching are achieved across the complete operating range. System efficiency of more than 90% is obtained for all loads greater than 10% rated load, while the peak efficiency is greater than 95%. Output peak deviations of less than 3% of rated output and settling times less than 250us are achieved for 80% step change in load. PCMC step response looks like a damped first order system. This C2000 MCU (TMS320F2802x) based implementation provides an ability to generate, and control, complex gate drive waveforms required for PCMC and VMC control schemes while still providing a level of intelligence unique to digitally controlled solutions. Following provides a snapshot of the PCMC GUI included in the software package accompanying this kit. A separate GUI for VMC implementation is also included. Figure 9. PCMC GUI 8 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com 1.5 Identifying Key Components on the Board Figure 10 shows key hardware components. Introduction Figure 10. HVPSFB Development Kit TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 9 Copyright © 2014, Texas Instruments Incorporated Introduction Figure 11 and Figure 12 provide the schematic diagram for the Piccolo-A controller card and the HVPSFB base board. www.ti.com Figure 11. MS320F28027(Piccolo-A) Controller Card Schematic 10 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com +VINB TP9 F1 390V/2A VIN+ 2 1 J1 VIN2 1 J2 R4 1.00M C2 + C3 0.47µF 330µF R14 1.00M R17 1.00M TP8 T3 56PR3362 8 R3 3.01 D2 1N4148W D7 MMSZ5242BT1G SPP20N60CFD Q1 R7 10.0k SPP20N60CFD R12 3.01 D9 Q4 1N4148W R16 D12 10.0k 5 6 7 MMSZ5242BT1G T1 PE63587 25 HS1 Q3,Q4 12 SPP20N60CFD R5 Q2 3.01 D3 1N4148W D8 R10 10.0k MMSZ5242BT1G R13 SPP20N60CFD 3.01 D10 Q3 1N4148W D5 MURS360T3G HS2 Q1, Q2 12 13 1 T2 75PR8107 3 10 J6 1 12 7 C20 1µF 9 C21 1µF 499 R25 499 R26 R15 10.0k D11 D13 MURS360T3G C13 5 6 7 8 T4 56PR3362 MMSZ5242BT1G 1000pF D1 1N4148W CS R1 R2 48.7 4.87k D4 ES3BB R6 100k D6 ES3BB L1 2.0 µH,75PR8108 C1 220nF R8 1.00k R9 VOUT 1.00k 1 R11 49.9 TP5 TP4 12V/50A TP6 VOUT+ J3 + C4 1500µF + C5 1500µF C9 1µF + C6 1500µF C10 1µF + C7 1500µF C11 1µF TP7 1 GND + C8 1500µF C12 1µF VOUT- J4 4 1 4 1 VBIAS C16 1µF 1 VOUT IOUT VINMON GND VBIAS OUTE OUTF OUTB OUTC OUTA OUTD SYNC CS C14 C15 1uF 1uF R18 R19 3.01 3.01 D14 BAT54 1 U1 UCC27324D OUTA 8 N/C N/C 1 7 OUTA INA 2 R29 10.0k 6 VDD GND 3 5 OUTB INB 4 R28 10.0k 1 D15 BAT54 OUTB L2 26 uH,60PR964 1 8 2 7 3 6 4 5 OUTE R32 10.0k R33 10.0k U2 UCC27324D 1 N/C N/C 8 2 INA OUTA 7 3 GND VDD 6 4 INB OUTB 5 1 OUTC R30 10.0k R31 10.0k 1 OUTD 1 U3 UCC27324D 1 N/C N/C 8 2 INA OUTA 7 3 GND VDD 6 4 INB OUTB 5 J5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pins 1 2 3 4,7 5 11 9 6 8 10 12 14 13 Description VOUT IOUT VINMON GND VDD OUTA OUTB OUTE OUTF OUTC OUTD SYNC CS OUTF VBIAS D16 D17 BAT54 BAT54 C17 1µF D18 BAT54 1 D19 BAT54 VBIAS GND SYNC GND TP2 SYNC TP3 C18 1µF 1 R22 0 External Connections C19 + 22µF TP1 External Bias 1 1 J8 +VINB HEADER100-2 TP10 PWRGND J7 1 +VIN +VSS 7 2 VAUX_PRI 6 3 4 VIN_MON PGND PGND 5 GND GND 1 VBIAS VINMON TP11 R20 3.01 Q5 FDP032N08 R23 10.0k HS3 Q5, Q6 12 R21 1 3.01 Q6 FDP032N08 R24 10.0k R27 .0005 IS- Figure 12. HVPSFB Base Board Schematic Introduction TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 11 Copyright © 2014, Texas Instruments Incorporated Functional Description 2 Functional Description www.ti.com 2.1 Peak Current Mode Control (PCMC) Implementing PCMC for a PSFB system requires complex PWM waveform generation with precise timing control. The Piccolo family of devices from Texas Instruments feature advanced on-chip control peripherals that make this implementation possible without any external support circuitry for this purpose. These peripherals include on-chip analog comparators, digital to analog converters (DAC), advanced PWM resources and unique programmable on-chip slope compensation hardware. Figure 13 provides a block diagram representation of the PCMC implementation. Transformer primary current is compared with the peak current reference calculated by the voltage loop using the on-chip comparator 1. As shown in Figure 14, in every half of the switching cycle when the transformer primary current reaches the commanded peak reference value, one of the PWM waveforms driving the switches (Q2/Q3) is ‘Reset’ immediately ending the power transfer phase. The PWM waveform driving the other switch in the same leg is ‘Set’ after a programmable dead-time (dead-band) window. Appropriate slope compensation is also applied that adds a ramp with a programmable negative slope to the peak reference current signal. The ‘Resetting’ and ‘Setting’ action of the PWMs in one leg results in a phase shift between PWM signals driving the two legs. The amount of this phase shift, and thereby the overlap between diagonal switches, is dependent on the amount of peak reference current. Higher the peak reference current, longer the overlap between diagonal switches, and thereby, more the energy transferred to the secondary. The controller regulates the output by controlling this energy transfer by way of controlling the peak reference current value. Thus this peak reference current is the controlled parameter. An important feature of this implementation is that the same peak reference current command is used for both halves of the switching cycle under all operating conditions. This provides optimal flux balance for the transformer primary reducing any chances of saturation. 100 KHz CNTL 2P2Z DAC Ref Fdbk Out Peak 10-bit + Slope Current Comp Command Voltage Controller A Analog Comp Blanking P W Trip M Zero H W ePWM1A ePWM1B ePWM2A ePWM2B ePWM4A dbAtoP dbPtoA ePWM4B Ipri Vfb_out Vfb_in 100 KHz rslt0 rslt1 ADC NCh DRV rslt2 A IN0 D C IN1 H IN2 W Figure 13. PCMC Block Diagram 12 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Functional Description Figure 14. PCMC PWM Waveforms 2.2 Voltage Mode Control (VMC) In the VMC implementation, switches in each leg are driven with complementary pulse width modulated (PWM) signals of fixed (50%) duty cycle and frequency. As shown in Figure 15, the controller directly drives and controls the phase shift of PWM signals driving switches in one leg of the bridge with respect to the ones driving switches in the other leg. This phase shift dictates the amount of overlap between diagonally opposite switches, which is clear in Figure 16. Longer the overlap between diagonal switches, longer the amount of time the input voltage is imposed across the transformer primary winding, and, thereby, larger the amount of energy transferred to the secondary. The controller regulates the output by controlling this energy transfer by way of directly controlling the phase shift between the PWM signals driving the two legs. Thus this phase shift is the controlled parameter. It should be noted that with VMC implementation there is a need to include a DC blocking capacitor in the transformer primary to avoid possible transformer saturation from flux imbalance over time. Therefore, jumper J6 in Figure 10 should be removed for the VMC implementation. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 13 Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com Figure 15. VMC Block Diagram Figure 16. VMC Waveforms 14 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Functional Description 2.3 Zero Voltage Switching (ZVS) or Low Voltage Switching (LVS) PSFB DC-DC converters make use of parasitic elements in the circuit to ensure zero voltage across the MOSFET switches before turning them ON, providing soft switching. This considerably reduces the amount of switching losses associated with hard switching. For the system discussed here, switching transitions for switches in the Q2- Q3 leg end the power transfer interval. Therefore this leg is called the ‘Active to Passive’ leg. When transitions occur for switches in this leg, current in the primary winding is close to its maximum magnitude for that half PWM switching cycle. The reflected load current aids the circulating energy in the primary circuit during this time, which makes it possible for voltage across switches in this leg to approach zero volts. It is possible to achieve ZVS for switches in this Q2-Q3 leg across the complete load range. It should be noted that as the load decreases the amount of dead-time needs to be increased to achieve/approach ZVS. Switching transitions for switches in the Q1- Q4 leg start the power transfer interval. Therefore this leg is called the ‘Passive to Active’ leg. During these switching transitions, primary current decreases. It crosses zero current value and changes direction. This results in lower available energy for ZVS. In fact for operations under low load conditions, voltage across these switches may not go to zero before turning them on. Switching losses can be kept to a minimum by turning these switches ON at a time when the voltage across them is at a minimum. This is called Low Voltage Switching or low voltage switching (LVS). As the load changes the time at which the switch should be turned on to achieve LVS changes, requiring dead-time adjustment similar to the Q2-Q3 leg switches. 2.4 Synchronous Rectification Synchronous rectifiers can work in one of the following three modes at any given time: 1. Mode 0: This is the classical diode current doubler mode achieved by keeping synchronous rectifiers turned OFF. It is useful for very low load operations where synchronous rectifier switching losses are greater than the power savings obtained by synchronous rectification. 2. Mode 1: In this mode the synchronous rectifier switches behave like ideal diodes. This mode is useful when operating at very low to low loads, typically when burst mode is being used. In this mode, synchronous rectifier MOSFETs are ON only when the corresponding diagonal bridge drive signals overlap. 3. Mode 2: Useful for all other load conditions. In this mode, synchronous rectifier MOSFETs are OFF only when the corresponding opposite diagonal bridge drive signals overlap. Figure 14 and Figure 16 depict waveforms generated for driving the synchronous rectifier switches in these modes. It is important to implement mode transitions seamlessly without any glitches or anomalies on the PWM outputs even during large load transients or sudden phase shift change commands to ensure safe operation of the system. 2.5 Output Voltage Regulation with Changing Load The regulated output voltage is affected by changing load conditions. This problem exists because of ripple on the output voltage that appears at two times the switching frequency. At low loads, peak-to-peak voltage ripple is relatively small, while at higher loads it increases considerably. If the ADC conversions are triggered at a fixed point within a switching cycle, as shown in Figure 17, the sensed ADC voltage result is smaller at high loads (for the same average voltage). This is shown below: Figure 17. Effect of Fixed-Point ADC Conversion Triggering for Output Voltage Sensing TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 15 Copyright © 2014, Texas Instruments Incorporated Functional Description www.ti.com Thus, for same average output voltage, a smaller output voltage is seen by the controller under high-load operation. The controller compensates for this ΔVadc, which results in an increase in the actual output voltage value as the load increases. A few possible solutions to minimize this effect are suggested here. 1. Start of ADC conversion can be triggered at an appropriate time in every half PWM switching cycle so as to directly sense the average output voltage. With PCMC implementation, duty cycle is not predetermined and hence this trigger point is unknown. This method works very well with VMC. 2. Average output voltage can be calculated at a slow rate and an outer slower loop can be used to adjust voltage reference or feedback. However, this may affect the dynamic performance. 3. The average output voltage can be calculated on a cycle-by-cycle basis by over-sampling it over one or two ripple cycles. Since the average output voltage is calculated over a full ripple cycle, any effects from higher/lower peak-to-peak ripple are avoided. Also, since the average is calculated in one or two ripple cycles and used for the next PWM switching cycle, the dynamic behavior and control loop performance do not suffer much. With this method multiple ADC conversions are required within a single PWM half cycle. This is the method recommended here for PCMC implementation. In this implementation the output voltage is oversampled eight times within a PWM switching cycle. 4. Increased filtering at the ADC input can attenuate the ripple and reduce ΔVadc. However, this affects system dynamic performance and achievable loop bandwidth, while the output voltage behavior still remains the same. 16 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com 3 Software Overview - PCMC Software Overview - PCMC 3.1 Software Control Flow The HVPSFB_PCMC project makes use of the “C-background/ASM-ISR” framework. It uses C-code as the main supporting program for the application, and is responsible for all system management tasks, decision making, intelligence, and host interaction. The assembly code is strictly limited to the ISR (Interrupt Service Routine), which runs all the critical control code and typically this includes ADC reading, control calculations, and PWM and DAC updates. Figure 18 depicts the general software flow for this project. Figure 18. PCMC Software Flow The key framework C files used this project are as follows: • HVPSFB-Main.c – This file is used to initialize, run, and manage the application. This is the “brains” behind the application. • HVPSFB-DevInit.c – this file is responsible for a one time initialization and configuration of the micro- controller, and includes functions such as setting up the clocks, PLL, GPIO, etc. The ISR consists of a single file: • HVPSFB-DPL-ISR.asm – this file contains all time critical “control type” code. This file has an initialization section (one time execute) and a run-time section which executes at twice the PWM switching frequency. The Power Library functions (modules) are “called” from this framework. Library modules may have both a C and an assembly component. In this project, following library modules are used. The C and corresponding assembly module names are: TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 17 Copyright © 2014, Texas Instruments Incorporated Software Overview - PCMC C configure Function DAC_Cnf.c ADC_SOC_Cnf.c ADC_SOC_Cnf.c Table 1. Library Modules ASM Initialization Macro DACDRV_RAMP_INIT n ADCDRV_4CD_INIT m, n, p, q ADCDRV_1CH_INIT n CNTL_2P2Z_INIT n www.ti.com ASM Run-Time Macro DACDRV_RAMP n ADCDRV_4CH m, n, p, q ADCDRV_1CH n CNTL_2P2Z n The control blocks can also be represented graphically, as shown in Figure 19. VfbSetSlewed Avg_Vout CNTL_2P2Z:1: Ref Fdbk Coef Out DBUFF CNTL_2P2Z_CoefStruct B0 B1 B2 A1 A2 Dmin Dmax DACDRV_RAMP:1: Iref RAMPMAXREF Iref DACDRV_RAMP_In:n: DACVAL Vout_A Vout_B Vout_C Vout_D ADCDRV_4ch:1,4,6,8: RltPtrA RltPtrB A D RltPtrC C RltPtrD ADC A0 ADC A0 ADC A0 ADC A0 Adc_Ifb Adc_Vfbin Adc_Iout ADCDRV_1ch:2: ADCDRV_1ch_Rlt ADC ADCDRV_1ch:3: ADCDRV_1ch_Rlt ADC ADCDRV_1ch:9: ADCDRV_1ch_Rlt ADC ADC A2 ADC B1 ADC B4 Vout_E Vout_F Vout_G Vout_H ADCDRV_4ch:1,4,6,8: RltPtrA RltPtrB A D RltPtrC C RltPtrD ADC A0 ADC A0 ADC A0 ADC A0 Figure 19. PCMC Software Blocks Notice the color coding for modules in Figure 19. Blocks in ‘dark blue’ represent hardware modules on the C2000 micro-controller. Blocks in ‘blue’ are the software drivers for these modules. Blocks in ‘yellow’ are the controller blocks for the control loop. Although a 2-pole 2-zero controller is used here, the controller could very well be a PI/PID, a 3-pole 3-zero or any other controller that can be suitably implemented for this application. Such a modular library structure makes it convenient to visualize and understand the complete system software flow as shown in Figure 20. It also allows for easy use and additions/deletions of various functionalities. This fact is amply demonstrated in this project by implementing an incremental build approach. This is discussed in more detail in Section 3.2. 18 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Software Overview - PCMC Avg_Vout Figure 20. PCMC Control Flow The system is controlled by two feedback loops; an outer voltage loop, implemented using software control block, and an inner peak current loop, implemented using the on-chip analog comparator, DAC and PWM hardware resources. Figure 20 also gives the rate at which control blocks are executed. For example, the voltage loop controller is executed at a rate of 100 kHz (same as the PWM frequency). Note that the interrupt service routine (ISR) is executed at twice the PWM frequency. Following explains the control implemented above. Output voltage is sampled at four points, equally separated from each other in time, in each half of the PWM switching cycle. The average (Avg_Vout) of these output voltage samples is calculated over one PWM cycle. Avg_Vout is compared with slewed version (VfbSetSlewed) of the voltage reference command (Vref) in the voltage controller. The voltage controller output is then translated to an appropriate DAC command. This is the peak current reference command that eventually dictates the amount of phase overlap between the two legs of the full bridge to regulate the output voltage. ‘Slope’ value for the slope compensation mechanism can be programmed from outside the control flow in slower system level tasks. A default slope of at least 0.04V/us is provided (Please refer to calculations provided in [1], [2] and [4]. The on-chip analog comparator compares the transformer primary current with the slope compensated peak current reference. Comparator output directly drives the PWM hardware on the device. Some time critical configuration code is executed inside the ISR, which is triggered twice in one PWM cycle. The dbAtoP and dbPtoA parameters provide dead band values for the ‘Active to Passive’ and ‘Passive to Active’ legs of the full bridge, respectively. These are used to achieve ZVS/LVS across the load range. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 19 Copyright © 2014, Texas Instruments Incorporated Software Overview - PCMC www.ti.com 3.2 Incremental Builds This project is divided into two incremental builds. This makes it easier to learn and get familiar with the board and the software. This approach is also good for debugging/testing boards. The build options are shown below. To select a particular build option, set the macro INCR_BUILD, found in the HVPSFB-Settings.h file, to the corresponding build selection as shown below. Once the build option is selected, compile the complete project by selecting rebuild-all compiler option. Next chapter provides more details to run each of the build options. Table 2. Incremental Build Options INCR_BUILD = 1 INCR_BUILD = 2 Incremental Build Options Peak current loop check with constant I command and open voltage loop (Check PWM drive circuit and sensing circuit) Closed current and voltage loop (Full PSFB) 20 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for running the incremental builds - PCMC 4 Procedure for running the incremental builds - PCMC The main source files, ISR assembly file and the project file for C framework to bring up the PSFB system are located in the following directory (please use the latest version of the software package. Version 1.1 is the latest software version as of March 2012) ..\controlSUITE\development_kits\HVPSFB_v1.1\HVPSFB_PCMC. The projects included with this software are targeted for CCSv4. Follow the steps below to build and run the example included in the HVPSFB_PCMC software. CAUTION There are high voltages present on the board. It should only be handled by experienced power supply professionals in a lab environment. To safely evaluate this board an appropriate isolated high voltage DC source should be used. Before DC power is applied to the board a voltmeter and an appropriate resistive or electronic load must be attached to the output. The unit should never be handled when the power is applied to it. 4.1 Build 1: Peak Current Loop Check with Open Voltage Loop 4.1.1 Objective The objective of this build is to evaluate the peak current mode operation of the system, verify the DAC and ADC driver modules, verify the MOSFET driver circuit and sensing circuit on the board and become familiar with the operation of Code Composer Studio (CCS). Since this system is running open-loop, the ADC measured values are only used for instrumentation purposes in this build. Steps required to build and run a project will be explored. 4.1.2 Overview The software in Build1 has been configured so that the user can quickly evaluate the DAC driver module by viewing various waveforms on an oscilloscope and observing the effect of change in peak current reference command on the output voltage by interactively adjusting this command from CCS. Additionally, the user can evaluate the ADC driver module by viewing the ADC sampled data in the watch view. The DAC and ADC driver macro instantiations are executed inside the _DPL_ISR as mentioned in the previous chapter. Figure 21 shows the blocks used in this build. The peak current reference command is written to the DACDRV_RAMP module. This module derives an appropriate 16-bit value (RAMPMAXREF)), which is the starting value of the RAMP used for slope compensation. This module also drives an appropriate 10-bit value to the DACVAL register, which can be used if slope compensation is not needed or provided externally. The on-chip analog comparator compares the transformer primary current with the slope compensated peak current reference. Comparator output is connected to the trip zone logic of the PWM modules. ePWM1 module acts as the master time-base for the system. It operates in up-down count mode, while other PWM modules operate in up-count mode. ePWM1A and ePWM1B drive Q1 and Q4 full-bridge switches, while ePWM2A and ePWM2B drive Q2 and Q3 full-bridge switches. ePWM4A and ePWM4B drive Q5 and Q6 synchronous rectifier switches. Whenever the comparator output goes high in a PWM half cycle, the ePWM2 module output (ePWM2A or ePWM2B) which was high at that instant is immediately pulled low while the other PWM2 module output is pulled high after an appropriate dead-band window (dbAtoP). ePWM4A and ePWM4B outputs are driven in a similar way. These waveforms are shown in Figure 14. It should be noted that this slope compensation ramp generation, comparator action and PWM waveform generation are all hardware generated without any software involvement as denoted by the dark blue blocks in Figure 21. Some register reconfigurations are done inside the ISR in preparation for the next half of the PWM cycle. This time critical code executes at the start of the ISR and should not be re-ordered or changed. The assembly ISR _DPL_ISR routine is triggered by ePWM1. Note that the ISR trigger frequency is twice that of the PWM switching frequency. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 21 Copyright © 2014, Texas Instruments Incorporated Procedure for running the incremental builds - PCMC www.ti.com Avg_Vout Figure 21. Build 1 Software Blocks The RAMPMAXREF and DACVAL values are derived from the input “Iref” (Q24 variable) command. Table 3 gives example RAMPMAXREF and DACVAL values calculated from ‘Iref’. Iref (Q24) 2097152d 8388608d 16776704d Table 3. Example RAMPMAXREF and DACVAL Values RAMPMAXREF = (Iref/2^8) 8192 32768 65534 DACVAL = (Iref/2^14) 128 512 1023 Peak Current Reference (Max = 6.776A) 0.845A 3.39A 6.77A The ADC driver modules are used to read 12-bit ADC results and convert them to Q24 values. In every half PWM cycle PWM1 SOCA (start of conversion A), PWM3 SOCA (start of conversion A) and PWM3 SOCB (start of conversion B) are used to trigger four ADC conversions for the output voltage. These conversion trigger points are equally separated from each other in time. These four results are read in every ISR thus providing a total of eight ADC conversion results of the output voltage within every PWM cycle. A few lines of code in the ISR are used to calculate the average output voltage over one PWM cycle based on these eight results. The output voltage sensing circuit is made up of simple voltage dividers. A current transformer, with a turns-ratio of 1:100, and a sense resistor (48.7 ohm) are used to sense the full-bridge transformer primary current. The input voltage sensing is provided by auxiliary power module (J7). Please refer to HVPSFBCalculations.xls file for details on these calculations. 22 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for running the incremental builds - PCMC 4.1.3 Protection At this stage, it is appropriate to introduce the shutdown mechanism used on this board. Here overcurrent protection is implemented for the transformer primary current using on-chip analog comparator 2. The reference trip level is set using the internal 10-bit DAC and fed to the inverting terminal of this comparator. The comparator outputs are configured to generate a one-shot trip action on ePWM1 whenever the sensed current is greater than the set limit. The flexibility of the trip mechanism on C2000 devices provides the possibilities for taking different actions on different trip events. In this project ePWM1A and ePWM1B outputs are driven low immediately to protect the power stage. ePWM2A, ePWM2B, ePWM4A and ePWm4B outputs are then forced low from software. All outputs are held in this state until a device reset is executed. Please refer to HVPSFB-Calculations.xls file for details on these calculations. An output under voltage shut down mechanism is also implemented from the software when operating under constant current or constant power modes. Input under voltage and over voltage lockout is also implemented in the software. 4.1.4 Resource Mapping The key signal connections between the C2000 MCU and the HVPSFB stage are summarized in Table 4. Note that PWM mapping is different between VMC and PCMC projects. Jumper (J2, J3 – PCMC and VMC PWM drive jumper enables) on the controller card need to be correctly configured for VMC mode (Default jumper positions are set for PCMC operation). Here are the jumper configurations for the two modes: PCMC: J2(1) -> J3(1), J2(2) -> J3(2), J2(3) -> J3(3), J2(4) -> J3(4), J2(7) -> J3(7), J2(8) -> J3(8), VMC: J2(1) -> J3(3), J2(2) -> J3(4), J2(3) -> J3(1), J2(4) -> J3(2), J2(7) -> J3(8), J2(8) -> J3(7) Table 4. HVPSFB Signal Interface Reference -PCM Signal Name Description Connection to C2000 Controller ePWM-1A PWM Drive for full-bridge switch Q1 GPIO-00 ePWM-1B PWM Drive for full-bridge switch Q4 GPIO-01 ePWM-2A PWM Drive for full-bridge switch Q2 GPIO-02 ePWM-2B PWM Drive for full-bridge switch Q3 GPIO-03 ePWM-4A PWM drive for synchronous rectifier switch Q5 GPIO-06 ePWM-4B PWM drive for synchronous rectifier switch Q6 GPIO-07 Vout PSFB output voltage ADC-A0 Ifb Transformer primary current ADC-A2/COMP1A Ifb Transformer primary current ADC-A4/COMP2A (1) Vfbin PSFB input voltage ADC-B1 Iout1 PSFB output current ADC-B3 Iout2 PSFB output current (heavily filtered) ADC-B4 (1) Default jumper J4 configuration on controller card. Input is configurable by jumper J4 selection. NOTE: The HVPSFB_PCMC and HVPSFB_VMC projects use DSP2802x_Comp.h and DSP2802x_EPWM.h header files that are located in their own project directories instead of the ones located in the device_support directory. The two files in device_support directory will be updated at a later update of ControlSuite, at which time these updated files may be used with the two projects. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 23 Copyright © 2014, Texas Instruments Incorporated Procedure for running the incremental builds - PCMC 4.1.5 Procedure www.ti.com 4.1.5.1 Start CCS and Open a Project To quickly execute this build, follow the following steps: 1. Ensure that jumpers J8 and J6 on the base board are populated. 2. By default, resistor R6 on Piccolo Macro of the controller card and jumper J1 are removed to enable – boot from FLASH. Re-populate these two to run and program RAM or program FLASH. Connect USB connector to the Piccolo controller card for emulation. Use of an appropriate isolated DC power supply set to output around 400V DC is recommended. DC power supply should remain off when it is connected to J1 and J2 on the main board. Use a 20AWG 600V wire to connect the Power Source to J1 and J2. Make sure that polarity of this connection is correct. Apply an appropriate resistive/DC electronic load to the phase shifted full bridge system at the DC output at J3 and J4. Do not turn on 400V DC power at this time. Power up the bias supply between TP1 and TP2 with around 11V DC (this voltage must be less than 12V). 3. Double click on the Code Composer Studio icon on the desktop. Maximize Code Composer Studio to fill your screen. Close the Welcome screen if it opens up. 4. A project contains all the files and build options needed to develop an executable output file (.out) which can be run on the MCU hardware. On the menu bar click: Project -> Import Existing CCS/CCE Eclipse Project and under Select root directory navigate to and select ..\controlSUITE\development_kits\HVPSFB_v1.1\HVPSFB_PCMC directory. Make sure that under the Projects tab HVPSFB_PCMC is checked. Click Finish. This project will invoke all the necessary tools (compiler, assembler, linker) to build the project. 5. In the project window on the left, click the plus sign (+) to the left of Project. Your project window will look like the following: 24 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com 4.1.5.2 Device Initialization, Main, and ISR Files Procedure for running the incremental builds - PCMC NOTE: Do not make any changes to the source files – Only Inspect 1. Open and inspect HVPSFB-DevInit_F2802x.c by double clicking on the filename in the project window. Notice that system clock, peripheral clock prescale, and peripheral clock enables have been setup. Next, notice that the shared GPIO pins have been configured. 2. Open and inspect HVPSFB-Main.c. Notice the call made to DeviceInit() function and other variable initialization. Also notice code for different incremental build options (specifically the build you are going to compile now), the ISR intialization and the background for(;;) loop. 3. Locate and inspect the following code in the main file under initialization code specific for build 1. This is where the DACDRV_RAMP block is connected and initialized in the control flow. 4. Locate and inspect the following code in the main file under initialization code specific for build 1. This is where the ADCDRV_4CH and multiple instantiations of ADCDRV_1CH blocks are configured, initialized and connected in the control flow. 5. Open and inspect HVPSFB-DPL-ISR.asm. Notice the _DPL_Init and _DPL_ISR sections. This is where the DAC and ADC driver macro instantiation is done for initialization and runtime, respectively. Optionally, you can close the inspected files. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 25 Copyright © 2014, Texas Instruments Incorporated Procedure for running the incremental builds - PCMC 4.1.5.3 Build and Load the Project 1. Select the Incremental build option as 1 in the HVPSFB-Settings.h file. www.ti.com NOTE: Whenever you change the incremental build option in HVPSFB-Settings.h always do a “Rebuild All”. 2. Click Project -> “Rebuild All” button and watch the tools run in the build window. 3. Click Target -> ”Debug Active Project”. CCS will ask you to open a new Target configuration file if one hasn’t already been selected. If a valid target configuration file has been created for this connection you may go to Step 5. In the New target Configuration Window type in the name of the .ccxml file for the target you will be working with (Example: xds100-F28027.ccxml). Check “Use shared location” and click Finish. 4. In the .ccxml file that opens up select Connection as “Texas Instruments XDS100v2 USB Emulator” and under the device, scroll down and select “TMS320F28027”. Click Save. 5. Click Target -> ”Debug Active Project”. The program will be loaded into the FLASH or RAM memory depending on the project configuration selected. This project comes in only F2802x_FLASH configuration. You should now be at the start of Main(). 4.1.5.4 Debug Environment Windows It is standard debug practice to watch local and global variables while debugging code. There are various methods for doing this in Code Composer Studio, such as memory views and watch views. Additionally, Code Composer Studio has the ability to make time (and frequency) domain plots. This allows the user to view waveforms using graph windows. 1. If a watch view did not open when the debug environment was launched, open a new watch view and add various parameters to it by following the procedure given below. 2. Click: View -> Watch on the menu bar. 3. Click the “Watch (1)" tab. You may add any variables to the watch view. 4. In the empty box in the "Name" column, type the symbol name of the variable you want to watch and press enter on keyboard. Be sure to modify the “Format” as needed. The watch view should look something like Figure 22. Please note that some of the variables have not been initialized at this point in the main code and may contain some garbage values. FaultFlg, if set, indicates an over current condition (discussed above), which shuts down the PWM outputs. PWM outputs are held in this state until a device reset (follow the proper procedure in Step 11 of Section 4.1.5.6). The Ipri_trip variable sets the internal 10-bit DAC reference level for the on-chip comparator 2. Please note that this is a Q15 number. Figure 22. 26 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for running the incremental builds - PCMC 4.1.5.5 Using Real-Time Emulation Real-time emulation is a special emulation feature that allows the windows within Code Composer Studio to be updated at up to a 10 Hz rate while the MCU is running. This not only allows graphs and watch views to update, but also allows the user to change values in watch or memory windows, and have those changes affect the MCU behavior. This is very useful when tuning control law parameters on-the-fly, for example. 1. Enable real-time mode by hovering your mouse on the buttons on the horizontal toolbar and clicking button 2. A message box may appear. If so, select YES to enable debug events. This will set bit 1 (DGBM bit) of status register 1 (ST1) to a “0”. The DGBM is the debug enable mask bit. When the DGBM bit is set to “0”, memory and register values can be passed to the host processor for updating the debugger windows. 3. Now click button on the same horizontal toolbar. 4. When a large number of windows are open, as bandwidth over the emulation link is limited, updating too many windows and variables in continuous refresh can cause the refresh frequency to bog down. Right click on the button in the watch view and select “Customize Continuous Refresh Interval..”. You can slow down the refresh rate for the watch view variables by changing the Continuous refresh interval (milliseconds) value. A rate of 4000 ms is usually enough for these exercises. 5. Click on Continuous Refresh buttons for the watch view. 4.1.5.6 Run the Code 1. Run the code by using the key, or using the Run button on the toolbar, or using Target -> Run on the menu bar. 2. In the watch view, the variable Gui_IfbSet should be set to 0.15 (Q12). This variable denotes the peak current reference command in Amperes and drives Iref to the DACDRV_RAMP module. Do not use a value of less than 0.15 for Gui_IfbSet. 3. Apply an appropriate resistive load to the PSFB system at the DC output. A load that draws around 3A – 6A current at 12V output is a good starting point. NOTE: For safety reasons it is recommended to use an isolated DC source to supply 400V DC input to the board. 4. Power the input at J1, J2 with 400V DC. 5. Increase the peak current reference command by setting Gui_IfbSet to a higher value 0.25(say) in the watch view. The output voltage should increase. Observe the output voltage carefully, this should not be allowed to exceed the capabilities of the board. Keep in mind that when operating with a certain Gui_IfbSet value if the load is suddenly reduced, the output voltage will go up. Therefore do not make any sudden changes of load or big increases in Gui_IfbSet command when operating in build 1. 6. Observe the different ADC results in the watch view for different Gui_IfbSet values. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 27 Copyright © 2014, Texas Instruments Incorporated Procedure for running the incremental builds - PCMC www.ti.com 7. Here is the watch view that corresponds to the operation of the system with a Gui_IfbSet command of 1.17A with an input voltage of around 400V and a load of around 6A at 12V output. Figure 23. 8. The following oscilloscope capture shows transformer primary voltage, primary sensed current and PWM waveforms driving two diagonally opposite switches (Q1 and Q3) seen under conditions described above. Figure 24. 28 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for running the incremental builds - PCMC 9. By default the synchronous rectifiers are operated in mode 2. You may change their mode of operation by changing SR_mode variable to 0, 1 or 2 from the watch view. Observe the change in amount of input current being drawn and change in output voltage with different SR modes. You may also probe the PWM waveforms driving the synchronous rectifier switches. Do not change between different SR modes when operating at very low loads or when the output voltage is very low (less than 6V). In these cases use the default SR mode 2. 10. Try different Gui_IfbSet values and observe the corresponding ADC results. Increase Gui_IfbSet in small steps. Always observe the output voltage carefully, this should not be allowed to exceed the capabilities of the board. Different waveforms, like the PWM gate drive signals, input voltage and current and output voltage may also be probed using an oscilloscope. Appropriate safety precautions should be taken and appropriate grounding requirements should be considered while probing these high voltages and high currents for this isolated DC-DC converter. 11. Fully halting the MCU when in real-time mode is a two-step process. With the 400V DC input turned off wait a few seconds. First, halt the processor by using the Halt button on the toolbar, or by using Target -> Halt. Then click MCU. button again to take the MCU out of real-time mode and then reset the 12. You may choose to leave Code Composer Studio running for the next exercise or optionally close CCS. 13. End of Exercise TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 29 Copyright © 2014, Texas Instruments Incorporated Procedure for running the incremental builds - PCMC 4.2 Build 2: Full HVPSFB www.ti.com 4.2.1 Objective The objective of this build is to verify the operation of the complete PCMC based HVPSFB project from the CCS environment. 4.2.2 Overview Figure 25 shows the software blocks used in this build. A two pole two zero controller is used for the voltage loop. Depending on the application’s control loop requirements some other controller block like a PI, a 3-pole 3-zero, etc may also be used. As seen in Figure 25, the voltage loop block is executed at 100 KHz. CNTL2P2Z is a 2nd order compensator realized from an IIR filter structure. This function is independent of any peripherals and therefore does not require a CNF function call. Avg_Vout Figure 25. Build 2 Software Block The five coefficients to be modified are stored as elements of the structure CNTL_2P2Z_CoefStruct1 whose other elements are used for clamping the controller output. The CNTL_2P2Z block can be instantiated multiple times if the system needs multiple loops. Each instance can have separate set of coefficients. Directly manipulating the five coefficients independently by trial and error is almost impossible, and requires mathematical analysis and/or assistance from tools such as matlab, mathcad, etc. These tools offer bode plot, root-locus and other features for determining phase margin, gain margin, etc. To keep loop tuning simple and without the need for complex mathematics or analysis tools, the coefficient selection problem has been reduced from five degrees of freedom to three, by conveniently mapping the more intuitive coefficient gains of P, I and D to B0, B1, B2, A1, and A2. This allows P, I and D to be adjusted independently and gradually. These mapping equations are given below. 30 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for running the incremental builds - PCMC The compensator block (CNTL_2P2Z) has 2 poles and 2 zeros and is based on the general IIR filter structure. It has a reference input and a feedback input. For the voltage loop the feedback is the average output voltage calculated over one PWM cycle (Avg_Vout), while the reference input to the controller is a slewed version (VfbSetSlewed) of the output voltage reference command (Vref). The transfer function is given by: ( ) U z b0 + b1z−1 + b2z−2 E(z) = 1 + a1z −1 + a2z−2 (1) The recursive form of the PID controller is given by the difference equation: u(k ) =u(k −1) + b0e(k ) + b1e(k −1) + b2e(k − 2) where b0 = Kp + Ki + Kd b1 = −Kp + Ki − 2Kd b2 = Kd And the z-domain transfer function form of this is: U z b0 b1z 1 b2 z 2 b0 z2 b1z b2 = = Ez 1 z1 z2 z (3) Comparing this with the general form, we can see that PID is nothing but a special case of CNTL_2P2Z control where: a1 = −1 and a2 = 0 (4) For the voltage loop these P, I and D coefficients are: Pgain, Igain and Dgain. These P, I and D coefficients are used in Q26 format. To simplify tuning from the GUI environment (or from CCS watch views) these three coefficients are further scaled to values from 0 to 999 (Pgain_Gui, Igain_Gui and Dgain_Gui). From the GUI environment the voltage loop can also be tuned using two poles (fp1, fp2), two zeroes (fz1, fz2) and gain (Kdc). These parameters provide b2_Gui, b1_Gui, b0_Gui, a2_Gui and a1_Gui coefficients in I5Q10 form which are then converted to the five Q26 coefficients for the 2P2Z controller. Although not recommended, b2_Gui, b1_Gui, b0_Gui, a2_Gui and a1_Gui values may also be directly changed from the CCS environment using watch views. Please refer to HVPSFB-Calculations.xls file for details on these calculations. The equations for deriving coefficient values based on poles, zeroes, gain and switching frequency are also clear from the GUI source file. This project allows easy evaluation of both methods of loop tuning by providing the ability to easily switch between coefficients during execution. This can be done by simply clicking on the 2P2Z(On)/PID(Off) button on the GUI or changing the pid2p2z_GUI variable to 0 or 1 on the watch view from CCS. PID based loop tuning (pid2p2z_GUI = 0) from the GUI environment was used as a starting point. Poles, zeroes and gain corresponding to these PID tuned coefficients were then used as a starting point for further loop tuning based on the second method (pid2p2z_GUI = 1). Much better results were then achieved by changing poles, zeroes and gain from the GUI environment to tune for optimum dynamic performance. By default coefficients based on these tuned poles, zeroes and gain values (pid2p2z_GUI = 1 – default) are used. NOTE: When tuning the system using the 2-pole 2-zero controller coefficient adjustments, if a choice of poles, zeroes and Kdc values is made in the GUI such that it result in the magnitude of any of the coefficients (b2, b1, b0, a2, a1) to be greater than or equal to 32, then these coefficient values are not sent to the controller by the GUI. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 31 Copyright © 2014, Texas Instruments Incorporated Procedure for running the incremental builds - PCMC www.ti.com 4.2.3 Constant Current (CC) and Constant Power (CP) Simple implementation for experimenting with constant current and constant power functionality has been included in this project. By default this functionality is disabled. Constant current function is implemented by changing the clamping value of the voltage loop controller. Constant power function is implemented by adjusting the voltage loop reference command based on load to maintain constant power at the output. Following provides the complete software flowchart for these functions. Figure 26. Constant Current and Constant Power Software Flowchart 32 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com 4.2.4 Procedure Procedure for running the incremental builds - PCMC 4.2.4.1 Build and Load Project To quickly execute this build using the pre-configured work environment, follow the following steps: 1. Follow Steps 1 to 2 exactly as in build 1. If you were working on build 1 the last time CCS was used, the same workspace should open up with the project. If this is not the case, you can open the workspace used for build1 by clicking File -> Switch Workspace and then navigating to the correct workspace. If a workspace was not saved or got deleted, please follow steps 3 and 4 exactly as in build1. 2. Locate and inspect the initialization code specific to build 2 in the main file. This is where all the control blocks are configured, initialized and connected in the control flow. 3. Select the Incremental build option as 2 in the HVPSFB-Settings.h. NOTE: Whenever you change the incremental build option in HVPSFB-Settings.h always do a “Rebuild All”. 4. Click Project -> “Rebuild All” button and watch the tools run in the build window. 5. Click Target -> ”Debug Active Project”. The program will be loaded into the FLASH or RAM memory depending on the project configuration. This project comes in only F2802x_FLASH configuration. You should now be at the start of Main(). 4.2.4.2 Debug Environment Windows It is standard debug practice to watch local and global variables while debugging code. There are various methods for doing this in Code Composer Studio, such as memory views and watch views. Additionally, Code Composer Studio has the ability to make time (and frequency) domain plots. This allows us to view waveforms using graph windows. 1. If a watch view did not open when the debug environment was launched, open a new watch view and add various parameters to it by following the procedure given below. 2. Click: View -> Watch on the menu bar. 3. Click the “Watch (1)" tab. 4. If a watch view is already open from the debug environment saved for build 1, click on button in the watch view. A “Watch (2)” tab will open and you may then drag it to be viewed in a window of your choice. You may add any variables to this watch view tab. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 33 Copyright © 2014, Texas Instruments Incorporated Procedure for running the incremental builds - PCMC www.ti.com 5. In the empty box in the "Name" column, type the symbol name of the variable you want to watch and press enter on keyboard. Be sure to modify the “Format” as needed. The watch view should look something like Figure 27. Please note that some of the variables have not been initialized at this point in the main code and may contain some garbage values. Figure 27. Notice the additional variables in the watch window. 6. Gui_VfbSet is used to set the output voltage command. 4.2.4.3 Run the Code 1. Follow steps 1 to 4 of the build 1 procedure to enable real-time mode and continuous refresh for the watch views and also for changing the continuous refresh interval for the watch view if needed. 2. Run the code by using the key,or using the Run button on the toolbar, or using Target -> Run on the menu bar. 3. Apply an appropriate resistive load to the PSFB system at the DC output. A load that draws around 3A – 6A current at 12V output is a good starting point. NOTE: For user safety, it is recommended to use an isolated DC source to supply 400V DC input to the board. 4. Power the input at J1, J2 with 400V DC. 5. By default Auto_Run is set to 1. If it is not make it 1 from the watch view. The output voltage should now start ramping up to 12V. This output voltage ramp up rate can be changed by changing the variable VfbSlewRate. 6. Here is the watch view that corresponds to the operation of the system with 12.2V at the output with an input voltage of around 400V and a load of around 6A output. 34 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for running the incremental builds - PCMC Figure 28. 7. The following oscilloscope capture shows the transformer primary voltage, the primary sensed current and PWM waveforms driving two diagonally opposite switches (Q1 and Q3) seen under conditions described above. ZVS switching of switch Q3 and LVS switching of switch Q4 are also shown under these conditions. Figure 29. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 35 Copyright © 2014, Texas Instruments Incorporated Procedure for running the incremental builds - PCMC www.ti.com Figure 30. Figure 31. 8. By default the synchronous rectifiers are operated in mode 2. You may change their mode of operation by changing SR_mode variable to 0, 1 or 2 from the watch view. Observe the change in amount of input current being drawn and change in output voltage with different SR modes. You may also probe the PWM waveforms driving the synchronous rectifier switches. Do not change between different SR modes when operating at very low loads (below 3A). In these cases use the default SR mode 2. 9. Observe the effect of varying the load* on the output voltage and input current. There should be virtually no effect on the output voltage. Similarly observe the effect of varying the input voltage*. Again there should be virtually no effect on the output voltage. NOTE: Ensure these changes are made within the abilities of the board, as listed in Section 1.3 of this document. 10. Different waveforms, like the PWM gate drive signals, input voltage and current and output voltage may also be probed using an oscilloscope. Appropriate safety precautions should be taken and appropriate grounding requirements should be considered while probing these high voltages and high currents for this isolated DC-DC converter. 11. Simple ‘Constant Current (CC)’ and ‘Constant Power (CP)’ functions are also implemented in this project and can be experimented with by enabling/disabling their corresponding flags (CC_Enable and CP_Enable). 12. Fully halting the MCU when in real-time mode is a two-step process. With the 400V DC input turned off wait a few seconds. First, halt the processor by using the Halt button on the toolbar, or by using Target -> Halt. Then click button again to take the MCU out of real-time mode and then reset the MCU. 13. Close CCS. 14. End of Exercise 36 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com 5 Software Overview – VMC Software Overview – VMC 5.1 Software Control Flow The HVPSFB_VMC project makes use of the “C-background/ASM-ISR” framework. It uses C-code as the main supporting program for the application, and is responsible for all system management tasks, decision making, intelligence, and host interaction. The assembly code is strictly limited to the ISR (Interrupt Service Routine), which runs all the critical control code and typically this includes ADC reading, control calculations, and PWM and DAC updates. Figure 32 depicts the general software flow for this project. Figure 32. VMC Software Flow The key framework C files used in this project are: HVPSFB-Main.c – This file is used to initialize, run, and manage the application. This is the “brains” behind the application. HVPSFB-DevInit.c – This file is responsible for a one time initialization and configuration of the F280x device, and includes functions such as setting up the clocks, PLL, GPIO, etc. The ISR consists of a single file: HVPSFB-DPL-ISR.asm – This file contains all time critical “control type” code. This file has an initialization section (one time execute) and a run-time section which executes (typically) at the same rate as the PWM timebase used to trigger it. The Power Library functions (modules) are “called” from this framework. Library modules may have both a C and an assembly component. In this project, following library modules are used. The C and corresponding assembly module names are: TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 37 Copyright © 2014, Texas Instruments Incorporated Software Overview – VMC C Configure Function PWMDRV_PSFB_VMC_S R_CNF ADC_SOC_Cnf.c Table 5. Library Modules ASM Initialization Macro PWMDRV_PSFB_VMC_SR_INIT n,m,p ADCDRV_4CH_INIT m,n,p,q CNTL_2P2Z_INIT n www.ti.com ASM Run-Time Macro PWMDRV_PSFB_VMC_SR n,m,p ADCDRV_4CH m,n,p,q CNTL_2P2Z n The control blocks can also be represented graphically as shown in Figure 33 Figure 33. VMC Software Blocks Notice the color coding for modules in Figure 33. Blocks in ‘dark blue’ represent hardware modules on the C2000 micro-controller. Blocks in ‘blue’ are the software drivers for these modules. Blocks in ‘orange’ are the controller blocks for the control loop. Although a 2-pole 2-zero controller is used here, the controller could very well be a PI/PID, a 3-pole 3-zero or any other controller that can be suitably implemented for this application. Such a modular library structure makes it convenient to visualize and understand the complete system software flow as shown in Figure 34. It also allows for easy use and additions/deletions of various functionalities. This fact is amply demonstrated in this project by implementing an incremental build approach. This is discussed in more detail in Section 5.2. 38 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Software Overview – VMC Figure 34. VMC Control Flow The system is controlled by one voltage feedback loop. Figure 34 also gives the rate at which control blocks are executed. For example, the voltage controller is executed at a rate of 100 kHz (same as the PWM switching frequency). Following explains the control implemented above. The sensed output voltage (Adc_Vfbout) is compared with slewed version (VfbSetSlewed) of the voltage reference command (Vref) in the voltage controller. The voltage controller output directly controls phase shift between PWM signals driving the two legs of the full bridge. This dictates the amount of phase overlap between the two legs of the full bridge to regulate the output voltage. The dbAtoP_leg and dbPtoA_leg values provide dead band values for the ‘Active to Passive’ and ‘Passive to Active’ legs of the full bridge, respectively. These are used to achieve ZVS/LVS across the load range. 5.2 Incremental Builds This project is divided into two incremental builds. This makes it easier to learn and get familiar with the board and the software. This approach is also good for debugging/testing boards. The build options are shown below. To select a particular build option, set the macro INCR_BUILD, found in the HVPSFBSettings.h file, to the corresponding build selection as shown below. Once the build option is selected, compile the complete project by selecting rebuild-all compiler option. Next chapter provides more details to run each of the build options. Table 6. Incremental Build Options for VMC INCR_BUILD = 1 INCR_BUILD = 2 Open loop PSFB drive with ADC feedback (Check PWM drive circuit and sensing circuit) Closed voltage loop (Full PSFB in VMC mode) TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 39 Copyright © 2014, Texas Instruments Incorporated Procedure for Running Incremental Builds www.ti.com 6 Procedure for Running Incremental Builds The main source files, ISR assembly file and the project file for C framework to bring up the PSFB system are located in the following directory (please use the latest version of the software package. Version 1.1 is the latest software version as of March 2012) ..\controlSUITE\development_kits\HVPSFB_v1.1\HVPSFB_VMC. The projects included with this software are targeted for CCSv4. Follow the steps below to build and run the example included in the HVPSFB_VMC software. 6.1 Build 1: Open-Loop Check with ADC Feedback 6.1.1 Objective The objective of this build is to evaluate the open loop operation of the system, verify the PWM and ADC driver modules, verify the MOSFET driver circuit and sensing circuit on the board and become familiar with the operation of Code Composer Studio (CCS). Since this system is running open-loop, the ADC measured values are only used for instrumentation purposes in this build. Steps required to build and run a project will be explored. 6.1.2 Overview The software in Build1 has been configured so that the user can quickly evaluate the phase shifted full bridge PWM driver module by viewing the output waveforms on an oscilloscope and observing the effect of change in phase on the output voltage by interactively adjusting the phase on CCS. Additionally, the user can evaluate the ADC driver module by viewing the ADC sampled data in the watch view. The PWM and ADC driver macro instantiations are executed inside the _DPL_ISR as mentioned in the previous chapter. Figure 35 shows the blocks used in this build. ePWM1A and ePWM1B drive Q2 and Q3 full-bridge switches, while ePWM2A and ePWM2B drive Q1 and Q4 full-bridge switches. ePWM4A and ePWM4B drive Q6 and Q5 synchronous rectifier switches. Figure 35. Build 1 Software Blocks 40 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for Running Incremental Builds These PWM signals need to be generated at a frequency of 100 kHz i.e. a period of 10 us. With the MCU operating at 60 MHz, one count of the time base counter of ePWM1, ePWM2 or ePWM4 corresponds to 16.667ns. This implies that a PWM period of 10 us will be equivalent to 600 counts of the time base counter (TBCNT1, TBCNT2 and TBCNT4). The ePWM1 and ePWM2 modules are configured to operate in up-count mode, while ePWM4 operates in up-down count mode. ePWM1A and ePWM1B outputs operate at 50% duty cycle and are complementary to each other. Similarly ePWM2A and ePWM2B operate at 50% duty cycles and are complementary to each other. Phase for ePWM2 time base may be changed dynamically with respect to ePWM1 phase. These PWM waveforms are shown in Figure 16. The phase input to the PWM driver module decides the amount of phase shift between PWM1 and PWM2 time bases. This phase value controls the amount of overlap between PWM signals driving diagonally opposite switch pairs of the full bridge. As phase increases, amount of overlap increases, which increases the amount of energy transferred to the secondary. The TBPHS2 value is derived from the input “phase” command. Table 7 gives example TBPHS2 values derived for a TBPRD value of 599. Phase (Q24) 2097152d 8388608d 16776704d Table 7. Phase Values for Reference TBPHS2 = (phase*TBPRD/2^25) 37 149 299 Phase Shift in Degrees 22.5 90 180 Note that each pair of diagonal switches of the full bridge overlaps once in one PWM period. This means the most overlap will occur when the phase shift is close to 180 degrees. The assembly ISR is triggered on a ZRO (TBCNT1 = 0) event of ePWM1. This is where the control driver macros are executed and the TBPHS2 and TBPHS4 registers updated. There is an important consideration regarding where the ADC input is sampled. The integrity of the ADC input signals is of high importance since this is where signals from the analog and digital domains interface. Turning a switch ON/OFF in the power stage may result in some noise or disturbance on the signals that are to be sensed around this point in time. Even with all the filtering provided on these signals to avoid this noise from showing up at the ADC inputs, it is prudent to sample the ADC inputs at a time such that this disturbance is avoided. Moreover, as discussed in Section 2.5, sensed output voltage should preferably be sampled at an appropriate point in the switching cycle where the output voltage value is close to its average value. To achieve this, the ADC input signals are sampled at a time so as to get as noise free a sample as possible and to also sample the average output voltage. For the full bridge this is achieved by sampling at the midpoint of the overlap between two diagonal switches (here overlap refers to the period when both switches are ON at the same time) i.e. as far away from the MOSFET switching as possible. This avoids any switching noise to be reflected on the ADC result. The flexibility of ADC and PWM modules on C2000 devices allow such precise and flexible triggering of ADC conversions. The ADC driver modules are used to read 12-bit ADC results and convert them to Q24 values. In every PWM cycle PWM2 SOCA (start of conversion A) is used to trigger five ADC conversions. 6.1.3 Protection At this stage, it is appropriate to introduce the shutdown mechanism used with this project. Here overcurrent protection is implemented for the transformer primary current using on-chip analog comparator 1. The reference trip level is set using the internal 10-bit DAC and fed to the inverting terminal of this comparator. The comparator outputs are configured to generate a one-shot trip action on ePWM1 and ePWM2 whenever the sensed current is greater than the set limit. The flexibility of the trip mechanism on C2000 devices provides the possibilities for taking different actions on different trip events. In this project ePWM1A, ePWM1B, ePWM2A, and ePWM2B outputs are driven low immediately to protect the power stage. These outputs are held in this state until a device reset is executed. Please refer to HVPSFBCalculations.xls file for details on these calculations. Input under voltage and over voltage lockout is also implemented in the software. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 41 Copyright © 2014, Texas Instruments Incorporated Procedure for Running Incremental Builds www.ti.com 6.1.4 Resource Mapping The key signal connections between the C2000 micro-controller and the HVPSFB stage are summarized in Table 8. Note that PWM mapping is different between VMC and PCMC projects. Jumper (J2, J3 – PCMC and VMC PWM drive jumper enables) on the controller card need to be correctly configured for VMC mode (Default jumper positions are set for PCMC operation). Here are the jumper configurations for the two modes: PCMC: J2(1) -> J3(1), J2(2) -> J3(2), J2(3) -> J3(3), J2(4) -> J3(4), J2(7) -> J3(7), J2(8) -> J3(8), VMC: J2(1) -> J3(3), J2(2) -> J3(4), J2(3) -> J3(1), J2(4) -> J3(2), J2(7) -> J3(8), J2(8) -> J3(7) Table 8. HVPSFB Signal Interface Reference –VMC Signal Name Description ePWM-1A PWM driver for full-bridge switch Q2 ePWM-1B PWM drive for full-bridge switch Q3 ePWM-2A PWM drive for full-bridge switch Q1 ePWM-2B PWM drive for full-bridge switch Q4 ePWM-4A PWM drive for synchronous rectifier switch Q6 ePWM-4B PWM drive for synchronous rectifier switch Q5 Vout PSFB output voltage Ifb Transformer primary current Ifb Transformer primary current Vfbin PSFB input voltage Iout1 PSFB output current Iout2 PSFB output current (heavily filtered) (1) Default jumper J4 configuration on controller card. Input is configurable by jumper J4 selection. Connection to C2000 Controller GPIO-00 GPIO-01 GPIO-02 GPIO-03 GPIO-06 GPIO-07 ADC-A0 ADC-A2/COMP1A ADC-A4/COMP2A (1) ADC-B1 ADC-B3 ADC-B4 NOTE: The HVPSFB_PCMC and HVPSFB_VMC projects use DSP2802x_Comp.h and DSP2802x_EPWM.h header files that are located in their own project directories instead of the ones located in the device_support directory. The two files in device_support directory will be updated at a later update of ControlSuite, at which time these updated files may be used with the two projects. 42 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com 6.1.4.1 Procedure Procedure for Running Incremental Builds 6.1.4.1.1 Start CCS and Open a Project To quickly execute this build, follow the following steps: 1. Make sure that jumper J6 on the base board is not populated, while jumper J8 is populated. 2. By default, resistor R6 on Piccolo Macro of the controller card and jumper J1 are removed to enable – boot from FLASH. Re-populate these two to run and program RAM or program FLASH. Connect USB connector to the Piccolo controller card for emulation. Use of an appropriate isolated DC power supply set to output around 400V DC is recommended. DC power supply needs to remain off before it is connected to J1 and J2 on the main board. Use a 20AWG 600V wire to connect the Power Source to J1 and J2. Make sure that the polarity of this connection is correct. Apply an appropriate resistive/DC electronic load to the phase shifted full bridge system at the DC output at J3 and J4. Do not turn on 400V DC power at this time. Power up the bias supply between TP1 and TP2 with around 11V DC (this voltage must be less than 12V). 3. Double click on the Code Composer Studio icon on the desktop. Maximize Code Composer Studio to fill your screen. Close the welcome screen if it opens up. 4. A project contains all the files and build options needed to develop an executable output file (.out) which can be run on the MCU hardware. On the menu bar click: Project -> Import Existing CCS/CCE Eclipse Project and under Select root directory navigate to and select ..\controlSUITE\development_kits\HVPSFB_v1.1\HVPSFB_VMC directory. Make sure that under the Projects tab HVPSFB_VMC is checked. Click Finish. This project will invoke all the necessary tools (compiler, assembler, linker) to build the project. 5. In the project window on the left, click the plus sign (+) to the left of Project. Your project window will look like the following: Figure 36. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 43 Copyright © 2014, Texas Instruments Incorporated Procedure for Running Incremental Builds 6.1.4.1.2 Device Initialization, Main, and ISR Files www.ti.com NOTE: Do not make any changes to the source files – Only Inspect 1. Open and inspect HVPSFB-DevInit_F2802x.c by double clicking on the filename in the project window. Notice that system clock, peripheral clock prescale, and peripheral clock enables have been setup. Next, notice that the shared GPIO pins have been configured. 2. Open and inspect HVPSFB-Main.c. Notice the call made to DeviceInit() function and other variable initialization. Also notice code for different incremental build options (specifically the build you are going to compile now), the ISR intialization and the background for(;;) loop. 3. Locate and inspect the following code in the main file under initialization code specific for build 1. This is where the PWMDRV_PSFB_VMC_SR block is connected and initialized in the control flow. 4. Locate and inspect the following code in the main file under initialization code specific for build 1. This is where the ADCDRV_4CH block is configured, initialized and connected in the control flow. 44 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for Running Incremental Builds 5. Open and inspect HVPSFB-DPL-ISR.asm. Notice the _DPL_Init and _DPL_ISR sections. This is where the PWM and ADC driver macro instantiation is done for initialization and runtime, respectively. Optionally, you can close the inspected files. 6.1.4.1.3 Buld and Load the Project 1. Select the Incremental build option as 1 in the HVPSFB-Settings.h file. NOTE: Whenever you change the incremental build option in HVPSFB-Settings.h always do a “Rebuild All”. 2. Click Project -> “Rebuild All” button and watch the tools run in the build window. 3. Click Target -> ”Debug Active Project”. CCS will ask you to open a new Target configuration file if one hasn’t already been selected. If a valid target configuration file has been created for this connection you may go to Step 5. In the New target Configuration Window type in the name of the .ccxml file for the target you will be working with (Example: xds100-F28027.ccxml). Check “Use shared location” and click Finish. 4. In the .ccxml file that opens up select Connection as “Texas Instruments XDS100v2 USB Emulator” and under the device, scroll down and select “TMS320F28027”. Click Save. 5. Click Target -> ”Debug Active Project”. The program will be loaded into the FLASH or RAM memory depending on the project configuration selected. This project comes in only F2802x_FLASH configuration. You should now be at the start of Main(). 6.1.4.1.4 Debug Environment Windows It is standard debug practice to watch local and global variables while debugging code. There are various methods for doing this in Code Composer Studio, such as memory views and watch views. Additionally, Code Composer Studio has the ability to make time (and frequency) domain plots. This allows the user to view waveforms using graph windows. 1. If a watch view did not open when the debug environment was launched, open a new watch view and add various parameters to it by following the procedure given below. Click: View -> Watch on the menu bar. 2. Click the “Watch (1)" tab. You may add any variables to the watch view. 3. In the empty box in the "Name" column, type the symbol name of the variable you want to watch and press enter on keyboard. Be sure to modify the “Format” as needed. The watch view should look something like Figure 37. Please note that some of the variables have not been initialized at this point in the main code and may contain some garbage values. FaultFlg, if set, indicates an over current condition (discussed above), which shuts down the PWM outputs. PWM outputs are held in this state until a device reset (follow proper procedure in Step 11 of Section 6.1.4.1.6). The Ipri_trip variable sets the internal 10-bit DAC reference level for the on-chip comparator 1. Please note that this is a Q15 number. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 45 Copyright © 2014, Texas Instruments Incorporated Procedure for Running Incremental Builds www.ti.com Figure 37. 6.1.4.1.5 Using Real-Time Emulation Real-time emulation is a special emulation feature that allows the windows within Code Composer Studio to be updated at up to a 10 Hz rate while the MCU is running. This not only allows graphs and watch views to update, but also allows the user to change values in watch or memory windows, and have those changes affect the MCU behavior. This is very useful when tuning control law parameters on-the-fly, for example. 1. Enable real-time mode by hovering your mouse on the buttons on the horizontal toolbar and clicking button. 2. A message box may appear. If so, select YES to enable debug events. This will set bit 1 (DGBM bit) of status register 1 (ST1) to a “0”. The DGBM is the debug enable mask bit. When the DGBM bit is set to “0”, memory and register values can be passed to the host processor for updating the debugger windows. 3. Now click button on the same horizontal toolbar. 4. When a large number of windows are open, as bandwidth over the emulation link is limited, updating too many windows and variables in continuous refresh can cause the refresh frequency to bog down. Right click on the button in the watch view and select “Customize Continuous Refresh Interval..”. You can slow down the refresh rate for the watch view variables by changing the Continuous refresh interval (milliseconds) value. A rate of 4000 ms is usually enough for these exercises. 5. Click on Continuous Refresh buttons for the watch view. 46 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for Running Incremental Builds 6.1.4.1.6 Run the Code 1. Run the code by using the key, or using the Run button on the toolbar, or using Target -> Run on the menu bar. 2. In the watch view, the variable phase should be set to 0.015625 (Q24). This variable denotes the phase shift command to the PWMDRV_PSFB_VMC_SR module. Do not use a value of less than 0.005 for phase. 3. Apply an appropriate resistive load to the PSFB system at the DC output. A load that draws around 3A – 6A current at 12V output is a good starting point. NOTE: For safety reasons it is recommended to use an isolated DC source to supply 400V DC input to the board. 4. Power the input at J1, J2 with 400V DC. 5. Increase the phase command by setting phase to a higher value 0.1(say) in the watch view. The output voltage should increase. Observe the output voltage carefully, this should not be allowed to exceed the capabilities of the board. Keep in mind that when operating with a certain phase value if the load is suddenly reduced, the output voltage will go up. Therefore do not make any sudden changes of load or big increases in phase command when operating in build 1. 6. Observe the different ADC results in the watch view for different phase values. 7. Here is the watch view that corresponds to the operation of the system with a phase command of 0.705 (Q24) with an input voltage of around 400V and a load of around 6A at 12V output. Figure 38. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 47 Copyright © 2014, Texas Instruments Incorporated Procedure for Running Incremental Builds www.ti.com 8. The following oscilloscope capture shows the transformer primary voltage and the sensed primary current seen under conditions described above. Figure 39. 9. By default the synchronous rectifiers are operated in mode 2. You may change their mode of operation by changing SR_mode variable to 0, 1 or 2 from the watch view. Observe the change in amount of input current being drawn and change in output voltage with different SR modes. You may also probe the PWM waveforms driving the synchronous rectifier switches. Do not change between different SR modes when operating at very low loads or when the output voltage is very low (less than 6V). In these cases use the default SR mode 2. 10. Try different phase values and observe the corresponding ADC results. Increase phase in small steps. Always observe the output voltage carefully, this should not be allowed to exceed the capabilities of the board. Different waveforms, like the PWM gate drive signals, input voltage and current and output voltage may also be probed using an oscilloscope. Appropriate safety precautions should be taken and appropriate grounding requirements should be considered while probing these high voltages and high currents for this isolated DC-DC converter. 11. Fully halting the MCU when in real-time mode is a two-step process. With the 400V DC input turned off wait a few seconds. First, halt the processor by using the Halt button on the toolbar, or by using Target -> Halt. Then click MCU. button again to take the MCU out of real-time mode and then reset the 12. You may choose to leave Code Composer Studio running for the next exercise or optionally close CCS. 13. End of Exercise 48 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for Running Incremental Builds 6.2 Build 2: Closed Voltage Loop (Full HVPSFB in VMC Mode) 6.2.1 Objective The objective of this build is to verify the operation of the complete VMC based HVPSFB project from the CCS environment. 6.2.2 Overview Figure 40 shows the software blocks used in this build. The PWM and ADC driver blocks are used in the same way as in the previous build. A two pole two zero controller is used for the voltage loop. Depending on the application’s control loop requirements some other controller block like a PI, a 3-pole 3-zero, etc may also be used. As seen in the Figure 40, the voltage loop block is executed at 100 KHz. CNTL2P2Z is a 2nd order compensator realized from an IIR filter structure. This function is independent of any peripherals and therefore does not require a CNF function call. VfbSetSlewed 100Khz CNTL_2P2Z:1: Ref Fdbk Coef Out DBUFF phase CNTL_2P2Z_CoefStruct B0 B1 B2 A1 A2 Dmin Dmax dbAtoP_leg dbPtoA_leg 100Khz PWMDRV_PSFB_VMC_SR 1,2,4 PWMDRV_PSFB_Phase:n: P W M H W PWMDRV_PSFB_DbAtoP:n: PWMDRV_PSFB_DbPtoA:n: ePWM1A ePWM1B ePWM2A ePWM2B ePWM4A ePWM4B Adc_Vfbout Adc_Ifb Adc_Vfbin Adc_Iout 100Khz ADCDRV_4ch:1,2,3,4: RltPtrA RltPtrB A D RltPtrC C RltPtrD ADC A0 ADC A2 ADC B1 ADC B4 Figure 40. Build 2 Software Blocks The five coefficients to be modified are stored as elements of the structure CNTL_2P2Z_CoefStruct1 whose other elements are used for clamping the controller output. The CNTL_2P2Z block can be instantiated multiple times if the system needs multiple loops. Each instance can have separate set of coefficients. Directly manipulating the five coefficients independently by trial and error is almost impossible, and requires mathematical analysis and/or assistance from tools such as matlab, mathcad, etc. These tools offer bode plot, root-locus and other features for determining phase margin, gain margin, etc. To keep loop tuning simple and without the need for complex mathematics or analysis tools, the coefficient selection problem has been reduced from five degrees of freedom to three, by conveniently mapping the more intuitive coefficient gains of P, I and D to B0, B1, B2, A1, and A2. This allows P, I and D to be adjusted independently and gradually. These mapping equations are given below. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 49 Copyright © 2014, Texas Instruments Incorporated Procedure for Running Incremental Builds www.ti.com The compensator block (CNTL_2P2Z) has 2 poles and 2 zeros and is based on the general IIR filter structure. It has a reference input and a feedback input. For the voltage loop the feedback is the sensed output voltage (Adc_Vfbout), while the reference input to the controller is a slewed version (VfbSetSlewed) of the output voltage reference command (Vref). The transfer function is given by: ( ) U z b0 + b1z−1 + b2z−2 E(z) = 1 + a1z −1 + a2z−2 (5) The recursive form of the PID controller is given by the difference equation: u(k ) =u(k −1) + b0e(k ) + b1e(k −1) + b2e(k − 2) where b0 = Kp + Ki + Kd b1 = −Kp + Ki − 2Kd b2 = Kd And the z-domain transfer function form of this is: U z b0 b1z 1 b2 z 2 b0 z2 b1z b2 = = Ez 1 z1 z2 z (7) Comparing this with the general form, we can see that PID is nothing but a special case of CNTL_2P2Z control where: a1 = −1 and a2 = 0 (8) For the voltage loop these P, I and D coefficients are: Pgain, Igain and Dgain. These P, I and D coefficients are used in Q26 format. To simplify tuning from the GUI environment (or from CCS watch views) these three coefficients are further scaled to values from 0 to 999 (Pgain_Gui, Igain_Gui and Dgain_Gui). From the GUI environment the voltage loop can also be tuned using two poles (fp1, fp2), two zeroes (fz1, fz2) and gain (Kdc). These parameters provide b2_Gui, b1_Gui, b0_Gui, a2_Gui and a1_Gui coefficients in I5Q10 form which are then converted to the five Q26 coefficients for the 2P2Z controller. Although not recommended, b2_Gui, b1_Gui, b0_Gui, a2_Gui and a1_Gui values may also be directly changed from the CCS environment using watch views. Please refer to HVPSFB-Calculations.xls file for details on these calculations. The equations for deriving coefficient values based on poles, zeroes, gain and switching frequency are also clear from the GUI source file. This project allows easy evaluation of both methods of loop tuning by providing the ability to easily switch between coefficients during execution. This can be done by simply clicking on the 2P2Z(On)/PID(Off) button on the GUI or changing the pid2p2z_GUI variable to 0 or 1 on the watch view from CCS. PID based loop tuning (pid2p2z_GUI = 0) from the GUI environment was used as a starting point. Poles, zeroes and gain corresponding to these PID tuned coefficients were then used as a starting point for further loop tuning based on the second method (pid2p2z_GUI = 1). Much better results were then achieved by changing poles, zeroes and gain from the GUI environment to tune for optimum dynamic performance. By default coefficients based on these tuned poles, zeroes and gain values (pid2p2z_GUI = 1 – default) are used. NOTE: This project allows easy evaluation of both methods of loop tuning by providing the ability to easily switch between coefficients during execution. This can be done by simply clicking on the 2P2Z(On)/PID(Off) button on the GUI or changing the pid2p2z_GUI variable to 0 or 1 on the watch view from CCS. PID based loop tuning (pid2p2z_GUI = 0) from the GUI environment was used as a starting point. Poles, zeroes and gain corresponding to these PID tuned coefficients were then used as a starting point for further loop tuning based on the second method (pid2p2z_GUI = 1). Much better results were then achieved by changing poles, zeroes and gain from the GUI environment to tune for optimum dynamic performance. By default coefficients based on these tuned poles, zeroes and gain values (pid2p2z_GUI = 1 – default) are used. 50 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com 6.2.3 Procedure Procedure for Running Incremental Builds 6.2.3.1 Build and Load Project To quickly execute this build using the pre-configured work environment, follow the following steps: 1. Follow Steps 1 to 2 exactly as in build 1. If you were working on build 1 the last time CCS was used, the same workspace should open up with the project. If this is not the case, you can open the workspace used for build1 by clicking File -> Switch Workspace and then navigating to the correct workspace. If a workspace was not saved or got deleted, please follow steps 3 and 4 exactly as in build1 2. Locate and inspect the initialization code specific to build 2 in the main file. This is where all the control blocks are configured, initialized and connected in the control flow. 3. Select the Incremental build option as 2 in the HVPSFB-Settings.h. NOTE: Whenever you change the incremental build option in HVPSFB-Settings.h always do a “Rebuild All”. 4. Click Project -> “Rebuild All” button and watch the tools run in the build window. 5. Click Target -> ”Debug Active Project”. The program will be loaded into the FLASH or RAM memory depending on the project configuration. This project comes in only F2802x_FLASH configuration. You should now be at the start of Main().. 6.2.3.2 Debug Environment Windows It is standard debug practice to watch local and global variables while debugging code. There are various methods for doing this in Code Composer Studio, such as memory views and watch views. Additionally, Code Composer Studio has the ability to make time (and frequency) domain plots. This allows us to view waveforms using graph windows. 1. If a watch view did not open when the debug environment was launched, open a new watch view and add various parameters to it by following the procedure given below. 2. Click: View -> Watch on the menu bar. 3. Click the “Watch (1)" tab. If a watch view is already open from the debug environment saved for build 1, click on button in the watch view. A “Watch (2)” tab will open and you may then drag it to be viewed in a window of your choice. You may add any variables to this watch view tab. 4. In the empty box in the "Name" column, type the symbol name of the variable you want to watch and press enter on keyboard. Be sure to modify the “Format” as needed. The watch view should look something like the following. Please note that some of the variables have not been initialized at this point in the main code and may contain some garbage values. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 51 Copyright © 2014, Texas Instruments Incorporated Procedure for Running Incremental Builds www.ti.com Figure 41. Notice the additional variables in the watch view. 5. Gui_VfbSet is used to set the output voltage command. 6.2.3.3 Run the Code 1. Follow steps 1 to 4 of the build 1 Procedure to enable real time mode and continuous refresh for the watch views and also for changing the continuous refresh interval for the watch view if needed. 2. Run the code by using the key, or using the Run button on the toolbar, or using Target -> Run on the menu bar. 3. Apply an appropriate resistive load to the PSFB system at the DC output. A load that draws around 3A – 6A current at 12V output is a good starting point. NOTE: For safety reasons it is recommended to use an isolated DC source to supply 400V DC input to the board. 4. Power the input at J1, J2 with 400V DC. 5. By default Auto_Run is set to 1. If it is not, make it 1 from the watch view. The output voltage should now start ramping up to 12V. This output voltage ramp up rate can be changed by changing the variable VfbSlewRate. 52 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com Procedure for Running Incremental Builds 6. Figure 42 is the watch view that corresponds to the operation of the system with 12V at the output with an input voltage of around 400V and a load of around 6A output. Figure 42. 7. The following picture shows waveforms captured under this condition. Figure 43. 8. By default the synchronous rectifiers are operated in mode 2. You may change their mode of operation by changing SR_mode variable to 0, 1 or 2 from the watch view. Observe the change in amount of input current being drawn and change in output voltage with different SR modes. You may also probe the PWM waveforms driving the synchronous rectifier switches. Do not change between different SR modes when operating at very low loads (below 3A). In these cases use the default SR mode 2. TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 53 Copyright © 2014, Texas Instruments Incorporated Procedure for Running Incremental Builds www.ti.com 9. Observe the effect of varying load* on the output voltage and input current. There should be virtually no effect on the output voltage. Similarly observe the effect of varying the input voltage*. Again there should be virtually no effect on the output voltage. NOTE: Ensure that these changes are made within the abilities of the board as listed in Section 1.3. 10. Different waveforms, like the PWM gate drive signals, input voltage and current and output voltage may also be probed using an oscilloscope. Appropriate safety precautions should be taken and appropriate grounding requirements should be considered while probing these high voltages and high currents for this isolated DC-DC converter. 11. Fully halting the MCU when in real-time mode is a two-step process. With the 400V DC input turned off wait a few seconds. First, halt the processor by using the Halt button on the toolbar, or by using Target -> Halt. Then click MCU. 12. Close CCS 13. End of Exercise button again to take the MCU out of real-time mode and then reset the 54 Phase-Shifted Full Bridge DC/DC Power Converter Design Guide Copyright © 2014, Texas Instruments Incorporated TIDU248 – May 2014 Submit Documentation Feedback www.ti.com References 7 References For more information, please refer to the following guides: 1. UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report (Literature Number SLUA560) 2. 600-W, Phase-Shifted, Full-Bridge Converter (Literature Number SLUU421) 3. H. Nene, “Implementing Advanced Control Strategies for Phase Shifted Full-Bridge DC-DC Converters using Micro-Controllers” PCIM Europe 2011, Nuremberg, Germany. 4. HVPSFB-Calculations.xls – a spreadsheet showing key calculations for the HVPSFB project. ..\controlSUITE\development_kits\HVPSFB_v1.1\~Docs 5. QSG-HVPSB-Rev1.1.pdf– gives an overview on how to quickly run and experiment with the HVPSFB project using an intuitive GUI interface. ..\controlSUITE\development_kits\HVPSFB_v1.1\~Docs 6. HVPSFB_RevB-HWdevPkg – a folder containing various files related to the base board and Piccolo-A controller card. ..\controlSUITE\development_kits\HVPSFB_v1.1\~HVPSFB_HWdevPkg\RevB 7. F28xxx User's Guides (http://www.ti.com/f28xuserguides) TIDU248 – May 2014 Submit Documentation Feedback Phase-Shifted Full Bridge DC/DC Power Converter Design Guide 55 Copyright © 2014, Texas Instruments Incorporated IMPORTANT NOTICE FOR TI REFERENCE DESIGNS Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“Buyers”) who are developing systems that incorporate TI semiconductor products (also referred to herein as “components”). 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