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MSP430x5xx and MSP430x6xx Family User's Guide Literature Number: SLAU208O June 2008 – Revised May 2015 Contents Preface....................................................................................................................................... 52 1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)....................... 54 1.1 System Control Module (SYS) Introduction ............................................................................ 55 1.2 System Reset and Initialization........................................................................................... 55 1.2.1 Device Initial Conditions After System Reset.................................................................. 57 1.3 Interrupts .................................................................................................................... 57 1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 58 1.3.2 SNMI Timing ....................................................................................................... 59 1.3.3 Maskable Interrupts ............................................................................................... 59 1.3.4 Interrupt Processing............................................................................................... 59 1.3.5 Interrupt Nesting................................................................................................... 61 1.3.6 Interrupt Vectors................................................................................................... 61 1.3.7 SYS Interrupt Vector Generators................................................................................ 62 1.4 Operating Modes ........................................................................................................... 63 1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4............................................. 66 1.4.2 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 66 1.4.3 Extended Time in Low-Power Modes .......................................................................... 67 1.5 Principles for Low-Power Applications .................................................................................. 68 1.6 Connection of Unused Pins ............................................................................................... 69 1.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 69 1.8 Configuring JTAG Pins .................................................................................................... 70 1.9 Boot Code ................................................................................................................... 70 1.10 Bootstrap Loader (BSL) ................................................................................................... 70 1.11 Memory Map – Uses and Abilities ....................................................................................... 71 1.11.1 Vacant Memory Space .......................................................................................... 72 1.11.2 JTAG Lock Mechanism Using the Electronic Fuse .......................................................... 72 1.12 JTAG Mailbox (JMB) System ............................................................................................ 72 1.12.1 JMB Configuration ............................................................................................... 72 1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox................................................................. 72 1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox....................................................................... 73 1.12.4 JMB NMI Usage .................................................................................................. 73 1.13 Device Descriptor Table ................................................................................................... 73 1.13.1 Identifying Device Type.......................................................................................... 74 1.13.2 TLV Descriptors .................................................................................................. 75 1.13.3 Peripheral Discovery Descriptor ............................................................................... 76 1.13.4 CRC Computation................................................................................................ 80 1.13.5 Calibration Values................................................................................................ 81 1.13.6 Temperature Sensor Calibration for Devices With CTSD16 ............................................... 82 1.14 SFR Registers .............................................................................................................. 83 1.14.1 SFRIE1 Register ................................................................................................. 84 1.14.2 SFRIFG1 Register ............................................................................................... 85 1.14.3 SFRRPCR Register.............................................................................................. 87 1.15 SYS Registers .............................................................................................................. 88 1.15.1 SYSCTL Register ................................................................................................ 89 1.15.2 SYSBSLC Register .............................................................................................. 90 2 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 1.15.3 SYSJMBC Register .............................................................................................. 91 1.15.4 SYSJMBI0 Register.............................................................................................. 92 1.15.5 SYSJMBI1 Register.............................................................................................. 92 1.15.6 SYSJMBO0 Register ............................................................................................ 93 1.15.7 SYSJMBO1 Register ............................................................................................ 93 1.15.8 SYSUNIV Register ............................................................................................... 94 1.15.9 SYSSNIV Register ............................................................................................... 95 1.15.10 SYSRSTIV Register ............................................................................................ 96 1.15.11 SYSBERRIV Register .......................................................................................... 97 2 Power Management Module and Supply Voltage Supervisor ................................................... 98 2.1 Power Management Module (PMM) Introduction ...................................................................... 99 2.2 PMM Operation ........................................................................................................... 101 2.2.1 VCORE and the Regulator......................................................................................... 101 2.2.2 Supply Voltage Supervisor and Monitor ...................................................................... 101 2.2.3 Supply Voltage Supervisor and Monitor - Power-Up........................................................ 107 2.2.4 Increasing VCORE to Support Higher MCLK Frequencies ................................................... 108 2.2.5 Decreasing VCORE for Power Optimization .................................................................... 109 2.2.6 Transition From LPM3 and LPM4 Modes to AM ............................................................ 109 2.2.7 LPM3.5 and LPM4.5 ............................................................................................ 109 2.2.8 Brownout Reset (BOR), Software BOR, Software POR .................................................... 110 2.2.9 SVS and SVM Performance Modes and Wakeup Times .................................................. 110 2.2.10 PMM Interrupts.................................................................................................. 113 2.2.11 Port I/O Control ................................................................................................. 113 2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional)...................................................... 113 2.3 PMM Registers............................................................................................................ 114 2.3.1 PMMCTL0 Register.............................................................................................. 115 2.3.2 PMMCTL1 Register.............................................................................................. 116 2.3.3 SVSMHCTL Register............................................................................................ 117 2.3.4 SVSMLCTL Register ............................................................................................ 118 2.3.5 SVSMIO Register ................................................................................................ 119 2.3.6 PMMIFG Register................................................................................................ 120 2.3.7 PMMRIE Register................................................................................................ 122 2.3.8 PM5CTL0 Register .............................................................................................. 123 3 Battery Backup System ..................................................................................................... 124 3.1 Battery Backup Introduction ............................................................................................. 125 3.2 Battery Backup Operation ............................................................................................... 125 3.2.1 Activate Access to Backup-Supplied Subsystem............................................................ 126 3.2.2 Manual Switching ................................................................................................ 127 3.2.3 Disable Switching ................................................................................................ 127 3.2.4 Measuring the Supplies ......................................................................................... 127 3.2.5 LPMx.5 and Backup Operation ................................................................................ 127 3.2.6 Resistive Charger................................................................................................ 128 3.3 Battery Backup Registers................................................................................................ 129 3.3.1 BAKCTL Register ................................................................................................ 130 3.3.2 BAKCHCTL Register ............................................................................................ 131 4 Auxiliary Supply System (AUX) .......................................................................................... 132 4.1 Auxiliary Supply System Introduction .................................................................................. 133 4.2 Auxiliary Supply Operation .............................................................................................. 134 4.2.1 Startup............................................................................................................. 135 4.2.2 Switching Control ................................................................................................ 135 4.2.3 Software-Controlled Switching ................................................................................. 135 4.2.4 Hardware-Controlled Switching ................................................................................ 136 4.2.5 Interactions Among fSYS, VCORE, VDSYS, SVMH, and AUXxLVL ............................................... 137 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 3 www.ti.com 4.2.6 Auxiliary Supply Monitor ........................................................................................ 139 4.2.7 LPMx.5 and Auxiliary Supply Operation ...................................................................... 141 4.2.8 Digital I/Os and Auxiliary Supplies............................................................................. 141 4.2.9 Measuring the Supplies ......................................................................................... 142 4.2.10 Resistive Charger............................................................................................... 143 4.2.11 Auxiliary Supply Interrupts..................................................................................... 143 4.2.12 Software Flow ................................................................................................... 145 4.2.13 Examples of AUX Operation .................................................................................. 146 4.3 AUX Registers............................................................................................................. 148 4.3.1 AUXCTL0 Register .............................................................................................. 149 4.3.2 AUXCTL1 Register .............................................................................................. 150 4.3.3 AUXCTL2 Register .............................................................................................. 151 4.3.4 AUX2CHCTL Register .......................................................................................... 152 4.3.5 AUX3CHCTL Register .......................................................................................... 153 4.3.6 AUXADCCTL Register .......................................................................................... 154 4.3.7 AUXIFG Register ................................................................................................ 155 4.3.8 AUXIE Register .................................................................................................. 156 4.3.9 AUXIV Register .................................................................................................. 157 5 Unified Clock System (UCS)............................................................................................... 158 5.1 Unified Clock System (UCS) Introduction ............................................................................. 159 5.2 UCS Operation ............................................................................................................ 161 5.2.1 UCS Module Features for Low-Power Applications ......................................................... 161 5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................ 161 5.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO) .......................................... 162 5.2.4 XT1 Oscillator .................................................................................................... 162 5.2.5 XT2 Oscillator ................................................................................................... 163 5.2.6 Digitally Controlled Oscillator (DCO) .......................................................................... 164 5.2.7 Frequency Locked Loop (FLL) ................................................................................. 165 5.2.8 DCO Modulator .................................................................................................. 166 5.2.9 Disabling FLL Hardware and Modulator ...................................................................... 166 5.2.10 FLL Operation From Low-Power Modes..................................................................... 167 5.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules................................ 167 5.2.12 UCS Module Fail-Safe Operation............................................................................. 168 5.2.13 Synchronization of Clock Signals............................................................................. 171 5.3 Module Oscillator (MODOSC)........................................................................................... 172 5.3.1 MODOSC Operation ............................................................................................ 172 5.4 UCS Registers ............................................................................................................ 173 5.4.1 UCSCTL0 Register .............................................................................................. 174 5.4.2 UCSCTL1 Register .............................................................................................. 175 5.4.3 UCSCTL2 Register .............................................................................................. 176 5.4.4 UCSCTL3 Register .............................................................................................. 177 5.4.5 UCSCTL4 Register .............................................................................................. 178 5.4.6 UCSCTL5 Register .............................................................................................. 179 5.4.7 UCSCTL6 Register .............................................................................................. 181 5.4.8 UCSCTL7 Register .............................................................................................. 183 5.4.9 UCSCTL8 Register .............................................................................................. 184 5.4.10 UCSCTL9 Register ............................................................................................. 185 6 CPUX .............................................................................................................................. 186 6.1 MSP430X CPU (CPUX) Introduction................................................................................... 187 6.2 Interrupts ................................................................................................................... 189 6.3 CPU Registers ............................................................................................................ 190 6.3.1 Program Counter (PC) .......................................................................................... 190 6.3.2 Stack Pointer (SP) ............................................................................................... 190 4 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.3.3 Status Register (SR) ............................................................................................ 192 6.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 193 6.3.5 General-Purpose Registers (R4 to R15)...................................................................... 194 6.4 Addressing Modes ........................................................................................................ 196 6.4.1 Register Mode.................................................................................................... 197 6.4.2 Indexed Mode .................................................................................................... 198 6.4.3 Symbolic Mode................................................................................................... 203 6.4.4 Absolute Mode ................................................................................................... 207 6.4.5 Indirect Register Mode .......................................................................................... 209 6.4.6 Indirect Autoincrement Mode................................................................................... 210 6.4.7 Immediate Mode ................................................................................................. 211 6.5 MSP430 and MSP430X Instructions ................................................................................... 213 6.5.1 MSP430 Instructions ............................................................................................ 213 6.5.2 MSP430X Extended Instructions .............................................................................. 218 6.6 Instruction Set Description............................................................................................... 229 6.6.1 Extended Instruction Binary Descriptions..................................................................... 230 6.6.2 MSP430 Instructions ............................................................................................ 232 6.6.3 Extended Instructions ........................................................................................... 284 6.6.4 Address Instructions............................................................................................. 327 7 Flash Memory Controller ................................................................................................... 342 7.1 Flash Memory Introduction .............................................................................................. 343 7.2 Flash Memory Segmentation............................................................................................ 344 7.2.1 Segment A ........................................................................................................ 345 7.3 Flash Memory Operation ................................................................................................ 346 7.3.1 Erasing Flash Memory .......................................................................................... 346 7.3.2 Writing Flash Memory ........................................................................................... 350 7.3.3 Flash Memory Access During Write or Erase................................................................ 357 7.3.4 Stopping Write or Erase Cycle ................................................................................. 358 7.3.5 Checking Flash Memory ........................................................................................ 358 7.3.6 Configuring and Accessing the Flash Memory Controller .................................................. 359 7.3.7 Flash Memory Controller Interrupts ........................................................................... 359 7.3.8 Programming Flash Memory Devices......................................................................... 360 7.4 FCTL Registers ........................................................................................................... 361 7.4.1 FCTL1 Register .................................................................................................. 362 7.4.2 FCTL3 Register .................................................................................................. 363 7.4.3 FCTL4 Register .................................................................................................. 364 7.4.4 SFRIE1 Register ................................................................................................. 365 8 Memory Integrity Detection (MID)........................................................................................ 366 8.1 MID Overview ............................................................................................................. 367 8.2 Flash Memory With MID Support ....................................................................................... 368 8.3 MID Parity Check Logic .................................................................................................. 368 8.4 Detecting Unprogrammed Memory Accesses ........................................................................ 369 8.5 MID ROM .................................................................................................................. 369 8.6 MID Support Software Function ........................................................................................ 369 8.6.1 MidEnable() Function............................................................................................ 370 8.6.2 MidDisable() Function ........................................................................................... 371 8.6.3 MidGetErrAdr() Function........................................................................................ 371 8.6.4 MidCheckMem() Function ...................................................................................... 372 8.6.5 MidSetRaw() Function........................................................................................... 372 8.6.6 MidGetParity() Function......................................................................................... 373 8.6.7 MidCalcVParity() Function ...................................................................................... 373 8.7 User's UNMI Interrupt Handler .......................................................................................... 373 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 5 www.ti.com 9 RAM Controller (RAMCTL) ................................................................................................. 374 9.1 RAM Controller (RAMCTL) Introduction ............................................................................... 375 9.2 RAMCTL Operation....................................................................................................... 375 9.3 RAMCTL Registers ....................................................................................................... 376 9.3.1 RCCTL0 Register ................................................................................................ 377 10 Backup RAM .................................................................................................................... 378 10.1 Backup RAM Introduction and Operation.............................................................................. 379 10.2 Battery Backup Registers................................................................................................ 379 11 Direct Memory Access (DMA) Controller Module .................................................................. 380 11.1 Direct Memory Access (DMA) Introduction............................................................................ 381 11.2 DMA Operation............................................................................................................ 383 11.2.1 DMA Addressing Modes ....................................................................................... 383 11.2.2 DMA Transfer Modes .......................................................................................... 384 11.2.3 Initiating DMA Transfers ....................................................................................... 390 11.2.4 Halting Executing Instructions for DMA Transfers.......................................................... 390 11.2.5 Stopping DMA Transfers....................................................................................... 391 11.2.6 DMA Channel Priorities ........................................................................................ 391 11.2.7 DMA Transfer Cycle Time ..................................................................................... 392 11.2.8 Using DMA With System Interrupts .......................................................................... 392 11.2.9 DMA Controller Interrupts ..................................................................................... 392 11.2.10 Using the USCI_B I2C Module With the DMA Controller................................................. 394 11.2.11 Using ADC10 With the DMA Controller .................................................................... 394 11.2.12 Using ADC12 With the DMA Controller .................................................................... 394 11.2.13 Using DAC12 With the DMA Controller .................................................................... 394 11.3 DMA Registers ............................................................................................................ 395 11.3.1 DMACTL0 Register............................................................................................. 397 11.3.2 DMACTL1 Register............................................................................................. 398 11.3.3 DMACTL2 Register............................................................................................. 399 11.3.4 DMACTL3 Register............................................................................................. 400 11.3.5 DMACTL4 Register............................................................................................. 401 11.3.6 DMAxCTL Register ............................................................................................. 402 11.3.7 DMAxSA Register .............................................................................................. 404 11.3.8 DMAxDA Register .............................................................................................. 405 11.3.9 DMAxSZ Register............................................................................................... 406 11.3.10 DMAIV Register ............................................................................................... 407 12 Digital I/O Module ............................................................................................................. 408 12.1 Digital I/O Introduction ................................................................................................... 409 12.2 Digital I/O Operation...................................................................................................... 410 12.2.1 Input Registers (PxIN).......................................................................................... 410 12.2.2 Output Registers (PxOUT) .................................................................................... 410 12.2.3 Direction Registers (PxDIR) ................................................................................... 410 12.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) .................................................. 410 12.2.5 Output Drive Strength Registers (PxDS) .................................................................... 411 12.2.6 Function Select Registers (PxSEL) .......................................................................... 411 12.2.7 Port Interrupts ................................................................................................... 411 12.2.8 Configuring Unused Port Pins ................................................................................ 413 12.3 I/O Configuration and LPMx.5 Low-Power Modes ................................................................... 413 12.4 Digital I/O Registers ...................................................................................................... 416 12.4.1 P1IV Register ................................................................................................... 422 12.4.2 P2IV Register ................................................................................................... 423 12.4.3 P1IES Register.................................................................................................. 424 12.4.4 P1IE Register ................................................................................................... 424 12.4.5 P1IFG Register.................................................................................................. 424 6 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 12.4.6 P2IES Register.................................................................................................. 425 12.4.7 P2IE Register ................................................................................................... 425 12.4.8 P2IFG Register.................................................................................................. 425 12.4.9 PxIN Register ................................................................................................... 426 12.4.10 PxOUT Register ............................................................................................... 426 12.4.11 PxDIR Register ................................................................................................ 426 12.4.12 PxREN Register ............................................................................................... 427 12.4.13 PxDS Register ................................................................................................. 427 12.4.14 PxSEL Register................................................................................................ 427 13 Port Mapping Controller .................................................................................................... 428 13.1 Port Mapping Controller Introduction................................................................................... 429 13.2 Port Mapping Controller Operation ..................................................................................... 429 13.2.1 Access ........................................................................................................... 429 13.2.2 Mapping.......................................................................................................... 429 13.3 Port Mapping Controller Registers ..................................................................................... 431 13.3.1 PMAPKEYID Register.......................................................................................... 432 13.3.2 PMAPCTL Register............................................................................................. 432 13.3.3 PxMAPy Register ............................................................................................... 432 14 Cyclic Redundancy Check (CRC) Module ............................................................................ 433 14.1 Cyclic Redundancy Check (CRC) Module Introduction.............................................................. 434 14.2 CRC Standard and Bit Order............................................................................................ 434 14.3 CRC Checksum Generation............................................................................................. 435 14.3.1 CRC Implementation ........................................................................................... 435 14.3.2 Assembler Examples........................................................................................... 436 14.4 CRC Registers ............................................................................................................ 438 14.4.1 CRCDI Register................................................................................................. 439 14.4.2 CRCDIRB Register ............................................................................................. 439 14.4.3 CRCINIRES Register........................................................................................... 440 14.4.4 CRCRESR Register ............................................................................................ 440 15 AES Accelerator ............................................................................................................... 441 15.1 AES Accelerator Introduction............................................................................................ 442 15.2 AES Accelerator Operation.............................................................................................. 443 15.2.1 Encryption ....................................................................................................... 444 15.2.2 Decryption ....................................................................................................... 445 15.2.3 Decryption Key Generation.................................................................................... 446 15.2.4 Using the AES Accelerator With Low-Power Modes....................................................... 447 15.2.5 AES Accelerator Interrupts .................................................................................... 447 15.2.6 Implementing Block Cipher Modes ........................................................................... 447 15.3 AES_ACCEL Registers .................................................................................................. 448 15.3.1 AESACTL0 Register............................................................................................ 449 15.3.2 AESACTL1 Register............................................................................................ 450 15.3.3 AESASTAT Register ........................................................................................... 451 15.3.4 AESAKEY Register............................................................................................. 452 15.3.5 AESADIN Register ............................................................................................. 453 15.3.6 AESADOUT Register .......................................................................................... 453 15.3.7 AESAXDIN Register............................................................................................ 454 15.3.8 AESAXIN Register.............................................................................................. 454 16 Watchdog Timer (WDT_A).................................................................................................. 455 16.1 WDT_A Introduction ...................................................................................................... 456 16.2 WDT_A Operation ........................................................................................................ 458 16.2.1 Watchdog Timer Counter (WDTCNT)........................................................................ 458 16.2.2 Watchdog Mode ................................................................................................ 458 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 7 www.ti.com 16.2.3 Interval Timer Mode ............................................................................................ 458 16.2.4 Watchdog Timer Interrupts .................................................................................... 458 16.2.5 Clock Fail-Safe Feature........................................................................................ 459 16.2.6 Operation in Low-Power Modes .............................................................................. 459 16.2.7 Software Examples ............................................................................................. 459 16.3 WDT_A Registers......................................................................................................... 460 16.3.1 WDTCTL Register .............................................................................................. 461 17 Timer_A........................................................................................................................... 462 17.1 Timer_A Introduction ..................................................................................................... 463 17.2 Timer_A Operation ....................................................................................................... 465 17.2.1 16-Bit Timer Counter ........................................................................................... 465 17.2.2 Starting the Timer............................................................................................... 465 17.2.3 Timer Mode Control ............................................................................................ 466 17.2.4 Capture/Compare Blocks ...................................................................................... 469 17.2.5 Output Unit ...................................................................................................... 471 17.2.6 Timer_A Interrupts.............................................................................................. 475 17.3 Timer_A Registers ........................................................................................................ 477 17.3.1 TAxCTL Register ............................................................................................... 478 17.3.2 TAxR Register................................................................................................... 479 17.3.3 TAxCCTLn Register ............................................................................................ 480 17.3.4 TAxCCRn Register ............................................................................................ 482 17.3.5 TAxIV Register .................................................................................................. 482 17.3.6 TAxEX0 Register ............................................................................................... 483 18 Timer_B........................................................................................................................... 484 18.1 Timer_B Introduction ..................................................................................................... 485 18.1.1 Similarities and Differences From Timer_A ................................................................. 485 18.2 Timer_B Operation ....................................................................................................... 487 18.2.1 16-Bit Timer Counter ........................................................................................... 487 18.2.2 Starting the Timer............................................................................................... 487 18.2.3 Timer Mode Control ............................................................................................ 488 18.2.4 Capture/Compare Blocks ...................................................................................... 491 18.2.5 Output Unit ...................................................................................................... 494 18.2.6 Timer_B Interrupts.............................................................................................. 498 18.3 Timer_B Registers ........................................................................................................ 500 18.3.1 TBxCTL Register ............................................................................................... 501 18.3.2 TBxR Register................................................................................................... 503 18.3.3 TBxCCTLn Register ............................................................................................ 504 18.3.4 TBxCCRn Register ............................................................................................. 506 18.3.5 TBxIV Register .................................................................................................. 507 18.3.6 TBxEX0 Register ............................................................................................... 508 19 Timer_D........................................................................................................................... 509 19.1 Timer_D Introduction ..................................................................................................... 510 19.1.1 Differences From Timer_B .................................................................................... 510 19.2 Timer_D Operation ....................................................................................................... 512 19.2.1 16-Bit Timer Counter ........................................................................................... 512 19.2.2 High-Resolution Generator .................................................................................... 513 19.2.3 Starting the Timer............................................................................................... 515 19.2.4 Timer Mode Control ............................................................................................ 515 19.2.5 PWM Generation ............................................................................................... 520 19.2.6 Capture/Compare Blocks ...................................................................................... 523 19.2.7 Compare Mode.................................................................................................. 526 19.2.8 Switching From Capture to Compare Mode................................................................. 527 19.2.9 Output Unit ...................................................................................................... 527 8 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 19.2.10 Synchronization Between Timer_D Instances ............................................................ 534 19.2.11 Timer_D Interrupts ............................................................................................ 534 19.3 Timer_D Registers........................................................................................................ 536 19.3.1 TDxCTL0 Register.............................................................................................. 537 19.3.2 TDxCTL1 Register.............................................................................................. 539 19.3.3 TDxCTL2 Register.............................................................................................. 540 19.3.4 TDxR Register .................................................................................................. 541 19.3.5 TDxCCTLn Register............................................................................................ 542 19.3.6 TDxCCRn Register ............................................................................................. 544 19.3.7 TDxCLn Register ............................................................................................... 544 19.3.8 TDxHCTL0 Register............................................................................................ 545 19.3.9 TDxHCTL1 Register............................................................................................ 546 19.3.10 TDxHINT Register............................................................................................. 547 19.3.11 TDxIV Register ................................................................................................ 548 20 Timer Event Control (TEC) ................................................................................................. 549 20.1 Timer Event Control Introduction ....................................................................................... 550 20.2 TEC Operation ............................................................................................................ 551 20.2.1 AUXCLK Selection Sub-Block ................................................................................ 551 20.2.2 External Clear Sub-Block ..................................................................................... 551 20.2.3 Channel Event Sub-Block..................................................................................... 551 20.2.4 Module Level Connection Between TEC and Timer_D.................................................... 552 20.2.5 Synchronization Mechanism Between Timer_D Instances................................................ 554 20.2.6 Timer Event Control Interrupts ................................................................................ 556 20.3 TEC Registers............................................................................................................. 557 20.3.1 TECxCTL0 Register ............................................................................................ 558 20.3.2 TECxCTL1 Register ............................................................................................ 560 20.3.3 TECxCTL2 Register ............................................................................................ 562 20.3.4 TECxSTA Register ............................................................................................. 563 20.3.5 TECxINT Register .............................................................................................. 564 20.3.6 TECxIV Register ................................................................................................ 565 21 Real-Time Clock (RTC) Overview ........................................................................................ 566 21.1 RTC Overview............................................................................................................. 566 22 Real-Time Clock (RTC_A) .................................................................................................. 567 22.1 RTC_A Introduction....................................................................................................... 568 22.2 RTC_A Operation......................................................................................................... 570 22.2.1 Counter Mode ................................................................................................... 570 22.2.2 Calendar Mode.................................................................................................. 570 22.2.3 Real-Time Clock Interrupts .................................................................................... 572 22.2.4 Real-Time Clock Calibration .................................................................................. 574 22.3 RTC_A Registers ......................................................................................................... 576 22.3.1 RTCCTL0 Register ............................................................................................. 578 22.3.2 RTCCTL1 Register ............................................................................................. 579 22.3.3 RTCCTL2 Register ............................................................................................. 580 22.3.4 RTCCTL3 Register ............................................................................................. 580 22.3.5 RTCNT1 Register............................................................................................... 581 22.3.6 RTCNT2 Register............................................................................................... 581 22.3.7 RTCNT3 Register............................................................................................... 581 22.3.8 RTCNT4 Register............................................................................................... 581 22.3.9 RTCSEC Register – Calendar Mode With Hexadecimal Format......................................... 582 22.3.10 RTCSEC Register – Calendar Mode With BCD Format ................................................. 582 22.3.11 RTCMIN Register – Calendar Mode With Hexadecimal Format........................................ 583 22.3.12 RTCMIN Register – Calendar Mode With BCD Format.................................................. 583 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 9 www.ti.com 22.3.13 RTCHOUR Register – Calendar Mode With Hexadecimal Format..................................... 584 22.3.14 RTCHOUR Register – Calendar Mode With BCD Format............................................... 584 22.3.15 RTCDOW Register – Calendar Mode ...................................................................... 585 22.3.16 RTCDAY Register – Calendar Mode With Hexadecimal Format ....................................... 585 22.3.17 RTCDAY Register – Calendar Mode With BCD Format ................................................. 585 22.3.18 RTCMON Register – Calendar Mode With Hexadecimal Format ...................................... 586 22.3.19 RTCMON Register – Calendar Mode With BCD Format ................................................ 586 22.3.20 RTCYEARL Register – Calendar Mode With Hexadecimal Format .................................... 587 22.3.21 RTCYEARL Register – Calendar Mode With BCD Format.............................................. 587 22.3.22 RTCYEARH Register – Calendar Mode With Hexadecimal Format ................................... 588 22.3.23 RTCYEARH Register – Calendar Mode With BCD Format ............................................. 588 22.3.24 RTCAMIN Register – Calendar Mode With Hexadecimal Format ...................................... 589 22.3.25 RTCAMIN Register – Calendar Mode With BCD Format ................................................ 589 22.3.26 RTCAHOUR Register – Calendar Mode With Hexadecimal Format ................................... 590 22.3.27 RTCAHOUR Register – Calendar Mode With BCD Format ............................................. 590 22.3.28 RTCADOW Register .......................................................................................... 591 22.3.29 RTCADAY Register – Calendar Mode With Hexadecimal Format ..................................... 591 22.3.30 RTCADAY Register – Calendar Mode With BCD Format ............................................... 591 22.3.31 RTCPS0CTL Register ........................................................................................ 593 22.3.32 RTCPS1CTL Register ........................................................................................ 594 22.3.33 RT0PS Register ............................................................................................... 595 22.3.34 RT1PS Register ............................................................................................... 595 22.3.35 RTCIV Register................................................................................................ 595 23 Real-Time Clock B (RTC_B) ............................................................................................... 596 23.1 Real-Time Clock RTC_B Introduction.................................................................................. 597 23.2 RTC_B Operation......................................................................................................... 599 23.2.1 Real-Time Clock and Prescale Dividers ..................................................................... 599 23.2.2 Real-Time Clock Alarm Function ............................................................................. 599 23.2.3 Reading or Writing Real-Time Clock Registers............................................................. 600 23.2.4 Real-Time Clock Interrupts .................................................................................... 600 23.2.5 Real-Time Clock Calibration .................................................................................. 602 23.2.6 Real-Time Clock Operation in LPM3.5 Low-Power Mode................................................. 603 23.3 RTC_B Registers ......................................................................................................... 604 23.3.1 RTCCTL0 Register ............................................................................................. 606 23.3.2 RTCCTL1 Register ............................................................................................. 607 23.3.3 RTCCTL2 Register ............................................................................................. 608 23.3.4 RTCCTL3 Register ............................................................................................. 608 23.3.5 RTCSEC Register – Hexadecimal Format .................................................................. 609 23.3.6 RTCSEC Register – BCD Format ............................................................................ 609 23.3.7 RTCMIN Register – Hexadecimal Format................................................................... 610 23.3.8 RTCMIN Register – BCD Format............................................................................. 610 23.3.9 RTCHOUR Register – Hexadecimal Format................................................................ 611 23.3.10 RTCHOUR Register – BCD Format ........................................................................ 611 23.3.11 RTCDOW Register............................................................................................ 612 23.3.12 RTCDAY Register – Hexadecimal Format................................................................. 612 23.3.13 RTCDAY Register – BCD Format........................................................................... 612 23.3.14 RTCMON Register – Hexadecimal Format ................................................................ 613 23.3.15 RTCMON Register – BCD Format.......................................................................... 613 23.3.16 RTCYEAR Register – Hexadecimal Format ............................................................... 614 23.3.17 RTCYEAR Register – BCD Format......................................................................... 614 23.3.18 RTCAMIN Register – Hexadecimal Format ............................................................... 615 23.3.19 RTCAMIN Register – BCD Format ......................................................................... 615 23.3.20 RTCAHOUR Register – Hexadecimal Format ............................................................ 616 10 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 23.3.21 RTCAHOUR Register – BCD Format ...................................................................... 616 23.3.22 RTCADOW Register .......................................................................................... 617 23.3.23 RTCADAY Register – Hexadecimal Format ............................................................... 618 23.3.24 RTCADAY Register – BCD Format......................................................................... 618 23.3.25 RTCPS0CTL Register ........................................................................................ 619 23.3.26 RTCPS1CTL Register ........................................................................................ 620 23.3.27 RTCPS0 Register ............................................................................................. 621 23.3.28 RTCPS1 Register ............................................................................................. 621 23.3.29 RTCIV Register................................................................................................ 622 23.3.30 BIN2BCD Register ............................................................................................ 623 23.3.31 BCD2BIN Register ............................................................................................ 623 24 Real-Time Clock C (RTC_C) ............................................................................................... 624 24.1 Real-Time Clock (RTC_C) Introduction................................................................................ 625 24.2 RTC_C Operation......................................................................................................... 627 24.2.1 Calendar Mode.................................................................................................. 627 24.2.2 Real-Time Clock and Prescale Dividers .................................................................... 627 24.2.3 Real-Time Clock Alarm Function ............................................................................ 627 24.2.4 Real-Time Clock Protection ................................................................................... 628 24.2.5 Reading or Writing Real-Time Clock Registers ............................................................ 629 24.2.6 Real-Time Clock Interrupts .................................................................................... 629 24.2.7 Real-Time Clock Calibration for Crystal Offset Error....................................................... 631 24.2.8 Real-Time Clock Compensation for Crystal Temperature Drift ........................................... 632 24.2.9 Real-Time Clock Operation in LPM3.5 Low-Power Mode................................................. 634 24.3 RTC_C Operation - Device-Dependent Features .................................................................... 636 24.3.1 Counter Mode ................................................................................................... 636 24.3.2 Real-Time Clock Event/Tamper Detection With Time Stamp............................................. 639 24.4 RTC_C Registers ......................................................................................................... 641 24.4.1 RTCCTL0_L Register .......................................................................................... 644 24.4.2 RTCCTL0_H Register.......................................................................................... 645 24.4.3 RTCCTL1 Register ............................................................................................. 646 24.4.4 RTCCTL3 Register ............................................................................................. 647 24.4.5 RTCOCAL Register ............................................................................................ 647 24.4.6 RTCTCMP Register ............................................................................................ 648 24.4.7 RTCNT1 Register............................................................................................... 649 24.4.8 RTCNT2 Register............................................................................................... 649 24.4.9 RTCNT3 Register............................................................................................... 649 24.4.10 RTCNT4 Register ............................................................................................. 649 24.4.11 RTCSEC Register – Calendar Mode With Hexadecimal Format ....................................... 650 24.4.12 RTCSEC Register – Calendar Mode With BCD Format ................................................. 650 24.4.13 RTCMIN Register – Calendar Mode With Hexadecimal Format........................................ 651 24.4.14 RTCMIN Register – Calendar Mode With BCD Format.................................................. 651 24.4.15 RTCHOUR Register – Calendar Mode With Hexadecimal Format..................................... 652 24.4.16 RTCHOUR Register – Calendar Mode With BCD Format............................................... 652 24.4.17 RTCDOW Register – Calendar Mode ...................................................................... 653 24.4.18 RTCDAY Register – Calendar Mode With Hexadecimal Format ....................................... 653 24.4.19 RTCDAY Register – Calendar Mode With BCD Format ................................................. 653 24.4.20 RTCMON Register – Calendar Mode With Hexadecimal Format ...................................... 654 24.4.21 RTCMON Register – Calendar Mode With BCD Format ................................................ 654 24.4.22 RTCYEAR Register – Calendar Mode With Hexadecimal Format ..................................... 655 24.4.23 RTCYEAR Register – Calendar Mode With BCD Format ............................................... 655 24.4.24 RTCAMIN Register – Calendar Mode With Hexadecimal Format ...................................... 656 24.4.25 RTCAMIN Register – Calendar Mode With BCD Format ................................................ 656 24.4.26 RTCAHOUR Register......................................................................................... 657 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 11 www.ti.com 24.4.27 RTCAHOUR Register – Calendar Mode With BCD Format ............................................. 657 24.4.28 RTCADOW Register – Calendar Mode .................................................................... 658 24.4.29 RTCADAY Register – Calendar Mode With Hexadecimal Format ..................................... 659 24.4.30 RTCADAY Register – Calendar Mode With BCD Format ............................................... 659 24.4.31 RTCPS0CTL Register ........................................................................................ 660 24.4.32 RTCPS1CTL Register ........................................................................................ 661 24.4.33 RTCPS0 Register ............................................................................................. 663 24.4.34 RTCPS1 Register ............................................................................................. 663 24.4.35 RTCIV Register................................................................................................ 664 24.4.36 BIN2BCD Register ............................................................................................ 665 24.4.37 BCD2BIN Register ............................................................................................ 665 24.4.38 RTCSECBAKx Register – Hexadecimal Format .......................................................... 666 24.4.39 RTCSECBAKx Register – BCD Format .................................................................... 666 24.4.40 RTCMINBAKx Register – Hexadecimal Format........................................................... 667 24.4.41 RTCMINBAKx Register – BCD Format .................................................................... 667 24.4.42 RTCHOURBAKx Register – Hexadecimal Format........................................................ 668 24.4.43 RTCHOURBAKx Register – BCD Format ................................................................. 668 24.4.44 RTCDAYBAKx Register – Hexadecimal Format .......................................................... 669 24.4.45 RTCDAYBAKx Register – BCD Format .................................................................... 669 24.4.46 RTCMONBAKx Register – Hexadecimal Format ......................................................... 670 24.4.47 RTCMONBAKx Register – BCD Format ................................................................... 670 24.4.48 RTCYEARBAKx Register – Hexadecimal Format ........................................................ 671 24.4.49 RTCYEARBAKx Register – BCD Format .................................................................. 671 24.4.50 RTCTCCTL0 Register ........................................................................................ 672 24.4.51 RTCTCCTL1 Register ........................................................................................ 672 24.4.52 RTCCAPxCTL Register ...................................................................................... 673 25 32-Bit Hardware Multiplier (MPY32) ..................................................................................... 674 25.1 32-Bit Hardware Multiplier (MPY32) Introduction..................................................................... 675 25.2 MPY32 Operation......................................................................................................... 677 25.2.1 Operand Registers ............................................................................................. 678 25.2.2 Result Registers ................................................................................................ 679 25.2.3 Software Examples ............................................................................................. 680 25.2.4 Fractional Numbers............................................................................................. 681 25.2.5 Putting It All Together .......................................................................................... 684 25.2.6 Indirect Addressing of Result Registers ..................................................................... 687 25.2.7 Using Interrupts ................................................................................................. 687 25.2.8 Using DMA ...................................................................................................... 688 25.3 MPY32 Registers ......................................................................................................... 689 25.3.1 MPY32CTL0 Register .......................................................................................... 691 26 REF................................................................................................................................. 692 26.1 REF Introduction .......................................................................................................... 693 26.2 Principle of Operation .................................................................................................... 696 26.2.1 Low-Power Operation .......................................................................................... 697 26.2.2 REFCTL.......................................................................................................... 697 26.2.3 Reference System Requests.................................................................................. 699 26.3 REF Registers............................................................................................................. 702 26.3.1 REFCTL0 Register (offset = 00h) [reset = 0080h] ......................................................... 703 27 ADC10_A ......................................................................................................................... 705 27.1 ADC10_A Introduction ................................................................................................... 706 27.2 ADC10_A Operation...................................................................................................... 708 27.2.1 10-Bit ADC Core ................................................................................................ 708 27.2.2 ADC10_A Inputs and Multiplexer ............................................................................. 708 27.2.3 Voltage Reference Generator................................................................................. 709 12 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 27.2.4 Auto Power Down .............................................................................................. 709 27.2.5 Sample and Conversion Timing .............................................................................. 709 27.2.6 Conversion Result .............................................................................................. 711 27.2.7 ADC10_A Conversion Modes................................................................................. 711 27.2.8 Window Comparator ........................................................................................... 716 27.2.9 Using the Integrated Temperature Sensor .................................................................. 717 27.2.10 ADC10_A Grounding and Noise Considerations ......................................................... 718 27.2.11 ADC10_A Interrupts .......................................................................................... 718 27.3 ADC10_A Registers ...................................................................................................... 720 27.3.1 ADC10CTL0 Register .......................................................................................... 721 27.3.2 ADC10CTL1 Register .......................................................................................... 722 27.3.3 ADC10CTL2 Register .......................................................................................... 724 27.3.4 ADC10MEM0 Register......................................................................................... 725 27.3.5 ADC10MEM0 Register, Twos-Complement Format ....................................................... 725 27.3.6 ADC10MCTL0 Register........................................................................................ 726 27.3.7 ADC10HI Register .............................................................................................. 727 27.3.8 ADC10HI Register, Twos-Complement Format ............................................................ 727 27.3.9 ADC10LO Register ............................................................................................. 728 27.3.10 ADC10LO Register, Twos-Complement Format .......................................................... 728 27.3.11 ADC10IE Register............................................................................................. 729 27.3.12 ADC10IFG Register........................................................................................... 730 27.3.13 ADC10IV Register............................................................................................. 731 28 ADC12_A ......................................................................................................................... 732 28.1 ADC12_A Introduction ................................................................................................... 733 28.2 ADC12_A Operation...................................................................................................... 736 28.2.1 12-Bit ADC Core ................................................................................................ 736 28.2.2 ADC12_A Inputs and Multiplexer ............................................................................. 736 28.2.3 Voltage Reference Generator................................................................................. 737 28.2.4 Auto Power Down .............................................................................................. 738 28.2.5 Sample and Conversion Timing .............................................................................. 738 28.2.6 Conversion Memory ............................................................................................ 740 28.2.7 ADC12_A Conversion Modes................................................................................. 740 28.2.8 Using the Integrated Temperature Sensor .................................................................. 746 28.2.9 ADC12_A Grounding and Noise Considerations ........................................................... 747 28.2.10 ADC12_A Interrupts .......................................................................................... 748 28.3 ADC12_A Registers ...................................................................................................... 750 28.3.1 ADC12CTL0 Register .......................................................................................... 752 28.3.2 ADC12CTL1 Register .......................................................................................... 754 28.3.3 ADC12CTL2 Register .......................................................................................... 755 28.3.4 ADC12MEMx Register ......................................................................................... 756 28.3.5 ADC12MCTLx Register ........................................................................................ 757 28.3.6 ADC12IE Register .............................................................................................. 758 28.3.7 ADC12IFG Register ............................................................................................ 760 28.3.8 ADC12IV Register .............................................................................................. 762 29 SD24_B ........................................................................................................................... 763 29.1 SD24_B Introduction ..................................................................................................... 764 29.2 SD24_B Operation........................................................................................................ 768 29.2.1 Principle of Operation .......................................................................................... 768 29.2.2 ADC Core........................................................................................................ 769 29.2.3 Voltage Reference.............................................................................................. 769 29.2.4 Modulator Clock................................................................................................. 769 29.2.5 Auto Power-Down .............................................................................................. 769 29.2.6 Analog Inputs.................................................................................................... 769 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 13 www.ti.com 29.2.7 Digital Filter ..................................................................................................... 770 29.2.8 Bitstream Input and Output.................................................................................... 774 29.2.9 Conversion Modes.............................................................................................. 774 29.2.10 Conversion Operation Using Preload....................................................................... 776 29.2.11 Grounding and Noise Considerations ...................................................................... 777 29.2.12 Trigger Generator ............................................................................................. 778 29.2.13 SD24_B Interrupts ............................................................................................ 779 29.2.14 Using SD24_B With DMA .................................................................................... 779 29.3 SD24_B Registers ........................................................................................................ 780 29.3.1 SD24BCTL0 Register .......................................................................................... 782 29.3.2 SD24BCTL1 Register .......................................................................................... 783 29.3.3 SD24BTRGCTL Register ...................................................................................... 784 29.3.4 SD24BIFG Register ............................................................................................ 785 29.3.5 SD24BIE Register .............................................................................................. 788 29.3.6 SD24BIV Register .............................................................................................. 790 29.3.7 SD24BCCTLx Register ........................................................................................ 791 29.3.8 SD24BINCTLx Register........................................................................................ 793 29.3.9 SD24BOSRx Register.......................................................................................... 794 29.3.10 SD24BTRGOSR Register.................................................................................... 794 29.3.11 SD24BPREx Register ........................................................................................ 795 29.3.12 SD24BTRGPRE Register .................................................................................... 795 29.3.13 SD24BMEMLx Register ...................................................................................... 796 29.3.14 SD24BMEMHx Register...................................................................................... 796 30 CTSD16 ........................................................................................................................... 797 30.1 CTSD16 Introduction ..................................................................................................... 798 30.2 CTSD16 Operation ....................................................................................................... 800 30.2.1 Principle of Operation .......................................................................................... 800 30.2.2 ADC Core........................................................................................................ 801 30.2.3 Voltage Reference.............................................................................................. 801 30.2.4 CTSD16 Clock .................................................................................................. 801 30.2.5 Auto Power-Down .............................................................................................. 802 30.2.6 Analog Inputs.................................................................................................... 802 30.2.7 Digital Filter ...................................................................................................... 803 30.2.8 Conversion Memory Registers: CTSD16MEMx ............................................................ 806 30.2.9 Conversion Modes.............................................................................................. 807 30.2.10 Conversion Operation Using Preload....................................................................... 809 30.2.11 Using the Integrated Temperature Sensor................................................................. 810 30.2.12 Using the Integrated AVCC Sense.......................................................................... 811 30.2.13 Grounding and Noise Considerations ...................................................................... 811 30.2.14 Interrupt Handling ............................................................................................. 811 30.3 CTSD16 Registers........................................................................................................ 813 30.3.1 CTSD16CTL Register .......................................................................................... 814 30.3.2 CTSD16CCTL0 to CTSD16CCTL6 Register................................................................ 815 30.3.3 CTSD16MEM0 to CTSD16MEM6 Register ................................................................. 816 30.3.4 CTSD16INCTL0 to CTSD16INCTL6 Register .............................................................. 817 30.3.5 CTSD16PRE0 to CTSD16PRE6 Register................................................................... 818 30.3.6 CTSD16IFG Register .......................................................................................... 819 30.3.7 CTSD16IE Register ............................................................................................ 821 30.3.8 CTSD16IV Register ............................................................................................ 823 31 DAC12_A ......................................................................................................................... 824 31.1 DAC12_A Introduction ................................................................................................... 825 31.2 DAC12_A Operation...................................................................................................... 828 31.2.1 DAC12_A Core.................................................................................................. 828 14 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 31.2.2 DAC12_A Port Selection....................................................................................... 828 31.2.3 DAC12_A Reference ........................................................................................... 828 31.2.4 Updating the DAC12_A Voltage Output ..................................................................... 829 31.2.5 DAC12_xDAT Data Formats .................................................................................. 829 31.2.6 DAC12_A Output Amplifier Offset Calibration .............................................................. 830 31.2.7 Grouping Multiple DAC12_A Modules ....................................................................... 831 31.2.8 DAC12_A Interrupts ............................................................................................ 832 31.3 DAC Outputs .............................................................................................................. 833 31.4 DAC12_A Registers ...................................................................................................... 834 31.4.1 DAC12_xCTL0 Register ....................................................................................... 835 31.4.2 DAC12_xCTL1 Register ....................................................................................... 837 31.4.3 DAC12_xDAT Register, Unsigned 12-Bit Binary Format, Right Justified ............................... 838 31.4.4 DAC12_xDAT Register, Unsigned 12-Bit Binary Format, Left Justified ................................. 838 31.4.5 DAC12_xDAT Register, Twos-Complement 12-Bit Binary Format, Right Justified .................... 839 31.4.6 DAC12_xDAT Register, Twos-Complement 12-Bit Binary Format, Left Justified...................... 839 31.4.7 DAC12_xDAT Register, Unsigned 8-Bit Binary Format, Right Justified................................. 840 31.4.8 DAC12_xDAT Register, Unsigned 8-Bit Binary Format, Left Justified................................... 840 31.4.9 DAC12_xDAT Register, Twos-Complement 8-Bit Binary Format, Right Justified ..................... 841 31.4.10 DAC12_xDAT Register, Twos-Complement 8-Bit Binary Format, Left Justified...................... 841 31.4.11 DAC12_xCALCTL Register .................................................................................. 842 31.4.12 DAC12_xCALDAT Register.................................................................................. 842 31.4.13 DAC12IV Register............................................................................................. 843 32 Comp_B .......................................................................................................................... 844 32.1 Comp_B Introduction ..................................................................................................... 845 32.2 Comp_B Operation ....................................................................................................... 846 32.2.1 Comparator ...................................................................................................... 846 32.2.2 Analog Input Switches ......................................................................................... 846 32.2.3 Port Logic ........................................................................................................ 846 32.2.4 Input Short Switch .............................................................................................. 846 32.2.5 Output Filter ..................................................................................................... 847 32.2.6 Reference Voltage Generator................................................................................. 848 32.2.7 Comp_B, Port Disable Register CBCTL3 ................................................................... 849 32.2.8 Comp_B Interrupts ............................................................................................. 849 32.2.9 Comp_B Used to Measure Resistive Elements ............................................................ 849 32.3 Comp_B Registers........................................................................................................ 852 32.3.1 CBCTL0 Register ............................................................................................... 853 32.3.2 CBCTL1 Register ............................................................................................... 854 32.3.3 CBCTL2 Register ............................................................................................... 855 32.3.4 CBCTL3 Register ............................................................................................... 856 32.3.5 CBINT Register ................................................................................................. 858 32.3.6 CBIV Register ................................................................................................... 859 33 Operational Amplifier (OA)................................................................................................. 860 33.1 OA Introduction ........................................................................................................... 861 33.2 OA Operation.............................................................................................................. 863 33.2.1 OA Modes ....................................................................................................... 863 33.2.2 Rail-to-Rail Input Modes ....................................................................................... 863 33.2.3 OA Inputs ........................................................................................................ 863 33.3 Ground Switches.......................................................................................................... 864 33.4 OA and Power Modes.................................................................................................... 864 33.5 OA Registers .............................................................................................................. 865 33.5.1 OAnCTL0 Register ............................................................................................. 866 33.5.2 OAnPSW Register.............................................................................................. 867 33.5.3 OAnNSW Register.............................................................................................. 868 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 15 www.ti.com 33.5.4 OAnGSW Register ............................................................................................. 869 34 LCD_B Controller.............................................................................................................. 870 34.1 LCD_B Controller Introduction .......................................................................................... 871 34.2 LCD_B Controller Operation ............................................................................................ 873 34.2.1 LCD Memory .................................................................................................... 873 34.2.2 LCD Timing Generation........................................................................................ 873 34.2.3 Blanking the LCD ............................................................................................... 874 34.2.4 LCD Blinking..................................................................................................... 874 34.2.5 LCD_B Voltage And Bias Generation........................................................................ 875 34.2.6 LCD Outputs..................................................................................................... 877 34.2.7 LCD_B Interrupts ............................................................................................... 877 34.2.8 Static Mode ...................................................................................................... 879 34.2.9 2-Mux Mode ..................................................................................................... 882 34.2.10 3-Mux Mode.................................................................................................... 885 34.2.11 4-Mux Mode.................................................................................................... 888 34.3 LCD_B Registers ......................................................................................................... 891 34.3.1 LCDBCTL0 Register............................................................................................ 894 34.3.2 LCDBCTL1 Register............................................................................................ 895 34.3.3 LCDBBLKCTL Register ........................................................................................ 896 34.3.4 LCDBMEMCTL Register....................................................................................... 897 34.3.5 LCDBVCTL Register ........................................................................................... 898 34.3.6 LCDBPCTL0 Register.......................................................................................... 900 34.3.7 LCDBPCTL1 Register.......................................................................................... 900 34.3.8 LCDBPCTL2 Register.......................................................................................... 901 34.3.9 LCDBPCTL3 Register.......................................................................................... 901 34.3.10 LCDBCPCTL Register........................................................................................ 902 34.3.11 LCDBIV Register .............................................................................................. 903 35 LCD_C Controller.............................................................................................................. 904 35.1 LCD_C Introduction....................................................................................................... 905 35.2 LCD_C Operation......................................................................................................... 907 35.2.1 LCD Memory .................................................................................................... 907 35.2.2 LCD Timing Generation........................................................................................ 908 35.2.3 Blanking the LCD ............................................................................................... 909 35.2.4 LCD Blinking..................................................................................................... 909 35.2.5 LCD Voltage And Bias Generation ........................................................................... 910 35.2.6 LCD Outputs..................................................................................................... 913 35.2.7 LCD Interrupts................................................................................................... 914 35.2.8 Static Mode ...................................................................................................... 916 35.2.9 2-Mux Mode ..................................................................................................... 917 35.2.10 3-Mux Mode.................................................................................................... 918 35.2.11 4-Mux Mode.................................................................................................... 919 35.2.12 6-Mux Mode.................................................................................................... 920 35.2.13 8-Mux Mode.................................................................................................... 921 35.3 LCD_C Registers ......................................................................................................... 923 35.3.1 LCDCCTL0 Register ........................................................................................... 928 35.3.2 LCDCCTL1 Register ........................................................................................... 930 35.3.3 LCDCBLKCTL Register........................................................................................ 931 35.3.4 LCDCMEMCTL Register....................................................................................... 932 35.3.5 LCDCVCTL Register ........................................................................................... 933 35.3.6 LCDCPCTL0 Register.......................................................................................... 935 35.3.7 LCDCPCTL1 Register.......................................................................................... 935 35.3.8 LCDCPCTL2 Register.......................................................................................... 936 35.3.9 LCDCPCTL3 Register.......................................................................................... 936 16 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 35.3.10 LCDCCPCTL Register........................................................................................ 937 35.3.11 LCDCIV Register .............................................................................................. 937 36 Universal Serial Communication Interface – UART Mode....................................................... 938 36.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 939 36.2 USCI Introduction – UART Mode ....................................................................................... 940 36.3 USCI Operation – UART Mode ......................................................................................... 942 36.3.1 USCI Initialization and Reset.................................................................................. 942 36.3.2 Character Format ............................................................................................... 942 36.3.3 Asynchronous Communication Format ...................................................................... 942 36.3.4 Automatic Baud-Rate Detection .............................................................................. 945 36.3.5 IrDA Encoding and Decoding ................................................................................. 946 36.3.6 Automatic Error Detection ..................................................................................... 947 36.3.7 USCI Receive Enable .......................................................................................... 948 36.3.8 USCI Transmit Enable ......................................................................................... 948 36.3.9 UART Baud-Rate Generation ................................................................................. 949 36.3.10 Setting a Baud Rate .......................................................................................... 951 36.3.11 Transmit Bit Timing ........................................................................................... 951 36.3.12 Receive Bit Timing ............................................................................................ 952 36.3.13 Typical Baud Rates and Errors.............................................................................. 953 36.3.14 Using the USCI Module in UART Mode With Low-Power Modes ...................................... 956 36.3.15 USCI Interrupts in UART Mode ............................................................................. 956 36.3.16 DMA Operation ................................................................................................ 957 36.4 USCI_A UART Mode Registers......................................................................................... 958 36.4.1 UCAxCTL0 Register............................................................................................ 959 36.4.2 UCAxCTL1 Register............................................................................................ 960 36.4.3 UCAxBR0 Register ............................................................................................. 961 36.4.4 UCAxBR1 Register ............................................................................................. 961 36.4.5 UCAxMCTL Register ........................................................................................... 961 36.4.6 UCAxSTAT Register ........................................................................................... 962 36.4.7 UCAxRXBUF Register ......................................................................................... 963 36.4.8 UCAxTXBUF Register ......................................................................................... 963 36.4.9 UCAxIRTCTL Register......................................................................................... 964 36.4.10 UCAxIRRCTL Register ....................................................................................... 964 36.4.11 UCAxABCTL Register ........................................................................................ 965 36.4.12 UCAxIE Register .............................................................................................. 966 36.4.13 UCAxIFG Register ............................................................................................ 966 36.4.14 UCAxIV Register .............................................................................................. 967 37 Universal Serial Communication Interface – SPI Mode .......................................................... 968 37.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 969 37.2 USCI Introduction – SPI Mode .......................................................................................... 970 37.3 USCI Operation – SPI Mode ............................................................................................ 972 37.3.1 USCI Initialization and Reset.................................................................................. 972 37.3.2 Character Format ............................................................................................... 972 37.3.3 Master Mode .................................................................................................... 973 37.3.4 Slave Mode ...................................................................................................... 974 37.3.5 SPI Enable....................................................................................................... 975 37.3.6 Serial Clock Control ............................................................................................ 975 37.3.7 Using the SPI Mode With Low-Power Modes............................................................... 976 37.3.8 USCI Interrupts in SPI Mode .................................................................................. 977 37.4 USCI_A SPI Mode Registers............................................................................................ 978 37.4.1 UCAxCTL0 Register............................................................................................ 979 37.4.2 UCAxCTL1 Register............................................................................................ 980 37.4.3 UCAxBR0 Register ............................................................................................. 981 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 17 www.ti.com 37.4.4 UCAxBR1 Register ............................................................................................. 981 37.4.5 UCAxMCTL Register ........................................................................................... 981 37.4.6 UCAxSTAT Register ........................................................................................... 982 37.4.7 UCAxRXBUF Register ......................................................................................... 983 37.4.8 UCAxTXBUF Register ......................................................................................... 983 37.4.9 UCAxIE Register................................................................................................ 984 37.4.10 UCAxIFG Register ............................................................................................ 984 37.4.11 UCAxIV Register .............................................................................................. 985 37.5 USCI_B SPI Mode Registers............................................................................................ 986 37.5.1 UCBxCTL0 Register............................................................................................ 987 37.5.2 UCBxCTL1 Register............................................................................................ 988 37.5.3 UCBxBR0 Register ............................................................................................. 989 37.5.4 UCBxBR1 Register ............................................................................................. 989 37.5.5 UCBxMCTL Register ........................................................................................... 989 37.5.6 UCBxSTAT Register ........................................................................................... 990 37.5.7 UCBxRXBUF Register ......................................................................................... 991 37.5.8 UCBxTXBUF Register ......................................................................................... 991 37.5.9 UCBxIE Register................................................................................................ 992 37.5.10 UCBxIFG Register ............................................................................................ 992 37.5.11 UCBxIV Register .............................................................................................. 993 38 Universal Serial Communication Interface – I2C Mode ........................................................... 994 38.1 Universal Serial Communication Interface (USCI) Overview ....................................................... 995 38.2 USCI Introduction – I2C Mode........................................................................................... 996 38.3 USCI Operation – I2C Mode ............................................................................................. 997 38.3.1 USCI Initialization and Reset.................................................................................. 998 38.3.2 I2C Serial Data .................................................................................................. 998 38.3.3 I2C Addressing Modes ........................................................................................ 1000 38.3.4 I2C Module Operating Modes ................................................................................ 1001 38.3.5 I2C Clock Generation and Synchronization ................................................................ 1012 38.3.6 Using the USCI Module in I2C Mode With Low-Power Modes .......................................... 1013 38.3.7 USCI Interrupts in I2C Mode ................................................................................. 1013 38.4 USCI_B I2C Mode Registers .......................................................................................... 1016 38.4.1 UCBxCTL0 Register .......................................................................................... 1017 38.4.2 UCBxCTL1 Register .......................................................................................... 1018 38.4.3 UCBxBR0 Register............................................................................................ 1019 38.4.4 UCBxBR1 Register............................................................................................ 1019 38.4.5 UCBxSTAT Register .......................................................................................... 1020 38.4.6 UCBxRXBUF Register........................................................................................ 1021 38.4.7 UCBxTXBUF Register ........................................................................................ 1021 38.4.8 UCBxI2COA Register......................................................................................... 1022 38.4.9 UCBxI2CSA Register ......................................................................................... 1022 38.4.10 UCBxIE Register............................................................................................. 1023 38.4.11 UCBxIFG Register........................................................................................... 1024 38.4.12 UCBxIV Register............................................................................................. 1025 39 Enhanced Universal Serial Communication Interface (eUSCI) – UART Mode .......................... 1026 39.1 Enhanced Universal Serial Communication Interface A (eUSCI_A) Overview ................................. 1027 39.2 eUSCI_A Introduction – UART Mode................................................................................. 1027 39.3 eUSCI_A Operation – UART Mode................................................................................... 1029 39.3.1 eUSCI_A Initialization and Reset ........................................................................... 1029 39.3.2 Character Format ............................................................................................. 1029 39.3.3 Asynchronous Communication Format..................................................................... 1029 39.3.4 Automatic Baud-Rate Detection............................................................................. 1032 39.3.5 IrDA Encoding and Decoding................................................................................ 1033 18 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 39.3.6 Automatic Error Detection.................................................................................... 1034 39.3.7 eUSCI_A Receive Enable.................................................................................... 1035 39.3.8 eUSCI_A Transmit Enable ................................................................................... 1035 39.3.9 UART Baud-Rate Generation ............................................................................... 1036 39.3.10 Setting a Baud Rate ......................................................................................... 1038 39.3.11 Transmit Bit Timing - Error calculation.................................................................... 1039 39.3.12 Receive Bit Timing – Error Calculation ................................................................... 1039 39.3.13 Typical Baud Rates and Errors ............................................................................ 1040 39.3.14 Using the eUSCI_A Module in UART Mode With Low-Power Modes ................................ 1042 39.3.15 eUSCI_A Interrupts in UART Mode ....................................................................... 1042 39.3.16 DMA Operation............................................................................................... 1044 39.4 eUSCI_A UART Registers ............................................................................................. 1045 39.4.1 UCAxCTLW0 Register........................................................................................ 1046 39.4.2 UCAxCTLW1 Register........................................................................................ 1047 39.4.3 UCAxBRW Register........................................................................................... 1048 39.4.4 UCAxMCTLW Register ....................................................................................... 1048 39.4.5 UCAxSTATW Register ....................................................................................... 1049 39.4.6 UCAxRXBUF Register........................................................................................ 1050 39.4.7 UCAxTXBUF Register ........................................................................................ 1050 39.4.8 UCAxABCTL Register ........................................................................................ 1051 39.4.9 UCAxIRCTL Register ......................................................................................... 1052 39.4.10 UCAxIE Register............................................................................................. 1053 39.4.11 UCAxIFG Register........................................................................................... 1054 39.4.12 UCAxIV Register............................................................................................. 1055 40 Enhanced Universal Serial Communication Interface (eUSCI) – SPI Mode.............................. 1056 40.1 Enhanced Universal Serial Communication Interfaces (eUSCI_A, eUSCI_B) Overview ...................... 1057 40.2 eUSCI Introduction – SPI Mode ....................................................................................... 1057 40.3 eUSCI Operation – SPI Mode ......................................................................................... 1059 40.3.1 eUSCI Initialization and Reset............................................................................... 1059 40.3.2 Character Format ............................................................................................. 1060 40.3.3 Master Mode ................................................................................................... 1060 40.3.4 Slave Mode .................................................................................................... 1061 40.3.5 SPI Enable ..................................................................................................... 1062 40.3.6 Serial Clock Control........................................................................................... 1062 40.3.7 Using the SPI Mode With Low-Power Modes ............................................................. 1063 40.3.8 eUSCI Interrupts in SPI Mode ............................................................................... 1063 40.4 eUSCI_A SPI Registers ................................................................................................ 1065 40.4.1 UCAxCTLW0 Register........................................................................................ 1066 40.4.2 UCAxBRW Register........................................................................................... 1067 40.4.3 UCAxSTATW Register ....................................................................................... 1068 40.4.4 UCAxRXBUF Register........................................................................................ 1069 40.4.5 UCAxTXBUF Register ........................................................................................ 1070 40.4.6 UCAxIE Register .............................................................................................. 1071 40.4.7 UCAxIFG Register ............................................................................................ 1072 40.4.8 UCAxIV Register .............................................................................................. 1073 40.5 eUSCI_B SPI Registers ................................................................................................ 1074 40.5.1 UCBxCTLW0 Register........................................................................................ 1075 40.5.2 UCBxBRW Register........................................................................................... 1076 40.5.3 UCBxSTATW Register ....................................................................................... 1076 40.5.4 UCBxRXBUF Register........................................................................................ 1077 40.5.5 UCBxTXBUF Register ........................................................................................ 1077 40.5.6 UCBxIE Register ............................................................................................. 1078 40.5.7 UCBxIFG Register ............................................................................................ 1078 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 19 www.ti.com 40.5.8 UCBxIV Register .............................................................................................. 1079 41 Enhanced Universal Serial Communication Interface (eUSCI) – I2C Mode .............................. 1080 41.0.9 I2C Quick Setup................................................................................................ 1085 41.0.10 Glitch Filtering ................................................................................................ 1096 41.0.11 Byte Counter ................................................................................................. 1097 41.0.12 Multiple Slave Addresses................................................................................... 1098 41.1 eUSCI_B I2C Registers ................................................................................................ 1102 41.1.1 UCBxCTLW0 Register........................................................................................ 1103 41.1.2 UCBxCTLW1 Register........................................................................................ 1105 41.1.3 UCBxBRW Register........................................................................................... 1107 41.1.4 UCBxSTATW .................................................................................................. 1107 41.1.5 UCBxTBCNT Register........................................................................................ 1108 41.1.6 UCBxRXBUF Register........................................................................................ 1109 41.1.7 UCBxTXBUF................................................................................................... 1109 41.1.8 UCBxI2COA0 Register ....................................................................................... 1110 41.1.9 UCBxI2COA1 Register ....................................................................................... 1111 41.1.10 UCBxI2COA2 Register...................................................................................... 1111 41.1.11 UCBxI2COA3 Register...................................................................................... 1112 41.1.12 UCBxADDRX Register...................................................................................... 1112 41.1.13 UCBxADDMASK Register .................................................................................. 1113 41.1.14 UCBxI2CSA Register ....................................................................................... 1113 41.1.15 UCBxIE Register............................................................................................. 1114 41.1.16 UCBxIFG Register........................................................................................... 1116 41.1.17 UCBxIV Register............................................................................................. 1118 42 USB Module ................................................................................................................... 1119 42.1 USB Introduction ........................................................................................................ 1120 42.2 USB Operation........................................................................................................... 1122 42.2.1 USB Transceiver (PHY) ...................................................................................... 1122 42.2.2 USB Power System ........................................................................................... 1123 42.2.3 USB Phase-Locked Loop (PLL) ............................................................................. 1126 42.2.4 USB Controller Engine ....................................................................................... 1128 42.2.5 USB Vector Interrupts ........................................................................................ 1132 42.2.6 Power Consumption .......................................................................................... 1132 42.2.7 Suspend and Resume ....................................................................................... 1133 42.3 USB Transfers ........................................................................................................... 1133 42.3.1 Control Transfers.............................................................................................. 1133 42.3.2 Interrupt Transfers ............................................................................................ 1137 42.3.3 Bulk Transfers ................................................................................................. 1138 42.4 USB Registers ........................................................................................................... 1140 42.4.1 USB Configuration Registers ................................................................................ 1140 42.4.2 USB Control Registers ....................................................................................... 1148 42.4.3 USB Buffer Registers and Memory ......................................................................... 1165 43 LDO-PWR Module ........................................................................................................... 1176 43.1 LDO-PWR Introduction ................................................................................................. 1177 43.2 LDO-PWR Operation ................................................................................................... 1178 43.2.1 Enabling/Disabling ............................................................................................ 1178 43.2.2 Powering the Rest of the MSP430 from the LDO-PWR ................................................. 1178 43.2.3 Powering Other Components in the System from LDO-PWR........................................... 1179 43.2.4 Applications That Do Not Require LDO-PWR ............................................................. 1179 43.2.5 Current Limitation and Overload Protection ............................................................... 1179 43.2.6 LDO-PWR Interrupts.......................................................................................... 1180 43.2.7 Port U Control ................................................................................................. 1180 43.3 LDO-PWR Registers.................................................................................................... 1181 20 Contents SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 43.3.1 LDOKEYPID Register ........................................................................................ 1182 43.3.2 PUCTL Register ............................................................................................... 1182 43.3.3 LDOPWRCTL Register ....................................................................................... 1183 44 Embedded Emulation Module (EEM).................................................................................. 1184 44.1 Embedded Emulation Module (EEM) Introduction .................................................................. 1185 44.2 EEM Building Blocks.................................................................................................... 1187 44.2.1 Triggers......................................................................................................... 1187 44.2.2 Trigger Sequencer ............................................................................................ 1187 44.2.3 State Storage (Internal Trace Buffer)....................................................................... 1187 44.2.4 Cycle Counter.................................................................................................. 1187 44.2.5 Clock Control .................................................................................................. 1187 44.3 EEM Configurations..................................................................................................... 1188 Revision History ...................................................................................................................... 1189 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Contents 21 www.ti.com List of Figures 1-1. BOR/POR/PUC Reset Circuit............................................................................................. 56 1-2. Interrupt Priority............................................................................................................. 58 1-3. NMIs With Reentrance Protection........................................................................................ 59 1-4. Interrupt Processing........................................................................................................ 60 1-5. Return From Interrupt...................................................................................................... 61 1-6. Operation Modes ........................................................................................................... 64 1-7. Devices Descriptor Table.................................................................................................. 74 1-8. SFRIE1 Register ........................................................................................................... 84 1-9. SFRIFG1 Register.......................................................................................................... 85 1-10. SFRRPCR Register ........................................................................................................ 87 1-11. SYSCTL Register .......................................................................................................... 89 1-12. SYSBSLC Register ........................................................................................................ 90 1-13. SYSJMBC Register ........................................................................................................ 91 1-14. SYSJMBI0 Register ........................................................................................................ 92 1-15. SYSJMBI1 Register ........................................................................................................ 92 1-16. SYSJMBO0 Register....................................................................................................... 93 1-17. SYSJMBO1 Register....................................................................................................... 93 1-18. SYSUNIV Register ......................................................................................................... 94 1-19. SYSSNIV Register ......................................................................................................... 95 1-20. SYSRSTIV Register........................................................................................................ 96 1-21. SYSBERRIV Register ..................................................................................................... 97 2-1. System Frequency, Supply Voltage, and Core Voltage – See Device-Specific Data Sheet ..................... 99 2-2. PMM Block Diagram...................................................................................................... 100 2-3. Available SVMH Settings Versus VCORE Settings ................................................................... 103 2-4. High-Side and Low-Side Voltage Failure and Resulting PMM Actions ............................................ 104 2-5. High-Side SVS and SVM ................................................................................................ 105 2-6. Low-Side SVS and SVM................................................................................................. 106 2-7. PMM Action at Device Power-Up....................................................................................... 107 2-8. Changing VCORE and SVML and SVSL Levels .......................................................................... 108 2-9. PMMCTL0 Register....................................................................................................... 115 2-10. PMMCTL1 Register....................................................................................................... 116 2-11. SVSMHCTL Register..................................................................................................... 117 2-12. SVSMLCTL Register ..................................................................................................... 118 2-13. SVSMIO Register ......................................................................................................... 119 2-14. PMMIFG Register......................................................................................................... 120 2-15. PMMRIE Register......................................................................................................... 122 2-16. PM5CTL0 Register ....................................................................................................... 123 3-1. Battery Backup Switch Overview ....................................................................................... 126 3-2. Charger Block Diagram .................................................................................................. 128 3-3. BAKCTL Register ......................................................................................................... 130 3-4. BAKCHCTL Register ..................................................................................................... 131 4-1. Auxiliary Supply Switch Overview ...................................................................................... 134 4-2. System Frequency vs Supply Voltage ................................................................................. 138 4-3. Available SVMH Settings vs VCORE Settings ............................................................................ 138 4-4. Available AUXxLVL Settings vs SVMH Settings ...................................................................... 139 4-5. Auxiliary Supply Monitor Block Diagram............................................................................... 140 4-6. I/Os Powered by Auxiliary Supplies .................................................................................... 142 22 List of Figures SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4-7. AUX Connection to ADC................................................................................................. 142 4-8. Charger Block Diagram .................................................................................................. 143 4-9. Software Flow Chart...................................................................................................... 145 4-10. AUXCTL0 Register ....................................................................................................... 149 4-11. AUXCTL1 Register ....................................................................................................... 150 4-12. AUXCTL2 Register ....................................................................................................... 151 4-13. AUX2CHCTL Register ................................................................................................... 152 4-14. AUX3CHCTL Register ................................................................................................... 153 4-15. AUXADCCTL Register ................................................................................................... 154 4-16. AUXIFG Register ......................................................................................................... 155 4-17. AUXIE Register ........................................................................................................... 156 4-18. AUXIV Register ........................................................................................................... 157 5-1. UCS Block Diagram ..................................................................................................... 160 5-2. Modulator Patterns ....................................................................................................... 166 5-3. Module Request Clock System ......................................................................................... 167 5-4. Oscillator Fault Logic ..................................................................................................... 170 5-5. Switch MCLK from DCOCLK to XT1CLK.............................................................................. 172 5-6. UCSCTL0 Register ....................................................................................................... 174 5-7. UCSCTL1 Register ....................................................................................................... 175 5-8. UCSCTL2 Register ....................................................................................................... 176 5-9. UCSCTL3 Register ....................................................................................................... 177 5-10. UCSCTL4 Register ....................................................................................................... 178 5-11. UCSCTL5 Register ....................................................................................................... 179 5-12. UCSCTL6 Register ....................................................................................................... 181 5-13. UCSCTL7 Register ....................................................................................................... 183 5-14. UCSCTL8 Register ....................................................................................................... 184 5-15. UCSCTL9 Register ....................................................................................................... 185 6-1. MSP430X CPU Block Diagram ......................................................................................... 188 6-2. PC Storage on the Stack for Interrupts ................................................................................ 189 6-3. Program Counter.......................................................................................................... 190 6-4. PC Storage on the Stack for CALLA ................................................................................... 190 6-5. Stack Pointer .............................................................................................................. 191 6-6. Stack Usage ............................................................................................................... 191 6-7. PUSHX.A Format on the Stack ......................................................................................... 191 6-8. PUSH SP, POP SP Sequence.......................................................................................... 191 6-9. SR Bits ..................................................................................................................... 192 6-10. Register-Byte and Byte-Register Operation........................................................................... 194 6-11. Register-Word Operation ................................................................................................ 194 6-12. Word-Register Operation ................................................................................................ 195 6-13. Register – Address-Word Operation ................................................................................... 195 6-14. Address-Word – Register Operation ................................................................................... 196 6-15. Indexed Mode in Lower 64KB........................................................................................... 198 6-16. Indexed Mode in Upper Memory ....................................................................................... 199 6-17. Overflow and Underflow for Indexed Mode ........................................................................... 200 6-18. Example for Indexed Mode.............................................................................................. 201 6-19. Symbolic Mode Running in Lower 64KB .............................................................................. 203 6-20. Symbolic Mode Running in Upper Memory ........................................................................... 204 6-21. Overflow and Underflow for Symbolic Mode .......................................................................... 205 6-22. MSP430 Double-Operand Instruction Format......................................................................... 213 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Figures 23 www.ti.com 6-23. MSP430 Single-Operand Instructions.................................................................................. 214 6-24. Format of Conditional Jump Instructions .............................................................................. 215 6-25. Extension Word for Register Modes ................................................................................... 218 6-26. Extension Word for Non-Register Modes.............................................................................. 218 6-27. Example for Extended Register or Register Instruction ............................................................. 219 6-28. Example for Extended Immediate or Indexed Instruction ........................................................... 220 6-29. Extended Format I Instruction Formats ................................................................................ 221 6-30. 20-Bit Addresses in Memory ............................................................................................ 221 6-31. Extended Format II Instruction Format................................................................................. 222 6-32. PUSHM and POPM Instruction Format................................................................................ 223 6-33. RRCM, RRAM, RRUM, and RLAM Instruction Format .............................................................. 223 6-34. BRA Instruction Format .................................................................................................. 223 6-35. CALLA Instruction Format ............................................................................................... 223 6-36. Decrement Overlap....................................................................................................... 249 6-37. Stack After a RET Instruction ........................................................................................... 268 6-38. Destination Operand—Arithmetic Shift Left ........................................................................... 270 6-39. Destination Operand—Carry Left Shift................................................................................. 271 6-40. Rotate Right Arithmetically RRA.B and RRA.W ...................................................................... 272 6-41. Rotate Right Through Carry RRC.B and RRC.W .................................................................... 273 6-42. Swap Bytes in Memory................................................................................................... 280 6-43. Swap Bytes in a Register ................................................................................................ 280 6-44. Rotate Left Arithmetically—RLAM[.W] and RLAM.A ................................................................. 307 6-45. Destination Operand-Arithmetic Shift Left ............................................................................. 308 6-46. Destination Operand-Carry Left Shift .................................................................................. 309 6-47. Rotate Right Arithmetically RRAM[.W] and RRAM.A ................................................................ 310 6-48. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode.......................................................... 312 6-49. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode .................................................... 312 6-50. Rotate Right Through Carry RRCM[.W] and RRCM.A .............................................................. 314 6-51. Rotate Right Through Carry RRCX(.B,.A) – Register Mode ........................................................ 316 6-52. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode .................................................. 316 6-53. Rotate Right Unsigned RRUM[.W] and RRUM.A..................................................................... 317 6-54. Rotate Right Unsigned RRUX(.B,.A) – Register Mode .............................................................. 318 6-55. Swap Bytes SWPBX.A Register Mode ................................................................................ 322 6-56. Swap Bytes SWPBX.A In Memory ..................................................................................... 322 6-57. Swap Bytes SWPBX[.W] Register Mode .............................................................................. 323 6-58. Swap Bytes SWPBX[.W] In Memory ................................................................................... 323 6-59. Sign Extend SXTX.A ..................................................................................................... 324 6-60. Sign Extend SXTX[.W] ................................................................................................... 324 7-1. Flash Memory Module Block Diagram ................................................................................. 343 7-2. 256KB of Flash Memory Segments Example ......................................................................... 344 7-3. Erase Cycle Timing....................................................................................................... 347 7-4. Erase Cycle From Flash ................................................................................................. 348 7-5. Erase Cycle From RAM.................................................................................................. 349 7-6. Byte, Word, and Long-Word Write Timing............................................................................. 350 7-7. Initiating a Byte or Word Write From Flash............................................................................ 351 7-8. Initiating a Byte or Word Write From RAM ............................................................................ 352 7-9. Initiating Long-Word Write From Flash ................................................................................ 353 7-10. Initiating Long-Word Write from RAM .................................................................................. 354 7-11. Block-Write Cycle Timing ................................................................................................ 355 24 List of Figures SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7-12. Block Write Flow .......................................................................................................... 356 7-13. User-Developed Programming Solution ............................................................................... 360 7-14. FCTL1 Register ........................................................................................................... 362 7-15. FCTL3 Register ........................................................................................................... 363 7-16. FCTL4 Register ........................................................................................................... 364 7-17. SFRIE1 Register .......................................................................................................... 365 8-1. Block Diagram of MID Implementation................................................................................. 367 8-2. Overview of MSP430 Flash Memory Segmentation ................................................................. 368 8-3. cw0 Parameter ............................................................................................................ 370 8-4. cw1 Parameter ............................................................................................................ 370 9-1. RCCTL0 Register ......................................................................................................... 377 11-1. DMA Controller Block Diagram ......................................................................................... 382 11-2. DMA Addressing Modes ................................................................................................. 383 11-3. DMA Single Transfer State Diagram ................................................................................... 385 11-4. DMA Block Transfer State Diagram .................................................................................... 387 11-5. DMA Burst-Block Transfer State Diagram............................................................................. 389 11-6. DMACTL0 Register....................................................................................................... 397 11-7. DMACTL1 Register....................................................................................................... 398 11-8. DMACTL2 Register....................................................................................................... 399 11-9. DMACTL3 Register....................................................................................................... 400 11-10. DMACTL4 Register....................................................................................................... 401 11-11. DMAxCTL Register ....................................................................................................... 402 11-12. DMAxSA Register ........................................................................................................ 404 11-13. DMAxDA Register ........................................................................................................ 405 11-14. DMAxSZ Register......................................................................................................... 406 11-15. DMAIV Register ........................................................................................................... 407 12-1. P1IV Register.............................................................................................................. 422 12-2. P2IV Register.............................................................................................................. 423 12-3. P1IES Register............................................................................................................ 424 12-4. P1IE Register.............................................................................................................. 424 12-5. P1IFG Register............................................................................................................ 424 12-6. P2IES Register............................................................................................................ 425 12-7. P2IE Register.............................................................................................................. 425 12-8. P2IFG Register............................................................................................................ 425 12-9. PxIN Register.............................................................................................................. 426 12-10. PxOUT Register........................................................................................................... 426 12-11. PxDIR Register............................................................................................................ 426 12-12. PxREN Register........................................................................................................... 427 12-13. PxDS Register............................................................................................................. 427 12-14. PxSEL Register ........................................................................................................... 427 13-1. PMAPKEYID Register.................................................................................................... 432 13-2. PMAPCTL Register....................................................................................................... 432 13-3. PxMAPy Register ......................................................................................................... 432 14-1. LFSR Implementation of CRC-CCITT Standard, Bit 0 is the MSB of the Result................................. 434 14-2. Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers .................................. 436 14-3. CRCDI Register ........................................................................................................... 439 14-4. CRCDIRB Register ....................................................................................................... 439 14-5. CRCINIRES Register..................................................................................................... 440 14-6. CRCRESR Register ...................................................................................................... 440 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Figures 25 www.ti.com 15-1. AES Accelerator Block Diagram ........................................................................................ 442 15-2. AES State Array Input and Output ..................................................................................... 443 15-3. AES-128 Encryption Process ........................................................................................... 444 15-4. AES-128 Decryption Process using AESOPx = 01 .................................................................. 445 15-5. AES-128 Decryption Process using AESOPx = 10 and 11 ......................................................... 446 15-6. AESACTL0 Register...................................................................................................... 449 15-7. AESACTL1 Register...................................................................................................... 450 15-8. AESASTAT Register ..................................................................................................... 451 15-9. AESAKEY Register....................................................................................................... 452 15-10. AESADIN Register........................................................................................................ 453 15-11. AESADOUT Register..................................................................................................... 453 15-12. AESAXDIN Register...................................................................................................... 454 15-13. AESAXIN Register........................................................................................................ 454 16-1. Watchdog Timer Block Diagram ........................................................................................ 457 16-2. WDTCTL Register ........................................................................................................ 461 17-1. Timer_A Block Diagram.................................................................................................. 464 17-2. Up Mode ................................................................................................................... 466 17-3. Up Mode Flag Setting .................................................................................................... 466 17-4. Continuous Mode ......................................................................................................... 467 17-5. Continuous Mode Flag Setting.......................................................................................... 467 17-6. Continuous Mode Time Intervals ....................................................................................... 467 17-7. Up/Down Mode............................................................................................................ 468 17-8. Up/Down Mode Flag Setting ............................................................................................ 468 17-9. Output Unit in Up/Down Mode .......................................................................................... 469 17-10. Capture Signal (SCS = 1)................................................................................................ 470 17-11. Capture Cycle ............................................................................................................. 470 17-12. Output Example – Timer in Up Mode .................................................................................. 472 17-13. Output Example – Timer in Continuous Mode ........................................................................ 473 17-14. Output Example – Timer in Up/Down Mode .......................................................................... 474 17-15. Capture/Compare Interrupt Flag ........................................................................................ 475 17-16. TAxCTL Register.......................................................................................................... 478 17-17. TAxR Register............................................................................................................. 479 17-18. TAxCCTLn Register ...................................................................................................... 480 17-19. TAxCCRn Register ....................................................................................................... 482 17-20. TAxIV Register ............................................................................................................ 482 17-21. TAxEX0 Register.......................................................................................................... 483 18-1. Timer_B Block Diagram.................................................................................................. 486 18-2. Up Mode ................................................................................................................... 488 18-3. Up Mode Flag Setting .................................................................................................... 488 18-4. Continuous Mode ......................................................................................................... 489 18-5. Continuous Mode Flag Setting.......................................................................................... 489 18-6. Continuous Mode Time Intervals ....................................................................................... 489 18-7. Up/Down Mode............................................................................................................ 490 18-8. Up/Down Mode Flag Setting ............................................................................................ 490 18-9. Output Unit in Up/Down Mode .......................................................................................... 491 18-10. Capture Signal (SCS = 1)................................................................................................ 492 18-11. Capture Cycle ............................................................................................................. 492 18-12. Output Example – Timer in Up Mode .................................................................................. 495 18-13. Output Example – Timer in Continuous Mode ........................................................................ 496 26 List of Figures SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 18-14. Output Example – Timer in Up/Down Mode .......................................................................... 497 18-15. Capture/Compare TBxCCR0 Interrupt Flag ........................................................................... 498 18-16. TBxCTL Register.......................................................................................................... 501 18-17. TBxR Register............................................................................................................. 503 18-18. TBxCCTLn Register ...................................................................................................... 504 18-19. TBxCCRn Register ....................................................................................................... 506 18-20. TBxIV Register ............................................................................................................ 507 18-21. TBxEX0 Register.......................................................................................................... 508 19-1. Timer_D Block Diagram.................................................................................................. 511 19-2. High Resolution Clock Generator....................................................................................... 513 19-3. Up Mode ................................................................................................................... 516 19-4. Up Mode Flag Setting .................................................................................................... 516 19-5. Continuous Mode ......................................................................................................... 516 19-6. Continuous Mode Flag Setting.......................................................................................... 517 19-7. Continuous Mode Time Intervals ....................................................................................... 517 19-8. TDxCCR0 PWM Generation Under Continuous Mode .............................................................. 518 19-9. Up/Down Mode............................................................................................................ 518 19-10. Up/Down Mode Flag Setting ............................................................................................ 519 19-11. Output Unit in Up/Down Mode .......................................................................................... 520 19-12. Controlling Rising and Falling Edge of PWM Output in Up Mode.................................................. 522 19-13. Deadband Generation (TDxCMB = 1) ................................................................................. 523 19-14. Capture Signal (SCS = 1)................................................................................................ 524 19-15. Single Capture Cycle..................................................................................................... 524 19-16. Sequential Capture Events in Dual Capture Mode................................................................... 525 19-17. COV in Dual Capture Mode ............................................................................................. 525 19-18. Output Example, Channel 1 – Timer in Up Mode .................................................................... 529 19-19. Output Example, Channel 1 - Timer in Up Mode With External Fault Signal..................................... 530 19-20. Output Example - Timer in Up Mode with External Timer Clear Signal ........................................... 531 19-21. Output Example – Timer in Continuous Mode ........................................................................ 532 19-22. Output Example – Timer in Up/Down Mode .......................................................................... 533 19-23. Capture/Compare TDxCCR0 Interrupt Flag........................................................................... 534 19-24. TDxCTL0 Register ........................................................................................................ 537 19-25. TDxCTL1 Register ........................................................................................................ 539 19-26. TDxCTL2 Register ........................................................................................................ 540 19-27. TDxR Register............................................................................................................. 541 19-28. TDxCCTLn Register ...................................................................................................... 542 19-29. TDxCCRn Register ....................................................................................................... 544 19-30. TDxCLn Register.......................................................................................................... 544 19-31. TDxHCTL0 Register ...................................................................................................... 545 19-32. TDxHCTL1 Register ...................................................................................................... 546 19-33. TDxHINT Register ........................................................................................................ 547 19-34. TDxIV Register ............................................................................................................ 548 20-1. Timer Event Control Block Diagram.................................................................................... 550 20-2. External Input Events Affect Timer_D Output ........................................................................ 552 20-3. Timer_D Output With Channel Combination .......................................................................... 552 20-4. Module Level Connection Between TEC and Timer_D ............................................................. 553 20-5. Synchronization Between Timer Instances............................................................................ 555 20-6. TECxCTL0 Register ...................................................................................................... 558 20-7. TECxCTL1 Register ...................................................................................................... 560 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Figures 27 www.ti.com 20-8. TECxCTL2 Register ...................................................................................................... 562 20-9. TECxSTA Register ....................................................................................................... 563 20-10. TECxINT Register ........................................................................................................ 564 20-11. TECxIV Register .......................................................................................................... 565 22-1. RTC_A ..................................................................................................................... 569 22-2. RTCCTL0 Register ....................................................................................................... 578 22-3. RTCCTL1 Register ....................................................................................................... 579 22-4. RTCCTL2 Register ....................................................................................................... 580 22-5. RTCCTL3 Register ....................................................................................................... 580 22-6. RTCNT1 Register......................................................................................................... 581 22-7. RTCNT2 Register......................................................................................................... 581 22-8. RTCNT3 Register......................................................................................................... 581 22-9. RTCNT4 Register......................................................................................................... 581 22-10. RTCSEC Register ........................................................................................................ 582 22-11. RTCSEC Register ........................................................................................................ 582 22-12. RTCMIN Register ......................................................................................................... 583 22-13. RTCMIN Register ......................................................................................................... 583 22-14. RTCHOUR Register ...................................................................................................... 584 22-15. RTCHOUR Register ...................................................................................................... 584 22-16. RTCDOW Register ....................................................................................................... 585 22-17. RTCDAY Register ........................................................................................................ 585 22-18. RTCDAY Register ........................................................................................................ 585 22-19. RTCMON Register........................................................................................................ 586 22-20. RTCMON Register........................................................................................................ 586 22-21. RTCYEARL Register ..................................................................................................... 587 22-22. RTCYEARL Register ..................................................................................................... 587 22-23. RTCYEARH Register..................................................................................................... 588 22-24. RTCYEARH Register..................................................................................................... 588 22-25. RTCAMIN Register ....................................................................................................... 589 22-26. RTCAMIN Register ....................................................................................................... 589 22-27. RTCAHOUR Register .................................................................................................... 590 22-28. RTCAHOUR Register .................................................................................................... 590 22-29. RTCADOW Register ..................................................................................................... 591 22-30. RTCADAY Register....................................................................................................... 591 22-31. RTCADAY Register....................................................................................................... 591 22-32. RTCPS0CTL Register.................................................................................................... 593 22-33. RTCPS1CTL Register.................................................................................................... 594 22-34. RT0PS Register........................................................................................................... 595 22-35. RTPS1 Register........................................................................................................... 595 22-36. RTCIV Register ........................................................................................................... 595 23-1. RTC_B Block Diagram ................................................................................................... 598 23-2. RTCCTL0 Register ....................................................................................................... 606 23-3. RTCCTL1 Register ....................................................................................................... 607 23-4. RTCCTL2 Register ....................................................................................................... 608 23-5. RTCCTL3 Register ....................................................................................................... 608 23-6. RTCSEC Register ........................................................................................................ 609 23-7. RTCSEC Register ........................................................................................................ 609 23-8. RTCMIN Register ......................................................................................................... 610 23-9. RTCMIN Register ......................................................................................................... 610 28 List of Figures SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 23-10. RTCHOUR Register ...................................................................................................... 611 23-11. RTCHOUR Register ...................................................................................................... 611 23-12. RTCDOW Register ....................................................................................................... 612 23-13. RTCDAY Register ........................................................................................................ 612 23-14. RTCDAY Register ........................................................................................................ 612 23-15. RTCMON Register........................................................................................................ 613 23-16. RTCMON Register........................................................................................................ 613 23-17. RTCYEAR Register....................................................................................................... 614 23-18. RTCYEAR Register....................................................................................................... 614 23-19. RTCAMIN Register ....................................................................................................... 615 23-20. RTCAMIN Register ....................................................................................................... 615 23-21. RTCAHOUR Register .................................................................................................... 616 23-22. RTCAHOUR Register .................................................................................................... 616 23-23. RTCADOW Register ..................................................................................................... 617 23-24. RTCADAY Register....................................................................................................... 618 23-25. RTCADAY Register....................................................................................................... 618 23-26. RTCPS0CTL Register.................................................................................................... 619 23-27. RTCPS1CTL Register.................................................................................................... 620 23-28. RTCPS0 Register......................................................................................................... 621 23-29. RTCPS1 Register......................................................................................................... 621 23-30. RTCIV Register ........................................................................................................... 622 23-31. BIN2BCD Register........................................................................................................ 623 23-32. BCD2BIN Register........................................................................................................ 623 24-1. RTC_C Block Diagram (RTCMODE=1)................................................................................ 626 24-2. RTC_C Offset Error Calibration and Temperature Compensation Scheme ...................................... 633 24-3. RTC_C Functional Block Diagram in Counter Mode (RTCMODE = 0)............................................ 636 24-4. RTCCTL0_L Register .................................................................................................... 644 24-5. RTCCTL0_H Register.................................................................................................... 645 24-6. RTCCTL1 Register ....................................................................................................... 646 24-7. RTCCTL3 Register ....................................................................................................... 647 24-8. RTCOCAL Register....................................................................................................... 647 24-9. RTCTCMP Register ...................................................................................................... 648 24-10. RTCNT1 Register......................................................................................................... 649 24-11. RTCNT2 Register......................................................................................................... 649 24-12. RTCNT3 Register......................................................................................................... 649 24-13. RTCNT4 Register......................................................................................................... 649 24-14. RTCSEC Register ........................................................................................................ 650 24-15. RTCSEC Register ........................................................................................................ 650 24-16. RTCMIN Register ......................................................................................................... 651 24-17. RTCMIN Register ......................................................................................................... 651 24-18. RTCHOUR Register ...................................................................................................... 652 24-19. RTCHOUR Register ...................................................................................................... 652 24-20. RTCDOW Register ....................................................................................................... 653 24-21. RTCDAY Register ........................................................................................................ 653 24-22. RTCDAY Register ........................................................................................................ 653 24-23. RTCMON Register........................................................................................................ 654 24-24. RTCMON Register........................................................................................................ 654 24-25. RTCYEAR Register....................................................................................................... 655 24-26. RTCYEAR Register....................................................................................................... 655 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Figures 29 www.ti.com 24-27. RTCAMIN Register ....................................................................................................... 656 24-28. RTCAMIN Register ....................................................................................................... 656 24-29. RTCAHOUR Register .................................................................................................... 657 24-30. RTCAHOUR Register .................................................................................................... 657 24-31. RTCADOW Register ..................................................................................................... 658 24-32. RTCADAY Register....................................................................................................... 659 24-33. RTCADAY Register....................................................................................................... 659 24-34. RTCPS0CTL Register.................................................................................................... 660 24-35. RTCPS1CTL Register.................................................................................................... 661 24-36. RTCPS0 Register......................................................................................................... 663 24-37. RTCPS1 Register......................................................................................................... 663 24-38. RTCIV Register ........................................................................................................... 664 24-39. BIN2BCD Register........................................................................................................ 665 24-40. BCD2BIN Register........................................................................................................ 665 24-41. RTCSECBAKx Register.................................................................................................. 666 24-42. RTCSECBAKx Register.................................................................................................. 666 24-43. RTCMINBAKx Register .................................................................................................. 667 24-44. RTCMINBAKx Register .................................................................................................. 667 24-45. RTCHOURBAKx Register ............................................................................................... 668 24-46. RTCHOURBAKx Register ............................................................................................... 668 24-47. RTCDAYBAKx Register.................................................................................................. 669 24-48. RTCDAYBAKx Register.................................................................................................. 669 24-49. RTCMONBAKx Register................................................................................................. 670 24-50. RTCMONBAKx Register................................................................................................. 670 24-51. RTCYEARBAKx Register................................................................................................ 671 24-52. RTCYEARBAKx Register................................................................................................ 671 24-53. RTCTCCTL0 Register.................................................................................................... 672 24-54. RTCTCCTL1 Register.................................................................................................... 672 24-55. RTCCAPxCTL Register .................................................................................................. 673 25-1. MPY32 Block Diagram ................................................................................................... 676 25-2. Q15 Format Representation............................................................................................. 681 25-3. Q14 Format Representation............................................................................................. 681 25-4. Saturation Flow Chart .................................................................................................... 683 25-5. Multiplication Flow Chart................................................................................................. 685 25-6. MPY32CTL0 Register .................................................................................................... 691 26-1. REF Block Diagram ...................................................................................................... 694 26-2. REF Block Diagram for Devices With a CTSD16 Module........................................................... 695 26-3. REFCTL0 Register ....................................................................................................... 703 27-1. ADC10_A Block Diagram ................................................................................................ 707 27-2. Analog Multiplexer ........................................................................................................ 708 27-3. Extended Sample Mode ................................................................................................. 710 27-4. Pulse Sample Mode ...................................................................................................... 710 27-5. Analog Input Equivalent Circuit ......................................................................................... 711 27-6. Single-Channel Single-Conversion Mode ............................................................................. 712 27-7. Sequence-of-Channels Mode ........................................................................................... 713 27-8. Repeat-Single-Channel Mode........................................................................................... 714 27-9. Repeat-Sequence-of-Channels Mode.................................................................................. 715 27-10. Typical Temperature Sensor Transfer Function ...................................................................... 717 27-11. ADC10_A Grounding and Noise Considerations ..................................................................... 718 30 List of Figures SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 27-12. ADC10CTL0 Register .................................................................................................... 721 27-13. ADC10CTL1 Register .................................................................................................... 722 27-14. ADC10CTL2 Register .................................................................................................... 724 27-15. ADC10MEM0 Register ................................................................................................... 725 27-16. ADC10MEM0 Register ................................................................................................... 725 27-17. ADC10MCTL0 Register .................................................................................................. 726 27-18. ADC10HI Register ........................................................................................................ 727 27-19. ADC10HI Register ........................................................................................................ 727 27-20. ADC10LO Register ....................................................................................................... 728 27-21. ADC10LO Register ....................................................................................................... 728 27-22. ADC10IE Register ........................................................................................................ 729 27-23. ADC10IFG Register ...................................................................................................... 730 27-24. ADC10IV Register ........................................................................................................ 731 28-1. ADC12_A Block Diagram (Devices With REF Module).............................................................. 734 28-2. ADC12_A MSP430F54xx (non-A) Block Diagram.................................................................... 735 28-3. Analog Multiplexer ........................................................................................................ 736 28-4. Extended Sample Mode ................................................................................................. 738 28-5. Pulse Sample Mode ...................................................................................................... 739 28-6. Analog Input Equivalent Circuit ......................................................................................... 739 28-7. Single-Channel Single-Conversion Mode ............................................................................. 741 28-8. Sequence-of-Channels Mode ........................................................................................... 742 28-9. Repeat-Single-Channel Mode........................................................................................... 743 28-10. Repeat-Sequence-of-Channels Mode.................................................................................. 744 28-11. Typical Temperature Sensor Transfer Function ...................................................................... 746 28-12. ADC12_A Grounding and Noise Considerations ..................................................................... 747 28-13. ADC12CTL0 Register .................................................................................................... 752 28-14. ADC12CTL1 Register .................................................................................................... 754 28-15. ADC12CTL2 Register .................................................................................................... 755 28-16. ADC12MEMx Register ................................................................................................... 756 28-17. ADC12MCTLx Register .................................................................................................. 757 28-18. ADC12IE Register ........................................................................................................ 758 28-19. ADC12IFG Register ...................................................................................................... 760 28-20. ADC12IV Register ........................................................................................................ 762 29-1. SD24_B Overview Block Diagram...................................................................................... 765 29-2. SD24_B Reference and Clock Generation Block Diagram.......................................................... 766 29-3. SD24_B Converter Block Diagram ..................................................................................... 767 29-4. Sigma-Delta Principle .................................................................................................... 768 29-5. Analog Input Equivalent Circuit ......................................................................................... 770 29-6. SINC3 Filter Structure .................................................................................................... 771 29-7. Comb Filter's Frequency Response With OSR = 32 ................................................................. 771 29-8. Digital Filter Step Response and Conversion Points Digital Filter Output......................................... 772 29-9. SD24_B Output Encoder and Input Decoder Block Diagram ....................................................... 774 29-10. Single Conversion Examples............................................................................................ 775 29-11. Grouped Operation - Internal Start-of-Conversion Trigger .......................................................... 776 29-12. Grouped Operation - External Start-of-Conversion Trigger ......................................................... 776 29-13. Conversion Delay Using Preload - Example .......................................................................... 776 29-14. Start of Conversion Using Preload - Example ........................................................................ 777 29-15. SD24_B Trigger Generator Block Diagram............................................................................ 778 29-16. SD24BCTL0 Register .................................................................................................... 782 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Figures 31 www.ti.com 29-17. SD24BCTL1 Register .................................................................................................... 783 29-18. SD24BTRGCTL Register ................................................................................................ 784 29-19. SD24BIFG Register ...................................................................................................... 785 29-20. SD24BIE Register ........................................................................................................ 788 29-21. SD24BIV Register ........................................................................................................ 790 29-22. SD24BCCTLx Register .................................................................................................. 791 29-23. SD24BINCTLx Register.................................................................................................. 793 29-24. SD24BOSRx Register.................................................................................................... 794 29-25. SD24BTRGOSR Register ............................................................................................... 794 29-26. SD24BPREx Register .................................................................................................... 795 29-27. SD24BTRGPRE Register................................................................................................ 795 29-28. SD24BMEMLx Register.................................................................................................. 796 29-29. SD24BMEMHx Register ................................................................................................. 796 30-1. CTSD16 Block Diagram.................................................................................................. 799 30-2. Sigma-Delta Principle .................................................................................................... 800 30-3. SINC3 Filter Structure .................................................................................................... 803 30-4. Comb Filter Frequency Response With OSR = 32................................................................... 804 30-5. Digital Filter Step Response and Conversion Points Digital Filter Output......................................... 804 30-6. Used Bits of Digital Filter Output........................................................................................ 805 30-7. Input Voltage vs Digital Output.......................................................................................... 806 30-8. Single Channel Operation Example .................................................................................... 807 30-9. Grouped Channel Operation Example ................................................................................. 808 30-10. Conversion Delay Using Preload Example............................................................................ 809 30-11. Start of Conversion Using Preload Example .......................................................................... 809 30-12. Preload and Channel Synchronization................................................................................. 810 30-13. Typical Temperature Sensor Transfer Function ...................................................................... 810 30-14. CTSD16CTL Register .................................................................................................... 814 30-15. CTSD16CCTL0 to CTSD16CCTL6 Register.......................................................................... 815 30-16. CTSD16MEM0 to CTSD16MEM6 Register ........................................................................... 816 30-17. CTSD16INCTL0 to CTSD16INCTL6 Register ........................................................................ 817 30-18. CTSD16PRE0 to CTSD16PRE6 Register............................................................................. 818 30-19. CTSD16IFG Register..................................................................................................... 819 30-20. CTSD16IE Register....................................................................................................... 821 30-21. CTSD16IV Register....................................................................................................... 823 31-1. DAC12_A Block Diagram for Two-Module Devices .................................................................. 826 31-2. DAC12_A Block Diagram For Single-Module Devices............................................................... 827 31-3. Output Voltage vs DAC Data, 12-Bit Straight-Binary Mode ......................................................... 829 31-4. Output Voltage vs DAC Data, 12-Bit Twos-Complement Mode .................................................... 830 31-5. Negative Offset............................................................................................................ 830 31-6. Positive Offset............................................................................................................. 830 31-7. DAC12_A Group Update Example, Timer_A3 Trigger............................................................... 831 31-8. DAC12_xCTL0 Register ................................................................................................. 835 31-9. DAC12_xCTL1 Register ................................................................................................. 837 31-10. DAC12_xDAT Register .................................................................................................. 838 31-11. DAC12_xDAT Register .................................................................................................. 838 31-12. DAC12_xDAT Register .................................................................................................. 839 31-13. DAC12_xDAT Register .................................................................................................. 839 31-14. DAC12_xDAT Register .................................................................................................. 840 31-15. DAC12_xDAT Register .................................................................................................. 840 32 List of Figures SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 31-16. DAC12_xDAT Register .................................................................................................. 841 31-17. DAC12_xDAT Register .................................................................................................. 841 31-18. DAC12_xCALCTL Register.............................................................................................. 842 31-19. DAC12_xCALDAT Register ............................................................................................. 842 31-20. DAC12IV Register ........................................................................................................ 843 32-1. Comp_B Block Diagram ................................................................................................. 845 32-2. Comp_B Sample-And-Hold.............................................................................................. 847 32-3. RC-Filter Response at the Output of the Comparator ............................................................... 848 32-4. Reference Generator Block Diagram .................................................................................. 848 32-5. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer ....................................... 849 32-6. Temperature Measurement System.................................................................................... 850 32-7. Timing for Temperature Measurement Systems...................................................................... 850 32-8. CBCTL0 Register ......................................................................................................... 853 32-9. CBCTL1 Register ......................................................................................................... 854 32-10. CBCTL2 Register ......................................................................................................... 855 32-11. CBCTL3 Register ......................................................................................................... 856 32-12. CBINT Register ........................................................................................................... 858 32-13. CBIV Register ............................................................................................................. 859 33-1. OA Block Diagram ........................................................................................................ 862 33-2. OAnCTL0 Register ....................................................................................................... 866 33-3. OAnPSW Register ........................................................................................................ 867 33-4. OAnNSW Register........................................................................................................ 868 33-5. OAnGSW Register........................................................................................................ 869 34-1. LCD_B Controller Block Diagram....................................................................................... 872 34-2. LCD Memory - Example for 160 Segments Maximum............................................................... 873 34-3. Bias Generation ........................................................................................................... 876 34-4. Example Static Waveforms.............................................................................................. 879 34-5. Static LCD Example (MAB addresses need to be replaced with LCDMx) ........................................ 880 34-6. Example 2-Mux Waveforms ............................................................................................. 882 34-7. 2-Mux LCD Example (MAB addresses need to be replaced with LCDMx) ....................................... 883 34-8. Example 3-Mux Waveforms ............................................................................................. 885 34-9. 3-Mux LCD Example (MAB addresses need to be replaced with LCDMx) ....................................... 886 34-10. Example 4-Mux Waveforms ............................................................................................. 888 34-11. 4-Mux LCD Example (MAB addresses need to be replaced with LCDMx) ....................................... 889 34-12. LCDBCTL0 Register...................................................................................................... 894 34-13. LCDBCTL1 Register...................................................................................................... 895 34-14. LCDBBLKCTL Register .................................................................................................. 896 34-15. LCDBMEMCTL Register................................................................................................. 897 34-16. LCDBVCTL Register ..................................................................................................... 898 34-17. LCDBPCTL0 Register.................................................................................................... 900 34-18. LCDBPCTL1 Register.................................................................................................... 900 34-19. LCDBPCTL2 Register.................................................................................................... 901 34-20. LCDBPCTL3 Register.................................................................................................... 901 34-21. LCDBCPCTL Register ................................................................................................... 902 34-22. LCDBIV Register.......................................................................................................... 903 35-1. LCD Controller Block Diagram .......................................................................................... 906 35-2. LCD Memory for Static and 2-Mux to 4-Mux Mode - Example for 160 Segments ............................... 907 35-3. LCD Memory for 5-Mux to 8-Mux Mode - Example for 160 Segments ............................................ 908 35-4. Bias Generation ........................................................................................................... 911 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Figures 33 www.ti.com 35-5. Example Static Waveforms.............................................................................................. 916 35-6. Example 2-Mux Waveforms ............................................................................................. 917 35-7. Example 3-Mux Waveforms ............................................................................................. 918 35-8. Example 4-Mux Waveforms ............................................................................................. 919 35-9. Example 6-Mux Waveforms ............................................................................................. 920 35-10. Example 8-Mux, 1/3 Bias Waveforms (LCDLP = 0).................................................................. 921 35-11. Example 8-Mux, 1/3 Bias Low-Power Waveforms (LCDLP = 1) ................................................... 922 35-12. LCDCCTL0 Register ..................................................................................................... 928 35-13. LCDCCTL1 Register ..................................................................................................... 930 35-14. LCDCBLKCTL Register .................................................................................................. 931 35-15. LCDCMEMCTL Register................................................................................................. 932 35-16. LCDCVCTL Register ..................................................................................................... 933 35-17. LCDCPCTL0 Register.................................................................................................... 935 35-18. LCDCPCTL1 Register.................................................................................................... 935 35-19. LCDCPCTL2 Register.................................................................................................... 936 35-20. LCDCPCTL3 Register.................................................................................................... 936 35-21. LCDCCPCTL Register ................................................................................................... 937 35-22. LCDCIV Register.......................................................................................................... 937 36-1. USCI_Ax Block Diagram – UART Mode (UCSYNC = 0) ............................................................ 941 36-2. Character Format ......................................................................................................... 942 36-3. Idle-Line Format........................................................................................................... 943 36-4. Address-Bit Multiprocessor Format..................................................................................... 944 36-5. Auto Baud-Rate Detection – Break/Synch Sequence ............................................................... 945 36-6. Auto Baud-Rate Detection – Synch Field.............................................................................. 945 36-7. UART vs IrDA Data Format ............................................................................................. 946 36-8. Glitch Suppression, USCI Receive Not Started ...................................................................... 948 36-9. Glitch Suppression, USCI Activated.................................................................................... 948 36-10. BITCLK Baud-Rate Timing With UCOS16 = 0 ........................................................................ 949 36-11. Receive Error.............................................................................................................. 952 36-12. UCAxCTL0 Register...................................................................................................... 959 36-13. UCAxCTL1 Register...................................................................................................... 960 36-14. UCAxBR0 Register ....................................................................................................... 961 36-15. UCAxBR1 Register ....................................................................................................... 961 36-16. UCAxMCTL Register ..................................................................................................... 961 36-17. UCAxSTAT Register ..................................................................................................... 962 36-18. UCAxRXBUF Register ................................................................................................... 963 36-19. UCAxTXBUF Register.................................................................................................... 963 36-20. UCAxIRTCTL Register ................................................................................................... 964 36-21. UCAxIRRCTL Register................................................................................................... 964 36-22. UCAxABCTL Register.................................................................................................... 965 36-23. UCAxIE Register.......................................................................................................... 966 36-24. UCAxIFG Register ........................................................................................................ 966 36-25. UCAxIV Register.......................................................................................................... 967 37-1. USCI Block Diagram – SPI Mode ...................................................................................... 971 37-2. USCI Master and External Slave ....................................................................................... 973 37-3. USCI Slave and External Master ....................................................................................... 974 37-4. USCI SPI Timing With UCMSB = 1 .................................................................................... 976 37-5. UCAxCTL0 Register...................................................................................................... 979 37-6. UCAxCTL1 Register...................................................................................................... 980 34 List of Figures SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 37-7. UCAxBR0 Register ....................................................................................................... 981 37-8. UCAxBR1 Register ....................................................................................................... 981 37-9. UCAxMCTL Register ..................................................................................................... 981 37-10. UCAxSTAT Register ..................................................................................................... 982 37-11. UCAxRXBUF Register ................................................................................................... 983 37-12. UCAxTXBUF Register.................................................................................................... 983 37-13. UCAxIE Register.......................................................................................................... 984 37-14. UCAxIFG Register ........................................................................................................ 984 37-15. UCAxIV Register.......................................................................................................... 985 37-16. UCBxCTL0 Register...................................................................................................... 987 37-17. UCBxCTL1 Register...................................................................................................... 988 37-18. UCBxBR0 Register ....................................................................................................... 989 37-19. UCBxBR1 Register ....................................................................................................... 989 37-20. UCBxMCTL Register ..................................................................................................... 989 37-21. UCBxSTAT Register ..................................................................................................... 990 37-22. UCBxRXBUF Register ................................................................................................... 991 37-23. UCBxTXBUF Register.................................................................................................... 991 37-24. UCBxIE Register.......................................................................................................... 992 37-25. UCBxIFG Register ........................................................................................................ 992 37-26. UCBxIV Register.......................................................................................................... 993 38-1. USCI Block Diagram – I2C Mode ....................................................................................... 997 38-2. I2C Bus Connection Diagram............................................................................................ 998 38-3. I2C Module Data Transfer................................................................................................ 999 38-4. Bit Transfer on I2C Bus................................................................................................... 999 38-5. I2C Module 7-Bit Addressing Format.................................................................................. 1000 38-6. I2C Module 10-Bit Addressing Format ................................................................................ 1000 38-7. I2C Module Addressing Format With Repeated START Condition ............................................... 1000 38-8. I2C Time-Line Legend................................................................................................... 1001 38-9. I2C Slave Transmitter Mode............................................................................................ 1002 38-10. I2C Slave Receiver Mode............................................................................................... 1004 38-11. I2C Slave 10-Bit Addressing Mode .................................................................................... 1005 38-12. I2C Master Transmitter Mode .......................................................................................... 1007 38-13. I2C Master Receiver Mode ............................................................................................. 1009 38-14. I2C Master 10-Bit Addressing Mode .................................................................................. 1010 38-15. Arbitration Procedure Between Two Master Transmitters ......................................................... 1011 38-16. Synchronization of Two I2C Clock Generators During Arbitration................................................. 1012 38-17. UCBxCTL0 Register .................................................................................................... 1017 38-18. UCBxCTL1 Register .................................................................................................... 1018 38-19. UCBxBR0 Register...................................................................................................... 1019 38-20. UCBxBR1 Register...................................................................................................... 1019 38-21. UCBxSTAT Register .................................................................................................... 1020 38-22. UCBxRXBUF Register.................................................................................................. 1021 38-23. UCBxTXBUF Register .................................................................................................. 1021 38-24. UCBxI2COA Register................................................................................................... 1022 38-25. UCBxI2CSA Register ................................................................................................... 1022 38-26. UCBxIE Register ........................................................................................................ 1023 38-27. UCBxIFG Register ...................................................................................................... 1024 38-28. UCBxIV Register ........................................................................................................ 1025 39-1. eUSCI_Ax Block Diagram – UART Mode (UCSYNC = 0) ......................................................... 1028 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Figures 35 www.ti.com 39-2. Character Format........................................................................................................ 1029 39-3. Idle-Line Format ......................................................................................................... 1030 39-4. Address-Bit Multiprocessor Format ................................................................................... 1031 39-5. Auto Baud-Rate Detection – Break/Synch Sequence .............................................................. 1032 39-6. Auto Baud-Rate Detection – Synch Field ............................................................................ 1032 39-7. UART vs IrDA Data Format............................................................................................ 1033 39-8. Glitch Suppression, eUSCI_A Receive Not Started ................................................................ 1035 39-9. Glitch Suppression, eUSCI_A Activated ............................................................................. 1035 39-10. BITCLK Baud-Rate Timing With UCOS16 = 0 ...................................................................... 1036 39-11. Receive Error ............................................................................................................ 1040 39-12. UCAxCTLW0 Register.................................................................................................. 1046 39-13. UCAxCTLW1 Register.................................................................................................. 1047 39-14. UCAxBRW Register..................................................................................................... 1048 39-15. UCAxMCTLW Register ................................................................................................. 1048 39-16. UCAxSTATW Register ................................................................................................. 1049 39-17. UCAxRXBUF Register.................................................................................................. 1050 39-18. UCAxTXBUF Register .................................................................................................. 1050 39-19. UCAxABCTL Register .................................................................................................. 1051 39-20. UCAxIRCTL Register ................................................................................................... 1052 39-21. UCAxIE Register ........................................................................................................ 1053 39-22. UCAxIFG Register ...................................................................................................... 1054 39-23. UCAxIV Register ........................................................................................................ 1055 40-1. eUSCI Block Diagram – SPI Mode ................................................................................... 1058 40-2. eUSCI Master and External Slave (UCSTEM = 0).................................................................. 1060 40-3. eUSCI Slave and External Master .................................................................................... 1061 40-4. eUSCI SPI Timing With UCMSB = 1 ................................................................................. 1063 40-5. UCAxCTLW0 Register.................................................................................................. 1066 40-6. UCAxBRW Register..................................................................................................... 1067 40-7. UCAxSTATW Register ................................................................................................. 1068 40-8. UCAxRXBUF Register.................................................................................................. 1069 40-9. UCAxTXBUF Register .................................................................................................. 1070 40-10. UCAxIE Register ........................................................................................................ 1071 40-11. UCAxIFG Register ...................................................................................................... 1072 40-12. UCAxIV Register ........................................................................................................ 1073 40-13. UCBxCTLW0 Register.................................................................................................. 1075 40-14. UCBxBRW Register..................................................................................................... 1076 40-15. UCBxSTATW Register ................................................................................................. 1076 40-16. UCBxRXBUF Register.................................................................................................. 1077 40-17. UCBxTXBUF Register .................................................................................................. 1077 40-18. UCBxIE Register ........................................................................................................ 1078 40-19. UCBxIFG Register ...................................................................................................... 1078 40-20. UCBxIV Register ........................................................................................................ 1079 41-1. eUSCI_B Block Diagram – I2C Mode ................................................................................. 1082 41-2. I2C Bus Connection Diagram .......................................................................................... 1083 41-3. I2C Module Data Transfer .............................................................................................. 1084 41-4. Bit Transfer on I2C Bus ................................................................................................. 1084 41-5. I2C Module 7-Bit Addressing Format.................................................................................. 1084 41-6. I2C Module 10-Bit Addressing Format ................................................................................ 1084 41-7. I2C Module Addressing Format With Repeated START Condition ............................................... 1085 36 List of Figures SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 41-8. I2C Time-Line Legend................................................................................................... 1086 41-9. I2C Slave Transmitter Mode............................................................................................ 1088 41-10. I2C Slave Receiver Mode............................................................................................... 1089 41-11. I2C Slave 10-Bit Addressing Mode .................................................................................... 1090 41-12. I2C Master Transmitter Mode .......................................................................................... 1092 41-13. I2C Master Receiver Mode ............................................................................................. 1094 41-14. I2C Master 10-Bit Addressing Mode .................................................................................. 1095 41-15. Arbitration Procedure Between Two Master Transmitters ......................................................... 1095 41-16. Synchronization of Two I2C Clock Generators During Arbitration................................................. 1096 41-17. UCBxCTLW0 Register.................................................................................................. 1103 41-18. UCBxCTLW1 Register.................................................................................................. 1105 41-19. UCBxBRW Register..................................................................................................... 1107 41-20. UCBxSTATW Register ................................................................................................. 1107 41-21. UCBxTBCNT Register .................................................................................................. 1108 41-22. UCBxRXBUF Register.................................................................................................. 1109 41-23. UCBxTXBUF Register .................................................................................................. 1109 41-24. UCBxI2COA0 Register ................................................................................................. 1110 41-25. UCBxI2COA1 Register ................................................................................................. 1111 41-26. UCBxI2COA2 Register ................................................................................................. 1111 41-27. UCBxI2COA3 Register ................................................................................................. 1112 41-28. UCBxADDRX Register ................................................................................................. 1112 41-29. UCBxADDMASK Register.............................................................................................. 1113 41-30. UCBxI2CSA Register ................................................................................................... 1113 41-31. UCBxIE Register ........................................................................................................ 1114 41-32. UCBxIFG Register ...................................................................................................... 1116 41-33. UCBxIV Register ........................................................................................................ 1118 42-1. USB Block Diagram..................................................................................................... 1121 42-2. USB Power System ..................................................................................................... 1123 42-3. USB Power Up and Down Profile ..................................................................................... 1124 42-4. Powering Entire MSP430 From VBUS ............................................................................... 1125 42-5. USB-PLL Analog Block Diagram ...................................................................................... 1126 42-6. Data Buffers and Descriptors .......................................................................................... 1129 42-7. USB Timer and Time Stamp Generation............................................................................. 1131 42-8. USBKEYPID Register .................................................................................................. 1141 42-9. USBCNF Register....................................................................................................... 1141 42-10. USBPHYCTL Register.................................................................................................. 1142 42-11. USBPWRCTL Register ................................................................................................. 1143 42-12. USBPLLCTL Register .................................................................................................. 1145 42-13. USBPLLDIVB Register ................................................................................................. 1146 42-14. USBPLLIR Register ..................................................................................................... 1147 42-15. USBIEPCNF_0 Register ............................................................................................... 1149 42-16. USBIEPBCNT_0 Register.............................................................................................. 1150 42-17. USBOEPCNFG_0 Register ............................................................................................ 1151 42-18. USBOEPBCNT_0 Register ............................................................................................ 1152 42-19. USBIEPIE Register ..................................................................................................... 1153 42-20. USBOEPIE Register .................................................................................................... 1155 42-21. USBIEPIFG Register.................................................................................................... 1157 42-22. USBOEPIFG Register .................................................................................................. 1158 42-23. USBVECINT Register .................................................................................................. 1159 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Figures 37 www.ti.com 42-24. USBMAINT Register .................................................................................................... 1160 42-25. USBTSREG Register ................................................................................................... 1161 42-26. USBFN Register......................................................................................................... 1161 42-27. USBCTL Register ....................................................................................................... 1162 42-28. USBIE Register.......................................................................................................... 1163 42-29. USBIFG Register ........................................................................................................ 1164 42-30. USBFUNADR Register ................................................................................................. 1164 42-31. USBOEPCNF_n Register .............................................................................................. 1168 42-32. USBOEPBBAX_n Register ............................................................................................ 1169 42-33. USBOEPBCTX_n Register ............................................................................................ 1170 42-34. USBOEPBBAY_n Register ............................................................................................ 1170 42-35. USBOEPBCTY_n Register ............................................................................................ 1171 42-36. USBOEPSIZXY_n Register ............................................................................................ 1171 42-37. USBIEPCNF_n Register ............................................................................................... 1172 42-38. USBIEPBBAX_n Register.............................................................................................. 1173 42-39. USBIEPBCTX_n Register.............................................................................................. 1174 42-40. USBIEPBBAY_n Register.............................................................................................. 1174 42-41. USBIEPBCTY_n Register.............................................................................................. 1175 42-42. USBIEPSIZXY_n Register ............................................................................................. 1175 43-1. LDO Block Diagram..................................................................................................... 1177 43-2. 3.3-V LDO Power Up/Down Profile ................................................................................... 1178 43-3. Powering Entire MSP430 From LDOI ................................................................................ 1179 43-4. LDOKEYPID Register .................................................................................................. 1182 43-5. PUCTL Register ......................................................................................................... 1182 43-6. LDOPWRCTL Register ................................................................................................. 1183 44-1. Large Implementation of EEM ......................................................................................... 1186 38 List of Figures SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com List of Tables 1-1. Interrupt Sources, Flags, and Vectors................................................................................... 61 1-2. Operation Modes ........................................................................................................... 65 1-3. Connection of Unused Pins ............................................................................................... 69 1-4. Tag Values .................................................................................................................. 75 1-5. Peripheral Discovery Descriptor.......................................................................................... 76 1-6. Values for Memory Entry .................................................................................................. 77 1-7. Values for Peripheral Entry ............................................................................................... 77 1-8. Peripheral IDs .............................................................................................................. 78 1-9. Sample Peripheral Discovery Descriptor................................................................................ 79 1-10. SFR Base Address......................................................................................................... 83 1-11. SFR Registers .............................................................................................................. 83 1-12. SFRIE1 Register Description ............................................................................................. 84 1-13. SFRIFG1 Register Description ........................................................................................... 85 1-14. SFRRPCR Register Description.......................................................................................... 87 1-15. SYS Base Address......................................................................................................... 88 1-16. SYS Registers .............................................................................................................. 88 1-17. SYSCTL Register Description ............................................................................................ 89 1-18. SYSBSLC Register Description .......................................................................................... 90 1-19. SYSJMBC Register Description .......................................................................................... 91 1-20. SYSJMBI0 Register Description.......................................................................................... 92 1-21. SYSJMBI1 Register Description.......................................................................................... 92 1-22. SYSJMBO0 Register Description ........................................................................................ 93 1-23. SYSJMBO1 Register Description ........................................................................................ 93 1-24. SYSUNIV Register Description........................................................................................... 94 1-25. SYSSNIV Register Description ........................................................................................... 95 1-26. SYSRSTIV Register Description ......................................................................................... 96 1-27. SYSBERRIV Register Description ....................................................................................... 97 2-1. SVS and SVM Thresholds............................................................................................... 102 2-2. Recommended SVSL Settings .......................................................................................... 102 2-3. Recommended SVSH Settings .......................................................................................... 102 2-4. Available SVSH and SVMH Settings Versus VCORE Settings.......................................................... 103 2-5. SVSL and SVML Control Mode Selection .............................................................................. 111 2-6. SVSL Automatic Performance Control ................................................................................. 111 2-7. SVSL Manual Performance Modes ..................................................................................... 111 2-8. SVML Automatic Performance Control ................................................................................. 111 2-9. SVML Manual Performance Modes..................................................................................... 111 2-10. SVSH and SVMH Control Mode Selection.............................................................................. 112 2-11. SVSH Automatic Performance Control ................................................................................. 112 2-12. SVSH Manual Performance Modes ..................................................................................... 112 2-13. SVMH Automatic Performance Control................................................................................. 112 2-14. SVMH Manual Performance Modes..................................................................................... 112 2-15. PMM Registers............................................................................................................ 114 2-16. PMMCTL0 Register Description ........................................................................................ 115 2-17. PMMCTL1 Register Description ........................................................................................ 116 2-18. SVSMHCTL Register Description ...................................................................................... 117 2-19. SVSMLCTL Register Description ....................................................................................... 118 2-20. SVSMIO Register Description........................................................................................... 119 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Tables 39 www.ti.com 2-21. PMMIFG Register Description .......................................................................................... 120 2-22. PMMRIE Register Description .......................................................................................... 122 2-23. PM5CTL0 Register Description ......................................................................................... 123 3-1. Battery Backup Registers................................................................................................ 129 3-2. BAKCTL Register Description........................................................................................... 130 3-3. BAKCHCTL Register Description....................................................................................... 131 4-1. Next Supply Voltage Selection.......................................................................................... 137 4-2. Minimum Voltage Thresholds for Selected fSYS ....................................................................... 139 4-3. Supply Selection During LPMx.5 ....................................................................................... 141 4-4. Auxiliary Supply Registers............................................................................................... 148 4-5. AUXCTL0 Register Description ......................................................................................... 149 4-6. AUXCTL1 Register Description ......................................................................................... 150 4-7. AUXCTL2 Register Description ......................................................................................... 151 4-8. AUX2CHCTL Register Description ..................................................................................... 152 4-9. AUX3CHCTL Register Description ..................................................................................... 153 4-10. AUXADCCTL Register Description..................................................................................... 154 4-11. AUXIFG Register Description ........................................................................................... 155 4-12. AUXIE Register Description ............................................................................................. 156 4-13. AUXIV Register Description ............................................................................................. 157 5-1. Clock Request System and Power Modes ............................................................................ 168 5-2. UCS Registers ............................................................................................................ 173 5-3. UCSCTL0 Register Description......................................................................................... 174 5-4. UCSCTL1 Register Description......................................................................................... 175 5-5. UCSCTL2 Register Description......................................................................................... 176 5-6. UCSCTL3 Register Description......................................................................................... 177 5-7. UCSCTL4 Register Description......................................................................................... 178 5-8. UCSCTL5 Register Description......................................................................................... 179 5-9. UCSCTL6 Register Description......................................................................................... 181 5-10. UCSCTL7 Register Description......................................................................................... 183 5-11. UCSCTL8 Register Description......................................................................................... 184 5-12. UCSCTL9 Register Description......................................................................................... 185 6-1. SR Bit Description ........................................................................................................ 192 6-2. Values of Constant Generators CG1, CG2............................................................................ 193 6-3. Source and Destination Addressing.................................................................................... 196 6-4. MSP430 Double-Operand Instructions................................................................................. 214 6-5. MSP430 Single-Operand Instructions.................................................................................. 214 6-6. Conditional Jump Instructions........................................................................................... 215 6-7. Emulated Instructions .................................................................................................... 215 6-8. Interrupt, Return, and Reset Cycles and Length ..................................................................... 216 6-9. MSP430 Format II Instruction Cycles and Length.................................................................... 216 6-10. MSP430 Format I Instructions Cycles and Length ................................................................... 217 6-11. Description of the Extension Word Bits for Register Mode.......................................................... 218 6-12. Description of Extension Word Bits for Non-Register Modes ....................................................... 219 6-13. Extended Double-Operand Instructions................................................................................ 220 6-14. Extended Single-Operand Instructions................................................................................. 222 6-15. Extended Emulated Instructions ........................................................................................ 224 6-16. Address Instructions, Operate on 20-Bit Register Data ............................................................. 225 6-17. MSP430X Format II Instruction Cycles and Length .................................................................. 226 6-18. MSP430X Format I Instruction Cycles and Length................................................................... 227 40 List of Tables SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6-19. Address Instruction Cycles and Length................................................................................ 228 6-20. Instruction Map of MSP430X............................................................................................ 229 7-1. Supported Simultaneous Code Execution and Flash Operations .................................................. 346 7-2. Erase Modes .............................................................................................................. 346 7-3. Write Modes ............................................................................................................... 350 7-4. Flash Access While Flash is Busy (BUSY = 1) ....................................................................... 357 7-5. FCTL Registers ........................................................................................................... 361 7-6. FCTL1 Register Description ............................................................................................. 362 7-7. FCTL3 Register Description ............................................................................................. 363 7-8. FCTL4 Register Description ............................................................................................. 364 7-9. SFRIE1 Register Description............................................................................................ 365 8-1. Overview of MID Support Software Functions ........................................................................ 369 9-1. RAMCTL Registers ....................................................................................................... 376 9-2. RCCTL0 Register Description........................................................................................... 377 10-1. Backup RAM Registers .................................................................................................. 379 11-1. DMA Transfer Modes..................................................................................................... 384 11-2. DMA Trigger Operation .................................................................................................. 391 11-3. Maximum Single-Transfer DMA Cycle Time .......................................................................... 392 11-4. DMA Registers ............................................................................................................ 395 11-5. DMACTL0 Register Description......................................................................................... 397 11-6. DMACTL1 Register Description......................................................................................... 398 11-7. DMACTL2 Register Description......................................................................................... 399 11-8. DMACTL3 Register Description......................................................................................... 400 11-9. DMACTL4 Register Description......................................................................................... 401 11-10. DMAxCTL Register Description......................................................................................... 402 11-11. DMAxSA Register Description .......................................................................................... 404 11-12. DMAxDA Register Description .......................................................................................... 405 11-13. DMAxSZ Register Description .......................................................................................... 406 11-14. DMAIV Register Description............................................................................................. 407 12-1. I/O Configuration.......................................................................................................... 410 12-2. Digital I/O Registers ...................................................................................................... 416 12-3. P1IV Register Description ............................................................................................... 422 12-4. P2IV Register Description ............................................................................................... 423 12-5. P1IES Register Description ............................................................................................. 424 12-6. P1IE Register Description ............................................................................................... 424 12-7. P1IFG Register Description ............................................................................................. 424 12-8. P2IES Register Description ............................................................................................. 425 12-9. P2IE Register Description ............................................................................................... 425 12-10. P2IFG Register Description ............................................................................................. 425 12-11. PxIN Register Description ............................................................................................... 426 12-12. PxOUT Register Description ............................................................................................ 426 12-13. PxDIR Register Description ............................................................................................. 426 12-14. PxREN Register Description ............................................................................................ 427 12-15. PxDS Register Description .............................................................................................. 427 12-16. PxSEL Register Description ............................................................................................. 427 13-1. Examples for Port Mapping Mnemonics and Functions ............................................................. 430 13-2. Port Mapping Control Registers ........................................................................................ 431 13-3. Port Mapping Registers for Port Px – Byte Access .................................................................. 431 13-4. Port Mapping Registers for Port Px – Word Access ................................................................. 431 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Tables 41 www.ti.com 13-5. PMAPKEYID Register Description ..................................................................................... 432 13-6. PMAPCTL Register Description ........................................................................................ 432 13-7. PxMAPy Register Description........................................................................................... 432 14-1. CRC Registers ............................................................................................................ 438 14-2. CRCDI Register Description............................................................................................. 439 14-3. CRCDIRB Register Description......................................................................................... 439 14-4. CRCINIRES Register Description ...................................................................................... 440 14-5. CRCRESR Register Description........................................................................................ 440 15-1. AES_ACCEL Registers .................................................................................................. 448 15-2. AESACTL0 Register Description ....................................................................................... 449 15-3. AESACTL1 Register Description ....................................................................................... 450 15-4. AESASTAT Register Description ....................................................................................... 451 15-5. AESAKEY Register Description......................................................................................... 452 15-6. AESADIN Register Description ......................................................................................... 453 15-7. AESADOUT Register Description ...................................................................................... 453 15-8. AESAXDIN Register Description ....................................................................................... 454 15-9. AESAXIN Register Description ......................................................................................... 454 16-1. WDT_A Registers......................................................................................................... 460 16-2. WDTCTL Register Description .......................................................................................... 461 17-1. Timer Modes .............................................................................................................. 466 17-2. Output Modes ............................................................................................................. 471 17-3. Timer_A Registers ........................................................................................................ 477 17-4. TAxCTL Register Description ........................................................................................... 478 17-5. TAxR Register Description .............................................................................................. 479 17-6. TAxCCTLn Register Description........................................................................................ 480 17-7. TAxCCRn Register Description ......................................................................................... 482 17-8. TAxIV Register Description.............................................................................................. 482 17-9. TAxEX0 Register Description ........................................................................................... 483 18-1. Timer Modes .............................................................................................................. 488 18-2. TBxCLn Load Events..................................................................................................... 493 18-3. Compare Latch Operating Modes ...................................................................................... 494 18-4. Output Modes ............................................................................................................. 494 18-5. Timer_B Registers ........................................................................................................ 500 18-6. TBxCTL Register Description ........................................................................................... 501 18-7. TBxR Register Description .............................................................................................. 503 18-8. TBxCCTLn Register Description........................................................................................ 504 18-9. TBxCCRn Register Description ......................................................................................... 506 18-10. TBxIV Register Description.............................................................................................. 507 18-11. TBxEX0 Register Description ........................................................................................... 508 19-1. Factory Preprogrammed Frequency and TDHMx, TDHCLKCR Bit Settings ..................................... 514 19-2. Timer Modes .............................................................................................................. 515 19-3. High-Resolution Mode Limitation (TDHEN = 1) - Minimum Duty Cycle ........................................... 521 19-4. High-Resolution Mode Limitation (TDHEN = 1) - Maximum Duty Cycle .......................................... 521 19-5. TDCLx Load Events ...................................................................................................... 526 19-6. Compare Latch Operating Modes ...................................................................................... 526 19-7. Output Modes ............................................................................................................. 527 19-8. Timer_D Registers........................................................................................................ 536 19-9. TDxCTL0 Register Description.......................................................................................... 537 19-10. TDxCTL1 Register Description.......................................................................................... 539 42 List of Tables SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 19-11. TDxCTL2 Register Description.......................................................................................... 540 19-12. TDxR Register Description .............................................................................................. 541 19-13. TDxCCTLn Register Description........................................................................................ 542 19-14. TDxCCRn Register Description......................................................................................... 544 19-15. TDxCLn Register Description ........................................................................................... 544 19-16. TDxHCTL0 Register Description........................................................................................ 545 19-17. TDxHCTL1 Register Description........................................................................................ 546 19-18. TDxHINT Register Description .......................................................................................... 547 19-19. TDxIV Register Description.............................................................................................. 548 20-1. TEC Registers............................................................................................................. 557 20-2. TECxCTL0 Register Description........................................................................................ 558 20-3. TECxCTL1 Register Description........................................................................................ 560 20-4. TECxCTL2 Register Description........................................................................................ 562 20-5. TECxSTA Register Description ......................................................................................... 563 20-6. TECxINT Register Description .......................................................................................... 564 20-7. TECxIV Register Description............................................................................................ 565 21-1. RTC Overview............................................................................................................. 566 22-1. RTC_A Registers ......................................................................................................... 576 22-2. RTCCTL0 Register Description ......................................................................................... 578 22-3. RTCCTL1 Register Description ......................................................................................... 579 22-4. RTCCTL2 Register Description ......................................................................................... 580 22-5. RTCCTL3 Register Description ......................................................................................... 580 22-6. RTCNT1 Register Description .......................................................................................... 581 22-7. RTCNT2 Register Description .......................................................................................... 581 22-8. RTCNT3 Register Description .......................................................................................... 581 22-9. RTCNT4 Register Description .......................................................................................... 581 22-10. RTCSEC Register Description .......................................................................................... 582 22-11. RTCSEC Register Description .......................................................................................... 582 22-12. RTCMIN Register Description........................................................................................... 583 22-13. RTCMIN Register Description........................................................................................... 583 22-14. RTCHOUR Register Description........................................................................................ 584 22-15. RTCHOUR Register Description........................................................................................ 584 22-16. RTCDOW Register Description ......................................................................................... 585 22-17. RTCDAY Register Description .......................................................................................... 585 22-18. RTCDAY Register Description .......................................................................................... 585 22-19. RTCMON Register Description ......................................................................................... 586 22-20. RTCMON Register Description ......................................................................................... 586 22-21. RTCYEARL Register Description....................................................................................... 587 22-22. RTCYEARL Register Description....................................................................................... 587 22-23. RTCYEARH Register Description ...................................................................................... 588 22-24. RTCYEARH Register Description ...................................................................................... 588 22-25. RTCAMIN Register Description......................................................................................... 589 22-26. RTCAMIN Register Description......................................................................................... 589 22-27. RTCAHOUR Register Description...................................................................................... 590 22-28. RTCAHOUR Register Description...................................................................................... 590 22-29. RTCADOW Register Description ....................................................................................... 591 22-30. RTCADAY Register Description ........................................................................................ 591 22-31. RTCADAY Register Description ........................................................................................ 591 22-32. RTCPS0CTL Register Description ..................................................................................... 593 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Tables 43 www.ti.com 22-33. RTCPS1CTL Register Description ..................................................................................... 594 22-34. RT0PS Register Description ............................................................................................ 595 22-35. RT1PS Register Description ............................................................................................ 595 22-36. RTCIV Register Description ............................................................................................. 595 23-1. RTC_B Registers ......................................................................................................... 604 23-2. RTCCTL0 Register Description ......................................................................................... 606 23-3. RTCCTL1 Register Description ......................................................................................... 607 23-4. RTCCTL2 Register Description ......................................................................................... 608 23-5. RTCCTL3 Register Description ......................................................................................... 608 23-6. RTCSEC Register Description .......................................................................................... 609 23-7. RTCSEC Register Description .......................................................................................... 609 23-8. RTCMIN Register Description........................................................................................... 610 23-9. RTCMIN Register Description........................................................................................... 610 23-10. RTCHOUR Register Description........................................................................................ 611 23-11. RTCHOUR Register Description........................................................................................ 611 23-12. RTCDOW Register Description ......................................................................................... 612 23-13. RTCDAY Register Description .......................................................................................... 612 23-14. RTCDAY Register Description .......................................................................................... 612 23-15. RTCMON Register Description ......................................................................................... 613 23-16. RTCMON Register Description ......................................................................................... 613 23-17. RTCYEAR Register Description ........................................................................................ 614 23-18. RTCYEAR Register Description ........................................................................................ 614 23-19. RTCAMIN Register Description......................................................................................... 615 23-20. RTCAMIN Register Description......................................................................................... 615 23-21. RTCAHOUR Register Description...................................................................................... 616 23-22. RTCAHOUR Register Description...................................................................................... 616 23-23. RTCADOW Register Description ....................................................................................... 617 23-24. RTCADAY Register Description ........................................................................................ 618 23-25. RTCADAY Register Description ........................................................................................ 618 23-26. RTCPS0CTL Register Description ..................................................................................... 619 23-27. RTCPS1CTL Register Description ..................................................................................... 620 23-28. RTCPS0 Register Description .......................................................................................... 621 23-29. RTCPS1 Register Description .......................................................................................... 621 23-30. RTCIV Register Description ............................................................................................. 622 23-31. BIN2BCD Register Description ......................................................................................... 623 23-32. BCD2BIN Register Description ......................................................................................... 623 24-1. RTCCAPx Pin Configuration ............................................................................................ 640 24-2. RTC_C Registers ......................................................................................................... 641 24-3. RTC_C Event and Tamper Detection Registers...................................................................... 643 24-4. RTC_C Real-Time Clock Counter Mode Aliases ..................................................................... 643 24-5. RTCCTL0_L Register Description ...................................................................................... 644 24-6. RTCCTL0_H Register Description...................................................................................... 645 24-7. RTCCTL1 Register Description ......................................................................................... 646 24-8. RTCCTL3 Register Description ......................................................................................... 647 24-9. RTCOCAL Register Description ........................................................................................ 647 24-10. RTCTCMP Register Description ........................................................................................ 648 24-11. RTCNT1 Register Description .......................................................................................... 649 24-12. RTCNT2 Register Description .......................................................................................... 649 24-13. RTCNT3 Register Description .......................................................................................... 649 44 List of Tables SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 24-14. RTCNT4 Register Description .......................................................................................... 649 24-15. RTCSEC Register Description .......................................................................................... 650 24-16. RTCSEC Register Description .......................................................................................... 650 24-17. RTCMIN Register Description........................................................................................... 651 24-18. RTCMIN Register Description........................................................................................... 651 24-19. RTCHOUR Register Description........................................................................................ 652 24-20. RTCHOUR Register Description........................................................................................ 652 24-21. RTCDOW Register Description ......................................................................................... 653 24-22. RTCDAY Register Description .......................................................................................... 653 24-23. RTCDAY Register Description .......................................................................................... 653 24-24. RTCMON Register Description ......................................................................................... 654 24-25. RTCMON Register Description ......................................................................................... 654 24-26. RTCYEAR Register Description ........................................................................................ 655 24-27. RTCYEAR Register Description ........................................................................................ 655 24-28. RTCAMIN Register Description......................................................................................... 656 24-29. RTCAMIN Register Description......................................................................................... 656 24-30. RTCAHOUR Register Description...................................................................................... 657 24-31. RTCAHOUR Register Description...................................................................................... 657 24-32. RTCADOW Register Description ....................................................................................... 658 24-33. RTCADAY Register Description ........................................................................................ 659 24-34. RTCADAY Register Description ........................................................................................ 659 24-35. RTCPS0CTL Register Description ..................................................................................... 660 24-36. RTCPS1CTL Register Description ..................................................................................... 661 24-37. RTCPS0 Register Description .......................................................................................... 663 24-38. RTCPS1 Register Description .......................................................................................... 663 24-39. RTCIV Register Description ............................................................................................. 664 24-40. BIN2BCD Register Description ......................................................................................... 665 24-41. BCD2BIN Register Description ......................................................................................... 665 24-42. RTCSECBAKx Register Description ................................................................................... 666 24-43. RTCSECBAKx Register Description ................................................................................... 666 24-44. RTCMINBAKx Register Description .................................................................................... 667 24-45. RTCMINBAKx Register Description .................................................................................... 667 24-46. RTCHOURBAKx Register Description ................................................................................. 668 24-47. RTCHOURBAKx Register Description ................................................................................. 668 24-48. RTCDAYBAKx Register Description ................................................................................... 669 24-49. RTCDAYBAKx Register Description ................................................................................... 669 24-50. RTCMONBAKx Register Description................................................................................... 670 24-51. RTCMONBAKx Register Description................................................................................... 670 24-52. RTCYEARBAKx Register Description ................................................................................. 671 24-53. RTCYEARBAKx Register Description ................................................................................. 671 24-54. RTCTCCTL0 Register Description ..................................................................................... 672 24-55. RTCTCCTL1 Register Description ..................................................................................... 672 24-56. RTCCAPxCTL Register Description.................................................................................... 673 25-1. Result Availability (MPYFRAC = 0, MPYSAT = 0) ................................................................... 677 25-2. OP1 Registers............................................................................................................. 678 25-3. OP2 Registers............................................................................................................. 678 25-4. SUMEXT and MPYC Contents.......................................................................................... 679 25-5. Result Availability in Fractional Mode (MPYFRAC = 1, MPYSAT = 0) ............................................ 682 25-6. Result Availability in Saturation Mode (MPYSAT = 1) ............................................................... 683 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Tables 45 www.ti.com 25-7. MPY32 Registers ......................................................................................................... 689 25-8. Alternative Registers ..................................................................................................... 690 25-9. MPY32CTL0 Register Description...................................................................................... 691 26-1. Reference Voltage Generation for Different Devices ................................................................ 696 26-2. REF Control of Reference System (REFMSTR = 1) (Default) for Devices Without CTSD16 .................. 697 26-3. REF Control of Reference System (REFMSTR = 1) (Default) for Devices With CTSD16 ...................... 698 26-4. Control of Reference System (REFMSTR = 0, ADC12_A Only) ................................................... 698 26-5. REF Registers............................................................................................................. 702 26-6. REFCTL0 Register Description ......................................................................................... 703 27-1. Conversion Mode Summary............................................................................................. 711 27-2. ADC10_A Registers ...................................................................................................... 720 27-3. ADC10CTL0 Register Description...................................................................................... 721 27-4. ADC10CTL1 Register Description...................................................................................... 722 27-5. ADC10CTL2 Register Description...................................................................................... 724 27-6. ADC10MEM0 Register Description..................................................................................... 725 27-7. ADC10MEM0 Register Description..................................................................................... 725 27-8. ADC10MCTL0 Register Description.................................................................................... 726 27-9. ADC10HI Register Description.......................................................................................... 727 27-10. ADC10HI Register Description.......................................................................................... 727 27-11. ADC10LO Register Description......................................................................................... 728 27-12. ADC10LO Register Description......................................................................................... 728 27-13. ADC10IE Register Description .......................................................................................... 729 27-14. ADC10IFG Register Description ........................................................................................ 730 27-15. ADC10IV Register Description .......................................................................................... 731 28-1. ADC12_A Conversion Result Formats................................................................................. 740 28-2. Conversion Mode Summary............................................................................................. 740 28-3. ADC12_A Registers ...................................................................................................... 750 28-4. ADC12CTL0 Register Description...................................................................................... 752 28-5. ADC12CTL1 Register Description...................................................................................... 754 28-6. ADC12CTL2 Register Description...................................................................................... 755 28-7. ADC12MEMx Register Description..................................................................................... 756 28-8. ADC12MCTLx Register Description.................................................................................... 757 28-9. ADC12IE Register Description .......................................................................................... 758 28-10. ADC12IFG Register Description ........................................................................................ 760 28-11. ADC12IV Register Description .......................................................................................... 762 29-1. Offset Binary Left Aligned Mapping .................................................................................... 773 29-2. Twos-Complement Left Aligned Mapping ............................................................................. 773 29-3. Data Format Example for OSR = 256.................................................................................. 773 29-4. Conversion Mode Summary............................................................................................. 774 29-5. SD24_B Registers ........................................................................................................ 780 29-6. SD24BCTL0 Register Description ...................................................................................... 782 29-7. SD24BCTL1 Register Description ...................................................................................... 783 29-8. SD24BTRGCTL Register Description.................................................................................. 784 29-9. SD24BIFG Register Description ........................................................................................ 785 29-10. SD24BIE Register Description .......................................................................................... 788 29-11. SD24BIV Register Description .......................................................................................... 790 29-12. SD24BCCTLx Register Description .................................................................................... 791 29-13. SD24BINCTLx Register Description ................................................................................... 793 29-14. SD24BOSRx Register Description ..................................................................................... 794 46 List of Tables SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 29-15. SD24BTRGOSR Register Description ................................................................................. 794 29-16. SD24BPREx Register Description...................................................................................... 795 29-17. SD24BTRGPRE Register Description ................................................................................. 795 29-18. SD24BMEMLx Register Description ................................................................................... 796 29-19. SD24BMEMHx Register Description ................................................................................... 796 30-1. Voltage Reference Signal Selection Requirements .................................................................. 801 30-2. Data Format ............................................................................................................... 806 30-3. Conversion Mode Summary............................................................................................. 807 30-4. CTSD16 Registers........................................................................................................ 813 30-5. CTSD16CTL Register Description...................................................................................... 814 30-6. CTSD16CCTL0 to CTSD16CCTL6 Register Description ........................................................... 815 30-7. CTSD16MEM0 to CTSD16MEM6 Register Description ............................................................. 816 30-8. CTSD16INCTL0 to CTSD16INCTL6 Register Description .......................................................... 817 30-9. CTSD16PRE0 to CTSD16PRE6 Register Description .............................................................. 818 30-10. CTSD16IFG Register Description ...................................................................................... 819 30-11. CTSD16IE Register Description ........................................................................................ 821 30-12. CTSD16IV Register Description ........................................................................................ 823 31-1. DAC Full-Scale Range (Vref = VeREF+ or VREF+ or VREFBG ) .............................................................. 828 31-2. DAC12SREFx = {2,3} Signal Selection Requirements for Devices With a CTSD16 Module................... 828 31-3. DAC Output Selection.................................................................................................... 833 31-4. DAC12_A Registers ...................................................................................................... 834 31-5. DAC12_xCTL0 Register Description ................................................................................... 835 31-6. DAC12_xCTL1 Register Description ................................................................................... 837 31-7. DAC12_xDAT Register Description .................................................................................... 838 31-8. DAC12_xDAT Register Description .................................................................................... 838 31-9. DAC12_xDAT Register Description .................................................................................... 839 31-10. DAC12_xDAT Register Description .................................................................................... 839 31-11. DAC12_xDAT Register Description .................................................................................... 840 31-12. DAC12_xDAT Register Description .................................................................................... 840 31-13. DAC12_xDAT Register Description .................................................................................... 841 31-14. DAC12_xDAT Register Description .................................................................................... 841 31-15. DAC12_xCALCTL Register Description ............................................................................... 842 31-16. DAC12_xCALDAT Register Description ............................................................................... 842 31-17. DAC12IV Register Description .......................................................................................... 843 32-1. Comp_B Registers........................................................................................................ 852 32-2. CBCTL0 Register Description........................................................................................... 853 32-3. CBCTL1 Register Description........................................................................................... 854 32-4. CBCTL2 Register Description........................................................................................... 855 32-5. CBCTL3 Register Description........................................................................................... 856 32-6. CBINT Register Description ............................................................................................. 858 32-7. CBIV Register Description............................................................................................... 859 33-1. OA Mode Select........................................................................................................... 863 33-2. OA Registers .............................................................................................................. 865 33-3. OAnCTL0 Register Description ......................................................................................... 866 33-4. OAnPSW Register Description.......................................................................................... 867 33-5. OAnNSW Register Description ......................................................................................... 868 33-6. OAnGSW Register Description ......................................................................................... 869 34-1. LCD Voltage and Biasing Characteristics ............................................................................. 877 34-2. LCD_B Registers ......................................................................................................... 891 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Tables 47 www.ti.com 34-3. LCD_B Memory Registers .............................................................................................. 892 34-4. LCD_B Blinking Memory Registers .................................................................................... 893 34-5. LCDBCTL0 Register Description ....................................................................................... 894 34-6. LCDBCTL1 Register Description ....................................................................................... 895 34-7. LCDBBLKCTL Register Description.................................................................................... 896 34-8. LCDBMEMCTL Register Description................................................................................... 897 34-9. LCDBVCTL Register Description ....................................................................................... 898 34-10. LCDBPCTL0 Register Description...................................................................................... 900 34-11. LCDBPCTL1 Register Description...................................................................................... 900 34-12. LCDBPCTL2 Register Description...................................................................................... 901 34-13. LCDBPCTL3 Register Description...................................................................................... 901 34-14. LCDBCPCTL Register Description ..................................................................................... 902 34-15. LCDBIV Register Description ........................................................................................... 903 35-1. Differences Between LCD_B and LCD_C............................................................................. 905 35-2. Bias Voltages and external Pins ........................................................................................ 912 35-3. LCD Voltage and Biasing Characteristics ............................................................................. 913 35-4. LCD_C Control Registers................................................................................................ 923 35-5. LCD_C Memory Registers for Static and 2-Mux to 4-Mux Modes ................................................. 924 35-6. LCD Blinking Memory Registers for Static and 2-Mux to 4-Mux Modes .......................................... 925 35-7. LCD Memory Registers for 5-Mux to 8-Mux .......................................................................... 926 35-8. LCDCCTL0 Register Description ....................................................................................... 928 35-9. LCDCCTL1 Register Description ....................................................................................... 930 35-10. LCDCBLKCTL Register Description.................................................................................... 931 35-11. LCDCMEMCTL Register Description .................................................................................. 932 35-12. LCDCVCTL Register Description ....................................................................................... 933 35-13. LCDCPCTL0 Register Description ..................................................................................... 935 35-14. LCDCPCTL1 Register Description ..................................................................................... 935 35-15. LCDCPCTL2 Register Description ..................................................................................... 936 35-16. LCDCPCTL3 Register Description ..................................................................................... 936 35-17. LCDCCPCTL Register Description ..................................................................................... 937 35-18. LCDCIV Register Description ........................................................................................... 937 36-1. Receive Error Conditions ................................................................................................ 947 36-2. BITCLK Modulation Pattern ............................................................................................. 949 36-3. BITCLK16 Modulation Pattern .......................................................................................... 950 36-4. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 ................................................. 953 36-5. Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 1 ................................................. 955 36-6. USCI_A UART Mode Registers......................................................................................... 958 36-7. UCAxCTL0 Register Description ....................................................................................... 959 36-8. UCAxCTL1 Register Description ....................................................................................... 960 36-9. UCAxBR0 Register Description......................................................................................... 961 36-10. UCAxBR1 Register Description......................................................................................... 961 36-11. UCAxMCTL Register Description....................................................................................... 961 36-12. UCAxSTAT Register Description ....................................................................................... 962 36-13. UCAxRXBUF Register Description ..................................................................................... 963 36-14. UCAxTXBUF Register Description ..................................................................................... 963 36-15. UCAxIRTCTL Register Description..................................................................................... 964 36-16. UCAxIRRCTL Register Description .................................................................................... 964 36-17. UCAxABCTL Register Description ..................................................................................... 965 36-18. UCAxIE Register Description............................................................................................ 966 48 List of Tables SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 36-19. UCAxIFG Register Description.......................................................................................... 966 36-20. UCAxIV Register Description............................................................................................ 967 37-1. UCxSTE Operation ....................................................................................................... 972 37-2. USCI_A SPI Mode Registers............................................................................................ 978 37-3. UCAxCTL0 Register Description ....................................................................................... 979 37-4. UCAxCTL1 Register Description ....................................................................................... 980 37-5. UCAxBR0 Register Description......................................................................................... 981 37-6. UCAxBR1 Register Description......................................................................................... 981 37-7. UCAxMCTL Register Description....................................................................................... 981 37-8. UCAxSTAT Register Description ....................................................................................... 982 37-9. UCAxRXBUF Register Description ..................................................................................... 983 37-10. UCAxTXBUF Register Description ..................................................................................... 983 37-11. UCAxIE Register Description............................................................................................ 984 37-12. UCAxIFG Register Description.......................................................................................... 984 37-13. UCAxIV Register Description............................................................................................ 985 37-14. USCI_B SPI Mode Registers............................................................................................ 986 37-15. UCBxCTL0 Register Description ....................................................................................... 987 37-16. UCBxCTL1 Register Description ....................................................................................... 988 37-17. UCBxBR0 Register Description......................................................................................... 989 37-18. UCBxBR1 Register Description......................................................................................... 989 37-19. UCBxMCTL Register Description....................................................................................... 989 37-20. UCBxSTAT Register Description ....................................................................................... 990 37-21. UCBxRXBUF Register Description ..................................................................................... 991 37-22. UCBxTXBUF Register Description ..................................................................................... 991 37-23. UCBxIE Register Description............................................................................................ 992 37-24. UCBxIFG Register Description.......................................................................................... 992 37-25. UCBxIV Register Description............................................................................................ 993 38-1. I2C State Change Interrupt Flags...................................................................................... 1014 38-2. USCI_B Registers....................................................................................................... 1016 38-3. UCBxCTL0 Register Description ...................................................................................... 1017 38-4. UCBxCTL1 Register Description ...................................................................................... 1018 38-5. UCBxBR0 Register Description ....................................................................................... 1019 38-6. UCBxBR1 Register Description ....................................................................................... 1019 38-7. UCBxSTAT Register Description...................................................................................... 1020 38-8. UCBxRXBUF Register Description ................................................................................... 1021 38-9. UCBxTXBUF Register Description.................................................................................... 1021 38-10. UCBxI2COA Register Description .................................................................................... 1022 38-11. UCBxI2CSA Register Description..................................................................................... 1022 38-12. UCBxIE Register Description .......................................................................................... 1023 38-13. UCBxIFG Register Description ........................................................................................ 1024 38-14. UCBxIV Register Description .......................................................................................... 1025 39-1. Receive Error Conditions............................................................................................... 1034 39-2. Modulation Pattern Examples ......................................................................................... 1036 39-3. BITCLK16 Modulation Pattern......................................................................................... 1037 39-4. UCBRSx Settings for Fractional Portion of N = fBRCLK/Baudrate ................................................... 1038 39-5. Recommended Settings for Typical Crystals and Baudrates...................................................... 1041 39-6. UART State Change Interrupt Flags.................................................................................. 1043 39-7. eUSCI_A UART Registers ............................................................................................. 1045 39-8. UCAxCTLW0 Register Description ................................................................................... 1046 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Tables 49 www.ti.com 39-9. UCAxCTLW1 Register Description ................................................................................... 1047 39-10. UCAxBRW Register Description ...................................................................................... 1048 39-11. UCAxMCTLW Register Description................................................................................... 1048 39-12. UCAxSTATW Register Description ................................................................................... 1049 39-13. UCAxRXBUF Register Description ................................................................................... 1050 39-14. UCAxTXBUF Register Description.................................................................................... 1050 39-15. UCAxABCTL Register Description .................................................................................... 1051 39-16. UCAxIRCTL Register Description..................................................................................... 1052 39-17. UCAxIE Register Description .......................................................................................... 1053 39-18. UCAxIFG Register Description ........................................................................................ 1054 39-19. UCAxIV Register Description .......................................................................................... 1055 40-1. UCxSTE Operation...................................................................................................... 1059 40-2. eUSCI_A SPI Registers ................................................................................................ 1065 40-3. UCAxCTLW0 Register Description ................................................................................... 1066 40-4. UCAxBRW Register Description ...................................................................................... 1067 40-5. UCAxSTATW Register Description ................................................................................... 1068 40-6. UCAxRXBUF Register Description ................................................................................... 1069 40-7. UCAxTXBUF Register Description.................................................................................... 1070 40-8. UCAxIE Register Description .......................................................................................... 1071 40-9. UCAxIFG Register Description ........................................................................................ 1072 40-10. UCAxIV Register Description .......................................................................................... 1073 40-11. eUSCI_B SPI Registers ................................................................................................ 1074 40-12. UCBxCTLW0 Register Description ................................................................................... 1075 40-13. UCBxBRW Register Description ...................................................................................... 1076 40-14. UCBxSTATW Register Description ................................................................................... 1076 40-15. UCBxRXBUF Register Description ................................................................................... 1077 40-16. UCBxTXBUF Register Description.................................................................................... 1077 40-17. UCBxIE Register Description .......................................................................................... 1078 40-18. UCBxIFG Register Description ........................................................................................ 1078 40-19. UCBxIV Register Description .......................................................................................... 1079 41-1. Glitch Filter Length Selection Bits..................................................................................... 1096 41-2. I2C State Change Interrupt Flags...................................................................................... 1099 41-3. eUSCI_B Registers ..................................................................................................... 1102 41-4. UCBxCTLW0 Register Description ................................................................................... 1103 41-5. UCBxCTLW1 Register Description ................................................................................... 1105 41-6. UCBxBRW Register Description ...................................................................................... 1107 41-7. UCBxSTATW Register Description ................................................................................... 1107 41-8. UCBxTBCNT Register Description.................................................................................... 1108 41-9. UCBxRXBUF Register Description ................................................................................... 1109 41-10. UCBxTXBUF Register Description.................................................................................... 1109 41-11. UCBxI2COA0 Register Description ................................................................................... 1110 41-12. UCBxI2COA1 Register Description ................................................................................... 1111 41-13. UCBxI2COA2 Register Description ................................................................................... 1111 41-14. UCBxI2COA3 Register Description ................................................................................... 1112 41-15. UCBxADDRX Register Description ................................................................................... 1112 41-16. UCBxADDMASK Register Description ............................................................................... 1113 41-17. UCBxI2CSA Register Description..................................................................................... 1113 41-18. UCBxIE Register Description .......................................................................................... 1114 41-19. UCBxIFG Register Description ........................................................................................ 1116 50 List of Tables SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 41-20. UCBxIV Register Description .......................................................................................... 1118 42-1. USB-PLL Pre-Scale Divider............................................................................................ 1127 42-2. Register Settings to Generate 48 MHz Using Common Clock Input Frequencies ............................. 1127 42-3. USB Buffer Memory Map............................................................................................... 1130 42-4. USB Interrupt Vector Generation...................................................................................... 1132 42-5. USB Configuration Registers .......................................................................................... 1140 42-6. USBKEYPID Register Description .................................................................................... 1141 42-7. USBCNF Register Description......................................................................................... 1141 42-8. USBPHYCTL Register Description ................................................................................... 1142 42-9. USBPWRCTL Register Description................................................................................... 1143 42-10. USBPLLCTL Register Description .................................................................................... 1145 42-11. USBPLLDIVB Register Description ................................................................................... 1146 42-12. USBPLLIR Register Description....................................................................................... 1147 42-13. USB Control Registers.................................................................................................. 1148 42-14. USBIEPCNF_0 Register Description ................................................................................. 1149 42-15. USBIEPBCNT_0 Register Description ............................................................................... 1150 42-16. USBOEPCNFG_0 Register Description.............................................................................. 1151 42-17. USBOEPBCNT_0 Register Description .............................................................................. 1152 42-18. USBIEPIE Register Description ....................................................................................... 1153 42-19. USBOEPIE Register Description...................................................................................... 1155 42-20. USBIEPIFG Register Description ..................................................................................... 1157 42-21. USBOEPIFG Register Description .................................................................................... 1158 42-22. USBVECINT Register Description .................................................................................... 1159 42-23. USBMAINT Register Description...................................................................................... 1160 42-24. USBTSREG Register Description..................................................................................... 1161 42-25. USBFN Register Description .......................................................................................... 1161 42-26. USBCTL Register Description ......................................................................................... 1162 42-27. USBIE Register Description............................................................................................ 1163 42-28. USBIFG Register Description.......................................................................................... 1164 42-29. USBFUNADR Register Description................................................................................... 1164 42-30. USB Buffer Memory..................................................................................................... 1165 42-31. USB Buffer Descriptor Registers ...................................................................................... 1165 42-32. USBOEPCNF_n Register Description................................................................................ 1168 42-33. USBOEPBBAX_n Register Description .............................................................................. 1169 42-34. USBOEPBCTX_n Register Description .............................................................................. 1170 42-35. USBOEPBBAY_n Register Description .............................................................................. 1170 42-36. USBOEPBCTY_n Register Description .............................................................................. 1171 42-37. USBOEPSIZXY_n Register Description.............................................................................. 1171 42-38. USBIEPCNF_n Register Description ................................................................................. 1172 42-39. USBIEPBBAX_n Register Description................................................................................ 1173 42-40. USBIEPBCTX_n Register Description................................................................................ 1174 42-41. USBIEPBBAY_n Register Description................................................................................ 1174 42-42. USBIEPBCTY_n Register Description................................................................................ 1175 42-43. USBIEPSIZXY_n Register Description ............................................................................... 1175 43-1. LDO-PWR Registers.................................................................................................... 1181 43-2. LDOKEYPID Register Description .................................................................................... 1182 43-3. PUCTL Register Description........................................................................................... 1182 43-4. LDOPWRCTL Register Description................................................................................... 1183 44-1. EEM Configurations..................................................................................................... 1188 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated List of Tables 51 Preface SLAU208O – June 2008 – Revised May 2015 Read This First About This Manual This manual describes the modules and peripherals of the MSP430x5xx and MSP430x6xx family of devices. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals may be present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family. Pin functions, internal signal connections, and operational parameters differ from device to device. The user should consult the device-specific data sheet for these details. Related Documentation From Texas Instruments For related documentation see the web site http://www.ti.com/msp430. FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Notational Conventions Program examples, are shown in a special typeface. Glossary ACLK ADC BOR BSL CPU DAC DCO dst FLL GIE Modes INT(N/2) I/O ISR LSB LSD LPM MAB Auxiliary Clock; see Section 5.1 Analog-to-Digital Converter Brown-Out Reset; see Section 1.2 Bootstrap Loader; see www.ti.com/msp430 for application reports Central Processing Unit; see Section 6.1 Digital-to-Analog Converter Digitally Controlled Oscillator; see Section 5.2.6 Destination; see Section 6.5 Frequency Locked Loop; see Section 5.2.7 General Interrupt Enable; see Section 1.3.3 Integer portion of N/2 Input/Output; see Chapter 12 Interrupt Service Routine Least-Significant Bit Least-Significant Digit Low-Power Mode; see Section 1.4; also named PM for Power Mode Memory Address Bus 52 Read This First SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com MCLK MDB MSB MSD NMI PC PM POR PUC RAM SCG SFR SMCLK SNMI SP SR src TOS UNMI WDT z16 Master Clock; see Section 5.1 Memory Data Bus Most-Significant Bit Most-Significant Digit (Non)-Maskable Interrupt; see Section 1.3.1; also split to UNMI and SNMI Program Counter; see Section 6.3.1 Power Mode; see Section 1.4 Power-On Reset; see Section 1.2 Power-Up Clear; see Section 1.2 Random Access Memory System Clock Generator; see Section 6.3.3 Special Function Register; Section 1.14 Sub-System Master Clock; see Section 5.1 System NMI; see Section 1.3.1 Stack Pointer; see Section 6.3.2 Status Register; see Section 6.3.3 Source; see Section 6.5 Top of stack; see Section 6.3.2 User NMI; see Section 1.3.1 Watchdog Timer; see Chapter 16 16-bit address space Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition Key rw r r0 r1 w w0 w1 (w) h0 h1 -0,-1 -(0),-(1) -[0],-[1] -{0},-{1} Bit Accessibility Read/write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0. Cleared by hardware Set by hardware Condition after PUC Condition after POR Condition after BOR Condition after Brownout SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Read This First 53 Chapter 1 SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) The system control module (SYS) is available on all devices. The following list shows the basic feature set of SYS. • Brownout reset (BOR) and power on reset (POR) handling • Power up clear (PUC) handling • (Non)maskable interrupt (SNMI and UNMI) event source selection and management • Address decoding • A user data-exchange mechanism using the JTAG mailbox (JMB) • Bootstrap loader (BSL) entry mechanism • Configuration management (device descriptors) • Provides interrupt vector generators for reset and NMIs Topic ........................................................................................................................... Page 1.1 System Control Module (SYS) Introduction .......................................................... 55 1.2 System Reset and Initialization ............................................................................ 55 1.3 Interrupts .......................................................................................................... 57 1.4 Operating Modes................................................................................................ 63 1.5 Principles for Low-Power Applications ................................................................. 68 1.6 Connection of Unused Pins ................................................................................. 69 1.7 Reset Pin (RST/NMI) Configuration....................................................................... 69 1.8 Configuring JTAG Pins ....................................................................................... 70 1.9 Boot Code ......................................................................................................... 70 1.10 Bootstrap Loader (BSL) ...................................................................................... 70 1.11 Memory Map – Uses and Abilities ........................................................................ 71 1.12 JTAG Mailbox (JMB) System .............................................................................. 72 1.13 Device Descriptor Table ...................................................................................... 73 1.14 SFR Registers.................................................................................................... 83 1.15 SYS Registers.................................................................................................... 88 54 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com System Control Module (SYS) Introduction 1.1 System Control Module (SYS) Introduction SYS is responsible for the interaction between various modules throughout the system. The functions that SYS provides for are not inherent to the modules themselves. Address decoding, bus arbitration, interrupt event consolidation, and reset generation are some examples of the many functions that SYS provides. 1.2 System Reset and Initialization The system reset circuitry is shown in Figure 1-1 and sources a brownout reset (BOR), a power on reset (POR), and a power up clear (PUC). Different events trigger these reset signals and different initial conditions exist depending on which signal was generated. A BOR is a device reset. A BOR is only generated by the following events: • Powering up the device • A low signal on RST/NMI pin when configured in the reset mode • A wake-up event from LPMx.5 (LPM3.5 or LPM4.5) modes • A software BOR event A POR is always generated when a BOR is generated, but a BOR is not generated by a POR. The following events trigger a POR: • A BOR signal • A SVSH and/or SVSM low condition when enabled (see the PMM chapter for details) • A SVSL and/or SVSL low condition when enabled (see the PMM chapter for details) • A software POR event A PUC is always generated when a POR is generated, but a POR is not generated by a PUC. The following events trigger a PUC: • A POR signal • Watchdog timer expiration when watchdog mode only (see the WDT_A chapter for details) • Watchdog timer password violation (see the WDT_A chapter for details) • A Flash memory password violation (see the Flash Controller chapter for details) • Power Management Module password violation (see the PMM chapter for details) • Fetch from peripheral area NOTE: The number and type of resets available may vary from device to device. See the devicespecific data sheet for all reset sources available. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 55 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated System Reset and Initialization BOR shadow s brownout circuit from port wakeup logic EN s clr RST/NMI PMMRSTIFG s clr SYSNMI notRST PMMBORIFG s clr PMMSWBOR event SVSHIFG s from SVSH SVSHPE from SVMH SVMHVLRIFG s SVMHVLRPE from SVSL SVSLIFG s SVSLPE from SVML SVMHLVLRIFG s SVMLVLRPE PMMSWPOR event Watchdog Timer PMMPORIFG s WDTIFG s Delay Delay Delay MCLK …. PUC Logic Figure 1-1. BOR/POR/PUC Reset Circuit www.ti.com BOR POR Module PUCs 56 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com System Reset and Initialization 1.2.1 Device Initial Conditions After System Reset After a BOR, the initial device conditions are: • The RST/NMI pin is configured in the reset mode. See Section 1.7 on configuring the RST/NMI pin. • I/O pins are switched to input mode as described in the Digital I/O chapter. • Other peripheral modules and registers are initialized as described in their respective chapters in this manual. • Status register (SR) is reset. • The watchdog timer powers up active in watchdog mode. • Program counter (PC) is loaded with the boot code address and boot code execution begins at that address. See Section 1.9 for more information regarding the boot code. Upon completion of the boot code, the PC is loaded with the address contained at the SYSRSTIV reset location (0FFFEh). After a system reset, user software must initialize the device for the application requirements. The following must occur: • Initialize the stack pointer (SP), typically to the top of RAM. • Initialize the watchdog to the requirements of the application. • Configure peripheral modules to the requirements of the application. NOTE: A device that is unprogrammed or blank is defined as having its reset vector value, residing at memory address FFFEh, equal to FFFFh. Upon system reset of a blank device, the device enters operating mode LPM4 automatically. See Section 1.4 for information on operating modes and Section 1.3.6 for details on interrupt vectors. NOTE: Some SRAM locations can be modified by the boot code (refer to Section 1.9) after a BOR event. These SRAM locations, when available, are at SRAM locations 01CFAh through 01CFFh and 023FAh through 023FFh. 1.3 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 1-2. Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously. There are three types of interrupts: • System reset • (Non)maskable • Maskable NOTE: The types of interrupt sources available and their respective priorities can change from device to device. See the device-specific data sheet for all interrupt sources and their priorities. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 57 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Interrupts RST/NMI Password violations ... BOR/POR/PUC circuit BOR POR PUC CPU high priority System NMI User NMI Module_A_int Module_B_int INT GIE NMI Interrupt daisy chain and vectors .. . .. Module_C_int Module_D_int low priority MAB - 6LSBs Figure 1-2. Interrupt Priority www.ti.com 1.3.1 (Non)Maskable Interrupts (NMIs) In general, NMIs are not masked by the general interrupt enable (GIE) bit. The family supports two levels of NMIs — system NMI (SNMI) and user NMI (UNMI). The NMI sources are enabled by individual interrupt enable bits. When an NMI interrupt is accepted, other NMIs of that level are automatically disabled to prevent nesting of consecutive NMIs of the same level. Program execution begins at the address stored in the NMI vector as shown in Table 1-1. To allow software backward compatibility to users of earlier MSP430 families, the software may, but does not need to, reenable NMI sources. The block diagram for NMI sources is shown in Figure 1-3. A UNMI interrupt can be generated by following sources: • An edge on the RST/NMI pin when configured in NMI mode • An oscillator fault occurs • An access violation to the flash memory A SNMI interrupt can be generated by following sources: • Power Management Module (PMM) SVML/SVMH supply voltage fault • PMM high/low side delay expiration • Vacant memory access • JTAG mailbox (JMB) event NOTE: The number and types of NMI sources may vary from device to device. See the devicespecific data sheet for all NMI sources available. 58 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Interrupts 1.3.2 SNMI Timing Consecutive SNMIs that occur at a higher rate than they can be handled (interrupt storm) allow the main program to execute one instruction after the SNMI handler is finished with a RETI instruction, before the SNMI handler is executed again. Consecutive SNMIs are not interrupted by UNMIs in this case. This avoids a blocking behavior on high SNMI rates. ACCV NMI … .. ACCVIFG ACCVIE NMIIFG NMIIE ...IFG ...IE User NMI _IRQA R S PUC RETI User NMI OSC Fault OFIFG OFIE SVML SVMH … .. SVMLIFG SVMLIE SVMHIFG SVMHIE ...IFG ...IE System NMI _IRQA Del. FF R S PUC RETI System NMI JMB event SYSJMBIFG SYSJMBIE Figure 1-3. NMIs With Reentrance Protection 1.3.3 Maskable Interrupts Maskable interrupts are caused by peripherals with interrupt capability. Each maskable interrupt source can be disabled individually by an interrupt enable bit, or all maskable interrupts can be disabled by the general interrupt enable (GIE) bit in the status register (SR). Each individual peripheral interrupt is discussed in its respective module chapter in this manual. 1.3.4 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set, the interrupt service routine is requested. Only the individual enable bit must be set for (non)maskable interrupts (NMI) to be requested. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 59 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Interrupts www.ti.com 1.3.4.1 Interrupt Acceptance The interrupt latency is six cycles, starting with the acceptance of an interrupt request, and lasting until the start of execution of the first instruction of the interrupt service routine, as shown in Figure 1-4. The interrupt logic executes the following: 1. Any currently executing instruction is completed. 2. The PC, which points to the next instruction, is pushed onto the stack. 3. The SR is pushed onto the stack. 4. The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service. 5. The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set for servicing by software. 6. All bits of SR are cleared except SCG0, thereby terminating any low-power mode. Because the GIE bit is cleared, further interrupts are disabled. 7. The content of the interrupt vector is loaded into the PC; the program continues with the interrupt service routine at that address. Before Interrupt After Interrupt Item1 Item1 SP Item2 TOS Item2 PC SP SR TOS Figure 1-4. Interrupt Processing NOTE: Enable and Disable Interrupt Due to the pipelined CPU architecture, setting the general interrupt enable (GIE) requires special care. • The instruction immediately after the enable interrupts instruction (EINT) is always executed, even if an interrupt service request is pending. • Include at least one instruction between the clear of an interrupt enable or interrupt flag and the EINT instruction. For example: Insert a NOP instruction in front of the EINT instruction. • Include at least one instruction between DINT and the start of an code sequence that requires protection from interrupts. For example: Insert a NOP instruction after the DINT. • Never clear the general interrupt enable (GIE) immediately after setting it. Insert at least one instruction in between such sequence. The rules above apply to all instructions that set or clear the general interrupt enable bit. Not following these rules might result in unexpected CPU execution. 60 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Interrupts 1.3.4.2 Return From Interrupt The interrupt handling routine terminates with the instruction: RETI //return from an interrupt service routine The return from the interrupt takes five cycles to execute the following actions and is shown in Figure 1-5. 1. The SR with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, and others are now in effect, regardless of the settings used during the interrupt service routine. 2. The PC pops from the stack and begins execution at the point where it was interrupted. Before Return From Interrupt After Item1 Item2 Item1 SP Item2 TOS PC PC SP SR TOS SR Figure 1-5. Return From Interrupt 1.3.5 Interrupt Nesting Interrupt nesting is enabled if the GIE bit is set inside an interrupt service routine. When interrupt nesting is enabled, any interrupt occurring during an interrupt service routine interrupts the routine, regardless of the interrupt priorities. 1.3.6 Interrupt Vectors The interrupt vectors are located in the address range 0FFFFh to 0FF80h, for a maximum of 64 interrupt sources. A vector is programmed by the user and points to the start location of the corresponding interrupt service routine. Table 1-1 is an example of the interrupt vectors available. See the device-specific data sheet for the complete interrupt vector list. Table 1-1. Interrupt Sources, Flags, and Vectors Interrupt Source Reset: power up, external reset watchdog, flash password System NMI: PMM User NMI: NMI, oscillator fault, flash memory access violation Device specific ... Watchdog timer ... Device specific Reserved Interrupt Flag ... WDTIFG KEYV ... NMIIFG OFIFG ACCVIFG WDTIFG System Interrupt ... Reset (Non)maskable ... (Non)maskable (Non)maskable (Non)maskable Maskable Maskable Word Address ... 0FFFEh 0FFFCh ... 0FFFAh 0FFF8h ... ... ... … … Priority ... Highest … ... … … ... ... ... … Lowest SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 61 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Interrupts www.ti.com Some interrupt enable bits, interrupt flags, and control bits for the RST/NMI pin are located in the special function registers (SFRs). The SFRs are located in the peripheral address range and are byte and word accessible. See the device-specific data sheet for the SFR configuration. 1.3.6.1 Alternate Interrupt Vectors It is possible to use the RAM as an alternate location for the interrupt vector locations. Setting the SYSRIVECT bit in SYSCTL causes the interrupt vectors to be remapped to the top of RAM. Once set, any interrupt vectors to the alternate locations now residing in RAM. Because SYSRIVECT is automatically cleared on a BOR, it is critical that the reset vector at location 0FFFEh still be available and handled properly in firmware. 1.3.7 SYS Interrupt Vector Generators SYS collects all system NMI (SNMI) sources, user NMI (UNMI) sources, and BOR/POR/PUC (reset) sources of all the other modules. They are combined into three interrupt vectors. The interrupt vector registers SYSRSTIV, SYSSNIV, SYSUNIV are used to determine which flags requested an interrupt or a reset. The interrupt with the highest priority of a group, when enabled, generates a number in the corresponding SYSRSTIV, SYSSNIV, SYSUNIV register. This number can be directly added to the program counter, causing a branch to the appropriate portion of the interrupt service routine. Disabled interrupts do not affect the SYSRSTIV, SYSSNIV, SYSUNIV values. Reading SYSRSTIV, SYSSNIV, SYSUNIV register automatically resets the highest pending interrupt flag of that register. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. Writing to the SYSRSTIV, SYSSNIV, SYSUNIV register automatically resets all pending interrupt flags of the group. 1.3.7.1 SYSSNIV Software Example The following software example shows the recommended use of SYSSNIV. The SYSSNIV value is added to the PC to automatically jump to the appropriate routine. For SYSRSTIV and SYSUNIV, a similar software approach can be used. The following is an example for a generic device. Vectors can change in priority for a given device. The device specific data sheet should be referenced for the vector locations. All vectors should be coded symbolically to allow for easy portability of code. SNI_ISR: ADD RETI JMP JMP JMP JMP JMP JMP JMBO_ISR: ... RETI SVML_ISR: ... RETI SVMH_ISR: ... RETI DLYL_ISR: ... RETI DLYH_ISR: ... RETI VMA_ISR: ... RETI JMBI_ISR: ... RETI &SYSSNIV,PC ; Add offset to jump table ; Vector 0: No interrupt SVML_ISR ; Vector 2: SVMLIFG SVMH_ISR ; Vector 4: SVMHIFG DLYL_ISR ; Vector 6: SVSMLDLYIFG DLYH_ISR ; Vector 8: SVSMHDLYIFG VMA_ISR ; Vector 10: VMAIFG JMBI_ISR ; Vector 12: JMBINIFG ; Vector 14: JMBOUTIFG ; Task_E starts here ; Return ; Vector 2 ; Task_2 starts here ; Return ; Vector 4 ; Task_4 starts here ; Return ; Vector 6 ; Task_6 starts here ; Return ; Vector 8 ; Task_8 starts here ; Return ; Vector A ; Task_A starts here ; Return ; Vector C ; Task_C starts here ; Return 62 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Operating Modes 1.3.7.2 SYSBERRIV Bus Error Interrupt Vector Generator Some devices, for example those that contain the USB module, include an additional system interrupt vector generator, SYSBERRIV. In general, any type of system related bus error or timeout error is associated with a user NMI event. Upon this event, the SYSUNIV contains an offset value corresponding to a bus error event (BUSIFG). This offset can be added to the PC to automatically jump to the appropriate NMI routine. Similarly, SYSBERRIV also contains an offset value corresponding to which specific event caused the bus error event. The offset value in SYSBERRIV can be added inside the NMI routine to automatically jump to the appropriate routine. In this way, the SYSBERRIV can be thought of as an extension to the user NMI vectors. 1.4 Operating Modes The MSP430 family is designed for ultra-low-power applications and uses different operating modes shown in Figure 1-6. The operating modes take into account three different needs: • Ultra-low power • Speed and data throughput • Minimization of individual peripheral current consumption The low-power modes LPM0 through LPM4 are configured with the CPUOFF, OSCOFF, SCG0, and SCG1 bits in the SR. The advantage of including the CPUOFF, OSCOFF, SCG0, and SCG1 mode-control bits in the SR is that the present operating mode is saved onto the stack during an interrupt service routine. Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine. Program flow can be returned to a different operating mode by manipulating the saved SR value on the stack inside of the interrupt service routine. When setting any of the modecontrol bits, the selected operating mode takes effect immediately. Peripherals operating with any disabled clock are disabled until the clock becomes active. Peripherals may also be disabled with their individual control register settings. All I/O port pins and RAM/registers are unchanged. Wakeup from LPM0 through LPM4 is possible through all enabled interrupts. When LPMx.5 (LPM3.5 or LPM4.5) is entered, the voltage regulator of the Power Management Module (PMM) is disabled. All RAM and register contents are lost. Although the I/O register contents are lost, the I/O pin states are locked upon LPMx.5 entry. See the Digital I/O chapter for further details. Wakeup from LPM4.5 is possible from a power sequence, a RST event, or from specific I/O. Wakeup from LPM3.5 is possible from a power sequence, a RST event, RTC event, or from specific I/O. NOTE: LPM3.5 and LPM4.5 low power modes are not available on all devices. See the device specific data sheet to see which LPMx.5 power modes are available. NOTE: The TEST/SBWTCK pin is used for interfacing to the development tools through Spy-Bi-Wire and JTAG. When the TEST/SBWTCK pin is high, wakeup times from LPM2, LPM3, and LPM4 may be different compared to when TEST/SBWTCK is low. Pay careful attention to the real-time behavior when exiting from LPM2, LPM3, and LPM4 with the device connected to a development tool (for example, MSP-FET430UIF). See the PMM chapter for details. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 63 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Operating Modes LPMx.5: VCORE = off (all modules off optional RTC) From active mode RTC wakeup Port wakeup RST/NMI (Reset wakeup) Brownout fault Security violation RST/NMI ‡ (Reset event) SVMH OVP-fault SVSH fault SVML OVP-fault SVSL fault WDT Active Time expired, Overflow WDT Active Password violation Peripheral area fetch BOR PMMSWBOR event Load calibration data POR PMMSWPOR event PUC PMM Password violation Flash Password violation www.ti.com CPUOFF=1 OSCOFF=0 SCG0=0 SCG1=0 LPM0: † CPU/MCLK = off FLL = on ACLK = on VCORE = on CPUOFF=1 OSCOFF=0 SCG0=1 SCG1=0 LPM1: CPU/MCLK = off FLL = off ACLK = on VCORE = on Active Mode: CPU is Active Various Modules are active PMMREGOFF = 1 to LPMx.5 † † † † CPUOFF=1 OSCOFF=0 SCG0=0 SCG1=1 CPUOFF=1 OSCOFF=0 SCG0=1 SCG1=1 LPM2: CPU/MCLK = off FLL = off ACLK = on VCORE = on CPUOFF=1 OSCOFF=1 SCG0=1 SCG1=1 LPM3: CPU/MCLK = off FLL = off ACLK = on VCORE = on LPM4: CPU/MCLK = off FLL = off ACLK = off VCORE = on Events Operating modes/Reset phases Arbitrary transitions † Any enabled interrupt and NMI performs this transition ‡ An enabled reset always restarts the device Figure 1-6. Operation Modes 64 System Resets, Interrupts, and Operating Modes, System Control Module (SYS) SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Operating Modes Table 1-2. Operation Modes SCG1 (1) SCG0 OSCOFF(1) CPUOFF(1) Mode CPU and Clocks Status(2) CPU, MCLK are active. ACLK is active. SMCLK optionally active (SMCLKOFF = 0). 0 0 0 0 Active DCO is enabled if sources ACLK, MCLK, or SMCLK (SMCLKOFF = 0). DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK (SMCLKOFF = 0). FLL is enabled if DCO is enabled. CPU, MCLK are disabled. ACLK is active. SMCLK optionally active (SMCLKOFF = 0). 0 0 0 1 LPM0 DCO is enabled if sources ACLK or SMCLK (SMCLKOFF = 0). DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK (SMCLKOFF = 0). FLL is enabled if DCO is enabled. CPU, MCLK are disabled. ACLK is active. SMCLK optionally active (SMCLKOFF = 0). 0 1 0 1 LPM1 DCO is enabled if sources ACLK or SMCLK (SMCLKOFF = 0). DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK (SMCLKOFF = 0). FLL is disabled. CPU, MCLK are disabled. ACLK is active. SMCLK is disabled. 1 0 0 1 LPM2 DCO is enabled if sources ACLK. FLL is disabled. CPU, MCLK are disabled. ACLK is active. SMCLK is disabled. 1 1 0 1 LPM3 DCO is enabled if sources ACLK. FLL is disabled. 1 1 1 1 LPM4 CPU and all clocks are disabled. When PMMREGOFF = 1, regulator is disabled. No memory retention. In this mode, 1 1 1 1 LPM3.5(3) RTC operation is possible when configured properly. See the RTC module for further details. 1 1 1 1 LPM4.5 (3) When PMMREGOFF = 1, regulator is disabled. No memory retention. In this mode, all clock sources are disabled; that is, no RTC operation is possible. (1) This bit is automatically reset when exiting low power modes. Refer to Section 1.4.1 for details. (2) The low-power modes and, hence, the system clocks can be affected by the clock request system. See the UCS chapter for details. (3) LPM3.5 and LPM4.5 modes are not available on all devices. See the device-specific data sheet for availability. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 65 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Operating Modes www.ti.com 1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4 An enabled interrupt event wakes the device from low-power operating modes LPM0 through LPM4. The program flow for exiting LPM0 through LPM4 is: • Enter interrupt service routine – The PC and SR are stored on the stack. – The CPUOFF, SCG1, and OSCOFF bits are automatically reset. • Options for returning from the interrupt service routine – The original SR is popped from the stack, restoring the previous operating mode. – The SR bits stored on the stack can be modified within the interrupt service routine returning to a different operating mode when the RETI instruction is executed. ; Enter LPM0 Example BIS #GIE+CPUOFF,SR ; ... ; ; Exit LPM0 Interrupt Service Routine BIC #CPUOFF,0(SP) RETI ; Enter LPM0 ; Program stops here ; Exit LPM0 on RETI ; Enter LPM3 Example BIS #GIE+CPUOFF+SCG1+SCG0,SR ; ... ; ; Exit LPM3 Interrupt Service Routine BIC #CPUOFF+SCG1+SCG0,0(SP) RETI ; Enter LPM3 ; Program stops here ; Exit LPM3 on RETI ; Enter LPM4 Example BIS #GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR ; ... ; ; Exit LPM4 Interrupt Service Routine BIC #CPUOFF+OSCOFF+SCG1+SCG0,0(SP) RETI ; Enter LPM4 ; Program stops here ; Exit LPM4 on RETI 1.4.2 Entering and Exiting Low-Power Modes LPMx.5 LPMx.5 entry and exit is handled differently than the other low power modes. LPMx.5, when used properly, gives the lowest power consumption available on a device. To achieve this, entry to LPMx.5 disables the LDO of the PMM module, removing the supply voltage from the core of the device. Since the supply voltage is removed from the core, all register contents, as well as, SRAM contents are lost. Exit from LPMx.5 causes a BOR event, which forces a complete reset of the system. Therefore, it is the application's responsibility to properly reconfigure the device upon exit from LPMx.5. The wakeup time from LPMx.5 is significantly longer than the wakeup time from the other power modes (see the device specific data sheet). This is primarily due to the facts that after exit from LPMx.5, time is required for the core voltage supply to be regenerated, as well as, boot code execution to complete before the application code can begin. Therefore, the use of LPMx.5 is restricted to very low duty cycle events. There are two LPMx.5 power modes, LPM3.5 and LPM4.5. Not all of these are available on all devices. See the device specific data sheet to see which LPMx.5 power modes are available. LPM4.5 allows for the lowest power consumption available. No clock sources are active during LPM4.5. LPM3.5 is similar to LPM4.5, but has the additional capability of having a RTC mode available. In addition to the wake-up events possible in LPM4.5, RTC wake-up events are also possible in LPM3.5. 66 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Operating Modes The program flow for entering LPMx.5 is: 1. Configure I/O appropriately. See the Digital I/O chapter for complete details on configuring I/O for LPMx.5. • Set all ports to general purpose I/O. Configure each port to ensure no floating inputs based on the application requirements. • If wakeup from I/O is desired, configure input ports with interrupt capability appropriately. 2. If LPM3.5 is available, and desired, enable RTC operation. In addition, configure any RTC interrupts, if desired for LPM3.5 wake-up event. See the RTC Overview chapter for complete details. 3. Ensure clock system settings allow LPMx.5 entry according to Table 5-1 in UCS chapter. 4. Enter LPMx.5 by setting PMMREGOFF = 1 and LPM4 status register bits. The following code example shows how to enter LPMx.5 mode. See the PMM chapter for further details. ; Enter LPMx.5 Example MOV.B #PMMPW_H, &PMMCTL0_H BIS.B #PMMREGOFF, &PMMCTL0_L BIS #GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR ; Open PMM registers for write ; ; Enter LPMx.5 when PMMREGOFF is set. NOTE: It is not possible to wake up from LPMx.5 if its respective interrupt flag is already asserted. TI recommends clearing the respective flag before entering LPMx.5. TI also recommends setting GIE = 1 before entry into LPMx.5. Any pending flags in this case could then be serviced before LPMx.5 entry. Although TI recommends setting GIE = 1 before entering LPMx.5, it is not required. Device wakeup from LPMx.5 with an enabled wake-up function will still cause the device to wake up from LPMx.5 even with GIE = 0. If GIE = 0 before LPMx.5, additional care may be required. Should the respective interrupt event should occur during LPMx.5 entry, the device may not recognize this or any future interrupt wake-up event on this function. Exit from LPMx.5 is possible with a RST event, a power on cycle, or through specific I/O. Any exit from LPMx.5 causes a BOR. Program execution continues at the location stored in the system reset vector location 0FFFEh after execution of the boot code. The PMMLPM5IFG bit inside the PMM module is set indicating that the device was in LPMx.5 before the wake-up event. Additionally, SYSRSTIV = 08h which can be used to generate an efficient reset handler routine. During LPMx.5, all I/O pin conditions are automatically locked to the current state. Upon exit from LPMx.5, the I/O pin conditions remain locked until the application unlocks them. See the Digital I/O chapter for complete details. If LPM3.5 was in effect, RTC operation continues uninterrupted upon wakeup. The program flow for exiting LPMx.5 is: • Enter system reset service routine – Reconfigure system as required for the application. – Reconfigure I/O as required for the application. 1.4.3 Extended Time in Low-Power Modes The temperature coefficient of the DCO should be considered when the DCO is disabled for extended lowpower mode periods. If the temperature changes significantly, the DCO frequency at wakeup may be significantly different from when the low-power mode was entered and may be out of the specified operating range. To avoid this, the DCO can be set to it lowest value before entering the low-power mode for extended periods of time where temperature can change. ; Enter LPM4 Example with lowest DCO Setting BIC #SCG0, SR ; Disable FLL MOV #0100h, &UCSCTL0 ; Set DCO tap to first tap, clear modulation. BIC #DCORSEL2+DCORSEL1+DCORSEL0,&UCSCTL1 ; Lowest DCORSEL BIS #GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR ; Enter LPM4 ; ... ; Program stops ; ; Interrupt Service Routine BIC #CPUOFF+OSCOFF+SCG1+SCG0,0(SR) ; Exit LPM4 on RETI RETI SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 67 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Principles for Low-Power Applications www.ti.com 1.5 Principles for Low-Power Applications Often, the most important factor for reducing power consumption is using the device clock system to maximize the time in LPM3 or LPM4 modes whenever possible. • Use interrupts to wake the processor and control program flow. • Peripherals should be switched on only when needed. • Use low-power integrated peripheral modules in place of software driven functions. For example, Timer_A and Timer_B can automatically generate PWM and capture external timing with no CPU resources. • Calculated branching and fast table look-ups should be used in place of flag polling and long software calculations. • Avoid frequent subroutine and function calls due to overhead. • For longer software routines, single-cycle CPU registers should be used. • Overwrite RAM control register RCCTL0 with all not available and unused segments set to powered down (= 1). For information about used RAM segments see the device-specific data sheet. If the application has low duty cycle, slow response time events, maximizing time in LPMx.5 can further reduce power consumption significantly. 68 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com 1.6 Connection of Unused Pins Table 1-3 lists the correct termination of all unused pins. Connection of Unused Pins Table 1-3. Connection of Unused Pins(1) Pin Potential Comment AVCC AVSS CPCAP DVCC DVSS Open For devices where charge pump in not used (no rail-to-rail OA and no rail-to-rail CTSD16). LCDCAP LDOI LDOO DVSS DVSS Open For devices with LDO-PWR module when not being used in the application. For devices with LDO-PWR module when not being used in the application. PJ.0/TDO PJ.1/TDI PJ.2/TMS PJ.3/TCK Open The JTAG pins are shared with general purpose I/O function (PJ.x). If not being used, these should be switched to port function, output direction (PJDIR.n = 1). When used as JTAG pins, these pins should remain open. PU.0/DP PU.1/DM Open For USB devices only when USB module is not being used in the application PUR (2) Px.y DVSS Open For USB devices only when USB module is not being used in the application Switched to port function, output direction (PxDIR.n = 1). Px.y represents port x and bit y of port x (for example, P1.0, P1.1, P2.2, PJ.0, PJ.1) RST/NMI TEST DVCC or VCC Open 47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF) pulldown(3) This pin always has an internal pulldown enabled. V18 Open For USB devices only when USB module is not being used in the application VBAK Open For devices where no separate battery backup supply in the system. Set bit BAKDIS = 1. VBAT DVCC For devices where no separate battery backup supply in the system. Set bit BAKDIS = 1. VBUS, VSSU VUSB DVSS Open For USB devices only when USB module is not being used in the application For USB devices only when USB module is not being used in the application XIN DVSS For dedicated XIN pins only. XIN pins with shared GPIO functions should be programmed to GPIO and follow Px.y recommendations. XOUT Open For dedicated XOUT pins only. XOUT pins with shared GPIO functions should be programmed to GPIO and follow Px.y recommendations. XT2IN DVSS For dedicated XT2IN pins only. XT2IN pins with shared GPIO functions should be programmed to GPIO and follow Px.y recommendations. XT2OUT Open For dedicated XT2OUT pins only. XT2OUT pins with shared GPIO functions should be programmed to GPIO and follow Px.y recommendations. (1) Any unused pin with a secondary function that is shared with general purpose I/O should follow the Px.y unused pin connection guidelines. (2) The default USB BSL evaluates the state of the PUR pin after a BOR reset. If it is pulled high externally, then the BSL is invoked. Therefore, unless invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. A 1-MΩ resistor to ground is recommended. (3) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4wire JTAG mode with TI tools such as FET interfaces or GANG programmers. 1.7 Reset Pin (RST/NMI) Configuration The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function Register (SFR), SFRRPCR. The minimum reset pulse duration is specified in the device-specific data sheet. Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI. Upon an external NMI event, the NMIIFG is set. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 69 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Configuring JTAG Pins www.ti.com The RST/NMI pin can have either a pullup or pulldown present or not. SYSRSTUP selects either pullup or pulldown and SYSRSTRE causes the pullup or pulldown to be enabled or not. If the RST/NMI pin is unused, it is required to have either the internal pullup selected and enabled or an external resistor connected to the RST/NMI pin as shown in Table 1-3. NOTE: All devices except the MSP430F543x (non-A devices) have the internal pullup enabled. In this case, no external pullup resistor is required. 1.8 Configuring JTAG Pins The JTAG pins are shared with general-purpose I/O pins. After a BOR, the SYSJTAGPIN bit in the SYSCTL register is cleared. With SYSJTAGPIN cleared, the pins with JTAG functionality are configured as general-purpose I/O. In this case, only a special sequences on the TEST and RST/NMI pins enables the JTAG functionality. As long as the TEST pin is pulled to DVCC, the pins remain in their JTAG functionality. If the TEST pin is released to DVSS, the shared JTAG pins revert to general-purpose I/Os. If SYSJTAGPIN = 1, the JTAG pins are permanently configured to 4-wire JTAG mode and remain in this mode until another BOR condition occurs. Use this feature early in the software if the MSP430 device is part of a JTAG chain. Note that this also disables the Spy-Bi-Wire mode. The SYSJTAGPIN is a write only once function. Clearing it by software is not possible. 1.9 Boot Code The boot code is always executed after a BOR. The boot code loads factory stored calibration values of the oscillator and reference voltages. In addition, it checks for the presence of a user-defined boot strap loader (BSL). 1.10 Bootstrap Loader (BSL) The BSL is software that is executed after start-up when a certain BSL entry condition is applied. The BSL enables the user to communicate with the embedded memory in the microcontroller during the prototyping phase, final production, and in service. All memory mapped resources, the programmable memory (flash memory), the data memory (RAM), and the peripherals, can be modified by the BSL as required. The user can define custom BSL code for flash-based devices and protect it against erasure and unintentional or unauthorized access. On devices without USB, a basic BSL program is provided by TI. This supports the commonly used UART protocol with RS232 interfacing, allowing flexible use of both hardware and software. To use the BSL, a specific BSL entry sequence must be applied to specific device pins. The correct entry sequence causes SYSBSLIND to be set. An added sequence of commands initiates the desired function. A boot-loading session can be exited by continuing operation at a defined user program address or by applying the standard reset sequence. Access to the device memory by the BSL is protected against misuse by a userdefined password. Devices with USB have a USB based BSL program provided by TI. For more details, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319). The amount of BSL memory that is available is device specific. The BSL memory size is organized into segments and can be set using the SYSBSLSIZE bits. See the device specific data sheet for the number and size of the segments available. It is possible to assign a small amount of RAM to the allocated BSL memory. Setting SYSBSLR allocates the lowest 16 bytes of RAM for the BSL. When the BSL memory is protected, access to these RAM locations is only possible from within the protected BSL memory segments. It may be desirable in some BSL applications to only allow changing of the Power Management Module settings from the protected BSL segments. This is possible with the SYSPMMPE bit. Normally, this bit is cleared and allows access of the PMM control registers from any memory location. Setting SYSPMMPE, allows access to the PMM control registers only from the protected BSL memory. Once set, SYSPMMPE can only be cleared by a BOR event. 70 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Memory Map – Uses and Abilities 1.11 Memory Map – Uses and Abilities This memory map represents the MSP430F5438 device. Though the address ranges differs from device to device, overall behavior remains the same. Can generate NMI on read/write/fetch Generates PUC on fetch access Protectable for read/write accesses Always able to access PMM registers from(1); Mass erase by user possible Mass erase by user possible Bank erase by user possible Segment erase by user possible Address Range 00000h-00FFFh 00000h-000FFh 00100h-00FEFh 00FF0h-00FF3h 00FF4h-00FF7h 01000h-011FFh 01200h-013FFh 01400h-015FFh 01600h-017FFh 017FCh-017FFh 01800h-0187Fh 01880h-018FFh 01900h-0197Fh 01980h-019FFh 01A00h-01A7Fh 01C00h-05BFFh 05B80-05BFFh 05C00h-0FFFFh 0FF80h-0FFFFh 10000h-45BFFh 45C00h-FFFFFh Name and Usage Peripherals with gaps Reserved for system extension Peripherals Descriptor type(2) Start address of descriptor structure BSL 0 x BSL 1 x BSL 2 x BSL 3 x BSL Signature Location Info D x Info C x Info B x Info A x Device Descriptor Table RAM 16KB Alternate Interrupt Vectors Program x x (1) Interrupt Vectors Program x x Vacant (1) Access rights are separately programmable for SYS and PMM. (2) Fixed ID for all MSP430 devices. See Section 1.13.1 for further details. (3) On vacant memory space, the value 03FFFh is driven on the data bus. Properties x x x x x x x x x x x x (3) SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 71 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Memory Map – Uses and Abilities www.ti.com 1.11.1 Vacant Memory Space Vacant memory is non-existent memory space. Accesses to vacant memory space generate a system (non)maskable interrupt (SNMI) when enabled (VMAIE = 1). Reads from vacant memory results in the value 3FFFh. In the case of a fetch, this is taken as JMP $. Fetch accesses from vacant peripheral space result in a PUC. After the boot code is executed, it behaves like vacant memory space and also causes an NMI on access. 1.11.2 JTAG Lock Mechanism Using the Electronic Fuse A device can be protected from unauthorized access by disabling the JTAG and SBW interface. This is achieved by programming the electronic fuse. Programming the electronic fuse, completely disables the debug and access capabilities associated with the JTAG and Spy-Bi-Wire interface. The JTAG is locked by programming a certain signature into the device flash memory at dedicated addresses. The JTAG security lock key resides at the end of the bootstrap loader (BSL) memory at addresses 17FCh through 17FFh. Anything other than 0h or FFFFFFFFh programmed to these addresses locks the JTAG interface. All of the 5xx MSP430 devices come with a preprogrammed BSL (TI-BSL) code that, by default, protects itself from unintended erase and write access. This is done by setting SYSBSLPE in the SYSBSLC register. Since the JTAG security lock key resides in the BSL memory address range, appropriate action must be taken to unprotect the BSL memory area before programming the protection key. For more details on the electronic fuse, see the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320). Some JTAG commands are still possible after the device is secured, including the BYPASS command (see IEEE1149-2001 Standard) and the JMB_EXCHANGE command which allows access to the JTAG Mailbox System (see Section 1.12 for details). NOTE: If a device has been protected, TI cannot access the device for a customer return. Access is only possible if a BSL is provided with its corresponding key or an unlock mechanism is provided by the customer. 1.12 JTAG Mailbox (JMB) System The SYS module provides the capability to exchange user data through the regular JTAG test/debug interface. The idea behind the JMB is to have a direct interface to the CPU during debugging, programming, and test that is identical for all '430 devices of this family and uses only few or no user application resources. The JTAG interface was chosen because it is available on all '430 devices and is a dedicated resource for debugging, programming, and test. Applications of the JMB are: • Providing entry password for device lock and unlock protection • Run-time data exchange (RTDX) 1.12.1 JMB Configuration The JMB supports two transfer modes, 16-bit and 32-bit. Setting JMBMODE enables 32-bit transfer mode. Clearing JMBMODE enables 16-bit transfer mode. 1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox Two 16-bit registers are available for outgoing messages to the JTAG port. JMBOUT0 is only used when using 16-bit transfer mode (JMBMODE = 0). JMBOUT1 is used in addition to JMBOUT0 when using 32-bit transfer mode (JMBMODE = 1). When the application wishes to send a message to the JTAG port, it writes data to JMBOUT0 for 16-bit mode, or JMBOUT0 and JMBOUT1 for 32-bit mode. JMBOUT0FG and JMBOUT1FG are read only flags that indicate the status of JMBOUT0 and JMBOUT1, respectively. When JMBOUT0FG is set, JMBOUT0 has been read by the JTAG port and is ready to receive new data. When JMBOUT0FG is reset, the JMBOUT0 is not ready to receive new data. JMBOUT1FG behaves similarly. 72 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com JTAG Mailbox (JMB) System 1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox Two 16-bit registers are available for incoming messages from the JTAG port. Only JMBIN0 is used when in 16-bit transfer mode (JMBMODE = 0). JMBIN1 is used in addition to JMBIN0 when using 32-bit transfer mode (JMBMODE = 1). When the JTAG port wishes to send a message to the application, it writes data to JMBIN0 for 16-bit mode, or JMBIN0 and JMBIN1 for 32-bit mode. JMBIN0FG and JMBIN1FG are flags that indicate the status of JMBIN0 and JMBIN1, respectively. When JMBIN0FG is set, JMBIN0 has data that is available for reading. When JMBIN0FG is reset, no new data is available in JMBIN0. JMBIN1FG behaves similarly. JMBIN0FG and JMBIN1FG can be configured to clear automatically by clearing JMBCLR0OFF and JMBCLR1OFF, respectively. Otherwise, these flags must be cleared by software. 1.12.4 JMB NMI Usage The JMB handshake mechanism can be configured to use interrupts to avoid unnecessary polling if desired. In 16-bit mode, JMBOUTIFG is set when JMBOUT0 has been read by the JTAG port and is ready to receive data. In 32-bit mode, JMBOUTIFG is set when both JMBOUT0 and JMBOUT1 has been read by the JTAG port and are ready to receive data. If JMBOUTIE is set, these events cause a system NMI. In 16-bit mode, JMBOUTIFG is cleared automatically when data is written to JMBOUT0. In 32-bit mode, JMBOUTIFG Is cleared automatically when data is written to both JMBOUT0 and JMBOUT1. In addition, the JMBOUTIFG can be cleared when reading SYSSNIV. Clearing JMBOUTIE disables the NMI interrupt. In 16-bit mode, JMBINIFG is set when JMBIN0 is available for reading. In 32-bit mode, JMBINIFG is set when both JMBIN0 and JMBIN1 are available for reading. If JMBOUTIE is set, these events cause a system NMI. In 16-bit mode, JMBINIFG is cleared automatically when JMBIN0 is read. In 32-bit mode, JMBINIFG Is cleared automatically when both JMBIN0 and JMBIN1 are read. In addition, the JMBINIFG can be cleared when reading SYSSNIV. Clearing JMBINIE disables the NMI interrupt. 1.13 Device Descriptor Table Each device provides a data structure in memory that allows an unambiguous identification of the device, as well as, a more detailed description of the available modules on a given device. SYS provides this information and can be used by device-adaptive SW tools and libraries to clearly identify a particular device and all modules and capabilities contained within it. The validity of the device descriptor can be verified by cyclic redundancy check (CRC). Figure 1-7 shows the logical order and structure of the device descriptor table. The complete device descriptor table and its contents can be found in the device specific data sheet. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 73 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Device Descriptor Table Descriptor start address Info_length CRC_length CRC_value DeviceID Firmware revision Hardware revision Tag 1 Len 1 Value field 1 Tag N Len N Value field N www.ti.com Information block Device ID and Revision Information First TLV entry (optional) Additional TLV entries (optional) Final TLV entry (optional) Figure 1-7. Devices Descriptor Table 1.13.1 Identifying Device Type The value read at address location 00FF0h identifies the family branch of the device. All values starting with 80h indicate a hierarchical structure consisting of the information block and a TLV tag-length-value (TLV) structure containing the various descriptors. Any other value than 80h read at address location 00FF0h indicates the device is of an older family and contains a flat descriptor beginning at location 0FF0h. The information block, shown in Figure 1-7 contains the device ID, die revisions, firmware revisions, and other manufacturer and tool related information. The descriptors contains information about the available peripherals, their subtypes and addresses and provides the information required to build adaptive hardware drivers for operating systems. The length of the descriptors represented by Info_length is computed as follows: Length = 2Info_length in 32-bit words (1) For example, if Info_length = 5, then the length of the descriptors equals 128 bytes. 74 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Device Descriptor Table 1.13.2 TLV Descriptors The TLV descriptors follow the information block. Because the information block is always a fixed length, the start location of the TLV descriptors is fixed for a given device family. For the MSP430x5xx family, this location is 01A08h. See the device-specific data sheet for the complete TLV structure and what descriptors are available. The TLV descriptors are unique to their respective TLV block and are always followed by the descriptor block length. Each TLV descriptor contains a tag field which identifies the descriptor type. Table 1-4 shows the currently supported tags. Short Name LDTAG PDTAG Reserved Reserved BLANK Reserved ADC12CAL REFCAL ADC10CAL Reserved CTSD16CAL Reserved TAGEXT Table 1-4. Tag Values Value 01h 02h 03h 04h 05h 06h 11h 12h 13h 14h-1Ch 1Dh 1Eh-FDh FEh Description Legacy descriptor (1xx, 2xx, 4xx families) Peripheral discovery descriptor Future use Future use Blank descriptor Future use ADC12 calibration REF calibration ADC10 calibration Future use CTSD16 calibration Future use Tag extender Each tag field is unique to its respective descriptor and is always followed by a length field. The length field is one byte if the tag value is 01h through 0FDh and represents the length of the descriptor in bytes. If the tag value equals 0FEh (TAGEXT), the next byte extends the tag values, and the following two bytes represent the length of the descriptor in bytes. In this way, a user can search through the TLV descriptor table for a particular tag value, using a routine similar to below written in pseudo code: // Identify the descriptor ID (d_ID_value) for the TLV descriptor of interest: descriptor_address = TLV_START address; while ( value at descriptor_address != d_ID_value && descriptor_address != TLV_TAGEND && descriptor_address < TLV_END) { // Point to next descriptor descriptor_address = descriptor_address + (length of the current TLV block) + 2; } if (value at descriptor_address == d_ID_value) { // Appropriate TLV descriptor has been found! Return length of descriptor & descriptor_address as the location of the TLV descriptor } else { // No TLV descriptor found with a matching d_ID_value Return a failing condition } SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 75 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Device Descriptor Table www.ti.com 1.13.3 Peripheral Discovery Descriptor This descriptor type can describe concatenated or distributed memory or peripheral mappings, as well as, the number of interrupt vectors and their order. The peripheral discovery descriptor has tag value 02h (PDTAG). Table 1-5 shows the structure of the peripheral discovery descriptor. NOTE: Peripheral Discovery Descriptor is not available in every device. See the Device Descriptors section in the device-specific data sheet for the availability and details on Peripheral Discovery Descriptor. Table 1-5. Peripheral Discovery Descriptor Element Memory entry 1 Memory entry 2 ... Delimiter (00h) Peripheral count Peripheral entry 1 Peripheral entry 2 ... Interrupt priority N-3 Interrupt priority N-4 ... Delimiter (00h) Size (bytes) 2 2 2 1 1 2 2 2 1 1 1 1 Comments Optional Optional Optional Mandatory Mandatory Optional Optional Optional Optional Optional Optional Mandatory The structures for a memory entry and peripheral entry are shown below. A memory entry consists of two bytes (one word). Table 1-6 shows the individual bit fields of a memory entry word and their respective meanings. Similarly, a peripheral entry consists of two bytes (one word). Table 1-7 shows the individual bit fields of a peripheral entry word and their respective meanings. 76 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Table 1-6. Values for Memory Entry [15:13] Memory Type 000: None 001: RAM 010: EEPROM 011: Reserved 100: FLASH 101: ROM 110: MemType appended 111: Undefined [12:9] Size 0000: 0 B 0001: 128 B 0010: 256 B 0011: 512 B 0100: 1KB 0101: 2KB 0110: 4KB 0111: 8KB 1000: 16KB 1001: 32KB 1010: 64KB 1011: 128KB 1100: 256KB 1101: 512KB 1110: Size appended 1111: Undefined Bit Fields [8] More 0: End Entry 1: More Entries [7] Unit Size 0: 0200h 1: 010000h Device Descriptor Table [6:0] Address Value 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 ... ... 1111111 Table 1-7. Values for Peripheral Entry Bit Fields [15:8] [7] [6:0] Peripheral ID (PID)(1) UnitSize AdrVal Any PID 0: 010h 0000000 Any PID 1: 0800h 0000001 Any PID 0000010 Any PID 0000011 Any PID 0000100 Any PID 0000101 Any PID ... Any PID ... Any PID 1111111 (1) The Peripheral IDs are listed in Table 1-8. This is not a complete list, but shown as an example. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 77 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Device Descriptor Table Table 1-8. Peripheral IDs(1) Peripheral or Module PID No Module 00h WDT 01h SFR 02h UCS 03h SYS 04h PMM 05h Flash Controller 08h CRC16 09h Port 1, 2 51h Port 3, 4 52h Port 5, 6 53h Port 7, 8 54h Port 9, 10 55h Port J 5Fh Timer A0 81h Timer A1 82h Special info appended FEh Undefined module FFh (1) This table is not a complete list of all peripheral IDs that might be available on a device, and is shown here for illustrative purposes only. www.ti.com 78 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Device Descriptor Table Table 1-9 shows a simple example for a peripheral discovery descriptor of a hypothetical device: Table 1-9. Sample Peripheral Discovery Descriptor Hex Binary Entry Type Description 030h, 0Eh 001_1000_ 0_0_0001110 memory RAM 16KB, Start address = 01C00h (0Eh × 0200h)(1) 09Bh, 02Eh 100_1011_0_0_0101110 memory Flash 128KB, Start address = 05C00h (2Eh × 0200h) 00h 0000_0000_0000_0000 delimiter No more memory entries 0Fh 0000_1111 peripheral count Peripheral count = 15 02h, 10h 00000010_0_0010000 peripheral SFR at address = 0100h (10h × 10h) 01h, 01h 00000001_0_0000001 peripheral WDT at address = 0110h (0100h + 10h) 05h, 01h 00000101_0_0000001 peripheral PMM at address = 0120h (0110h + 10h) 03h, 01h 00000011_0_0000001 peripheral UCS at address = 0130h (0120h + 10h) 08h, 01h 00001000_0_0000001 peripheral FLCTL at address = 0140h (0130h + 10h) 09h, 01h 00001001_0_0000001 peripheral CRC16 at address = 0150h (0140h + 10h) 04h, 01h 00000100_0_0000001 peripheral SYS at address = 0160h (0150h + 10h) 51h, 0Ah 01010001_0_0001010 peripheral Port 1, 2 at address = 0200h (0160h + 10h × 10h) 52h, 02h 01010010_0_0000010 peripheral Port 3, 4 at address = 0220h (0200h + 02h × 10h) 53h, 02h 01010011_0_0000010 peripheral Port 5, 6 at address = 0240h (0220h + 02h × 10h) 54h, 02h 01010100_0_0000010 peripheral Port 7, 8 at address = 0260h (0240h + 02h × 10h) 55h, 02h 01010101_0_0000010 peripheral Port 9, 10 at address = 0280h (0260h + 02h × 10h) 5Fh, 0Ah 01011111_0_0001010 peripheral Port J at address = 0320h (0280h + 0Ah × 10h) 81h, 02h 10000001_0_0000010 peripheral Timer A0 at address = 0340h (0320h + 02h × 10h) 82h, 04h 10000010_0_0000100 peripheral Timer A1 at address = 0380h (0340h + 04h × 10h) – No appended entries SYSRSTIV at 0FFFEh (implied) SYSSNIV at 0FFFCh (implied) SYSUNIV at 0FFFAh (implied) 81h 1000_0001 interrupt TA0 CCR0 at 0FFF8h 81h 1000_0001 interrupt TA0 CCR1, CCR1, TA0IFG at 0FFF6h 51h 0101_0001 interrupt Port 1 at 0FFF4h 82h 1000_0010 interrupt TA1CCR0 at 0FFF2h 51h 0101_0001 interrupt Port 2 at 0FFF0h 81h 1000_0010 interrupt TA1 CCR1, CCR1, TA1IFG at 0FFEEh 00h 0000_0000 delimiter No more interrupt entries (1) In this example, the memory type is RAM (bits[15:13] = 001b), the size is 16KB (bits[12:9] = 1000b), and the starting address is 01C00h. The starting address is computed by taking the size field indicated by bit[7] (in this case, 0200h) and multiplying it by the address value (bits[6:0] = 0001110b. In this case, 0200h × 00Eh = 01C00h. NOTE: The interrupt ordering has some implied rules: • For timers, CCR0 interrupt has higher priority over all other CCRn interrupts. • For communication ports, RX has higher priority over TX • For port pairs, Port 1 has higher priority than Port 2, Port 3 has higher priority than Port 4, and so on. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 79 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Device Descriptor Table www.ti.com 1.13.4 CRC Computation The CRC checksum for the TLV structure is stored at memory locations 0x1A02 and 0x1A03. The least significant byte (LSB) and most significant byte (MSB) reside at memory locations 0x1A02 and 0x1A03, respectively. The checksum is computed using data stored at memory locations 0x1A04 through 0x1AFF. The CRC checksum can be easily computed using the CRC16 module. The following simplified C code utilizes the CRC16 module to compute the checksum. See the CRC16 chapter for further details on the CRC algorithm implementation. NOTE: The CRC module on the MSP430F543x and MSP430F541x non-A versions does not support the bit-wise reverse feature used in this code example. Registers CRCDIRB and CRCRESR, along with their respective functionality, are not available. unsigned int i; unsigned char CRCRESULT_LSB, CRCRESULT_MSB; WDTCTL = WDTPW + WDTHOLD; CRCINIRES = 0xFFFF; for (i = 0x01A04; i <= 0x01AFF; i++){ CRCDIRB_L = *(unsigned char*)(i); } CRCRESULT_LSB = CRCINIRES_L; // value stored at 0x1A02 CRCRESULT_MSB = CRCINIRES_H; // value stored at 0x1A03 80 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Device Descriptor Table 1.13.5 Calibration Values The TLV structure contains calibration values that can be used to improve the measurement capability of various functions. The calibration values available on a given device are shown in the TLV structure of the device-specific data sheet. 1.13.5.1 REF Calibration The calibration data for the REF module consists of three words, one word for each reference voltage available (1.5, 2.0, and 2.5 V). The reference voltages are measured at room temperature. The measured values are normalized by 1.5 V, 2.0 V, or 2.5 V before being stored into the TLV structure: CAL _ ADC _15VREF _ FACTOR V = REF + ´ 215 1.5V CAL _ ADC _ 20VREF _ FACTOR V = REF + ´ 215 2.0V CAL _ ADC _ 25VREF _ FACTOR V = REF + ´ 215 2.5V (2) In this way, a conversion result is corrected by multiplying it with the CAL_15VREF_FACTOR (or CAL_20VREF_FACTOR, CAL_25VREF_FACTOR) and dividing the result by 215 as shown for each of the respective reference voltages: 1 ADC(corrected) = ADC(raw)´CAL _ ADC15VREF _ FACTOR ´ 215 1 ADC(corrected ) = ADC(raw)´CAL _ ADC20VREF _ FACTOR ´ 2 15 1 ADC(corrected) = ADC(raw)´CAL _ ADC25VREF _ FACTOR ´ 215 (3) In the following example, the integrated 1.5-V reference voltage is used during a conversion. • Conversion result: 0x0100 = 256 decimal • Reference voltage calibration factor (CAL_15VREF_FACTOR) : 0x7BBB The following steps show how the ADC conversion result can be corrected: • Multiply the conversion result by 2 (this step simplifies the final division): 0x0100 x 0x0002 = 0x0200 • Multiply the result by CAL_15VREF_FACTOR: 0x200 x 0x7FEE = 0x00F7_7600 • Divide the result by 216: 0x00F7_7600 / 0x0001_0000 = 0x0000_00F7 = 247 decimal 1.13.5.2 ADC and CTSD16 Offset and Gain Calibration The offset of the ADC (ADC10, ADC12, or CTSD16) is determined and stored as a twos-complement number in the TLV structure. The offset error correction is done by adding the CAL_ADC_OFFSET to the conversion result. ADC(offset _ corrected ) = ADC(raw) + CAL _ ADC _ OFFSET (4) The gain of the ADC is calculated by Equation 5: CAL _ ADC _ GAIN _ FACTOR = 1 ´ 215 GAIN (5) The conversion result is gain corrected by multiplying it with the CAL_ADC_GAIN_FACTOR and dividing the result by 215: SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 81 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Device Descriptor Table 1 ADC(gain _ corrected ) = ADC(raw) ´ CAL _ ADC _ GAIN _ FACTOR ´ 215 If both gain and offset are corrected, the gain correction is done first: 1 ADC(gain _ corrected ) = ADC(raw) ´ CAL _ ADC _ GAIN _ FACTOR ´ 215 www.ti.com (6) ADC( final) = ADC(gain _ corrected ) + CAL _ ADC _ OFFSET (7) 1.13.5.3 Temperature Sensor Calibration for Devices With ADCx The temperature sensor is calibrated using the internal voltage references. Each reference voltage (1.5/2.0/2.5 V) contains a measured value for two temperatures, 30°C ±3°C and 85°C ±3°C and are stored in the TLV structure. The characteristic equation of the temperature sensor voltage, in mV is: VSENSE = TCSENSOR ´ Temp + VSENSOR (8) The temperature coefficient, TCSENSORin mV/°C, represents the slope of the equation. VSENSOR, in mV, represents the y-intercept of the equation. Temp, in °C, is the temperature of interest. The temperature (Temp, °C) can be computed as follows for each of the reference voltages used in the ADC measurement: Tem p = (AD C (raw) - CAL _ ADC _ T 30 )´ ççèæ C A L _ ADC 85 _ T 85 - 30 - CAL _ ADC _ T 30 ÷÷øö + 30 (9) 1.13.6 Temperature Sensor Calibration for Devices With CTSD16 The temperature sensor is calibrated using the internal VREFBG voltage reference. A value for two temperatures, 30°C ±3°C and 85°C ±3°C, is stored in the TLV structure. The characteristic equation of the temperature sensor voltage, in mV is: VSENSE = TCSENSOR ´ Temp + VSENSOR (10) The temperature coefficient, TCSENSORin mV/°C, represents the slope of the equation. VSENSOR, in mV, represents the y-intercept of the equation. Temp, in °C, is the temperature of interest. The temperature (Temp, °C) can be computed as follows: Tem p = (AD C (raw) - CAL _ ADC _ T 30 )´ ççèæ C A L _ ADC 85 _ T 85 - 30 - CAL _ ADC _ T 30 ÷÷øö + 30 (11) 82 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com SFR Registers 1.14 SFR Registers The SFRs are listed in Table 1-11. The base address for the SFRs is listed in Table 1-10. Many of the bits inside the SFRs are described in other chapters throughout this user's guide. These bits are marked with a note and a reference. See the specific chapter of the respective module for details. NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15). Table 1-10. SFR Base Address Module SFR Base Address 00100h Offset 00h 00h 01h 02h 02h 03h 04h 04h 05h Table 1-11. SFR Registers Acronym SFRIE1 SFRIE1_L (IE1) SFRIE1_H (IE2) SFRIFG1 SFRIFG1_L (IFG1) SFRIFG1_H (IFG2) SFRRPCR SFRRPCR_L SFRRPCR_H Register Name Interrupt Enable Interrupt Flag Reset Pin Control Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Access Word Byte Byte Word Byte Byte Word Byte Byte Reset 0000h 00h 00h 0082h 82h 00h 0000h 00h 00h Section Section 7.4.4 Section 1.14.2 Section 1.14.3 SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 83 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated SFR Registers 1.14.1 SFRIE1 Register Interrupt Enable Register www.ti.com 15 14 13 r0 r0 r0 7 JMBOUTIE rw-0 6 JMBINIE rw-0 5 ACCVIE (1) rw-0 (1) See the Flash Controller chapter for details. (2) See the UCS chapter for details. (3) See the WDT_A chapter for details. Figure 1-8. SFRIE1 Register 12 11 10 Reserved r0 r0 r0 4 NMIIE rw-0 3 VMAIE rw-0 2 Reserved r0 9 r0 1 OFIE (2) rw-0 8 r0 0 WDTIE (3) rw-0 Bit 15-8 7 Field Reserved JMBOUTIE 6 JMBINIE 5 ACCVIE 4 NMIIE 3 VMAIE 2 Reserved 1 OFIE 0 WDTIE Type R RW RW RW RW RW R RW RW Table 1-12. SFRIE1 Register Description Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. JTAG mailbox output interrupt enable flag 0b = Interrupts disabled 1b = Interrupts enabled JTAG mailbox input interrupt enable flag 0b = Interrupts disabled 1b = Interrupts enabled Flash controller access violation interrupt enable flag 0b = Interrupts disabled 1b = Interrupts enabled NMI pin interrupt enable flag 0b = Interrupts disabled 1b = Interrupts enabled Vacant memory access interrupt enable flag 0b = Interrupts disabled 1b = Interrupts enabled Reserved. Always reads as 0. Oscillator fault interrupt enable flag 0b = Interrupts disabled 1b = Interrupts enabled Watchdog timer interrupt enable. This bit enables the WDTIFG interrupt for interval timer mode. It is not necessary to set this bit for watchdog mode. Because other bits in ~IE1 may be used for other modules, it is recommended to set or clear this bit using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instruction 0b = Interrupts disabled 1b = Interrupts enabled 84 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com 1.14.2 SFRIFG1 Register Interrupt Flag Register SFR Registers 15 14 13 r0 r0 r0 7 JMBOUTIFG rw-(1) 6 JMBINIFG rw-(0) 5 Reserved r0 (1) See the UCS chapter for details. (2) See the WDT_A chapter for details. Figure 1-9. SFRIFG1 Register 12 11 10 Reserved r0 r0 r0 4 NMIIFG rw-0 3 VMAIFG rw-0 2 Reserved r0 9 r0 1 OFIFG (1) rw-(1) 8 r0 0 WDTIFG (2) rw-0 Bit 15-8 7 Field Reserved JMBOUTIFG 6 JMBINIFG 5 Reserved 4 NMIIFG 3 VMAIFG 2 Reserved 1 OFIFG Type R RW RW R RW RW R RW Table 1-13. SFRIFG1 Register Description Reset 0h 1h 0h 0h 0h 0h 0h 1h Description Reserved. Always reads as 0. JTAG mailbox output interrupt flag 0b = No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is cleared automatically when JMBO0 has been written with a new message to the JTAG module by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is cleared automatically when both JMBO0 and JMBO1 have been written with new messages to the JTAG module by the CPU. This bit is also cleared when the associated vector in SYSUNIV has been read. 1b = Interrupt pending, JMBO registers are ready for new messages. In 16-bit mode (JMBMODE = 0), JMBO0 has been received by the JTAG module and is ready for a new message from the CPU. In 32-bit mode (JMBMODE = 1) , JMBO0 and JMBO1 have been received by the JTAG module and are ready for new messages from the CPU. JTAG mailbox input interrupt flag 0b = No interrupt pending. When in 16-bit mode (JMBMODE = 0), this bit is cleared automatically when JMBI0 is read by the CPU. When in 32-bit mode (JMBMODE = 1), this bit is cleared automatically when both JMBI0 and JMBI1 have been read by the CPU. This bit is also cleared when the associated vector in SYSUNIV has been read 1b = Interrupt pending, a message is waiting in the JMBIN registers. In 16-bit mode (JMBMODE = 0) when JMBI0 has been written by the JTAG module. In 32-bit mode (JMBMODE = 1) when JMBI0 and JMBI1 have been written by the JTAG module. Reserved. Always reads as 0. NMI pin interrupt flag 0b = No interrupt pending 1b = Interrupt pending Vacant memory access interrupt flag 0b = No interrupt pending 1b = Interrupt pending Reserved. Always reads as 0. Oscillator fault interrupt flag 0b = No interrupt pending 1b = Interrupt pending SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 85 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated SFR Registers Bit Field 0 WDTIFG www.ti.com Table 1-13. SFRIFG1 Register Description (continued) Type RW Reset 0h Description Watchdog timer interrupt flag. In watchdog mode, WDTIFG will self clear upon a watchdog timeout event. The SYSRSTIV can be read to determine if the reset was caused by a watchdog timeout event. In interval mode, WDTIFG is reset automatically by servicing the interrupt, or can be reset by software. Because other bits in ~IFG1 may be used for other modules, it is recommended to set or clear WDTIFG by using BIS.B or BIC.B instructions, rather than MOV.B or CLR.B instructions. 0b = No interrupt pending 1b = Interrupt pending 86 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com 1.14.3 SFRRPCR Register Reset Pin Control Register SFR Registers Figure 1-10. SFRRPCR Register 15 14 13 12 11 10 Reserved r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 Reserved SYSRSTRE(1) SYSRSTUP(1) r0 r0 r0 r0 rw-1 rw-1 (1) All devices except the MSP430F5438 (non-A) default to pullup enabled on the reset pin. 9 r0 1 SYSNMIIES rw-0 8 r0 0 SYSNMI rw-0 Bit 15-4 3 Field Reserved SYSRSTRE 2 SYSRSTUP 1 SYSNMIIES 0 SYSNMI Type R RW RW RW RW Table 1-14. SFRRPCR Register Description Reset 0h 1h 1h 0h 0h Description Reserved. Always reads as 0. Reset pin resistor enable 0b = Pullup/pulldown resistor at the RST/NMI pin is disabled 1b = Pullup/pulldown resistor at the RST/NMI pin is enabled Reset resistor pin pullup/pulldown 0b = Pulldown is selected 1b = Pullup is selected NMI edge select. This bit selects the interrupt edge for the NMI when SYSNMI = 1. Modifying this bit can trigger an NMI. Modify this bit when SYSNMI = 0 to avoid triggering an accidental NMI. 0b = NMI on rising edge 1b = NMI on falling edge NMI select. This bit selects the function for the RST/NMI pin. 0b = Reset function 1b = NMI function SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 87 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated SYS Registers www.ti.com 1.15 SYS Registers The SYS configuration registers are listed in Table 1-16 and the base address is listed in Table 1-15. A detailed description of each register and its bits is also provided. Each register starts at a word boundary. Either word or byte data can be written to the SYS configuration registers. NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15). Table 1-15. SYS Base Address Module SYS Base Address 00180h Offset 00h 00h 01h 02h 02h 03h 06h 06h 07h 08h 08h 09h 0Ah 0Ah 0Bh 0Ch 0Ch 0Dh 0Eh 0Eh 0Fh 18h 1Ah 1Ch 1Eh Acronym SYSCTL SYSCTL_L SYSCTL_H SYSBSLC SYSBSLC_L SYSBSLC_H SYSJMBC SYSJMBC_L SYSJMBC_H SYSJMBI0 SYSJMBI0_L SYSJMBI0_H SYSJMBI1 SYSJMBI1_L SYSJMBI1_H SYSJMBO0 SYSJMBO0_L SYSJMBO0_H SYSJMBO1 SYSJMBO1_L SYSJMBO1_H SYSBERRIV SYSUNIV SYSSNIV SYSRSTIV Table 1-16. SYS Registers Register Name System Control Bootstrap Loader Configuration JTAG Mailbox Control JTAG Mailbox Input 0 JTAG Mailbox Input 1 JTAG Mailbox Output 0 JTAG Mailbox Output 1 Bus Error Vector Generator User NMI Vector Generator System NMI Vector Generator Reset Vector Generator Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read Read Read Read Access Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Word Word Word Reset 0000h 00h 00h 0003h 03h 00h 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h 0000h 0000h 0000h 0002h Section Section 1.15.1 Section 1.15.2 Section 1.15.3 Section 1.15.4 Section 1.15.5 Section 1.15.6 Section 1.15.7 Section 1.15.11 Section 1.15.8 Section 1.15.9 Section 1.15.10 88 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com 1.15.1 SYSCTL Register SYS Control Register 15 14 r0 r0 7 6 Reserved r0 r0 13 r0 5 SYSJTAGPIN rw-[0] Figure 1-11. SYSCTL Register 12 11 10 Reserved r0 r0 r0 4 SYSBSLIND r-0 3 Reserved r0 2 SYSPMMPE rw-[0] SYS Registers 9 r0 1 Reserved r0 8 r0 0 SYSRIVECT rw-[0] Bit 15-6 5 Field Reserved SYSJTAGPIN 4 SYSBSLIND 3 Reserved 2 SYSPMMPE 1 Reserved 0 SYSRIVECT Type R RW RW R RW R RW Table 1-17. SYSCTL Register Description Reset 0h 0h 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. Dedicated JTAG pins enable. Setting this bit disables the shared functionality of the JTAG pins and permanently enables the JTAG function. This bit can be set only once. After it is set, it remains set until a BOR occurs. 0b = Shared JTAG pins (JTAG mode selectable by SBW sequence) 1b = Dedicated JTAG pins (explicit 4-wire JTAG mode selection) BSL entry indication. This bit indicates a BSL entry sequence detected on the Spy-Bi-Wire pins. 0b = No BSL entry sequence detected 1b = BSL entry sequence detected Reserved. Always reads as 0. PMM access protect. This controls the accessibility of the PMM control registers. Once set to 1, it only can be cleared by a BOR. 0b = Access from anywhere in memory 1b = Access only from the protected BSL segments Reserved. Always reads as 0. RAM-based interrupt vectors 0b = Interrupt vectors generated with end address TOP of lower 64KB of flash, FFFFh 1b = Interrupt vectors generated with end address TOP of RAM SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 89 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated SYS Registers 1.15.2 SYSBSLC Register Bootstrap Loader Configuration Register 15 SYSBSLPE rw-[0] 7 14 SYSBSLOFF rw-[0] 6 r0 r0 13 r0 5 Reserved r0 Figure 1-12. SYSBSLC Register 12 11 10 Reserved r0 r0 r0 4 3 2 SYSBSLR r0 r0 rw-[0] www.ti.com 9 8 r0 r0 1 0 SYSBSLSIZE rw-[1] rw-[1] Bit Field 15 SYSBSLPE 14 SYSBSLOFF 13-3 2 Reserved SYSBSLR 1-0 SYSBSLSIZE Type RW RW R RW RW Table 1-18. SYSBSLC Register Description Reset 0h 0h 0h 0h 03h Description Bootstrap loader memory protection enable for the size covered in SYSBSLSIZE. By default, this bit is cleared by hardware with a BOR event (as indicated above), however the boot code that checks for an available BSL may set this bit by software to protect the BSL. Because devices normally come with a TI BSL preprogrammed and protected, the boot code sets this bit. 0b = Area not protected. Read, program, and erase of BSL memory is possible. 1b = Area protected Bootstrap loader memory disable for the size covered in SYSBSLSIZE 0b = BSL memory is addressed when this area is read. 1b = BSL memory behaves like vacant memory. Reads cause 3FFFh to be read. Fetches cause JMP $ to be executed. Reserved. Always reads as 0. RAM assigned to BSL 0b = No RAM assigned to BSL area 1b = Lowest 16 bytes of RAM assigned to BSL Bootstrap loader size. Defines the space and size of flash memory that is reserved for the BSL. 00b = Size: BSL segment 3 01b = Size: BSL segments 2 and 3 10b = Size: BSL segments 1, 2, and 3 11b = Size: BSL segments 0, 1, 2, and 3 90 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com 1.15.3 SYSJMBC Register JTAG Mailbox Control Register 15 14 13 r0 r0 7 JMBCLR1OFF rw-(0) 6 JMBCLR0OFF rw-(0) r0 5 Reserved r0 Figure 1-13. SYSJMBC Register 12 11 10 Reserved r0 r0 r0 4 JMBM0DE rw-0 3 JMBOUT1FG r-(1) 2 JMBOUT0FG r-(1) SYS Registers 9 r0 1 JMBIN1FG rw-(0) 8 r0 0 JMBIN0FG rw-(0) Bit 15-8 7 Field Reserved JMBCLR1OFF 6 JMBCLR0OFF 5 Reserved 4 JMBMODE 3 JMBOUT1FG 2 JMBOUT0FG 1 JMBIN1FG 0 JMBIN0FG Type R RW RW R RW RW RW RW RW Table 1-19. SYSJMBC Register Description Reset 0h 0h 0h 0h 0h 1h 1h 0h 0h Description Reserved. Always reads as 0. Incoming JTAG Mailbox 1 flag auto-clear disable 0b = JMBIN1FG cleared on read of JMB1IN register 1b = JMBIN1FG cleared by software Incoming JTAG Mailbox 0 flag auto-clear disable 0b = JMBIN0FG cleared on read of JMB0IN register 1b = JMBIN0FG cleared by software Reserved. Always reads as 0. This bit defines the operation mode of JMB for JMBI0/1 and JMBO0/1. Before switching this bit, pad and flush out any partial content to avoid data drops. 0b = 16-bit transfers using JMBO0 and JMBI0 only 1b = 32-bit transfers using JMBO0/1 and JMBI0/1 Outgoing JTAG Mailbox 1 flag. This bit is cleared automatically when a message is written to the upper byte of JMBO1 or as word access (by the CPU, DMA,…) and is set after the message was read by JTAG. 0b = JMBO1 is not ready to receive new data. 1b = JMBO1 is ready to receive new data. Outgoing JTAG Mailbox 0 flag. This bit is cleared automatically when a message is written to the upper byte of JMBO0 or as word access (by the CPU, DMA,…) and is set after the message was read by JTAG. 0b = JMBO0 is not ready to receive new data. 1b = JMBO0 is ready to receive new data. Incoming JTAG Mailbox 1 flag. This bit is set when a new message (provided by JTAG) is available in JMBI1. This flag is cleared automatically on read of JMBI1 when JMBCLR1OFF = 0 (auto clear mode). On JMBCLR1OFF = 1, JMBIN1FG needs to be cleared by SW. 0b = JMBI1 has no new data. 1b = JMBI1 has new data available. Incoming JTAG Mailbox 0 flag. This bit is set when a new message (provided by JTAG) is available in JMBI0. This flag is cleared automatically on read of JMBI0 when JMBCLR0OFF = 0 (auto clear mode). On JMBCLR0OFF = 1, JMBIN0FG needs to be cleared by SW. 0b = JMBI1 has no new data. 1b = JMBI1 has new data available. SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 91 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated SYS Registers 1.15.4 SYSJMBI0 Register JTAG Mailbox Input 0 Register Figure 1-14. SYSJMBI0 Register 15 14 13 12 11 10 9 MSGHI r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 MSGLO r-0 r-0 r-0 r-0 r-0 r-0 r-0 Bit 15-8 7-0 Field MSGHI MSGLO Type R R Table 1-20. SYSJMBI0 Register Description Reset 0h 0h Description JTAG mailbox incoming message high byte JTAG mailbox incoming message low byte 1.15.5 SYSJMBI1 Register JTAG Mailbox Input 0 Register Figure 1-15. SYSJMBI1 Register 15 14 13 12 11 10 9 MSGHI r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 MSGLO r-0 r-0 r-0 r-0 r-0 r-0 r-0 Bit 15-8 7-0 Field MSGHI MSGLO Type R R Table 1-21. SYSJMBI1 Register Description Reset 0h 0h Description JTAG mailbox incoming message high byte JTAG mailbox incoming message low byte www.ti.com 8 r-0 0 r-0 8 r-0 0 r-0 92 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com 1.15.6 SYSJMBO0 Register JTAG Mailbox Output 0 Register Figure 1-16. SYSJMBO0 Register 15 14 13 12 11 10 MSGHI rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 MSGL0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit 15-8 7-0 Field MSGHI MSGLO Table 1-22. SYSJMBO0 Register Description Type RW RW Reset 0h 0h Description JTAG mailbox outgoing message high byte JTAG mailbox outgoing message low byte 1.15.7 SYSJMBO1 Register JTAG Mailbox Output 1 Register Figure 1-17. SYSJMBO1 Register 15 14 13 12 11 10 MSGHI rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 MSGL0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit 15-8 7-0 Field MSGHI MSGLO Table 1-23. SYSJMBO1 Register Description Type RW RW Reset 0h 0h Description JTAG mailbox outgoing message high byte JTAG mailbox outgoing message low byte SYS Registers 9 8 rw-0 rw-0 1 0 rw-0 rw-0 9 8 rw-0 rw-0 1 0 rw-0 rw-0 SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 93 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated SYS Registers 1.15.8 SYSUNIV Register User NMI Vector Register www.ti.com NOTE: Additional events for more complex devices are appended to this table; sources that are removed reduce the length of this table. The vectors are expected to be accessed symbolic only with the corresponding include file of the device in use. 15 14 r0 r0 7 6 r0 r0 Bit 15-0 Field SYSUNIV Figure 1-18. SYSUNIV Register 13 12 11 10 9 8 SYSUNVEC r0 r0 r0 r0 r0 r0 5 4 3 2 1 0 SYSUNVEC r0 r-0 r-0 r-0 r-0 r0 Type R Table 1-24. SYSUNIV Register Description Reset 0h Description User NMI vector. Generates a value that can be used as address offset for fast interrupt service routine handling. Writing to this register clears all pending user NMI flags. 00h = No interrupt pending 02h = NMIIFG interrupt pending (highest priority) 04h = OFIFG interrupt pending 06h = ACCVIFG interrupt pending 08h = BUSIFG interrupt pending (Not present on all devices. See device-specific datasheet) 94 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com 1.15.9 SYSSNIV Register System NMI Vector Register SYS Registers NOTE: Additional events for more complex devices are appended to this table; sources that are removed reduce the length of this table. The vectors are expected to be accessed symbolic only with the corresponding include file of the used device. 15 14 r0 r0 7 6 r0 r0 Bit 15-0 Field SYSSNIV Figure 1-19. SYSSNIV Register 13 12 11 10 9 8 SYSSNVEC r0 r0 r0 r0 r0 r0 5 4 3 2 1 0 SYSSNVEC r0 r-0 r-0 r-0 r-0 r0 Type R Table 1-25. SYSSNIV Register Description Reset 0h Description System NMI vector. Generates a value that can be used as address offset for fast interrupt service routine handling. Writing to this register clears all pending system NMI flags. 00h = No interrupt pending 02h = SVMLIFG interrupt pending (highest priority) 04h = SVMHIFG interrupt pending 06h = SVSMLDLYIFG interrupt pending 08h = SVSMHDLYIFG interrupt pending 0Ah = VMAIFG interrupt pending 0Ch = JMBINIFG interrupt pending 0Eh = JMBOUTIFG interrupt pending 10h = SVMLVLRIFG interrupt pending 12h = SVMHVLRIFG interrupt pending 14h = Reserved SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 95 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated SYS Registers www.ti.com 1.15.10 SYSRSTIV Register Reset Interrupt Vector Register NOTE: Additional events for more complex devices are appended to this table; sources that are removed reduce the length of this table. The vectors are expected to be accessed symbolic only with the corresponding include file of the used device. Figure 1-20. SYSRSTIV Register 15 14 13 12 11 10 9 8 SYSRSTVEC r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 SYSRSTVEC r0 r0 r (1) r (1) r (1) r (1) r (1) r0 (1) Reset value depends on reset source. Bit 15-0 Field SYSRSTIV Type R (1) Reset value depends on reset source. Table 1-26. SYSRSTIV Register Description Reset 02h3Eh (1) Description Reset interrupt vector. Generates a value that can be used as address offset for fast interrupt service routine handling to identify the last cause of a reset (BOR, POR, PUC) . Writing to this register clears all pending reset source flags. 00h = No interrupt pending 02h = Brownout (BOR) (highest priority) 04h = RST/NMI (BOR) 06h = PMMSWBOR (BOR) 08h = Wakeup from LPMx.5 (BOR) 0Ah = Security violation (BOR) 0Ch = SVSL (POR) 0Eh = SVSH (POR) 10h = SVML_OVP (POR) 12h = SVMH_OVP (POR) 14h = PMMSWPOR (POR) 16h = WDT time out (PUC) 18h = WDT password violation (PUC) 1Ah = Flash password violation (PUC) 1Ch = Reserved 1Eh = PERF peripheral/configuration area fetch (PUC) 20h = PMM password violation (PUC) 22h to 3Eh = Reserved 96 System Resets, Interrupts, and Operating Modes, System Control Module SLAU208O – June 2008 – Revised May 2015 (SYS) Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com SYS Registers 1.15.11 SYSBERRIV Register System Bus Error Interrupt Vector Register NOTE: Additional events for more complex devices are appended to this table; sources that are removed reduce the length of this table. The vectors are expected to be accessed symbolic only with the corresponding include file of the used device. Figure 1-21. SYSBERRIV Register 15 14 13 12 11 10 9 8 SYSBERRIV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 SYSBERRIV r0 r0 r0 r-0 r-0 r-0 r-0 r0 Bit 15-0 Field SYSBERRIV Table 1-27. SYSBERRIV Register Description Type R Reset 0h Description System bus error interrupt vector. Generates a value that can be used as an address offset for fast interrupt service routine handling. Writing to this register clears all pending flags. 00h = No interrupt pending 02h = USB module timed out. Wait state time out of 8 clock cycles. 16 clock cycles only on the F552x and F551x devices. 04h = Reserved for future extensions 06h = Reserved for future extensions 08h = Reserved for future extensions SLAU208O – June 2008 – Revised May 2015 System Resets, Interrupts, and Operating Modes, System Control Module 97 Submit Documentation Feedback (SYS) Copyright © 2008–2015, Texas Instruments Incorporated Chapter 2 SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor This chapter describes the operation of the Power Management Module (PMM) and Supply Voltage Supervisor (SVS). Topic ........................................................................................................................... Page 2.1 Power Management Module (PMM) Introduction .................................................... 99 2.2 PMM Operation................................................................................................. 101 2.3 PMM Registers ................................................................................................. 114 98 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Power Management Module (PMM) Introduction 2.1 Power Management Module (PMM) Introduction PMM features include: • Wide supply voltage (DVCC) range: 1.8 V to 3.6 V • Generation of voltage for the device core (VCORE) with up to four programmable levels • Supply voltage supervisor (SVS) for DVCC and VCORE with programmable threshold levels • Supply voltage monitor (SVM) for DVCC and VCORE with programmable threshold levels • Brownout reset (BOR) • Software accessible power-fail indicators • I/O protection during power-fail condition • Software selectable supervisor or monitor state output (optional) The PMM manages all functions related to the power supply and its supervision for the device. Its primary functions are first to generate a supply voltage for the core logic, and second, provide several mechanisms for the supervision and monitoring of both the voltage applied to the device (DVCC) and the voltage generated for the core (VCORE). The PMM uses an integrated low-dropout voltage regulator (LDO) to produce a secondary core voltage (VCORE) from the primary one applied to the device (DVCC). In general, VCORE supplies the CPU, memories (flash and RAM), and the digital modules, while DVCC supplies the I/Os and all analog modules (including the oscillators). The VCORE output is maintained using a dedicated voltage reference. VCORE is programmable up to four steps, to provide only as much power as is needed for the speed that has been selected for the CPU. This enhances power efficiency of the system. The input or primary side of the regulator is referred to in this chapter as its high side. The output or secondary side is referred to in this chapter as its low side. The required minimum voltage for the core depends on the selected MCLK rate. Figure 2-1 shows the relationship between the system frequency for a given core voltage setting, as well as the minimum required voltage applied to the device. Figure 2-1 is only an example—see the device-specific data sheet to determine which core voltage levels are supported and what level of system frequency performance is possible for a given device. System Frequency - MHz f3 3 f2 2 2, 3 f1 1 1, 2 1, 2, 3 f0 0 0, 1 0, 1, 2 0, 1, 2, 3 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 2-1. System Frequency, Supply Voltage, and Core Voltage – See Device-Specific Data Sheet SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 99 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Power Management Module (PMM) Introduction www.ti.com The PMM module provides means for DVCC and VCORE to be supervised and monitored. Both of these functions detect when a voltage falls under a specific threshold. In general, the difference is that supervision results in a power-on reset (POR) event, while monitoring results in the generation of an interrupt flag that software may then handle. As such, DVCC is supervised and monitored by the high-side supervisor (SVSH) and high-side monitor (SVMH), respectively. VCORE is supervised and monitored by the low-side supervisor (SVSL) and low-side monitor (SVML), respectively. Thus, there are four separate supervision and monitoring modules that can be active at any given time. The thresholds enforced by these modules are derived from the same voltage reference used by the regulator to generate VCORE. In addition to the SVSH, SVMH, SVSL, and SVML modules, VCORE is further monitored by the brownout reset (BOR) circuit. As DVCC ramps up from 0 V at power up, the BOR keeps the device in reset until VCORE is at a sufficient level for operation at the default MCLK rate and for the SVSH and SVSL mechanisms to be activated. During operation, the BOR also generates a reset if VCORE falls below a preset threshold. BOR can be used to provide an even lower-power means of monitoring the supply rail if the flexibility of the SVSL is not required. The block diagram of the PMM is shown in Figure 2-2. Control bits PMMCOREV DVCC Regulator VCORE SVSH SVMH Reference SVSL SVML BOR To reset logic Ports ON NOR OR To reset logic Figure 2-2. PMM Block Diagram 100 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 2.2 PMM Operation PMM Operation 2.2.1 VCORE and the Regulator DVCC can be powered from a wide input voltage range, but the core logic of the device must be kept at a voltage lower than what this range allows. For this reason, a regulator has been integrated into the PMM. The regulator derives the necessary core voltage (VCORE) from DVCC. Higher MCLK speeds require higher levels of VCORE. Higher levels of VCORE consume more power, and so the core voltage has been made programmable in up to four steps to allow it to provide only as much power as is required for a given MCLK setting. The level is controlled by the PMMCOREV bits. Note that the default setting, the lowest value of PMMCOREV, enables operation of MCLK over a very wide frequency range. As such, no PMM changes are required for many applications. See the device-specific data sheet for performance characteristics and core step levels supported. Before increasing MCLK to a higher speed, it is necessary for software to ensure that the VCORE level is sufficiently high for the chosen frequency. Failure to do so may force the CPU to attempt operation without sufficient power, which can cause unpredictable results. See Section 2.2.4 for more information on the appropriate procedure to raise VCORE for higher MCLK frequencies. The regulator supports two different load settings to optimize power. The high-current mode is required when: • The CPU is in active, LPM0, or LPM1 modes • A clock source greater than 32 kHz is used to drive any module • An interrupt is executed Otherwise, the low-current mode is used. The hardware controls the load settings automatically, according to the criteria above. 2.2.2 Supply Voltage Supervisor and Monitor The high-side supervisor and monitor (SVSH and SVMH) oversee DVCC, and the low-side supervisor and monitor (SVSL and SVML) oversee VCORE. By default, all of these modules are active, but each can be disabled using the corresponding enable bit (SVSHE, SVMHE, SVSLE, SVMLE), resulting in some power savings. Typical application scenarios for supply voltage supervisors and monitors are: • High-Side Supervisor, SVSH – Supervision of external power supply (DVCC) – Device reset because of low battery or supply voltage • High-Side Monitor, SVMH – Monitoring of external power supply (DVCC) – Detection of low battery voltage (Pre-warning) • Low-Side Supervisor, SVSL – Supervision of internal core voltage used to supply digital core – Device reset because of disruptive conditions at external VCORE pin (for example a short). The internal core voltage never drops below a critical level if parasitic events at the external VCORE pin are avoided. • Low-Side Monitor, SVML – Monitoring of internal core voltage used to supply digital core – Detection of correct internal voltage levels when changing (especially increasing) the core voltage level before changing, for example, to higher system frequencies (also see Section 2.2.4). SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 101 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Operation www.ti.com 2.2.2.1 SVS and SVM Thresholds The voltage thresholds enforced by the SVS and SVM modules are selectable. Table 2-1 shows the SVS and SVM threshold registers, the voltage threshold they control, and the number of threshold options. Table 2-1. SVS and SVM Thresholds Register Description Threshold SVSHRVL SVSH reset voltage level SVSH_IT- SVSMHRRL SVSH, SVMH reset release voltage level SVSH_IT+, SVMH SVSLRVL SVSL reset voltage level SVSL_IT- SVSMLRRL SVSL, SVML reset release voltage level SVSL_IT+, SVML (1) The register settings support up to eight levels (0 through 7); however, levels 3 through 7 are identical. Available Steps 4 8 4 4 (1) 2.2.2.1.1 Recommended SVSL Settings For each of the core voltages, there are two supply voltage supervisor levels available. The SVSLRVL bits define the voltage level of VCORE below which the reset is activated. The SVSMLRRL bits define the voltage level of VCORE at which the reset is released. Although various settings can be chosen, there is one set of SVSLRVL and SVSMLRRL settings that is well suited for each core voltage selected by PMMCOREV. By default, an SVSL event always generates a POR (SVSLPE = 1), and it is recommended to always configure SVSLPE = 1 for reliable device startup. The most commonly used and recommended settings are shown in Table 2-2. PMMCOREV[1:0] 00 01 10 11 Table 2-2. Recommended SVSL Settings DVCC (V) ≥ 1.8 ≥ 2.0 ≥ 2.2 ≥ 2.4 SVSLRVL[1:0] Sets SVSL_IT- Level 00 01 10 11 SVSMLRRL[2:0] Sets SVSL_IT+ and SVML levels 000 001 010 011 2.2.2.1.1.1 Recommended SVSH Settings For the high-side supply, there are two supply voltage supervisor levels available. The SVSMHRRL bits define the voltage level of DVCC at which the reset is released. The SVSHRVL register defines the voltage level of DVCC below which the reset is turned on. These settings should be selected according to the minimum voltages required for device operation in a given application, as well as system power supply characteristics. See the device-specific data sheet for threshold values corresponding to the settings shown here. Although various settings are available, the most common are based on the maximum frequency required which, in turn, determines the minimum DVCC level supervised. By default, an SVSH event always generates a POR (SVSHPE = 1), and it is recommended to always configure SVSHPE = 1 for reliable device startup. The most commonly used and recommended settings are shown in Table 4-2 . fSYS Max (MHz) 8 12 20 25 Table 2-3. Recommended SVSH Settings DVCC (V) >1.8 >2.0 >2.2 >2.4 SVSHRVL[1:0] Sets SVSH_IT- Level 00 01 10 11 SVSMHRRL[2:0] Sets SVSH_IT+ and SVMH Levels 000 001 010 011 PMMCOREV[1:0] 00 01 10 11 102 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com PMM Operation The available voltage threshold settings of SVSH and SVMH are dependent on the voltage level setting of VCORE. Table 2-4 summarizes all of the possible settings available. All other settings not listed are invalid and should not be used. Also SVSMHRRL must always be equal or larger than SVSHRVL. Figure 2-3 shows the available settings for the SVMH. Table 2-4. Available SVSH and SVMH Settings Versus VCORE Settings PMMCOREV[1:0] 00 01 10 11 SVSHRVL[1:0] Sets SVSH_IT- Level 00 through 11 00 through 11 00 through 11 00 through 11 SVSMHRRL[2:0] Sets SVSH_IT+ and SVMH Levels 000 through 011 001 through 100 010 through 101 011 through 111 111 (7) 110 (6) Invalid 101 (5) SVSMHRRLx 100 (4) 011 (3) 010 (2) Valid 001 (1) 000 (0) Invalid 00 01 10 11 PMMCOREVx Figure 2-3. Available SVMH Settings Versus VCORE Settings The behavior of the SVS and SVM according to these thresholds is best portrayed graphically. Figure 2-4 shows how the supervisors and monitors respond to various supply failure conditions. As Figure 2-4 shows, there is hysteresis built into the supervision thresholds, such that the thresholds in force depend on whether the voltage rail is going up or down. There is no hysteresis in the monitoring thresholds. NOTE: SVS Hysteresis There is only a reliable hysteresis if the bit setting for SVSMHRRL is equal or larger than the bit setting for SVSHRVL. Thus you must select a SVSMHRRL setting that is equal or larger than the SVSHRVL setting. SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 103 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Operation Voltage DVCC SVMH,SVSH_IT+ SVSH_IT- VCORE SVML,SVSL_IT+ SVSL_IT- www.ti.com Set SVMHIFG Set SVMHVLRIFG Set SVSHIFG Set SVMLIFG Set SVMLVLRIFG Set SVSLIFG POR Time Figure 2-4. High-Side and Low-Side Voltage Failure and Resulting PMM Actions 104 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com PMM Operation 2.2.2.2 High-Side Supervisor (SVSH) and High-Side Monitor (SVMH) The SVSH and SVMH modules are enabled by default. They can be disabled by clearing the SVSHE and SVMHE bits, respectively. Their block diagrams are shown in Figure 2-5. SVMHVLRPE SVMHOVPE 0 Set POR 1 SVMHIE SVMH Interrupt SVMHFP SVMHE SVMH ON SVSMHRRL Set IFG Set IFG SVMHVLRIE SVMHIFG SVMHVLRIFG SVMH Reached Interrupt SVSHFP SVSH ON SVSHE SVSHMD High power mode LPM or SVSMHCTL change SVSMHEVM SVSHRVL EN SVSHPE Set IFG SVSMHDLYIE Figure 2-5. High-Side SVS and SVM Set SVSHIFG Set POR SVSMHDLYIFG High Side Delay Interrupt If DVCC falls below the SVSH level, SVSHIFG (SVSH interrupt flag) is set. If DVCC remains below the SVSH level and software attempts to clear SVSHIFG, it is immediately set again by hardware. If the SVSHPE (SVSH POR enable) bit is set when SVSHIFG gets set, a POR is generated. If DVCC falls below the SVMH level, SVMHIFG (SVMH interrupt flag) is set. If DVCC remains below the SVMH level and software attempts to clear SVMHIFG, it is immediately set again by hardware. If the SVMHIE (SVMH interrupt enable) bit is set when SVMHIFG gets set, an interrupt is generated. If a POR is desired when SVMHIFG is set, the SVMH can be configured to do so by setting the SVMHVLRPE (SVMH voltage level reached POR enable) bit while SVMHOVPE bit is cleared. If DVCC rises above the SVMH level, the SVMHVLRIFG (SVMH voltage level reached) interrupt flag is set. If SVMHVLRIE (SVMH voltage level reached interrupt enable) is set when this occurs, an interrupt is also generated. Alternatively the SVMH module can be used for overvoltage detection, but only with the highest core voltage setting (PMMCOREV = 11b), . This is accomplished by setting the SVMHOVPE (SVMH overvoltage POR enable) bit in addition to setting SVMHVLRPE. Under these conditions, if a rising DVCC exceeds safe device operation, a POR is generated. SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 105 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Operation www.ti.com The SVSH and SVMH modules have configurable performance modes for power-saving operation. (See Section 2.2.9 for more information.) If these SVSH and SVMH power modes are modified, or if a voltage level is modified, a delay element masks the interrupts and POR sources until the SVSH and SVMH circuits have settled. When SVSMHDLYST (delay status) reads zero, the delay has expired. In addition, the SVSMHDLYIFG (SVSH and SVMH delay expired) interrupt flag is set. If the SVSMHDLYIE (SVSH and SVMH delay expired interrupt enable) is set when this occurs, an interrupt is also generated. In case of power-fail conditions, setting SVSHMD causes the SVSH interrupt flag to be set in LPM2, LPM3, and LPM4. If SVSHMD is not set, the SVSH interrupt flag is not set in LPM2, LPM3, and LPM4. In addition, all SVSH and SVMH events can be masked by setting SVSMHEVM. For most applications, SVSMHEVM should be cleared. All the interrupt flags of SVSH and SVMH remain set until cleared by a BOR or by software. 2.2.2.3 Low-Side Supervisor (SVSL) and Low-Side Monitor (SVML) The SVSL and SVML modules are enabled by default. They can be disabled by clearing SVSLE and SVMLE bits, respectively. Their block diagrams are shown in Figure 2-6. SVMLVLRPE SVMLOVPE 0 Set POR 1 SVMLIE SVML Interrupt SVMLFP SVMLE SVML ON SVSMLRRL Set IFG Set IFG SVMLVLRIE SVMLIFG SVMLVLRIFG SVML Reached Interrupt SVSLFP SVSL ON SVSLE SVSLMD High power mode LPM or SVSMLCTL change SVSMLEVM SVSLRVL EN SVSLPE Set IFG SVSMLDLYIE Figure 2-6. Low-Side SVS and SVM Set SVSLIFG Set POR SVSMLDLYIFG Low Side Delay Interrupt If VCORE falls below the SVSL level, SVSLIFG (SVSL interrupt flag) is set. If VCORE remains below the SVSL level and software attempts to clear SVSLIFG, it is immediately set again by hardware. If the SVSLPE (SVSL POR enable) bit is set when SVSLIFG gets set, a POR is generated. 106 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com PMM Operation If VCORE falls below the SVML level, SVMLIFG (SVML interrupt flag) is set. If VCORE remains below the SVML level and software attempts to clear SVMLIFG, it is immediately set again by hardware. If the SVMLIE (SVML interrupt enable) bit is set when SVMLIFG gets set, an interrupt is generated. If a POR is desired when SVMLIFG is set, the SVML can be configured to do so by setting the SVMLVLRPE (SVML voltage level reached POR enable) bit while SVMLOVPE bit is cleared. If VCORE rises above the SVML level, the SVMLVLRIFG (SVML voltage level reached) interrupt flag is set. If SVMLVLRIE (SVML voltage level reached interrupt enable) is set when this occurs, an interrupt is also generated. The SVML module can also be used for overvoltage detection. This is accomplished by setting the SVMLOVPE (SVML overvoltage POR enable) bit, in addition to setting SVMLVLRPE. Under these conditions, if VCORE exceeds safe device operation, a POR is generated. The SVSL and SVML modules have configurable performance modes for power-saving operation. (See Section 2.2.9 for more information.) If these SVSL and SVML power modes are modified, or if a voltage level is modified, a delay element masks the interrupts and POR sources until the SVSL and SVML circuits have settled. When SVSMLDLYST (delay status) reads zero, the delay has expired. In addition, the SVSMLDLYIFG (SVSL/SVML delay expired) interrupt flag is set. If the SVSMLDLYIE (SVSL and SVML delay expired interrupt enable) is set when this occurs, an interrupt is also generated. In case of power-fail conditions, setting SVSLMD causes the SVSL interrupt flag to be set in LPM2, LPM3, and LPM4. If SVSLMD is not set, the SVSL interrupt flag is not set in LPM2, LPM3, and LPM4. In addition, all SVSL and SVML events can be masked by setting SVSMLEVM. For most applications, SVSMLEVM should be cleared. All the interrupt flags of SVSL and SVML remain set until cleared by a BOR or by software. 2.2.3 Supply Voltage Supervisor and Monitor - Power-Up When the device is powering up, the SVSH and SVSL functions are enabled by default. Initially, DVCC is low, and therefore the PMM holds the device in POR reset. When both the SVSH and SVSL levels are met, the reset is released. Figure 2-7 shows this process. Voltage DVCC SVSH_IT+ VCORE SVSL_IT+ Reset from SVSH Reset from SVSL POR Time Figure 2-7. PMM Action at Device Power-Up After this point, both voltage domains are supervised and monitored while the respective modules are enabled. SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 107 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Operation www.ti.com 2.2.4 Increasing VCORE to Support Higher MCLK Frequencies With a reset, VCORE and all the PMM thresholds, default to their lowest possible levels. These default settings allow a wide range of MCLK operation, and in many applications no change to these levels is required. However, if the application requires the performance provided by higher MCLK frequencies, software should ensure that VCORE has been raised to a sufficient voltage level before changing MCLK, since failing to supply sufficient voltage to the CPU could produce unpredictable results. For a given device, minimum VCORE levels required for maximum MCLK frequencies have been established (See the device data sheet for specific values). After setting PMMCOREV to increase VCORE, there is a time delay until the new voltage has been established. Software must not raise MCLK until the necessary core voltage has settled. SVML can be used to verify that VCORE has met the required minimum value, prior to increasing MCLK. Figure 2-8 shows this procedure. Voltage SVML 1 3 4 2 SVSL VCORE 6 5 Time Figure 2-8. Changing VCORE and SVML and SVSL Levels It is critical that the VCORE level be increased by only one level at a time. The following steps 1 through 4 show the procedure to increase VCORE by one level. This sequence is repeated to change the VCORE level until the targeted level is obtained: • Step 1: Make sure that DVCC has settled before you continue with the next steps. • Step 2: Program the SVMH and SVSH to the next level. This makes sure that DVCC is high enough for the next VCORE level. • Step 3: Program the SVML to the next level and wait until SVSMLDLYIFG is one. • Step 4: Program PMMCOREV to the next VCORE level. • Step 5: Wait until SVMLVLRIFG flag is one. It indicates that the core voltage reached the level you programmed in Step 4. • Step 6: Program the SVSL to the next level. As a reference, the following is a C code example for increasing VCORE. The sample libraries provide routines for increasing and decreasing the VCORE and should be used whenever possible. ; C Code example for increasing core voltage. ; Note: Change core voltage one level at a time. void SetVCoreUp (unsigned int level) { // Open PMM registers for write access PMMCTL0_H = 0xA5; // Make sure no flags are set for iterative sequences while ((PMMIFG & SVSMHDLYIFG) == 0); while ((PMMIFG & SVSMLDLYIFG) == 0); // Set SVS/SVM high side new level SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level; // Set SVM low side to new level SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level; // Wait till SVM is settled while ((PMMIFG & SVSMLDLYIFG) == 0); 108 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com // Clear already set flags PMMIFG &= ~(SVMLVLRIFG + SVMLIFG); // Set VCore to new level PMMCTL0_L = PMMCOREV0 * level; // Wait till new level reached if ((PMMIFG & SVMLIFG)) while ((PMMIFG & SVMLVLRIFG) == 0); // Set SVS/SVM low side to new level SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level; // Lock PMM registers for write access PMMCTL0_H = 0x00; } PMM Operation NOTE: See the MSP430x5xx and MSP430x6xx Core Libraries (SLAA448). These libraries contain useful and ready-to-use functions for easily configuring and using the PMM module. 2.2.5 Decreasing VCORE for Power Optimization The risk posed by increasing MCLK frequency does not exist when decreasing MCLK from the current VCORE or higher settings, because higher VCORE levels can still support MCLK frequencies below the ones for which they were intended. However, significant power efficiency gains can be made by operating VCORE at the lowest value required for a given MCLK frequency. It is critical that the VCORE level be decreased by only one level at a time. The following steps show the procedure to decrease VCORE by one level. This sequence is repeated to change the VCORE level until the targeted level is obtained: The following steps show the procedure to decrease VCORE: • Step 1: Program the SVML and SVSL to the new level and wait for (SVSMLDLYIFG) to be set. • Step 2: Program PMMCOREV to the new VCORE level. It is critical when lowering the VCORE setting that the maximum MCLK frequency for the new VCORE setting is not violated (see the device-specific data sheet). 2.2.6 Transition From LPM3 and LPM4 Modes to AM The LDO requires time to settle when the application transitions from low-power modes to active modes. If a transition from LPM3 or LPM4 occurs and the devices does not stay in active mode long enough, the LDO does not have time to settle sufficiently. Circuitry inside the LDO ensures that the LDO has its minimum required time to settle to its proper operating voltage. The circuitry ensures that every eighth transition from LPM3 or LPM4 causes the LDO to remain on long enough to properly settle. This is handled automatically and requires no setting by the application. 2.2.7 LPM3.5 and LPM4.5 LPM3.5 and LPM4.5 are additional low-power modes in which the regulator of the PMM is completely disabled, providing additional power savings. Not all devices support all LPMx.5 modes, so see the device-specific data sheet. Because there is no power supplied to VCORE during LPMx.5, the CPU and all digital modules including RAM are unpowered. This disables the entire device and, as a result, the contents of the registers and RAM are lost. Any essential values should be stored to flash prior to entering LPMx.5. PMMREGOFF bit is used to disable the regulator. See the SYS module for complete descriptions and proper uses of LPMx.5. Because the regulator of the PMM is disabled upon entering LPMx.5, all I/O register configurations are lost. Therefore, the configuration of I/O pins must be handled differently to ensure that all pins in the application behave in a controlled manner upon entering and exiting LPMx.5. Properly setting the I/O pins is critical to achieving the lowest possible power consumption in LPMx.5, as well as preventing any possible uncontrolled input or output I/O state in the application. The application has complete control of SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 109 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Operation www.ti.com the I/O pin conditions preventing the possibility of unwanted spurious activity upon entry and exit from LPMx.5. The I/O pin state is held and locked based on the settings prior to LPMx.5 entry. Upon entry into LPMx.5, the LOCKLPM5 bit in PM5CTL0 of the PMM module is set automatically. Note that only the pin condition is retained. All other port configuration register settings are lost. See the Digital I/O chapter for further details. 2.2.8 Brownout Reset (BOR), Software BOR, Software POR The primary function of the brownout reset (BOR) circuit occurs when the device is powering up. It is functional very early in the power-up ramp, generating a POR that initializes the system. It also functions when no SVS is enabled and a brownout condition occurs. It sustains this reset until the input power is sufficient for the logic, for proper reset of the system. In an application, it may be desired to cause a BOR by software. Setting PMMSWBOR causes a softwaredriven BOR. PMMBORIFG is set accordingly. Note that a BOR also initiates a POR and PUC. PMMBORIFG can be cleared by software or by reading SYSRSTIV. Similarly, it is possible to cause a POR by software by setting PMMSWPOR. PMMPORIFG is set accordingly. A POR also initiates a PUC. PMMPORIFG can be cleared by software or by reading SYSRSTIV. Both PMMSWBOR and PMMSWPOR are self clearing. See the SYS module for complete descriptions of BOR, POR, and PUC resets. 2.2.9 SVS and SVM Performance Modes and Wakeup Times The supervisors/monitors can function in one of two modes: normal and full performance. The difference is a tradeoff in response time versus the power consumed; full-performance mode has a faster response time but consumes considerably more power than normal mode. Full-performance mode might be considered in applications in which the decoupling of the external power supply cannot adequately prevent fast spikes on DVCC from occurring, or when the application has a particular intolerance to failure. In such cases, full-performance mode provides an additional layer of protection. There are two ways to control the performance mode: manual and automatic. In manual mode, the normal/full-performance selection is the same for every operational mode except LPMx.5 (the SVS and SVM are always disabled in LPMx.5). In this case, the normal or full-performance selection is made with the SVSHFP, SVMHFP, SVSLFP, or SVMLFP bit, for their respective modules. In automatic mode, hardware changes the normal or full-performance selection depending on the operational mode in effect. The wake-up time of the device from low-power modes is affected by the settings of the SVSL and SVML performance modes as listed in Table 2-6, Table 2-7, Table 2-8, and Table 2-9. The wake-up time from low-power modes is not affected by the settings of the SVSH and SVMH. All wake-ups from LPMx.5 (LPM3.5 or LPM4.5), are defined by the data sheet parametric, t , WAKE-UP-LPM5 regardless of the performance modes for SVSL or SVML, because these are disabled in LPMx.5. The tables in Section 2.2.9.1 and Section 2.2.9.2 show the required settings to select the control and performance modes for SVSL, SVML, SVSH, and SVMH. NOTE: Low-Power Modes Even if the CPU requests a specific low-power mode, the device might not go into that state because of modules requesting clocks that should be switched off or have higher frequencies or because of modules requesting a higher drive capability of the LDO. The lowpower modes mentioned in the tables assume that the device is actually in the requested state; that is, no module is requesting a deviating clock setting or drive capability. 110 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 2.2.9.1 Low-Side SVS and SVM Control and Performance Mode Selection PMM Operation SVSMLACE 0 0 1 1 Table 2-5. SVSL and SVML Control Mode Selection SVSLMD 0 1 0 1 SVSL Control Mode Automatic (see Table 2-6) Manual (see Table 2-7) Automatic (see Table 2-6) Automatic (see Table 2-6) SVML Control Mode Manual (see Table 2-8) Manual (see Table 2-8) Automatic (see Table 2-9) Automatic (see Table 2-9) SVSLE 0 1 1 1 1 SVSLMD x 0 0 1 1 Table 2-6. SVSL Automatic Performance Control SVSLFP x 0 1 0 1 AM, LPM0, LPM1 SVSL State Off Normal Full performance Normal Full performance LPM2, LPM3, LPM4 SVSL State Off Off Off Off Normal SVSLE 0 1 1 SVSLFP x 0 1 Table 2-7. SVSL Manual Performance Modes AM, LPM0, LPM1 SVSL State Off Normal Full performance LPM2, LPM3, LPM4 SVSL State Off Normal Full performance SVMLE 0 1 1 SVMLFP x 0 1 Table 2-8. SVML Automatic Performance Control AM, LPM0, LPM1 SVML State Off Normal Full performance LPM2, LPM3, LPM4 SVML State Off Off Normal SVMLE 0 1 1 SVMLFP x 0 1 Table 2-9. SVML Manual Performance Modes AM, LPM0, LPM1 SVML State Off Normal Full performance LPM2, LPM3, LPM4 SVML State Off Normal Full performance Wakeup Time LPM2, LPM3, LPM4 tWAKE-UP-FAST tWAKE-UP-SLOW tWAKE-UP-FAST tWAKE-UP-SLOW tWAKE-UP-FAST Wakeup Time LPM2, LPM3, LPM4 tWAKE-UP-FAST tWAKE-UP-SLOW tWAKE-UP-FAST Wakeup Time LPM2, LPM3, LPM4 tWAKE-UP-FAST tWAKE-UP-SLOW tWAKE-UP-FAST Wakeup Time LPM2, LPM3, LPM4 tWAKE-UP-FAST tWAKE-UP-SLOW tWAKE-UP-FAST SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 111 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Operation 2.2.9.2 High-Side SVS and SVM Control and Performance Mode Selection www.ti.com SVSMHACE 0 0 1 1 Table 2-10. SVSH and SVMH Control Mode Selection SVSHMD 0 1 0 1 SVSH Control Mode Automatic (see Table 2-11) Manual (see Table 2-12) Automatic (see Table 2-11) Automatic (see Table 2-11) SVMH Control Mode Manual (see Table 2-13) Manual (see Table 2-13) Automatic (see Table 2-14) Automatic (see Table 2-14) SVSHE 0 1 1 1 1 Table 2-11. SVSH Automatic Performance Control SVSHMD x 0 0 1 1 SVSHFP x 0 1 0 1 AM, LPM0, LPM1 SVSH State Off Normal Full performance Normal Full performance LPM2, LPM3, LPM4 SVSH State Off Off Off Off Normal SVSHE 0 1 1 Table 2-12. SVSH Manual Performance Modes SVSHFP x 0 1 AM, LPM0, LPM1 SVSH State Off Normal Full performance LPM2, LPM3, LPM4 SVSH State Off Normal Full performance SVMHE 0 1 1 Table 2-13. SVMH Automatic Performance Control SVMHFP x 0 1 AM, LPM0, LPM1 SVMH State Off Normal Full performance LPM2, LPM3, LPM4 SVMH State Off Off Normal SVMHE 0 1 1 Table 2-14. SVMH Manual Performance Modes SVMHFP x 0 1 AM, LPM0, LPM1 SVMH State Off Normal Full performance LPM2, LPM3, LPM4 SVMH State Off Normal Full performance 2.2.9.3 Wake-up Times in Debug Mode The TEST/SBWTCK pin is used for interfacing to the development tools by Spy-Bi-Wire and JTAG. When the TEST/SBWTCK pin is high, wake-up times from LPM2, LPM3, and LPM4 may be different compared to when TEST/SBWTCK is low. When the TEST/SBWTCK pin is high, all delays associated with the SVSL and SVML settings have no effect and the device wakes within tWAKE-UP-FAST . Pay careful attention to the real-time behavior when exiting from LPM2, LPM3, and LPM4 with the device connected to a development tool (for example, MSP-FET430UIF). 112 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com PMM Operation 2.2.10 PMM Interrupts Interrupt flags generated by the PMM are routed to the system NMI interrupt vector generator register, SYSSNIV. When the PMM causes a reset, a value is generated in the system reset interrupt vector generator register, SYSRSTIV, corresponding to the source of the reset. These registers are defined within the SYS module. More information on the relationship between the PMM and SYS modules is available in the SYS chapter. 2.2.11 Port I/O Control The PMM provides a means of ensuring that I/O pins cannot behave in uncontrolled fashion during an undervoltage event. During these times, outputs are disabled, both normal drive and the weak pullup/pulldown function. If the CPU is functioning normally, and then an undervoltage event occurs, any pin configured as an input has its PxIN register value locked in at the point the event occurs, until voltage is restored. During the undervoltage event, external voltage changes on the pin are not registered internally. This helps prevent erratic behavior from occurring. 2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional) The state of SVMLIFG, SVMLVLRIFG, SVMHIFG, and SVMLVLRIFG can be monitored on the external SVMOUT pin. Each of these interrupt flags can be enabled (SVMLOE, SVMLVLROE, SVMHOE, SVMLVLROE) to generate an output signal. The polarity of the output is selected by the SVMOUTPOL bit. If SVMOUTPOL is set, the output is set to 1 if an enabled interrupt flag is set. SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 113 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Registers www.ti.com 2.3 PMM Registers The PMM registers are listed in Table 2-15. The base address of the PMM module can be found in the device-specific data sheet. The address offset of each PMM register is given in Table 2-15. The password, PMMPW, defined in the PMMCTL0 register controls access to all PMM, SVS, and SVM registers. Once the correct password is written, the write access is enabled. The write access is disabled by writing a wrong password in byte mode to the PMMCTL0 upper byte. Word accesses to PMMCTL0 with a wrong password triggers a PUC. A write access to a register other than PMMCTL0 while write access is not enabled causes a PUC. NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15). Offset 00h 00h 01h 02h 02h 03h 04h 04h 05h 06h 06h 07h 08h Acronym PMMCTL0 PMMCTL0_L PMMCTL0_H PMMCTL1 PMMCTL1_L PMMCTL1_H SVSMHCTL SVSMHCTL_L SVSMHCTL_H SVSMLCTL SVSMLCTL_L SVSMLCTL_H SVSMIO 08h 09h 0Ch 0Ch 0Dh 0Eh 0Eh 0Fh 10h 10h 11h SVSMIO_L SVSMIO_H PMMIFG PMMIFG_L PMMIFG_H PMMRIE PMMRIE_L PMMRIE_H PM5CTL0 PM5CTL0_L PM5CTL0_H Table 2-15. PMM Registers Register Name PMM control register 0 PMM control register 1 SVS and SVM high side control register SVS and SVM low side control register SVSIN and SVMOUT control register (optional) PMM interrupt flag register PMM interrupt enable register Power mode 5 control register 0 Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Access Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Reset 9600h 00h 96h 0000h 00h 00h 4400h 00h 44h 4400h 00h 44h 0020h Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte 20h 00h 0000h 00h 00h 1100h 00h 11h 0000h 00h 00h Section Section 2.3.1 Section 2.3.2 Section 2.3.3 Section 2.3.4 Section 2.3.5 Section 2.3.6 Section 2.3.7 Section 2.3.8 114 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 2.3.1 PMMCTL0 Register Power Management Module Control Register 0 15 rw-1 7 Reserved rw-0 14 13 rw-0 rw-0 6 5 Reserved r-0 r-0 Figure 2-9. PMMCTL0 Register 12 11 10 PMMPW rw-1 rw-0 rw-1 4 PMMREGOFF rw-0 3 PMMSWPOR rw-0 2 PMMSWBOR rw-0 PMM Registers 9 8 rw-1 rw-0 1 0 PMMCOREV rw-[0] rw-[0] Bit 15-8 Field PMMPW 7 Reserved 6-5 Reserved 4 PMMREGOFF 3 PMMSWPOR 2 PMMSWBOR 1-0 PMMCOREV Type RW RW R RW RW RW RW Table 2-16. PMMCTL0 Register Description Reset 96h 0h 0h 0h 0h 0h 0h Description PMM password. Always read as 096h. When using word operations, must be written with 0A5h or a PUC is generated. When using byte operation, writing 0A5h unlocks all PMM registers. When using byte operation, writing anything different than 0A5h locks all PMM registers. Reserved. Must always be written as 0. Reserved. Always reads as 0. Regulator off (see the SYS chapter for details) Software power-on reset. Setting this bit to 1 triggers a POR. This bit is self clearing. Software brownout reset. Setting this bit to 1 triggers a BOR. This bit is self clearing. Core voltage (see the device-specific data sheet for supported levels and corresponding voltages) 00b = V(CORE) level 0 01b = V(CORE) level 1 10b = V(CORE) level 2 11b = V(CORE) level 3 SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 115 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Registers 2.3.2 PMMCTL1 Register Power Management Module Control Register 1 15 14 r-0 r-0 7 6 Reserved r-0 r-0 Figure 2-10. PMMCTL1 Register 13 12 11 10 Reserved r-0 r-0 r-0 r-0 5 4 Reserved rw-[0] rw-[0] 3 2 Reserved r-0 r-0 Bit 15-6 5-4 3-2 1-0 Field Reserved Reserved Reserved Reserved Type R RW R RW Table 2-17. PMMCTL1 Register Description Reset 0h 0h 0h 0h Description Reserved. Always reads as 0. Reserved. Must always be written with 0. Reserved. Always reads as 0. Reserved. Must always be written with 0. www.ti.com 9 8 r-0 r-0 1 0 Reserved rw-0 rw-0 116 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 2.3.3 SVSMHCTL Register Supply Voltage Supervisor and Monitor High-Side Control Register 15 SVMHFP rw-[0] 7 SVSMHACE rw-[0] 14 SVMHE rw-1 6 SVSMHEVM rw-0 13 Reserved r-0 5 Reserved r-0 Figure 2-11. SVSMHCTL Register 12 11 10 SVMHOVPE SVSHFP SVSHE rw-[0] rw-[0] rw-1 4 SVSHMD rw-0 3 SVSMHDLYST r-0 2 rw-[0] PMM Registers 9 8 SVSHRVL rw-[0] rw-[0] 1 SVSMHRRL rw-[0] 0 rw-[0] Bit Field 15 SVMHFP 14 SVMHE 13 Reserved 12 SVMHOVPE 11 SVSHFP 10 SVSHE 9-8 SVSHRVL 7 SVSMHACE 6 SVSMHEVM 5 Reserved 4 SVSHMD 3 SVSMHDLYST 2-0 SVSMHRRL Table 2-18. SVSMHCTL Register Description Type RW RW R RW RW RW RW RW RW R RW R RW Reset 0h 1h 0h 0h 0h 1h 0h 0h 0h 0h 0h 0h 0h Description SVM high-side full-performance mode. If this bit is set, the SVMH operates in full-performance mode. 0b = Normal mode. See the device-specific data sheet for response times. 1b = Full-performance mode. See the device-specific data sheet for response times. SVM high-side enable. If this bit is set, the SVMH is enabled. Reserved. Always reads as 0. SVM high-side overvoltage enable. If this bit is set, the SVMH overvoltage detection is enabled. If SVMHVLRPE is also set, a POR occurs on an overvoltage condition. SVS high-side full-performance mode. If this bit is set, the SVSH operates in fullperformance mode. 0b = Normal mode. See the device-specific data sheet for response times. 1b = Full-performance mode. See the device-specific data sheet for response times. SVS high-side enable. If this bit is set, the SVSH is enabled. SVS high-side reset voltage level. If DVCC falls short of the SVSH voltage level selected by SVSHRVL, a reset is triggered (if SVSHPE = 1). The voltage levels are defined in the device-specific data sheet. Note: SVSMHRRL must always be equal or larger than SVSHRVL. SVS and SVM high-side automatic control enable. If this bit is set, the low-power mode of the SVSH and SVMH circuits is under hardware control. SVS and SVM high-side event mask. If this bit is set, the SVSH and SVMH events are masked. 0b = No events are masked. 1b = All events are masked. Reserved. Always reads as 0. SVS high-side mode. If this bit is set, the SVSH interrupt flag is set in LPM2, LPM3, and LPM4 in case of power-fail conditions. If this bit is not set, the SVSH interrupt is not set in LPM2, LPM3, and LPM4. SVS and SVM high-side delay status. If this bit is set, the SVSH and SVMH events are masked for some delay time. The delay time depends on the power mode of the SVSH and SVMH. If SVMHFP = 1 and SVSHFP = 1 (that is, fullperformance mode), the delay is shorter. See the device-specific data sheet for details. The bit is cleared by hardware if the delay has expired. SVS and SVM high-side reset release voltage level. These bits define the reset release voltage level of the SVSH. It is also used for the SVMH to define the voltage reached level. The voltage levels are defined in the device-specific data sheet. Note: SVSMHRRL must always be equal or larger than SVSHRVL. SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 117 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Registers 2.3.4 SVSMLCTL Register Supply Voltage Supervisor and Monitor Low-Side Control Register 15 SVMLFP rw-[0] 7 SVSMLACE rw-[0] 14 SVMLE rw-1 6 SVSMLEVM rw-0 13 Reserved r-0 5 Reserved r-0 Figure 2-12. SVSMLCTL Register 12 11 10 SVMLOVPE SVSLFP SVSLE rw-[0] rw-[0] rw-1 4 SVSLMD rw-0 3 SVSMLDLYST r-0 2 rw-[0] www.ti.com 9 8 SVSLRVL rw-[0] rw-[0] 1 SVSMLRRL rw-[0] 0 rw-[0] Bit Field 15 SVMLFP 14 SVMLE 13 Reserved 12 SVMLOVPE 11 SVSLFP 10 SVSLE 9-8 SVSLRVL 7 SVSMLACE 6 SVSMLEVM 5 Reserved 4 SVSLMD 3 SVSMLDLYST 2-0 SVSMLRRL Table 2-19. SVSMLCTL Register Description Type RW RW R RW RW RW RW RW RW R RW RW RW Reset 0h 1h 0h 0h 0h 1h 0h 0h 0h 0h 0h 0h 0h Description SVM low-side full-performance mode. If this bit is set, the SVML operates in fullperformance mode. 0b = Normal mode. See the device-specific data sheet for response times. 1b = Full-performance mode. See the device-specific data sheet for response times. SVM low-side enable. If this bit is set, the SVML is enabled. Reserved. Always reads as 0. SVM low-side overvoltage enable. If this bit is set, the SVML overvoltage detection is enabled. SVS low-side full-performance mode. If this bit is set, the SVSL operates in fullperformance mode. 0b = Normal mode. See the device-specific data sheet for response times. 1b = Full-performance mode. See the device-specific data sheet for response times. SVS low-side enable. If this bit is set, the SVSL is enabled. SVS low-side reset voltage level. If V(CORE) falls short of the SVSL voltage level selected by SVSLRVL, a reset is triggered (if SVSLPE = 1). Note: SVSMLRRL must always be equal or larger than SVSLRVL. SVS and SVM low-side automatic control enable. If this bit is set, the low-power mode of the SVSL and SVML circuits is under hardware control. SVS and SVM low-side event mask. If this bit is set, the SVSL and SVML events are masked. 0b = No events are masked. 1b = All events are masked. Reserved. Always reads as 0. SVS low-side mode. If this bit is set, the SVSL interrupt flag is set in LPM2, LPM3 and LPM4 in case of power-fail conditions. If this bit is not set, the SVSL interrupt is not set in LPM2, LPM3, and LPM4. SVS and SVM low-side delay status. If this bit is set, the SVSL and SVML events are masked for a delay time. The delay time depends on the power mode of the SVSL and SVML. If SVMLFP = 1 and SVSLFP = 1 (that is, full-performance mode), the delay is shorter. The bit is cleared by hardware if the delay has expired. SVS and SVM low-side reset release voltage level. These bits define the reset release voltage level of the SVSL. It is also used for the SVML to define the voltage reached level. Note: SVSMLRRL must always be equal or larger than SVSLRVL. 118 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 2.3.5 SVSMIO Register SVSIN and SVMOUT Control Register 15 14 Reserved r-0 r-0 7 6 Reserved r-0 r-0 13 r-0 5 SVMOUTPOL rw-[1] Figure 2-13. SVSMIO Register 12 11 10 SVMHVLROE SVMHOE rw-[0] rw-[0] r-0 4 3 2 SVMLVLROE SVMLOE rw-[0] rw-[0] r-0 PMM Registers 9 8 Reserved r-0 r-0 1 0 Reserved r-0 r-0 Bit 15-13 12 Field Reserved SVMHVLROE 11 SVMHOE 10-6 5 Reserved SVMOUTPOL 4 SVMLVLROE 3 SVMLOE 2-0 Reserved Type R RW RW R RW RW RW R Table 2-20. SVSMIO Register Description Reset 0h 0h 0h 0h 1h 0h 0h 0h Description Reserved. Always reads as 0. SVM high-side voltage level reached output enable. If this bit is set, the SVMHVLRIFG bit is output to the device SVMOUT pin. The device-specific port logic has to be configured accordingly. SVM high-side output enable. If this bit is set, the SVMHIFG bit is output to the device SVMOUT pin. The device-specific port logic has to be configured accordingly. Reserved. Always reads as 0. SVMOUT pin polarity. If this bit is set, SVMOUT is active high. An error condition is signaled by a 1 at SVMOUT. If SVMOUTPOL is cleared, the error condition is signaled by a 0 at the SVMOUT pin. SVM low-side voltage level reached output enable. If this bit is set, the SVMLVLRIFG bit is output to the device SVMOUT pin. The device-specific port logic has to be configured accordingly. SVM low-side output enable. If this bit is set, the SVMLIFG bit is output to the device SVMOUT pin. The device-specific port logic has to be configured accordingly. Reserved. Always reads as 0. SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 119 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Registers 2.3.6 PMMIFG Register Power Management Module Interrupt Flag Register www.ti.com 15 PMMLPM5IFG rw-[0] 14 Reserved r-0 13 SVSLIFG (1) rw-[0] Figure 2-14. PMMIFG Register 12 11 10 SVSHIFG (1) Reserved PMMPORIFG rw-[0] r-0 rw-[0] 9 PMMRSTIFG rw-[0] 8 PMMBORIFG rw-[0] 7 Reserved r-0 6 SVMHVLRIFG ( 1) rw-[0] 5 SVMHIFG rw-[0] 4 SVSMHDLYIF G rw-0 3 Reserved r-0 2 SVMLVLRIFG (1 ) rw-[0] 1 SVMLIFG rw-[0] 0 SVSMLDLYIFG rw-0 (1) After power up, the reset value depends on the power sequence. (1) After power up, the reset value depends on the power sequence. Bit Field 15 PMMLPM5IFG 14 Reserved 13 SVSLIFG 12 SVSHIFG 11 Reserved 10 PMMPORIFG 9 PMMRSTIFG 8 PMMBORIFG 7 Reserved 6 SVMHVLRIFG 5 SVMHIFG Type RW R RW RW R RW RW RW R RW RW Table 2-21. PMMIFG Register Description Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h Description LPMx.5 flag. This bit is set if the system was in LPMx.5 before. The bit is cleared by software or by reading the reset vector word. A power failure on the DVCC domain clears the bit. 0b = No interrupt pending 1b = Interrupt pending Reserved. Always reads as 0. SVS low-side interrupt flag. The bit is cleared by software or by reading the reset vector word. 0b = No interrupt pending 1b = Interrupt pending SVS high-side interrupt flag. The bit is cleared by software or by reading the reset vector word. 0b = No interrupt pending 1b = Interrupt pending Reserved. Always reads as 0. PMM software power-on reset interrupt flag. This interrupt flag is set if a software POR is triggered. The bit is cleared by software or by reading the reset vector word, SYSRSTIV. 0b = No interrupt pending 1b = Interrupt pending PMM reset pin interrupt flag. This interrupt flag is set if the RST/NMI pin is the reset source. The bit is cleared by software or by reading the reset vector word. 0b = No interrupt pending 1b = Interrupt pending PMM software brownout reset interrupt flag. This interrupt flag is set if a software BOR (PMMSWBOR) is triggered. The bit is cleared by software or by reading the reset vector word, SYSRSTIV. 0b = No interrupt pending 1b = Interrupt pending Reserved. Always reads as 0. SVM high-side voltage level reached interrupt flag. The bit is cleared by software or by reading the reset vector (SVSHPE = 1) word or by reading the interrupt vector (SVSHPE = 0) word. 0b = No interrupt pending 1b = Interrupt pending SVM high-side interrupt flag. The bit is cleared by software. 0b = No interrupt pending 1b = Interrupt pending 120 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Bit Field 4 SVSMHDLYIFG 3 Reserved 2 SVMLVLRIFG 1 SVMLIFG 0 SVSMLDLYIFG PMM Registers Table 2-21. PMMIFG Register Description (continued) Type RW R RW RW RW Reset 0h 0h 0h 0h 0h Description SVS and SVM high-side delay expired interrupt flag. This interrupt flag is set if the delay element expired. The bit is cleared by software or by reading the interrupt vector word. 0b = No interrupt pending 1b = Interrupt pending Reserved. Always reads as 0. SVM low-side voltage level reached interrupt flag. The bit is cleared by software or by reading the reset vector (SVSLPE = 1) word or by reading the interrupt vector (SVSLPE = 0) word. 0b = No interrupt pending 1b = Interrupt pending SVM low-side interrupt flag. The bit is cleared by software. 0b = No interrupt pending 1b = Interrupt pending SVS and SVM low-side delay expired interrupt flag. This interrupt flag is set if the delay element expired. The bit is cleared by software or by reading the interrupt vector word. 0b = No interrupt pending 1b = Interrupt pending SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 121 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated PMM Registers 2.3.7 PMMRIE Register Power Management Module Reset and Interrupt Enable Register 15 14 Reserved r-0 r-0 7 Reserved r-0 6 SVMHVLRIE rw-0 13 SVMHVLRPE rw-[0] 5 SVMHIE rw-0 Figure 2-15. PMMRIE Register 12 11 10 SVSHPE Reserved rw-[1] r-0 r-0 4 SVSMHDLYIE rw-0 3 Reserved r-0 2 SVMLVLRIE rw-0 www.ti.com 9 SVMLVLRPE rw-[0] 1 SVMLIE rw-0 8 SVSLPE rw-[1] 0 SVSMLDLYIE rw-0 Bit 15-14 13 12 11-10 9 8 7 6 5 4 3 2 1 0 Field Reserved SVMHVLRPE SVSHPE Reserved SVMLVLRPE SVSLPE Reserved SVMHVLRIE SVMHIE SVSMHDLYIE Reserved SVMLVLRIE SVMLIE SVSMLDLYIE Type R RW RW R RW RW R RW RW RW R RW RW RW Table 2-22. PMMRIE Register Description Reset 0h 0h 1h 0h 0h 1h 0h 0h 0h 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. SVM high-side voltage level reached power-on reset enable. If this bit is set, exceeding the SVMH voltage level triggers a POR. SVS high-side power-on reset enable. If this bit is set, falling below the SVSH voltage level triggers a POR. Reserved. Always reads as 0. SVM low-side voltage level reached power-on reset enable. If this bit is set, exceeding the SVML voltage level triggers a POR. SVS low-side power-on reset enable. If this bit is set, falling below the SVSL voltage level triggers a POR. Reserved. Always reads as 0. SVM high-side reset voltage level interrupt enable SVM high-side interrupt enable. This bit is cleared by software or if the interrupt vector word is read. SVS and SVM high-side delay expired interrupt enable Reserved. Always reads as 0. SVM low-side reset voltage level interrupt enable SVM low-side interrupt enable. This bit is cleared by software or if the interrupt vector word is read. SVS and SVM low-side delay expired interrupt enable 122 Power Management Module and Supply Voltage Supervisor SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 2.3.8 PM5CTL0 Register Power Mode 5 Control Register 0 Figure 2-16. PM5CTL0 Register 15 14 13 12 11 10 Reserved r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 Reserved r0 r0 r0 r0 r0 r0 PMM Registers 9 8 r0 r0 1 0 LOCKLPM5 r0 rw-[0] Bit 15-1 0 Field Reserved LOCKLPM5 Type R RW Table 2-23. PM5CTL0 Register Description Reset 0h 0h Description Reserved. Always reads as 0. Lock I/O pin configuration upon entry to or exit from LPMx.5. When power is applied to the device, this bit, once set, can only be cleared by the user or via another power cycle. Note: This bit was formerly named LOCKIO, and some application reports and code examples may continue to use this terminology. 0b = I/O pin configuration is not locked and defaults to its reset condition. 1b = I/O pin configuration remains locked. Pin state is held during LPMx.5 entry and exit. SLAU208O – June 2008 – Revised May 2015 Power Management Module and Supply Voltage Supervisor 123 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Chapter 3 SLAU208O – June 2008 – Revised May 2015 Battery Backup System The battery backup system can operate a real-time clock (RTC_B module) and retain some bytes in a backup RAM from a backup source when the primary supply fails. The battery backup system also includes a simple charging circuitry to charge capacitors connected to the backup supply. This chapter describes the battery backup system. Topic ........................................................................................................................... Page 3.1 Battery Backup Introduction .............................................................................. 125 3.2 Battery Backup Operation ................................................................................. 125 3.3 Battery Backup Registers .................................................................................. 129 124 Battery Backup System SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Battery Backup Introduction 3.1 Battery Backup Introduction The battery backup system features include: • Automatic and manual switching to the backup supply • Backup-supplied backup subsystem that can contain: – Backup-supplied real-time clock with 32-kHz crystal oscillator (see the RTC_B chapter and Clock System chapter) – Backup-supplied backup RAM (see the Backup RAM chapter) • Resistive charger for backup capacitors NOTE: Operation without separate battery backup supply If there is no separate battery backup supply in the system, connect the VBAT pin to DVCC and set bit BAKDIS=1. 3.2 Battery Backup Operation The battery backup system supplies a subsystem from a secondary supply (VBAT) if the primary supply (DVCC) fails. The backup-supplied subsystem usually contains a real-time clock module (together with the required LF-crystal oscillator) and a backup RAM. These modules are described in their respective User's Guide chapters. The high-side SVS (SVSH) that is located in the PMM module and supervises the primary supply (DVCC) controls the switching between primary and secondary supply. NOTE: Restrictions When the lowest high-side SVS level (00b) is used to monitor the primary supply, the temperature range is restricted to 0°C to 85°C. Figure 3-1 shows an overview of the battery backup switch. The secondary supply VBAT powers the backup-supplied subsystem • at power on • if bit BAKDIS = 0 in the BAKCTL register and – if the primary supply drops below the configured high-side SVS level – if the high-side SVS (SVSH) is disabled – during LPMx.5 – if bit BAKSW=1 in the BAKCTL register The primary supply DVCC powers the backup-supplied subsystem • if the primary supply rises above the power-on level of the high-side SVS level • if the primary supply remains above the configured high-side SVS level • if bit BAKDIS = 1 in the BAKCTL register If the backup-supplied subsystem is powered by the secondary supply VBAT, the access and control to modules located in the subsystem is restricted: • The data stored in the backup RAM is retained but cannot be accessed. • The RTC, if enabled, together with the 32-kHz crystal oscillator continue to operate but the time and date information cannot be accessed. • Changes to the LF crystal oscillator setting in the clock system do not take effect. If the backup-supplied subsystem is powered by the primary supply DVCC and LOCKBAK = 0, the modules located in the subsystem can be access and controlled normally. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Battery Backup System 125 Battery Backup Operation DVCC VCC BAKCHEN BAKCHCx BAKCHVx Charger VBAT VBAT Switch Control BAKSW BAKDIS www.ti.com VBAK VBAK CBAK 1 VBAK Supply voltage of backup subsystem BAKADC Enable signal from ADC VBAT3 1 To ADC input (usually channel 12; see the respective ADC chapter and the device-specific data sheet for details) Figure 3-1. Battery Backup Switch Overview NOTE: CBAK shown in Figure 3-1 is used to ensure proper decoupling during a switchover event. See the device-specific data sheet for recommended values. This capacitance should not be confused with an external capacitor that may be placed on VBAT to maintain charge during backup operation in the application. 3.2.1 Activate Access to Backup-Supplied Subsystem If the backup-supplied subsystem is powered by the secondary supply VBAT the LOCKBAK bit is automatically set. While LOCKBAK=1 it is impossible to access to the information stored in the backupsupplied subsystem. After its supply switched back to the primary supply do the following steps to get access to it : 1. Initialize the configuration registers of the real-time clock module exactly the same way as they were configured before the switch to the secondary supply. 2. Clear the LOCKBAK bit in the BAKCTL register. 3. Check the LOCKBAK bit. If LOCKBAK = 0, continue with the next step. If LOCKBAK = 1, the supply for the backup-supplied subsystem has not settled yet. Continue with step 2. 4. Enable RTC interrupts. 5. The enabled RTC interrupts will now be serviced as normal interrupts. 126 Battery Backup System SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Battery Backup Operation 3.2.2 Manual Switching The backup-supplied subsystem is always powered from the secondary supply VBAT if the bit BAKSW in the Battery Backup Control register BAKCTL is set to 1. A POR resets the BAKSW bit, and the system returns to automatic switch control. 3.2.3 Disable Switching If the bit BAKDIS in the Battery Backup Control register BAKCTL is set to 1, the battery backup system is disabled and the backup-supplied subsystem is always powered from the primary supply DVCC. A POR resets the BAKDIS bit, and the system returns to automatic switch control. 3.2.4 Measuring the Supplies With an integrated ADC, the primary and secondary supplies can be measured. Select the channel of the ADC that is reserved to measure the supply voltage of the device. This is usually ADC channel 12; see the respective ADC chapter and the device-specific data sheet for details. If BAKADC = 0, VBAT measurement is disabled. If BAKADC = 1, the secondary supply VBAT is measured. The resistive dividers are connected to the supplies only during the sampling phase of the ADC. 3.2.5 LPMx.5 and Backup Operation During LPMx.5 (LPM3.5 or LPM4.5), the backup subsystem is always supplied from the backup battery, except when switching is completely disabled by setting the BAKDIS bit. If using a capacitor to source the backup supply, the device can wake up regularly from LPMx.5, recharge the capacitor, and return to LPMx.5. The time interval must be designed such that the remaining charge on the capacitor is always sufficient to bridge the worst-case backup time (that is, the time without any primary supply). SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Battery Backup System 127 Battery Backup Operation www.ti.com 3.2.6 Resistive Charger Together with the battery backup switch, a resistive charging circuit is implemented to charge capacitors connected to the backup supply. A simplified block diagram of the charger is shown in Figure 3-2. The charger is enabled by writing the correct password (069h) into the upper byte of BAKCHCTL, together with BAKCHEN = 1, selecting a charging resistor with BAKCHCx ≠ 00b, and a charge end voltage with BAKCHVx ≠ 00b. Writing to the charger control register with an incorrect password disables the charger, and all control register bits are reset to 0. If VCC is selected as charge end voltage with BACKCHVx = 01b (or if VCC < 2.7 V with BACKCHVx = 10b), an attached capacitor is charged to VCC with VBAT(t) ≈ VCC × (1 – exp(-t/RC), with R being the selected charging resistor and C being the capacitor attached to pin VBAT (this is not CBAK). If a charge end voltage of 2.7 V is selected (BACKCHVx = 10b) and VCC > 2.7 V, then an attached capacitor is charged with VBAT(t) ≈ VCC × (1 – exp(-t/RC) (same as above) but as soon as VBAT reaches approximately 2.7 V, the charging process is halted. If VBAT drops by approximately 70 mV (the comparator hysteresis), the charging process continues again until the capacitor connected to pin VBAT is again charged to approximately 2.7 V. Note: For low power reasons, the VBAT voltage is compared against the 2.7-V limit only once during each VLO clock cycle, and only then is charging disabled or re-enabled. DVCC Charger enable Charger BAKCHCx BAKCHV1 ~2.7V VBAT Figure 3-2. Charger Block Diagram 128 Battery Backup System SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Battery Backup Registers 3.3 Battery Backup Registers The battery backup registers are listed in Table 3-1. The base address for the backup RAM registers can be found in the device-specific data sheet. The address offsets are given in Table 3-1. Offset 00h 02h Acronym BAKCTL BAKCHCTL Table 3-1. Battery Backup Registers Register Name Battery Backup Control Battery Charger Control Type Read/write Read/write LPMx.5, Backup Retention not retained not retained Section Section 3.3.1 Section 3.3.2 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Battery Backup System 129 Battery Backup Registers 3.3.1 BAKCTL Register Battery Backup Control Register 15 14 13 r r r0 7 6 5 Reserved r0 r0 r0 Figure 3-3. BAKCTL Register 12 11 10 Reserved r0 r0 r0 4 3 2 BAKDIS BAKADC r0 rw rw-(0) www.ti.com 9 r0 1 BAKSW rw-(0) 8 r0 0 LOCKBAK r/w0-[1] Bit 15-4 3 Field Reserved BAKDIS 2 BAKADC 1 BAKSW 0 LOCKBAK Type R RW RW RW RW Table 3-2. BAKCTL Register Description Reset 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. Disable backup supply switching. Reset to 0 after a complete power cycle. 0b = Backup supply switching enabled 1b = Backup supply switching disabled. Backup subsystem always powered from VCC (also during LPMx.5). Battery backup supply to ADC 0b = Vbat measurement disabled 1b = Vbat measurement enabled Manual switch to battery backup supply 0b = Switching is automatic 1b = Switch to battery backup supply Lock backup subsystem. Can only be written as 0. The LOCKBAK bit should only be written as 0 after configuring the RTC control registers. This ensures that RTC will not be stopped after leaving backup or LPMx.5 mode. SVSH has to be active when LOCKBAK bit is cleared. LOCKBAK is always set to 1 by hardware after the core was powered down either due to a complete power cycle of the main supply DVCC or due to LPMx.5 operation. 0b = Backup subsystem not locked 1b = Backup subsystem locked 130 Battery Backup System SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 3.3.2 BAKCHCTL Register Battery Charger Control Register Battery Backup Registers 15 14 rw rw 7 6 Reserved r0 r0 Figure 3-4. BAKCHCTL Register 13 12 11 10 9 BAKCHKEYx rw rw rw rw rw 5 4 BAKCHVx rw-0 rw-0 3 Reserved r0 2 1 BAKCHCx rw-0 rw-0 8 rw 0 BAKCHEN rw-0 Bit 15-8 Field BAKCHKEYx 7-6 Reserved 5-4 BAKCHVx 3 Reserved 2-1 BAKCHCx 0 BAKCHEN Type RW R RW R RW RW Table 3-3. BAKCHCTL Register Description Reset 5Ah 0h 0h 0h 0h 0h Description Charger access key. Always read as 05Ah. Must be written as 069h together with low byte; any other write disables the charger and all control register bits are reset to 0. Reserved. Always reads as 0. Charger end voltage 00b = Charger disabled 01b = VCC 10b = Approximately 2.7 V, or VCC if VCC is lower than 2.7 V 11b = Reserved Reserved. Always reads as 0. Charger charge current 00b = Charger disabled 01b = Charge current defined by a maximum 5-kΩ resistor 10b = Charge current defined by a maximum 10-kΩ resistor 11b = Charge current defined by a maximum 20-kΩ resistor Charger enable 0b = Charger disabled 1b = Charger enabled SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Battery Backup System 131 Chapter 4 SLAU208O – June 2008 – Revised May 2015 Auxiliary Supply System (AUX) The auxiliary supply system (AUX) allows the device to operate from alternate supplies (also called auxiliary supplies) if the primary supply (DVCC and AVCC) fails. The AUX includes simple charging circuitry to charge capacitors connected to the auxiliary supplies. This chapter describes the AUX. Topic ........................................................................................................................... Page 4.1 Auxiliary Supply System Introduction ................................................................. 133 4.2 Auxiliary Supply Operation ................................................................................ 134 4.3 AUX Registers.................................................................................................. 148 132 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Auxiliary Supply System Introduction 4.1 Auxiliary Supply System Introduction The auxiliary supply system features include: • Automatic or manual switching from the primary supply to an auxiliary supply while maintaining full functionality. • One or two auxiliary supplies (AUXVCC1 and AUXVCC2), depending on the specific device. • Automatic threshold-based monitoring of primary and auxiliary supplies. • At startup, automatically chooses between the primary supply (DVCC/AVCC) and AUXVCC1, based on which one is higher voltage. • A separate auxiliary supply (AUXVCC3) can power a backup subsystem .(1) • Simple charger for capacitors on AUXVCC2 and AUXVCC3. NOTE: Unused auxiliary supplies Any unused auxiliary supply inputs (AUXVCC1, or AUXVCC2) must be connected to DVSS. If AUXVCC1 or AUXVCC2 are unused, they should be disabled by setting AUXxMD = 1 and AUXxOK = 0 in software, too. If AUXVCC3 is not powered by a dedicated supply, it can either be connected to DVCC externally or powered by enabling the AUXVCC3 charger. If powered by the charger, the recommended capacitor should be connected externally. If AUXVCC3 is not powered or connected to DVSS, the backup subsystem (including, for example, the 32-kHz crystal oscillator) is not functional. (1) The backup subsystem usually contains a real-time clock (RTC) module with a 32-kHz crystal oscillator, backup RAM, and optionally (device-specific) up to two digital I/O pins. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 133 Auxiliary Supply Operation www.ti.com 4.2 Auxiliary Supply Operation The AUX module allows the device to switch between the primary supply (DVCC and AVCC) and up to two auxiliary supplies (AUXVCC1 and AUXVCC2) while maintaining full device functionality. When using an auxiliary supply, both AVCC and DVCC are switched to the same auxiliary supply. Switching can be controlled automatically through hardware or manually through software. In the hardware-controlled mode, switching is triggered by the high-side supply voltage monitor (SVM), which must be enabled and configured as described in Section 4.2.4. In the software-controlled mode, switching is triggered by changing values in AUX module registers, as described in Section 4.2.3. Figure 4-1 shows an overview of the auxiliary supply switches. The digital core of the device is supplied through the Power Management Module (PMM) by the internal digital system voltage VDSYS. In the PMM chapter of this user's guide, that supply is assumed to be DVCC; however, on devices with the AUX module, AUX switches VDSYS among the DVCC, AUXVCC1, and AUXVCC2 inputs. VDSYS is also output on the VDSYS pin, which must be connected to an external capacitor as specified in the device-specific data sheet. The analog modules of the device are supplied by the internal analog system voltage VASYS. The AUX module switches VASYS among the AVCC, AUXVCC1, and AUXVCC2 inputs. VASYS is also output on the VASYS pin, which must be connected to an external capacitor as specified in the device-specific data sheet. The switches for the digital and the analog system voltages are controlled by the same signals and always connect to the same voltage (primary voltage DVCC/AVCC, first auxiliary voltage AUXVCC1, or second auxiliary voltage AUXVCC2). Auxiliary voltage AUXVCC3 supplies VBAK to the backup subsystem, which usually contains a real-time clock (RTC) module with a 32-kHz crystal oscillator, some backup RAM, and optionally (device-specific) up to two digital I/O pins. AVCC VASYS Analog Modules VASYS DVCC AUXVCC1 AUXVCC2 Charger VDSYS PMM->Core Logic VDSYS AUXVCC3 Charger VBAK Figure 4-1. Auxiliary Supply Switch Overview Backup Subsystem 134 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Auxiliary Supply Operation 4.2.1 Startup The device starts whenever a supply is connected to DVCC or AUXVCC1. If both supplies are connected, AUX uses whichever voltage is higher to supply the digital and analog system voltages, VDSYS and VASYS. If the supplies (DVCC/AVCC and AUXVCC1) differ by less than 100 mV the selected supply can be either DVCC/AVCC or AUXVCC1 - only if the difference is greater than 100 mV always the supply with the higher voltage is selected. After startup from any condition that causes a BOR event (including connection of power or wake from LPMx.5), the AUX module is automatically locked (that is, the LOCKAUX bit is set). The behavior of the auxiliary supply system can then be configured in software (see Section 4.2.2). After configuration is completed, unlock the AUX module by clearing the LOCKAUX bit. The AUX module is then operational and switches between the input supplies as defined during configuration. If the LOCKAUX bit remains set, the programmed configuration is ignored, and the device continues to be supplied by DVCC or AUXVCC1 (whichever was selected at startup). Section 4.2.7 describes additional considerations for setting the power supply before entering LPMx.5. NOTE: Highest Supply Voltage To ensure reliable operation, the selected supply voltage (by default, the highest voltage in the system) must always supply at least 0.5 µA to critical circuitry. NOTE: DVCC vs AUXVCC1 at Startup Under normal operating conditions it is recommended to have DVCC supplied by a voltage at least 100 mV higher than AUXVCC1. This ensures a reliable startup from DVCC and avoids an unwanted startup from AUXVCC1. 4.2.2 Switching Control During normal operation (that is, when the LOCKAUX bit is cleared) switching to another supply is triggered either by software or by hardware (specifically, by the high-side SVM). Section 4.2.3 describes the configuration and control of the AUX for software-controlled switching. Section 4.2.4 describes configuration and control of the AUX for hardware-controlled switching. Section 4.2.13 includes examples of how to configure hardware-controlled mode based on different usage scenarios. 4.2.3 Software-Controlled Switching To enable or disable a supply using software-controlled switching: 1. To enable software control of a supply, set AUXxMD = 1 (AUX0MD for DVCC, AUX1MD for AUXVCC1, and AUX2MD for AUXVCC2). 2. To select the supply to use, set AUXxOK = 1 (AUX0OK for DVCC, AUX1OK for AUXVCC1, and AUX2OK for AUXVCC2). When AUXxOK is set, the AUX module immediately switches to the specified supply. If AUXxOK = 1 for more than one supply, AUX uses the one with the highest priority. The default priority is DVCC, then AUXVCC1, then AUXVCC2. To make AUXVCC2 priority higher than AUXVCC1, set AUX2PRIO = 1. 3. To disable a supply, clear AUXxOK = 0. If the current supply is software-controlled (AUXxMD = 1) and AUXxOK is changed from 1 to 0, the next available supply (considering the priority defined by AUX2PRIO) is used to source the system voltages. When a switch from one supply to another occurs, interrupts are generated as described in Section 4.2.11. The software control can be used to permanently disable a supply or, for example, to qualify the quality of the supplies by measuring the actual supply voltage with an ADC (see Section 4.2.9) instead of using the auxiliary supply monitor (see Section 4.2.6). SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 135 Auxiliary Supply Operation www.ti.com When using software-controlled mode for all supplies, the SVS and SVM in the PMM are not required. They may be enabled, and they will operate as described in the PMM chapter, but they do not interact with the AUX during software-controlled mode. 4.2.4 Hardware-Controlled Switching To enable hardware-controlled switching, clear AUXxMD = 0 (AUX0MD for DVCC, AUX1MD for AUXVCC1, and AUX2MD for AUXVCC2). A supply can be disabled and, therefore, excluded from the automatic switching system by setting the corresponding AUXxMD = 1 and AUXxOK = 0. For example, to disable AUXVCC2, set AUX2MD = 1 and AUX2OK = 0. During hardware-controlled switching, the SVM in the PMM must be enabled and configured. The SVS can also be enabled and operates as described in the PMM chapter, but it does not interact with the AUX module. The high-side SVM of the PMM monitors VDSYS, which is output from the AUX module. If VDSYS falls below the voltage set by the SVSMHRRVL bits, the SVM notifies AUX to switch to the next valid supply. AUX switches to the next valid supply immediately after receiving the trigger from the SVM. When a switch occurs, interrupts are generated as described in Section 4.2.11. NOTE: Voltage Dip on VDSYS Because the SVM does not signal AUX to change the supply until the voltage on VDSYS falls to the SVM monitoring level (set in the SVSMHRRL bits), there is a dip in VDSYS from the nominal operating level. This change in voltage must be considered when selecting system frequency and core voltage (see Section 4.2.5). AUX determines which supplies are valid based on the threshold voltage set in the AUXxLVL bits. The validity of a supply is reported by the corresponding AUXxOK bit. When AUXxMD = 0, the AUXxOK bit is controlled by hardware and cannot be written by software. AUXxOK = 1 indicates a valid/"good" supply voltage, and AUXxOK = 0 indicates an invalid/"bad" supply voltage. See Section 4.2.6 for details on the monitoring of the auxiliary supplies. NOTE: Interactions Among SVMH, VCORE, and AUX Because of the relationship between supply voltage, core voltage, and maximum system frequency, see Section 4.2.5 for considerations when setting the AUXxLVL and SVMH levels. In particular, note that AUX0LVL must be higher than the SVMH level. The selection of the next valid supply depends on the state of the AUXxOK and AUX2PRIO bits when the trigger occurs as shown in Table 4-1. If there is no valid supply available to switch to (that is, all other AUXxOK bits are 0) no switching takes place, and the device eventually goes into reset if the current supply continues to fall. To avoid rapid switching back and forth between supplies, any further switching is prevented during a "recovery time" of several 100 µs as specified in the device-specific data sheet after each switch-over. 136 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Table 4-1. Next Supply Voltage Selection Auxiliary Supply Operation Current Supply Next Supply(1) DVCC OK? (AUX0OK) AUXVCC1 OK? (AUX1OK) don't care 1 AUXVCC1 don't care 1 DVCC/AVCC don't care 0 AUXVCC2 don't care 1 DVCC 1 don't care AUXVCC1 AUXVCC2 0 don't care DVCC 1 don't care AUXVCC2 AUXVCC1 0 1 (1) If there is no valid supply available to switch to, no switching takes place. AUXVCC2 OK? (AUX2OK) don't care 0 1 1 don't care 1 don't care don't care AUXVCC1/ AUXVCC2 Priority (AUX2PRIO) 0 1 don't care 1 don't care don't care don't care don't care NOTE: Special Case for Switching to DVCC/AVCC If the device is supplied by AUXVCC1 or AUXVCC2, and the AUX0OK bit transitions from 0 to 1 (either by hardware or by software), AUX switches to the DVCC/AVCC supply without any signal from the SVM. AUX does not automatically switch from AUX2VCC to AUX1VCC when AUX1OK transitions from 0 to 1, unless the SVM signals that a switch is necessary. 4.2.5 Interactions Among fSYS, VCORE, VDSYS, SVMH, and AUXxLVL The interactions that must be considered when setting the threshold levels in the SVM and AUX are: • Minimum VCORE required to support the selected system frequency (fSYS) • Valid SVMH to support the selected VCORE • Minimum VDSYS and minimum AUXxLVL required to support the selected VCORE The interactions among fSYS, DVCC (VDSYS for devices with AUX), VCORE, and SVMH are described in detail in the PMM chapter. This section adds considerations for the valid AUXxLVL values. NOTE: Maximum System Frequency The following discussion describes all system frequencies supported in this family. However, the maximum system frequency varies by device; therefore, see the device-specific data sheet to determine this value. Figure 4-2 shows typical requirements for supply voltage and VCORE compared to the system frequency (see the device-specific data sheet for the values required for each device). As shown here, there is a minimum VCORE (set by PMMCOREV[1:0]) and a minimum supply voltage (VDSYS) for each system frequency. For details on the recommended settings for PMMCOREV[1:0] and supply voltage, see Section 2.2.2.1. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 137 Auxiliary Supply Operation www.ti.com System Frequency - MHz 25 3 20 2 2, 3 12 1 1, 2 1, 2, 3 8 0 0, 1 0, 1, 2 0, 1, 2, 3 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 4-2. System Frequency vs Supply Voltage After selecting the system frequency and PMMCOREV[1:0] values, the SVM threshold must be selected. Figure 4-3 shows the valid values for SVMH (SVSMHRRL[2:0]) based on the selected VCORE (PMMCOREV[1:0]). This information is also included in Section 2.2.2.1. SVSMHRRLx 111 (7) 110 (6) 101 (5) 100 (4) 011 (3) 010 (2) 001 (1) 000 (0) Invalid 2.35 2.2 2.1 1.9 1.7 3.00 3.00 2.65 Invalid 00 01 10 11 PMMCOREVx Figure 4-3. Available SVMH Settings vs VCORE Settings 138 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Auxiliary Supply Operation Based on the preceding selections, the auxiliary supply threshold levels must be set. These thresholds are the minimum supply voltage that are available from each auxiliary supply. Figure 4-4 shows the valid AUXxLVL settings compared to the selected SVM setting. The level setting for DVCC/AVCC AUX0LVL must be chosen at least one step above the SVSMHRRLx level to avoid any unwanted switching between DVCC/AVCC and AUXVCC1 or AUXVCC2. 111 (7) 3.0 110 (6) 3.0 101 (5) 2.65 AUX0LVLx AUX1LVLx/AUX2LVLx 100 (4) 2.35 011 (3) 2.2 010 (2) 2.1 001 (1) 1.9 Invalid 000 (0) 1.7 000 001 010 011 100 101 110 111 (0) (1) (2) (3) (4) (5) (6) (7) SVSMHRRLx Figure 4-4. Available AUXxLVL Settings vs SVMH Settings Table 4-2 combines the information from the preceding figures and discussions. fSYS (max) (MHz) 8 12 20 25 Table 4-2. Minimum Voltage Thresholds for Selected fSYS Minimum PMMCOREV[1:0] 00 01 10 11 Minimum SVSMHRRL[2:0] (Sets SVMH Level) 000 001 010 011 Minimum VDSYS 1.8 V 2.0 V 2.2 V 2.4 V Minimum AUX0LVL 001 010 011 100 Minimum AUX1LVL, AUX2LVL 000 001 010 011 4.2.6 Auxiliary Supply Monitor Supplies that are not currently in use and that are not software controlled (AUXxMD = 0) are monitored using a low-power comparator. For example, if DVCC supplies the device and the AUXxMD bits are 0 for both AUXVCC1 and AUXVCC2, then AUXVCC1 and AUXVCC2 are monitored. As another example, if AUXVCC1 supplies the device and AUX2MD = 1, only DVCC is monitored. If all unselected supplies are controlled by software (AUXxMD = 1), then the automatic monitoring is disabled. The level the supply voltages are compared against is programmable with the AUXxLVL bits. If a supply drops below the selected threshold level the corresponding AUXxDRPIFG is set. Figure 4-5 shows a principle block diagram of the monitoring circuitry. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 139 Auxiliary Supply Operation www.ti.com If two supplies are monitored this happens in a time-division multiplexing scheme clocked by the VLO. During one VLO clock period, one supply is compared against its AUXxLVL threshold; during the next VLO clock period, the other supply is compared against its threshold. This means the AUXxOK bits of these supplies are updated approximately every 300 µs (worst case) with VLO clock frequency of approximately 6 kHz. If only one supply is monitored, the output of the comparator is sampled using the VLO clock, so that an update of the corresponding AUXxOK bit occurs approximately every 150 µs (worst case). Each monitoring cycle uses some charge from the monitored supply. The discharge of the monitored supplies can be reduced by decreasing the monitoing rate by changing the AUXMRx bits. By default (with AUXMRx = 00b) the supplies are monitored continously as described above. By setting AUXMRx = 01b, the supplies are monitored every 32 VLO clock cycles; by setting AUXMRx = 10b, the supplies are monitored every 1024 VLO clock cycles. The AUXMONIFG signals the completion of each monitoring cycle. If an unused supply is changed from software to hardware control (AUXxMD is changed from 1 to 0) a new monitoring cycle is started with the next VLO clock cycle. Switching of the supplies does not affect the timing of the monitoring cycles, it only changes which supplies are monitored. The auxiliary supply monitor is enabled after clearing the LOCKAUX bit unless all unused supplies are controlled by software. The monitored supplies are considered "not okay" until the first montoring cycle completes. NOTE: Switching and Monitoring Switching is independent from the update interval of the AUXxOK bits. Switching is triggered either by the high-side SVM or by software and takes place immediate after the trigger occurs, taking the current AUXxOK states into account to select the next supply. Only a change of AUX0OK from 0 to 1 indicating the DVCC changed from a "not okay" to an "okay" state triggers a switch back to DVCC. AUX0LVLx AUX1LVLx AUX2LVLx DVCC AUXVCC1 AUXVCC2 Threshold DAC Comparator DEMUX AUX0OK AUX1OK AUX2OK VLOCLK Control Logic Figure 4-5. Auxiliary Supply Monitor Block Diagram 140 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Auxiliary Supply Operation 4.2.7 LPMx.5 and Auxiliary Supply Operation During LPMx.5, the device is powered by whichever input supply was active when entering the low-power mode. To force the device to use a specific supply during LPMx.5, activate that supply before entering LPMx.5. Table 4-3 lists the supply selection during LPMx.5 based on the disabled supplies. The automatic threshold-based supply monitoring scheme is always disabled during LPMx.5. Table 4-3. Supply Selection During LPMx.5 Supply During LPMx.5 DVCC/AVCC Status(1) AUXVCC1 Status(2) DVCC/AVCC or AUXVCC1 (whichever is higher(3)) Not disabled Not disabled DVCC/AVCC Not disabled Disabled AUXVCC1 Disabled Not disabled AUXVCC2 Disabled Disabled (1) DVCC/AVCC is disabled if AUX0MD = 1 and AUX0OK = 0; otherwise it is enabled. (2) AUXVCC1 is disabled if AUX1MD = 1 and AUX1OK = 0; otherwise it is enabled. (3) If the supplies (DVCC/AVCC and AUXVCC1) differ by less than 100 mV, the selected supply can be either DVCC/AVCC or AUXVCC1. The supply with the higher voltage is selected only if the difference is greater than 100 mV. After wakeup from LPMx.5, the LOCKAUX bit is set. The LPMx.5 supply selection remains active until the LOCKAUX bit is cleared. When the LOCKAUX bit is cleared, the auxiliary supply system is controlled as defined by the control register settings that were configured before clearing the LOCKAUX bit. None of the AUX registers are retained during LPMx.5; thus, all registers must be reconfigured after wakeup from LPMx.5 and before releasing LOCKAUX. The supplies monitored by hardware (AUXxMD = 0) are considered "not okay" until the status is updated for the first time by the auxiliary supply monitor. Only the supply that was used during LPMx.5 is considered "okay" unless it drops below the programmed SVM level. If this behavior is unwanted, the state can be set to "okay" by temporarily switching to software mode (AUXxMD = 1), setting the AUXxOK bit to 1, and then return to hardware mode (AUXxMD = 0). The last state defined in software mode is retained when switching back to hardware mode until the first update occurs by the auxililary supply monitor. The supplies controlled by software (AUXxMD = 1) are considered "not okay" or "okay" according to their AUXxOK setting. If the supply that was used during LPMx.5 is set to "not okay" (AUXxMD = 1 and AUXxOK = 0) the auxiliary supply system tries to switch to another ("okay") supply according to Table 4-1 as soon as LOCKAUX is cleared. NOTE: DVCC vs AUXVCC1 during LPMx.5 Under normal operating conditions, TI recommends supplying DVCC by a voltage at least 100 mV higher than AUXVCC1 if automatic switching between DVCC and AUXVCC1 is active (that is, if both supplies are not disabled when entering LPMx.5) (see Table 4-3). This ensures a reliable operation from DVCC and avoids a potentially unwanted operation from AUXVCC1. 4.2.8 Digital I/Os and Auxiliary Supplies In most devices that implement the auxiliary supply system, the digital I/Os can be powered by the switched supplies. In this case, care must be taken that large currents sink to DVSS and are not sourced from the switched supplies, because of the voltage drop across the supply switches as shown in Figure 46. CAUTION Check connection of external loads at digital I/Os to avoid high voltage drops across switches. This might cause unwanted resets. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 141 Auxiliary Supply Operation DVSYS DVCC DVSYS source www.ti.com sink Correct Incorrect Figure 4-6. I/Os Powered by Auxiliary Supplies 4.2.9 Measuring the Supplies The primary and all auxiliary supply voltages can be measured if the device provides an ADC. The supply to be measured is selected with the AUXADCSELx bit in the AUXADCCTL register. In addition, the resistive load applied to the selected supply during the sampling phase of the ADC can be selected with the AUXADCRx bits. This allows to perform a "health" check of the supplies even when not loaded by the application. The ADC supply voltage channel (usually channel 12 (0Ch)) must be selected and the auxiliary supply voltage measurement must be enabled with AUXADC = 1. The resistive divider is connected to the supplies only during the sampling phase of the ADC. AUXADCSELx 2 DVCC 00 AUXVCC1 01 AUXVCC2 10 AUXVCC3 11 AUXADC ADC Sampling and INCHx = 0Ch AUXADCRx 2 To ADC (A12) Figure 4-7. AUX Connection to ADC 142 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Auxiliary Supply Operation 4.2.10 Resistive Charger Two simple resistive charging circuits are implemented to charge capacitors connected to AUXVCC2 and AUXVCC3. A simplified block diagram of the charger is shown in Figure 4-8. The charger for AUXVCC2 or AUXVCC3 is enabled by writing the correct key (069h) into the upper byte of AUX2CHCTL or AUX3CHCTL, respectively, together with AUXCHVx = 01b, AUXCHEN = 1 and selecting a charging resistor with AUXCHCx ≠ 00b. Writing to the charger control register with an incorrect key disables the charger, and all control register bits are reset to 0. Both chargers are disabled when DVCC is not selected as the supply source and AUXCHEN is reset by hardware. DVCC Charger Charger enable AUXCHCx AUXVCC2 or AUXVCC3 Figure 4-8. Charger Block Diagram 4.2.11 Auxiliary Supply Interrupts The auxiliary supply system provides seven interrupt sources: • AUXSWNMIFG: (non-)maskable supplies switched interrupt • AUX0SWIFG: switched to DVCC interrupt • AUX1SWIFG: switched to AUXVCC1 interrupt • AUX2SWIFG: switched to AUXVCC2 interrupt • AUX1DRPIFG: AUXVCC1 dropped below threshold interrupt • AUX2DRPIFG: AUXVCC2 dropped below threshold interrupt • AUXMONIFG: supply monitor interrupt The AUXSWNMIFG is set after the system switched from one supply to another supply. A nonmaskable interrupt request is generated if the AUXSWNMIE bit is set; otherwise, if (only) the AUXSWGIE bit and additionally the GIE bit are set, a maskable interrupt request is generated. The AUXxSWIFG bits are set if the auxiliary supply system switched to the corresponding supply (DVCC, AUXVCC1 or AUXVCC2). This information can be used in the interrupt service routine together with the interrupt vector generator AUXIV to reconfigure the device to the new supply situation. A (maskable) interrupt request is generated if the corresponding AUXxSWIE bit and the GIE bit are set. The AUXxDRPIFG bits are set if the corresponding supplies AUXxOK state changes from 1 to 0 due to the supply voltage dropping below the selected threshold value AUXxLVL with the hardware monitor being enabled (AUXxMD = 0). A (maskable) interrupt request is generated if the corresponding AUXxDRPIE bit and the GIE bit are set. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 143 Auxiliary Supply Operation www.ti.com The AUXMONIFG bit is set if a hardware monitoring cycle is completed and the supply AUXxOK states are updated accordingly. A (maskable) interrupt request is generated if the corresonding AUXMONIE bit and the GIE bit are set. 4.2.11.1 AUXIV, Interrupt Vector Generator All (maskable) auxiliary supply system interrupt sources are prioritized and combined to source a single interrupt vector. AUXIV is used to determine which enabled interrupt source requested an interrupt. The highest priority interrupt request that is enabled generates a number in the AUXIV register (see register description). This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled interrupts do not affect the AUXIV value. Any read access of the AUXIV register automatically resets the highest pending interrupt flag. A write access to the AUXIV register automatically resets all pending interrupt flags. All interrupt flags can also be cleared by software. 4.2.11.2 Auxiliary Supply Nonmaskable Interrupt If AUXSWNMIFG is configured as a nonmaskable interrupt source (with AUXSWNMIE=1), it will source (together with interrupt flags from other modules) the user-NMI interrupt vector. In the user-NMI interrupt service routine, the SYSUNIV interrupt vector word register can be evaluated or added to the program counter to automatically enter the appropriate part of the user-NMI interrupt service routine. Refer to device-specific data sheet concerning the user-NMI interrupt vector sources and priorities. If both AUXSWNMIE and AUXSWGIE are set, the nonmaskable interrupt service routine is called when AUXSWNMIFG is set because the user-NMI has a higher priority. In this case, both interrupt vector generators, the SYSUNIV and the AUXIV, indicate a pending AUXSWNMIFG. 144 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Auxiliary Supply Operation 4.2.12 Software Flow Figure 4-9 shows a sample software flow chart for the use and control of the auxiliary supply system. Reset “only” PUC no LOCKAUX=1? yes Configure Aux. Supply System LOCKAUX=0 AUXSW-ISR Interrupt Request by AUXxSWIFG “Main Program” DVCC Updated high-side SVM level (if needed) “New” Supply? AUX1 Updated high-side SVM level (if needed) AUX2 Updated high-side SVM level (if needed) Restore “Full” System Performance Reduce System Performance Reduce to RTC only Example RETI (End of ISR) NOTE: Configuration of the auxiliary supply system is required after wakeup from LPMx.5. None of the AUX registers are retained during LPMx.5. Figure 4-9. Software Flow Chart SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 145 Auxiliary Supply Operation www.ti.com 4.2.13 Examples of AUX Operation The following sections show sample configurations of the AUX module. Some settings in these examples do not apply to all devices; see the device-specific data sheet. 4.2.13.1 Example 1 This example shows configuration for running at 25-MHz system frequency at a supply voltage of 3 V ± 0.3 V, maintaining that frequency when switching to AUX1 or AUX2. The maximum SVMH level must be less than or equal to 2.7 V, so that switching occurs only when VDSYS goes outside 3 V ± 0.3 V. To switch back to DVCC/AVCC as soon as possible when it is within 3 V ± 0.3 V, the maximum AUX0LVL must also be less than or equal to 2.7 V. Because AUX0LVL must be 1 higher than SVSMHRRL, set AUX0LVL = 4 and SVSMHRRL = 3. To support 25-MHz operation, PMMCOREV must equal 3. With SVSMHRRL = 3, all core voltage settings are supported, so this is valid. Based on this core voltage setting, configure SVS levels (see Section 2.2.2.1.1.1 for details). To continue operation at 25-MHz without glitches even when using AUX1 and AUX2, the thresholds for these must be equal to or higher than SVSMHRRL. To minimize use of the auxiliary supplies, they should be set equal to SVSMHRRL. Therefore, set AUX1LVL and AUX2LVL = 3. 4.2.13.2 Example 2 This example shows configuration for running at a supply voltage of 3.3 V ± 0.3 V and allowing for switching supplies without functional glitches. The maximum SVMH level must be less than or equal to 3 V, so that switching occurs only when VDSYS goes outside 3.3 V ± 0.3 V. To switch back to DVCC/AVCC as soon as possible when it is within 3.3 V ± 0.3 V, the maximum AUX0LVL must also be less than or equal to 3 V. Because AUX0LVL must be 1 higher than SVSMHRRL, set = 6 and SVSMHRRL = 5. With SVSMHRRL = 5, the core voltage setting (PMMCOREV) must be 2 or 3. Assuming the application requires a system frequency up to 20 MHz, set PMMCOREV = 2. Based on this core voltage setting, configure SVS levels (see Section 2.2.2.1.1.1 for details). To continue operation without glitches when switching to AUX1 and AUX2, the thresholds for these must be equal to or higher than SVSMHRRL. To minimize use of the auxiliary supplies, they should be set equal to SVSMHRRL. Therefore, set AUX1LVL and AUX2LVL = 5. 4.2.13.3 Example 3 This example shows configuration for running at a system frequency of 8 MHz an a nominal supply voltage of 3.3 V with settings designed to minimize power consumption. To minimize power consumption at 8 MHz, set PMMCOREV = 0. With this core voltage, the recommended SVMH setting is SVSMHRRL = 0. Because AUX0LVL must be at least 1 higher than SVSMHRRL, set AUX0LVL = 1. To continue operation without glitches when switching to AUX1 and AUX2, the thresholds for these must be equal to or higher than SVSMHRRL. To minimize use of the auxiliary supplies, they should be set equal to SVSMHRRL. Therefore, set AUX1LVL and AUX2LVL = 0. 4.2.13.4 Example 4 This example shows configuration for running at a system frequency of 25 MHz when operating on a supply voltage of 3 V ± 0.3 V from DVCC, and then changing the system frequency to 12 MHz when supplied from AUX1 and to 8 MHz when supplied from AUX2. The maximum SVMH level must be less than or equal to 2.7 V, so that switching occurs only when VDSYS goes outside 3 V ± 0.3 V. To switch back to DVCC/AVCC as soon as possible when it is within 3 V ± 0.3 V, the maximum AUX0LVL must also be less than or equal to 2.7 V. Because AUX0LVL must be 1 higher than SVSMHRRL, set = 4 and SVSMHRRL = 3. 146 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Auxiliary Supply Operation To support 25-MHz operation, PMMCOREV must equal 3. With SVSMHRRL = 3, all core voltage settings are supported, so this is valid. Based on this core voltage setting, configure SVS levels (see Section 2.2.2.1.1.1 for details). When switching back to AUX0 (DVCC/AVCC) after having failed over to AUX1 or AUX2, these same settings must be restored. Given that the system frequency should be changed to 12 MHz when running from AUX1, settings must be changed when switching to AUX1. When switching from AUX0 (DVCC/AVCC) to AUX1: 1. Decrease system frequency to 12 MHz 2. Decrease core voltage level by setting PMMCOREV = 1 (also change SVS settings) 3. Decrease the SVM level by setting SVSMHRRL = 1 4. Set AUX1LVL and AUX2LVL to 1 When switching from AUX2 to AUX1: 1. Increase AUX1LVL and AUX2LVL to 1 2. Increase the SVM level by setting SVSMHRRL = 1 3. Increase core voltage level by setting PMMCOREV = 1 (also change SVS settings) 4. Increase system frequency to 12 MHz Given that the system frequency should be changed to 8 MHz when running from AUX2, settings must be changed when switching to AUX2. 1. Decrease system frequency to 8 MHz 2. Decrease core voltage level by setting PMMCOREV = 0 (also change SVS settings) 3. Decrease the SVM level by setting SVSMHRRL = 0 4. Set AUX1LVL and AUX2LVL to 0 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 147 AUX Registers www.ti.com 4.3 AUX Registers The registers to control the auxiliary supplies are listed in Table 4-4. The base address for the registers can be found in the device-specific data sheet. The address offsets are given in Table 4-4. The access key, AUXKEY, defined in the AUXCTL0 register controls access to the AUXCTLx registers. Once the correct key is written, the write access is enabled. The write access is disabled by writing a wrong key in byte mode to the AUXCTL0 upper byte. Word accesses to AUXCTL0 with a wrong key also disables the write access. A write access to a AUXCTLx register other than AUXCTL0 while write access is not enabled is ignored. NOTE: Bit Naming Convention The bits and bit fields in the AUXCTL0 to AUXCTL2 registers are named according to what supplies they refer to: AUX0... refers to DVCC, AUX1... refers to AUXVCC1, and AUX2... refers to AUXVCC2. In any description, the occurence of a bit name like AUXx... refers to all the bit names AUX0..., AUX1..., and AUX2.... Table 4-4. Auxiliary Supply Registers Offset Acronym Register Name 00h AUXCTL0 Auxiliary Supply Control 0 register(1) 02h AUXCTL1 Auxiliary Supply Control 1 register(1) 04h AUXCTL2 Auxiliary Supply Control 2 register(1) 06h Reserved 08h Reserved 0Ah Reserved 0Ch Reserved 0Eh Reserved 10h Reserved 12h AUX2CHCTL AUX2 Charger Control 14h AUX3CHCTL AUX3 Charger Control 16h AUXADCCTL AUX ADC Control 18h Reserved 1Ah AUXIFG AUX Interrupt Flag 1Ch AUXIE AUX Interrupt Enable 1Eh AUXIV AUX Interrupt Vector Word (1) Access protected by key AUXKEY in AUXCTL0. Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Reset 9601h 0000h 0000h 5A00h 5A00h 0000h 0000h 0000h 0000h Section Section 4.3.1 Section 4.3.2 Section 4.3.3 Section 4.3.4 Section 4.3.5 Section 4.3.6 Section 4.3.7 Section 4.3.8 Section 4.3.9 148 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.3.1 AUXCTL0 Register Auxiliary Supply Control 0 Register Figure 4-10. AUXCTL0 Register 15 14 13 12 11 10 AUXKEY rw-1 rw-0 rw-0 rw-1 rw-0 rw-1 7 6 5 4 3 2 Reserved AUX2SW AUX1SW r0 r0 r0 r0 r-(0) r-(0) AUX Registers 9 rw-1 1 AUX0SW r-(0) 8 rw-0 0 LOCKAUX r/w0-[1] Bit 15-8 7-4 3 Field AUXKEY Reserved AUX2SW 2 AUX1SW 1 AUX0SW 0 LOCKAUX Type RW R R R R RW Table 4-5. AUXCTL0 Register Description Reset 96h 0h 0h 0h 0h 0h Description AUX access key. Always read as 096h. Must be written with 0A5h or all writes to AUXCTLx registers are ignored. Reserved. Always reads as 0. AUXVCC2 switch state 0b = AUXVCC2 switch open 1b = AUXVCC2 switch closed AUXVCC1 switch state 0b = AUXVCC1 switch open 1b = AUXVCC1 switch closed DVCC switch state 0b = DVCC switch open 1b = DVCC switch closed Lock auxiliary supply system. Can only be written as 0. LOCKAUX is always set to 1 by hardware after the core was powered down either due to a complete power cycle of the main suppies (DVCC, AUXVCC1, or AUXVCC2) or due to LPMx.5 operation. 0b = Auxiliary supply system not locked 1b = Auxiliary supply system locked - operating from either DVCC or AUXVCC1 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 149 AUX Registers 4.3.2 AUXCTL1 Register Auxiliary Supply Control 1 Register Figure 4-11. AUXCTL1 Register 15 14 13 12 11 10 Reserved AUX2MD r0 r0 r0 r0 r0 rw-(0) 7 6 5 4 3 2 Reserved AUX2PRIO AUX2OK r0 r0 r0 r0 rw-(0) rw-(0) 9 AUX1MD rw-(0) 1 AUX1OK rw-(0) www.ti.com 8 AUX0MD rw-(0) 0 AUX0OK rw-(0) Bit 15-11 10 Field Reserved AUX2MD 9 AUX1MD 8 AUX0MD 7-4 Reserved 3 AUX2PRIO 2 AUX2OK 1 AUX1OK 0 AUX0OK Type R RW RW RW R RW RW RW RW Table 4-6. AUXCTL1 Register Description Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. AUXVCC2 auxiliary supply mode 0b = Hardware controlled 1b = Software controlled AUXVCC1 auxiliary supply mode 0b = Hardware controlled 1b = Software controlled DVCC auxiliary supply mode 0b = Hardware controlled 1b = Software controlled Reserved. Always reads as 0. Auxiliary supply AUXVCC2 priority. Defines order of switching between AUXVCC1 and AUXVCC2. 0b = AUXVCC2 has lower priority than AUXVCC1 1b = AUXVCC2 has higher priority than AUXVCC1 AUXVCC2 okay flag. Read-only if AUX2MD = 0 and indicates the status monitored by the hardware based on the selected level AUX2LVLx. If AUX2MD = 1 the bit must be controlled by software to indicate the status of the supply. It is not modified by hardware in this case. 0b = Supply not okay - below AUX2LVLx if AUX2MD = 0 1b = Supply okay - above AUX2LVLx if AUX2MD = 0 AUXVCC1 okay flag. Read-only if AUX1MD = 0 and indicates the status monitored by the hardware based on the selected level AUX1LVLx. If AUX1MD = 1 the bit must be controlled by software to indicate the status of the supply. It is not modified by hardware in this case. 0b = Supply not okay - below AUX1LVLx if AUX1MD = 0 1b = Supply okay - above AUX1LVLx if AUX1MD = 0 DVCC okay flag. Read-only if AUX0MD = 0 and indicates the status monitored by the hardware based on the selected level AUX0LVLx. If AUX0MD = 1 the bit must be controlled by software to indicate the status of the supply. It is not modified by hardware in this case. 0b = Supply not okay - below AUX0LVLx if AUX0MD = 0 1b = Supply okay - above AUX0LVLx if AUX0MD = 0 150 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.3.3 AUXCTL2 Register Auxiliary Supply Control 2 Register 15 14 Reserved r0 r0 7 Reserved r0 6 rw-(0) Figure 4-12. AUXCTL2 Register 13 12 11 10 AUXMRx Reserved rw-(0) rw-(0) r0 rw-(0) 5 AUX1LVLx rw-(0) 4 rw-(0) 3 Reserved r0 2 rw-(0) AUX Registers 9 AUX2LVLx rw-(0) 1 AUX0LVLx rw-(0) 8 rw-(0) 0 rw-(0) Bit 15-14 13-12 Field Reserved AUXMRx 11 10-8 Reserved AUX2LVLx 7 Reserved 6-4 AUX1LVLx 3 Reserved 2-0 AUX0LVLx Type R RW R RW R RW R RW Table 4-7. AUXCTL2 Register Description Reset 0h 0h 0h 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. Auxiliary supply monitoring rate 00b = Continous monitoring 01b = Monitoring every 32 VLO clock cycles (≈5ms) 10b = Monitoring every 1024 VLO clock cycles (≈150ms) 11b = Reserved Reserved. Always reads as 0. AUXVCC2 auxiliary supply threshold level. The levels are specified in the devicespecific data sheet. 000b = Approximately 1.74 V 001b = Approximately 1.94 V 010b = Approximately 2.14 V 011b = Approximately 2.26 V 100b = Approximately 2.40 V 101b = Approximately 2.70 V 110b = Approximately 3.00 V 111b = Approximately 3.00 V Reserved. Always reads as 0. AUXVCC1 auxiliary supply threshold level. The levels are specified in the devicespecific data sheet. 000b = Approximately 1.74 V 001b = Approximately 1.94 V 010b = Approximately 2.14 V 011b = Approximately 2.26 V 100b = Approximately 2.40 V 101b = Approximately 2.70 V 110b = Approximately 3.00 V 111b = Approximately 3.00 V Reserved. Always reads as 0. DVCC auxiliary supply threshold level. The levels are specified in the devicespecific data sheet. 000b = Approximately 1.74 V 001b = Approximately 1.94 V 010b = Approximately 2.14 V 011b = Approximately 2.26 V 100b = Approximately 2.40 V 101b = Approximately 2.70 V 110b = Approximately 3.00 V 111b = Approximately 3.00 V SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 151 AUX Registers 4.3.4 AUX2CHCTL Register AUX Charger Control Register for AUX2 15 14 rw-0 rw-1 7 6 Reserved r0 r0 Figure 4-13. AUX2CHCTL Register 13 12 11 10 9 AUXCHKEYx rw-0 rw-1 rw-1 rw-0 rw-1 5 4 AUXCHVx rw-0 rw-0 3 Reserved r0 2 1 AUXCHCx rw-0 rw-0 www.ti.com 8 rw-0 0 AUXCHEN rw-0 Bit 15-8 Field AUXCHKEYx 7-6 Reserved 5-4 AUXCHVx 3 Reserved 2-1 AUXCHCx 0 AUXCHEN Table 4-8. AUX2CHCTL Register Description Type RW R RW R RW RW Reset 5Ah 0h 0h 0h 0h 0h Description Charger access key. Always read as 05Ah. Must be written as 069h together with low byte; writing any other value disables the charger and all control register bits are reset to 0. Reserved. Always reads as 0. Charger end voltage 00b = Charger disabled 01b = VCC 10b = Reserved 11b = Reserved Reserved. Always reads as 0. Charger charge current 00b = Charger disabled 01b = Charge current defined by a maximum 5-kΩ resistor 10b = Charge current defined by a maximum 10-kΩ resistor 11b = Charge current defined by a maximum 20-kΩ resistor Charger enable 0b = Charger disabled 1b = Charger enabled 152 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.3.5 AUX3CHCTL Register AUX Charger Control Register for AUX3 15 14 rw-0 rw-1 7 6 Reserved r0 r0 Figure 4-14. AUX3CHCTL Register 13 12 11 10 9 AUXCHKEYx rw-0 rw-1 rw-1 rw-0 rw-1 5 4 AUXCHVx rw-0 rw-0 3 Reserved r0 2 1 AUXCHCx rw-0 rw-0 AUX Registers 8 rw-0 0 AUXCHEN rw-0 Bit 15-8 Field AUXCHKEYx 7-6 Reserved 5-4 AUXCHVx 3 Reserved 2-1 AUXCHCx 0 AUXCHEN Table 4-9. AUX3CHCTL Register Description Type RW R RW R RW RW Reset 5Ah 0h 0h 0h 0h 0h Description Charger access key. Always read as 05Ah. Must be written as 069h together with low byte; writing any other value disables the charger and all control register bits are reset to 0. Reserved. Always reads as 0. Charger end voltage 00b = Charger disabled 01b = VCC 10b = Reserved 11b = Reserved Reserved. Always reads as 0. Charger charge current 00b = Charger disabled 01b = Charge current defined by a maximum 5-kΩ resistor 10b = Charge current defined by a maximum 10-kΩ resistor 11b = Charge current defined by a maximum 20-kΩ resistor Charger enable 0b = Charger disabled 1b = Charger enabled SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 153 AUX Registers 4.3.6 AUXADCCTL Register Auxiliary Supply ADC Control Register 15 14 r0 r0 7 6 Reserved r0 r0 Figure 4-15. AUXADCCTL Register 13 12 11 10 9 Reserved r0 r0 r0 r0 r0 5 4 AUXADCRx rw-0 rw-0 3 Reserved r0 2 1 AUXADCSELx rw-0 rw-0 www.ti.com 8 r0 0 AUXADC rw-0 Bit 15-6 5-4 Field Reserved AUXADCRx 3 Reserved 2-1 AUXADCSELx 0 AUXADC Table 4-10. AUXADCCTL Register Description Type R RW R RW RW Reset 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. Load resistance (R(tot) = 3R) during sampling of selected supply. Refer to the device-specific data sheet, too. 00b = R(tot) ≈ 15 kΩ - I = U/R = 3.6 V / 15 kΩ = 240 µA; I = 1.8 V / 16 kΩ = 120 µA 01b = R(tot) ≈ 1.5 kΩ - I = 2.4 mA at 3.6 V; I = 1.2 mA at 1.8V 10b = R(tot) ≈ 0.5 kΩ - I = 7.2 mA at 3.6 V; I = 3.6 mA at 1.8 V 11b = Reserved Reserved. Always reads as 0. Select supply to be measured with ADC. 00b = DVCC 01b = AUXVCC1 10b = AUXVCC2 11b = AUXVCC3 Auxiliary supplies to ADC 0b = Auxiliary supply measurement disabled 1b = Auxiliary supply measurement enabled 154 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.3.7 AUXIFG Register Auxiliary Supply Interrupt Flag Register AUX Registers 15 r0 7 AUXMONIFG rw-(0) 14 13 r0 6 AUX2DRPIFG rw-(0) r0 5 AUX1DRPIFG rw-(0) Figure 4-16. AUXIFG Register 12 11 10 Reserved r0 r0 r0 4 Reserved rw-(0) 3 Reserved r0 2 AUX2SWIFG rw-(0) 9 r0 1 AUX1SWIFG rw-(0) 8 AUXSWNMIFG rw-(0) 0 AUX0SWIFG rw-(0) Bit 15-9 8 Field Reserved AUXSWNMIFG 7 AUXMONIFG 6 AUX2DRPIFG 5 AUX1DRPIFG 4 Reserved 3 Reserved 2 AUX2SWIFG 1 AUX1SWIFG 0 AUX0SWIFG Type R RW RW RW RW RW R RW RW RW Table 4-11. AUXIFG Register Description Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. Supplies switched (non-)maskable interrupt flag. Set if a switch from any supply to any other supply happened. Sources an NMI if AUXSWNMIE is set, otherwise sources a maskable interrupt if AUXSWGIE and GIE is set. 0b = No interrupt pending 1b = Interrupt pending Supply monitor interrupt flag. Set after completion of a hardware monitoring cycle. 0b = No interrupt pending 1b = Interrupt pending AUXVCC2 dropped below its threshold interrupt flag. 0b = No interrupt pending 1b = Interrupt pending AUXVCC1 dropped below its threshold interrupt flag. 0b = No interrupt pending 1b = Interrupt pending Reserved. Always write as 0. Reserved. Always reads as 0. Switched to AUXVCC2 interrupt flag. 0b = No interrupt pending 1b = Interrupt pending Switched to AUXVCC1 interrupt flag. 0b = No interrupt pending 1b = Interrupt pending Switched to DVCC interrupt flag. 0b = No interrupt pending 1b = Interrupt pending SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 155 AUX Registers 4.3.8 AUXIE Register Auxiliary Supply Interrupt Enable Register 15 r0 7 AUXMONIE rw-0 14 13 r0 6 AUX2DRPIE rw-0 r0 5 AUX1DRPIE rw-0 Figure 4-17. AUXIE Register 12 11 10 Reserved r0 r0 r0 4 Reserved rw-0 3 AUXSWGIE rw-0 2 AUX2SWIE rw-0 www.ti.com 9 r0 1 AUX1SWIE rw-0 8 AUXSWNMIE r0 0 AUX0SWIE rw-0 Bit 15-9 8 Field Reserved AUXSWNMIE 7 AUXMONIE 6 AUX2DRPIE 5 AUX1DRPIE 4 Reserved 3 AUXSWGIE 2 AUX2SWIE 1 AUX1SWIE 0 AUX0SWIE Type R R RW RW RW RW RW RW RW RW Table 4-12. AUXIE Register Description Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. Supplies switched non-maskable interrupt enable. 0b = Non-maskable interrupt disabled 1b = Non-maskable interrupt enabled Supply monitor interrupt enable. 0b = Interrupt disabled 1b = Interrupt enabled AUXVCC2 dropped below its threshold interrupt enable. 0b = Interrupt disabled 1b = Interrupt enabled AUXVCC1 dropped below its threshold interrupt enable. 0b = Interrupt disabled 1b = Interrupt enabled Reserved. Always write as 0. Global supply switched interrupt enable. 0b = Interrupt disabled 1b = Interrupt enabled Switched to AUXVCC2 interrupt enable. 0b = Interrupt disabled 1b = Interrupt enabled Switched to AUXVCC1 interrupt enable. 0b = Interrupt disabled 1b = Interrupt enabled Switched to DVCC interrupt enable. 0b = Interrupt disabled 1b = Interrupt enabled 156 Auxiliary Supply System (AUX) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 4.3.9 AUXIV Register Auxiliary Supply Interrupt Vector Register Figure 4-18. AUXIV Register 15 14 13 12 11 10 AUXIVx r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 AUXIVx r0 r0 r-(0) r-(0) r-(0) r-(0) AUX Registers 9 8 r0 r0 1 0 r-(0) r0 Bit 15-0 Field AUXIVx Type R Table 4-13. AUXIV Register Description Reset 0h Description Auxiliary Supply Interrupt vector value. It generates a value that can be used as address offset for fast interrupt service routine handling. Writing to this register clears all pending interrupt flags. 00h = No interrupt pending 02h = Interrupt Source: Global (non-)maskable supply switched interrupt flag; Interrupt Flag: AUXSWNMIFG; Interrupt Priority: Highest 04h = Interrupt Source: Switched to DVCC interrupt flag; Interrupt Flag: AUX0SWIFG 06h = Interrupt Source: Switched to AUXVCC1 interrupt flag; Interrupt Flag: AUX1SWIFG 08h = Interrupt Source: Switched to AUXVCC2 interrupt flag; Interrupt Flag: AUX2SWIFG 0Ah = Interrupt Source: Reserved; Interrupt Flag: - 0Ch = Interrupt Source: AUXVCC1 below threshold interrupt flag; Interrupt Flag: AUX1DRPIFG 0Eh = Interrupt Source: AUXVCC2 below threshold interrupt flag; Interrupt Flag: AUX2DRPIFG 10h = Interrupt Source: Supply monitor interrupt flag; Interrupt Flag: AUXMONIFG; Interrupt Priority: Lowest SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Auxiliary Supply System (AUX) 157 Chapter 5 SLAU208O – June 2008 – Revised May 2015 Unified Clock System (UCS) The Unified Clock System (UCS) module provides the various clocks for a device. This chapter describes the operation of the UCS module, which is implemented in all devices. Topic ........................................................................................................................... Page 5.1 Unified Clock System (UCS) Introduction ............................................................ 159 5.2 UCS Operation ................................................................................................. 161 5.3 Module Oscillator (MODOSC) ............................................................................. 172 5.4 UCS Registers.................................................................................................. 173 158 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Unified Clock System (UCS) Introduction 5.1 Unified Clock System (UCS) Introduction The UCS module supports low system cost and ultra-low power consumption. Using three internal clock signals, the user can select the best balance of performance and low power consumption. The UCS module can be configured to operate without any external components, with one or two external crystals, or with resonators, under full software control. The UCS module includes up to five clock sources: • XT1CLK: Low-frequency or high-frequency oscillator that can be used either with low-frequency 32768Hz watch crystals, standard crystals, resonators, or external clock sources in the 4 MHz to 32 MHz range. XT1CLK can be used as a clock reference into the FLL. Some devices only support the lowfrequency oscillator for XT1CLK. See the device-specific data sheet for supported functions. • VLOCLK: Internal very low power, low-frequency oscillator with 10-kHz typical frequency • REFOCLK: Internal, trimmed, low-frequency oscillator with 32768-Hz typical frequency, with the ability to be used as a clock reference into the FLL • DCOCLK: Internal digitally controlled oscillator (DCO) that can be stabilized by the FLL • XT2CLK: Optional high-frequency oscillator that can be used with standard crystals, resonators, or external clock sources in the 4 MHz to 32 MHz range. XT2CLK can be used as a clock reference into the FLL. Three clock signals are available from the UCS module: • ACLK: Auxiliary clock. The ACLK is software selectable as XT1CLK, REFOCLK, VLOCLK, DCOCLK, DCOCLKDIV, and when available, XT2CLK. DCOCLKDIV is the DCOCLK frequency divided by 1, 2, 4, 8, 16, or 32 within the FLL block. ACLK can be divided by 1, 2, 4, 8, 16, or 32. ACLK/n is ACLK divided by 1, 2, 4, 8, 16, or 32 and is available externally at a pin. ACLK is software selectable by individual peripheral modules. • MCLK: Master clock. MCLK is software selectable as XT1CLK, REFOCLK, VLOCLK, DCOCLK, DCOCLKDIV, and when available, XT2CLK. DCOCLKDIV is the DCOCLK frequency divided by 1, 2, 4, 8, 16, or 32 within the FLL block. MCLK can be divided by 1, 2, 4, 8, 16, or 32. MCLK is used by the CPU and system. • SMCLK: Subsystem master clock. SMCLK is software selectable as XT1CLK, REFOCLK, VLOCLK, DCOCLK, DCOCLKDIV, and when available, XT2CLK. DCOCLKDIV is the DCOCLK frequency divided by 1, 2, 4, 8, 16, or 32 within the FLL block. SMCLK can be divided by 1, 2, 4, 8, 16, or 32. SMCLK is software selectable by individual peripheral modules. The block diagram of the UCS module is shown in Figure 5-1. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 159 Unified Clock System (UCS) Introduction OSC XT1BYPASS 1 0 XT1 Fault Detection VLO XT1CLK VLOCLK REFOCLK XTS REFO XIN XOUT XT1 0V LF HF 0V 2 2 XCAP XT1DRIVE FLL FLLREFDIV 3 Divider /1/2/4/8/12/16 10 FLLN Divider /(N+1) SCG0 PUC off Reset + 10-bit Frequency Integrator − SCG1 DCORSELDISMOD DCO, 3 10 MOD off DC Generator DCO + Modulator FLLD 3 Prescaler /1/2/4/8/16/32 FLLREFCLK SELREF 3 000 001 010 011 100 101 110 111 DCOCLK DCOCLKDIV XT2IN XT2 (Optional) XT2BYPASS 1 XT2CLK 0 XT2 Fault Detection XT20FF 2 XT2DRIVE XT2OUT XT2 Oscillator Figure 5-1. UCS Block Diagram www.ti.com ACLK_REQEN ACLK_REQ SELA 3 OSCOFF ACLK Enable Logic EN 3 000 001 DIVA 3 010 011 Divider /1/2/4/8/16/32 0 100 101 1 110 111 DIVPA 3 Divider ACLK/n /1/2/4/8/16/32 ACLK MCLK_REQEN MCLK_REQ SELM 3 CPUOFF MCLK Enable Logic EN 3 000 001 DIVM 3 010 011 Divider /1/2/4/8/16/32 0 100 101 1 110 111 MCLK SMCLK_REQEN SMCLK_REQ SELS 3 SMCLKOFF SMCLK Enable Logic EN 3 000 001 DIVS 3 010 011 Divider /1/2/4/8/16/32 0 100 101 1 110 111 MODOSC_REQEN SMCLK MODOSC_REQ Unconditonal MODOSC request.s EN MODOSC MODCLK 160 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com UCS Operation 5.2 UCS Operation After a PUC, the UCS module default configuration is: • XT1 in LF mode is selected as the oscillator source for XT1CLK. XT1CLK is selected for ACLK. • DCOCLKDIV is selected for MCLK. • DCOCLKDIV is selected for SMCLK. • FLL operation is enabled and XT1CLK is selected as the FLL reference clock, FLLREFCLK. • On devices that have XIN and XOUT shared with general-purpose I/O, XIN and XOUT pins are set to general-purpose I/Os and XT1 remains disabled until the I/O ports are configured for XT1 operation. If XIN and XOUT are not shared with general-purpose I/Os, XT1 is enabled. • When available, XT2IN and XT2OUT pins are set to general-purpose I/Os and XT2 is disabled. As previously stated, FLL operation with XT1 is selected by default. If the crystal pins (XIN, XOUT) are shared with general-purpose I/Os, XT1 will remain disabled until the PSEL bits associated with the crystal pins are set. If XIN and XOUT are not shared with general-purpose I/O, XT1 is enabled. When a 32768Hz crystal is used for XT1CLK, the fault control logic immediately causes ACLK to be sourced by the REFOCLK, because XT1 is not stable immediately (see Section 5.2.12). When crystal startup is obtained and settled, the FLL stabilizes MCLK and SMCLK to 1.048576 MHz and fDCO = 2.097152 MHz. Status register control bits (SCG0, SCG1, OSCOFF, and CPUOFF) configure the operating modes and enable or disable portions of the UCS module (see the SYS chapter). Registers UCSCTL0 through UCSCTL8 configure the UCS module. The UCS module can be configured or reconfigured by software at any time during program execution. NOTE: For devices using RTC_B, RTC_C, or RTC_D (RTC modules that support LPM3.5), setting bit RTCHOLD = 0 in register RTCCTL1 also enables XT1, independent from UCS configuration. 5.2.1 UCS Module Features for Low-Power Applications Conflicting requirements typically exist in battery-powered applications: • Low clock frequency for energy conservation and time keeping • High clock frequency for fast response times and fast burst processing capabilities • Clock stability over operating temperature and supply voltage • Low-cost applications with less-constrained clock accuracy requirements The UCS module addresses these conflicting requirements by allowing the user to select from the three available clock signals: ACLK, MCLK, and SMCLK. All three available clock signals can be sourced from any of the available clock sources (XT1CLK, VLOCLK, REFOCLK, DCOCLK, DCOCLKDIV, or XT2CLK), giving complete flexibility in the system clock configuration. A flexible clock distribution and divider system is provided to fine tune the individual clock requirements. 5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) The internal VLO provides a typical frequency of 10 kHz (see device-specific data sheet for parameters) without requiring a crystal. The VLO provides for a low-cost ultra-low-power clock source for applications that do not require an accurate time base. The VLO is enabled when it is used to source ACLK, MCLK, or SMCLK (SELA = {1} or SELM = {1} or SELS = {1}). SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 161 UCS Operation www.ti.com 5.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO) The internal trimmed low-frequency REFO can be used for cost-sensitive applications where a crystal is not required or desired. REFO is internally trimmed to 32.768 kHz typical and provides for a stable reference frequency that can be used as FLLREFCLK. REFO, combined with the FLL, provides for a flexible range of system clock settings without the need for a crystal. REFO consumes no power when not being used. REFO is enabled under any of the following conditions: • REFO is a source for ACLK (SELA = {2}) and in active mode (AM) through LPM3 (OSCOFF = 0) • REFO is a source for MCLK (SELM = {2}) and in active mode (AM) (CPUOFF = 0) • REFO is a source for SMCLK (SELS = {2}) and in active mode (AM) through LPM1 (SMCLKOFF = 0) • REFO is a source for FLLREFCLK (SELREF = {2}) and the DCO is a source for ACLK (SELA = {3,4}) and in active mode (AM) through LPM3 (OSCOFF = 0) • REFO is a source for FLLREFCLK (SELREF = {2}) and the DCO is a source for MCLK (SELM = {3,4}) and in active mode (AM) (CPUOFF = 0) • REFO is a source for FLLREFCLK (SELREF = {2}) and the DCO is a source for SMCLK (SELS = {3,4}) and in active mode (AM) through LPM1 (SMCLKOFF = 0) NOTE: REFO Enable for MSP430F543x, MSP430F541x devices REFO is enabled under any of the following conditions: • REFO is a source for ACLK (SELA = {2}), MCLK (SELM = {2}), or SMCLK (SELS = {2}) and in active mode (AM) through LPM3 (OSCOFF = 0) • REFO is a source for FLLREFCLK (SELREF = {2}) and the DCO is a source for ACLK, MCLK, or SMCLK (SELA = {3,4}), MCLK (SELM = {3,4}), or SMCLK (SELS = {3,4}) and in active mode (AM) through LPM3 (OSCOFF = 0) 5.2.4 XT1 Oscillator The XT1 oscillator supports ultra-low-current consumption using a 32768-Hz watch crystal in lowfrequency (LF) mode (XTS = 0) . A watch crystal connects to XIN and XOUT without any other external components. The software-selectable XCAP bits configure the internally provided load capacitance for the XT1 crystal in LF mode. This capacitance can be selected as 2 pF, 6 pF, 9 pF, or 12 pF (typical). Additional external capacitors can be added if necessary. On some devices, the XT1 oscillator also supports high-speed crystals or resonators when in highfrequency (HF) mode (XTS = 1). The high-speed crystal or resonator connects to XIN and XOUT and requires external capacitors on both terminals. These capacitors should be sized according to the crystal or resonator specifications. The drive settings of XT1 in LF mode can be increased with the XT1DRIVE bits. At power up, the XT1 starts with the highest drive settings for fast, reliable startup. If needed, user software can reduce the drive strength to further reduce power. In HF mode, different crystal or resonator ranges are supported by choosing the proper XT1DRIVE settings . XT1 may be used with an external clock signal on the XIN pin in either LF or HF mode by setting XT1BYPASS. When used with an external signal, the external frequency must meet the data sheet parameters for the chosen mode. XT1 is powered down when used in bypass mode. Some devices support XT1 bypass operation with external clock inputs that reside on a different external supply domain, called DVIO. Refer to the device-specific data sheet. On these devices, DVIO has a voltage range of 1.8 V ± 10 %. When using the XT1 bypass operation with external clock inputs that reside on DVIO, it is required that XT1BYPASSLV = 1. For example, when XT1BYPASSLV = 1, it is assumed the external clock signal swings from 0 V to DVIO. With XT1BYPASS = 0, it is assumed the external clock signal swings from 0 V to DVCC. The usage of XT1BYPASSLV allows for interfacing to external clock sources that reside on either the DVCC or DVIO supply domains. When used with an external signal, the external frequency must meet the data sheet parameters for the chosen mode. XT1 is powered down when used in bypass mode. 162 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com UCS Operation On many devices, the XT1 pins are shared with general-purpose I/O ports (refer to the device-specific data sheet for availability). At power up, the default operation is XT1, LF mode of operation. However, for devices that have XT1 shared with general-purpose I/O ports, XT1 will remain disabled until the ports shared with XT1 are configured for XT1 operation. The configuration of the shared I/O is determined by the PSEL bit associated with XIN and the XT1BYPASS bit. Setting the PSEL bit causes the XIN and XOUT ports to be configured for XT1 operation. If XT1BYPASS is also set, XT1 is configured for bypass mode of operation, and the oscillator associated with XT1 is powered down. In bypass mode of operation, XIN can accept an external clock input signal and XOUT is configured as a general-purpose I/O. The PSEL bit associated with XOUT is a don't care. If the PSEL bit associated with XIN is cleared, both XIN and XOUT ports are configured as general-purpose I/Os, and XT1 is disabled. On devices where XT1 is not shared with general-purpose I/O ports, XT1 is enabled at power up. In bypass mode of operation (XT1BYPASS = 1), XIN can accept an external clock input signal, and XT1 is powered down. XT1 is enabled under any of the following conditions: • XT1 is a source for ACLK (SELA = {0}) and in active mode (AM) through LPM3 (OSCOFF = 0) • XT1 is a source for MCLK (SELM = {0}) and in active mode (AM) (CPUOFF = 0) • XT1 is a source for SMCLK (SELS = {0}) and in active mode (AM) through LPM1 (SMCLKOFF = 0) • XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for ACLK (SELA = {3,4}) and in active mode (AM) through LPM3 (OSCOFF = 0) • XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for MCLK (SELM = {3,4}) and in active mode (AM) (CPUOFF = 0) • XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for SMCLK (SELS = {3,4}) and in active mode (AM) through LPM1 (SMCLKOFF = 0) • XT1OFF = 0. XT1 enabled in active mode (AM) through LPM4. For devices that support LPMx.5, XT1 also remains enabled. NOTE: XT1 Enable for MSP430F543x, MSP430F541x devices XT1 is enabled under any of the following conditions: • XT1 is a source for ACLK, MCLK, or SMCLK (SELA = {0}), MCLK (SELM = {0}), or SMCLK (SELS = {0}) and in active mode (AM) through LPM3 (OSCOFF = 0) • XT1 is a source for FLLREFCLK (SELREF = {0}) and the DCO is a source for ACLK, MCLK, or SMCLK (SELA = {3,4}), MCLK (SELM = {3,4}), or SMCLK (SELS = {3,4}) and in active mode (AM) through LPM3 (OSCOFF = 0) • XT1OFF = 0. XT1 enabled in active mode (AM) through LPM4. 5.2.5 XT2 Oscillator Some devices have a second crystal oscillator, XT2. XT2 sources XT2CLK, and its characteristics are identical to XT1 in HF mode. The XT2DRIVE bits select the frequency range of operation of XT2. XT2 may be used with external clock signals on the XT2IN pin by setting XT2BYPASS. When used with an external signal, the external frequency must meet the data-sheet parameters for XT2. XT2 is powered down when used in bypass mode. Some devices support XT2 bypass operation with external clock inputs that reside on a different external supply domain, called DVIO. Refer to the device-specific data sheet. On these devices, DVIO has a voltage range of 1.8 V ±10%. When using the XT2 bypass operation with external clock inputs that reside on DVIO, it is required that XT2BYPASSLV = 1. For example, when XT2BYPASSLV = 1, it is assumed the external clock signal swings from 0 V to DVIO. With XT2BYPASS = 0, it is assumed the external clock signal swings from 0 V to DVCC. The use of XT2BYPASSLV allows for interfacing to external clock sources that reside on either the DVCC or DVIO supply domains. When used with an external signal, the external frequency must meet the data sheet parameters for the chosen mode. XT2 is powered down when used in bypass mode. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 163 UCS Operation www.ti.com The XT2 pins are shared with general-purpose I/O ports. At power up, the default operation is XT2. However, XT2 remains disabled until the ports shared with XT2 are configured for XT2 operation. The configuration of the shared I/O is determined by the PSEL bit associated with XT2IN and the XT2BYPASS bit. Setting the PSEL bit causes the XT2IN and XT2OUT ports to be configured for XT2 operation. If XT2BYPASS is also set, XT2 is configured for bypass mode of operation, and the oscillator associated with XT2 is powered down. In bypass mode of operation, XT2IN can accept an external clock input signal and XT2OUT is configured as a general-purpose I/O. The PSEL bit associated with XT2OUT is a don't care. If the PSEL bit associated with XT2IN is cleared, both XT2IN and XT2OUT ports are configured as general-purpose I/Os, and XT2 is disabled. XT2 is enabled under any of the following conditions: • XT2 is a source for ACLK (SELA = {5,6,7}) and in active mode (AM) through LPM3 (OSCOFF = 0) • XT2 is a source for MCLK (SELM = {5,6,7}) and in active mode (AM) (CPUOFF = 0) • XT2 is a source for SMCLK (SELS = {5,6,7}) and in active mode (AM) through LPM1 (SMCLKOFF = 0) • XT2 is a source for FLLREFCLK (SELREF = {5,6}) and the DCO is a source for ACLK (SELA = {3,4}) and in active mode (AM) through LPM3 (OSCOFF = 0) • XT2 is a source for FLLREFCLK (SELREF = {5,6}) and the DCO is a source for MCLK (SELM = {3,4}) and in active mode (AM) (CPUOFF = 0) • XT2 is a source for FLLREFCLK (SELREF = {5,6}) and the DCO is a source for SMCLK (SELS = {3,4}) and in active mode (AM) through LPM1 (SMCLKOFF = 0) • XT2OFF = 0. XT2 enabled in active mode (AM) through LPM4. For devices that support LPMx.5, XT2 also remains enabled. NOTE: XT2 Enable for MSP430F543x and MSP430F541x devices XT2 is enabled under any of the following conditions: • XT2 is a source for ACLK, MCLK, or SMCLK (SELA = {5,6,7}), MCLK (SELM = {5,6,7}), or SMCLK (SELS = {5,6,7}) and in active mode (AM) through LPM3 (OSCOFF = 0) • XT2 is a source for FLLREFCLK (SELREF = {5,6,7}) and the DCO is a source for ACLK, MCLK, or SMCLK (SELA = {3,4}), MCLK (SELM = {3,4}), or SMCLK (SELS = {3,4}) and in active mode (AM) through LPM3 (OSCOFF = 0) • XT2OFF = 0. XT2 enabled in active mode (AM) through LPM4. 5.2.6 Digitally Controlled Oscillator (DCO) The DCO is an integrated digitally controlled oscillator. The DCO frequency can be adjusted by software using the DCORSEL, DCO, and MOD bits. The DCO frequency can be optionally stabilized by the FLL to a multiple frequency of FLLREFCLK/n. The FLL can accept different reference sources selectable by the SELREF bits. Reference sources include XT1CLK, REFOCLK, or XT2CLK (if available) . The value of n is defined by the FLLREFDIV bits (n = 1, 2, 4, 8, 12, or 16). The default is n = 1. There may be scenarios in which FLL operation is not required or desired; in these cases, no FLLREFCLK is necessary. This can be accomplished by setting SELREF = {7}. NOTE: For the F543x and F541x non-A versions only. Setting SELREF = {7} sets XT2CLK as the FLL reference clock. The FLLD bits configure the FLL prescaler divider value D to 1, 2, 4, 8, 16, or 32. By default, D = 2, and MCLK and SMCLK are sourced from DCOCLKDIV, providing a clock frequency DCOCLK/2. 164 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com UCS Operation The divider (N + 1) and the divider value D define the DCOCLK and DCOCLKDIV frequencies. The divider (N + 1) can be set using the FLLN bits, where N > 0. The smallest divider (N + 1) that can be used is a divider of two. The logic will cause FLLN = 1h, if FLLN = 0h is unintentionally written. Therefore setting FLLN = 0h is also equivalent to setting FLLN = 1h and will result in a divider of 2. All other FLLN settings behave as described; for example, FLLN = 2h results in a divider of 3, or FLLN = 3h results in a divider of 4. fDCOCLK = D × (N + 1) × (fFLLREFCLK ÷ n) fDCOCLKDIV = (N + 1) × (fFLLREFCLK ÷ n) 5.2.6.1 Adjusting DCO Frequency By default, FLL operation is enabled. FLL operation can be disabled by setting SCG0 or SCG1. When the FLL is disabled, the DCO continues to operate at the current settings defined in UCSCTL0 and UCSCTL1. The DCO frequency can be adjusted manually if desired. Otherwise, the DCO frequency is stabilized by the FLL operation. After a PUC, DCORSEL = {2} and DCO = {0}. MCLK and SMCLK are sourced from DCOCLKDIV. Because the CPU executes code from MCLK, which is sourced from the fast-starting DCO, code execution begins from PUC in less than 5 µs. The frequency of DCOCLK is set by the following functions: • The three DCORSEL bits select one of eight nominal frequency ranges for the DCO. These ranges are defined for an individual device in the device-specific data sheet. • The five DCO bits divide the DCO range selected by the DCORSEL bits into 32 frequency steps, separated by approximately 8%. • The five MOD bits switch between the frequency selected by the DCO bits and the next-higher frequency set by {DCO + 1}. When DCO = {31}, the MOD bits have no effect, because the DCO is already at the highest setting for the selected DCORSEL range. 5.2.7 Frequency Locked Loop (FLL) The FLL continuously counts up or down a frequency integrator. The output of the frequency integrator that drives the DCO can be read in UCSCTL0, UCSCTL1 (bits MOD and DCO). The count is adjusted +1 with the frequency fFLLREFCLK/n (n = 1, 2, 4, 8, 12, or 16) or –1 with the frequency fDCOCLK/[D × (N+1)]. NOTE: Reading MOD and DCO bits The integrator is updated by the DCOCLK, which may differ in frequency of operation of MCLK. It is possible that immediate reads of a previously written value are not visible to the user because the update to the integrator has not occurred. This is normal. When the integrator is updated at the next successive DCOCLK, the correct value can be read. In addition, because the MCLK can be asynchronous to the integrator updates, reading the values may be cause a corrupted value to be read under this condition. In this case, a majority vote method should be performed. Five of the integrator bits (UCSCTL0 bits 12 to 8) set the DCO frequency tap. Thirty-two taps are implemented for the DCO, and each is approximately 8% higher than the previous. The modulator mixes two adjacent DCO frequencies to produce fractional taps. For a given DCO bias range setting, time must be allowed for the DCO to settle on the proper tap for normal operation. (n × 32) fFLLREFCLK cycles are required between taps requiring a worst case of (n × 32 × 32) fFLLREFCLK cycles for the DCO to settle. The value n is defined by the FLLREFDIV bits (n = 1, 2, 4, 8, 12, or 16). SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 165 UCS Operation www.ti.com 5.2.8 DCO Modulator The modulator mixes two DCO frequencies, fDCO and fDCO+1 to produce an intermediate effective frequency between fDCO and fDCO+1 and spread the clock energy, reducing electromagnetic interference (EMI). The modulator mixes fDCO and fDCO+1 for 32 DCOCLK clock cycles and is configured with the MOD bits. When MOD = {0}, the modulator is off. The modulator mixing formula is: t = (32 – MOD) × tDCO + MOD × tDCO+1 Figure 5-2 shows the modulator operation. When FLL operation is enabled, the modulator settings and DCO are controlled by the FLL hardware. If FLL operation is not desired, the modulator settings and DCO control can be configured with software. MODx 31 24 16 15 5 4 3 2 Lower DCO Tap Frequency fDCO 1 0 Upper DCO Tap Frequency fDCO+1 Figure 5-2. Modulator Patterns 5.2.9 Disabling FLL Hardware and Modulator The FLL is disabled when the status register bits SCG0 or SCG1 are set. When the FLL is disabled, the DCO runs at the previously selected tap and DCOCLK is not automatically stabilized. The DCO modulator is disabled when DISMOD is set. When the DCO modulator is disabled, the DCOCLK is adjusted to the DCO tap selected by the DCO bits. NOTE: DCO operation without FLL When the FLL operation is disabled, the DCO continues to operate at the current settings. Because it is not stabilized by the FLL, temperature and voltage variations influence the frequency of operation. See the device-specific data sheet for voltage and temperature coefficients to ensure reliable operation. 166 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com UCS Operation 5.2.10 FLL Operation From Low-Power Modes An interrupt service request clears SCG1, CPUOFF, and OSCOFF if set, but does not clear SCG0. This means that for FLL operation from within an interrupt service routine entered from LPM1, 3, or 4, the FLL remains disabled and the DCO operates at the previous setting as defined in UCSCTL0 and UCSCTL1. SCG0 can be cleared by user software if FLL operation is required. 5.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules A peripheral module requests its clock sources automatically from the UCS module if required for its proper operation, regardless of the current mode of operation, as shown in Figure 5-3. A peripheral module asserts one of three possible clock request signals based on its control bits: ACLK_REQ, MCLK_REQ, or SMCLK_REQ. These request signals are based on the configuration and clock selection of the respective module. For example, if a timer selects ACLK as its clock source and the timer is enabled, the timer generates an ACLK_REQ signal to the UCS system. The UCS, in turn, enables ACLK regardless of the LPM settings. Any clock request from a peripheral module causes its respective clock off signal to be overridden, but does not change the setting of clock off control bit. For example, a peripheral module may require ACLK that is currently disabled by the OSCOFF bit (OSCOFF = 1). The module can request ACLK by generating an ACLK_REQ. This causes the OSCOFF bit to have no effect, thereby allowing ACLK to be available to the requesting peripheral module. The OSCOFF bit remains at its current setting (OSCOFF = 1). If the requested source is not active, the software NMI handler must take care of the required actions. For the previous example, if ACLK was sourced by XT1 and XT1 was not enabled, an oscillator fault condition occurs and the software must handle the event. The watchdog, due to its security requirement, actively selects the VLOCLK source if the originally selected clock source is not available. Due to the clock request feature, care must be taken in the application when entering low-power modes to save power. Although the device enters the selected low-power mode, a clock request may exhibit more current consumption than the specified values in the data sheet. SMCLK_REQ 0 MCLK_REQ 0 0 ACLK_REQ 0 UCS ACLK_REQ MCLK_REQ SMCLK_REQ Module n−2 ACLK_REQ MCLK_REQ SMCLK_REQ Module n−1 SMCLK MCLK ACLK WDTACLKON WDTSMCLKON Direct clock request in Watchdog mode Watch Dog Timer Module Figure 5-3. Module Request Clock System ACLK_REQ MCLK_REQ SMCLK_REQ Module n SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 167 UCS Operation www.ti.com By default, the clock request logic is enabled. The clock request logic can be disabled by clearing ACLKREQEN, MCLKREQEN, or SMCLKREQEN, for each respective system clock. When ACLKREQEN or MCLKREQEN bits are set, or active, the clock is available to the system and prevents entry into a lowpower mode until all modules requesting the clock are disabled. When ACLKREQEN or MCLKREQEN bits are cleared, or disabled, the clock is always halted as defined by the low-power modes. The SMCLKREQEN logic behaves similarly, but is also influenced by the SMCLKOFF bit in the UCSCTL6 register. Table 5-1 shows the relationship between the system clocks and the low-power modes in conjunction with the clock request logic. Table 5-1. Clock Request System and Power Modes ACLK Mode ACLKREQEN ACLKREQEN =0 =1 AM LPM0 LPM1 LPM2 LPM3 LPM4 LPM3.5 (1) Active Active Active Active Active Disabled Disabled Active Active Active Active Active Active Disabled MCLK MCLKREQEN MCLKREQEN =0 =1 Active Disabled Disabled Disabled Disabled Disabled Active Active Active Active Active Active SMCLK SMCLKOFF = 0 SMCLKOFF = 1 SMCLKREQEN SMCLKREQEN SMCLKREQEN SMCLKREQEN =0 =1 =0 =1 Active Active Disabled Active Active Active Disabled Active Active Active Disabled Active Disabled Active Disabled Active Disabled Active Disabled Active Disabled Active Disabled Active Disabled Disabled Disabled Disabled Disabled Disabled LPM4.5 (1) Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled (1) Any clock request prior to entry into LPM3.5 or LPM4.5 is ignored and LPM3.5 or LPM4.5 entry occurs. For the special case when XT1OFF = 0 or XT2OFF = 0, the LPMx.5 request is ignored and the device does not enter LPMx.5. 5.2.12 UCS Module Fail-Safe Operation The UCS module incorporates an oscillator-fault fail-safe feature. This feature detects an oscillator fault for XT1, DCO, and XT2 as shown in Figure 5-4. The available fault conditions are: • Low-frequency oscillator fault (XT1LFOFFG) for XT1 in LF mode • High-frequency oscillator fault (XT1HFOFFG) for XT1 in HF mode • High-frequency oscillator fault (XT2OFFG) for XT2 • DCO fault flag (DCOFFG) for the DCO The crystal oscillator fault bits XT1LFOFFG, XT1HFOFFG, and XT2OFFG are set if the corresponding crystal oscillator is turned on and not operating properly. After the fault bits are set, they remain set until reset in software, even if the fault condition no longer exists. If the user clears the fault bits and the fault condition still exists, the fault bits are automatically set, otherwise they remain cleared. When using XT1 operation in LF mode as the reference source into the FLL (SELREF = {0}), a crystal fault automatically causes the FLL reference source, FLLREFCLK, to be sourced by the REFO. XT1LFOFFG is set. When using XT1 operation in HF mode as the reference source into the FLL, a crystal fault causes no FLLREFCLK signal to be generated and the FLL continues to count down to zero in an attempt to lock FLLREFCLK and DCOCLK/[D × (N + 1)]. The DCO tap moves to the lowest position (DCO are cleared) and the DCOFFG is set. DCOFFG is also set if the N-multiplier value is set too high for the selected DCO frequency range, resulting in the DCO tap moving to the highest position (UCSCTL0.12 to UCSCTL0.8 are set). The DCOFFG remains set until cleared by the user. If the user clears the DCOFFG and the fault condition remains, it is automatically set, otherwise it remains cleared. XT1HFOFFG is set. When using XT2 as the reference source into the FLL, a crystal fault causes no FLLREFCLK signal to be generated, and the FLL continues to count down to zero in an attempt to lock FLLREFCLK and DCOCLK/[D × (N + 1)]. The DCO tap moves to the lowest position (DCO are cleared) and the DCOFFG is set. DCOFFG is also set if the N-multiplier value is set too high for the selected DCO frequency range, resulting in the DCO tap moving to the highest position (UCSCTL0.12 to UCSCTL0.8 are set). The DCOFFG remains set until cleared by the user. If the user clears the DCOFFG and the fault condition remains, it is automatically set, otherwise it remains cleared. XT2OFFG is set. 168 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com UCS Operation The OFIFG oscillator-fault interrupt flag is set and latched at POR or when any oscillator fault (XT1LFOFFG, XT1HFOFFG, XT2OFFG, DCOFFG , or CTSD16OFFG (if available)) is detected. When OFIFG is set and OFIE is set, the OFIFG requests an NMI. When the interrupt is granted, the OFIE is not reset automatically as it is in previous MSP430 families. It is no longer required to reset the OFIE. NMI entry and exit circuitry removes this requirement. The OFIFG flag must be cleared by software. The source of the fault can be identified by checking the individual fault bits. If a fault is detected for the oscillator sourcing MCLK, MCLK is automatically switched to the DCO for its clock source (DCOCLKDIV) for all clock sources except XT1 LF mode. If MCLK is sourced from XT1 in LF mode, an oscillator fault causes MCLK to be automatically switched to the REFO for its clock source (REFOCLK). This does not change the SELM bit settings. This condition must be handled by user software. If a fault is detected for the oscillator sourcing SMCLK, SMCLK is automatically switched to the DCO for its clock source (DCOCLKDIV) for all clock sources except XT1 LF mode. If SMCLK is sourced from XT1 in LF mode, an oscillator fault causes SMCLK to be automatically switched to the REFO for its clock source (REFOCLK). This does not change the SELS bit settings. This condition must be handled by user software. If a fault is detected for the oscillator sourcing ACLK, ACLK is automatically switched to the DCO for its clock source (DCOCLKDIV) for all clock sources except XT1 LF mode. If ACLK is sourced from XT1 in LF mode, an oscillator fault causes ACLK to be automatically switched to the REFO for its clock source (REFOCLK). This does not change the SELA bit settings. This condition must be handled by user software. NOTE: DCO active during oscillator fault DCOCLKDIV is active even at the lowest DCO tap. The clock signal is available for the CPU to execute code and service an NMI during an oscillator fault. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 169 UCS Operation DCO _ Fault POR XT 1 _ LF _ OscFault XT 1 _ HF _ OscFault XT 2 _ OscFault SQ R DCOFFG S Q DCO _ OF RR www.ti.com SQ XT 1 LFOFFG R S Q XT 1 _ LFOF RR SQ XT 1 HFOFFG R S Q XT 1 _ HFOF RR SQ R XT 2 OFFG S Q XT 2 _ OF CTSD16OFFG (from CTSD16 module) RR OscFault_Set S Q OFIFG NMIRS Q OscFault_Clr S OFIE Q PUC NMI _ IRQA RR Figure 5-4. Oscillator Fault Logic 170 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com UCS Operation NOTE: Fault conditions DCO_Fault: DCOFFG is set if DCO bits in UCSCTL0 register value equals {0} or {31}. CTSD16CLK_Fault: This signal is set after a fault has been detected in the CTSD16CLK. When set, the fault bits remain set until reset in software, even if the fault condition no longer exists. The fault condition causes CTSD16OFFG in the CTSD16CTL register to be set and remain set. If software clears CTSD16OFFG and the fault condition still exists, CTSD16OFFG remains set. XT1_LF_OscFault: This signal is set after the XT1 (LF mode) oscillator has stopped operation and cleared after operation resumes. The fault condition causes XT1LFOFFG to be set and remain set. If software clears XT1LFOFFG and the fault condition still exists, XT1LFOFFG remains set. XT1_HF_OscFault: This signal is set after the XT1 (HF mode) oscillator has stopped operation and cleared after operation resumes. The fault condition causes XT1HFOFFG to be set and remain set. If software clears XT1HFOFFG and the fault condition still exists, XT1HFOFFG remains set. XT2_OscFault: This signal is set after the XT2 oscillator has stopped operation and cleared after operation resumes. The fault condition causes XT2OFFG to be set and remain set. If software clears XT2OFFG and the fault condition still exists, XT2OFFG remains set. NOTE: Fault logic As long as a fault condition still exists, the OFIFG remains set. The application must take special care when clearing the OFIFG signal. If no fault condition remains when the OFIFG signal is cleared, the clock logic switches back to the original user settings prior to the fault condition. NOTE: Fault logic counters Each crystal oscillator circuit has hardware counters. These counters are reset each time a fault condition occurs on its respective oscillator, causing the fault flag to be set. The counters begin to count after the fault condition is removed. When the maximum count is reached, the fault flag is removed. In XT1 LF mode, the maximum count is 8192. In XT1 HF mode (and XT2 when available), the maximum count is 1024. In bypass modes, regardless of LF or HF settings, the maximum count is 8192. 5.2.13 Synchronization of Clock Signals When switching MCLK or SMCLK from one clock source to the another, the switch is synchronized to avoid critical race conditions as shown in Figure 5-5: • The current clock cycle continues until the next rising edge. • The clock remains high until the next rising edge of the new clock. • The new clock source is selected and continues with a full high period. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 171 Module Oscillator (MODOSC) Select ACLK DCOCLK www.ti.com ACLK MCLK DCOCLK Wait for ACLK ACLK Figure 5-5. Switch MCLK from DCOCLK to XT1CLK 5.3 Module Oscillator (MODOSC) The UCS module also supports an internal oscillator, MODOSC, that is used by the flash memory controller module and optionally by other modules in the system. The MODOSC sources MODCLK. 5.3.1 MODOSC Operation To conserve power, MODOSC is powered down when not needed and is enabled only when required. When the MODOSC source is required, the respective module requests it. MODOSC is enabled based on unconditional and conditional requests. Setting MODOSCREQEN enables conditional requests. Unconditional requests are always enabled. It is not necessary to set MODOSCREQEN for modules that use unconditional requests; for example, the flash controller or ADC12_A. The flash memory controller only requires MODCLK when performing write or erase operations. When performing such operations, the flash memory controller issues an unconditional request for the MODOSC source. Upon doing so, the MODOSC source is enabled, if it is not already enabled by previous requests from other modules. The ADC12_A may optionally use MODOSC as a clock source for its conversion clock. The user chooses the ADC12OSC as the conversion clock source. During a conversion, the ADC12_A module issues an unconditional request for the ADC12OSC clock source. Upon doing so, the MODOSC source is enabled, if it is not already enabled by previous requests from other modules. 172 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com UCS Registers 5.4 UCS Registers The UCS module registers are listed in Table 5-2. The base address can be found in the device-specific data sheet. The address offset is listed in Table 5-2. NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15). Table 5-2. UCS Registers Offset Acronym Register Name Type 00h UCSCTL0 Unified Clock System Control 0 Read/write 00h UCSCTL0_L Read/write 01h UCSCTL0_H Read/write 02h UCSCTL1 Unified Clock System Control 1 Read/write 02h UCSCTL1_L Read/write 03h UCSCTL1_H Read/write 04h UCSCTL2 Unified Clock System Control 2 Read/write 04h UCSCTL2_L Read/write 05h UCSCTL2_H Read/write 06h UCSCTL3 Unified Clock System Control 3 Read/write 06h UCSCTL3_L Read/write 07h UCSCTL3_H Read/write 08h UCSCTL4 Unified Clock System Control 4 Read/write 08h UCSCTL4_L Read/write 09h UCSCTL4_H Read/write 0Ah UCSCTL5 Unified Clock System Control 5 Read/write 0Ah UCSCTL5_L Read/write 0Bh UCSCTL5_H Read/write 0Ch UCSCTL6 Unified Clock System Control 6 Read/write 0Ch UCSCTL6_L Read/write 0Dh UCSCTL6_H Read/write 0Eh UCSCTL7 Unified Clock System Control 7 Read/write 0Eh UCSCTL7_L Read/write 0Fh UCSCTL7_H Read/write 10h UCSCTL8 Unified Clock System Control 8 Read/write 10h UCSCTL8_L Read/write 11h UCSCTL8_H Read/write 12h UCSCTL9 Unified Clock System Control 9(1) Read/write 12h UCSCTL9_L Read/write 13h UCSCTL9_H Read/write (1) This register is not available on all devices. See the device-specific data sheet. Access Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Reset 0000h 00h 00h 0020h 20h 00h 101Fh 1Fh 10h 0000h 00h 00h 0044h 44h 00h 0000h 00h 00h C1CDh CDh C1h 0703h 03h 07h 0707h 07h 07h 0000h 00h 00h Section Section 5.4.1 Section 5.4.2 Section 5.4.3 Section 5.4.4 Section 5.4.5 Section 5.4.6 Section 5.4.7 Section 5.4.8 Section 5.4.9 Section 5.4.10 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 173 UCS Registers 5.4.1 UCSCTL0 Register Unified Clock System Control 0 Register Figure 5-6. UCSCTL0 Register 15 14 13 12 11 10 Reserved DCO r0 r0 r0 rw-0 rw-0 rw-0 7 6 5 4 3 2 MOD rw-0 rw-0 rw-0 rw-0 rw-0 r0 www.ti.com 9 8 rw-0 rw-0 1 0 Reserved r0 r0 Bit 15-13 12-8 7-3 Field Reserved DCO MOD 2-0 Reserved Type R RW RW R Table 5-3. UCSCTL0 Register Description Reset 0h 0h 0h 0h Description Reserved. Always reads as 0. DCO tap selection. These bits select the DCO tap and are modified automatically during FLL operation. Modulation bit counter. These bits select the modulation pattern. All MOD bits are modified automatically during FLL operation. The DCO register value is incremented when the modulation bit counter rolls over from 31 to 0. If the modulation bit counter decrements from 0 to the maximum count, the DCO register value is also decremented. Reserved. Always reads as 0. 174 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5.4.2 UCSCTL1 Register Unified Clock System Control 1 Register 15 r0 7 Reserved r0 Figure 5-7. UCSCTL1 Register 14 13 12 11 10 Reserved r0 r0 r0 r0 r0 6 5 4 DCORSEL rw-0 rw-1 rw-0 3 2 Reserved r0 r0 UCS Registers 9 r0 1 Reserved rw-0 8 r0 0 DISMOD rw-0 Bit 15-7 6-4 3-2 1 0 Field Reserved DCORSEL Reserved Reserved DISMOD Type R RW R RW RW Table 5-4. UCSCTL1 Register Description Reset 0h 2h 0h 0h 0h Description Reserved. Always reads as 0. DCO frequency range select. These bits select the DCO frequency range of operation defined in the device-specific datasheet. Reserved. Always reads as 0. Reserved. Always reads as 0. Modulation. This bit enables or disables the modulation. 0b = Modulation enabled 1b = Modulation disabled SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 175 UCS Registers 5.4.3 UCSCTL2 Register Unified Clock System Control 2 Register 15 14 Reserved r0 rw-0 7 6 rw-0 rw-0 13 FLLD rw-0 5 rw-0 Figure 5-8. UCSCTL2 Register 12 11 10 Reserved rw-1 r0 r0 4 3 2 FLLN rw-1 rw-1 rw-1 www.ti.com 9 8 FLLN rw-0 rw-0 1 0 rw-1 rw-1 Bit 15 14-12 Field Reserved FLLD 11-10 9-0 Reserved FLLN Type R RW R RW Table 5-5. UCSCTL2 Register Description Reset 0h 1h 0h 1Fh Description Reserved. Always reads as 0. FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits. 000b = fDCOCLK/1 001b = fDCOCLK/2 010b = fDCOCLK/4 011b = fDCOCLK/8 100b = fDCOCLK/16 101b = fDCOCLK/32 110b = Reserved for future use. Defaults to fDCOCLK/32. 111b = Reserved for future use. Defaults to fDCOCLK/32. Reserved. Always reads as 0. Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1. 176 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5.4.4 UCSCTL3 Register Unified Clock System Control 3 Register Figure 5-9. UCSCTL3 Register 15 14 13 12 11 10 Reserved r0 r0 r0 r0 r0 r0 7 6 Reserved r0 rw-0 5 SELREF rw-0 4 3 2 Reserved rw-0 r0 rw-0 UCS Registers 9 8 r0 r0 1 0 FLLREFDIV rw-0 rw-0 Bit 15-7 6-4 Field Reserved SELREF 3 Reserved 2-0 FLLREFDIV Type R RW R RW Table 5-6. UCSCTL3 Register Description Reset 0h 0h 0h 0h Description Reserved. Always reads as 0. FLL reference select. These bits select the FLL reference clock source. 000b = XT1CLK 001b = Reserved for future use. Defaults to XT1CLK. 010b = REFOCLK 011b = Reserved for future use. Defaults to REFOCLK. 100b = Reserved for future use. Defaults to REFOCLK. 101b = XT2CLK when available, otherwise REFOCLK. 110b = Reserved for future use. XT2CLK when available, otherwise REFOCLK. 111b = Reserved for future use. XT2CLK when available, otherwise REFOCLK. Reserved. Always reads as 0. FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the FLL reference frequency. 000b = fFLLREFCLK/1 001b = fFLLREFCLK/2 010b = fFLLREFCLK/4 011b = fFLLREFCLK/8 100b = fFLLREFCLK/12 101b = fFLLREFCLK/16 110b = Reserved for future use. Defaults to fFLLREFCLK/16. 111b = Reserved for future use. Defaults to fFLLREFCLK/16. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 177 UCS Registers 5.4.5 UCSCTL4 Register Unified Clock System Control 4 Register Figure 5-10. UCSCTL4 Register 15 14 13 12 11 10 Reserved r0 r0 r0 r0 r0 rw-0 7 6 Reserved r0 rw-1 5 SELS rw-0 4 3 2 Reserved rw-0 r0 rw-1 www.ti.com 9 8 SELA rw-0 rw-0 1 0 SELM rw-0 rw-0 Bit 15-11 10-8 Field Reserved SELA 7 Reserved 6-4 SELS 3 Reserved 2-0 SELM Type R RW R RW R RW Table 5-7. UCSCTL4 Register Description Reset 0h 0h 0h 4h 0h 4h Description Reserved. Always reads as 0. Selects the ACLK source 000b = XT1CLK 001b = VLOCLK 010b = REFOCLK 011b = DCOCLK 100b = DCOCLKDIV 101b = XT2CLK when available, otherwise DCOCLKDIV 110b = Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111b = Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. Reserved. Always reads as 0. Selects the SMCLK source 000b = XT1CLK 001b = VLOCLK 010b = REFOCLK 011b = DCOCLK 100b = DCOCLKDIV 101b = XT2CLK when available, otherwise DCOCLKDIV 110b = Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111b = Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. Reserved. Always reads as 0. Selects the MCLK source 000b = XT1CLK 001b = VLOCLK 010b = REFOCLK 011b = DCOCLK 100b = DCOCLKDIV 101b = XT2CLK when available, otherwise DCOCLKDIV 110b = Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 111b = Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. 178 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5.4.6 UCSCTL5 Register Unified Clock System Control 5 Register 15 14 Reserved r0 rw-0 7 6 Reserved r0 rw-0 13 DIVPA rw-0 5 DIVS rw-0 Figure 5-11. UCSCTL5 Register 12 11 10 Reserved rw-0 r0 rw-0 4 3 2 Reserved rw-0 r0 rw-0 UCS Registers 9 8 DIVA rw-0 rw-0 1 0 DIVM rw-0 rw-0 Bit 15 14-12 Field Reserved DIVPA 11 10-8 Reserved DIVA 7 Reserved 6-4 DIVS 3 Reserved Type R RW R RW R RW R Table 5-8. UCSCTL5 Register Description Reset 0h 0h 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. ACLK source divider available at external pin. Divides the frequency of ACLK and presents it to an external pin. 000b = fACLK/1 001b = fACLK/2 010b = fACLK/4 011b = fACLK/8 100b = fACLK/16 101b = fACLK/32 110b = Reserved for future use. Defaults to fACLK/32. 111b = Reserved for future use. Defaults to fACLK/32. Reserved. Always reads as 0. ACLK source divider. Divides the frequency of the ACLK clock source. 000b = fACLK/1 001b = fACLK/2 010b = fACLK/4 011b = fACLK/8 100b = fACLK/16 101b = fACLK/32 110b = Reserved for future use. Defaults to fACLK/32. 111b = Reserved for future use. Defaults to fACLK/32. Reserved. Always reads as 0. SMCLK source divider 000b = fSMCLK/1 001b = fSMCLK/2 010b = fSMCLK/4 011b = fSMCLK/8 100b = fSMCLK/16 101b = fSMCLK/32 110b = Reserved for future use. Defaults to fSMCLK/32. 111b = Reserved for future use. Defaults to fSMCLK/32. Reserved. Always reads as 0. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 179 UCS Registers Bit Field 2-0 DIVM Table 5-8. UCSCTL5 Register Description (continued) Type RW Reset 0h Description MCLK source divider 000b = fMCLK/1 001b = fMCLK/2 010b = fMCLK/4 011b = fMCLK/8 100b = fMCLK/16 101b = fMCLK/32 110b = Reserved for future use. Defaults to fMCLK/32. 111b = Reserved for future use. Defaults to fMCLK/32. www.ti.com 180 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5.4.7 UCSCTL6 Register Unified Clock System Control 6 Register 15 14 XT2DRIVE rw-1 rw-1 7 6 XT1DRIVE rw-1 rw-1 13 Reserved r0 5 XTS rw-0 Figure 5-12. UCSCTL6 Register 12 11 10 XT2BYPASS Reserved rw-0 r0 r0 4 XT1BYPASS rw-0 3 2 XCAP rw-1 rw-1 UCS Registers 9 r0 1 SMCLKOFF rw-0 8 XT2OFF rw-1 0 XT1OFF rw-1 Bit 15-14 Field XT2DRIVE 13 Reserved 12 XT2BYPASS 11-9 8 Reserved XT2OFF 7-6 XT1DRIVE 5 XTS 4 XT1BYPASS Type RW R RW R RW RW RW RW Table 5-9. UCSCTL6 Register Description Reset 3h 0h 0h 0h 1h 3h 0h 0h Description The XT2 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. 00b = Lowest current consumption. XT2 oscillator operating range is 4 MHz to 8 MHz. 01b = Increased drive strength XT2 oscillator. XT2 oscillator operating range is 8 MHz to 16 MHz. 10b = Increased drive capability XT2 oscillator. XT2 oscillator operating range is 16 MHz to 24 MHz. 11b = Maximum drive capability and maximum current consumption for both XT2 oscillator. XT2 oscillator operating range is 24 MHz to 32 MHz. Reserved. Always reads as 0. XT2 bypass select 0b = XT2 sourced from external crystal 1b = XT2 sourced from external clock signal Reserved. Always reads as 0. Turns off the XT2 oscillator 0b = XT2 is on if XT2 is selected by the port selection and XT2 is not in bypass mode of operation 1b = XT2 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source required for FLL operation The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. 00b = Lowest current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 4 MHz to 8 MHz. 01b = Increased drive strength for XT1 LF mode. XT1 oscillator operating range in HF mode is 8 MHz to 16 MHz. 10b = Increased drive capability for XT1 LF mode. XT1 oscillator operating range in HF mode is 16 MHz to 24 MHz. 11b = Maximum drive capability and maximum current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 24 MHz to 32 MHz. XT1 mode select 0b = Low-frequency mode. XCAP bits define the capacitance at the XIN and XOUT pins. 1b = High-frequency mode. XCAP bits are not used. XT1 bypass select 0b = XT1 sourced from external crystal 1b = XT1 sourced from external clock signal SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 181 UCS Registers Bit Field 3-2 XCAP 1 SMCLKOFF 0 XT1OFF www.ti.com Table 5-9. UCSCTL6 Register Description (continued) Type RW RW RW Reset 3h 0h 1h Description Oscillator capacitor selection. These bits select the capacitors applied to the LF crystal or resonator in the LF mode (XTS = 0). The effective capacitance (seen by the crystal) is C(eff) ≈ (C(XIN) + 2 pF) / 2. It is assumed that C(XIN) = C(XOUT) and that a parasitic capacitance of 2 pF is added by the package and the printed circuit board. For details about the typical internal and the effective capacitors, see the device-specific data sheet. SMCLK off. This bit turns off the SMCLK. 0b = SMCLK on 1b = SMCLK off XT1 off. This bit turns off the XT1. 0b = XT1 is on if XT1 is selected by the port selection and XT1 is not in bypass mode of operation. 1b = XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source required for FLL operation. 182 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5.4.8 UCSCTL7 Register Unified Clock System Control 7 Register UCS Registers 15 14 Reserved r0 r0 Figure 5-13. UCSCTL7 Register 13 12 11 10 Reserved Reserved rw-0 rw-(0) rw-(1) rw-(1) 7 6 5 4 3 2 Reserved Reserved XT2OFFG(1) XT1HFOFFG(1) r0 r0 r0 rw-(0) rw-(0) rw-(0) (1) Not available on all devices. When not available, this bit is reserved. 9 8 Reserved r-1 r-1 1 XT1LFOFFG rw-(1) 0 DCOFFG rw-(1) Table 5-10. UCSCTL7 Register Description Bit Field Type Reset Description 15-14 Reserved R 0h Reserved. Always reads as 0. 13-12 Reserved RW 0h Reserved. Must always be written with 0. 11-10 Reserved RW 3h Reserved. The states of these bits should be ignored. 9-8 Reserved R 3h Reserved. The states of these bits should be ignored. 7-5 Reserved R 0h Reserved. Always reads as 0. 4 Reserved RW 0h Reserved. The state of this bit should be ignored. 3 XT2OFFG (1) RW 0h XT2 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT2OFFG is set if a XT2 fault condition exists. XT2OFFG can be cleared by software. If the XT2 fault condition still remains, XT2OFFG is set. 0b = No fault condition occurred after the last reset. 1b = XT2 fault. An XT2 fault occurred after the last reset. 2 XT1HFOFFG (1) RW 0h XT1 oscillator fault flag (HF mode). If this bit is set, the OFIFG flag is also set. XT1HFOFFG is set if a XT1 fault condition exists. XT1HFOFFG can be cleared by software. If the XT1 fault condition still remains, XT1HFOFFG is set. 0b = No fault condition occurred after the last reset. 1b = XT1 fault. An XT1 fault occurred after the last reset. 1 XT1LFOFFG RW 1h XT1 oscillator fault flag (LF mode). If this bit is set, the OFIFG flag is also set. XT1LFOFFG is set if a XT1 fault condition exists. XT1LFOFFG can be cleared by software. If the XT1 fault condition still remains, XT1LFOFFG is set. 0b = No fault condition occurred after the last reset. 1b = XT1 fault (LF mode). A XT1 fault occurred after the last reset. 0 DCOFFG RW 1h DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is set if DCO = {0} or DCO = {31}. DCOFFG can be cleared by software. If the DCO fault condition still remains, DCOFFG is set. 0b = No fault condition occurred after the last reset. 1b = DCO fault. A DCO fault occurred after the last reset. (1) Not available on all devices. When not available, this bit is reserved. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 183 UCS Registers 5.4.9 UCSCTL8 Register Unified Clock System Control 8 Register www.ti.com Figure 5-14. UCSCTL8 Register 15 14 13 12 11 10 9 8 Reserved Reserved r0 r0 r0 r0 r0 rw-(1) rw-(1) rw-(1) 7 6 5 4 3 2 1 0 Reserved Reserved MODOSCREQ SMCLKREQEN MCLKREQEN ACLKREQEN EN r0 r0 r0 rw-(0) rw-(0) rw-(1) rw-(1) rw-(1) Bit 15-11 10-8 7-5 4 3 2 1 0 Field Reserved Reserved Reserved Reserved MODOSCREQEN SMCLKREQEN MCLKREQEN ACLKREQEN Type R R R R RW RW RW RW Table 5-11. UCSCTL8 Register Description Reset 0h 0h 0h 0h 0h 1h 1h 1h Description Reserved. Always reads as 0. Reserved. Must always be written as 1. Reserved. Always reads as 0. Reserved. Must always be written as 0. MODOSC clock request enable. Setting this enables conditional module requests for MODOSC. 0b = MODOSC conditional requests are disabled. 1b = MODOSC conditional requests are enabled. SMCLK clock request enable. Setting this enables conditional module requests for SMCLK 0b = SMCLK conditional requests are disabled. 1b = SMCLK conditional requests are enabled. MCLK clock request enable. Setting this enables conditional module requests for MCLK 0b = MCLK conditional requests are disabled. 1b = MCLK conditional requests are enabled. ACLK clock request enable. Setting this enables conditional module requests for ACLK 0b = ACLK conditional requests are disabled. 1b = ACLK conditional requests are enabled. 184 Unified Clock System (UCS) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 5.4.10 UCSCTL9 Register Unified Clock System Control 9 Register This register is not available on all devices. See the device-specific data sheet. UCS Registers Figure 5-15. UCSCTL9 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved XT2BYPASSLV XT1BYPASSLV r0 r0 r0 r0 r0 r0 rw-0 rw-0 Bit 15-2 1 Field Reserved XT2BYPASSLV 0 XT1BYPASSLV Type R RW RW Table 5-12. UCSCTL9 Register Description Reset 0h 0h 0h Description Reserved. Always reads as 0. Selects XT2 bypass input swing level. Must be set for reduced swing operation. 0b = Input range from 0 to DVCC 1b = Input range from 0 to DVIO Selects XT1 bypass input swing level. Must be set for reduced swing operation. 0b = Input range from 0 to DVCC 1b = Input range from 0 to DVIO SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Unified Clock System (UCS) 185 Chapter 6 SLAU208O – June 2008 – Revised May 2015 CPUX This chapter describes the extended MSP430X 16-bit RISC CPU (CPUX) with 1MB memory access, its addressing modes, and instruction set. NOTE: The MSP430X CPUX implemented on this device family, formally called CPUXV2, has in some cases, slightly different cycle counts from the MSP430X CPUX implemented on the 2xx and 4xx families. Topic ........................................................................................................................... Page 6.1 MSP430X CPU (CPUX) Introduction .................................................................... 187 6.2 Interrupts......................................................................................................... 189 6.3 CPU Registers.................................................................................................. 190 6.4 Addressing Modes............................................................................................ 196 6.5 MSP430 and MSP430X Instructions .................................................................... 213 6.6 Instruction Set Description ................................................................................ 229 186 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430X CPU (CPUX) Introduction 6.1 MSP430X CPU (CPUX) Introduction The MSP430X CPU incorporates features specifically designed for modern programming techniques, such as calculated branching, table processing, and the use of high-level languages such as C. The MSP430X CPU can address a 1MB address range without paging. The MSP430X CPU is completely backward compatible with the MSP430 CPU. The MSP430X CPU features include: • RISC architecture • Orthogonal architecture • Full register access including program counter (PC), status register (SR), and stack pointer (SP) • Single-cycle register operations • Large register file reduces fetches to memory. • 20-bit address bus allows direct access and branching throughout the entire memory range without paging. • 16-bit data bus allows direct manipulation of word-wide arguments. • Constant generator provides the six most often used immediate values and reduces code size. • Direct memory-to-memory transfers without intermediate register holding • Byte, word, and 20-bit address-word addressing The block diagram of the MSP430X CPU is shown in Figure 6-1. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 187 MSP430X CPU (CPUX) Introduction MDB − Memory Data Bus Memory Address Bus − MAB 19 16 15 0 R0/PC Program Counter 0 R1/SP Pointer Stack 0 R2/SR Status Register R3/CG2 Constant Generator R4 General Purpose R5 General Purpose R6 General Purpose R7 General Purpose R8 General Purpose R9 General Purpose R10 General Purpose R11 General Purpose R12 General Purpose R13 General Purpose R14 General Purpose R15 General Purpose 16 Zero, Z Carry, C Overflow,V dst src 16/20-bit ALU Negative,N 20 MCLK Figure 6-1. MSP430X CPU Block Diagram www.ti.com 188 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Interrupts 6.2 Interrupts The MSP430X has the following interrupt structure: • Vectored interrupts with no polling necessary • Interrupt vectors are located downward from address 0FFFEh. The interrupt vectors contain 16-bit addresses that point into the lower 64KB memory. This means all interrupt handlers must start in the lower 64KB memory. During an interrupt, the program counter (PC) and the status register (SR) are pushed onto the stack as shown in Figure 6-2. The MSP430X architecture stores the complete 20-bit PC value efficiently by appending the PC bits 19:16 to the stored SR value automatically on the stack. When the RETI instruction is executed, the full 20-bit PC is restored making return from interrupt to any address in the memory range possible. SP old SP Item n-1 PC.15:0 PC.19:16 SR.11:0 Figure 6-2. PC Storage on the Stack for Interrupts SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 189 CPU Registers www.ti.com 6.3 CPU Registers The CPU incorporates 16 registers (R0 through R15). Registers R0, R1, R2, and R3 have dedicated functions. Registers R4 through R15 are working registers for general use. 6.3.1 Program Counter (PC) The 20-bit Program Counter (PC, also called R0) points to the next instruction to be executed. Each instruction uses an even number of bytes (2, 4, 6, or 8 bytes), and the PC is incremented accordingly. Instruction accesses are performed on word boundaries, and the PC is aligned to even addresses. Figure 6-3 shows the PC. 19 16 15 10 Program Counter Bits 19 to 1 0 Figure 6-3. Program Counter The PC can be addressed with all instructions and addressing modes. A few examples: MOV.W #LABEL,PC ; Branch to address LABEL (lower 64KB) MOVA #LABEL,PC ; Branch to address LABEL (1MB memory) MOV.W LABEL,PC ; Branch to address in word LABEL ; (lower 64KB) MOV.W @R14,PC ; Branch indirect to address in ; R14 (lower 64KB) ADDA #4,PC ; Skip two words (1MB memory) The BR and CALL instructions reset the upper four PC bits to 0. Only addresses in the lower 64KB address range can be reached with the BR or CALL instruction. When branching or calling, addresses beyond the lower 64KB range can only be reached using the BRA or CALLA instructions. Also, any instruction to directly modify the PC does so according to the used addressing mode. For example, MOV.W #value,PC clears the upper four bits of the PC, because it is a .W instruction. The PC is automatically stored on the stack with CALL (or CALLA) instructions and during an interrupt service routine. Figure 6-4 shows the storage of the PC with the return address after a CALLA instruction. A CALL instruction stores only bits 15:0 of the PC. SP old SP Item n PC.19:16 PC.15:0 Figure 6-4. PC Storage on the Stack for CALLA The RETA instruction restores bits 19:0 of the PC and adds 4 to the stack pointer (SP). The RET instruction restores bits 15:0 to the PC and adds 2 to the SP. 6.3.2 Stack Pointer (SP) The 20-bit Stack Pointer (SP, also called R1) is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. In addition, the SP can be used by software with all instructions and addressing modes. Figure 6-5 shows the SP. The SP is initialized into RAM by the user, and is always aligned to even addresses. 190 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com CPU Registers Figure 6-6 shows the stack usage. Figure 6-7 shows the stack usage when 20-bit address words are pushed. 19 10 Stack Pointer Bits 19 to 1 0 MOV.W MOV.W PUSH POP 2(SP),R6 R7,0(SP) #0123h R8 ; Copy Item I2 to R6 ; Overwrite TOS with R7 ; Put 0123h on stack ; R8 = 0123h Figure 6-5. Stack Pointer Address PUSH #0123h POP R8 0xxxh I1 I1 I1 0xxxh - 2 I2 0xxxh - 4 I3 I2 SP I3 I2 I3 SP 0xxxh - 6 0123h SP 0xxxh - 8 Figure 6-6. Stack Usage SP old SP Item n-1 Item.19:16 Item.15:0 Figure 6-7. PUSHX.A Format on the Stack The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 6-8. PUSH SP POP SP SPold SP1 SPold SP2 SP1 The stack pointer is changed after a PUSH SP instruction. The stack pointer is not changed after a POP SP instruction. The POP SP instruction places SP1 into the stack pointer SP (SP2 = SP1) Figure 6-8. PUSH SP, POP SP Sequence SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 191 CPU Registers www.ti.com 6.3.3 Status Register (SR) The 16-bit Status Register (SR, also called R2), used as a source or destination register, can only be used in register mode addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator. Figure 6-9 shows the SR bits. Do not write 20-bit values to the SR. Unpredictable operation can result. 15 Reserved 98 7 0 OSC CPU V SCG1 SCG0 OFF OFF GIE N Z C rw-0 Figure 6-9. SR Bits Table 6-1 describes the SR bits. Table 6-1. SR Bit Description Bit Reserved V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C Description Reserved Overflow. This bit is set when the result of an arithmetic operation overflows the signed-variable range. ADD(.B), ADDX(.B,.A), ADDC(.B), ADDCX(.B.A), ADDA Set when: positive + positive = negative negative + negative = positive otherwise reset SUB(.B), SUBX(.B,.A), SUBC(.B),SUBCX(.B,.A), SUBA, CMP(.B), CMPX(.B,.A), CMPA Set when: positive – negative = negative negative – positive = positive otherwise reset System clock generator 1. This bit may be used to enable or disable functions in the clock system depending on the device family; for example, DCO bias enable or disable. System clock generator 0. This bit may be used to enable or disable functions in the clock system depending on the device family; for example, FLL enable or disable. Oscillator off. When this bit is set, it turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or SMCLK. CPU off. When this bit is set, it turns off the CPU. General interrupt enable. When this bit is set, it enables maskable interrupts. When it is reset, all maskable interrupts are disabled. Negative. This bit is set when the result of an operation is negative and cleared when the result is positive. Zero. This bit is set when the result of an operation is 0 and cleared when the result is not 0. Carry. This bit is set when the result of an operation produced a carry and cleared when no carry occurred. NOTE: Bit manipulations of the SR should be done by the following instructions: MOV, BIS, and BIC. 192 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com CPU Registers 6.3.4 Constant Generator Registers (CG1 and CG2) Six commonly-used constants are generated with the constant generator registers R2 (CG1) and R3 (CG2), without requiring an additional 16-bit word of program code. The constants are selected with the source register addressing modes (As), as described in Table 6-2. Table 6-2. Values of Constant Generators CG1, CG2 Register As R2 00 R2 01 R2 10 R2 11 R3 00 R3 01 R3 10 R3 11 Constant – (0) 00004h 00008h 00000h 00001h 00002h FFh, FFFFh, FFFFFh Remarks Register mode Absolute address mode +4, bit processing +8, bit processing 0, word processing +1 +2, bit processing –1, word processing The constant generator advantages are: • No special instructions required • No additional code word for the six constants • No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act as source-only registers. 6.3.4.1 Constant Generator – Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions. However, the constant generator allows the MSP430 assembler to support 24 additional emulated instructions. For example, the single-operand instruction: CLR dst is emulated by the double-operand instruction with the same length: MOV R3,dst where the #0 is replaced by the assembler, and R3 is used with As = 00. INC dst is replaced by: ADD #1,dst SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 193 CPU Registers www.ti.com 6.3.5 General-Purpose Registers (R4 to R15) The 12 CPU registers (R4 to R15) contain 8-bit, 16-bit, or 20-bit values. Any byte-write to a CPU register clears bits 19:8. Any word-write to a register clears bits 19:16. The only exception is the SXT instruction. The SXT instruction extends the sign through the complete 20-bit register. Figure 6-10 through Figure 6-14 show the handling of byte, word, and address-word data. Note the reset of the leading most significant bits (MSBs) if a register is the destination of a byte or word instruction. Figure 6-10 shows byte handling (8-bit data, .B suffix). The handling is shown for a source register and a destination memory byte and for a source memory byte and a destination register. Register-Byte Operation High Byte Low Byte 19 16 15 87 0 Unused Unused Register Byte-Register Operation High Byte Low Byte Memory Memory 19 16 15 87 Un- Unused used 0 Register Operation Operation Memory 0 0 Register Figure 6-10. Register-Byte and Byte-Register Operation Figure 6-11 and Figure 6-12 show 16-bit word handling (.W suffix). The handling is shown for a source register and a destination memory word and for a source memory word and a destination register. Register-Word Operation High Byte Low Byte 19 16 15 87 0 Unused Register Memory Operation Memory Figure 6-11. Register-Word Operation 194 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Word-Register Operation High Byte Low Byte Memory 19 16 15 87 Un- used 0 Register Operation CPU Registers 0 Register Figure 6-12. Word-Register Operation Figure 6-13 and Figure 6-14 show 20-bit address-word handling (.A suffix). The handling is shown for a source register and a destination memory address-word and for a source memory address-word and a destination register. Register - Ad dress-Word Operation High Byte Low Byte 19 16 15 87 0 Register Memory +2 Unused Memory Operation Memory +2 0 Memory Figure 6-13. Register – Address-Word Operation SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 195 Addressing Modes Memory +2 Address-Word - Register Operation High Byte Low Byte 19 16 15 87 0 Unused Memory www.ti.com Register Operation Register Figure 6-14. Address-Word – Register Operation 6.4 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand use 16-bit or 20-bit addresses (see Table 6-3). The MSP430 and MSP430X instructions are usable throughout the entire 1MB memory range. As, Ad Addressing Mode 00, 0 Register 01, 1 Indexed 01, 1 Symbolic 01, 1 Absolute 10, – 11, – 11, – Indirect Register Indirect Autoincrement Immediate Table 6-3. Source and Destination Addressing Syntax Rn X(Rn) ADDR &ADDR @Rn @Rn+ #N Description Register contents are operand. (Rn + X) points to the operand. X is stored in the next word, or stored in combination of the preceding extension word and the next word. (PC + X) points to the operand. X is stored in the next word, or stored in combination of the preceding extension word and the next word. Indexed mode X(PC) is used. The word following the instruction contains the absolute address. X is stored in the next word, or stored in combination of the preceding extension word and the next word. Indexed mode X(SR) is used. Rn is used as a pointer to the operand. Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for .B instructions, by 2 for .W instructions, and by 4 for .A instructions. N is stored in the next word, or stored in combination of the preceding extension word and the next word. Indirect autoincrement mode @PC+ is used. The seven addressing modes are explained in detail in the following sections. Most of the examples show the same addressing mode for the source and destination, but any valid combination of source and destination addressing modes is possible in an instruction. NOTE: Use of Labels EDE, TONI, TOM, and LEO Throughout MSP430 documentation, EDE, TONI, TOM, and LEO are used as generic labels. They are only labels and have no special meaning. 196 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.4.1 Register Mode Addressing Modes Operation: Length: Comment: Byte operation: Word operation: Address-word operation: SXT exception: Example: The operand is the 8-, 16-, or 20-bit content of the used CPU register. One, two, or three words Valid for source and destination Byte operation reads only the eight least significant bits (LSBs) of the source register Rsrc and writes the result to the eight LSBs of the destination register Rdst. The bits Rdst.19:8 are cleared. The register Rsrc is not modified. Word operation reads the 16 LSBs of the source register Rsrc and writes the result to the 16 LSBs of the destination register Rdst. The bits Rdst.19:16 are cleared. The register Rsrc is not modified. Address-word operation reads the 20 bits of the source register Rsrc and writes the result to the 20 bits of the destination register Rdst. The register Rsrc is not modified The SXT instruction is the only exception for register operation. The sign of the low byte in bit 7 is extended to the bits Rdst.19:8. BIS.W R5,R6 ; This instruction logically ORs the 16-bit data contained in R5 with the 16-bit contents of R6. R6.19:16 is cleared. Before: Address Space Register After: Address Space Register 21036h xxxxh R5 AA550h 21034h D506h PC R6 11111h 21036h 21034h xxxxh D506h PC R5 AA550h R6 0B551h Example: BISX.A R5,R6 ; A550h.or.1111h = B551h This instruction logically ORs the 20-bit data contained in R5 with the 20-bit contents of R6. The extension word contains the A/L bit for 20-bit data. The instruction word uses byte mode with bits A/L:B/W = 01. The result of the instruction is: Before: Address Space Register After: Address Space Register 21036h xxxxh R5 AA550h 21034h D546h R6 11111h 21032h 1800h PC 21036h xxxxh 21034h D546h 21032h 1800h PC R5 AA550h R6 BB551h AA550h.or.11111h = BB551h SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 197 Addressing Modes www.ti.com 6.4.2 Indexed Mode The Indexed mode calculates the address of the operand by adding the signed index to a CPU register. The Indexed mode has four addressing possibilities: • Indexed mode in lower 64KB memory • MSP430 instruction with Indexed mode addressing memory above the lower 64KB memory • MSP430X instruction with Indexed mode • MSP430X address instructions with Indexed mode 6.4.2.1 Indexed Mode in Lower 64KB Memory If the CPU register Rn points to an address in the lower 64KB of the memory range, the calculated memory address bits 19:16 are cleared after the addition of the CPU register Rn and the signed 16-bit index. This means the calculated memory address is always located in the lower 64KB and does not overflow or underflow out of the lower 64KB memory space. The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 6-15. FFFFF Lower 64 KB Rn.19:16 = 0 19 16 15 0 0 CPU Register Rn 10000 0FFFF Rn.19:0 S 16-bit byte index 16-bit signed index 16-bit signed add Lower 64KB 00000 0 Memory address Figure 6-15. Indexed Mode in Lower 64KB Length: Operation: Comment: Example: Source: Destination: Two or three words The signed 16-bit index is located in the next word after the instruction and is added to the CPU register Rn. The resulting bits 19:16 are cleared giving a truncated 16-bit memory address, which points to an operand address in the range 00000h to 0FFFFh. The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the register index and inserts it. ADD.B 1000h(R5),0F000h(R6); This instruction adds the 8-bit data contained in source byte 1000h(R5) and the destination byte 0F000h(R6) and places the result into the destination byte. Source and destination bytes are both located in the lower 64KB due to the cleared bits 19:16 of registers R5 and R6. The byte pointed to by R5 + 1000h results in address 0479Ch + 1000h = 0579Ch after truncation to a 16-bit address. The byte pointed to by R6 + F000h results in address 01778h + F000h = 00778h after truncation to a 16-bit address. 198 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes Before: Address Space Register After: Address Space Register 1103Ah 11038h 11036h 11034h xxxxh F000h 1000h 55D6h R5 0479Ch R6 01778h PC 1103Ah 11038h 11036h 11034h xxxxh F000h 1000h 55D6h PC R5 0479Ch R6 01778h 0077Ah 00778h xxxxh xx45h 01778h +F000h 00778h 0077Ah 00778h xxxxh xx77h 32h +45h 77h src dst Sum 0579Eh 0579Ch xxxxh xx32h 0479Ch +1000h 0579Ch 0579Eh 0579Ch xxxxh xx32h 6.4.2.2 MSP430 Instruction With Indexed Mode in Upper Memory If the CPU register Rn points to an address above the lower 64KB memory, the Rn bits 19:16 are used for the address calculation of the operand. The operand may be located in memory in the range Rn ±32KB, because the index, X, is a signed 16-bit value. In this case, the address of the operand can overflow or underflow into the lower 64KB memory space (see Figure 6-16 and Figure 6-17). FFFFF Upper Memory Rn.19:16 > 0 19 16 15 1 ... 15 0 CPU Register Rn Rn.19:0 Rn ± 32 KB 10000 0FFFF S S 16-bit byte index 16-bit signed index (sign extended to 20 bits) 20-bit signed add Lower 64 KB 00000 Memory address Figure 6-16. Indexed Mode in Upper Memory SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 199 Addressing Modes www.ti.com FFFFF Rn.19:0 Rn.19:0 ±32 KB ±32 KB Lower 64 KB 10000 0,FFFF Rn.19:0 Rn.19:0 0000C Figure 6-17. Overflow and Underflow for Indexed Mode Length: Operation: Comment: Example: Source: Destination: Two or three words The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the CPU register Rn. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh. The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the register index and inserts it. ADD.W 8346h(R5),2100h(R6) ; This instruction adds the 16-bit data contained in the source and the destination addresses and places the 16-bit result into the destination. Source and destination operand can be located in the entire address range. The word pointed to by R5 + 8346h. The negative index 8346h is sign extended, which results in address 23456h + F8346h = 1B79Ch. The word pointed to by R6 + 2100h results in address 15678h + 2100h = 17778h. 200 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes Before: Address Space Register After: Address Space Register 1103Ah 11038h 11036h 11034h xxxxh 2100h 8346h 5596h R5 23456h R6 15678h PC 1103Ah 11038h 11036h 11034h xxxxh 2100h 8346h 5596h PC R5 23456h R6 15678h 1777Ah 17778h xxxxh 2345h 15678h +02100h 17778h 1777Ah 17778h xxxxh 7777h 05432h +02345h 07777h src dst Sum 1B79Eh 1B79Ch xxxxh 5432h 23456h +F8346h 1B79Ch 1B79Eh 1B79Ch xxxxh 5432h Figure 6-18. Example for Indexed Mode 6.4.2.3 MSP430X Instruction With Indexed Mode When using an MSP430X instruction with Indexed mode, the operand can be located anywhere in the range of Rn + 19 bits. Length: Operation: Comment: Example: Source: Destination: Three or four words The operand address is the sum of the 20-bit CPU register content and the 20-bit index. The 4 MSBs of the index are contained in the extension word; the 16 LSBs are contained in the word following the instruction. The CPU register is not modified Valid for source and destination. The assembler calculates the register index and inserts it. ADDX.A 12346h(R5),32100h(R6) ; This instruction adds the 20-bit data contained in the source and the destination addresses and places the result into the destination. Two words pointed to by R5 + 12346h which results in address 23456h + 12346h = 3579Ch. Two words pointed to by R6 + 32100h which results in address 45678h + 32100h = 77778h. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 201 Addressing Modes www.ti.com The extension word contains the MSBs of the source index and of the destination index and the A/L bit for 20-bit data. The instruction word uses byte mode due to the 20-bit data length with bits A/L:B/W = 01. Before: Address Space Register After: Address Space Register 2103Ah 21038h 21036h 21034h 21032h xxxxh 2100h 2346h 55D6h 1883h R5 23456h R6 45678h PC 2103Ah 21038h 21036h 21034h 21032h xxxxh 2100h 2346h 55D6h 1883h PC R5 23456h R6 45678h 7777Ah 77778h 0001h 2345h 45678h +32100h 77778h 7777Ah 77778h 0007h 7777h 65432h +12345h 77777h src dst Sum 3579Eh 3579Ch 0006h 5432h 23456h +12346h 3579Ch 3579Eh 3579Ch 0006h 5432h 6.4.2.4 MSP430X Address Instructions With Indexed Mode When using an MSP430X Address Instruction with Indexed mode, the operand is located in memory in the range Rn ±32KB, because the index, X, is a signed 16-bit value. Length: Operation: Comment: Example: Source: Destination: Two words The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the CPU register Rn. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh. The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the register index and inserts it. MOVA 8002h(R5),R6 ; // R5 = 0x100 This instruction loads the 20-bit data contained in the source address into destination register. Two words pointed to by R5 + 8002h and R5 + 8002h + 2h which results in address 00100h + F8002h (+2h) = F8102h and F8104h. Register R6 202 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes 6.4.3 Symbolic Mode The Symbolic mode calculates the address of the operand by adding the signed index to the PC. The Symbolic mode has three addressing possibilities: • Symbolic mode in lower 64KB of memory • MSP430 instruction with Symbolic mode addressing memory above the lower 64KB of memory. • MSP430X instruction with Symbolic mode 6.4.3.1 Symbolic Mode in Lower 64KB If the PC points to an address in the lower 64KB of the memory range, the calculated memory address bits 19:16 are cleared after the addition of the PC and the signed 16-bit index. This means the calculated memory address is always located in the lower 64KB and does not overflow or underflow out of the lower 64KB memory space. The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 6-19. FFFFF Lower 64 KB PC.19:16 = 0 19 16 15 0 0 Program counter PC 10000 0FFFF PC.19:0 S 16-bit byte index 16-bit signed PC index 16-bit signed add Lower 64 KB 00000 0 Memory address Figure 6-19. Symbolic Mode Running in Lower 64KB Operation: Length: Comment: Example: Source: Destination: The signed 16-bit index in the next word after the instruction is added temporarily to the PC. The resulting bits 19:16 are cleared giving a truncated 16-bit memory address, which points to an operand address in the range 00000h to 0FFFFh. The operand is the content of the addressed memory location. Two or three words Valid for source and destination. The assembler calculates the PC index and inserts it. ADD.B EDE,TONI ; This instruction adds the 8-bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI. Bytes EDE and TONI and the program are located in the lower 64KB. Byte EDE located at address 0579Ch, pointed to by PC + 4766h, where the PC index 4766h is the result of 0579Ch – 01036h = 04766h. Address 01036h is the location of the index for this example. Byte TONI located at address 00778h, pointed to by PC + F740h, is the truncated 16-bit result of 00778h – 1038h = FF740h. Address 01038h is the location of the index for this example. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 203 Addressing Modes Before: Address Space 0103Ah 01038h 01036h 01034h xxxxh F740h 4766h 05D0h PC After: Address Space 0103Ah 01038h 01036h 01034h xxxxh PC F740h 4766h 50D0h 0077Ah 00778h xxxxh xx45h 01038h +0F740h 00778h 0077Ah 00778h xxxxh xx77h 32h +45h 77h src dst Sum www.ti.com 0579Eh 0579Ch xxxxh xx32h 01036h +04766h 0579Ch 0579Eh 0579Ch xxxxh xx32h 6.4.3.2 MSP430 Instruction With Symbolic Mode in Upper Memory If the PC points to an address above the lower 64KB memory, the PC bits 19:16 are used for the address calculation of the operand. The operand may be located in memory in the range PC ± 32KB, because the index, X, is a signed 16-bit value. In this case, the address of the operand can overflow or underflow into the lower 64KB memory space as shown in Figure 6-20 and Figure 6-21. FFFFF Upper Memory PC.19:16 > 0 19 16 15 1 ... 15 0 Program counter PC PC.19:0 PC ±32 KB 10000 0FFFF S S 16-bit byte index 16-bit signed PC index (sign extended to 20 bits) 20-bit signed add Lower 64 KB 00000 Memory address Figure 6-20. Symbolic Mode Running in Upper Memory 204 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes FFFFF PC.19:0 ±32 KB PC.19:0 ±32 KB Lower 64 KB 10000 0FFFF PC.19:0 PC.19:0 0000C Figure 6-21. Overflow and Underflow for Symbolic Mode Length: Operation: Comment: Example: Source: Destination: Two or three words The sign-extended 16-bit index in the next word after the instruction is added to the 20 bits of the PC. This delivers a 20-bit address, which points to an address in the range 0 to FFFFFh. The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the PC index and inserts it ADD.W EDE,&TONI ; This instruction adds the 16-bit data contained in source word EDE and destination word TONI and places the 16-bit result into the destination word TONI. For this example, the instruction is located at address 2F034h. Word EDE at address 3379Ch, pointed to by PC + 4766h, which is the 16-bit result of 3379Ch – 2F036h = 04766h. Address 2F036h is the location of the index for this example. Word TONI located at address 00778h pointed to by the absolute address 00778h SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 205 Addressing Modes Before: Address Space 2F03Ah 2F038h 2F036h 2F034h xxxxh 0778h 4766h 5092h PC After: Address Space 2F03Ah 2F038h 2F036h 2F034h xxxxh PC 0778h 4766h 5092h 3379Eh 3379Ch xxxxh 5432h 2F036h +04766h 3379Ch 3379Eh 3379Ch xxxxh 5432h www.ti.com 0077Ah 00778h xxxxh 2345h 0077Ah 00778h xxxxh 7777h 5432h +2345h 7777h src dst Sum 6.4.3.3 MSP430X Instruction With Symbolic Mode When using an MSP430X instruction with Symbolic mode, the operand can be located anywhere in the range of PC + 19 bits. Length: Operation: Comment: Example: Source: Destination: Three or four words The operand address is the sum of the 20-bit PC and the 20-bit index. The 4 MSBs of the index are contained in the extension word; the 16 LSBs are contained in the word following the instruction. Valid for source and destination. The assembler calculates the register index and inserts it. ADDX.B EDE,TONI ; This instruction adds the 8-bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI. Byte EDE located at address 3579Ch, pointed to by PC + 14766h, is the 20-bit result of 3579Ch – 21036h = 14766h. Address 21036h is the address of the index in this example. Byte TONI located at address 77778h, pointed to by PC + 56740h, is the 20-bit result of 77778h – 21038h = 56740h. Address 21038h is the address of the index in this example. 206 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Before: Address Space 2103Ah 21038h 21036h 21034h 21032h xxxxh 6740h 4766h 50D0h 18C5h PC After: Address Space 2103Ah xxxxh PC 21038h 6740h 21036h 4766h 21034h 50D0h 21032h 18C5h Addressing Modes 7777Ah 77778h xxxxh xx45h 21038h +56740h 77778h 7777Ah 77778h xxxxh xx77h 32h +45h 77h src dst Sum 3579Eh 3579Ch xxxxh xx32h 21036h +14766h 3579Ch 3579Eh 3579Ch xxxxh xx32h 6.4.4 Absolute Mode The Absolute mode uses the contents of the word following the instruction as the address of the operand. The Absolute mode has two addressing possibilities: • Absolute mode in lower 64KB memory • MSP430X instruction with Absolute mode 6.4.4.1 Absolute Mode in Lower 64KB If an MSP430 instruction is used with Absolute addressing mode, the absolute address is a 16-bit value and, therefore, points to an address in the lower 64KB of the memory range. The address is calculated as an index from 0 and is stored in the word following the instruction The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications. Length: Operation: Comment: Example: Source: Destination: Two or three words The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the index from 0 and inserts it. ADD.W &EDE,&TONI ; This instruction adds the 16-bit data contained in the absolute source and destination addresses and places the result into the destination. Word at address EDE Word at address TONI SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 207 Addressing Modes Before: Address Space 2103Ah 21038h 21036h 21034h xxxxh 7778h 579Ch 5292h PC 0777Ah 07778h xxxxh 2345h After: Address Space 2103Ah 21038h 21036h 21034h xxxxh PC 7778h 579Ch 5292h 0777Ah 07778h xxxxh 7777h 5432h +2345h 7777h src dst Sum www.ti.com 0579Eh 0579Ch xxxxh 5432h 0579Eh 0579Ch xxxxh 5432h 6.4.4.2 MSP430X Instruction With Absolute Mode If an MSP430X instruction is used with Absolute addressing mode, the absolute address is a 20-bit value and, therefore, points to any address in the memory range. The address value is calculated as an index from 0. The 4 MSBs of the index are contained in the extension word, and the 16 LSBs are contained in the word following the instruction. Length: Operation: Comment: Example: Source: Destination: Three or four words The operand is the content of the addressed memory location. Valid for source and destination. The assembler calculates the index from 0 and inserts it. ADDX.A &EDE,&TONI ; This instruction adds the 20-bit data contained in the absolute source and destination addresses and places the result into the destination. Two words beginning with address EDE Two words beginning with address TONI 208 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Before: Address Space 2103Ah 21038h 21036h 21034h 21032h xxxxh 7778h 579Ch 52D2h 1987h PC 7777Ah 77778h 0001h 2345h After: Address Space 2103Ah xxxxh PC 21038h 7778h 21036h 579Ch 21034h 52D2h 21032h 1987h Addressing Modes 7777Ah 77778h 0007h 7777h 65432h +12345h 77777h src dst Sum 3579Eh 3579Ch 0006h 5432h 3579Eh 3579Ch 0006h 5432h 6.4.5 Indirect Register Mode The Indirect Register mode uses the contents of the CPU register Rsrc as the source operand. The Indirect Register mode always uses a 20-bit address. Length: Operation: Comment: Example: Source: Destination: One, two, or three words The operand is the content the addressed memory location. The source register Rsrc is not modified. Valid only for the source operand. The substitute for the destination operand is 0(Rdst). ADDX.W @R5,2100h(R6) This instruction adds the two 16-bit operands contained in the source and the destination addresses and places the result into the destination. Word pointed to by R5. R5 contains address 3579Ch for this example. Word pointed to by R6 + 2100h, which results in address 45678h + 2100h = 7778h SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 209 Addressing Modes Before: Address Space Register After: Address Space Register 21038h 21036h 21034h xxxxh 2100h 55A6h R5 R6 PC 3579Ch 45678h 21038h 21036h 21034h xxxxh 2100h 55A6h PC R5 3579Ch R6 45678h www.ti.com 4777Ah 47778h xxxxh 2345h 45678h +02100h 47778h 4777Ah 47778h xxxxh 7777h 5432h +2345h 7777h src dst Sum 3579Eh 3579Ch xxxxh 5432h R5 3579Eh 3579Ch xxxxh 5432h R5 6.4.6 Indirect Autoincrement Mode The Indirect Autoincrement mode uses the contents of the CPU register Rsrc as the source operand. Rsrc is then automatically incremented by 1 for byte instructions, by 2 for word instructions, and by 4 for address-word instructions immediately after accessing the source operand. If the same register is used for source and destination, it contains the incremented address for the destination access. Indirect Autoincrement mode always uses 20-bit addresses. Length: Operation: Comment: Example: Source: Destination: One, two, or three words The operand is the content of the addressed memory location. Valid only for the source operand ADD.B @R5+,0(R6) This instruction adds the 8-bit data contained in the source and the destination addresses and places the result into the destination. Byte pointed to by R5. R5 contains address 3579Ch for this example. Byte pointed to by R6 + 0h, which results in address 0778h for this example 210 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Addressing Modes Before: Address Space Register After: Address Space Register 21038h 21036h 21034h xxxxh 0000h 55F6h R5 R6 PC 3579Ch 00778h 21038h 21036h 21034h xxxxh 0000h 55F6h PC R5 3579Dh R6 00778h 0077Ah 00778h xxxxh xx45h 00778h +0000h 00778h 0077Ah 00778h xxxxh xx77h 32h +45h 77h src dst Sum 3579Dh 3579Ch xxh 32h R5 3579Dh 3579Ch xxh R5 xx32h 6.4.7 Immediate Mode The Immediate mode allows accessing constants as operands by including the constant in the memory location following the instruction. The PC is used with the Indirect Autoincrement mode. The PC points to the immediate value contained in the next word. After the fetching of the immediate operand, the PC is incremented by 2 for byte, word, or address-word instructions. The Immediate mode has two addressing possibilities: • 8-bit or 16-bit constants with MSP430 instructions • 20-bit constants with MSP430X instruction 6.4.7.1 MSP430 Instructions With Immediate Mode If an MSP430 instruction is used with Immediate addressing mode, the constant is an 8- or 16-bit value and is stored in the word following the instruction. Length: Operation: Comment: Example: Source: Destination: Two or three words. One word less if a constant of the constant generator can be used for the immediate operand. The 16-bit immediate source operand is used together with the 16-bit destination operand. Valid only for the source operand ADD #3456h,&TONI This instruction adds the 16-bit immediate operand 3456h to the data in the destination address TONI. 16-bit immediate value 3456h Word at address TONI SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 211 Addressing Modes Before: Address Space 2103Ah xxxxh 21038h 0778h 21036h 3456h 21034h 50B2h PC 0077Ah 00778h xxxxh 2345h After: Address Space 2103Ah xxxxh PC 21038h 0778h 21036h 3456h 21034h 50B2h 0077Ah 00778h xxxxh 579Bh 3456h +2345h 579Bh src dst Sum www.ti.com 6.4.7.2 MSP430X Instructions With Immediate Mode If an MSP430X instruction is used with Immediate addressing mode, the constant is a 20-bit value. The 4 MSBs of the constant are stored in the extension word, and the 16 LSBs of the constant are stored in the word following the instruction. Length: Operation: Comment: Example: Source: Destination: Three or four words. One word less if a constant of the constant generator can be used for the immediate operand. The 20-bit immediate source operand is used together with the 20-bit destination operand. Valid only for the source operand ADDX.A #23456h,&TONI ; This instruction adds the 20-bit immediate operand 23456h to the data in the destination address TONI. 20-bit immediate value 23456h Two words beginning with address TONI Before: Address Space After: Address Space 2103Ah 21038h 21036h 21034h 21032h xxxxh 7778h 3456h 50F2h 1907h PC 2103Ah xxxxh PC 21038h 7778h 21036h 3456h 21034h 50F2h 21032h 1907h 7777Ah 77778h 0001h 2345h 7777Ah 77778h 0003h 579Bh 23456h +12345h 3579Bh src dst Sum 212 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 6.5 MSP430 and MSP430X Instructions MSP430 instructions are the 27 implemented instructions of the MSP430 CPU. These instructions are used throughout the 1MB memory range unless their 16-bit capability is exceeded. The MSP430X instructions are used when the addressing of the operands or the data length exceeds the 16-bit capability of the MSP430 instructions. There are three possibilities when choosing between an MSP430 and MSP430X instruction: • To use only the MSP430 instructions – The only exceptions are the CALLA and the RETA instruction. This can be done if a few, simple rules are met: – Place all constants, variables, arrays, tables, and data in the lower 64KB. This allows the use of MSP430 instructions with 16-bit addressing for all data accesses. No pointers with 20-bit addresses are needed. – Place subroutine constants immediately after the subroutine code. This allows the use of the symbolic addressing mode with its 16-bit index to reach addresses within the range of PC + 32KB. • To use only MSP430X instructions – The disadvantages of this method are the reduced speed due to the additional CPU cycles and the increased program space due to the necessary extension word for any double-operand instruction. • Use the best fitting instruction where needed. Section 6.5.1 lists and describes the MSP430 instructions, and Section 6.5.2 lists and describes the MSP430X instructions. 6.5.1 MSP430 Instructions The MSP430 instructions can be used, regardless if the program resides in the lower 64KB or beyond it. The only exceptions are the instructions CALL and RET, which are limited to the lower 64KB address range. CALLA and RETA instructions have been added to the MSP430X CPU to handle subroutines in the entire address range with no code size overhead. 6.5.1.1 MSP430 Double-Operand (Format I) Instructions Figure 6-22 shows the format of the MSP430 double-operand instructions. Source and destination words are appended for the Indexed, Symbolic, Absolute, and Immediate modes. Table 6-4 lists the 12 MSP430 double-operand instructions. 15 12 11 87654 0 Op-code Rsrc Ad B/W As Rdst Source or Destination 15:0 Destination 15:0 Figure 6-22. MSP430 Double-Operand Instruction Format SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 213 MSP430 and MSP430X Instructions Table 6-4. MSP430 Double-Operand Instructions Mnemonic S-Reg, D-Reg Operation V MOV(.B) src,dst src → dst – ADD(.B) src,dst src + dst → dst * ADDC(.B) src,dst src + dst + C → dst * SUB(.B) src,dst dst + .not.src + 1 → dst * SUBC(.B) src,dst dst + .not.src + C → dst * CMP(.B) src,dst dst - src * DADD(.B) src,dst src + dst + C → dst (decimally) * BIT(.B) src,dst src .and. dst 0 BIC(.B) src,dst .not.src .and. dst → dst – BIS(.B) src,dst src .or. dst → dst – XOR(.B) src,dst src .xor. dst → dst * AND(.B) src,dst src .and. dst → dst 0 (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. www.ti.com Status Bits(1) N Z C – – – * * * * * * * * * * * * * * * * * * * * Z – – – – – – * * Z * * Z 6.5.1.2 MSP430 Single-Operand (Format II) Instructions Figure 6-23 shows the format for MSP430 single-operand instructions, except RETI. The destination word is appended for the Indexed, Symbolic, Absolute, and Immediate modes. Table 6-5 lists the seven singleoperand instructions. 15 7654 0 Op-code B/W Ad Rdst Destination 15:0 Figure 6-23. MSP430 Single-Operand Instructions Table 6-5. MSP430 Single-Operand Instructions Mnemonic S-Reg, D-Reg Operation RRC(.B) dst C → MSB →.......LSB → C RRA(.B) dst PUSH(.B) src SWPB dst MSB → MSB →....LSB → C SP - 2 → SP, src → SP bit 15...bit 8 ↔ bit 7...bit 0 CALL dst Call subroutine in lower 64KB RETI TOS → SR, SP + 2 → SP TOS → PC,SP + 2 → SP SXT dst Register mode: bit 7 → bit 8...bit 19 Other modes: bit 7 → bit 8...bit 15 (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. Status Bits(1) V N Z C 0 * * * 0 * * * – – – – – – – – – – – – * * * * 0 * * Z 214 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 6.5.1.3 Jump Instructions Figure 6-24 shows the format for MSP430 and MSP430X jump instructions. The signed 10-bit word offset of the jump instruction is multiplied by two, sign-extended to a 20-bit address, and added to the 20-bit PC. This allows jumps in a range of –511 to +512 words relative to the PC in the full 20-bit address space. Jumps do not affect the status bits. Table 6-6 lists and describes the eight jump instructions. 15 13 12 10 9 8 0 Op-Code Condition S 10-Bit Signed PC Offset Figure 6-24. Format of Conditional Jump Instructions Mnemonic JEQ, JZ JNE, JNZ JC JNC JN JGE JL JMP Table 6-6. Conditional Jump Instructions S-Reg, D-Reg Label Label Label Label Label Label Label Label Operation Jump to label if zero bit is set Jump to label if zero bit is reset Jump to label if carry bit is set Jump to label if carry bit is reset Jump to label if negative bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally 6.5.1.4 Emulated Instructions In addition to the MSP430 and MSP430X instructions, emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves. Instead, they are replaced automatically by the assembler with a core instruction. There is no code or performance penalty for using emulated instructions. The emulated instructions are listed in Table 6-7. Table 6-7. Emulated Instructions Instruction ADC(.B) dst BR dst CLR(.B) dst CLRC CLRN CLRZ DADC(.B) dst DEC(.B) dst DECD(.B) dst DINT EINT INC(.B) dst INCD(.B) dst Explanation Add Carry to dst Branch indirectly dst Clear dst Clear Carry bit Clear Negative bit Clear Zero bit Add Carry to dst decimally Decrement dst by 1 Decrement dst by 2 Disable interrupt Enable interrupt Increment dst by 1 Increment dst by 2 Emulation Status Bits(1) V N Z C ADDC(.B) #0,dst * * * * MOV dst,PC – – – – MOV(.B) #0,dst – – – – BIC #1,SR – – – 0 BIC #4,SR – 0 – – BIC #2,SR – – 0 – DADD(.B) #0,dst * * * * SUB(.B) #1,dst * * * * SUB(.B) #2,dst * * * * BIC #8,SR – – – – BIS #8,SR – – – – ADD(.B) #1,dst * * * * ADD(.B) #2,dst * * * * (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 215 MSP430 and MSP430X Instructions Table 6-7. Emulated Instructions (continued) Instruction INV(.B) dst NOP POP dst RET RLA(.B) dst RLC(.B) dst SBC(.B) dst SETC SETN SETZ TST(.B) dst Explanation Emulation V Invert dst XOR(.B) #–1,dst * No operation MOV R3,R3 – Pop operand from stack MOV @SP+,dst – Return from subroutine MOV @SP+,PC – Shift left dst arithmetically ADD(.B) dst,dst * Shift left dst logically through Carry ADDC(.B) dst,dst * Subtract Carry from dst SUBC(.B) #0,dst * Set Carry bit BIS #1,SR – Set Negative bit BIS #4,SR – Set Zero bit BIS #2,SR – Test dst (compare with 0) CMP(.B) #0,dst 0 www.ti.com Status Bits(1) N Z C * * * – – – – – – – – – * * * * * * * * * – – 1 1 – – – 1 – * * 1 6.5.1.5 MSP430 Instruction Execution The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used – not the instruction itself. The number of clock cycles refers to MCLK. 6.5.1.5.1 Instruction Cycles and Length for Interrupt, Reset, and Subroutines Table 6-8 lists the length and the CPU cycles for reset, interrupts, and subroutines. Table 6-8. Interrupt, Return, and Reset Cycles and Length Action Return from interrupt RETI Return from subroutine RET Interrupt request service (cycles needed before first instruction) WDT reset Reset (RST/NMI) Execution Time (MCLK Cycles) 5 4 6 4 4 Length of Instruction (Words) 1 1 – – – 6.5.1.5.2 Format II (Single-Operand) Instruction Cycles and Lengths Table 6-9 lists the length and the CPU cycles for all addressing modes of the MSP430 single-operand instructions. Table 6-9. MSP430 Format II Instruction Cycles and Length Addressing Mode Rn @Rn @Rn+ #N X(Rn) EDE &EDE No. of Cycles RRA, RRC SWPB, SXT PUSH 1 3 3 3 3 3 N/A 3 4 4 4 4 4 4 CALL 4 4 4 4 5 5 6 Length of Instruction 1 1 1 2 2 2 2 Example SWPB R5 RRC @R9 SWPB @R10+ CALL #LABEL CALL 2(R7) PUSH EDE SXT &EDE 216 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 6.5.1.5.3 Jump Instructions Cycles and Lengths All jump instructions require one code word and take two CPU cycles to execute, regardless of whether the jump is taken or not. 6.5.1.5.4 Format I (Double-Operand) Instruction Cycles and Lengths Table 6-10 lists the length and CPU cycles for all addressing modes of the MSP430 Format I instructions. Table 6-10. MSP430 Format I Instructions Cycles and Length Addressing Mode Source Destination No. of Cycles Length of Instruction Rn Rm 1 1 PC 3 1 x(Rm) 4 (1) 2 EDE 4 (1) 2 &EDE 4 (1) 2 @Rn Rm 2 1 PC 4 1 x(Rm) 5 (1) 2 EDE 5 (1) 2 &EDE 5 (1) 2 @Rn+ Rm 2 1 PC 4 1 x(Rm) 5 (1) 2 EDE 5 (1) 2 &EDE 5 (1) 2 #N Rm 2 2 PC 3 2 x(Rm) 5 (1) 3 EDE 5 (1) 3 &EDE 5 (1) 3 x(Rn) Rm 3 2 PC 5 2 TONI 6 (1) 3 x(Rm) 6 (1) 3 &TONI 6 (1) 3 EDE Rm 3 2 PC 5 2 TONI 6 (1) 3 x(Rm) 6 (1) 3 &TONI 6 (1) 3 &EDE Rm 3 2 PC 5 2 TONI 6 (1) 3 x(Rm) 6 (1) 3 &TONI 6 (1) 3 (1) MOV, BIT, and CMP instructions execute in one fewer cycle. Example MOV R5,R8 BR R9 ADD R5,4(R6) XOR R8,EDE MOV R5,&EDE AND @R4,R5 BR @R8 XOR @R5,8(R6) MOV @R5,EDE XOR @R5,&EDE ADD @R5+,R6 BR @R9+ XOR @R5,8(R6) MOV @R9+,EDE MOV @R9+,&EDE MOV #20,R9 BR #2AEh MOV #0300h,0(SP) ADD #33,EDE ADD #33,&EDE MOV 2(R5),R7 BR 2(R6) MOV 4(R7),TONI ADD 4(R4),6(R9) MOV 2(R4),&TONI AND EDE,R6 BR EDE CMP EDE,TONI MOV EDE,0(SP) MOV EDE,&TONI MOV &EDE,R8 BR &EDE MOV &EDE,TONI MOV &EDE,0(SP) MOV &EDE,&TONI SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 217 MSP430 and MSP430X Instructions www.ti.com 6.5.2 MSP430X Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space. Most MSP430X instructions require an additional word of op-code called the extension word. Some extended instructions do not require an additional word and are noted in the instruction description. All addresses, indexes, and immediate numbers have 20-bit values when preceded by the extension word. There are two types of extension words: • Register or register mode for Format I instructions and register mode for Format II instructions • Extension word for all other address mode combinations 6.5.2.1 Register Mode Extension Word The register mode extension word is shown in Figure 6-25 and described in Table 6-11. An example is shown in Figure 6-27. 15 12 11 10 9 8 7 6 5 4 3 0 0001 1 00 ZC # A/L 0 0 (n-1)/Rn Figure 6-25. Extension Word for Register Modes Bit 15:11 10:9 ZC # A/L 5:4 3:0 Table 6-11. Description of the Extension Word Bits for Register Mode Description Extension word op-code. Op-codes 1800h to 1FFFh are extension words. Reserved Zero carry 0 The executed instruction uses the status of the carry bit C. 1 The executed instruction uses the carry bit as 0. The carry bit is defined by the result of the final operation after instruction execution. Repetition 0 The number of instruction repetitions is set by extension word bits 3:0. 1 The number of instruction repetitions is defined by the value of the four LSBs of Rn. See description for bits 3:0. Data length extension. Together with the B/W bits of the following MSP430 instruction, the AL bit defines the used data length of the instruction. A/L B/W Comment 0 0 Reserved 0 1 20-bit address word 1 0 16-bit word 1 1 8-bit byte Reserved Repetition count # = 0 These four bits set the repetition count n. These bits contain n – 1. # = 1 These four bits define the CPU register whose bits 3:0 set the number of repetitions. Rn.3:0 contain n – 1. 6.5.2.2 Non-Register Mode Extension Word The extension word for non-register modes is shown in Figure 6-26 and described in Table 6-12. An example is shown in Figure 6-28. 15 12 11 10 76543 0 0 0 0 1 1 Source bits 19:16 A/L 0 0 Destination bits 19:16 Figure 6-26. Extension Word for Non-Register Modes 218 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions Table 6-12. Description of Extension Word Bits for Non-Register Modes Bit Description 15:11 Extension word op-code. Op-codes 1800h to 1FFFh are extension words. Source Bits The four MSBs of the 20-bit source. Depending on the source addressing mode, these four MSBs may belong to an 19:16 immediate operand, an index, or to an absolute address. A/L Data length extension. Together with the B/W bits of the following MSP430 instruction, the AL bit defines the used data length of the instruction. A/L B/W Comment 0 0 Reserved 0 1 20-bit address word 1 0 16-bit word 1 1 8-bit byte 5:4 Reserved Destination The four MSBs of the 20-bit destination. Depending on the destination addressing mode, these four MSBs may Bits 19:16 belong to an index or to an absolute address. NOTE: B/W and A/L bit settings for SWPBX and SXTX A/L B/W 0 0 SWPBX.A, SXTX.A 0 1 N/A 1 0 SWPB.W, SXTX.W 1 1 N/A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00011 00 ZC # A/L Rsvd (n-1)/Rn Op-code Rsrc Ad B/W As Rdst XORX.A R9,R8 1: Repetition count in bits 3:0 0: Use Carry 01:Address word 00011 0 000 0 0 14(XOR) 9 01 0 8(R8) XORX instruction Source R9 Destination R8 Destination register mode Source register mode Figure 6-27. Example for Extended Register or Register Instruction SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 219 MSP430 and MSP430X Instructions 15 14 13 12 11 10 9 8 7 6 5 4 00011 Source 19:16 A/L Rsvd 3210 Destination 19:16 Op-code Rsrc Ad B/W As Rdst Source 15:0 Destination 15:0 XORX.A #12345h, 45678h(R15) 18xx extension word 00011 X(Rn) 01: Address word 12345h 1 0 0 @PC+ 4 14 (XOR) 0 (PC) 11 3 15 (R15) Immediate operand LSBs: 2345h Index destination LSBs: 5678h Figure 6-28. Example for Extended Immediate or Indexed Instruction www.ti.com 6.5.2.3 Extended Double-Operand (Format I) Instructions All 12 double-operand instructions have extended versions as listed in Table 6-13. Table 6-13. Extended Double-Operand Instructions Mnemonic Operands Operation Status Bits(1) V N Z C MOVX(.B,.A) src,dst src → dst – – – – ADDX(.B,.A) src,dst src + dst → dst * * * * ADDCX(.B,.A) src,dst src + dst + C → dst * * * * SUBX(.B,.A) src,dst dst + .not.src + 1 → dst * * * * SUBCX(.B,.A) src,dst dst + .not.src + C → dst * * * * CMPX(.B,.A) src,dst dst – src * * * * DADDX(.B,.A) src,dst src + dst + C → dst (decimal) * * * * BITX(.B,.A) src,dst src .and. dst 0 * * Z BICX(.B,.A) src,dst .not.src .and. dst → dst – – – – BISX(.B,.A) src,dst src .or. dst → dst – – – – XORX(.B,.A) src,dst src .xor. dst → dst * * * Z ANDX(.B,.A) src,dst src .and. dst → dst 0 * * Z (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. 220 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions The four possible addressing combinations for the extension word for Format I instructions are shown in Figure 6-29. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn Op-code src 0 B/W 0 0 dst 0 0 01 1 Op-code src.19:16 A/L 0 0 0 0 0 0 src Ad B/W As dst src.15:0 0 0 0 1 1 0 0 0 0 A/L 0 0 Op-code src Ad B/W As dst.15:0 dst.19:16 dst 0 0 01 1 Op-code src.19:16 A/L 0 0 src Ad B/W As src.15:0 dst.15:0 dst.19:16 dst Figure 6-29. Extended Format I Instruction Formats If the 20-bit address of a source or destination operand is located in memory, not in a CPU register, then two words are used for this operand as shown in Figure 6-30. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address+2 0 .......................................................................................0 19:16 Address Operand LSBs 15:0 Figure 6-30. 20-Bit Addresses in Memory SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 221 MSP430 and MSP430X Instructions 6.5.2.4 Extended Single-Operand (Format II) Instructions Extended MSP430X Format II instructions are listed in Table 6-14. www.ti.com Table 6-14. Extended Single-Operand Instructions Mnemonic Operands Operation CALLA dst POPM.A #n,Rdst POPM.W #n,Rdst PUSHM.A #n,Rsrc PUSHM.W #n,Rsrc PUSHX(.B,.A) src RRCM(.A) #n,Rdst RRUM(.A) #n,Rdst RRAM(.A) #n,Rdst RLAM(.A) #n,Rdst RRCX(.B,.A) dst RRUX(.B,.A) Rdst RRAX(.B,.A) dst SWPBX(.A) dst SXTX(.A) Rdst SXTX(.A) dst (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. Call indirect to subroutine (20-bit address) Pop n 20-bit registers from stack Pop n 16-bit registers from stack Push n 20-bit registers to stack Push n 16-bit registers to stack Push 8-, 16-, or 20-bit source to stack Rotate right Rdst n bits through carry (16-, 20-bit register) Rotate right Rdst n bits unsigned (16-, 20-bit register) Rotate right Rdst n bits arithmetically (16-, 20-bit register) Rotate left Rdst n bits arithmetically (16-, 20-bit register) Rotate right dst through carry (8-, 16-, 20-bit data) Rotate right dst unsigned (8-, 16-, 20-bit) Rotate right dst arithmetically Exchange low byte with high byte Bit7 → bit8 ... bit19 Bit7 → bit8 ... MSB n 1 to 16 1 to 16 1 to 16 1 to 16 1 to 4 1 to 4 1 to 4 1 to 4 1 1 1 1 1 1 Status Bits(1) VNZC –––– –––– –––– –––– –––– –––– 0* * * 0* * * 0* * * **** 0* * * 0* * * 0* * * –––– 0* *Z 0* *Z The three possible addressing mode combinations for Format II instructions are shown in Figure 6-31. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn Op-code B/W 0 0 dst 0 0 0 1 1 0 0 0 0 A/L 0 0 0 0 0 0 Op-code B/W 1 x dst 0 0 01 1 0 0 Op-code 0 0 A/L 0 0 B/W x 1 dst.15:0 dst.19:16 dst Figure 6-31. Extended Format II Instruction Format 222 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 6.5.2.4.1 Extended Format II Instruction Format Exceptions Exceptions for the Format II instruction formats are shown in Figure 6-32 through Figure 6-35. 15 87 43 0 Op-code n-1 Rdst - n+1 Figure 6-32. PUSHM and POPM Instruction Format 15 12 11 10 9 C n-1 Op-code 43 0 Rdst Figure 6-33. RRCM, RRAM, RRUM, and RLAM Instruction Format 15 12 11 87 43 0 C Rsrc Op-code 0(PC) C #imm/abs19:16 Op-code #imm15:0 / &abs15:0 0(PC) C 15 Rsrc Op-code index15:0 0(PC) Figure 6-34. BRA Instruction Format Op-code 43 0 Rdst Op-code index15:0 Rdst Op-code #imm15:0 / index15:0 / &abs15:0 #imm/ix/abs19:16 Figure 6-35. CALLA Instruction Format SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 223 MSP430 and MSP430X Instructions www.ti.com 6.5.2.5 Extended Emulated Instructions The extended instructions together with the constant generator form the extended emulated instructions. Table 6-15 lists the emulated instructions. Instruction ADCX(.B,.A) dst BRA dst RETA CLRA Rdst CLRX(.B,.A) dst DADCX(.B,.A) dst DECX(.B,.A) dst DECDA Rdst DECDX(.B,.A) dst INCX(.B,.A) dst INCDA Rdst INCDX(.B,.A) dst INVX(.B,.A) dst RLAX(.B,.A) dst RLCX(.B,.A) dst SBCX(.B,.A) dst TSTA Rdst TSTX(.B,.A) dst POPX dst Table 6-15. Extended Emulated Instructions Explanation Add carry to dst Branch indirect dst Return from subroutine Clear Rdst Clear dst Add carry to dst decimally Decrement dst by 1 Decrement Rdst by 2 Decrement dst by 2 Increment dst by 1 Increment Rdst by 2 Increment dst by 2 Invert dst Shift left dst arithmetically Shift left dst logically through carry Subtract carry from dst Test Rdst (compare with 0) Test dst (compare with 0) Pop to dst Emulation ADDCX(.B,.A) #0,dst MOVA dst,PC MOVA @SP+,PC MOV #0,Rdst MOVX(.B,.A) #0,dst DADDX(.B,.A) #0,dst SUBX(.B,.A) #1,dst SUBA #2,Rdst SUBX(.B,.A) #2,dst ADDX(.B,.A) #1,dst ADDA #2,Rdst ADDX(.B,.A) #2,dst XORX(.B,.A) #-1,dst ADDX(.B,.A) dst,dst ADDCX(.B,.A) dst,dst SUBCX(.B,.A) #0,dst CMPA #0,Rdst CMPX(.B,.A) #0,dst MOVX(.B, .A) @SP+,dst 224 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 6.5.2.6 MSP430X Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode, except for the MOVA instruction as listed in Table 6-16. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time. Address instructions should be used any time an MSP430X instruction is needed with the corresponding restricted addressing mode. Table 6-16. Address Instructions, Operate on 20-Bit Register Data Mnemonic Operands ADDA Rsrc,Rdst #imm20,Rdst MOVA Rsrc,Rdst #imm20,Rdst z16(Rsrc),Rdst EDE,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,z16(Rdst) Rsrc,&abs20 CMPA Rsrc,Rdst #imm20,Rdst SUBA Rsrc,Rdst #imm20,Rdst (1) * = Status bit is affected. – = Status bit is not affected. 0 = Status bit is cleared. 1 = Status bit is set. Operation Add source to destination register Move source to destination Status Bits(1) VNZC **** –––– Compare source to destination register * * * * Subtract source from destination register * * * * SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 225 MSP430 and MSP430X Instructions www.ti.com 6.5.2.7 MSP430X Instruction Execution The number of CPU clock cycles required for an MSP430X instruction depends on the instruction format and the addressing modes used, not the instruction itself. The number of clock cycles refers to MCLK. 6.5.2.7.1 MSP430X Format II (Single-Operand) Instruction Cycles and Lengths Table 6-17 lists the length and the CPU cycles for all addressing modes of the MSP430X extended singleoperand instructions. Table 6-17. MSP430X Format II Instruction Cycles and Length Instruction Rn RRAM n, 1 RRCM n, 1 RRUM n, 1 RLAM n, 1 PUSHM 2+n, 1 PUSHM.A 2+2n, 1 POPM 2+n, 1 POPM.A 2+2n, 1 CALLA 5, 1 RRAX(.B) 1+n, 2 RRAX.A 1+n, 2 RRCX(.B) 1+n, 2 RRCX.A 1+n, 2 PUSHX(.B) 4, 2 PUSHX.A 5, 2 POPX(.B) 3, 2 POPX.A 4, 2 (1) Add one cycle when Rn = SP Execution Cycles, Length of Instruction (Words) @Rn @Rn+ #N X(Rn) EDE – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 6, 1 6, 1 5, 2 5(1), 2 7, 2 4, 2 4, 2 – 5, 3 5, 3 6, 2 6, 2 – 7, 3 7, 3 4, 2 4, 2 – 5, 3 5, 3 6, 2 6, 2 – 7, 3 7, 3 4, 2 4, 2 4, 3 5(1), 3 5, 3 6, 2 6, 2 5, 3 7(1), 3 7, 3 – – – 5, 3 5, 3 – – – 7, 3 7, 3 &EDE – – – – – – – – 7, 2 5, 3 7, 3 5, 3 7, 3 5, 3 7, 3 5, 3 7, 3 226 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MSP430 and MSP430X Instructions 6.5.2.7.2 MSP430X Format I (Double-Operand) Instruction Cycles and Lengths Table 6-18 lists the length and CPU cycles for all addressing modes of the MSP430X extended Format I instructions. Table 6-18. MSP430X Format I Instruction Cycles and Length Addressing Mode Source Destination No. of Cycles .B/.W .A Length of Instruction .B/.W/.A Examples Rn Rm (1) 2 2 2 BITX.B R5,R8 PC 4 4 2 ADDX R9,PC x(Rm) 5 (2) 7 (3) 3 ANDX.A R5,4(R6) EDE 5 (2) 7 (3) 3 XORX R8,EDE &EDE 5 (2) 7 (3) 3 BITX.W R5,&EDE @Rn Rm 3 4 2 BITX @R5,R8 PC 5 6 2 ADDX @R9,PC x(Rm) 6 (2) 9 (3) 3 ANDX.A @R5,4(R6) EDE 6 (2) 9 (3) 3 XORX @R8,EDE &EDE 6 (2) 9 (3) 3 BITX.B @R5,&EDE @Rn+ Rm 3 4 2 BITX @R5+,R8 PC 5 6 2 ADDX.A @R9+,PC x(Rm) 6 (2) 9 (3) 3 ANDX @R5+,4(R6) EDE 6 (2) 9 (3) 3 XORX.B @R8+,EDE &EDE 6 (2) 9 (3) 3 BITX @R5+,&EDE #N Rm 3 3 3 BITX #20,R8 PC (4) 4 4 3 ADDX.A #FE000h,PC x(Rm) 6 (2) 8 (3) 4 ANDX #1234,4(R6) EDE 6 (2) 8 (3) 4 XORX #A5A5h,EDE &EDE 6 (2) 8 (3) 4 BITX.B #12,&EDE x(Rn) Rm 4 5 3 BITX 2(R5),R8 PC (4) 6 7 3 SUBX.A 2(R6),PC TONI 7 (2) 10 (3) 4 ANDX 4(R7),4(R6) x(Rm) 7 (2) 10 (3) 4 XORX.B 2(R6),EDE &TONI 7 (2) 10 (3) 4 BITX 8(SP),&EDE EDE Rm 4 5 3 BITX.B EDE,R8 PC (4) 6 7 3 ADDX.A EDE,PC TONI 7 (2) 10 (3) 4 ANDX EDE,4(R6) x(Rm) 7 (2) 10 (3) 4 ANDX EDE,TONI &TONI 7 (2) 10 (3) 4 BITX EDE,&TONI &EDE Rm 4 5 3 BITX &EDE,R8 PC (4) 6 7 3 ADDX.A &EDE,PC TONI 7 (2) 10 (3) 4 ANDX.B &EDE,4(R6) x(Rm) 7 (2) 10 (3) 4 XORX &EDE,TONI &TONI 7 (2) 10 (3) 4 BITX &EDE,&TONI (1) Repeat instructions require n + 1 cycles, where n is the number of times the instruction is executed. (2) Reduce the cycle count by one for MOV, BIT, and CMP instructions. (3) Reduce the cycle count by two for MOV, BIT, and CMP instructions. (4) Reduce the cycle count by one for MOV, ADD, and SUB instructions. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 227 MSP430 and MSP430X Instructions www.ti.com 6.5.2.7.3 MSP430X Address Instruction Cycles and Lengths Table 6-19 lists the length and the CPU cycles for all addressing modes of the MSP430X address instructions. Addressing Mode Source Destination Rn @Rn @Rn+ #N x(Rn) EDE &EDE Rn PC x(Rm) EDE &EDE Rm PC Rm PC Rm PC Rm PC Rm PC Rm PC Table 6-19. Address Instruction Cycles and Length Execution Time (MCLK Cycles) MOVA BRA CMPA ADDA SUBA 1 1 3 3 4 – 4 – 4 – 3 – 5 – 3 – 5 – 2 3 3 3 4 – 6 – 4 – 6 – 4 – 6 – Length of Instruction (Words) MOVA CMPA ADDA SUBA 1 1 1 1 2 – 2 – 2 – 1 – 1 – 1 – 1 – 2 2 2 2 2 – 2 – 2 – 2 – 2 – 2 – Example CMPA R5,R8 SUBA R9,PC MOVA R5,4(R6) MOVA R8,EDE MOVA R5,&EDE MOVA @R5,R8 MOVA @R9,PC MOVA @R5+,R8 MOVA @R9+,PC CMPA #20,R8 SUBA #FE000h,PC MOVA 2(R5),R8 MOVA 2(R6),PC MOVA EDE,R8 MOVA EDE,PC MOVA &EDE,R8 MOVA &EDE,PC 228 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6 Instruction Set Description Table 6-20 shows all available instructions: Instruction Set Description Table 6-20. Instruction Map of MSP430X 000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0 0xxx MOVA, CMPA, ADDA, SUBA, RRCM, RRAM, RLAM, RRUM 10xx RRC RRC. B SWP B RRA RRA. B SXT PUS H PUS H.B CALL RETI CALL A 14xx PUSHM.A, POPM.A, PUSHM.W, POPM.W 18xx 1Cxx Extension word for Format I and Format II instructions 20xx JNE, JNZ 24xx JEQ, JZ 28xx JNC 2Cxx JC 30xx JN 34xx JGE 38xx JL 3Cxx JMP 4xxx MOV, MOV.B 5xxx ADD, ADD.B 6xxx ADDC, ADDC.B 7xxx SUBC, SUBC.B 8xxx SUB, SUB.B 9xxx CMP, CMP.B Axxx DADD, DADD.B Bxxx BIT, BIT.B Cxxx BIC, BIC.B Dxxx BIS, BIS.B Exxx XOR, XOR.B Fxxx AND, AND.B SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 229 Instruction Set Description 6.6.1 Extended Instruction Binary Descriptions Detailed MSP430X instruction binary descriptions are shown in the following tables. www.ti.com Instruction MOVA CMPA ADDA SUBA MOVA CMPA ADDA SUBA Instruction Group src or data.19:16 Instruction Identifier 15 12 11 87 4 0000 src 0000 0000 src 0001 0000 &abs.19:16 0010 &abs.15:0 0000 src 0011 x.15:0 0000 src 0110 &abs.15:0 0000 src 0111 x.15:0 0000 imm.19:16 1000 imm.15:0 0000 imm.19:16 1001 imm.15:0 0000 imm.19:16 1010 imm.15:0 0000 imm.19:16 1011 imm.15:0 0000 src 1100 0000 src 1101 0000 src 1110 0000 src 1111 dst 3 0 dst MOVA @Rsrc,Rdst dst MOVA @Rsrc+,Rdst dst MOVA &abs20,Rdst dst MOVA z16(Rsrc),Rdst &abs.19:16 MOVA Rsrc,&abs20 dst MOVA Rsrc,z16(Rdst) dst MOVA #imm20,Rdst dst CMPA #imm20,Rdst dst ADDA #imm20,Rdst dst SUBA #imm20,Rdst dst MOVA Rsrc,Rdst dst CMPA Rsrc,Rdst dst ADDA Rsrc,Rdst dst SUBA Rsrc,Rdst Instruction Instruction Group Bit Loc. Inst. ID Instruction Identifier dst 15 12 11 10 9 8 7 43 0 RRCM.A 0 0 0 0 n–1 0 0 0 1 0 0 dst RRCM.A #n,Rdst RRAM.A 0 0 0 0 n–1 0 1 0 1 0 0 dst RRAM.A #n,Rdst RLAM.A 0 0 0 0 n–1 1 0 0 1 0 0 dst RLAM.A #n,Rdst RRUM.A 0 0 0 0 n–1 1 1 0 1 0 0 dst RRUM.A #n,Rdst RRCM.W 0 0 0 0 n–1 0 0 0 1 0 1 dst RRCM.W #n,Rdst RRAM.W 0 0 0 0 n–1 0 1 0 1 0 1 dst RRAM.W #n,Rdst RLAM.W 0 0 0 0 n–1 1 0 0 1 0 1 dst RLAM.W #n,Rdst RRUM.W 0 0 0 0 n–1 1 1 0 1 0 1 dst RRUM.W #n,Rdst 230 CPUX SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Instruction RETI CALLA Reserved Reserved PUSHM.A PUSHM.W POPM.A POPM.W Instruction Set Description Instruction Identifier dst 15 12 11 876543 0 0001001100000000 000100110100 dst CALLA Rdst 000100110101 dst CALLA x(Rdst) x.15:0 000100110110 dst CALLA @Rdst 000100110111 dst CALLA @Rdst+ 000100111000 &abs.19:16 CALLA &abs20 &abs.15:0 000100111001 x.19:16 CALLA EDE x.15:0 CALLA x(PC) 000100111011 imm.19:16 CALLA #imm20 imm.15:0 000100111010xxxx 0001001111xxxxxx 00010100 n–1 dst PUSHM.A #n,Rdst 00010101 n–1 dst PUSHM.W #n,Rdst 00010110 n–1 dst – n + 1 POPM.A #n,Rdst 00010111 n–1 dst – n + 1 POPM.W #n,Rdst SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 231 Instruction Set Description 6.6.2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages. www.ti.com 232 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.1 ADC Instruction Set Description * ADC[.W] * ADC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Add carry to destination Add carry to destination ADC dst or ADC.W dst ADC.B dst dst + C → dst ADDC #0,dst ADDC.B #0,dst The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if dst was incremented from 0FFFFh to 0000, reset otherwise Set if dst was incremented from 0FFh to 00, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. The 16-bit counter pointed to by R13 is added to a 32-bit counter pointed to by R12. ADD @R13,0(R12) ADC 2(R12) ; Add LSDs ; Add carry to MSD Example The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ADC.B 1(R12) ; Add LSDs ; Add carry to MSD SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 233 Instruction Set Description 6.6.2.2 ADD www.ti.com ADD[.W] ADD.B Syntax Operation Description Status Bits Mode Bits Example Add source word to destination word Add source byte to destination byte ADD src,dst or ADD.W src,dst ADD.B src,dst src + dst → dst The source operand is added to the destination operand. The previous content of the destination is lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Ten is added to the 16-bit counter CNTR located in lower 64 K. ADD.W #10,&CNTR ; Add 10 to 16-bit counter Example A table word pointed to by R5 (20-bit address in R5) is added to R6. The jump to label TONI is performed on a carry. ADD.W JC ... @R5,R6 TONI ; Add table word to R6. R6.19:16 = 0 ; Jump if carry ; No carry Example A table byte pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. R6.19:8 = 0 ADD.B JNC ... @R5+,R6 TONI ; Add byte to R6. R5 + 1. R6: 000xxh ; Jump if no carry ; Carry occurred 234 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.3 ADDC Instruction Set Description ADDC[.W] ADDC.B Syntax Operation Description Status Bits Mode Bits Example Add source word and carry to destination word Add source byte and carry to destination byte ADDC src,dst or ADDC.W src,dst ADDC.B src,dst src + dst + C → dst The source operand and the carry bit C are added to the destination operand. The previous content of the destination is lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Constant value 15 and the carry of the previous instruction are added to the 16-bit counter CNTR located in lower 64 K. ADDC.W #15,&CNTR ; Add 15 + C to 16-bit CNTR Example A table word pointed to by R5 (20-bit address) and the carry C are added to R6. The jump to label TONI is performed on a carry. R6.19:16 = 0 ADDC.W JC ... @R5,R6 TONI ; Add table word + C to R6 ; Jump if carry ; No carry Example A table byte pointed to by R5 (20-bit address) and the carry bit C are added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. R6.19:8 = 0 ADDC.B JNC ... @R5+,R6 TONI ; Add table byte + C to R6. R5 + 1 ; Jump if no carry ; Carry occurred SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 235 Instruction Set Description 6.6.2.4 AND www.ti.com AND[.W] AND.B Syntax Operation Description Status Bits Mode Bits Example Logical AND of source word with destination word Logical AND of source byte with destination byte AND src,dst or AND.W src,dst AND.B src,dst src .and. dst → dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The bits set in R5 (16-bit data) are used as a mask (AA55h) for the word TOM located in the lower 64 K. If the result is zero, a branch is taken to label TONI. R5.19:16 = 0 MOV #AA55h,R5 ; Load 16-bit mask to R5 AND R5,&TOM ; TOM .and. R5 -> TOM JZ TONI ; Jump if result 0 ... ; Result > 0 or shorter: AND #AA55h,&TOM ; TOM .and. AA55h -> TOM JZ TONI ; Jump if result 0 Example A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R5 is incremented by 1 after the fetching of the byte. R6.19:8 = 0 AND.B @R5+,R6 ; AND table byte with R6. R5 + 1 236 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.5 BIC Instruction Set Description BIC[.W] BIC.B Syntax Operation Description Status Bits Mode Bits Example Clear bits set in source word in destination word Clear bits set in source byte in destination byte BIC src,dst or BIC.W src,dst BIC.B src,dst (.not. src) .and. dst → dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The bits 15:14 of R5 (16-bit data) are cleared. R5.19:16 = 0 BIC #0C000h,R5 ; Clear R5.19:14 bits Example A table word pointed to by R5 (20-bit address) is used to clear bits in R7. R7.19:16 = 0 BIC.W @R5,R7 ; Clear bits in R7 set in @R5 Example A table byte pointed to by R5 (20-bit address) is used to clear bits in Port1. BIC.B @R5,&P1OUT ; Clear I/O port P1 bits set in @R5 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 237 Instruction Set Description 6.6.2.6 BIS www.ti.com BIS[.W] BIS.B Syntax Operation Description Status Bits Mode Bits Example Set bits set in source word in destination word Set bits set in source byte in destination byte BIS src,dst or BIS.W src,dst BIS.B src,dst src .or. dst → dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Bits 15 and 13 of R5 (16-bit data) are set to one. R5.19:16 = 0 BIS #A000h,R5 ; Set R5 bits Example A table word pointed to by R5 (20-bit address) is used to set bits in R7. R7.19:16 = 0 BIS.W @R5,R7 ; Set bits in R7 Example A table byte pointed to by R5 (20-bit address) is used to set bits in Port1. R5 is incremented by 1 afterwards. BIS.B @R5+,&P1OUT ; Set I/O port P1 bits. R5 + 1 238 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.7 BIT Instruction Set Description BIT[.W] BIT.B Syntax Operation Description Status Bits Mode Bits Example Test bits set in source word in destination word Test bits set in source byte in destination byte BIT src,dst or BIT.W src,dst BIT.B src,dst src .and. dst The source operand and the destination operand are logically ANDed. The result affects only the status bits in SR. Register mode: the register bits Rdst.19:16 (.W) resp. Rdst. 19:8 (.B) are not cleared! N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. Test if one (or both) of bits 15 and 14 of R5 (16-bit data) is set. Jump to label TONI if this is the case. R5.19:16 are not affected. BIT #C000h,R5 JNZ TONI ... ; Test R5.15:14 bits ; At least one bit is set in R5 ; Both bits are reset Example A table word pointed to by R5 (20-bit address) is used to test bits in R7. Jump to label TONI if at least one bit is set. R7.19:16 are not affected. BIT.W JC ... @R5,R7 TONI ; Test bits in R7 ; At least one bit is set ; Both are reset Example A table byte pointed to by R5 (20-bit address) is used to test bits in output Port1. Jump to label TONI if no bit is set. The next table byte is addressed. BIT.B JNC ... @R5+,&P1OUT TONI ; Test I/O port P1 bits. R5 + 1 ; No corresponding bit is set ; At least one bit is set SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 239 Instruction Set Description 6.6.2.8 BR, BRANCH www.ti.com * BR, BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination in lower 64K address space BR dst dst → PC MOV dst,PC An unconditional branch is taken to an address anywhere in the lower 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. BR #EXEC ; Branch to label EXEC or direct branch (for example #0A4h) ; Core instruction MOV @PC+,PC BR EXEC ; Branch to the address contained in EXEC ; Core instruction MOV X(PC),PC ; Indirect address BR &EXEC ; Branch to the address contained in absolute ; address EXEC ; Core instruction MOV X(0),PC ; Indirect address BR R5 ; Branch to the address contained in R5 ; Core instruction MOV R5,PC ; Indirect R5 BR @R5 ; Branch to the address contained in the word ; pointed to by R5. ; Core instruction MOV @R5,PC ; Indirect, indirect R5 BR @R5+ ; Branch to the address contained in the word pointed ; to by R5 and increment pointer in R5 afterwards. ; The next time-S/W flow uses R5 pointer-it can ; alter program execution due to access to ; next address in a table pointed to by R5 ; Core instruction MOV @R5,PC ; Indirect, indirect R5 with autoincrement BR X(R5) ; Branch to the address contained in the address ; pointed to by R5 + X (for example table with address ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X 240 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.9 CALL Instruction Set Description CALL Syntax Operation Description Status Bits Mode Bits Examples Call a subroutine in lower 64 K CALL dst dst → tmp 16-bit dst is evaluated and stored SP – 2 → SP PC → @SP updated PC with return address to TOS tmp → PC saved 16-bit dst to PC A subroutine call is made from an address in the lower 64 K to a subroutine address in the lower 64 K. All seven source addressing modes can be used. The call instruction is a word instruction. The return is made with the RET instruction. Status bits are not affected. PC.19:16 cleared (address in lower 64 K) OSCOFF, CPUOFF, and GIE are not affected. Examples for all addressing modes are given. Immediate Mode: Call a subroutine at label EXEC (lower 64 K) or call directly to address. CALL #EXEC CALL #0AA04h ; Start address EXEC ; Start address 0AA04h Symbolic Mode: Call a subroutine at the 16-bit address contained in address EXEC. EXEC is located at the address (PC + X) where X is within PC ± 32 K. CALL EXEC ; Start address at @EXEC. z16(PC) Absolute Mode: Call a subroutine at the 16-bit address contained in absolute address EXEC in the lower 64 K. CALL &EXEC ; Start address at @EXEC Register mode: Call a subroutine at the 16-bit address contained in register R5.15:0. CALL R5 ; Start address at R5 Indirect Mode: Call a subroutine at the 16-bit address contained in the word pointed to by register R5 (20-bit address). CALL @R5 ; Start address at @R5 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 241 Instruction Set Description 6.6.2.10 CLR * CLR[.W] * CLR.B Syntax Operation Emulation Description Status Bits Example Clear destination Clear destination CLR dst or CLR.B dst CLR.W dst 0 → dst MOV #0,dst MOV.B #0,dst The destination operand is cleared. Status bits are not affected. RAM word TONI is cleared. CLR TONI ; 0 -> TONI Example Register R5 is cleared. CLR R5 Example RAM byte TONI is cleared. CLR.B TONI ; 0 -> TONI www.ti.com 242 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.11 CLRC Instruction Set Description * CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Clear carry bit CLRC 0→C BIC #1,SR The carry bit (C) is cleared. The clear carry instruction is a word instruction. N: Not affected Z: Not affected C: Cleared V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12. CLRC DADD DADC @R13,0(R12) 2(R12) ; C=0: defines start ; add 16-bit counter to low word of 32-bit counter ; add carry to high word of 32-bit counter SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 243 Instruction Set Description 6.6.2.12 CLRN www.ti.com * CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example Clear negative bit CLRN 0→N or (.NOT.src .AND. dst → dst) BIC #4,SR The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction. N: Reset to 0 Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The negative bit in the SR is cleared. This avoids special treatment with negative numbers of the subroutine called. SUBR SUBRET CLRN CALL SUBR ...... ...... JN SUBRET ...... ...... ...... RET ; If input is negative: do nothing and return 244 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.13 CLRZ Instruction Set Description * CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Clear zero bit CLRZ 0→Z or (.NOT.src .AND. dst → dst) BIC #2,SR The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. N: Not affected Z: Reset to 0 C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The zero bit in the SR is cleared. CLRZ Indirect, Auto-Increment mode: Call a subroutine at the 16-bit address contained in the word pointed to by register R5 (20-bit address) and increment the 16-bit address in R5 afterwards by 2. The next time the software uses R5 as a pointer, it can alter the program execution due to access to the next word address in the table pointed to by R5. CALL @R5+ ; Start address at @R5. R5 + 2 Indexed mode: Call a subroutine at the 16-bit address contained in the 20-bit address pointed to by register (R5 + X); for example, a table with addresses starting at X. The address is within the lower 64KB. X is within ±32KB. CALL X(R5) ; Start address at @(R5+X). z16(R5) SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 245 Instruction Set Description 6.6.2.14 CMP www.ti.com CMP[.W] CMP.B Syntax Operation Emulation Description Status Bits Mode Bits Example Compare source word and destination word Compare source byte and destination byte CMP src,dst or CMP.W src,dst CMP.B src,dst (.not.src) + 1 + dst or dst – src BIC #2,SR The source operand is subtracted from the destination operand. This is made by adding the 1s complement of the source + 1 to the destination. The result affects only the status bits in SR. Register mode: the register bits Rdst.19:16 (.W) resp. Rdst. 19:8 (.B) are not cleared. N: Set if result is negative (src > dst), reset if positive (src = dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. Compare word EDE with a 16-bit constant 1800h. Jump to label TONI if EDE equals the constant. The address of EDE is within PC + 32 K. CMP #01800h,EDE ; Compare word EDE with 1800h JEQ TONI ; EDE contains 1800h ... ; Not equal Example A table word pointed to by (R5 + 10) is compared with R7. Jump to label TONI if R7 contains a lower, signed 16-bit number. R7.19:16 is not cleared. The address of the source operand is a 20-bit address in full memory range. CMP.W JL ... 10(R5),R7 TONI ; Compare two signed numbers ; R7 < 10(R5) ; R7 >= 10(R5) Example A table byte pointed to by R5 (20-bit address) is compared to the value in output Port1. Jump to label TONI if values are equal. The next table byte is addressed. CMP.B JEQ ... @R5+,&P1OUT TONI ; Compare P1 bits with table. R5 + 1 ; Equal contents ; Not equal 246 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.15 DADC Instruction Set Description * DADC[.W] * DADC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Add carry decimally to destination Add carry decimally to destination DADC dst or DADC.W dst DADC.B dst dst + C → dst (decimally) DADD #0,dst DADD.B #0,dst The carry bit (C) is added decimally to the destination. N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise C: Set if destination increments from 9999 to 0000, reset otherwise Set if destination increments from 99 to 00, reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The four-digit decimal number contained in R5 is added to an eight-digit decimal number pointed to by R8. CLRC DADD R5,0(R8) DADC 2(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSD Example The two-digit decimal number contained in R5 is added to a four-digit decimal number pointed to by R8. CLRC DADD.B R5,0(R8) DADC 1(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSDs SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 247 Instruction Set Description 6.6.2.16 DADD www.ti.com * DADD[.W] * DADD.B Syntax Operation Description Status Bits Mode Bits Example Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADD src,dst or DADD.W src,dst DADD.B src,dst src + dst + C → dst (decimally) The source operand and the destination operand are treated as two (.B) or four (.W) binary coded decimals (BCD) with positive signs. The source operand and the carry bit C are added decimally to the destination operand. The source operand is not affected. The previous content of the destination is lost. The result is not defined for non-BCD numbers. N: Set if MSB of result is 1 (word > 7999h, byte > 79h), reset if MSB is 0 Z: Set if result is zero, reset otherwise C: Set if the BCD result is too large (word > 9999h, byte > 99h), reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. Decimal 10 is added to the 16-bit BCD counter DECCNTR. DADD #10h,&DECCNTR ; Add 10 to 4-digit BCD counter Example The eight-digit BCD number contained in 16-bit RAM addresses BCD and BCD+2 is added decimally to an eight-digit BCD number contained in R4 and R5 (BCD+2 and R5 contain the MSDs). The carry C is added, and cleared. CLRC DADD.W DADD.W JC ... &BCD,R4 &BCD+2,R5 OVERFLOW ; Clear carry ; Add LSDs. R4.19:16 = 0 ; Add MSDs with carry. R5.19:16 = 0 ; Result >9999,9999: go to error routine ; Result ok Example The two-digit BCD number contained in word BCD (16-bit address) is added decimally to a two-digit BCD number contained in R4. The carry C is added, also. R4.19:8 = 0 CLRC DADD.B &BCD,R4 ; Clear carry ; Add BCD to R4 decimally. R4: 0,00ddh 248 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.17 DEC Instruction Set Description * DEC[.W] * DEC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Decrement destination Decrement destination DEC dst or DEC.W dst DEC.B dst dst – 1 → dst SUB #1,dst SUB.B #1,dst The destination operand is decremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08000h, otherwise reset. Set if initial value of destination was 080h, otherwise reset. OSCOFF, CPUOFF, and GIE are not affected. R10 is decremented by 1. DEC R10 ; Decrement R10 ; Move a block of 255 bytes from memory location starting with EDE to ; memory location starting with TONI. Tables should not overlap: start of ; destination address TONI must not be within the range EDE to EDE+0FEh MOV #EDE,R6 MOV #255,R10 L$1 MOV.B @R6+,TONI-EDE-1(R6) DEC R10 JNZ L$1 Do not transfer tables using the routine above with the overlap shown in Figure 6-36. EDE EDE+254 TONI TONI+254 Figure 6-36. Decrement Overlap SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 249 Instruction Set Description 6.6.2.18 DECD www.ti.com * DECD[.W] * DECD.B Syntax Operation Emulation Description Status Bits Mode Bits Example Double-decrement destination Double-decrement destination DECD dst or DECD.W dst DECD.B dst dst – 2 → dst SUB #2,dst SUB.B #2,dst The destination operand is decremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset Set if initial value of destination was 08001 or 08000h, otherwise reset Set if initial value of destination was 081 or 080h, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. R10 is decremented by 2. DECD R10 ; Decrement R10 by two ; Move a block of 255 bytes from memory location starting with EDE to ; memory location starting with TONI. ; Tables should not overlap: start of destination address TONI must not ; be within the range EDE to EDE+0FEh MOV #EDE,R6 MOV #255,R10 L$1 MOV.B @R6+,TONI-EDE-2(R6) DECD R10 JNZ L$1 Example Memory at location LEO is decremented by two. DECD.B LEO ; Decrement MEM(LEO) Decrement status byte STATUS by two DECD.B STATUS 250 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.19 DINT Instruction Set Description * DINT Syntax Operation Emulation Description Status Bits Mode Bits Example Disable (general) interrupts DINT 0 → GIE or (0FFF7h .AND. SR → SR / .NOT.src .AND. dst → dst) BIC #8,SR All interrupts are disabled. The constant 08h is inverted and logically ANDed with the SR. The result is placed into the SR. Status bits are not affected. GIE is reset. OSCOFF and CPUOFF are not affected. The general interrupt enable (GIE) bit in the SR is cleared to allow a nondisrupted move of a 32-bit counter. This ensures that the counter is not modified during the move by any interrupt. DINT NOP MOV MOV EINT COUNTHI,R5 COUNTLO,R6 ; All interrupt events using the GIE bit are disabled ; Required due to pipelined CPU architecture ; Copy counter ; All interrupt events using the GIE bit are enabled NOTE: Disable interrupt Due to the pipelined CPU architecture, clearing the general interrupt enable (GIE) requires special care. • Include at least one instruction between DINT and the start of an code sequence that requires protection from interrupts. For example: Insert a NOP instruction after the DINT. • Never clear the general interrupt enable (GIE) immediately after setting it. Insert at least one instruction in between such sequence. The rules above apply to all instructions that clear the general interrupt enable bit. Not following these rules might result in unexpected CPU execution. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 251 Instruction Set Description 6.6.2.20 EINT www.ti.com * EINT Syntax Operation Emulation Description Status Bits Mode Bits Example Enable (general) interrupts EINT 1 → GIE or (0008h .OR. SR → SR / .src .OR. dst → dst) BIS #8,SR All interrupts are enabled. The constant #08h and the SR are logically ORed. The result is placed into the SR. Status bits are not affected. GIE is set. OSCOFF and CPUOFF are not affected. The general interrupt enable (GIE) bit in the SR is set. MaskOK PUSH.B BIC.B NOP EINT &P1IN @SP,&P1IFG BIT #Mask,@SP JEQ MaskOK ...... BIC #Mask,@SP ...... INCD SP RETI ; Reset only accepted flags ; Required due to pipelined CPU architecture ; Preset port 1 interrupt flags stored on stack ; other interrupts are allowed ; Flags are present identically to mask: jump ; Housekeeping: inverse to PUSH instruction ; at the start of interrupt subroutine. Corrects ; the stack pointer. NOTE: Enable interrupt Due to the pipelined CPU architecture, setting the general interrupt enable (GIE) requires special care. • The instruction immediately after the enable interrupts instruction (EINT) is always executed, even if an interrupt service request is pending. • Include at least one instruction between the clear of an interrupt enable or interrupt flag and the EINT instruction. For example: Insert a NOP instruction in front of the EINT instruction. • Never clear the general interrupt enable (GIE) immediately after setting it. Insert at least one instruction in between such sequence. The rules above apply to all instructions that set the general interrupt enable bit. Not following these rules might result in unexpected CPU execution. 252 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.21 INC Instruction Set Description * INC[.W] * INC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Increment destination Increment destination INC dst or INC.W dst INC.B dst dst + 1 → dst ADD #1,dst The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The status byte, STATUS, of a process is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B CMP.B JEQ STATUS #11,STATUS OVFL SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 253 Instruction Set Description 6.6.2.22 INCD www.ti.com * INCD[.W] * INCD.B Syntax Operation Emulation Description Status Bits Mode Bits Example Double-increment destination Double-increment destination INCD dst or INCD.W dst INCD.B dst dst + 2 → dst ADD #2,dst The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The item on the top of the stack (TOS) is removed without using a register. ....... PUSH R5 INCD SP RET ; R5 is the result of a calculation, which is stored ; in the system stack ; Remove TOS by double-increment from stack ; Do not use INCD.B, SP is a word-aligned register Example The byte on the top of the stack is incremented by two. INCD.B 0(SP) ; Byte on TOS is increment by two 254 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.23 INV Instruction Set Description * INV[.W] * INV.B Syntax Operation Emulation Description Status Bits Mode Bits Example Invert destination Invert destination INV dst or INV.W dst INV.B dst .not.dst → dst XOR #0FFFFh,dst XOR.B #0FFh,dst The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. Content of R5 is negated (twos complement). MOV #00AEh,R5 ; R5 = 000AEh INV R5 ; Invert R5, R5 = 0FF51h INC R5 ; R5 is now negated, R5 = 0FF52h Example Content of memory byte LEO is negated. MOV.B INV.B INC.B #0AEh,LEO LEO LEO ; MEM(LEO) = 0AEh ; Invert LEO, MEM(LEO) = 051h ; MEM(LEO) is negated, MEM(LEO) = 052h SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 255 Instruction Set Description 6.6.2.24 JC, JHS www.ti.com JC JHS Syntax Operation Description Status Bits Mode Bits Example Jump if carry Jump if higher or same (unsigned) JC label JHS label If C = 1: PC + (2 × Offset) → PC If C = 0: execute the following instruction The carry bit C in the SR is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range. If C is reset, the instruction after the jump is executed. JC is used for the test of the carry bit C. JHS is used for the comparison of unsigned numbers. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected. The state of the port 1 pin P1IN.1 bit defines the program flow. BIT.B JC ... #2,&P1IN Label1 ; Port 1, bit 1 set? Bit -> C ; Yes, proceed at Label1 ; No, continue Example If R5 ≥ R6 (unsigned), the program continues at Label2. CMP R6,R 5 JHS Label2 ... ; Is R5 >= R6? Info to C ; Yes, C = 1 ; No, R5 < R6. Continue Example If R5 ≥ 12345h (unsigned operands), the program continues at Label2. CMPA JHS ... #12345h,R5 Label2 ; Is R5 >= 12345h? Info to C ; Yes, 12344h < R5 <= F,FFFFh. C = 1 ; No, R5 < 12345h. Continue 256 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.25 JEQ, JZ Instruction Set Description JEQ JZ Syntax Operation Description Status Bits Mode Bits Example Jump if equal Jump if zero JEQ label JZ label If Z = 1: PC + (2 × Offset) → PC If Z = 0: execute following instruction The zero bit Z in the SR is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range. If Z is reset, the instruction after the jump is executed. JZ is used for the test of the zero bit Z. JEQ is used for the comparison of operands. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected. The state of the P2IN.0 bit defines the program flow. BIT.B JZ ... #1,&P2IN Label1 ; Port 2, bit 0 reset? ; Yes, proceed at Label1 ; No, set, continue Example If R5 = 15000h (20-bit data), the program continues at Label2. CMPA JEQ ... #15000h,R5 Label2 ; Is R5 = 15000h? Info to SR ; Yes, R5 = 15000h. Z = 1 ; No, R5 not equal 15000h. Continue Example R7 (20-bit counter) is incremented. If its content is zero, the program continues at Label4. ADDA JZ ... #1,R7 Label4 ; Increment R7 ; Zero reached: Go to Label4 ; R7 not equal 0. Continue here. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 257 Instruction Set Description 6.6.2.26 JGE www.ti.com JGE Syntax Operation Description Status Bits Mode Bits Example Jump if greater or equal (signed) JGE label If (N .xor. V) = 0: PC + (2 × Offset) → PC If (N .xor. V) = 1: execute following instruction The negative bit N and the overflow bit V in the SR are tested. If both bits are set or both are reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range -511 to +512 words relative to the PC in full Memory range. If only one bit is set, the instruction after the jump is executed. JGE is used for the comparison of signed operands: also for incorrect results due to overflow, the decision made by the JGE instruction is correct. Note that JGE emulates the nonimplemented JP (jump if positive) instruction if used after the instructions AND, BIT, RRA, SXTX, and TST. These instructions clear the V bit. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. If byte EDE (lower 64 K) contains positive data, go to Label1. Software can run in the full memory range. TST.B JGE ... &EDE Label1 ; Is EDE positive? V <- 0 ; Yes, JGE emulates JP ; No, 80h <= EDE <= FFh Example If the content of R6 is greater than or equal to the memory pointed to by R7, the program continues a Label5. Signed data. Data and program in full memory range. CMP @R7,R6 JGE Label5 ... ; Is R6 >= @R7? ; Yes, go to Label5 ; No, continue here Example If R5 ≥ 12345h (signed operands), the program continues at Label2. Program in full memory range. CMPA JGE ... #12345h,R5 Label2 ; Is R5 >= 12345h? ; Yes, 12344h < R5 <= 7FFFFh ; No, 80000h <= R5 < 12345h 258 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.27 JL Instruction Set Description JL Syntax Operation Description Status Bits Mode Bits Example Jump if less (signed) JL label If (N .xor. V) = 1: PC + (2 × Offset) → PC If (N .xor. V) = 0: execute following instruction The negative bit N and the overflow bit V in the SR are tested. If only one is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in full memory range. If both bits N and V are set or both are reset, the instruction after the jump is executed. JL is used for the comparison of signed operands: also for incorrect results due to overflow, the decision made by the JL instruction is correct. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. If byte EDE contains a smaller, signed operand than byte TONI, continue at Label1. The address EDE is within PC ± 32 K. CMP.B JL ... &TONI,EDE Label1 ; Is EDE < TONI ; Yes ; No, TONI <= EDE Example If the signed content of R6 is less than the memory pointed to by R7 (20-bit address), the program continues at Label5. Data and program in full memory range. CMP @R7,R6 JL Label5 ... ; Is R6 < @R7? ; Yes, go to Label5 ; No, continue here Example If R5 < 12345h (signed operands), the program continues at Label2. Data and program in full memory range. CMPA JL ... #12345h,R5 Label2 ; Is R5 < 12345h? ; Yes, 80000h =< R5 < 12345h ; No, 12344h < R5 <= 7FFFFh SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 259 Instruction Set Description 6.6.2.28 JMP www.ti.com JMP Syntax Operation Description Status Bits Mode Bits Example Jump unconditionally JMP label PC + (2 × Offset) → PC The signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means an unconditional jump in the range –511 to +512 words relative to the PC in the full memory. The JMP instruction may be used as a BR or BRA instruction within its limited range relative to the PC. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected. The byte STATUS is set to 10. Then a jump to label MAINLOOP is made. Data in lower 64 K, program in full memory range. MOV.B #10,&STATUS JMP MAINLOOP ; Set STATUS to 10 ; Go to main loop Example The interrupt vector TAIV of Timer_A3 is read and used for the program flow. Program in full memory range, but interrupt handlers always starts in lower 64 K. ADD RETI JMP JMP RETI &TAIV,PC IHCCR1 IHCCR2 ; Add Timer_A interrupt vector to PC ; No Timer_A interrupt pending ; Timer block 1 caused interrupt ; Timer block 2 caused interrupt ; No legal interrupt, return 260 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.29 JN Instruction Set Description JN Syntax Operation Description Status Bits Mode Bits Example Jump if negative JN label If N = 1: PC + (2 × Offset) → PC If N = 0: execute following instruction The negative bit N in the SR is tested. If it is set, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit program PC. This means a jump in the range -511 to +512 words relative to the PC in the full memory range. If N is reset, the instruction after the jump is executed. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The byte COUNT is tested. If it is negative, program execution continues at Label0. Data in lower 64 K, program in full memory range. TST.B JN ... &COUNT Label0 ; Is byte COUNT negative? ; Yes, proceed at Label0 ; COUNT >= 0 Example R6 is subtracted from R5. If the result is negative, program continues at Label2. Program in full memory range. SUB R6,R5 ; R5 - R6 -> R5 JN Label2 ; R5 is negative: R6 > R5 (N = 1) ... ; R5 >= 0. Continue here. Example R7 (20-bit counter) is decremented. If its content is below zero, the program continues at Label4. Program in full memory range. SUBA JN ... #1,R7 Label4 ; Decrement R7 ; R7 < 0: Go to Label4 ; R7 >= 0. Continue here. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 261 Instruction Set Description 6.6.2.30 JNC, JLO www.ti.com JNC JLO Syntax Operation Description Status Bits Mode Bits Example Jump if no carry Jump if lower (unsigned) JNC label JLO label If C = 0: PC + (2 × Offset) → PC If C = 1: execute following instruction The carry bit C in the SR is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range. If C is set, the instruction after the jump is executed. JNC is used for the test of the carry bit C. JLO is used for the comparison of unsigned numbers. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. If byte EDE < 15, the program continues at Label2. Unsigned data. Data in lower 64 K, program in full memory range. CMP.B JLO ... #15,&EDE Label2 ; Is EDE < 15? Info to C ; Yes, EDE < 15. C = 0 ; No, EDE >= 15. Continue Example The word TONI is added to R5. If no carry occurs, continue at Label0. The address of TONI is within PC ± 32 K. ADD TONI,R5 JNC Label0 ... ; TONI + R5 -> R5. Carry -> C ; No carry ; Carry = 1: continue here 262 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.31 JNZ, JNE Instruction Set Description JNZ JNE Syntax Operation Description Status Bits Mode Bits Example Jump if not zero Jump if not equal JNZ label JNE label If Z = 0: PC + (2 × Offset) → PC If Z = 1: execute following instruction The zero bit Z in the SR is tested. If it is reset, the signed 10-bit word offset contained in the instruction is multiplied by two, sign extended, and added to the 20-bit PC. This means a jump in the range –511 to +512 words relative to the PC in the full memory range. If Z is set, the instruction after the jump is executed. JNZ is used for the test of the zero bit Z. JNE is used for the comparison of operands. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. The byte STATUS is tested. If it is not zero, the program continues at Label3. The address of STATUS is within PC ± 32 K. TST.B JNZ ... STATUS Label3 ; Is STATUS = 0? ; No, proceed at Label3 ; Yes, continue here Example If word EDE ≠ 1500, the program continues at Label2. Data in lower 64 K, program in full memory range. CMP #1500,&EDE ; Is EDE = 1500? Info to SR JNE Label2 ; No, EDE not equal 1500. ... ; Yes, R5 = 1500. Continue Example R7 (20-bit counter) is decremented. If its content is not zero, the program continues at Label4. Program in full memory range. SUBA JNZ ... #1,R7 Label4 ; Decrement R7 ; Zero not reached: Go to Label4 ; Yes, R7 = 0. Continue here. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 263 Instruction Set Description 6.6.2.32 MOV www.ti.com MOV[.W] MOV.B Syntax Operation Description Status Bits Mode Bits Example Move source word to destination word Move source byte to destination byte MOV src,dst or MOV.W src,dst MOV.B src,dst src → dst The source operand is copied to the destination. The source operand is not affected. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Move a 16-bit constant 1800h to absolute address-word EDE (lower 64 K) MOV #01800h,&EDE ; Move 1800h to EDE Example The contents of table EDE (word data, 16-bit addresses) are copied to table TOM. The length of the tables is 030h words. Both tables reside in the lower 64 K. MOV Loop MOV CMP JLO ... #EDE,R10 @R10+,TOM-EDE-2(R10) #EDE+60h,R10 Loop ; Prepare pointer (16-bit address) ; R10 points to both tables. ; R10+2 ; End of table reached? ; Not yet ; Copy completed Example The contents of table EDE (byte data, 16-bit addresses) are copied to table TOM. The length of the tables is 020h bytes. Both tables may reside in full memory range, but must be within R10 ± 32 K. Loop MOVA MOV MOV.B DEC JNZ ... #EDE,R10 #20h,R9 @R10+,TOM-EDE-1(R10) R9 Loop ; Prepare pointer (20-bit) ; Prepare counter ; R10 points to both tables. ; R10+1 ; Decrement counter ; Not yet done ; Copy completed 264 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.33 NOP Instruction Set Description * NOP Syntax Operation Emulation Description Status Bits No operation NOP None MOV #0, R3 No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status bits are not affected. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 265 Instruction Set Description 6.6.2.34 POP www.ti.com * POP[.W] * POP.B Syntax Operation Emulation Description Status Bits Example Pop word from stack to destination Pop byte from stack to destination POP dst POP.B dst @SP → temp SP + 2 → SP temp → dst MOV @SP+,dst or MOV.W @SP+,dst MOV.B @SP+,dst The stack location pointed to by the SP (TOS) is moved to the destination. The SP is incremented by two afterwards. Status bits are not affected. The contents of R7 and the SR are restored from the stack. POP R7 POP SR ; Restore R7 ; Restore status register Example The contents of RAM byte LEO is restored from the stack. POP.B LEO ; The low byte of the stack is moved to LEO. Example The contents of R7 is restored from the stack. POP.B R7 ; The low byte of the stack is moved to R7, ; the high byte of R7 is 00h Example The contents of the memory pointed to by R7 and the SR are restored from the stack. POP.B POP 0(R7) SR ; The low byte of the stack is moved to the ; the byte which is pointed to by R7 : Example: R7 = 203h ; Mem(R7) = low byte of system stack : Example: R7 = 20Ah ; Mem(R7) = low byte of system stack ; Last word on stack moved to the SR NOTE: System stack pointer The system SP is always incremented by two, independent of the byte suffix. 266 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.35 PUSH Instruction Set Description PUSH[.W] PUSH.B Syntax Operation Description Status Bits Mode Bits Example Save a word on the stack Save a byte on the stack PUSH dst or PUSH.W dst PUSH.B dst SP – 2 → SP dst → @SP The 20-bit SP SP is decremented by two. The operand is then copied to the RAM word addressed by the SP. A pushed byte is stored in the low byte; the high byte is not affected. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Save the two 16-bit registers R9 and R10 on the stack PUSH R9 PUSH R10 ; Save R9 and R10 XXXXh ; YYYYh Example Save the two bytes EDE and TONI on the stack. The addresses EDE and TONI are within PC ± 32 K. PUSH.B EDE PUSH.B TONI ; Save EDE xxXXh ; Save TONI xxYYh SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 267 Instruction Set Description 6.6.2.36 RET www.ti.com * RET Syntax Operation Description Status Bits Mode Bits Example Return from subroutine RET @SP →PC.15:0 Saved PC to PC.15:0. PC.19:16 ← 0 SP + 2 → SP The 16-bit return address (lower 64 K), pushed onto the stack by a CALL instruction is restored to the PC. The program continues at the address following the subroutine call. The four MSBs of the PC.19:16 are cleared. Status bits are not affected. PC.19:16: Cleared OSCOFF, CPUOFF, and GIE are not affected. Call a subroutine SUBR in the lower 64 K and return to the address in the lower 64 K after the CALL. SUBR CALL ... PUSH ... POP RET #SUBR R14 R14 ; Call subroutine starting at SUBR ; Return by RET to here ; Save R14 (16 bit data) ; Subroutine code ; Restore R14 ; Return to lower 64 K Item n SP PC Return SP Item n Stack before RET instruction Stack after RET instruction Figure 6-37. Stack After a RET Instruction 268 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.37 RETI Instruction Set Description RETI Syntax Operation Description Status Bits Mode Bits Example Return from interrupt RETI @SP → SR.15:0 Restore saved SR with PC.19:16 SP + 2 → SP @SP → PC.15:0 Restore saved PC.15:0 SP + 2 → SP Housekeeping The SR is restored to the value at the beginning of the interrupt service routine. This includes the four MSBs of the PC.19:16. The SP is incremented by two afterward. The 20-bit PC is restored from PC.19:16 (from same stack location as the status bits) and PC.15:0. The 20-bit PC is restored to the value at the beginning of the interrupt service routine. The program continues at the address following the last executed instruction when the interrupt was granted. The SP is incremented by two afterward. No interrupt flags are modified by this command. N: Restored from stack C: Restored from stack Z: Restored from stack V: Restored from stack OSCOFF, CPUOFF, and GIE are restored from stack. Interrupt handler in the lower 64 K. A 20-bit return address is stored on the stack. INTRPT PUSHM.A ... POPM.A RETI #2,R14 #2,R14 ; Save R14 and R13 (20-bit data) ; Interrupt handler code ; Restore R13 and R14 (20-bit data) ; Return to 20-bit address in full memory range SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 269 Instruction Set Description 6.6.2.38 RLA www.ti.com * RLA[.W] * RLA.B Syntax Operation Emulation Description Status Bits Mode Bits Example Rotate left arithmetically Rotate left arithmetically RLA dst or RLA.W dst RLA.B dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 ADD dst,dst ADD.B dst,dst The destination operand is shifted left one position as shown in Figure 6-38. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2. An overflow occurs if dst ≥ 04000h and dst < 0C000h before operation is performed; the result has changed sign. Word 15 0 C 0 Byte 7 0 Figure 6-38. Destination Operand—Arithmetic Shift Left An overflow occurs if dst ≥ 040h and dst < 0C0h before the operation is performed; the result has changed sign. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs; the initial value is 04000h ≤ dst < 0C000h, reset otherwise Set if an arithmetic overflow occurs; the initial value is 040h ≤ dst < 0C0h, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R7 is multiplied by 2. RLA R7 ; Shift left R7 (x 2) Example The low byte of R7 is multiplied by 4. RLA.B R7 RLA.B R7 ; Shift left low byte of R7 (x 2) ; Shift left low byte of R7 (x 4) NOTE: RLA substitution The assembler does not recognize the instructions: RLA @R5+ RLA.B @R5+ They must be substituted by: ADD @R5+,-2(R5) ADD.B @R5+,-1(R5) RLA(.B) @R5 ADD(.B) @R5 270 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.39 RLC Instruction Set Description * RLC[.W] * RLC.B Syntax Operation Emulation Description Rotate left through carry Rotate left through carry RLC dst or RLC.W dst RLC.B dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← C ADDC dst,dst The destination operand is shifted left one position as shown in Figure 6-39. The carry bit (C) is shifted into the LSB, and the MSB is shifted into the carry bit (C). Word 15 0 C Byte 7 0 Figure 6-39. Destination Operand—Carry Left Shift Status Bits Mode Bits Example N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs; the initial value is 04000h ≤ dst < 0C000h, reset otherwise Set if an arithmetic overflow occurs; the initial value is 040h ≤ dst < 0C0h, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R5 is shifted left one position. RLC R5 ; (R5 x 2) + C -> R5 Example The input P1IN.1 information is shifted into the LSB of R5. BIT.B #2,&P1IN RLC R5 ; Information -> Carry ; Carry=P0in.1 -> LSB of R5 Example The MEM(LEO) content is shifted left one position. RLC.B LEO ; Mem(LEO) x 2 + C -> Mem(LEO) NOTE: RLA substitution The assembler does not recognize the instructions: RLC @R5+ RLC.B @R5+ They must be substituted by: ADDC @R5+,-2(R5) ADDC.B @R5+,-1(R5) RLC(.B) @R5 ADDC(.B) @R5 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 271 Instruction Set Description 6.6.2.40 RRA www.ti.com RRA[.W] RRA.B Syntax Operation Description Status Bits Mode Bits Example Rotate right arithmetically destination word Rotate right arithmetically destination byte RRA.B dst or RRA.W dst MSB → MSB → MSB–1 → ... LSB+1 → LSB → C The destination operand is shifted right arithmetically by one bit position as shown in Figure 6-40. The MSB retains its value (sign). RRA operates equal to a signed division by 2. The MSB is retained and shifted into the MSB–1. The LSB+1 is shifted into the LSB. The previous LSB is shifted into the carry bit C. N: Set if result is negative (MSB = 1), reset otherwise (MSB = 0) Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 16-bit number in R5 is shifted arithmetically right one position. RRA R5 ; R5/2 -> R5 Example The signed RAM byte EDE is shifted arithmetically right one position. RRA.B EDE ; EDE/2 -> EDE 19 15 7 0 C 0 0 0 0 0 0 0 0 0 0 0 0 MSB LSB 19 15 C 0 0 0 0 MSB 0 LSB Figure 6-40. Rotate Right Arithmetically RRA.B and RRA.W 272 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.41 RRC Instruction Set Description RRC[.W] RRC.B Syntax Operation Description Status Bits Mode Bits Example Rotate right through carry destination word Rotate right through carry destination byte RRC dst or RRC.W dst RRC.B dst C → MSB → MSB–1 → ... LSB+1 → LSB → C The destination operand is shifted right by one bit position as shown in Figure 6-41. The carry bit C is shifted into the MSB and the LSB is shifted into the carry bit C. N: Set if result is negative (MSB = 1), reset otherwise (MSB = 0) Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. RAM word EDE is shifted right one bit position. The MSB is loaded with 1. SETC RRC EDE ; Prepare carry for MSB ; EDE = EDE >> 1 + 8000h 19 15 7 0 C 0 0 0 0 0 0 0 0 0 0 0 0 MSB LSB 19 15 C 0 0 0 0 MSB 0 LSB Figure 6-41. Rotate Right Through Carry RRC.B and RRC.W SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 273 Instruction Set Description 6.6.2.42 SBC www.ti.com * SBC[.W] * SBC.B Syntax Operation Emulation Description Status Bits Mode Bits Example Subtract borrow (.NOT. carry) from destination Subtract borrow (.NOT. carry) from destination SBC dst or SBC.W dst SBC.B dst dst + 0FFFFh + C → dst dst + 0FFh + C → dst SUBC #0,dst SUBC.B #0,dst The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise Set to 1 if no borrow, reset if borrow V: Set if an arithmetic overflow occurs, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 16-bit counter pointed to by R13 is subtracted from a 32-bit counter pointed to by R12. SUB @R13,0(R12) ; Subtract LSDs SBC 2(R12) ; Subtract carry from MSD Example The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUB.B @R13,0(R12) SBC.B 1(R12) ; Subtract LSDs ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Yes No Carry Bit 0 1 274 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.43 SETC Instruction Set Description * SETC Syntax Operation Emulation Description Status Bits Mode Bits Example Set carry bit SETC 1→C BIS #1,SR The carry bit (C) is set. N: Not affected Z: Not affected C: Set V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Emulation of the decimal subtraction: Subtract R5 from R6 decimally. Assume that R5 = 03987h and R6 = 04137h. DSUB ADD #06666h,R5 INV R5 SETC DADD R5,R6 ; Move content R5 from 0-9 to 6-0Fh ; R5 = 03987h + 06666h = 09FEDh ; Invert this (result back to 0-9) ; R5 = .NOT. R5 = 06012h ; Prepare carry = 1 ; Emulate subtraction by addition of: ; (010000h - R5 - 1) ; R6 = R6 + R5 + 1 ; R6 = 0150h SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 275 Instruction Set Description 6.6.2.44 SETN * SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1→N BIS #4,SR The negative bit (N) is set. N: Set Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. www.ti.com 276 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.45 SETZ * SETZ Syntax Operation Emulation Description Status Bits Mode Bits Set zero bit SETZ 1→N BIS #2,SR The zero bit (Z) is set. N: Not affected Z: Set C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Instruction Set Description SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 277 Instruction Set Description 6.6.2.46 SUB www.ti.com SUB[.W] SUB.B Syntax Operation Description Status Bits Mode Bits Example Subtract source word from destination word Subtract source byte from destination byte SUB src,dst or SUB.W src,dst SUB.B src,dst (.not.src) + 1 + dst → dst or dst – src → dst The source operand is subtracted from the destination operand. This is made by adding the 1s complement of the source + 1 to the destination. The source operand is not affected, the result is written to the destination operand. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. A 16-bit constant 7654h is subtracted from RAM word EDE. SUB #7654h,&EDE ; Subtract 7654h from EDE Example A table word pointed to by R5 (20-bit address) is subtracted from R7. Afterwards, if R7 contains zero, jump to label TONI. R5 is then auto-incremented by 2. R7.19:16 = 0. SUB @R5+,R7 JZ TONI ... ; Subtract table number from R7. R5 + 2 ; R7 = @R5 (before subtraction) ; R7 <> @R5 (before subtraction) Example Byte CNT is subtracted from byte R12 points to. The address of CNT is within PC ± 32K. The address R12 points to is in full memory range. SUB.B CNT,0(R12) ; Subtract CNT from @R12 278 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.47 SUBC Instruction Set Description SUBC[.W] SUBC.B Syntax Operation Description Status Bits Mode Bits Example Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBC src,dst or SUBC.W src,dst SUBC.B src,dst (.not.src) + C + dst → dst or dst – (src – 1) + C → dst The source operand is subtracted from the destination operand. This is done by adding the 1s complement of the source + carry to the destination. The source operand is not affected, the result is written to the destination operand. Used for 32, 48, and 64-bit operands. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. A 16-bit constant 7654h is subtracted from R5 with the carry from the previous instruction. R5.19:16 = 0 SUBC.W #7654h,R5 ; Subtract 7654h + C from R5 Example A 48-bit number (3 words) pointed to by R5 (20-bit address) is subtracted from a 48-bit counter in RAM, pointed to by R7. R5 points to the next 48-bit number afterwards. The address R7 points to is in full memory range. SUB SUBC SUBC @R5+,0(R7) @R5+,2(R7) @R5+,4(R7) ; Subtract LSBs. R5 + 2 ; Subtract MIDs with C. R5 + 2 ; Subtract MSBs with C. R5 + 2 Example Byte CNT is subtracted from the byte, R12 points to. The carry of the previous instruction is used. The address of CNT is in lower 64 K. SUBC.B &CNT,0(R12) ; Subtract byte CNT from @R12 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 279 Instruction Set Description 6.6.2.48 SWPB www.ti.com SWPB Syntax Operation Description Status Bits Mode Bits Example Swap bytes SWPB dst dst.15:8 ↔ dst.7:0 The high and the low byte of the operand are exchanged. PC.19:16 bits are cleared in register mode. Status bits are not affected OSCOFF, CPUOFF, and GIE are not affected. Exchange the bytes of RAM word EDE (lower 64 K) MOV #1234h,&EDE SWPB &EDE ; 1234h -> EDE ; 3412h -> EDE Before SWPB 15 87 0 High Byte Low Byte After SWPB 15 Low Byte 87 0 High Byte Figure 6-42. Swap Bytes in Memory Before SWPB 19 16 15 87 0 x High Byte Low Byte After SWPB 19 16 15 87 0 0 ... 0 Low Byte High Byte Figure 6-43. Swap Bytes in a Register 280 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.49 SXT Instruction Set Description SXT Syntax Operation Description Status Bits Mode Bits Example Extend sign SXT dst dst.7 → dst.15:8, dst.7 → dst.19:8 (register mode) Register mode: the sign of the low byte of the operand is extended into the bits Rdst.19:8. Rdst.7 = 0: Rdst.19:8 = 000h afterwards Rdst.7 = 1: Rdst.19:8 = FFFh afterwards Other modes: the sign of the low byte of the operand is extended into the high byte. dst.7 = 0: high byte = 00h afterwards dst.7 = 1: high byte = FFh afterwards N: Set if result is negative, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (C = .not.Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 8-bit data in EDE (lower 64 K) is sign extended and added to the 16-bit signed data in R7. MOV.B SXT ADD &EDE,R5 R5 R5,R7 ; EDE -> R5. 00XXh ; Sign extend low byte to R5.19:8 ; Add signed 16-bit values Example The signed 8-bit data in EDE (PC +32 K) is sign extended and added to the 20-bit data in R7. MOV.B SXT ADDA EDE,R5 R5 R5,R7 ; EDE -> R5. 00XXh ; Sign extend low byte to R5.19:8 ; Add signed 20-bit values SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 281 Instruction Set Description 6.6.2.50 TST www.ti.com * TST[.W] * TST.B Syntax Operation Emulation Description Status Bits Mode Bits Example Test destination Test destination TST dst or TST.W dst TST.B dst dst + 0FFFFh + 1 dst + 0FFh + 1 CMP #0,dst CMP.B #0,dst The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TST JN JZ ...... ...... ...... R7 R7NEG R7ZERO ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero Example The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TST.B JN JZ ...... ..... ...... R7 R7NEG R7ZERO ; Test low byte of R7 ; Low byte of R7 is negative ; Low byte of R7 is zero ; Low byte of R7 is positive but not zero ; Low byte of R7 is negative ; Low byte of R7 is zero 282 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.2.51 XOR Instruction Set Description XOR[.W] XOR.B Syntax Operation Description Status Bits Mode Bits Example Exclusive OR source word with destination word Exclusive OR source byte with destination byte XOR src,dst or XOR.W src,dst XOR.B src,dst src .xor. dst → dst The source and destination operands are exclusively ORed. The result is placed into the destination. The source operand is not affected. The previous content of the destination is lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (C = .not. Z) V: Set if both operands are negative before execution, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Toggle bits in word CNTR (16-bit data) with information (bit = 1) in address-word TONI. Both operands are located in lower 64 K. XOR &TONI,&CNTR ; Toggle bits in CNTR Example A table word pointed to by R5 (20-bit address) is used to toggle bits in R6. R6.19:16 = 0. XOR @R5,R6 ; Toggle bits in R6 Example Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE. R7.19:8 = 0. The address of EDE is within PC ± 32 K. XOR.B EDE,R7 INV.B R7 ; Set different bits to 1 in R7. ; Invert low byte of R7, high byte is 0h SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 283 Instruction Set Description www.ti.com 6.6.3 Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20-bit address space. MSP430X instructions require an additional word of op-code called the extension word. All addresses, indexes, and immediate numbers have 20-bit values when preceded by the extension word. The MSP430X extended instructions are listed and described in the following pages. 284 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.1 ADCX Instruction Set Description * ADCX.A * ADCX.[W] * ADCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Add carry to destination address-word Add carry to destination word Add carry to destination byte ADCX.A dst ADCX dst or ADCX.W dst ADCX.B dst dst + C → dst ADDCX.A #0,dst ADDCX #0,dst ADDCX.B #0,dst The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 40-bit counter, pointed to by R12 and R13, is incremented. INCX.A @R12 ADCX.A @R13 ; Increment lower 20 bits ; Add carry to upper 20 bits SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 285 Instruction Set Description 6.6.3.2 ADDX www.ti.com ADDX.A ADDX.[W] ADDX.B Syntax Operation Description Status Bits Mode Bits Example Add source address-word to destination address-word Add source word to destination word Add source byte to destination byte ADDX.A src,dst ADDX src,dst or ADDX.W src,dst ADDX.B src,dst src + dst → dst The source operand is added to the destination operand. The previous contents of the destination are lost. Both operands can be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Ten is added to the 20-bit pointer CNTR located in two words CNTR (LSBs) and CNTR+2 (MSBs). ADDX.A #10,CNTR ; Add 10 to 20-bit pointer Example A table word (16-bit) pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is performed on a carry. ADDX.W JC ... @R5,R6 TONI ; Add table word to R6 ; Jump if carry ; No carry Example A table byte pointed to by R5 (20-bit address) is added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. ADDX.B JNC ... @R5+,R6 TONI ; Add table byte to R6. R5 + 1. R6: 000xxh ; Jump if no carry ; Carry occurred Note: Use ADDA for the following two cases for better code density and execution. ADDX.A Rsrc,Rdst ADDX.A #imm20,Rdst 286 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.3 ADDCX Instruction Set Description ADDCX.A ADDCX.[W] ADDCX.B Syntax Operation Description Status Bits Mode Bits Example Add source address-word and carry to destination address-word Add source word and carry to destination word Add source byte and carry to destination byte ADDCX.A src,dst ADDCX src,dst or ADDCX.W src,dst ADDCX.B src,dst src + dst + C → dst The source operand and the carry bit C are added to the destination operand. The previous contents of the destination are lost. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Constant 15 and the carry of the previous instruction are added to the 20-bit counter CNTR located in two words. ADDCX.A #15,&CNTR ; Add 15 + C to 20-bit CNTR Example A table word pointed to by R5 (20-bit address) and the carry C are added to R6. The jump to label TONI is performed on a carry. ADDCX.W JC ... @R5,R6 TONI ; Add table word + C to R6 ; Jump if carry ; No carry Example A table byte pointed to by R5 (20-bit address) and the carry bit C are added to R6. The jump to label TONI is performed if no carry occurs. The table pointer is auto-incremented by 1. ADDCX.B JNC ... @R5+,R6 TONI ; Add table byte + C to R6. R5 + 1 ; Jump if no carry ; Carry occurred SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 287 Instruction Set Description 6.6.3.4 ANDX www.ti.com ANDX.A ANDX.[W] ANDX.B Syntax Operation Description Status Bits Mode Bits Example Logical AND of source address-word with destination address-word Logical AND of source word with destination word Logical AND of source byte with destination byte ANDX.A src,dst ANDX src,dst or ANDX.W src,dst ANDX.B src,dst src .and. dst → dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The bits set in R5 (20-bit data) are used as a mask (AAA55h) for the address-word TOM located in two words. If the result is zero, a branch is taken to label TONI. MOVA ANDX.A JZ ... #AAA55h,R5 R5,TOM TONI ; Load 20-bit mask to R5 ; TOM .and. R5 -> TOM ; Jump if result 0 ; Result > 0 or shorter: ANDX.A #AAA55h,TOM JZ TONI ; TOM .and. AAA55h -> TOM ; Jump if result 0 Example A table byte pointed to by R5 (20-bit address) is logically ANDed with R6. R6.19:8 = 0. The table pointer is auto-incremented by 1. ANDX.B @R5+,R6 ; AND table byte with R6. R5 + 1 288 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.5 BICX Instruction Set Description BICX.A BICX.[W] BICX.B Syntax Operation Description Status Bits Mode Bits Example Clear bits set in source address-word in destination address-word Clear bits set in source word in destination word Clear bits set in source byte in destination byte BICX.A src,dst BICX src,dst or BICX.W src,dst BICX.B src,dst (.not. src) .and. dst → dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. Both operands may be located in the full address space. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. The bits 19:15 of R5 (20-bit data) are cleared. BICX.A #0F8000h,R5 ; Clear R5.19:15 bits Example A table word pointed to by R5 (20-bit address) is used to clear bits in R7. R7.19:16 = 0. BICX.W @R5,R7 ; Clear bits in R7 Example A table byte pointed to by R5 (20-bit address) is used to clear bits in output Port1. BICX.B @R5,&P1OUT ; Clear I/O port P1 bits SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 289 Instruction Set Description 6.6.3.6 BISX www.ti.com BISX.A BISX.[W] BISX.B Syntax Operation Description Status Bits Mode Bits Example Set bits set in source address-word in destination address-word Set bits set in source word in destination word Set bits set in source byte in destination byte BISX.A src,dst BISX src,dst or BISX.W src,dst BISX.B src,dst src .or. dst → dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. Both operands may be located in the full address space. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Bits 16 and 15 of R5 (20-bit data) are set to one. BISX.A #018000h,R5 ; Set R5.16:15 bits Example A table word pointed to by R5 (20-bit address) is used to set bits in R7. BISX.W @R5,R7 ; Set bits in R7 Example A table byte pointed to by R5 (20-bit address) is used to set bits in output Port1. BISX.B @R5,&P1OUT ; Set I/O port P1 bits 290 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.7 BITX Instruction Set Description BITX.A BITX.[W] BITX.B Syntax Operation Description Status Bits Mode Bits Example Test bits set in source address-word in destination address-word Test bits set in source word in destination word Test bits set in source byte in destination byte BITX.A src,dst BITX src,dst or BITX.W src,dst BITX.B src,dst src .and. dst → dst The source operand and the destination operand are logically ANDed. The result affects only the status bits. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if the result is not zero, reset otherwise. C = (.not. Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. Test if bit 16 or 15 of R5 (20-bit data) is set. Jump to label TONI if so. BITX.A JNZ ... #018000h,R5 TONI ; Test R5.16:15 bits ; At least one bit is set ; Both are reset Example A table word pointed to by R5 (20-bit address) is used to test bits in R7. Jump to label TONI if at least one bit is set. BITX.W JC ... @R5,R7 TONI ; Test bits in R7: C = .not.Z ; At least one is set ; Both are reset Example A table byte pointed to by R5 (20-bit address) is used to test bits in input Port1. Jump to label TONI if no bit is set. The next table byte is addressed. BITX.B JNC ... @R5+,&P1IN TONI ; Test input P1 bits. R5 + 1 ; No corresponding input bit is set ; At least one bit is set SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 291 Instruction Set Description 6.6.3.8 CLRX * CLRX.A * CLRX.[W] * CLRX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Clear destination address-word Clear destination word Clear destination byte CLRX.A dst CLRX dst or CLRX.W dst CLRX.B dst 0 → dst MOVX.A #0,dst MOVX #0,dst MOVX.B #0,dst The destination operand is cleared. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. RAM address-word TONI is cleared. CLRX.A TONI ; 0 -> TONI www.ti.com 292 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.9 CMPX Instruction Set Description CMPX.A CMPX.[W] CMPX.B Syntax Operation Description Status Bits Mode Bits Example Compare source address-word and destination address-word Compare source word and destination word Compare source byte and destination byte CMPX.A src,dst CMPX src,dst or CMPX.W src,dst CMPX.B src,dst (.not. src) + 1 + dst or dst – src The source operand is subtracted from the destination operand by adding the 1s complement of the source + 1 to the destination. The result affects only the status bits. Both operands may be located in the full address space. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. Compare EDE with a 20-bit constant 18000h. Jump to label TONI if EDE equals the constant. CMPX.A JEQ ... #018000h,EDE TONI ; Compare EDE with 18000h ; EDE contains 18000h ; Not equal Example A table word pointed to by R5 (20-bit address) is compared with R7. Jump to label TONI if R7 contains a lower, signed, 16-bit number. CMPX.W JL ... @R5,R7 TONI ; Compare two signed numbers ; R7 < @R5 ; R7 >= @R5 Example A table byte pointed to by R5 (20-bit address) is compared to the input in I/O Port1. Jump to label TONI if the values are equal. The next table byte is addressed. CMPX.B JEQ ... @R5+,&P1IN TONI ; Compare P1 bits with table. R5 + 1 ; Equal contents ; Not equal Note: Use CMPA for the following two cases for better density and execution. CMPA CMPA Rsrc,Rdst #imm20,Rdst SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 293 Instruction Set Description 6.6.3.10 DADCX www.ti.com * DADCX.A * DADCX.[W] * DADCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Add carry decimally to destination address-word Add carry decimally to destination word Add carry decimally to destination byte DADCX.A dst DADCX dst or DADCX.W dst DADCX.B dst dst + C → dst (decimally) DADDX.A #0,dst DADDX #0,dst DADDX.B #0,dst The carry bit (C) is added decimally to the destination. N: Set if MSB of result is 1 (address-word > 79999h, word > 7999h, byte > 79h), reset if MSB is 0 Z: Set if result is zero, reset otherwise C: Set if the BCD result is too large (address-word > 99999h, word > 9999h, byte > 99h), reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The 40-bit counter, pointed to by R12 and R13, is incremented decimally. DADDX.A #1,0(R12) DADCX.A 0(R13) ; Increment lower 20 bits ; Add carry to upper 20 bits 294 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.11 DADDX Instruction Set Description DADDX.A DADDX.[W] DADDX.B Syntax Operation Description Status Bits Mode Bits Example Add source address-word and carry decimally to destination address-word Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADDX.A src,dst DADDX src,dst or DADDX.W src,dst DADDX.B src,dst src + dst + C → dst (decimally) The source operand and the destination operand are treated as two (.B), four (.W), or five (.A) binary coded decimals (BCD) with positive signs. The source operand and the carry bit C are added decimally to the destination operand. The source operand is not affected. The previous contents of the destination are lost. The result is not defined for non-BCD numbers. Both operands may be located in the full address space. N: Set if MSB of result is 1 (address-word > 79999h, word > 7999h, byte > 79h), reset if MSB is 0. Z: Set if result is zero, reset otherwise C: Set if the BCD result is too large (address-word > 99999h, word > 9999h, byte > 99h), reset otherwise V: Undefined OSCOFF, CPUOFF, and GIE are not affected. Decimal 10 is added to the 20-bit BCD counter DECCNTR located in two words. DADDX.A #10h,&DECCNTR ; Add 10 to 20-bit BCD counter Example The eight-digit BCD number contained in 20-bit addresses BCD and BCD+2 is added decimally to an eight-digit BCD number contained in R4 and R5 (BCD+2 and R5 contain the MSDs). CLRC DADDX.W DADDX.W JC ... BCD,R4 BCD+2,R5 OVERFLOW ; Clear carry ; Add LSDs ; Add MSDs with carry ; Result >99999999: go to error routine ; Result ok Example The two-digit BCD number contained in 20-bit address BCD is added decimally to a twodigit BCD number contained in R4. CLRC DADDX.B BCD,R4 ; Clear carry ; Add BCD to R4 decimally. ; R4: 000ddh SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 295 Instruction Set Description 6.6.3.12 DECX www.ti.com * DECX.A * DECX.[W] * DECX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Decrement destination address-word Decrement destination word Decrement destination byte DECX.A dst DECX dst or DECX.W dst DECX.B dst dst – 1 → dst SUBX.A #1,dst SUBX #1,dst SUBX.B #1,dst The destination operand is decremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 1, reset otherwise C: Reset if dst contained 0, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. RAM address-word TONI is decremented by one. DECX.A TONI ; Decrement TONI 296 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.13 DECDX Instruction Set Description * DECDX.A * DECDX.[W] * DECDX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Double-decrement destination address-word Double-decrement destination word Double-decrement destination byte DECDX.A dst DECDX dst or DECDX.W dst DECDX.B dst dst – 2 → dst SUBX.A #2,dst SUBX #2,dst SUBX.B #2,dst The destination operand is decremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 2, reset otherwise C: Reset if dst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. RAM address-word TONI is decremented by two. DECDX.A TONI ; Decrement TONI SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 297 Instruction Set Description 6.6.3.14 INCX www.ti.com * INCX.A * INCX.[W] * INCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Increment destination address-word Increment destination word Increment destination byte INCX.A dst INCX dst or INCX.W dst INCX.B dst dst + 1 → dst ADDX.A #1,dst ADDX #1,dst ADDX.B #1,dst The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFFh, reset otherwise Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFFh, reset otherwise Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. RAM address-wordTONI is incremented by one. INCX.A TONI ; Increment TONI (20-bits) 298 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.15 INCDX Instruction Set Description * INCDX.A * INCDX.[W] * INCDX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Double-increment destination address-word Double-increment destination word Double-increment destination byte INCDX.A dst INCDX dst or INCDX.W dst INCDX.B dst dst + 2 → dst ADDX.A #2,dst ADDX #2,dst ADDX.B #2,dst The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFEh, reset otherwise Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFFEh or 0FFFFFh, reset otherwise Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFFEh or 07FFFFh, reset otherwise Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. RAM byte LEO is incremented by two; PC points to upper memory. INCDX.B LEO ; Increment LEO by two SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 299 Instruction Set Description 6.6.3.16 INVX * INVX.A * INVX.[W] * INVX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Invert destination Invert destination Invert destination INVX.A dst INVX dst or INVX.W dst INVX.B dst .NOT.dst → dst XORX.A #0FFFFFh,dst XORX #0FFFFh,dst XORX.B #0FFh,dst The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFFh, reset otherwise Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. 20-bit content of R5 is negated (twos complement). INVX.A R5 INCX.A R5 ; Invert R5 ; R5 is now negated Example Content of memory byte LEO is negated. PC is pointing to upper memory. INVX.B LEO INCX.B LEO ; Invert LEO ; MEM(LEO) is negated www.ti.com 300 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.17 MOVX Instruction Set Description MOVX.A MOVX.[W] MOVX.B Syntax Operation Description Status Bits Mode Bits Example Move source address-word to destination address-word Move source word to destination word Move source byte to destination byte MOVX.A src,dst MOVX src,dst or MOVX.W src,dst MOVX.B src,dst src → dst The source operand is copied to the destination. The source operand is not affected. Both operands may be located in the full address space. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Move a 20-bit constant 18000h to absolute address-word EDE MOVX.A #018000h,&EDE ; Move 18000h to EDE Example The contents of table EDE (word data, 20-bit addresses) are copied to table TOM. The length of the table is 030h words. MOVA Loop MOVX.W CMPA JLO ... #EDE,R10 @R10+,TOM-EDE-2(R10) #EDE+60h,R10 Loop ; Prepare pointer (20-bit address) ; R10 points to both tables. ; R10+2 ; End of table reached? ; Not yet ; Copy completed Example The contents of table EDE (byte data, 20-bit addresses) are copied to table TOM. The length of the table is 020h bytes. MOVA MOV Loop MOVX.W DEC JNZ ... #EDE,R10 #20h,R9 @R10+,TOM-EDE-2(R10) R9 Loop ; Prepare pointer (20-bit) ; Prepare counter ; R10 points to both tables. ; R10+1 ; Decrement counter ; Not yet done ; Copy completed Ten of the 28 possible addressing combinations of the MOVX.A instruction can use the MOVA instruction. This saves two bytes and code cycles. Examples for the addressing combinations are: MOVX.A MOVX.A MOVX.A MOVX.A MOVX.A MOVX.A Rsrc,Rdst #imm20,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,&abs20 MOVA MOVA MOVA MOVA MOVA MOVA Rsrc,Rdst #imm20,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,&abs20 ; Reg/Reg ; Immediate/Reg ; Absolute/Reg ; Indirect/Reg ; Indirect,Auto/Reg ; Reg/Absolute The next four replacements are possible only if 16-bit indexes are sufficient for the addressing: SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 301 Instruction Set Description MOVX.A MOVX.A MOVX.A MOVX.A z20(Rsrc),Rdst Rsrc,z20(Rdst) symb20,Rdst Rsrc,symb20 MOVA MOVA MOVA MOVA z16(Rsrc),Rdst Rsrc,z16(Rdst) symb16,Rdst Rsrc,symb16 ; Indexed/Reg ; Reg/Indexed ; Symbolic/Reg ; Reg/Symbolic www.ti.com 302 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.18 POPM Instruction Set Description POPM.A POPM.[W] Syntax Operation Description Status Bits Mode Bits Example Restore n CPU registers (20-bit data) from the stack Restore n CPU registers (16-bit data) from the stack POPM.A #n,Rdst 1 ≤ n ≤ 16 POPM.W #n,Rdst or POPM #n,Rdst 1 ≤ n ≤ 16 POPM.A: Restore the register values from stack to the specified CPU registers. The SP is incremented by four for each register restored from stack. The 20-bit values from stack (two words per register) are restored to the registers. POPM.W: Restore the 16-bit register values from stack to the specified CPU registers. The SP is incremented by two for each register restored from stack. The 16-bit values from stack (one word per register) are restored to the CPU registers. Note : This instruction does not use the extension word. POPM.A: The CPU registers pushed on the stack are moved to the extended CPU registers, starting with the CPU register (Rdst – n + 1). The SP is incremented by (n × 4) after the operation. POPM.W: The 16-bit registers pushed on the stack are moved back to the CPU registers, starting with CPU register (Rdst – n + 1). The SP is incremented by (n × 2) after the instruction. The MSBs (Rdst.19:16) of the restored CPU registers are cleared. Status bits are not affected, except SR is included in the operation. OSCOFF, CPUOFF, and GIE are not affected. Restore the 20-bit registers R9, R10, R11, R12, R13 from the stack POPM.A #5,R13 ; Restore R9, R10, R11, R12, R13 Example Restore the 16-bit registers R9, R10, R11, R12, R13 from the stack. POPM.W #5,R13 ; Restore R9, R10, R11, R12, R13 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 303 Instruction Set Description 6.6.3.19 PUSHM www.ti.com PUSHM.A PUSHM.[W] Syntax Operation Description Status Bits Mode Bits Example Save n CPU registers (20-bit data) on the stack Save n CPU registers (16-bit words) on the stack PUSHM.A #n,Rdst 1 ≤ n ≤ 16 PUSHM.W #n,Rdst or PUSHM #n,Rdst 1 ≤ n ≤ 16 PUSHM.A: Save the 20-bit CPU register values on the stack. The SP is decremented by four for each register stored on the stack. The MSBs are stored first (higher address). PUSHM.W: Save the 16-bit CPU register values on the stack. The SP is decremented by two for each register stored on the stack. PUSHM.A: The n CPU registers, starting with Rdst backwards, are stored on the stack. The SP is decremented by (n × 4) after the operation. The data (Rn.19:0) of the pushed CPU registers is not affected. PUSHM.W: The n registers, starting with Rdst backwards, are stored on the stack. The SP is decremented by (n × 2) after the operation. The data (Rn.19:0) of the pushed CPU registers is not affected. Note : This instruction does not use the extension word. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Save the five 20-bit registers R9, R10, R11, R12, R13 on the stack PUSHM.A #5,R13 ; Save R13, R12, R11, R10, R9 Example Save the five 16-bit registers R9, R10, R11, R12, R13 on the stack PUSHM.W #5,R13 ; Save R13, R12, R11, R10, R9 304 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.20 POPX Instruction Set Description * POPX.A * POPX.[W] * POPX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Restore single address-word from the stack Restore single word from the stack Restore single byte from the stack POPX.A dst POPX dst or POPX.W dst POPX.B dst Restore the 8-, 16-, 20-bit value from the stack to the destination. 20-bit addresses are possible. The SP is incremented by two (byte and word operands) and by four (address-word operand). MOVX(.B,.A) @SP+,dst The item on TOS is written to the destination operand. Register mode, Indexed mode, Symbolic mode, and Absolute mode are possible. The SP is incremented by two or four. Note: the SP is incremented by two also for byte operations. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Write the 16-bit value on TOS to the 20-bit address &EDE POPX.W &EDE ; Write word to address EDE Example Write the 20-bit value on TOS to R9 POPX.A R9 ; Write address-word to R9 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 305 Instruction Set Description 6.6.3.21 PUSHX www.ti.com PUSHX.A PUSHX.[W] PUSHX.B Syntax Operation Description Status Bits Mode Bits Example Save single address-word to the stack Save single word to the stack Save single byte to the stack PUSHX.A src PUSHX src or PUSHX.W src PUSHX.B src Save the 8-, 16-, 20-bit value of the source operand on the TOS. 20-bit addresses are possible. The SP is decremented by two (byte and word operands) or by four (addressword operand) before the write operation. The SP is decremented by two (byte and word operands) or by four (address-word operand). Then the source operand is written to the TOS. All seven addressing modes are possible for the source operand. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Save the byte at the 20-bit address &EDE on the stack PUSHX.B &EDE ; Save byte at address EDE Example Save the 20-bit value in R9 on the stack. PUSHX.A R9 ; Save address-word in R9 306 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.22 RLAM Instruction Set Description RLAM.A RLAM.[W] Syntax Operation Description Status Bits Mode Bits Example Rotate left arithmetically the 20-bit CPU register content Rotate left arithmetically the 16-bit CPU register content RLAM.A #n,Rdst 1≤n≤4 RLAM.W #n,Rdst or RLAM #n,Rdst 1≤n≤4 C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 The destination operand is shifted arithmetically left one, two, three, or four positions as shown in Figure 6-44. RLAM works as a multiplication (signed and unsigned) with 2, 4, 8, or 16. The word instruction RLAM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the MSB (n = 1), MSB-1 (n = 2), MSB-2 (n = 3), MSB-3 (n = 4) V: Undefined OSCOFF, CPUOFF, and GIE are not affected. The 20-bit operand in R5 is shifted left by three positions. It operates equal to an arithmetic multiplication by 8. RLAM.A #3,R5 ; R5 = R5 x 8 19 16 15 C 0000 MSB 0 LSB 0 19 C MSB 0 LSB 0 Figure 6-44. Rotate Left Arithmetically—RLAM[.W] and RLAM.A SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 307 Instruction Set Description 6.6.3.23 RLAX www.ti.com * RLAX.A * RLAX.[W] * RLAX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Rotate left arithmetically address-word Rotate left arithmetically word Rotate left arithmetically byte RLAX.A dst RLAX dst or RLAX.W dst RLAX.B dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← 0 ADDX.A dst,dst ADDX dst,dst ADDX.B dst,dst The destination operand is shifted left one position as shown in Figure 6-45. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLAX instruction acts as a signed multiplication by 2. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs: the initial value is 040000h ≤ dst < 0C0000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R7 is multiplied by 2 RLAX.A R7 ; Shift left R7 (20-bit) 0 C MSB LSB 0 Figure 6-45. Destination Operand-Arithmetic Shift Left 308 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.24 RLCX Instruction Set Description * RLCX.A * RLCX.[W] * RLCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Rotate left through carry address-word Rotate left through carry word Rotate left through carry byte RLCX.A dst RLCX dst or RLCX.W dst RLCX.B dst C ← MSB ← MSB-1 .... LSB+1 ← LSB ← C ADDCX.A dst,dst ADDCX dst,dst ADDCX.B dst,dst The destination operand is shifted left one position as shown in Figure 6-46. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C). N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Loaded from the MSB V: Set if an arithmetic overflow occurs: the initial value is 040000h ≤ dst < 0C0000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 04000h ≤ dst < 0C000h; reset otherwise Set if an arithmetic overflow occurs: the initial value is 040h ≤ dst < 0C0h; reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is shifted left one position. RLCX.A R5 ; (R5 x 2) + C -> R5 Example The RAM byte LEO is shifted left one position. PC is pointing to upper memory. RLCX.B LEO ; RAM(LEO) x 2 + C -> RAM(LEO) 0 C MSB LSB Figure 6-46. Destination Operand-Carry Left Shift SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 309 Instruction Set Description 6.6.3.25 RRAM www.ti.com RRAM.A RRAM.[W] Syntax Operation Description Status Bits Mode Bits Example Rotate right arithmetically the 20-bit CPU register content Rotate right arithmetically the 16-bit CPU register content RRAM.A #n,Rdst 1≤n≤4 RRAM.W #n,Rdst or RRAM #n,Rdst 1≤n≤4 MSB → MSB → MSB–1 ... LSB+1 → LSB → C The destination operand is shifted right arithmetically by one, two, three, or four bit positions as shown in Figure 6-47. The MSB retains its value (sign). RRAM operates equal to a signed division by 2, 4, 8, or 16. The MSB is retained and shifted into MSB-1. The LSB+1 is shifted into the LSB, and the LSB is shifted into the carry bit C. The word instruction RRAM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 20-bit number in R5 is shifted arithmetically right two positions. RRAM.A #2,R5 ; R5/4 -> R5 Example The signed 20-bit value in R15 is multiplied by 0.75. (0.5 + 0.25) × R15. PUSHM.A RRAM.A ADDX.A RRAM.A #1,R15 #1,R15 @SP+,R15 #1,R15 19 16 C 0000 ; Save extended R15 on stack ; R15 y 0.5 -> R15 ; R15 y 0.5 + R15 = 1.5 y R15 -> R15 ; (1.5 y R15) y 0.5 = 0.75 y R15 -> R15 15 0 MSB LSB 19 C MSB 0 LSB Figure 6-47. Rotate Right Arithmetically RRAM[.W] and RRAM.A 310 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.26 RRAX Instruction Set Description RRAX.A RRAX.[W] RRAX.B Syntax Operation Description Status Bits Mode Bits Example Rotate right arithmetically the 20-bit operand Rotate right arithmetically the 16-bit operand Rotate right arithmetically the 8-bit operand RRAX.A Rdst RRAX.W Rdst RRAX Rdst RRAX.B Rdst RRAX.A dst RRAX dst or RRAX.W dst RRAX.B dst MSB → MSB → MSB–1 ... LSB+1 → LSB → C Register mode for the destination: the destination operand is shifted right by one bit position as shown in Figure 6-48. The MSB retains its value (sign). The word instruction RRAX.W clears the bits Rdst.19:16, the byte instruction RRAX.B clears the bits Rdst.19:8. The MSB retains its value (sign), the LSB is shifted into the carry bit. RRAX here operates equal to a signed division by 2. All other modes for the destination: the destination operand is shifted right arithmetically by one bit position as shown in Figure 6-49. The MSB retains its value (sign), the LSB is shifted into the carry bit. RRAX here operates equal to a signed division by 2. All addressing modes, with the exception of the Immediate mode, are possible in the full memory. N: Set if result is negative, reset if positive .A: dst.19 = 1, reset if dst.19 = 0 .W: dst.15 = 1, reset if dst.15 = 0 .B: dst.7 = 1, reset if dst.7 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 20-bit number in R5 is shifted arithmetically right four positions. RPT #4 RRAX.A R5 ; R5/16 -> R5 Example The signed 8-bit value in EDE is multiplied by 0.5. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 311 Instruction Set Description RRAX.B C &EDE 19 0 ; EDE/2 -> EDE 8 0 7 MSB 0 LSB www.ti.com 19 16 C 0000 15 MSB 0 LSB 19 C MSB 0 LSB Figure 6-48. Rotate Right Arithmetically RRAX(.B,.A) – Register Mode 7 0 C MSB LSB 15 C MSB 0 LSB 31 0 19 C MSB 20 0 0 LSB Figure 6-49. Rotate Right Arithmetically RRAX(.B,.A) – Non-Register Mode 312 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.27 RRCM Instruction Set Description RRCM.A RRCM.[W] Syntax Operation Description Status Bits Mode Bits Rotate right through carry the 20-bit CPU register content Rotate right through carry the 16-bit CPU register content RRCM.A #n,Rdst 1≤n≤4 RRCM.W #n,Rdst or RRCM #n,Rdst 1≤n≤4 C → MSB → MSB–1 ... LSB+1 → LSB → C The destination operand is shifted right by one, two, three, or four bit positions as shown in Figure 6-50. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. The word instruction RRCM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) V: Reset OSCOFF, CPUOFF, and GIE are not affected. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 313 Instruction Set Description www.ti.com Example The address-word in R5 is shifted right by three positions. The MSB–2 is loaded with 1. SETC RRCM.A #3,R5 ; Prepare carry for MSB-2 ; R5 = R5 » 3 + 20000h Example The word in R6 is shifted right by two positions. The MSB is loaded with the LSB. The MSB–1 is loaded with the contents of the carry flag. RRCM.W #2,R6 ; R6 = R6 » 2. R6.19:16 = 0 19 16 15 0 C 0 MSB LSB 19 C MSB 0 LSB Figure 6-50. Rotate Right Through Carry RRCM[.W] and RRCM.A 314 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.28 RRCX Instruction Set Description RRCX.A RRCX.[W] RRCX.B Syntax Operation Description Status Bits Mode Bits Example Rotate right through carry the 20-bit operand Rotate right through carry the 16-bit operand Rotate right through carry the 8-bit operand RRCX.A Rdst RRCX.W Rdst RRCX Rdst RRCX.B Rdst RRCX.A dst RRCX dst or RRCX.W dst RRCX.B dst C → MSB → MSB–1 ... LSB+1 → LSB → C Register mode for the destination: the destination operand is shifted right by one bit position as shown in Figure 6-51. The word instruction RRCX.W clears the bits Rdst.19:16, the byte instruction RRCX.B clears the bits Rdst.19:8. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. All other modes for the destination: the destination operand is shifted right by one bit position as shown in Figure 6-52. The carry bit C is shifted into the MSB, the LSB is shifted into the carry bit. All addressing modes, with the exception of the Immediate mode, are possible in the full memory. N: Set if result is negative .A: dst.19 = 1, reset if dst.19 = 0 .W: dst.15 = 1, reset if dst.15 = 0 .B: dst.7 = 1, reset if dst.7 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The 20-bit operand at address EDE is shifted right by one position. The MSB is loaded with 1. SETC RRCX.A EDE ; Prepare carry for MSB ; EDE = EDE » 1 + 80000h Example The word in R6 is shifted right by 12 positions. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 315 Instruction Set Description RPT RRCX.W C #12 R6 ; R6 = R6 » 12. R6.19:16 = 0 19 87 0--------------------0 MSB 19 16 15 C 0 0 0 0 MSB 0 LSB 0 LSB www.ti.com 19 C MSB 0 LSB Figure 6-51. Rotate Right Through Carry RRCX(.B,.A) – Register Mode 7 0 C MSB LSB 15 C MSB 0 LSB 31 0 19 C MSB 20 0 0 LSB Figure 6-52. Rotate Right Through Carry RRCX(.B,.A) – Non-Register Mode 316 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.29 RRUM Instruction Set Description RRUM.A RRUM.[W] Syntax Operation Description Status Bits Mode Bits Example Rotate right through carry the 20-bit CPU register content Rotate right through carry the 16-bit CPU register content RRUM.A #n,Rdst 1≤n≤4 RRUM.W #n,Rdst or RRUM #n,Rdst 1≤n≤4 0 → MSB → MSB–1 ... LSB+1 → LSB → C The destination operand is shifted right by one, two, three, or four bit positions as shown in Figure 6-53. Zero is shifted into the MSB, the LSB is shifted into the carry bit. RRUM works like an unsigned division by 2, 4, 8, or 16. The word instruction RRUM.W clears the bits Rdst.19:16. Note : This instruction does not use the extension word. N: Set if result is negative .A: Rdst.19 = 1, reset if Rdst.19 = 0 .W: Rdst.15 = 1, reset if Rdst.15 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB (n = 1), LSB+1 (n = 2), LSB+2 (n = 3), or LSB+3 (n = 4) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The unsigned address-word in R5 is divided by 16. RRUM.A #4,R5 ; R5 = R5 » 4. R5/16 Example The word in R6 is shifted right by one bit. The MSB R6.15 is loaded with 0. RRUM.W #1,R6 ; R6 = R6/2. R6.19:15 = 0 19 16 15 0 C 0000 MSB LSB 0 C0 19 MSB 0 LSB Figure 6-53. Rotate Right Unsigned RRUM[.W] and RRUM.A SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 317 Instruction Set Description 6.6.3.30 RRUX www.ti.com RRUX.A RRUX.[W] RRUX.B Syntax Operation Description Status Bits Mode Bits Example Shift right unsigned the 20-bit CPU register content Shift right unsigned the 16-bit CPU register content Shift right unsigned the 8-bit CPU register content RRUX.A Rdst RRUX.W Rdst RRUX Rdst RRUX.B Rdst C=0 → MSB → MSB–1 ... LSB+1 → LSB → C RRUX is valid for register mode only: the destination operand is shifted right by one bit position as shown in Figure 6-54. The word instruction RRUX.W clears the bits Rdst.19:16. The byte instruction RRUX.B clears the bits Rdst.19:8. Zero is shifted into the MSB, the LSB is shifted into the carry bit. N: Set if result is negative .A: dst.19 = 1, reset if dst.19 = 0 .W: dst.15 = 1, reset if dst.15 = 0 .B: dst.7 = 1, reset if dst.7 = 0 Z: Set if result is zero, reset otherwise C: Loaded from the LSB V: Reset OSCOFF, CPUOFF, and GIE are not affected. The word in R6 is shifted right by 12 positions. RPT #12 RRUX.W R6 ; R6 = R6 » 12. R6.19:16 = 0 19 87 0 C 0--------------------0 MSB LSB 0 19 16 15 C 0 0 0 0 MSB 0 LSB 0 C0 19 MSB 0 LSB Figure 6-54. Rotate Right Unsigned RRUX(.B,.A) – Register Mode 318 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.31 SBCX Instruction Set Description * SBCX.A * SBCX.[W] * SBCX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Subtract borrow (.NOT. carry) from destination address-word Subtract borrow (.NOT. carry) from destination word Subtract borrow (.NOT. carry) from destination byte SBCX.A dst SBCX dst or SBCX.W dst SBCX.B dst dst + 0FFFFFh + C → dst dst + 0FFFFh + C → dst dst + 0FFh + C → dst SBCX.A #0,dst SBCX #0,dst SBCX.B #0,dst The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise Set to 1 if no borrow, reset if borrow V: Set if an arithmetic overflow occurs, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUBX.B @R13,0(R12) SBCX.B 1(R12) ; Subtract LSDs ; Subtract carry from MSD NOTE: Borrow implementation The borrow is treated as a .NOT. carry: Borrow Yes No Carry Bit 0 1 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 319 Instruction Set Description 6.6.3.32 SUBX www.ti.com SUBX.A SUBX.[W] SUBX.B Syntax Operation Description Status Bits Mode Bits Example Subtract source address-word from destination address-word Subtract source word from destination word Subtract source byte from destination byte SUBX.A src,dst SUBX src,dst or SUBX.W src,dst SUBX.B src,dst (.not. src) + 1 + dst → dst or dst – src → dst The source operand is subtracted from the destination operand. This is done by adding the 1s complement of the source + 1 to the destination. The source operand is not affected. The result is written to the destination operand. Both operands may be located in the full address space. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. A 20-bit constant 87654h is subtracted from EDE (LSBs) and EDE+2 (MSBs). SUBX.A #87654h,EDE ; Subtract 87654h from EDE+2|EDE Example A table word pointed to by R5 (20-bit address) is subtracted from R7. Jump to label TONI if R7 contains zero after the instruction. R5 is auto-incremented by two. R7.19:16 = 0. SUBX.W JZ ... @R5+,R7 TONI ; Subtract table number from R7. R5 + 2 ; R7 = @R5 (before subtraction) ; R7 <> @R5 (before subtraction) Example Byte CNT is subtracted from the byte R12 points to in the full address space. Address of CNT is within PC ± 512 K. SUBX.B CNT,0(R12) ; Subtract CNT from @R12 Note: Use SUBA for the following two cases for better density and execution. SUBX.A Rsrc,Rdst SUBX.A #imm20,Rdst 320 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.33 SUBCX Instruction Set Description SUBCX.A SUBCX.[W] SUBCX.B Syntax Operation Description Status Bits Mode Bits Example Subtract source address-word with carry from destination address-word Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBCX.A src,dst SUBCX src,dst or SUBCX.W src,dst SUBCX.B src,dst (.not. src) + C + dst → dst or dst – (src – 1) + C → dst The source operand is subtracted from the destination operand. This is made by adding the 1s complement of the source + carry to the destination. The source operand is not affected, the result is written to the destination operand. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow). OSCOFF, CPUOFF, and GIE are not affected. A 20-bit constant 87654h is subtracted from R5 with the carry from the previous instruction. SUBCX.A #87654h,R5 ; Subtract 87654h + C from R5 Example A 48-bit number (3 words) pointed to by R5 (20-bit address) is subtracted from a 48-bit counter in RAM, pointed to by R7. R5 auto-increments to point to the next 48-bit number. SUBX.W SUBCX.W SUBCX.W @R5+,0(R7) @R5+,2(R7) @R5+,4(R7) ; Subtract LSBs. R5 + 2 ; Subtract MIDs with C. R5 + 2 ; Subtract MSBs with C. R5 + 2 Example Byte CNT is subtracted from the byte R12 points to. The carry of the previous instruction is used. 20-bit addresses. SUBCX.B &CNT,0(R12) ; Subtract byte CNT from @R12 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 321 Instruction Set Description 6.6.3.34 SWPBX www.ti.com SWPBX.A SWPBX.[W] Syntax Operation Description Status Bits Mode Bits Example Swap bytes of lower word Swap bytes of word SWPBX.A dst SWPBX dst or SWPBX.W dst dst.15:8 ↔ dst.7:0 Register mode: Rn.15:8 are swapped with Rn.7:0. When the .A extension is used, Rn.19:16 are unchanged. When the .W extension is used, Rn.19:16 are cleared. Other modes: When the .A extension is used, bits 31:20 of the destination address are cleared, bits 19:16 are left unchanged, and bits 15:8 are swapped with bits 7:0. When the .W extension is used, bits 15:8 are swapped with bits 7:0 of the addressed word. Status bits are not affected. OSCOFF, CPUOFF, and GIE are not affected. Exchange the bytes of RAM address-word EDE MOVX.A #23456h,&EDE SWPBX.A EDE ; 23456h -> EDE ; 25634h -> EDE Example Exchange the bytes of R5 MOVA #23456h,R5 SWPBX.W R5 ; 23456h -> R5 ; 05634h -> R5 Before SWPBX.A 19 16 15 87 0 X High Byte Low Byte After SWPBX.A 19 16 15 87 0 X Low Byte High Byte Figure 6-55. Swap Bytes SWPBX.A Register Mode Before SWPBX.A 31 20 19 16 15 X X High Byte 87 0 Low Byte After SWPBX.A 31 20 19 16 15 0 X Low Byte 87 0 High Byte Figure 6-56. Swap Bytes SWPBX.A In Memory 322 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Before SWPBX 19 16 15 X High Byte 87 Low Byte Instruction Set Description 0 After SWPBX 19 16 15 87 0 0 Low Byte High Byte Figure 6-57. Swap Bytes SWPBX[.W] Register Mode Before SWPBX 15 87 0 High Byte Low Byte After SWPBX 15 87 0 Low Byte High Byte Figure 6-58. Swap Bytes SWPBX[.W] In Memory SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 323 Instruction Set Description 6.6.3.35 SXTX www.ti.com SXTX.A SXTX.[W] Syntax Operation Description Status Bits Mode Bits Example Extend sign of lower byte to address-word Extend sign of lower byte to word SXTX.A dst SXTX dst or SXTX.W dst dst.7 → dst.15:8, Rdst.7 → Rdst.19:8 (Register mode) Register mode: The sign of the low byte of the operand (Rdst.7) is extended into the bits Rdst.19:8. Other modes: SXTX.A: the sign of the low byte of the operand (dst.7) is extended into dst.19:8. The bits dst.31:20 are cleared. SXTX[.W]: the sign of the low byte of the operand (dst.7) is extended into dst.15:8. N: Set if result is negative, reset otherwise Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (C = .not.Z) V: Reset OSCOFF, CPUOFF, and GIE are not affected. The signed 8-bit data in EDE.7:0 is sign extended to 20 bits: EDE.19:8. Bits 31:20 located in EDE+2 are cleared. SXTX.A &EDE SXTX.A Rdst ; Sign extended EDE -> EDE+2/EDE 19 16 15 876 0 S SXTX.A dst 31 0 ...... 20 19 0 16 15 876 0 S Figure 6-59. Sign Extend SXTX.A SXTX[.W] Rdst 19 16 15 876 0 S SXTX[.W] dst 15 876 0 S Figure 6-60. Sign Extend SXTX[.W] 324 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.3.36 TSTX Instruction Set Description * TSTX.A * TSTX.[W] * TSTX.B Syntax Operation Emulation Description Status Bits Mode Bits Example Test destination address-word Test destination word Test destination byte TSTX.A dst TSTX dst or TSTX.W dst TSTX.B dst dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 CMPX.A #0,dst CMPX #0,dst CMPX.B #0,dst The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Set if destination is negative, reset if positive Z: Set if destination contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. RAM byte LEO is tested; PC is pointing to upper memory. If it is negative, continue at LEONEG; if it is positive but not zero, continue at LEOPOS. LEOPOS LEONEG LEOZERO TSTX.B JN JZ ...... ...... ...... LEO LEONEG LEOZERO ; Test LEO ; LEO is negative ; LEO is zero ; LEO is positive but not zero ; LEO is negative ; LEO is zero SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 325 Instruction Set Description 6.6.3.37 XORX www.ti.com XORX.A XORX.[W] XORX.B Syntax Operation Description Status Bits Mode Bits Example Exclusive OR source address-word with destination address-word Exclusive OR source word with destination word Exclusive OR source byte with destination byte XORX.A src,dst XORX src,dst or XORX.W src,dst XORX.B src,dst src .xor. dst → dst The source and destination operands are exclusively ORed. The result is placed into the destination. The source operand is not affected. The previous contents of the destination are lost. Both operands may be located in the full address space. N: Set if result is negative (MSB = 1), reset if positive (MSB = 0) Z: Set if result is zero, reset otherwise C: Set if result is not zero, reset otherwise (carry = .not. Zero) V: Set if both operands are negative (before execution), reset otherwise OSCOFF, CPUOFF, and GIE are not affected. Toggle bits in address-word CNTR (20-bit data) with information in address-word TONI (20-bit address) XORX.A TONI,&CNTR ; Toggle bits in CNTR Example A table word pointed to by R5 (20-bit address) is used to toggle bits in R6. XORX.W @R5,R6 ; Toggle bits in R6. R6.19:16 = 0 Example Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE (20-bit address) XORX.B EDE,R7 INV.B R7 ; Set different bits to 1 in R7 ; Invert low byte of R7. R7.19:8 = 0. 326 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Instruction Set Description 6.6.4 Address Instructions MSP430X address instructions are instructions that support 20-bit operands but have restricted addressing modes. The addressing modes are restricted to the Register mode and the Immediate mode, except for the MOVA instruction. Restricting the addressing modes removes the need for the additional extension-word op-code improving code density and execution time. The MSP430X address instructions are listed and described in the following pages. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 327 Instruction Set Description 6.6.4.1 ADDA www.ti.com ADDA Syntax Operation Description Status Bits Mode Bits Example Add 20-bit source to a 20-bit destination register ADDA Rsrc,Rdst ADDA #imm20,Rdst src + Rdst → Rdst The 20-bit source operand is added to the 20-bit destination CPU register. The previous contents of the destination are lost. The source operand is not affected. N: Set if result is negative (Rdst.19 = 1), reset if positive (Rdst.19 = 0) Z: Set if result is zero, reset otherwise C: Set if there is a carry from the 20-bit result, reset otherwise V: Set if the result of two positive operands is negative, or if the result of two negative numbers is positive, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. R5 is increased by 0A4320h. The jump to TONI is performed if a carry occurs. ADDA JC ... #0A4320h,R5 TONI ; Add A4320h to 20-bit R5 ; Jump on carry ; No carry occurred 328 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.4.2 BRA Instruction Set Description * BRA Syntax Operation Emulation Description Status Bits Mode Bits Examples Branch to destination BRA dst dst → PC MOVA dst,PC An unconditional branch is taken to a 20-bit address anywhere in the full address space. All seven source addressing modes can be used. The branch instruction is an address-word instruction. If the destination address is contained in a memory location X, it is contained in two ascending words: X (LSBs) and (X + 2) (MSBs). N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Examples for all addressing modes are given. Immediate mode: Branch to label EDE located anywhere in the 20-bit address space or branch directly to address. BRA #EDE ; MOVA #imm20,PC BRA #01AA04h Symbolic mode: Branch to the 20-bit address contained in addresses EXEC (LSBs) and EXEC+2 (MSBs). EXEC is located at the address (PC + X) where X is within ±32 K. Indirect addressing. BRA EXEC ; MOVA z16(PC),PC Note: If the 16-bit index is not sufficient, a 20-bit index may be used with the following instruction. MOVX.A EXEC,PC ; 1M byte range with 20-bit index Absolute mode: Branch to the 20-bit address contained in absolute addresses EXEC (LSBs) and EXEC+2 (MSBs). Indirect addressing. BRA &EXEC ; MOVA &abs20,PC Register mode: Branch to the 20-bit address contained in register R5. Indirect R5. BRA R5 ; MOVA R5,PC Indirect mode: Branch to the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. BRA @R5 ; MOVA @R5,PC SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 329 Instruction Set Description www.ti.com Indirect, Auto-Increment mode: Branch to the 20-bit address contained in the words pointed to by register R5 and increment the address in R5 afterwards by 4. The next time the software flow uses R5 as a pointer, it can alter the program execution due to access to the next address in the table pointed to by R5. Indirect, indirect R5. BRA @R5+ ; MOVA @R5+,PC. R5 + 4 Indexed mode: Branch to the 20-bit address contained in the address pointed to by register (R5 + X) (for example, a table with addresses starting at X). (R5 + X) points to the LSBs, (R5 + X + 2) points to the MSBs of the address. X is within R5 ± 32 K. Indirect, indirect (R5 + X). BRA X(R5) ; MOVA z16(R5),PC Note: If the 16-bit index is not sufficient, a 20-bit index X may be used with the following instruction: MOVX.A X(R5),PC ; 1M byte range with 20-bit index 330 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.4.3 CALLA Instruction Set Description CALLA Syntax Operation Description Status Bits Mode Bits Examples Call a subroutine CALLA dst dst → tmp 20-bit dst is evaluated and stored SP – 2 → SP PC.19:16 → @SP updated PC with return address to TOS (MSBs) SP – 2 → SP PC.15:0 → @SP updated PC to TOS (LSBs) tmp → PC saved 20-bit dst to PC A subroutine call is made to a 20-bit address anywhere in the full address space. All seven source addressing modes can be used. The call instruction is an address-word instruction. If the destination address is contained in a memory location X, it is contained in two ascending words, X (LSBs) and (X + 2) (MSBs). Two words on the stack are needed for the return address. The return is made with the instruction RETA. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Examples for all addressing modes are given. Immediate mode: Call a subroutine at label EXEC or call directly an address. CALLA #EXEC CALLA #01AA04h ; Start address EXEC ; Start address 01AA04h Symbolic mode: Call a subroutine at the 20-bit address contained in addresses EXEC (LSBs) and EXEC+2 (MSBs). EXEC is located at the address (PC + X) where X is within ±32 K. Indirect addressing. CALLA EXEC ; Start address at @EXEC. z16(PC) Absolute mode: Call a subroutine at the 20-bit address contained in absolute addresses EXEC (LSBs) and EXEC+2 (MSBs). Indirect addressing. CALLA &EXEC ; Start address at @EXEC Register mode: Call a subroutine at the 20-bit address contained in register R5. Indirect R5. CALLA R5 ; Start address at @R5 Indirect mode: Call a subroutine at the 20-bit address contained in the word pointed to by register R5 (LSBs). The MSBs have the address (R5 + 2). Indirect, indirect R5. CALLA @R5 ; Start address at @R5 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 331 Instruction Set Description www.ti.com Indirect, Auto-Increment mode: Call a subroutine at the 20-bit address contained in the words pointed to by register R5 and increment the 20-bit address in R5 afterwards by 4. The next time the software flow uses R5 as a pointer, it can alter the program execution due to access to the next word address in the table pointed to by R5. Indirect, indirect R5. CALLA @R5+ ; Start address at @R5. R5 + 4 Indexed mode: Call a subroutine at the 20-bit address contained in the address pointed to by register (R5 + X); for example, a table with addresses starting at X. (R5 + X) points to the LSBs, (R5 + X + 2) points to the MSBs of the word address. X is within R5 ± 32 K. Indirect, indirect (R5 + X). CALLA X(R5) ; Start address at @(R5+X). z16(R5) 332 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.4.4 CLRA * CLRA Syntax Operation Emulation Description Status Bits Example Clear 20-bit destination register CLRA Rdst 0 → Rdst MOVA #0,Rdst The destination register is cleared. Status bits are not affected. The 20-bit value in R10 is cleared. CLRA R10 ; 0 -> R10 Instruction Set Description SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 333 Instruction Set Description 6.6.4.5 CMPA www.ti.com CMPA Syntax Operation Description Status Bits Mode Bits Example Compare the 20-bit source with a 20-bit destination register CMPA Rsrc,Rdst CMPA #imm20,Rdst (.not. src) + 1 + Rdst or Rdst – src The 20-bit source operand is subtracted from the 20-bit destination CPU register. This is made by adding the 1s complement of the source + 1 to the destination register. The result affects only the status bits. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB, reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. A 20-bit immediate operand and R6 are compared. If they are equal, the program continues at label EQUAL. CMPA JEQ ... #12345h,R6 EQUAL ; Compare R6 with 12345h ; R6 = 12345h ; Not equal Example The 20-bit values in R5 and R6 are compared. If R5 is greater than (signed) or equal to R6, the program continues at label GRE. CMPA JGE ... R6,R5 GRE ; Compare R6 with R5 (R5 - R6) ; R5 >= R6 ; R5 < R6 334 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.4.6 DECDA Instruction Set Description * DECDA Syntax Operation Emulation Description Status Bits Mode Bits Example Double-decrement 20-bit destination register DECDA Rdst Rdst – 2 → Rdst SUBA #2,Rdst The destination register is decremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if Rdst contained 2, reset otherwise C: Reset if Rdst contained 0 or 1, set otherwise V: Set if an arithmetic overflow occurs, otherwise reset OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is decremented by 2. DECDA R5 ; Decrement R5 by two SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 335 Instruction Set Description 6.6.4.7 INCDA www.ti.com * INCDA Syntax Operation Emulation Description Status Bits Mode Bits Example Double-increment 20-bit destination register INCDA Rdst Rdst + 2 → Rdst ADDA #2,Rdst The destination register is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if Rdst contained 0FFFFEh, reset otherwise Set if Rdst contained 0FFFEh, reset otherwise Set if Rdst contained 0FEh, reset otherwise C: Set if Rdst contained 0FFFFEh or 0FFFFFh, reset otherwise Set if Rdst contained 0FFFEh or 0FFFFh, reset otherwise Set if Rdst contained 0FEh or 0FFh, reset otherwise V: Set if Rdst contained 07FFFEh or 07FFFFh, reset otherwise Set if Rdst contained 07FFEh or 07FFFh, reset otherwise Set if Rdst contained 07Eh or 07Fh, reset otherwise OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is incremented by two. INCDA R5 ; Increment R5 by two 336 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.4.8 MOVA Instruction Set Description MOVA Syntax Operation Description Status Bits Mode Bits Examples Move the 20-bit source to the 20-bit destination MOVA Rsrc,Rdst MOVA #imm20,Rdst MOVA z16(Rsrc),Rdst MOVA EDE,Rdst MOVA &abs20,Rdst MOVA @Rsrc,Rdst MOVA @Rsrc+,Rdst MOVA Rsrc,z16(Rdst) MOVA Rsrc,&abs20 src → Rdst Rsrc → dst The 20-bit source operand is moved to the 20-bit destination. The source operand is not affected. The previous content of the destination is lost. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Copy 20-bit value in R9 to R8 MOVA R9,R8 ; R9 -> R8 Write 20-bit immediate value 12345h to R12 MOVA #12345h,R12 ; 12345h -> R12 Copy 20-bit value addressed by (R9 + 100h) to R8. Source operand in addresses (R9 + 100h) LSBs and (R9 + 102h) MSBs. MOVA 100h(R9),R8 ; Index: + 32 K. 2 words transferred Move 20-bit value in 20-bit absolute addresses EDE (LSBs) and EDE+2 (MSBs) to R12 MOVA &EDE,R12 ; &EDE -> R12. 2 words transferred Move 20-bit value in 20-bit addresses EDE (LSBs) and EDE+2 (MSBs) to R12. PC index ± 32 K. MOVA EDE,R12 ; EDE -> R12. 2 words transferred Copy 20-bit value R9 points to (20 bit address) to R8. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9,R8 ; @R9 -> R8. 2 words transferred SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 337 Instruction Set Description www.ti.com Copy 20-bit value R9 points to (20 bit address) to R8. R9 is incremented by four afterwards. Source operand in addresses @R9 LSBs and @(R9 + 2) MSBs. MOVA @R9+,R8 ; @R9 -> R8. R9 + 4. 2 words transferred. Copy 20-bit value in R8 to destination addressed by (R9 + 100h). Destination operand in addresses @(R9 + 100h) LSBs and @(R9 + 102h) MSBs. MOVA R8,100h(R9) ; Index: +- 32 K. 2 words transferred Move 20-bit value in R13 to 20-bit absolute addresses EDE (LSBs) and EDE+2 (MSBs) MOVA R13,&EDE ; R13 -> EDE. 2 words transferred Move 20-bit value in R13 to 20-bit addresses EDE (LSBs) and EDE+2 (MSBs). PC index ± 32 K. MOVA R13,EDE ; R13 -> EDE. 2 words transferred 338 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.4.9 RETA Instruction Set Description * RETA Syntax Operation Emulation Description Status Bits Mode Bits Example Return from subroutine RETA @SP → PC.15:0 LSBs (15:0) of saved PC to PC.15:0 SP + 2 → SP @SP → PC.19:16 MSBs (19:16) of saved PC to PC.19:16 SP + 2 → SP MOVA @SP+,PC The 20-bit return address information, pushed onto the stack by a CALLA instruction, is restored to the PC. The program continues at the address following the subroutine call. The SR bits SR.11:0 are not affected. This allows the transfer of information with these bits. N: Not affected Z: Not affected C: Not affected V: Not affected OSCOFF, CPUOFF, and GIE are not affected. Call a subroutine SUBR from anywhere in the 20-bit address space and return to the address after the CALLA SUBR CALLA ... PUSHM.A ... POPM.A RETA #SUBR #2,R14 #2,R14 ; Call subroutine starting at SUBR ; Return by RETA to here ; Save R14 and R13 (20 bit data) ; Subroutine code ; Restore R13 and R14 (20 bit data) ; Return (to full address space) SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 339 Instruction Set Description 6.6.4.10 SUBA www.ti.com SUBA Syntax Operation Description Status Bits Mode Bits Example Subtract 20-bit source from 20-bit destination register SUBA Rsrc,Rdst SUBA #imm20,Rdst (.not.src) + 1 + Rdst → Rdst or Rdst – src → Rdst The 20-bit source operand is subtracted from the 20-bit destination register. This is made by adding the 1s complement of the source + 1 to the destination. The result is written to the destination register, the source is not affected. N: Set if result is negative (src > dst), reset if positive (src ≤ dst) Z: Set if result is zero (src = dst), reset otherwise (src ≠ dst) C: Set if there is a carry from the MSB (Rdst.19), reset otherwise V: Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result, or if the subtraction of a positive source operand from a negative destination operand delivers a positive result, reset otherwise (no overflow) OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R5 is subtracted from R6. If a carry occurs, the program continues at label TONI. SUBA R5,R6 JC TONI ... ; R6 - R5 -> R6 ; Carry occurred ; No carry 340 CPUX SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 6.6.4.11 TSTA Instruction Set Description * TSTA Syntax Operation Emulation Description Status Bits Mode Bits Example Test 20-bit destination register TSTA Rdst dst + 0FFFFFh + 1 dst + 0FFFFh + 1 dst + 0FFh + 1 CMPA #0,Rdst The destination register is compared with zero. The status bits are set according to the result. The destination register is not affected. N: Set if destination register is negative, reset if positive Z: Set if destination register contains zero, reset otherwise C: Set V: Reset OSCOFF, CPUOFF, and GIE are not affected. The 20-bit value in R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. R7POS R7NEG R7ZERO TSTA R7 JN R7NEG JZ R7ZERO ...... ...... ...... ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CPUX 341 Chapter 7 SLAU208O – June 2008 – Revised May 2015 Flash Memory Controller This chapter describes the operation of the flash memory controller. Topic ........................................................................................................................... Page 7.1 Flash Memory Introduction ................................................................................ 343 7.2 Flash Memory Segmentation.............................................................................. 344 7.3 Flash Memory Operation ................................................................................... 346 7.4 FCTL Registers ................................................................................................ 361 342 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Introduction 7.1 Flash Memory Introduction The flash memory is byte, word, and long-word addressable and programmable. The flash memory module has an integrated controller that controls programming and erase operations. The module contains three registers, a timing generator, and a voltage generator to supply program and erase voltages. The cumulative high-voltage time must not be exceeded, and each 32-bit word can be written not more than four times (in byte, word, or long word write modes) before another erase cycle (see device-specific data sheet for details). The flash memory features include: • Internal programming voltage generation • Byte, word (2 bytes), and long (4 bytes) programmable • Ultra-low-power operation • Segment erase, bank erase (device specific), and mass erase • Marginal 0 and marginal 1 read modes • Each bank (device specific) can be erased individually while program execution can proceed in a different flash bank. NOTE: Bank operations are not supported on all devices. See the device-specific data sheet for banks supported and their respective sizes. Figure 7-1 shows the block diagram of the flash memory and controller. MAB MDB Control Registers Address/Data Latch Timing Generator Programming Voltage Generator Flash Memory Array Figure 7-1. Flash Memory Module Block Diagram SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 343 Flash Memory Segmentation www.ti.com 7.2 Flash Memory Segmentation The flash main memory is partitioned into 512-byte segments. Single bits, bytes, or words can be written to flash memory, but a segment is the smallest size of the flash memory that can be erased. The flash memory is partitioned into main and information memory sections. There is no difference in the operation of the main and information memory sections. Code and data can be located in either section. The difference between the sections is the segment size. There are four information memory segments, A through D. Each information memory segment contains 128 bytes and can be erased individually. The bootstrap loader (BSL) memory consists of four segments, A through D. Each BSL memory segment contains 512 bytes and can be erased individually. The main memory segment size is 512 byte. See the device-specific data sheet for the start and end addresses of each bank, when available, and for the complete memory map of a device. Figure 7-2 shows the flash segmentation using an example of 256KB of flash that has four banks of 64KB (segments A through D) and information memory. 128-byte Information Memory Segment A 128-byte Information Memory Segment B 512-byte BSL Memory A 512-byte BSL Memory C 128-byte Information Memory Segment C 128-byte Information Memory Segment D 512-byte BSL Memory B 512-byte BSL Memory D 64-kbyte Flash Memory Bank A 64-kbyte Flash Memory Bank B Segment 0 Segment 0 Segment 0 Segment 1 Segment 2 Segment X 64-kbyte Flash Memory Bank C 64-kbyte Flash Memory Bank D Segment 125 Segment 126 Segment 127 Figure 7-2. 256KB of Flash Memory Segments Example 344 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Segmentation 7.2.1 Segment A Segment A of the information memory is locked separately from all other segments with the LOCKA bit. If LOCKA = 1, segment A cannot be written or erased, and all information memory is protected from being segment erased. If LOCKA = 0, segment A can be erased and written like any other flash memory segment. The state of the LOCKA bit is toggled when a 1 is written to it. Writing a 0 to LOCKA has no effect. This allows existing flash programming routines to be used unchanged. ; Unlock Info Memory MOV #FWPW,&FCTL4 ; Unlock SegmentA BIT #LOCKA,&FCTL3 JZ SEGA_UNLOCKED MOV #FWPW+LOCKA,&FCTL3 SEGA_UNLOCKED ; SegmentA is unlocked ; Clear LOCKINFO, if set ; Test LOCKA ; Already unlocked? ; No, unlock SegmentA ; Yes, continue ; Lock SegmentA BIT #LOCKA,&FCTL3 JNZ SEGA_LOCKED MOV #FWPW+LOCKA,&FCTL3 SEGA_LOCKED ; SegmentA is locked ; Lock Info Memory MOV #FWPW+LOCKINFO,&FCTL4 ; Test LOCKA ; Already locked? ; No, lock SegmentA ; Yes, continue ; Set LOCKINFO SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 345 Flash Memory Operation www.ti.com 7.3 Flash Memory Operation The default mode of the flash memory is read mode. In read mode, the flash memory is not being erased or written, the flash timing generator and voltage generator are off, and the memory operates identically to ROM. Read and fetch while erase – The flash memory allows execution of a program from flash while a different flash bank is erased. Data reads are also possible from any flash bank not being erased. NOTE: Read and fetch while erase The read and fetch while erase feature is available in flash memory configurations where more than one flash bank is available. If there is one flash bank available, holding the complete flash program memory, the read from the program memory and information memory and BSL memory during the erase is not provided. Table 7-1 summarizes which flash operations are supported for devices that support read and fetch while erasing. Table 7-1. Supported Simultaneous Code Execution and Flash Operations Flash Operation Bank Erase Segment Erase Byte, word, long-word write Simultaneous Code Execution Within Flash Within RAM Supported Executed code must not reside in the bank to be erased Supported Not Supported Supported Not supported Supported Flash memory is in-system programmable (ISP) without the need for additional external voltage. The CPU can program the flash memory. The flash memory write and erase modes are selected by the BLKWRT, WRT, MERAS, and ERASE bits and are: • Byte, word, or long-word (32-bit) write • Block write • Segment erase • Bank erase (only main memory) • Mass erase (all main memory banks) • Read during bank erase (except for the one currently read from) Reading or writing to flash memory while it is busy programming or erasing (page, mass, or bank) from the same bank is prohibited. Any flash erase or programming can be initiated from within flash memory or RAM. 7.3.1 Erasing Flash Memory The logical value of an erased flash memory bit is 1. Each bit can be programmed from 1 to 0 individually, but to reprogram from 0 to 1 requires an erase cycle. The smallest amount of flash that can be erased is one segment. There are three erase modes selected by the ERASE and MERAS bits listed in Table 7-2. Table 7-2. Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Bank erase (of one bank) selected by the dummy write address(1) 1 1 Mass erase (all memory banks are erased. Information memory A to D and BSL segments A to D are not erased) (1) Bank operations are not supported on all devices. See the device-specific data sheet for support of bank operations. 346 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Operation 7.3.1.1 Erase Cycle An erase cycle is initiated by a dummy write to the address range of the segment to be erased. The dummy write starts the erase operation and is required for all erase operations including mass erase. Figure 7-3 shows the erase cycle timing. The BUSY bit is set immediately after the dummy write and remains set throughout the erase cycle. BUSY, MERAS, and ERASE are automatically cleared when the cycle completes. No additional dummy write access should be made while the control bits are cleared, otherwise, ACCVIFG is set. The mass erase cycle timing is not dependent on the amount of flash memory present on a device. Erase cycle times are equivalent for all devices. Generate Programming Voltage Erase Operation Active Remove Programming Voltage Erase Time, Current Consumption is Increased BUSY t = t Erase Mass_erase, Segment_erase, Bank_erase Figure 7-3. Erase Cycle Timing 7.3.1.2 Erasing Main Memory The main memory consists of one or more banks. Each bank can be erased individually (bank erase). All main memory banks can be erased in the mass erase mode. 7.3.1.3 Erasing Information Memory or BSL Flash Segments The information memory A to D and the BSL segments A to D can only be erased in segment erase mode. They are not erased during a bank erase or a mass erase. Erasing is only possible by first clearing the LOCKINFO bit. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 347 Flash Memory Operation www.ti.com 7.3.1.4 Initiating Erase From Flash An erase cycle can be initiated from within flash memory. During a bank erase, code can be executed from flash or RAM. The executed code cannot be located in a bank to be erased. For any segment erase, the CPU is held until the erase cycle completes regardless of the bank the code resides in. After the segment erase cycle ends, the CPU resumes code execution with the instruction following the dummy write. When initiating an erase cycle from within flash memory, it is possible to erase the code needed for execution after the erase operation. If this occurs, CPU execution is unpredictable after the erase cycle. The flow to initiate an erase from flash is shown in Figure 7-4. Disable watchdog Yes BUSY = 1 Setup flash controller and erase mode Dummy write Set LOCK = 1, (Set LOCKINFO = 1) reenable watchdog Figure 7-4. Erase Cycle From Flash ; Segment Erase from flash. ; Assumes Program Memory. Information memory or BSL ; requires LOCKINFO to be cleared as well. ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWPW,&FCTL3 ; Clear LOCK MOV #FWPW+ERASE,&FCTL1 ; Enable segment erase CLR &0FC10h ; Dummy write L2 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L2 ; Loop while busy MOV #FWPW+LOCK,&FCTL3 ; Done, set LOCK ... ; Re-enable WDT? 348 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Operation 7.3.1.5 Initiating Erase From RAM An erase cycle can be initiated from RAM. In this case, the CPU is not held and continues to execute code from RAM. The mass erase (all main memory banks) operation is initiated while executing from RAM. The BUSY bit is used to determine the end of the erase cycle. If the flash is busy completing a bank erase, flash addresses of a different bank can be used to read data or to fetch instructions. While the flash is BUSY, starting an erase cycle or a programming cycle causes an access violation, ACCIFG is set to 1, and the result of the erase operation is unpredictable. The flow to initiate an erase from flash from RAM is shown in Figure 7-5. Disable watchdog Yes BUSY = 1 Setup flash controller and erase mode Dummy write Yes BUSY = 1 Set LOCK = 1, (Set LOCKINFO = 1) Reenable watchdog Figure 7-5. Erase Cycle From RAM ; segment Erase from RAM. ; Assumes Program Memory. Information memory or BSL ; requires LOCKINFO to be cleared as well. ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWPW,&FCTL3 ; Clear LOCK MOV #FWPW+ERASE,&FCTL1 ; Enable page erase CLR &0FC10h ; Dummy write L2 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L2 ; Loop while busy MOV #FWPW+LOCK,&FCTL3 ; Done, set LOCK ... ; Re-enable WDT? SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 349 Flash Memory Operation 7.3.2 Writing Flash Memory The write modes, selected by the WRT and BLKWRT bits, are listed in Table 7-3. BLKWRT 0 1 1 Table 7-3. Write Modes WRT 1 0 1 Write Mode Byte or word write Long-word write Long-word block write www.ti.com The write modes use a sequence of individual write instructions. Using the long-word write mode is approximately twice as fast as the byte or word mode. Using the long-word block write mode is approximately four times faster than byte or word mode, because the voltage generator remains on for the complete block write, and long-words are written in parallel. Any instruction that modifies a destination can be used to modify a flash location in either byte or word write mode, long-word write mode, or block longword write mode. The BUSY bit is set while the write operation is active and cleared when the operation completes. If the write operation is initiated from RAM, the CPU must not access flash while BUSY is set to 1. Otherwise, an access violation occurs, ACCVIFG is set, and the flash write is unpredictable. 7.3.2.1 Byte or Word Write A byte or word write operation can be initiated from within flash memory or from RAM. When initiating from within flash memory, the CPU is held while the write completes. After the write completes, the CPU resumes code execution with the instruction following the write access. The byte, word, and long-word write timing is shown in Figure 7-6. Byte, word, and long-word write times are identical. Generate Programming Voltage Programming Operation Active Remove Programming Voltage Programming Time, VCC Current Consumption is Increased BUSY tWrite Figure 7-6. Byte, Word, and Long-Word Write Timing When a byte or word write is executed from RAM, the CPU continues to execute code from RAM. The BUSY bit must be zero before the CPU accesses flash again, otherwise an access violation occurs, ACCVIFG is set, and the write result is unpredictable. In any write mode, the internally-generated programming voltage is applied to the complete 128-byte block. The cumulative programming time, tCPT, must not be exceeded for any block. Each byte, word, or long-word write adds to the cumulative program time of a segment. If the maximum cumulative program time is reached or exceeded, the segment must be erased. Further programming or using the data returns unpredictable results (see the device-specific data sheet for specifications). 350 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.3.2.2 Initiating Byte or Word Write From Flash The flow to initiate a byte or word write from flash is shown in Figure 7-7. Disable watchdog Flash Memory Operation Setup flash controller and set WRT = 1 Write byte or word Set WRT = 0, LOCK = 1, reenable watchdog Figure 7-7. Initiating a Byte or Word Write From Flash ; Byte or word write from flash. ; Assumes 0x0FF1E is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT MOV #FWPW,&FCTL3 ; Clear LOCK MOV #FWPW+WRT,&FCTL1 ; Enable write MOV #0123h,&0FF1Eh ; 0123h -> 0x0FF1E MOV #FWPW,&FCTL1 ; Done. Clear WRT MOV #FWPW+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT? SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 351 Flash Memory Operation 7.3.2.3 Initiating Byte or Word Write From RAM The flow to initiate a byte or word write from RAM is shown in Figure 7-8. Disable watchdog Yes BUSY = 1 Setup flash controller and set WRT = 1 Write byte or word Yes BUSY = 1 Set WRT = 0, LOCK = 1, Reenable watchdog Figure 7-8. Initiating a Byte or Word Write From RAM ; Byte or word write from RAM. ; Assumes 0x0FF1E is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWPW,&FCTL3 ; Clear LOCK MOV #FWPW+WRT,&FCTL1 ; Enable write MOV #0123h,&0FF1Eh ; 0123h -> 0x0FF1E L2 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L2 ; Loop while busy MOV #FWPW,&FCTL1 ; Clear WRT MOV #FWPW+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT? www.ti.com 352 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Operation 7.3.2.4 Long-Word Write A long-word write operation can be initiated from within flash memory or from RAM. The BUSY bit is set to 1 after 32 bits are written to the flash controller and the programming cycle starts. When initiating from within flash memory, the CPU is held while the write completes. After the write completes, the CPU resumes code execution with the instruction following the write access. The long-word write timing is shown in Figure 7-6. A long-word consists of four consecutive bytes aligned to at 32-bit address (only the lower two address bits are different). The bytes can be written in any order or any combination of bytes and words. If a byte or word is written more than once, the last data written to the four bytes are stored into the flash memory. If a write to a flash address outside of the 32-bit address happens before all four bytes are available, the data written so far is discarded, and the latest byte or word written defines the new 32-bit aligned address. When 32 bits are available, the write cycle is executed. When executing from RAM, the CPU continues to execute code. The BUSY bit must be zero before the CPU accesses flash again, otherwise an access violation occurs, ACCVIFG is set, and the write result is unpredictable. In long-word write mode, the internally-generated programming voltage is applied to a complete 128-byte block. The cumulative programming time, tCPT, must not be exceeded for any block. Each write adds to the cumulative program time of a segment. If the maximum cumulative program time is reached or exceeded, the segment must be erased. Further programming or using the data returns unpredictable results. With each write, the amount of time the block is subjected to the programming voltage accumulates. If the cumulative programming time is reached or exceeded, the block must be erased before further programming or use (see the device-specific data sheet for specifications). 7.3.2.5 Initiating Long-Word Write From Flash The flow to initiate a long-word write from flash is shown in Figure 7-9. Disable watchdog Setup flash controller and set BLKWRT = 1 Write 4 bytes or 2 words Set BLKWRT = 0, LOCK = 1, Reenable watchdog Figure 7-9. Initiating Long-Word Write From Flash ; Long-word write from flash. ; Assumes 0x0FF1C and 0x0FF1E is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT MOV #FWPW,&FCTL3 ; Clear LOCK MOV #FWPW+BLKWRT,&FCTL1 ; Enable 2-word write MOV #0123h,&0FF1Ch ; 0123h -> 0x0FF1C MOV #45676h,&0FF1Eh ; 04567h -> 0x0FF1E MOV #FWPW,&FCTL1 ; Done. Clear BLKWRT MOV #FWPW+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT? SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 353 Flash Memory Operation 7.3.2.6 Initiating Long-Word Write From RAM The flow to initiate a long-word write from RAM is shown in Figure 7-10. Disable watchdog Yes BUSY = 1 Setup flash controller and set BLKWRT = 1 Write 4 bytes or 2 words Yes BUSY = 1 Set BLKWRT=0, LOCK = 1, Reenable watchdog Figure 7-10. Initiating Long-Word Write from RAM ; Two 16-bit word writes from RAM. ; Assumes 0x0FF1C and 0x0FF1E is already erased ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWPW,&FCTL3 ; Clear LOCK MOV #FWPW+BLKWRT,&FCTL1 ; Enable write MOV #0123h,&0FF1Ch ; 0123h -> 0x0FF1C MOV #4567h,&0FF1Eh ; 4567h -> 0x0FF1E L2 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L2 ; Loop while busy MOV #FWPW,&FCTL1 ; Clear WRT MOV #FWPW+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT? www.ti.com 354 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Operation 7.3.2.7 Block Write The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed. The flash programming voltage remains on for the duration of writing the 128byte row. The cumulative programming time, tCPT, must not be exceeded for any row during a block write. Only long-word writes are possible using block write mode. A block write cannot be initiated from within flash memory. The block write must be initiated from RAM. The BUSY bit remains set throughout the duration of the block write. The WAIT bit must be checked between writing four bytes, or two words, to the block. When WAIT is set, then four bytes, or two 16-bit words, of the block can be written. When writing successive blocks, the BLKWRT bit must be cleared after the current block is completed. BLKWRT can be set initiating the next block write after the required flash recovery time given by tEND. BUSY is cleared following each block write completion, indicating the next block can be written. Figure 7-11 shows the block write timing. The first long-word write requires tBlock,0 and the last long-write requires tBlock,N. All other blocks require t . Block,1-(N-1) BLKWRT bit Write to Flash; e.g., MOV #0123h, &Flash MOV #4567h, &Flash1 Generate Programming Voltage Programming Operation Active Remove Programming Voltage BUSY Cumulative Programming Time < tCPT, VCC Current Consumption is Increased WAIT tBlock,0 tBlock,1–(N-1) tBlock,N Figure 7-11. Block-Write Cycle Timing SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 355 Flash Memory Operation 7.3.2.8 Block Write Flow and Example A block write flow is shown in Figure 7-12 and the following code example. Disable watchdog Yes BUSY = 1 Setup flash controller Set BLKWRT = WRT = 1 Write 4 bytes or 2 words Yes WAIT = 0? No Block Border? Set BLKWRT=0 Yes BUSY = 1 Yes Another Block? Set WRT = 0, LOCK = 1, Reenable WDT Figure 7-12. Block Write Flow www.ti.com 356 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ; Write one block starting at 0F000h. ; Must be executed from RAM, Assumes Flash is already erased. ; Assumes ACCVIE = NMIIE = OFIE = 0. MOV #32,R5 ; Use as write counter MOV #0F000h,R6 ; Write pointer MOV #WDTPW+WDTHOLD,&WDTCTL ; Disable WDT L1 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L1 ; Loop while busy MOV #FWPW,&FCTL3 ; Clear LOCK MOV #FWPW+BLKWRT+WRT,&FCTL1 ; Enable block write L2 MOV Write_Value1,0(R6) ; Write 1st location MOV Write_Value2,2(R6) ; Write 2nd word L3 BIT #WAIT,&FCTL3 ; Test WAIT JZ L3 ; Loop while WAIT=0 INCD R6 ; Point to next words INCD R6 ; Point to next words DEC R5 ; Decrement write counter JNZ L2 ; End of block? MOV #FWPW,&FCTL1 ; Clear WRT, BLKWRT L4 BIT #BUSY,&FCTL3 ; Test BUSY JNZ L4 ; Loop while busy MOV #FWPW+LOCK,&FCTL3 ; Set LOCK ... ; Re-enable WDT if needed Flash Memory Operation 7.3.3 Flash Memory Access During Write or Erase When a write or an erase operation is initiated from RAM while BUSY = 1, the CPU may not write to any flash location. Otherwise, an access violation occurs, ACCVIFG is set, and the result is unpredictable. ACCVIFG is also set if a Flash write or erase access is attempted without any Flash write or erase mode selected first. When a write operation is initiated from within flash memory, the CPU continues code execution with the next instruction fetch after the write cycle completed (BUSY = 0). The op-code 3FFFh is the JMP PC instruction. This causes the CPU to loop until the flash operation is finished. When the operation is finished and BUSY = 0, the flash controller allows the CPU to fetch the opcode and program execution resumes. The flash access conditions while BUSY = 1 are listed in Table 7-4. Flash Operation Bank erase Segment erase Word or byte write or long-word write Block write Table 7-4. Flash Access While Flash is Busy (BUSY = 1) Flash Access Read Write Instruction fetch Read Write Instruction fetch Read Write Instruction fetch Any Read Write Instruction fetch WAIT 0 0 0 0 0 0 0 0 0 0 1 1 1 Result From the erased bank: ACCVIFG = 0. 03FFFh is the value read. From any other flash location: ACCVIFG = 0. Valid read. ACCVIFG = 1. Write is ignored. From the erased bank: ACCVIFG = 0. CPU fetches 03FFFh. This is the JMP PC instruction. From any other flash location: ACCVIFG = 0. Valid instruction fetch. ACCVIFG = 0: 03FFFh is the value read. ACCVIFG = 1: Write is ignored. ACCVIFG = 0: CPU fetches 03FFFh. This is the JMP PC instruction. ACCVIFG = 0: 03FFFh is the value read. ACCVIFG = 1: Write is ignored. ACCVIFG = 0: CPU fetches 03FFFh. This is the JMP PC instruction. ACCVIFG = 1: LOCK = 1, block write is exited. ACCVIFG = 0: 03FFFh is the value read. ACCVIFG = 0: Valid write ACCVIFG = 1: LOCK = 1, block write is exited SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 357 Flash Memory Operation www.ti.com Interrupts are automatically disabled during any flash operation. The watchdog timer (in watchdog mode) should be disabled before a flash erase cycle. A reset aborts the erase and the result is unpredictable. After the erase cycle has completed, the watchdog may be reenabled. 7.3.4 Stopping Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX. Setting the EMEX bit stops the active operation and resets the flash controller. All flash operations cease, the flash returns to read mode, and all bits in the FCTL1 register are reset. The LOCK bit of FCTL3 is set. The result of the intended operation is unpredictable. 7.3.4.1 EMEX With Single Bank Flash Memory For devices with single bank flash memories, write and erase operations initiated from flash, the CPU is held until the flash operation completes. Therefore it is not possible to perform an emergency exit by the EMEX bit. The emergency exit of write or erase operations initiated from RAM can be performed using the EMEX bit. The BUSY bit is used to determine the end of the emergency exit cycle. The user must ensure that code execution does not continue until the BUSY bit is cleared by the flash controller. 7.3.4.2 EMEX With Multiple Bank Flash Memory For devices with multiple bank flash memories, write and segment erase operations initiated from flash, regardless of which bank the code resides in, the CPU is held until the flash operation completes. Therefore it is not possible to perform an emergency exit by the EMEX bit. For bank erase, there is a possibility to perform an EMEX if the bank being erased is not where the code resides. The BUSY bit is used to determine the end of the emergency exit cycle. The user must ensure that code execution does not continue until the BUSY bit is cleared by the flash controller. The emergency exit of write or any erase operations initiated from RAM can be performed using the EMEX bit. The BUSY bit is used to determine the end of the emergency exit cycle. The user must ensure that code execution does not continue until the BUSY bit is cleared by the flash controller. 7.3.5 Checking Flash Memory The result of a programming cycle of the flash memory can be checked by calculating and storing a checksum (CRC) of parts or the complete flash memory content. The CRC module can be used for this purpose (see the device-specific data sheet). During the runtime of the system, the known checksums can be recalculated and compared with the expected values stored in the flash memory. The program checking the flash memory content is executed in RAM. To get an early indication of weak memory cells, reading the flash can be done in combination with the device-specific marginal read modes. The marginal read modes are controlled by the FCTL4.MRG0 and FCTL4.MRG1 register bits if available (device specific). During marginal read mode, marginally programmed flash memory bit locations can be detected. One method for identifying such memory locations would be to periodically perform a checksum calculation over a section of flash memory (for example, a flash segment) and repeating this procedure with the marginal read mode enabled. If they do not match, it could indicate an insufficiently programmed flash memory location. It is possible to refresh the affected Flash memory segment by disabling marginal read mode, copying to RAM, erasing the flash segment, and writing back to it from RAM. The program checking the flash memory contents must be executed from RAM. Executing code from flash automatically disables the marginal read mode. The marginal read modes are controlled by the MRG0 and MRG1 register bits. Setting MRG1 is used to detect insufficiently programmed flash cells containing a "1" (erased bits). Setting MRG0 is used to detect insufficiently programmed flash cells containing a "0" (programmed bits). Only one of these bits should be set at a time. Therefore, a full marginal read check requires two passes of checking the flash memory content’s integrity. During marginal read mode, the flash access speed (MCLK) must be limited to 1 MHz (see the device-specific data sheet). 358 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Flash Memory Operation 7.3.6 Configuring and Accessing the Flash Memory Controller The FCTLx registers are 16-bit password-protected read and write registers. Any read or write access must use word instructions, and write accesses must include the write password 0A5h in the upper byte. Any write to any FCTLx register with a value other than 0A5h in the upper byte is a password violation, sets the KEYV flag, and triggers a PUC system reset. Any read of any FCTLx registers reads 096h in the upper byte. Any write to FCTL1 during an erase or byte, word, double-word write operation is an access violation and sets ACCVIFG. Writing to FCTL1 is allowed in block write mode when WAIT = 1, but writing to FCTL1 in block write mode when WAIT = 0 is an access violation and sets ACCVIFG. Any write to FCTL2 (this register is currently not implemented) when BUSY = 1 is an access violation. Any FCTLx register may be read when BUSY = 1. A read does not cause an access violation. 7.3.7 Flash Memory Controller Interrupts The flash controller has two interrupt sources, KEYV and ACCVIFG. ACCVIFG is set when an access violation occurs. When the ACCVIE bit is reenabled after a flash write or erase, a set ACCVIFG flag generates an interrupt request. The ACCVIE bit resides in the Special Function Register, SFRIE1 (see the SYS chapter for details). ACCVIFG sources the NMI interrupt vector, so it is not necessary for GIE to be set for ACCVIFG to request an interrupt. ACCVIFG may also be checked by software to determine if an access violation occurred. ACCVIFG must be reset by software. The password violation flag, KEYV, is set when any of the flash control registers are written with an incorrect password. When this occurs, a PUC is generated immediately, resetting the device. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 359 Flash Memory Operation www.ti.com 7.3.8 Programming Flash Memory Devices There are three options for programming a flash device. All options support in-system programming. • Program through JTAG (Section 7.3.8.1) • Program through the BSL (Section 7.3.8.2) • Program through a custom solution (Section 7.3.8.3) 7.3.8.1 Programming Flash Memory Through JTAG Devices can be programmed through the JTAG port. The JTAG interface requires four signals (five signals on 20- and 28-pin devices), ground, and optionally VCC and RST/NMI. The JTAG port is protected with a fuse. Blowing the fuse completely disables the JTAG port and is not reversible. Further access to the device through JTAG is not possible. For more details, see the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320). 7.3.8.2 Programming Flash Memory Via Bootstrap Loader (BSL) Every flash device contains a BSL. The BSL enables users to read or program the flash memory or RAM using a UART serial interface. Access to the flash memory through the BSL is protected by a 256-bit userdefined password. For more details, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319). 7.3.8.3 Programming Flash Memory Through Custom Solution The ability of the MSP430 CPU to write to its own flash memory allows for in-system and external custom programming solutions as shown in Figure 7-13. The user can choose to provide data through any means available (for example, UART or SPI). User-developed software can receive the data and program the flash memory. Because this type of solution is developed by the user, it can be completely customized to fit the application needs for programming, erasing, or updating the flash memory. Host MSP430 Commands, data, etc. Flash memory UART, Px.x, SPI, etc. CPU executes user software Read/write flash memory Figure 7-13. User-Developed Programming Solution 360 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com FCTL Registers 7.4 FCTL Registers The flash memory controller (FCTL) registers are listed in Table 7-5. The base address can be found in the device-specific data sheet. The address offset is given in Table 7-5. NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15). Offset 00h 00h 01h 04h 04h 05h 06h 06h 07h Acronym FCTL1 FCTL1_L FCTL1_H FCTL3 FCTL3_L FCTL3_H FCTL4 FCTL4_L FCTL4_H Table 7-5. FCTL Registers Register Name Flash Memory Control 1 Flash Memory Control 3 Flash Memory Control 4 Type Read/write Read/Write Read/Write Read/write Read/Write Read/Write Read/write Read/Write Read/Write Access Word Byte Byte Word Byte Byte Word Byte Byte Reset 9600h 00h 96h 9658h 58h 96h 9600h 00h 96h Section Section 7.4.1 Section 7.4.2 Section 7.4.3 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 361 FCTL Registers 7.4.1 FCTL1 Register Flash Memory Control 1 Register 15 7 BLKWRT rw-0 14 6 WRT rw-0 13 5 SWRT rw-0 Figure 7-14. FCTL1 Register 12 11 10 FRPW/FWPW 4 3 Reserved r-0 r-0 2 MERAS rw-0 www.ti.com 9 1 ERASE rw-0 8 0 Reserved r-0 Bit 15-8 7 Field FRPW/FWPW BLKWRT 6 WRT 5 SWRT 4-3 Reserved 2 MERAS 1 ERASE 0 Reserved Type RW RW RW RW R R Table 7-6. FCTL1 Register Description Reset 96h 0h 0h 0h 0h 0h Description FCTL password. Always read as 096h. Must be written as 0A5h or a PUC is generated. Block write. BLKWRT and WRT are used together to select the write mode. The values shown below are for BLKWRT-WRT. 0-0 = Reserved 0-1 = Byte or word write 1-0 = Long-word write 1-1 = Long-word block write Write. BLKWRT and WRT are used together to select the write mode. The values shown below are for BLKWRT-WRT. 0-0 = Reserved 0-1 = Byte or word write 1-0 = Long-word write 1-1 = Long-word block write Smart write. If this bit is set, the program time is shortened. The programming quality has to be checked by marginal read modes. Reserved. Always reads as 0. Mass erase. MERAS and ERASE are used together to select the erase mode. MERAS and ERASE are automatically reset when EMEX is set or a flash erase operation has completed. The values shown below are for MERAS-ERASE. 0-0 = No erase 0-1 = Segment erase 1-0 = Bank erase (erase of one bank) 1-1 = Mass erase (erase all flash memory banks) Erase. MERAS and ERASE are used together to select the erase mode. MERAS and ERASE are automatically reset when EMEX is set or a flash erase operation has completed. The values shown below are for MERAS-ERASE. 0-0 = No erase 0-1 = Segment erase 1-0 = Bank erase (erase of one bank) 1-1 = Mass erase (erase all flash memory banks) Reserved. Always reads as 0. 362 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.4.2 FCTL3 Register Flash Memory Control 3 Register 15 7 Reserved r-0 14 6 LOCKA rw-1 13 5 EMEX rw-0 Figure 7-15. FCTL3 Register 12 11 10 FRPW/FWPW 4 LOCK rw-1 3 WAIT r-1 2 ACCVIFG rw-0 FCTL Registers 9 1 KEYV rw-(0) 8 0 BUSY r-0 Bit 15-8 7 6 Field FRPW/FWPW Reserved LOCKA 5 EMEX 4 LOCK 3 WAIT 2 ACCVIFG 1 KEYV 0 BUSY Type RW R RW RW RW R RW RW R Table 7-7. FCTL3 Register Description Reset 96h 0h 1h 0h 1h 1h 0h 0h 0h Description FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC is generated. Reserved. Always reads as 0. Segment A lock. Write a 1 to this bit to change its state. Writing 0 has no effect. 0b = Segment A of the information memory is unlocked and can be written or erased in segment erase mode. 1b = Segment A of the information memory is locked and can not be written or erased in segment erase mode. Emergency exit. Setting this bit stops any erase or write operation. The LOCK bit is set. 0b = No emergency exit 1b = Emergency exit Lock. This bit unlocks the flash memory for writing or erasing. The LOCK bit can be set any time during a byte or word write or erase operation, and the operation completes normally. In the block write mode, if the LOCK bit is set while BLKWRT = WAIT = 1, BLKWRT and WAIT are reset and the mode ends normally. 0b = Unlocked 1b = Locked Wait. Indicates the flash memory is being written to. 0b = Flash memory is not ready for the next byte or word write. 1b = Flash memory is ready for the next byte or word write. Access violation interrupt flag 0b = No interrupt pending 1b = Interrupt pending Flash password violation. This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set. KEYV must be reset with software. 0b = FCTLx password was written correctly. 1b = FCTLx password was written incorrectly. Busy. This bit indicates if the flash is currently busy erasing or programming. 0b = Not busy 1b = Busy SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 363 FCTL Registers 7.4.3 FCTL4 Register Flash Memory Control 4 Register Figure 7-16. FCTL4 Register 15 14 13 12 11 10 9 FRPW/FWPW 7 LOCKINFO rw-0 6 Reserved r-0 5 MRG1 rw-0 4 MRG0 rw-0 3 2 1 Reserved r-0 r-0 r-0 www.ti.com 8 0 VPE rw-0 Bit 15-8 7 6 5 Field FRPW/FWPW LOCKINFO Reserved MRG1 4 MRG0 3-1 Reserved 0 VPE Type RW RW R RW RW R RW Table 7-8. FCTL4 Register Description Reset 96h 0h 0h 0h 0h 0h 0h Description FCTLx password. Always reads as 096h. Must be written as 0A5h or a PUC is generated. Lock information memory. If set, the information memory cannot be erased in segment erase mode and cannot be written to. Reserved. Always reads as 0. Marginal read 1 mode. This bit enables the marginal 1 read mode. The marginal read 1 bit is valid for reads from the flash memory only. During a fetch cycle, the marginal mode is turned off automatically. If both MRG1 and MRG0 are set, MRG1 is active and MRG0 is ignored. 0b = Marginal 1 read mode is disabled. 1b = Marginal 1 read mode is enabled. Marginal read 0 mode. This bit enables the marginal 0 read mode. The marginal read 1 bit is valid for reads from the flash memory only. During a fetch cycle, the marginal mode is turned off automatically. If both MRG1 and MRG0 are set, MRG1 is active and MRG0 is ignored. 0b = Marginal 0 read mode is disabled. 1b = Marginal 0 read mode is enabled. Reserved. Always reads as 0. Voltage changed during program error. This bit is set by hardware and can only be cleared by software. If DVCC changed significantly during programming, this bit is set to indicate an invalid result. The ACCVIFG bit is set if VPE is set. 364 Flash Memory Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 7.4.4 SFRIE1 Register Interrupt Enable 1 Register 15 14 13 OTHER 7 6 5 ACCVIE rw-0 Figure 7-17. SFRIE1 Register 12 11 10 4 3 2 FCTL Registers 9 8 1 0 Bit 15-6 5 Field ACCVIE 4-0 Type RW Table 7-9. SFRIE1 Register Description Reset 0h Description These bits may be used by other modules (see the device-specific data sheet and the SYS chapter for details). Flash memory access violation interrupt enable. This bit enables the ACCVIFG interrupt. Because other bits in SFRIE1 may be used for other modules, it is recommended to set or clear this bit using BIS or BIC instructions, rather than MOV or CLR instructions. See the SYS chapter for more details. 0b = Interrupt not enabled 1b = Interrupt enabled These bits may be used by other modules (see the device-specific data sheet and the SYS chapter for details). SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory Controller 365 Chapter 8 SLAU208O – June 2008 – Revised May 2015 Memory Integrity Detection (MID) Memory Integrity Detection (MID) is a program and data protection mechanism that is available on several device families (for example, MSP430F6659). It provides a high level of operation safety for fault-critical application areas. This chapter explains how to use the firmware for the level of operational safety and overall fault response that suits different applications. Topic ........................................................................................................................... Page 8.1 MID Overview................................................................................................... 367 8.2 Flash Memory With MID Support ........................................................................ 368 8.3 MID Parity Check Logic ..................................................................................... 368 8.4 Detecting Unprogrammed Memory Accesses....................................................... 369 8.5 MID ROM ......................................................................................................... 369 8.6 MID Support Software Function.......................................................................... 369 8.7 User's UNMI Interrupt Handler............................................................................ 373 366 Memory Integrity Detection (MID) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MID Overview 8.1 MID Overview The MID is an add-on to the MSP430 flash memory controller. MID provides additional functionality over the regular flash operation methods as described in the Flash Memory Controller chapter. The main purpose of the MID function is to help gain higher reliability of flash content and overall system integrity in harsh environments and in applications requiring such features. The additional level of security is reached by calculating parity information. The complete MID solution consists of the blocks Parity Generator and Parity Check and MID ROM. The Parity Generator and Parity Check provides all of the necessary logic elements needed to identify bit errors in the whole memory array. The on-chip MID ROM contains the MID Support Software, and this software performs all the necessary tasks to operate MID. The built-in MID functions provide all functionality to use the MID features. MAB MDB Control Registers Address/Data Latch Parity Generator and Parity Check MID ROM (Preprogrammed MID support software allows control of MID hardware) MID Parity Information (horizontal Parity Bits) Timing Generator Programming Voltage Generator Flash Memory Array (plain data) MSP430 Flash Memory Controller MID Add-on Figure 8-1. Block Diagram of MID Implementation SLAU208O – June 2008 – Revised May 2015 Memory Integrity Detection (MID) 367 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Flash Memory With MID Support www.ti.com 8.2 Flash Memory With MID Support The MSP430 flash memory is partitioned into different memory areas—main and information memory, banks, segments, and memory blocks—where MID protection can be enabled. Figure 8-2 shows an example for a typical MSP430 flash segmentation including the MID feature. MSP430 Flash Memory Main Memory Banks Bank 3 Bank 2 Bank 1 Bank 0 Segments ... ... ... ... MID Flash Memory Blocks Enable bits (see Note 1) ¬ CW0.15 ¬ CW0.14 ¬ CW0.13 ¬ CW0.12 ¬ CW0.11 ¬ CW0.10 ¬ CW0.9 ¬ CW0.8 ¬ CW0.7 ¬ CW0.6 ¬ CW0.5 ¬ CW0.4 ¬ CW0.3 ¬ CW0.2 ¬ CW0.1 ¬ CW0.0 Information Memory Bootstrap Loader (BSL) Info A Info B Info C Info D BSL 3 BSL 2 BSL 1 BSL 0 Info A Info B Info C Info D BSL 3 BSL 2 BSL 1 BSL 0 ¬ CW1.4 ¬ CW1.5 ¬ CW1.6 ¬ CW1.7 ¬ CW1.3 ¬ CW1.2 ¬ CW1.1 ¬ CW1.0 (1) The cw0.x and cw1.x bits are used to enable MID functionality for the individual memory ranges. Further information can be found in Section 8.6.1. Figure 8-2. Overview of MSP430 Flash Memory Segmentation The whole flash memory array consist of MID supported flash memory blocks. For a device with 512KB of flash main memory, each MID flash memory block has a size of 32KB (main memory divided by 16). Each row consists of one word of plain data (16 bits) and a horizontal parity bit (H-parity bit). Erased segments show all ones in the data array field and horizontal parity. Writing to flash memory (with MID after reset) automatically writes the horizontal parity bits along with the data bits. Writing to the plain data field can, of course, be interrupted and continued in any order. Adding content after the horizontal parity has been written is impractical, as the horizontal parity information changes as well. The whole segment (not just a single MID memory block) would need to be erased before it can be written again. The shown method is excellent for data content of static nature like code, tables, and so on. For data acquisition into flash, other methods (for example, majority vote) are more suitable; but complete blocks of acquisition data can be protected with this method again. 8.3 MID Parity Check Logic Any access to MID enabled flash memory causes a verification of its horizontal parity in the background. It does not matter if code or data is read from the flash memory. If a parity error is detected, the bus error event "parity error" is triggered and calls the user NMI exception handler. The application software can then react on the failure by, for example, showing an error message on the application's display. 368 Memory Integrity Detection (MID) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Detecting Unprogrammed Memory Accesses 8.4 Detecting Unprogrammed Memory Accesses All bits are set after erasing the flash memory; this also includes the horizontal parity bit. If an erased memory range is accessed, the MID causes a NMI interrupt, because of a detected parity failure. Only programmed addresses are accessible without a MID failure interrupt; that is especially the case for the content 0xFFFF. If memory content should be 0xFFFF, it must be programmed. This ensures that the horizontal parity bit is cleared (0). Enabling the MID functionality for nonprogrammed memory ranges allows detecting memory accesses to these nonprogrammed addresses. 8.5 MID ROM The MID ROM is 1KB of read-only memory. The on-chip MID ROM is factory programmed with MID support software. These software functions are used to enable or disable the MID module. The start address of the MID ROM depends on the MSP430 device; see the device-specific data sheet for specifications. 8.6 MID Support Software Function The MID is disabled by default after power-up of the device. To use the MID feature, it must be enabled within the application software. Enabling is done by calling the MidInit() function with parameters that define which MID memory blocks should be enabled or disabled. Table 8-1 list all existing MID functions. These functions are stored in the MID ROM; its start address is defined in the device-specific data sheet. Function Revision MidEnable MidDisable MidGetErrAdr MidCheckMem MidSetRaw MidGetParity MidCalcVParity Reserved Reserved Reserved Reserved Table 8-1. Overview of MID Support Software Functions Address Offset 0x00 0x02 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C Description Content of address: 2843h Content of address: 80xyh, xy is the revision word Initialization and enabling of MID MID is disabled Returns the error location Memory check is performed Writing a data word and parity bit into a defined address Read out horizontal parity bit Calculating vertical parity SLAU208O – June 2008 – Revised May 2015 Memory Integrity Detection (MID) 369 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated MID Support Software Function www.ti.com 8.6.1 MidEnable() Function Function void MidEnable(unsigned short cw0,unsigned short cw1); Function Description This function initializes and enables MID. The argument cw0 and cw1 allow an explicit control what MID flash memory blocks are to be protected. MID feature is disabled after a power-up or BOR. MidEnable() function is expected to be called early after application start. Calling it again later reconfigures the settings. Parameters Name cw0 cw1 Type unsigned short R12.W unsigned short R13.W Description Configuration word 0. It is used to activate the MID feature for certain memory ranges. The main memory is divided into 16 blocks. The LSB bit of cw0 activates the lowest address range (see Figure 8-3). Configuration word 1. This bit is used the same as cw0, the only difference is that BAL and Info memory are used instead of main memory (see Figure 8-4). 15 cw0.15 7 cw0.7 14 cw0.14 6 cw0.6 13 cw0.13 5 cw0.5 Figure 8-3. cw0 Parameter 12 11 10 cw0.12 cw0.11 cw0.10 4 cw0.4 3 cw0.3 2 cw0.2 9 cw0.9 1 cw0.1 8 cw0.8 0 cw0.0 Bit 15-0 Field cw0.x 15 Reserved 7 cw1.7 14 Reserved 6 cw1.6 Description Main memory is split into MID flash memory blocks. Each MID flash memory block has a size of main memory divided by 16 (for example, for a 512KB main memory, the MID memory block size is 32KB). The cw0.x bits allow to enable MID support for the different flash memory blocks. For example, cw0.0 activates the lowest flash memory block, and cw0.15 activates the highest flash memory block. 0 = MID support is deactivated 1 = MID support is active 13 Reserved 5 cw1.5 Figure 8-4. cw1 Parameter 12 11 10 Reserved Reserved Reserved 4 cw1.4 3 cw1.3 2 cw1.2 9 Reserved 1 cw1.1 8 Reserved 0 cw1.0 Bit 15-8 7 6 5 4 Field Reserved cw1.7 cw1.6 cw1.5 cw1.4 Description These bits are reserved. It is strongly recommended to reset (0) these bits. Enables or disables MID for the flash information memory segment D. 0 = MID support is deactivated 1 = MID support is active Enables or disables MID for the flash information memory segment C. 0 = MID support is deactivated 1 = MID support is active Enables or disables MID for the flash information memory segment B. 0 = MID support is deactivated 1 = MID support is active Enables or disables MID for the flash information memory segment A. 0 = MID support is deactivated 1 = MID support is active 370 Memory Integrity Detection (MID) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Bit Field 3 cw1.3 2 cw1.2 1 cw1.1 0 cw1.0 MID Support Software Function Description Enables or disables MID for the bootstrap loader memory 3. 0 = MID support is deactivated 1 = MID support is active Enables or disables MID for the bootstrap loader memory 2. 0 = MID support is deactivated 1 = MID support is active Enables or disables MID for the bootstrap loader memory 1. 0 = MID support is deactivated 1 = MID support is active Enables or disables MID for the bootstrap loader memory 0. 0 = MID support is deactivated 1 = MID support is active 8.6.2 MidDisable() Function Function void MidDisable(void); Function Description This function clears the cw0 and cw1 parameters that were set during MidEnable() function call and it disables the MID hardware. 8.6.3 MidGetErrAdr() Function Function unsigned short * MidGetErrAdr(void); Function Description This function returns the error location is there was a memory integrity failure. If there is no valid failure address or error location, the function returns the value F'FFFFh. Note that the MidGetErrAdr() function returns only the correct error address when this function is called prior to a read access of SYSBERRIV register. The code example in Section 8.7 shows where the MidGetErrAdr() function call should be placed. SLAU208O – June 2008 – Revised May 2015 Memory Integrity Detection (MID) 371 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated MID Support Software Function www.ti.com 8.6.4 MidCheckMem() Function Function void MidCheckMem(unsigned short * startAdr, unsigned short * endAdr); Function Description This function allows doing a memory integrity check. First, the MidEnable function should be called. This function enables MID and it defines the memory blocks that should be protected. After that the MidCheckMem function can be called. Its parameter list defines an address range that is accessed with wordwise reads. An UNMI interrupt (MID interrupt) is generated in case a parity error occurs and the read address is enabled for MID protection. Parameters Name startAdr endAdr Type unsigned short *R12.W unsigned short R13.W Description Start address for the memory integrity check. The startAdr must be an even number. End address for the memory integrity check. The endAdr must be an even number. The address defined with endAdr is included in the memory integrity check. 8.6.5 MidSetRaw() Function Function void MidSetRaw(unsigned short data, unsigned short parity, unsigned short * adr, unsigned short flashKey); Function Description This function writes one word (data) and a separately definable parity bit (parity) to an MID memory address (adr). The Flash memory key is needed to allow access to flash control registers; this parameter is passed through the argument flashKey (see the follwoing example). Parameters Name data parity adr flashKey Type unsigned short R12.W unsigned short R13.W unsigned short *R14.A unsigned short R15.W Data to be written Description If parity = 0, the parity bit 0 is written. If parity <> 0, the parity bit 1 is written. Destination address where raw information is written Flash memory key. This is needed to allow the MidSetRaw function access to the flash control registers. The passing parameter is usually defined in the standard MSP430 header files; therefore, "FWKEY" can be used here. Example #include const unsigned short FlashAdr=0xFF00; // Flash memory address will be reprogrammed void main(void) { static unsigned short Data; // variable for data the will be read static unsigned short Parity; // H-parity bit that will be read WDTCTL=WTDPW+WDTHOLD; // disable Watchdog Data=0x5A5A; // data that will be written into flash memory Parity=0; // parity bit that will be written MIDSetRaw(Data,Parity,&FlashAdr,FWKEY); // write data and parity bit while(1); } 372 Memory Integrity Detection (MID) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com MID Support Software Function 8.6.6 MidGetParity() Function Function unsigned short MidGetParity(unsigned short * adr); Function Description This function returns the parity bit of the appropriate address. Reading the parity bit works only when MID was enabled before calling MidGetParity() function and the appropriate MID memory block is enabled. Parameters Name adr Type unsigned short *R12.A Description Defines the address where the parity bit should be read. 8.6.7 MidCalcVParity() Function Function unsigned short MidCalcVParity(unsigned short * startAdr, unsigned short * endAdr); Function Description This function allows to calculate a vertical parity for a defined memory range. Parameters Name startAdr endAdr Type unsigned short *R12.A unsigned short *R13.A Description Defines the start address for calculating vertical parity. The startAdr must be an even number. End address for calculating vertical parity. The endAdr must be an even number. The address defined with endAdr is included in the vertical parity calculation. 8.7 User's UNMI Interrupt Handler If an error is detected, the on-chip MID generates an UNMI interrupt. The application software must manage error handling. UNMI handler framework for MID error handling: __interrupt void unmi_isr(void) { switch(__even_in_range(SYSUNIV, 0x08)) { case 0x00: break; case 0x02: break; // NMIIFG case 0x04: break; // OFIFG case 0x06: break; // ACCVIFG case 0x08: // BUSIFG // If needed, obtain the flash error location here. ErrorLocation = MidGetErrAdr(); default: } switch(__even_in_range(SYSBERRIV, 0x08)) { case 0x00: break; // no bus error case 0x02: break; // USB bus error case 0x04: break; // reserved case 0x06: // MID error break; case 0x08: break; default: break; } break; break; SLAU208O – June 2008 – Revised May 2015 Memory Integrity Detection (MID) 373 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Chapter 9 SLAU208O – June 2008 – Revised May 2015 RAM Controller (RAMCTL) The RAM controller (RAMCTL) allows control of the operation of the RAM. Topic ........................................................................................................................... Page 9.1 RAM Controller (RAMCTL) Introduction............................................................... 375 9.2 RAMCTL Operation ........................................................................................... 375 9.3 RAMCTL Registers ........................................................................................... 376 374 RAM Controller (RAMCTL) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com RAM Controller (RAMCTL) Introduction 9.1 RAM Controller (RAMCTL) Introduction The RAMCTL provides access to the different power modes of the RAM. The RAMCTL enters retention mode to reduce the leakage current while the CPU is off. The RAM can also be switched off by software. In retention mode, the RAM content is saved. In off mode, the RAM content is lost. The RAM is partitioned in sectors, typically of 4KB (sector) size. See the device-specific data sheet for actual block allocation and size. Each sector is controlled by the RAM controller RAM Sector Off control bit (RCRSyOFF) of the RAMCTL Control 0 register (RCCTL0). The RCCTL0 register is protected with a key. The RCCTL0 register content can be modified only if the correct key is written during a word write. Byte write accesses or write accesses with a wrong key are ignored. 9.2 RAMCTL Operation Active mode In active mode, the RAM can be read and written at any time. If any RAM address in a sector must hold data, the whole sector cannot be switched off. Low-power modes In all low-power modes, the CPU is switched off. As soon as the CPU is switched off, the RAM enters retention mode to reduce the leakage current. RAM off mode Each sector can be turned off independent of the other sectors by setting the respective RCRSyOFF bit to 1. Reading from a switched off RAM sector returns 0 as data. All data previously stored in a switched off RAM sector is lost and cannot be read, even if the sector is turned on again. Stack pointer The program stack is located in RAM. Sectors holding the stack must not be turned off if an interrupt must be executed or if a low-power mode is entered. USB buffer memory On devices with USB, the USB buffer memory is located in RAM. Sector 7 is used for this purpose. RCRS7OFF can be set to switch off this memory if it is not required for USB operation or is not being used in normal operation. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated RAM Controller (RAMCTL) 375 RAMCTL Registers www.ti.com 9.3 RAMCTL Registers The RAMCTL module register is listed in Table 9-1. The base address can be found in the device-specific data sheet. The address offset is given in Table 9-1. NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15). Offset 00h 00h 01h Table 9-1. RAMCTL Registers Acronym Register Name RCCTL0 RAM Controller Control 0 RCCTL0_L RCCTL0_H Type Read/write Read/write Read/write Access Word Byte Byte Reset 6900h 00h 69h Section Section 9.3.1 376 RAM Controller (RAMCTL) SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 9.3.1 RCCTL0 Register RAM Controller Control 0 Register 15 14 13 rw-0 7 RCRS7OFF rw-0 rw-1 6 RCRS6OFF rw-0 rw-1 5 RCRS5OFF rw-0 Figure 9-1. RCCTL0 Register 12 11 10 RCKEY rw-0 rw-1 rw-0 4 RCRS4OFF rw-0 3 RCRS3OFF rw-0 2 RCRS2OFF rw-0 RAMCTL Registers 9 8 rw-0 1 RCRS1OFF rw-0 rw-1 0 RCRS0OFF rw-0 Bit 15-8 7 Field RCKEY RCRS7OFF 6 RCRS6OFF 5 RCRS5OFF 4 RCRS4OFF 3 RCRS3OFF 2 RCRS2OFF 1 RCRS1OFF 0 RCRS0OFF Type RW RW RW RW RW RW RW RW RW Table 9-2. RCCTL0 Register Description Reset 69h 0h 0h 0h 0h 0h 0h 0h 0h Description RAM controller key. Always read as 69h. Must be written as 5Ah, otherwise the RAMCTL write is ignored. RAM controller RAM sector 7 off. Setting the bit to 1 turns off the RAM sector 7. All data of the RAM sector 7 is lost. See the device-specific data sheet to find the the number of RAM sectors available along with their respective address ranges and sizes. RAM controller RAM sector 6 off. Setting the bit to 1 turns off the RAM sector 6. All data of the RAM sector 6 is lost. See the device-specific data sheet to find the the number of RAM sectors available along with their respective address ranges and sizes. RAM controller RAM sector 5 off. Setting the bit to 1 turns off the RAM sector 5. All data of the RAM sector 5 is lost. See the device-specific data sheet to find the the number of RAM sectors available along with their respective address ranges and sizes. RAM controller RAM sector 4 off. Setting the bit to 1 turns off the RAM sector 4. All data of the RAM sector 4 is lost. See the device-specific data sheet to find the the number of RAM sectors available along with their respective address ranges and sizes. RAM controller RAM sector 3 off. Setting the bit to 1 turns off the RAM sector 3. All data of the RAM sector 3 is lost. See the device-specific data sheet to find the the number of RAM sectors available along with their respective address ranges and sizes. RAM controller RAM sector 2 off. Setting the bit to 1 turns off the RAM sector 2. All data of the RAM sector 2 is lost. See the device-specific data sheet to find the the number of RAM sectors available along with their respective address ranges and sizes. RAM controller RAM sector 1 off. Setting the bit to 1 turns off the RAM sector 1. All data of the RAM sector 1 is lost. See the device-specific data sheet to find the the number of RAM sectors available along with their respective address ranges and sizes. RAM controller RAM sector 0 off. Setting the bit to 1 turns off the RAM sector 0. All data of the RAM sector 0 is lost. See the device-specific data sheet to find the the number of RAM sectors available along with their respective address ranges and sizes. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated RAM Controller (RAMCTL) 377 Chapter 10 SLAU208O – June 2008 – Revised May 2015 Backup RAM The backup RAM is a (volatile) memory that is retained during LPMx.5 and operation from a backup supply (if supported by the device). This chapter describes the backup RAM. Topic ........................................................................................................................... Page 10.1 Backup RAM Introduction and Operation ............................................................ 379 10.2 Battery Backup Registers .................................................................................. 379 378 Backup RAM SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Backup RAM Introduction and Operation 10.1 Backup RAM Introduction and Operation The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during operation from a backup supply (if the device integrates the complete battery backup system). At least one byte or one word (one word is preferred) should be used to generate a checksum of the stored data or to store a signature to ensure that the data is still reliable when returning from LPMx.5 or from backup operation. 10.2 Battery Backup Registers The backup RAM registers are listed in Table 10-1. The base address for the backup RAM registers can be found in the device-specific data sheet. The address offsets are given in Table 10-1. NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15). Offset Acronym 00h 00h 01h 02h 02h 03h 04h 04h 05h 06h 06h 07h BAKMEM0 BAKMEM0_L BAKMEM0_H BAKMEM1 BAKMEM1_L BAKMEM1_H BAKMEM2 BAKMEM2_L BAKMEM2_H BAKMEM3 BAKMEM3_L BAKMEM3_H Table 10-1. Backup RAM Registers Register Name Battery Backup Memory 0 Battery Backup Memory 1 Battery Backup Memory 2 Battery Backup Memory 3 Type Access Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined LPMx.5 Backup Operation retained retained retained retained retained retained retained retained retained retained retained retained SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Backup RAM 379 Chapter 11 SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module The direct memory access (DMA) controller module transfers data from one address to another without CPU intervention. This chapter describes the operation of the DMA controller. Topic ........................................................................................................................... Page 11.1 Direct Memory Access (DMA) Introduction .......................................................... 381 11.2 DMA Operation................................................................................................. 383 11.3 DMA Registers ................................................................................................. 395 380 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Direct Memory Access (DMA) Introduction 11.1 Direct Memory Access (DMA) Introduction The DMA controller transfers data from one address to another, without CPU intervention, across the entire address range. For example, the DMA controller can move data from the ADC conversion memory to RAM. Devices that contain a DMA controller may have up to eight DMA channels available. Therefore, depending on the number of DMA channels available, some features described in this chapter are not applicable to all devices. See the device-specific data sheet for number of channels supported. Using the DMA controller can increase the throughput of peripheral modules. It can also reduce system power consumption by allowing the CPU to remain in a low-power mode, without having to awaken to move data to or from a peripheral. DMA controller features include: • Up to eight independent transfer channels • Configurable DMA channel priorities • Requires only two MCLK clock cycles per transfer • Byte or word and mixed byte and word transfer capability • Block sizes up to 65535 bytes or words • Configurable transfer trigger selections • Selectable-edge or level-triggered transfer • Four addressing modes • Single, block, or burst-block transfer modes Figure 11-1 shows the DMA controller block diagram. SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 381 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Direct Memory Access (DMA) Introduction DMA0TSEL 5 DMA0TRIG0 00000 DMA0TRIG1 00001 DMA0TRIG31 11111 to USB if available DMA1TSEL 5 DMA1TRIG0 00000 DMA1TRIG1 00001 JTAG Active Halt ROUNDROBIN NMI Interrupt Request ENNMI DMADT DMADSTINCR 2 DMADSTBYTE 3 DMA Channel 0 DMA0SA DMA0DA DMA0SZ 2 DMASRSBYTE DMASRCINCR DMAEN DMADT DMADSTINCR 2 DMADSTBYTE 3 DMA Channel1 DMA1SA DMA1DA DMA1SZ Address Space DMA Priority and Control DMA1TRIG31 11111 to USB if available DMAnTSEL 5 DMAnTRIG0 00000 DMAnTRIG1 00001 2 DMASRSBYTE DMASRCINCR DMAEN DMADSTINCR DMADT 2 DMADSTBYTE 3 DMA Channel n DMAnSA DMAnDA DMAnSZ 2 DMASRSBYTE DMAEN DMASRCINCR DMAnTRIG31 11111 DMARMWDIS to USB if available Halt CPU Figure 11-1. DMA Controller Block Diagram www.ti.com 382 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation 11.2 DMA Operation The DMA controller is configured with user software. The setup and operation of the DMA is discussed in the following sections. 11.2.1 DMA Addressing Modes The DMA controller has four addressing modes. The addressing mode for each DMA channel is independently configurable. For example, channel 0 may transfer between two fixed addresses, while channel 1 transfers between two blocks of addresses. The addressing modes are shown in Figure 11-2. The addressing modes are: • Fixed address to fixed address • Fixed address to block of addresses • Block of addresses to fixed address • Block of addresses to block of addresses The addressing modes are configured with the DMASRCINCR and DMADSTINCR control bits. The DMASRCINCR bits select if the source address is incremented, decremented, or unchanged after each transfer. The DMADSTINCR bits select if the destination address is incremented, decremented, or unchanged after each transfer. Transfers may be byte to byte, word to word, byte to word, or word to byte. When transferring word to byte, only the lower byte of the source-word transfers. When transferring byte to word, the upper byte of the destination-word is cleared when the transfer occurs. DMA Controller Address Space DMA Controller Address Space Fixed Address To Fixed Address Fixed Address To Block Of Addresses DMA Controller Address Space DMA Controller Address Space Block Of Addresses To Fixed Address Block Of Addresses To Block Of Addresses Figure 11-2. DMA Addressing Modes SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 383 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Operation www.ti.com 11.2.2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADT bits as listed in Table 11-1. Each channel is individually configurable for its transfer mode. For example, channel 0 may be configured in single transfer mode, while channel 1 is configured for burst-block transfer mode, and channel 2 operates in repeated block mode. The transfer mode is configured independently from the addressing mode. Any addressing mode can be used with any transfer mode. Two types of data can be transferred selectable by the DMAxCTL DSTBYTE and SRCBYTE fields. The source and/or destination location can be either byte or word data. It is also possible to transfer byte to byte, word to word, or any combination. DMADT 000 001 010, 011 100 101 110, 111 Table 11-1. DMA Transfer Modes Transfer Mode Description Single transfer Each transfer requires a trigger. DMAEN is automatically cleared when DMAxSZ transfers have been made. Block transfer A complete block is transferred with one trigger. DMAEN is automatically cleared at the end of the block transfer. Burst-block transfer CPU activity is interleaved with a block transfer. DMAEN is automatically cleared at the end of the burst-block transfer. Repeated single transfer Each transfer requires a trigger. DMAEN remains enabled. Repeated block transfer A complete block is transferred with one trigger. DMAEN remains enabled. Repeated burst-block transfer CPU activity is interleaved with a block transfer. DMAEN remains enabled. 384 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation 11.2.2.1 Single Transfer In single transfer mode, each byte/word transfer requires a separate trigger. The single transfer state diagram is shown in Figure 11-3. The DMAxSZ register is used to define the number of transfers to be made. The DMADSTINCR and DMASRCINCR bits select if the destination address and the source address are incremented or decremented after each transfer. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer. The DMAxSZ register is decremented after each transfer. When the DMAxSZ register decrements to zero, it is reloaded from its temporary register and the corresponding DMAIFG flag is set. When DMADT = {0}, the DMAEN bit is cleared automatically when DMAxSZ decrements to zero and must be set again for another transfer to occur. In repeated single transfer mode, the DMA controller remains enabled with DMAEN = 1, and a transfer occurs every time a trigger occurs. DMAEN = 0 Reset DMAEN = 0 DMAREQ = 0 DMAEN = 1 T_Size → DMAxSZ DMAxSZ → T_Size [ DMADT = {0} AND DMAxSZ = 0] DMAxSA → T_SourceAdd DMAxDA → T_DestAdd OR DMAEN = 0 DMAABORT = 1 DMAEN = 0 Idle DMAABORT=0 DMAREQ = 0 Wait forTrigger DMAxSZ > 0 AND DMAEN = 1 2 x MCLK [+Trigger AND DMALEVEL = 0 ] OR [Trigger = 1 AND DMALEVEL = 1] Hold CPU, Transfer one word/byte [ENNMI = 1 AND NMI event] OR [DMALEVEL = 1 AND Trigger = 0] T_Size → DMAxSZ DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMADT = {4} AND DMAxSZ = 0 AND DMAEN = 1 Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd Figure 11-3. DMA Single Transfer State Diagram SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 385 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Operation www.ti.com 11.2.2.2 Block Transfer In block transfer mode, a transfer of a complete block of data occurs after one trigger. When DMADT = {1} ,the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered. After a block transfer has been triggered, further trigger signals occurring during the block transfer are ignored. The block transfer state diagram is shown in Figure 11-4. The DMAxSZ register is used to define the size of the block, and the DMADSTINCR and DMASRCINCR bits select if the destination address and the source address are incremented or decremented after each transfer of the block. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block. The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block. When the DMAxSZ register decrements to zero, it is reloaded from its temporary register and the corresponding DMAIFG flag is set. During a block transfer, the CPU is halted until the complete block has been transferred. The block transfer takes 2 × MCLK × DMAxSZ clock cycles to complete. CPU execution resumes with its previous state after the block transfer is complete. In repeated block transfer mode, the DMAEN bit remains set after completion of the block transfer. The next trigger after the completion of a repeated block transfer triggers another block transfer. 386 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation DMAEN = 0 DMAEN = 0 DMAREQ = 0 T_Size → DMAxSZ Reset DMAEN = 1 [DMADT = {1} AND DMAxSZ = 0] OR DMAEN = 0 DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMAABORT = 1 DMAEN = 0 Idle DMAABORT = 0 DMAREQ = 0 T_Size → DMAxSZ DMAxSA → T_SourceAdd DMAxDA → T_DestAdd Wait forTrigger 2 × MCLK [+TriggerAND DMALEVEL= 0 ] OR [Trigger=1AND DMALEVEL=1] DMADT = {5} AND DMAxSZ = 0 AND DMAEN = 1 Hold CPU, Transfer one word/byte [ENNMI = 1 AND NMI event] OR [DMALEVEL = 1 AND Trigger = 0] Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd DMAxSZ > 0 Figure 11-4. DMA Block Transfer State Diagram SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 387 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Operation www.ti.com 11.2.2.3 Burst-Block Transfer In burst-block mode, transfers are block transfers with CPU activity interleaved. The CPU executes two MCLK cycles after every four byte/word transfers of the block, resulting in 20% CPU execution capacity. After the burst-block, CPU execution resumes at 100% capacity and the DMAEN bit is cleared. DMAEN must be set again before another burst-block transfer can be triggered. After a burst-block transfer has been triggered, further trigger signals occurring during the burst-block transfer are ignored. The burst-block transfer state diagram is shown in Figure 11-5. The DMAxSZ register is used to define the size of the block, and the DMADSTINCR and DMASRCINCR bits select if the destination address and the source address are incremented or decremented after each transfer of the block. If DMAxSZ = 0, no transfers occur. The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary registers. The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block. The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block. When the DMAxSZ register decrements to zero, it is reloaded from its temporary register and the corresponding DMAIFG flag is set. In repeated burst-block mode, the DMAEN bit remains set after completion of the burst-block transfer and no further trigger signals are required to initiate another burst-block transfer. Another burst-block transfer begins immediately after completion of a burst-block transfer. In this case, the transfers must be stopped by clearing the DMAEN bit, or by an (non)maskable interrupt (NMI) when ENNMI is set. In repeated burstblock mode the CPU executes at 20% capacity continuously until the repeated burst-block transfer is stopped. 388 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMAEN = 0 DMAEN = 0 DMAREQ = 0 T_Size → DMAxSZ Reset DMAEN = 1 [DMADT = {2, 3} AND DMAxSZ = 0] OR DMAEN = 0 DMAxSZ → T_Size DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMAABORT = 1 DMAEN = 0 Idle DMA Operation DMAABORT=0 Wait for Trigger 2 × MCLK [+Trigger AND DMALEVEL = 0 ] OR [Trigger=1 AND DMALEVEL=1] [ENNMI = 1 AND NMI event] OR [DMALEVEL = 1 AND Trigger = 0] Hold CPU, Transfer one word/byte Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd T_Size → DMAxSZ DMAxSA → T_SourceAdd DMAxDA → T_DestAdd DMAxSZ > 0 DMAxSZ > 0 AND a multiple of 4 words/bytes were transferred 2 × MCLK Burst State (release CPU for 2 × MCLK) DMAxSZ > 0 [DMADT = {6, 7} AND DMAxSZ = 0] Figure 11-5. DMA Burst-Block Transfer State Diagram SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 389 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Operation www.ti.com 11.2.3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSEL. The DMAxTSEL bits should be modified only when the DMACTLx DMAEN bit is 0. Otherwise, unpredictable DMA triggers may occur.Table 11-2 describes the trigger operation for each type of module. See the device-specific data sheet for the list of triggers available, along with their respective DMAxTSEL values. When selecting the trigger, the trigger must not have already occurred, or the transfer does not take place. NOTE: DMA trigger selection and USB On devices that contain a USB module, the triggers selection from DMA channels 0, 1, or 2 can be used for the USB time stamp event selection (see the USB module description for further details). 11.2.3.1 Edge-Sensitive Triggers When DMALEVEL = 0, edge-sensitive triggers are used, and the rising edge of the trigger signal initiates the transfer. In single-transfer mode, each transfer requires its own trigger. When using block or burstblock modes, only one trigger is required to initiate the block or burst-block transfer. 11.2.3.2 Level-Sensitive Triggers When DMALEVEL = 1, level-sensitive triggers are used. For proper operation, level-sensitive triggers can only be used when external trigger DMAE0 is selected as the trigger. DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set. The trigger signal must remain high for a block or burst-block transfer to complete. If the trigger signal goes low during a block or burst-block transfer, the DMA controller is held in its current state until the trigger goes back high or until the DMA registers are modified by software. If the DMA registers are not modified by software, when the trigger signal goes high again, the transfer resumes from where it was when the trigger signal went low. When DMALEVEL = 1, transfer modes selected when DMADT = {0, 1, 2, 3} are recommended because the DMAEN bit is automatically reset after the configured transfer. 11.2.4 Halting Executing Instructions for DMA Transfers The DMARMWDIS bit controls when the CPU is halted for DMA transfers. When DMARMWDIS = 0, the CPU is halted immediately and the transfer begins when a trigger is received. In this case, it is possible that CPU read-modify-write operations can be interrupted by a DMA transfer. When DMARMWDIS = 1, the CPU finishes the currently executing read-modify-write operation before the DMA controller halts the CPU and the transfer begins (see Table 11-2). 390 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Module DMA Timer_A Timer_B USCI_Ax USCI_Bx DAC12_A ADC10_A ADC12_A MPY Reserved Table 11-2. DMA Trigger Operation DMA Operation Operation A transfer is triggered when the DMAREQ bit is set. The DMAREQ bit is automatically reset when the transfer starts. A transfer is triggered when the DMAxIFG flag is set. DMA0IFG triggers channel 1, DMA1IFG triggers channel 2, and DMA2IFG triggers channel 0. None of the DMAxIFG flags are automatically reset when the transfer starts. A transfer is triggered by the external trigger DMAE0. A transfer is triggered when the TAxCCR0 CCIFG flag is set. The TAxCCR0 CCIFG flag is automatically reset when the transfer starts. If the TAxCCR0 CCIE bit is set, the TAxCCR0 CCIFG flag dies not trigger a transfer. A transfer is triggered when the TAxCCR2 CCIFG flag is set. The TAxCCR2 CCIFG flag is automatically reset when the transfer starts. If the TAxCCR2 CCIE bit is set, the TAxCCR2 CCIFG flag does not trigger a transfer. A transfer is triggered when the TBxCCR0 CCIFG flag is set. The TBxCCR0 CCIFG flag is automatically reset when the transfer starts. If the TBxCCR0 CCIE bit is set, the TBxCCR0 CCIFG flag does not trigger a transfer. A transfer is triggered when the TBxCCR2 CCIFG flag is set. The TBxCCR2 CCIFG flag is automatically reset when the transfer starts. If the TBxCCR2 CCIE bit is set, the TBxCCR2 CCIFG flag does not trigger a transfer. A transfer is triggered when USCI_Ax receives new data. UCAxRXIFG is automatically reset when the transfer starts. If UCAxRXIE is set, the UCAxRXIFG does not trigger a transfer. A transfer is triggered when USCI_Ax is ready to transmit new data. UCAxTXIFG is automatically reset when the transfer starts. If UCAxTXIE is set, the UCAxTXIFG does not trigger a transfer. A transfer is triggered when USCI_Bx receives new data. UCBxRXIFG is automatically reset when the transfer starts. If UCBxRXIE is set, the UCBxRXIFG does not trigger a transfer. A transfer is triggered when USCI_Bx is ready to transmit new data. UCBxTXIFG is automatically reset when the transfer starts. If UCBxTXIE is set, the UCBxTXIFG does not trigger a transfer. A transfer is triggered when the DAC12_xCTL0 DAC12IFG flag is set. The DAC12_xCTL0 DAC12IFG flag is automatically cleared when the transfer starts. If the DAC12_xCTL0 DAC12IE bit is set, the DAC12_xCTL0 DAC12IFG flag does not trigger a transfer. A transfer is triggered by an ADC10IFG0 flag. A transfer is triggered when the conversion is completed and the ADC10IFG0 is set. Setting the ADC10IFG0 with software does not trigger a transfer. The ADC10IFG0 flag is automatically reset when the ADC10MEM0 register is accessed by the DMA controller. A transfer is triggered by an ADC12IFG flag. When single-channel conversions are performed, the corresponding ADC12IFG is the trigger. When sequences are used, the ADC12IFG for the last conversion in the sequence is the trigger. A transfer is triggered when the conversion is completed and the ADC12IFG is set. Setting the ADC12IFG with software does not trigger a transfer. All ADC12IFG flags are automatically reset when the associated ADC12MEMx register is accessed by the DMA controller. A transfer is triggered when the hardware multiplier is ready for a new operand. No transfer is triggered. 11.2.5 Stopping DMA Transfers There are two ways to stop DMA transfers in progress: • A single, block, or burst-block transfer may be stopped with an NMI, if the ENNMI bit is set in register DMACTL1. • A burst-block transfer may be stopped by clearing the DMAEN bit. 11.2.6 DMA Channel Priorities The default DMA channel priorities are DMA0 through DMA7. If two or three triggers happen simultaneously or are pending, the channel with the highest priority completes its transfer (single, block, or burst-block transfer) first, then the second priority channel, then the third priority channel. Transfers in progress are not halted if a higher-priority channel is triggered. The higher-priority channel waits until the transfer in progress completes before starting. The DMA channel priorities are configurable with the ROUNDROBIN bit. When the ROUNDROBIN bit is set, the channel that completes a transfer becomes the lowest priority. The order of the priority of the channels always stays the same, DMA0-DMA1-DMA2, for example, for three channels. When the ROUNDROBIN bit is cleared, the channel priority returns to the default priority. DMA Priority DMA0-DMA1-DMA2 DMA2-DMA0-DMA1 DMA0-DMA1-DMA2 Transfer Occurs DMA1 DMA2 DMA0 New DMA Priority DMA2-DMA0-DMA1 DMA0-DMA1-DMA2 DMA1-DMA2-DMA0 SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 391 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Operation www.ti.com 11.2.7 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst-block transfer. Each byte/word transfer requires two MCLK cycles after synchronization, and one cycle of wait time after the transfer. Because the DMA controller uses MCLK, the DMA cycle time is dependent on the MSP430 operating mode and clock system setup. If the MCLK source is active but the CPU is off, the DMA controller uses the MCLK source for each transfer, without reenabling the CPU. If the MCLK source is off, the DMA controller temporarily restarts MCLK, sourced with DCOCLK, for the single transfer or complete block or burst-block transfer. The CPU remains off and after the transfer completes, MCLK is turned off. The maximum DMA cycle time for all operating modes is shown in Table 11-3. Table 11-3. Maximum Single-Transfer DMA Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time Active mode MCLK = DCOCLK 4 MCLK cycles Active mode MCLK = LFXT1CLK 4 MCLK cycles Low-power mode LPM0/1 MCLK = DCOCLK 5 MCLK cycles Low-power mode LPM3/4 MCLK = DCOCLK 5 MCLK cycles + 5 µs(1) Low-power mode LPM0/1 MCLK = LFXT1CLK 5 MCLK cycles Low-power mode LPM3 MCLK = LFXT1CLK 5 MCLK cycles Low-power mode LPM4 MCLK = LFXT1CLK 5 MCLK cycles + 5 µs(1) (1) The additional 5 µs are needed to start the DCOCLK. It is the t(LPMx) parameter in the data sheet. 11.2.8 Using DMA With System Interrupts DMA transfers are not interruptible by system interrupts. System interrupts remain pending until the completion of the transfer. NMIs can interrupt the DMA controller if the ENNMI bit is set. System interrupt service routines are interrupted by DMA transfers. If an interrupt service routine or other routine must execute with no interruptions, the DMA controller should be disabled prior to executing the routine. 11.2.9 DMA Controller Interrupts Each DMA channel has its own DMAIFG flag. Each DMAIFG flag is set in any mode when the corresponding DMAxSZ register counts to zero. If the corresponding DMAIE and GIE bits are set, an interrupt request is generated. All DMAIFG flags are prioritized, with DMA0IFG being the highest, and combined to source a single interrupt vector. The highest-priority enabled interrupt generates a number in the DMAIV register. This number can be evaluated or added to the program counter (PC) to automatically enter the appropriate software routine. Disabled DMA interrupts do not affect the DMAIV value. Any access, read or write, of the DMAIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. For example, assume that DMA0 has the highest priority. If the DMA0IFG and DMA2IFG flags are set when the interrupt service routine accesses the DMAIV register, DMA0IFG is reset automatically. After the RETI instruction of the interrupt service routine is executed, the DMA2IFG generates another interrupt. 392 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Operation 11.2.9.1 DMAIV Software Example The following software example shows the recommended use of DMAIV and the handling overhead for an eight channel DMA controller. The DMAIV value is added to the PC to automatically jump to the appropriate routine. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. ;Interrupt handler for DMAxIFG Cycles DMA_HND ... ; Interrupt latency 6 ADD &DMAIV,PC ; Add offset to Jump table 3 RETI ; Vector 0: No interrupt 5 JMP DMA0_HND ; Vector 2: DMA channel 0 2 JMP DMA1_HND ; Vector 4: DMA channel 1 2 JMP DMA2_HND ; Vector 6: DMA channel 2 2 JMP DMA3_HND ; Vector 8: DMA channel 3 2 JMP DMA4_HND ; Vector 10: DMA channel 4 2 JMP DMA5_HND ; Vector 12: DMA channel 5 2 JMP DMA6_HND ; Vector 14: DMA channel 6 2 JMP DMA7_HND ; Vector 16: DMA channel 7 2 DMA7_HND ... RETI ; Vector 16: DMA channel 7 ; Task starts here ; Back to main program 5 DMA6_HND ... RETI ; Vector 14: DMA channel 6 ; Task starts here ; Back to main program 5 DMA5_HND ... RETI ; Vector 12: DMA channel 5 ; Task starts here ; Back to main program 5 DMA4_HND ... RETI ; Vector 10: DMA channel 4 ; Task starts here ; Back to main program 5 DMA3_HND ... RETI ; Vector 8: DMA channel 3 ; Task starts here ; Back to main program 5 DMA2_HND ... RETI ; Vector 6: DMA channel 2 ; Task starts here ; Back to main program 5 DMA1_HND ... RETI ; Vector 4: DMA channel 1 ; Task starts here ; Back to main program 5 DMA0_HND ... RETI ; Vector 2: DMA channel 0 ; Task starts here ; Back to main program 5 SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 393 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Operation www.ti.com 11.2.10 Using the USCI_B I2C Module With the DMA Controller The USCI_B I2C module provides two trigger sources for the DMA controller. The USCI_B I2C module can trigger a transfer when new I2C data is received and the when the transmit data is needed. 11.2.11 Using ADC10 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from the ADC10MEM0 register to another location. DMA transfers are done without CPU intervention and independently of any low-power modes. The DMA controller increases throughput of the ADC10 module and enhances lowpower applications allowing the CPU to remain off while data transfers occur. A transfer is triggered when the conversion is completed and the ADC10IFG0 is set. Setting the ADC10IFG0 with software does not trigger a transfer. The ADC10IFG0 flag is automatically reset when the ADC10MEM0 register is accessed by the DMA controller. 11.2.12 Using ADC12 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from any ADC12MEMx register to another location. DMA transfers are done without CPU intervention and independently of any low-power modes. The DMA controller increases throughput of the ADC12 module, and enhances lowpower applications allowing the CPU to remain off while data transfers occur. DMA transfers can be triggered from any ADC12IFG flag. When CONSEQx = {0,2}, the ADC12IFG flag for the ADC12MEMx used for the conversion can trigger a DMA transfer. When CONSEQx = {1,3}, the ADC12IFG flag for the last ADC12MEMx in the sequence can trigger a DMA transfer. Any ADC12IFG flag is automatically cleared when the DMA controller accesses the corresponding ADC12MEMx. 11.2.13 Using DAC12 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the DAC12_xDAT register. DMA transfers are done without CPU intervention and independently of any low-power modes. The DMA controller increases throughput to the DAC12 module, and enhances low-power applications allowing the CPU to remain off while data transfers occur. Applications requiring periodic waveform generation can benefit from using the DMA controller with the DAC12. For example, an application that produces a sinusoidal waveform may store the sinusoid values in a table. The DMA controller can continuously and automatically transfer the values to the DAC12 at specific intervals creating the sinusoid with zero CPU execution. The DAC12_xCTL DAC12IFG flag is automatically cleared when the DMA controller accesses the DAC12_xDAT register. 394 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com DMA Registers 11.3 DMA Registers The DMA module registers are listed in Table 11-4. The base addresses can be found in the devicespecific data sheet. Each channel starts at its respective base address. The address offsets are listed in Table 11-4. Offset 00h 02h 04h 06h 08h 0Eh 00h 02h 06h 0Ah 00h 02h 06h 0Ah 00h 02h 06h 0Ah 00h 02h 06h 0Ah 00h 02h 06h 0Ah 00h 02h 06h 0Ah Acronym DMACTL0 DMACTL1 DMACTL2 DMACTL3 DMACTL4 DMAIV DMA0CTL DMA0SA DMA0DA DMA0SZ DMA1CTL DMA1SA DMA1DA DMA1SZ DMA2CTL DMA2SA DMA2DA DMA2SZ DMA3CTL DMA3SA DMA3DA DMA3SZ DMA4CTL DMA4SA DMA4DA DMA4SZ DMA5CTL DMA5SA DMA5DA DMA5SZ Table 11-4. DMA Registers Register Name DMA Control 0 DMA Control 1 DMA Control 2 DMA Control 3 DMA Control 4 DMA Interrupt Vector DMA Channel 0 Control DMA Channel 0 Source Address DMA Channel 0 Destination Address DMA Channel 0 Transfer Size DMA Channel 1 Control DMA Channel 1 Source Address DMA Channel 1 Destination Address DMA Channel 1 Transfer Size DMA Channel 2 Control DMA Channel 2 Source Address DMA Channel 2 Destination Address DMA Channel 2 Transfer Size DMA Channel 3 Control DMA Channel 3 Source Address DMA Channel 3 Destination Address DMA Channel 3 Transfer Size DMA Channel 4 Control DMA Channel 4 Source Address DMA Channel 4 Destination Address DMA Channel 4 Transfer Size DMA Channel 5 Control DMA Channel 5 Source Address DMA Channel 5 Destination Address DMA Channel 5 Transfer Size Type Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Access Reset Word 0000h Word 0000h Word 0000h Word 0000h Word 0000h Word 0000h Word 0000h Word, undefined double word Word, undefined double word Word undefined Word 0000h Word, undefined double word Word, undefined double word Word undefined Word 0000h Word, undefined double word Word, undefined double word Word undefined Word 0000h Word, undefined double word Word, undefined double word Word undefined Word 0000h Word, undefined double word Word, undefined double word Word undefined Word 0000h Word, undefined double word Word, undefined double word Word undefined Section Section 11.3.1 Section 11.3.2 Section 11.3.3 Section 11.3.4 Section 11.3.5 Section 11.3.10 Section 11.3.6 Section 11.3.7 Section 11.3.8 Section 11.3.9 Section 11.3.6 Section 11.3.7 Section 11.3.8 Section 11.3.9 Section 11.3.6 Section 11.3.7 Section 11.3.8 Section 11.3.9 Section 11.3.6 Section 11.3.7 Section 11.3.8 Section 11.3.9 Section 11.3.6 Section 11.3.7 Section 11.3.8 Section 11.3.9 Section 11.3.6 Section 11.3.7 Section 11.3.8 Section 11.3.9 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Direct Memory Access (DMA) Controller Module 395 Copyright © 2008–2015, Texas Instruments Incorporated DMA Registers www.ti.com Offset 00h 02h 06h 0Ah 00h 02h 06h 0Ah Acronym DMA6CTL DMA6SA DMA6DA DMA6SZ DMA7CTL DMA7SA DMA7DA DMA7SZ Table 11-4. DMA Registers (continued) Register Name DMA Channel 6 Control DMA Channel 6 Source Address DMA Channel 6 Destination Address DMA Channel 6 Transfer Size DMA Channel 7 Control DMA Channel 7 Source Address DMA Channel 7 Destination Address DMA Channel 7 Transfer Size Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Access Reset Word 0000h Word, undefined double word Word, undefined double word Word undefined Word 0000h Word, undefined double word Word, undefined double word Word undefined Section Section 11.3.6 Section 11.3.7 Section 11.3.8 Section 11.3.9 Section 11.3.6 Section 11.3.7 Section 11.3.8 Section 11.3.9 396 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 11.3.1 DMACTL0 Register DMA Control 0 Register 15 14 13 Reserved r0 r0 r0 7 6 5 Reserved r0 r0 r0 Figure 11-6. DMACTL0 Register 12 11 10 DMA1TSEL rw-(0) rw-(0) rw-(0) 4 rw-(0) 3 rw-(0) 2 DMA0TSEL rw-(0) DMA Registers 9 rw-(0) 1 rw-(0) 8 rw-(0) 0 rw-(0) Bit 15-13 12-8 Field Reserved DMA1TSEL 7-5 Reserved 4-0 DMA0TSEL Type R RW R RW Table 11-5. DMACTL0 Register Description Reset 0h 0h 0h 0h Description Reserved. Always reads as 0. DMA 1 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment. 00000b = DMA1TRIG0 00001b = DMA1TRIG1 00010b = DMA1TRIG2 ⋮ 11110b = DMA1TRIG30 11111b = DMA1TRIG31 Reserved. Always reads as 0. DMA 0 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment. 00000b = DMA0TRIG0 00001b = DMA0TRIG1 00010b = DMA0TRIG2 ⋮ 11110b = DMA0TRIG30 11111b = DMA0TRIG31 SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 397 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Registers 11.3.2 DMACTL1 Register DMA Control 1 Register 15 14 13 Reserved r0 r0 r0 7 6 5 Reserved r0 r0 r0 Figure 11-7. DMACTL1 Register 12 11 10 DMA3TSEL rw-(0) rw-(0) rw-(0) 4 rw-(0) 3 rw-(0) 2 DMA2TSEL rw-(0) 9 rw-(0) 1 rw-(0) www.ti.com 8 rw-(0) 0 rw-(0) Bit 15-13 12-8 Field Reserved DMA3TSEL 7-5 Reserved 4-0 DMA2TSEL Type R RW R RW Table 11-6. DMACTL1 Register Description Reset 0h 0h 0h 0h Description Reserved. Always reads as 0. DMA 3 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment. 00000b = DMA3TRIG0 00001b = DMA3TRIG1 00010b = DMA3TRIG2 ⋮ 11110b = DMA3TRIG30 11111b = DMA3TRIG31 Reserved. Always reads as 0. DMA 2 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment. 00000b = DMA2TRIG0 00001b = DMA2TRIG1 00010b = DMA2TRIG2 ⋮ 11110b = DMA2TRIG30 11111b = DMA2TRIG31 398 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 11.3.3 DMACTL2 Register DMA Control 2 Register 15 14 13 Reserved r0 r0 r0 7 6 5 Reserved r0 r0 r0 Figure 11-8. DMACTL2 Register 12 11 10 DMA5TSEL rw-(0) rw-(0) rw-(0) 4 rw-(0) 3 rw-(0) 2 DMA4TSEL rw-(0) DMA Registers 9 rw-(0) 1 rw-(0) 8 rw-(0) 0 rw-(0) Bit 15-13 12-8 Field Reserved DMA5TSEL 7-5 Reserved 4-0 DMA4TSEL Type R RW R RW Table 11-7. DMACTL2 Register Description Reset 0h 0h 0h 0h Description Reserved. Always reads as 0. DMA 5 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment. 00000b = DMA5TRIG0 00001b = DMA5TRIG1 00010b = DMA5TRIG2 ⋮ 11110b = DMA5TRIG30 11111b = DMA5TRIG31 Reserved. Always reads as 0. DMA 4 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment. 00000b = DMA4TRIG0 00001b = DMA4TRIG1 00010b = DMA4TRIG2 ⋮ 11110b = DMA4TRIG30 11111b = DMA4TRIG31 SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 399 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Registers 11.3.4 DMACTL3 Register DMA Control 3 Register 15 14 13 Reserved r0 r0 r0 7 6 5 Reserved r0 r0 r0 Figure 11-9. DMACTL3 Register 12 11 10 DMA7TSEL rw-(0) rw-(0) rw-(0) 4 rw-(0) 3 rw-(0) 2 DMA6TSEL rw-(0) 9 rw-(0) 1 rw-(0) www.ti.com 8 rw-(0) 0 rw-(0) Bit 15-13 12-8 Field Reserved DMA7TSEL 7-5 Reserved 4-0 DMA6TSEL Type R RW R RW Table 11-8. DMACTL3 Register Description Reset 0h 0h 0h 0h Description Reserved. Always reads as 0. DMA 7 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment. 00000b = DMA7TRIG0 00001b = DMA7TRIG1 00010b = DMA7TRIG2 ⋮ 11110b = DMA7TRIG30 11111b = DMA7TRIG31 Reserved. Always reads as 0. DMA 6 trigger select. These bits select the DMA transfer trigger. See the devicespecific data sheet for number of channels and trigger assignment. 00000b = DMA6TRIG0 00001b = DMA6TRIG1 00010b = DMA6TRIG2 ⋮ 11110b = DMA6TRIG30 11111b = DMA6TRIG31 400 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 11.3.5 DMACTL4 Register DMA Control 4 Register DMA Registers Figure 11-10. DMACTL4 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved DMARMWDIS ROUNDROBIN ENNMI r0 r0 r0 r0 r0 rw-(0) rw-(0) rw-(0) Bit 15-3 2 Field Reserved DMARMWDIS 1 ROUNDROBIN 0 ENNMI Type R RW RW RW Table 11-9. DMACTL4 Register Description Reset 0h 0h 0h 0h Description Reserved. Always reads as 0. Read-modify-write disable. When set, this bit inhibits any DMA transfers from occurring during CPU read-modify-write operations. 0b = DMA transfers can occur during read-modify-write CPU operations. 1b = DMA transfers inhibited during read-modify-write CPU operations Round robin. This bit enables the round-robin DMA channel priorities. 0b = DMA channel priority is DMA0-DMA1-DMA2 - ...... -DMA7. 1b = DMA channel priority changes with each transfer. Enable NMI. This bit enables the interruption of a DMA transfer by an NMI. When an NMI interrupts a DMA transfer, the current transfer is completed normally, further transfers are stopped and DMAABORT is set. 0b = NMI does not interrupt DMA transfer. 1b = NMI interrupts a DMA transfer. SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 401 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Registers 11.3.6 DMAxCTL Register DMA Channel x Control Register 15 Reserved r0 14 rw-(0) 7 6 DMADSTBYTE DMASRCBYTE rw-(0) rw-(0) 13 DMADT rw-(0) Figure 11-11. DMAxCTL Register 12 11 10 DMADSTINCR rw-(0) rw-(0) rw-(0) 5 DMALEVEL rw-(0) 4 DMAEN rw-(0) 3 DMAIFG rw-(0) 2 DMAIE rw-(0) www.ti.com 9 8 DMASRCINCR rw-(0) rw-(0) 1 DMAABORT rw-(0) 0 DMAREQ rw-(0) Bit 15 14-12 Field Reserved DMADT 11-10 DMADSTINCR 9-8 DMASRCINCR 7 DMADSTBYTE 6 DMASRCBYTE 5 DMALEVEL 4 DMAEN Table 11-10. DMAxCTL Register Description Type R RW RW RW RW RW RW RW Reset 0h 0h 0h 0h 0h 0h 0h 0h Description Reserved. Always reads as 0. DMA transfer mode 000b = Single transfer 001b = Block transfer 010b = Burst-block transfer 011b = Burst-block transfer 100b = Repeated single transfer 101b = Repeated block transfer 110b = Repeated burst-block transfer 111b = Repeated burst-block transfer DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer. When DMADSTBYTE = 1, the destination address increments/decrements by one. When DMADSTBYTE = 0, the destination address increments/decrements by two. The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented. DMAxDA is not incremented or decremented. 00b = Destination address is unchanged. 01b = Destination address is unchanged. 10b = Destination address is decremented. 11b = Destination address is incremented. DMA source increment. This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer. When DMASRCBYTE = 1, the source address increments/decrements by one. When DMASRCBYTE = 0, the source address increments/decrements by two. The DMAxSA is copied into a temporary register and the temporary register is incremented or decremented. DMAxSA is not incremented or decremented. 00b = Source address is unchanged. 01b = Source address is unchanged. 10b = Source address is decremented. 11b = Source address is incremented. DMA destination byte. This bit selects the destination as a byte or word. 0b = Word 1b = Byte DMA source byte. This bit selects the source as a byte or word. 0b = Word 1b = Byte DMA level. This bit selects between edge-sensitive and level-sensitive triggers. 0b = Edge sensitive (rising edge) 1b = Level sensitive (high level) DMA enable 0b = Disabled 1b = Enabled 402 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Bit Field 3 DMAIFG 2 DMAIE 1 DMAABORT 0 DMAREQ DMA Registers Table 11-10. DMAxCTL Register Description (continued) Type RW RW RW RW Reset 0h 0h 0h 0h Description DMA interrupt flag 0b = No interrupt pending 1b = Interrupt pending DMA interrupt enable 0b = Disabled 1b = Enabled DMA abort. This bit indicates if a DMA transfer was interrupt by an NMI. 0b = DMA transfer not interrupted 1b = DMA transfer interrupted by NMI DMA request. Software-controlled DMA start. DMAREQ is reset automatically. 0b = No DMA start 1b = Start DMA SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 403 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Registers 11.3.7 DMAxSA Register DMA Channel x Source Address Register Figure 11-12. DMAxSA Register 31 30 29 28 27 26 25 Reserved r0 r0 r0 r0 r0 r0 r0 23 22 21 20 19 18 17 Reserved DMAxSA r0 r0 r0 r0 rw rw rw 15 14 13 12 11 10 9 DMAxSA rw rw rw rw rw rw rw 7 6 5 4 3 2 1 DMAxSA rw rw rw rw rw rw rw www.ti.com 24 r0 16 rw 8 rw 0 rw Bit 31-20 19-0 Field Reserved DMAxSA Type R RW Table 11-11. DMAxSA Register Description Reset 0h undefined Description Reserved. Always reads as 0. DMA source address. The source address register points to the DMA source address for single transfers or the first source address for block transfers. The source address register remains unchanged during block and burst-block transfers. There are two words for the DMAxSA register. Bits 31-20 are reserved and always read as zero. Reading or writing bits 19-16 requires the use of extended instructions. When writing to DMAxSA with word instructions, bits 19-16 are cleared. 404 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 11.3.8 DMAxDA Register DMA Channel x Destination Address Register Figure 11-13. DMAxDA Register 31 30 29 28 27 26 25 Reserved r0 r0 r0 r0 r0 r0 r0 23 22 21 20 19 18 17 Reserved DMAxDA r0 r0 r0 r0 rw rw rw 15 14 13 12 11 10 9 DMAxDA rw rw rw rw rw rw rw 7 6 5 4 3 2 1 DMAxDA rw rw rw rw rw rw rw DMA Registers 24 r0 16 rw 8 rw 0 rw Bit 31-20 19-0 Field Reserved DMAxDA Type R RW Table 11-12. DMAxDA Register Description Reset 0h undefined Description Reserved. Always reads as 0. DMA destination address. The destination address register points to the DMA destination address for single transfers or the first destination address for block transfers. The destination address register remains unchanged during block and burst-block transfers. There are two words for the DMAxDA register. Bits 31-20 are reserved and always read as zero. Reading or writing bits 19-16 requires the use of extended instructions. When writing to DMAxDA with word instructions, bits 19-16 are cleared. SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 405 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated DMA Registers 11.3.9 DMAxSZ Register DMA Channel x Size Address Register Figure 11-14. DMAxSZ Register 15 14 13 12 11 10 DMAxSZ rw rw rw rw rw rw 7 6 5 4 3 2 DMAxSZ rw rw rw rw rw rw www.ti.com 9 8 rw rw 1 0 rw rw Bit 15-0 Field DMAxSZ Type RW Table 11-13. DMAxSZ Register Description Reset undefined Description DMA size. The DMA size register defines the number of byte/word data per block transfer. DMAxSZ register decrements with each word or byte transfer. When DMAxSZ decrements to 0, it is immediately and automatically reloaded with its previously initialized value. 00000h = Transfer is disabled. 00001h = One byte or word is transferred. 00002h = Two bytes or words are transferred. ⋮ 0FFFFh = 65535 bytes or words are transferred. 406 Direct Memory Access (DMA) Controller Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 11.3.10 DMAIV Register DMA Interrupt Vector Register 15 14 13 r0 r0 r0 7 6 5 r0 r0 r-(0) Figure 11-15. DMAIV Register 12 11 10 DMAIV r0 r0 r0 4 3 2 DMAIV r-(0) r-(0) r-(0) DMA Registers 9 8 r0 r0 1 0 r-(0) r0 Bit 15-0 Field DMAIV Type R Table 11-14. DMAIV Register Description Reset 0h Description DMA interrupt vector value 00h = No interrupt pending 02h = Interrupt Source: DMA channel 0; Interrupt Flag: DMA0IFG; Interrupt Priority: Highest 04h = Interrupt Source: DMA channel 1; Interrupt Flag: DMA1IFG 06h = Interrupt Source: DMA channel 2; Interrupt Flag: DMA2IFG 08h = Interrupt Source: DMA channel 3; Interrupt Flag: DMA3IFG 0Ah = Interrupt Source: DMA channel 4; Interrupt Flag: DMA4IFG 0Ch = Interrupt Source: DMA channel 5; Interrupt Flag: DMA5IFG 0Eh = Interrupt Source: DMA channel 6; Interrupt Flag: DMA6IFG 10h = Interrupt Source: DMA channel 7; Interrupt Flag: DMA7IFG; Interrupt Priority: Lowest SLAU208O – June 2008 – Revised May 2015 Direct Memory Access (DMA) Controller Module 407 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Chapter 12 SLAU208O – June 2008 – Revised May 2015 Digital I/O Module This chapter describes the operation of the digital I/O ports in all devices. Topic ........................................................................................................................... Page 12.1 Digital I/O Introduction ...................................................................................... 409 12.2 Digital I/O Operation ......................................................................................... 410 12.3 I/O Configuration and LPMx.5 Low-Power Modes ................................................. 413 12.4 Digital I/O Registers .......................................................................................... 416 408 Digital I/O Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Digital I/O Introduction 12.1 Digital I/O Introduction The digital I/O features include: • Independently programmable individual I/Os • Any combination of input or output • Individually configurable P1 and P2 interrupts. Some devices may include additional port interrupts. • Independent input and output data registers • Individually configurable pullup or pulldown resistors Devices within the family may have up to twelve digital I/O ports implemented (P1 to P11 and PJ). Most ports contain eight I/O lines; however, some ports may contain less (see the device-specific data sheet for ports available). Each I/O line is individually configurable for input or output direction, and each can be individually read or written. Each I/O line is individually configurable for pullup or pulldown resistors, as well as, configurable drive strength, full or reduced. PJ contains only four I/O lines. Ports P1 and P2 always have interrupt capability. Each interrupt for the P1 and P2 I/O lines can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal. All P1 I/O lines source a single interrupt vector P1IV, and all P2 I/O lines source a different, single interrupt vector P2IV. On some devices, additional ports with interrupt capability may be available (see the devicespecific data sheet for details) and contain their own respective interrupt vectors. Individual ports can be accessed as byte-wide ports or can be combined into word-wide ports and accessed in word formats. Port pairs P1 and P2, P3 and P4, P5 and P6, and so on, are associated with the names PA, PB, PC, and so on, respectively. All port registers are handled in this manner with this naming convention except for the interrupt vector registers; for example, PAIV does not exist for P1IV and P2IV. When writing to port PA with word operations, all 16 bits are written to the port. When writing to the lower byte of the PA port using byte operations, the upper byte remains unchanged. Similarly, writing to the upper byte of the PA port using byte instructions leaves the lower byte unchanged. When writing to a port that contains less than the maximum number of bits possible, the unused bits are a "don't care". Ports PB, PC, PD, PE, and PF behave similarly. Reading of the PA port using word operations causes all 16 bits to be transferred to the destination. Reading the lower or upper byte of the PA port (P1 or P2) and storing to memory using byte operations causes only the lower or upper byte to be transferred to the destination, respectively. Reading of the PA port and storing to a general-purpose register using byte operations causes the byte transferred to be written to the least significant byte of the register. The upper significant byte of the destination register is cleared automatically. Ports PB, PC, PD, PE, and PF behave similarly. When reading from ports that contain less than the maximum bits possible, unused bits are read as zeros (similarly for port PJ). SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 409 Digital I/O Operation www.ti.com 12.2 Digital I/O Operation The digital I/O are configured with user software. The setup and operation of the digital I/O are discussed in the following sections. 12.2.1 Input Registers (PxIN) Each bit in each PxIN register reflects the value of the input signal at the corresponding I/O pin when the pin is configured as I/O function. These registers are read only. • Bit = 0: Input is low • Bit = 1: Input is high NOTE: Writing to read-only registers PxIN Writing to these read-only registers results in increased current consumption while the write attempt is active. 12.2.2 Output Registers (PxOUT) Each bit in each PxOUT register is the value to be output on the corresponding I/O pin when the pin is configured as I/O function, output direction. • Bit = 0: Output is low • Bit = 1: Output is high If the pin is configured as I/O function, input direction and the pullup or pulldown resistor are enabled; the corresponding bit in the PxOUT register selects pullup or pulldown. • Bit = 0: Pin is pulled down • Bit = 1: Pin is pulled up 12.2.3 Direction Registers (PxDIR) Each bit in each PxDIR register selects the direction of the corresponding I/O pin, regardless of the selected function for the pin. PxDIR bits for I/O pins that are selected for other functions must be set as required by the other function. • Bit = 0: Port pin is switched to input direction • Bit = 1: Port pin is switched to output direction 12.2.4 Pullup or Pulldown Resistor Enable Registers (PxREN) Each bit in each PxREN register enables or disables the pullup or pulldown resistor of the corresponding I/O pin. The corresponding bit in the PxOUT register selects if the pin contains a pullup or pulldown. • Bit = 0: Pullup or pulldown resistor disabled • Bit = 1: Pullup or pulldown resistor enabled Table 12-1 summarizes the usage of PxDIR, PxREN, and PxOUT for proper I/O configuration. PxDIR 0 0 0 1 Table 12-1. I/O Configuration PxREN 0 1 1 x PxOUT x 0 1 x I/O Configuration Input Input with pulldown resistor Input with pullup resistor Output 410 Digital I/O Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Digital I/O Operation 12.2.5 Output Drive Strength Registers (PxDS) Each bit in each PxDS register selects either full drive or reduced drive strength. Default is reduced drive strength. • Bit = 0: Reduced drive strength • Bit = 1: Full drive strength NOTE: Drive strength and EMI All outputs default to reduced drive strength to reduce EMI. Using full drive strength can result in increased EMI. 12.2.6 Function Select Registers (PxSEL) Port pins are often multiplexed with other peripheral module functions. See the device-specific data sheet to determine pin functions. Each PxSEL bit is used to select the pin function – I/O port or peripheral module function. • Bit = 0: I/O Function is selected for the pin • Bit = 1: Peripheral module function is selected for the pin Setting PxSEL = 1 does not automatically set the pin direction. Other peripheral module functions may require the PxDIR bits to be configured according to the direction needed for the module function. See the pin schematics in the device-specific data sheet. NOTE: P1 and P2 interrupts are disabled when PxSEL = 1 When any PxSEL bit is set, the corresponding pin’s interrupt function is disabled. Therefore, signals on these pins does not generate P1 or P2 interrupts, regardless of the state of the corresponding P1IE or P2IE bit. When a port pin is selected as an input to a peripheral, the input signal to the peripheral is a latched representation of the signal at the device pin. While its corresponding PxSEL = 1, the internal input signal follows the signal at the pin. However, if its PxSEL = 0, the input to the peripheral maintains the value of the input signal at the device pin before its corresponding PxSEL bit was reset. 12.2.7 Port Interrupts Each pin in ports P1 and P2 has interrupt capability, configured with the PxIFG, PxIE, and PxIES registers. On some devices, additional ports have interrupt capability (see the device-specific data sheet). All P1 interrupt flags are prioritized, with P1IFG.0 being the highest, and combined to source a single interrupt vector. The highest priority enabled interrupt generates a number in the P1IV register. This number can be evaluated or added to the program counter to automatically enter the appropriate software routine. Disabled P1 interrupts do not affect the P1IV value. The same functionality exists for P2. Some devices may contain additional port interrupts besides P1 and P2. See the device specific data sheet to determine which port interrupts are available. Each PxIFG bit is the interrupt flag for its corresponding I/O pin and is set when the selected input signal edge occurs at the pin. All PxIFG interrupt flags request an interrupt when their corresponding PxIE bit and the GIE bit are set. Software can also set each PxIFG flag, providing a way to generate a softwareinitiated interrupt. • Bit = 0: No interrupt is pending • Bit = 1: An interrupt is pending Only transitions, not static levels, cause interrupts. If any PxIFG flag becomes set during a Px interrupt service routine, or is set after the RETI instruction of a Px interrupt service routine is executed, the set PxIFG flag generates another interrupt. This ensures that each transition is acknowledged. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 411 Digital I/O Operation www.ti.com NOTE: PxIFG flags when changing PxOUT, PxDIR, or PxREN Writing to P1OUT, P1DIR, P1REN, P2OUT, P2DIR, or P2REN can result in setting the corresponding P1IFG or P2IFG flags. Any access (read or write) of the lower byte of the P1IV register, either word or byte access, automatically resets the highest pending interrupt flag. If another interrupt flag is set, another interrupt is immediately generated after servicing the initial interrupt. For example, assume that P1IFG.0 has the highest priority. If the P1IFG.0 and P1IFG.2 flags are set when the interrupt service routine accesses the P1IV register, P1IFG.0 is reset automatically. After the RETI instruction of the interrupt service routine is executed, the P1IFG.2 generates another interrupt. Port P2 interrupts behave similarly, and source a separate single interrupt vector and utilize the P2IV register. 12.2.7.1 Port Interrupt Software Example The following software example shows the recommended use of P1IV and the handling overhead. The P1IV value is added to the PC to automatically jump to the appropriate routine. The P2IV is similar. The numbers at the right margin show the necessary CPU cycles for each instruction. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles, but not the task handling itself. ;Interrupt handler for P1 P1_HND ... ADD &P1IV,PC RETI JMP P1_0_HND JMP P1_1_HND JMP P1_2_HND JMP P1_3_HND JMP P1_4_HND JMP P1_5_HND JMP P1_6_HND JMP P1_7_HND ; Interrupt latency ; Add offset to Jump table ; Vector 0: No interrupt ; Vector 2: Port 1 bit 0 ; Vector 4: Port 1 bit 1 ; Vector 6: Port 1 bit 2 ; Vector 8: Port 1 bit 3 ; Vector 10: Port 1 bit 4 ; Vector 12: Port 1 bit 5 ; Vector 14: Port 1 bit 6 ; Vector 16: Port 1 bit 7 Cycles 6 3 5 2 2 2 2 2 2 2 2 P1_7_HND ... RETI ; Vector 16: Port 1 bit 7 ; Task starts here ; Back to main program 5 P1_6_HND ... RETI ; Vector 14: Port 1 bit 6 ; Task starts here ; Back to main program 5 P1_5_HND ... RETI ; Vector 12: Port 1 bit 5 ; Task starts here ; Back to main program 5 P1_4_HND ... RETI ; Vector 10: Port 1 bit 4 ; Task starts here ; Back to main program 5 P1_3_HND ... RETI ; Vector 8: Port 1 bit 3 ; Task starts here ; Back to main program 5 P1_2_HND ... RETI ; Vector 6: Port 1 bit 2 ; Task starts here ; Back to main program 5 P1_1_HND ... RETI P1_0_HND ; Vector 4: Port 1 bit 1 ; Task starts here ; Back to main program 5 ; Vector 2: Port 1 bit 0 412 Digital I/O Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com ... RETI ; Task starts here ; Back to main program 5 12.2.7.2 Interrupt Edge Select Registers (PxIES) Each PxIES bit selects the interrupt edge for the corresponding I/O pin. • Bit = 0: Respective PxIFG flag is set with a low-to-high transition • Bit = 1: Respective PxIFG flag is set with a high-to-low transition Digital I/O Operation NOTE: Writing to PxIES Writing to P1IES or P2IES for each corresponding I/O can result in setting the corresponding interrupt flags. PxIES 0→1 0→1 1→0 1→0 PxIN 0 1 0 1 PxIFG Will be set Unchanged Unchanged Will be set 12.2.7.3 Interrupt Enable Registers (PxIE) Each PxIE bit enables the associated PxIFG interrupt flag. • Bit = 0: The interrupt is disabled • Bit = 1: The interrupt is enabled 12.2.8 Configuring Unused Port Pins Unused I/O pins should be configured as I/O function, output direction, and left unconnected on the PC board, to prevent a floating input and reduce power consumption. The value of the PxOUT bit is don't care, because the pin is unconnected. Alternatively, the integrated pullup or pulldown resistor can be enabled by setting the PxREN bit of the unused pin to prevent the floating input. See the SYS chapter for termination of unused pins. NOTE: Configuring port J and shared JTAG pins: Application should ensure that port PJ is configured properly to prevent a floating input. Because port PJ is shared with the JTAG function, floating inputs may not be noticed when in an emulation environment. Port J is initialized to high-impedance inputs by default. 12.3 I/O Configuration and LPMx.5 Low-Power Modes NOTE: The LPMx.5 low-power modes may not be available on all devices. The LPM4.5 power mode allows for lowest power consumption and no clocks are available. The LPM3.5 power mode allows for RTC mode operation at the lowest power consumption available. See the SYS chapter for details; also see the device-specific datasheet for LPMx.5 low-power modes that are available. With respect to the digital I/O, this section is applicable for both LPM3.5 and LPM4.5. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 413 I/O Configuration and LPMx.5 Low-Power Modes www.ti.com The regulator of the Power Management Module (PMM) is disabled upon entering LPMx.5 (LPM3.5 or LPM4.5), which causes all I/O register configurations to be lost. Because the I/O register configurations are lost, the configuration of I/O pins must be handled differently to ensure that all pins in the application behave in a controlled manner upon entering and exiting LPMx.5. Properly setting the I/O pins is critical to achieving the lowest possible power consumption in LPMx.5, as well as preventing any possible uncontrolled input or output I/O state in the application. The application has complete control of the I/O pin conditions preventing the possibility of unwanted spurious activity upon entry and exit from LPMx.5. The detailed flow for entering and exiting LPMx.5 with respect to the I/O operation is as follows: 1. Set all I/Os to general-purpose I/Os and configure as needed. Each I/O can be set to input high impedance, input with pulldown, input with pullup, output high (low or high drive strength), or output low (low or high drive strength). It is critical that no inputs are left floating in the application, otherwise excess current may be drawn in LPMx.5. Configuring the I/O in this manner ensures that each pin is in a safe condition before entering LPMx.5. Optionally, configure input interrupt pins for wakeup from LPMx.5. To wake the device from LPMx.5, a general-purpose I/O port must contain an input port with interrupt capability. Not all devices include wakeup from LPMx.5 by I/O, and not all inputs with interrupt capability offer wakeup from LPMx.5. See the device-specific data sheet for availability. To configure a port to wake the device, the I/O should be configured properly before entering LPMx.5. Each port should be configured as general-purpose input. Pulldowns or pullups can be applied if required. Setting the PxIES bit of the corresponding register determines the edge transition that wakes the device. Last, the PxIE for the port must be enabled, as well as the general interrupt enable. NOTE: It is not possible to wake from LPMx.5 if the respective I/O interrupt flag is already asserted. It is recommended that the respective flag be cleared before entering LPMx.5. It is also recommended that GIE = 1 be set before entry into LPMx.5. Any pending flags in this case could then be serviced before LPMx.5 entry. Although it is recommended to set GIE = 1 before entering LPMx.5, it is not required. Device wakeup from LPMx.5 with an enabled wake-up function still causes the device to wake from LPMx.5 even with GIE = 0. If GIE = 0 before LPMx.5, additional care may be required. If the respective interrupt event occurs during LPMx.5 entry, the device may not recognize this or any future interrupt wakeup event on this function. 2. Enter LPMx.5 with LPMx.5 entry sequence, enable general interrupts for wakeup: MOV.B #PMMPW_H, &PMMCTL0_H BIS.B #PMMREGOFF, &PMMCTL0_L BIS #GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR ; Open PMM registers for write ; ; Enter LPMx.5 when PMMREGOFF is set 3. Upon entry into LPMx.5, the LOCKLPM5 bit in the PM5CTL0 register of the PMM module is set automatically. The I/O pin states are held and locked based on the settings before LPMx.5 entry. Note that only the pin conditions are retained. All other port configuration register settings such as PxDIR, PxREN, PxOUT, PxDS, PxIES, and PxIE contents are lost. 4. An LPMx.5 wake-up event (for example, an edge on a configured wake-up input pin) starts the BOR entry sequence together with the regulator. All peripheral registers are set to their default conditions. Upon exit from LPMx.5, the I/O pins remain locked while LOCKLPM5 remains set. Keeping the I/O pins locked ensures that all pin conditions remain stable upon entering the active mode regardless of the default I/O register settings. 5. When in active mode, the I/O configuration and I/O interrupt configuration that was not retained during LPMx.5 should be restored to the values before entering LPMx.5. It is recommended to reconfigure the PxIES and PxIE to their previous settings to prevent a false port interrupt from occurring. The LOCKLPM5 bit can then be cleared, which releases the I/O pin conditions and I/O interrupt configuration. Any changes to the port configuration registers while LOCKLPM5 is set have no effect on the I/O pins. 6. After enabling the I/O interrupts, the I/O interrupt that caused the wakeup can be serviced indicated by the PxIFG flags. These flags can be used directly, or the corresponding PxIV register may be used. Note that the PxIFG flag cannot be cleared until the LOCKLPM5 bit has been cleared. 414 Digital I/O Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com I/O Configuration and LPMx.5 Low-Power Modes NOTE: It is possible that multiple events occurred on various ports. In these cases, multiple PxIFG flags will be set, and it cannot be determined which port has caused the I/O wakeup. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 415 Digital I/O Registers www.ti.com 12.4 Digital I/O Registers The digital I/O registers are listed in Table 12-2. The base addresses can be found in the device-specific data sheet. Each port grouping begins at its base address. The address offsets are given in Table 12-2. NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15). Offset 0Eh 0Eh 0Fh 1Eh 1Eh 1Fh 00h 02h 04h 06h 08h 0Ah 18h 1Ah 1Ch 01h 03h 05h 07h 09h 0Bh 19h 1Bh 1Dh 00h 02h Acronym P1IV P1IV_L P1IV_H P2IV P2IV_L P2IV_H P1IN or PAIN_L P1OUT or PAOUT_L P1DIR or PADIR_L P1REN or PAREN_L P1DS or PADS_L P1SEL or PASEL_L P1IES or PAIES_L P1IE or PAIE_L P1IFG or PAIFG_L P2IN or PAIN_H P2OUT or PAOUT_H P2DIR or PADIR_H P2REN or PAREN_H P2DS or PADS_H P2SEL or PASEL_H P2IES or PAIES_H P2IE or PAIE_H P2IFG or PAIFG_H P3IN or PBIN_L P3OUT or PBOUT_L 416 Digital I/O Module Table 12-2. Digital I/O Registers Register Name Port 1 Interrupt Vector Port 2 Interrupt Vector Port 1 Input Type Read only Read only Read only Read only Read only Read only Read only Access Word Byte Byte Word Byte Byte Byte Reset 0000h 00h 00h 0000h 00h 00h Section Section 12.4.1 Section 12.4.2 Section 12.4.9 Port 1 Output Read/write Byte undefined Section 12.4.10 Port 1 Direction Read/write Byte 00h Section 12.4.11 Port 1 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 1 Drive Strength Read/write Byte 00h Section 12.4.13 Port 1 Port Select Read/write Byte 00h Section 12.4.14 Port 1 Interrupt Edge Select Read/write Byte undefined Section 12.4.3 Port 1 Interrupt Enable Read/write Byte 00h Section 12.4.4 Port 1 Interrupt Flag Read/write Byte 00h Section 12.4.5 Port 2 Input Read only Byte Section 12.4.9 Port 2 Output Read/write Byte undefined Section 12.4.10 Port 2 Direction Read/write Byte 00h Section 12.4.11 Port 2 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 2 Drive Strength Read/write Byte 00h Section 12.4.13 Port 2 Port Select Read/write Byte 00h Section 12.4.14 Port 2 Interrupt Edge Select Read/write Byte undefined Section 12.4.6 Port 2 Interrupt Enable Read/write Byte 00h Section 12.4.7 Port 2 Interrupt Flag Read/write Byte 00h Section 12.4.8 Port 3 Input Read only Byte Section 12.4.9 Port 3 Output Read/write Byte undefined Section 12.4.10 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Offset 04h 06h 08h 0Ah 01h 03h 05h 07h 09h 0Bh 00h 02h 04h 06h 08h 0Ah 01h 03h 05h 07h 09h 0Bh 00h 02h 04h 06h 08h 0Ah Acronym P3DIR or PBDIR_L P3REN or PBREN_L P3DS or PBDS_L P3SEL or PBSEL_L P4IN or PBIN_H P4OUT or PBOUT_H P4DIR or PBDIR_H P4REN or PBREN_H P4DS or PBDS_H P4SEL or PBSEL_H P5IN or PCIN_L P5OUT or PCOUT_L P5DIR or PCDIR_L P5REN or PCREN_L P5DS or PCDS_L P5SEL or PCSEL_L P6IN or PCIN_H P6OUT or PCOUT_H P6DIR or PCDIR_H P6REN or PCREN_H P6DS or PCDS_H P6SEL or PCSEL_H P7IN or PDIN_L P7OUT or PDOUT_L P7DIR or PDDIR_L P7REN or PDREN_L P7DS or PDDS_L P7SEL or PDSEL_L Digital I/O Registers Table 12-2. Digital I/O Registers (continued) Register Name Port 3 Direction Type Access Reset Read/write Byte 00h Section Section 12.4.11 Port 3 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 3 Drive Strength Read/write Byte 00h Section 12.4.13 Port 3 Port Select Read/write Byte 00h Section 12.4.14 Port 4 Input Read only Byte Section 12.4.9 Port 4 Output Read/write Byte undefined Section 12.4.10 Port 4 Direction Read/write Byte 00h Section 12.4.11 Port 4 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 4 Drive Strength Read/write Byte 00h Section 12.4.13 Port 4 Port Select Read/write Byte 00h Section 12.4.14 Port 5 Input Read only Byte Section 12.4.9 Port 5 Output Read/write Byte undefined Section 12.4.10 Port 5 Direction Read/write Byte 00h Section 12.4.11 Port 5 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 5 Drive Strength Read/write Byte 00h Section 12.4.13 Port 5 Port Select Read/write Byte 00h Section 12.4.14 Port 6 Input Read only Byte Section 12.4.9 Port 6 Output Read/write Byte undefined Section 12.4.10 Port 6 Direction Read/write Byte 00h Section 12.4.11 Port 6 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 6 Drive Strength Read/write Byte 00h Section 12.4.13 Port 6 Port Select Read/write Byte 00h Section 12.4.14 Port 7 Input Read only Byte Section 12.4.9 Port 7 Output Read/write Byte undefined Section 12.4.10 Port 7 Direction Read/write Byte 00h Section 12.4.11 Port 7 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 7 Drive Strength Read/write Byte 00h Section 12.4.13 Port 7 Port Select Read/write Byte 00h Section 12.4.14 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 417 Digital I/O Registers Offset 01h 03h 05h 07h 09h 0Bh 00h 02h 04h 06h 08h 0Ah 01h 03h 05h 07h 09h 0Bh 00h 02h 04h 06h 08h 0Ah 00h 00h 01h 02h 02h 03h 04h Acronym P8IN or PDIN_H P8OUT or PDOUT_H P8DIR or PDDIR_H P8REN or PDREN_H P8DS or PDDS_H P8SEL or PDSEL_H P9IN or PEIN_L P9OUT or PEOUT_L P9DIR or PEDIR_L P9REN or PEREN_L P9DS or PEDS_L P9SEL or PESEL_L P10IN or PEIN_H P10OUT or PEOUT_H P10DIR or PEDIR_H P10REN or PEREN_H P10DS or PEDS_H P10SEL or PESEL_H P11IN or PFIN_L P11OUT or PFOUT_L P11DIR or PFDIR_L P11REN or PFREN_L P11DS or PFDS_L P11SEL or PFSEL_L PAIN PAIN_L PAIN_H PAOUT PAOUT_L PAOUT_H PADIR 418 Digital I/O Module www.ti.com Table 12-2. Digital I/O Registers (continued) Register Name Port 8 Input Type Read only Access Reset Byte Section Section 12.4.9 Port 8 Output Read/write Byte undefined Section 12.4.10 Port 8 Direction Read/write Byte 00h Section 12.4.11 Port 8 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 8 Drive Strength Read/write Byte 00h Section 12.4.13 Port 8 Port Select Read/write Byte 00h Section 12.4.14 Port 9 Input Read only Byte Section 12.4.9 Port 9 Output Read/write Byte undefined Section 12.4.10 Port 9 Direction Read/write Byte 00h Section 12.4.11 Port 9 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 9 Drive Strength Read/write Byte 00h Section 12.4.13 Port 9 Port Select Read/write Byte 00h Section 12.4.14 Port 10 Input Read only Byte Section 12.4.9 Port 10 Output Read/write Byte undefined Section 12.4.10 Port 10 Direction Read/write Byte 00h Section 12.4.11 Port 10 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 10 Drive Strength Read/write Byte 00h Section 12.4.13 Port 10 Port Select Read/write Byte 00h Section 12.4.14 Port 11 Input Read only Byte Section 12.4.9 Port 11 Output Read/write Byte undefined Section 12.4.10 Port 11 Direction Read/write Byte 00h Section 12.4.11 Port 11 Resistor Enable Read/write Byte 00h Section 12.4.12 Port 11 Drive Strength Read/write Byte 00h Section 12.4.13 Port 11 Port Select Read/write Byte 00h Section 12.4.14 Port A Input Port A Output Port A Direction Read only Read only Read only Read/write Read/write Read/write Read/write Word Byte Byte Word Byte Byte Word undefined undefined undefined 0000h SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Offset 04h 05h 06h 06h 07h 08h 08h 09h 0Ah 0Ah 0Bh 18h 18h 19h 1Ah 1Ah 1Bh 1Ch 1Ch 1Dh 00h 00h 01h 02h 02h 03h 04h 04h 05h 06h 06h 07h 08h 08h 09h 0Ah 0Ah 0Bh 00h 00h 01h 02h 02h 03h 04h 04h 05h Acronym PADIR_L PADIR_H PAREN PAREN_L PAREN_H PADS PADS_L PADS_H PASEL PASEL_L PASEL_H PAIES PAIES_L PAIES_H PAIE PAIE_L PAIE_H PAIFG PAIFG_L PAIFG_H PBIN PBIN_L PBIN_H PBOUT PBOUT_L PBOUT_H PBDIR PBDIR_L PBDIR_H PBREN PBREN_L PBREN_H PBDS PBDS_L PBDS_H PBSEL PBSEL_L PBSEL_H PCIN PCIN_L PCIN_H PCOUT PCOUT_L PCOUT_H PCDIR PCDIR_L PCDIR_H Digital I/O Registers Table 12-2. Digital I/O Registers (continued) Register Name Port A Resistor Enable Port A Drive Strength Port A Port Select Port A Interrupt Edge Select Port A Interrupt Enable Port A Interrupt Flag Port B Input Port B Output Port B Direction Port B Resistor Enable Port B Drive Strength Port B Port Select Port C Input Port C Output Port C Direction Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Access Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Reset 00h 00h 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h undefined undefined undefined 0000h 00h 00h 0000h 00h 00h undefined undefined undefined 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h undefined undefined undefined 0000h 00h 00h Section SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 419 Digital I/O Registers Offset 06h 06h 07h 08h 08h 09h 0Ah 0Ah 0Bh 00h 00h 01h 02h 02h 03h 04h 04h 05h 06h 06h 07h 08h 08h 09h 0Ah 0Ah 0Bh 00h 00h 01h 02h 02h 03h 04h 04h 05h 06h 06h 07h 08h 08h 09h 0Ah 0Ah 0Bh 00h 00h Acronym PCREN PCREN_L PCREN_H PCDS PCDS_L PCDS_H PCSEL PCSEL_L PCSEL_H PDIN PDIN_L PDIN_H PDOUT PDOUT_L PDOUT_H PDDIR PDDIR_L PDDIR_H PDREN PDREN_L PDREN_H PDDS PDDS_L PDDS_H PDSEL PDSEL_L PDSEL_H PEIN PEIN_L PEIN_H PEOUT PEOUT_L PEOUT_H PEDIR PEDIR_L PEDIR_H PEREN PEREN_L PEREN_H PEDS PEDS_L PEDS_H PESEL PESEL_L PESEL_H PFIN PFIN_L 420 Digital I/O Module www.ti.com Table 12-2. Digital I/O Registers (continued) Register Name Port C Resistor Enable Port C Drive Strength Port C Port Select Port D Input Port D Output Port D Direction Port D Resistor Enable Port D Drive Strength Port D Port Select Port E Input Port E Output Port E Direction Port E Resistor Enable Port E Drive Strength Port E Port Select Port F Input Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Access Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Reset 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h undefined undefined undefined 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h undefined undefined undefined 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h Section SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated www.ti.com Offset 01h 02h 02h 03h 04h 04h 05h 06h 06h 07h 08h 08h 09h 0Ah 0Ah 0Bh 00h 00h 01h 02h 02h 03h 04h 04h 05h 06h 06h 07h 08h 08h 09h Acronym PFIN_H PFOUT PFOUT_L PFOUT_H PFDIR PFDIR_L PFDIR_H PFREN PFREN_L PFREN_H PFDS PFDS_L PFDS_H PFSEL PFSEL_L PFSEL_H PJIN PJIN_L PJIN_H PJOUT PJOUT_L PJOUT_H PJDIR PJDIR_L PJDIR_H PJREN PJREN_L PJREN_H PJDS PJDS_L PJDS_H Digital I/O Registers Table 12-2. Digital I/O Registers (continued) Register Name Port F Output Port F Direction Port F Resistor Enable Port F Drive Strength Port F Port Select Port J Input Port J Output Port J Direction Port J Resistor Enable Port J Drive Strength Type Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Access Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Reset undefined undefined undefined 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h undefined undefined undefined 0000h 00h 00h 0000h 00h 00h 0000h 00h 00h Section SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 421 Digital I/O Registers 12.4.1 P1IV Register Port 1 Interrupt Vector Register 15 14 13 r0 r0 r0 7 6 5 r0 r0 r0 Figure 12-1. P1IV Register 12 11 10 P1IV r0 r0 r0 4 3 2 P1IV r-0 r-0 r-0 www.ti.com 9 8 r0 r0 1 0 r-0 r0 Bit 15-0 Field P1IV Type R Table 12-3. P1IV Register Description Reset 0h Description Port 1 interrupt vector value 00h = No interrupt pending 02h = Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG.0; Interrupt Priority: Highest 04h = Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG.1 06h = Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG.2 08h = Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG.3 0Ah = Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG.4 0Ch = Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG.5 0Eh = Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG.6 10h = Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG.7; Interrupt Priority: Lowest 422 Digital I/O Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 12.4.2 P2IV Register Port 2 Interrupt Vector Register 15 14 13 r0 r0 r0 7 6 5 r0 r0 r0 Figure 12-2. P2IV Register 12 11 10 P2IV r0 r0 r0 4 3 2 P2IV r-0 r-0 r-0 Digital I/O Registers 9 8 r0 r0 1 0 r-0 r0 Bit 15-0 Field P2IV Type R Table 12-4. P2IV Register Description Reset 0h Description Port 2 interrupt vector value 00h = No interrupt pending 02h = Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG.0; Interrupt Priority: Highest 04h = Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG.1 06h = Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG.2 08h = Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG.3 0Ah = Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG.4 0Ch = Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG.5 0Eh = Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG.6 10h = Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG.7; Interrupt Priority: Lowest SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 423 Digital I/O Registers 12.4.3 P1IES Register Port 1 Interrupt Edge Select Register Figure 12-3. P1IES Register 7 6 5 4 3 2 1 P1IES rw rw rw rw rw rw rw Bit Field 7-0 P1IES Type RW Table 12-5. P1IES Register Description Reset undefined Description Port 1 interrupt edge select 0b = P1IFG flag is set with a low-to-high transition. 1b = P1IFG flag is set with a high-to-low transition. 12.4.4 P1IE Register Port 1 Interrupt Enable Register Figure 12-4. P1IE Register 7 6 5 4 3 2 1 P1IE rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit Field 7-0 P1IE Type RW Table 12-6. P1IE Register Description Reset 0h Description Port 1 interrupt enable 0b = Corresponding port interrupt disabled 1b = Corresponding port interrupt enabled 12.4.5 P1IFG Register Port 1 Interrupt Flag Register Figure 12-5. P1IFG Register 7 6 5 4 3 2 1 P1IFG rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit Field 7-0 P1IFG Type RW Table 12-7. P1IFG Register Description Reset 0h Description Port 1 interrupt flag 0b = No interrupt is pending 1b = Interrupt is pending www.ti.com 0 rw 0 rw-0 0 rw-0 424 Digital I/O Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 12.4.6 P2IES Register Port 2 Interrupt Edge Select Register Figure 12-6. P2IES Register 7 6 5 4 3 2 P2IES rw rw rw rw rw rw Digital I/O Registers 1 0 rw rw Bit Field 7-0 P2IES Type RW Table 12-8. P2IES Register Description Reset undefined Description Port 2 interrupt edge select 0b = P2IFG flag is set with a low-to-high transition. 1b = P2IFG flag is set with a high-to-low transition. 12.4.7 P2IE Register Port 2 Interrupt Enable Register Figure 12-7. P2IE Register 7 6 5 4 3 2 1 0 P2IE rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit Field 7-0 P2IE Type RW Table 12-9. P2IE Register Description Reset 0h Description Port 2 interrupt enable 0b = Corresponding port interrupt disabled 1b = Corresponding port interrupt enabled 12.4.8 P2IFG Register Port 2 Interrupt Flag Register Figure 12-8. P2IFG Register 7 6 5 4 3 2 1 0 P2IFG rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit Field 7-0 P2IFG Type RW Table 12-10. P2IFG Register Description Reset 0h Description Port 2 interrupt flag 0b = No interrupt is pending 1b = Interrupt is pending SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 425 Digital I/O Registers 12.4.9 PxIN Register Port x Input Register 7 6 5 r r r Figure 12-9. PxIN Register 4 3 2 PxIN r r r www.ti.com 1 0 r r Bit Field 7-0 PxIN Type R Table 12-11. PxIN Register Description Reset Description undefined Port x input. Read only. 12.4.10 PxOUT Register Port x Output Register Figure 12-10. PxOUT Register 7 6 5 4 3 2 1 0 PxOUT rw rw rw rw rw rw rw rw Bit Field 7-0 PxOUT Type RW Table 12-12. PxOUT Register Description Reset undefined Description Port x output When I/O configured to output mode: 0b = Output is low 1b = Output is high When I/O configured to input mode and pullups/pulldowns enabled: 0b = Pulldown selected 1b = Pullup selected 12.4.11 PxDIR Register Port x Direction Register Figure 12-11. PxDIR Register 7 6 5 4 3 2 1 0 PxDIR rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit Field 7-0 PxDIR Type RW Table 12-13. PxDIR Register Description Reset 0h Description Port x direction 0b = Port configured as input 1b = Port configured as output 426 Digital I/O Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 12.4.12 PxREN Register Port x Pullup/Pulldown Resistor Enable Register Figure 12-12. PxREN Register 7 6 5 4 3 2 PxREN rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Digital I/O Registers 1 0 rw-0 rw-0 Bit Field 7-0 PxREN Type RW Table 12-14. PxREN Register Description Reset 0h Description Port x pullup or pulldown resistor enable. When respective port is configured as input, setting this bit will enable the pullup or pulldown. See Table 12-1 0b = Pullup or pulldown disabled 1b = Pullup or pulldown enabled 12.4.13 PxDS Register Port x Drive Strength Register Figure 12-13. PxDS Register 7 6 5 4 3 2 1 0 PxDS rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit Field 7-0 PxDS Type RW Table 12-15. PxDS Register Description Reset 0h Description Port x drive strength 0b = Reduced output drive strength 1b = Full output drive strength 12.4.14 PxSEL Register Port x Port Select Register Figure 12-14. PxSEL Register 7 6 5 4 3 2 1 0 PxSEL rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit Field 7-0 PxSEL Type RW Table 12-16. PxSEL Register Description Reset 0h Description Port x function selection 0b = I/O function is selected 1b = Peripheral module function is selected SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Digital I/O Module 427 Chapter 13 SLAU208O – June 2008 – Revised May 2015 Port Mapping Controller The port mapping controller allows a flexible mapping of digital functions to port pins. This chapter describes the port mapping controller. Topic ........................................................................................................................... Page 13.1 Port Mapping Controller Introduction.................................................................. 429 13.2 Port Mapping Controller Operation ..................................................................... 429 13.3 Port Mapping Controller Registers...................................................................... 431 428 Port Mapping Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Port Mapping Controller Introduction 13.1 Port Mapping Controller Introduction The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port pins. The port mapping controller features are: • Configuration protected by write access key. • Default mapping provided for each port pin (device-dependent, the device pinout in the device-specific data sheet). • Mapping can be reconfigured during runtime. • Each output signal can be mapped to several output pins. 13.2 Port Mapping Controller Operation The port mapping is configured with user software. The setup is discussed in the following sections. 13.2.1 Access To enable write access to any of the port mapping controller registers, the correct key must be written into the PMAPKEYID register. The PMAPKEYID register always reads 096A5h. Writing the key 02D52h grants write access to all port mapping controller registers. Read access is always possible. If an invalid key is written while write access is granted, any further write accesses are prevented. It is recommended that the application completes mapping configuration by writing an invalid key. There is a timeout counter implemented that is incremented with each (assembler) instruction, and when it counts to 32, the write access is locked again. Any access to the port mapping controller registers resets the counter. Interrupts should be disabled during the configuration process or the application should take precautions that the execution of an interrupt service routine does not accidentally cause a permanent lock of the port mapping registers; for example, by using the reconfiguration capability (see Section 13.2.2). The access status is reflected in the PMAPLOCK bit. By default, the port mapping controller allows only one configuration after PUC. A second attempt to enable write access by writing the correct key is ignored, and the registers remain locked. A PUC is required to disable the permanent lock again. If it is necessary to reconfigure the mapping during runtime, the PMAPRECFG bit must be set during the first write access timeslot. If PMAPRECFG is cleared during later configuration sessions, no more configuration sessions are possible. 13.2.2 Mapping For each port pin, Px.y, on ports providing the mapping functionality, a mapping register, PxMAPy, is available. Setting this register to a certain value maps a module's input and output signals to the respective port pin Px.y. The port pin itself is switched from a general purpose I/O to the selected peripheral/secondary function by setting the corresponding PxSEL.y bit to 1. If the input or the output function of the module is used, it is typically defined by the setting the PxDIR.y bit. If PxDIR.y = 0, the pin is an input, if PxDIR.y = 1, the pin is an output. There are also peripherals (for example, the USCI module) that control the direction or even other functions of the pin (for example, open drain), and these options are documented in the mapping table. With the port mapping functionality the output of a module can be mapped to multiple pins. Also the input of a module can receive inputs from multiple pins. When mapping multiple inputs onto one function, care needs to be taken because the input signals are logically ORed together without applying any priority; therefore, a logic one on any of the inputs results in a logic one at the module. If the PxSEL.y bit is 0, the corresponding input signal is a logic zero. The mapping is device-dependent; see the device-specific data sheet for available functions and specific values. The use of mapping mnemonics to abstract the underlying PxMAPy values is recommended to allow simple portability between different devices. Table 13-1 shows some examples for mapping mnemonics of some common peripherals. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Port Mapping Controller 429 Port Mapping Controller Operation www.ti.com All mappable port pins provide the function PM_ANALOG (0FFh). Setting the port mapping register PxMAPy to PM_ANALOG together with PxSEL.y = 1 disables the output driver and the input Schmitttrigger, to prevent parasitic cross currents when applying analog signals. Table 13-1. Examples for Port Mapping Mnemonics and Functions PxMAPy Mnemonic PM_NONE PM_ACLK PM_MCLK PM_SMCLK PM_TA0CLK PM_TA0CCR0A PM_TA0CCR1A PM_TA0CCR2A PM_TA0CCR3A PM_TA0CCR4A PM_TA1CLK PM_TA1CCR0A PM_TA1CCR1A PM_TA1CCR2A PM_TBCLK PM_TBOUTH PM_TBCCR0A PM_TBCCR1A PM_TBCCR2A PM_TBCCR3A PM_TBCCR4A PM_TBCCR5A PM_TBCCR6A PM_UCA0RXD PM_UCA0SOMI PM_UCA0TXD PM_UCA0SIMO PM_UCA0CLK PM_UCA0STE PM_UCB0SOMI PM_UCB0SCL PM_UCB0SIMO PM_UCB0SDA PM_UCB0CLK PM_UCB0STE PM_ANALOG Input Pin Function With PxSEL.y = 1 and PxDIR.y = 0 Output Pin Function With PxSEL.y = 1 and PxDIR.y = 1 None DVSS None ACLK None MCLK None SMCLK Timer_A0 clock input DVSS Timer_A0 CCR0 capture input CCI0A TA0 CCR0 compare output Out0 Timer_A0 CCR1 capture input CCI1A TA0 CCR1 compare output Out1 Timer_A0 CCR2 capture input CCI2A TA0 CCR2 compare output Out2 Timer_A0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3 Timer_A0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4 Timer_A1 clock input DVSS Timer_A1 CCR0 capture input CCI0A TA1 CCR0 compare output Out0 Timer_A1 CCR1 capture input CCI1A TA1 CCR1 compare output Out1 Timer_A1 CCR2 capture input CCI2A TA1 CCR2 compare output Out2 Timer_B clock input DVSS Timer_B outputs high impedance DVSS Timer_B CCR0 capture input CCI0A TB CCR0 compare output Out0 [direction controlled by Timer_B (TBOUTH)] Timer_B CCR1 capture input CCI1A TB CCR1 compare output Out1 [direction controlled by Timer_B (TBOUTH)] Timer_B CCR2 capture input CCI2A TB CCR2 compare output Out2 [direction controlled by Timer_B (TBOUTH)] Timer_B CCR3 capture input CCI3A TB CCR3 compare output Out3 [direction controlled by Timer_B (TBOUTH)] Timer_B CCR4 capture input CCI4A TB CCR4 compare output Out4 [direction controlled by Timer_B (TBOUTH)] Timer_B CCR5 capture input CCI3A TB CCR5 compare output Out5 [direction controlled by Timer_B (TBOUTH)] Timer_B CCR6 capture input CCI4A TB CCR6 compare output Out6 [direction controlled by Timer_B (TBOUTH)] USCI_A0 UART RXD (direction controlled by USCI - input) USCI_A0 SPI slave out master in (direction controlled by USCI) USCI_A0 UART TXD (direction controlled by USCI - output) USCI_A0 SPI slave in master out (direction controlled by USCI) USCI_A0 clock input/output (direction controlled by USCI) USCI_A0 SPI slave transmit enable (direction controlled by USCI) USCI_B0 SPI slave out master in (direction controlled by USCI) USCI_B0 I2C clock (open drain and direction controlled by USCI USCI_B0 SPI slave in master out (direction controlled by USCI) USCI_B0 I2C data (open drain and direction controlled by USCI) USCI_B0 clock input/output (direction controlled by USCI) USCI_B0 SPI slave transmit enable (direction controlled by USCI) Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals 430 Port Mapping Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com Port Mapping Controller Registers 13.3 Port Mapping Controller Registers The control register for the port mapping controller are listed in Table 13-2. The mapping registers are listed in Table 13-3. The mapping registers can also be accessed as words, as shown in Table 13-4. Offset 00h 02h Acronym PMAPKEYID PMAPCTL Table 13-2. Port Mapping Control Registers Register Name Port mapping key register Port mapping control register Type Read/write Read/write Reset Reset with PUC Reset with PUC Offset 00h 01h 02h 03h 04h 05h 06h 07h Table 13-3. Port Mapping Registers for Port Px – Byte Access Acronym PxMAP0 PxMAP1 PxMAP2 PxMAP3 PxMAP4 PxMAP5 PxMAP6 PxMAP7 Register Name Port Px.0 mapping register Port Px.1 mapping register Port Px.2 mapping register Port Px.3 mapping register Port Px.4 mapping register Port Px.5 mapping register Port Px.6 mapping register Port Px.7 mapping register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Reset Device dependent Device dependent Device dependent Device dependent Device dependent Device dependent Device dependent Device dependent Offset 00h 02h 04h 06h Table 13-4. Port Mapping Registers for Port Px – Word Access Acronym PxMAP01 PxMAP23 PxMAP45 PxMAP67 Register Name Port Px.0/Port Px.1 mapping register Port Px.2/Port Px.3 mapping register Port Px.4/Port Px.5 mapping register Port Px.6/Port Px.7 mapping register Type Read/write Read/write Read/write Read/write Reset Device dependent Device dependent Device dependent Device dependent SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Port Mapping Controller 431 Port Mapping Controller Registers 13.3.1 PMAPKEYID Register Port Mapping Key Register 15 14 13 7 6 5 Figure 13-1. PMAPKEYID Register 12 11 10 PMAPKEYx 4 3 2 PMAPKEYx www.ti.com 9 8 1 0 Bit 15-0 Field PMAPKEYx Table 13-5. PMAPKEYID Register Description Type RW Reset 96A5h Description Port write access key. Always reads 096A5h. Must be written 02D52h for write access to the port mapping registers. 13.3.2 PMAPCTL Register Port Mapping Control Register Figure 13-2. PMAPCTL Register 15 14 13 12 11 10 Reserved r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 Reserved r0 r0 r0 r0 r0 r0 9 8 r0 r0 1 PMAPRECFG rw-0 0 PMAPLOCKED r-1 Bit 15-2 1 Field Reserved PMAPRECFG 0 PMAPLOCKED Type R RW R Table 13-6. PMAPCTL Register Description Reset 0h 0h 1h Description Reserved. Always reads as 0. Port mapping reconfiguration control bit 0b = Configuration allowed only once 1b = Allow reconfiguration of port mapping Port mapping lock bit. Read only 0b = Access to mapping registers is granted 1b = Access to mapping registers is locked 13.3.3 PxMAPy Register Port Px.y Mapping Register Figure 13-3. PxMAPy Register 7 rw-0 (1) 6 rw-0 (1) 5 rw-0 (1) 4 3 PMAPx rw-0 (1) rw-0 (1) 2 rw-0 (1) (1) If not all bits are required to decode all provided functions, the unused bits are r0. 1 rw-0 (1) 0 rw-0 (1) Bit Field 7-0 PMAPx Type RW Table 13-7. PxMAPy Register Description Reset 0h Description Selects secondary port function. Settings are device-dependent; see the devicespecific data sheet. 432 Port Mapping Controller SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Chapter 14 SLAU208O – June 2008 – Revised May 2015 Cyclic Redundancy Check (CRC) Module The cyclic redundancy check (CRC) module provides a signature for a given data sequence. This chapter describes the operation and use of the CRC module. NOTE: The CRC module on the MSP430F543x and MSP430F541x non-A versions does not support the bit-wise reverse feature described in this module description. Registers CRCDIRB and CRCRESR, along with their respective functionality, are not available. Topic ........................................................................................................................... Page 14.1 Cyclic Redundancy Check (CRC) Module Introduction.......................................... 434 14.2 CRC Standard and Bit Order .............................................................................. 434 14.3 CRC Checksum Generation ............................................................................... 435 14.4 CRC Registers.................................................................................................. 438 SLAU208O – June 2008 – Revised May 2015 Cyclic Redundancy Check (CRC) Module 433 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Cyclic Redundancy Check (CRC) Module Introduction www.ti.com 14.1 Cyclic Redundancy Check (CRC) Module Introduction The CRC module produces a signature for a given sequence of data values. The signature is generated through a feedback path from data bits 0, 4, 11, and 15 (see Figure 14-1). The CRC signature is based on the polynomial given in the CRC-CCITT-BR polynomial (see Equation 12) . f(x) = x16 + x12 + x5 +1 (12) Data In QD QD QD QD QD QD QD QD QD QD Bit Bit 15 12 Bit Bit Bit Bit 11 10 6 5 Bit Bit Bit Bit 4 3 1 0 Shift Clock Figure 14-1. LFSR Implementation of CRC-CCITT Standard, Bit 0 is the MSB of the Result Identical input data sequences result in identical signatures when the CRC is initialized with a fixed seed value, whereas different sequences of input data, in general, result in different signatures. 14.2 CRC Standard and Bit Order The definitions of the various CRC standards were done in the era of main frame computers, and by convention bit 0 was treated as the MSB. Today, as in most microcontrollers such as the MSP430, bit 0 normally denotes the LSB. In Figure 14-1, the bit convention shown is as given in the original standards i.e. bit 0 is the MSB. The fact that bit 0 is treated for some as LSB, and for others as MSB, continues to cause confusion. The CRC16 module therefore provides a bit reversed register pair for CRC16 operations to support both conventions. 434 Cyclic Redundancy Check (CRC) Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com CRC Checksum Generation 14.3 CRC Checksum Generation The CRC generator is first initialized by writing a 16-bit word (seed) to the CRC Initialization and Result (CRCINIRES) register. Any data that should be included into the CRC calculation must be written to the CRC Data Input (CRCDI or CRCDIRB) register in the same order that the original CRC signature was calculated. The actual signature can be read from the CRCINIRES register to compare the computed checksum with the expected checksum. Signature generation describes a method on how the result of a signature operation can be calculated. The calculated signature, which is computed by an external tool, is called checksum in the following text. The checksum is stored in the product's memory and is used to check the correctness of the CRC operation result. 14.3.1 CRC Implementation To allow parallel processing of the CRC, the linear feedback shift register (LFSR) functionality is implemented with an XOR tree. This implementation shows the identical behavior as the LFSR approach after 8 bits of data are shifted in when the LSB is 'shifted' in first. The generation of a signature calculation has to be started by writing a seed to the CRCINIRES register to initialize the register. Software or hardware (for example, DMA) can transfer data to the CRCDI or CRCDIRB register (for example, from memory). The value in CRCDI or CRCDIRB is then included into the signature, and the result is available in the signature result registers at the next read access (CRCINIRES and CRCRESR). The signature can be generated using word or byte data. If a word data is processed, the lower byte at the even address is used at the first clock (MCLK) cycle. During the second clock cycle, the higher byte is processed. Thus, it takes two clock cycles to process word data, while it takes only one clock (MCLK) cycle to process byte data. Data bytes written to CRCDIRB in word mode or the data byte in byte mode are bit-wise reversed before the CRC engine adds them to the signature. The bits among each byte are reversed. Data bytes written to CRCDI in word mode or the data byte in byte mode are not bit reversed before use by the CRC engine. If the Check Sum itself (with reversed bit order) is included into the CRC operation (as data written to CRCDI or CRCDIRB), the result in the CRCINIRES and CRCRESR registers must be zero. SLAU208O – June 2008 – Revised May 2015 Cyclic Redundancy Check (CRC) Module 435 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CRC Checksum Generation Data In 8-bit or 16-bit CRC Data In Register CRCDI 8 8 Byte MUX 8 16 www.ti.com Write to CRCINIRES 16 CRC Initialization and Result Register CRCINIRES Figure 14-2. Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers 14.3.2 Assembler Examples 14.3.2.1 General Assembler Example This example demonstrates the operation of the on-chip CRC: ... PUSH PUSH MOV MOV MOV L1 MOV CMP JLO MOV TST JNZ ... POP POP R4 R5 #StartAddress,R4 #EndAddress,R5 &INIT, &CRCINIRES @R4+,&CRCDI R5,R4 L1 &Check_Sum,&CRCDI &CRCINIRES CRC_ERROR R5 R4 ; Save registers ; StartAddress < EndAddress ; INIT to CRCINIRES ; Item to Data In register ; End address reached? ; No ; Yes, Include checksum ; Result = 0? ; No, CRCRES <> 0: error ; Yes, CRCRES=0: ; information ok. ; Restore registers 436 Cyclic Redundancy Check (CRC) Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com CRC Checksum Generation 14.3.2.2 Reference Data Sequence The details of the implemented CRC algorithm is shown by the following data sequences using word or byte accesses and the CRC data-in as well as the CRC data-in reverse byte registers: ... mov mov.b mov.b mov.b mov.b mov.b mov.b mov.b mov.b mov.b #0FFFFh,&CRCINIRES #00031h,&CRCDI_L #00032h,&CRCDI_L #00033h,&CRCDI_L #00034h,&CRCDI_L #00035h,&CRCDI_L #00036h,&CRCDI_L #00037h,&CRCDI_L #00038h,&CRCDI_L #00039h,&CRCDI_L ; initialize CRC ; "1" ; "2" ; "3" ; "4" ; "5" ; "6" ; "7" ; "8" ; "9" cmp jeq br mov mov.w mov.w mov.w mov.w mov.b #089F6h,&CRCINIRES &Success &Error #0FFFFh,&CRCINIRES #03231h,&CRCDI #03433h,&CRCDI #03635h,&CRCDI #03837h,&CRCDI #039h, &CRCDI_L ; compare result ; CRCRESR contains 06F91h ; no error ; to error handler ; initialize CRC ; "1" & "2" ; "3" & "4" ; "5" & "6" ; "7" & "8" ; "9" cmp jeq br ... mov mov.b mov.b mov.b mov.b mov.b mov.b mov.b mov.b mov.b #089F6h,&CRCINIRES &Success &Error #0FFFFh,&CRCINIRES #00031h,&CRCDIRB_L #00032h,&CRCDIRB_L #00033h,&CRCDIRB_L #00034h,&CRCDIRB_L #00035h,&CRCDIRB_L #00036h,&CRCDIRB_L #00037h,&CRCDIRB_L #00038h,&CRCDIRB_L #00039h,&CRCDIRB_L ; compare result ; CRCRESR contains 06F91h ; no error ; to error handler ; initialize CRC ; "1" ; "2" ; "3" ; "4" ; "5" ; "6" ; "7" ; "8" ; "9" cmp jeq br ... mov mov.w mov.w mov.w mov.w mov.b #029B1h,&CRCINIRES &Success &Error ; compare result ; CRCRESR contains 08D94h ; no error ; to error handler #0FFFFh,&CRCINIRES #03231h,&CRCDIRB #03433h,&CRCDIRB #03635h,&CRCDIRB #03837h,&CRCDIRB #039h, &CRCDIRB_L ; initialize CRC ; "1" & "2" ; "3" & "4" ; "5" & "6" ; "7" & "8" ; "9" cmp #029B1h,&CRCINIRES ; compare result ; CRCRESR contains 08D94h jeq &Success ; no error br &Error ; to error handler SLAU208O – June 2008 – Revised May 2015 Cyclic Redundancy Check (CRC) Module 437 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CRC Registers www.ti.com 14.4 CRC Registers The CRC module registers are listed in Table 14-1. The base address can be found in the device-specific data sheet. The address offset is given in Table 14-1. NOTE: All registers have word or byte register access. For a generic register ANYREG, the suffix "_L" (ANYREG_L) refers to the lower byte of the register (bits 0 through 7). The suffix "_H" (ANYREG_H) refers to the upper byte of the register (bits 8 through 15). Table 14-1. CRC Registers Offset Acronym Register Name 0000h CRCDI CRC Data In 0000h CRCDI_L 0001h CRCDI_H 0002h CRCDIRB CRC Data In Reverse Byte(1) 0002h CRCDIRB_L 0003h CRCDIRB_H 0004h CRCINIRES CRC Initialization and Result 0004h CRCINIRES_L 0005h CRCINIRES_H 0006h CRCRESR CRC Result Reverse(1) 0006h CRCRESR_L 0007h CRCRESR_H (1) Not available on MSP430F543x and MSP430F541x non-A versions. Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read/write Read/write Access Word Byte Byte Word Byte Byte Word Byte Byte Word Byte Byte Reset 0000h 00h 00h 0000h 00h 00h FFFFh FFh FFh FFFFh FFh FFh Section Section 14.4.1 Section 14.4.2 Section 14.4.3 Section 14.4.4 438 Cyclic Redundancy Check (CRC) Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 14.4.1 CRCDI Register CRC Data In Register 15 14 13 rw-0 rw-0 rw-0 7 6 5 rw-0 rw-0 rw-0 Figure 14-3. CRCDI Register 12 11 10 CRCDI rw-0 rw-0 rw-0 4 3 2 CRCDI rw-0 rw-0 rw-0 CRC Registers 9 8 rw-0 rw-0 1 0 rw-0 rw-0 Bit 15-0 Field CRCDI Type RW Table 14-2. CRCDI Register Description Reset 0h Description CRC data in. Data written to the CRCDI register is included to the present signature in the CRCINIRES register according to the CRC-CCITT standard. 14.4.2 CRCDIRB Register CRC Data In Reverse Register Figure 14-4. CRCDIRB Register 15 14 13 12 11 10 9 8 CRCDIRB rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 CRCDIRB rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Bit 15-0 Field CRCDIRB Type RW Table 14-3. CRCDIRB Register Description Reset 0h Description CRC data in reverse byte. Data written to the CRCDIRB register is included to the present signature in the CRCINIRES and CRCRESR registers according to the CRC-CCITT standard. Reading the register returns the register CRCDI content. SLAU208O – June 2008 – Revised May 2015 Cyclic Redundancy Check (CRC) Module 439 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated CRC Registers 14.4.3 CRCINIRES Register CRC Initialization and Result Register Figure 14-5. CRCINIRES Register 15 14 13 12 11 10 CRCINIRES rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 7 6 5 4 3 2 CRCINIRES rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 www.ti.com 9 8 rw-1 rw-1 1 0 rw-1 rw-1 Bit 15-0 Field CRCINIRES Table 14-4. CRCINIRES Register Description Type RW Reset FFFFh Description CRC initialization and result. This register holds the current CRC result (according to the CRC-CCITT standard). Writing to this register initializes the CRC calculation with the value written to it. The value just written can be read from CRCINIRES register. 14.4.4 CRCRESR Register CRC Reverse Result Register Figure 14-6. CRCRESR Register 15 14 13 12 11 10 9 8 CRCRESR r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 7 6 5 4 3 2 1 0 CRCRESR r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 Bit 15-0 Field CRCRESR Type R Table 14-5. CRCRESR Register Description Reset FFFFh Description CRC reverse result. This register holds the current CRC result (according to the CRC-CCITT standard). The order of bits is reversed (for example, CRCINIRES[15] = CRCRESR[0]) compared to the order of bits in the CRCINIRES register (see example code). 440 Cyclic Redundancy Check (CRC) Module SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Chapter 15 SLAU208O – June 2008 – Revised May 2015 AES Accelerator The AES accelerator module performs AES128 encryption or decryption in hardware. This chapter describes the AES accelerator. Topic ........................................................................................................................... Page 15.1 AES Accelerator Introduction............................................................................. 442 15.2 AES Accelerator Operation ................................................................................ 443 15.3 AES_ACCEL Registers...................................................................................... 448 SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated AES Accelerator 441 AES Accelerator Introduction www.ti.com 15.1 AES Accelerator Introduction The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys according to the advanced encryption standard (AES) (FIPS PUB 197) in hardware. The AES accelerator features are: • Encryption and decryption according to AES FIPS PUB 197 with 128-bit key • On-the-fly key expansion for encryption and decryption • Off-line key generation for decryption • Byte and word access to key, input, and output data • AES ready interrupt flag The AES accelerator block diagram is shown in Figure 15-1. AESADIN AESAKEY Key Buffer AES128 Encryption/ Decryption Core AESADOUT Figure 15-1. AES Accelerator Block Diagram 442 AES Accelerator SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com AES Accelerator Operation 15.2 AES Accelerator Operation The AES accelerator is configured with user software. The setup and operation is discussed in the following sections. Internally, the AES algorithm’s operations are performed on a two-dimensional array of bytes called the State. For AES-128, the State consists of four rows of bytes, each containing four bytes. The input is assigned to the State array as illustrated in Figure 15-2, with in[0] being the first data byte written into the AES accelerator data input register, AESADIN. The encrypt or decrypt operations are then conducted on the State array, after which its final values can be read from the output with out[0] being the first data byte read from the AES accelerator data output register, AESADOUT. Input bytes State array Output bytes in[0] in[4] in[8] in[12] s[0,0] s[0,1] s[0,2] s[0,3] out[0] out[4] out[8] out[12] in[1] in[5] in[9] in[13] s[1,0] s[1,1] s[1,2] s[1,3] out[1] out[5] out[9] out[13] in[2] in[6] in[10] in[14] s[2,0] s[2,1] s[2,2] s[2,3] out[2] out[6] out[10] out[14] in[3] in[7] in[11] in[15] s[3,0] s[3,1] s[3,2] s[3,3] out[3] out[7] out[11] out[15] Figure 15-2. AES State Array Input and Output The module allows word and byte access to all data registers, AESAKEY, AESADIN, and AESADOUT. Word and byte access should not be mixed while reading from or writing into one of the registers. However, it is possible to write one of the registers using byte access and another using word access. NOTE: Access Restrictions While the AES accelerator is busy (AESBUSY = 1), AESADOUT always reads as zero, the AESDOUTCNTx counter, the AESDOUTRD flag, and the AESDINWR flag are reset, any attempt to change AESOPx, AESDINWR, or AESKEYWR is ignored, and writing to AESAKEY or AESADIN aborts the current operation, the complete module is reset (except for AESRDYIE and AESOPx), and the AES error flag AESERRFG is set. AESADIN and AESAKEY are write-only registers and always read as zero. Writing data into AESADIN influences the content of the corresponding output data; for example, writing in[0] alters out[0], writing in[1] alters out[1], etc., but interleafed operation is possible; for example, first reading out[0], then writing in[0], and continuing with reading out[1], writing in[1], etc. NOTE: When using a code debugger, the AES module does not stop its operation when program code is halted or single stepped. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated AES Accelerator 443 AES Accelerator Operation www.ti.com 15.2.1 Encryption Figure 15-3 shows the encryption process with the cipher being a series of transformations that converts the plaintext written into the AESADIN register to a ciphertext that can be read from the AESADOUT register using the cipher key provided via the AESAKEY register. Encryption Process Cipher Key (AESAKEY) Plaintext (AESADIN) Initial Key Round Key 1 Round Key 2 Initial Round Round 1 Round 2 Cipher Round Key 9 Round Key 10 Round 9 Final Round Ciphertext (AESADOUT) Figure 15-3. AES-128 Encryption Process The steps to perform encryption are: 1. Set AESOPx = 00 to select encryption. Changing the AESOPx bits clears the AESKEYWR flag, and a new key must be loaded in the next step. 2. Load the 128-bit key into AESAKEY or set the AESKEYWR flag by software, if the key from a previous operation should be used. When all 16 bytes are written, the AESKEYWR flag indicates completion. If a key was loaded previously without changing AESOPx, the AESKEYWR flag is cleared with the first write access to AESAKEY. Loading the key mist be completed before the next step is performed. 3. Load 128-bit data into AESADIN, or set the AESDINWR flag by software if the output data from a previous operation should be encrypted. When all 16 bytes are written, the AESDINWR flag indicates completion. The module starts encrypting the presented data when AESDINWR = 1. 4. While the AES module is performing encryption, the AESBUSY bit is 1. The encryption takes 167 MCLK clock cycles. After its completion, the AESRDYIFG is set, and the result can be read from AESADOUT. When all 16 bytes are read, the AESDOUTRD flag indicates completion. The AESRDYIFG flag is cleared when reading AESADOUT or writing to AESAKEY or AESADIN. 5. If additional data should be encrypted with the same key loaded in step 2, new data can be written into AESADIN after the results of the operation on the previous data were read from AESADOUT. When an additional 16 data bytes are written, the module automatically starts the encryption using the key loaded in step 2. When using the output feedback (OFB) cipher block chaining mode, setting the AESDINWR flag is sufficient to trigger the next encryption, and the module starts the encryption automatically using the output data from the previous encryption as input data. 444 AES Accelerator SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com AES Accelerator Operation 15.2.2 Decryption Figure 15-4 shows the decryption process with the inverse cipher being a series of transformations that convert the ciphertext written into the AESADIN register to a plaintext that can be read from the AESADOUT register using the cipher key provided via the AESAKEY register. Decrypt Key Generation Decryption Process – Inverse Cipher Cipher Key (AESAKEY) Plaintext (AESADOUT) Initial Key Round Key 1 Initial Key Round Key 1 Inverse Initial Round Inverse Round 1 Round Key 2 Round Key 2 Inverse Round 2 Inverse Cipher Round Key 9 Round Key 10 Round Key 9 Round Key 10 Inverse Round 9 Inverse Final Round Ciphertext (AESADIN) Figure 15-4. AES-128 Decryption Process using AESOPx = 01 The steps to perform decryption are: 1. Set AESOPx = 01 to select decryption using the same key used for encryption. Set AESOPx = 11 if the first-round key required for decryption (round key 10) is already generated and is loaded in step 2. Changing the AESOPx bits clears the AESKEYWR flag, and a new key must be loaded in step 2. 2. Load the 128-bit key into AESAKEY, or set the AESKEYWR flag by software, if the key from a previous operation should be used. When all 16 bytes are written, the AESKEYWR flag indicates completion. If a key was loaded previously without changing AESOPx, the AESKEYWR flag is cleared with the first write access to AESAKEY. Loading the key must be completed before the next step is performed. 3. Load 128-bit data into AESADIN or set the AESDINWR flag by software if the output data from a previous operation should be decrypted. When all 16 bytes are written, the AESDINWR flag indicates completion. The module starts decrypting the presented data as soon as AESDINWR = 1. 4. While the AES module is performing decryption, the AESBUSY bit is 1. The decryption takes 214 MCLK clock cycles with AESOPx = 01 and 167 MCLK clock cycles with AESOPx = 11. After its completion, the AESRDYIFG is set, and the result can be read from AESADOUT. When all 16 bytes are read the AESDOUTRD flag indicates completion. The AESRDYIFG flag is cleared when reading AESADOUT or writing to AESAKEY or AESADIN. 5. If additional data should be decrypted with the same key loaded in step 2, new data can be written into AESADIN after the results of the operation on the previous data were read from AESADOUT. When additional 16 data bytes are written, the module automatically starts the decryption using the key loaded in step 2. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated AES Accelerator 445 AES Accelerator Operation www.ti.com 15.2.3 Decryption Key Generation Figure 15-5 shows the decryption process with a pregenerated decryption key. In this case, the decryption key is calculated first with AESOPx = 10, then the precalculated key can be used together with the decryption operation AESOPx = 11. Decrypt Key Generation (AESOPx = 10) Cipher Key (AESAKEY) Decryption Process – Inverse Cipher (AESOPx = 11) Plaintext (AESADOUT) Initial Key Round Key 1 Initial Key Round Key 1 Inverse Initial Round Inverse Round 1 Round Key 2 Round Key 2 Inverse Round 2 Inverse Cipher Round Key 9 Round Key 10 Pregenerated Key (AESADOUT) Round Key 9 Round Key 10 Pregenerated Key (AESAKEY) Inverse Round 9 Inverse Final Round Ciphertext (AESADIN) Figure 15-5. AES-128 Decryption Process using AESOPx = 10 and 11 To generate the decryption key independent from the actual decryption, the following steps are required: 1. Set AESOPx = 10 to select decryption key generation. Changing the AESOPx bits clears the AESKEYWR flag, and a new key must be loaded in step 2. 2. Load the 128-bit key into AESAKEY, or set the AESKEYWR flag by software if the key from a previous operation should be used. When all 16 bytes are written, the AESKEYWR flag indicates completion. The generation of the first round key required for decryption is started immediately. 3. While the AES module is performing the key generation, the AESBUSY bit is 1. It takes 52 CPU clock cycles to complete the key generation. After its completion, the AESRDYIFG is set, and the result can be read from AESADOUT. When all 16 bytes are read, the AESDOUTRD flag indicates completion. The AESRDYIFG flag is cleared when reading AESADOUT or writing to AESAKEY or AESADIN. 4. If data should be decrypted with the generated key, AESOPx must be set to 11. Then the generated key must be loaded or, if it was just generated with AESOPx = 10, it is sufficient to set the AESKEYWR flag by software to indicate that the key is already valid. Afterward, the steps described in Section 15.2.2 to load the data, etc., must be followed. 446 AES Accelerator SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com AES Accelerator Operation 15.2.4 Using the AES Accelerator With Low-Power Modes The AES accelerator module provides automatic clock activation for MCLK for use with low-power modes. When the AES accelerator is busy, it automatically activates MCLK, regardless of the control-bit settings for the clock source. The clock remains active until the AES accelerator completes its operation. 15.2.5 AES Accelerator Interrupts The AESRDYIFG interrupt flag is set when the AES module completes the selected operation on the provided data. An interrupt request is generated if AESRDYIE and GIE are also set. AESRDYIFG is automatically reset if the AES interrupt is serviced, if AESADOUT is read, or if AESADIN or AESAKEY are written. AESRDYIFG is reset after a PUC or with AESSWRST = 1. AESRDYIE is reset after a PUC but is not reset by AESSWRST = 1. 15.2.6 Implementing Block Cipher Modes All block cipher modes can be implemented using the AES accelerator together with software. A separate application report describes the block cipher modes together with their implementation in software. SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated AES Accelerator 447 AES_ACCEL Registers 15.3 AES_ACCEL Registers The AES Accelerator registers are listed in Table 15-1. Offset 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh Acronym AESACTL0 AESACTL1 AESASTAT AESAKEY AESADIN AESADOUT AESAXDIN AESAXIN Table 15-1. AES_ACCEL Registers Register Name AES accelerator control register 0 AES accelerator control register 1 AES accelerator status register AES accelerator key register AES accelerator data in register AES accelerator data out register AES accelerator XORed data in register AES accelerator XORed data in register (no trigger) Type Read/write Read/write Read only Read/write Read/write Read/write Read/write Read/write Access Word Word Word Word Word Word Word Word Reset 00h 00h 00h 00h 00h 00h 00h 00h www.ti.com Section Section 15.3.1 Section 15.3.2 Section 15.3.3 Section 15.3.4 Section 15.3.5 Section 15.3.6 Section 15.3.7 Section 15.3.8 448 AES Accelerator SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.3.1 AESACTL0 Register AES Accelerator Control Register 0 AESACTL0 is shown in Figure 15-6 and described in Table 15-2. AES_ACCEL Registers 15 AESCMEN rw-0 7 AESSWRST rw-0 14 13 Reserved r0 r0 6 5 AESCMx r0 r0 Figure 15-6. AESACTL0 Register 12 11 10 9 AESRDYIE AESERRFG Reserved rw-0 rw-0 r0 r0 8 AESRDYIFG rw-0 4 Reserved r0 3 2 AESKLx rw-0 rw-0 1 0 AESOPx rw-0 rw-0 Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. Bit Field 15 AESCMEN 14-13 12 Reserved AESRDYIE 11 AESERRFG 10-9 8 Reserved AESRDYIFG 7 AESSWRST 6-5 AESCMx 4 Reserved Table 15-2. AESACTL0 Register Description Type RW R RW RW R RW RW R R Reset 0h 0h 0h 0h 0h 0h 0h 0h 0h Description AESCMEN enables the support of the ciphermodes ECB, CBC, OFB, and CFB together with the DMA. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 0 = No DMA triggers are generated 1 = DMA ciphermode support operation is enabled and the corresponding DMA triggers are generated. Reserved AES ready interrupt enable. AESRDYIE is not reset by AESSWRST = 1. 0 = Interrupt disabled 1 = Interrupt enabled AES error flag. AESAKEY or AESADIN were written while an AES operation was in progress. The bit must be cleared by software. 0 = No error 1 = Error occurred Reserved AES ready interrupt flag. Set when the selected AES operation was completed and the result can be read from AESADOUT. Automatically cleared when AESADOUT is read or AESAKEY or AESADIN is written. 0 = No interrupt pending 1 = Interrupt pending AES software reset. Immediately resets the complete AES accelerator module even when busy except for the AESRDYIE, AESKLx, and AESOPx bits. It also clears the (internal) state memory. The AESSWRST bit is automatically reset and always reads as zero. 0 = No reset 1 = Reset AES accelerator module AES cipher mode select. These bits are ignored for AESCMEN = 0. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 00 = ECB 01 = CBC 10 = OFB 11 = CFB Reserved SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated AES Accelerator 449 AES_ACCEL Registers Bit Field 3-2 AESKLx 1-0 AESOPx www.ti.com Table 15-2. AESACTL0 Register Description (continued) Type RW RW Reset 0h 0h Description AES key length. These bits define which of the three AES standards is performed. The AESKLx bits are not reset by AESSWRST = 1. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 00 = AES128. The key size is 128 bit. 01 = AES192. The key size is 192 bit. 10 = AES256. The key size is 256 bit. 11 = Reserved AES operation. The AESOPx bits are not reset by AESSWRST = 1. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 00 = Encryption 01 = Decryption. The provided key is the same key used for encryption. 10 = Generate first round key required for decryption. 11 = Decryption. The provided key is the first round key required for decryption. 15.3.2 AESACTL1 Register AES Accelerator Control Register 1 AESACTL1 is shown in Figure 15-7 and described in Table 15-3. Figure 15-7. AESACTL1 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 AESBLKCNTx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. Bit 15-8 7-0 Field Reserved AESBLKCNTx Table 15-3. AESACTL1 Register Description Type R RW Reset 0 0 Description Reserved. Always reads 0. Cipher Block Counter. Number of blocks to be encrypted or decrypted with block cipher modes enabled (AESCMEN = 1). Ignored if AESCMEN = 0. The block counter decrements with each performed encryption or decryption. Writes are ignored when AESCMEN = 1 and AESBLKCNTx > 0. 450 AES Accelerator SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.3.3 AESASTAT Register AES Accelerator Status Register AESASTAT is shown in Figure 15-8 and described in Table 15-4. AES_ACCEL Registers Figure 15-8. AESASTAT Register 15 14 13 12 11 10 9 8 AESDOUTCNTx AESDINCNTx r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 AESKEYCNTx AESDOUTRD AESDINWR AEKEYWR AESBUSY r-0 r-0 r-0 r-0 r-0 rw-0 rw-0 r-0 Bit 15-12 Field AESDOUTCNTx 11-8 AESDINCNTx 7-4 AESKEYCNTx 3 AESDOUTRD 2 AESDINWR 1 AESKEYWR 0 AESBUSY Table 15-4. AESASTAT Register Description Type R R R R RW RW R Reset 0h 0h 0h 0h 0h 0h 0h Description Bytes read from AESADOUT. Reset when AESDOUTRD is reset. If AESDOUTCNTx = 0 and AESDOUTRD = 0, no bytes were read. If AESDOUTCNTx = 0 and AESDOUTRD = 1, all bytes were read. Bytes written by AESADIN, AESAXDIN, or AESAXIN. Reset when AESDINWR is reset. If AESDINCNTx = 0 and AESDINWR = 0, no bytes were written. If AESDINCNTx = 0 and AESDINWR = 1, all bytes were written. Bytes written by AESAKEY for AESKLx = 00, words written by AESAKEY if AESKLx = 01, 10, or 11. Reset when AESKEYWR is reset. If AESKEYCNTx = 0 and AESKEYWR = 0, no bytes were written. If AESKEYCNTx = 0 and AESKEYWR = 1, all bytes were written. All 16 bytes read from AESADOUT. AESDOUTRD is reset by PUC, AESSWRST, an error condition, changing AESOPx, changing AESKLx, when the AES accelerator is busy, or when the output data is read again. 0 = Not all bytes read 1 = All bytes read All 16 bytes written to AESADIN, AESAXDIN, or AESAXIN. This bit can be modified by software only if AESCMEN = 0. Changing its state by software also resets the AESDINCNTx bits. AESDINWR is reset by PUC, AESSWRST, an error condition, changing AESOPx, changing AESKLx, the start to (over)write the data, or when the AES accelerator is busy. Because it is reset when AESOPx or AESKLx is changed, it can be set by software again to indicate that the current data is still valid. 0 = Not all bytes written 1 = All bytes written All 16 bytes written to AESAKEY. This bit can be modified by software but it must not be reset by software (1→0) if AESCMEN = 1. Changing its state by software also resets the AESKEYCNTx bits. AESKEYWR is reset by PUC, AESSWRST, an error condition, changing AESOPx, changing AESKLx, or the start to (over)write a new key. Because it is reset when AESOPx is changed, it can be set by software again to indicate that the loaded key is still valid. 0 = Not all bytes written 1 = All bytes written AES accelerator module busy; encryption, decryption, or key generation in progress. 0 = Not busy 1 = Busy SLAU208O – June 2008 – Revised May 2015 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated AES Accelerator 451 AES_ACCEL Registers 15.3.4 AESAKEY Register AES Accelerator Key Register AESAKEY is shown in Figure 15-9 and described in Table 15-5. Figure 15-9. AESAKEY Register 15 14 13 12 11 10 9 AESKEY1x (Key Byte n+1) w-0 w-0 w-0 w-0 w-0 w-0 w-0 7 6 5 4 3 2 1 AESKEY0x (Key Byte n) w-0 w-0 w-0 w-0 w-0 w-0 w-0 Bit 15-8 Field AESKEY1x 7-0 AESKEY0x Type W W Table 15-5. AESAKEY Register Description Reset 0 0 Description AES key byte n+1 when AESAKEY is written as word. Do not use these bits for byte access. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1. AES key byte n when AESAKEY is written as word. AES next key byte when AESAKEY_L is written as byte. Do not mix word and byte access. Always reads as zero. The key is reset by PUC or by AESSWRST = 1. www.ti.com 8 w-0 0 w-0 452 AES Accelerator SLAU208O – June 2008 – Revised May 2015 Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback www.ti.com 15.3.5 AESADIN Register AES Accelerator Data In Register AESADIN is shown in Figure 15-10 and described in Table 15-6. Figure 15-10. AESADIN Register 15 14 13 12 11 10 AESDIN1x (DIN Byte n+1) w-0 w-0 w-0 w-0 w-0 w-0 7 6 5 4 3 2 AESDIN0x (DIN Byte n) w-0 w-0 w-0 w-0 w-0 w-0 AES_ACCEL Registers 9 8 w-0 w-0 1 0 w-0 w-0 Bit 15-8 Field AESDIN1x 7-0 AESDIN0x Type W W Table 15-6. AESADIN Register Description Reset 0 0 Description AES data in byte n+1 when AESADIN is