本文提出了一种可在LDO应用中使用的两相运算放大器,它具有很高的PSRR,CMRR,相位裕度和增益值。 拟议的设计已在联电180nm技术中实现。 设计电路的拓扑结构要求差分对通过CSA和用于输出目的的公共漏极配置进行跟踪。 提出的设计用于获得98.277dB的高PSRR值,该值用于LDO征求。 在1.8V下用尽Cadence,Virtuoso,Spectre和Assura软件进行仿真,在43.892MHz的单位带宽下获得61dB的增益和60.045deg的相位裕量,功耗小于0.214mW,CMRR为62.309dB。 完整的定制IC布局设计占地约20,000平方微米。
This paper presents 2-phase operational -Amplifier that can be cast-off for LDO applicationthat provides a very high value of PSRR, CMRR, Phase margin and Gain. The proposed designwas implemented in UMC 180nm technology. The topology of the design circuit entails of adifferential pair tracked up through a CSA and common drain configuration which is used forloading purposes. The proposed design is used to obtain a high PSRR value of 98.277dB whichis used for LDO solicitations. Simulation is done exhausting software Cadence, Virtuoso,Spectre and Assura under 1.8V to obtain Gain of 61dB and Phase margin of 60.045deg at unitybandwidth of 43.892MHz with power dissipation less than 0.214mW along with CMRR of62.309dB. A full custom IC layout design occupies the area of about 20,000 square micrometers.
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