首页资源分类IC设计及制造 > IS42S1参考资料

IS42S1参考资料

已有 460221个资源

下载专区


TI最新应用解决方案

工业电子 汽车电子 个人消费电子

文档信息举报收藏

标    签: IS

分    享:

文档简介

芯片资料,详细内容丰富

文档预览

IS42S16400F 捷多邦,您值得信赖的PCB打样专家! IC42S16400F 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM March 2008 FEATURES • Clock frequency: 200, 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Self refresh modes • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Package: 400-mil 54-pin TSOP II • Lead-free package is available • Available in Industrial Temperature • Please contact Product Manager for informa- tion on mobile functions (Power Down and Deep Power Down Mode, Partial Array Self Refresh, Temperature Compensated Self Refresh, Output Driver Strength Selection) OVERVIEW ISSI's 64Mb Synchronous DRAM IS42S16400F and IC42S16400F are organized as 1,048,576 bits x 16-bit x 4-bank for improved performance.ThesynchronousDRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS 54-Pin TSOP (Type II) VDD 1 DQ0 2 VDDQ 3 DQ1 4 DQ2 5 GNDQ 6 DQ3 7 DQ4 8 VDDQ 9 DQ5 10 DQ6 11 GNDQ 12 DQ7 13 VDD 14 LDQM 15 WE 16 CAS 17 RAS 18 CS 19 BA0 20 BA1 21 A10 22 A0 23 A1 24 A2 25 A3 26 VDD 27 54 GND 53 DQ15 52 GNDQ 51 DQ14 50 DQ13 49 VDDQ 48 DQ12 47 DQ11 46 GNDQ 45 DQ10 44 DQ9 43 VDDQ 42 DQ8 41 GND 40 NC 39 UDQM 38 CLK 37 CKE 36 NC 35 A11 34 A9 33 A8 32 A7 31 A6 30 A5 29 A4 28 GND PIN DESCRIPTIONS A0-A11 Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command WE LDQM UDQM VDD GND VDDq GNDq NC Write Enable Lower Bye, Input/Output Mask Upper Bye, Input/Output Mask Power Ground Power Supply for DQ Pin Ground for DQ Pin No Connection Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. A 03/19/08 IS42S16400F IC42S16400F GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 64Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled.  Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM CLK CKE CS RAS CAS WE A10 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 COMMAND DECODER & CLOCK GENERATOR MODE REGISTER 12 ROW ADDRESS 12 LATCH COLUMN ADDRESS LATCH 8 BURST COUNTER COLUMN ADDRESS BUFFER 2 MULTIPLEXER ROW DECODER REFRESH CONTROLLER SELF REFRESH CONTROLLER REFRESH COUNTER ROW ADDRESS BUFFER 12 DATA IN BUFFER 16 16 DQM DQ 0-15 DATA OUT BUFFER 16 16 VDD/VDDQ GND/GNDQ 4096 4096 4096 MEMORY CELL 12 4096 ARRAY BANK 0 SENSE AMP I/O GATE BANK CONTROL LOGIC 256K (x 16) COLUMN DECODER 8 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F PIN FUNCTIONS Symbol TSOP Pin No. Type A0-A11 23 to 26 Input Pin 29 to 34 22, 35 BA0, BA1 CAS CKE 20, 21 17 37 Input Pin Input Pin Input Pin CLK 38 Input Pin CS 19 Input Pin DQ0 to DQ15 LDQM, UDQM 2, 4, 5, 7, 8, 10, 11,13, 42, 44, 45, 47, 48, 50, 51, 53 15, 39 DQ Pin Input Pin RAS WE Vddq Vdd GNDq GND 18 Input Pin 16 Input Pin 3, 9, 43, 49 1, 14, 27 6, 12, 46, 52 28, 41, 54 Power Supply Pin Power Supply Pin Power Supply Pin Power Supply Pin Function (In Detail) Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (A0-A7 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the "Command Truth Table" for details on device commands. The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, clock suspend mode, or self refresh mode. CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. DQ0 to DQ15 are I/O pins. I/O through these pins can be controlled in byte units using the LDQM and UDQM pins. LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE, forms the device command. See the "Command Truth Table" item for details on device commands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command Truth Table" item for details on device commands. Vddq is the output buffer power supply. Vdd is the device internal power supply. GNDq is the output buffer ground. GND is the device internal ground. Integrated Silicon Solution, Inc. — www.issi.com 3 Rev.  A 03/19/08 IS42S16400F IC42S16400F Function (In Detail) A0-A11 are address inputs sampled during the ACTIVE (row-address A0-A11) and READ/WRITE command (A0-A7 with A10 defining auto PRECHARGE). A10 is sampled during a PRECHARGE command to determine if all banks are to be PRECHARGED (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address (BA0 and BA1) defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the “Command Truth Table” for details on device commands. The CKE input determines whether the CLK input is enabled. The next rising edge of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW, the device will be in either power-down mode, CLOCK SUSPEND mode, or SELF-REFRESH mode. CKE is an asynchronous input. CLK is the master clock input for this device. Except for CKE, all inputs to this device are acquired in synchronization with the rising edge of this pin. The CS input determines whether command input is enabled within the device. Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device remains in the previous state when CS is HIGH. DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units using the LDQM and UDQM pins. LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH Impedance State when LDQM/UDQM is HIGH. This function corresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be written to the device. RAS, in conjunction with CAS and WE , forms the device command. See the “Command Truth Table” item for details on device commands. WE , in conjunction with RAS and CAS , forms the device command. See the “Command Truth Table” item for details on device commands. VDDq is the output buffer power supply. VDD is the device internal power supply. GNDq is the output buffer ground. GND is the device internal ground. 4 READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A7 provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ’s read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ’s will be High-Z two clocks later. DQ’s will provide valid data when the DQM signal was registered LOW. WRITE A burst write access to an active row is initiated with the WRITE command. BA0, BA1 inputs selects the bank, and the starting column location is provided by inputs A0-A7. Whether or not AUTO-PRECHARGE is used is determined by A10. The row being accessed will be precharged at the end of the WRITE burst, if AUTO PRECHARGE is selected. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. A memory array is written with corresponding input data on DQ’s and DQM input logic level appearing at the same time. Data will be written to memory when DQM signal is LOW. When DQM is HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. BA0, BA1 can be used to select which bank is precharged or they are treated as “Don’t Care”. A10 determined whether one or all banks are precharged. After executing this command, the next command for the selected banks(s) is executed after passage of the period tRP, which is the period required for bank precharging. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE The AUTO PRECHARGE function ensures that the precharge is initiated at the earliest valid stage within a burst. This function allows for individual-bank precharge without requiring an explicit command. A10 to enables the AUTO PRECHARGE function in conjunction with a specific READ or WRITE command. For each individual READ or WRITE command, auto precharge is either enabled or disabled. Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed. AUTO REFRESH COMMAND This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically generatedduringthisoperation.  Thestipulatedperiod(trc) is required for a single refresh operation, and no other commands can be executed during this period.  This command is executed at least 4096 times every 64ms. During an AUTO REFRESH command, address bits are “Don’t Care”. This command corresponds to CBR Auto-refresh. SELF REFRESH During the SELF REFRESH operation, the row address to be refreshed, the bank, and the refresh interval are generated automatically internally. SELF REFRESH can be used to retain data in the SDRAM without external clocking, even if the rest of the system is powered down. The SELF REFRESH operation is started by dropping the CKE pin from HIGH to LOW. During the SELF REFRESH operation all other inputs to the SDRAM become “Don’t Care”. The device must remain in self refresh mode for a minimum period equal to tras or may remain in self refresh mode for an indefinite period beyond that. The SELF-REFRESH operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins. The next command cannot be executed until the device internal recovery period (trc) has elapsed. Once CKE goes HIGH, the NOP command must be issued (minimum of two clocks) to provide time for the completion of any internal refresh in progress. After the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an AUTO-REFRESH should immediately be performed for all addresses. BURST TERMINATE The BURST TERMINATE command forcibly terminates the burst read and write operations by truncating either fixed-length or full-page bursts and the most recently registered READ or WRITE command prior to the BURST TERMINATE. COMMAND INHIBIT COMMAND INHIBIT prevents new commands from being executed. Operations in progress are not affected, apart from whether the CLK signal is enabled NO OPERATION When CS is low, the NOP command prevents unwanted commands from being registered during idle or wait states. LOAD MODE REGISTER During the LOAD MODE REGISTER command the mode register is loaded from A0-A11. This command can only be issued when all banks are idle. ACTIVE COMMAND When the ACTIVE COMMAND is activated, BA0, BA1 inputs selects a bank to be accessed, and the address inputs on A0-A11 selects the row. Until a PRECHARGE command is issued to the bank, the row remains open for accesses. Integrated Silicon Solution, Inc. — www.issi.com 5 Rev.  A 03/19/08 IS42S16400F IC42S16400F TRUTH TABLE – COMMANDS AND DQM OPERATION(1) FUNCTION CS RAS CAS WE DQM ADDR DQs COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row)(3) L L H H X Bank/Row X READ (Select bank/column, start READ burst)(4) L H L H L/H(8) Bank/Col X WRITE (Select bank/column, start WRITE burst)(4) L H L L L/H(8) Bank/Col Valid BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks)(5) L L H L X Code X AUTO REFRESH or SELF REFRESH(6,7) L L L H X X X (Enter self refresh mode) LOAD MODE REGISTER(2) L L L L X Op-Code X Write Enable/Output Enable(8) ­— ­— ­— ­— L ­— Active Write Inhibit/Output High-Z(8) ­— ­— ­— ­— H ­— High-Z NOTES: 1. CKE is HIGH for all commands except SELF REFRESH. 2. A0-A11 define the op-code written to the mode register. 3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. 4. A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables auto precharge; BA0, BA1 determine which bank is being read from or written to. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 6. AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 6 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F TRUTH TABLE – CKE (1-4) CURRENT STATE COMMANDn Power-Down X Self Refresh X Clock Suspend X Power-Down(5) COMMAND INHIBIT or NOP Self Refresh(6) COMMAND INHIBIT or NOP Clock Suspend(7) X All Banks Idle COMMAND INHIBIT or NOP All Banks Idle AUTO REFRESH Reading or Writing VALID ACTIONn Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Exit Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Self Refresh Entry Clock Suspend Entry CKEn-1 L L L L L L H H H CKEn L L L H H H L L L See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n H H NOTES: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that tcks is met). 6. Exiting self refresh at clock edge n will put the device in all banks idle state once txsr is met. COMMAND INHIBIT or NOP commands should be issued on clock edges occurring during the txsr period. A minimum of two NOP commands must be sent during txsr period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1. TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6) CURRENT STATE COMMAND (ACTION) CS RAS CAS WE Any COMMAND INHIBIT (NOP/Continue previous operation) HX XX NO OPERATION (NOP/Continue previous operation) LH HH Idle ACTIVE (Select and activate row) L L HH AUTO REFRESH(7) LL LH LOAD MODE REGISTER(7) LL LL PRECHARGE(11) LL HL Row Active READ (Select column and start READ burst)(10) LH LH WRITE (Select column and start WRITE burst)(10) LH LL PRECHARGE (Deactivate row in bank or banks)(8) LL HL Read READ (Select column and start new READ burst)(10) LH LH (Auto WRITE (Select column and start WRITE burst)(10) LH LL Precharge PRECHARGE (Truncate READ burst, start PRECHARGE)(8) LL HL Disabled) BURST TERMINATE(9) LH HL Write READ (Select column and start READ burst)(10) LH LH (Auto WRITE (Select column and start new WRITE burst)(10) LH LL Precharge PRECHARGE (Truncate WRITE burst, start PRECHARGE)(8) LL HL Disabled) BURST TERMINATE(9) LH HL NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after txsr has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. Integrated Silicon Solution, Inc. — www.issi.com 7 Rev.  A 03/19/08 IS42S16400F IC42S16400F 3. Current state definitions: Idle: The bank has been precharged, and trp has been met. Row Active: A row in the bank has been activated, and trcd has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and CURRENT STATE BANK n truth tables. Precharging: Starts with registration of a PRECHARGE command and ends when trp is met. Once trp is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when trcd is met. Once trcd is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when trp has been met. Once trp is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when trp has been met. Once trp is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when trc is met. Once trc is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tmrd has been met. Once tmrd is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when trp is met. Once trp is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m (1-6) CURRENT STATE COMMAND (ACTION) CS RAS CAS WE Any COMMAND INHIBIT (NOP/Continue previous operation) HX XX NO OPERATION (NOP/Continue previous operation) LH HH Idle Any Command Otherwise Allowed to Bank m XX XX Row ACTIVE (Select and activate row) L L HH Activating, READ (Select column and start READ burst)(7) LH LH Active, or WRITE (Select column and start WRITE burst)(7) LH LL Precharging PRECHARGE LL HL Read ACTIVE (Select and activate row) L L HH (Auto READ (Select column and start new READ burst)(7,10) LH LH Precharge WRITE (Select column and start WRITE burst)(7,11) LH LL Disabled) PRECHARGE(9) LL HL Write ACTIVE (Select and activate row) L L HH (Auto READ (Select column and start READ burst)(7,12) LH LH Precharge WRITE (Select column and start new WRITE burst)(7,13) LH LL Disabled) PRECHARGE(9) LL HL Read ACTIVE (Select and activate row) L L HH (With Auto READ (Select column and start new READ burst)(7,8,14) LH LH Precharge) WRITE (Select column and start WRITE burst)(7,8,15) LH LL PRECHARGE(9) LL HL Write ACTIVE (Select and activate row) L L HH (With Auto READ (Select column and start READ burst)(7,8,16) LH LH Precharge) WRITE (Select column and start new WRITE burst)(7,8,17) LH LL PRECHARGE(9) LL HL NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (Truth Table - CKE) and after txsr has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and trp has been met. Row Active: A row in the bank has been activated, and trcd has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when trp has been met. Once trp is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when trp has been met. Once trp is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. Integrated Silicon Solution, Inc. — www.issi.com 9 Rev.  A 03/19/08 IS42S16400F IC42S16400F 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted by bank m’s burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Consecutive READ Bursts). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will inter- rupt the READ on bank n when registered (READ to WRITE). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (WRITE to READ), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (WRITE to WRITE). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Fig CAP 1). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Fig CAP 2). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where twr begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Fig CAP 3). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after twr is met, where t WR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Fig CAP 4). 10 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters Rating Unit VDD max Maximum Supply Voltage –1.0 to +4.6 V VDDq max Maximum Supply Voltage for Output Buffer –1.0 to +4.6 V Vin Input Voltage –1.0 to Vddq + 0.5 V Vout Output Voltage –1.0 to Vddq + 0.5 V Pd max Allowable Power Dissipation 1 W Ics Output Shorted Current 50 mA Topr Operating Temperature Com. Ind. 0 to +70 °C -40 to +85 °C Tstg Storage Temperature –65 to +150 °C DC RECOMMENDED OPERATING CONDITIONS(2) (At Ta = 0 to +70°C) Symbol VDD, VDDq Vih Vil Parameter Supply Voltage Input High Voltage(3) Input Low Voltage(4) Min. 3.0 2.0 -0.3 Typ. Max. Unit 3.3 3.6 V — Vdd + 0.3 V — +0.8 V CAPACITANCE CHARACTERISTICS(1,2) (At Ta = 0 to +25°C, Vdd = Vddq = 3.3 ± 0.3V, f = 1 MHz) Symbol Parameter Typ. Max. Unit Cin Input Capacitance: Address and Control — 3.8 pF Cclk Input Capacitance: (CLK) — 3.5 pF CI/O Data Input/Output Capacitance: I/O0-I/O15 — 6.5 pF Notes: 1.  Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2.  All voltages are referenced to GND. 3. Vih(max) = Vddq + 2.0V with a pulse width < 3ns. 4. Vil(min) = GND - 2.0V with a pulse width < 3ns. Integrated Silicon Solution, Inc. — www.issi.com 11 Rev.  A 03/19/08 IS42S16400F IC42S16400F DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Symbol Parameter Test Condition Speed Min. Max. Unit Iil Input Leakage Current 0V ≤ Vin ≤ Vdd, with pins other than –5 5 µA the tested pin at 0V Iol Output Leakage Current Output is disabled, 0V ≤ Vout ≤ Vdd –5 5 µA Voh Output High Voltage Level Iout = –2 mA 2.4 — V Vol Output Low Voltage Level Iout = +2 mA — 0.4 V Icc1 Operating Current(1,2) One Bank Operation, CAS latency = 3 Com. -5 Burst Length=1 Com. -6 trc ≥ trc (min.) Com. -7 Iout = 0mA Ind. -5 Ind. -6 Ind. -7 Icc2p Precharge Standby Current CKE ≤ Vil (max) tck = 15ns Com. — Ind. — Icc2ps (In Power-Down Mode) tck = ∞ Com. — Ind. — — 110 mA — 95 mA — 85 mA — 180 mA — 155 mA — 145 mA — 2 mA — 4 mA — 2 mA — 3 mA Icc2n(3) Precharge Standby Current CKE ≥ Vih (min) tck = 15ns — — 20 mA Icc2ns (In Non Power-Down Mode) tck = ∞ Com. — — 15 mA Ind. — — 15 mA Icc3p Active Standby Current CKE ≤ Vil (max) tck = 10ns Com. — — 7 mA Ind. — — 7 mA Icc3ps (In Power-Down Mode) tck = ∞ Com. — — 5 mA Ind. — — 5 mA Icc3n(3) Active Standby Current CKE ≥ Vih (min) tck = 15ns — Icc3ns (In Non Power-Down Mode) tck = ∞ Com. — Ind. — Icc4 Operating Current tck = tck (min) CAS latency = 3 Com. -5 — 30 mA — 25 mA — 25 mA — 140 mA (In Burst Mode)(1) Iout = 0mA BL = 4; 4 banks activated Com. -6 Com. -7 — 130 mA — 100 mA Ind. -5 Ind. -6 Ind. -7 — 150 mA — 140 mA — 110 mA Icc5 Auto-Refresh Current trc = trc (min) CAS latency = 3Com. -5 — 160 mA tclk = tclk (min) Com. -6 Com. -7 — 150 mA — 130 mA Ind. -5 Ind. -6 Ind. -7 — 180 mA — 170 mA — 150 mA Icc6 Self-Refresh Current CKE ≤ 0.2V — ­— 2 mA Notes: 1.  These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time in- creases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vdd and GND for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents. 2.  Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state. 3. Input signal chnage once per 30ns. 12 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F AC ELECTRICAL CHARACTERISTICS (1,2,3) -6 -7 -5 Symbol Parameter tck3 Clock Cycle Time tck2 CAS Latency = 3 CAS Latency = 2 tac3 Access Time From CLK(4,6) tac2 CAS Latency = 3 CAS Latency = 2 Min. Max. 6 — 7.5 — — 5 — 6 Min. Max. 7 — 7.5 — — 5.4 — 6 Min. Max. 5 — 7.5 — — 5 — 6 Units ns ns ns ns tchi CLK HIGH Level Width 2 — 2.5 — 2 — ns tcl CLK LOW Level Width toh3 Output Data Hold Time(6) toh2 CAS Latency = 3 CAS Latency = 2 2 — 2.5 — 2 — ns 2.5 — 2.7 — 2.5 — ns 2.5 — 3 — 2.5 — ns tlz Output LOW Impedance Time thz3 Output HIGH Impedance Time(5) thz2 CAS Latency = 3 CAS Latency = 2 0 — 0 — 0 — ns — 5 — 5.4 — 5 ns — 6 — 6 — 6 ns tds Input Data Setup Time 1.5 — 1.5 — 1.5 — ns tdh Input Data Hold Time 0.8 — 0.8 — 0.8 — ns tas Address Setup Time 1.5 — 1.5 — 1.5 — ns tah Address Hold Time 0.8 — 0.8 — 0.8 — ns tcks CKE Setup Time 1.5 — 1.5 — 1.5 — ns tckh CKE Hold Time 0.8 — 0.8 — 0.8 — ns tcka CKE to CLK Recovery Delay Time 1CLK+3 — 1CLK+3 — 1CLK+3 — ns tcs Command Setup Time (CS, RAS, CAS, WE, DQM) 1.5 — 2.0 — 1.5 — ns tch Command Hold Time (CS, RAS, CAS, WE, DQM) 0.8 — 1 — 0.8 1 ns trc Command Period (REF to REF / ACT to ACT) 60 — 63 — 55 — ns tras Command Period (ACT to PRE) 42 100,000 42 100,000 42 100,000 ns trp Command Period (PRE to ACT) 18 — 20 — 15 — ns trcd Active Command To Read / Write Command Delay Time 18 — 20 — 15 — ns trrd Command Period (ACT [0] to ACT[1]) 12 — 14 — 10 — ns tdpl or Input Data To Precharge CAS Latency = 3 2CLK — 2CLK — 2CLK — ns twr Command Delay time CAS Latency = 2 2CLK — 2CLK — 2CLK — ns tdal Input Data To Active / Refresh CAS Latency = 3 2CLK+trp — 2CLK+trp — 2CLK+trp — ns Command Delay time (During Auto-Precharge) CAS Latency = 2 2CLK+trp — 2CLK+trp — 2CLK+trp — ns tt Transition Time 1 10 1 10 1 10 ns tref Refresh Cycle Time (4096) — 64 — 64 — 64 ms Notes: 1.  When power is first applied, memory operation should be started 200 µs after Vdd and Vddq reach their stipulated voltages. Also note that the power-on sequence must be executed before starting memory operation. 2.  Measured with tt = 1 ns. 3.  The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between Vih (min.) and Vil (max.). 4.  Access time is measured at 1.4V with the load shown in the figure below. 5.  The time thz (max.) is defined as the time required for the output voltage to transition by ± 200 mV from Voh (min.) or Vol (max.) when the output is in the high impedance state. 6. If clock rising time is longer than 1ns, tr/2 - 0.5ns should be added to the parameter. Integrated Silicon Solution, Inc. — www.issi.com 13 Rev.  A 03/19/08 IS42S16400F IC42S16400F OPERATING FREQUENCY / LATENCY RELATIONSHIPS Symbol Parameter -6 -7 -5 Units — Clock Cycle Time 6 7 5 ns — Operating Frequency 166 143 200 MHz tccd READ/WRITE command to READ/WRITE command 1 1 1 cycle tcked CKE to clock disable or power-down entry mode 1 1 1 cycle tped CKE to clock enable or power-down exit setup mode 1 1 1 cycle tdqd DQM to input data delay 0 0 0 cycle tdqm DQM to data mask during WRITEs 0 0 0 cycle tdqz DQM to data high-impedance during READs 2 2 2 cycle tdwd WRITE command to input data delay 0 0 0 cycle tdal Data-in to ACTIVE command 5 5 5 cycle tdpl Data-in to PRECHARGE command 2 2 2 cycle tbdl Last data-in to burst STOP command 1 1 1 cycle tcdl Last data-in to new READ/WRITE command 1 1 1 cycle trdl Last data-in to PRECHARGE command 2 2 2 cycle tmrd LOAD MODE REGISTER command to ACTIVE or REFRESH command 2 2 2 cycle troh Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 3 3 3 cycle 2 2 2 cycle Note: 1.  A minimum setup time tss + 1CLK must be satisfied. AC TEST CONDITIONS (Input/Output Reference Level: 1.4V) Input Load Output Load 2.0V CLK 1.4V 0.8V 2.0V INPUT 1.4V 0.8V OUTPUT tCK tCHI tCL tCS tCH tAC tOH 1.4V 1.4V I/O 50 Ω 50 pF +1.5V 14 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F FUNCTIONAL DESCRIPTION The 64Mb SDRAMs (1 Meg x 16 x 4 banks) are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row).The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. The 64M SDRAM is initialized after the power is applied to Vdd and Vddq (simultaneously), and the clock is stable with DQM High and CKE High. A 100µs delay is required prior to issuing any command other than a COMMAND INHIBIT or a NOP. The COMMAND INHIBIT or NOP may be applied during the 100µs period and continue should at least through the end of the period. With at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied once the 100µs delay has been satisfied. All banks must be precharged. This will leave all banks in an idle state, after which at least two AUTO REFRESH cycles must be performed.  After the AUTO REFRESH cycles are complete, the SDRAM is then ready for mode register programming. The mode register should be loaded prior to applying any operational command because it will power up in an unknown state. After the Load Mode Register command, at least two NOP commands must be asserted prior to any command. Integrated Silicon Solution, Inc. — www.issi.com 15 Rev.  A 03/19/08 IS42S16400F IC42S16400F Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4- M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation.Violating either of these requirements will result in unspecified operation. MODE REGISTER DEFINITION A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Mode Register (Mx) Reserved(1) Burst Length M2 M1 M0 000 001 010 011 100 101 110 111 M3=0 1 2 4 8 Reserved Reserved Reserved Full Page M3=1 1 2 4 8 Reserved Reserved Reserved Reserved Burst Type M3 Type 0 Sequential 1 Interleaved Latency Mode M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved Operating Mode M8 M7 00 —— M6-M0 Defined — Mode Standard Operation All Other States Reserved Write Burst Mode M9 Mode 0 Programmed Burst Length 1 Single Location Access 1. To ensure compatibility with future devices, should program M11, M10 = "0, 0" 16 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, mean- ing that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 (x16) when the burst length is set to two; by A2-A7 (x16) when the burst length is set to four; and by A3-A7 (x16) when the burst length is set to eight.The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. Burst Definition Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential Type = Interleaved A0 2 0 0-1 0-1 1 1-0 1-0 A1 A0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Full n = A0-A7 Page (y) (location 0-y) Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 4... …Cn - 1, Cn… Not Supported Integrated Silicon Solution, Inc. — www.issi.com 17 Rev.  A 03/19/08 IS42S16400F IC42S16400F CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. CAS Latency Allowable Operating Frequency (MHz) Speed CAS Latency = 2 CAS Latency = 3 5 133 200 6 ­133 166 7 133 143 CAS Latency T0 T1 T2 T3 CLK COMMAND DQ READ NOP NOP tAC DOUT tLZ tOH CAS Latency - 2 T0 T1 T2 T3 T4 CLK COMMAND READ DQ NOP NOP tAC tLZ CAS Latency - 3 NOP DOUT tOH DON'T CARE UNDEFINED 18 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the trcd specification. Minimum trcd should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a trcd specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in the following example, which covers any case where 2 < [trcd (MIN)/tck] ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by trc. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by trrd. Activating Specific Row Within Specific Bank CLK CKE HIGH - Z CS RAS CAS WE A0-A11 ROW ADDRESS BA0, BA1 BANK ADDRESS Example: Meeting trcd (MIN) when 2 < [trcd (min)/tck] ≤ 3 T0 T1 CLK COMMAND ACTIVE NOP tRCD T2 T3 T4 NOP READ or WRITE DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com 19 Rev.  A 03/19/08 IS42S16400F IC42S16400F READs READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. The CAS Latency diagram shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Consecutive READ Bursts for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Random READ Accesses, or each subsequent READ may be performed to a different bank. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. 20 READ COMMAND CLK HIGH-Z CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 A10 BA0, BA1 AUTO PRECHARGE NO PRECHARGE BANK ADDRESS The DQM input is used to avoid I/O contention, as shown in Figures RW1 and RW2. The DQM signal must be asserted (HIGH) at least three clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure RW2, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank.The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to PRECHARGE Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F diagram for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until trp is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated.The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ Burst Termination diagram for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. CAS Latency T0 T1 T2 T3 CLK COMMAND DQ READ NOP NOP tAC DOUT tLZ tOH CAS Latency - 2 T0 T1 T2 T3 T4 CLK COMMAND READ DQ NOP NOP tAC tLZ CAS Latency - 3 NOP DOUT tOH DON'T CARE UNDEFINED Integrated Silicon Solution, Inc. — www.issi.com 21 Rev.  A 03/19/08 IS42S16400F IC42S16400F Consecutive READ Bursts T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP READ NOP x=1 cycle BANK, COL b NOP DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b CAS Latency - 2 DON'T CARE T0 T1 T2 CLK COMMAND READ NOP NOP ADDRESS BANK, COL n DQ CAS Latency - 3 T3 T4 T5 T6 T7 NOP READ NOP x = 2 cycles BANK, COL b NOP NOP DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DOUT b DON'T CARE 22 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F Random READ Accesses T0 T1 T2 T3 T4 T5 CLK COMMAND READ READ READ READ NOP NOP ADDRESS BANK, COL n BANK, COL b BANK, COL m BANK, COL x DQ DOUT n DOUT b DOUT m DOUT x CAS Latency - 2 DON'T CARE T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ READ READ READ NOP NOP NOP ADDRESS BANK, COL n BANK, COL b BANK, COL m DQ CAS Latency - 3 BANK, COL x DOUT n DOUT b DOUT m DOUT x DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com 23 Rev.  A 03/19/08 IS42S16400F IC42S16400F RW1 - READ to WRITE T0 T1 T2 T3 T4 T5 T6 CLK DQM COMMAND READ NOP NOP NOP NOP NOP WRITE ADDRESS DQ BANK, COL n CAS Latency - 2 DOUT n tHZ DOUT n+1 BANK, COL b DOUT n+2 DIN b tDS DON'T CARE RW2 - READ to WRITE T0 T1 T2 T3 T4 T5 CLK DQM COMMAND READ NOP NOP ADDRESS BANK, COL n DQ CAS Latency - 3 NOP NOP WRITE tHZ DOUT n BANK, COL b DIN b tDS DON'T CARE 24 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F READ to PRECHARGE T0 T1 CLK COMMAND READ NOP ADDRESS BANK a, COL n T2 NOP T3 T4 T5 T6 NOP tRP PRECHARGE NOP x = 1 cycle BANK (a or all) NOP T7 ACTIVE BANK a, ROW DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 CAS Latency - 2 DON'T CARE T0 T1 T2 CLK COMMAND READ NOP NOP ADDRESS BANK, COL n DQ CAS Latency - 3 T3 NOP T4 T5 T6 tRP PRECHARGE NOP x = 2 cycles BANK, COL b NOP T7 ACTIVE BANK a, ROW DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com 25 Rev.  A 03/19/08 IS42S16400F IC42S16400F READ Burst Termination T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK a, COL n NOP NOP NOP BURST TERMINATE NOP x = 1 cycle NOP DQ DOUT n DOUT n+1 DOUT n+2 DOUT n+3 CAS Latency - 2 DON'T CARE T0 T1 T2 CLK COMMAND READ NOP NOP ADDRESS BANK, COL n DQ CAS Latency - 3 T3 T4 T5 T6 T7 NOP BURST TERMINATE NOP x = 2 cycles NOP NOP DOUT n DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE 26 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F WRITEs WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE Command CLK CKE HIGH - Z CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 A10 BA0, BA1 AUTO PRECHARGE NO PRECHARGE BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see WRITE Burst). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 An example is shown in WRITE to WRITE diagram. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command.Full-speed random write accesses within a page can be performed to the same bank, as shown in Random WRITE Cycles, or each subsequent WRITE may be performed to a different bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a subsequent READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in WRITE to READ. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued twr after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a twr of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in the WRITE to PRECHARGE diagram. Data n+1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until trp is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge.The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in WRITE Burst Termination, where data n is the last desired data element of a longer burst. 27 IS42S16400F IC42S16400F WRITE Burst T0 T1 CLK COMMAND WRITE NOP ADDRESS BANK, COL n DQ DIN n DIN n+1 T2 T3 NOP NOP DON'T CARE WRITE to WRITE T0 T1 T2 CLK COMMAND WRITE NOP WRITE ADDRESS BANK, COL n DQ DIN n BANK, COL b DIN n+1 DIN b DON'T CARE Random WRITE Cycles T0 T1 T2 T3 CLK COMMAND WRITE WRITE WRITE WRITE ADDRESS BANK, COL n DQ DIN n BANK, COL b DIN b BANK, COL m DIN m BANK, COL x DIN x 28 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F WRITE to READ T0 T1 T2 T3 T4 T5 CLK COMMAND WRITE NOP READ NOP NOP NOP ADDRESS BANK, COL n DQ DIN n DIN n+1 BANK, COL b DOUT b CAS Latency - 2 DOUT b+1 DON'T CARE WP1 - WRITE to PRECHARGE T0 T1 T2 T3 T4 T5 T6 CLK DQM COMMAND WRITE NOP PRECHARGE tRP NOP ACTIVE NOP NOP ADDRESS DQ BANK a, COL n DIN n tWR DIN n+1 BANK (a or all) BANK a, ROW CAS Latency - 2 DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com 29 Rev.  A 03/19/08 IS42S16400F IC42S16400F WP2 - WRITE to PRECHARGE T0 T1 T2 T3 T4 T5 T6 CLK DQM COMMAND WRITE NOP PRECHARGE tRP NOP NOP ACTIVE NOP ADDRESS DQ BANK a, COL n DIN n tWR DIN n+1 BANK (a or all) CAS Latency - 3 BANK a, ROW DON'T CARE WRITE Burst Termination T0 T1 T2 CLK COMMAND WRITE BURST TERMINATE NEXT COMMAND ADDRESS BANK, COL n (ADDRESS) DQ DIN n (DATA) DON'T CARE 30 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F PRECHARGE The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in all banks.The bank(s) will be available for a subsequent row access some specified time (trp) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tcks). See figure below. PRECHARGE Command CLK HIGH - Z CKE CS RAS CAS WE A0-A9, A11 A10 BA0, BA1 ALL BANKS BANK SELECT BANK ADDRESS POWER-DOWN CLK tCKS CKE ≥ tCKS COMMAND NOP All banks idle Input buffers gated off NOP Enter power-down mode Exit power-down mode ACTIVE tRCD tRAS tRC DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com 31 Rev.  A 03/19/08 IS42S16400F IC42S16400F CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See following examples.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Clock Suspend During WRITE Burst T0 T1 T2 CLK CKE INTERNAL CLOCK COMMAND NOP ADDRESS DQ WRITE BANK a, COL n DIN n T3 T4 T5 NOP NOP DIN n+1 DIN n+2 DON'T CARE Clock Suspend During READ Burst T0 T1 T2 T3 T4 T5 T6 CLK CKE INTERNAL CLOCK COMMAND READ ADDRESS BANK a, COL n DQ NOP NOP DOUT n NOP NOP NOP DOUT n+1 DOUT n+2 DOUT n+3 DON'T CARE 32 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered. 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered. Fig CAP 1 - READ With Auto Precharge interrupted by a READ CLK COMMAND T0 NOP T1 READ - AP BANK n T2 NOP T3 READ - AP BANK m T4 NOP T5 NOP T6 NOP T7 NOP BANK n Page Active READ with Burst of 4 Internal States BANK m Page Active Interrupt Burst, Precharge tRP - BANK n READ with Burst of 4 Idle tRP - BANK m Precharge ADDRESS DQ BANK n, COL a BANK m, COL b DOUT a DOUT a+1 CAS Latency - 3 (BANK n) CAS Latency - 3 (BANK m) DOUT b DOUT b+1 DON'T CARE Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE T0 T1 T2 T3 T4 T5 CLK COMMAND WRITE - AP BANK n NOP NOP NOP WRITE - AP BANK m NOP T6 NOP T7 NOP BANK n READ with Burst of 4 Internal States Page Active BANK m Page Active Interrupt Burst, Precharge tRP - BANK n WRITE with Burst of 4 Idle tRP - BANK m Write-Back ADDRESS DQM BANK n, COL a BANK m, COL b DQ DOUT a DIN b DIN b+1 DIN b+2 DIN b+3 CAS Latency - 3 (BANK n) DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com 33 Rev.  A 03/19/08 IS42S16400F IC42S16400F WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after twr is met, where twr begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 4. Interrupted by a WRITE (with or without auto precharge): AWRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after twr is met, where twr begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m. Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND NOP WRITE - AP BANK n NOP READ - AP BANK m NOP NOP NOP NOP BANK n Page Active WRITE with Burst of 4 Internal States BANK m Page Active Interrupt Burst, Write-Back tWR - BANK n READ with Burst of 4 Precharge tRP - BANK n tRP - BANK m Precharge ADDRESS BANK n, COL a BANK m, COL b DQ DIN a DIN a+1 DOUT b DOUT b+1 CAS Latency - 3 (BANK m) DON'T CARE Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND NOP WRITE - AP BANK n NOP NOP WRITE - AP BANK m NOP NOP NOP BANK n Page Active Internal States BANK m WRITE with Burst of 4 Page Active Interrupt Burst, Write-Back tWR - BANK n WRITE with Burst of 4 Precharge tRP - BANK n tRP - BANK m Write-Back ADDRESS BANK n, COL a BANK m, COL b DQ DIN a DIN a+1 DIN a+2 DIN b DIN b+1 DIN b+2 DIN b+3 DON'T CARE 34 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F Initialize and Load Mode Register(1) CLK T0 tCK tCKS tCKH CKE tCMH tCMS COMMAND NOP T1 tCMH tCMS PRECHARGE Tn+1 tCH tCMH tCMS AUTO REFRESH DQM/ DQML, DQMH To+1 tCL NOP AUTO REFRESH A0-A9, A11 A10 BA0, BA1 ALL BANKS SINGLE BANK ALL BANKS Tp+1 Tp+2 Tp+3 NOP Load MODE REGISTER NOP ACTIVE tAS tAH CODE tAS tAH CODE ROW ROW BANK DQ T Power-up: VCC and CLK stable T = 100µs Min. tRP tRC tRC Precharge AUTO REFRESH AUTO REFRESH all banks At least 2 Auto-Refresh Commands tMRD Program MODE REGISTER(2, 3, 4) DON'T CARE Notes: 1. If CS is High at clock High time, all commands applied are NOP. 2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired. 3. JEDEC and PC100 specify three clocks. 4. Outputs are guaranteed High-Z after the command is issued. Integrated Silicon Solution, Inc. — www.issi.com 35 Rev.  A 03/19/08 IS42S16400F IC42S16400F Power-Down Mode Cycle T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND PRECHARGE T1 tCK NOP T2 tCL tCH tCKS NOP DQM/ DQML, DQMH Tn+1 Tn+2 tCKS NOP ACTIVE A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK DQ High-Z Two clock cycles Precharge all active banks All banks idle, enter power-down mode ROW ROW BANK Input buffers gated off while in power-down mode All banks idle Exit power-down mode DON'T CARE CAS latency = 2, 3 36 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F Clock Suspend Mode T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK tCK tCL tCH tCKS tCKH tCKS tCKH CKE tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 READ tAS tAH COLUMN m(2) tAS tAH tAS tAH BANK NOP tCMS tCMH DQ NOP tAC tLZ NOP NOP NOP WRITE DOUT m tAC tOH tHZ DOUT m+1 COLUMN n(2) BANK tDS tDH DOUT e Notes: 1. CAS latency = 3, burst length = 2 2. A8, A9, and A11 = "Don't Care" T9 NOP DOUT e+1 DON'T CARE UNDEFINED Integrated Silicon Solution, Inc. — www.issi.com 37 Rev.  A 03/19/08 IS42S16400F IC42S16400F Auto-Refresh Cycle T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND PRECHARGE T1 tCK NOP DQM/ DQML, DQMH T2 tCL tCH Auto Refresh A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(s) tAS tAH DQ High-Z tRP NOP tRC CAS latency = 2, 3 Tn+1 Auto Refresh To+1 NOP ACTIVE ROW ROW BANK tRC DON'T CARE 38 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F Self-Refresh Cycle CLK T0 tCK tCKS tCKH CKE tCMS tCMH COMMAND PRECHARGE DQM/ DQML, DQMH T1 tCH T2 tCL tCKS NOP Auto Refresh ≥ tRAS Tn+1 To+1 To+2 NOP tCKS NOP Auto Refresh A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS tAH BA0, BA1 BANK DQ High-Z Precharge all active banks tRP Enter self refresh mode tXSR CLK stable prior to exiting Exit self refresh mode self refresh mode (Restart refresh time base) CAS latency = 2, 3 DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com 39 Rev.  A 03/19/08 IS42S16400F IC42S16400F READ WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK DQ T1 T2 T3 tCK tCL tCH NOP READ tCMS tCMH NOP COLUMN m(2) DISABLE AUTO PRECHARGE BANK tAC tRCD tRAS tRC tLZ CAS Latency T4 NOP tAC DOUT m tOH T5 T6 NOP PRECHARGE ALL BANKS SINGLE BANK BANK tAC DOUT m+1 tOH tAC DOUT m+2 tOH T7 T8 NOP ACTIVE ROW ROW tHZ DOUT m+3 tOH tRP BANK DON'T CARE UNDEFINED Notes: 1. CAS latency = 2, burst length = 4 2. A8, A9, and A11 = "Don't Care" 40 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F READ WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK DQ T1 T2 T3 tCK tCL tCH NOP READ tCMS tCMH NOP COLUMN m(2) ENABLE AUTO PRECHARGE tRCD tRAS tRC BANK tAC tLZ CAS Latency T4 NOP tAC DOUT m tOH T5 NOP tAC DOUT m+1 tOH T6 NOP tAC DOUT m+2 tOH T7 T8 NOP ACTIVE ROW ROW tHZ DOUT m+3 tOH tRP BANK DON'T CARE UNDEFINED Notes: 1. CAS latency = 2, burst length = 4 2. A8, A9, and A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com 41 Rev.  A 03/19/08 IS42S16400F IC42S16400F SINGLE READ WITHOUT AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK DQ T1 T2 T3 tCK tCL tCH NOP READ tCMS tCMH NOP COLUMN m(2) DISABLE AUTO PRECHARGE BANK tAC tRCD tRAS tRC tLZ CAS Latency T4 T5 NOP PRECHARGE ALL BANKS SINGLE BANK BANK tOH DOUT m tHZ T6 NOP tRP T7 ACTIVE ROW ROW BANK T8 NOP DON'T CARE UNDEFINED Notes: 1. CAS latency = 2, burst length = 1 2. A8, A9, and A11 = "Don't Care" 42 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F SINGLE READ WITH AUTO PRECHARGE T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE T1 tCK NOP T2 tCL tCH NOP DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK DQ tRCD tRAS tRC T3 T4 T5 T6 T7 NOP READ tCMS tCMH NOP NOP ACTIVE COLUMN m(2) ENABLE AUTO PRECHARGE ROW ROW BANK tAC CAS Latency tOH DOUT m tHZ tRP BANK T8 NOP DON'T CARE UNDEFINED Notes: 1. CAS latency = 2, burst length = 1 2. A8, A9, and A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com 43 Rev.  A 03/19/08 IS42S16400F IC42S16400F ALTERNATING BANK READ ACCESSES T0 CLK T1 tCK T2 T3 tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 NOP READ tCMS tCMH NOP COLUMN m(2) ENABLE AUTO PRECHARGE BANK 0 T4 ACTIVE ROW ROW BANK 3 T5 T6 T7 NOP READ NOP COLUMN b(2) ENABLE AUTO PRECHARGE BANK 3 T8 ACTIVE ROW ROW BANK 0 tLZ tOH tOH tOH tOH tOH DQ DOUT m DOUT m+1 DOUT m+2 DOUT m+3 DOUT b tAC tAC tAC tAC tAC tAC tRCD - BANK 0 CAS Latency - BANK 0 tRP - BANK 0 tRCD - BANK 0 tRRD tRCD - BANK 3 CAS Latency - BANK 3 tRAS - BANK 0 tRC - BANK 0 DON'T CARE Notes: 1. CAS latency = 2, burst length = 4 2. A8, A9, and A11 = "Don't Care" 44 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F READ - FULL-PAGE BURST T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE T1 tCK NOP DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK DQ tRCD T2 T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4 tCL tCH READ NOP NOP NOP NOP NOP BURST TERM NOP NOP tCMS tCMH COLUMN m(2) BANK tAC tLZ CAS Latency tAC tAC tAC tAC tAC DOUT m DOUT m+1 DOUT m+2 DOUT m-1 DOUT m tOH tOH tOH tOH tOH each row (x4) has 1,024 locations Full page Full-page burst not self-terminating. completion Use BURST TERMINATE command. tHZ DOUT m+1 tOH DON'T CARE UNDEFINED Notes: 1. CAS latency = 2, burst length = full page 2. A8, A9, and A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com 45 Rev.  A 03/19/08 IS42S16400F IC42S16400F READ - DQM OPERATION T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK DQ T1 tCK T2 T3 tCL tCH NOP READ tCMS tCMH NOP COLUMN m(2) ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK tAC tLZ tRCD CAS Latency T4 T5 NOP NOP tOH DOUT m tHZ tAC tLZ T6 T7 T8 NOP NOP NOP tOH DOUT m+2 tAC tOH DOUT m+3 tHZ DON'T CARE UNDEFINED Notes: 1. CAS latency = 2, burst length = 4 2. A8, A9, and A11 = "Don't Care" 46 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F WRITE - WITHOUT AUTO PRECHARGE T0 CLK T1 T2 T3 tCK tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK NOP WRITE tCMS tCMH NOP COLUMN m(2) DISABLE AUTO PRECHARGE BANK tDS tDH tDS tDH DQ tRCD tRAS tRC DIN m DIN m+1 T4 T5 T6 T7 NOP NOP PRECHARGE NOP ALL BANKS SINGLE BANK tDS tDH tDS tDH BANK DIN m+2 DIN m+3 tWR(3) tRP T8 ACTIVE ROW ROW BANK DON'T CARE Notes: 1. burst length = 4 2. A8, A9, and A11 = "Don't Care" 3. tras must not be violated Integrated Silicon Solution, Inc. — www.issi.com 47 Rev.  A 03/19/08 IS42S16400F IC42S16400F WRITE - WITH AUTO PRECHARGE T0 CLK T1 T2 T3 tCK tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK NOP WRITE tCMS tCMH NOP COLUMN m(2) ENABLE AUTO PRECHARGE BANK tDS tDH tDS tDH DQ tRCD tRAS tRC DIN m DIN m+1 T4 T5 NOP NOP tDS tDH tDS tDH DIN m+2 DIN m+3 T6 NOP tWR T7 T8 T9 NOP NOP ACTIVE ROW ROW BANK tRP DON'T CARE Notes: 1. burst length = 4 2. A8, A9, and A11 = "Don't Care" 48 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F SINGLE WRITE - WITHOUT AUTO PRECHARGE T0 T1 T2 T3 T4 CLK tCK tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK NOP WRITE tCMS tCMH NOP(4) COLUMN m(2) DISABLE AUTO PRECHARGE BANK tDS tDH NOP(4) DQ tRCD tRAS tRC DIN m tWR(3) T5 T6 PRECHARGE NOP ROW ALL BANKS SINGLE BANK BANK tRP T7 T8 ACTIVE NOP ROW BANK DON'T CARE Notes: 1. burst length = 1 2. A8, A9, and A11 = "Don't Care" 3. tras must not be violated Integrated Silicon Solution, Inc. — www.issi.com 49 Rev.  A 03/19/08 IS42S16400F IC42S16400F SINGLE WRITE - WITH AUTO PRECHARGE T0 CLK T1 tCK T2 tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE NOP(3) NOP(3) DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK DQ tRCD tRAS tRC T3 T4 T5 NOP(3) WRITE tCMS tCMH NOP COLUMN m(2) ENABLE AUTO PRECHARGE BANK tDS tDH DIN m tWR T6 T7 T8 T9 NOP NOP ACTIVE NOP ROW ROW BANK tRP DON'T CARE Notes: 1. burst length = 1 2. A8, A9, and A11 = "Don't Care" 50 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F ALTERNATING BANK WRITE ACCESS T0 CLK T1 tCK T2 T3 tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK 0 NOP WRITE tCMS tCMH NOP COLUMN m(2) ENABLE AUTO PRECHARGE BANK 0 tDS tDH tDS tDH DQ DIN m DIN m+1 tRCD - BANK 0 tRRD tRAS - BANK 0 tRC - BANK 0 T4 T5 T6 T7 T8 ACTIVE NOP WRITE NOP NOP ROW ROW COLUMN b(2) ENABLE AUTO PRECHARGE BANK 1 tDS tDH tDS tDH BANK 1 tDS tDH DIN m+2 DIN m+3 DIN b tWR - BANK 0 tRCD - BANK 1 tDS tDH tDS tDH DIN b+1 DIN b+2 tRP - BANK 0 T9 ACTIVE ROW ROW BANK 0 tDS tDH DIN b+3 tRCD - BANK 0 tWR - BANK 1 DON'T CARE Notes: 1. burst length = 4 2. A8, A9, and A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com 51 Rev.  A 03/19/08 IS42S16400F IC42S16400F write - full page burst T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE T1 tCK NOP DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK DQ tRCD T2 T3 T4 T5 Tn+1 Tn+2 tCL tCH WRITE tCMS tCMH NOP NOP NOP NOP BURST TERM NOP COLUMN m(2) BANK tDS tDH DIN m tDS tDH DIN m+1 tDS tDH DIN m+2 tDS tDH DIN m+3 tDS tDH DIN m-1 Full page completed tDS tDH DON'T CARE Notes: 1. burst length = full page 2. A8, A9, and A11 = "Don't Care" 52 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 IS42S16400F IC42S16400F WRITE - DQM OPERATION T0 CLK tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11 A10 BA0, BA1 tAS tAH ROW tAS tAH ROW tAS tAH BANK DQ T1 T2 T3 tCK tCL tCH NOP WRITE tCMS tCMH NOP COLUMN m(2) ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK tDS tDH DIN m tRCD T4 T5 T6 T7 NOP NOP NOP NOP tDS tDH DIN m+2 tDS tDH DIN m+3 DON'T CARE Notes: 1. burst length = 4 2. A8, A9, and A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com 53 Rev.  A 03/19/08 IS42S16400F IC42S16400F ORDERING INFORMATION Commercial Range: 0°C to 70°C Frequency Speed (ns) Order Part No. 200 MHz 5 200 MHz 5 IS42S16400F-5TL IC42S16400F-5TL 166 MHz 6 166 MHz 6 IS42S16400F-6TL IC42S16400F-6TL 143 MHz 7 143 MHz 7 IS42S16400F-7TL IC42S16400F-7TL Industrial Range: -40°C to 85°C Frequency Speed (ns) Order Part No. 200 MHz 5 IS42S16400F-5TLI 166 MHz 6 IS42S16400F-6TLI 143 MHz 7 IS42S16400F-7TLI Package 400-mil TSOP II, Lead-free 400-mil TSOP II, Lead-free 400-mil TSOP II, Lead-free 400-mil TSOP II, Lead-free 400-mil TSOP II, Lead-free 400-mil TSOP II, Lead-free Package 400-mil TSOP II, Lead-free 400-mil TSOP II, Lead-free 400-mil TSOP II, Lead-free 54 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 03/19/08 PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II) N 1 D ZD e N/2+1 E1 E N/2 Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. SEATING PLANE A b A1 L α C Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 54 A — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 A2 — — —— b 0.30 0.45 0.012 0.018 C 0.12 0.21 0.005 0.0083 D 22.02 22.42 0.867 0.8827 E1 10.03 10.29 0.395 0.405 E 11.56 11.96 0.455 0.471 e 0.80 BSC 0.031 BSC L 0.40 0.60 0.016 0.024 L1 — — —— ZD 0.71 REF α 0° 8° 0° 8° Integrated Silicon Solution, Inc. Rev. D 03/13/07 Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 86 A — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 C 0.12 0.21 0.005 0.008 D 22.02 22.42 0.867 0.8827 E1 10.03 10.29 0.395 0.405 E 11.56 11.96 0.455 0.471 e 0.50 BSC 0.020 BSC L 0.40 0.60 0.016 0.024 L1 0.80 REF 0.031 REF ZD 0.61 REF 0.024 BSC α 0° 8° 0° 8° 1

Top_arrow
回到顶部
EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。