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430F449芯片手册

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MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption: – Active Mode: 280 µA at 1 MHz, 2.2 V – Standby Mode: 1.1 µA – Off Mode (RAM Retention): 0.1 µA D Five Power Saving Modes D Wake-Up From Standby Mode in 6 µs D 16-Bit RISC Architecture, 125-ns Instruction Cycle Time D 12-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature D 16-Bit Timer_B With Three† or Seven‡ Capture/Compare-With-Shadow Registers D 16-Bit Timer_A With Three Capture/Compare Registers D On-Chip Comparator D Serial Communication Interface (USART), Select Asynchronous UART or Synchronous SPI by Software: – Two USARTs (USART0, USART1) — MSP430x44x Devices – One USART (USART0) — MSP430x43x Devices D Brownout Detector D Supply Voltage Supervisor/Monitor With Programmable Level Detection SLAS344C – JANUARY 2002 – REVISED MARCH2003 D Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse D Integrated LCD Driver for Up to 160 Segments D Family Members Include: – MSP430F435: 16KB+256B Flash Memory, 512B RAM – MSP430F436: 24KB+256B Flash Memory, 1KB RAM – MSP430F437: 32KB+256B Flash Memory, 1KB RAM – MSP430F447: 32KB+256B Flash Memory, 1KB RAM – MSP430F448: 48KB+256B Flash Memory, 2KB RAM – MSP430F449: 60KB+256B Flash Memory, 2KB RAM D For Complete Module Descriptions, See The MSP430x4xx Family User’s Guide, Literature Number SLAU056 † ’F435, ’F436, and ’F437 devices ‡ ’F447, ’F448, and ’F449 devices description The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs. The MSP430x43x and the MSP430x44x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and a liquid crystal driver (LCD) with up to 160 segments. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process and transmit the data to a host system, or process this data and displays it on a LCD panel. The timers make the configurations ideal for industrial control applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code and hardware-compatible family solution. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002 – 2003, Texas Instruments Incorporated • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 80-PIN QFP PLASTIC 100-PIN QFP (PN) (PZ) –40°C to 85°C MSP430F435IPN MSP430F436IPN MSP430F437IPN MSP430F435IPZ MSP430F436IPZ MSP430F437IPZ MSP430F447IPZ MSP430F448IPZ MSP430F449IPZ pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN PN PACKAGE (TOP VIEW) AVCC DVSS1 AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.6/CA0 DVCC1 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSin VREF+ XIN XOUT/TCLK VeREF+ VREF–/VeREF– P5.1/S0 P5.0/S1 P4.7/S2 P4.6/S3 P4.5/S4 P4.4/S5 P4.3/S6 P4.2/S7 P4.1/S8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 MSP430F435IPN 52 10 MSP430F436IPN 51 11 MSP430F437IPN 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P1.7CA1 P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.3/TB2 P2.4/UTXD0 P2.5/URXD0 DVSS2 DVCC2 P5.7/R33 P5.6/R23 P5.5/R13 R03 P5.4/COM3 P5.3/COM2 P5.2/COM1 COM0 P3.0/STE0/S31 P3.1/SIMO0/S30 P3.2/SOMI0/S29 P4.0/S9 S10 S11 S12 S13 S14 S15 S16 S17 P2.7/ADC12CLK/S18 P2.6/CAOUT/S19 S20 S21 S22 S23 P3.7/S24 P3.6/S25 P3.5/S26 P3.4/S27 P3.3/UCLK0/S28 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ PZ PACKAGE (TOP VIEW) 100 AVCC 99 DVSS1 98 AVSS 97 P6.2/A2 96 P6.1/A1 95 P6.0/A0 94 RST/NMI 93 TCK 92 TMS 91 TDI 90 TDO/TDI 89 XT2IN 88 XT2OUT 87 P1.0/TA0 86 P1.1/TA0/MCLK 85 P1.2/TA1 84 P1.3/TBOUTH/SVSOUT 83 P1.4/TBCLK/SMCLK 82 P1.5/TACLK/ACLK 81 P1.6/CA0 80 P1.7/CA1 79 P2.0/TA2 78 P2.1/TB0 77 P2.2/TB1 76 P2.3/TB2 DVCC1 1 P6.3/A3 2 P6.4/A4 3 P6.5/A5 4 P6.6/A6 5 P6.7/A7/SVSin 6 VREF+ 7 XIN 8 XOUT/TCLK 9 VeREF+ 10 VREF–/VeREF– 11 P5.1/S0 12 P5.0/S1 13 S2 14 S3 15 S4 16 S5 17 S6 18 S7 19 S8 20 S9 21 S10 22 S11 23 S12 24 S13 25 MSP430F435IPZ MSP430F436IPZ MSP430F437IPZ 75 P2.4/UTXD0 74 P2.5/URXD0 73 P2.6/CAOUT 72 P2.7/ADC12CLK 71 P3.0/STE0 70 P3.1/SIMO0 69 P3.2/SOMI0 68 P3.3/UCLK0 67 P3.4 66 P3.5 65 P3.6 64 P3.7 63 P4.0 62 P4.1 61 DVSS2 60 DVCC2 59 P5.7/R33 58 P5.6/R23 57 P5.5/R13 56 R03 55 P5.4/COM3 54 P5.3/COM2 53 P5.2/COM1 52 COM0 51 P4.2/S39 S14 26 S15 27 S16 28 S17 29 S18 30 S19 31 S20 32 S21 33 S22 34 S23 35 S24 36 S25 37 S26 38 S27 39 S28 40 S29 41 S30 42 S31 43 S32 44 S33 45 P4.7/S34 46 P4.6/S35 47 P4.5/S36 48 P4.4/S37 49 P4.3/S38 50 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ PZ PACKAGE (TOP VIEW) 100 AVCC 99 DVSS1 98 AVSS 97 P6.2/A2 96 P6.1/A1 95 P6.0/A0 94 RST/NMI 93 TCK 92 TMS 91 TDI 90 TDO/TDI 89 XT2IN 88 XT2OUT 87 P1.0/TA0 86 P1.1/TA0/MCLK 85 P1.2/TA1 84 P1.3/TBOUTH/SVSOUT 83 P1.4/TBCLK/SMCLK 82 P1.5/TACLK/ACLK 81 P1.6/CA0 80 P1.7/CA1 79 P2.0/TA2 78 P2.1/TB0 77 P2.2/TB1 76 P2.3/TB2 DVCC1 1 P6.3/A3 2 P6.4/A4 3 P6.5/A5 4 P6.6/A6 5 P6.7/A7/SVSin 6 VREF+ 7 XIN 8 XOUT/TCLK 9 VeREF+ 10 VREF–/VeREF– 11 P5.1/S0 12 P5.0/S1 13 S2 14 S3 15 S4 16 S5 17 S6 18 S7 19 S8 20 S9 21 S10 22 S11 23 S12 24 S13 25 MSP430F447IPZ MSP430F448IPZ MSP430F449IPZ 75 P2.4/UTXD0 74 P2.5/URXD0 73 P2.6/CAOUT 72 P2.7/ADC12CLK 71 P3.0/STE0 70 P3.1/SIMO0 69 P3.2/SOMI0 68 P3.3/UCLK0 67 P3.4/TB3 66 P3.5/TB4 65 P3.6/TB5 64 P3.7/TB6 63 P4.0/UTXD1 62 P4.1/URXD1 61 DVSS2 60 DVCC2 59 P5.7/R33 58 P5.6/R23 57 P5.5/R13 56 R03 55 P5.4/COM3 54 P5.3/COM2 53 P5.2/COM1 52 COM0 51 P4.2/STE1/S39 S14 26 S15 27 S16 28 S17 29 S18 30 S19 31 S20 32 S21 33 S22 34 S23 35 S24 36 S25 37 S26 38 S27 39 S28 40 S29 41 S30 42 S31 43 S32 44 S33 45 P4.7/S34 46 P4.6/S35 47 P4.5/UCLK1/S36 48 P4.4/SOMI1/S37 49 4.3/SIMO1/S38 50 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x functional block diagrams XIN XOUT/TCLK DVCC DVSS AVCC AVSS RST/NMI MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 P5 P6 P3 P4 P1 P2 XT2IN XT2OUT Oscillator FLL+ ACLK SMCLK 16 kB Flash 24 kB Flash 32 kB Flash 512 B RAM 1 kB RAM 1 kB RAM 12 Bit ADC 8 Channels <10 µs Conv. I/O Port 5/6 I/O Port 3/4 16 I/Os MCLK CPU Incl. 16 Reg. Test MAB, 16 Bit JTAG MCB MAB, 4 Bit I/O Port 1/2 16 I/Os, With Interrupt Capability USART0 UART or SPI Function Emulation Module 4 TMS TCK TDI TDO/TDI MDB, 16 Bit Bus Conv Watchdog Timer 15 / 16 Bit Timer_B3 Timer_A3 3 CC–Reg 3 CC-Reg. Shadow Reg. MSP430x44x functional block diagrams XIN XOUT/TCLK DVCC DVSS AVCC AVSS RST/NMI MDB, 8 Bit POR SVS Brownout Comparator A Basic Timer1 1 Interrupt Vector LCD 160 Segments 1,2,3,4 MUX fLCD P5 P6 P3 P4 P1 P2 XT2IN XT2OUT TMS TCK TDI TDO/TDI Oscillator FLL+ ACLK SMCLK 32 kB Flash 48 kB Flash 60 kB Flash 1 kB RAM 12 Bit ADC 2 kB RAM 8 Channels 2 kB RAM <10 µs Conv. I/O Port 5/6 I/O Port 3/4 16 I/Os MCLK CPU Incl. 16 Reg. Test MAB, 16 Bit JTAG MCB MAB, 4 Bit I/O Port 1/2 16 I/Os, With Interrupt Capability USART0 USART1 UART or SPI Function Emulation Module 4 Multiply MPY, MPYS MAC,MACS 8×8 Bit 8×16 Bit 16×8 Bit 16×16 Bit MDB, 16 Bit Bus Conv MDB, 8 Bit Watchdog Timer 15 / 16 Bit Timer_B7 Timer_A3 7 CC-Reg. 3 CC-Reg. Shadow Reg. POR SVS Brownout Comparator A Basic Timer1 1 Interrupt Vector LCD 160 Segments 1,2,3,4 MUX fLCD • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 MSP430x43x Terminal Functions PN NAME DVCC1 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSin TERMINAL I/O NO. PZ NAME 1 DVCC1 2 I/O P6.3/A3 3 I/O P6.4/A4 4 I/O P6.5/A5 5 I/O P6.6/A6 6 I/O P6.7/A7/SVSin VREF+ 7 XIN 8 XOUT/TCLK 9 VeREF+ 10 VREF–/VeREF– 11 P5.1/S0 12 P5.0/S1 13 P4.7/S2 14 P4.6/S3 15 P4.5/S4 16 P4.4/S5 17 P4.3/S6 18 P4.2/S7 19 P4.1/S8 20 P4.0/S9 21 S10 22 S11 23 S12 24 S13 25 S14 26 S15 27 S16 28 S17 29 P2.7/ADC12CLK/ 30 S18 P2.6/CAOUT/S19 31 S20 32 S21 33 S22 34 S23 35 P3.7/S24 36 P3.6/S25 37 P3.5/S26 38 P3.4/S27 39 O VREF+ I XIN I/O XOUT/TCLK I VeREF+ I VREF–/VeREF– I/O P5.1/S0 I/O P5.0/S1 I/O S2 I/O S3 I/O S4 I/O S5 I/O S6 I/O S7 I/O S8 I/O S9 O S10 O S11 O S12 O S13 O S14 O S15 O S16 O S17 I/O S18 I/O S19 O S20 O S21 O S22 O S23 I/O S24 I/O S25 I/O S26 I/O S27 I/O NO. DESCRIPTION 1 Digital supply voltage, positive terminal. Supplies all digital parts 2 I/O General-purpose digital I/O, analog input a3—12-bit ADC 3 I/O General-purpose digital I/O, analog input a4—12-bit ADC 4 I/O General-purpose digital I/O, analog input a5—12-bit ADC 5 I/O General-purpose digital I/O, analog input a6—12-bit ADC 6 I/O General-purpose digital I/O, analog input a7—12-bit ADC, analog input to brownout, supply voltage supervisor 7 O Output of positive terminal of the reference voltage in the ADC Input port for crystal oscillator XT1. Standard or watch crystals can be 8 I connected. 9 I/O Output terminal of crystal oscillator XT1 or test clock input 10 I Input for an external reference voltage to the ADC 11 I Negative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage. 12 I/O General-purpose I/O / LCD segment output 0 13 I/O General-purpose I/O / LCD segment output 1 14 O General-purpose I/O / LCD segment output 2 15 O General-purpose I/O / LCD segment output 3 16 O General-purpose I/O / LCD segment output 4 17 O General-purpose I/O / LCD segment output 5 18 O General-purpose I/O / LCD segment output 6 19 O General-purpose I/O / LCD segment output 7 20 O General-purpose I/O / LCD segment output 8 21 O General-purpose I/O / LCD segment output 9 22 O LCD segment output 10 23 O LCD segment output 11 24 O LCD segment output 12 25 O LCD segment output 13 26 O LCD segment output 14 27 O LCD segment output 15 28 O LCD segment output 16 29 O LCD segment output 17 30 O General-purpose digital I/O / conversion clock—12-bit ADC LCD segment output 18 31 O General-purpose digital I/O / Comparator_A output / LCD segment output 19 32 O LCD segment output 20 33 O LCD segment output 21 34 O LCD segment output 22 35 O LCD segment output 23 36 O General-purpose digital I/O / LCD segment output 24 37 O General-purpose digital I/O / LCD segment output 25 38 O General-purpose digital I/O / LCD segment output 26 39 O General-purpose digital I/O / LCD segment output 27 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 MSP430x43x Terminal Functions (Continued) TERMINAL PN NAME I/O NO. PZ NAME P3.3/UCLK0/S28 40 I/O S28 I/O NO. DESCRIPTION General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI 40 O mode, clock o/p—USART0/SPI mode / LCD segment output 28 P3.2/SOMI0/S29 41 I/O S29 General-purpose digital I/O / slave out/master in of USART0/SPI mode 41 O / LCD segment output 29 P3.1/SIMO0/S30 42 I/O S30 42 O General-purpose digital I/O / slave out/master out of USART0/SPI mode / LCD segment output 30 P3.0/STE0/S31 43 I/O S31 43 O General-purpose digital I/O / slave transmit enable-USART0/SPI mode / LCD segment output 31 S32 44 O LCD segment output 32 S33 45 O LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35 P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36 P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37 P4.3/S38 50 I/O General-purpose digital I/O / LCD segment output 38 P4.2/S39 51 I/O General-purpose digital I/O / LCD segment output 39 COM0 44 O COM0 52 O COM0–3 are used for LCD backplanes. P5.2/COM1 45 I/O P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0–3 are used for LCD backplanes. P5.3/COM2 46 I/O P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0–3 are used for LCD backplanes. P5.4/COM3 47 I/O P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0–3 are used for LCD backplanes. R03 48 I R03 56 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R13 49 I/O P5.5/R13 57 I/O General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3) P5.6/R23 50 I/O P5.6/R23 58 I/O General-purpose digital I/O / input port of second most positive analog LCD level (V2) P5.7/R33 51 I/O P5.7/R33 59 I/O General-purpose digital I/O / output port of most positive analog LCD level (V1) DVCC2 DVSS2 52 DVCC2 53 DVSS2 P4.1 60 61 62 I/O General-purpose digital I/O P4.0 63 I/O General-purpose digital I/O P3.7 64 I/O General-purpose digital I/O P3.6 65 I/O General-purpose digital I/O P3.5 66 I/O General-purpose digital I/O P3.4 67 I/O General-purpose digital I/O P3.3/UCLK0 68 I/O General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock output—USART0/SPI mode P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable USART0/SPI mode P2.7/ADC12CLK 72 I/O General-purpose digital I/O / conversion clock—12-bit ADC P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output P2.5/URXD0 54 I/O P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 MSP430x43x Terminal Functions (Continued) PN NAME P2.4/UTXD0 P2.3/TB2 P2.2/TB1 P2.1/TB0 P2.0/TA2 P1.7/CA1 P1.6/CA0 P1.5/TACLK/ ACLK P1.4/TBCLK/ SMCLK P1.3/TBOUTH/ SVSOUT P1.2/TA1 P1.1/TA0/MCLK P1.0/TA0 XT2OUT XT2IN TDO/TDI TDI TMS TCK RST/NMI P6.0/A0 P6.1/A1 P6.2/A2 AVSS DVSS1 AVCC TERMINAL I/O NO. PZ NAME 55 I/O P2.4/UTXD0 56 I/O P2.3/TB2 57 I/O P2.2/TB1 58 I/O P2.1/TB0 59 I/O P2.0/TA2 60 I/O P1.7/CA1 61 I/O P1.6/CA0 62 I/O P1.5/TACLK/ ACLK 63 I/O P1.4/TBCLK/ SMCLK 64 I/O P1.3/TBOUTH/ SVSOUT 65 I/O P1.2/TA1 66 I/O P1.1/TA0/MCLK 67 I/O P1.0/TA0 68 O XT2OUT 69 I XT2IN 70 I/O TDO/TDI 71 I TDI 72 I TMS 73 I TCK 74 I RST/NMI 75 I/O P6.0/A0 76 I/O P6.1/A1 77 I/O P6.2/A2 78 AVSS 79 DVSS1 80 AVCC I/O NO. DESCRIPTION 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode General-purpose digital I/O / Timer_B3 CCR2. 76 I/O Capture: CCI2A/CCI2B input, compare: Out2 output General-purpose digital I/O / Timer_B3 CCR1. 77 I/O Capture: CCI1A/CCI1B input, compare: Out1 output 78 I/O General-purpose digital I/O / Timer_B3 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output 80 I/O General-purpose digital I/O / Comparator_A input 81 I/O General-purpose digital I/O / Comparator_A input 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8) 83 I/O General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain system clock SMCLK output 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: 85 I/O Out1 output 86 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this pin. 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output 88 O Output terminal of crystal oscillator XT2 Input port for crystal oscillator XT2. Only standard crystals can be 89 I connected. 90 I/O Test data output port. TDO/TDI data output or programming data input terminal 91 I Test data input. TDI is used as a data input port. The device protection fuse is connected to TDI. 92 I Test mode select. TMS is used as an input port for device programming and test. 93 I Test clock. TCK is the clock input port for device programming and test. 94 I General-purpose digital I/O / reset input or nonmaskable interrupt input port 95 I/O General-purpose digital I/O / analog input a0 – 12-bit ADC 96 I/O General-purpose digital I/O / analog input a1 – 12-bit ADC 97 I/O General-purpose digital I/O / analog input a2 – 12-bit ADC 98 Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD resistive divider circuitry. 99 Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via AVCC/AVSS. Positive terminal that supplies SVS, brownout, oscillator, FLL+, 100 comparator_A, port 1, and LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2. 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER TERMINAL PN NAME NO. DVCC1 1 P6.3/A3 2 P6.4/A4 3 P6.5/A5 4 P6.6/A6 5 P6.7/A7/SVSin 6 VREF+ 7 XIN 8 XOUT/TCLK 9 VeREF+ 10 VREF–/VeREF– 11 P5.1/S0 12 P5.0/S1 13 S2 14 S3 15 S4 16 S5 17 S6 18 S7 19 S8 20 S9 21 S10 22 S11 23 S12 24 S13 25 S14 26 S15 27 S16 28 S17 29 S18 30 S19 31 S20 32 S21 33 S22 34 S23 35 S24 36 S25 37 S26 38 S27 39 S28 40 SLAS344C – JANUARY 2002 – REVISED MARCH2003 MSP430x44x Terminal Functions I/O DESCRIPTION Digital supply voltage, positive terminal. Supplies all digital parts I/O General-purpose digital I/O, analog input a3—12-bit ADC I/O General-purpose digital I/O, analog input a4—12-bit ADC I/O General-purpose digital I/O, analog input a5—12-bit ADC I/O General-purpose digital I/O, analog input a6—12-bit ADC General-purpose digital I/O, analog input a7—12-bit ADC, analog input to brownout, supply voltage I/O supervisor O Output of positive terminal of the reference voltage in the ADC I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. I/O Output terminal of crystal oscillator XT1 or test clock input I Input for an external reference voltage to the ADC I Negative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage O General-purpose digital I/O, LCD segment output 0 O General-purpose digital I/O, LCD segment output 1 O LCD segment output 2 O LCD segment output 3 O LCD segment output 4 O LCD segment output 5 O LCD segment output 6 O LCD segment output 7 O LCD segment output 8 O LCD segment output 9 O LCD segment output 10 O LCD segment output 11 O LCD segment output 12 O LCD segment output 13 O LCD segment output 14 O LCD segment output 15 O LCD segment output 16 O LCD segment output 17 O LCD segment output 18 O LCD segment output 19 O LCD segment output 20 O LCD segment output 21 O LCD segment output 22 O LCD segment output 23 O LCD segment output 24 O LCD segment output 25 O LCD segment output 26 O LCD segment output 27 O LCD segment output 28 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 MSP430x44x Terminal Functions (Continued) TERMINAL PN NAME NO. S29 41 S30 42 S31 43 S32 44 S33 45 P4.7/S34 46 P4.6/S35 47 P4.5/UCLK1/S36 48 P4.4/SOMI1/S37 49 P4.3/SIMO1/S38 50 P4.2/STE1/S39 51 COM0 52 P5.2/COM1 53 P5.3/COM2 54 P5.4/COM3 55 R03 56 P5.5/R13 57 P5.6/R23 58 P5.7/R33 59 DVCC2 60 DVSS2 61 P4.1/URXD1 62 P4.0/UTXD1 63 P3.7/TB6 64 P3.6/TB5 65 P3.5/TB4 66 P3.4/TB3 67 P3.3/UCLK0 68 P3.2/SOMI0 69 P3.1/SIMO0 70 P3.0/STE0 71 P2.7/ADC12CLK 72 P2.6/CAOUT 73 P2.5/URXD0 74 P2.4/UTXD0 75 P2.3/TB2 76 P2.2/TB1 77 P2.1/TB0 78 P2.0/TA2 79 P1.7/CA1 80 I/O DESCRIPTION O LCD segment output 29 O LCD segment output 30 O LCD segment output 31 O LCD segment output 32 O LCD segment output 33 I/O General-purpose digital I/O / LCD segment output 34 I/O General-purpose digital I/O / LCD segment output 35 I/O General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock output—USART1/SPI MODE / LCD segment output 36 I/O General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37 I/O General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38 I/O General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output 39 O COM0–3 are used for LCD backplanes. I/O General-purpose digital I/O / common output, COM0–3 are used for LCD backplanes. I/O General-purpose digital I/O / common output, COM0–3 are used for LCD backplanes. I/O General-purpose digital I/O / common output, COM0–3 are used for LCD backplanes. I Input port of fourth positive (lowest) analog LCD level (V5) I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3) I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2) I/O General-purpose digital I/O / Output port of most positive analog LCD level (V1) I/O General-purpose digital I/O / receive data in—USART1/UART mode I/O General-purpose digital I/O / transmit data out—USART1/UART mode I/O General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output I/O General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output I/O General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output I/O General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output I/O General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock output—USART0/SPI mode I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode I/O General-purpose digital I/O / conversion clock—12-bit ADC I/O General-purpose digital I/O / Comparator_A output I/O General-purpose digital I/O / receive data in—USART0/UART mode I/O General-purpose digital I/O / transmit data out—USART0/UART mode I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output I/O General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output I/O General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output I/O General-purpose digital I/O / Comparator_A input 10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER TERMINAL PN NAME NO. P1.6/CA0 81 P1.5/TACLK/ ACLK 82 P1.4/TBCLK/ SMCLK 83 P1.3/TBOutH/ SVSOut 84 P1.2/TA1 85 P1.1/TA0/MCLK 86 P1.0/TA0 87 XT2OUT 88 XT2IN 89 TDO/TDI 90 TDI 91 TMS 92 TCK 93 RST/NMI 94 P6.0/A0 95 P6.1/A1 96 P6.2/A2 97 AVSS 98 DVSS1 99 AVCC 100 SLAS344C – JANUARY 2002 – REVISED MARCH2003 MSP430x44x Terminal Functions (Continued) I/O DESCRIPTION I/O General-purpose digital I/O / Comparator_A input I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8) I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0 to TB6 / SVS: output of SVS comparator I/O General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output I/O General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this pin. I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output O Output terminal of crystal oscillator XT2 I Input port for crystal oscillator XT2. Only standard crystals can be connected. I/O Test data output port. TDO/TDI data output or programming data input terminal I Test data input. TDI is used as a data input port. The device protection fuse is connected to TDI. I Test mode select. TMS is used as an input port for device programming and test. I Test clock. TCK is the clock input port for device programming and test. I Reset input or nonmaskable interrupt input port I/O General-purpose digital I/O, analog input a0—12-bit ADC I/O General-purpose digital I/O, analog input a1—12-bit ADC I/O General-purpose digital I/O, analog input a2—12-bit ADC Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD resistive divider circuitry. Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via AVCC/AVSS. Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 1. Instruction Word Formats Dual operands, source-destination Single operands, destination only Relative jump, un/conditional e.g. ADD R4,R5 e.g. CALL R8 e.g. JNE R4 + R5 –––> R5 PC ––>(TOS), R8––> PC Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX Register nn MOV Rs,Rd Indexed n n MOV X(Rn),Y(Rm) Symbolic (PC relative) n n MOV EDE,TONI Absolute nn MOV and MEM,and TCDAT Indirect n MOV @Rn,Y(Rm) Indirect autoincrement n MOV @Rn+,Rm Immediate n MOV #X,TONI NOTE: S = source D = destination EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI OPERATION R10 ––> R11 M(2+R5)––> M(6+R6) M(EDE) ––> M(TONI) M(MEM) ––> M(TCDAT) M(R10) ––> M(Tab+R6) M(R10) ––> R11 R10 + 2––> R10 #45 ––> M(TONI) 12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode AM; – All clocks are active D Low-power mode 0 (LPM0); – CPU is disabled ACLK and SMCLK remain active. MCLK is disabled FLL+ Loop control remains active D Low-power mode 1 (LPM1); – CPU is disabled FLL+ Loop control is disabled ACLK and SMCLK remain active. MCLK is disabled D Low-power mode 2 (LPM2); – CPU is disabled MCLK and FLL+ loop control and DCOCLK are disabled DCO’s dc-generator remains enabled ACLK remains active D Low-power mode 3 (LPM3); – CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled ACLK remains active D Low-power mode 4 (LPM4); – CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 13 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh – 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3. Interrupt Sources, Flags, and Vectors of 4xx Configurations INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-Up External Reset Watchdog Flash Memory WDTIFG KEYV (see Note 1) Reset 0FFFEh 15, highest NMI Oscillator Fault Flash Memory Access Violation Timer_B7† NMIIFG (see Notes 1 and 3) OFIFG (see Notes 1 and 3) ACCVIFG (see Notes 1 and 3) TBCCR0 CCIFG (see Note 2) (Non)maskable (Non)maskable 0FFFCh 14 (Non)maskable Maskable 0FFFAh 13 Timer_B7† TBCCR1 to TBCCR6 CCIFGs TBIFG (see Notes 1 and 2) Maskable 0FFF8h 12 Comparator_A CAIFG Maskable 0FFF6h 11 Watchdog Timer WDTIFG Maskable 0FFF4h 10 USART0 Receive URXIFG0 Maskable 0FFF2h 9 USART0 Transmit UTXIFG0 Maskable 0FFF0h 8 ADC12 ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 7 Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6 Timer_A3 TACCR1 and TACCR2 CCIFGs, TAIFG (see Notes 1 and 2) Maskable 0FFEAh 5 I/O Port P1 (Eight Flags) USART1 Receive‡ USART1 Transmit‡ P1IFG.0 (see Notes 1 and 2) To P1IFG.7 (see Notes 1 and 2) URXIFG1 UTXIFG1 Maskable Maskable Maskable 0FFE8h 4 0FFE6h 3 0FFE4h 2 I/O Port P2 (Eight Flags) P2IFG.0 (see Notes 1 and 2) To P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 1 Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest † ’43x uses Timer_B3 with TBCCR0, 1 and 2 CCIFG flags, and TBIFG. ’44x uses Timer_B7 with TBCCR0 CCIFG, TBCCR1 to TBCCR6 CCIFGs, and TBIFG ‡ USART1 is implemented in ’44x only. NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it. 14 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 special function registers Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access. interrupt enable 1 and 2 Address 7 6 5 4 3 0h UTXIE0 URXIE0 ACCVIE NMIIE rw–0 rw–0 rw–0 rw–0 2 1 0 OFIE WDTIE rw–0 rw–0 WDTIE: OFIE: NMIIE: ACCVIE: URXIE0: UTXIE0: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator-fault-interrupt enable Nonmaskable-interrupt enable Flash access violation interrupt enable USART0, UART, and SPI receive-interrupt enable USART0, UART, and SPI transmit-interrupt enable Address 7 6 5 4 3 2 1 0 01h BTIE UTXIE1 URXIE1 rw–0 rw–0 rw–0 URXIE1: UTXIE1: BTIE: USART1, UART, and SPI receive-interrupt enable (MSP430F44x devices only) USART1, UART, and SPI transmit-interrupt enable (MSP430F44x devices only) Basic timer interrupt enable interrupt flag register 1 and 2 Address 7 6 5 4 3 02h UTXIFG0 URXIFG0 NMIIFG rw–1 rw–0 rw–0 2 1 0 OFIFG WDTIFG rw–1 rw–0 WDTIFG: OFIFG: NMIIFG: URXIFG0: UTXIFG0: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power up or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI pin USART0, UART, and SPI receive flag USART0, UART, and SPI transmit flag Address 7 6 5 4 3 2 1 0 03h BTIFG UTXIFG1 URXIFG1 rw rw–1 rw–0 URXIFG1: UTXIFG1: BTIFG: USART1, UART, and SPI receive flag (MSP430F44x devices only) USART1, UART, and SPI transmit flag (MSP430F44x devices only) Basic timer flag • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 15 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 module enable registers 1 and 2 Address 7 6 5 4 3 2 1 0 04h UTXE0 URXE0 USPIE0 rw–0 rw–0 URXE0: UTXE0: USPIE0: USART0, UART mode receive enable USART0, UART mode transmit enable USART0, SPI mode transmit and receive enable Address 7 6 5 4 3 2 1 0 05h UTXE1 URXE1 USPIE1 rw–0 rw–0 URXE1: UTXE1: USPIE1: USART1, UART mode receive enable (MSP430F44x devices only) USART1, UART mode transmit enable (MSP430F44x devices only) USART1, SPI mode transmit and receive enable (MSP430F44x devices only) Legend: rw: rw–0: Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset by PUC. SFR Bit Not Present in Device memory organization Memory Main: interrupt vector Main: code memory Information memory Boot memory RAM Peripherals Size Flash Flash Size Flash Size ROM Size 16-bit 8-bit 8-bit SFR MSP430F435 16KB 0FFFFh – 0FFE0h 0FFFFh – 0C000h 256 Byte 010FFh – 01000h 1KB 0FFFh – 0C00h 512 Byte 03FFh – 0200h 01FFh – 0100h 0FFh – 010h 0Fh – 00h MSP430F436 24KB 0FFFFh – 0FFE0h 0FFFFh – 0A000h 256 Byte 010FFh – 01000h 1KB 0FFFh – 0C00h 1KB 05FFh – 0200h 01FFh – 0100h 0FFh – 010h 0Fh – 00h MSP430F437 MSP430F447 32KB 0FFFFh – 0FFE0h 0FFFFh – 08000h 256 Byte 010FFh – 01000h 1KB 0FFFh – 0C00h 1KB 05FFh – 0200h 01FFh – 0100h 0FFh – 010h 0Fh – 00h MSP430F448 48KB 0FFFFh – 0FFE0h 0FFFFh – 04000h 256 Byte 010FFh – 01000h 1KB 0FFFh – 0C00h 2KB 09FFh – 0200h 01FFh – 0100h 0FFh – 010h 0Fh – 00h MSP430F449 60KB 0FFFFh – 0FFE0h 0FFFFh – 01100h 256 Byte 010FFh – 01000h 1KB 0FFFh – 0C00h 2KB 09FFh – 0200h 01FFh – 0100h 0FFh – 010h 0Fh – 00h bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089. 16 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0–n. Segments A and B are also called information memory. D New devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. 16KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 24KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 32KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 48KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 60KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh Segment 0 w/ Interrupt Vectors Segment 1 Segment 2 Main Memory 0C400h 0C3FFh 0C200h 0C1FFh 0C000h 010FFh 01080h 0107Fh 01000h 0A400h 0A3FFh 0A200h 0A1FFh 0A000h 010FFh 01080h 0107Fh 01000h 08400h 083FFh 08200h 081FFh 08000h 010FFh 01080h 0107Fh 01000h 04400h 043FFh 04200h 041FFh 04000h 010FFh 01080h 0107Fh 01000h 01400h 013FFh 01200h 011FFh 01100h 010FFh 01080h 0107Fh 01000h Segment n-1 Segment n Segment A Segment B Information Memory peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. digital I/O There are six 8-bit I/O ports implemented—ports P1 through P6: D All individual I/O bits are independently programmable. D Any combination of input, output, and interrupt conditions is possible. D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. D Read/write access to port-control registers is supported by all instructions. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 17 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344C – JANUARY 2002 – REVISED MARCH2003 oscillator and system clock The clock system in the MSP430x43x and MSP43x44x family of devices is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module provides the following clock signals: D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8. brownout, supply voltage supervisor The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min). multiplication (MSP430x44x Only) The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16, 16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required. Basic Timer1 The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module. LCD drive The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. 18 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 19 POST OFFICE BOX 655303• DALLAS, TEXAS 75265 Table 4. MSP430x43xIPN Terminal Function, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM TERMINAL NAME P5.1/S0 P5.0/S1 P4.7/S2 P4.6/S3 P4.5/S4 P4.4/S5 P4.3/S6 P4.2/S7 P4.1/S8 P4.0/S9 S10–S17 P2.7/ADC10CLK/S18 P2.6/CAOUT/S19 S20–S23 P3.7/S24 P3.6/S25 P3.5/S26 P3.4/S27 P3.3/UCLK0/S28 P3.2/SOMI0/S29 P3.1/SIMO0/S30 P3.0/STE0/S31 I/O NO 000X XXXX 001X XXXX BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM 010X XXX 011X XXXX 100X XXXX 101X XXXX 110X XXX 12 I/O P5.1 S0 13 I/O P5.0 S1 14 I/O P4.7 S2 15 I/O P4.6 S3 16 I/O P4.5 S4 17 I/O P4.4 S5 18 I/O P4.3 S6 19 I/O P4.2 S7 20 I/O P4.1 S8 21 I/O P4.0 S9 22–29 O S10–S17 30 I/O P2.7/ADC10CLK P2.7/ADC10CLK S18 31 I/O P2.6/CAOUT P2.6/CAOUT S19 32–35 O S20–S23 36 I/O P3.7 P3.7 P3.7 P3.7 S24 37 I/O P3.6 P3.6 P3.6 P3.6 S25 38 I/O P3.5 P3.5 P3.5 P3.5 S26 39 I/O P3.4 P3.4 P3.4 P3.4 S27 40 I/O P3.3/UCLK0 P3.3/UCLK0 P3.3/UCLK0 P3.3/UCLK0 P3.3/UCLK0 S28 41 I/O P3.2/SOMI0 P3.2/SOMI0 P3.2/SOMI0 P3.2/SOMI0 P3.2/SOMI0 S29 42 I/O P3.1/SIMO0 P3.1/SIMO0 P3.1/SIMO0 P3.1/SIMO0 P3.1/SIMO0 S30 43 I/O P3.0/STE0 P3.0/STE0 P3.0/STE0 P3.0/STE0 P3.0/STE0 S31 111X XXXX MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 20 Table 5. MSP430x43xIPZ Terminal Functions, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM TERMINAL I/O NAME NO P5.1/S0 12 I/O P5.0/S1 13 I/O S2–S33 14–45 O P4.7/S34 46 I/O P4.6/S35 47 I/O P4.5/S36 48 I/O P4.4/S36 48 I/O P4.3/S36 48 I/O P4.2/S36 48 I/O 000X XXXX P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 001X XXXX P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM 010X XXX 011X XXXX 100X XXXX 101X XXXX P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 S0 S1 S2–S33 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 110X XXXX 111X XXXX S34 S35 P4.5 S36 P4.4 S37 P4.3 S38 P4.2 S39 POST OFFICE BOX 655303• DALLAS, TEXAS 75265 Table 6. MSP430x44xIPZ Terminal Functions, Selected by Bits 5/6/7 in LCD Mode Control Register LCDM TERMINAL I/O NAME NO P5.1/S0 12 I/O P5.0/S1 13 I/O S2–S33 14–45 O P4.7/S34 46 I/O P4.6/S35 47 I/O P4.5/UCLK1/S36 48 I/O P4.4/SOMI1/S37 49 I/O P4.3/SIMO1/S38 50 I/O P4.2/STE1/S39 51 I/O 000X XXXX P5.1 P5.0 P4.7 P4.6 P4.5/UCLK1 P4.4/SOMI1 P4.3/SIMO1 P4.2/STE1 001X XXXX P4.7 P4.6 P4.5UCLK1 P4.4/SOMI1 P4.3/SIMO1 P4.2/STE1 BITS 5/6/7 IN LCD MODE CONTROL REGISTER LCDM 010X XXX P4.7 P4.6 P4.5/UCLK1 P4.4/SOMI1 P4.3/SIMO1 P4.2/STE1 011X XXXX P4.7 P4.6 P4.5/UCLK1 P4.4/SOMI1 P4.3/SIMO1 P4.2/STE1 100X XXXX S0 S1 S2–S33 P4.7 P4.6 P4.5/UCLK1 P4.4/SOMI1 P4.3/SIMO1 P4.2/STE1 101X XXXX P4.7 P4.6 P4.5/UCLK1 P4.4/SOMI1 P4.3/SIMO1 P4.2/STE1 110X XXXX 111X XXXX S34 S35 P4.5/UCLK1 S36 P4.4/SOMI1 S37 P4.3/SIMO1 S38 P4.2/STE1 S39 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 watchdog timer The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. USART0 The MSP430x43x and the MSP430x44x have one hardware universal synchronous/asynchronous receive transmit (USART0) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. USART1 (MSP430x44x Only) The MSP430x44x has a second hardware universal synchronous/asynchronous receive transmit (USART1) peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels. Operation of USART1 is identical to USART0. timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer_B7 (MSP430x44x Only) Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer_B3 (MSP430x43x Only) Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. comparator_A The primary function of the comparator_A module is to support precision slope analog–to–digital conversions, battery–voltage supervision, and monitoring of external analog signals. ADC12 The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 21 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 peripheral file map PERIPHERALS WITH WORD ACCESS Watchdog Watchdog timer control WDTCTL 0120h Timer_B7 Timer_B3 (see Note 6) Capture/compare register 6 Capture/compare register 5 Capture/compare register 4 TBCCR6 TBCCR5 TBCCR4 019Eh 019Ch 019Ah Capture/compare register 3 TBCCR3 0198h Capture/compare register 2 TBCCR2 0196h Capture/compare register 1 TBCCR1 0194h Capture/compare register 0 TBCCR0 0192h Timer_B register TBR 0190h Capture/compare control 6 TBCCTL6 018Eh Capture/compare control 5 TBCCTL5 018Ch Capture/compare control 4 TBCCTL4 018Ah Capture/compare control 3 TBCCTL3 0188h Capture/compare control 2 TBCCTL2 0186h Capture/compare control 1 TBCCTL1 0184h Capture/compare control 0 TBCCTL0 0182h Timer_B control TBCTL 0180h Timer_B interrupt vector TBIV 011Eh Timer_A3 Reserved 017Eh Reserved 017Ch Reserved 017Ah Reserved 0178h Capture/compare register 2 TACCR2 0176h Capture/compare register 1 TACCR1 0174h Capture/compare register 0 TACCR0 0172h Timer_A register TAR 0170h Reserved 016Eh Reserved 016Ch Reserved 016Ah Reserved 0168h Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh Multiply Sum extend (MSP430x44x only) Result high word SUMEXT RESHI 013Eh 013Ch Result low word RESLO 013Ah Second operand OP2 0138h Multiply signed + accumulate/operand1 MACS 0136h Multiply + accumulate/operand1 MAC 0134h Multiply signed/operand1 MPYS 0132h Multiply unsigned/operand1 MPY 0130h NOTE 4: Timer_B7 in the MSP430x44x family has seven CCRs; Timer_B3 in the MSP430x43x family has three CCRs. 22 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 peripheral file map (continued) Flash ADC12 PERIPHERALS WITH WORD ACCESS (CONTINUED) Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h Conversion memory 15 ADC12MEM15 015Eh Conversion memory 14 ADC12MEM14 015Ch Conversion memory 13 ADC12MEM13 015Ah Conversion memory 12 ADC12MEM12 0158h Conversion memory 11 ADC12MEM11 0156h Conversion memory 10 ADC12MEM10 0154h Conversion memory 9 ADC12MEM9 0152h Conversion memory 8 ADC12MEM8 0150h Conversion memory 7 ADC12MEM7 014Eh Conversion memory 6 ADC12MEM6 014Ch Conversion memory 5 ADC12MEM5 014Ah Conversion memory 4 ADC12MEM4 0148h Conversion memory 3 ADC12MEM3 0146h Conversion memory 2 ADC12MEM2 0144h Conversion memory 1 ADC12MEM1 0142h Conversion memory 0 ADC12MEM0 0140h Interrupt-vector-word register ADC12IV 01A8h Inerrupt-enable register ADC12IE 01A6h Inerrupt-flag register ADC12IFG 01A4h Control register 1 ADC12CTL1 01A2h Control register 0 ADC12CTL0 01A0h ADC memory-control register15 ADC12MCTL15 08Fh ADC memory-control register14 ADC12MCTL14 08Eh ADC memory-control register13 ADC12MCTL13 08Dh ADC memory-control register12 ADC12MCTL12 08Ch ADC memory-control register11 ADC12MCTL11 08Bh ADC memory-control register10 ADC12MCTL10 08Ah ADC memory-control register9 ADC12MCTL9 089h ADC memory-control register8 ADC12MCTL8 088h ADC memory-control register7 ADC12MCTL7 087h ADC memory-control register6 ADC12MCTL6 086h ADC memory-control register5 ADC12MCTL5 085h ADC memory-control register4 ADC12MCTL4 084h ADC memory-control register3 ADC12MCTL3 083h ADC memory-control register2 ADC12MCTL2 082h ADC memory-control register1 ADC12MCTL1 081h ADC memory-control register0 ADC12MCTL0 080h • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 23 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 peripheral file map (continued) LCD USART1 (Only in ‘x44x) USART0 Comparator_A BrownOUT, SVS FLL+ Clock Basic Timer1 Port P6 Port P5 PERIPHERALS WITH BYTE ACCESS LCD memory 20 : LCD memory 16 LCD memory 15 : LCD memory 1 LCD control and mode Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control Comparator_A port disable Comparator_A control2 Comparator_A control1 SVS control register (Reset by brownout signal) FLL+ Control1 FLL+ Control0 System clock frequency control System clock frequency integrator System clock frequency integrator BT counter2 BT counter1 BT control Port P6 selection Port P6 direction Port P6 output Port P6 input Port P5 selection Port P5 direction Port P5 output Port P5 input LCDM20 : LCDM16 LCDM15 : LCDM1 LCDCTL U1TXBUF U1RXBUF U1BR1 U1BR0 U1MCTL U1RCTL U1TCTL U1CTL U0TXBUF U0RXBUF U0BR1 U0BR0 U0MCTL U0RCTL U0TCTL U0CTL CAPD CACTL2 CACTL1 SVSCTL FLL_CTL1 FLL_CTL0 SCFQCTL SCFI1 SCFI0 BTCNT2 BTCNT1 BTCTL P6SEL P6DIR P6OUT P6IN P5SEL P5DIR P5OUT P5IN 0A4h : 0A0h 09Fh : 091h 090h 07Fh 07Eh 07Dh 07Ch 07Bh 07Ah 079h 078h 077h 076h 075h 074h 073h 072h 071h 070h 05Bh 05Ah 059h 056h 054h 053h 052h 051h 050h 047h 046h 040h 037h 036h 035h 034h 033h 032h 031h 030h 24 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 peripheral file map (continued) Port P4 Port P3 Port P2 Port P1 Special functions PERIPHERALS WITH BYTE ACCESS Port P4 selection Port P4 direction Port P4 output Port P4 input Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 selection Port P2 interrupt enable Port P2 interrupt-edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 selection Port P1 interrupt enable Port P1 interrupt-edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input SFR module enable2 SFR module enable1 SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 P4SEL P4DIR P4OUT P4IN P3SEL P3DIR P3OUT P3IN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN ME2 ME1 IFG2 IFG1 IE2 IE1 01Fh 01Eh 01Dh 01Ch 01Bh 01Ah 019h 018h 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 026h 025h 024h 023h 022h 021h 020h 005h 004h 003h 002h 001h 000h absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.1 V Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature, Tstg: (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 25 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 recommended operating conditions MIN NOM MAX UNITS Supply voltage during program execution, VCC (AVCC = DVCC1 = DVCC2 = VCC) MSP430F43x, MSP430F44x 1.8 Supply voltage during flash memory programming, VCC (AVCC = DVCC1 = DVCC2 = VCC) MSP430F43x, MSP430F44x 2.7 Supply voltage during program execution, SVS enabled (see Note 1), VCC (AVCC = DVCC1 = DVCC2 = VCC) MSP430F43x, MSP430F44x 2 Supply voltage, VSS (AVSS = DVSS1 = DVSS2 = VSS) 0 Operating free-air temperature range, TA MSP430x43x MSP430x44x –40 3.6 V 3.6 V 3.6 V 0V 85 °C LF selected, XTS_FLL=0 Watch crystal 32.768 kHz LFXT1 crystal frequency, f(LFXT1) (see Note 2) XT1 selected, XTS_FLL=1 Ceramic resonator 450 8000 kHz XT1 selected, XTS_FLL=1 Crystal 1000 8000 kHz XT2 crystal frequency, f(XT2) Ceramic resonator Crystal 450 1000 8000 kHz 8000 Processor frequency (signal MCLK), f(System) Flash-timing-generator frequency, f(FTG) VCC = 1.8 V DC VCC = 3.6 V DC MSP430F43x, MSP430F44x 257 4.15 MHz 8 476 kHz Cumulative program time, t(CPT) (see Note 3) VCC = 2.7 V/3.6 V MSP430F43x MSP430F44x 3 ms Mass erase time, t(MEras) (See the flash memory, timing generator, control register FCTL2 section and Note 4) VCC = 2.7 V/3.6 V 200 ms Low-level input voltage (TCK, TMS, TDI, RST/NMI), VIL (excluding Xin, Xout) VCC = 2.2 V/3 V VSS VSS + 0.6 V High-level input voltage (TCK, TMS, TDI, RST/NMI), VIH (excluding Xin, Xout) VCC = 2.2 V/3 V 0.8 × VCC VCC V Input levels at Xin and Xout VIL(Xin, Xout) VIH(Xin, Xout) VCC = 2.2 V/3 V VSS 0.8 × VCC 0.2 × VCC V VCC NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry. 2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal. 3. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if segment write option is used. 4. The mass erase duration generated by the flash timing generator is at least 11.1 ms. The cumulative mass erase time needed is 200 ms. This can be achieved by repeating the mass erase operation until the cumulative mass erase time is met (a minimum of 19 cycles may be required). 26 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 typical characteristics f (MHz) 8 MHz 4.15 MHz ÎÎÎÎÎ Supply voltage range, ÎÎÎÎÎ ’F43x/’F44x, during ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ program execution Supply voltage range, ’F43x/’F44x, during flash memory programming 1.8 2.7 3 3.6 Supply Voltage – V Figure 1. Frequency vs Supply Voltage, MSP430F43x or MSP430F44x electrical characteristics over recommended operating free-air temperature (unless otherwise noted) supply current into AVCC + DVCC excluding external current PARAMETER TEST CONDITIONS MIN NOM MAX UNIT I(AM) Active mode, (see Note 1) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) F43x, F44x TA = –40°C to 85°C VCC = 2.2 V VCC = 3 V 280 350 µA 420 560 Low-power mode, (LPM0) I(LPM0) (see Note 1) F43x, F44x Low-power mode, (LPM2), I(LPM2) f(MCLK) = f (SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2) TA = –40°C to 85°C TA = –40°C to 85°C VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V 32 45 55 70 µA 11 14 µA 17 22 TA = –40°C 1 1.5 I(LPM3) Low-power mode, (LPM3) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 (see Note 3) TA = 25°C TA = 60°C TA = 85°C TA = –40°C VCC = 2.2 V 1.1 1.5 µA 2 3 3.5 6 1.8 2.2 TA = 25°C TA = 60°C VCC = 3 V 1.6 1.9 2.5 3.5 µA TA = 85°C 4.2 7.5 TA = –40°C 0.1 0.5 I(LPM4) Low-power mode, (LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 (see Note 2) TA = 25°C TA = 60°C TA = 85°C TA = –40°C TA = 25°C TA = 60°C VCC = 2.2 V VCC = 3 V 0.1 0.5 µA 0.7 1.1 1.7 3 0.1 0.5 0.1 0.5 µA 0.8 1.2 TA = 85°C 1.9 3.5 NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. 3. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumption in LPM3 is measured with active Basic Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified in the respective sections. The LPM3 currents are characterized with a KDS Daishinku DT–38 (6 pF) crystal and OSCCAP=1. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 27 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Current consumption of active mode versus system frequency, F-version: I(AM) = I(AM) [1 MHz] × f(System) [MHz] Current consumption of active mode versus supply voltage, F-version: I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V) SCHMITT-trigger inputs – ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI, TDO VIT+ PARAMETER Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ – VIT–) TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN TYP MAX 1.1 1.5 1.5 1.9 0.4 0.9 0.9 1.3 0.3 1.1 0.5 1 UNIT V V V outputs – ports P1, P2, P3, P4, P5, and P6 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH(max) = –1.5 mA, VCC = 2.2 V, See Note 1 VCC–0.25 VCC VOH High-level output voltage IOH(max) = –6 mA, VCC = 2.2 V, IOH(max) = –1.5 mA, VCC = 3 V, See Note 2 See Note 1 VCC–0.6 VCC–0.25 VCC V VCC IOH(max) = –6 mA, VCC = 3 V, See Note 2 VCC–0.6 VCC IOL(max) = 1.5 mA, VCC = 2.2 V, See Note 1 VSS VSS+0.25 VOL Low-level output voltage IOL(max) = 6 mA, IOL(max) = 1.5 mA, VCC = 2.2 V, VCC = 3 V, See Note 2 See Note 1 VSS VSS VSS+0.6 V VSS+0.25 IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6 NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified voltage drop. 28 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 typical characteristics I OL– Typical Low-level Output Current – mA TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 16 VCC = 2.2 V 14 P2.7 TA = 25°C 12 TA = 85°C 10 8 6 4 2 0 0.0 0.5 1.0 1.5 2.0 2.5 VOL – Low-Level Output Voltage – V Figure 2 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 VCC = 2.2 V P2.7 –2 –4 –6 –8 –10 TA = 85°C –12 TA = 25°C –14 0.0 0.5 1.0 1.5 2.0 2.5 VOH – High-Level Output Voltage – V Figure 4 I OL– Typical High-level Output Current – mA I OL – Typical Low-level Output Current – mA MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 25 VCC = 3 V P2.7 TA = 25°C 20 TA = 85°C 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL – Low-Level Output Voltage – V Figure 3 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 VCC = 3 V P2.7 –5 –10 –15 –20 TA = 85°C –25 TA = 25°C –30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH – High-Level Output Voltage – V Figure 5 I OL– Typical High-level Output Current – mA • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 29 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) output frequency PARAMETER f(Px.y) (1 ≤ x ≤ 6, 0 ≤ y ≤ 7) f(ACLK) f(MCLK) f(SMCLK) P1.1/TA0/MCLK, P1.5/TACLK/ ACLK P1.4/TBCLK/SMCLK t(Xdc) Duty cycle of output frequency TEST CONDITIONS MIN CL = 20 pF, VCC = 2.2 V DC IL = ±1.5 mA VCC = 3 V DC CL = 20 pF P1.5/TACLK/ACLK, CL = 20 pF VCC = 2.2 V / 3 V P1.1/TA0/MCLK, CL = 20 pF, VCC = 2.2 V / 3 V P1.4/TBCLK/SMCLK, CL = 20 pF, VCC = 2.2 V / 3 V f(ACLK) = f(LFXT1) = f(XT1) f(ACLK) = f(LFXT1) = f(LF) f(ACLK) = f(LFXT1) f(MCLK) = f(XT1) f(MCLK) = f(DCOCLK) f(SMCLK) = f(XT2) f(SMCLK) = f(DCOCLK) 40% 30% 40% 50%– 15 ns 40% 50%– 15 ns TYP MAX 5 7.5 f(System) 50% 50% 50% 60% 70% 60% 50%+ 15 ns 60% 50%+ 15 ns UNIT MHz MHz inputs Px.x, TAx, TBx PARAMETER t(int) External interrupt timing TEST CONDITIONS Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag, (see Note 1) VCC 2.2 V/3 V 2.2 V 3V MIN TYP MAX UNIT 1.5 cycle 62 ns 50 t(cap) Timer_A, Timer_B capture timing TA0, TA1, TA2 (see Note 2) TB0, TB1, TB2, TB3, TB4, TB5, TB6 (see Note 3) 2.2 V/3 V 1.5 2.2 V 62 3V 50 cycle ns f(TAext) f(TBext) Timer_A, Timer_B clock frequency externally applied to pin TACLK, TBCLK, INCLK: t(H) = t(L) 2.2 V 3V 8 MHz 10 f(TAint) Timer_A, Timer_B clock f(BTAint) frequency SMCLK or ACLK signal selected 2.2 V 3V 8 MHz 10 NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles. 2. The external capture signal triggers the capture event every time the minimum t(cap) cycle and time parameters are met. A capture may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a correct capture of the 16-bit timer value and to ensure the flag is set. 3. Seven capture/compare registers in ’x44x and three capture/compare registers in ’x43x. wake-up LPM3 PARAMETER td(LPM3) Delay time TEST CONDITIONS f = 1 MHz f = 2 MHz f = 3 MHz VCC = 2.2 V/3 V MIN TYP MAX UNIT 6 6 µs 6 30 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) leakage current (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN TYP MAX Ilkg(P1.x) Ilkg(P6.x) Leakage current Port P1 Port 1: V(P1.x) Port P6 Port 6: V(P6.x) VCC = 2.2 V/3 V ±50 ±50 NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor. UNIT nA RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRAMh CPU halted (see Note 1) 1.6 V NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition. LCD PARAMETER V(33) V(23) V(13) V(33) – V(03) I(R03) Analog voltage I(R13) Input leakage I(R23) V(Sxx0) V(Sxx1) V(Sxx2) V(Sxx3) Segment line voltage TEST CONDITIONS Voltage at P5.7/R33 Voltage at P5.6/R23 Voltage at P5.5/R13 VCC = 3 V Voltage at R33 to R03 R03 = VSS P5.5/R13 = VCC/3 P5.6/R23 = 2 × VCC/3 No load at all segment and common lines, VCC = 3 V I(Sxx) = –3 µA, VCC = 3 V MIN TYP MAX 2.5 VCC + 0.2 [V(33)–V(03)] × 2/3 + V(03) [V(33)–V(03)] × 1/3 + V(03) 2.5 VCC + 0.2 ±20 ±20 ±20 V(03) V(13) V(23) V(33) V(03) – 0.1 V(13) – 0.1 V(23) – 0.1 V(33) + 0.1 UNIT V nA V • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 31 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) Comparator_A (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(CC) I(Refladder/RefDiode) CAON=1, CARSEL=0, CAREF=0 CAON=1, CARSEL=0, CAREF=1/2/3, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V 25 40 µA 45 60 30 50 µA 45 71 V(Ref025) V(Ref050) Voltage @ 0.25 VCC node VCC Voltage @ 0.5 VCC node VCC V(RefVT) VIC Common-mode input voltage range PCA0=1, CARSEL=1, CAREF=1, No load at P2.3/CA0 and P2.4/CA1 PCA0=1, CARSEL=1, CAREF=2, No load at P2.3/CA0 and P2.4/CA1 PCA0=1, CARSEL=1, CAREF=3, No load at P2.3/CA0 and P2.4/CA1; TA = 85°C CAON=1 VCC = 2.2 V / 3 V 0.23 0.24 0.25 VCC = 2.2V / 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V / 3 V 0.47 0.48 0.5 390 480 400 490 540 mV 550 0 VCC–1 V Vp–VS Offset voltage See Note 2 VCC = 2.2 V / 3 V –30 30 mV Vhys Input hysteresis CAON = 1 VCC = 2.2 V / 3 V 0 0.7 1.4 mV t(response LH) TA = 25°C, Overdrive 10 mV, without filter: CAF = 0 TA = 25°C Overdrive 10 mV, with filter: CAF = 1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V 160 210 80 150 1.4 1.9 0.9 1.5 300 ns 240 3.4 µs 2.6 t(response HL) TA = 25°C Overdrive 10 mV, without filter: CAF = 0 TA = 25°C, Overdrive 10 mV, with filter: CAF = 1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V 130 210 80 150 1.4 1.9 0.9 1.5 300 ns 240 3.4 2.6 µs NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together. 32 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 typical characteristics REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 650 VCC = 3 V 600 Typical 550 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE 650 VCC = 2.2 V 600 Typical 550 VREF – Reference Voltage – V VREF – Reference Voltage – V 500 500 450 450 400 –45 –25 –5 15 35 55 75 95 TA – Free-Air Temperature – °C Figure 6. V(RefVT) vs Temperature 0 V VCC 01 CAON 400 –45 –25 –5 15 35 55 75 95 TA – Free-Air Temperature – °C Figure 7. V(RefVT) vs Temperature CAF V+ + V– _ Low-Pass Filter 0 0 1 1 To Internal Modules CAOUT τ ≈ 2 µs Figure 8. Block Diagram of Comparator_A Module Overdrive V– VCAOUT Set CAIFG Flag 400 mV V+ t(response) Figure 9. Overdrive Definition • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 33 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) POR/brownout reset (BOR) (see Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(BOR) 2000 µs VCC(start) dVCC/dt ≤ 3 V/s (see Figure 10) 0.7 × V(B_IT–) V V(B_IT–) Vhys(B_IT–) Brownout (see dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12) Note 2) dVCC/dt ≤ 3 V/s (see Figure 10) 1.71 V 70 130 180 mV t(reset) Pulse length needed at RST/NMI pin to accepted reset internally, VCC = 2.2 V/3 V 2 µs NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) + Vhys(B_IT–) is ≤ 1.8V. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B,IT–) + Vhys(B,IT–). The default FLL+ settings must not be changed until VCC ≥ VCC(min). See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit. typical characteristics VCC Vhys(B_IT–) V(B_IT–) VCC(start) 1 VCC(min)– V 0 t d(BOR) Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage 2 VCC = 3 V Typical Conditions 1.5 VCC t pw 3V 1 VCC(min) 0.5 0 0.001 1 tpw – Pulse Width – µs 1000 1 ns 1 ns tpw – Pulse Width – µs 34 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 Figure 11. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal typical characteristics 2 VCC = 3 V 1.5 Typical Conditions VCC t pw 3V VCC(min)– V 1 VCC(min) 0.5 0 0.001 1 1000 tf = tr tf tr tpw – Pulse Width – µs tpw – Pulse Width – µs Figure 12. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal electrical characteristics over recommended operating free-air temperature (unless otherwise noted) SVS (supply voltage supervisor/monitor) PARAMETER TEST CONDITIONS t(SVSR) td(SVSon) tsettle V(SVSstart) dVCC/dt > 30 V/ms (see Figure 13) dVCC/dt ≤ 30 V/ms SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V VLD ≠ 0‡ VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13) Vhys(B_IT–) VCC/dt ≤ 3 V/s (see Figure 13) VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied on A7 V(SVS_IT–) VCC/dt ≤ 3 V/s (see Figure 13) VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied on A7 ICC(SVS) (see Note 1) VLD ≠ 0, VCC = 2.2 V/3 V † The recommended operating voltage range is limited to 3.6 V. VLD = 1 VLD = 2 .. 14 MIN NOM MAX 5 150 2000 20 150 12 1.55 1.7 70 120 155 V(SVS_IT–) x 0.004 V(SVS_IT–) x 0.008 UNIT µs µs µs µs V mV VLD = 15 4.4 10.4 mV VLD = 1 VLD = 2 VLD = 3 VLD = 4 VLD = 5 VLD = 6 VLD = 7 VLD = 8 VLD = 9 VLD = 10 VLD = 11 VLD = 12 VLD = 13 VLD = 14 1.8 1.9 2.05 1.94 2.1 2.25 2.05 2.2 2.37 2.14 2.3 2.48 2.24 2.4 2.6 2.33 2.5 2.71 2.46 2.65 2.86 2.58 2.8 3 V 2.69 2.9 3.13 2.83 3.05 3.29 2.94 3.2 3.42 3.11 3.35 3.61† 3.24 3.5 3.76† 3.43 3.7† 3.99† VLD = 15 1.1 1.2 1.3 10 15 µA • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 35 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 ‡ tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data. VCC V(SVS_IT–) V(SVSstart) V(B_IT–) VCC(start) Brownout 1 Vhys(SVS_IT–) Vhys(B_IT–) Brownout Region Software Sets VLD>0: SVS is Active BrownOut Region 0 SVSOut 1 td(BOR) SVS Circuit is Active From VLD > to VCC < V(B_IT–) td(BOR) 0 Set POR 1 0 td(SVSon) undefined td(SVSR) Figure 13. SVS Reset (SVSR) vs Supply Voltage 36 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER VCC 3V SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 t pw 2 Rectangular Drop 1.5 Triangular Drop VCC(min)– V 1 0.5 0 1 10 100 tpw – Pulse Width – µs VCC 3V 1000 1 ns t pw VCC(min) 1 ns tf = tr tf tr t – Pulse Width – µs Figure 14. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 37 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) DCO PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f(DCOCLK) f(DCO2) f(DCO27) f(DCO2) f(DCO27) f(DCO2) f(DCO27) f(DCO2) f(DCO27) f(DCO2) f(DCO27) S N(DCO)=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2, DCOPLUS= 0 VCC = 2.2 V/3 V 1 MHz FN_8=FN_4=FN_3=FN_2=0 , DCO+ = 1 VCC = 2.2 V VCC = 3 V 0.3 0.65 1.25 MHz 0.3 0.7 1.3 FN_8=FN_4=FN_3=FN_2=0, DCO+ = 1, (see Note 1) VCC = 2.2 V VCC = 3 V 2.5 5.6 10.5 MHz 2.7 6.1 11.3 FN_8=FN_4=FN_3=0, FN_2=1; DCO+ = 1 VCC = 2.2 V VCC = 3 V 0.7 1.3 2.3 MHz 0.8 1.5 2.5 FN_8=FN_4=FN_3=0, FN_2=1; DCO+ = 1, (see Note 1) VCC = 2.2 V VCC = 3 V 5.7 10.8 6.5 12.1 18 MHz 20 FN_8=FN_4=0, FN_3= 1, FN_2=x; DCO+ = 1 VCC = 2.2 V VCC = 3 V 1.2 2 3 MHz 1.3 2.2 3.5 FN_8=FN_4=0, FN_3= 1, FN_2=x;, DCO+ = 1, (see Note 1) VCC = 2.2 V VCC = 3 V 9 15.5 25 MHz 10.3 17.9 28.5 FN_8=0, FN_4= 1, FN_3= FN_2=x; DCO+ = 1 VCC = 2.2 V VCC = 3 V 1.8 2.8 4.2 MHz 2.1 3.4 5.2 FN_8=0, FN_4=1, FN_3= FN_2=x; DCO+ = 1, (see Note 1) VCC = 2.2 V VCC = 3 V 13.5 21.5 16 26.6 33 MHz 41 FN_8=1, FN_4=FN_3=FN_2=x; DCO+ = 1 VCC = 2.2 V VCC = 3 V 2.8 4.2 6.2 MHz 4.2 6.3 9.2 FN_8=1,FN_4=FN_3=FN_2=x,DCO+ = 1, (see Note 1) VCC = 2.2 V VCC = 3 V 21 32 46 MHz 30 46 70 f(NDCO)+1 = f(NDCO) 2 < TAP ≤ 20 1.06 1.13 TAP > 20 1.1 1.17 Dt Temperature drift, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0 D = 2, DCO+ = 0, (see Note 2) DV NOTES: Drift with VCC variation, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0 D = 2, DCO+ = 0 (see Note 2) 1. Do not exceed the maximum system frequency. 2. This parameter not production tested. VCC = 2.2 V VCC = 3 V –0.2 –0.3 –0.4 –0.2 –0.3 –0.4 %/_C 0 5 15 %/V f(DCO) f(DCO3V) f(DCO) f(DCO20 C) 1.0 1.0 0 1.8 2.4 3.0 3.6 VCC – V –40 –20 0 20 40 60 Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature 85 TA – °C 38 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 f(DCO) Legend Tolerance at Tap 27 DCO Frequency Adjusted by Bits 29 to 2 5 in SCFI1 {N (DCO)} Tolerance at Tap 2 Overlapping DCO Ranges: uninterrupted frequency range FN_2=0 FN_3=0 FN_4=0 FN_8=0 FN_2=1 FN_3=0 FN_4=0 FN_8=0 FN_2=x FN_3=1 FN_4=0 FN_8=0 FN_2=x FN_3=x FN_4=1 FN_8=0 FN_2=x FN_3=x FN_4=x FN_8=1 Figure 16. Five Overlapping DCO Ranges Controlled by FN_x Bits electrical characteristics over recommended operating free-air temperature (unless otherwise noted) crystal oscillator, LFXT1 oscillator (see Notes 1 and 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OSCCAP = 0, VCC = 2.2 V / 3 V 0 C(XIN) Integrated input capacitance OSCCAP = 1, VCC = 2.2 V / 3 V OSCCAP = 2, VCC = 2.2 V / 3 V 10 pF 14 OSCCAP = 3, VCC = 2.2 V / 3 V 18 OSCCAP = 0, VCC = 2.2 V / 3 V 0 C(XOUT) Integrated output capacitance OSCCAP = 1, VCC = 2.2 V / 3 V OSCCAP = 2, VCC = 2.2 V / 3 V 10 pF 14 OSCCAP = 3, VCC = 2.2 V / 3 V 18 NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is (X(CIN) x X(COUT)) / (X(CIN) + X(COUT)). This is independent of XST_FLL. 2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed. – Keep as short of a trace as possible between the F43x/44x and the crystal. – Design a good ground plane around the oscillator pins. – Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. – Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. – Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. – If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. – Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 39 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, XT2 oscillator (see Note 1) PARAMETER TEST CONDITIONS MIN XCIN Integrated input capacitance VCC = 2.2 V/3 V XCOUT Integrated output capacitance VCC = 2.2 V/3 V XINL XINH Input levels at XIN, XOUT VCC = 2.2 V/3 V VSS 0.8 × VCC NOTE 1: The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. NOM MAX 2 2 0.2 × VCC VCC UNIT pF pF V V USART0, USART1 (see Note 1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT t(τ) USART0/1: deglitch time VCC = 2.2 V VCC = 3 V 200 430 800 ns 150 280 500 NOTE 1: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t(t) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(t). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0/1 line. 40 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 12-bit ADC, power supply and input range conditions (see Note 1) AVCC PARAMETER Analog supply voltage TEST CONDITIONS AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V MIN NOM 2.2 MAX UNIT 3.6 V VCC(min) VO(REF+) IL(VREF+) IL(VREF+)† 0 mA ≤ I(Load) ≤ 0.5 mA Positive built-in reference voltage output Load current out of VREF+ terminal Load-current regulation VREF+ terminal 0.5 mA ≤ I(Load) ≤ 1.5 mA REF2_5 V = 1 for 2.5-V built-in reference REF2_5 V = 0 for 1.5-V built-in reference I(VREF+) ≤ I(VREF+_max) I(VREF+) = 500 µA ±100 µA Analog input voltage ~0.75 V; REF2_5 V = 0 I(VREF+) = 500 µA ± 100 µA Analog input voltage ~1.25 V; REF2_5 V = 1 VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 3 V VREF+ VREF+ 2.4 2.5 1.44 1.5 0.01 VREF+ + 150 mV VREF+ + 350 mV 2.6 V 1.56 –0.5 mA –1 ±2 LSB ±2 ±2 LSB IL(VREF+)‡ Vref(VREF+) Load current regulation VREF+ terminal I(VREF+) =100 µA → 900 µA, VCC = 3 V, ax ~0.5 x VREF+ Error of conversion result ≤ 1 LSB C(VREF+) = 5 µF Positive external reference voltage VeREF+ > VREF–/VeREF– (see Note 2) 1.4 input 20 ns V(AVCC) V Negative external Vref(VREF– /VeREF–) reference voltage VeREF+ > VREF–/VeREF– (see Note 3) 0 1.2 V input † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The leakage current is defined in the leakage current table with P6.x/Ax parameter. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 41 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 12-bit ADC, power supply and input range conditions (continued) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT (VeREF+ – VREF–/VeREF–) Differential external reference voltage input VeREF+ > VREF–/VeREF– (see Note 1) 1.4 V(AVCC) V VI(P6.x/Ax) IDD(ADC12) IDD(REF+) Analog input voltage range (see Note 2) Operating supply current into AVCC terminal (see Note 3) Operating supply current into AVCC terminal (see Note 4) Operating supply current (see Note 4) All P6.0/A0 to P6.7/A7/SVSin terminals. Analog inputs selected in ADC12MCTLx register and P6Sel.x=1 0 ≤ x ≤ 7; V(AVSS) ≤ VI(P6.x/Ax) ≤ V(AVCC) f(ADC12CLK) = 5 MHz ADC12ON = 1, REFON = 0 VCC = 2.2 V SHT0=0, SHT1=0, ADC12DIV=0 VCC = 3 V f(ADC12CLK) = 5 MHz ADC12ON = 0, REFON = 1, 2_5V = 1 VCC = 3 V f(ADC12CLK) = 5 MHz ADC12ON = 0, REFON = 1, 2_5V = 0 VCC = 2.2 V VCC = 3 V 0 V(AVCC) V 0.65 1.3 mA 0.8 1.6 0.5 0.8 mA 0.5 0.8 0.5 0.8 NOTES: 1. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. 2. The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results 3. The internal reference supply current is not included in current consumption parameter IDD(ADC12). 4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion. 12-bit ADC, built-in reference (see Note 1) PARAMETER IDD(VeREF+) Static input current (see Note 2) IDD(VREF–/VeREF–) Static input current (see Note 2) C(VREF+) Capacitance at pin VREF+ (see Note 3) Ci‡ Input capacitance (see Note 4) TEST CONDITIONS 0 V ≤ VeREF+ ≤ V(AVCC) VCC = 2.2 V/3 V MIN NOM MAX UNIT ±1 µA 0 V ≤ VeREF– ≤ V(AVCC) VCC = 2.2 V/3 V REFON = 1, 0 mA ≤ I(VREF+) ≤ I(VREF_max) Only one terminal can be selected at one time, P6.x/Ax VCC = 2.2 V/3 V VCC = 2.2 V 5 10 ±1 µA µF 40 pF Zi‡ Input MUX ON resistance (see Note 4) 0 V ≤ V(Ax) ≤ V(AVCC) VCC = 3 V 2000 Ω T(REF+)† Temperature coefficient of built-in reference I(VREF+) is a constant in the range of 0 mA ≤ I(VREF+) ≤ 1 mA VCC = 2.2 V/3 V ±100 ppm/°C † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The voltage source on VeREF+ and VREF–/VeREF– needs to have low-dynamic impedance for 12-bit accuracy to allow the charge to settle for this accuracy (See Figure 9 and Figure 10). 2. The external reference is used during conversion to charge and discharge the capacitance array. The dynamic impedance should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 3. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. 4. The input capacitance is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF–/VeREF– and AVSS: 10-µF tantalum and 100-nF ceramic. 42 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 timing requirements 12-bit ADC, timing parameters PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ts(REF_ON)† Settle time of internal reference voltage (see Figure 17 and Note 1) I(VREF+) = 0.5 mA, C(VREF+) = 10 µF, VREF+ = 1.5 V, V(AVCC) = 2.2 V 17 ms f(ADC12CLK) Error of conversion result ≤ ±2 LSB 2.2V/3V 5 MHz f(ADC12OSC) ADC12DIV=0 [f(ADC12CLK) = f(ADC12OSC)] VCC = 2.2 V/3 V 3.7 6.3 MHz AVCC(min)≤ V(AVCC)≤AVCC(max), C(VREF+) ≥ 5 µF, internal oscillator, fOSC = 3.7 MHz to 6.3 MHz VCC = 2.2 V/3 V 2.06 3.51 µs tc Conversion time AVCC(min) ≤ V(AVCC) ≤ AVCC(max), External fADC12CLK from ACLK or MCLK or SMCLK: ADC12SSEL ≠ 0 13×ADC12DIV× 1/fADC12CLK µs ts(ADC12ON)‡ Settle time of the ADC AVCC(min) ≤ V(AVCC) ≤ AVCC(max) (see Note 2) 100 ns V(AVCC_min) < V(AVCC) < V(AVCC_max) VCC = 3 V 1220 t(Sample)‡ Sampling time Ri(source) = 400 Ω, Zi = 1000 Ω, Ci = 30 pF ns τ = [Ri(source) x+ Zi] x Ci, VCC = 2.2 V 1400 (see Note 3) † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The condition is that the error in a conversion started after ts(REF_ON) is less than ±0.5 LSB. The settling time depends on the external capacitive load. 2. The condition is that the error in a conversion started after ts(ADC12ON) is less than ±0.5 LSB. The reference and input signal are already settled. 3. Ten Tau (τ) are needed to get an error of less than ±0.5 LSB. t(Sample) = 10 x (Ri + Zi) x Ci + 800 ns C(VREF+) 100 µF 10 µF t(REF_ON) ~ 0.66 x C(VREF+) [ms] With C(VREF+) in µF 1 µF 0 1 ms 10 ms 100 ms t(REF_ON) Figure 17. Typical Settling Time of Internal Reference t(REF_ON) vs External Capacitor on VREF+ • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 43 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit ADC, linearity parameters, VCC = 2.2 V/3 V PARAMETER TEST CONDITIONS E(I) Integral linearity error ED Differential linearity error 1.4 V ≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V 1.6 V < (VeREF+ – VREF–/VeREF–) min ≤ [V(AVCC)] (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic) EO Offset error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), internal impedance of source Ri < 100 Ω, C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic) EG Gain error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic) E(T) Total unadjusted error (VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–), C(VREF+) = 10 µF (tantalum) and 100 nF (ceramic) MIN NOM MAX ±2 ±1.7 UNIT LSB ±1 LSB ±2 ±4 LSB ±1.1 ±2 LSB ±2 ±5 LSB From Power + Supply – 10 µ F 100 nF DVCC1/DVCC2 DVSS1/DVSS2 + – Apply External Reference (VeREF+) or Use Internal Reference (VREF+) 10 µ F 100 nF + – 10 µ F Apply External + Reference – 100 nF AVCC MSP430F43x AVSS MSP430F44x VREF+ or VeREF+ VREF–/VeREF– 10 µ F 100 nF Figure 18. Supply Voltage and Reference Voltage Design VREF–/VeREF– External Supply 44 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 From Power + Supply – 10 µ F 100 nF DVCC1/DVCC2 DVSS1/DVSS2 Apply External Reference (VeREF+) or Use Internal Reference (VREF+) + – 10 µ F 100 nF + – AVCC MSP430F43x AVSS MSP430F44x VREF+ or VeREF+ Reference Is Internally Switched to AVSS 10 µ F 100 nF VREF–/VeREF– Figure 19. Supply Voltage and Reference Voltage Design VREF–/VeREF– = AVSS, Internally Connected electrical characteristics over recommended operating free-air temperature (unless otherwise noted) 12-bit ADC, temperature sensor and built-in Vmid PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Operating supply current ICC(SENSOR) into AVCC terminal (see Note 1) V(REFON) = 0, INCH = 0Ah, ADC12ON = NA, TA = 25_C VCC = 2.2 V VCC = 3 V 40 120 µA 60 160 V(SENSOR)† TC(SENSOR)† ts(SENSOR)† Sample time required if channel 10 is selected (see Note 2) ADC12ON = 1, INCH = 0Ah, TA = 0°C ADC12ON = 1, INCH = 0Ah VCC = 2.2 V/3 V VCC = 2.2 V/3 V ADC12ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB VCC = 2.2 V/3 V 986 986±5% mV 3.55 3.55±3% mV/°C 30 µs V(MID) ADC12ON = 1, INCH = 0Bh, AVCC divider at channel 11 V(MID) is ~0.5 x V(AVCC) VCC = 2.2 V VCC = 3 V 1.1 1.1±0.04 V 1.5 1.5±0.04 t(ON_VMID) On-time if channel 11 is selected (see Note 3) ADC12ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB VCC = 2.2 V/3 V NA ns † Not production tested, limits characterized ‡ Not production tested, limits verified by design NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and V(REFON) = 1), or (ADC12ON=1 AND INCH=0Ah and sample signal is high). Therefore, it includes the constant current through the sensor and the reference. 2. The typical equivalent impedance of the sensor is 51 kΩ. The sample time needed is the sensor-on time t(SENSOR_ON) 3. The on-time t(ON_VMID) is identical to sampling time t(Sample); no additional on time is needed. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 45 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 JTAG, program memory and fuse PARAMETER TEST CONDITIONS MIN NOM MAX UNIT f(TCK) JTAG/Test (see Note 4) VCC(FB) V(FB) I(FB) JTAG/fuse (see Note 2) TCK frequency Pull-up resistors on TMS, TCK, TDI (see Note 1) Supply voltage during fuse blow condition, TA = 25°C Fuse-blow voltage, F versions (see Note 3) Supply current on TDI with fuse blown Time to blow the fuse VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V DC 5 MHz DC 10 25 60 90 kΩ 2.5 V 6 7 100 mA 1 ms I(DD-PGM) F-versions only Current from DVCC when programming is active VCC = 2.7 V/3.6 V 3 I(DD-Erase) (see Note 4) Current from DVCC when erase is active VCC = 2.7 V/3.6 V 3 t(retention) Write/erase cycles F-versions only Data retention TJ = 25°C 104 105 100 5 mA 5 mA cycles years NOTES: 1. TMS, TDI, and TCK pull-up resistors are implemented in all F versions. 2. Once the fuse is blown, no further access to the MSP430 JTAG/test feature is possible. The JTAG block is switched to bypass mode. 3. The supply voltage to blow the fuse is applied to the TDI pin. 4. f(TCK) may be restricted to meet the timing requirements of the module selected. Duration of the program/erase cycle is determined by f(FTG) applied to the flash timing controller. It can be calculated as follows: t(word write) = 35 1/f(FTG) t(block write, byte 0) = 30 1/f(FTG) t(block write, byte 1 – 63) = 20 1/f(FTG) t(block write, sequence end) = 6 1/f (FTG) t(mass erase) = 5297 1/f(FTG) t(segment erase) = 4819 1/f(FTG) 46 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 input/output schematic Port P1, P1.0 to P1.5, input/output with Schmitt-trigger MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 Pad Logic CAPD.x P1SEL.x P1DIR.x Direction Control From Module P1OUT.x Module X OUT P1IN.x Module X IN 0 1 0 1 EN D 0: Input 1: Output Bus Keeper P1.x P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOutH/SVSOut P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1IRQ.x P1IE.x EN Q P1IFG.x Set Interrupt Edge Select Note: 0 < x< 5 P1IES.x P1SEL.x Note: Port function is active if CAPD.x = 0 PnSel.x P1Sel.0 P1Sel.1 P1Sel.2 PnDIR.x P1DIR.0 P1DIR.1 P1DIR.2 Direction Control PnOUT.x From Module P1DIR.0 P1OUT.0 Module X OUT Out0 sig. † P1DIR.1 P1DIR.2 P1OUT.1 P1OUT.2 MCLK † Out1 sig. PnIN.x P1IN.0 P1IN.1 P1IN.2 Module X IN PnIE.x CCI0A † † CCI0B † CCI1A P1IE.0 P1IE.1 P1IE.2 P1Sel.3 P1DIR.3 P1DIR.3 P1OUT.3 SVSOut P1IN.3 TBOutH ‡ P1IE.3 P1Sel.4 P1DIR.4 P1Sel.5 † Timer_A ‡ Timer_B P1DIR.5 P1DIR.4 P1DIR.5 P1OUT.4 P1OUT.5 SMCLK ACLK P1IN.4 P1IN.5 TBCLK ‡ † TACLK P1IE.4 P1IE.5 PnIFG.x PnIES.x P1IFG.0 P1IES.0 P1IFG.1 P1IES.1 P1IFG.2 P1IES.2 P1IFG.3 P1IES.3 P1IFG.4 P1IES.4 P1IFG.5 P1IES.5 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 47 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 input/output schematic (continued) Port P1, P1.6, P1.7, input/output with Schmitt-trigger Pad Logic CAPD.6 P1SEL.6 P1DIR.6 P1DIR.6 P1OUT.6 DVSS P1IN.6 Note: Port function is active if CAPD.6 = 0 0 1 0 1 EN unused D P1IRQ.07 P1IE.7 EN Q P1IFG.7 Set Interrupt Edge Select 0: Input 1: Output Bus Keeper P1IES.x P1SEL.x CCI1B to Timer_Ax Comparator_A AVcc P2CA CAREF CAEX CAF + – 2 CAREF Reference Block Pad Logic CAPD.7 P1SEL.7 P1DIR.7 P1DIR.7 P1OUT.7 DVSS P1IN.7 Note: Port function is active if CAPD.7 = 0 0 1 0 1 EN unused D 0: input 1: output Bus keeper P1IRQ.07 P1IE.7 EN Q P1IFG.7 Set Interrupt Edge Select P1IES.7 P1SEL.7 P1.6/ CA0 CA0 CA1 P1.7/ CA1 48 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER input/output schematic (continued) port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 DVSS DVSS Pad Logic P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT P2IN.x Module X IN 0 1 0 1 EN D 0: Input 1: Output Bus Keeper P2.0/TA2 P2.4/UTXD0 P2.5/URXD0 P2IRQ.x P2IE.x P2IFG.x EN Q Set Interrupt Edge Select P2IES.x P2SEL.x Note: x {0,4,5} PnSel.x PnDIR.x P2Sel.0 P2DIR.0 P2Sel.4 P2DIR.4 Dir. Control from module PnOUT.x P2DIR.0 P2OUT.0 DVCC P2OUT.4 Module X OUT Out2 sig. † UTXD0‡ P2Sel.5 †Timer_A ‡USART0 P2DIR.5 DVSS P2OUT.5 DVSS PnIN.x Module X IN PnIE.x P2IN.0 CCI2A † P2IE.0 P2IN.4 P2IN.5 unused URXD0 ‡ P2IE.4 P2IE.5 PnIFG.x PnIES.x P2IFG.0 P2IFG.4 P2IFG.5 P2IES.0 P2IES.4 P2IES.5 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 49 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 input/output schematic (continued) port P2, P2.1 to P2.3, input/output with Schmitt-trigger DVSS DVSS Module IN of pin P1.3/TBOutH/SVSOut P1DIR.3 P1SEL.3 Pad Logic P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT P2IN.x Module X IN 0 1 0 1 EN D 0: Input 1: Output Bus Keeper P2.1/TB0 P2.2/TB1 P2.3/TB2 P2IRQ.x P2IE.x P2IFG.x EN Q Set Interrupt Edge Select P2IES.x P2SEL.x Note: 1 < x < 3 PnSel.x PnDIR.x Dir. Control PnOUT.x from module P2Sel.1 P2DIR.1 P2DIR.1 P2OUT.1 P2Sel.2 P2DIR.2 P2DIR.2 P2OUT.2 P2Sel.3 †Timer_B P2DIR.3 P2DIR.3 P2OUT.3 Module X OUT Out0 sig. † Out1 sig. † Out2 sig. † PnIN.x P2IN.1 P2IN.2 P2IN.3 Module X IN PnIE.x CCI0A † CCI0B CCI1A † CCI1B CCI2A † CCI2B P2IE.1 P2IE.2 P2IE.3 PnIFG.x PnIES.x P2IFG.1 P2IFG.2 P2IFG.3 P2IES.1 P2IES.2 P2IES.3 50 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 input/output schematic (continued) port P2, P2.6 to P2.7, input/output with Schmitt-trigger Port/LCD‡ Segment xx‡ 0: Port active 1: Segment xx function active MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 Pad Logic P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT P2IN.x Module X IN 0 1 0 1 EN D 0: Input 1: Output Bus Keeper P2.6/CAOUT/S19‡ P2.7/ADC12CLK/S18‡ ‡Segment function only available with MSP430x43xIPN P2IRQ.x P2IE.x P2IFG.x EN Q Set Interrupt Edge Select Note: 6 < x < 7 P2IES.x P2SEL.x PnSel.x P2Sel.6 P2Sel.7 PnDIR.x P2DIR.6 Dir. Control PnOUT.x from module P2DIR.6 P2OUT.6 Module X OUT CAOUT † PnIN.x Module X IN P2IN.6 unused P2DIR.7 P2DIR.7 P2OUT.7 ADC12CLK§ P2IN.7 unused PnIE.x P2IE.6 P2IE.7 † Comparator_A ‡Port/LCD signal is 1 only with MSP430xIPN and LCDM ≥40h. § ADC12 PnIFG.x PnIES.x Port/LCD‡ P2IFG.6 P2IFG.7 P2IES.6 P2IES.7 0: LCDM<40h ‡ 0: LCDM<40h ‡ • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 51 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 input/output schematic (continued) port P3, P3.0 to P3.3, input/output with Schmitt-trigger LCDM.5 LCDM.6 LCDM.7 Segment xx MSP430x43xIPN (80-Pin) Only 0: Port active 1: Segment xx function active x43xIPZ and x44xIPZ have not segment Function on Port P3: Both lines are low. Pad Logic P3SEL.x P3DIR.x Direction Control From Module P3OUT.x Module X OUT P3IN.x Module X IN Note: 0 < x < 3 0 0: Input 1: Output 1 0 1 Bus Keeper EN D PnSel.x P3Sel.0 P3Sel.1 P3Sel.2 P3Sel.3 PnDIR.x P3DIR.0 P3DIR.1 P3DIR.2 P3DIR.3 Direction Control PnOUT.x From Module DVSS P3OUT.0 DCM_SIMO0 P3OUT.1 DCM_SOMI0 P3OUT.2 DCM_UCLK0 P3OUT.3 Module X OUT PnIN.x DVSS P3IN.0 SIMO0(out) P3IN.1 SOMIO(out) P3IN.2 UCLK0(out) P3IN.3 Module X IN STE0(in) SIMO0(in) SOMI0(in) UCLK0(in) P3.0/STEO/S31† P3.1/SIMO0/S30† P3.2/SOMI0/S29† P3.3/UCLK0/S28† † S24 to S31 shared with port function only at MSP430x43xIPN (80-pin QFP) SYNC MM STC STE Direction Control for SIMO0 and UCLK0 DCM_SIMO0 DCM_UCLK0 SYNC MM STC STE Direction Control for SOMI0 DCM_SOMI0 52 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER port P3, P3.4 to P3.7, input/output with Schmitt-trigger SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 LCDM.7† or DVSS‡ Segmentxx† or DVSS‡ TBoutHiZ# or DVSS§ P3SEL.x P3DIR.x Direction Control From Module P3OUT.x Module XOUT P3IN.x Module X IN 0: Port active 1: Segment xx function active 0 1 0 1 EN D Pad Logic 0: Input 1: Output Bus Keeper ’x43xIPN 80-Pin ’x43xIPZ 100-Pin ’x44x P3.4/S27 P3.5/S26 P3.6/S25 P3.7/S24 P3.4 P3.5 P3.6 P3.7 P3.4/TB3 P3.5/TB4 P3.6/TB5 P3.7/TB6 Note: 4 < x < 7 Module IN of pin P1.3/TBOutH/SVSOut P1DIR.3 P1SEL.3 P3DIR.x P3SEL.x TBoutHiZ PnSel.x P3Sel.4 P3Sel.5 P3Sel.6 P3Sel.7 Dir. Control Module X PnDIR.x from module PnOUT.x OUT P3DIR.4 P3DIR.5 P3DIR.6 P3DIR.7 P3DIR.4 P3DIR.5 P3DIR.6 P3DIR.7 P3OUT.4 P3OUT.5 P3OUT.6 P3OUT.7 DVSS § OUT3 # DVSS § OUT4 # DVSS § OUT5 # DVSS § OUT6 # PnIN.x Module X IN P3IN.4 P3IN.5 P3IN.6 P3IN.7 unused § CCI3A/B# unused § CCI4A/B# unused § CCI5A/B# unused § CCI6A/B# † MSP430x43xIPN ‡ MSP430x43xIPZ, MSP430x44xIPZ § MSP430x43x # MSP430x44x • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 53 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 input/output schematic (continued) port P4, P4.0 to P4.7, input/output with Schmitt-trigger Port/LCD§ Segment xx 0: Port active 1: Segment xx function active Pad Logic P4SEL.x P4DIR.x Direction Control From Module P4OUT.x Module X OUT P4IN.x Module X IN Note: 0 < x < 7 0 0: Input 1: Output 1 0 1 Bus Keeper x43xIPN x43xIPZ 80-Pin 100-Pin QFP: QFP: x44x P4.7/S2 P4.7/S34 P4.7/S34 EN P4.6/S3 P4.6/S35 P4.6/S35 P4.5/S4 P4.5/S36 P4.5/UCLK1/S36 D P4.3/S6 P4.3/S37 P4.4/SMO1/S37 P4.4/S5 P4.4/S38 P4.3/SIMO1/S38 P4.2/S7 P4.2/S39 P4.2/STE1/S39 P4.1/S8 P4.0 P4.1/URXD1 P4.0/S9 P4.1 P4.0/UTXD1 PnSel.x P4Sel.0 P4Sel.1 P4Sel.2 P4Sel.3 P4Sel.4 P4Sel.5 Direction PnDIR.x Control From Module PnOUT.x Module X OUT P4DIR.0 P4DIR.1 P4DIR.0† DVCC‡ P4DIR.1† DVSS‡ P4OUT.0 UDTVXSDS1†‡ P4OUT.1 DVSS P4DIR.2 P4DIR.2† DVSS‡ P4OUT.2 DVSS P4DIR.3 P4DIR.4 P4DIR.5 P4DIR3.† DCM_SIMO1‡ P4DIR4.† DCM_SOMI1‡ P4DIR5.† DCM_UCLK1‡ P4OUT.3 P4OUT.4 P4OUT.5 SIMDOV1S(So†ut)‡ SODMVI1S(So†ut)‡ UCDLKV1S(So†ut)‡ PnIN.x Module X IN P4IN.0 unused P4IN.1 P4IN.2 P4IN.3 P4IN.4 P4IN.5 unused† URXD1‡ unused† STE1(in)‡ unused† SIMO1(in)‡ unused SOMI1(in)‡ unused† UCLK1(in)‡ P4Sel.6 P4DIR.4 P4DIR.6 P4OUT.6 DVSS P4IN.6 unused P4Sel.7 P4DIR.5 P4DIR.7 P4OUT.7 DVSS P4IN.7 unused † Signal at MSP430x43x ‡ Signal at MSP430x44x § DEVICE x43xIPN 80-pin QFP x43xIPZ 100-pin QFP x44xIPZ 100-pin QFP PORT BITS P4.0 . . .P4.7 P4.2 . . .P4.5 P4.6 . . .P4.7 PORT FUNCTION LCDM < 020h LCDM < 0E0h LCDM < 0C0h LCD SEG. FUNCTION LCDM ≥ 020h LCDM ≥ 0E0h LCDM ≥ 0C0h 54 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 input/output schematic (continued) MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 SYNC MM STC STE Direction Control for SIMO1 and UCLK1 DCM_SIMO1 DCM_UCLK1 port P5, P5.0 to P5.1, input/output with Schmitt-trigger Port/LCD Segment 0: Port active 1: Segment function active SYNC MM STC STE Direction Control for SOMI1 DCM_SOMI1 Segment Pad Logic P5SEL.x P5DIR.x Direction Control From Module P5OUT.x Module X OUT P5IN.x Module X IN 0 1 0 1 EN D 0: Input 1: Output Port Pad Logic Bus Keeper P5.0/S1 P5.1/S0 Note: 0 < x < 1 PnSel.x PnDIR.x P5Sel.0 P5DIR.0 P5Sel.1 P5DIR.1 Dir. Control from module PnOUT.x Module X OUT P5DIR.0 P5DIR.1 P5OUT.0 P5OUT.1 DVSS DVSS PnIN.x Module X IN P5IN.0 P5IN.1 unused unused Segment Port/LCD S1 0: LCDM<20h S0 0: LCDM<20h • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 55 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 input/output schematic (continued) port P5, P5.2 to P5.4, input/output with Schmitt-trigger Port/LCD LCD signal 0: Port active 1: LCD function active Pad Logic P5SEL.x P5DIR.x Direction Control From Module P5OUT.x Module X OUT P5IN.x Module X IN 0 1 0 1 EN D 0: Input 1: Output Bus Keeper P5.2/COM1 P5.3/COM2 P5.4/COM3 Note: 2 < x < 4 PnSel.x PnDIR.x Dir. Control from module PnOUT.x Module X OUT PnIN.x Module X IN LCD signal P5Sel.2 P5DIR.2 P5DIR.2 P5OUT.2 DVSS P5IN.2 unused COM1 P5Sel.3 P5DIR.3 P5DIR.3 P5OUT.3 DVSS P5IN.3 unused COM2 P5Sel.4 P5DIR.4 P5DIR.4 P5OUT.4 DVSS P5IN.4 unused COM3 Port/LCD P5SEL.2 P5SEL.3 P5SEL.4 56 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 input/output schematic (continued) port P5, P5.5 to P5.7, input/output with Schmitt-trigger Port/LCD LCD signal 0: Port active 1: LCD function active MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 Pad Logic P5SEL.x P5DIR.x Direction Control From Module P5OUT.x Module X OUT P5IN.x Module X IN 0 1 0 1 EN D 0: Input 1: Output Bus Keeper P5.5/R13 P5.6/R23 P5.7/R33 Note: 5 < x < 7 PnSel.x PnDIR.x Dir. Control from module PnOUT.x Module X OUT PnIN.x Module X IN LCD signal P5Sel.5 P5DIR.5 P5DIR.5 P5OUT.5 DVSS P5IN.5 unused R13 P5Sel.6 P5DIR.6 P5DIR.6 P5OUT.6 DVSS P5IN.6 unused R23 P5Sel.7 P5DIR.7 P5DIR.7 P5OUT.7 DVSS P5IN.7 unused R33 Port/LCD P5SEL.5 P5SEL.6 P5SEL.7 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 57 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 input/output schematic (continued) port P6, P6.0 to P6.6, input/output with Schmitt-trigger P6SEL.x P6DIR.x Direction Control From Module 0 0: Input 1 1: Output 0 P6OUT.x Module X OUT 1 Pad Logic P6IN.x EN Module X IN D Bus Keeper P6.0/A0 .. P6.6/A6 From ADC To ADC x: Bit Identifier, 0 to 6 for Port P6 NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 0→1 or 1←0. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 µA. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12. PnSel.x PnDIR.x Dir. Control From Module PnOUT.x P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 P6Sel.3 P6DIR.3 P6DIR.3 P6OUT.3 P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 P6Sel.6 P6DIR.6 P6DIR.6 P6OUT.6 NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module. Module X OUT DVSS DVSS DVSS DVSS DVSS DVSS DVSS PnIN.x P6IN.0 P6IN.1 P6IN.2 P6IN.3 P6IN.4 P6IN.5 P6IN.6 Module X IN unused unused unused unused unused unused unused 58 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 input/output schematic (continued) port P6, P6.7, input/output with Schmitt-trigger P6SEL.x VLP(SVS)=15 P6DIR.x Direction Control From Module 0 0: Input 1 1: Output 0 P6OUT.x Module X OUT 1 P6IN.x EN Module X IN D MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 Pad Logic P6.7/A7/SVSin Bus Keeper From ADC To ADC To Brownout/SVS Module x: Bit Identifier, 7 for Port P6 NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 0→1 or 1←0. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 µA. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12. PnSel.x PnDIR.x Dir. Control From Module PnOUT.x Module X OUT PnIN.x Module X IN P6Sel.7 P6DIR.7 P6DIR.7 P6OUT.7 DVSS P6IN.7 unused NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module. The signal at pin P6.7/A7/SVSin is also connected to the input multiplexer in the module brownout/supply voltage supervisor. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 59 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 input/output schematic (continued) JTAG pins TMS, TCK, TDI, TDO/TDI, input/output with Schmitt-trigger or output JTAG TDO Controlled by JTAG Controlled by JTAG TDI Controlled by JTAG TDO/TDI DVCC Test and Emulation Module TMS TCK Burn and Test Fuse TDI DVCC TMS DVCC TCK RST/NMI Tau ~ 50 ns D Brownout G U S TCK D G U S 60 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 JTAG fuse check mode MSP430 devices that have the fuse on the TDI terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF)) of 1 mA at 3 V can flow from the TDI pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 20). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination. Time TMS Goes Low After POR TMS I(TF) I(TDI) Figure 20. Fuse Check Mode Current MSP430x43x, MSP430x44x • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 61 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 PN (S-PQFP-G80) MECHANICAL DATA 0,50 60 0,27 0,17 41 0,08 M 61 40 PLASTIC QUAD FLATPACK 0,13 NOM 80 21 1 1,45 1,35 20 9,50 TYP 12,20 11,80 SQ 14,20 13,80 SQ 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 0,25 0,05 MIN 0,75 0,45 Seating Plane 0,08 Gage Plane 0°–ā7° 4040135/B 11/96 62 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 PZ (S-PQFP-G100) 0,50 75 76 MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002 MECHANICAL DATA PLASTIC QUAD FLATPACK 0,27 0,17 51 0,08 M 50 100 1 1,45 1,35 1,60 MAX 12,00 TYP 14,20 13,80 SQ 16,20 15,80 SQ 26 25 0,25 0,05 MIN 0,75 0,45 Seating Plane 0,08 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 0,13 NOM Gage Plane 0°–ā7° 4040149/B 11/96 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 63 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. 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