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Code Composer Studio 6.1 for MSP432 User's Guide

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      Code Composer Studio 6.1 for MSP432 User's Guide

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      User's Guide SLAU622 – March 2015 MSP432P401R Bootstrap Loader (BSL) User's Guide The MSP432™ BSL enables users to communicate with embedded memory in the MSP432 microcontroller during the prototyping phase, final production, and in service. Both the programmable memory (flash memory) and the data memory (RAM) can be modified as required. Do not confuse the bootstrap loader with programs found in some digital signal processors (DSPs) that automatically load program code (and data) from external memory to the internal memory of the DSP. These programs are often referred to as bootstrap loaders as well. Contents 1 Introduction ................................................................................................................... 2 2 Other Useful Documentation ............................................................................................... 2 3 BSL Architecture ............................................................................................................. 2 4 BSL Memories .............................................................................................................. 10 5 BSL Protocol ................................................................................................................ 16 6 Low-Power Mode Support ................................................................................................ 37 7 MSP432P4xx BSL Version Information ................................................................................. 37 List of Figures 1 BSL_PER_IF_SEL........................................................................................................... 3 2 BSL_PORTCNF_UART..................................................................................................... 4 3 BSL_PORTCNF_SPI........................................................................................................ 6 4 BSL_PORTCNF_I2C ........................................................................................................ 8 5 Standard RESET Sequence .............................................................................................. 16 6 BSL Entry Sequence at Configured GPIO Pin ......................................................................... 16 List of Tables 1 BSL Interface Selection Location in TLV ................................................................................. 2 2 BSL_PER_IF_SEL Field Descriptions .................................................................................... 3 3 BSL_PORTCNF_UART Field Descriptions .............................................................................. 5 4 BSL_PORTCNF_SPI Field Descriptions ................................................................................. 6 5 BSL_PORTCNF_I2C Field Descriptions.................................................................................. 8 6 BSL Code Space ........................................................................................................... 10 7 BSL Entry Function Parameters.......................................................................................... 11 8 Boot Override Flash Mailbox.............................................................................................. 12 9 BSL Data Packet ........................................................................................................... 16 10 BSL Core Commands ..................................................................................................... 17 11 RX Data Block .............................................................................................................. 18 12 RX Data Block 32 .......................................................................................................... 19 13 RX Password ............................................................................................................... 20 14 BSL Core Responses...................................................................................................... 33 15 BSL Core Messages ....................................................................................................... 33 16 UART BSL Command ..................................................................................................... 34 17 UART BSL Response...................................................................................................... 34 MSP432 is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 1 Copyright © 2015, Texas Instruments Incorporated Introduction www.ti.com 18 I2C BSL Command ......................................................................................................... 35 19 I2C BSL Response ......................................................................................................... 35 20 SPI BSL Command ........................................................................................................ 36 21 SPI BSL Response......................................................................................................... 36 22 Error Messages............................................................................................................. 37 23 MSP432P4xx BSL Information ........................................................................................... 37 1 Introduction To use the bootstrap loader, a user-selectable BSL entry sequence must be applied. An added sequence of commands initiates the desired function. A boot-loading session can be exited by continuing operation at a defined user program address or by the reset condition. If the device is secured by disabling JTAG, it is still possible to use the BSL. Access to the MSP432 memory through the BSL is protected against misuse by a user-defined password. To avoid accidental overwriting of the BSL code, the code is protected in the flash by default. To prevent unwanted source readout, any BSL command that directly or indirectly allows data reading is password protected. For more information about password-protected commands, refer to Section 5.3. To invoke the bootstrap loader, the BSL entry sequence must be applied to dedicated pins. After that, the BSL header character, followed by the data frame of a specific command, initiates the desired function. 2 Other Useful Documentation MSP432P4xx Technical Reference Manual (SLAU356) MSP430 BSL Wiki (http://processors.wiki.ti.com/index.php/BSL_(MSP430)) 3 BSL Architecture 3.1 Physical Interfaces The MSP432 BSL is implemented on UART, I2C, and SPI serial interfaces. In MSP432 devices, the BSL can automatically select the interface used to communicate with the device. The specific instance of the peripheral interfaces that is used depends on the selected device and can be found in the device-specific data sheet. This information is also part of the Device Descriptor Table (TLV) table, which is used by the BSL to select the correct instance of the interface. Table 1 shows the BSL interface information in the Device Descriptor Table (TLV). The BSL parses the TLV information and dynamically assesses the ports and interfaces to use. All interface setup calls from the BSL use the driver library in the ROM of the device. Table 1. BSL Interface Selection Location in TLV Information Module ID_BSL tag BSL peripheral interface instance (BSL_PER_IF_SEL) BSL port interface configuration UART (BSL_PORTCNF_UART) BSL port interface configuration SPI (BSL_PORTCNF_SPI) BSL port interface configuration I2C (BSL_PORTCNF_I2C) TLV Address Base address of BSL information in TLV (BA) BA + 0x4 BA + 0x8 BA + 0xC BA + 0x10 2 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com BSL Architecture 3.1.1 BSL_PER_IF_SEL TLV Entry BSL_PER_IF_SEL TLV entry helps the BSL to estimate the following: 1. Interface multiplexing status: If the corresponding interface is directly available on device pins or if it is multiplexed with GPIO. 2. Interface module: Module used to implement the interface (for example, eUSCIA or eUSCIB). 3. Instance of the module used by the BSL. The BSL_PER_IF_SEL field is split as shown in Figure 1 Figure 1. BSL_PER_IF_SEL 31 30 29 28 27 26 25 24 Reserved r r r r r r r r 23 22 21 20 19 18 17 16 I2C_MUX Reserved I2C_MOD I2C_INST r r r r r r r r 15 14 13 12 11 10 9 8 SPI_MUX Reserved SPI_MOD SPI_INST r r r r r r r r 7 6 5 4 3 2 1 0 UART_MUX Reserved UART_MOD UART_INST r r r r r r r r Bit 31-24 23 Field Reserved I2C_MUX 22 Reserved 21-20 I2C_MOD 19-16 I2C_INST 15 SPI_MUX 14 Reserved 13-12 SPI_MOD Table 2. BSL_PER_IF_SEL Field Descriptions Value FFh 1h 0h 1h 0h 1h-3h 0h 1h ... Fh 1h 0h 1h 0h 1h 2h-3h Description Reserved for future use. I2C interface mux status I2C is muxed with GPIO I2C pins are dedicated on device pin out Reserved for future use. Module used to implement I2C. eUSCIB Reserved for future IPs implementing I2C. Instance number of the IP specifically used to implement I2C. Use instance 0 of the IP used for implementing I2C (for example, eUSCIB0 when I2C_MOD = 00) Use instance 1 of the IP used for implementing I2C (for example, eUSCIB1 when I2C_MOD = 00) ... Use instance 15 of the IP used for implementing I2C (for example, eUSCIB15, when I2C_MOD = 00) SPI interface mux status SPI is muxed with GPIO SPI pins are dedicated on device pin out Reserved for future use. Module used to implement SPI. eUSCIA eUSCIB Reserved for future IPs implementing SPI. SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 3 Copyright © 2015, Texas Instruments Incorporated BSL Architecture Bit Field 11-8 SPI_INST 7 UART_MUX 6 Reserved 5-4 UART_MOD 3-0 UART_INST www.ti.com Table 2. BSL_PER_IF_SEL Field Descriptions (continued) Value 0h 1h ... Fh 1h 0h 1h 0h 1h-3h 0h 1h ... Fh Description Instance number of the IP specifically used to implement SPI. Use instance 0 of the IP used for implementing SPI (for example, eUSCIB0 when SPI_MOD = 01) Use instance 1 of the IP used for implementing SPI (for example, eUSCIB1 when SPI_MOD = 01) ... Use instance 15 of the IP used for implementing SPI (for example, eUSCIB15, when I2C_MOD = 01) UART interface mux status UART is muxed with GPIO UART pins are dedicated on device pin out Reserved for future use. Module used to implement UART. eUSCIA Reserved for future IPs implementing UART. Instance number of the IP specifically used to implement UART. Use instance 0 of the IP used for implementing UART (for example, eUSCIA0, when UART_MOD = 00) Use instance 1 of the IP used for implementing UART (for example, eUSCIA1, when UART_MOD = 00) ... Use instance 15 of the IP used for implementing UART (for example, eUSCIA15, when UART_MOD = 00) 3.1.2 BSL_PORTCNF_UART, BSL_PORTCNF_SPI, BSL_PORTCNF_I2C TLV Entries The BSL needs the GPIO configuration details for the module type, module instance, and mux status of the interface being used (obtained from BSL_PER_IF_SEL). The BSL_PORTCNF_UART, BSL_PORTCNF_SPI, and BSL_PORTCNF_I2C TLV entries provide the BSL with these details. If eUSCIA is the module used to implement UART, BSL_PORTCNF_UART field is split as shown in Figure 2. 31 r 23 r 15 r 7 BITPOS_TXD r 30 29 Reserved r r Figure 2. BSL_PORTCNF_UART 28 27 26 Reserved Reserved r r r 25 PSEL1_TXD r 24 PSEL1_RXD r 22 21 Reserved r r 20 19 18 17 16 Reserved Reserved PSEL0_TXD PSEL0_RXD r r r r r 14 13 Reserved r r 12 11 10 Reserved r r r 9 8 BITPOS_TXD r r 6 5 4 3 2 1 0 BITPOS_RXD UART_PORT r r r r r r r 4 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com Bit 31-26 25 Field Reserved PSEL1_TXD 24 PSEL1_RXD 23-18 Reserved 17 PSEL0_TXD 16 PSEL0_RXD 15-10 Reserved 9-7 BITPOS_TXD 6-4 BITPOS_RXD 3-0 UART_PORT Table 3. BSL_PORTCNF_UART Field Descriptions BSL Architecture Value 3Fh 0h 1h 0h 1h 3Fh 0h 1h 0h 1h 3Fh 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h ... Fh Description Reserved for future use. PSEL1 value for GPIO mux of UCAxTXD line PSEL1 bit for UCAxTXD should be programed with a value of 0. PSEL1 bit for UCAxTXD should be programed with a value of 1. PSEL1 value for GPIO mux of UCAxRXD line PSEL1 bit for UCAxRXD should be programed with a value of 0. PSEL1 bit for UCAxRXD should be programed with a value of 1. Reserved for future use. PSEL0 value for GPIO mux of UCAxTXD line PSEL0 bit for UCAxTXD should be programed with a value of 0. PSEL0 bit for UCAxTXD should be programed with a value of 1. PSEL0 value for GPIO mux of UCAxRXD line PSEL0 bit for UCAxRXD should be programed with a value of 0. PSEL0 bit for UCAxRXD should be programed with a value of 1. Reserved for future use. Bit position of UCAxTXD in the 8 bit port. For example, in MSP432P401x devices, UCA0TXD is muxed on P1.3. This field therefore reads as 0x3 to represent BIT3. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit position of UCAxRXD in the 8 bit port. For example, in MSP432P401x devices, UCA0RXD is muxed on P1.2. This field therefore reads as 0x2 to represent BIT2. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Port number on which the UART IP is muxed. Port 1 Port 2 ... Port 16 SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 5 Copyright © 2015, Texas Instruments Incorporated BSL Architecture www.ti.com If eUSCIA or eUSCIB is the module used to implement SPI, BSL_PORTCNF_SPI field is split as shown in Figure 3. 31 r 23 r 15 r 7 BITPOS_SIMO r 30 29 Reserved r r 22 21 Reserved r r 14 13 BITPOS_STE r r 6 5 BITPOS_SOMI r r Figure 3. BSL_PORTCNF_SPI 28 27 26 PSEL1_STE PSEL1_CLK r r r 25 PSEL1_SIMO r 24 PSEL1_SOMI r 20 19 18 17 16 PSEL0_STE PSEL0_CLK PSEL0_SIMO PSEL0_SOMI r r r r r 12 11 10 BITPOS_CLK r r r 9 8 BITPOS_SIMO r r 4 3 2 1 0 SPI_PORT r r r r r Bit 31-28 27 Field Reserved PSEL1_STE 26 PSEL1_CLK 25 PSEL1_SIMO 24 PSEL1_SOMI 23-20 Reserved 19 PSEL0_STE 18 PSEL0_CLK 17 PSEL0_SIMO 16 PSEL0_SOMI Table 4. BSL_PORTCNF_SPI Field Descriptions Value Fh 0h 1h 0h 1h 0h 1h 0h 1h Fh 0h 1h 0h 1h 0h 1h 0h 1h Description Reserved for future use. PSEL1 value for GPIO mux of UCxxSTE line PSEL1 bit for UCxxSTE should be programed with a value of 0. PSEL1 bit for UCxxSTE should be programed with a value of 1. PSEL1 value for GPIO mux of UCxxCLK line PSEL1 bit for UCxxCLK should be programed with a value of 0. PSEL1 bit for UCxxCLK should be programed with a value of 1. PSEL1 value for GPIO mux of UCxxSIMO line PSEL1 bit for UCxxSIMO should be programed with a value of 0. PSEL1 bit for UCxxSIMO should be programed with a value of 1. PSEL1 value for GPIO mux of UCxxSOMI line PSEL1 bit for UCxxSOMI should be programed with a value of 0. PSEL1 bit for UCxxSOMI should be programed with a value of 1. Reserved for future use. PSEL0 value for GPIO mux of UCxxSTE line PSEL0 bit for UCxxSTE should be programed with a value of 0. PSEL0 bit for UCxxSTE should be programed with a value of 1. PSEL0 value for GPIO mux of UCxxCLK line PSEL0 bit for UCxxCLK should be programed with a value of 0. PSEL0 bit for UCxxCLK should be programed with a value of 1. PSEL0 value for GPIO mux of UCxxSIMO line PSEL0 bit for UCxxSIMO should be programed with a value of 0. PSEL0 bit for UCxxSIMO should be programed with a value of 1. PSEL0 value for GPIO mux of UCxxSOMI line PSEL0 bit for UCxxSOMI should be programed with a value of 0. PSEL0 bit for UCxxSOMI should be programed with a value of 1. 6 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com BSL Architecture Bit Field 15-13 BITPOS_STE 12-10 BITPOS_CLK 9-7 BITPOS_SIMO 6-4 BITPOS_SOMI 3-0 SPI_PORT Table 4. BSL_PORTCNF_SPI Field Descriptions (continued) Value 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h ... Fh Description Bit position of UCxxSTE in the 8 bit port. For example, in MSP432P401x devices, UCA0STE is muxed on P1.0. This field therefore reads as 0x0 to represent BIT0. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit position of UCxxCLK in the 8 bit port. For example, in MSP432P401x devices, UCA0CLK is muxed on P1.1. This field therefore reads as 0x1 to represent BIT1. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit position of UCxxSIMO in the 8 bit port. For example, in MSP432P401x devices, UCA0SIMO is muxed on P1.3. This field therefore reads as 0x3 to represent BIT3. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit position of UCxxSOMI in the 8 bit port. For example, in MSP432P401x devices, UCA0SOMI is muxed on P1.2. This field therefore reads as 0x2 to represent BIT2. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Port number on which the SPI IP is muxed. Port 1 Port 2 ... Port 16 SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 7 Copyright © 2015, Texas Instruments Incorporated BSL Architecture www.ti.com If eUSCIB is the module used to implement I2C, BSL_PORTCNF_I2C field is split as shown in Figure 4. 31 r 23 r 15 r 7 BITPOS_SDA r 30 29 Reserved r r 22 21 Reserved r r 14 13 Reserved r r 6 5 BITPOS_SCL r r Figure 4. BSL_PORTCNF_I2C 28 27 26 Reserved Reserved r r r 25 PSEL1_SDA r 24 PSEL1_SCL r 20 19 18 17 16 Reserved Reserved PSEL0_SDA PSEL0_SCL r r r r r 12 11 10 Reserved r r r 9 8 BITPOS_SDA r r 4 3 2 1 0 I2C_PORT r r r r r Bit 31-26 25 Field Reserved PSEL1_SDA 24 PSEL1_SCL 23-18 Reserved 17 PSEL0_SDA 16 PSEL0_SCL 15-10 Reserved 9-7 BITPOS_SDA Table 5. BSL_PORTCNF_I2C Field Descriptions Value 3Fh 0h 1h 0h 1h 3Fh 0h 1h 0h 1h 3Fh 0h 1h 2h 3h 4h 5h 6h 7h Description Reserved for future use. PSEL1 value for GPIO mux of UCBxSDA line PSEL1 bit for UCBxSDA should be programed with a value of 0. PSEL1 bit for UCBxSDA should be programed with a value of 1. PSEL1 value for GPIO mux of UCBxSCL line PSEL1 bit for UCBxSCL should be programed with a value of 0. PSEL1 bit for UCBxSCL should be programed with a value of 1. Reserved for future use. PSEL0 value for GPIO mux of UCBxSDA line PSEL0 bit for UCBxSDA should be programed with a value of 0. PSEL0 bit for UCBxSDA should be programed with a value of 1. PSEL0 value for GPIO mux of UCBxSCL line PSEL0 bit for UCBxSCL should be programed with a value of 0. PSEL0 bit for UCBxSCL should be programed with a value of 1. Reserved for future use. Bit position of UCBxSDA in the 8 bit port. For example, in MSP432P401x devices, UCB3SDA is muxed on P10.2. This field therefore reads as 0x2 to represent BIT2. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 8 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com Bit Field 6-4 BITPOS_SCL 3-0 I2C_PORT BSL Architecture Table 5. BSL_PORTCNF_I2C Field Descriptions (continued) Value 0h 1h 2h 3h 4h 5h 6h 7h 0h 1h ... Fh Description Bit position of UCBxSCL in the 8 bit port. For example, in MSP432P401x devices, UCB3SCL is muxed on P10.3. This field therefore reads as 0x3 to represent BIT3. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Port number on which the I2C IP is muxed. Port 1 Port 2 ... Port 16 3.2 UART Protocol Definition The UART protocol used by the BSL is defined as: 1. Automatic baud-rate detection is run by the BSL slave to determine the initial baud rate of the host that is trying to connect into the BSL. The host can connect into the BSL with the initial baud rates of 9600, 19200, 38400, 57600, or 115200 baud. The sync character for this to be transmitted by the host is 0xFF. The BSL responds with an 0x00 in the BSL response cycle if the communication was successfully established with the BSL. 2. The protocol used for the communication is: Start bit, 8 data bits (LSB first), an even parity bit, 1 stop bit. 3. Handshake for commands is performed by an acknowledge character in the BSL core response format as specified in Table 17. 4. After characters have been received from the MSP432 BSL, there is no additional time delay required before sending new characters. 3.3 I2C Protocol Definition The I2C protocol used by the BSL is defined as: 1. Master must request data from BSL slave. 2. 7-bit addressing mode is used, and by default, the slave listens to address 0x48. (Can be changed using a boot override). 3. In addition to the I2C protocol based hardware ACK, handshake for commands is performed by an acknowledge character in the BSL core response format as specified in Table 19 4. After characters have been received from the MSP432 BSL, there is no additional time delay required before sending new characters. 5. Repeated starts are not required by the BSL but can be used. SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 9 Copyright © 2015, Texas Instruments Incorporated BSL Architecture www.ti.com 3.4 SPI Protocol Definition The SPI protocol used by the BSL is defined as: 1. 4-pin SPI slave mode is used. Data is changed on the first clock edge and captured on the following edge. (CKPH = 0). Clock is high when inactive (CKPL = 1). Slave transmit enable (STE) is active low. 2. Master must request data from the BSL slave by transmitting a dummy 0xFF byte. Dummy transmission is needed to drive the clock lines. 3. 8-bit serial data character format (MSB first transmit and receive) is used. 4. Handshake for commands is performed by an acknowledge character in the BSL core response format as specified in Table 21. 4 BSL Memories 4.1 BSL Memory Layout Table 6 shows the BSL code space. Space Code Data Table 6. BSL Code Space Flash Region Flash information memory: Bank 2 sectors 1 and 2 SRAM CTL Bank 0 Length (Bytes) 0x2000 0x800 Start Address 0x0020:2000 0x2000:0000 4.2 BSL Memory Considerations After initialization, the BSL uses RAM between the addresses 0x2000:0000 and 0x2000:07FF for data buffer and local variables. When invoking the BSL from a main application, the contents of RAM may be lost. 4.3 BSL Invocation The MSP432 BSL is invoked by any of the three following approaches. Any one of the conditions is a sufficient condition for BSL entry. 1. The BSL is called by the bootcode when the application memory is erased. Bootcode reads out addresses 0x0 and 0x4 from the application flash memory and compares it with 0xFFFFFFFF to determine whether or not the application memory is erased. 2. The BSL is called by application software (refer to Section 4.3.1). 3. The BSL is called by the device bootcode by applying a hardware entry sequence (refer to Section 4.3.2). 10 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com BSL Memories 4.3.1 Software BSL Invocation The BSL has an API table at address 0x0020:2000 that the application can call. The table contains the address of the function that starts the BSL execution. The application needs to pass a certain set of parameters that determines the following: 1. BSL interface (automatic, UART, I2C, SPI). 2. BSL I2C slave address (default = 0x48). The API table contains the address of the BSL entry function. This function takes a 32-bit argument that is formatted the same as the BSL hardware invoke parameters in the Boot Override Flash Mailbox (see Table 7). Bit 31 30:26 25:16 15:13 12 11:7 6:4 3:0 Table 7. BSL Entry Function Parameters Value N/A for BSL as entry function parameter. Reserved. Default should be 0x1F, but N/A for BSL as entry function parameter. I2C slave address. Default = 0x48. Interface selection. 7h = Automatic 6h = UART 5h = SPI 4h = I2C 3h-0h = Reserved for future expansion; defaults to automatic mode. N/A for BSL as entry function parameter. Reserved. Default should be 0x1F, but N/A for BSL as entry function parameter. N/A for BSL as entry function parameter. N/A for BSL as entry function parameter. The following C code example demonstrates how the address from the API table is used to start the BSL and pass the BSL entry function parameters by the application: #define BSL_PARAM 0xFC48FFFF // I2C slave address = 0x48, Interface selection = Auto #define BSL_API_TABLE_ADDR 0x00202000 // Address of BSL API table #define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t)BSL_PARAM); // Call the BSL with given BSL parameters SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 11 Copyright © 2015, Texas Instruments Incorporated BSL Memories www.ti.com 4.3.2 Hardware BSL Invocation Hardware invocation on the MSP432 BSL differs from the hardware invocation on the MSP430 devices. On MSP432 devices, the BSL invocation takes advantage of the boot-override mechanism. (See the SYSCTL chapter in the MSP432P4xx Technical Reference Manual (SLAU356) for details on boot overrides). The boot-override command used for setting up BSL for hardware invocation is BSL_PARAMS. Table 8 provides the flash mailbox structure for the boot-overrides possible in MSP432. Table 8. Boot Override Flash Mailbox Mailbox Offset Group 0x0 0x4 GEN_PARAMS 0x8 FACTORY_RESET 0xC 0x10 0x14-0x20 0x24-0x40 JTAG_SWD_LOCK_PARAMS 0x44-0x50 0x54 0x58-0x5C 0x60 0x64 0x68 0x6C-0x78 0x7C-0x98 SEC_ZONE0_PARAMS 0x9C-0xA8 0xAC 0xB0 0xB4 0xB8-BC Description Value MB_START Mail box start 0x0115ACF6 CMD Command for Boot override operations. ACK Acknowledgment for this command Reserved 0xFFFFFFFF JTAG_SWD_LOCK_SECEN JTAG and SWD Lock Enable Disable = 0xFFFFFFFF Enable = 0x00000000 JTAG_SWD_LOCK_AES_INIT_VECT[0- JTAG and SWD lock AES initialization vector for AES-CBC 3] to be used for enrypted updates JTAG_SWD_LOCK_AES_SECKEYS[0-7] JTAG and SWD lock AES CBC security Keys 0-7. This should be the key that is used to generate the ENCPAYLOAD when the user intends to do an upgrade. 0xFFFFFFFF when disabled. JTAG_SWD_LOCK_UNENC_PWD[0-3] JTAG and SWD lock unencrypted password 0xFFFFFFFF when security is disabled. ACK Acknowledgment for this command Reserved Reserved SEC_ZONE0_SECEN Disable = 0xFFFFFFFF Enable = 0x00000000 SEC_ZONE0_START_ADDR Start address of IP protected secure zone 0. Should be aligned to 4KB boundary. SEC_ZONE0_LENGTH Length of IP protected secure zone 0 in number of bytes. Should be multiples of 4KB flash sector size. SEC_ZONE0_AESINIT_VECT[0-3] IP protected secure zone 0 AES initialization vector for AES-CBC to be used for Encrypted Updates. SEC_ZONE0_SECKEYS[0-7] AES-CBC security keys. This should be the key that is used to generate the ENCPAYLOAD when the user intends to do an upgrade. 0xFFFFFFFF when IP protected secure zone 0 security disabled. SEC_ZONE0_UNENC_PWD[0-3] Unencrypted password for authentication. 0xFFFFFFFF when IP protected secure zone 0 security disabled. SEC_ZONE0_ENCUPDATE_EN Disable = 0xFFFFFFFF Enable = 0x0000000 SEC_ZONE0_DATA_EN Disable = 0xFFFFFFFF Enable = 0x00000000 ACK Acknowledgment for this command RESERVED 0xFFFFFFFF 12 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com BSL Memories Table 8. Boot Override Flash Mailbox (continued) Mailbox Offset 0xC0 0xC4 0xC8 0xCC-0xD8 Group 0xDC-0xF8 SEC_ZONE1_PARAMS 0xFC0x108 0x10C 0x110 0x114 0x1180x11C 0x120 0x124 0x128 0x12C0x138 0x13C0x158 SEC_ZONE2_PARAMS 0x15C0x168 0x16C 0x170 0x174 0x1780x17C Description SEC_ZONE1_SECEN SEC_ZONE1_START_ADDR SEC_ZONE1_LENGTH SEC_ZONE1_AESINIT_VECT[0-3] SEC_ZONE1_SECKEYS[0-7] SEC_ZONE1_UNENC_PWD[0-3] SEC_ZONE1_ENCUPDATE_EN SEC_ZONE1_DATA_EN ACK RESERVED SEC_ZONE2_SECEN SEC_ZONE2_START_ADDR SEC_ZONE2_LENGTH SEC_ZONE2_AESINIT_VECT[0-3] SEC_ZONE2_SECKEYS[0-7] SEC_ZONE2_UNENC_PWD[0-3] SEC_ZONE2_ENCUPDATE_EN SEC_ZONE2_DATA_EN ACK RESERVED Value Disable = 0xFFFFFFFF Enable = 0x00000000 Start address of IP protected secure zone 1. Should be aligned to 4KB boundary. Length of IP protected secure zone 1 in number of bytes. Should be multiples of 4KB flash sector size. IP protected secure zone 1 AES initialization vector for AES-CBC to be used for Encrypted Updates. AES-CBC security keys. This should be the key that is used to generate the ENCPAYLOAD when the user intends to do an upgrade. 0xFFFFFFFF when IP protected secure zone 1 security disabled. Unencrypted password for authentication. 0xFFFFFFFF when IP protected secure zone 1 security disabled. Disable = 0xFFFFFFFF Enable = 0x0000000 Disable = 0xFFFFFFFF Enable = 0x00000000 Acknowledgment for this command 0xFFFFFFFF Disable = 0xFFFFFFFF Enable = 0x00000000 Start address of IP protected secure zone 2. Should be aligned to 4KB boundary. Length of IP protected secure zone 2 in number of bytes. Should be multiples of 4KB flash sector size. IP protected secure zone 2 AES initialization vector for AES-CBC to be used for Encrypted Updates. AES-CBC security keys. This should be the key that is used to generate the ENCPAYLOAD when the user intends to do an upgrade. 0xFFFFFFFF when IP protected secure zone 2 security disabled. Unencrypted password for authentication. 0xFFFFFFFF when IP protected secure zone 2 security disabled. Disable = 0xFFFFFFFF Enable = 0x0000000 Disable = 0xFFFFFFFF Enable = 0x00000000 Acknowledgment for this command 0xFFFFFFFF SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 13 Copyright © 2015, Texas Instruments Incorporated BSL Memories www.ti.com Table 8. Boot Override Flash Mailbox (continued) Mailbox Offset 0x180 0x184 0x188 0x18C0x198 Group 0x19C0x1B8 SEC_ZONE3_PARAMS 0x1BC0x1C8 0x1CC 0x1D0 0x1D4 0x1D80x1DC 0x1E0 0x1E4 0x1E8 BSL_PARAMS 0x1EC0x1F0 0x1F4 Description SEC_ZONE3_SECEN SEC_ZONE3_START_ADDR SEC_ZONE3_LENGTH SEC_ZONE3_AESINIT_VECT[0-3] SEC_ZONE3_SECKEYS[0-7] SEC_ZONE3_UNENC_PWD[0-3] SEC_ZONE3_ENCUPDATE_EN SEC_ZONE3_DATA_EN ACK RESERVED BSL Enable BSL Start Address BSL hardware invoke parameters Reserved ACK Value Disable = 0xFFFFFFFF Enable = 0x00000000 Start address of IP protected secure zone 3. Should be aligned to 4KB boundary. Length of IP protected secure zone 3 in number of bytes. Should be multiples of 4KB flash sector size. IP protected secure zone 3 AES initialization vector for AES-CBC to be used for Encrypted Updates. AES-CBC security keys. This should be the key that is used to generate the ENCPAYLOAD when the user intends to do an upgrade. 0xFFFFFFFF when IP protected secure zone 3 security disabled. Unencrypted password for authentication. 0xFFFFFFFF when IP protected secure zone 3 security disabled. Disable = 0xFFFFFFFF Enable = 0x0000000 Disable = 0xFFFFFFFF Enable = 0x00000000 Acknowledgment for this command 0xFFFFFFFF Disable = 0xFFFFFFFF Enable = 0x00000000 Contains the pointer to the BSL function. Bootcode reads this location and uses this as a function pointer. Default = TI BSL API table address. Hardware invoke field. Bootcode will jump to the BSL after matching the values in the field with the corresponding port pins of the device. Bit 31 1h = Disable 0h = Enable Bits 30:26 Reserved. Default should be 0x1F. Bits 25:16 I2C slave address. Default = 0x48. Bits 15:13 Interface selection. 7h = Automatic 6h = UART 5h = SPI 4h = I2C 3h-0h = Reserved for future expansion; Defaults to automatic mode. Bit 12 Polarity of port pin. 0h = Low 1h = High Bits 11:7 Reserved for future expansion. Default should be 0x1F. Bits 6:4 Pin number of the port to be used for BSL entry. 0h = BIT0 1h = BIT1 2h = BIT2 3h = BIT3 4h = BIT4 5h = BIT5 6h = BIT6 7h = BIT7 Bits 3:0 Port to be used for HW BSL entry sequence. 0h = P1 1h = P2 2h = P3 3h-Fh = Reserved 0xFFFFFFFF Acknowledgment for this command 14 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com BSL Memories Mailbox Offset 0x1F8 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C 0x240 0x244 0x248 0x24C Table 8. Boot Override Flash Mailbox (continued) Group JTAG_SWD_LOCK_ ENC_UPDATE SEC_ZONE0_UPDATE SEC_ZONE1_UPDATE SEC_ZONE2_UPDATE SEC_ZONE3_UPDATE Description Value JTAG_SWD_LOCK_ENCPAYLOADADD R JTAG_SWD_LOCK_ENCPAYLOADLEN JTAG_SWD_LOCK_DST_ADDR ACK RESERVED SEC_ZONE0_PAYLOADADDR SEC_ZONE0_PAYLOADLEN ACK Reserved SEC_ZONE1_ENCPAYLOADADDR SEC_ZONE1_ENCPAYLOADLEN ACK Reserved SEC_ZONE2_ENCPAYLOADADDR SEC_ZONE2_ENCPAYLOADLEN ACK Reserved SEC_ZONE3_ENCPAYLOADADDR SEC_ZONE3_ENCPAYLOADLEN ACK Reserved MB_END Start address where the payload is loaded in the device. Length of the encrypted payload in bytes. This value should be a multiple of 4KB flash sector size. Destination address where the final data needs to be stored into the device. Should be aligned to 4KB boundary. Acknowledgment for this command 0xFFFFFFFF Start address where the payload is loaded in the device. Length of the payload in bytes. This value should match the SEC_ZONE0_LENGTH parameter + 128 bits. There is a limitation that the IP protected secure zone update restricts the user to update a full secure zone. User cannot initiate a partial update to the IP protected secure zone. Acknowledgment for this command 0xFFFFFFFF Start address where the payload is loaded in the device. Length of the payload in bytes. This value should match the SEC_ZONE1_LENGTH parameter + 128 bits. There is a limitation that the IP protected secure zone update restricts the user to update a full secure zone. User cannot initiate a partial update to the IP protected secure zone. Acknowledgment for this command 0xFFFFFFFF Start address where the payload is loaded in the device. Length of the payload in bytes. This value should match the SEC_ZONE2_LENGTH parameter + 128 bits. There is a limitation that the IP protected secure zone update restricts the user to update a full secure zone. User cannot initiate a partial update to the IP protected secure zone. Acknowledgment for this command 0xFFFFFFFF Start address where the payload is loaded in the device. Length of the payload in bytes. This value should match the SEC_ZONE3_LENGTH parameter + 128 bits. There is a limitation that the IP protected secure zone update restricts the user to update a full secure zone. User cannot initiate a partial update to the IP protected secure zone. Acknowledgment for this command 0xFFFFFFFF Mailbox end 0x011E11D The hardware based BSL invocation enable is different from the "BSL enable" in theboot-override fields. The hardware based BSL invocation enable will not be affected by using the"BSL Enable" field of the boot override mail box. The user needs to configure hardware based BSLinvoke using the boot-override mailbox with the "BSL hardware invoke parameters". for example, Assume a user wishes to use the I2C mode of BSL with a slave address of 0x42, and wishes to use Port 1-bit 0-level 1 as the BSL entry sequence. The user will need to populate the mailbox command of BSL_PARAMS with the following: 1. BSL Enable = 0x0 2. BSL start address = TI BSL API table address. 3. BSL hardware invocation parameters = 0x7C429F80. (Bit 31 = 0 (Enable), Bits 25:16 = 0x42 (I2C address), Bits 15:13 = 0x4 (I2C), Bit 12 = 1 (Level 1), Bits 6:4 = 0x0 (BIT0), Bits 3:0 = 0x0 (PORT1) After this the user needs to issue a reboot-reset into the device. This will enable the Hardware based BSL invocation in the system. From then on the device would enter BSL whenever it finds the sequence as provided in Figure 6 (this figure is applicable for the previous example). SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 15 Copyright © 2015, Texas Instruments Incorporated BSL Protocol www.ti.com RSTn P1.0 Boot execution Boot execution start ends/User program starts Figure 5. Standard RESET Sequence RSTn P1.0 Boot execution Boot execution start ends/BSL start Figure 6. BSL Entry Sequence at Configured GPIO Pin 5 BSL Protocol 5.1 BSL Data Packet The BSL data packet has a layered structure. The BSL core command contains the actual command data to be processed by the BSL. In addition the standard BSL commands, there can be wrapper data before and after each core command known as the peripheral interface code (PI Code). This wrapper data is information that is specific to the peripheral and protocol being used, and it contains information that allows for correct transmission of the BSL core command. Taken together, the wrapper and core command constitute a BSL data packet. PI Code Table 9. BSL Data Packet BSL Core Command PI code 5.2 BSL Security To protect data within the device, most core commands are protected. A protected command is successfully complete only after the device has been unlocked by sending the RX Password command with the correct password. In addition, commands specific to the peripheral interface are not protected. 16 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com 5.3 BSL Core Commands Table 10 shows the format of the BSL core commands. Table 10. BSL Core Commands BSL Command Protected CMD A0 A1 A2 A3 RX Data Block Yes RX Data Block 32 Yes RX Password No Erase Sector Yes Erase Sector 32 Yes Mass Erase No Reboot reset No 0x10 (A0) (A1) (A2) - 0x20 (A0) (A1) (A2) (A3) 0x21 - - - - 0x12 (A0) (A1) (A2) - 0x22 (A0) (A1) (A2) (A3) 0x15 - - - - 0x25 - - - - CRC Check Yes 0x16 (A0) (A1) (A2) - CRC Check 32 Load PC Load PC 32 TX Data Block Yes 0x26 (A0) (A1) (A2) (A3) Yes 0x17 (A0) (A1) (A2) - Yes 0x27 (A0) (A1) (A2) (A3) Yes 0x18 (A0) (A1) (A2) - TX Data Block 32 Yes TX BSL Version Yes Change Baud Rate No 0x28 (A0) (A1) (A2) (A3) 0x19 - - - - 0x52 - - - - BSL Protocol Data D1..Dn D1..Dn D1..D256 Length (low byte), Length (high byte) Length (low byte), Length (high byte) Length (low byte), Length (high byte) Length (low byte), Length (high byte) D1 BSL Core Response Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes No A0, A1, A2, A3 Address bytes. These represent the 4 bytes from LSB to MSB, respectively, of a 32 bit address. D1...Dn Data bytes 1 through n. Length A byte containing a value from 1 to 255 describing the number of bytes to be transmitted or used in a CRC. In the case of multiple length bytes, they are combined together as described to form a larger value describing the number of required bytes. - No data required. No delay should be given, and any subsequently required data should be sent as the immediate next byte. SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 17 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.3.1 RX Data Block Table 11 shows the RX data block format. BSL Command RX Data Block Protecte d Yes CMD 0x10 Table 11. RX Data Block A0 A1 A2 A3 (A0) (A1) (A2) - Data D1…Dn www.ti.com BSL Core Response Yes Description The BSL core writes bytes D1 through Dn starting from the location specified in the address fields. This command has been kept for backward compatibility with MSP430 BSL and will allow to address the lower 24 bits of the device. Protection This command is password protected and fails if the password has not been sent. Command 0x10 Command Address Address where the received data should be written. Command Data Command consists of the data D1 through Dn to be written. The command consists of n bytes, where n has maximum 256. Command Returns BSL acknowledgment and a BSL core response with the status of the operation. See Table 10 for more information on BSL core responses. Command Example Write data 0x76543210 to address 0x0001:0000: Header Length Length 0x80 0x08 0x00 CMD 0x10 A0 0x00 A1 0x00 A2 0x01 D1 0x10 D2 0x32 D3 0x54 D4 0x76 CKL 0x93 CKH 0xCA BSL response for a successful data write: ACK 0x00 Header 0x80 Length 0x02 Length 0x00 CMD 0x3B MSG 0x00 CKL 0x60 CKH 0xC4 18 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com 5.3.2 RX Data Block 32 Table 12 shows the RX data block 32 format. BSL Command RX Data Block 32 Protecte d Yes CMD 0x20 Table 12. RX Data Block 32 A0 A1 A2 A3 (A0) (A1) (A2) (A3) Data D1…Dn BSL Protocol BSL Core Response Yes Description The BSL core writes bytes D1 through Dn starting from the location specified in the address fields. This command allows the BSL to address the device with the full 32 bit range. Protection This command is password protected and fails if the password has not been sent. Command 0x20 Command Address Address where the received data should be written. Command Data Command consists of the data D1 through Dn to be written. The command consists of n bytes, where n has maximum 256. Command Returns BSL acknowledgment and a BSL core response with the status of the operation. See Table 10 for more information on BSL core responses. Command Example Write data 0x76543210 to address 0x0001:0000: Header Length Length CMD 0x80 0x09 0x00 0x20 A0 0x00 A1 0x00 A2 0x01 A3 0x00 D1 0x10 D2 0x32 D3 0x54 D4 0x76 CKL 0x66 CKH 0x96 BSL response for a successful data write: ACK 0x00 Header 0x80 Length 0x02 Length 0x00 CMD 0x3B MSG 0x00 CKL 0x60 CKH 0xC4 SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 19 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.3.3 RX Password Table 13 shows the RX password format. Table 13. RX Password BSL Protecte CMD A0 A1 A2 A3 Command d RX Password No 0x21 - - - - www.ti.com Data D1…D256 BSL Core Response Yes Description The BSL core receives the password contained in the packet and unlocks the BSL protected commands if the password matches the top 256 bytes in the BSL interrupt vector table (located between addresses 0x0 to 0xFF). When an incorrect password is given, a Boot Override factory reset is initiated. This means all code in flash main memory is erased, but not Information Memory. When a mass erase is performed, the password is always be 0xFF for all bytes. This is commonly used to gain access to an empty device or to load a new application to a locked device without password. Protection This command is not password protected. Command 0x11 Command Address N/A Command Data The command data is 256 bytes long and contains the device password. Command Returns BSL acknowledgment and a BSL core response with the status of the operation. See Table 10 for more information on BSL core responses. Command Example Unlock a blank device: Header Length Length 0x80 0x01 0x01 CMD 0x21 D1 0xFF D2 0xFF D3 0xFF D4 0xFF D5 0xFF D6 0xFF D7 0xFF D8 0xFF D9 0xFF D10 0xFF D11 0xFF D12 0xFF D13 0xFF D14 0xFF D15 0xFF D16 0xFF D17 0xFF D18 0xFF D19 0xFF D20 0xFF D21 0xFF D22 0xFF D23 0xFF D24 0xFF D25 0xFF D26 0xFF D27 0xFF D28 0xFF D29 0xFF D30 0xFF D31 0xFF D32 0xFF D33 0xFF D34 0xFF D35 0xFF D36 0xFF D37 0xFF D38 0xFF D39 0xFF D40 0xFF D41 0xFF D42 0xFF D43 0xFF D44 0xFF D45 0xFF D46 0xFF D47 0xFF ... 0xFF ... 0xFF ... 0xFF ... 0xFF ... 0xFF ... 0xFF .. 0xFF ... 0xFF D250 0xFF 20 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com D251 0xFF D252 0xFF D253 0xFF D254 0xFF BSL response for a successful password: ACK 0x00 Header 0x80 Length 0x02 Length 0x00 D255 0xFF CMD 0x3B D256 0xFF MSG 0x00 CKL 0xAD CKL 0x60 CKH 0x08 BSL Protocol CKH 0xC4 5.3.4 Erase Sector BSL Command Protecte d CMD A0 A1 A2 A3 Erase Sector Yes 0x12 (A0) (A1) (A2) - Data - BSL Core Response Yes Description All code flash (Main or Information flash) in the MSP432 in the sector corresponding to the address is erased except for areas defined as IP Protected secure zones. This function does not erase RAM. Protection This command is password protected. Command 0x12 Command Address Any address (24 bits) in the sector for which erase is to be performed. Command Data N/A Command Returns BSL acknowledgment and a BSL core response with the status of the operation. See Table 10 for more information on BSL core responses. Command Example Initiate a Erase sector at address 0x0020:0000: Header 0x80 Length 0x04 Length 0x00 CMD 0x12 A0 0x00 A1 0x00 A2 0x20 CKL 0x6D CKH 0x56 BSL response (successful operation): ACK 0x00 Header 0x80 Length 0x02 Length 0x00 CMD 0x3B MSG 0x00 CKL 0x60 CKH 0xC4 SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 21 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.3.5 Erase Sector 32 www.ti.com BSL Command Protecte d CMD A0 A1 A2 A3 Erase Sector 32 Yes 0x22 (A0) (A1) (A2) (A3) Data - BSL Core Response Yes Description All code flash (Main or Information flash) in the MSP432 in the sector corresponding to the address is erased except for areas defined as IP Protected secure zones. This function does not erase RAM. Protection This command is password protected. Command 0x22 Command Address Any address (32 bits) in the sector for which erase is to be performed. Command Data N/A Command Returns BSL acknowledgment and a BSL core response with the status of the operation. See Table 10 for more information on BSL core responses. Command Example Initiate a Erase sector at address 0x0020:0000: Header Length Length CMD 0x80 0x05 0x00 0x12 A0 0x00 A1 0x00 A2 0x20 A3 0x00 CKL 0x33 CKH 0x57 BSL response (successful operation): ACK 0x00 Header 0x80 Length 0x02 Length 0x00 CMD 0x3B MSG 0x00 CKL 0x60 CKH 0xC4 22 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com 5.3.6 Mass Erase BSL Protocol BSL Command Protected CMD A0 A1 A2 A3 Mass Erase No 0x15 - - - - Data - BSL Core Response Yes Description All code flash in the MSP432 is erased except for areas defined as IP protected secure zones. This function does not erase Information Memory and RAM. Protection This command is not password protected. Command 0x15 Command Address N/A Command Data N/A Command Returns BSL acknowledgment and a BSL core response with the status of the operation. See Table 10 for more information on BSL core responses. Command Example Initiate a mass erase: Header 0x80 Length 0x01 Length 0x00 CMD 0x15 CKL 0x64 CKH 0xA3 BSL response (successful operation): ACK 0x00 Header 0x80 Length 0x02 Length 0x00 CMD 0x3B MSG 0x00 CKL 0x60 CKH 0xC4 SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 23 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.3.7 Reboot Reset BSL Protected CMD A0 A1 A2 A3 Command Reboot reset No 0x25 - - - - Data - Description This command is used to initiate a reboot-reset into the MSP432 system. Protection This command is not password protected. Command 0x25 Command Address N/A Command Data N/A Command Returns None. The devices resets after successfully receiving the command. Command Example Initiate a reboot reset into MSP432: Header 0x80 Length 0x01 Length 0x00 CMD 0x25 CKL 0x37 CKH 0x95 BSL Response: None www.ti.com BSL Core Response No 24 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com 5.3.8 CRC Check BSL Protocol BSL Protected CMD A0 A1 A2 A3 Command CRC Check Yes 0x16 (A0) (A1) (A2) - Data Length (low byte), Length (high byte) BSL Core Response Yes Description The MSP432 device performs a 16-bit CRC check using the CCITT standard. The address given is the first byte of the CRC check. Two bytes are used for the length. Refer to the CRC chapter of the MSP432P4xx Technical Reference Manual (SLAU356) for more details on the CRC that is used. This command is retained from MSP430 for backward compatibility and is capable of address device memory with up to 24 bits of address. Protection This command is password protected and fails if the password has not been sent. Command 0x16 Command Address Address to begin the CRC check. Command Data The 16-bit length of the CRC check. D1 is the low byte of the length, and D2 is the high byte of the length. Command Returns BSL acknowledgment and a BSL core response with the CRC value. See Table 10 for more information on BSL core responses. Command Example Perform a CRC check from address 0x0000:4400 to 0x0000:47FF (size of 1024): Header Length Length CMD 0x80 0x06 0x00 0x16 A0 0x00 A1 0x44 A2 0x00 D1 0x00 D2 0x04 CKL 0x9C CKH 0x7D BSL response where 0x55 is the low byte of the calculated checksum and 0xAA is the high byte of the calculated checksum: ACK 0x00 Header 0x80 Length 0x03 Length 0x00 CMD 0x3A D1 0x55 D2 0xAA CKL 0x12 CKH 0x2B SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 25 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.3.9 CRC Check 32 www.ti.com BSL Protected CMD A0 A1 A2 A3 Command CRC Check 32 Yes 0x26 (A0) (A1) (A2) (A3) Data Length (low byte), Length (high byte) BSL Core Response Yes Description The MSP432 device performs a 16-bit CRC check using the CCITT standard. The address given is the first byte of the CRC check. Two bytes are used for the length. Refer to the CRC chapter of the MSP432P4xx Technical Reference Manual (SLAU356) for more details on the CRC that is used. Protection This command is password protected and fails if the password has not been sent. Command 0x26 Command Address Address to begin the CRC check. Command Data The 16-bit length of the CRC check. D1 is the low byte of the length, and D2 is the high byte of the length. Command Returns BSL acknowledgment and a BSL core response with the CRC value. See Table 10 for more information on BSL core responses. Command Example Perform a CRC check from address 0x0000:4400 to 0x0000:47FF (size of 1024): Heade r Length Length 0x80 0x07 0x00 CMD 0x26 A0 0x00 A1 0x44 A2 0x00 A3 0x00 D1 0x00 D2 0x04 CKL 0xF7 CKH 0xE6 BSL response where 0x55 is the low byte of the calculated checksum and 0xAA is the high byte of the calculated checksum: ACK 0x00 Header 0x80 Length 0x03 Length 0x00 CMD 0x3A D1 0x55 D2 0xAA CKL 0x12 CKH 0x2B 26 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com 5.3.10 Load PC BSL Protocol BSL Command Protecte d CMD A0 A1 A2 A3 Load PC Yes 0x17 (A0) (A1) (A2) - Data - BSL Core Response Yes Description Causes the BSL to begin execution at the given address. As BSL code is immediately exited with this instruction, no core response can be expected. This command is retained from MSP430 for backward compatibility and is capable of address device memory with up to 24 bits of address. Protection This command is password protected and fails if the password has not been sent. Command 0x17 Command Address Address to set the Program Counter. Command Data N/A Command Returns BSL acknowledgment and a BSL core response with the status of the operation. Load PC always return success or a BSL locked status. This status is sent only if the main application returns to the BSL. See Table 10 for more information on BSL core responses. Command Example Set program counter to 0x0000:4451: Header 0x80 Length 0x04 Length 0x00 CMD 0x17 A0 0x51 A1 0x44 A2 0x00 CKL 0xBC CKH 0x66 The BSL does not respond after the application gains control. SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 27 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.3.11 Load PC 32 www.ti.com BSL Command Protected CMD A0 A1 A2 A3 Load PC 32 Yes 0x27 (A0) (A1) (A2) (A3) Data - BSL Core Response Yes Description Causes the BSL to begin execution at the given address. As BSL code is immediately exited with this instruction, no core response can be expected. Protection This command is password protected and fails if the password has not been sent. Command 0x27 Command Address Address to set the Program Counter. Command Data N/A Command Returns BSL acknowledgment and a BSL core response with the status of the operation. Load PC always return success or a BSL locked status. This status is sent only if the main application returns to the BSL. See Table 10 for more information on BSL core responses. Command Example Set program counter to 0x0000:4451: Header Length Length 0x80 0x05 0x00 CMD 0x27 A0 0x51 A1 0x44 A2 0x00 A3 0x00 CKL 0x8E CKH 0xBC The BSL does not respond after the application gains control. 28 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com 5.3.12 TX Data Block BSL Protocol BSL Protected CMD A0 A1 A2 A3 Command TX Data Block Yes 0x18 (A0) (A1) (A2) - Data Length (low byte), Length (high byte) BSL Core Response Yes Description The BSL transmits data starting at the command address and with size command data. This command initiates multiple packets if the size is greater than or equal to the buffer size. This command is retained from MSP430 for backward compatibility and is capable of address device memory with up to 24 bits of address. Protection This command is password protected and fails if the password has not been sent. Command 0x18 Command Address Address to begin transmitting data from. Command Data The 16-bit length of the data to transmit. D1 is the low byte of the length, and D2 is the high byte of the length. Command Returns BSL acknowledgment and a BSL core response with n data packets where n is: HAJCPD J = ceiling l >QBBAN OEVA F p 1 For example, if 512 bytes are requested, BSL sends two packets: the first packet with a length of 262 (1 CMD + 261 data bytes) and the second with a length of 252 (1 CMD + 251 data bytes). See Table 10 for more information on BSL core responses. Command Example Transmit 4 bytes of data from address 0x0000:1C00: Header Length Length CMD 0x80 0x06 0x00 0x18 A0 0x00 A1 0x1C A2 0x00 D1 0x04 D2 0x00 CKL 0x87 CKH 0x81 BSL response where D1..D4 are the data bytes requested: ACK Header Length Length CMD 0x00 0x80 0x05 0x00 0x3A D1 0x11 D2 0x33 D3 0x55 D4 0x77 CKL 0x90 CKH 0x55 SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 29 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.3.13 TX Data Block 32 www.ti.com BSL Protected CMD A0 A1 A2 A3 Command Data BSL Core Response TX Data Block 32 Yes 0x28 (A0) (A1) (A2) (A3) Length (low byte), Length (high byte) Yes Description The BSL transmits data starting at the command address and with size command data. This command initiates multiple packets if the size is greater than or equal to the buffer size. Protection This command is password protected and fails if the password has not been sent. Command 0x28 Command Address Address to begin transmitting data from. Command Data The 16-bit length of the data to transmit. D1 is the low byte of the length, and D2 is the high byte of the length. Command Returns BSL acknowledgment and a BSL core response with n data packets where n is: HAJCPD J = ceiling l>QBBAN OEVA F 1p For example, if 512 bytes are requested, BSL sends two packets: the first packet with a length of 262 (1 CMD + 261 data bytes) and the second with a length of 252 (1 CMD + 251 data bytes). See Table 10 for more information on BSL core responses. Command Example Transmit 4 bytes of data from address 0x0000:1C00: Heade r Length Length 0x80 0x07 0x00 CMD 0x28 A0 0x00 A1 0x1C A2 0x00 A3 0x00 D1 0x04 D2 0x00 CKL 0x20 CKH 0x4F BSL response where D1..D4 are the data bytes requested: ACK Header Length Length CMD 0x00 0x80 0x05 0x00 0x3A D1 0x11 D2 0x33 D3 0x55 D4 0x77 CKL 0x90 CKH 0x55 30 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com 5.3.14 TX BSL Version BSL Protocol BSL Protected CMD A0 A1 A2 A3 Command TX BSL Version No 0x19 - - - - Data - BSL Core Response Yes Description BSL transmits its version information. Protection This command is password protected and fails if the password has not been sent. Command 0x19 Command Address N/A Command Data N/A Command Returns BSL acknowledgment and a BSL core response with its version number. The data is transmitted as it appears in memory with the following data bytes: Version Byte BSL Vendor Command Interpreter API Peripheral Interface Build ID Data (Low Byte, High Byte) D1, D2 D3, D4 D5, D6 D7, D8 D9, D10 See Table 10 for more information on BSL core responses. Command Example Request the BSL version: Header 0x80 Length 0x01 Length 0x00 CMD 0x19 CKL 0xE8 CKH 0x62 BSL response (version 0011.2233.4455.6677.8899 of the BSL): ACK Hea der Len gth Len gth CM D D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 CKL CK H 0x0 0x8 0x0 0x0 0x3 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xC 0x1 00B0A0 1 2 34 5 6 7 8 9FD SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 31 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.3.15 Change Baud Rate www.ti.com BSL Protected CMD A0 A1 A2 A3 Command Change Baud Rate No 0x52 - - - - Data D1 BSL Core Response No Description This command changes the baud rate for all subsequently received data packets. The command is acknowledged with either a single ACK or an error byte sent with the old baud rate before changing to the new one. No subsequent message packets can be expected. Protection This command is not password protected. Command 0x52 Command Address N/A Command Data Single byte, D1, that specifies the new baud rate to use. D1 0x01 0x03 0x04 0x05 0x06 Baud Rate 9600 19200 38400 57600 115200 Command Returns BSL acknowledgment Command Example Change baud rate to 115200: Header 0x80 Length 0x02 Length 0x00 CMD 0x52 D1 0x06 CKL 0x14 CKH 0x15 BSL Response: ACK 0x00 32 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com BSL Protocol 5.4 BSL Core Responses The BSL core responses are always wrapped in a peripheral interface wrapper with the identical format to that of received commands. The BSL core can respond in the format shown in Table 14. All numbers are in hexadecimal format. Table 14. BSL Core Responses BSL Response Data Block BSL Version CRC Value Buffer Size Message CMD 0x3A 0x3A 0x3A 0x3A 0x3B Data D1 ... Dn D1 ... D10 DL, DH NL, NH MSG CMD A required field used to distinguish between a message from the BSL and a data transmission from the BSL. MSG A byte containing a response from the BSL core describing the result of the requested action. This can either be an error code or an acknowledgment of a successful operation. It should be noted, in cases where the BSL is required to respond with data (for example, memory, version, CRC, or buffer size), no successful operation reply occurs, and the BSL core immediately sends the data. D1, Dx Data bytes containing the requested data. DL, DH Data low and high bytes, respectively, of a requested 16-bit CRC value. NL, NH Data bytes describing the length of the buffer size in bytes. To manage sizes above 255, the size is broken up into a low byte and a high byte. 5.5 BSL Core Messages Table 15 describes the BSL core messages MSG 0x00 0x04 0x05 0x07 Table 15. BSL Core Messages Meaning Operation Successful BSL Locked. The correct password has not yet been supplied to unlock the BSL. BSL Password Error. An incorrect password was supplied to the BSL when attempting an unlock. Unknown Command. The command given to the BSL was not recognized. SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 33 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.6 UART Peripheral Interface (PI) www.ti.com 5.6.1 UART Peripheral Interface Wrapper The MSP432 UART BSL protocol interface is implemented in multiple packets. The first packet is transmitted to the BSL device and contains the BSL Core Command and its wrapper. This has the format shown in Table 16 . The second packet is received from the BSL device and contains the BSL acknowledgment and the BSL Core Response if one is required by the BSL Core Command that was sent (see Table 8 for more information about what commands return a BSL Core Response). The BSL response is shown in Table 17. Header 0x80 Length NL Table 16. UART BSL Command Length NH BSL Core Command See Table 10 CKL CKL CKH CKH ACK ACK from BSL Header 0x80 Table 17. UART BSL Response Length Length BSL Core Response CKL NL NH See Table 15 CKL CKH CKH The BSL acknowledgment indicates any errors in the first packet. If a response other than ACK is received, the BSL Core Response is not sent. It is important that the host programmer check this first byte to determine if more data will be sent. CKL, CKH CRC checksum high and low bytes. The checksum is computed on bytes in BSL core command section only. The BSL uses CRC-CCITT for the checksum and computes it using the MSP432 CRC module (see the CRC chapter of the MSP432P401R Family User's Guide (SLAU356) for more details about the CRC hardware). NL, NH Number of bytes in BSL core data packet, broken into high and low bytes. ACK Sent by the BSL after the packet is received to acknowledge receiving the data correctly. This does not imply the BSL core data is a correct command or that it was executed correctly. ACK signifies only that the packet was formatted as expected and had a correct checksum. 34 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com 5.7 I2C Peripheral Interface (PI) BSL Protocol 5.7.1 I2C Peripheral Interface Wrapper The MSP432 I2C BSL protocol interface is implemented in multiple packets. The first packet is sent as a write request to the BSL slave address and contains the BSL Core Command and its wrapper. This has the format shown in Table 18. The second packet is sent as a read request to the BSL slave address and contains the BSL acknowledgment and the BSL Core Response if one is required by the BSL Core Command that was sent (see Section 5.3 for more information about what commands return a BSL Core Response). Table 19 shows the format of this BSL response. Table 18. I2C BSL Command I2C S/A/W Header 0x80 Length NL Length NH BSL Core Command See Table 10 CKL CKL CKH CKH Table 19. I2C BSL Response I2C ACK Header Length S/A/R ACK from BSL 0x80 NL (1) BSL Core Response is not always included. Length NH BSL Core Response(1) See Table 15 CKL CKL CKH CKH I2C STOP The BSL acknowledgment indicates any errors in the first packet. If a response other than ACK is received, the BSL Core Response is not sent. It is important that the host programmer check this first byte to determine if more data will be sent. CKL, CKH CRC checksum high and low bytes. The checksum is computed on bytes in BSL core command section only. The CRC is computed using the MSP432 CRC module specification (see the CRC chapter of the MSP432P4xx Technical Reference Manual (SLAU356) for implementation details). NL, NH Number of bytes in BSL core data packet, broken into high and low bytes. ACK Sent by the BSL after the packet is received to acknowledge receiving the data correctly. This does not imply the BSL core data is a correct command or that it was executed correctly. ACK signifies only that the packet was formatted as expected and had a correct checksum. S/A/W I2C start sequence sent by the host programmer to the MSP432 BSL slave device. This sequence specifies that the host would like to start a write to the device with the specified slave address. See the eUSCI I2C mode chapter of the MSP432P4xx Technical Reference Manual (SLAU356) for more details on I2C communication. S/A/R I2C start or re-start sequence sent by the host programmer to the MSP432 BSL slave device. This sequence specifies that the host would like to start a read from the device with the specified slave address. This does not need to be a re-start, the host programmer can send a stop followed by another start. See the eUSCI I2C mode chapter of the MSP432P4xx Technical Reference Manual (SLAU356) for more details on I2C communication. STOP I2C stop bit indicating the end of an I2C read or write. SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 35 Copyright © 2015, Texas Instruments Incorporated BSL Protocol 5.8 SPI Peripheral Interface www.ti.com 5.8.1 SPI Peripheral Interface The MSP432 SPI BSL protocol interface is implemented in multiple packets. The first packet is sent as a write request to the BSL slave address and contains the BSL Core Command and its wrapper. This has the format shown in Table 20. The second packet is sent as a read request to the BSL slave address and contains the BSL acknowledgment and the BSL Core Response if one is required by the BSL Core Command that was sent (see Section 5.3 for more information about what commands return a BSL Core Response). Table 21 shows the format of this BSL response. Header 0x80 Length NL Table 20. SPI BSL Command Length NH BSL Core Command See Table 10 CKL CKL CKH CKH Table 21. SPI BSL Response ACK Header Length ACK from BSL 0x80 NL (1) BSL Core Response is not always included. Length NH BSL Core Response(1) See Table 15 CKL CKL CKH CKH The BSL acknowledgment indicates any errors in the first packet. If a response other than ACK is received, the BSL Core Response is not sent. It is important that the host programmer check this first byte to determine if more data will be sent. CKL, CKH CRC checksum high and low bytes. The checksum is computed on bytes in BSL core command section only. The CRC is computed using the MSP432 CRC module specification (see the CRC chapter of the MSP432P4xx Technical Reference Manual (SLAU356) for implementation details). NL, NH Number of bytes in BSL core data packet, broken into high and low bytes. ACK Sent by the BSL after the packet is received to acknowledge receiving the data correctly. This does not imply the BSL core data is a correct command or that it was executed correctly. ACK signifies only that the packet was formatted as expected and had a correct checksum. 36 MSP432P401R Bootstrap Loader (BSL) User's Guide Copyright © 2015, Texas Instruments Incorporated SLAU622 – March 2015 Submit Documentation Feedback www.ti.com BSL Protocol 5.9 BSL Messages The peripheral interface section of the BSL software parses the wrapper section of the BSL data packet. If there are errors with the data transmission, an error message is sent immediately. An ACK is sent after all data has been successfully received and does not mean that the command has been correctly executed (or even that the command was valid) but, rather, that the data packet was formatted correctly and passed on to the BSL core software for interpretation. The BSL protocol dictates that every BSL data packet sent is responded to with a single byte acknowledgment in addition to any BSL data packets that are sent. Table 22 lists all possible acknowledgment responses from the BSL. If an acknowledgment byte other than ACK is sent, the BSL does not send any BSL data packets. The host programmer needs to check the acknowledgment error and retry transmission. Data 0x00 0x51 0x52 0x53 0x54 0x55 0x56 Table 22. Error Messages Meaning ACK Header incorrect. The packet did not begin with the required value of 0x80. Checksum incorrect. The packet did not have the correct checksum value. Packet size zero. The size for the BSL core command was given as 0. Packet size exceeds buffer. The packet size given is too big for the RX buffer. Unknown error. Unknown baud rate. The supplied data for baud rate change is not a known value. (UART only). 6 Low-Power Mode Support The MSP432 BSL supports low-power of operation. If the device starts up into the BSL, and the BSL does not detect any user input within 10 seconds, the BSL puts the device into the lowest power mode of the device, LPM4.5. After the device BSL enters the LPM4.5 mode of operation, only a pulse on the device RST pin can bring the device back up and go into the BSL. 7 MSP432P4xx BSL Version Information Table 23. MSP432P4xx BSL Information BSL Information Device BSL version Buffer size for core commands Value MSP432P401R 0000.0002.0003.0102.0003 262 bytes SLAU622 – March 2015 Submit Documentation Feedback MSP432P401R Bootstrap Loader (BSL) User's Guide 37 Copyright © 2015, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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