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STK682-010-E_芯片资料

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    标    签:STK682010E

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    这个一个驱动步进电机的子的资料。

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    Preliminary Datasheet Product Name STK682-010-E 1.Case Outline:19 pins (See attached case outline dimensions.) 2.Function :PWM current control stepping motor driver 3.Application :Industrial equipment etc. 4.Features: ・Output on-resistance (High side 0.3 Ω, Low side 0.25 Ω, Total 0.55 Ω; Ta = 25℃, IO = 2.5A) ・VMmax=36V(DC),Iopmax=3.0A ・2, 1-2, W1-2, 2W1-2, 4W1-2, 8W1-2, 16W1-2, 32W1-2 phase excitation are selectable ・With built-in automatic half current maintenance energizing function ・Over current protection circuit ・Thermal shutdown circuit ・Input pull down resistance ・With reset pin and enable pin 5.Absolute Maximum Ratings/Tc=25℃ Parameter supply voltage Peak output current Logic input voltage VREF input voltage Operating substrate temperature Storage temperature Symbol VMmax Iopmax VINmax VREFmax Tc Tstg Conditions 6.Allowable Operating Ranges/Ta=25℃ Parameter Supply voltage range Logic input voltage range VCC input voltage range VREF input voltage range Output current1 Output current2 Output current3 Symbol VM VIN VCC VREF Io1 Io2 Io3 Conditions 1-2Phase-ex,Tc≦90℃ 1-2Phase-ex,Tc=105℃ 2Phase-ex,Tc=105℃ Ratings Unit 36 V 3.0 A 6 V 6 V -20 to +105 ℃ -40 to +125 ℃ Ratings Unit 9 to 32 V 0 to 5 V 0 to 5 V 0 to 3 V 3.0 A 2.5 A 1.8 A RoHS DIRECTIVE PASS 130228HI 018-13-00** No.1 STK682-010-E 7.Electrical Characteristics/Tc=25℃, VM=24V Parameter Symbol Conditions Standby mode current drain Current drain IMstn IM VCC=”L” VCC=”H”,ENABLE="H" Thermal shutdown temperature Thermal hysteresis width TSD ΔTSD No Load Design guarantee Design guarantee Logic pin input current Logic input high-level voltage Logic input low-level voltage FDT pin high-level voltage FDT pin middle-level voltage FDT pin low-level voltage IinL1 IinH1 Vinh Vinl Vfdth Vfdtm Vfdtl VIN=0.8V VIN=5V Pins 2,3,16,17,18,19 Pins 2,3,16,17,18,19 Pin 6 Pin 6 Pin 6 Chopping frequency Chopping frequency Chopping oscillator circuit threshold voltage Fch Iosc1 C1=100pF Vtup1 Vtdown1 VREF pin input voltage DOWN output residual voltage Hold current switching frequency Blanking time Iref VolDO Falert Tb1 VREF=1.5V,CLK=10kHz Idown=1mA,CLK=Low Output block Output on-resistance Ronu Rond Output leakage current Ioleak Diode forward voltage VD Current setting reference voltage VRF Output short-circuit protection block Timer latch time Tscp IO=2.0A, high-side ON resistance IO=2.0A, low-side ON resistance VM=36V ID=-2.0A VREF=1.5V, Current ratio 100% Ratings Unit min. typ. max. 70 100 μA 3.3 4.6 mA 150 180 210 ℃ 40 ℃ 3 8 15 μA 30 50 70 μA 2.0 V 0.8 V 3.5 V 1.1 3.1 V 0.8 V 58 83 108 kHz 10 μA 1 V 0.5 V -0.5 μA 40 mV 1.6 Hz 1 μs 0.30 0.42 Ω 0.25 0.35 Ω 50 μA 1.1 1.4 V 300 mV 256 μs 130228HI 018-13-00** No.2 STK682-010-E 8. Block diagram VM 14 PGND A PGND B VREG1 VREF 5 NFA OUT1A OUT1B OUT2A OUT2B NFB 12 13 9 11 7 8 VREG2 Regulator 2 Output pre stage Output pre stage Output pre stage Output pre stage Regulator 1 Oscillator Output control logic Current select circuit OSC2 Current select circuit Decay Mode setting circuit 1.2k DOWN 1 10 15 GND PGND VCC 16 17 18 2 3 19 6 4 M1 M2 M3 CW/CCW CLK ENABLE FDT OSC1 9.Application Circuit Example CW/CCW CLK 5V R1 VCC M1 M2 M3 ENABLE FDT R2 VREF 2 3 STK682-010-E 5 VM 14 OUT2B 7 OUT1B 9 15 16 17 18 19 6 OSC1 4 GND 1 8 10 NFB PGND OUT2A 11 OUT1A 13 12 NFA VM=24V C3 C2 C1 RFB RFA GND 130228HI 018-13-00** No.3 STK682-010-E 10.Pin Functions Pin No. Pin symbol 1 GND 2 CW/CCW 3 CLK 4 OSC1 5 VREF 6 FDT 7 OUT2B 8 NFB 9 OUT1B 10 PGND 11 OUT2A 12 NFA 13 OUT1A 14 VM 15 VCC 16 M1 17 M2 18 M3 19 ENABLE Pin Functions Circuit GND Forward / Reverse signal input Clock pulse signal input Chopping frequency setting capacitor connection Constant-current control reference voltage input Decay mode select voltage input B phase OUTB output B phase current sense resistance connection B phase OUTA output Power GND A phase OUTB output A phase current sense resistance connection A phase OUTA output Motor supply connection Chip enable input Excitation-mode switching pin Output enable signal input 130228HI 018-13-00** No.4 11. Equivalent circuit diagram Pin No. 3 2 19 18 17 16 Pin type CLK CW/CCW ENABLE M3 M2 M1 15 VCC STK682-010-E VREG1 Equivalent Circuit Diagram GND VREG1 1100kKΩ 110000kKΩ 13 OUT1A 10 PGND 14 VM 12 NFA 11 OUT2A 9 OUT1B 8 NFB 7 OUT2B 130228HI 15 51kΩ Internal reset Input pin 100kΩ 1μF GND 2200KkΩ 1100kKΩ 8800KkΩ 51411 GND 13 3 9 9 77 1131 1100kkΩ 4 1120 86 1102 550000Ω 50000Ω 018-13-00** Continued on next page. No.5 Continued from preceding page. Pin No. Pin type 5 VREF STK682-010-E VREG1 Equivalent Circuit Diagram 5 ¥ 550000Ω GND 0.1μF VREG1 4 OSC1 GND VREG1 110000kkΩ 1.2kΩ DOWN 550000Ω 50000Ω GND 130228HI 018-13-00** No.6 12.Description of functions STK682-010-E (1) Excitation setting method Set the excitation setting as shown in the following table by setting M1 pin, M2 pin and M3 pin Input signal Initial position M3 M2 M1 MODE(Excitation) A phase current B phase current L L L 2 Phase 100% -100% L L H 1-2 Phase 100% 0% L H L W1-2 Phase 100% 0% L H H 2W1-2 Phase 100% 0% H L L 4W1-2 Phase 100% 0% H L H 8W1-2 Phase 100% 0% H H L 16W1-2 Phase 100% 0% H H H 32W1-2 Phase 100% 0% The initial position is also the default state at start-up and excitation position at counter-reset in each excitation mode (2)Output current setting Output current is set as shown below by the VREF pin (applied voltage) and a resistance value between NFA (B) pin and GND. IOUT = (VREF / 5) / NFA (B) resistance * The setting value above is a 100% output current in each excitation mode. (Example) When VREF=1.5V and NFA (B) resistance is 0.3 Ω, the setting current is shown below. IOUT = (1.5 V / 5) / 0.3 Ω = 1.0 A (3) Chip enable terminal/ VCC function When Chip enable terminal/ VCC pin is at low levels, the IC enters stand-by mode, all logic is reset and output is turned OFF. When Chip enable terminal/ VCC pin is at high levels, the stand-by mode is released (4) Step pin function CLK pin step signal input allows advancing excitation step Input Operation VCC CLK L * Stand-by mode H Excitation step feed H Excitation step hold 130228HI 018-13-00** No.7 STK682-010-E (5) Forward / reverse switching function CW/CCW Operation L CW H CCW CW / CCW CLK CW mode CCW mode CW mode Excitation (1) (2) (3) (4) (5) (6) (5) (4) (3) (4) (5) position A phase output B phase output The internal D / A converter proceeds by a bit on the rising edge of the step signal input to the CLK pin. In addition, CW and CCW mode are switched by CW and CCW pin setting. In CW mode, the B phase current is delayed by 90 relative to the A phase current. In CCW mode, the B phase current is advanced by 90 relative to the A phase current. (6) Output enable function When the ENABLE pin is set Low, the output is forced OFF and goes to high impedance. However, the internal logic circuits are operating, so the excitation position proceeds when the CLK is input. Therefore, when ENABLE pin is returned to High, the output level conforms to the excitation position proceeded by the CLK input. ENABLE CLK MO A phase output 0% B phase output High impedance output 130228HI 018-13-00** No.8 STK682-010-E (7) DECAY mode The DECAY mode of the output current becomes only MIXED DECAY. FDT voltage 3.5V to 1.1V to 3.1V or OPEN to 0.8V DECAY method SLOW DECAY MIXED DECAY FAST DECAY (8) Chopping frequency setting function Chopping frequency is set as shown below by a capacitor between OSC1 pin and GND. Fch = 1 / (C1+20pF/10×10-6) (Hz) (Example) When Cosc1=100pF, the chopping frequency is shown below. Fch = 1 / ((20+ 100)×10-12/10×10-6) (Hz) = 83.3(kHz) Note ・The 20pF is a stray capacitance which is involved by the package of STK682-010-E. (9) Output short-circuit protection circuit Build-in output short-circuit protection circuit makes output to enter in stand-by mode. This function prevents the IC from damaging when the output shorts circuit by a voltage short or a ground short, etc. When output short state is detected, short-circuit detection circuit starts the operating and output is once turned OFF. After the timer latch time (typ: 256μs), output is turned ON again. Still the output is at short state, the output is turned OFF and fixed in stand-by mode. When output is fixed in stand-by mode by output short protection circuit, output is released the latch by setting Chip enable terminal/ VCC="L" (10) Internal DOWN pin The DOWN pin is an open drain connection. This pin is turned ON when no rising edge of CLK between the input signals while a period determined by a capacitor between OSC2 and GND, and outputs at low levels. The DOWN pin output in once turned ON, is turned OFF at the next rising edge of CLK. Holding current switching time (0.6sectyp) is set by an internal capacitor between OSC2 pin and GND. (11) Output current tolerance 130228HI 018-13-00** No.9 Output出 c力urre電nt(流(Iピopーeakク値)I)oIo A A STK682-010-E STK682-010T-HEB712O8u-tEp ut 出cu力rre電nt流tol許era容n範ce囲I o-IoT-c Tc 3.5 3 2.5 2 1-2相励 1-2 phase磁e超xcitation and more 1.5 2相励磁 2 phase excitation 1 0.5 0 0 10 20 30 40 50 60 70 80 90 100 110 Opera動tin作g s時ub基stra板te温tem度pTecra tu℃re Tc ℃ (12) When mounting multiple drivers on a single PC board When mounting multiple drivers on a single PC board, the GND design should mount a VCC decoupling capacitor,C2 and C3, for each driver to stabilize the GND potential of the other drivers. The key wiring points are as follows. 130228HI 018-13-00** No.10 STK682-010-E VM=24 V 5V 5V R1 CW/CC W CLK FDT 2 3 14 6 STK682-010-E V M VRE FVC 5 C 15 OUT2 7B M1 16 OUT1 M M2 ENA3B 17 18 LEOSC1 19 4 GND 1 9B OUT 11 2A OUT 13 1A PGND 2phase stepping motor 8 10 12 R NFB NFA 2 RFB RFA C3 C2 R1 CW/CC W CLK 2 3 14 V M FDT VREF 6 5 STK682-010-E VC C 15 7 OUT2 B M1 16 OUT1 M M2 ENA3B 17 18 LEOSC1 19 4 9B OUT 11 2A OUT 2phase stepping motor GND 1 13 1A PGND 8 10 12 R NFB NFA 2 RFB RFA C3 C2 C1 C1 GND 130228HI 018-13-00** No.11 STK682-010-E (13) Output current vector locus (1 step normalized 90°) Phase A current ratio (%) 100.0 θ 00 66.7 θ 8 θ 1166 θ 2244 θ 3322 θ 4400 θ 4488 θ 566 θ 6644 θθ6644 ' ((22PPHHAASSEE)) θ 7722 θ 800 θ 8888 33.3 θ 966 θ 110044 θ 111122 θ 112200 0.0 0.0 33.3 66.7 Phase B current ratio (%) θ 1128 100.0 130228HI 018-13-00** No.12 STK682-010-E (14) Current setting ratio in each excitation mode 32W1-2 phase(%)16W1-2 phase(%) 8W1-2 phase(%) 4W1-2 phase(%) 2W1-2 phase(%) W1-2 phase(%) 1-2 phase(%) 2 phase(%) 32W1-2 phase(%)16W1-2 phase(%) 8W1-2 phase(%) 4W1-2 phase(%) 2W1-2 phase(%) W1-2 phase(%) 1-2 phase(%) 2 phase(%) STEP Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch STEP Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch Ach Bch θ0 100 0 100 0 100 0 100 0 100 0 100 0 100 0 θ65 70 72 θ1 100 1 θ66 69 72 69 72 θ2 100 2 100 2 θ67 68 73 θ3 100 4 θ68 67 74 67 74 67 74 θ4 100 5 100 5 100 5 θ69 66 75 θ5 100 6 θ70 65 76 65 76 θ6 100 7 100 7 θ71 64 77 θ7 100 9 θ72 63 77 63 77 63 77 63 77 θ8 100 10 100 10 100 10 100 10 θ73 62 78 θ9 99 11 θ74 62 79 62 79 θ10 99 12 99 12 θ75 61 80 θ11 99 13 θ76 60 80 60 80 60 80 θ12 99 15 99 15 99 15 θ77 59 81 θ13 99 16 θ78 58 82 58 82 θ14 99 17 99 17 θ79 57 82 θ15 98 18 θ80 56 83 56 83 56 83 56 83 56 83 θ16 98 20 98 20 98 20 98 20 98 20 θ81 55 84 θ17 98 21 θ82 53 84 53 84 θ18 98 22 98 22 θ83 52 85 θ19 97 23 θ84 51 86 51 86 51 86 θ20 97 24 97 24 97 24 θ85 50 86 θ21 97 25 θ86 49 87 49 87 θ22 96 27 96 27 θ87 48 88 θ23 96 28 θ88 47 88 47 88 47 88 47 88 θ24 96 29 96 29 96 29 96 29 θ89 46 89 θ25 95 30 θ90 45 89 45 89 θ26 95 31 95 31 θ91 44 90 θ27 95 33 θ92 43 90 43 90 43 90 θ28 94 34 94 34 94 34 θ93 42 91 θ29 94 35 θ94 41 91 41 91 θ30 93 36 93 36 θ95 39 92 θ31 93 37 θ96 38 92 38 92 38 92 38 92 38 92 38 92 θ32 92 38 92 38 92 38 92 38 92 38 92 38 θ97 37 93 θ33 92 39 θ98 36 93 36 93 θ34 91 41 91 41 θ99 35 94 θ35 91 42 θ100 34 94 34 94 34 94 θ36 90 43 90 43 90 43 θ101 33 95 θ37 90 44 θ102 31 95 31 95 θ38 89 45 89 45 θ103 30 95 θ39 89 46 θ104 29 96 29 96 29 96 29 96 θ40 88 47 88 47 88 47 88 47 θ105 28 96 θ41 88 48 θ106 27 96 27 96 θ42 87 49 87 49 θ107 25 97 θ43 86 50 θ108 24 97 24 97 24 97 θ44 86 51 86 51 86 51 θ109 23 97 θ45 85 52 θ110 22 98 22 98 θ46 84 53 84 53 θ111 21 98 θ47 84 55 θ112 20 98 20 98 20 98 20 98 20 98 θ48 83 56 83 56 83 56 83 56 83 56 θ113 18 98 θ49 82 57 θ114 17 99 17 99 θ50 82 58 82 58 θ115 16 99 θ51 81 59 θ116 15 99 15 99 15 99 θ52 80 60 80 60 80 60 θ117 13 99 θ53 80 61 θ118 12 99 12 99 θ54 79 62 79 62 θ119 11 99 θ55 78 62 θ120 10 100 10 100 10 100 10 100 θ56 77 63 77 63 77 63 77 63 θ121 9 100 θ57 77 64 θ122 7 100 7 100 θ58 76 65 76 65 θ123 6 100 θ59 75 66 θ124 5 100 5 100 5 100 θ60 74 67 74 67 74 67 θ125 4 100 θ61 73 68 θ126 2 100 2 100 θ62 72 69 72 69 θ127 1 100 θ63 72 70 θ128 0 100 0 100 0 100 0 100 0 100 0 100 0 100 θ64 71 71 71 71 71 71 71 71 71 71 71 71 71 71 100 100 130228HI 018-13-00** No.13 STK682-010-E (15) Current wave example in each excitation mode (2 phase, 1-2 phase, W1-2 phase, 4W1-2 phase) 2 phase excitation (CW mode) CLK (%) 100 IA 0 (%) -100 100 IB 0 -100 1-2 phase excitation (CW mode) CLK (%) 100 IA 0 -100 (%) 100 IB 0 -100 130228HI 018-13-00** No.14 W1-2 phase excitation (CW mode) CLK (%) 100 IA 0 -100 (%) 100 IB 0 -100 STK682-010-E 4W1-2 phase excitation (CW mode) CLK MO [%] 100 50 IA 0 -50 -100 [%] 100 50 IB 0 -50 -100 130228HI 018-13-00** No.15 STK682-010-E (16) Current control operation SLOW DECAY current control operation When FDT pin voltage is a voltage over 3.5 V, the constant-current control is operated in SLOW DECAY mode. (Sine-wave increasing direction) CLK CLK Setting current Coil current fchop Setting current Blanking Time Current mode CHARGE SLOW (Sine-wave decreasing direction) CLK Setting current Coil current Blanking Time CHARGE SLOW Setting current fchop Current mode CHARGE SLOW Blanking Time SLOW Blanking Time SLOW Each of current modes operates with the follow sequence. ・The IC enters CHARGE mode at a rising edge of the chopping oscillation. (A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1 μs, regardless of the current value of the coil current (ICOIL) and set current (IREF) ). ・After the period of the blanking time, the IC operates in CHARGE mode until ICOIL ≥ IREF. After that, the mode switches to the SLOW DECAY mode and the coil current is attenuated until the end of a chopping period. At the constant-current control in SLOW DECAY mode, following to the setting current from the coil current may take time (or not follow) for the current delay attenuation. 130228HI 018-13-00** No.16 STK682-010-E FAST DECAY current control operation When FDT pin voltage is a voltage under 0.8V, the constant-current control is operated in FAST DECAY mode. (Sine-wave increasing direction) CLK Setting current Setting current Coil current fchop Blanking Time Current mode CHARGE FAST CHARGE FAST (Sine-wave decreasing direction) CLK CLK Setting current se Setting current se Coil current Coil current Blanking Time Blanking Time fchop fchop Current mode CHARGE Current mode CHARGE FAST FAST Setting current se Setting current se Blanking Time Blanking Time FAST FAST CHARGE CHARGE FAST FAST Each of current modes operates with the follow sequence. The IC enters CHARGE mode at a rising edge of the chopping oscillation. (A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1 s, regardless of the current value of the coil current (ICOIL) and set current (IREF)). After the period of the blanking time, The IC operates in CHARGE mode until ICOIL ≥ IREF. After that, the mode switches to the FAST DECAY mode and the coil current is attenuated until the end of a chopping period. At the constant-current control in FAST DECAY mode, following to the setting current from the coil current takes short-time for the current fast attenuation, but, the current ripple value may be higher. 130228HI 018-13-00** No.17 STK682-010-E MIXED DECAY current control operation (Sine-wave increasing direction) CSLTKP Coil current fchop Setting current Blanking Time Setting current Current mode CHARGE SLOW FAST (Sine-wave decreasing direction) CLK Setting current CHARGE SLOW FAST Coil current Blanking Time Setting current fchop Current mode CHARGE SLOW FAST Blanking Time FAST CHARGE SLOW Each of current modes operates with the follow sequence. The IC enters CHARGE mode at a rising edge of the chopping oscillation. (A period of CHARGE mode (Blanking Time) is forcibly present in approximately 1 μs, regardless of the current value of the coil current (ICOIL) and set current (IREF)). In a period of Blanking Time, the coil current (ICOIL) and the setting current (IREF) are compared. If an ICOIL IREF state exists during the charge period: The IC operates in CHAGE mode until ICOIL IREF. After that, it switches to SLOW DECAY mode and then switches to FAST DECAY mode in the last approximately 1 μs of the period. If no ICOIL IREF state exists during the charge period: The IC switches to FAST DECAY mode and the coil current is attenuated with the FAST DECAY operation until the end of a chopping period. The above operation is repeated. Normally, in the sine wave increasing direction the IC operates in SLOW (+FAST) DECAY mode, and in the sine wave decreasing direction the IC operates in FAST DECAY mode until the current is attenuated and reaches the set value and the IC operates in SLOW (+FAST) DECAY mode. 130228HI 018-13-00** No.18 STK682-010-E Package Outline Diagram Product Name STK682-010-E note2 TSHTKB6872-101208H 1 note1 19 note3 ② Unit mm Tolerance ±0.4 Don’t scale this drawing. Control No. Date 130228HI ③ ① note1:Mark for No.1 pin identification. note2:The form of a character in this      drawing differs from that of HIC. note3:This indicates the date code.     The form of a character in this      drawing differs from that of HIC. No. Part Name ① Case ② Substrate ③ Lead Frame Material EPOXY IMST Substrate Cu Treatment Sn Revision 018-13-00** In charge Approval No.19

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