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矽创ST7565R IC资料

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Sitronix ST7565R 65 x 132 Dot Matrix LCD Controller/Driver INTRODUCTION ST7565R is a single-chip dot matrix LCD driver which incorporates LCD controller and common/segment drivers. ST7565R can be connected directly to a microprocessor with 8-bit parallel interface or 4-line serial interface (SPI-4). Display data sent from MPU is stored in the internal Display Data RAM (DDRAM) of 65x132 bits. The display data bits which are stored in DDRAM are directly related to the pixels of LCD panel. ST7565R contains 132 segment-outputs, 64 common-outputs and 1 icon-common-output. With built-in oscillation circuit and low power consumption power circuit, ST7565R generates LCD driving signal without external clock or power, so that it is possible to make a display system with the minimal power consumption. FEATURES Single-chip LCD Controller & Driver On-chip Display Data RAM (DDRAM) Capacity: 65x132=8580 bits Directly display RAM pattern from DDRAM Selectable Display Duty (by SEL3 & SEL2 & SEL1) 1/65 duty : 65 common x 132 segment 1/55 duty : 55 common x 132 segment 1/53 duty : 53 common x 132 segment 1/49 duty : 49 common x 132 segment 1/33 duty : 33 common x 132 segment Microprocessor Interface Bidirectional 8-bit parallel interface supports: 8080-series and 6800-series MPU Serial interface (SPI-4) is also supported (write only) Abundant Functions Display ON/OFF, Normal/Reverse Display Mode, Set Display Start Line, Read IC Status, Set all Display Points ON, Set LCD Bias, Electronic Volume Control, Read-modify-Write, Select Segment Driver Direction, Power Saving Mode, Select Common Driver Direction, Select Voltage Regulator Resistor Ratio (for V0). External Hardware Reset Pin (RSTB) Built-in Oscillation Circuit No external component required The external clock is also supported. Low Power Consumption Analog Circuit Built-in Voltage Booster (x2~x6) High-accuracy Voltage Regulator for LCD Vop: (Thermal Gradient: -0.05%/°C) Voltage Follower for LCD Bias Voltage Wide Operation Voltage Range VDD1-VSS=2.4V~3.3V VDD2-VSS=2.4V~3.3V Recommend panel size is smaller than 1.8” (A.A.). Temperature Range: -30~80°C Package Type: COG ST7565R 6800 , 8080 , 4-Line Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. Ver 1.9 1/53 2012/04/03 ST7565R ST7565R COG OUTLINE Chip Size: 5900 X 1000 Bump Height: 9 (for G-1) Bump Pitch: 34 (Min.) Unit: um Part Number Chip Thickness ST7565R 480 Bump Size PAD No. Size 1~67 42 x 54 68~73 56 x 54 74~84 42 x 54 85~282 17 x 118 * Refer to section “PAD CENTER COORDINATES” for ITO layout. Fig 1. Chip Outline Ver 1.9 2/53 2012/04/03 ST7565R PAD CENTER COORDINATES 65 Duty PAD NO. PIN Name X Y 1 TEST[6] 2575 392 2 FR 2515 392 3 CL 2455 392 4 DOFB 2395 392 5 VSS 2335 392 6 CS1B 2275 392 7 CS2 2215 392 8 VDD 2155 392 9 RST 2095 392 10 A0 2035 392 11 VSS 1975 392 12 /WR(R/W) 1915 392 13 /RD(E) 1855 392 14 VDD 1795 392 15 D0 1735 392 16 D1 1675 392 17 D2 1615 392 18 D3 1555 392 19 D4 1495 392 20 D5 1435 392 21 D6 1375 392 22 D7 1315 392 23 VDD 1255 392 24 VDD2 1195 392 25 VDD2 1135 392 26 VSS 1075 392 27 VSS 1015 392 28 VSS 955 392 29 VSS 895 392 30 VOUT 821 392 31 VOUT 761 392 32 CAP5P 701 392 33 CAP5P 641 392 34 CAP1N 581 392 35 CAP1N 521 392 36 CAP3P 461 392 37 CAP3P 401 392 38 CAP1N 341 392 39 CAP1N 281 392 40 CAP1P 221 392 Fig 2. PAD Location Ver 1.9 3/53 2012/04/03 ST7565R PAD NO. PIN Name X Y 41 CAP1P 161 392 42 CAP2P 101 392 43 CAP2P 41 392 44 CAP2N -19 392 45 CAP2N -79 392 46 CAP4P -139 392 47 CAP4P -199 392 48 VSS -273 392 49 VSS -333 392 50 VRS -408 392 51 VRS -468 392 52 VDD2 -542 392 53 VDD -602 392 54 V4 -676 392 55 V4 -736 392 56 V3 -796 392 57 V3 -856 392 58 V2 -916 392 59 V2 -976 392 60 V1 -1036 392 61 V1 -1096 392 62 V0 -1156 392 63 V0 -1216 392 64 VR -1276 392 65 VR -1336 392 66 VDD -1410 392 67 VDD2 -1470 392 68 TEST[0] -1537 392 69 TEST[1] -1611 392 70 TEST[2] -1685 392 71 TEST[3] -1759 392 72 TEST[4] -1833 392 73 TEST[5] -1907 392 74 VDD -1974 392 75 TEST[7] -2034 392 76 CLS -2094 392 77 C86 -2154 392 78 PSB -2214 392 79 HPMB -2274 392 80 IRS -2334 392 PAD NO. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name SEL1 SEL2 SEL3 VSS COM[31] COM[30] COM[29] COM[28] COM[27] COM[26] COM[25] COM[24] COM[23] COM[22] COM[21] COM[20] COM[19] COM[18] COM[17] COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[0] COMS2 SEG[0] SEG[1] SEG[2] X -2394 -2454 -2514 -2574 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2810 -2573 -2539 -2505 -2471 -2437 -2403 -2369 -2335 -2301 -2267 -2227 -2193 -2159 Y 392 392 392 392 373 339 305 271 237 203 169 135 101 67 33 -1 -35 -69 -103 -137 -171 -205 -239 -273 -307 -341 -375 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 Ver 1.9 4/53 2012/04/03 ST7565R PAD NO. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PIN Name SEG[3] SEG[4] SEG[5] SEG[6] SEG[7] SEG[8] SEG[9] SEG[10] SEG[11] SEG[12] SEG[13] SEG[14] SEG[15] SEG[16] SEG[17] SEG[18] SEG[19] SEG[20] SEG[21] SEG[22] SEG[23] SEG[24] SEG[25] SEG[26] SEG[27] SEG[28] SEG[29] SEG[30] SEG[31] SEG[32] SEG[33] SEG[34] SEG[35] SEG[36] SEG[37] SEG[38] SEG[39] SEG[40] SEG[41] SEG[42] X -2125 -2091 -2057 -2023 -1989 -1955 -1921 -1887 -1853 -1819 -1785 -1751 -1717 -1683 -1649 -1615 -1581 -1547 -1513 -1479 -1445 -1411 -1377 -1343 -1309 -1275 -1241 -1207 -1173 -1139 -1105 -1071 -1037 -1003 -969 -935 -901 -867 -833 -799 Y -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 PAD NO. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG[43] SEG[44] SEG[45] SEG[46] SEG[47] SEG[48] SEG[49] SEG[50] SEG[51] SEG[52] SEG[53] SEG[54] SEG[55] SEG[56] SEG[57] SEG[58] SEG[59] SEG[60] SEG[61] SEG[62] SEG[63] SEG[64] SEG[65] SEG[66] SEG[67] SEG[68] SEG[69] SEG[70] SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] SEG[81] SEG[82] X -765 -731 -697 -663 -629 -595 -561 -527 -493 -459 -425 -391 -357 -323 -289 -255 -221 -187 -153 -119 -85 -51 -17 17 51 85 119 153 187 221 255 289 323 357 391 425 459 493 527 561 Y -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 Ver 1.9 5/53 2012/04/03 ST7565R PAD NO. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name SEG[83] SEG[84] SEG[85] SEG[86] SEG[87] SEG[88] SEG[89] SEG[90] SEG[91] SEG[92] SEG[93] SEG[94] SEG[95] SEG[96] SEG[97] SEG[98] SEG[99] SEG[100] SEG[101] SEG[102] SEG[103] SEG[104] SEG[105] SEG[106] SEG[107] SEG[108] SEG[109] SEG[110] SEG[111] SEG[112] SEG[113] SEG[114] SEG[115] SEG[116] SEG[117] SEG[118] SEG[119] SEG[120] SEG[121] SEG[122] X 595 629 663 697 731 765 799 833 867 901 935 969 1003 1037 1071 1105 1139 1173 1207 1241 1275 1309 1343 1377 1411 1445 1479 1513 1547 1581 1615 1649 1683 1717 1751 1785 1819 1853 1887 1921 Y -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 PAD NO. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PIN Name SEG[123] SEG[124] SEG[125] SEG[126] SEG[127] SEG[128] SEG[129] SEG[130] SEG[131] COM[32] COM[33] COM[34] COM[35] COM[36] COM[37] COM[38] COM[39] COM[40] COM[41] COM[42] COM[43] COM[44] COM[45] COM[46] COM[47] COM[48] COM[49] COM[50] COM[51] COM[52] COM[53] COM[54] COM[55] COM[56] COM[57] COM[58] COM[59] COM[60] COM[61] COM[62] X 1955 1989 2023 2057 2091 2125 2159 2193 2227 2267 2301 2335 2369 2403 2437 2471 2505 2539 2573 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 2810 Y -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -360 -375 -341 -307 -273 -239 -205 -171 -137 -103 -69 -35 -1 33 67 101 135 169 203 237 271 305 Ver 1.9 6/53 2012/04/03 ST7565R PAD NO. PIN Name X Y 281 COM[63] 2810 339 282 COMS1 2810 373 Note: 1. Unit: um 2. This is the default PAD Center Coordinate Table with 1/65 Duty. Other duty output mapping can be found in Section FUNCTION DESCRIPTION and Fig 9. 3. Tolerance: +/- 0.05 um. 4. The definition of pin name is in full duty (1/65 Duty). 5. The definition of output pin name in different duty (1/55 Duty, 1/53 Duty, 1/49 Duty and 1/33 Duty) please refers Fig 9. Ver 1.9 7/53 2012/04/03 ST7565R BLOCK DIAGRAM VDD V0 V1 V2 V3 V4 VSS HPMB V0 VR VRS IRS VOUT CAP1N CAP1P CAP2N CAP2P CAP3N CAP4P CAP5P VDD2 VSS Voltage Follower Circuit Voltage Regulator Circuit Voltage Booster Circuit Power Supply Circuit Status 132 SEGMENT DRIVERS 64 COMMON DRI VERS COM Output Control Circuit Display Data Latch Circuit DISPLAY DATA RAM 65 X 132 = 8580 Bits Column Address Circuit FRS M/S CL DOF FR CLS Command Hecoder Bus Holder MPU INTERFACE ( Parallel and Serial ) Fig 3. Block Diagram Ver 1.9 8/53 2012/04/03 ST7565R PIN DESCRIPTION LCD Driver Output Pins Pin Name Type Description LCD segment driver outputs. The display data and the frame control the output voltage. Display data Frame Segment Driver Output Voltage Normal Display Inverse Display SEG0 to SEG131 O + V0 V2 H - VSS V3 + V2 L - V3 V0 VSS Display OFF, Power Save VSS VSS LCD common driver outputs. The internal scanning signal and the frame control the output voltage. COM0 to COM63 O Scan signal Frame + H + L Display OFF, Power Save Common Driver Output Voltage Normal Display Inverse Display VSS V0 V1 V4 VSS LCD common driver outputs for icons. COMS1, COMS2 O The output signals of these two pins are the same. (COMS) When icon feature is not used, these pins should be left open. No. of Pins 132 64 2 Microprocessor Interface Pins Pin Name Type Description No. of Pins RSTB Hardware reset input pin. When RSTB is “L”, internal initialization is executed I 1 and the internal registers will be initialized. CS1B CB2 Chip select input pin. Interface access is enabled when CS1B is “L” and CB2 is 1 I “H”. When chip is on-active (CS1B=“H” or CS2=”L”), D[7:0] pins are high 1 impedance. It determines whether the access is related to data or command. A0 I A0=“H”: Indicates that signals on D[7:0] are display data. 1 A0=“L”: Indicates that signals on D[7:0] are command. Read/Write execution control pin. When PSB is “H”, C86 MPU Type RWR Description Read/Write control input pin. 6800 H R/W R/W=“H”: read. series RWR I R/W=“L”: write. 1 Write enable input pin. 8080 L /WR Signals on D[7:0] will be latched at the rising series edge of /WR signal. RWR is not used in serial interface and should fix to “H” by VDD. Ver 1.9 9/53 2012/04/03 ST7565R Pin Name Type Description No. of Pins Read/Write execution control pin. When PSB is “H”, C86 MPU Type ERD Description Read/Write control input pin. ERD R/W=”H“: When E is “H”, D[7:0] are in output 6800 H E mode. I series 1 R/W=”L“: Signals on D[7:0] are latched at the falling edge of E signal. 8080 Read enable input pin. L /RD series When /RD is “L”, D[7:0] are in output mode. ERD is not used in serial interface and should fix to “H” by VDD. When using 8-bit parallel interface: (6800 or 8080 mode) 8-bit bi-directional data bus. Connect to the data bus of 8-bit microprocessor. I/O When CS1B and CS2 are non-active (CS1B=“H” & CS2=”L”), D[7:0] pins are high impedance. When using serial interface: 4-LINE D[7:0] 8 D7=SDA: Serial data input. D6=SCL: Serial clock input. I D[5:0] are not used and should connect to “H” by VDD. When CS1B and CS2 are non-active (CS1B=“H” & CS2=”L”), D[7:0] pins are high impedance. Note: 1. After VDD is turned ON, any MPU interface pins cannot be left floating. Configuration Pins Pin Name Type PSB I C86 I SEL[3:1] I Description PSB selects the interface type: Serial or Parallel. No. of Pins 1 C86 selects the microprocessor type in parallel interface mode. PSB C86 Selected Interface “H” “H” Parallel 6800 Series MPU Interface “H” “L” Parallel 8080 Series MPU Interface 1 “L” “X” Serial 4-Line SPI Interface Please refer to “APPLICATION NOTES” and “Microprocessor Interface” (Section 6) for detailed connection of the selected interface. These pins select the display duty and bias of ST7565R. SEL3 “L” “L” SEL2 “L” “L” SEL1 “L” “H” Duty 1/65 1/49 Bias 1/9 or 1/7 1/8 or 1/6 “L” “H” “L” 1/33 1/6 or 1/5 3 “L” “H” “H” 1/55 1/8 or 1/6 “H” “L” “L” 1/53 1/8 or 1/6 “H” - 0 Reserved Reserved Note: 1. The detailed definition of output pin name can be found in Fig 9. Ver 1.9 10/53 2012/04/03 ST7565R Pin Name Type CLS I IRS I HPMB I M/S I Description This pin selects built-in OSC circuit is enable or disable. CLS=”H”: built-in OSC circuit is enabled. CLS=”L”: built-in OSC circuit is disabled. This pin selects built-in resistor for V0 adjustment is enable or disable. IRS=H”: built-in resistor is enabled. IRS=”L”: built-in resistor is disabled. This pin is used to select power supply mode. HPMB=”H”: normal mode. HPMB=”L”: high power mode (suggested). This pin must connected to VDD. No. of Pins 1 1 1 Power System Pins Pin Name Type VDD Power VDD2 Power VSS Power VRS Power VOUT Power CAP1P CAP1N CAP2P CAP2N CAP3P CAP4P CAP5P V0 V1 V2 V3 V4 Power Power VR Power Description No. of Pins Digital power. If VDD=VDD2, connect to VDD2 externally. 13 Analog power. If VDD=VDD2, connect to VDD externally. 10 Ground of chip. 2 This pin is output internal VREG power for built-in LCD power circuit. 2 DC-DC voltage converter for LCD driver circuit. Connect a capacitor between 2 VOUT and VSS. 2 2 DC-DC voltage converter for LCD driver circuit. If using built-in voltage booster 2 circuit, the application circuit please refers to section of Liquid Crystal Driver 2 Power Circuit. 2 2 2 2 The power supply pins for LCD. 2 Insure the voltage levels of VOUT, V0, V1, V2, V3 and V4 always match below 2 relation: VOUT > V0 > V1 > V2 > V3 > V4 > VSS 2 2 If using external resistance for V0 voltage regulator, this pin is provided to 2 connect external resistor for voltage divide. Test Pins Pin Name TEST[7:0] CL DOFB FR Type T T T T Description Do NOT use. Reserved for testing. TEST[6:0] must be floating. TEST7 must connected to VDD. This pin is clock input terminal. If CLS=”H”, CL is output pin. If CLS=”L”, CL is input pin. Do NOT use. Reserved for testing. Do NOT use. Reserved for testing. No. of Pins 8 1 1 1 Ver 1.9 11/53 2012/04/03 ST7565R Recommend ITO Resistance Pin Name ITO Resistance TEST[7:0], VRS Floating CL, FR, DOFB, C86, PSB, HPMB, SEL[3:1], CLS, IRS No Limitation VDD, VDD2, VSS, VOUT, VR < 100Ω V0, V1, V2, V3, V4, CAP1P, CAP1N, CAP2P, CAP2N, CAP3P, CAP4P, CAP5P < 300Ω CS1B, CS2, ERD, RWR, A0, D[7:0] < 1KΩ RSTB < 10KΩ Note: 1. To prevent the ESD pulse resetting the internal register, applications should increase the resistance of RSTB signal (add a series resistor or increase ITO resistance). The value is different from modules. 2. The option setting to be “H” should connect to VDD. 3. The option setting to be “L” should connect to VSS. Ver 1.9 12/53 2012/04/03 ST7565R FUNCTION DESCRIPTION Microprocessor Interface Chip Select Input CS1B and CS2 pins are used for chip selection. When CS1B=“L” and CS2=”H”, the microprocessor interface is enabled and ST7565R can interface with an MPU. When CS1B=“H” or CS2=”L”, the inputs of A0, ERD and RWR with any combination will be ignored and D[7:0] are high impedance. In 4-Line serial interface, the internal shift register and serial counter are reset when CS1B=“H” or CS2=”L”. MCU Interface Selection The interface selection is controlled by C86 and PSB pins. The selection for parallel or serial interface is shown in Table 1. Table 1. Parallel/Serial Interface Mode PSB C86 CS1B CS2 A0 ERD RWR D[7:0] “H” “H” E R/W “H” “L” CS1B CS2 A0 /RD /WR D[7:0] “L” “X” - - Refer to serial interface. * The un-used pins are marked as “-” and should be fixed to “H” by VDD. MPU Interface 6800-series parallel interface 8080-series parallel interface 4-Line SPI interface Parallel Interface When PSB= “H”, the 8-bit bi-directional parallel interface is enabled and the type of MPU is selected by “C86” pin as shown in Table 2. The data transfer type is determined by signals on A0, ERD and RWR as shown in Table 3. Table 2. Microprocessor Selection for Parallel Interface PSB C86 CS1B CS2 A0 ERD RWR “H” “H” “L” CS1B CS2 A0 E R/W /RD /WR D[7:0] D[7:0] MPU Interface 6800-series parallel interface 8080-series parallel interface Common Pins CS1B CS2 A0 “H” “L” “H” “H” “L” “L” Table 3. Parallel Data Transfer Type 6800-Series E (ERD) “H” “H” “H” “H” R/W (RWR) “H” “L” “H” “L” 8080-Series /RD (ERD) /WR (RWR) Description “L” “H” Display data read out “H” “L” Display data write “L” “H” Internal status read “H” “L” Writes to internal register (instruction) Setting Serial Interface Serial Mode PSB C86 CS1B CS2 A0 4-Line SPI interface “L” X CS1B CS2 A0 * The un-used pins are marked as “-” and should be fixed to “H” by VDD. * C86 is marked as “X” and can be fixed to “H” or “L”. ERD - RWR - D7 SDA D6 D[5:0] SCLK - Note: 1. The option setting to be “H” should connect to VDD. 2. The option setting to be “L” should connect to VSS. Ver 1.9 13/53 2012/04/03 ST7565R 4-line SPI interface (PSB=“L”, C86=“H” or “L”) When ST7565R is active (CS1B=“L” and CS2=”H”), serial data (SDA) and serial clock (SCLK) inputs are enabled. When ST7565R is not active (CS1B=“H” or CS2=”L”), the internal 8-bit shift register and 3-bit counter are reset. Serial data on SDA is latched at the rising edge of serial clock on SCLK. After the 8th serial clock, the serial data will be processed to be 8-bit parallel data. The address selection pin (A0), which is latched at the 8th clock, indicates the 8-bit parallel data is display data or instruction. The 8-bit parallel data will be display data when A0 is “H” and will be instruction when A0 is “L”. The read feature is not available in this mode. The DDRAM column address pointer will be increased by one automatically after each byte of DDRAM access. Please note that the SCLK signal quality is very important and external noise maybe causes unexpected data/instruction latch. Fig 4. 4-Line SPI Access Note: Some MPU will set the interface to be Hi-Z (high impedance) mode when power saving mode or after hardware reset. This is not allowed when the VDD of ST7565R is turned ON. Because the floating input (especially for those control pins such as CS1B, CS2, RSTB, RWR or ERD…) maybe cause abnormal latch and cause abnormal display. Ver 1.9 14/53 2012/04/03 ST7565R Data Transfer ST7565R uses bus latch and internal data bus for interface data transfer. When writing data from MPU to the DDRAM, data is automatically transferred from the bus latch to the DDRAM as shown in Fig 5. When reading data from the on-chip DDRAM to MPU, the first read cycle reads the content in bus latch (dummy read) and the data that MPU should read will be output at the next read cycle as shown in Fig 6. That means: after setting the target address, a dummy read cycle is required before the following read-operation. Therefore, the data of the specified address cannot be read at the first read of display data right after setting the address, but can be read at the second read of display data. Fig 5. Data Transfer : Write Fig 6. Data Transfer : Read Ver 1.9 15/53 2012/04/03 ST7565R Display Data RAM (DDRAM) ST7565R is built-in a RAM with 65X132 bit capacity which stores the display data. The display data RAM (DDRAM) store the dot data of the LCD. It is an addressable array with 132 columns by 65 rows (8-page with 8-bit and 1-page with 1-bit). The X-address is directly related to the column output number. Each pixel can be selected when the page and column addresses are specified (please refer to Fig 7 for detailed illustration). The rows are divided into: 8 pages (Page-0 ~ Page-7) each with 8 lines (for COM0~63) and Page-8 with only 1 line (COMS, for icon). The display data (D7~D0) corresponds to the LCD common-line direction and D0 is on top. All pages can be accessed through D[7:0] directly except icon page. Icon RAM uses only 1-bit of data bus (D0). Refer to Fig 8 for detailed illustration. The microprocessor can write to and read from (only Parallel interfaces) DDRAM by the I/O buffer. Since the LCD controller operates independently, data can be written into DDRAM at the same time as data is being displayed without causing the LCD flicker or data-conflict. Fig 7. DDRAM Mapping Mode (Default Setting) Fig 8. DDRAM Format Ver 1.9 16/53 2012/04/03 ST7565R Addressing Data is downloaded into the Display Data RAM matrix in ST7565R as byte-format. The Display Data RAM has a matrix of 65 by 132 bits. The address ranges are: X=0~131 (column address), Y=0~8 (page address). Addresses outside these ranges are not allowed. Page Address Circuit This circuit provides the page address of DDRAM. It incorporates 4-bit Page Address Register which can be modified by the “Page Address Set” instruction only. The Page Address must be set before accessing DDRAM content. Page Address “8” is a special RAM area for the icons with only one valid bit: D0. Column Address Circuit The column address of DDRAM is specified by the Column Address Set command. The column address is increased (+1) after each display data access (read/write). This allows MPU accessing DDRAM content continuously. This feature stops at the end of each page (Column Address “83h”) because the Column Address and Page Address circuits are independent. For example, both Page Address and Column Address should be assigned for changing the DDRAM pointer from (Page-0, Column-83h) to (Page-1, Column-0). Furthermore, Register MX and MY makes it possible to invert the relationship between the DDRAM and the outputs (COM/SEG). It is necessary to rewrite the display data into DDRAM after changing MX setting. Ver 1.9 17/53 2012/04/03 ST7565R The relation between DDRAM and outputs with different MX or MY setting is shown below. 118 119 120 Page Address Data D3 D2 D1 D0 D0 D1 D2 0000 D3 D4 D5 D6 D7 D0 D1 D2 0001 D3 D4 D5 D6 D7 D0 D1 D2 0010 D3 D4 D5 D6 D7 D0 D1 D2 0011 D3 D4 D5 D6 D7 D0 D1 D2 0100 D3 D4 D5 D6 D7 D0 D1 D2 0101 D3 D4 D5 D6 D7 D0 D1 D2 0110 D3 D4 D5 D6 D7 D0 D1 D2 0111 D3 D4 D5 D6 D7 1 0 0 0 D0 BBB B B B BBB B B B BBB BBB B B B B B BBB BBBBB B B B B B B BBBB B B B B BBBB BB B B B B BBB B B B B B B B B B B BBB B B BB B BBB BBB BBB B BB B B BBB B B B B B BBB B B B B BB B BB B B B B 83 00 82 01 81 02 80 03 7F 04 7E 05 7D 06 7C 07 7B 08 Column Address (Hex) MX=0 MX=1 Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 08 7B 07 7C 121 122 123 124 125 126 241 242 243 06 7D 244 05 7E 245 04 7F 246 03 80 247 02 81 248 01 82 249 00 83 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH PAD No. (SEG) Reserved Reserved Reserved Reserved Reserved Reserved Line Address (Hex), Start Line S[6:0] = 0 1/65 Duty MY=0 MY=1 COM0 COM63 COM1 COM62 COM2 COM61 COM3 COM60 COM4 COM59 COM5 COM58 COM6 COM57 COM7 COM56 COM8 COM55 COM9 COM54 COM10 COM53 COM11 COM52 COM12 COM51 COM13 COM50 COM14 COM49 COM15 COM48 COM16 COM47 COM17 COM46 COM18 COM45 COM19 COM44 COM20 COM43 COM21 COM42 COM22 COM41 COM23 COM40 COM24 COM39 COM25 COM38 COM26 COM37 COM27 COM36 COM28 COM35 COM29 COM34 COM30 COM33 COM31 COM32 COM32 COM31 COM33 COM30 COM34 COM29 COM35 COM28 COM36 COM27 COM37 COM26 COM38 COM25 COM39 COM24 COM40 COM23 COM41 COM22 COM42 COM21 COM43 COM20 COM44 COM19 COM45 COM18 COM46 COM17 COM47 COM16 COM48 COM15 COM49 COM14 COM50 COM13 COM51 COM12 COM52 COM11 COM53 COM10 COM54 COM9 COM55 COM8 COM56 COM7 COM57 COM6 COM58 COM5 COM59 COM4 COM60 COM3 COM61 COM2 COM62 COM1 COM63 COM0 COM Output Map 1/49 Duty MY=0 MY=1 COM0 COM47 COM1 COM46 COM2 COM45 COM3 COM44 COM4 COM43 COM5 COM42 COM6 COM41 COM7 COM40 COM8 COM39 COM9 COM38 COM10 COM37 COM11 COM36 COM12 COM35 COM13 COM34 COM14 COM33 COM15 COM32 COM16 COM31 COM17 COM30 COM18 COM29 COM19 COM28 COM20 COM27 COM21 COM26 COM22 COM25 COM23 COM24 1/33 Duty MY=0 MY=1 COM0 COM31 COM1 COM30 COM2 COM29 COM3 COM28 COM4 COM27 COM5 COM26 COM6 COM25 COM7 COM24 COM8 COM23 COM9 COM22 COM10 COM21 COM11 COM20 COM12 COM19 COM13 COM18 COM14 COM17 COM15 COM16 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 ICON (COMS1, COMS2) 1/55 Duty MY=0 MY=1 COM0 COM53 COM1 COM52 COM2 COM51 COM3 COM50 COM4 COM49 COM5 COM48 COM6 COM47 COM7 COM46 COM8 COM45 COM9 COM44 COM10 COM43 COM11 COM42 COM12 COM41 COM13 COM40 COM14 COM39 COM15 COM38 COM16 COM37 COM17 COM36 COM18 COM35 COM19 COM34 COM20 COM33 COM21 COM32 COM22 COM31 COM23 COM30 COM24 COM29 COM25 COM28 COM26 COM27 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 PAD No. (COM) 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282, 117 Fig 9. DDRAM and Output Map (COM/SEG) Ver 1.9 18/53 2012/04/03 ST7565R Line Address Circuit The Line Address Circuit incorporates a counter and a Line Address register which is changed only by the “Display Start Line Set” instruction. This circuit assigns DDRAM a Line Address corresponding to the first display line (COM0). Therefore, by setting Line Address repeatedly, ST7565R can realize the screen scrolling without changing the contents of DDRAM as shown in Fig 10. The last common is always the COMS (common output for the icons). That means the icons will never scroll with the general display data. S0 118 S1 119 S2 120 S3 121 S4 122 S5 123 S6 124 S7 125 S8 126 S123 241 S124 242 S125 243 S126 244 S127 245 S128 246 S129 247 S130 248 S131 249 83 00 82 01 81 02 80 03 7F 04 7E 05 7D 06 7C 07 7B 08 08 7B 07 7C 06 7D 05 7E 04 7F 03 80 02 81 01 82 00 83 Page Address D3 D2 D1 D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 BBB B B B BBB B B B BBB BBB B B B B B BBB BBBBB B B B B B B BBBB B B B B BBBB BB B B B B BBB B B B B B B B B B B BBB B B BB B BBB BBB BBB B BB B B BBB B B B B B BBB B B B B BB B BB B B B B Column Address (Hex) MX=0 MX=1 Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH PAD No. SEG No. (MX=0) Line Address (Hex), Start Line S[6:0] = 0x1C Start 64 Lines When the common output is normal MY=0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 ICON (COMS) Regardless of the display start line address. Always the last line. Fig 10. Start Line Function Ver 1.9 19/53 2012/04/03 ST7565R Display Data Latch Circuit The display data latch circuit latches temporarily display data of each segment output which will be output at the next clock. The special functions such as reverse display, display OFF and display all points ON only change the data in the latch and the content in the Display Data RAM is not changed. Oscillation Circuit The built-in oscillation circuit generates the system clock for the liquid crystal driving circuit. The oscillation circuit is enabled after initializing ST7565R. The clock will not be output to reduce the power consumption. Liquid Crystal Driver Power Circuit The built-in power circuits generate the voltage levels which are necessary to drive the liquid crystal. The built-in power system has voltage booster, voltage regulator and voltage follower circuits. The functionality of voltage booster, voltage regulator and voltage follower circuits can be turned ON and OFF individually. ST7565R is possible to use built-in power circuit and external power supply through the command “Power Control Set”. The relationship of command setting and power using is shown below. Before power ST7565R OFF, a Power OFF procedure is needed (please refer to the OPERATION FLOW section). Power Control Set VB VR VF 1 1 1 0 1 1 0 0 1 0 0 0 Built-in Circuit Power Supply Booster Regulator Follower VOUT V0 V1 V2 V3 V4 ON ON ON Internal Internal Internal Internal Internal Internal OFF ON ON External Internal Internal Internal Internal Internal OFF OFF ON External External Internal Internal Internal Internal OFF OFF OFF External External External External External External Table 4. Power Control Ver 1.9 20/53 2012/04/03 ST7565R Booster Circuit Base on VDD2-VSS, ST7565R is able to product step-up voltages of x2, x3, x4, x5 and x6 through hardware and software setting. Fig 11. External Component of Booster Circuit Ver 1.9 21/53 2012/04/03 ST7565R Regulator Circuit ST7565R provides two kinds power supply for LCD driving voltage V0. Built-in regulator circuit or external power supply for V0 is available for LCD driving. The built-in high accuracy regulation circuit has 8 regulation ratios and each one has 64 EV-levels for voltage adjustment. Without additional external component, the output voltage can be changed by instructions such as “Regulation Ratio” and “Set EV”. The detailed setting method can be found in the INSTRUCTION DESCRIPTION section. Built-in Resistor Is Used For Regulator Circuit The internal regulator circuit can be controlled by built-in regulation ratio and the electronic volume setting. Internal Ra VEV (Constant Voltage Supply + Electronic Volume) VSS V0 Internal Rb V0 =(1+ Rb Ra ) x VEV = ( 1 + Rb ) x ( 1 Ra α 162 ) x VREG α VEV = ( 1 - 162 ) x VREG Fig 12. Built-in Regulation Ratio VREG is built-in constant voltage supply for regulator circuit. The voltage level of VREG is 2.1V at temperature 25°C. α is determined by command “Set EV”. Base on command “Set EV”, the relationship between EV[5:0] and α is shown below. EV5 EV4 EV3 EV2 EV1 EV0 α 000000 63 000001 62 000010 61 000011 60 : : : : : : : 111100 3 111101 2 111110 1 111111 0 Table 5. Relationship between Electronic Volume and α Ver 1.9 22/53 2012/04/03 ST7565R (1+Rb/Ra) is internal regulation ratio for regulator circuit. The relationship between regulation ratio and RR[2:0] is shown below. RR2 RR1 RR0 1+Rb/Ra 000 3.0 001 3.5 010 4.0 011 4.5 100 5.0 101 5.5 110 6.0 111 6.5 Table 6. Relationship between Regulation Ratio and RR[2:0] External Resistor Is Used For Regulator Circuit Through hardware setting IRS=”L” and external resistor, ST7565R is able to use external regulation ratio to control the voltage level of V0. External Ra' VEV (Constant Voltage Supply + Electronic Volume) VSS V0 External Rb' V0 =(1+ Rb' Ra' ) x VEV = ( 1 + Rb' ) x ( 1 Ra' α 162 ) x VREG α VEV = ( 1 - 162 ) x VREG Fig 13. External Regulation Ratio The setting condition of ST7565R for external regulation ratio is V0=8.0V, α=31 and VREG=2.1V. The current consumption through Ra’ and Rb’ is limited to 5uA. Base on above condition, the relationship of Ra’ and Rb’ is Ra’ + Rb’ = 1.6MΩ. V0 = 1+ R b R a ' '  × 1−  α 162   × VREG 8V = 1 + R b R a ' '  × 1 − 31 162   × 2.1 Ra '+Rb ' = 1.6MΩ (1.1) (1.2) (1.3) Ver 1.9 23/53 2012/04/03 ST7565R According to equation (1.2) and (1.3) R' b = 3.71 R' a R a ' = 340kΩ R b ' = 1260kΩ High Power Mode ST7565R has two kinds of power mode for driving LCD. When HPMB pin is connected to “H” by VDD, ST7565R will enter normal power mode. Normal power mode has lower power consumption for driving. If the panel loading or size is larger, normal power mode may cause display quality to reduce. For improve display quality, ST7565R provides high power mode through connect HPMB pin to “L” by VSS. SITRONIX recommends that whether using high power mode or normal power mode is determined by actually display quality. Besides, if improvement is unsatisfactory after using high power mode, external power supply for LCD driving is necessary. Power System Set The following sections illustrate the connection of typical application. Built-in Booster, Regulator and Follower Circuit are used 1. Built-in regulation ratio is used with x4 step-up 2. VDD Built-in regulation ratio is not used with x4 step-up VSS VDD2 or VSS C1 C1 C1 C1 C2 C2 C2 C2 C2 VDD2 or VSS IRS VDD2 or VSS VOUT CAP3P CAP1N CAP1P CAP2N CAP2P VSS VR V0 V1 V2 V3 V4 CAP4P CAP5P VDD2 or VSS C1 C1 C1 C1 R2 R1 C2 C2 C2 C2 C2 VDD2 or VSS IRS VDD2 or VSS VOUT CAP3P CAP1N CAP1P CAP2N CAP2P VSS VR V0 V1 V2 V3 V4 CAP4P CAP5P Ver 1.9 24/53 2012/04/03 ST7565R Built-in Regulator and Follower Circuit are alone used 1. Built-in regulation ratio is used 2. Built-in regulation ratio is not used Built-in Follower Circuit is alone used VDD VDD2 or VSS External power supply C2 C2 C2 C2 C2 VDD2 or VSS IRS VDD2 or VSS VOUT CAP3P CAP1N CAP1P CAP2N CAP2P VSS VR V0 V1 V2 V3 V4 CAP4P CAP5P Ver 1.9 25/53 2012/04/03 ST7565R Built-in Booster, Regulator and Follower Circuit are not used The optimum values of C1 and C2 are determined by panel loading and actually display quality. The values of capacitor should be determined by user. User should check display quality of used pattern and power stability after capacitor value is determined. The following table is a quick reference for the initial setting. Symbol C1 C2 Type Capacitor for step-up and LCD voltage stabilization Capacitor for LCD voltage stabilization Reference Value (uF) 1.0 ~ 4.7 0.1 ~ 4.7 Ver 1.9 26/53 2012/04/03 ST7565R RESET CIRCUIT Setting RSTB to “L” can initialize internal function. While RSTB is “L”, no instruction except read status can be accepted. RSTB pin must connect to the reset pin of MPU and initialization by RSTB pin is essential before operating. Please note the hardware reset is not same as the software reset. When RSTB becomes “L”, the hardware reset procedure will start. When RESET instruction is executed, the software reset procedure will start. The procedure is listed below: Procedure Hardware Reset Software Reset Display OFF: D=0, all SEGs/COMs output at VSS V X Normal Display: INV=0, AP=0 V X SEG Normal Direction: MX=0 V X Clear Serial Counter and Shift Register (if using Serial Interface) V X Bias Selection: BS=0 V X Booster Level BL=0 V X Exit Power Saving Mode V X Power Control OFF: VB=0, VR=0, VF=0 V X Exit Read-modify-Write mode V V Static Indicator OFF V V Static Indicator Register SIR[1:0]=(0,0) V V Start Line S[5:0]=0 V V Column Address X[7:0]=0 V V Page Address Y[3:0]=0 V V COM Normal Direction: MY=0 V V V0 Regulation Ratio RR[2:0]=(1,0,0) V V EV[5:0]=(1,0,0,0,0,0) V V Exit Test Mode V V After power-on, RAM data are undefined and the display status is “Display OFF”. It’s better to initialize whole DDRAM (ex: fill all 00h or write the display pattern) before turning the Display ON. Besides, the power is not stable at the time that the power is just turned ON. A hardware reset is needed to initialize those internal registers after the power is stable. Ver 1.9 27/53 2012/04/03 ST7565R INSTRUCTION TABLE INSTRUCTION A0 R/W (RWR) D7 D6 Display ON/OFF 0 0 1 0 Set Start Line 0 Set Page Address 0 Set Column Address 0 0 Read Status 0 Write Data 1 Read Data 1 0 0 1 0 1 0 0 0 0 0 0 0 1 BUSY MX 0 D7 D6 1 D7 D6 SEG Direction 0 0 1 0 Inverse Display All Pixel ON Bias Select Read-modify-Write END RESET COM Direction 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Power Control 0 0 0 0 Regulation Ratio Set EV 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Power Save Mode Set 0 0 1 0 0 0 Power Save 0 0 Set Booster 0 0 1 1 0 0 0 0 COMMAND BYTE D5 D4 D3 D2 1 0 1 1 S5 S4 S3 S2 1 1 Y3 Y2 0 1 X7 X6 0 0 X3 X2 D RST 0 0 D5 D4 D3 D2 D5 D4 D3 D2 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 0 MY - 1 0 1 VB 1 0 0 RR2 0 0 0 0 EV5 EV4 EV3 EV2 D1 1 S1 Y1 X5 X1 0 D1 D1 0 1 0 1 0 1 1 - VR RR1 0 EV1 DESCRIPTION D0 D D=1, display ON D=0, display OFF S0 Set display start line Y0 Set page address X4 Set column address (MSB) X0 Set column address (LSB) 0 Read IC Status D0 Write display data to RAM D0 Read display data from RAM Set scan direction of SEG MX MX=1, reverse direction MX=0, normal direction INV INV =1, inverse display INV =0, normal display AP AP=1, set all pixel ON AP=0, normal display BS Select bias setting 0=1/9; 1=1/7 (at 1/65 duty) 0 Column address increment: Read:+0 , Write:+1 0 Exit Read-modify-Write mode 0 Software reset Set output direction of COM - MY=1, reverse direction MY=0, normal direction VF Control built-in power circuit ON/OFF RR0 Select regulation resistor ratio 1 Double command!! Set EV0 electronic volume (EV) level 1 0 1 1 0 MD MD=0, sleep mode MD=1, normal 0 0 0 0 0 0 Compound Command 1 1 1 0 0 0 0 0 Display OFF + All Pixel ON Double command!! 0 0 Set booster level: BL[1:0]=(0,0), x2, x3, x4 BL1 BL0 BL[1:0]=(0,1), x5 BL[1:0]=(1,1), x6 NOP 0 0 1 1 1 0 0 0 1 1 No operation Test 0 0 1 1 1 1 - - - - Do NOT use. Reserved for testing. Note: Symbol “-” means this bit can be “H” or “L”. Ver 1.9 28/53 2012/04/03 ST7565R INSTRUCTION DESCRIPTION Display ON/OFF The D flag selects the display mode. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 1 1 1 D D=1: Normal Display Mode. D=0: Display OFF. All SEGs/COMs output with VSS. Set Start Line This instruction sets the line address of the Display Data RAM to determine the initial display line. The display data of the specified line address is displayed at the top row (COM0) of the LCD panel. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 S5 S4 S3 S2 S1 S0 S5 S4 S3 S2 S1 S0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 1 1 3 : : : : : : : 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Set Page Address Y [3:0] defines the Y address vector address of the display RAM. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 1 Y3 Y2 Y1 Y0 Y3 Y2 Y1 Y0 Page Address 0 0 0 0 Page0 0 0 0 1 Page1 0 0 1 0 Page2 : : : : : 0 1 1 0 Page6 0 1 1 1 Page7 1 0 0 0 Page8 (icon page) Valid Bit D0~ D7 D0~ D7 D0~ D7 : D0~ D7 D0~ D7 D0 Ver 1.9 29/53 2012/04/03 ST7565R Set Column Address The range of column address is 0…131. The parameter is separated into 2 instructions. The column address is increased (+1) after each byte of display data access (read/write). This allows MPU accessing DDRAM content continuously. This feature stops at the end of each page (Column Address “83h”). A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 X7 X6 X5 X4 A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 X3 X2 X1 X0 X7 X6 X5 X4 X3 X2 X1 X0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 1 1 3 : : : : : : : : : 1 0 0 0 0 0 0 1 129 1 0 0 0 0 0 1 0 120 1 0 0 0 0 0 1 1 131 Read Status Read the internal status of ST7565R. The read function is not available in serial interface mode. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 1 BUSY MX D RST 0 0 0 0 Flag BUSY MX D RST Description BUSY=0: Command can be accepted BUSY=1: Command or reset procedure is executed MX=0: Reverse direction (SEG131->SEG0) MX=1: Normal direction (SEG0->SEG131) D=0: Display ON D=1: Display OFF RST=1: During reset (hardware or software reset) RST=0: Normal operation Write Data 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 1 0 Write Data Read Data 8-bit data of Display Data from the RAM location specified by the column address and page address can be read to the microprocessor. The read function is not available in serial interface mode. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 1 1 Read Data Ver 1.9 30/53 2012/04/03 ST7565R SEG Direction A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 0 0 0 MX Flag MX MX=0: Normal direction (SEG0->SEG131) MX=1: Reverse direction (SEG131->SEG0) Description Inverse Display This instruction changes the selected and non-selected voltage of SEG. The display will be inversed (white -> Black, Black -> White) while the display data in the Display Data RAM is never changed. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 0 1 1 INV Flag INV INV=0: Normal display INV =1: Inverse display Description All Pixel ON This instruction will let all segments output the selected voltage and make all pixels turned ON. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 0 1 0 AP Flag AP AP =0: Normal display AP =1: All pixels ON Description Bias Select Select LCD bias ratio of the voltage required for driving the LCD. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 0 0 1 BS Duty 1/65 1/49 1/33 1/55 1/53 BS=0 1/9 1/8 1/6 1/8 1/8 Bias BS=1 1/7 1/6 1/5 1/6 1/6 Reference LCD Bias Voltage (1/65 Duty with 1/9 Bias) Symbol V0 V1 V2 V3 V4 VSS Bias Voltage V0 8/9 x V0 7/9 x V0 2/9 x V0 1/9 x V0 VSS Ver 1.9 31/53 2012/04/03 ST7565R Read-modify-Write This command is used paired with the “END” instruction. Once this command has been input, the display data read operation will not change the column address, but only the display data write operation will increase the column address (X[7:0]+1). This mode is maintained until the END command is input. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as a blanking cursor. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 0 0 0 0 0 * In Read-modify-Write mode, other instructions aside from display data read/write commands can also be used. Read-Modify-Write Page Address Set Column Address Set Read-Modify-Write Cycle Dummy Read Data Read No Modify Data Data Write (at same Address) Finished? Yes Done END When the END command is input, the Read-modify-Write mode is released and the column address returns to the address it was when the Read-modify-Write instruction was entered. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 0 1 1 1 0 RESET This instruction resets Start Line (S[5:0]), Column Address (X[7:0]), Page Address (Y[3:0]) and COM Direction (MY) to their default setting. Please note this instruction is not complete same as hardware reset (RSTB=L) and cannot initialize the built-in power circuit which is initialized by the RSTB pin. The detailed information is in “Section RESET CIRCUIT”. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 0 0 0 1 0 Ver 1.9 32/53 2012/04/03 ST7565R COM Direction This instruction controls the common output status which changes the vertical display direction. The detailed information can be found in Fig 9. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 MY - - - Flag MY MY=0: Normal direction (COM0->COM63) MY=1: Reverse direction (COM63->COM0) Description Power Control This instruction controls the built-in power circuits. Typically, these 3 flags are turned ON at the same time. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 1 VB VR VF Flag VB VR VF VB=0: Built-in Booster OFF VB=1: Built-in Booster ON VR=0: Built-in Regulator OFF VR=1: Built-in Regulator ON VF=0: Built-in Follower OFF VF=1: Built-in Follower ON Description Regulation Ratio This instruction controls the regulation ratio of the built-in regulator. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 RR2 RR1 RR0 RR2 0 0 0 0 1 1 1 1 RR1 0 0 1 1 0 0 1 1 RR0 0 1 0 1 0 1 0 1 Regulation Ratio (RR) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 The operation voltage (V0) calculation formula is shown below: (RR comes from Regulation Ratio, EV comes from EV[5:0]) V0 = RR X [ 1 – (63 – EV) / 162 ] X 2.1, or V0 = RR X [ ( 99 + EV ) / 162 ] X 2.1 SYMBOL RR EV REGISTER RR[2:0] EV[5:0] VALUE 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0 and 6.5 0~63 Ver 1.9 33/53 2012/04/03 ST7565R Set EV This is double byte instruction. The first byte set ST7565R into EV adjust mode and the following instruction will change the EV setting. That means these 2 bytes must be used together. They control the electronic volume to adjust a suitable V0 voltage for the LCD. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 EV5 EV4 EV3 EV2 EV1 EV0 Electronic Volume Set Set EV (byte-1) (0x81) Set EV (byte-2) (depends on requirement) No Set Complete? Yes Done The maximum voltage that can be generated is dependent on the VDD2 voltage and the loading of LCD module. There are 8 V0 voltage curve can be selected. It is recommended the EV should be close to the center (1FH) for easy contrast adjustment. Please refer to the “Selection of Application Voltage” section for detailed information. Ver 1.9 EV[5:0] and RR[2:0] vs. V0 Voltage Fig 21 Setting V0 Voltage 34/53 2012/04/03 ST7565R Power Save Mode Set This is double byte instruction to set power save mode. This instruction used to set mode of power save only. ST7565R can not enter sleep mode after this instruction is executed. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 1 1 0 MD 0 0 0 0 0 0 0 0 0 0 Flag MD MD=0: Sleep Mode MD=1: Normal Mode Description Power Save (Compound Instruction) This is compound instruction. The 1st instruction is Display OFF (D=0) and the 2nd instruction is All Pixel ON (AP=1). The Power Save mode starts the following procedure: (the display data and register settings are still kept except D-Flag and AP-Flag) 1. Stops internal oscillation circuit; 2. Stops the built-in power circuits; 3. Stops the LCD driving circuits and keeps the common and segment outputs at VSS. Power Save Mode Set Preceding Command Set Following Command Set No Set Complete? Yes Done Fig 21 Power Save Mode Set Procedure Exit Sleep Mode Enter Sleep Mode Normal Mode Power Save Mode Set (Sleep Mode) Display OFF Display all points ON Power Save Display all points OFF Power Save Mode Set (Normal Mode) Normal Mode (Exit Power Save) Fig 21 Power Save Procedure After exiting Power Save, the settings will return to be as they were before. Ver 1.9 35/53 2012/04/03 ST7565R Set Booster This is double byte instruction. The first byte set ST7565R into booster configuration mode and the following instruction will change the booster setting. That means these 2 bytes must be used together. They control the built-in booster circuit to provide the power source of the built-in regulator. Hardware connection should be changed according to booster level setting. If the hardware connection and software setting is not corresponding, ST7565R will cause extra power consumption. ST7565R will not damage through the extra power consumption. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 BL1 BL0 BL1 BL0 0 0 0 1 1 1 Boost Level X2, x3, x4 x5 x6 Booster Ratio Set Set Booster (byte-1) (F8H) Set Booster (byte-2) (depends on requirement) No Set Complete? Yes Done NOP “No Operation” instruction. ST7565R will do nothing when receiving this instruction. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 0 0 0 1 1 Test The test mode is reserved for IC testing. Please don’t use this instruction. If the test mode is enabled accidentally, it can be cleared by: issuing an “L” pulse on RSTB pin, issuing RESET instruction or issuing NOP instruction. A0 R/W(RWR) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 1 - - - - Note: “-” means “1” or “0”. Ver 1.9 36/53 2012/04/03 ST7565R OPERATION FLOW This section introduces some reference operation flows. Power ON RRReeefffeeerrreeennntttiiiaaalllOOOpppeeerrraaatttiiiooonnnFFFlllooowww OOOpppeeerrraaatttiiiooonnnSSSeeeqqquuueeennnccceee Case 1: RSTB=L while Power ON Case 2: RSTB=H while Power ON VDD1 * 50% VDDI (VDD1) VDDA (VDD2,VDD3) VDD1 * 90% tON-V2 VDD2 * 50% VDD2 * 90% RSTB tRW tON-RST VIL Note: The detailed description can be found in the respective sections listed below. 1. Please refer to the timing specification of tRW and tR. 2. Refer to Section RESET CIRCUIT. 3. The 5ms requirement depends on the characteristics of LCD panel and the external component of the power circuit. It is recommended to check with the real products with external component. 4. The detailed instruction functionality is described in Section INSTRUCTION DESCRIPTION; 5. Power stable is defined as the time that the later power (VDDI or VDDA) reaches 90% of its rated voltage. Timing Requirement: Item Symbol Requirement Note VDDA power delay tON-V2 0 ≤ tON-V2 Applying VDDI and VDDA in any order will not damage IC. If RSTB is Low, High or unstable during power ON, a successful hardware reset by RSTB is required after VDDI is stable. RSTB input time tON-RST No Limitation RSTB=L can be input at any time after power is stable. tRW & tR should match the timing specification of RSTB. To prevent abnormal display, the recommended timing is: 0 ≤ tON-RST ≤ 30 ms. The requirement listed here is to prevent abnormal display on LCD module. Ver 1.9 37/53 2012/04/03 ST7565R Display Data Notes: Reference items 1. The detailed instruction functionality is described in Section INSTRUCTION DESCRIPTION; 2. It is recommended to write display data (initialize DDRAM) before Display ON. Refresh It is recommended to use the refresh sequence regularly in a specified interval. Refresh Flow Use Reset command or NOP command Set all commands to the ready state Refresh DDRAM Ver 1.9 38/53 2012/04/03 ST7565R Power-Save Flow and Sequence POWER SAVE MODE SET PROCEDURE Power Save Mode Set Preceding Command Set Following Command Set No Set Complete? Yes Done Exit Sleep Mode Enter Sleep Mode POWER SAVE PROCEDURE Normal Mode Power Save Mode Set (Sleep Mode) Display OFF Display all points ON Power Save Display all points OFF Power Save Mode Set (Normal Mode) Normal Mode (Exit Power Save) Ver 1.9 39/53 2012/04/03 ST7565R Power OFF Flow and Sequence In power save mode, LCD outputs are fixed to VSS and all analog outputs are discharged. The power can be turned OFF after ST7565R is in the power save mode. The power save mode can be triggered by the following two methods. RRReeefffeeerrreeennntttiiiaaalllPPPooowwweeerrrOOOFFFFFFFFFlllooowww OOOpppeeerrraaatttiiiooonnnSSSeeeqqquuueeennnccceee CASE 1: Use Power Save Instruction Data AEH A5H Power Sequence /WR VDDA (VDD2) VDD1, RSTB VOUT V0 V1 V2 V3 V4 Vss Instruction Flow COM, SEG After the built-in power circuits are OFF and completely discharged (the power level of built-in analog circuit is smaller than VTH of LCD panel), the power (VDDI, VDDA) can be removed. VTH is around 0.2V to 1.0V. CASE 2: Use Hardware Reset Function Normal Mode tPFall Turn Off VDD2 after discharge complete tPOFF tV2OFF VTH Vss If VDD1/VDD2<1V, internal status can NOT be guaranteed VDD1/VDD2 is gone, the outputs can NOT be guaranteed Set RSTB=L (wait > tRW) Set RSTB=H Wait 250ms Turn VDD1~VDD2 OFF Power OFF Power OFF Flow Instruction Flow After the built-in power circuits are OFF and completely discharged (the power level of built-in analog circuit is smaller than VTH of LCD panel), the power (VDDI, VDDA) can be removed. VTH is around 0.2V to 1.0V. Note: 1. tPOFF: Internal Power discharge time. Discharge time for built-in circuit is dependent on user’s system design. 2. tV2OFF: Period between VDDI and VDDA OFF time. => 0 ms (min). 3. It is NOT recommended to turn VDDI OFF before VDDA. Without VDDI, the internal status cannot be guaranteed and internal discharge-process maybe stopped. The un-discharged power maybe flows into COM/SEG output(s) and the liquid crystal in panel maybe polarized. 4. IC will NOT be damaged if either VDDI or VDDA is OFF while another is ON. 5. The timing is dependent on panel loading and the external capacitor(s). Ver 1.9 40/53 2012/04/03 ST7565R LIMITING VALUES In accordance with the Absolute Maximum Rating System; please refer to notes 1 and 2. Parameter Symbol Conditions Unit Digital Power Supply Voltage VDD -0.3 ~ 3.6 V Analog Power supply voltage VDD2 -0.3 ~ 3.6 V LCD Power supply voltage VOUT, V0 -0.3 ~ 13.5 V LCD Power supply voltage Operating temperature Storage temperature V1, V2, V3, V4 TOPR TSTR -0.3 ~ V0 V –25 to +80 °C –55 to +125 °C Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure the voltage levels of VOUT, V0, V1, V2, V3, V4 and VSS always match the correct relation: VOUT ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS Ver 1.9 41/53 2012/04/03 ST7565R HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. DC CHARACTERISTICS VSS=0V; Tamb = -30°C to +85°C; unless otherwise specified. Item Symbol Condition Operating Voltage (1) Operating Voltage (2) VDD VDD2 Input High-level Voltage VIHC Input Low-level Voltage Output High-level Voltage Output Low-level Voltage Input Leakage Current VILC VOHC VOLC ILI IOUT=1mA, VDD=1.8V IOUT=-1mA, VDD=1.8V Output Leakage Current External Step-up Voltage Cicuit Supply Voltage Regulator Circuit Supply Voltage Follower Circuit Reference Voltage Liquid Crystal Driver ON Resistance Internal Oscillator External Oscillator Oscillator Frequency Internal Oscillator External Oscillator ILO VOUT VOUT V0 VRS RON fOSC fCL fOSC fCL Ta=25°C Ta=25°C V0=13V V0=8V 1/65 Duty Ta=25°C 1/33 Duty 1/49 Duty 1/53 Duty Ta=25°C 1/55 Duty Min. 2.4 2.4 Rating Typ. — — Max. 3.3 3.3 0.8 x VDD — VDD VSS — 0.2 x VDD 0.8 x VDD — VDD VSS — 0.2 x VDD -1.0 — 1.0 -3.0 — 3.0 Applicable Unit Pin V VDD V VDD2 MPU V Interface MPU V Interface V D[7:0] V D[7:0] MPU µA Interface MPU µA Interface — — 13.5 V VOUT 6.0 — 13.5 V VOUT 4.0 — 13.5 V V0 2.07 2.10 2.13 — 2.0 3.5 — 3.2 5.4 V VRS KΩ COMx KΩ SEGx 17 20 24 kHz 17 20 24 kHz CL 25 30 35 kHz 25 30 35 kHz CL Ver 1.9 42/53 2012/04/03 ST7565R Current consumption: During Display, without internal power system, current consumed by whole IC (bare die). Test Pattern Symbol Condition Min. Rating Typ. Unit Max. Display Pattern: SNOW ISS (Static) VDD=VDD2 =3.0V, V0=11.0V, Ta=25°C — 19 32 µA VDD=VDD2 =3.0V, Display OFF ISS V0=11.0V, Ta=25°C — 16 27 uA Note Current consumption: During Display, with internal power system, current consumed by whole IC (bare die). Test Pattern Symbol Condition Min. Rating Typ. Unit Max. Note Display Pattern: SNOW ISS VDD=VDD2 =3.0V, V0=11.0V, Booster=x4, Ta=25°C Normal — 100 147 uA Mode High Power — 135 205 uA Mode Display OFF Normal VDD=VDD2 =3.0V, — 90 130 uA Mode ISS V0=11.0V, Booster=x4, Ta=25°C High Power — 128 193 uA Mode Sleep Mode ISS VDD=VDD2 =3.0V, Ta=25°C — 0.4 4 uA Note: The Current Consumption is DC characteristics The relationship between oscillator frequency fOSC, display clock frequency fCL and liquid crystal frame rate frequency fFR Item fCL fFR 1/65 Duty Internal Oscillator Circuit External Display Clock fOSC / 4 External Display Clock (fCL) fOSC / 4 / 65 fCL / 260 1/49 Duty Internal Oscillator Circuit External Display Clock fOSC / 8 External Display Clock (fCL) fOSC / 4 / 49 fCL / 196 1/33 Duty Internal Oscillator Circuit External Display Clock fOSC / 8 External Display Clock (fCL) fOSC / 4 / 33 fCL / 264 1/55 Duty Internal Oscillator Circuit External Display Clock fOSC / 8 External Display Clock (fCL) fOSC / 4 / 55 fCL / 220 1/53 Duty Internal Oscillator Circuit External Display Clock fOSC / 8 External Display Clock (fCL) fOSC / 4 / 53 fCL / 212 Ver 1.9 43/53 2012/04/03 ST7565R TIMING CHARACTERISTICS System Bus Timing for 6800 Series MPU Item Address setup time Address hold time System cycle time Enable L pulse width (WRITE) Enable H pulse width (WRITE) Enable L pulse width (READ) Enable H pulse width (READ) Write data setup time Write data hold time Read data access time Read data output disable time Signal A0 E D[7:0] Symbol tAW6 tAH6 tCYC6 tEWLW tEWHW tEWLR tEWHR tDS6 tDH6 tACC6 tOH6 Condition CL = 100 pF CL = 100 pF (VDD = 3.3V , Ta =25°C) Min. Max. Unit 0 — 0 — 240 — 80 — 80 — 80 — ns 140 40 — 10 — — 70 5 50 (VDD = 2.7V , Ta =25°C) Item Signal Symbol Condition Min. Max. Unit Address setup time Address hold time tAW6 A0 tAH6 0 — 0 — System cycle time tCYC6 400 — Enable L pulse width (WRITE) tEWLW 220 — Enable H pulse width (WRITE) E tEWHW 180 — Enable L pulse width (READ) tEWLR 220 — ns Enable H pulse width (READ) tEWHR 180 — Write data setup time tDS6 40 — Write data hold time Read data access time D[7:0] tDH6 tACC6 CL = 100 pF 0 — — 140 Read data output disable time tOH6 CL = 100 pF 10 100 *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between CS1B being “L” (CS2=“H”) and E. Ver 1.9 44/53 2012/04/03 ST7565R System Bus Timing for 8080 Series MPU Item Address setup time Address hold time System cycle time /WR L pulse width (WRITE) /WR H pulse width (WRITE) /RD L pulse width (READ) /RD H pulse width (READ) WRITE Data setup time WRITE Data hold time READ access time READ Output disable time Signal A0 /WR RD D[7:0] Symbol tAW8 tAH8 tCYC8 tCCLW tCCHW tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 Condition CL = 100 pF CL = 100 pF (VDD = 3.3V , Ta =25°C) Min. Max. Unit 0 — 0 — 240 — 80 — 80 — 140 — ns 80 40 — 20 — — 70 5 50 (VDD = 2.7V , Ta =25°C) Item Signal Symbol Condition Min. Max. Unit Address setup time Address hold time tAW8 A0 tAH8 0 — 0 — System cycle time tCYC8 400 — /WR L pulse width (WRITE) /WR tCCLW 220 — /WR H pulse width (WRITE) tCCHW 180 — /RD L pulse width (READ) /RD H pulse width (READ) tCCLR RD tCCHR 220 — ns 180 — WRITE Data setup time tDS8 40 — WRITE Data hold time READ access time D[7:0] tDH8 tACC8 CL = 100 pF 0 — — 140 READ Output disable time tOH8 CL = 100 pF 10 100 *1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr + tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified. *2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between CS1B being “L” (CS2=“H”) and WR and RD being at the “L” level. Ver 1.9 45/53 2012/04/03 ST7565R System Bus Timing for 4-Line Serial Interface Item Serial clock period SCLK “H” pulse width SCLK “L” pulse width Address setup time Address hold time Data setup time Data hold time CS-SCLK time CS-SCLK time Signal SCLK A0 SDA CS1B CS2 Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Item Signal Symbol Condition Serial clock period tSCYC SCLK “H” pulse width SCLK tSHW SCLK “L” pulse width tSLW Address setup time Address hold time tSAS A0 tSAH Data setup time Data hold time SDA tSDS tSDH CS-SCLK time CS1B tCSS CS-SCLK time CS2 tCSH *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard. (VDD = 3.3V , Ta =25°C) Min. Max. Unit 50 — 25 — 25 — 20 — 10 — ns 20 — 10 — 20 — 40 — (VDD = 2.7V , Ta =25°C) Min. Max. Unit 100 — 50 — 50 — 30 — 20 — ns 30 — 20 — 30 — 60 — Ver 1.9 46/53 2012/04/03 ST7565R Hardware Reset Timing RSTB Internal Status Item Reset time Reset “L” pulse width Item Reset time Reset “L” pulse width t RW t R During Reset ... Reset Finished Symbol tR tRW Symbol tR tRW Condition Condition (VDD = 3.3V , Ta =25°C) Min. Max. Unit — 1.0 us 1.0 — (VDD = 2.7V , Ta =25°C) Min. Max. Unit — 2.0 us 2.0 — Ver 1.9 47/53 2012/04/03 ST7565R APPLICATION NOTE Application Circuits Ver 1.9 48/53 2012/04/03 ST7565R Ver 1.9 49/53 2012/04/03 ST7565R Ver 1.9 50/53 2012/04/03 ST7565R Recommend LCD Setting Duty 1/65 1/55 1/53 VDD/VDD2 3.0 C1 1.0uF~2.2uF C2 0.1uF~1.0uF 3.0 1.0uF~2.2uF 0.1uF~1.0uF 3.0 1.0uF~2.2uF 0.1uF~1.0uF 1/49 3.0 1.0uF~2.2uF 0.1uF~1.0uF 1/33 3.0 1.0uF~2.2uF 0.1uF~1.0uF Booster x4 x4 x4 x3 x4 x3 x4 x3 x3 x3 BIAS 1/9 1/7 1/8 1/6 1/8 1/6 1/8 1/6 1/6 1/5 Vop 8.0V~9.5V 7.0V~8.5V 7.0V~8.5V 6.0V~7.5V 7.0V~8.5V 6.0V~7.5V 7.0V~8.5V 6.0V~7.5V 6.0V~7.5V 5.0V~6.5V Ver 1.9 51/53 2012/04/03 ST7565R REVERSION HISTORY Version Ver 0.1 Ver 0.2 Date 2005/03/24 2005/05/20 Ver 0.3 2005/08/10 Ver 0.4 2005/09/29 Ver 1.0 2005/10/20 Ver 1.1 2005/10/21 Ver 1.2 2005/11/07 Ver 1.3 2005/11/25 Ver 1.4 2006/02/13 Ver 1.5 2006/03/10 Ver 1.6 2007/04/24 Ver 1.6a 2007/05/14 Ver 1.7 Ver 1.7a Ver 1.7b Ver 1.7c Ver 1.8 2007/06/01 2007/07/24 2009/02/23 2009/09/14 2010/08/12 Description Preliminary Bump Height Shipping Forms Pad Arrangement, Bump Height, Bump Pitch, Bump Height Pad Names- remove ”:P”, “:g”, rename FUSE, VSSF as TEST Connections Between LCD Drivers Application Notes Unused Data Pin In 4-Line SPI Fixed To ‘H’ ITO Resister Limitation Modify the Absolute Maximum Ratings. Modify the operating range of VDD, VDD2, VOUT and V0. Modify the description of features. Modify the Operating Temperature. Modify the Ta value of DC Characteristics and Reset Timing. Remove redundant features on Page 2. Remove Preliminary Modify the Pad Arrangement(COG) on Page 2. Modify the I/O PIN ITO Resister Limitation on Page 22. Modify the Operating Temperature Unused Data Pin In 4-Line C86 Fixed To ‘H’ Unused Data Pin In 4-Line /RD Fixed To ‘H’ Unused Data Pin In 4-Line /WR Fixed To ‘H’ Modify the flow chart on Page 46, 47 and 49. Modify the description of DC characteristics. Modify function description. Redraw figures. Redraw the PAD DIAGRAM. Highlight the HPM (High Power Mode) description. Put emphasis on the power OFF procedure (Page 54-55). Fix Ver. 1.4: Booster Circuit mistake (Booster X6, Page 32). Add V0 capacitor notes. Add application notes. Modify ITO resistance limitation. Modify operation voltage. Add a section for “Recommend LCD Setting”. Modify the recommend setting of “Recommend LCD Setting”. Remove slave function. Remove static indicator function. Modify version mark mistake. Modify mistake of Status Read. Modify the mistake of The Reset Circuit. Modify the mistake of Application Circuit. Ver 1.9 52/53 2012/04/03 ST7565R Version Ver 1.9 Date 2012/04/03 Modify SPEC style Modify bump height. Description Ver 1.9 53/53 2012/04/03

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