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三星NAND闪存规格书 K9F4G08U0D

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标签: 三星闪存K9F4F08U0D

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Rev02 May 2010 K9F4G08U0D K9K8G08U0D K9K8G08U1D K9WAG08U1D Advance 4Gb Ddie NAND Flash SingleLevelCell 1bitcell datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS INFORMATION AND SPECIFICATIONS WITHOUT NOTICE Products and specifications discussed herein are for reference purposes only All information discussed herein is provided on an AS IS basis without warranties of any kind This document and all information discussed herein remain the sole and exclusive property of Samsun......

Rev.0.2, May. 2010 K9F4G08U0D K9K8G08U0D K9K8G08U1D K9WAG08U1D Advance 4Gb D-die NAND Flash Single-Level-Cell (1bit/cell) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved. - 1 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D Revision History datasheet Advance Rev. 0.2 FLASH MEMORY Revision No. History 0.0 0.1 0.2 1. Initial issue 1. Corrected errata. 2. Chapter 1.2 Features revised. 1. DDP/QDP Part ID are added. Draft Date Remark Editor Jan. 12, 2010 Advance - May. 03, 2010 Advance H.K.Kim May. 26, 2010 Advance H.K.Kim The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. - 2 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY Table Of Contents 1.0 INTRODUCTION ........................................................................................................................................................4 1.1 General Description................................................................................................................................................. 4 1.2 Features .................................................................................................................................................................. 4 1.3 PRODUCT LIST ...................................................................................................................................................... 4 1.4 Pin Configuration (TSOP1)...................................................................................................................................... 5 1.4.1 PACKAGE DIMENSIONS ................................................................................................................................. 5 1.5 Pin Configuration (TSOP1)...................................................................................................................................... 6 1.5.1 PACKAGE DIMENSIONS ................................................................................................................................. 6 1.6 Pin Description ........................................................................................................................................................ 7 2.0 PRODUCT INTRODUCTION......................................................................................................................................9 2.1 Absolute Maximum Ratings..................................................................................................................................... 10 2.2 Recommended Operating Conditions ..................................................................................................................... 10 2.3 DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.) ..................10 2.4 Valid Block............................................................................................................................................................... 11 2.5 Ac Test Condition .................................................................................................................................................... 11 2.6 Capacitance(TA=25°C, VCC=3.3V, f=1.0MHz)....................................................................................................... 11 2.7 Mode Selection........................................................................................................................................................ 11 2.8 Program / Erase Characteristics ........................................................................................................................12 2.9 AC Timing Characteristics for Command / Address / Data Input ............................................................................ 12 2.10 AC Characteristics for Operation........................................................................................................................... 13 3.0 NAND Flash Technical Notes ....................................................................................................................................14 3.1 Initial Invalid Block(s)............................................................................................................................................... 14 3.2 Identifying Initial Invalid Block(s) ............................................................................................................................. 14 3.3 Error in write or read operation................................................................................................................................ 15 3.4 Addressing for program operation ........................................................................................................................... 17 3.5 System Interface Using CE don’t-care. ................................................................................................................... 18 4.0 TIMING DIAGRAMS ..................................................................................................................................................19 4.1 Command Latch Cycle ........................................................................................................................................... 19 4.2 Address Latch Cycle............................................................................................................................................... 19 4.3 Input Data Latch Cycle ........................................................................................................................................... 20 4.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)..................................................................................... 20 4.5 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) .................................................................... 21 4.6 Status Read Cycle.................................................................................................................................................. 21 4.7 Read Operation ...................................................................................................................................................... 22 4.8 Read Operation(Intercepted by CE) ....................................................................................................................... 22 4.9 Random Data Output In a Page ............................................................................................................................. 23 4.10 Page Program Operation...................................................................................................................................... 24 4.11 Page Program Operation with Random Data Input .............................................................................................. 25 4.12 Copy-Back Program Operation ............................................................................................................................ 26 4.13 Copy-Back Program Operation with Random Data Input..................................................................................... 27 4.14 Two-Plane Page Program Operation ................................................................................................................... 28 4.15 Block Erase Operation.......................................................................................................................................... 29 4.16 Two-Plane Block Erase Operation ....................................................................................................................... 30 4.17 Read ID Operation................................................................................................................................................ 31 5.0 DEVICE OPERATION ................................................................................................................................................33 5.1 Page Read............................................................................................................................................................... 33 5.2 Page Program ......................................................................................................................................................... 34 5.3 Copy-back Program................................................................................................................................................. 35 5.4 Block Erase ............................................................................................................................................................. 36 5.5 Two-plane Page Program........................................................................................................................................ 36 5.6 Two-plane Block Erase............................................................................................................................................ 37 5.7 Two-plane Copy-back Program............................................................................................................................... 37 5.8 Read Status............................................................................................................................................................. 39 5.9 Read ID ................................................................................................................................................................... 40 5.10 Reset ..................................................................................................................................................................... 40 5.11 Ready/Busy ........................................................................................................................................................... 41 5.12 Data Protection & Power Up Sequence ................................................................................................................ 42 - 3 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 1.0 INTRODUCTION 1.1 General Description Offered in 512Mx8bit, the K9F4G08U0D is a 4G-bit NAND Flash Memory with spare 128M-bit. The device is offered in 3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250μs on the (2K+64)Byte page and an erase operation can be performed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F4G08U0D′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F4G08U0D is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requir- ing non-volatility. 1.2 Features • Voltage Supply - 3.3V Device(K9F4G08U0D) : 2.7V ~ 3.6V • Organization - Memory Cell Array : (512M + 16M) x 8bit - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 25μs(Max.) - Serial Access : 25ns(Min.) • Fast Write Cycle Time - Page Program time : 250μs(Typ.) - Block Erase Time : 2ms(Typ.) 1.3 PRODUCT LIST Part Number K9F4G08U0D-S K9K8G08U0D-S K9K8G08U1D-S K9WAG08U1D-S • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - ECC Requirement : 1bit/528Byte - Endurance & Data Retention : Please refer to the qualification report • Command Register Operation • Unique ID for Copyright Protection • Package : - K9F4G08U0D-SCB0/SIB0 : Pb-FREE, Halogen-FREE PACKAGE 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) - K9K8G08U0D-SCB0/SIB0 : Pb-FREE, Halogen-FREE PACKAGE 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) - K9K8G08U1D-SCB0/SIB0 : Pb-FREE, Halogen-FREE PACKAGE 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) - K9WAG08U1D-SCB0/SIB0 : Pb-FREE, Halogen-FREE PACKAGE 48 - Pin TSOP1 (12 x 20 / 0.5 mm pitch) Vcc Range Organization PKG Type 2.70 ~ 3.60V X8 TSOP1 - 4 - K9F4G08U0D K9K8G08U1D K9K8G08U0D K9WAG08U1D datasheet Advance Rev. 0.2 FLASH MEMORY 1.4 Pin Configuration (TSOP1) K9F4G08U0D-SCB0/SIB0 K9K8G08U0D-SCB0/SIB0 48-pin TSOP1 Standard Type 12mm x 20mm N.C N.C N.C N.C N.C N.C R/B1 RE CE1 N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C 1.4.1 PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220F Unit :mm/Inch 20.00±0.20 0.787±0.008 #1 . 7 0 0 + 3 0 0 - . 0 2 . 0 3 0 0 . 0 + . 1 0 0 0 - 8 0 0 . 0 7 9 1 0 . 0 5 . 0 0 #24 P Y T 5 2 . 0 0 1 0 . 0 0~8° 0.45~0.75 0.018~0.030 18.40±0.10 0.724±0.004 X A M 0 1 . 0 4 0 0 . 0 #48 #25 5 7 0 . 0 + 5 3 0 . 0 5 2 1 . 0 3 0 0 . 0 + 1 0 0 . 0 - 5 0 0 . 0 ) 5 2 . 0 0 1 0 . 0 ( X A M 0 4 . 2 1 8 8 4 . 0 0 0 . 2 1 2 7 4 . 0 0.05 MIN 0.002 1.00±0.05 0.039±0.002 1.20 MAX 0.047 ( 0.50 0.020 ) - 5 -
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