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《设计与验证VerilogHDL》源码实例 和 Verilog规范

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标    签: VerilogHDL源码实例Verilog规范

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《设计与验证VerilogHDL》源码实例 和 Verilog规范,代码,说明文档

文件列表

.BMP
----|000005.BMP
----|000010.BMP
----|000024.BMP
----|000025.BMP
----|000027.BMP
----|000039.BMP
----|000059.BMP
----|000068.BMP
----|000074.BMP
----|000078.BMP
----|000092.BMP
----|000108.BMP
----|000109.BMP
----|000113.BMP
----|000122.BMP
----|Thumbs.db
.dep
----|lcd_lib.o.d
----|main.o.d
----|twi_i2c.o.d
.deps
----|ControlResource.Po
----|DCU99Editor.Po
----|DuplexEditor.Po
.eclipseme.tmp
----|emulation
----|----|PhoneBook.jad
----|----|PhoneBook.jar
verified
----|classes
----|----|com
----|----|----|north
----|----|----|----|phonebook
----|----|----|----|----|model
----|----|----|----|----|----|Account.class
----|----|----|----|----|----|ApplicationException.class
----|----|----|----|----|----|Index.class
----|----|----|----|----|----|Model$AccountFilter.class
----|----|----|----|----|----|Model$IndexFilter.class
----|----|----|----|----|----|Model.class
----|----|----|----|----|----|Preference.class
----|----|----|----|----|----|UserModel.class
ui
----|ConfirmationDialog.class
----|DetailInfoUI.class
----|Dialog.class
----|DialogListener.class
----|IndexFunctionUI$ListIndex.class
----|IndexFunctionUI.class
----|ListMerchantGroupUI.class
----|ListPhoneUI.class
----|LoginUI.class
----|MerchantGroupDetailInfoUI.class
----|NewPhoneUI.class
----|SearchPhoneUI.class
----|Title.class
----|UIController$1.class
----|UIController$EventID.class
----|UIController.class
----|WaitCanvas$1.class
----|WaitCanvas.class
----|WelcomeUI.class
PhoneBookMIDlet.class
.myeclipse
----|CVS
----|----|Repository
----|----|Root
.settings
----|CVS
----|----|Entries
----|----|Repository
----|----|Root
org.eclipse.core.resources.prefs
.svn
----|prop-base
props
text-base
----|readme.txt.svn-base
tmp
----|prop-base
props
text-base
all-wcprops
dir-prop-base
entries
format
.tmp_versions
----|dw4002.mod
Example-4-20
----|case
----|----|PrecisionRTL
----|----|----|case_impl_1
----|----|----|----|rtlc.out
----|----|----|----|----|EXEM_MACRO_DIR
INCR
----|AREA
emptymod.list
hier.list
incr_driver.log
incr_rtlc.log
MEM
NET
NM
depend
----|TOPMODULE.list
.rtlc_compile
.top
autotop.conf
legalmodmap.db
rtlc.args
rtlc_args1.file
vmw.mem_contents
rtlc_libs
----|work
----|----|case1.mod
----|----|case1.mod.body
----|----|rtlc_version_info
case1.edf
case1.prf
case1.xdb
case1_area.rep
case1_con_rep.sdc
case1_rtl.ixdb
case1_tech_con_rep.sdc
case1_timing.rep
case_impl_1.psi
hdlAnalyze_verilogfile
precision.log
precision_rtl.sdc
precision_tech.sdc
unfolded_operators.txt
Thumbs.db
case.psp
case_RTL_schematic.bmp
case_schematic.bmp
SynplifyPro
----|rev_2
----|----|par_1
syntmp
----|case1.msg
----|case1.plg
AutoConstraint_case1.sdc
case1.edn
case1.fse
case1.prf
case1.srm
case1.srr
case1.srs
case1.tlg
generic.fse
generic.srd
Thumbs.db
case1.prd
case1.prj
case_rtl_view.bmp
case_tech_view.bmp
case1.v
syntmp.msg
decode
----|case
----|----|decode_case_impl_1
----|----|----|rtlc.out
----|----|----|----|EXEM_MACRO_DIR
INCR
----|AREA
emptymod.list
hier.list
incr_driver.log
incr_rtlc.log
MEM
NET
NM
depend
----|TOPMODULE.list
.rtlc_compile
.top
autotop.conf
legalmodmap.db
rtlc.args
rtlc_args1.file
vmw.mem_contents
rtlc_libs
----|work
----|----|case_decode.mod
----|----|case_decode.mod.body
----|----|rtlc_version_info
case_decode.edf
case_decode.prf
case_decode.xdb
case_decode_area.rep
case_decode_con_rep.sdc
case_decode_rtl.ixdb
case_decode_tech_con_rep.sdc
case_decode_timing.rep
decode_case_impl_1.psi
hdlAnalyze_verilogfile
precision.log
precision_rtl.sdc
precision_tech.sdc
unfolded_operators.txt
rev_1
----|syntmp
----|----|case_decode.msg
----|----|case_decode.plg
AutoConstraint_case_decode.sdc
case_decode.edn
case_decode.fse
case_decode.prf
case_decode.srm
case_decode.srr
case_decode.srs
case_decode.tlg
generic.fse
generic.srd
case_decode.v
decode_case.psp
precision_RTL_schematic.bmp
precision_schematic.bmp
synplify.prd
synplify.prj
synplify_rtl_view.bmp
synplify_tech_view.bmp
if_mult
----|precision_impl_1
----|----|rtlc.out
----|----|----|EXEM_MACRO_DIR
INCR
----|AREA
emptymod.list
hier.list
incr_driver.log
incr_rtlc.log
MEM
NET
NM
depend
----|TOPMODULE.list
.rtlc_compile
.top
autotop.conf
legalmodmap.db
rtlc.args
rtlc_args1.file
vmw.mem_contents
rtlc_libs
----|work
----|----|if_mult_decode.mod
----|----|if_mult_decode.mod.body
----|----|rtlc_version_info
hdlAnalyze_verilogfile
if_mult_decode.edf
if_mult_decode.prf
if_mult_decode.xdb
if_mult_decode_area.rep
if_mult_decode_con_rep.sdc
if_mult_decode_rtl.ixdb
if_mult_decode_tech_con_rep.sdc
if_mult_decode_timing.rep
precision.log
precision_impl_1.psi
precision_rtl.sdc
precision_tech.sdc
unfolded_operators.txt
rev_2
----|syntmp
----|----|if_mult_decode.msg
----|----|if_mult_decode.plg
AutoConstraint_if_mult_decode.sdc
generic.fse
generic.srd
if_mult_decode.edn
if_mult_decode.fse
if_mult_decode.prf
if_mult_decode.srm
if_mult_decode.srr
if_mult_decode.srs
if_mult_decode.tlg
if_mult_RTL_schematic.bmp
if_mult_decode.prd
if_mult_decode.prj
if_mult_decode.v
if_mult_decode_RTL_veiw.bmp
if_mult_decode_tech_veiw.bmp
if_mult_schematic.bmp
precision.psp
if_single
----|precision_impl_1
----|----|rtlc.out
----|----|----|EXEM_MACRO_DIR
INCR
----|AREA
emptymod.list
hier.list
incr_driver.log
incr_rtlc.log
MEM
NET
NM
depend
----|TOPMODULE.list
.rtlc_compile
.top
autotop.conf
legalmodmap.db
rtlc.args
rtlc_args1.file
vmw.mem_contents
rtlc_libs
----|work
----|----|if_single_decode.mod
----|----|if_single_decode.mod.body
----|----|rtlc_version_info
hdlAnalyze_verilogfile
if_single_decode.edf
if_single_decode.prf
if_single_decode.xdb
if_single_decode_area.rep
if_single_decode_con_rep.sdc
if_single_decode_rtl.ixdb
if_single_decode_tech_con_rep.sdc
if_single_decode_timing.rep
precision.log
precision_impl_1.psi
precision_rtl.sdc
precision_tech.sdc
unfolded_operators.txt
rev_1
----|syntmp
----|----|if_single_decode.msg
----|----|if_single_decode.plg
AutoConstraint_if_single_decode.sdc
generic.fse
generic.srd
if_single_decode.edn
if_single_decode.fse
if_single_decode.prf
if_single_decode.srm
if_single_decode.srr
if_single_decode.srs
if_single_decode.tlg
if_single_RTL_schematic.bmp
if_single_decode.prd
if_single_decode.prj
if_single_decode.v
if_single_decode_RTL_view.bmp
if_single_decode_tech_view.bmp
if_single_schematic.bmp
precision.log
precision.psp
if_mult
----|Latch_if_mult
----|----|rev_2
----|----|----|syntmp
----|----|----|----|latch_mult_if.msg
----|----|----|----|latch_mult_if.plg
AutoConstraint_mult_if.sdc
generic.fse
generic.srd
latch_mult_if.edn
latch_mult_if.fse
latch_mult_if.prf
latch_mult_if.srm
latch_mult_if.srr
latch_mult_if.srs
latch_mult_if.tlg
Latch_Synplify_RTL_view.bmp
Latch_Synplify_tech_view.bmp
latch_if_mult.prd
latch_if_mult.prj
latch_mult_if.v
PrecisionRTL
----|if_mult_impl_1
----|----|rtlc.out
----|----|----|EXEM_MACRO_DIR
INCR
----|AREA
emptymod.list
hier.list
incr_driver.log
incr_rtlc.log
MEM
NET
NM
depend
----|TOPMODULE.list
.rtlc_compile
.top
autotop.conf
legalmodmap.db
rtlc.args
rtlc_args1.file
vmw.mem_contents
rtlc_libs
----|work
----|----|mult_if.mod
----|----|mult_if.mod.body
----|----|rtlc_version_info
hdlAnalyze_verilogfile
if_mult_impl_1.psi
mult_if.edf
mult_if.prf
mult_if.xdb
mult_if_area.rep
mult_if_con_rep.sdc
mult_if_rtl.ixdb
mult_if_tech_con_rep.sdc
mult_if_timing.rep
precision.log
precision_rtl.sdc
precision_tech.sdc
unfolded_operators.txt
Thumbs.db
if_mult.psp
if_mult_RTL_schematic.bmp
if_mult_schematic.bmp
SynplifyPro
----|rev_1
----|----|syntmp
----|----|----|mult_if.msg
----|----|----|mult_if.plg
AutoConstraint_mult_if.sdc
generic.fse
generic.srd
mult_if.edn
mult_if.fse
mult_if.prf
mult_if.srm
mult_if.srr
mult_if.srs
mult_if.tlg
if_mult.prd
if_mult.prj
if_mult_rtl_view.bmp
if_mult_tech_view.bmp
syntmp.msg
latch_mult_if.v
mult_if.v
if_single
----|PrecisionRTL
----|----|if_single_impl_1
----|----|----|rtlc.out
----|----|----|----|EXEM_MACRO_DIR
INCR
----|AREA
emptymod.list
hier.list
incr_driver.log
incr_rtlc.log
MEM
NET
NM
depend
----|TOPMODULE.list
.rtlc_compile
.top
autotop.conf
legalmodmap.db
rtlc.args
rtlc_args1.file
vmw.mem_contents
rtlc_libs
----|work
----|----|rtlc_version_info
----|----|single_if.mod
----|----|single_if.mod.body
hdlAnalyze_verilogfile
if_single_impl_1.psi
precision.log
precision_rtl.sdc
precision_tech.sdc
single_if.edf
single_if.prf
single_if.xdb
single_if_area.rep
single_if_con_rep.sdc
single_if_rtl.ixdb
single_if_tech_con_rep.sdc
single_if_timing.rep
unfolded_operators.txt
Thumbs.db
if_single.psp
if_single_RTL_schemaitc.bmp
if_single_schematic.bmp
SynplifyPro
----|rev_2
----|----|syntmp
----|----|----|single_if.msg
----|----|----|single_if.plg
AutoConstraint_single_if.sdc
generic.fse
generic.srd
single_if.edn
single_if.fse
single_if.prf
single_if.srm
single_if.srr
single_if.srs
single_if.tlg
if_single.prd
if_single.prj
if_single_rtl_view.bmp
if_single_tech_view.bmp
syntmp.msg
single_if.v
. Online calibration of Nyquist-rate analog-to-digital converters.pdf
..dir.dat
._CotEditor_346
._MacOS_Setup
._PortVaR
.actionScriptProperties
.apriori_config
.ccsproject
.classpath
.cproject
.cxl
.depend
.dw4002.ko.cmd
.dw4002.mod.o.cmd
.dw4002.o.cmd
.exe
.flexProperties
.gitignore
.htaccess
.indent.pro
.message
.pdf
.project
.qmake.internal.cache
.screenrc
.synopsys_dc.setup
.synopsys_pt.setup
.untf
.vimrc
.xhdl3.xref

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