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uc3842的介绍

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    www.ti.com UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 SLUS223C – APRIL 1997 – REVISED JUNE 2007 CURRENT MODE PWM CONTROLLER FEATURES • Optimized For Off-line and DC-to-DC Converters • Low Start-Up Current (<1 mA) • Automatic Feed Forward Compensation • Pulse-by-Pulse Current Limiting • Enhanced Load Response Characteristics • Under-Voltage Lockout With Hysteresis • Double Pulse Suppression • High Current Totem Pole Output • Internally Trimmed Bandgap Reference • 500-kHz Operation • Low RO Error Amp DESCRIPTION The UC1842/3/4/5 family of control devices provides the necessary features to implement off-line or dc-to-dc fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include under-voltage lockout featuring start up current less than 1 mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off state. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16 VON and 10 VOFF, ideally suited to off-line applications. The corresponding thresholds for the UC1843 and UC1845 are 8.4 V and 7.6 V. The UC1842 and UC1843 can operate to duty cycles approaching 100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. BLOCK DIAGRAM Vcc 7 12 GROUND 5 9 34 V UVLO 5V S/R REF 2.50 V 47 RT/CT OSC Error Amp VREF Good Logic 2R Internal BIAS T S VFB 2 3 COMP 1 1 CURRENT SENSE 3 5 R R PWM LATCH 1 V CURRENT SENSE COMPARATOR Note 1: A/B A = DIL−8 Pin Number. B = SO−14 and CFP−14 Pin Number. Note 2: Toggle flip flop used only in 1844 and 1845. 8 14 VREF 5V 50 mA 7 11 VC 6 10 OUTPUT 58 POWER GROUND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997–2007, Texas Instruments Incorporated UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 SLUS223C – APRIL 1997 – REVISED JUNE 2007 ABSOLUTE MAXIMUM RATINGS(1) Supply voltage Output current Low impedance source ICC < 30 mA Output energy (capacitive load) Analog inputs (Pins 2, 3) Error amp output sink current Power dissipation Storage temperature range TA≤ 25°C (DIL-8) TA≤ 25°C (SOIC-14) TA≤ 25°C (SOIC-8) Junction temperature range Lead temperature (soldering, 10 seconds) www.ti.com UNIT 30 V Self Limiting ±1 A 5 µJ –0.3 V to 6.3 V 10 mA 1W 725 mW 650 mW –65°C to 150°C –55°C to 150°C 300°C (1) All voltages are with respect to Pin 5. All currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. CONNECTION DIAGRAMS DIL-8, SOIC-8 N or J PACKAGE, D8 PACKAGE (TOP VIEW) COMP 1 VFB 2 ISENSE 3 RT/CT 4 8 VREF 7 VCC 6 OUTPUT 5 GROUND SOIC-14, CFP-14 D or W PACKAGE (TOP VIEW) COMP 1 14 NC 2 13 VFB 3 12 NC 4 11 ISENSE 5 10 NC 6 9 RT/CT 7 8 VREF NC VCC VC OUTPUT GROUND PWR GND NC RT / CT NC PWR GND GROUND PLCC-20 Q PACKAGE (TOP VIEW) NC COMP NC VREF NC 3 2 1 20 19 NC 4 VFB 5 NC 6 18 VCC 17 VC 16 NC ISENSE 7 NC 8 15 OUTPUT 14 NC 9 10 11 12 13 NC − No internal connection 2 Submit Documentation Feedback www.ti.com THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) DIL-8 SOIC-8 SOIC-14 CFP-14 PLCC-20 PACKAGE J N D8 D14 W Q UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 SLUS223C – APRIL 1997 – REVISED JUNE 2007 θJC 28 (1) 25 42 35 5.49°C/W 34 θJA 125-160 110 (2) 84-160 (2) 50-120 (2) 175.4C/W 43-75 (2) (1) θJC data values stated were derived from MIL-STD-1835B. (2) Specified θJA (junction to ambient) is for devices mounted to 5 in2 FR4 PC board with one ounce copper where noted. When resistance range is given, lower values are for 5 in2. Test PWB was 0.062 in thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace widths for non-power packages with 100 x 100-mil probe land area at the end of each trace. DISSIPATION RATINGS PACKAGE W TA≤ 25°C POWER RATING 700 mW DERATING FACTOR ABOVE TA≤ 25°C 5.5 mW/°C TA≤ 70°C POWER RATING 452 mW TA≤ 85°CPO WER RATING 370 mW TA≤ 125°C POWER RATING 150 mW ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for –55°C ≤ TA≤ 125°C for the UC184X; –40°C ≤ TA≤ 85°C for the UC284X; 0°C ≤ TA≤ 70°C for the 384X; VCC = 15 V(1); RT = 10 kΩ; CT = 3.3 nF, TA = TJ. PARAMETER TEST CONDITIONS UC1842/3/4/5 UC2842/3/4/5 MIN TYP MAX UC3842/3/4/5 MIN TYP MAX UNIT REFERENCE SECTION Output Voltage Line Regulation Load Regulation Temp. Stability Total Output Variation Output Noise Voltage Long Term Stability Output Short Circuit TJ = 25°C, IO = 1 mA 12 ≤ VIN≤ 25 V 1 ≤ I0≤ 20 mA See (2) (3) Line, load, tempature (2) 10 Hz≤ f ≤ 10 kHz, TJ = 25°C(2) TA = 125°C, 1000 Hrs(2) 4.95 5.00 5.05 4.90 5.00 5.10 V 6 20 6 25 6 20 mV 6 25 0.2 0.4 0.2 0.4 mV/°C 4.9 5.1 4.82 5.18 V 50 50 µV 5 25 5 25 mV –30 –100 –180 –30 –100 –180 mA OSCILLATOR SECTION Initial Accuracy Voltage Stability Temp. Stability Amplitude TJ = 25°C(4) 12 ≤ VCC≤ 25 V TMIN≤ TA≤ TMAX (2) VPIN 4 peak-to-peak (2) 47 52 57 0.2% 1% 5% 1.7 47 52 0.2% 5% 1.7 57 kHz 1% V (1) Adjust VCC above the start threshold before setting at 15 V. (2) These parameters, although specified, are not 100% tested in production. (3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation: Temp Stability + VREF(max) TJ(max) * * VREF (min) TJ (min) VREF(max) and VREF(min) are the maximum and minimum reference voltages measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature. (4) Output frequency equals oscillator frequency for the UC1842 and UC1843. Output frequency is one half oscillator frequency for the UC1844 and UC1845. Submit Documentation Feedback 3 UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 SLUS223C – APRIL 1997 – REVISED JUNE 2007 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, these specifications apply for –55°C ≤ TA≤ 125°C for the UC184X; –40°C ≤ TA≤ 85°C for the UC284X; 0°C ≤ TA≤ 70°C for the 384X; VCC = 15 V; RT = 10 kΩ; CT = 3.3 nF, TA = TJ. PARAMETER TEST CONDITIONS UC1842/3/4/5 UC2842/3/4/5 MIN TYP MAX UC3842/3/4/5 MIN TYP MAX UNIT ERROR AMP SECTION Input Voltage Input Bias Current VPIN 1 = 2.5 V 2.45 2.50 2.55 2.42 2.50 2.58 V –0.3 –1 –0.3 –2 µA AVOL Unity Gain Bandwidth PSRR Output Sink Current Output Source Current VOUT High VOUT Low CURRENT SENSE SECTION 2 ≤ VO≤ 4 V TJ = 25°C (5) 12 ≤ VCC≤ 25 V VPIN 2 = 2.7 V, VPIN 1 = 1.1 V VPIN 2 = 2.3 V, VPIN 1 = 5 V VPIN 2 = 2.3 V, RL = 15 kΩ to ground VPIN 2 = 2.7 V, RL = 15 kΩ to Pin 8 65 90 65 90 dB 0.7 1 0.7 1 MHz 60 70 60 70 dB 2 6 2 6 mA –0.5 –0.8 –0.5 –0.8 5 6 0.7 1.1 5 6 V 0.7 1.1 Gain See (6) (7) 2.85 3 3.15 2.85 3 3.15 V/V Maximum Input Signal PSRR Input Bias Current VPIN 1 = 5 V (6) 12 ≤ VCC≤ 25 V (5) (6) 0.9 1 1.1 0.9 1 1.1 V 70 70 dB –2 –10 –2 –10 µA Delay to Output OUTPUT SECTION VPIN 3 = 0 V to 2 V (5) 150 300 150 300 ns Output Low Level ISINK = 20 mA ISINK = 200 mA Output High Level ISOURCE = 20 mA ISOURCE = 200 mA Rise Time TJ = 25°C, CL = 1 nF (5) Fall Time TJ = 25°C, CL = 1nF(5) UNDER-VOLTAGE LOCKOUT SECTION 0.1 0.4 0.1 0.4 1.5 2.2 1.5 2.2 V 13 13.5 13 13.5 12 13.5 12 13.5 50 150 50 150 50 150 ns 50 150 Start Threshold Min. Operating Voltage After Turn On X842/4 X843/5 X842/4 X843/5 15 16 17 14.5 16 17.5 7.8 8.4 9.0 7.8 8.4 9.0 V 9 10 11 8.5 10 11.5 7.0 7.6 8.2 7.0 7.6 8.2 PWM SECTION Maximum Duty Cycle X842/3 X844/5 95% 46% 97% 100% 95% 48% 50% 47% 97% 100% 48% 50% Minimum Duty Cycle 0% 0% TOTAL STANDBY CURRENT Start-Up Current Operating Supply Current VCC Zener Voltager VPIN 2 = VPIN 3 = 0 V ICC = 25 mA 0.5 1 11 17 0.5 1 mA 11 17 30 34 30 34 V (5) These parameters, although specified, are not 100% tested in production. (6) Parameter measured at trip point of latch with VPIN 2 = 0. (7) Gain defined as: A + DVPIN DVPIN 1 3 , 0 v VPIN 3 v 0.8 V 4 Submit Documentation Feedback www.ti.com ERROR AMP CONFIGURATION Error amp can source or sink up to 0.5 mA. 2.5 V + UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 SLUS223C – APRIL 1997 – REVISED JUNE 2007 0.5 mA ZI VFB 2 _ COMP ZF 1 UNDER-VOLTAGE LOCKOUT During under-voltage lock-out, the output drive is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents. VCC VCC 7 ON/OFF Command to REST of IC VON VOFF UC1842 UC1844 16 V 10 V UC1843 UC1845 8.4 V 7.6 V <17 mA <1 mA VOFF VON VCC CURRENT SENSE CIRCUIT A small RC filter may be required to suppress switch transients. IS R RS C 5 ERROR AMP COMP 1 CURRENT 3 SENSE GND 5 2R R 1 V CURRENT SENSE COMPARATOR Peak Current (IS) is Determined By The Formula ISMAX ,1.0 V RS Submit Documentation Feedback 5 UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 SLUS223C – APRIL 1997 – REVISED JUNE 2007 OSCILLATOR SECTION VREF 8 RT/CT 4 RT Deadtime vs CT (RT >5 kW) 30 10 CT 3 td − ms GROUND 5 For RT> 5 K f ~ 1.72 RTCT 1 0.3 1 2.2 4.7 10 22 47 100 CT − nF OUTPUT SATURATION CHARACTERISTICS 4 VCC = 15 V RT − (k W) www.ti.com Timing Resistance vs Frequency 100 30 10 3 100 1 k 10 k 100 k 1 M f − Frequency − Hz Saturation Voltage − V 3 TA = 25°C TA = −55°C 2 SOURCE SAT 1 (VCC − VOH) SINK SAT (VOL) 0 .01 .02 .03 .04 .05 .07 .1 .2 .3 .4 .5 .7 1 Output Current, Source or Sink − A ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE Phase Margin − ° Voltage Gain − dB 80 0 60 −45 θ 40 −90 20 −135 Av 0 −180 10 100 1k 10 k 100 k 1M 10 M f − Frequency − Hz 6 Submit Documentation Feedback www.ti.com UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 SLUS223C – APRIL 1997 – REVISED JUNE 2007 OPEN-LOOP LABORATORY FIXTURE High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypas capacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. VREF 4.7 kW 1 kW ERROR AMP ADJUST 4.7 kW 2N2222 100 kW 5 kW ISENSE ADJUST R1 UC1842 1 COMP VREF 8 2 VFB VCC 7 3 ISENSE OUTPUT 6 4 RT / CT GROUND 5 A VCC 0.1 mF 0.1 mF 1 kW 1 W OUTPUT GROUND CT SHUTDOWN TECHNIQUES Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1 V or pull pin 1 below a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this pint the reference turns off, allowing the SCR to reset. 1 kW 8 VREF 1 COMP 330 W SHUTDOWN 500 W 3 ISENSE To Current SENSE RESISTOR SHUTDOWN Submit Documentation Feedback 7 UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5 SLUS223C – APRIL 1997 – REVISED JUNE 2007 www.ti.com OFFLINE FLYBACK REGULATOR R1 5Ω1W 117 VAC VARO VM 68 C1 250 µF 250 V R2 56 kΩ 2W R12 4.7 kΩ 2W C9 3300 pF 600 V NP D4 1N3613 R4 4.7 kΩ R3 20 kΩ D2 1N3612 D3 1N3612 R5 150 kΩ C14 27 1 UC3844 100 pF 8 C5 0.01 µF R6 10 kΩ 4 C6 0.0022 µF 6 3 5 C2 100 µF 25 V C3 22 µF USD1120 R9 68 Ω 3W C4 47 µF 25 V NC R7 22 Ω R8 1 kΩ C7 470 pF R13 20 kΩ T1 D6 L1 U9D946 N5 C10 4700 µF 10 V C11 4700 µF 10 V D7 UF81002 C12 N12 2200 µF 16 V N12 C13 2200 µF 16 V Q1 UFN833 D8 UES1002 C8 680 pF 600 V +6 V COM +12 V ±12 V COM −12 V R10 0.55 Ω 1W D8 1N3613 R11 2.7 kΩ 2W Power Supply Specifications 1. Input Voltages a. 5VAC to 130VA (50 Hz/60 Hz) 2. Line Isolation: 3750 V 3. Switchng Frequency: 40 kHz 4. Efficiency at Full Load 70% 5. Output Voltage: a. +5 V, ±5%; 1A to 4A load Ripple voltage: 50 mV P-P Max b. +12 V, ±3%; 0.1A to 0.3A load Ripple voltage: 100 mV P-P Max c. –12 V, ±3%; 0.1A to 0.3A load Ripple voltage: 100 mV P-P Max SLOPE COMPENSATION A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. VREF 8 RT / CT 4 UC1842/3 ISENSE 3 0.1 mF RT CT R1 R2 C ISENSE RSENSE 8 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 19-Feb-2015 PACKAGING INFORMATION Orderable Device 5962-8670401PA Status Package Type Package Pins Package (1) Drawing Qty ACTIVE CDIP JG 8 1 Eco Plan (2) TBD 5962-8670401VPA ACTIVE CDIP JG 8 1 TBD 5962-8670401VXA ACTIVE LCCC FK 20 1 TBD Lead/Ball Finish (6) A42 A42 POST-PLATE 5962-8670401XA ACTIVE LCCC FK 20 1 TBD POST-PLATE 5962-8670402PA 5962-8670402XA ACTIVE ACTIVE CDIP LCCC JG 8 1 FK 20 1 TBD TBD A42 POST-PLATE 5962-8670403PA 5962-8670403VPA 5962-8670403VXA ACTIVE ACTIVE ACTIVE CDIP CDIP LCCC JG 8 1 JG 8 1 FK 20 1 TBD TBD TBD A42 A42 POST-PLATE 5962-8670403XA ACTIVE LCCC FK 20 1 TBD POST-PLATE 5962-8670404DA 5962-8670404PA 5962-8670404VPA ACTIVE ACTIVE ACTIVE CFP CDIP CDIP W 14 1 TBD A42 JG 8 1 TBD A42 JG 8 1 TBD A42 Addendum-Page 1 MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type N / A for Pkg Type -55 to 125 -55 to 125 N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type -55 to 125 -55 to 125 -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type -55 to 125 Device Marking (4/5) 8670401PA UC1842 8670401VPA UC1842 59628670401VXA UC1842L QMLV 59628670401XA UC1842L/ 883B 8670402PA UC1843 59628670402XA UC1843L/ 883B 8670403PA UC1844 8670403VPA UC1844 59628670403VXA UC1844L QMLV 59628670403XA UC1844L/ 883B 5962-8670404DA UC1845W/883B 8670404PA UC1845 8670404VPA UC1845 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 5962-8670404VXA 5962-8670404XA UC1842J UC1842J883B UC1842L883B UC1842W UC1843J UC1843J883B UC1843L UC1843L883B UC1843W UC1844J UC1844J883B UC1844L883B UC1845J 19-Feb-2015 Status Package Type Package Pins Package (1) Drawing Qty ACTIVE LCCC FK 20 1 Eco Plan (2) TBD ACTIVE LCCC FK 20 1 TBD ACTIVE ACTIVE ACTIVE CDIP CDIP LCCC JG 8 1 JG 8 1 FK 20 1 TBD TBD TBD ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE CFP CDIP CDIP LCCC LCCC W 14 1 JG 8 1 JG 8 1 FK 20 1 FK 20 1 TBD TBD TBD TBD TBD ACTIVE ACTIVE ACTIVE ACTIVE CFP CDIP CDIP LCCC W 14 1 JG 8 1 JG 8 1 FK 20 1 TBD TBD TBD TBD ACTIVE CDIP JG 8 1 TBD Lead/Ball Finish (6) POST-PLATE POST-PLATE A42 A42 POST-PLATE A42 A42 A42 POST-PLATE POST-PLATE A42 A42 A42 POST-PLATE A42 MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 N / A for Pkg Type -55 to 125 N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type -55 to 125 -55 to 125 -55 to 125 N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type -55 to 125 -55 to 125 -55 to 125 -55 to 125 N / A for Pkg Type -55 to 125 Device Marking (4/5) 59628670404VXA UC1845L QMLV 59628670404XA UC1845L/ 883B UC1842J 8670401PA UC1842 59628670401XA UC1842L/ 883B UC1842W UC1843J 8670402PA UC1843 UC1843L 59628670402XA UC1843L/ 883B UC1843W UC1844J 8670403PA UC1844 59628670403XA UC1844L/ 883B UC1845J Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Feb-2015 Orderable Device UC1845J883B UC1845L UC1845L883B UC1845W UC1845W883B UC2842D UC2842D8 UC2842D8G4 UC2842D8TR UC2842D8TRG4 UC2842DG4 UC2842DTR UC2842J UC2842N UC2842NG4 UC2843D UC2843D8 UC2843D8G4 Status Package Type Package Pins Package (1) Drawing Qty ACTIVE CDIP JG 8 1 Eco Plan (2) TBD ACTIVE ACTIVE LCCC LCCC FK 20 1 FK 20 1 TBD TBD Lead/Ball Finish (6) A42 POST-PLATE POST-PLATE MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 N / A for Pkg Type N / A for Pkg Type -55 to 125 -55 to 125 ACTIVE ACTIVE CFP CFP ACTIVE SOIC ACTIVE SOIC ACTIVE SOIC ACTIVE SOIC ACTIVE SOIC ACTIVE SOIC ACTIVE SOIC OBSOLETE ACTIVE CDIP PDIP ACTIVE PDIP ACTIVE SOIC ACTIVE SOIC ACTIVE SOIC W 14 1 W 14 1 TBD TBD D 14 50 Green (RoHS & no Sb/Br) D 8 75 Green (RoHS & no Sb/Br) D 8 75 Green (RoHS & no Sb/Br) D 8 2500 Green (RoHS & no Sb/Br) D 8 2500 Green (RoHS & no Sb/Br) D 14 50 Green (RoHS & no Sb/Br) D 14 2500 Green (RoHS & no Sb/Br) JG 8 TBD P 8 50 Green (RoHS & no Sb/Br) P 8 50 Green (RoHS & no Sb/Br) D 14 50 Green (RoHS & no Sb/Br) D 8 75 Green (RoHS & no Sb/Br) D 8 75 Green (RoHS & no Sb/Br) A42 A42 CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU N / A for Pkg Type N / A for Pkg Type -55 to 125 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Call TI N / A for Pkg Type -40 to 85 -40 to 85 N / A for Pkg Type -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Device Marking (4/5) 8670404PA UC1845 UC1845L 59628670404XA UC1845L/ 883B UC1845W 5962-8670404DA UC1845W/883B UC2842D UC2842 D8 UC2842 D8 UC2842 D8 UC2842 D8 UC2842D UC2842D UC2842N UC2842N UC2843D UC2843 D8 UC2843 D8 Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-Feb-2015 Orderable Device UC2843D8TR UC2843D8TRG4 UC2843DG4 UC2843DTR UC2843DTRG4 UC2843J UC2843N UC2843NG4 UC2844D UC2844D8 UC2844D8G4 UC2844D8TR UC2844DG4 UC2844DTR UC2844N UC2844NG4 UC2845D UC2845D8 Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) OBSOLETE CDIP JG 8 TBD ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) Lead/Ball Finish (6) CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp Op Temp (°C) (3) Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Call TI N / A for Pkg Type -40 to 85 -40 to 85 N / A for Pkg Type -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 N / A for Pkg Type -40 to 85 N / A for Pkg Type -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Device Marking (4/5) UC2843 D8 UC2843 D8 UC2843D UC2843D UC2843D UC2843N UC2843N UC2844D UC2844 D8 UC2844 D8 UC2844 D8 UC2844D UC2844D UC2844N UC2844N UC2845D UC2845 D8 Samples Addendum-Page 4 PACKAGE OPTION ADDENDUM www.ti.com 19-Feb-2015 Orderable Device UC2845D8G4 UC2845D8TR UC2845D8TRG4 UC2845DG4 UC2845DTR UC2845DTRG4 UC2845J UC2845N UC2845NG4 UC3842D UC3842D8 UC3842D8G4 UC3842D8TR UC3842DG4 UC3842DTR UC3842N UC3842NG4 UC3843D Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) OBSOLETE CDIP JG 8 TBD ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) Lead/Ball Finish (6) CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp Op Temp (°C) (3) Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Call TI N / A for Pkg Type -40 to 85 -40 to 85 N / A for Pkg Type -40 to 85 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 N / A for Pkg Type 0 to 70 N / A for Pkg Type 0 to 70 Level-1-260C-UNLIM 0 to 70 Device Marking (4/5) UC2845 D8 UC2845 D8 UC2845 D8 UC2845D UC2845D UC2845D UC2845N UC2845N UC3842D UC3842 D8 UC3842 D8 UC3842 D8 UC3842D UC3842D UC3842N UC3842N UC3843D Samples Addendum-Page 5 PACKAGE OPTION ADDENDUM www.ti.com 19-Feb-2015 Orderable Device UC3843D8 UC3843D8G4 UC3843D8TR UC3843D8TRG4 UC3843DG4 UC3843DTR UC3843N UC3843NG4 UC3843QTR UC3844D UC3844D8 UC3844D8G4 UC3844D8TR UC3844D8TRG4 UC3844DG4 UC3844DTR UC3844DTRG4 UC3844N Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) OBSOLETE PLCC FN 20 TBD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) Lead/Ball Finish (6) CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp Op Temp (°C) (3) Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 N / A for Pkg Type 0 to 70 N / A for Pkg Type 0 to 70 Call TI Level-1-260C-UNLIM 0 to 70 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 N / A for Pkg Type 0 to 70 Device Marking (4/5) UC3843 D8 UC3843 D8 UC3843 D8 UC3843 D8 UC3843D UC3843D UC3843N UC3843N UC3844D UC3844 D8 UC3844 D8 UC3844 D8 UC3844 D8 UC3844D UC3844D UC3844D UC3844N Samples Addendum-Page 6 PACKAGE OPTION ADDENDUM www.ti.com 19-Feb-2015 Orderable Device UC3844NG4 UC3845AJ Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) ACTIVE PDIP P 8 50 Green (RoHS & no Sb/Br) ACTIVE CDIP JG 8 1 TBD Lead/Ball Finish (6) CU NIPDAU A42 MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) 0 to 70 N / A for Pkg Type 0 to 70 UC3845D UC3845D8 UC3845D8G4 UC3845D8TR UC3845D8TRG4 UC3845DG4 UC3845DTR UC3845DTRG4 UC3845N UC3845NG4 ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP D 14 50 Green (RoHS & no Sb/Br) D 8 75 Green (RoHS & no Sb/Br) D 8 75 Green (RoHS & no Sb/Br) D 8 2500 Green (RoHS & no Sb/Br) D 8 2500 Green (RoHS & no Sb/Br) D 14 50 Green (RoHS & no Sb/Br) D 14 2500 Green (RoHS & no Sb/Br) D 14 2500 Green (RoHS & no Sb/Br) P 8 50 Green (RoHS & no Sb/Br) P 8 50 Green (RoHS & no Sb/Br) CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Device Marking (4/5) UC3844N UC3845AJ UC3845D UC3845 D8 UC3845 D8 UC3845 D8 UC3845 D8 UC3845D UC3845D UC3845D UC3845N UC3845N (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Samples Addendum-Page 7 PACKAGE OPTION ADDENDUM www.ti.com 19-Feb-2015 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UC1842, UC1842-SP, UC1843, UC1844, UC1844-SP, UC1845, UC1845-SP, UC3842, UC3843, UC3844, UC3845, UC3845AM : • Catalog: UC3842, UC1842, UC3843, UC3844, UC1844, UC3845, UC1845, UC3842M, UC3845A • Military: UC1842, UC1843, UC1844, UC1845 • Space: UC1842-SP, UC1843-SP, UC1844-SP, UC1845-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 8 www.ti.com TAPE AND REEL INFORMATION PACKAGE MATERIALS INFORMATION 19-Mar-2008 *All dimensions are nominal Device Package Package Pins Type Drawing UC2842D8TR UC2842DTR UC2843D8TR UC2843DTR UC2844D8TR UC2844DTR UC2845D8TR UC2845DTR UC3842D8TR UC3842DTR UC3843D8TR UC3843DTR UC3844D8TR UC3844DTR UC3845D8TR UC3845DTR SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 SPQ 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 Reel Reel Diameter Width (mm) W1 (mm) 330.0 12.4 330.0 16.4 330.0 12.4 330.0 16.4 330.0 12.4 330.0 16.4 330.0 12.4 330.0 16.4 330.0 12.4 330.0 16.4 330.0 12.4 330.0 16.4 330.0 12.4 330.0 16.4 330.0 12.4 330.0 16.4 A0 (mm) 6.4 6.5 6.4 6.5 6.4 6.5 6.4 6.5 6.4 6.5 6.4 6.5 6.4 6.5 6.4 6.5 B0 (mm) 5.2 9.0 5.2 9.0 5.2 9.0 5.2 9.0 5.2 9.0 5.2 9.0 5.2 9.0 5.2 9.0 K0 (mm) P1 W Pin1 (mm) (mm) Quadrant 2.1 8.0 12.0 Q1 2.1 8.0 16.0 Q1 2.1 8.0 12.0 Q1 2.1 8.0 16.0 Q1 2.1 8.0 12.0 Q1 2.1 8.0 16.0 Q1 2.1 8.0 12.0 Q1 2.1 8.0 16.0 Q1 2.1 8.0 12.0 Q1 2.1 8.0 16.0 Q1 2.1 8.0 12.0 Q1 2.1 8.0 16.0 Q1 2.1 8.0 12.0 Q1 2.1 8.0 16.0 Q1 2.1 8.0 12.0 Q1 2.1 8.0 16.0 Q1 Pack Materials-Page 1 www.ti.com PACKAGE MATERIALS INFORMATION 19-Mar-2008 *All dimensions are nominal Device UC2842D8TR UC2842DTR UC2843D8TR UC2843DTR UC2844D8TR UC2844DTR UC2845D8TR UC2845DTR UC3842D8TR UC3842DTR UC3843D8TR UC3843DTR UC3844D8TR UC3844DTR UC3845D8TR UC3845DTR Package Type SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing Pins D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 D 8 D 14 SPQ 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 2500 Length (mm) 340.5 333.2 340.5 333.2 340.5 333.2 340.5 333.2 340.5 333.2 340.5 333.2 340.5 333.2 340.5 333.2 Width (mm) 338.1 345.9 338.1 345.9 338.1 345.9 338.1 345.9 338.1 345.9 338.1 345.9 338.1 345.9 338.1 345.9 Height (mm) 20.6 28.6 20.6 28.6 20.6 28.6 20.6 28.6 20.6 28.6 20.6 28.6 20.6 28.6 20.6 28.6 Pack Materials-Page 2 JG (R-GDIP-T8) 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 CERAMIC DUAL-IN-LINE 1 0.063 (1,60) 0.015 (0,38) 0.100 (2,54) 4 0.065 (1,65) 0.045 (1,14) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) 0°–15° 4040107/C 08/96 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MECHANICAL DATA FN (S-PQCC-J**) 20 PIN SHOWN D D1 3 1 19 4 MPLC004A – OCTOBER 1994 PLASTIC J-LEADED CHIP CARRIER 0.032 (0,81) 0.026 (0,66) 18 Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) 0.020 (0,51) MIN D2 / E2 E E1 8 14 D2 / E2 0.050 (1,27) 9 13 0.008 (0,20) NOM 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M NO. OF PINS ** D/E MIN MAX D1 / E1 MIN MAX D2 / E2 MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 4040005 / B 03/95 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. 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With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Audio Amplifiers Data Converters DLP® Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity Applications www.ti.com/audio Automotive and Transportation amplifier.ti.com Communications and Telecom dataconverter.ti.com Computers and Peripherals www.dlp.com Consumer Electronics dsp.ti.com Energy and Lighting www.ti.com/clocks Industrial interface.ti.com Medical logic.ti.com Security power.ti.com Space, Avionics and Defense microcontroller.ti.com Video and Imaging www.ti-rfid.com www.ti.com/omap TI E2E Community www.ti.com/wirelessconnectivity www.ti.com/automotive www.ti.com/communications www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated

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