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w WM8994 Multi-Channel Audio Hub CODEC for Smartphones DESCRIPTION FEATURES The WM8994[1] is a highly integrated ultra-low power hi-fi CODEC designed for smartphones and other portable devices rich in multimedia features. An integrated stereo class D/AB speaker driver and class W headphone driver minimize power consumption during audio playback. The device requires only two voltage supplies, with all other internal supply rails generated from integrated LDOs. Stereo full duplex asynchronous sample rate conversion and multi-channel digital mixing combined with powerful analogue mixing allow the device to support a huge range of different architectures and use cases. A fully programmable parametric EQ provides speaker compensation and a dynamic range controller can be used in the ADC or DAC paths for maintaining a constant signal level, maximizing loudness and protecting speakers against overloading and clipping. A smart digital microphone interface provides power regulation, a low jitter clock output and decimation filters for up to four digital microphones. A MIC activity detect with interrupt is available. Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity. Active ground loop noise rejection and DC offset correction help prevent pop noise and suppress ground noise on the headphone outputs.  Hi-fi 24-bit 4-channel DAC and 2-channel ADC  100dB SNR during DAC playback (‘A’ weighted)  Smart MIC interface - Power, clocking and data input for up to four digital MICs - High performance analogue MIC interface - MIC activity detect & interrupt allows processor to sleep  2W stereo (2 x 2W) class D/AB speaker driver  Capless Class W headphone drivers - Integrated charge pump - 5.3mW total power for DAC playback to headphones  4 Line outputs (single-ended or differential)  BTL Earpiece driver  Digital audio interfaces for multi-processor architecture - Asynchronous stereo duplex sample rate conversion - Powerful mixing and digital loopback functions  ReTuneTM Mobile 5-band, 6-channel parametric EQ  Programmable dynamic range controller  Dual FLL provides all necessary clocks - Self-clocking modes allow processor to sleep - All standard sample rates from 8kHz to 96kHz  Active noise reduction circuits - DC offset correction removes pops and clicks - Ground loop noise cancellation  Integrated LDO regulators  72-ball W-CSP package (4.511 x 4.023 x 0.7mm) APPLICATIONS  Smartphones and music phones  Portable navigation  Tablets  eBooks  Portable Media Players WOLFSON MICROELECTRONICS plc Product Brief, May 2012, Rev 4.1 [1] This product is protected by Patents US 7,622,984, US 7,626,445,US 7,765,019 and GB 2,432,765 To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews Copyright 2012 Wolfson Microelectronics plc WM8994 TABLE OF CONTENTS Product Brief DESCRIPTION....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 TABLE OF CONTENTS......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 3 ORDERING INFORMATION.................................................................................. 3 PIN DESCRIPTION................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ........................................................................ 6 RECOMMENDED OPERATING CONDITIONS..................................................... 8 DEVICE DESCRIPTION ........................................................................................ 9 RECOMMENDED EXTERNAL COMPONENTS.................................................. 11 PACKAGE DIMENSIONS.................................................................................... 12 IMPORTANT NOTICE ......................................................................................... 13 ADDRESS: ..................................................................................................................... 13 REVISION HISTORY ........................................................................................... 14 w Product Brief, May 2012, Rev 4.1 2 Product Brief PIN CONFIGURATION WM8994 ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE WM8994ECS/R Note: Reel quantity = 3500 -40C to +85C 72-ball W-CSP (Pb-free, Tape and reel) MOISTURE SENSITIVITY LEVEL MSL1 PEAK SOLDERING TEMPERATURE 260C w Product Brief, May 2012, Rev 4.1 3 WM8994 Product Brief PIN DESCRIPTION A description of each pin on the WM8994 is provided below. Note that a table detailing the associated power domain for every input and output pin is provided on the following page. Note that, where multiple pins share a common name, these pins should be tied together on the PCB. PIN NO F2 G3 NAME ADCDAT1 ADCLRCLK1/ GPIO1 D6, E7, E8 D9 AGND AVDD1 D8 AVDD2 G1 BCLK1 A4 CIFMODE G8 CPCA H8 CPCB H9 CPGND G9 CPVDD H7 CPVOUTN G7 CPVOUTP G2 C¯¯S/ADDR E4 DACDAT1 D2 DBVDD F1 DCVDD E2 DGND C6 DMICCLK H5 GPIO10/ LRCLK3 F6 GPIO11/ BCLK3 E1 GPIO2/ MCLK2 H2 GPIO3/ BCLK2 F4 GPIO4/ LRCLK2 H3 GPIO5/ DACDAT2 G4 GPIO6/ ADCLRCLK2 E5 GPIO7/ ADCDAT2 H4 GPIO8/ DACDAT3 F5 GPIO9/ ADCDAT3 F7 HP2GND G5 HPOUT1FB TYPE Digital Output Digital Input / Output Supply DESCRIPTION Audio interface 1 ADC digital audio data Audio interface 1 ADC left / right clock / General Purpose pin GPIO 1/ Control interface data output Analogue ground (Return path for AVDD1, AVDD2 and LDO1VDD)) Supply / Analogue Output Supply Digital Input / Output Digital Input Analogue Output Analogue Output Supply Supply Analogue Output Analogue Output Digital Input Digital Input Supply Supply / Analogue Output Supply Digital Output Digital Input / Output Digital Input / Output Digital Input Digital Input / Output Digital Input / Output Digital Input / Output Digital Input / Output Digital Input / Output Digital Input / Output Digital Input / Output Supply Analogue Input Analogue core supply / LDO1 Output Bandgap reference, analogue class D and FLL supply Audio interface 1 bit clock Selects 2-wire or 3/4-wire control interface mode Charge pump fly-back capacitor pin Charge pump fly-back capacitor pin Charge pump ground (Return path for CPVDD) Charge pump supply Charge pump negative supply decoupling pin (HPOUT1L, HPOUT1R) Charge pump positive supply decoupling pin (HPOUT1L, HPOUT1R) 3-/4-wire (SPI) chip select or 2-wire (I2C) address select Audio interface 1 DAC digital audio data Digital buffer (I/O) supply Digital core supply / LDO2 output Digital ground (Return path for DCVDD and DBVDD, DBVDD and LDO2VDD)) Digital MIC clock output General Purpose pin GPIO 10 / Audio interface 3 left / right clock General Purpose pin GPIO 11 / Audio interface 3 bit clock General Purpose pin GPI 2 / Master clock 2 General Purpose pin GPIO 3 / Audio interface 2 bit clock General Purpose pin GPIO 4 / Audio interface 2 left / right clock General Purpose pin GPIO 5 / Audio interface 2 DAC digital audio data General Purpose pin GPIO 6 / Audio interface 2 ADC left / right clock General Purpose pin GPIO 7 / Audio interface 2 ADC digital audio data General Purpose pin GPIO 8 / Audio interface 3 DAC digital audio data General Purpose pin GPIO 9 / Audio interface 3 ADC digital audio data Analogue ground HPOUT1L and HPOUT1R ground loop noise rejection feedback w Product Brief, May 2012, Rev 4.1 4 Product Brief PIN NO H6 G6 F9 F8 D7 NAME HPOUT1L HPOUT1R HPOUT2N HPOUT2P IN1LN C8 IN1LP B7 IN1RN C7 IN1RP B9 IN2LN/ DMICDAT1 B8 IN2LP/VRXN A9 IN2RN/ DMICDAT2 A8 IN2RP/VRXP D4 LDO1ENA E9 LDO1VDD D5 LDO2ENA D1 LDO2VDD C5 LINEOUT1N B5 LINEOUT1P C4 LINEOUT2N B4 LINEOUT2P A6 LINEOUTFB E3 LRCLK1 D3 MCLK1 A7 MICBIAS1 B6 MICBIAS2 A5 REFGND H1 SCLK F3 SDA A1 SPKGND1 C1 SPKGND2 A3 SPKMODE B1 SPKOUTLN A2 SPKOUTLP C3 SPKOUTRN B3 SPKOUTRP B2 SPKVDD1 C2 SPKVDD2 C9 VMIDC E6 VREFC WM8994 TYPE Analogue Output Analogue Output Analogue Output Analogue Output Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input / Digital Input Analogue Input Analogue Input / Digital Input Analogue Input Digital Input Supply Digital Input Supply Analogue Output Analogue Output Analogue Output Analogue Output Analogue Input Digital Input / Output Digital Input Analogue Output Analogue Output Supply Digital Input Digital Input / Output Supply Supply Digital Input Analogue Output Analogue Output Analogue Output Analogue Output Supply Supply Analogue Output Analogue Output DESCRIPTION Left headphone output Right headphone output Earpiece speaker inverted output Earpiece speaker non-inverted output Left channel single-ended MIC input / Left channel negative differential MIC input Left channel line input / Left channel positive differential MIC input Right channel single-ended MIC input / Right channel negative differential MIC input Right channel line input / Right channel positive differential MIC input Left channel line input / Left channel negative differential MIC input / Digital MIC data input 1 Left channel line input / Left channel positive differential MIC input / Mono differential negative input (RXVOICE -) Right channel line input / Right channel negative differential MIC input / Digital MIC data input 2 Left channel line input / Left channel positive differential MIC input / Mono differential positive input (RXVOICE +) Enable pin for LDO1 Supply for LDO1 Enable pin for LDO2 Supply for LDO2 Negative mono line output / Positive left or right line output Positive mono line output / Positive left line output Negative mono line output / Positive left or right line output Positive mono line output / Positive left line output Line output ground loop noise rejection feedback Audio interface 1 left / right clock Master clock 1 Microphone bias 1 Microphone bias 2 Analogue ground Control interface clock input Control interface data input and output / 2-wire acknowledge output Ground for speaker driver (Return path for SPKVDD1) Ground for speaker driver (Return path for SPKVDD2) 2W Mono/1W StereoMono / Stereo speaker mode select Left speaker negative output Left speaker positive output Right speaker negative output Right speaker positive output Supply for speaker driver 1 (Left channel) Supply for speaker driver 2 (Right channel) Midrail voltage decoupling capacitor Bandgap reference decoupling capacitor w Product Brief, May 2012, Rev 4.1 5 WM8994 The following table identifies the power domain and ground reference associated with each of the input / output pins. Product Brief PIN NO F2 G3 G1 G2 E4 C6 E1 H2 F4 H3 G4 E5 H4 F5 H5 F6 H6 G6 F9 F8 D7 C8 B7 C7 B9 B8 A9 A8 D4 D5 C5 B5 C4 B4 E3 D3 H1 NAME ADCDAT1 ADCLRCLK1/ GPIO1 BCLK1 C¯¯S/ADDR DACDAT1 DMICCLK GPIO2/ MCLK2 GPIO3/ BCLK2 GPIO4/ LRCLK2 GPIO5/ DACDAT2 GPIO6/ ADCLRCLK2 GPIO7/ ADCDAT2 GPIO8/ DACDAT3 GPIO9/ ADCDAT3 GPIO10/ LRCLK3 GPIO11/ BCLK3 HPOUT1L HPOUT1R HPOUT2N HPOUT2P IN1LN IN1LP IN1RN IN1RP IN2LN/ DMICDAT1 IN2LP/VRXN IN2RN/ DMICDAT2 IN2RP/VRXP LDO1ENA LDO2ENA LINEOUT1N LINEOUT1P LINEOUT2N LINEOUT2P LRCLK1 MCLK1 SCLK POWER DOMAIN DBVDD DBVDD DBVDD DBVDD DBVDD MICBIAS1 DBVDD DBVDD DBVDD DBVDD DBVDD DBVDD DBVDD DBVDD DBVDD DBVDD CPVOUTP, CPVOUTN CPVOUTP, CPVOUTN CPVOUTP, CPVOUTN CPVOUTP, CPVOUTN AVDD1 AVDD1 AVDD1 AVDD1 AVDD1 (IN2LN) or MICBIAS1 (DMICDAT1) AVDD1 AVDD1 (IN2RN) or MICBIAS1 (DMICDAT2) AVDD1 DBVDD DBVDD AVDD1 AVDD1 AVDD1 AVDD1 DBVDD DBVDD DBVDD GROUND DOMAIN DGND DGND DGND DGND DGND AGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND CPGND CPGND CPGND CPGND AGND AGND AGND AGND AGND AGND AGND AGND DGND DGND AGND AGND AGND AGND DGND DGND DGND w Product Brief, May 2012, Rev 4.1 6 Product Brief PIN NO F3 A3 B1 A2 C3 B3 NAME SDA SPKMODE SPKOUTLN SPKOUTLP SPKOUTRN SPKOUTRP POWER DOMAIN DBVDD DBVDD SPKVDD1 SPKVDD1 SPKVDD2 SPKVDD2 GROUND DOMAIN DGND DGND SPKGND1 SPKGND1 SPKGND2 SPKGND2 WM8994 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION MIN MAX Supply voltages (AVDD1, DBVDD) Supply voltages (AVDD2, DCVDD, LDO2VDD) -0.3V -0.3V +4.5V +2.5V Supply voltages (CPVDD) Supply voltages (SPKVDD1, SPKVDD2, LDO1VDD) Voltage range digital inputs (DBVDD domain) -0.3V -0.3V AGND -0.3V +2.2V +7.0V DBVDD +0.3V Voltage range digital inputs (DMICDATn) Voltage range analogue inputs (AVDD1 domain) Voltage range analogue inputs (LINEOUTFB) AGND - 0.3V AGND -0.3V AGND - 0.3V AVDD1 + 0.3V AVDD1 +0.3V AVDD1 + 0.3V Voltage range analogue inputs (HPOUT1FB) Ground (DGND, CPGND, SPKGND1, SPKGND2, REFGND, HP2GND) Operating temperature range, TA Junction temperature, TJMAX Storage temperature after soldering AGND - 0.3V AGND - 0.3V -40ºC -40ºC -65ºC AGND + 0.3V AGND + 0.3V +85ºC +150ºC +150ºC w Product Brief, May 2012, Rev 4.1 7 WM8994 Product Brief RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN TYP MAX UNIT Digital supply range (Core) See notes 7,8 DCVDD 0.95 1.0 2.0 V Digital supply range (I/O) DBVDD 1.62 1.8 3.6 V Analogue supply 1 range See notes 3,4,5,6 AVDD1 2.4 3.0 3.3 V Analogue supply 2 range Charge Pump supply range Speaker supply range AVDD2 1.71 1.8 2.0 V CPVDD 1.71 1.8 2.0 V SPKVDD1, SPKVDD2 2.7 5.0 5.5 V LDO1 supply range LDO2 supply range Ground Power supply rise time (notes 6, 7 and 8) LDO1VDD 2.7 5.0 5.5 V LDO2VDD 1.71 1.8 2.0 V DGND, AGND, CPGND, 0 V SPKGND1, SPKGND2, REFGND, HP2GND All supplies 1 s Operating temperature range Notes: TA -40 85 °C 1. Analogue, digital and speaker grounds must always be within 0.3V of AGND. 2. There is no power sequencing requirement; the supplies may be enabled in any order. 3. AVDD1 must be less than or equal to SPKVDD1 and SPKVDD2. 4. An internal LDO (powered by LDO1VDD) can be used to provide the AVDD1 supply. 5. When AVDD1 is supplied externally (not from LDO1), the LDO1VDD voltage must be greater than or equal to AVDD1 6. The WM8994 can operate with AVDD1 tied to 0V; power consumption may be reduced, but the analogue audio functions will not be supported. 7. An internal LDO (powered by LDO2VDD) can be used to provide the DCVDD supply. 8. When DCVDD is supplied externally (not from LDO2), the LDO2VDD voltage must be greater than or equal to DCVDD 9. DCVDD and AVDD1 minimum rise times do not apply when these domains are powered using the internal LDOs. 10. The specified minimum power supply rise times assume a minimum decoupling capacitance of 100nF per pin. However, Wolfson strongly advises that the recommended decoupling capacitors are present on the PCB and that appropriate layout guidelines are observed (see “Applications Information” section). 11. The specified minimum power supply rise times also assume a maximum PCB inductance of 10nH between decoupling capacitor and pin. w Product Brief, May 2012, Rev 4.1 8 Product Brief WM8994 DEVICE DESCRIPTION The WM8994 is a low power, high quality audio codec designed to interface with a wide range of processors and analogue components. A high level of mixed-signal integration in a very small footprint makes it ideal for portable applications such as mobile phones. Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity. The analogue circuits of the WM8994 are almost entirely backwards-compatible with the WM8993 with the exception of two additional DAC channels, a dual FLL and two integrated LDO regulators. Three sets of audio interface pins are available in order to provide independent and fully asynchronous connections to multiple processors, typically an application processor, baseband processor and wireless transceiver. Any two of these interfaces can operate totally independently and asynchronously while the third interface can be synchronised to either of the other two and can also provide ultra low power loopback modes to support, for example, wireless headset voice calls. Four digital microphone input channels are available to support advanced multi-microphone applications such as noise cancellation. An integrated microphone activity monitor is available to enable the processor to sleep during periods of microphone inactivity, saving power. Four DAC channels are available to support use cases requiring up to four simultaneous digital audio streams to the output drivers. Eight highly flexible analogue inputs allow interfacing to up to four microphone inputs (single-ended or differential), plus multiple stereo or mono line inputs. Connections to an external voice CODEC, FM radio, line input, handset MIC and headset MIC are all fully supported. Signal routing to the output mixers and within the CODEC has been designed for maximum flexibility to support a wide variety of usage modes. A ‘Direct Voice’ path from a voice CODEC directly to the Speaker or Earpiece output drivers is included. Nine analogue output drivers are integrated, including a stereo pair of high power, high quality Class D/AB switchable speaker drivers; these can support 2W each in stereo mode. It is also possible to configure the speaker drivers as a mono output, giving enhanced performance. A mono earpiece driver is provided, providing output from the output mixers or from the low-power differential ‘Direct Voice’ path. One pair of ground-reference headphone outputs is provided; these are powered from an integrated Charge Pump, enabling high quality, power efficient headphone playback without any requirement for DC blocking capacitors. A DC Servo circuit is available for DC offset correction, thereby suppressing pops and reducing power consumption. Four line outputs are provided, with multiple configuration options including 4 x single-ended output or 2 x differential outputs. The line outputs are suitable for output to a voice CODEC, an external speaker driver or line output connector. Ground loop feedback is available on the headphone outputs and the line outputs, providing rejection of noise on the ground connections. All outputs have integrated pop and click suppression features. Internal differential signal routing and amplifier configurations have been optimised to provide the highest performance and lowest possible power consumption for a wide range of usage scenarios, including voice calls and music playback. The speaker drivers offer low leakage and high PSRR; this enables direct connection to a Lithium battery. The speaker drivers provide eight levels of AC and DC gain to allow output signal levels to be maximised for many commonly-used SPKVDD/AVDD1 combinations. The ADCs and DACs are of hi-fi quality, using a 24-bit low-order oversampling architecture to deliver optimum performance. A flexible clocking arrangement supports mixed sample rates, whilst integrated ultra-low power dual FLLs provide additional flexibility. A high pass filter is available in all ADC and digital MIC paths for removing DC offsets and suppressing low frequency noise such as mechanical vibration and wind noise. A digital mixing path from the ADC or digital MICs to the DAC provides a sidetone of enhanced quality during voice calls. DAC soft mute and un-mute is available for pop-free music playback. The integrated Dynamic Range Controllers (DRC) and ReTuneTM Mobile 5-band parametric equaliser (EQ) provide further processing capability of the digital audio paths. The DRC provides compression and signal level control to improve the handling of unpredictable signal levels. ‘Anti-clip’ and ‘quick release’ algorithms improve intelligibility in the presence of transients and impulsive noises. The EQ provides the capability to tailor the audio path according to the frequency characteristics of an earpiece or loudspeaker, and/or according to user preferences. w Product Brief, May 2012, Rev 4.1 9 WM8994 Product Brief The WM8994 has highly flexible digital audio interfaces, supporting a number of protocols, including I2S, DSP, MSB-first left/right justified, and can operate in master or slave modes. PCM operation is supported in the DSP mode. A-law and -law companding are also supported. Time division multiplexing (TDM) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power. The four digital MIC and ADC channels and four DAC channels are available via four TDM channels on Digital Audio Interface 1 (AIF1). A powerful digital mixing core allows data from each TDM channel of each audio interface and from the ADCs and digital MICs to be mixed and re-routed back to a different audio interface and to the 4 DAC output channels. The digital mixing core can operate synchronously with either Audio Interface 1 or Audio Interface 2, with asynchronous stereo full duplex sample rate conversion performed on the other audio interface as required. The system clock (SYSCLK) provides clocking for the ADCs, DACs, DSP core, digital audio interface and other circuits. SYSCLK can be derived directly from one of the MCLK1 or MCLK2 pins or via one of two integrated FLLs, providing flexibility to support a wide range of clocking schemes. Typical portable system MCLK frequencies, and sample rates from 8kHz to 96kHz are all supported. Automatic configuration of the clocking circuits is available, derived from the sample rate and from the MCLK / SYSCLK ratio. The WM8994 uses a standard 2, 3 or 4-wire control interface, providing full software control of all features, together with device register readback. An integrated Control Write Sequencer enables automatic scheduling of control sequences; commonly-used signal configurations may be selected using ready-programmed sequences, including time-optimised control of the WM8994 pop suppression features. It is an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Unused circuitry can be disabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery-powered applications. Versatile GPIO functionality is provided, with support for button/accessory detect inputs, or for clock, system status, or programmable logic level output for control of additional external circuitry. Interrupt logic, status readback and de-bouncing options are supported within this functionality. w Product Brief, May 2012, Rev 4.1 10 Product Brief RECOMMENDED EXTERNAL COMPONENTS WM8994 w Product Brief, May 2012, Rev 4.1 11 WM8994 PACKAGE DIMENSIONS Product Brief B: 72 BALL W-CSP PACKAGE 4.511 X 4.023 X 0.7 mm BODY, 0.50 mm BALL PITCH DETAIL 1 2 A G A2 9 8 7 6 5 4 3 2 1 D 6 A B 4 A1 CORNER C D e E1 E 5 F G DM068.C E H DETAIL 2 e D1 BOTTOM VIEW 2X 2X 0.10 Z 0.10 Z TOP VIEW f1 SOLDER BALL bbb Z f2 h 1 Z A1 DETAIL 2 Symbols A A1 A2 D D1 E E1 e f1 f2 g h MIN 0.615 0.219 0.361 4.471 3.983 0.035 Dimensions (mm) NOM MAX 0.7 0.244 0.386 4.511 4.00 BSC 4.023 0.785 0.269 0.411 4.551 4.063 3.50 BSC 0.50 BSC 0.2555 BSC 0.2615 BSC 0.070 0.105 0.314 BSC NOTE 5 8 9 NOTES: 1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’ AND BACKSIDE COATING. 3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE. 4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. 7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C. 8. f1 = NOMINAL DISTANCE OF BALL CENTRE TO DIE EDGE X AXIS (AS PER POD) – APPLICABLE TO ALL CORNERS OF DIE. 9. f2 = NOMINAL DISTANCE OF DIE CENTRE TO DIE EDGE IN Y AXIS (AS PER POD) – APPLICABLE TO ALL CORNERS OF DIE. w Product Brief, May 2012, Rev 4.1 12 Product Brief IMPORTANT NOTICE WM8994 Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: Wolfson Microelectronics plc 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w Product Brief, May 2012, Rev 4.1 13 WM8994 REVISION HISTORY Product Brief DATE 29/06/09 22/12/09 28/09/10 25/10/10 8/2/11 27/05/11 30/05/11 06/12/11 25/04/12 25/04/12 25/04/12 REV 1.1 1.2 3.0 3.0 3.0 3.0 3.1/4.0 4.0 4.0 4.1 4.1 4.1 4.1 First Release DESCRIPTION OF CHANGES Order code changed from WM8994ECS/RV to WM8994ECS/R Content updated from Rev 3.4 datasheet External components drawing updated to show MICBIAS capacitors Updated header to replace “Pre-Production” with “Product Brief” Added arrow to “Speaker Mode Select” line on “Recommended External Components Diagram” Added notes on RF immunity. 2W Stereo (into 4ohms) now specified. Pin Description updated: A3, A9, D6 and E2 Added Table of Contents Front page updated Power domain table added Additional details in Absolute Maximum Ratings Recommended Operating Conditions updated PAGE 2 All 10 All 9 12 1 6 7 8 CHANGED BY DH JMacD PH PH KOL KOL PH JMacD JMacD PH JMacD JMacD JMacD w Product Brief, May 2012, Rev 4.1 14

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