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CY7C68003手册

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  • 日期: 2018-03-15
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标签: USBFPGA

USB开发方案芯片手册                            

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CY7C68003 MoBLUSB TX2UL USB 20 ULPI Transceiver UART pass through mode ESD compliance JESD22A114D 8 kV Contact human body model HBM for DP DM and VSS pins IEC61000 42 8 kV contact discharge IEC61000 42 15 kV air discharge Support for industrial temperature range 40 C to 85 C Low power consumption for mobile applications 5 A nominal sleep mode 30 mA nominal active HS transfer Small package for mobile applications 214 x 176 mm 20pin WLCSP 04 mm pitch 4 x 4 mm 24pin QFN Applications ......

CY7C68003 MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver ■ UART pass through mode ■ ESD compliance: ❐ JESD22-A114D 8 kV Contact human body model (HBM) for DP, DM, and VSS pins ❐ IEC61000 - 4-2 8 kV contact discharge ❐ IEC61000 - 4-2 15 kV air discharge ■ Support for industrial temperature range: (-40 °C to 85 °C) ■ Low power consumption for mobile applications: ❐ 5 µA nominal sleep mode ❐ 30 mA nominal active HS transfer ■ Small package for mobile applications: ❐ 2.14 x 1.76 mm 20-pin WLCSP 0.4 mm pitch ❐ 4 x 4 mm 24-pin QFN Applications ■ Mobile phones ■ PDAs ■ Portable media players (PMPs) ■ DTV applications ■ Portable GPS units MoBL-USB™ TX2UL USB 2.0 ULPI Transceiver Features The Cypress MoBL-USB™ TX2UL is a low voltage high speed (HS) USB 2.0 UTMI+ Low Pin Interface (ULPI) Transceiver. The TX2UL is specifically designed for mobile handset applications by offering tiny package options and low power consumption. ■ USB 2.0 Full Speed and High Speed compliant transceiver ■ Multi range (1.8 V to 3.3 V) I/O voltages ■ Fully compliant ULPI link interface ■ 8-bit SDR ULPI data path ■ UTMI+ level 0 support ■ Support USB device mode only ■ Integrated oscillator ■ Integrated phase locked loop (PLL) – 13, 19.2, 24, or 26 MHz reference ■ Integrated USB pull-up and termination resistors ■ 3.0 V to 5.775 V VBATT input ■ Chip select pin ■ Single ended device RESET input TX2UL Block Diagram CLOCK DATA[7:0] DIR STP NXT I/O Control/ Data Logic Operational mode tracking interrupt Registers Block ULPI Wrapper Global Control Block Reset / Clock / Power / Misc. Control POR XOSC PLL RESET_N CS_N VBATT VCC (1.8 V) XI XO (3.0 – 5.775 V) 13/19.2/ 24/26 MHz TX2UL ULPI Block Tx/Rx Core UTMI+ Level0 USB FS/HS PHY DP DM RXD TXD 3.3 V Regulator Block 1.8 V Bandgap Cypress Semiconductor Corporation Document Number: 001-15775 Rev. *O • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 30, 2017 Contents Functional Overview ........................................................3 UTMI+ Low Pin Interface (ULPI) .................................3 Oscillator (OSC) ..........................................................3 Phase Locked Loop (PLL) ...........................................3 Power On Reset (POR) ...............................................3 Reset (RESET_N) .......................................................3 DP and DM pins ..........................................................3 Chip Select (CS_N) .....................................................3 USB2 Transceiver Macrocell Interface (UTMI+) ..........3 Global Control .............................................................3 Full Speed and High Speed USB Transceivers (FS/HS) ......................3 USB Pull up and Intr Detect, Termination Resistors (Pull up/TERM) ...............................3 UART Pass Through Mode .........................................3 Clocking .......................................................................4 Power Domains ...........................................................4 Operation Modes .........................................................5 VID and PID ................................................................6 Pinouts ..............................................................................7 Synchronous Operation Modes ......................................9 ULPI Transmit Command Byte (TX CMD) ..................9 ULPI Receive Command Byte (RX CMD) ...................9 USB Data Transmit (NOPID) .....................................10 USB Data Transmit (PID) ..........................................11 USB Packet Receive .................................................11 Immediate Register Read and Write .........................12 Immediate Register Read and Write Aborted by USB Receive ..................................................13 Back to Back Immediate Register Read and Write and USB Receive .............................................................14 CY7C68003 Configuration Mode ........................................................ 16 Configuration Mode in 20-Pin CSP package ............. 16 Configuration Mode in 24-Pin QFN package ............. 16 Power On Reset (POR) ............................................. 16 Register ..................................................................... 16 Register Map ............................................................. 16 Immediate Register Set ............................................. 17 Function Control Register .......................................... 17 Interface Control Register ......................................... 18 Debug Register ......................................................... 18 Scratch Register ........................................................ 18 Carkit Control Register .............................................. 18 Drive Strength and Slew Rate Configuration Register ............................. 19 USB Interface Control Register ................................. 19 Absolute Maximum Ratings .......................................... 20 Operating Conditions ..................................................... 20 DC Characteristics ......................................................... 21 AC Characteristics ......................................................... 21 Ordering Information ...................................................... 24 Ordering Code Definitions ......................................... 24 Package Diagrams .......................................................... 25 Acronyms ........................................................................ 27 Document Conventions ................................................. 27 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 30 Worldwide Sales and Design Support ....................... 30 Products .................................................................... 30 PSoC® Solutions ...................................................... 30 Cypress Developer Community ................................. 30 Technical Support ..................................................... 30 Document Number: 001-15775 Rev. *O Page 2 of 30 CY7C68003 USB2 Transceiver Macrocell Interface (UTMI+) This block conforms to the UTMI+ Level 0 standard. It performs all the UTMI to USB translation. Global Control This block is the digital control logic that ties the blocks of the device together. Its functions include pull up control, over current protect control, and more. Full Speed and High Speed USB Transceivers (FS/HS) The FS and HS Transceivers comply fully with the USB 2.0 specifications. USB Pull up and Intr Detect, Termination Resistors (Pull up/TERM) These blocks contain the USB pull-up and termination resistors as specified by the USB 2.0 specification. UART Pass Through Mode TX2UL supports Carkit UART Pass Through Mode. When the Carkit Mode bit in the Interface Control register is set, it enables the Link to communicate through the DP/DM to a remote system using UART signaling. By default, the clock is powered down when the TX2UL enters Carkit Mode. Entering and exiting the Carkit Mode is identical to the Serial Mode. Table 1, Table 2, and Figure 1 show the UART Signal Mapping between the DP/DM and DATA[1:0] at ULPI interface. Table 1. UART Signal Mapping at ULPI Interface Signal txd rxd Maps to DATA[0] DATA[1] Reserved DATA[7:2] Direction Description IN OUT - UART TXD signal routed to DM pin UART RXD signal routed to DP pin Reserved Table 2. UART Signal Mapping at USB Interface Signal TXD RXD Maps to Direction Description DM DP OUT INT UART TXD signal UART RXD signal Figure 1. UART Signal Mapping in Pass Through Mode ULPI INTERFACE txd rxd DATA[0] DATA[1] TX2UL USB INTERFACE TXD RXD DM DP It for clock parameters. Functional Overview UTMI+ Low Pin Interface (ULPI) This block conforms to the ULPI specification. It supports the 8-bit wide SDR data path. The primary I/Os of this block support multi-range LVCMOS signaling from 1.8 V to 3.3 V (±5%). The level used is automatically selected by the voltage applied to VCCIO and is set at any voltage between 1.8 V and 3.3 V. Oscillator (OSC) This block meets the requirements of both the on-chip PLL and the USB-IF requirements is a fundamental mode parallel resonant oscillator with a maximum ESR of 60 Ω. It supports the following: ■ Integrated Crystal Oscillator – 13, 19.2, 24, or 26 MHz crystal ■ 13, 19.2, 24, or 26 MHz LVCMOS single ended input clock on XI Phase Locked Loop (PLL) The PLL meets all clock stability requirements imposed by this device and the USB standard. It supports all requirements to make the device compliant to the USB 2.0 specifications. It also has a fractional multiplier that enables it to supply the correct frequency to the device when it is presented with a 13, 19.2, 24, or 26 MHz reference clock. Power On Reset (POR) This block provides a POR signal (internal) based on the input supply. An internal POR is generated when VCC input rises above VPOR(trip). Reset (RESET_N) The three major functions of RESET_N pin are as follows: ■ Reset TX2UL ■ Place TX2UL into Sleep Mode ■ Place TX2UL into Configuration Mode When the RESET_N pin is asserted (low) for tSTATE (tSTATE is specified in Table 21 on page 21), the TX2UL enters either Sleep Mode or Configuration Mode depending on the CS_N state. When RESET_N is asserted while CS_N is asserted, TX2UL enters Sleep Mode. When RESET_N is asserted for tSTATE while CS_N is deasserted, TX2UL enters Configuration Mode. In these modes, all the pins in the ULPI interface are tristated. If the RESET_N pin is not used, it must be pulled high. For information about different modes of configuration, see Table 5 on page 5. DP and DM pins The DP and DM pins are the differential pins for the USB. They must be connected to the corresponding DP and DM pins of the USB receptacle. Chip Select (CS_N) This signal pin is available only in 24-pin QFN package. The two major functions of CS_N are as follows: ■ Tristate the ULPI bus output pins ■ Associate with RESET_N to place TX2UL in the Sleep mode When the CS_N pin is deasserted (high), all the pins in the ULPI interface are tristated. Document Number: 001-15775 Rev. *O Page 3 of 30 Clocking TX2UL supports external crystal and clock inputs at the 13, 19.2, 24, and 26 MHz frequencies. The internal PLL applies the proper clock multiply option depending on the input frequency. For appli- cations that use an external clock source to drive XI, the XO pin (in the 24-pin QFN package) is left floating. TX2UL has an on-chip oscillator circuit that uses an external 13, 19.2, 24, or 26 MHz (±100 ppm) crystal with the following characteristics: ■ Parallel resonant ■ Fundamental mode ■ 750 µW drive level ■ 12 pF (5 percent tolerance) load capacitors ■ 150 ppm TX2UL operates on one of two primary clock sources: ■ LVCMOS square wave clock input driven on the XI pin ■ Crystal generated sine wave clock on the XI and XO pins Table 3. External Clock Requirements Parameter Description Vn PN_100 PN_1k PN_10k PN_100k PN_1M Supply voltage noise at frequencies < 50 MHz Input phase noise at 100 Hz Input phase noise at 1 kHz offset Input phase noise at 10 kHz offset Input phase noise at 100 kHz offset Input phase noise at 1 MHz offset Duty cycle Maximum frequency deviation Power Domains The TX2UL has three power supply domains: ■ VCC ■ VIO ■ VBATT TX2UL has two grounds: ■ VSS ■ VSSBATT VCC This is the core 1.8 V power supply for the TX2UL. It can range anywhere from 1.7 V to 1.9 V during actual operation. VIO This is the 1.8 V to 3.3 V multi range supply to the I/O ring. It can range anywhere from 1.7 V to 3.6 V during actual operation. CY7C68003 The selection between input clock source and frequency on the XI pin is determined by the Chip Configuration register loaded through the RESET_N during Configuration Mode. The external clock source requirements are shown in Figure 3 on page 5. Figure 2. Crystal Configuration TX2UL PLL XI XO XTAL 12 pf 12 pf * 12 pF capacitor values assumes a trace capacitance of 3 pF per side on a four layer FR4 PCA Specification Min – – – – – – 30 – Max 20 75 104 120 128 130 70 150 Unit mV p-p dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz % ppm VBATT This is the battery input supply that powers the 3.3 V regulator block. It can range anywhere from 3.0 to 5.775 V during actual operation. Voltage Regulator The internal 3.3 V regulator block regulates the VBATT supply to the internal 3.3 V supply for the USBIO and XOSC blocks. If the supply voltage at VBATT is below 3.3 V, the regulator block switches the VBATT supply directly for the USBIO and XOSC blocks. Power Supply Sequence TX2UL does not require a power supply sequence. All power supplies are independently sequenced without damaging the part. All supplies are up and stable for the device to function properly. The analog block contains circuitry that senses the power supply to determine when all supplies are valid. Document Number: 001-15775 Rev. *O Page 4 of 30 CY7C68003 Operation Modes There are six operation modes available in TX2UL. They are: ■ Normal operation mode ■ Configuration mode ■ ULPI low power mode ■ Sleep mode ■ Carkit UART pass through mode ■ Tristate ULPI interface output mode (only available in 24-pin QFN package) When changing the operation modes, if the current and changing modes are not the normal operation Mode, TX2UL first changes to the normal operation mode. For example, to change from ULPI low power mode to Sleep mode, TX2UL changes to normal operation mode first, and then to Sleep mode. The Mode Change State diagram in Figure 3 shows the mode change path of TX2UL. The entries of the six operations modes (20-pin CSP package has five operation modes) are listed in Table 4 and Table 5. There are three mode change transactions that require the RESET_N assert or deassert with tSTATE (see Table 21 on page 21 for tSTATE). The three mode change transactions are: ■ Change from normal operation mode to configuration mode; RESET_N is required to assert with tSTATE ■ Change from configuration mode to normal operation mode; RESET_N is required to de-assert with tSTATE ■ Change from normal operation mode to sleep mode; RESET_N is required to assert with tSTATE Figure 3. Mode Change State Diagram Sleep Mode Carkit UART Pass Through Mode Tristate ULPI Interface Output Mode (available in 24-pin QFN package only) Normal Operation Mode Configuration Mode ULPI Low Power Mode Table 5. TX2UL 24-Pin QFN Package Operation Modes Table 4. TX2UL 20-Pin CPS Package Operation Modes RESET_N 0 (Low) Sleep mode 1 (High) Normal operation mode 1 (High) Enter into ULPI low power mode by setting SuspendM register bit (in Function Control Register) to 0 during the normal operation mode. Mode 1 (High) Enter into Carkit UART pass through mode by setting Carkit mode register bit (in Interface Control Register) to 1 during the normal operation mode. Enter into Configuration Mode 0 (Low) when Power On (VCC On) CS_N 0 (Low) 0 (Low) 0 (Low) Mode RESET_N 0 (Low) 1 (High) Normal operation mode 1 (High) Sleep mode Enter into ULPI low power mode by setting SuspendM register bit (in Function Control Register) to 0 during the normal operation mode. Enter into Carkit UART pass through mode by setting Carkit Mode register bit (in Interface Control Register) to 1 during the normal operation mode. Configuration mode Tristate ULPI interface output pins 0 (Low) 1 (High) 1 (High) 1 (High) 0 (Low) 1 (High) Document Number: 001-15775 Rev. *O Page 5 of 30
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