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FPGA实现简易频率检测

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标    签:FPGA频率检测

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测频率并用LCD显示,从信号源接入一个信号(正弦波,三角波或者方波),经过AD1转换后,送入FPGA中。在FPGA中,使用双值法整形,得到标准的方波,然后测出频率,并送入1602中显示。经测试,其测频误差小于0.5%,其测频范围为10Hz~10MHz。

文件列表

.myeclipse
----|CVS
----|----|Repository
----|----|Root
.settings
----|CVS
----|----|Entries
----|----|Repository
----|----|Root
org.eclipse.core.resources.prefs
.svn
----|prop-base
props
text-base
----|readme.txt.svn-base
tmp
----|prop-base
props
text-base
all-wcprops
dir-prop-base
entries
format
pinlvji_demo
----|_ngo
----|----|netlist.lst
_xmsgs
----|pn_parser.xmsgs
iseconfig
----|pinlvji_demo.projectmgr
----|topdesign.xreport
pinlvji_demo_xdb
----|tmp
Project.dhp
__projnav.log
_impact.cmd
_impact.log
automake.log
bitgen.ut
pinlvji_demo.dhp
pinlvji_demo.gise
pinlvji_demo.ise_ISE_Backup
pinlvji_demo.xise
pinlvji_demo_ise12migration.zip
topdesign.bgn
topdesign.bit
topdesign.bld
topdesign.cmd_log
topdesign.drc
topdesign.lso
topdesign.mrp
topdesign.ncd
topdesign.ngc
topdesign.ngd
topdesign.ngm
topdesign.ngr
topdesign.pad
topdesign.par
topdesign.pcf
topdesign.prj
topdesign.stx
topdesign.syr
topdesign.twr
topdesign.twx
topdesign.ucf
topdesign.ut
topdesign.v
topdesign.xpi
topdesign_last_par.ncd
topdesign_map.ncd
topdesign_map.ngm
topdesign_pad.csv
topdesign_pad.txt
topdesign_summary.html
topdesign_vhdl.prj
._CotEditor_346
.classpath
.cproject
.cxl
.pdf
.project
.qmake.internal.cache
.synopsys_dc.setup
.synopsys_pt.setup
.untf
.xhdl3.xref

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