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msp430f6638数据手册

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MSP430F663x www.ti.com.cn 混合信号微控制器 ZHCS409C – JUNE 2010 – REVISED APRIL 2012 特性 1 •2 低电源电压范围: 1.8V 至 3.6V • 超低功耗 – 激活模式(AM): 所有系统时钟激活: 在 8MHz,3.0V,闪存程序执行时为 270µA/MHz(典型值) – 待机模式 (LPM3): 带有晶振的安全装置、且电源监控器可用、完全 RAM 保持、快速唤醒; 2.2V 时为 1.8µA,3.0V 时为 2.1µA(典型值) – 关断 RTC 模式 (LPM 3.5): 关断模式,带有晶振的有源实时时钟: 3.0V 时为 1.1µA(典型值) – 关断模式 (LPM4.5): 3.0V 时为 0.3µA(典型值) • 在 3µs 内从待机模式唤醒(典型值) • 16 位精简指令集 (RISC) 架构、扩展内存、高达 20MHz 的系统时钟 • 灵活的电源管理系统 – 具有可编程经稳压内核电源电压的完全集成低压 降稳压器 (LDO) – 电源电压监控、监视、和临时限电 • 统一时钟系统 – 针对频率稳定的锁频环路 (FLL) 控制环路 – 低功耗低频内部时钟源 (VLO) – 低频修整内部参照源 (REFO) – 32kHz 晶体 (XT1) – 高达 32MHz 的高频晶振 (XT2) • 四个 配有 3,5,或者 7 个捕捉/比较寄存器的 16 位寄存器 • 2 个通用串行通信接口 – USCI_A0 和 USCI_A1 每个都支持: – 增强型 UART 支持自动波特率检测 – IrDA 编码器和解码器 – 同步 SPI – USCI_B0 和 USCI_B1每个支持: – I2CTM – 同步 SPI • 全速通用串行总线 (USB) – 集成的 USB - 物理层 (PHY) – 集成 3.3V 和 1.8V USB 电源系统 – 集成 USB- 锁相环 (PLL) – 8 输入和 8 输出端点 • 具有内部共用基准、采样保持、和自动扫面功能的 12 位模数 (A/D) 转换器 • 具有同步功能的双通道 12 位数模 (D/A) 转换器 • 电压比较器 • 具有高达 160 段对比度控制的集成 LCD 驱动器 • 支持 32 位运算的硬件乘法器 • 串行板上编程,无需外部编程电压 • 6 通道内部直接内存访问 (DMA) • 具有电源电压后备开关的实时时钟模块 • 系列成员汇总于表 1 • 要获得完整的模块说明,请参阅《MSP430x5xx 和 MSP430x6xx 系列产品用户指南》 (文献 号:SLAU208) 说明 德州仪器 (TI) 的 MSP430 系列超低功耗微控制器由多个器件组成,这些器件特有针对多种应用的不同外设集。 这 种架构与 5 种低功耗模式相组合,专为在便携式测量应用中延长电池使用寿命而优化。 该器件具有一个强大的 16 位 RISC CPU,16 位寄存器和有助于获得最大编码效率的常数发生器。 此数控振荡器 (DCO) 可在 3 µs(典型 值)内实现从低功率模式唤醒至激活模式。 MSP430F663x 系列是配置有一个高性能 12 位模数 (A/D) 转换器,比较器,两个通用串行通信接口 (USCI),USB 2.0,硬件乘法器,DAM,四个 16 位定时器,带有报警功能的实时时钟,LCD 驱动器,和多达 74 个 I/O 引脚的微 控制器。 这个器件的典型应用包括模拟和数字传感器系统、数字电机控制、遥控、恒温器、数字定时器、手持仪表等。 可提供的系列产品汇总于表 1。 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 版权 © 2010–2012, Texas Instruments Incorporated English Data Sheet: SLAS566 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn 表 1. 系列产品 器件 闪存 (KB) MSP430F6638 256 MSP430F6637 192 MSP430F6636 128 MSP430F6635 256 MSP430F6634 192 MSP430F6633 128 MSP430F6632 256 MSP430F6631 192 MSP430F6630 128 USCI SRAM (KB) (1) Timer_A(2) Timer_B(3) 通道 A: UART,IrD 通道 B: SPI,I2C ADC12_A DAC12_A Comp_B (Ch) (Ch) (Ch) I/O 封装类型 A,SPI 16+2 5, 3, 3 7 2 12 个外部 2 通道,4 个 2 内部通道 12 74 100 PZ, 113 ZQW 16+2 5, 3, 3 7 2 12 个外部 2 通道,4 个 2 内部通道 12 74 100 PZ, 113 ZQW 16+2 5, 3, 3 7 2 12 个外部 2 通道,4 个 2 内部通道 12 74 100 PZ, 113 ZQW 16+2 5, 3, 3 7 2 12 个外部 2 通达,4 个 - 内部通道 12 74 100 PZ, 113 ZQW 16+2 5, 3, 3 7 2 12 个外部 2 通道,4 个 - 内部通道 12 74 100 PZ, 113 ZQW 16+2 5, 3, 3 7 2 12 个外部 2 通道,4 个 - 内部通道 12 74 100 PZ, 113 ZQW 16+2 5, 3, 3 7 2 2 - - 12 74 100 PZ, 113 ZQW 16+2 5, 3, 3 7 2 2 - - 12 74 100 PZ, 113 ZQW 16+2 5, 3, 3 7 2 2 - - 12 74 100 PZ, 113 ZQW (1) 列出的额外 2KB USB SRAM 在 USB 未使用时可被用作通用 SRAM。 (2) 序列中的每个数代表 Timer_A 的一个例示,并反映出其可使用的捕获/比较寄存器及脉宽调制 (PWM) 输出发生器的相关数量。 例如:一个 (3, 5) 数列将代表 Timer_A 的两个例示,第一个例示和第二个例示分别具有 3 个和 5 个捕获/比较寄存器和 PWM 输出发生器。 (3) 序列中的每个数代表 Timer_B 的一个例示,并反映出其可使用的捕获/比较寄存器及 PWM 输出发生器的相关数量。 例如:一个 (3, 5) 数 列将代表 Timer_B 的两个例示,第一个例示和第二个例示分别具有 3 个和 5 个捕获/比较寄存器和 PWM 输出发生器。 TA -40°C 至 85°C 表 2. 订购信息(1) 封装的器件 (2) 塑料 100 引脚薄型四方扁平 (TQFP) (PZ) 封装 塑料 113 焊球球状栅格阵列 (BGA) (ZQW) 封装 MSP430F6638IPZ MSP430F6638IZQW MSP430F6637IPZ MSP430F6637IZQW MSP430F6636IPZ MSP430F6636IZQW MSP430F6635IPZ MSP430F6635IZQW MSP430F6634IPZ MSP430F6634IZQW MSP430F6633IPZ MSP430F6633IZQW MSP430F6632IPZ MSP430F6632IZQW MSP430F6631IPZ MSP430F6631IZQW MSP430F6630IPZ MSP430F6630IZQW (1) 要获得最新的封装和订购信息,请参阅本文档末尾的封装选项附录,或者浏览 TI 网站www.ti.com。 (2) 封装图示,标准包装数量,散热数据,符号以及 PCB 设计指南: 。 2 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Functional Block Diagram, MSP430F6638, MSP430F6637, MSP430F6636 XIN XOUT DVCC DVSS AVCC AVSS RST/NMI PA PB PC PD P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x XT2IN XT2OUT Unified Clock System ACLK SMCLK MCLK 256KB 192KB 128KB Flash 16KB RAM +2KB RAM USB Buffer +8B Backup RAM CPUXV2 and Working Registers Power SYS Management Watchdog LDO SVM/SVS Brownout P2 Port Mapping Controller I/O Ports P1/P2 2×8 I/Os Interrupt Capability PA 1×16 I/Os I/O Ports P3/P4 2×8 I/Os Interrupt Capability PB 1×16 I/Os I/O Ports P5/P6 2×8 I/Os PC 1×16 I/Os I/O Ports P7/P8 1×6 I/Os 1×8 I/Os PD 1×14 I/Os I/O Ports P9 1×8 I/Os PE 1×8 I/Os USCI0,1 Ax: UART, IrDA, SPI USB Full-speed Bx: SPI, I2C PJ.x EEM (L: 8+2) JTAG/ SBW Interface/ Port PJ MPY32 TA0 Timer_A 5 CC Registers TA1 and TA2 2 Timer_A each with 3 CC Registers TB0 Timer_B 7 CC Registers RTC_B Battery Backup System CRC16 Comp_B ADC12_A 12 Bit 200 KSPS 16 Channels (12 ext/4 int) Autoscan DAC12_A 12 bit 2 channels voltage out REF Reference 1.5V, 2.0V, 2.5V LCD_B 160 Segments DMA 6 Channel Functional Block Diagram, MSP430F6635, MSP430F6634, MSP430F6633 XIN XOUT DVCC DVSS AVCC AVSS RST/NMI PA PB PC PD P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x XT2IN XT2OUT Unified Clock System ACLK SMCLK MCLK 256KB 192KB 128KB Flash 16KB RAM +2KB RAM USB Buffer +8B Backup RAM CPUXV2 and Working Registers Power SYS Management Watchdog LDO SVM/SVS Brownout P2 Port Mapping Controller I/O Ports P1/P2 2×8 I/Os Interrupt Capability PA 1×16 I/Os I/O Ports P3/P4 2×8 I/Os Interrupt Capability PB 1×16 I/Os I/O Ports P5/P6 2×8 I/Os PC 1×16 I/Os I/O Ports P7/P8 1×6 I/Os 1×8 I/Os PD 1×14 I/Os I/O Ports P9 1×8 I/Os PE 1×8 I/Os USCI0,1 Ax: UART, IrDA, SPI USB Full-speed Bx: SPI, I2C PJ.x EEM (L: 8+2) JTAG/ SBW Interface/ Port PJ MPY32 TA0 Timer_A 5 CC Registers TA1 and TA2 2 Timer_A each with 3 CC Registers TB0 Timer_B 7 CC Registers RTC_B Battery Backup System CRC16 Comp_B ADC12_A 12 Bit 200 KSPS 16 Channels (12 ext/4 int) Autoscan REF Reference 1.5V, 2.0V, 2.5V LCD_B 160 Segments DMA 6 Channel Copyright © 2010–2012, Texas Instruments Incorporated 3 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Functional Block Diagram, MSP430F6632, MSP430F6631, MSP430F6630 XIN XOUT DVCC DVSS AVCC AVSS RST/NMI PA PB PC PD P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x www.ti.com.cn XT2IN XT2OUT Unified Clock System ACLK SMCLK MCLK 256KB 192KB 128KB Flash 16KB RAM +2KB RAM USB Buffer +8B Backup RAM CPUXV2 and Working Registers Power SYS Management Watchdog LDO SVM/SVS Brownout P2 Port Mapping Controller I/O Ports P1/P2 2×8 I/Os Interrupt Capability PA 1×16 I/Os I/O Ports P3/P4 2×8 I/Os Interrupt Capability PB 1×16 I/Os I/O Ports P5/P6 2×8 I/Os PC 1×16 I/Os I/O Ports P7/P8 1×6 I/Os 1×8 I/Os PD 1×14 I/Os I/O Ports P9 1×8 I/Os PE 1×8 I/Os USCI0,1 Ax: UART, IrDA, SPI USB Full-speed Bx: SPI, I2C PJ.x EEM (L: 8+2) JTAG/ SBW Interface/ Port PJ MPY32 TA0 Timer_A 5 CC Registers TA1 and TA2 2 Timer_A each with 3 CC Registers TB0 Timer_B 7 CC Registers RTC_B Battery Backup System CRC16 Comp_B REF Reference 1.5V, 2.0V, 2.5V LCD_B 160 Segments DMA 6 Channel 4 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pin Designation, MSP430F6638IPZ, MSP430F6637IPZ, MSP430F6636IPZ 100 P6.3/CB3/A3 99 P6.2/CB2/A2 98 P6.1/CB1/A1 97 P6.0/CB0/A0 96 RST/NMI/SBWTDIO 95 PJ.3/TCK 94 PJ.2/TMS 93 PJ.1/TDI/TCLK 92 PJ.0/TDO 91 TEST/SBWTCK 90 DVSS3 89 DVCC3 88 P5.7/RTCCLK 87 VBAT 86 VBAK 85 P7.3/XT2OUT 84 P7.2/XT2IN 83 AVSS3 82 V18 81 VUSB 80 VBUS 79 PU.1/DM 78 PUR 77 PU.0/DP 76 VSSU P6.4/CB4/A4 1 P6.5/CB5/A5 2 P6.6/CB6/A6/DAC0 3 P6.7/CB7/A7/DAC1 4 P7.4/CB8/A12 5 P7.5/CB9/A13 6 P7.6/CB10/A14/DAC0 7 P7.7/CB11/A15/DAC1 8 P5.0/VREF+/VeREF+ 9 P5.1/VREF−/VeREF− 10 AVCC1 11 AVSS1 12 XIN 13 XOUT 14 AVSS2 15 P5.6/ADC12CLK/DMAE0 16 P2.0/P2MAP0 17 P2.1/P2MAP1 18 P2.2/P2MAP2 19 P2.3/P2MAP3 20 P2.4/P2MAP4 21 P2.5/P2MAP5 22 P2.6/P2MAP6/R03 23 P2.7/P2MAP7/LCDREF/R13 24 DVCC1 25 MSP430F6638 MSP430F6637 MSP430F6636 PZ PACKAGE (TOP VIEW) 75 P9.7/S0 74 P9.6/S1 73 P9.5/S2 72 P9.4/S3 71 P9.3/S4 70 P9.2/S5 69 P9.1/S6 68 P9.0/S7 67 P8.7/S8 66 P8.6/UCB1SOMI/UCB1SCL/S9 65 P8.5/UCB1SIMO/UCB1SDA/S10 64 DVCC2 63 DVSS2 62 P8.4/UCB1CLK/UCA1STE/S11 61 P8.3/UCA1RXD/UCA1SOMI/S12 60 P8.2/UCA1TXD/UCA1SIMO/S13 59 P8.1/UCB1STE/UCA1CLK/S14 58 P8.0/TB0CLK/S15 57 P4.7/TB0OUTH/SVMOUT/S16 56 P4.6/TB0.6/S17 55 P4.5/TB0.5/S18 54 P4.4/TB0.4/S19 53 P4.3/TB0.3/S20 52 P4.2/TB0.2/S21 51 P4.1/TB0.1/S22 DVSS1 26 VCORE 27 P5.2/R23 28 LCDCAP/R33 29 COM0 30 P5.3/COM1/S42 31 P5.4/COM2/S41 32 P5.5/COM3/S40 33 P1.0/TA0CLK/ACLK/S39 34 P1.1/TA0.0/S38 35 P1.2/TA0.1/S37 36 P1.3/TA0.2/S36 37 P1.4/TA0.3/S35 38 P1.5/TA0.4/S34 39 P1.6/TA0.1/S33 40 P1.7/TA0.2/S32 41 P3.0/TA1CLK/CBOUT/S31 42 P3.1/TA1.0/S30 43 P3.2/TA1.1/S29 44 P3.3/TA1.2/S28 45 P3.4/TA2CLK/SMCLK/S27 46 P3.5/TA2.0/S26 47 P3.6/TA2.1/S25 48 P3.7/TA2.2/S24 49 P4.0/TB0.0/S23 50 CAUTION: LCDCAP/R33 must be connected to DVSS if not used. Copyright © 2010–2012, Texas Instruments Incorporated 5 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pin Designation, MSP430F6635IPZ, MSP430F6634IPZ, MSP430F6633IPZ www.ti.com.cn 100 P6.3/CB3/A3 99 P6.2/CB2/A2 98 P6.1/CB1/A1 97 P6.0/CB0/A0 96 RST/NMI/SBWTDIO 95 PJ.3/TCK 94 PJ.2/TMS 93 PJ.1/TDI/TCLK 92 PJ.0/TDO 91 TEST/SBWTCK 90 DVSS3 89 DVCC3 88 P5.7/RTCCLK 87 VBAT 86 VBAK 85 P7.3/XT2OUT 84 P7.2/XT2IN 83 AVSS3 82 V18 81 VUSB 80 VBUS 79 PU.1/DM 78 PUR 77 PU.0/DP 76 VSSU P6.4/CB4/A4 1 P6.5/CB5/A5 2 P6.6/CB6/A6 3 P6.7/CB7/A7 4 P7.4/CB8/A12 5 P7.5/CB9/A13 6 P7.6/CB10/A14 7 P7.7/CB11/A15 8 P5.0/VREF+/VeREF+ 9 P5.1/VREF−/VeREF− 10 AVCC1 11 AVSS1 12 XIN 13 XOUT 14 AVSS2 15 P5.6/ADC12CLK/DMAE0 16 P2.0/P2MAP0 17 P2.1/P2MAP1 18 P2.2/P2MAP2 19 P2.3/P2MAP3 20 P2.4/P2MAP4 21 P2.5/P2MAP5 22 P2.6/P2MAP6/R03 23 P2.7/P2MAP7/LCDREF/R13 24 DVCC1 25 MSP430F6635 MSP430F6634 MSP430F6633 PZ PACKAGE (TOP VIEW) 75 P9.7/S0 74 P9.6/S1 73 P9.5/S2 72 P9.4/S3 71 P9.3/S4 70 P9.2/S5 69 P9.1/S6 68 P9.0/S7 67 P8.7/S8 66 P8.6/UCB1SOMI/UCB1SCL/S9 65 P8.5/UCB1SIMO/UCB1SDA/S10 64 DVCC2 63 DVSS2 62 P8.4/UCB1CLK/UCA1STE/S11 61 P8.3/UCA1RXD/UCA1SOMI/S12 60 P8.2/UCA1TXD/UCA1SIMO/S13 59 P8.1/UCB1STE/UCA1CLK/S14 58 P8.0/TB0CLK/S15 57 P4.7/TB0OUTH/SVMOUT/S16 56 P4.6/TB0.6/S17 55 P4.5/TB0.5/S18 54 P4.4/TB0.4/S19 53 P4.3/TB0.3/S20 52 P4.2/TB0.2/S21 51 P4.1/TB0.1/S22 DVSS1 26 VCORE 27 P5.2/R23 28 LCDCAP/R33 29 COM0 30 P5.3/COM1/S42 31 P5.4/COM2/S41 32 P5.5/COM3/S40 33 P1.0/TA0CLK/ACLK/S39 34 P1.1/TA0.0/S38 35 P1.2/TA0.1/S37 36 P1.3/TA0.2/S36 37 P1.4/TA0.3/S35 38 P1.5/TA0.4/S34 39 P1.6/TA0.1/S33 40 P1.7/TA0.2/S32 41 P3.0/TA1CLK/CBOUT/S31 42 P3.1/TA1.0/S30 43 P3.2/TA1.1/S29 44 P3.3/TA1.2/S28 45 P3.4/TA2CLK/SMCLK/S27 46 P3.5/TA2.0/S26 47 P3.6/TA2.1/S25 48 P3.7/TA2.2/S24 49 P4.0/TB0.0/S23 50 CAUTION: LCDCAP/R33 must be connected to DVSS if not used. 6 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pin Designation, MSP430F6632IPZ, MSP430F6631IPZ, MSP430F6630IPZ 100 P6.3/CB3 99 P6.2/CB2 98 P6.1/CB1 97 P6.0/CB0 96 RST/NMI/SBWTDIO 95 PJ.3/TCK 94 PJ.2/TMS 93 PJ.1/TDI/TCLK 92 PJ.0/TDO 91 TEST/SBWTCK 90 DVSS3 89 DVCC3 88 P5.7/RTCCLK 87 VBAT 86 VBAK 85 P7.3/XT2OUT 84 P7.2/XT2IN 83 AVSS3 82 V18 81 VUSB 80 VBUS 79 PU.1/DM 78 PUR 77 PU.0/DP 76 VSSU P6.4/CB4 1 P6.5/CB5 2 P6.6/CB6 3 P6.7/CB7 4 P7.4/CB8 5 P7.5/CB9 6 P7.6/CB10 7 P7.7/CB11 8 P5.0/VREF+/VeREF+ 9 P5.1/VREF−/VeREF− 10 AVCC1 11 AVSS1 12 XIN 13 XOUT 14 AVSS2 15 P5.6/DMAE0 16 P2.0/P2MAP0 17 P2.1/P2MAP1 18 P2.2/P2MAP2 19 P2.3/P2MAP3 20 P2.4/P2MAP4 21 P2.5/P2MAP5 22 P2.6/P2MAP6/R03 23 P2.7/P2MAP7/LCDREF/R13 24 DVCC1 25 MSP430F6632 MSP430F6631 MSP430F6630 PZ PACKAGE (TOP VIEW) 75 P9.7/S0 74 P9.6/S1 73 P9.5/S2 72 P9.4/S3 71 P9.3/S4 70 P9.2/S5 69 P9.1/S6 68 P9.0/S7 67 P8.7/S8 66 P8.6/UCB1SOMI/UCB1SCL/S9 65 P8.5/UCB1SIMO/UCB1SDA/S10 64 DVCC2 63 DVSS2 62 P8.4/UCB1CLK/UCA1STE/S11 61 P8.3/UCA1RXD/UCA1SOMI/S12 60 P8.2/UCA1TXD/UCA1SIMO/S13 59 P8.1/UCB1STE/UCA1CLK/S14 58 P8.0/TB0CLK/S15 57 P4.7/TB0OUTH/SVMOUT/S16 56 P4.6/TB0.6/S17 55 P4.5/TB0.5/S18 54 P4.4/TB0.4/S19 53 P4.3/TB0.3/S20 52 P4.2/TB0.2/S21 51 P4.1/TB0.1/S22 DVSS1 26 VCORE 27 P5.2/R23 28 LCDCAP/R33 29 COM0 30 P5.3/COM1/S42 31 P5.4/COM2/S41 32 P5.5/COM3/S40 33 P1.0/TA0CLK/ACLK/S39 34 P1.1/TA0.0/S38 35 P1.2/TA0.1/S37 36 P1.3/TA0.2/S36 37 P1.4/TA0.3/S35 38 P1.5/TA0.4/S34 39 P1.6/TA0.1/S33 40 P1.7/TA0.2/S32 41 P3.0/TA1CLK/CBOUT/S31 42 P3.1/TA1.0/S30 43 P3.2/TA1.1/S29 44 P3.3/TA1.2/S28 45 P3.4/TA2CLK/SMCLK/S27 46 P3.5/TA2.0/S26 47 P3.6/TA2.1/S25 48 P3.7/TA2.2/S24 49 P4.0/TB0.0/S23 50 CAUTION: LCDCAP/R33 must be connected to DVSS if not used. Copyright © 2010–2012, Texas Instruments Incorporated 7 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pin Designation, MSP430F6638IZQW, MSP430F6637IZQW, MSP430F6636IZQW, MSP430F6635IZQW, MSP430F6634IZQW, MSP430F6633IZQW, MSP430F6632IZQW, MSP430F6631IZQW, MSP430F6630IZQW ZQW PACKAGE (TOP VIEW) www.ti.com.cn A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C11 C12 D1 D2 D4 D5 D6 D7 D8 D9 D11 D12 E1 E2 E4 E5 E6 E7 E8 E9 E11 E12 F1 F2 F4 F5 F8 F9 F11 F12 G1 G2 G4 G5 G8 G9 G11 G12 H1 H2 H4 H5 H6 H7 H8 H9 H11 H12 J1 J2 J4 J5 J6 J7 J8 J9 J11 J12 K1 K2 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 NOTE: For terminal assignments, see Table 3 8 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn TERMINAL NAME P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1 P7.4/CB8/A12 P7.5/CB9/A13 P7.6/CB10/A14/DAC0 P7.7/CB11/A15/DAC1 P5.0/VREF+/VeREF+ P5.1/VREF-/VeREFAVCC1 AVSS1 XIN XOUT AVSS2 MSP430F663x Table 3. Terminal Functions ZHCS409C – JUNE 2010 – REVISED APRIL 2012 NO. I/O (1) PZ ZQW DESCRIPTION General-purpose digital I/O 1 A1 I/O Comparator_B input CB4 Analog input A4 – ADC(not available on F6632, F6631, F6630 devices) General-purpose digital I/O 2 B2 I/O Comparator_B input CB5 Analog input A5 – ADC(not available on F6632, F6631, F6630 devices) General-purpose digital I/O Comparator_B input CB6 3 B1 I/O Analog input A6 – ADC (not available on F6632, F6631, F6630 devices) DAC12.0 output (not available on F6635, F6634, F6633, F6632, F6631, F6630 devices) General-purpose digital I/O Comparator_B input CB7 4 C2 I/O Analog input A7 – ADC (not available on F6632, F6631, F6630 devices) DAC12.1 output (not available on F6635, F6634, F6633, F6632, F6631, F6630 devices) General-purpose digital I/O 5 C1 I/O Comparator_B input CB8 Analog input A12 –ADC (not available on F6632, F6631, F6630 devices) General-purpose digital I/O 6 C3 I/O Comparator_B input CB9 Analog input A13 – ADC (not available on F6632, F6631, F6630 devices) General-purpose digital I/O Comparator_B input CB10 7 D2 I/O Analog input A14 – ADC (not available on F6632, F6631, F6630 devices) DAC12.0 output (not available on F6635, F6634, F6633, F6632, F6631, F6630 devices) General-purpose digital I/O Comparator_B input CB11 8 D1 I/O Analog input A15 – ADC (not available on F6632, F6631, F6630 devices) DAC12.1 output (not available on F6635, F6634, F6633, F6632, F6631, F6630 devices) General-purpose digital I/O 9 D4 I/O Output of reference voltage to the ADC Input for an external reference voltage to the ADC General-purpose digital I/O 10 E4 I/O Negative terminal for the ADC's reference voltage for both sources, the internal reference voltage, or an external applied reference voltage 11 E1, E2 Analog power supply 12 F2 Analog ground supply 13 F1 I Input terminal for crystal oscillator XT1 14 G1 O Output terminal of crystal oscillator XT1 15 G2 Analog ground supply (1) I = input, O = output, N/A = not available on this package offering Copyright © 2010–2012, Texas Instruments Incorporated 9 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn TERMINAL NAME P5.6/ADC12CLK/DMAE0 P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6/R03 P2.7/P2MAP7/LCDREF/R13 DVCC1 DVSS1 VCORE (2) P5.2/R23 LCDCAP/R33 COM0 P5.3/COM1/S42 P5.4/COM2/S41 P5.5/COM3/S40 Table 3. Terminal Functions (continued) NO. I/O (1) PZ ZQW DESCRIPTION General-purpose digital I/O 16 H1 I/O Conversion clock output ADC (not available on F6632, F6631, F6630 devices) DMA external trigger input 17 G4 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output 18 H2 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data 19 J1 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock 20 H4 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable 21 J2 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out 22 K1 I/O General-purpose digital I/O with port interrupt and mappable secondary function Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in General-purpose digital I/O with port interrupt and mappable secondary function 23 K2 I/O Default mapping: no secondary function Input/output port of lowest analog LCD voltage (V5) General-purpose digital I/O with port interrupt and mappable secondary function 24 L2 I/O Default mapping: no secondary function External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4) 25 L1 Digital power supply 26 M1 Digital ground supply 27 M2 Regulated core power supply (internal use only, no external current loading) 28 L3 I/O General-purpose digital I/O Input/output port of second most positive analog LCD voltage (V2) LCD capacitor connection 29 M3 I/O Input/output port of most positive analog LCD voltage (V1) CAUTION: LCDCAP/R33 must be connected to DVSS if not used. 30 J4 O LCD common output COM0 for LCD backplane General-purpose digital I/O 31 L4 I/O LCD common output COM1 for LCD backplane LCD segment output S42 General-purpose digital I/O 32 M4 I/O LCD common output COM2 for LCD backplane LCD segment output S41 General-purpose digital I/O 33 J5 I/O LCD common output COM3 for LCD backplane LCD segment output S40 (2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. 10 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn TERMINAL NAME P1.0/TA0CLK/ACLK/S39 P1.1/TA0.0/S38 P1.2/TA0.1/S37 P1.3/TA0.2/S36 P1.4/TA0.3/S35 P1.5/TA0.4/S34 P1.6/TA0.1/S33 P1.7/TA0.2/S32 P3.0/TA1CLK/CBOUT/S31 P3.1/TA1.0/S30 P3.2/TA1.1/S29 P3.3/TA1.2/S28 P3.4/TA2CLK/SMCLK/S27 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 3. Terminal Functions (continued) NO. I/O (1) PZ ZQW DESCRIPTION General-purpose digital I/O with port interrupt 34 L5 I/O Timer TA0 clock signal TACLK input ACLK output (divided by 1, 2, 4, 8, 16, or 32) LCD segment output S39 General-purpose digital I/O with port interrupt 35 M5 I/O Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output BSL transmit output LCD segment output S38 General-purpose digital I/O with port interrupt 36 J6 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output BSL receive input LCD segment output S37 General-purpose digital I/O with port interrupt 37 H6 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output LCD segment output S36 General-purpose digital I/O with port interrupt 38 M6 I/O Timer TA0 CCR3 capture: CCI3A input compare: Out3 output LCD segment output S35 General-purpose digital I/O with port interrupt 39 L6 I/O Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output LCD segment output S34 General-purpose digital I/O with port interrupt 40 J7 I/O Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output LCD segment output S33 General-purpose digital I/O with port interrupt 41 M7 I/O Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output LCD segment output S32 General-purpose digital I/O with port interrupt 42 L7 I/O Timer TA1 clock input Comparator_B output LCD segment output S31 General-purpose digital I/O with port interrupt 43 H7 I/O Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output LCD segment output S30 General-purpose digital I/O with port interrupt 44 M8 I/O Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output LCD segment output S29 General-purpose digital I/O with port interrupt 45 L8 I/O Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S28 General-purpose digital I/O with port interrupt 46 J8 I/O Timer TA2 clock input SMCLK output LCD segment output S27 Copyright © 2010–2012, Texas Instruments Incorporated 11 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn TERMINAL NAME P3.5/TA2.0/S26 P3.6/TA2.1/S25 P3.7/TA2.2/S24 P4.0/TB0.0/S23 P4.1/TB0.1/S22 P4.2/TB0.2/S21 P4.3/TB0.3/S20 P4.4/TB0.4/S19 P4.5/TB0.5/S18 P4.6/TB0.6/S17 P4.7/TB0OUTH/SVMOUT/S16 P8.0/TB0CLK/S15 P8.1/UCB1STE/UCA1CLK/S14 P8.2/UCA1TXD/UCA1SIMO/S13 Table 3. Terminal Functions (continued) NO. I/O (1) PZ ZQW DESCRIPTION General-purpose digital I/O with port interrupt 47 M9 I/O Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output LCD segment output S26 General-purpose digital I/O with port interrupt 48 L9 I/O Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output LCD segment output S25 General-purpose digital I/O with port interrupt 49 M10 I/O Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S24 General-purpose digital I/O with port interrupt 50 J9 I/O Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output LCD segment output S23 General-purpose digital I/O with port interrupt 51 M11 I/O Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output LCD segment output S22 General-purpose digital I/O with port interrupt 52 L10 I/O Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S21 General-purpose digital I/O with port interrupt 53 M12 I/O Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output LCD segment output S20 General-purpose digital I/O with port interrupt 54 L12 I/O Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output LCD segment output S19 General-purpose digital I/O with port interrupt 55 L11 I/O Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output LCD segment output S18 General-purpose digital I/O with port interrupt 56 K11 I/O Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output LCD segment output S17 General-purpose digital I/O with port interrupt 57 K12 I/O Timer TB0: Switch all PWM outputs high impedance SVM output LCD segment output S16 General-purpose digital I/O 58 J11 I/O Timer TB0 clock input LCD segment output S15 General-purpose digital I/O 59 J12 I/O USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output LCD segment output S14 General-purpose digital I/O 60 H11 I/O USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out LCD segment output S13 12 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 TERMINAL NAME P8.3/UCA1RXD/UCA1SOMI/S12 P8.4/UCB1CLK/UCA1STE/S11 DVSS2 DVCC2 P8.5/UCB1SIMO/UCB1SDA/S10 P8.6/UCB1SOMI/UCB1SCL/S9 P8.7/S8 P9.0/S7 P9.1/S6 P9.2/S5 P9.3/S4 P9.4/S3 P9.5/S2 P9.6/S1 P9.7/S0 VSSU PU.0/DP PUR PU.1/DM VBUS VUSB V18 Table 3. Terminal Functions (continued) NO. I/O (1) PZ ZQW DESCRIPTION General-purpose digital I/O 61 H12 I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in LCD segment output S12 General-purpose digital I/O 62 G11 I/O USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable LCD segment output S11 63 G12 Digital ground supply 64 F12 Digital power supply General-purpose digital I/O 65 F11 I/O USCI_B1 SPI slave in/master out; USCI_B1 I2C data LCD segment output S10 General-purpose digital I/O 66 G9 I/O USCI_B1 SPI slave out/master in; USCI_B1 I2C clock LCD segment output S9 67 E12 I/O General-purpose digital I/O LCD segment output S8 68 E11 I/O General-purpose digital I/O LCD segment output S7 69 F9 I/O General-purpose digital I/O LCD segment output S6 70 D12 I/O General-purpose digital I/O LCD segment output S5 71 D11 I/O General-purpose digital I/O LCD segment output S4 72 E9 I/O General-purpose digital I/O LCD segment output S3 73 C12 I/O General-purpose digital I/O LCD segment output S2 74 C11 I/O General-purpose digital I/O LCD segment output S1 75 D9 I/O General-purpose digital I/O LCD segment output S0 B11 76 and B12 USB PHY ground supply 77 A12 I/O General-purpose digital I/O - controlled by USB control register USB data terminal DP USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to 78 B10 I/O invoke the default USB BSL. Recommended 1-MΩ resistor to ground. See USB BSL for more information. 79 A11 I/O General-purpose digital I/O - controlled by USB control register USB data terminal DM 80 A10 USB LDO input (connect to USB power source) 81 A9 USB LDO output 82 B9 USB regulated power (internal use only, no external current loading) Copyright © 2010–2012, Texas Instruments Incorporated 13 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn TERMINAL NAME AVSS3 P7.2/XT2IN P7.3/XT2OUT VBAK VBAT P5.7/RTCCLK DVCC3 DVSS3 TEST/SBWTCK PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK RST/NMI/SBWTDIO P6.0/CB0/A0 P6.1/CB1/A1 P6.2/CB2/A2 P6.3/CB3/A3 Table 3. Terminal Functions (continued) NO. I/O (1) PZ ZQW 83 A8 Analog ground supply DESCRIPTION 84 B8 I/O General-purpose digital I/O Input terminal for crystal oscillator XT2 85 B7 I/O General-purpose digital I/O Output terminal of crystal oscillator XT2 86 A7 87 D8 Capacitor for backup subsystem. Do not load this pin externally. For capacitor values, see CBAK in Recommended Operating Conditions. Backup or secondary supply voltage. If backup voltage is not supplied, connect to DVCC externally. 88 D7 I/O General-purpose digital I/O RTCCLK output 89 A6 Digital power supply 90 A5 Digital ground supply 91 B6 I Test mode pin; selects digital I/O on JTAG pins Spy-bi-wire input clock 92 B5 I/O General-purpose digital I/O Test data output port 93 A4 I/O General-purpose digital I/O Test data input or test clock input 94 E7 I/O General-purpose digital I/O Test mode select 95 D6 I/O General-purpose digital I/O Test clock Reset input (active low) 96 A3 I/O Non-maskable interrupt input Spy-bi-wire data input/output General-purpose digital I/O 97 B4 I/O Comparator_B input CB0 Analog input A0 – ADC (not available on F6632, F6631, F6630 devices) General-purpose digital I/O 98 B3 I/O Comparator_B input CB1 Analog input A1 – ADC (not available on F6632, F6631, F6630 devices) General-purpose digital I/O 99 A2 I/O Comparator_B input CB2 Analog input A2 – ADC (not available on F6632, F6631, F6630 devices) 100 D5 General-purpose digital I/O I/O Comparator_B input CB3 Analog input A3 – ADC (not available on F6632, F6631, F6630 devices) 14 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn TERMINAL NAME Reserved MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 3. Terminal Functions (continued) NO. I/O (1) DESCRIPTION PZ ZQW E5, E6, E8, F4, F5, N/A F8, G5, G8, H5, H8, H9 Reserved. It is recommended to connect to ground (DVSS, AVSS). Copyright © 2010–2012, Texas Instruments Incorporated 15 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 SHORT-FORM DESCRIPTION www.ti.com.cn CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. Instruction Set The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 4 shows examples of the three types of instruction formats; Table 5 shows the address modes. Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 INSTRUCTION WORD FORMAT Dual operands, source-destination Single operands, destination only Relative jump, un/conditional Table 4. Instruction Word Formats EXAMPLE ADD R4,R5 CALL R8 JNE OPERATION R4 + R5 → R5 PC → (TOS), R8 → PC Jump-on-equal bit = 0 ADDRESS MODE S (1) Register + Indexed + Symbolic (PC relative) + Absolute + Indirect + Indirect auto-increment + Immediate + (1) S = source, D = destination Table 5. Address Mode Descriptions D (1) SYNTAX EXAMPLE + MOV Rs,Rd MOV R10,R11 + MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) + MOV EDE,TONI + MOV &MEM, &TCDAT MOV @Rn,Y(Rm) MOV @R10,Tab(R6) MOV @Rn+,Rm MOV @R10+,R11 MOV #X,TONI MOV #45,TONI OPERATION R10 → R11 M(2+R5) → M(6+R6) M(EDE) → M(TONI) M(MEM) → M(TCDAT) M(R10) → M(Tab+R6) M(R10) → R11 R10 + 2 → R10 #45 → M(TONI) 16 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Operating Modes The MSP430 has one active mode and seven software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following seven operating modes can be configured by software: • Active mode (AM) – All clocks are active • Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active, MCLK is disabled – FLL loop control remains active • Low-power mode 1 (LPM1) – CPU is disabled – FLL loop control is disabled – ACLK and SMCLK remain active, MCLK is disabled • Low-power mode 2 (LPM2) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc generator remains enabled – ACLK remains active • Low-power mode 3 (LPM3) – CPU is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc generator is disabled – ACLK remains active • Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK, FLL loop control, and DCOCLK are disabled – DCO's dc generator is disabled – Crystal oscillator is stopped – Complete data retention • Low-power mode 3.5 (LPM3.5) – Internal regulator disabled – No data retention – RTC enabled and clocked by low-frequency oscillator – Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4 • Low-power mode 4.5 (LPM4.5) – Internal regulator disabled – No data retention – Wakeup from RST/NMI, RTC_B, P1, P2, P3, and P4 Copyright © 2010–2012, Texas Instruments Incorporated 17 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 6. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations INTERRUPT SOURCE INTERRUPT FLAG System Reset Power-Up, External Reset Watchdog Timeout, Key Violation Flash Memory Key Violation System NMI PMM Vacant Memory Access JTAG Mailbox User NMI NMI Oscillator Fault Flash Memory Access Violation Comp_B Timer TB0 Timer TB0 Watchdog Interval Timer Mode USCI_A0 Receive or Transmit USCI_B0 Receive or Transmit ADC12_A (4) Timer TA0 Timer TA0 USB_UBM DMA Timer TA1 Timer TA1 I/O Port P1 USCI_A1 Receive or Transmit USCI_B1 Receive or Transmit I/O Port P2 LCD_B RTC_B DAC12_A (5) Timer TA2 Timer TA2 I/O Port P3 I/O Port P4 WDTIFG, KEYV (SYSRSTIV)(1)(2) SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)(1) NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV) (1) (2) Comparator B interrupt flags (CBIV)(1)(3) TB0CCR0 CCIFG0(3) TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6, TB0IFG (TBIV)(1) (3) WDTIFG UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(3) UCB0RXIFG, UCB0TXIFG (UCB0IV)(1)(3) ADC12IFG0 to ADC12IFG15 (ADC12IV)(1)(3) TA0CCR0 CCIFG0(3) TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0IFG (TA0IV)(1)(3) USB interrupts (USBIV)(1)(3) DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG, DMA4IFG, DMA5IFG (DMAIV)(1)(3) TA1CCR0 CCIFG0(3) TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV)(1)(3) P1IFG.0 to P1IFG.7 (P1IV)(1) (3) UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(3) UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(3) P2IFG.0 to P2IFG.7 (P2IV)(1) (3) LCD_B Interrupt Flags (LCDBIV)(1) RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1)(3) DAC12_0IFG, DAC12_1IFG(1)(3) TA2CCR0 CCIFG0(3) TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2, TA2IFG (TA2IV)(1)(3) P3IFG.0 to P3IFG.7 (P3IV)(1)(3) P4IFG.0 to P4IFG.7 (P4IV)(1)(3) SYSTEM INTERRUPT Reset (Non)maskable (Non)maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable WORD ADDRESS 0FFFEh 0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h 0FFDEh 0FFDCh 0FFDAh 0FFD8h 0FFD6h 0FFD4h 0FFD2h 0FFD0h 0FFCEh 0FFCCh 0FFCAh PRIORITY 63, highest 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 (1) Multiple source flags (2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (3) Interrupt flags are located in the module. (4) Only on devices with peripheral module ADC12_A, otherwise reserved. (5) Only on devices with peripheral module DAC12_A, otherwise reserved. 18 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 6. Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations (continued) INTERRUPT SOURCE Reserved INTERRUPT FLAG Reserved (6) SYSTEM INTERRUPT WORD ADDRESS 0FFC8h ⋮ 0FF80h PRIORITY 36 ⋮ 0, lowest (6) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatability with other devices, it is recommended to reserve these locations. Memory Organization Memory (flash) Main: interrupt vector Total Size Bank 3 Table 7. Memory Organization(1)(2) MSP430F6636 MSP430F6633 MSP430F6630 128KB 00FFFFh–00FF80h N/A MSP430F6637 MSP430F6634 MSP430F6631 192KB 00FFFFh–00FF80h N/A Main: code memory RAM USB RAM(3) Information memory (flash) Bootstrap loader (BSL) memory (flash) Peripherals Bank 2 Bank 1 Bank 0 Sector 3 Sector 2 Sector 1 Sector 0 Size RAM Info A Info B Info C Info D BSL 3 BSL 2 BSL 1 BSL 0 Size N/A 64 KB 027FFF-018000h 64 KB 017FFF-008000h 4 KB 0063FFh–005400h 4 KB 0053FFh–004400h 4 KB 0043FFh–003400h 4 KB 0033FFh–002400h 2KB 0023FFh-001C00h 128 B 0019FFh–001980h 128 B 00197Fh–001900h 128 B 0018FFh–001880h 128 B 00187Fh–001800h 512 B 0017FFh–001600h 512 B 0015FFh–001400h 512 B 0013FFh–001200h 512 B 0011FFh–001000h 4KB 000FFFh–000000h 64 KB 037FFF-028000h 64 KB 027FFF-018000h 64 KB 017FFF-008000h 4 KB 0063FFh–005400h 4 KB 0053FFh–004400h 4 KB 0043FFh–003400h 4 KB 0033FFh–002400h 2KB 0023FFh-001C00h 128 B 0019FFh–001980h 128 B 00197Fh–001900h 128 B 0018FFh–001880h 128 B 00187Fh–001800h 512 B 0017FFh–001600h 512 B 0015FFh–001400h 512 B 0013FFh–001200h 512 B 0011FFh–001000h 4KB 000FFFh–000000h (1) N/A = Not available. (2) Backup RAM is accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. (3) USB RAM can be used as general purpose RAM when not used for USB operation. MSP430F6638 MSP430F6635 MSP430F6632 256KB 00FFFFh–00FF80h 64 KB 047FFF-038000h 64 KB 037FFF-028000h 64 KB 027FFF-018000h 64 KB 017FFF-008000h 4 KB 0063FFh–005400h 4 KB 0053FFh–004400h 4 KB 0043FFh–003400h 4 KB 0033FFh–002400h 2KB 0023FFh-001C00h 128 B 0019FFh–001980h 128 B 00197Fh–001900h 128 B 0018FFh–001880h 128 B 00187Fh–001800h 512 B 0017FFh–001600h 512 B 0015FFh–001400h 512 B 0013FFh–001200h 512 B 0011FFh–001000h 4KB 000FFFh–000000h Copyright © 2010–2012, Texas Instruments Incorporated 19 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Bootstrap Loader (BSL) The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the device memory via the BSL is protected by an user-defined password. For complete description of the features of the BSL and its implementation, see MSP430 Programming Via the Bootstrap Loader (BSL) (SLAU319). USB BSL All devices come pre-programmed with the USB BSL. Use of the USB BSL requires external access to the six pins shown in Table 8. In addition to these pins, the application must support external components necessary for normal USB operation; for example, the proper crystal on XT2IN and XT2OUT or proper decoupling. Table 8. USB BSL Pin Requirements and Functions DEVICE SIGNAL RST/NMI/SBWTDIO PU.0/DP PU.1/DM PUR VBUS VSSU BSL FUNCTION Entry sequence signal USB data terminal DP USB data terminal DM USB pullup resistor terminal USB bus power supply USB ground supply NOTE The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is pulled high externally, then the BSL is invoked. Therefore, unless the application is invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. Applying a 1-MΩ resistor to ground is recommended. UART BSL A UART BSL is also available that can be programmed by the user into the BSL memory by replacing the preprogrammed, factory supplied, USB BSL. Use of the UART BSL requires external access to the six pins shown in Table 9. Table 9. UART BSL Pin Requirements and Functions DEVICE SIGNAL RST/NMI/SBWTDIO TEST/SBWTCK P1.1 P1.2 VCC VSS BSL FUNCTION Entry sequence signal Entry sequence signal Data transmit Data receive Power supply Ground supply JTAG Operation JTAG Standard Interface The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. The JTAG pin requirements are shown in Table 10. For further details on interfacing to development tools and device programmers, see the MSP430(tm) Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320). 20 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 10. JTAG Pin Requirements and Functions DEVICE SIGNAL PJ.3/TCK PJ.2/TMS PJ.1/TDI/TCLK PJ.0/TDO TEST/SBWTCK RST/NMI/SBWTDIO VCC VSS DIRECTION IN IN IN OUT IN IN FUNCTION JTAG clock input JTAG state control JTAG data input, TCLK input JTAG data output Enable JTAG pins External reset Power supply Ground supply Spy-Bi-Wire Interface In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. SpyBi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire interface pin requirements are shown in Table 11. For further details on interfacing to development tools and device programmers, see the MSP430(tm) Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320). Table 11. Spy-Bi-Wire Pin Requirements and Functions DEVICE SIGNAL TEST/SBWTCK RST/NMI/SBWTDIO VCC VSS DIRECTION IN IN, OUT FUNCTION Spy-Bi-Wire clock input Spy-Bi-Wire data input/output Power supply Ground supply Flash Memory The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 128 bytes each. Each segment in main memory is 512 bytes in size. • Segments 0 to n may be erased in one step, or each segment may be individually erased. • Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory. • Segment A can be locked separately. RAM Memory The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage, however all data is lost. Features of the RAM memory include: • RAM memory has n sectors. The size of a sector can be found in Memory Organization. • Each sector 0 to n can be complete disabled, however data retention is lost. • Each sector 0 to n automatically enters low power retention mode when possible. • For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required. Backup RAM Memory The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during operation from a backup supply if the Battery Backup System module is implemented. There are 8 bytes of Backup RAM available on MSP430F663x. It can be wordwise accessed via the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3. Copyright © 2010–2012, Texas Instruments Incorporated 21 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Digital I/O There are up to nine 8-bit I/O ports implemented: P1 through P9 are complete, and port PJ contains four individual I/O ports. • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt conditions is possible. • Programmable pullup or pulldown on all ports. • Programmable drive strength on all ports. • Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4. • Read/write access to port-control registers is supported by all instructions. • Ports can be accessed byte-wise (P1 through P9) or word-wise in pairs (PA through PD). Port Mapping Controller The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2. VALUE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Table 12. Port Mapping, Mnemonics and Functions PxMAPy MNEMONIC PM_NONE PM_CBOUT PM_TB0CLK PM_ADC12CLK PM_DMAE0 PM_SVMOUT PM_TB0OUTH PM_TB0CCR0B PM_TB0CCR1B PM_TB0CCR2B PM_TB0CCR3B PM_TB0CCR4B PM_TB0CCR5B PM_TB0CCR6B PM_UCA0RXD PM_UCA0SOMI PM_UCA0TXD PM_UCA0SIMO PM_UCA0CLK PM_UCB0STE PM_UCB0SOMI PM_UCB0SCL PM_UCB0SIMO PM_UCB0SDA PM_UCB0CLK PM_UCA0STE PM_MCLK Reserved INPUT PIN FUNCTION OUTPUT PIN FUNCTION None - DVSS Comparator_B output Timer TB0 clock input - - ADC12CLK DMAE0 Input - - SVM output Timer TB0 high impedance input TB0OUTH - Timer TB0 CCR0 capture input CCI0B Timer TB0: TB0.0 compare output Out0 Timer TB0 CCR1 capture input CCI1B Timer TB0: TB0.1 compare output Out1 Timer TB0 CCR2 capture input CCI2B Timer TB0: TB0.2 compare output Out2 Timer TB0 CCR3 capture input CCI3B Timer TB0: TB0.3 compare output Out3 Timer TB0 CCR4 capture input CCI4B Timer TB0: TB0.4 compare output Out4 Timer TB0 CCR5 capture input CCI5B Timer TB0: TB0.5 compare output Out5 Timer TB0 CCR6 capture input CCI6B Timer TB0: TB0.6 compare output Out6 USCI_A0 UART RXD (Direction controlled by USCI - input) USCI_A0 SPI slave out master in (direction controlled by USCI) USCI_A0 UART TXD (Direction controlled by USCI - output) USCI_A0 SPI slave in master out (direction controlled by USCI) USCI_A0 clock input/output (direction controlled by USCI) USCI_B0 SPI slave transmit enable (direction controlled by USCI - input) USCI_B0 SPI slave out master in (direction controlled by USCI) USCI_B0 I2C clock (open drain and direction controlled by USCI) USCI_B0 SPI slave in master out (direction controlled by USCI) USCI_B0 I2C data (open drain and direction controlled by USCI) USCI_B0 clock input/output (direction controlled by USCI) USCI_A0 SPI slave transmit enable (direction controlled by USCI - input) - MCLK Reserved for test purposes. Do not use this setting. 22 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 12. Port Mapping, Mnemonics and Functions (continued) VALUE 19 20-30 31 (0FFh)(1) PxMAPy MNEMONIC Reserved Reserved PM_ANALOG INPUT PIN FUNCTION OUTPUT PIN FUNCTION Reserved for test purposes. Do not use this setting. None DVSS Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when applying analog signals. (1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored, which results in a read out value of 31. PIN P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6/R03 P2.7/P2MAP7/LCDREF/R13 Table 13. Default Mapping PxMAPy MNEMONIC PM_UCB0STE, PM_UCA0CLK PM_UCB0SIMO, PM_UCB0SDA PM_UCB0SOMI, PM_UCB0SCL PM_UCB0CLK, PM_UCA0STE PM_UCA0TXD, PM_UCA0SIMO PM_UCA0RXD, PM_UCA0SOMI PM_NONE PM_NONE INPUT PIN FUNCTION OUTPUT PIN FUNCTION USCI_B0 SPI slave transmit enable (direction controlled by USCI - input), USCI_A0 clock input/output (direction controlled by USCI) USCI_B0 SPI slave in master out (direction controlled by USCI), USCI_B0 I2C data (open drain and direction controlled by USCI) USCI_B0 SPI slave out master in (direction controlled by USCI), USCI_B0 I2C clock (open drain and direction controlled by USCI) USCI_B0 clock input/output (direction controlled by USCI), USCI_A0 SPI slave transmit enable (direction controlled by USCI - input) USCI_A0 UART TXD (direction controlled by USCI - output), USCI_A0 SPI slave in master out (direction controlled by USCI) USCI_A0 UART RXD (direction controlled by USCI - input), USCI_A0 SPI slave out master in (direction controlled by USCI) - DVSS - DVSS Oscillator and System Clock The clock system in the MSP430F663x family of devices is supported by the Unified Clock System (UCS) module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in 3 µs (typical). The UCS module provides the following clock signals: • Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitallycontrolled oscillator DCO. • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to ACLK. • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by same sources available to ACLK. • ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32. Power Management Module (PMM) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The SVS and SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supply and core supply. Copyright © 2010–2012, Texas Instruments Incorporated 23 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Hardware Multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-bit, 24-bit, 16-bit, and 8-bit operands. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. Real-Time Clock (RTC_B) The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes, hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in LPM3.5 mode and operation from a backup supply. Watchdog Timer (WDT_A) The primary function of the watchdog timer (WDT_A) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. System Module (SYS) The SYS module handles many of the system functions within the device. These include power-on reset and power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootstrap loader entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange mechanism via JTAG called a JTAG mailbox that can be used in the application. INTERRUPT VECTOR REGISTER SYSRSTIV, System Reset Table 14. System Module Interrupt Vector Registers INTERRUPT EVENT No interrupt pending Brownout (BOR) RST/NMI (BOR) DoBOR (BOR) LPM3.5 or LPM4.5 wakeup (BOR) Security violation (BOR) SVSL (POR) SVSH (POR) SVML_OVP (POR) SVMH_OVP (POR) DoPOR (POR) WDT timeout (PUC) WDT key violation (PUC) KEYV flash key violation (PUC) Reserved Peripheral area fetch (PUC) PMM key violation (PUC) Reserved WORD ADDRESS 019Eh OFFSET 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h to 3Eh PRIORITY Highest Lowest 24 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 14. System Module Interrupt Vector Registers (continued) INTERRUPT VECTOR REGISTER SYSSNIV, System NMI SYSUNIV, User NMI SYSBERRIV, Bus Error INTERRUPT EVENT No interrupt pending SVMLIFG SVMHIFG DLYLIFG DLYHIFG VMAIFG JMBINIFG JMBOUTIFG SVMLVLRIFG SVMHVLRIFG Reserved No interrupt pending NMIFG OFIFG ACCVIFG BUSIFG Reserved No interrupt pending USB wait state timeout Reserved WORD ADDRESS 019Ch 019Ah 0198h OFFSET 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h to 1Eh 00h 02h 04h 06h 08h 0Ah to 1Eh 00h 02h 04h to 1Eh PRIORITY Highest Lowest Highest Lowest Highest Lowest Copyright © 2010–2012, Texas Instruments Incorporated 25 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12_A conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments described in Table 15. Table 15. DMA Trigger Assignments(1) Trigger 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 DMA5IFG 1 DMA0IFG Channel 2 3 DMAREQ TA0CCR0 CCIFG TA0CCR2 CCIFG TA1CCR0 CCIFG TA1CCR2 CCIFG TA2CCR0 CCIFG TA2CCR2 CCIFG TBCCR0 CCIFG TBCCR2 CCIFG Reserved Reserved Reserved Reserved Reserved Reserved Reserved UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG UCA1RXIFG UCA1TXIFG UCB1RXIFG UCB1TXIFG ADC12IFGx (2) DAC12_0IFG (3) DAC12_1IFG (3) USB FNRXD USB ready MPY ready DMA1IFG DMA2IFG DMAE0 4 DMA3IFG 5 DMA4IFG (1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers will not cause any DMA trigger event when selected. (2) Only on devices with peripheral module ADC12_A. Reserved on devices without ADC. (3) Only on devices with peripheral module DAC12_A. Reserved on devices without DAC. 26 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Universal Serial Communication Interface (USCI) The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions, A and B. The USCI_An module provides support for SPI (3 or 4 pin), UART, enhanced UART, or IrDA. The USCI_Bn module provides support for SPI (3 or 4 pin) or I2C. The MSP430F663x series includes two complete USCI modules (n = 0 to 1). Timer TA0 Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 16. Timer TA0 Signal Connections INPUT PIN NUMBER PZ ZQW 34-P1.0 L5-P1.0 34-P1.0 35-P1.1 L5-P1.0 M5-P1.1 36-P1.2 40-P1.6 J6-P1.2 J7-P1.6 DEVICE INPUT SIGNAL TA0CLK ACLK SMCLK TA0CLK TA0.0 DVSS DVSS DVCC TA0.1 TA0.1 DVSS MODULE INPUT SIGNAL TACLK ACLK SMCLK TACLK CCI0A CCI0B GND VCC CCI1A CCI1B GND MODULE BLOCK Timer CCR0 CCR1 MODULE OUTPUT SIGNAL NA TA0 TA1 DEVICE OUTPUT SIGNAL NA TA0.0 TA0.1 37-P1.3 H6-P1.3 DVCC TA0.2 VCC CCI2A 41-P1.7 M7-P1.7 TA0.2 CCI2B CCR2 TA2 DVSS GND DVCC VCC 38-P1.4 M6-P1.4 TA0.3 CCI3A DVSS CCI3B CCR3 TA3 DVSS GND DVCC VCC 39-P1.5 L6-P1.5 TA0.4 CCI4A DVSS CCI4B CCR4 TA4 DVSS GND DVCC VCC TA0.2 TA0.3 TA0.4 (1) Only on devices with peripheral module ADC12_A. OUTPUT PIN NUMBER PZ ZQW 35-P1.1 M5-P1.1 36-P1.2 J6-P1.2 40-P1.6 J7-P1.6 ADC12_A (internal)(1) ADC12SHSx = {1} 37-P1.3 41-P1.7 H6-P1.3 M7-P1.7 38-P1.4 M6-P1.4 39-P1.5 L6-P1.5 Copyright © 2010–2012, Texas Instruments Incorporated 27 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Timer TA1 Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. INPUT PIN NUMBER PZ ZQW 42-P3.0 L7-P3.0 42-P3.0 43-P3.1 L7-P3.0 H7-P3.1 44-P3.2 M8-P3.2 Table 17. Timer TA1 Signal Connections DEVICE INPUT SIGNAL TA1CLK ACLK SMCLK TA1CLK TA1.0 DVSS DVSS DVCC TA1.1 MODULE INPUT SIGNAL TACLK ACLK SMCLK TACLK CCI0A CCI0B GND VCC CCI1A MODULE BLOCK Timer CCR0 MODULE OUTPUT SIGNAL NA TA0 DEVICE OUTPUT SIGNAL NA TA1.0 CBOUT (internal) CCI1B CCR1 TA1 45-P3.3 L8-P3.3 DVSS DVCC TA1.2 GND VCC CCI2A ACLK (internal) CCI2B CCR2 TA2 DVSS GND DVCC VCC (1) Only on devices with peripheral module DAC12_A. TA1.1 TA1.2 OUTPUT PIN NUMBER PZ ZQW 43-P3.1 H7-P3.1 44-P3.2 M8-P3.2 DAC12_A (1) DAC12_0, DAC12_1 (internal) 45-P3.3 L8-P3.3 28 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Timer TA2 Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It supports multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. INPUT PIN NUMBER PZ ZQW 46-P3.4 J8-P3.4 46-P3.4 47-P3.5 J8-P3.4 M9-P3.5 48-P3.6 L9-P3.6 49-P3.7 M10-P3.7 Table 18. Timer TA2 Signal Connections DEVICE INPUT SIGNAL TA2CLK ACLK SMCLK TA2CLK TA2.0 DVSS DVSS DVCC TA2.1 CBOUT (internal) DVSS DVCC TA2.2 ACLK (internal) DVSS DVCC MODULE INPUT SIGNAL TACLK ACLK SMCLK TACLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC MODULE BLOCK Timer CCR0 CCR1 CCR2 MODULE OUTPUT SIGNAL NA TA0 TA1 TA2 DEVICE OUTPUT SIGNAL NA TA2.0 TA2.1 TA2.2 OUTPUT PIN NUMBER PZ ZQW 47-P3.5 M9-P3.5 48-P3.6 L9-P3.6 49-P3.7 M10-P3.7 Copyright © 2010–2012, Texas Instruments Incorporated 29 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Timer TB0 Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It supports multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. INPUT PIN NUMBER PZ ZQW 58-P8.0 P2MAPx (1) J11-P8.0 P2MAPx (1) 58-P8.0 P2MAPx (1) 50-P4.0 P2MAPx (1) J11-P8.0 P2MAPx (1) J9-P4.0 P2MAPx (1) 51-P4.1 P2MAPx (1) M11-P4.1 P2MAPx (1) 52-P4.2 P2MAPx (1) L10-P4.2 P2MAPx (1) Table 19. Timer TB0 Signal Connections DEVICE INPUT SIGNAL MODULE INPUT SIGNAL MODULE BLOCK MODULE OUTPUT SIGNAL DEVICE OUTPUT SIGNAL TB0CLK TB0CLK ACLK ACLK Timer NA NA SMCLK SMCLK TB0CLK TB0CLK TB0.0 CCI0A TB0.0 CCI0B CCR0 TB0 DVSS GND DVCC TB0.1 VCC CCI1A TB0.1 CCI1B CCR1 TB1 DVSS GND DVCC TB0.2 TB0.2 VCC CCI2A CCI2B CCR2 TB2 DVSS GND TB0.0 TB0.1 TB0.2 DVCC VCC 53-P4.3 M12-P4.3 TB0.3 CCI3A P2MAPx(1) P2MAPx(1) TB0.3 CCI3B CCR3 TB3 DVSS GND DVCC VCC 54-P4.4 L12-P4.4 TB0.4 CCI4A P2MAPx(1) P2MAPx(1) TB0.4 CCI4B CCR4 TB4 DVSS GND DVCC VCC 55-P4.5 L11-P4.5 TB0.5 CCI5A P2MAPx(1) P2MAPx(1) TB0.5 CCI5B CCR5 TB5 DVSS GND DVCC VCC 56-P4.6 K11-P4.6 TB0.6 CCI6A P2MAPx(1) P2MAPx(1) TB0.6 CCI6B CCR6 TB6 DVSS GND DVCC VCC (1) Timer functions selectable via the port mapping controller. (2) Only on devices with peripheral module ADC12_A. (3) Only on devices with peripheral module DAC12_A. TB0.3 TB0.4 TB0.5 TB0.6 OUTPUT PIN NUMBER PZ ZQW 50-P4.0 J9-P4.0 P2MAPx(1) P2MAPx(1) ADC12 (internal) (2) ADC12SHSx = {2} 51-P4.1 M11-P4.1 P2MAPx(1) P2MAPx(1) ADC12 (internal) (2) ADC12SHSx = {3} 52-P4.2 L10-P4.2 P2MAPx(1) P2MAPx(1) DAC12_A (3) DAC12_0, DAC12_1 (internal) 53-P4.3 P2MAPx (1) M12-P4.3 P2MAPx (1) 54-P4.4 P2MAPx (1) L12-P4.4 P2MAPx (1) 55-P4.5 P2MAPx (1) L11-P4.5 P2MAPx (1) 56-P4.6 P2MAPx (1) K11-P4.6 P2MAPx (1) 30 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Comparator_B The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. ADC12_A The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversionand-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. DAC12_A The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A may be used in 8-bit or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12_A modules are present, they may be grouped together for synchronous operation. CRC16 The CRC16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. The CRC16 module signature is based on the CRC-CCITT standard. REF Voltage Reference The reference module (REF) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. LCD_B The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal display (LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to control the level of the LCD voltage, and thus contrast, by software. The module also provides an automatic blinking capability for individual segments. USB Universal Serial Bus The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO, PHY, and PLL. The PLL is highly flexible and can support a wide range of input clock frequencies. USB RAM, when not used for USB communication, can be used by the system. Embedded Emulation Module (EEM) The Embedded Emulation Module (EEM) supports real-time in-system debugging. The L version of the EEM implemented on these devices has the following features: • Eight hardware triggers/breakpoints on memory access • Two hardware triggers/breakpoints on CPU register write access • Up to ten hardware triggers can be combined to form complex triggers/breakpoints • Two cycle counters • Sequencer • State storage • Clock control on module level Copyright © 2010–2012, Texas Instruments Incorporated 31 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Peripheral File Map www.ti.com.cn MODULE NAME Special Functions (see Table 21) PMM (see Table 22) Flash Control (see Table 23) CRC16 (see Table 24) RAM Control (see Table 25) Watchdog (see Table 26) UCS (see Table 27) SYS (see Table 28) Shared Reference (see Table 29) Port Mapping Control (see Table 30) Port Mapping Port P2 (see Table 30) Port P1/P2 (see Table 31) Port P3/P4 (see Table 32) Port P5/P6 (see Table 33) Port P7/P8 (see Table 34) Port P9 (see Table 35) Port PJ (see Table 36) Timer TA0 (see Table 37) Timer TA1 (see Table 38) Timer TB0 (see Table 39) Timer TA2 (see Table 40) Battery Backup (see Table 41) RTC_B (see Table 42) 32-bit Hardware Multiplier (see Table 43) DMA General Control (see Table 44) DMA Channel 0 (see Table 44) DMA Channel 1 (see Table 44) DMA Channel 2 (see Table 44) DMA Channel 3 (see Table 44) DMA Channel 4 (see Table 44) DMA Channel 5 (see Table 44) USCI_A0 (see Table 45) USCI_B0 (see Table 46) USCI_A1 (see Table 47) USCI_B1 (see Table 48) ADC12_A (see Table 49) DAC12_A (see Table 50) Comparator_B (see Table 51) USB configuration (see Table 52) USB control (see Table 53) LCD_B control (see Table 54) Table 20. Peripherals BASE ADDRESS 0100h 0120h 0140h 0150h 0158h 015Ch 0160h 0180h 01B0h 01C0h 01D0h 0200h 0220h 0240h 0260h 0280h 0320h 0340h 0380h 03C0h 0400h 0480h 04A0h 04C0h 0500h 0510h 0520h 0530h 0540h 0550h 0560h 05C0h 05E0h 0600h 0620h 0700h 0780h 08C0h 0900h 0920h 0A00h OFFSET ADDRESS RANGE(1) 000h - 01Fh 000h - 00Fh 000h - 00Fh 000h - 007h 000h - 001h 000h - 001h 000h - 01Fh 000h - 01Fh 000h - 001h 000h - 003h 000h - 007h 000h - 01Fh 000h - 01Fh 000h - 00Bh 000h - 00Bh 000h - 00Bh 000h - 01Fh 000h - 02Eh 000h - 02Eh 000h - 02Eh 000h - 02Eh 000h - 01Fh 000h - 01Fh 000h - 02Fh 000h - 00Fh 000h - 00Ah 000h - 00Ah 000h - 00Ah 000h - 00Ah 000h - 00Ah 000h - 00Ah 000h - 01Fh 000h - 01Fh 000h - 01Fh 000h - 01Fh 000h - 03Fh 000h - 01Fh 000h - 00Fh 000h - 014h 000h - 01Fh 000h - 05Fh (1) For a detailed description of the individual control register offset addresses, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). 32 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn SFR interrupt enable SFR interrupt flag SFR reset pin control ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 21. Special Function Registers (Base Address: 0100h) REGISTER DESCRIPTION REGISTER SFRIE1 00h SFRIFG1 02h SFRRPCR 04h OFFSET PMM Control 0 PMM control 1 SVS high side control SVS low side control PMM interrupt flags PMM interrupt enable Table 22. PMM Registers (Base Address: 0120h) REGISTER DESCRIPTION REGISTER PMMCTL0 PMMCTL1 SVSMHCTL SVSMLCTL PMMIFG PMMIE OFFSET 00h 02h 04h 06h 0Ch 0Eh Flash control 1 Flash control 3 Flash control 4 Table 23. Flash Control Registers (Base Address: 0140h) REGISTER DESCRIPTION REGISTER FCTL1 FCTL3 FCTL4 OFFSET 00h 04h 06h CRC data input CRC result Table 24. CRC16 Registers (Base Address: 0150h) REGISTER DESCRIPTION REGISTER CRC16DI CRC16INIRES OFFSET 00h 04h RAM control 0 Table 25. RAM Control Registers (Base Address: 0158h) REGISTER DESCRIPTION REGISTER RCCTL0 OFFSET 00h Watchdog timer control Table 26. Watchdog Registers (Base Address: 015Ch) REGISTER DESCRIPTION REGISTER WDTCTL OFFSET 00h UCS control 0 UCS control 1 UCS control 2 UCS control 3 UCS control 4 UCS control 5 UCS control 6 UCS control 7 UCS control 8 Table 27. UCS Registers (Base Address: 0160h) REGISTER DESCRIPTION REGISTER UCSCTL0 UCSCTL1 UCSCTL2 UCSCTL3 UCSCTL4 UCSCTL5 UCSCTL6 UCSCTL7 UCSCTL8 OFFSET 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h Copyright © 2010–2012, Texas Instruments Incorporated 33 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 28. SYS Registers (Base Address: 0180h) REGISTER DESCRIPTION System control Bootstrap loader configuration area JTAG mailbox control JTAG mailbox input 0 JTAG mailbox input 1 JTAG mailbox output 0 JTAG mailbox output 1 Bus Error vector generator User NMI vector generator System NMI vector generator Reset vector generator REGISTER SYSCTL SYSBSLC SYSJMBC SYSJMBI0 SYSJMBI1 SYSJMBO0 SYSJMBO1 SYSBERRIV SYSUNIV SYSSNIV SYSRSTIV www.ti.com.cn OFFSET 00h 02h 06h 08h 0Ah 0Ch 0Eh 18h 1Ah 1Ch 1Eh Table 29. Shared Reference Registers (Base Address: 01B0h) REGISTER DESCRIPTION Shared reference control REGISTER REFCTL 00h OFFSET Table 30. Port Mapping Registers (Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h) REGISTER DESCRIPTION Port mapping password register Port mapping control register Port P2.0 mapping register Port P2.1 mapping register Port P2.2 mapping register Port P2.3 mapping register Port P2.4 mapping register Port P2.5 mapping register Port P2.6 mapping register Port P2.7 mapping register REGISTER PMAPPWD 00h PMAPCTL 02h P2MAP0 00h P2MAP1 01h P2MAP2 02h P2MAP3 03h P2MAP4 04h P2MAP5 05h P2MAP6 06h P2MAP7 07h OFFSET Table 31. Port P1/P2 Registers (Base Address: 0200h) REGISTER DESCRIPTION Port P1 input Port P1 output Port P1 direction Port P1 pullup/pulldown enable Port P1 drive strength Port P1 selection Port P1 interrupt vector word Port P1 interrupt edge select Port P1 interrupt enable Port P1 interrupt flag Port P2 input Port P2 output Port P2 direction Port P2 pullup/pulldown enable Port P2 drive strength REGISTER P1IN P1OUT P1DIR P1REN P1DS P1SEL P1IV P1IES P1IE P1IFG P2IN P2OUT P2DIR P2REN P2DS OFFSET 00h 02h 04h 06h 08h 0Ah 0Eh 18h 1Ah 1Ch 01h 03h 05h 07h 09h 34 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 31. Port P1/P2 Registers (Base Address: 0200h) (continued) REGISTER DESCRIPTION Port P2 selection Port P2 interrupt vector word Port P2 interrupt edge select Port P2 interrupt enable Port P2 interrupt flag REGISTER P2SEL 0Bh P2IV 1Eh P2IES 19h P2IE 1Bh P2IFG 1Dh OFFSET Table 32. Port P3/P4 Registers (Base Address: 0220h) REGISTER DESCRIPTION Port P3 input Port P3 output Port P3 direction Port P3 pullup/pulldown enable Port P3 drive strength Port P3 selection Port P3 interrupt vector word Port P3 interrupt edge select Port P3 interrupt enable Port P3 interrupt flag Port P4 input Port P4 output Port P4 direction Port P4 pullup/pulldown enable Port P4 drive strength Port P4 selection Port P4 interrupt vector word Port P4 interrupt edge select Port P4 interrupt enable Port P4 interrupt flag REGISTER P3IN P3OUT P3DIR P3REN P3DS P3SEL P3IV P3IES P3IE P3IFG P4IN P4OUT P4DIR P4REN P4DS P4SEL P4IV P4IES P4IE P4IFG OFFSET 00h 02h 04h 06h 08h 0Ah 0Eh 18h 1Ah 1Ch 01h 03h 05h 07h 09h 0Bh 1Eh 19h 1Bh 1Dh Table 33. Port P5/P6 Registers (Base Address: 0240h) REGISTER DESCRIPTION Port P5 input Port P5 output Port P5 direction Port P5 pullup/pulldown enable Port P5 drive strength Port P5 selection Port P6 input Port P6 output Port P6 direction Port P6 pullup/pulldown enable Port P6 drive strength Port P6 selection REGISTER P5IN P5OUT P5DIR P5REN P5DS P5SEL P6IN P6OUT P6DIR P6REN P6DS P6SEL OFFSET 00h 02h 04h 06h 08h 0Ah 01h 03h 05h 07h 09h 0Bh Copyright © 2010–2012, Texas Instruments Incorporated 35 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Table 34. Port P7/P8 Registers (Base Address: 0260h) REGISTER DESCRIPTION Port P7 input Port P7 output Port P7 direction Port P7 pullup/pulldown enable Port P7 drive strength Port P7 selection Port P8 input Port P8 output Port P8 direction Port P8 pullup/pulldown enable Port P8 drive strength Port P8 selection REGISTER P7IN P7OUT P7DIR P7REN P7DS P7SEL P8IN P8OUT P8DIR P8REN P8DS P8SEL OFFSET 00h 02h 04h 06h 08h 0Ah 01h 03h 05h 07h 09h 0Bh Table 35. Port P9 Register (Base Address: 0280h) REGISTER DESCRIPTION Port P9 input Port P9 output Port P9 direction Port P9 pullup/pulldown enable Port P9 drive strength Port P9 selection REGISTER P9IN P9OUT P9DIR P9REN P9DS P9SEL OFFSET 00h 02h 04h 06h 08h 0Ah Table 36. Port J Registers (Base Address: 0320h) REGISTER DESCRIPTION Port PJ input Port PJ output Port PJ direction Port PJ pullup/pulldown enable Port PJ drive strength REGISTER PJIN PJOUT PJDIR PJREN PJDS OFFSET 00h 02h 04h 06h 08h Table 37. TA0 Registers (Base Address: 0340h) REGISTER DESCRIPTION TA0 control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Capture/compare control 3 Capture/compare control 4 TA0 counter register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Capture/compare register 3 Capture/compare register 4 TA0 expansion register 0 TA0 interrupt vector REGISTER TA0CTL TA0CCTL0 TA0CCTL1 TA0CCTL2 TA0CCTL3 TA0CCTL4 TA0R TA0CCR0 TA0CCR1 TA0CCR2 TA0CCR3 TA0CCR4 TA0EX0 TA0IV OFFSET 00h 02h 04h 06h 08h 0Ah 10h 12h 14h 16h 18h 1Ah 20h 2Eh 36 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 38. TA1 Registers (Base Address: 0380h) REGISTER DESCRIPTION TA1 control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 TA1 counter register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 TA1 expansion register 0 TA1 interrupt vector REGISTER TA1CTL TA1CCTL0 TA1CCTL1 TA1CCTL2 TA1R TA1CCR0 TA1CCR1 TA1CCR2 TA1EX0 TA1IV OFFSET 00h 02h 04h 06h 10h 12h 14h 16h 20h 2Eh Table 39. TB0 Registers (Base Address: 03C0h) REGISTER DESCRIPTION TB0 control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Capture/compare control 3 Capture/compare control 4 Capture/compare control 5 Capture/compare control 6 TB0 register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Capture/compare register 3 Capture/compare register 4 Capture/compare register 5 Capture/compare register 6 TB0 expansion register 0 TB0 interrupt vector REGISTER TB0CTL TB0CCTL0 TB0CCTL1 TB0CCTL2 TB0CCTL3 TB0CCTL4 TB0CCTL5 TB0CCTL6 TB0R TB0CCR0 TB0CCR1 TB0CCR2 TB0CCR3 TB0CCR4 TB0CCR5 TB0CCR6 TB0EX0 TB0IV OFFSET 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 2Eh Table 40. TA2 Registers (Base Address: 0400h) REGISTER DESCRIPTION TA2 control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 TA2 counter register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 TA2 expansion register 0 TA2 interrupt vector REGISTER TA2CTL TA2CCTL0 TA2CCTL1 TA2CCTL2 TA2R TA2CCR0 TA2CCR1 TA2CCR2 TA2EX0 TA2IV OFFSET 00h 02h 04h 06h 10h 12h 14h 16h 20h 2Eh Copyright © 2010–2012, Texas Instruments Incorporated 37 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 41. Battery Backup Registers (Base Address: 0480h) REGISTER DESCRIPTION Battery Backup Memory 0 Battery Backup Memory 1 Battery Backup Memory 2 Battery Backup Memory 3 Battery Backup Control Battery Charger Control REGISTER BAKMEM0 00h BAKMEM1 02h BAKMEM2 04h BAKMEM3 06h BAKCTL 1Ch BAKCHCTL 1Eh www.ti.com.cn OFFSET Table 42. Real-Time Clock Registers (Base Address: 04A0h) REGISTER DESCRIPTION RTC control register 0 RTC control register 1 RTC control register 2 RTC control register 3 RTC prescaler 0 control register RTC prescaler 1 control register RTC prescaler 0 RTC prescaler 1 RTC interrupt vector word RTC seconds RTC minutes RTC hours RTC day of week RTC days RTC month RTC year low RTC year high RTC alarm minutes RTC alarm hours RTC alarm day of week RTC alarm days Binary-to-BCD conversion register BCD-to-binary conversion register REGISTER RTCCTL0 00h RTCCTL1 01h RTCCTL2 02h RTCCTL3 03h RTCPS0CTL 08h RTCPS1CTL 0Ah RTCPS0 0Ch RTCPS1 0Dh RTCIV 0Eh RTCSEC 10h RTCMIN 11h RTCHOUR 12h RTCDOW 13h RTCDAY 14h RTCMON 15h RTCYEARL 16h RTCYEARH 17h RTCAMIN 18h RTCAHOUR 19h RTCADOW 1Ah RTCADAY 1Bh BIN2BCD 1Ch BCD2BIN 1Eh OFFSET Table 43. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) REGISTER DESCRIPTION 16-bit operand 1 – multiply 16-bit operand 1 – signed multiply 16-bit operand 1 – multiply accumulate 16-bit operand 1 – signed multiply accumulate 16-bit operand 2 16 × 16 result low word 16 × 16 result high word 16 × 16 sum extension register 32-bit operand 1 – multiply low word 32-bit operand 1 – multiply high word 32-bit operand 1 – signed multiply low word 32-bit operand 1 – signed multiply high word REGISTER MPY 00h MPYS 02h MAC 04h MACS 06h OP2 08h RESLO 0Ah RESHI 0Ch SUMEXT 0Eh MPY32L 10h MPY32H 12h MPYS32L 14h MPYS32H 16h OFFSET 38 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 43. 32-bit Hardware Multiplier Registers (Base Address: 04C0h) (continued) REGISTER DESCRIPTION 32-bit operand 1 – multiply accumulate low word 32-bit operand 1 – multiply accumulate high word 32-bit operand 1 – signed multiply accumulate low word 32-bit operand 1 – signed multiply accumulate high word 32-bit operand 2 – low word 32-bit operand 2 – high word 32 × 32 result 0 – least significant word 32 × 32 result 1 32 × 32 result 2 32 × 32 result 3 – most significant word MPY32 control register 0 REGISTER MAC32L MAC32H MACS32L MACS32H OP2L OP2H RES0 RES1 RES2 RES3 MPY32CTL0 OFFSET 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch Table 44. DMA Registers (Base Address DMA General Control: 0500h, DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA Channel 4: 0550h, DMA Channel 5: 0560h) REGISTER DESCRIPTION DMA General Control: DMA module control 0 DMA General Control: DMA module control 1 DMA General Control: DMA module control 2 DMA General Control: DMA module control 3 DMA General Control: DMA module control 4 DMA General Control: DMA interrupt vector DMA Channel 0 control DMA Channel 0 source address low DMA Channel 0 source address high DMA Channel 0 destination address low DMA Channel 0 destination address high DMA Channel 0 transfer size DMA Channel 1 control DMA Channel 1 source address low DMA Channel 1 source address high DMA Channel 1 destination address low DMA Channel 1 destination address high DMA Channel 1 transfer size DMA Channel 2 control DMA Channel 2 source address low DMA Channel 2 source address high DMA Channel 2 destination address low DMA Channel 2 destination address high DMA Channel 2 transfer size DMA Channel 3 control DMA Channel 3 source address low DMA Channel 3 source address high DMA Channel 3 destination address low DMA Channel 3 destination address high DMA Channel 3 transfer size DMA Channel 4 control DMA Channel 4 source address low REGISTER DMACTL0 DMACTL1 DMACTL2 DMACTL3 DMACTL4 DMAIV DMA0CTL DMA0SAL DMA0SAH DMA0DAL DMA0DAH DMA0SZ DMA1CTL DMA1SAL DMA1SAH DMA1DAL DMA1DAH DMA1SZ DMA2CTL DMA2SAL DMA2SAH DMA2DAL DMA2DAH DMA2SZ DMA3CTL DMA3SAL DMA3SAH DMA3DAL DMA3DAH DMA3SZ DMA4CTL DMA4SAL OFFSET 00h 02h 04h 06h 08h 0Ah 00h 02h 04h 06h 08h 0Ah 00h 02h 04h 06h 08h 0Ah 00h 02h 04h 06h 08h 0Ah 00h 02h 04h 06h 08h 0Ah 00h 02h Copyright © 2010–2012, Texas Instruments Incorporated 39 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Table 44. DMA Registers (Base Address DMA General Control: 0500h, DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA Channel 4: 0550h, DMA Channel 5: 0560h) (continued) REGISTER DESCRIPTION DMA Channel 4 source address high DMA Channel 4 destination address low DMA Channel 4 destination address high DMA Channel 4 transfer size DMA Channel 5 control DMA Channel 5 source address low DMA Channel 5 source address high DMA Channel 5 destination address low DMA Channel 5 destination address high DMA Channel 5 transfer size REGISTER DMA4SAH DMA4DAL DMA4DAH DMA4SZ DMA5CTL DMA5SAL DMA5SAH DMA5DAL DMA5DAH DMA5SZ OFFSET 04h 06h 08h 0Ah 00h 02h 04h 06h 08h 0Ah Table 45. USCI_A0 Registers (Base Address: 05C0h) REGISTER DESCRIPTION USCI control 0 USCI control 1 USCI baud rate 0 USCI baud rate 1 USCI modulation control USCI status USCI receive buffer USCI transmit buffer USCI LIN control USCI IrDA transmit control USCI IrDA receive control USCI interrupt enable USCI interrupt flags USCI interrupt vector word REGISTER UCA0CTL0 UCA0CTL1 UCA0BR0 UCA0BR1 UCA0MCTL UCA0STAT UCA0RXBUF UCA0TXBUF UCA0ABCTL UCA0IRTCTL UCA0IRRCTL UCA0IE UCA0IFG UCA0IV OFFSET 00h 01h 06h 07h 08h 0Ah 0Ch 0Eh 10h 12h 13h 1Ch 1Dh 1Eh Table 46. USCI_B0 Registers (Base Address: 05E0h) REGISTER DESCRIPTION USCI synchronous control 0 USCI synchronous control 1 USCI synchronous bit rate 0 USCI synchronous bit rate 1 USCI synchronous status USCI synchronous receive buffer USCI synchronous transmit buffer USCI I2C own address USCI I2C slave address USCI interrupt enable USCI interrupt flags USCI interrupt vector word REGISTER UCB0CTL0 UCB0CTL1 UCB0BR0 UCB0BR1 UCB0STAT UCB0RXBUF UCB0TXBUF UCB0I2COA UCB0I2CSA UCB0IE UCB0IFG UCB0IV OFFSET 00h 01h 06h 07h 0Ah 0Ch 0Eh 10h 12h 1Ch 1Dh 1Eh 40 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 47. USCI_A1 Registers (Base Address: 0600h) REGISTER DESCRIPTION USCI control 0 USCI control 1 USCI baud rate 0 USCI baud rate 1 USCI modulation control USCI status USCI receive buffer USCI transmit buffer USCI LIN control USCI IrDA transmit control USCI IrDA receive control USCI interrupt enable USCI interrupt flags USCI interrupt vector word REGISTER UCA1CTL0 UCA1CTL1 UCA1BR0 UCA1BR1 UCA1MCTL UCA1STAT UCA1RXBUF UCA1TXBUF UCA1ABCTL UCA1IRTCTL UCA1IRRCTL UCA1IE UCA1IFG UCA1IV OFFSET 00h 01h 06h 07h 08h 0Ah 0Ch 0Eh 10h 12h 13h 1Ch 1Dh 1Eh Table 48. USCI_B1 Registers (Base Address: 0620h) REGISTER DESCRIPTION USCI synchronous control 0 USCI synchronous control 1 USCI synchronous bit rate 0 USCI synchronous bit rate 1 USCI synchronous status USCI synchronous receive buffer USCI synchronous transmit buffer USCI I2C own address USCI I2C slave address USCI interrupt enable USCI interrupt flags USCI interrupt vector word REGISTER UCB1CTL0 UCB1CTL1 UCB1BR0 UCB1BR1 UCB1STAT UCB1RXBUF UCB1TXBUF UCB1I2COA UCB1I2CSA UCB1IE UCB1IFG UCB1IV OFFSET 00h 01h 06h 07h 0Ah 0Ch 0Eh 10h 12h 1Ch 1Dh 1Eh Table 49. ADC12_A Registers (Base Address: 0700h) REGISTER DESCRIPTION Control register 0 Control register 1 Control register 2 Interrupt-flag register Interrupt-enable register Interrupt-vector-word register ADC memory-control register 0 ADC memory-control register 1 ADC memory-control register 2 ADC memory-control register 3 ADC memory-control register 4 ADC memory-control register 5 ADC memory-control register 6 ADC memory-control register 7 ADC memory-control register 8 REGISTER ADC12CTL0 ADC12CTL1 ADC12CTL2 ADC12IFG ADC12IE ADC12IV ADC12MCTL0 ADC12MCTL1 ADC12MCTL2 ADC12MCTL3 ADC12MCTL4 ADC12MCTL5 ADC12MCTL6 ADC12MCTL7 ADC12MCTL8 OFFSET 00h 02h 04h 0Ah 0Ch 0Eh 10h 11h 12h 13h 14h 15h 16h 17h 18h Copyright © 2010–2012, Texas Instruments Incorporated 41 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 49. ADC12_A Registers (Base Address: 0700h) (continued) REGISTER DESCRIPTION ADC memory-control register 9 ADC memory-control register 10 ADC memory-control register 11 ADC memory-control register 12 ADC memory-control register 13 ADC memory-control register 14 ADC memory-control register 15 Conversion memory 0 Conversion memory 1 Conversion memory 2 Conversion memory 3 Conversion memory 4 Conversion memory 5 Conversion memory 6 Conversion memory 7 Conversion memory 8 Conversion memory 9 Conversion memory 10 Conversion memory 11 Conversion memory 12 Conversion memory 13 Conversion memory 14 Conversion memory 15 REGISTER ADC12MCTL9 19h ADC12MCTL10 1Ah ADC12MCTL11 1Bh ADC12MCTL12 1Ch ADC12MCTL13 1Dh ADC12MCTL14 1Eh ADC12MCTL15 1Fh ADC12MEM0 20h ADC12MEM1 22h ADC12MEM2 24h ADC12MEM3 26h ADC12MEM4 28h ADC12MEM5 2Ah ADC12MEM6 2Ch ADC12MEM7 2Eh ADC12MEM8 30h ADC12MEM9 32h ADC12MEM10 34h ADC12MEM11 36h ADC12MEM12 38h ADC12MEM13 3Ah ADC12MEM14 3Ch ADC12MEM15 3Eh www.ti.com.cn OFFSET Table 50. DAC12_A Registers (Base Address: 0780h) REGISTER DESCRIPTION DAC12_A channel 0 control register 0 DAC12_A channel 0 control register 1 DAC12_A channel 0 data register DAC12_A channel 0 calibration control register DAC12_A channel 0 calibration data register DAC12_A channel 1 control register 0 DAC12_A channel 1 control register 1 DAC12_A channel 1 data register DAC12_A channel 1 calibration control register DAC12_A channel 1 calibration data register DAC12_A interrupt vector word REGISTER DAC12_0CTL0 DAC12_0CTL1 DAC12_0DAT DAC12_0CALCTL DAC12_0CALDAT DAC12_1CTL0 DAC12_1CTL1 DAC12_1DAT DAC12_1CALCTL DAC12_1CALDAT DAC12IV OFFSET 00h 02h 04h 06h 08h 10h 12h 14h 16h 18h 1Eh Table 51. Comparator_B Registers (Base Address: 08C0h) REGISTER DESCRIPTION Comp_B control register 0 Comp_B control register 1 Comp_B control register 2 Comp_B control register 3 Comp_B interrupt register Comp_B interrupt vector word REGISTER CBCTL0 CBCTL1 CBCTL2 CBCTL3 CBINT CBIV OFFSET 00h 02h 04h 06h 0Ch 0Eh 42 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 52. USB Configuration Registers (Base Address: 0900h) REGISTER DESCRIPTION USB key/ID USB module configuration USB PHY control USB power control USB power voltage setting USB PLL control USB PLL divider USB PLL interrupts REGISTER USBKEYID 00h USBCNF 02h USBPHYCTL 04h USBPWRCTL 08h USBPWRVSR 0Ah USBPLLCTL 10h USBPLLDIV 12h USBPLLIR 14h OFFSET Table 53. USB Control Registers (Base Address: 0920h) REGISTER DESCRIPTION Input endpoint#0 configuration Input endpoint #0 byte count Output endpoint#0 configuration Output endpoint #0 byte count Input endpoint interrupt enables Output endpoint interrupt enables Input endpoint interrupt flags Output endpoint interrupt flags USB interrupt vector USB maintenance Time stamp USB frame number USB control USB interrupt enables USB interrupt flags Function address REGISTER IEPCNF_0 IEPCNT_0 OEPCNF_0 OEPCNT_0 IEPIE OEPIE IEPIFG OEPIFG USBIV MAINT TSREG USBFN USBCTL USBIE USBIFG FUNADR OFFSET 00h 01h 02h 03h 0Eh 0Fh 10h 11h 12h 16h 18h 1Ah 1Ch 1Dh 1Eh 1Fh Table 54. LCD_B Registers (Base Address: 0A00h) REGISTER DESCRIPTION LCD_B control register 0 LCD_B control register 1 LCD_B blinking control register LCD_B memory control register LCD_B voltage control register LCD_B port control register 0 LCD_B port control register 1 LCD_B port control register 2 LCD_B charge pump control register LCD_B interrupt vector word LCD_B memory 1 LCD_B memory 2 ⋮ LCD_B memory 22 LCD_B blinking memory 1 LCD_B blinking memory 2 ⋮ REGISTER LCDBCTL0 LCDBCTL1 LCDBBLKCTL LCDBMEMCTL LCDBVCTL LCDBPCTL0 LCDBPCTL1 LCDBPCTL2 LCDBCTL0 LCDBIV LCDM1 LCDM2 ⋮ LCDM22 LCDBM1 LCDBM2 ⋮ 000h 002h 004h 006h 008h 00Ah 00Ch 00Eh 012h 01Eh 020h 021h ⋮ 035h 040h 041h ⋮ OFFSET Copyright © 2010–2012, Texas Instruments Incorporated 43 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Table 54. LCD_B Registers (Base Address: 0A00h) (continued) REGISTER DESCRIPTION LCD_B blinking memory 22 REGISTER LCDBM22 055h OFFSET 44 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Absolute Maximum Ratings(1) over operating free-air temperature range (unless otherwise noted) Voltage applied at VCC to VSS Voltage applied to any pin (excluding VCORE, VBUS, V18)(2) Diode current at any device pin Storage temperature range, Tstg(3) Maximum junction temperature, TJ –0.3 V to 4.1 V –0.3 V to VCC + 0.3 V ±2 mA –55°C to 150°C 95°C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages referenced to VSS. VCORE is for internal device use only. No external dc loading or voltage should be applied. (3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Thermal Packaging Characteristics PARAMETER θJA Junction-to-ambient thermal resistance, still air(1) θJC(TOP) Junction-to-case (top) thermal resistance(2) θJB Junction-to-board thermal resistance(3) QFP (PZ) BGA (ZQW) QFP (PZ) BGA (ZQW) QFP (PZ) BGA (ZQW) VALUE 122 108 83 72 98 76 UNIT °C/W °C/W °C/W (1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. Recommended Operating Conditions VCC VCC,USB VSS VBAT,RTC VBAT,MEM TA TJ CBAK Supply voltage during program execution and flash programming (AVCC1 = DVCC1 = DVCC2 = DVCC3 = DVCC = VCC) (1) (2) PMMCOREVx = 0 PMMCOREVx = 0, 1 PMMCOREVx = 0, 1, 2 PMMCOREVx = 0, 1, 2, 3 PMMCOREVx = 0 Supply voltage during USB operation, USB PLL disabled (USB_EN = 1, UPLLEN = 0) PMMCOREVx = 0, 1 PMMCOREVx = 0, 1, 2 PMMCOREVx = 0, 1, 2, 3 Supply voltage during USB operation, USB PLL enabled(3) PMMCOREVx = 2 (USB_EN = 1, UPLLEN = 1) PMMCOREVx = 2, 3 Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = VSS) Backup-supply voltage with RTC operational Backup-supply voltage with backup memory retained. Operating free-air temperature TA = 0°C to 85°C TA = –40°C to 85°C TA = –40°C to 85°C I version Operating junction temperature I version Capacitance at pin VBAK MIN NOM MAX UNIT 1.8 3.6 2.0 3.6 V 2.2 3.6 2.4 3.6 1.8 3.6 2.0 3.6 2.2 3.6 V 2.4 3.6 2.2 3.6 2.4 3.6 0 V 1.55 3.6 V 1.70 3.6 1.20 3.6 V –40 85 °C –40 85 °C 1 4.7 10 nF (1) It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation. (2) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold parameters for the exact values and further details. (3) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation. Copyright © 2010–2012, Texas Instruments Incorporated 45 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Recommended Operating Conditions (continued) CVCORE CDVCC/ CVCORE Capacitor at VCORE Capacitor ratio of DVCC to VCORE fSYSTEM Processor frequency (maximum MCLK frequency)(4)(5) (see Figure 1) fSYSTEM_USB Minimum processor frequency for USB operation USB_wait Wait state cycles during USB operation PMMCOREVx = 0, 1.8 V ≤ VCC ≤ 3.6 V (default condition) PMMCOREVx = 1, 2 V ≤ VCC ≤ 3.6 V PMMCOREVx = 2, 2.2 V ≤ VCC ≤ 3.6 V PMMCOREVx = 3, 2.4 V ≤ VCC ≤ 3.6 V MIN NOM MAX UNIT 470 nF 10 0 8.0 0 12.0 MHz 0 16.0 0 20.0 1.5 16 MHz cycles (4) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency. (5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet. System Frequency - MHz 25 20 3 16 2 2, 3 12 1 1, 2 1, 2, 3 8 0 0, 1 0, 1, 2 0, 1, 2, 3 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. Figure 1. Frequency vs Supply Voltage 46 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn Electrical Characteristics ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Active Mode Supply Current Into VCC Excluding External Current over recommended operating free-air temperature (unless otherwise noted)(1)(2)(3) PARAMETER EXECUTION MEMORY FREQUENCY (fDCO = fMCLK = fSMCLK) VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 20 MHz TYP MAX TYP MAX TYP MAX TYP MAX 0 0.32 0.36 2.1 2.4 1 0.36 2.4 3.6 4.0 IAM, Flash Flash 3V 2 0.37 2.5 3.8 3 0.39 2.7 4.0 6.6 0 0.18 0.21 1.0 1.2 1 0.20 1.2 1.7 1.9 IAM, RAM RAM 3V 2 0.22 1.3 2.0 3 0.23 1.4 2.1 3.6 UNIT mA mA (1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF. (3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0). fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0. Copyright © 2010–2012, Texas Instruments Incorporated 47 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2) PARAMETER -40°C 25°C 60°C 85°C VCC PMMCOREVx TYP MAX TYP MAX TYP MAX TYP UNIT MAX ILPM0,1MHz Low-power mode 0 (3)(4) 2.2 V 3V 0 3 71 78 75 87 81 83 98 89 85 99 µA 94 108 ILPM2 Low-power mode 2(5)(4) 2.2 V 3V 0 3 6.3 6.6 6.7 9.9 9.0 7.0 11 10 11 16 µA 12 18 0 1.6 1.8 2.4 4.7 6.5 10.5 2.2 V 1 1.6 1.9 4.8 6.6 2 1.7 ILPM3,XT1LF Low-power mode 3, crystal mode(6)(4) 0 1.9 1 1.9 3V 2 2.0 2.0 4.9 2.1 2.7 5.0 2.1 5.1 2.2 5.2 6.7 6.8 10.8 µA 7.0 7.1 3 2.0 2.2 2.9 5.4 7.3 12.6 0 0.9 ILPM3, Low-power mode 3, VLO mode, Watchdog 3V 1 0.9 VLO,WDT enabled (7) (4) 2 1.0 3 1.0 1.2 1.9 4.0 1.2 4.1 1.3 4.2 1.3 2.2 4.3 5.9 10.3 6.0 µA 6.1 6.3 11.3 0 0.9 1.1 1.8 3.9 5.8 10 ILPM4 Low-power mode 4(8)(4) 3 V 1 2 0.9 1.0 1.1 1.2 4.0 4.1 5.9 µA 6.1 3 1.0 1.2 2.1 4.2 6.2 11 Low-power mode 3.5 ILPM3.5, RTC,VCC (LPM3.5) current with active RTC into primary 3V supply pin DVCC (9) Low-power mode 3.5 ILPM3.5, RTC,VBAT (LPM3.5) current with active RTC into backup 3V supply pin VBAT(10) 0.5 0.8 1.4 µA 0.6 0.8 1.4 µA ILPM3.5, Total low-power mode 3.5 (LPM3.5) current 3V RTC,TOT with active RTC(11) 1.0 1.1 1.3 1.6 2.8 µA (1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF. (3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz USB disabled (VUSBEN = 0, SLDOEN = 0). (4) Current for brownout included. Low side supervisor and monitors disabled (SVSL, SVML). High side supervisor and monitor disabled (SVSH, SVMH). RAM retention enabled. (5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1 MHz operation, DCO bias generator enabled. USB disabled (VUSBEN = 0, SLDOEN = 0). (6) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz USB disabled (VUSBEN = 0, SLDOEN = 0). (7) Current for watchdog timer clocked by VLO included. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fMCLK = fSMCLK = fDCO = 0 MHz USB disabled (VUSBEN = 0, SLDOEN = 0). (8) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz USB disabled (VUSBEN = 0, SLDOEN = 0). (9) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active (10) VVBAT = VCC - 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK (11) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK 48 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Low-Power Mode Supply Currents (Into VCC) Excluding External Current (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2) PARAMETER -40°C 25°C 60°C 85°C VCC PMMCOREVx TYP MAX TYP MAX TYP MAX TYP UNIT MAX ILPM4.5 Low-power mode 4.5 (LPM4.5) (12) 3V 0.2 0.3 0.6 0.7 0.9 1.4 µA (12) Internal regulator disabled. No data retention. CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2) PARAMETER Temperature (TA) VCC PMMCOREVx -40°C 25°C 60°C 85°C TYP MAX TYP MAX TYP MAX TYP MAX 0 2.3 ILPM3, LCD, ext. bias Low-power mode 3 (LPM3) current, LCD 4mux mode, external 3V biasing(3) (4) 1 2 2.3 2.4 3 2.4 2.7 3.1 5.4 2.7 5.6 2.8 5.8 2.8 3.5 5.9 7.4 11.5 7.5 7.7 7.9 13.2 Low-power mode 3 0 2.7 ILPM3, (LPM3) current, LCD 4- 1 2.7 LCD, mux mode, internal 3V int. bias biasing, charge pump 2 2.8 disabled (3) (5) 3 2.8 3.2 3.8 5.9 3.2 6.1 3.3 6.2 3.3 4.9 6.4 7.9 12.2 8.1 8.3 8.4 13.7 0 3.8 2.2 V 1 3.9 ILPM3 LCD,CP Low-power mode 3 (LPM3) current, LCD 4- mux mode, internal biasing, charge pump enabled (3) (6) 3V 2 0 1 4.0 4.0 4.1 2 4.2 3 4.2 UNIT µA µA µA µA (1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance are chosen to closely match the required 9 pF. (3) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0). CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz Current for brownout included. Low side supervisor and monitors disabled (SVSL, SVML). High side supervisor and monitor disabled (SVSH, SVMH). RAM retention enabled. (4) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz) Current through external resistors not included (voltage levels are supplied by test equipment). Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load. (5) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz) Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load. (6) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump enabled), VLCDx = 1000 (VLCD = 3 V, typ.), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz/32/4 = 256 Hz) Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load. Schmitt-Trigger Inputs – General Purpose I/O(1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT+ Positive-going input threshold voltage TEST CONDITIONS VCC 1.8 V 3V MIN TYP 0.80 1.50 MAX 1.40 2.10 UNIT V (1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN). Copyright © 2010–2012, Texas Instruments Incorporated 49 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Schmitt-Trigger Inputs – General Purpose I/O(1) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT– Negative-going input threshold voltage TEST CONDITIONS VCC 1.8 V 3V MIN TYP 0.45 0.75 Vhys Input voltage hysteresis (VIT+ – VIT–) 1.8 V 0.3 3V 0.4 RPull CI Pullup or pulldown resistor Input capacitance For pullup: VIN = VSS For pulldown: VIN = VCC VIN = VSS or VCC 20 35 5 MAX 1.00 1.65 0.8 1.0 UNIT V V 50 kΩ pF Inputs – Ports P1, P2, P3, and P4(1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) External interrupt timing(2) TEST CONDITIONS Port P1, P2, P3, P4: P1.x to P4.x, External trigger pulse duration to set interrupt flag VCC MIN 2.2 V, 3 V 20 MAX UNIT ns (1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions. (2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int). Leakage Current – General Purpose I/O over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Ilkg(Px.x) PARAMETER High-impedance leakage current TEST CONDITIONS (1) (2) VCC 1.8 V, 3 V MIN MAX UNIT ±50 nA (1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled. Outputs – General Purpose I/O (Full Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS I(OHmax) = –3 mA (1) I(OHmax) = –10 mA (2) I(OHmax) = –5 mA(1) I(OHmax) = –15 mA(2) I(OLmax) = 3 mA (1) I(OLmax) = 10 mA(2) I(OLmax) = 5 mA (1) I(OLmax) = 15 mA(2) VCC 1.8 V 3V 1.8 V 3V MIN VCC – 0.25 VCC – 0.60 VCC – 0.25 VCC – 0.60 VSS VSS VSS VSS MAX VCC VCC VCC VCC VSS + 0.25 VSS + 0.60 VSS + 0.25 VSS + 0.60 UNIT V V (1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified. (2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified. 50 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Outputs – General Purpose I/O (Reduced Drive Strength) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) PARAMETER VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS I(OHmax) = –1 mA (2) I(OHmax) = –3 mA (3) I(OHmax) = –2 mA(2) I(OHmax) = –6 mA(3) I(OLmax) = 1 mA (2) I(OLmax) = 3 mA (3) I(OLmax) = 2 mA (2) I(OLmax) = 6 mA (3) VCC 1.8 V 3V 1.8 V 3V MIN VCC – 0.25 VCC – 0.60 VCC – 0.25 VCC – 0.60 VSS VSS VSS VSS MAX VCC VCC VCC VCC VSS + 0.25 VSS + 0.60 VSS + 0.25 VSS + 0.60 UNIT V V (1) Selecting reduced drive strength may reduce EMI. (2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. (3) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified. Output Frequency – Ports P1, P2, and P3 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN fPx.y Port output frequency (with load) P3.4/TA2CLK/SMCLK/S27 CL = 20 pF, RL = 1 kΩ(1) or 3.2 kΩ (2)(3) VCC = 1.8 V PMMCOREVx = 0 VCC = 3 V PMMCOREVx = 3 fPort_CLK Clock output frequency P1.0/TA0CLK/ACLK/S39 P3.4/TA2CLK/SMCLK/S27 P2.0/P2MAP0 (P2MAP0 = PM_MCLK ) CL = 20 pF(3) VCC = 1.8 V PMMCOREVx = 0 VCC = 3 V PMMCOREVx = 3 MAX UNIT 8 MHz 20 8 MHz 20 (1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider. (2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider. (3) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Copyright © 2010–2012, Texas Instruments Incorporated 51 MSP430F663x OLI – Typical Low-Level Output Current – mA OLI – Typical Low-Level Output Current – mA ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 25.0 VCC = 3.0 V P3.2 20.0 TA = 25°C TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 8.0 VCC = 1.8 V 7.0 P3.2 TA = 25°C 6.0 15.0 TA = 85°C 5.0 4.0 TA = 85°C 10.0 3.0 2.0 5.0 1.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL – Low-Level Output Voltage – V Figure 2. 0.0 0.0 0.5 1.0 1.5 2.0 VOL – Low-Level Output Voltage – V Figure 3. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 VCC = 3.0 V P3.2 −5.0 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 −1.0 VCC = 1.8 V P3.2 −2.0 OH I – Typical High-Level Output Current – mA OH I – Typical High-Level Output Current – mA −10.0 −15.0 TA = 85°C −20.0 TA = 25°C −3.0 −4.0 −5.0 TA = 85°C −6.0 −7.0 TA = 25°C −25.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH – High-Level Output Voltage – V Figure 4. −8.0 0.0 0.5 1.0 1.5 2.0 VOH – High-Level Output Voltage – V Figure 5. 52 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) OLI – Typical Low-Level Output Current – mA TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 60.0 55.0 50.0 VCC = 3.0 V P3.2 TA = 25°C 45.0 TA = 85°C 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL – Low-Level Output Voltage – V Figure 6. OLI – Typical Low-Level Output Current – mA TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 24 VCC = 1.8 V P3.2 20 TA = 25°C 16 TA = 85°C 12 8 4 0 0.0 0.5 1.0 1.5 2.0 VOL – Low-Level Output Voltage – V Figure 7. OH I – Typical High-Level Output Current – mA 0.0 −5.0 −10.0 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE VCC = 3.0 V P3.2 −15.0 −20.0 −25.0 −30.0 −35.0 −40.0 −45.0 −50.0 TA = 85°C −55.0 −60.0 TA = 25°C 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH – High-Level Output Voltage – V Figure 8. OH I – Typical High-Level Output Current – mA TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 VCC = 1.8 V P3.2 −4 −8 −12 TA = 85°C −16 TA = 25°C −20 0.0 0.5 1.0 1.5 2.0 VOH – High-Level Output Voltage – V Figure 9. Copyright © 2010–2012, Texas Instruments Incorporated 53 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Crystal Oscillator, XT1, Low-Frequency Mode(1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ΔIDVCC,LF fXT1,LF0 PARAMETER Differential XT1 oscillator crystal current consumption from lowest drive setting, LF mode XT1 oscillator crystal frequency, LF mode TEST CONDITIONS fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, TA = 25°C fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 2, TA = 25°C fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C XTS = 0, XT1BYPASS = 0 VCC MIN TYP MAX UNIT 0.075 3V 0.170 µA 0.290 32768 Hz fXT1,LF,SW XT1 oscillator logic-level squarewave input frequency, LF mode XTS = 0, XT1BYPASS = 1(2) (3) 10 32.768 50 kHz OALF Oscillation allowance for LF crystals(4) XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, fXT1,LF = 32768 Hz, CL,eff = 6 pF XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 1, fXT1,LF = 32768 Hz, CL,eff = 12 pF XTS = 0, XCAPx = 0(6) 210 kΩ 300 2 CL,eff Integrated effective load capacitance, LF mode(5) XTS = 0, XCAPx = 1 XTS = 0, XCAPx = 2 5.5 pF 8.5 XTS = 0, XCAPx = 3 12.0 fFault,LF Duty cycle, LF mode Oscillator fault frequency, LF mode(7) XTS = 0, Measured at ACLK, fXT1,LF = 32768 Hz XTS = 0(8) 30 70 % 10 10000 Hz fOSC = 32768 Hz, XTS = 0, XT1BYPASS = 0, XT1DRIVEx = 0, TA = 25°C, tSTART,LF Startup time, LF mode CL,eff = 6 pF fOSC = 32768 Hz, XTS = 0, 3V XT1BYPASS = 0, XT1DRIVEx = 3, TA = 25°C, CL,eff = 12 pF 1000 ms 500 (1) To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (2) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger Inputs section of this datasheet. (3) Maximum frequency of operation of the entire device cannot be exceeded. (4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: (a) For XT1DRIVEx = 0, CL,eff ≤ 6 pF. (b) For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF. (c) For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF. (d) For XT1DRIVEx = 3, CL,ef f ≥ 6 pF. (5) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. (6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals. 54 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Crystal Oscillator, XT2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2) IDVCC,XT2 fXT2,HF0 PARAMETER XT2 oscillator crystal current consumption XT2 oscillator crystal frequency, mode 0 TEST CONDITIONS fOSC = 4 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C fOSC = 12 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 1, TA = 25°C fOSC = 20 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 2, TA = 25°C fOSC = 32 MHz, XT2OFF = 0, XT2BYPASS = 0, XT2DRIVEx = 3, TA = 25°C XT2DRIVEx = 0, XT2BYPASS = 0(3) VCC MIN TYP MAX UNIT 200 260 3V µA 325 450 4 8 MHz fXT2,HF1 XT2 oscillator crystal frequency, mode 1 XT2DRIVEx = 1, XT2BYPASS = 0(3) 8 16 MHz fXT2,HF2 XT2 oscillator crystal frequency, mode 2 XT2DRIVEx = 2, XT2BYPASS = 0(3) 16 24 MHz fXT2,HF3 XT2 oscillator crystal frequency, mode 3 XT2DRIVEx = 3, XT2BYPASS = 0(3) 24 32 MHz fXT2,HF,SW XT2 oscillator logic-level squarewave input frequency XT2BYPASS = 1(4) (3) 0.7 32 MHz XT2DRIVEx = 0, XT2BYPASS = 0, fXT2,HF0 = 6 MHz, CL,eff = 15 pF OAHF Oscillation allowance for HF crystals(5) XT2DRIVEx = 1, XT2BYPASS = 0, fXT2,HF1 = 12 MHz, CL,eff = 15 pF XT2DRIVEx = 2, XT2BYPASS = 0, fXT2,HF2 = 20 MHz, CL,eff = 15 pF XT2DRIVEx = 3, XT2BYPASS = 0, fXT2,HF3 = 32 MHz, CL,eff = 15 pF tSTART,HF Startup time fOSC = 6 MHz XT2BYPASS = 0, XT2DRIVEx = 0, TA = 25°C, CL,eff = 15 pF 3V fOSC = 20 MHz XT2BYPASS = 0, XT2DRIVEx = 3, TA = 25°C, CL,eff = 15 pF CL,eff Integrated effective load capacitance, HF mode(6) (1) 450 320 Ω 200 200 0.5 ms 0.3 1 pF fFault,HF Duty cycle Oscillator fault frequency(7) Measured at ACLK, fXT2,HF2 = 20 MHz XT2BYPASS = 1(8) 40 50 60 % 30 300 kHz (1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. (2) To improve EMI on the XT2 oscillator the following guidelines should be observed. (a) Keep the traces between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT. (d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (3) Maximum frequency of operation of the entire device cannot be exceeded. (4) When XT2BYPASS is set, the XT2 circuit is automatically powered down. (5) Oscillation allowance is based on a safety factor of 5 for recommended crystals. (6) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. (7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. (8) Measured with logic-level input frequency but also applies to operation with crystals. Copyright © 2010–2012, Texas Instruments Incorporated 55 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fVLO VLO frequency dfVLO/dT VLO frequency temperature drift dfVLO/dVCC VLO frequency supply voltage drift Duty cycle TEST CONDITIONS Measured at ACLK Measured at ACLK(1) Measured at ACLK(2) Measured at ACLK VCC 1.8 V to 3.6 V 1.8 V to 3.6 V 1.8 V to 3.6 V 1.8 V to 3.6 V MIN TYP 6 9.4 0.5 4 40 50 (1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C)) (2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V) MAX 14 60 UNIT kHz %/°C %/V % Internal Reference, Low-Frequency Oscillator (REFO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) IREFO PARAMETER REFO oscillator current consumption TEST CONDITIONS TA = 25°C VCC 1.8 V to 3.6 V MIN TYP 3 REFO frequency calibrated Measured at ACLK 1.8 V to 3.6 V 32768 fREFO dfREFO/dT dfREFO/dVCC REFO absolute tolerance calibrated REFO frequency temperature drift REFO frequency supply voltage drift Full temperature range TA = 25°C Measured at ACLK(1) Measured at ACLK(2) 1.8 V to 3.6 V 3V 1.8 V to 3.6 V 1.8 V to 3.6 V 0.01 1.0 Duty cycle Measured at ACLK 1.8 V to 3.6 V 40 50 tSTART REFO startup time 40%/60% duty cycle 1.8 V to 3.6 V 25 (1) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C – (–40°C)) (2) Calculated using the box method: (MAX(1.8 to 3.6 V) – MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V – 1.8 V) MAX UNIT µA Hz ±3.5 % ±1.5 % %/°C %/V 60 % µs 56 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP fDCO(0,0) fDCO(0,31) fDCO(1,0) fDCO(1,31) fDCO(2,0) fDCO(2,31) fDCO(3,0) fDCO(3,31) fDCO(4,0) fDCO(4,31) fDCO(5,0) fDCO(5,31) fDCO(6,0) fDCO(6,31) fDCO(7,0) fDCO(7,31) SDCORSEL DCO frequency (0, 0) DCO frequency (0, 31) DCO frequency (1, 0) DCO frequency (1, 31) DCO frequency (2, 0) DCO frequency (2, 31) DCO frequency (3, 0) DCO frequency (3, 31) DCO frequency (4, 0) DCO frequency (4, 31) DCO frequency (5, 0) DCO frequency (5, 31) DCO frequency (6, 0) DCO frequency (6, 31) DCO frequency (7, 0) DCO frequency (7, 31) Frequency step between range DCORSEL and DCORSEL + 1 DCORSELx = 0, DCOx = 0, MODx = 0 DCORSELx = 0, DCOx = 31, MODx = 0 DCORSELx = 1, DCOx = 0, MODx = 0 DCORSELx = 1, DCOx = 31, MODx = 0 DCORSELx = 2, DCOx = 0, MODx = 0 DCORSELx = 2, DCOx = 31, MODx = 0 DCORSELx = 3, DCOx = 0, MODx = 0 DCORSELx = 3, DCOx = 31, MODx = 0 DCORSELx = 4, DCOx = 0, MODx = 0 DCORSELx = 4, DCOx = 31, MODx = 0 DCORSELx = 5, DCOx = 0, MODx = 0 DCORSELx = 5, DCOx = 31, MODx = 0 DCORSELx = 6, DCOx = 0, MODx = 0 DCORSELx = 6, DCOx = 31, MODx = 0 DCORSELx = 7, DCOx = 0, MODx = 0 DCORSELx = 7, DCOx = 31, MODx = 0 SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO) 0.07 0.70 0.15 1.47 0.32 3.17 0.64 6.07 1.3 12.3 2.5 23.7 4.6 39.0 8.5 60 1.2 SDCO Frequency step between tap DCO and DCO + 1 SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO) 1.02 Duty cycle Measured at SMCLK 40 50 dfDCO/dT DCO frequency temperature drift fDCO = 1 MHz, 0.1 dfDCO/dVCC DCO frequency voltage drift fDCO = 1 MHz 1.9 MAX 0.20 1.70 0.36 3.45 0.75 7.38 1.51 14.0 3.2 28.2 6.0 54.1 10.7 88.0 19.6 135 UNIT MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 2.3 ratio 1.12 ratio 60 % %/°C %/V Typical DCO Frequency, VCC = 3.0 V, TA = 25°C 100 DCO f – MHz 10 DCOx = 31 1 DCOx = 0 0.1 0 1 2 3 4 5 6 7 DCORSEL Figure 10. Typical DCO frequency Copyright © 2010–2012, Texas Instruments Incorporated 57 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn PMM, Brown-Out Reset (BOR) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP V(DVCC_BOR_IT–) V(DVCC_BOR_IT+) V(DVCC_BOR_hys) tRESET BORH on voltage, DVCC falling level BORH off voltage, DVCC rising level BORH hysteresis Pulse length required at RST/NMI pin to accept a reset | dDVCC/dt | < 3 V/s | dDVCC/dt | < 3 V/s 0.80 1.30 60 2 MAX UNIT 1.45 V 1.50 V 250 mV µs PMM, Core Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VCORE3(AM) Core voltage, active mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA 1.90 VCORE2(AM) Core voltage, active mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA 1.80 VCORE1(AM) Core voltage, active mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA 1.60 VCORE0(AM) Core voltage, active mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA 1.40 VCORE3(LPM) Core voltage, low-current mode, PMMCOREV = 3 2.4 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA 1.94 VCORE2(LPM) Core voltage, low-current mode, PMMCOREV = 2 2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA 1.84 VCORE1(LPM) Core voltage, low-current mode, PMMCOREV = 1 2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA 1.64 VCORE0(LPM) Core voltage, low-current mode, PMMCOREV = 0 1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA 1.44 MAX UNIT V V V V V V V V PMM, SVS High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP I(SVSH) SVS current consumption SVSHE = 0, DVCC = 3.6 V SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0 SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1 SVSHE = 1, SVSHRVL = 0 0 200 2.0 1.59 1.64 V(SVSH_IT–) SVSH on voltage level(1) SVSHE = 1, SVSHRVL = 1 SVSHE = 1, SVSHRVL = 2 1.79 1.84 1.98 2.04 SVSHE = 1, SVSHRVL = 3 2.10 2.16 SVSHE = 1, SVSMHRRL = 0 1.62 1.74 SVSHE = 1, SVSMHRRL = 1 1.88 1.94 SVSHE = 1, SVSMHRRL = 2 2.07 2.14 V(SVSH_IT+) SVSH off voltage level(1) SVSHE = 1, SVSMHRRL = 3 SVSHE = 1, SVSMHRRL = 4 2.20 2.26 2.32 2.40 SVSHE = 1, SVSMHRRL = 5 2.56 2.70 SVSHE = 1, SVSMHRRL = 6 2.85 3.00 SVSHE = 1, SVSMHRRL = 7 2.85 3.00 MAX 1.69 1.91 2.11 2.23 1.81 2.01 2.21 2.33 2.48 2.84 3.15 3.15 UNIT nA nA µA V V (1) The SVSH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage. 58 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 PMM, SVS High Side (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP tpd(SVSH) t(SVSH) SVSH propagation delay SVSH on/off delay time SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1 SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0 SVSHE = 0→1, SVSHFP = 1 SVSHE = 0→1, SVSHFP = 0 2.5 20 12.5 100 dVDVCC/dt DVCC rise time 0 MAX UNIT µs µs 1000 V/s PMM, SVM High Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVMHE = 0, DVCC = 3.6 V 0 I(SVMH) SVMH current consumption SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0 200 SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1 2.0 SVMHE = 1, SVSMHRRL = 0 1.65 1.74 SVMHE = 1, SVSMHRRL = 1 1.85 1.94 SVMHE = 1, SVSMHRRL = 2 2.02 2.14 V(SVMH) SVMH on or off voltage level(1) SVMHE = 1, SVSMHRRL = 3 SVMHE = 1, SVSMHRRL = 4 SVMHE = 1, SVSMHRRL = 5 2.18 2.26 2.32 2.40 2.56 2.70 SVMHE = 1, SVSMHRRL = 6 2.85 3.00 SVMHE = 1, SVSMHRRL = 7 2.85 3.00 SVMHE = 1, SVMHOVPE = 1 3.75 tpd(SVMH) SVMH propagation delay t(SVMH) SVMH on or off delay time SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1 SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0 SVMHE = 0→1, SVSMFP = 1 SVMHE = 0→1, SVMHFP = 0 2.5 20 12.5 100 MAX 1.86 2.02 2.22 2.35 2.48 2.84 3.15 3.15 UNIT nA nA µA V µs µs µs µs (1) The SVMH settings available depend on the VCORE (PMMCOREVx) setting. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) on recommended settings and usage. PMM, SVS Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVSLE = 0, PMMCOREV = 2 0 I(SVSL) SVSL current consumption SVSLE = 1, PMMCOREV = 2, SVSLFP = 0 200 SVSLE = 1, PMMCOREV = 2, SVSLFP = 1 2.0 tpd(SVSL) t(SVSL) SVSL propagation delay SVSL on/off delay time SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1 SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0 SVSLE = 0→1, SVSLFP = 1 SVSLE = 0→1, SVSLFP = 0 2.5 20 12.5 100 MAX UNIT nA nA µA µs µs PMM, SVM Low Side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP SVMLE = 0, PMMCOREV = 2 0 I(SVML) SVML current consumption SVMLE = 1, PMMCOREV = 2, SVMLFP = 0 200 SVMLE = 1, PMMCOREV = 2, SVMLFP = 1 2.0 MAX UNIT nA nA µA Copyright © 2010–2012, Texas Instruments Incorporated 59 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn PMM, SVM Low Side (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP tpd(SVML) SVML propagation delay t(SVML) SVML on/off delay time SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1 SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0 SVMLE = 0→1, SVMLFP = 1 SVMLE = 0→1, SVMLFP = 0 2.5 20 12.5 100 MAX UNIT µs µs Wake-Up From Low-Power Modes and Reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n fMCLK ≥ 4 MHz 3 tWAKE-UP-FAST LPM3, or LPM4 to active mode (1) (where n = 0, 1, 2, or 3), SVSLFP = 1 1 MHz < fMCLK < 4 MHz 4 Wake-up time from LPM2, PMMCOREV = SVSMLRRL = n tWAKE-UP-SLOW LPM3 or LPM4 to active (where n = 0, 1, 2, or 3), 150 mode (2) SVSLFP = 0 tWAKE-UP-LPM5 Wake-up time from LPM3.5 or LPM4.5 to active mode(3) 2 tWAKE-UP-RESET Wake-up time from RST or BOR event to active mode(3) 2 MAX 6.5 8.0 UNIT µs 165 µs 3 ms 3 ms (1) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low-side supervisor (SVSL) and low side monitor (SVML). Fastest wakeup times are possible with SVSLand SVML in full performance mode or disabled when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (2) This value represents the time from the wakeup event to the first active edge of MCLK. The wakeup time depends on the performance mode of the low-side supervisor (SVSL) and low side monitor (SVML). In this case, the SVSLand SVML are in normal mode (low current) mode when operating in AM, LPM0, and LPM1. Various options are available for SVSLand SVML while operating in LPM2, LPM3, and LPM4. See the Power Management Module and Supply Voltage Supervisor chapter in the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (3) This value represents the time from the wakeup event to the reset vector execution. Timer_A, Timers TA0, TA1, and TA2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Internal: SMCLK, ACLK fTA Timer_A input clock frequency External: TACLK Duty cycle = 50% ± 10% VCC 1.8 V, 3 V MIN TYP tTA,cap Timer_A capture timing All capture inputs, Minimum pulse duration required for 1.8 V, 3 V 20 capture MAX UNIT 20 MHz ns Timer_B, Timer TB0 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS Internal: SMCLK, ACLK fTB Timer_B input clock frequency External: TBCLK Duty cycle = 50% ± 10% VCC 1.8 V, 3 V MIN TYP tTB,cap Timer_B capture timing All capture inputs, Minimum pulse duration required for 1.8 V, 3 V 20 capture MAX UNIT 20 MHz ns 60 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Battery Backup over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IVBAT VBAT = 1.7 V, DVCC not connected, RTC running Current into VBAT terminal in VBAT = 2.2 V, case no primary battery is DVCC not connected, connected. RTC running VBAT = 3 V, DVCC not connected, RTC running TA = -40°C TA = 25°C TA = 60°C TA = 85°C TA = -40°C TA = 25°C TA = 60°C TA = 85°C TA = -40°C TA = 25°C TA = 60°C TA = 85°C General VSWITCH Switch-over level (VCC to VBAT) CVCC = 4.7 µF SVSHRL = 0 SVSHRL = 1 SVSHRL = 2 SVSHRL = 3 RON_VBAT On-resistance of switch between VBAT and VBAK VBAT = 1.8 V VBAT3 tSample,VBA T3 VCHVx VBAT to ADC input channel 12: VBAT divide, VBAT3 ≠ VBAT /3 VBAT to ADC: Sampling time required if VBAT3 selected ADC12ON = 1, Error of conversion result ≤ 1 LSB Charger end voltage CHVx = 2 CHCx = 1 RCHARGE Charge limiting resistor CHCx = 2 CHCx = 3 VCC 0V 1.8 V 3V 3.6 V MIN 1.59 1.79 1.98 2.10 1000 2.65 TYP 0.43 0.52 0.58 0.64 0.50 0.59 0.64 0.71 0.68 0.75 0.79 0.86 VSVSH_IT- 0.35 0.6 1.0 1.2 2.7 MAX UNIT µA µA µA 1.69 1.91 V 2.11 2.23 1 kΩ ±5% ±5% V ±5% ns 2.9 V 5 10 kΩ 20 USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) fUSCI PARAMETER USCI input clock frequency TEST CONDITIONS Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% VCC MIN TYP MAX UNIT fSYSTEM MHz fBITCLK BITCLK clock frequency (equals baud rate in MBaud) 1 MHz tτ UART receive deglitch time(1) 2.2 V 50 3V 50 600 ns 600 (1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. Copyright © 2010–2012, Texas Instruments Incorporated 61 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 11 and ) fUSCI PARAMETER USCI input clock frequency TEST CONDITIONS SMCLK, ACLK, Duty cycle = 50% ± 10% VCC MIN TYP tSU,MI SOMI input data setup time PMMCOREV = 0 PMMCOREV = 3 1.8 V 55 3V 38 2.4 V 30 3V 25 tHD,MI SOMI input data hold time PMMCOREV = 0 PMMCOREV = 3 1.8 V 0 3V 0 2.4 V 0 3V 0 tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 0 UCLK edge to SIMO valid, CL = 20 pF, PMMCOREV = 3 1.8 V 3V 2.4 V 3V tHD,MO SIMO output data hold time(3) CL = 20 pF, PMMCOREV = 0 CL = 20 pF, PMMCOREV = 3 1.8 V -10 3V -8 2.4 V -10 3V -8 MAX fSYSTEM 20 18 16 15 UNIT MHz ns ns ns ns ns ns ns ns (1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)). For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave. (2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 11 and . (3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 11 and . CKPL = 0 1/fUCxCLK UCLK CKPL = 1 SOMI tLO/HI tLO/HI tSU,MI tHD,MI SIMO tHD,MO tVALID,MO Figure 11. SPI Master Mode, CKPH = 0 62 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 CKPL = 0 UCLK CKPL = 1 SOMI 1/fUCxCLK tLO/HI tLO/HI tSU,MI tHD,MI SIMO tHD,MO tVALID,MO Figure 12. SPI Master Mode, CKPH = 1 Copyright © 2010–2012, Texas Instruments Incorporated 63 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (see Figure 13 and Figure 14) PARAMETER tSTE,LEAD STE lead time, STE low to clock TEST CONDITIONS PMMCOREV = 0 PMMCOREV = 3 VCC 1.8 V 3V 2.4 V 3V MIN TYP 11 8 7 6 tSTE,LAG STE lag time, Last clock to STE high PMMCOREV = 0 PMMCOREV = 3 1.8 V 3 3V 3 2.4 V 3 3V 3 tSTE,ACC STE access time, STE low to SOMI data out PMMCOREV = 0 PMMCOREV = 3 1.8 V 3V 2.4 V 3V tSTE,DIS STE disable time, STE high to SOMI high impedance PMMCOREV = 0 PMMCOREV = 3 1.8 V 3V 2.4 V 3V tSU,SI SIMO input data setup time PMMCOREV = 0 PMMCOREV = 3 1.8 V 5 3V 5 2.4 V 2 3V 2 tHD,SI SIMO input data hold time PMMCOREV = 0 PMMCOREV = 3 1.8 V 5 3V 5 2.4 V 5 3V 5 tVALID,SO SOMI output data valid time(2) UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 0 UCLK edge to SOMI valid, CL = 20 pF, PMMCOREV = 3 1.8 V 3V 2.4 V 3V tHD,SO SOMI output data hold time(3) CL = 20 pF, PMMCOREV = 0 CL = 20 pF, PMMCOREV = 3 1.8 V 18 3V 12 2.4 V 10 3V 8 MAX UNIT ns ns ns ns 66 ns 50 36 ns 30 30 ns 23 16 ns 13 ns ns ns ns 76 ns 60 44 ns 40 ns ns (1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)). For the master's parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached slave. (2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 13 and Figure 14. (3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 13 and Figure 14. 64 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 STE CKPL = 0 UCLK CKPL = 1 SIMO tSTE,LEAD 1/fUCxCLK tLO/HI tLO/HI tSTE,LAG tSU,SI tHD,SI SOMI tSTE,ACC tHD,SO tVALID,SO tSTE,DIS Figure 13. SPI Slave Mode, CKPH = 0 STE CKPL = 0 UCLK CKPL = 1 SIMO tSTE,LEAD 1/fUCxCLK tLO/HI tLO/HI tSTE,LAG tSU,SI tHD,SI SOMI tSTE,ACC tHD,MO tVALID,SO tSTE,DIS Figure 14. SPI Slave Mode, CKPH = 1 Copyright © 2010–2012, Texas Instruments Incorporated 65 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 15) fUSCI PARAMETER USCI input clock frequency TEST CONDITIONS Internal: SMCLK, ACLK External: UCLK Duty cycle = 50% ± 10% VCC MIN TYP MAX UNIT fSYSTEM MHz fSCL tHD,STA tSU,STA tHD,DAT tSU,DAT tSU,STO tSP SCL clock frequency Hold time (repeated) START Setup time for a repeated START Data hold time Data setup time Setup time for STOP fSCL ≤ 100 kHz fSCL > 100 kHz fSCL ≤ 100 kHz fSCL > 100 kHz fSCL ≤ 100 kHz fSCL > 100 kHz Pulse width of spikes suppressed by input filter 2.2 V, 3 V 0 4.0 2.2 V, 3 V 0.6 4.7 2.2 V, 3 V 0.6 2.2 V, 3 V 0 2.2 V, 3 V 250 4.0 2.2 V, 3 V 0.6 2.2 V 50 3V 50 400 kHz µs µs ns ns µs 600 ns 600 SDA tHD,STA tSU,STA tHD,STA tBUF tLOW tHIGH tSP SCL tHD,DAT tSU,DAT Figure 15. I2C Mode Timing tSU,STO 66 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 LCD_B, Recommended Operating Conditions PARAMETER CONDITIONS VCC,LCD_B, CP en,3.6 Supply voltage range, charge pump enabled, VLCD ≤ 3.6 V VCC,LCD_B, CP en,3.3 Supply voltage range, charge pump enabled, VLCD ≤ 3.3 V VCC,LCD_B, int. bias Supply voltage range, internal biasing, charge pump disabled LCDCPEN = 1, 0000 < VLCDx ≤ 1111 (charge pump enabled, VLCD ≤ 3.6 V) LCDCPEN = 1, 0000 < VLCDx ≤ 1100 (charge pump enabled, VLCD ≤ 3.3 V) LCDCPEN = 0, VLCDEXT = 0 VCC,LCD_B, ext. bias VCC,LCD_B, VLCDEXT Supply voltage range, external biasing, charge pump disabled Supply voltage range, external LCD voltage, internal or external biasing, charge pump disabled LCDCPEN = 0, VLCDEXT = 0 LCDCPEN = 0, VLCDEXT = 1 VLCDCAP/R33 External LCD voltage at LCDCAP/R33, internal or external biasing, charge LCDCPEN = 0, VLCDEXT = 1 pump disabled CLCDCAP Capacitor on LCDCAP when charge pump enabled LCDCPEN = 1, VLCDx > 0000 (charge pump enabled) fFrame LCD frame frequency range fLCD = 2 × mux × fFRAME (mux = 1 (static), 2, 3, 4) fACLK,in CPanel ACLK input frequency range Panel capacitance 100-Hz frame frequency VR33 Analog input voltage at R33 LCDCPEN = 0, VLCDEXT = 1 VR23,1/3bias VR13,1/3bias VR13,1/2bias VR03 VLCD-VR03 VLCDREF/R13 Analog input voltage at R23 LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 Analog input voltage at R13 with 1/3 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 0 Analog input voltage at R13 with 1/2 biasing LCDREXT = 1, LCDEXTBIAS = 1, LCD2B = 1 Analog input voltage at R03 R0EXT = 1 Voltage difference between VLCD and R03 LCDCPEN = 0, R0EXT = 1 External LCD reference voltage applied at LCDREF/R13 VLCDREFx = 01 MIN NOM MAX UNIT 2.2 3.6 V 2.0 3.6 V 2.4 3.6 V 2.4 3.6 V 2.0 3.6 V 2.4 3.6 V 4.7 4.7 10 µF 0 100 Hz 30 32 40 kHz 10000 pF 2.4 VCC + 0.2 V VR13 VR03 + 2/3 × (VR33-VR03) VR33 V VR03 VR03 + 1/3 × (VR33-VR03) VR23 V VR03 VR03 + 1/2 × (VR33-VR03) VR33 V VSS V 2.4 VCC+0 .2 V 0.8 1.2 1.5 V Copyright © 2010–2012, Texas Instruments Incorporated 67 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn LCD_B, Electrical Characteristics over operating free-air temperature range (unless otherwise noted) VLCD PARAMETER LCD voltage TEST CONDITIONS VCC MIN TYP MAX UNIT VLCDx = 0000, VLCDEXT = 0 2.4 V - 3.6 V VCC V LCDCPEN = 1, VLCDx = 0001 2 V - 3.6 V 2.60 V LCDCPEN = 1, VLCDx = 0010 2 V - 3.6 V 2.66 V LCDCPEN = 1, VLCDx = 0011 2 V - 3.6 V 2.72 V LCDCPEN = 1, VLCDx = 0100 2 V - 3.6 V 2.79 V LCDCPEN = 1, VLCDx = 0101 2 V - 3.6 V 2.85 V LCDCPEN = 1, VLCDx = 0110 2 V - 3.6 V 2.92 V LCDCPEN = 1, VLCDx = 0111 2 V - 3.6 V 2.98 V LCDCPEN = 1, VLCDx = 1000 2 V - 3.6 V 3.05 V LCDCPEN = 1, VLCDx = 1001 2 V - 3.6 V 3.10 V LCDCPEN = 1, VLCDx = 1010 2 V - 3.6 V 3.17 V LCDCPEN = 1, VLCDx = 1011 2 V - 3.6 V 3.24 V LCDCPEN = 1, VLCDx = 1100 2 V - 3.6 V 3.30 V LCDCPEN = 1, VLCDx = 1101 2.2 V - 3.6 V 3.36 V LCDCPEN = 1, VLCDx = 1110 2.2 V - 3.6 V 3.42 V LCDCPEN = 1, VLCDx = 1111 2.2 V - 3.6 V 3.48 3.6 V ICC,Peak,CP Peak supply currents due to charge pump activities LCDCPEN = 1, VLCDx = 1111 2.2 V 400 µA tLCD,CP,on Time to charge CLCD when discharged CLCD = 4.7 µF, LCDCPEN = 0→1, VLCDx = 1111 2.2 V 100 500 ms ICP,Load Maximum charge pump load LCDCPEN = 1, VLCDx = 1111 2.2 V 50 µA current RLCD,Seg RLCD,COM LCD driver output impedance, segment lines LCD driver output impedance, common lines LCDCPEN = 1, VLCDx = 1000, ILOAD = ±10 µA LCDCPEN = 1, VLCDx = 1000, ILOAD = ±10 µA 2.2 V 2.2 V 10 kΩ 10 kΩ 12-Bit ADC, Power Supply and Input Range Conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) AVCC V(Ax) IADC12_A PARAMETER Analog supply voltage Analog input voltage range(2) TEST CONDITIONS AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V All ADC12 analog input pins Ax Operating supply current into AVCC terminal(3) fADC12CLK = 5 MHz (4) VCC 2.2 V 3V MIN TYP MAX UNIT 2.2 3.6 V 0 AVCC V 150 200 µA 150 250 CI Input capacitance Only one terminal Ax can be selected at one time 2.2 V 20 25 pF RI Input MUX ON resistance 0 V ≤ VIN ≤ V(AVCC) 10 200 1900 Ω (1) The leakage current is specified by the digital I/O input leakage. (2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the reference voltage is supplied by an external source or if the internal voltage is used and REFOUT = 1, then decoupling capacitors are required. See REF, External Reference and REF, Built-In Reference. (3) The internal reference supply current is not included in current consumption parameter IADC12. (4) ADC12ON = 1, REFON = 0, SHT0 = 0, SHT1 = 0, ADC12DIV = 0 68 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 12-Bit ADC, Timing Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT For specified performance of ADC12 linearity parameters using an external reference voltage or AVCC as reference(1) 0.45 4.8 5.0 fADC12CLK ADC conversion clock For specified performance of ADC12 linearity parameters using the internal reference(2) 2.2 V, 3 V 0.45 2.4 4.0 MHz For specified performance of ADC12 linearity parameters using the internal reference(3) 0.45 2.4 2.7 fADC12OSC Internal ADC12 oscillator (4) ADC12DIV = 0, fADC12CLK = fADC12OSC 2.2 V, 3 V 4.2 4.8 5.4 MHz tCONVERT Conversion time REFON = 0, Internal oscillator, ADC12OSC used for ADC conversion clock 2.2 V, 3 V 2.4 3.1 µs External fADC12CLK from ACLK, MCLK or SMCLK, (5) ADC12SSEL ≠ 0 tSample Sampling time RS = 400 Ω, RI = 200 Ω, CI = 20 pF, τ = [RS + RI] × CI(6) 2.2 V, 3 V 1000 ns (1) REFOUT = 0, external reference voltage: SREF2 = 0, SREF1 = 1, SREF0 = 0. AVCC as reference voltage: SREF2 = 0, SREF1 = 0, SREF0 = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC. For other clock sources, the specified performance of the ADC12 linearity is ensured with fADC12CLK maximum of 5 MHz. (2) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 1 (3) SREF2 = 0, SREF1 = 1, SREF0 = 0, ADC12SR = 0, REFOUT = 0. The specified performance of the ADC12 linearity is ensured when using the ADC12OSC divided by 2. (4) The ADC12OSC is sourced directly from MODOSC inside the UCS. (5) 13 × ADC12DIV × 1/fADC12CLK (6) Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB: tSample = ln(2n+1) x (RS + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance 12-Bit ADC, Linearity Parameters Using an External Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER EI Integral linearity error(1) TEST CONDITIONS 1.4 V ≤ dVREF ≤ 1.6 V(2) 1.6 V < dVREF (2) VCC 2.2 V, 3 V MIN TYP ED Differential linearity error(1) (2) EO Offset error(3) dVREF ≤ 2.2 V(2) dVREF > 2.2 V(2) EG Gain error(3) (2) ET Total unadjusted error dVREF ≤ 2.2 V(2) dVREF > 2.2 V(2) 2.2 V, 3 V 2.2 V, 3 V ±3 2.2 V, 3 V ±1.5 2.2 V, 3 V ±1 2.2 V, 3 V ±3.5 2.2 V, 3 V ±2 MAX ±2 ±1.7 UNIT LSB ±1 LSB ±5.6 LSB ±3.5 ±2.5 LSB ±7.1 LSB ±5 (1) Parameters are derived using the histogram method. (2) The external reference voltage is selected by: SREF2 = 0 or 1, SREF1 = 1, SREF0 = 0. dVREF = VR+ - VR-. VR+ < AVCC. VR-> AVSS. Unless otherwise mentioned, dVREF > 1.5 V. Impedance of the external reference voltage R < 100 Ω, and two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF+/VREF- to decouple the dynamic current. See also the MSP430F5xx and MSP430F6xx Family User's Guide (SLAU208). (3) Parameters are derived using a best fit curve. 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER EI Integral linearity error(1) ED Differential linearity error(1) TEST CONDITIONS See (2) See (2) VCC 2.2 V, 3 V 2.2 V, 3 V MIN TYP MAX ±1.7 ±1 UNIT LSB LSB (1) Parameters are derived using the histogram method. (2) AVCC as reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 0. Copyright © 2010–2012, Texas Instruments Incorporated 69 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn 12-Bit ADC, Linearity Parameters Using AVCC as Reference Voltage (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER EO Offset error(3) EG Gain error(3) ET Total unadjusted error TEST CONDITIONS See (2) See (2) See (2) VCC 2.2 V, 3 V 2.2 V, 3 V 2.2 V, 3 V MIN TYP ±1 ±2 ±2 (3) Parameters are derived using a best fit curve. MAX ±2 ±4 ±5 UNIT LSB LSB LSB 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS(1) VCC MIN TYP EI Integral linearity error(2) ADC12SR = 0, REFOUT = 1 ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 4.0 MHz fADC12CLK ≤ 2.7 MHz 2.2 V, 3 V ED Differential linearity error(2) ADC12SR = 0, REFOUT = 1 ADC12SR = 0, REFOUT = 1 ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 4.0 MHz -1 fADC12CLK ≤ 2.7 MHz 2.2 V, 3 V fADC12CLK ≤ 2.7 MHz -1 EO Offset error(3) ADC12SR = 0, REFOUT = 1 ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 4.0 MHz fADC12CLK ≤ 2.7 MHz 2.2 V, 3 V ±2 ±2 EG Gain error(3) ADC12SR = 0, REFOUT = 1 ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 4.0 MHz fADC12CLK ≤ 2.7 MHz 2.2 V, 3 V ±1 ET Total unadjusted error ADC12SR = 0, REFOUT = 1 ADC12SR = 0, REFOUT = 0 fADC12CLK ≤ 4.0 MHz fADC12CLK ≤ 2.7 MHz 2.2 V, 3 V ±2 MAX ±1.7 ±2.5 +1.5 ±1 +2.5 ±4 ±4 ±2.5 ±1% (4) ±5 ±1% (4) UNIT LSB LSB LSB LSB VREF LSB VREF (1) The external reference voltage is selected by: SREF2 = 0, SREF1 = 0, SREF0 = 1. dVREF = VR+ - VR-. (2) Parameters are derived using the histogram method. (3) Parameters are derived using a best fit curve. (4) The gain error and the total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. In this mode the reference voltage used by the ADC12_A is not available on a pin. 12-Bit ADC, Temperature Sensor and Built-In VMID(1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VSENSOR PARAMETER See (2) TEST CONDITIONS ADC12ON = 1, INCH = 0Ah, TA = 0°C VCC 2.2 V 3V MIN TYP 680 680 TCSENSOR 2.2 V 2.25 ADC12ON = 1, INCH = 0Ah 3V 2.25 tSENSOR(sample) Sample time required if channel 10 is selected(3) ADC12ON = 1, INCH = 0Ah, Error of conversion result ≤ 1 LSB 2.2 V 100 3V 100 VMID AVCC divider at channel 11 ADC12ON = 1, INCH = 0Bh, VMID is approximately 0.5 × VAVCC 2.2 V 3V 1.06 1.1 1.46 1.5 tVMID(sample) Sample time required if channel 11 is selected(4) ADC12ON = 1, INCH = 0Bh, Error of conversion result ≤ 1 LSB 2.2 V, 3 V 1000 MAX UNIT mV mV/°C µs 1.14 V 1.54 ns (1) The temperature sensor is provided by the REF module. See the REF module parametric, IREF+, regarding the current consumption of the temperature sensor. (2) The temperature sensor offset can be significant. A single-point calibration is recommended to minimize the offset error of the built-in temperature sensor. The TLV structure contains calibration values for 30°C ± 3°C and 85°C ± 3°C for each of the available reference voltage levels. The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and VSENSOR can be computed from the calibration values for higher accuracy. See also the MSP430F5xx and MSP430F6xx Family User's Guide (SLAU208). (3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on). (4) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. 70 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn Typical Temperature Sensor Voltage - mV MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 1000 950 900 850 800 750 700 650 600 550 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Ambient Temperature - ˚C Figure 16. Typical Temperature Sensor Voltage REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) VeREF+ PARAMETER Positive external reference voltage input TEST CONDITIONS VeREF+ > VREF–/VeREF– (2) VCC MIN TYP 1.4 VREF–/VeREF– Negative external reference voltage input VeREF+ > VREF–/VeREF– (3) 0 VeREF+ – VREF–/VeREF– IVeREF+, IVREF–/VeREF– Differential external reference voltage input Static input current VeREF+ > VREF–/VeREF– (4) 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC12CLK = 5 MHz, ADC12SHTx = 1h, Conversion rate 200 ksps 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC12CLK = 5 MHZ, ADC12SHTx = 8h, Conversion rate 20 ksps 1.4 2.2 V, 3 V -26 2.2 V, 3 V -1.2 CVREF+/- Capacitance at VREF+/terminal (5) 10 MAX UNIT AVCC V 1.2 V AVCC V 26 µA +1.2 µA µF (1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, Ci, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. (2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. (3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. (4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. (5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Copyright © 2010–2012, Texas Instruments Incorporated 71 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn REF, Built-In Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) VREF+ AVCC(min) IREF+ PARAMETER TEST CONDITIONS REFVSEL = {2} for 2.5 V, REFON = REFOUT = 1 , IVREF+ = 0 A Positive built-in reference voltage output REFVSEL = {1} for 2 V, REFON = REFOUT = 1, IVREF+ = 0 A REFVSEL = {0} for 1.5 V, REFON = REFOUT = 1, IVREF+ = 0 A AVCC minimum voltage, REFVSEL = {0} for 1.5 V Positive built-in reference REFVSEL = {1} for 2 V active REFVSEL = {2} for 2.5 V ADC12SR = 1(4), REFON = 1, REFOUT = 0, REFBURST = 0 Operating supply current into AVCC terminal (2) (3) ADC12SR = 1(4), REFON = 1, REFOUT = 1, REFBURST = 0 ADC12SR = 0(4), REFON = 1, REFOUT = 0, REFBURST = 0 ADC12SR = 0(4), REFON = 1, REFOUT = 1, REFBURST = 0 VCC MIN TYP 3V 2.5 3V 2.0 2.2 V, 3 V 3V 3V 3V 3V 1.5 2.2 2.3 2.8 70 0.45 210 0.95 IL(VREF+) Load-current regulation, VREF+ terminal(5) CVREF+ TCREF+ TCREF+ Capacitance at VREF+ terminal Temperature coefficient of built-in reference(7) Temperature coefficient of built-in reference(7) PSRR_DC Power supply rejection ratio (dc) REFVSEL = {0, 1, 2} IVREF+ = +10 µA / -1000 µA AVCC = AVCC(min) for each reference level, REFVSEL = {0, 1, 2}, REFON = REFOUT = 1 REFON = REFOUT = 1, (6) 0 mA ≤ IVREF+ ≤ IVREF+(max) IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ –1 mA REFOUT = 0 IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ –1 mA REFOUT = 1 AVCC = AVCC(min) - AVCC(max), TA = 25°C, REFVSEL = {0, 1, 2}, REFON = 1, REFOUT = 0 or 1 2.2 V, 3 V 2.2 V, 3 V 2.2 V, 3 V 1500 20 20 20 120 PSRR_AC Power supply rejection ratio (ac) AVCC = AVCC(min) - AVCC(max), TA = 25°C, REFVSEL = {0, 1, 2}, REFON = 1, REFOUT = 0 or 1 1 MAX UNIT ±1% ±1% V ±1% V 100 µA 0.75 mA 310 µA 1.7 mA 2500 µV/mA 100 pF ppm/ °C 50 ppm/ °C 300 µV/V mV/V (1) The reference is supplied to the ADC by the REF module and is buffered locally inside the ADC. The ADC uses two internal buffers, one smaller and one larger for driving the VREF+ terminal. When REFOUT = 1, the reference is available at the VREF+ terminal, as well as, used as the reference for the conversion and utilizes the larger buffer. When REFOUT = 0, the reference is only used as the reference for the conversion and utilizes the smaller buffer. (2) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. REFOUT = 0 represents the current contribution of the smaller buffer. REFOUT = 1 represents the current contribution of the larger buffer without external load. (3) The temperature sensor is provided by the REF module. Its current is supplied via terminal AVCC and is equivalent to IREF+ with REFON = 1 and REFOUT = 0. (4) For devices without the ADC12, the parametric with ADC12SR = 0 are applicable. (5) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB traces or other external factors. (6) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC12_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). (7) Calculated using the box method: (MAX(-40 to 85°C) – MIN(-40 to 85°C)) / MIN(-40 to 85°C)/(85°C – (–40°C)). 72 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 REF, Built-In Reference (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) tSETTLE PARAMETER TEST CONDITIONS Settling time of reference voltage (8) AVCC = AVCC(min) - AVCC(max), REFVSEL = {0, 1, 2}, REFOUT = 0, REFON = 0 → 1 AVCC = AVCC(min) - AVCC(max), CVREF = CVREF(max), REFVSEL = {0, 1, 2}, REFOUT = 1, REFON = 0 → 1 VCC MIN TYP 75 75 MAX UNIT µs (8) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external capacitive load when REFOUT = 1. 12-Bit DAC, Supply Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER AVCC Analog supply voltage TEST CONDITIONS AVCC = DVCC, AVSS = DVSS = 0 V DAC12AMPx = 2, DAC12IR = 0, DAC12IOG = 1, DAC12_xDAT = 0800h, VeREF+ = VREF+ = 1.5 V VCC MIN TYP 2.20 3V 65 DAC12AMPx = 2, DAC12IR = 1, DAC12_xDAT = 0800h, 125 IDD Supply current, single DAC channel(1) (2) VeREF+ = VREF+ = AVCC DAC12AMPx = 5, DAC12IR = 1, DAC12_xDAT = 0800h, 2.2 V, 3 V 250 VeREF+ = VREF+ = AVCC DAC12AMPx = 7, DAC12IR = 1, DAC12_xDAT = 0800h, 750 VeREF+ = VREF+ = AVCC DAC12_xDAT = 800h, VeREF+ = 1.5 V, ΔAVCC = 100 mV 2.2 V 70 PSRR Power supply rejection ratio(3) (4) DAC12_xDAT = 800h, VeREF+ = 1.5 V or 2.5 V, 3V 70 ΔAVCC = 100 mV MAX UNIT 3.60 V 110 165 µA 350 1100 dB (1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly. (2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications. (3) PSRR = 20 log (ΔAVCC / ΔVDAC12_xOUT) (4) The internal reference is not used. 12-Bit DAC, Linearity Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17) INL DNL PARAMETER Resolution Integral nonlinearity (1) Differential nonlinearity (1) TEST CONDITIONS 12-bit monotonic VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 VCC 2.2 V 3V 2.2 V 3V MIN TYP MAX UNIT 12 bits ±2 ±4(2) LSB ±2 ±4 ±0.4 ±0.4 ±1 (2) LSB ±1 (1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1. (2) This parameter is not production tested. Copyright © 2010–2012, Texas Instruments Incorporated 73 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn 12-Bit DAC, Linearity Specifications (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17) PARAMETER EO Offset voltage TEST CONDITIONS Without calibration(1) (3) VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 With calibration(1) (3) VeREF+ = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 VCC 2.2 V MIN TYP MAX UNIT ±21 (2) 3V 2.2 V ±21 mV ±1.5 (2) 3V ±1.5 dE(O)/dT Offset error temperature coefficient (1) With calibration 2.2 V, 3 V ±10 µV/°C EG Gain error VeREF+ = 1.5 V VeREF+ = 2.5 V 2.2 V 3V ±2.5 %FSR ±2.5 dE(G)/dT Gain temperature coefficient (1) 2.2 V, 3 V ppm 10 of FSR/ °C tOffset_Cal Time for offset calibration (4) DAC12AMPx = 2 DAC12AMPx = 3, 5 DAC12AMPx = 4, 6, 7 2.2 V, 3 V 165 66 ms 16.5 (3) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON (4) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect accuracy and is not recommended. DAC Output RLoad = ¥ AVCC 2 CLoad = 100 pF DAC VOUT VR+ Ideal transfer function Offset Error Positive Negative Gain Error DAC Code Figure 17. Linearity Test Load Conditions and Gain/Offset Definition 74 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 12-Bit DAC, Output Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS No load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 VCC MIN TYP 0 VO Output voltage range(1) (see Figure 18) No load, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 RLoad = 3 kΩ, VeREF+ = AVCC, 2.2 V, 3 V AVCC – 0.05 DAC12_xDAT = 0h, DAC12IR = 1, 0 DAC12AMPx = 7 RLoad = 3 kΩ, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 AVCC – 0.13 CL(DAC12) Maximum DAC12 load capacitance 2.2 V, 3 V IL(DAC12) Maximum DAC12 load current DAC12AMPx = 2, DAC12xDAT = 0FFFh, VO/P(DAC12) > AVCC – 0.3 DAC12AMPx = 2, DAC12xDAT = 0h, VO/P(DAC12) < 0.3 V RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V, DAC12AMPx = 2, DAC12_xDAT = 0h 2.2 V, 3 V –1 150 RO/P(DAC12) Output resistance RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V, (see Figure 18) DAC12_xDAT = 0FFFh 2.2 V, 3 V 150 RLoad = 3 kΩ, 0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V (1) Data is valid after the offset calibration of the output amplifier. MAX UNIT 0.005 AVCC V 0.1 AVCC 100 pF mA 1 250 250 Ω 6 ILoad DAC12 O/P(DAC12_x) RLoad AVCC 2 CLoad = 100 pF RO/P(DAC12_x) Max Min 0.3 Figure 18. DAC12_x Output Resistance Tests AVCC – 0.3 V VOUT AVCC Copyright © 2010–2012, Texas Instruments Incorporated 75 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn 12-Bit DAC, Reference Input Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VeREF+ Reference input voltage range TEST CONDITIONS DAC12IR = 0(1) (2) DAC12IR = 1(3) (4) VCC 2.2 V, 3 V MIN TYP AVCC /3 AVCC Ri(VREF+), Ri(VeREF+) Reference input resistance(5) DAC12_0 IR = DAC12_1 IR = 0 DAC12_0 IR = 1, DAC12_1 IR = 0 DAC12_0 IR = 0, DAC12_1 IR = 1 DAC12_0 IR = DAC12_1 IR = 1, DAC12_0 SREFx = DAC12_1 SREFx(6) 2.2 V, 3 V 20 48 48 24 MAX AVCC + 0.2 AVCC + 0.2 UNIT V MΩ kΩ (1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC). (2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)]. (3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC). (4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG). (5) This impedance depends on tradeoff in power savings. Current devices have 48 kΩ for each channel when divide is enabled. Can be increased if performance can be maintained. (6) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance. 12-Bit DAC, Dynamic Specifications VREF = VCC, DAC12IR = 1 (see Figure 19 and Figure 20), over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tON DAC12 on time TEST CONDITIONS DAC12_xDAT = 800h, ErrorV(O) < ±0.5 LSB(1) (see Figure 19) DAC12AMPx = 0 → {2, 3, 4} DAC12AMPx = 0 → {5, 6} DAC12AMPx = 0 → 7 VCC 2.2 V, 3 V MIN TYP MAX UNIT 60 120 15 30 µs 6 12 tS(FS) Settling time, full scale DAC12_xDAT = 80h → F7Fh → 80h DAC12AMPx = 2 DAC12AMPx = 3, 5 DAC12AMPx = 4, 6, 7 2.2 V, 3 V 100 200 40 80 µs 15 30 tS(C-C) Settling time, code to code DAC12_xDAT = 3F8h → 408h → 3F8h, BF8h → C08h → BF8h DAC12AMPx = 2 DAC12AMPx = 3, 5 DAC12AMPx = 4, 6, 7 2.2 V, 3 V 5 2 µs 1 SR Slew rate DAC12_xDAT = 80h → F7Fh → 80h(2) DAC12AMPx = 2 DAC12AMPx = 3, 5 DAC12AMPx = 4, 6, 7 2.2 V, 3 V 0.05 0.35 0.35 1.10 1.50 5.20 V/µs Glitch energy DAC12_xDAT = 800h → 7FFh → 800h DAC12AMPx = 7 2.2 V, 3 V 35 nV-s (1) RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 19. (2) Slew rate applies to output voltage steps ≥ 200 mV. DAC Output RO/P(DAC12.x) RLoad = 3 kW ILoad AVCC 2 CLoad = 100 pF Conversion 1 Conversion 2 VOUT Glitch Energy ±1/2 LSB Conversion 3 ±1/2 LSB tsettleLH Figure 19. Settling Time and Glitch Energy Testing tsettleHL 76 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Conversion 1 V OUT Conversion 2 90% Conversion 3 90% 10% 10% t SRLH t SRHL Figure 20. Slew Rate Testing 12-Bit DAC, Dynamic Specifications (Continued) over recommended ranges of supply voltage and TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS VCC BW–3dB 3-dB bandwidth, VDC = 1.5 V, VAC = 0.1 VPP (see Figure 21) DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h 2.2 V, 3 V Channel-to-channel crosstalk(1) (see Figure 22) DAC12_0DAT = 800h, No load, DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ, fDAC12_0OUT = 10 kHz at 50/50 duty cycle DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ, DAC12_1DAT = 800h, No load, fDAC12_0OUT = 10 kHz at 50/50 duty cycle 2.2 V, 3 V (1) RLoad = 3 kΩ, CLoad = 100 pF VeREF+ AC DC DAC12_x RLoad = 3 kW ILoad DACx CLoad = 100 pF AVCC 2 MIN TYP MAX UNIT 40 180 kHz 550 –80 dB –80 VREF+ Figure 21. Test Conditions for 3-dB Bandwidth Specification DAC12_0 DAC12_1 ILoad RLoad DAC0 CLoad = 100 pF AVCC 2 ILoad RLoad DAC1 CLoad = 100 pF AVCC 2 DAC12_xDAT 080h VOUT VDAC12_yOUT VDAC12_xOUT 7F7h 080h fToggle Figure 22. Crosstalk Test Conditions 7F7h 080h Copyright © 2010–2012, Texas Instruments Incorporated 77 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Comparator_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC Supply voltage TEST CONDITIONS VCC 1.8 V MIN TYP 1.8 IAVCC_COMP Comparator operating supply current into AVCC terminal, Excludes reference resistor ladder CBPWRMD = 00 CBPWRMD = 01 2.2 V 30 3V 40 2.2 V, 3 V 10 CBPWRMD = 10 2.2 V, 3 V 0.1 IAVCC_REF Quiescent current of local reference voltage amplifier into AVCC terminal CBREFACC = 1, CBREFLx = 01 VIC Common mode input range 0 VOFFSET Input offset voltage CBPWRMD = 00 CBPWRMD = 01, 10 CIN RSIN Input capacitance Series input resistance ON - switch closed OFF - switch opened 5 3 50 CBPWRMD = 00, CBF = 0 tPD Propagation delay, response time CBPWRMD = 01, CBF = 0 CBPWRMD = 10, CBF = 0 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 00 0.35 0.6 tPD,filter Propagation delay with filter active CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 01 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 10 0.6 1.0 1.0 1.8 CBPWRMD = 00, CBON = 1, CBF = 1, CBFDLY = 11 1.8 3.4 tEN_CMP Comparator enable time, settling time CBON = 0 to CBON = 1 CBPWRMD = 00, 01, 10 1 tEN_REF Resistor reference enable time CBON = 0 to CBON = 1 0.3 VCB_REF Reference voltage for a given VIN = reference into resistor ladder, tap n = 0 to 31 VIN × VIN × (n+0.5) (n+1) / 32 / 32 www.ti.com.cn MAX 3.6 40 50 65 30 0.5 UNIT V µA 22 µA VCC - 1 V ±20 mV ±10 pF 4 kΩ MΩ 450 ns 600 ns 50 µs 1.0 µs 1.8 µs 3.4 µs 6.5 µs 2 µs 1.5 µs VIN × (n+1.5) V / 32 78 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Ports PU.0 and PU.1 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage VIH High-level input voltage VIL Low-level input voltage TEST CONDITIONS VUSB = 3.3 V ± 10%, IOH = -25 mA VUSB = 3.3 V ± 10%, IOL = 25 mA VUSB = 3.3 V ± 10% VUSB = 3.3 V ± 10% VCC MIN TYP 2.4 2.0 MAX 0.4 0.8 UNIT V V V V USB Output Ports DP and DM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP VOH D+, D- single ended USB 2.0 load conditions 2.8 VOL D+, D- single ended USB 2.0 load conditions 0 Z(DRV) D+, D- impedance Including external series resistor of 27 Ω 28 tRISE Rise time Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 4 tFALL Fall time Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+ 4 MAX 3.6 0.3 44 20 20 UNIT V V Ω ns ns USB Input Ports DP and DM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP V(CM) Differential input common mode range 0.8 Z(IN) Input impedance 300 VCRS Crossover voltage 1.3 VIL Static SE input logic low level 0.8 VIH Static SE input logic high level VDI Differential input voltage MAX 2.5 2.0 2.0 0.2 UNIT V kΩ V V V V USB-PWR (USB Power System) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VLAUNCH VBUS VUSB V18 IUSB_EXT IDET ISUSPEND VBUS detection threshold USB bus voltage USB LDO output voltage Internal USB voltage(1) Maximum external current from VUSB terminal(2) USB LDO current overload detection(3) Operating supply current into VBUS terminal.(4) Normal operation USB LDO is on USB LDO is on, USB PLL disabled 3.75 V 3.76 5.5 V 3.3 ±9% V 1.8 V 12 mA 60 100 mA 250 µA CBUS CUSB C18 tENABLE VBUS terminal recommended capacitance VUSB terminal recommended capacitance V18 terminal recommended capacitance Settling time VUSB and V18 Within 2%, recommended capacitances 4.7 µF 220 nF 220 nF 2 ms RPUR Pullup resistance of PUR terminal 70 110 150 Ω (1) This voltage is for internal use only. No external dc loading should be applied. (2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB operation. (3) A current overload is detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value. (4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification. Copyright © 2010–2012, Texas Instruments Incorporated 79 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn USB-PLL (USB Phase-Locked Loop) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) IPLL fPLL fUPD tLOCK tJitter PARAMETER Operating supply current PLL frequency PLL reference frequency PLL lock time PLL jitter TEST CONDITIONS VCC MIN TYP 48 1.5 1000 MAX 7 3 2 UNIT mA MHz MHz ms ps Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP DVCC(PGM/ERASE) Program and erase supply voltage IPGM Average supply current from DVCC during program IERASE Average supply current from DVCC during erase IMERASE, IBANK Average supply current from DVCC during mass erase or bank erase tCPT Cumulative program time Program and erase endurance See (1) 1.8 3 104 105 tRetention tWord tBlock, 0 Data retention duration Word or byte program time Block program time for first byte or word TJ = 25°C 100 See (2) 64 See (2) 49 tBlock, 1–(N–1) Block program time for each additional byte or word, except for last byte or word See (2) 37 tBlock, N Block program time for last byte or word See (2) 55 tSeg Erase Erase time for segment, mass erase, and bank erase when available See (2) 23 fMCLK,MGR MCLK frequency in marginal read mode (FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1) 0 MAX UNIT 3.6 V 5 mA 2.5 mA 2 mA 16 ms cycles years 85 µs 65 µs 49 µs 73 µs 32 ms 1 MHz (1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming methods: individual word or byte write and block write modes. (2) These values are hardwired into the flash controller's state machine. JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP fSBW tSBW,Low tSBW, En Spy-Bi-Wire input frequency Spy-Bi-Wire low clock pulse duration Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge) (1) 2.2 V, 3 V 2.2 V, 3 V 2.2 V, 3 V 0 0.025 tSBW,Rst fTCK Spy-Bi-Wire return to normal operation time TCK input frequency (4-wire JTAG)(2) 15 2.2 V 0 3V 0 Rinternal Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 MAX UNIT 20 MHz 15 µs 1 µs 100 µs 5 MHz 10 MHz 80 kΩ (1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the first SBWTCK clock edge. (2) fTCK may be restricted to meet the timing requirements of the module selected. 80 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn INPUT/OUTPUT SCHEMATICS Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger ZHCS409C – JUNE 2010 – REVISED APRIL 2012 S32...S39 LCDS32...LCDS39 Pad Logic P1REN.x P1DIR.x P1OUT.x Module X OUT P1SEL.x P1IN.x Module X IN P1IRQ.x 0 Direction 1 0: Input 1: Output 0 1 EN D P1IE.x P1IFG.x EN Q Set P1SEL.x P1IES.x Interrupt Edge Select DVSS 0 DVCC 1 1 P1DS.x 0: Low drive 1: High drive Bus Keeper P1.0/TA0CLK/ACLK/S39 P1.1/TA0.0/S38 P1.2/TA0.1/S37 P1.3/TA0.2/S36 P1.4/TA0.3/S35 P1.5/TA0.4/S34 P1.6/TA0.1/S33 P1.7/TA0.2/S32 Copyright © 2010–2012, Texas Instruments Incorporated 81 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn PIN NAME (P1.x) P1.0/TA0CLK/ACLK/ S39 P1.1/TA0.0/S38 P1.2/TA0.1/S37 P1.3/TA0.2/S36 P1.4/TA0.3/S35 P1.5/TA0.4/S34 P1.6/TA0.1/S33 P1.7/TA0.2/S32 (1) X = Don't care Table 55. Port P1 (P1.0 to P1.7) Pin Functions x FUNCTION CONTROL BITS/SIGNALS(1) P1DIR.x P1SEL.x LCDS32...39 0 P1.0 (I/O) I: 0; O: 1 0 0 Timer TA0.TA0CLK 0 1 0 ACLK 1 1 0 S39 X X 1 1 P1.1 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI0A capture input 0 1 0 Timer TA0.0 output 1 1 0 S38 X X 1 2 P1.2 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI1A capture input 0 1 0 Timer TA0.1 output 1 1 0 S37 X X 1 3 P1.3 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI2A capture input 0 1 0 Timer TA0.2 output 1 1 0 S36 X X 1 4 P1.4 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI3A capture input 0 1 0 Timer TA0.3 output 1 1 0 S35 X X 1 5 P1.5 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI4A capture input 0 1 0 Timer TA0.4 output 1 1 0 S34 X X 1 6 P1.6 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI1B capture input 0 1 0 Timer TA0.1 output 1 1 0 S33 X X 1 7 P1.7 (I/O) I: 0; O: 1 0 0 Timer TA0.CCI2B capture input 0 1 0 Timer TA0.2 output 1 1 0 S32 X X 1 82 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger to LCD_B from LCD_B P2REN.x MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pad Logic P2DIR.x From Port Mapping P2OUT.x From Port Mapping P2SEL.x P2IN.x From Port Mapping To Port Mapping P2IRQ.x 0 Direction 1 0: Input 1: Output 0 1 EN D P2IE.x P2IFG.x EN Q Set P2SEL.x P2IES.x Interrupt Edge Select DVSS 0 DVCC 1 1 P2DS.x 0: Low drive 1: High drive P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6/R03 P2.7/P2MAP7/LCDREF/R13 Copyright © 2010–2012, Texas Instruments Incorporated 83 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn PIN NAME (P2.x) P2.0/P2MAP0 P2.1/P2MAP1 P2.2/P2MAP2 P2.3/P2MAP3 P2.4/P2MAP4 P2.5/P2MAP5 P2.6/P2MAP6/R03 P2.7/P2MAP7/ LCDREF/R13 (1) X = Don't care Table 56. Port P2 (P2.0 to P2.7) Pin Functions x FUNCTION CONTROL BITS/SIGNALS(1) P2DIR.x P2SEL.x P2MAPx 0 P2.0 (I/O) I: 0; O: 1 0 Mapped secondary digital function X 1 ≤ 19 1 P2.1 (I/O) I: 0; O: 1 0 Mapped secondary digital function X 1 ≤ 19 2 P2.2 (I/O) I: 0; O: 1 0 Mapped secondary digital function X 1 ≤ 19 3 P2.3 (I/O) I: 0; O: 1 0 Mapped secondary digital function X 1 ≤ 19 4 P2.4 (I/O) I: 0; O: 1 0 Mapped secondary digital function X 1 ≤ 19 5 P2.5 (I/O I: 0; O: 1 0 Mapped secondary digital function X 1 ≤ 19 6 P2.6 (I/O) I: 0; O: 1 0 Mapped secondary digital function X 1 ≤ 19 R03 X 1 = 31 7 P2.7 (I/O) I: 0; O: 1 0 Mapped secondary digital function X 1 ≤ 19 LCDREF/R13 X 1 = 31 84 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger S24...S31 LCDS24...LCDS31 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pad Logic P3REN.x P3DIR.x P3OUT.x Module X OUT P3SEL.x P3IN.x Module X IN P3IRQ.x 0 Direction 1 0: Input 1: Output 0 1 EN D P3IE.x P3IFG.x EN Q Set P3SEL.x P3IES.x Interrupt Edge Select DVSS 0 DVCC 1 1 P3DS.x 0: Low drive 1: High drive Bus Keeper P3.0/TA1CLK/CBOUT/S31 P3.1/TA1.0/S30 P3.2/TA1.1/S29 P3.3/TA1.2/S28 P3.4/TA2CLK/SMCLK/S27 P3.5/TA2.0/S26 P3.6/TA2.1/S25 P3.7/TA2.2/S24 Copyright © 2010–2012, Texas Instruments Incorporated 85 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn PIN NAME (P3.x) P3.0/TA1CLK/CBOUT/ S31 P3.1/TA1.0/S30 P3.2/TA1.1/S29 P3.3/TA1.2/S28 P3.4/TA2CLK/SMCLK/ S27 P3.5/TA2.0/S26 P3.6/TA2.1/S25 P3.7/TA2.2/S24 Table 57. Port P3 (P3.0 to P3.7) Pin Functions x FUNCTION CONTROL BITS/SIGNALS(1) P3DIR.x P3SEL.x LCDS24...31 0 P3.0 (I/O) I: 0; O: 1 0 0 Timer TA1.TA1CLK 0 1 0 CBOUT 1 1 0 S31 X X 1 1 P3.1 (I/O) I: 0; O: 1 0 0 Timer TA1.CCI0A capture input 0 1 0 Timer TA1.0 output 1 1 0 S30 X X 1 2 P3.2 (I/O) I: 0; O: 1 0 0 Timer TA1.CCI1A capture input 0 1 0 Timer TA1.1 output 1 1 0 S29 X X 1 3 P3.3 (I/O) I: 0; O: 1 0 0 Timer TA1.CCI2A capture input 0 1 0 Timer TA1.2 output 1 1 0 S28 X X 1 4 P3.4 (I/O) I: 0; O: 1 0 0 Timer TA2.TA2CLK 0 1 0 SMCLK 1 1 0 S27 X X 1 5 P3.5 (I/O) I: 0; O: 1 0 0 Timer TA2.CCI0A capture input 0 1 0 Timer TA2.0 output 1 1 0 S26 X X 1 6 P3.6 (I/O) I: 0; O: 1 0 0 Timer TA2.CCI1A capture input 0 1 0 Timer TA2.1 output 1 1 1 S25 X X 1 7 P3.7 (I/O) I: 0; O: 1 0 0 Timer TA2.CCI2A capture input 0 1 0 Timer TA2.2 output 1 1 0 S24 X X 1 (1) X = Don't care 86 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger S16...S23 LCDS16...LCDS23 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pad Logic P4REN.x P4DIR.x P4OUT.x Module X OUT P4SEL.x P4IN.x Module X IN P4IRQ.x 0 Direction 1 0: Input 1: Output 0 1 EN D P4IE.x P4IFG.x EN Q Set P4SEL.x P4IES.x Interrupt Edge Select DVSS 0 DVCC 1 1 P4DS.x 0: Low drive 1: High drive Bus Keeper P4.0/TB0.0/S23 P4.1/TB0.1/S22 P4.2/TB0.2/S21 P4.3/TB0.3/S20 P4.4/TB0.4/S19 P4.5/TB0.5/S18 P4.6/TB0.6/S17 P4.7/TB0OUTH/SVMOUT/S16 Copyright © 2010–2012, Texas Instruments Incorporated 87 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn PIN NAME (P4.x) P4.0/TB0.0/S23 P4.1/TB0.1/S22 P4.2/TB0.2/S21 P4.3/TB0.3/S20 P4.4/TB0.4/S19 P4.5/TB0.5/S18 P4.6/TB0.6/S17 P4.7/TB0OUTH/ SVMOUT/S16 Table 58. Port P4 (P4.0 to P4.7) Pin Functions x FUNCTION CONTROL BITS/SIGNALS(1) P4DIR.x P4SEL.x LCDS16...23 0 P4.0 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI0A capture input Timer TB0.0 output(2) 0 1 0 1 1 0 S23 X X 1 1 P4.1 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI1A capture input Timer TB0.1 output(2) 0 1 0 1 1 0 S22 X X 1 2 P4.2 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI2A capture input Timer TB0.2 output(2) 0 1 0 1 1 0 S21 X X 1 3 P4.3 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI3A capture input Timer TB0.3 output(2) 0 1 0 1 1 0 S20 X X 1 4 P4.4 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI4A capture input Timer TB0.4 output(2) 0 1 0 1 1 0 S19 X X 1 5 P4.5 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI5A capture input Timer TB0.5 output(2) 0 1 0 1 1 0 S18 X X 1 6 P4.6 (I/O) I: 0; O: 1 0 0 Timer TB0.CCI6A capture input Timer TB0.6 output(2) 0 1 0 1 1 0 S17 X X 1 7 P4.7 (I/O) I: 0; O: 1 0 0 Timer TB0.TB0OUTH 0 1 0 SVMOUT 1 1 0 S16 X X 1 (1) X = Don't care (2) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance. 88 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger To/From Reference MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pad Logic P5REN.x P5DIR.x P5OUT.x Module X OUT P5SEL.x P5IN.x Module X IN 0 1 0 1 EN D DVSS 0 DVCC 1 1 P5DS.x 0: Low drive 1: High drive Bus Keeper P5.0/VREF+/VeREF+ P5.1/VREF–/VeREF– PIN NAME (P5.x) P5.0/VREF+/VeREF+ P5.1/VREF–/VeREF– Table 59. Port P5 (P5.0 and P5.1) Pin Functions x 0 P5.0 (I/O)(2) VeREF+ (3) VREF+ (4) 1 P5.1 (I/O)(2) VeREF– (5) VREF– (6) FUNCTION CONTROL BITS/SIGNALS(1) P5DIR.x P5SEL.x REFOUT I: 0; O: 1 0 X X 1 0 X 1 1 I: 0; O: 1 0 X X 1 0 X 1 1 (1) X = Don't care (2) Default condition (3) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF+ and used as the reference for the ADC12_A, Comparator_B, or DAC12_A. (4) Setting the P5SEL.0 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF+ reference is available at the pin. (5) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. An external voltage can be applied to VeREF- and used as the reference for the ADC12_A, Comparator_B, or DAC12_A. (6) Setting the P5SEL.1 bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. The ADC12_A, VREF– reference is available at the pin. Copyright © 2010–2012, Texas Instruments Incorporated 89 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Port P5, P5.2 to P5.7, Input/Output With Schmitt Trigger S40...S42 LCDS40...LCDS42 www.ti.com.cn Pad Logic P5REN.x P5DIR.x P5OUT.x Module X OUT P5SEL.x P5IN.x Module X IN 0 1 0 1 EN D Direction 0: Input 1: Output DVSS 0 DVCC 1 1 P5DS.x 0: Low drive 1: High drive Bus Keeper P5.2/R23 P5.3/COM1/S42 P5.4/COM2/S41 P5.5/COM3/S40 P5.6/ADC12CLK/DMAE0 P5.7/RTCCLK PIN NAME (P5.x) P5.2/R23 P5.3/COM1/S42 P5.4/COM2/S41 P5.5/COM3/S40 P5.6/ADC12CLK/DMAE0 P5.7/RTCCLK (1) X = Don't care Table 60. Port P5 (P5.2 to P5.7) Pin Functions x FUNCTION CONTROL BITS/SIGNALS(1) P5DIR.x P5SEL.x LCDS40...42 2 P5.2 (I/O) I: 0; O: 1 0 na R23 X 1 na 3 P5.3 (I/O) I: 0; O: 1 0 0 COM1 X 1 X S42 X 0 1 4 P5.4 (I/O) I: 0; O: 1 0 0 COM2 X 1 X S41 X 0 1 5 P5.5 (I/O) I: 0; O: 1 0 0 COM3 X 1 X S40 X 0 1 6 P5.6 (I/O) I: 0; O: 1 0 na ADC12CLK 1 1 na DMAE0 0 1 na 7 P5.7 (I/O) I: 0; O: 1 0 na RTCCLK 1 1 na 90 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger To ADC12 INCHx = y Dvss From DAC12_A To Comparator_B From Comparator_B CBPD.x DAC12AMPx>0 DAC12OPS P6REN.x 0 1 2 0 if DAC12AMPx=0 1 if DAC12AMPx=1 2 if DAC12AMPx>1 P6DIR.x MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pad Logic DVSS 0 DVCC 1 1 P6OUT.x P6SEL.x P6IN.x P6DS.x 0: Low drive 1: High drive Bus Keeper P6.0/CB0/A0 P6.1/CB1/A1 P6.2/CB2/A2 P6.3/CB3/A3 P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1 Copyright © 2010–2012, Texas Instruments Incorporated 91 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn PIN NAME (P6.x) P6.0/CB0/A0 P6.1/CB1/A1 P6.2/CB2/A2 P6.3/CB3/A3 P6.4/CB4/A4 P6.5/CB5/A5 P6.6/CB6/A6/DAC0 P6.7/CB7/A7/DAC1 Table 61. Port P6 (P6.0 to P6.7) Pin Functions CONTROL BITS/SIGNALS(1) x FUNCTION P6DIR.x P6SEL.x CBPD.x DAC12OPS DAC12AMPx 0 P6.0 (I/O) I: 0; O: 1 0 0 n/a n/a CB0 A0 (2) (3) X X 1 n/a n/a X 1 X n/a n/a 1 P6.1 (I/O) I: 0; O: 1 0 0 n/a n/a CB1 A1(2) (3) X X 1 n/a n/a X 1 X n/a n/a 2 P6.2 (I/O) I: 0; O: 1 0 0 n/a n/a CB2 A2(2) (3) X X 1 n/a n/a X 1 X n/a n/a 3 P6.3 (I/O) I: 0; O: 1 0 0 n/a n/a CB3 A3(2) (3) X X 1 n/a n/a X 1 X n/a n/a 4 P6.4 (I/O) I: 0; O: 1 0 0 n/a n/a CB4 A4(2) (3) X X 1 n/a n/a X 1 X n/a n/a 5 P6.5 (I/O) I: 0; O: 1 0 0 n/a n/a CB5 A5 (4) (2) (3) X X 1 n/a n/a X 1 X n/a n/a 6 P6.6 (I/O) I: 0; O: 1 0 0 X 0 CB6 A6(2) (3) X X 1 X 0 X 1 X X 0 DAC0 X X X 0 >1 7 P6.7 (I/O) I: 0; O: 1 0 0 X 0 CB7 A7(2) (3) X X 1 X 0 X 1 X X 0 DAC1 X X X 0 >1 (1) X = Don't care (2) Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits. (4) X = Don't care 92 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn Port P7, P7.2, Input/Output With Schmitt Trigger To XT2 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pad Logic P7REN.2 P7DIR.2 0 1 P7OUT.2 P7SEL.2 P7IN.2 DVSS 0 DVCC 1 1 P7DS.2 0: Low drive 1: High drive Bus Keeper P7.2/XT2IN Copyright © 2010–2012, Texas Instruments Incorporated 93 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Port P7, P7.3, Input/Output With Schmitt Trigger To XT2 www.ti.com.cn Pad Logic P7REN.3 P7DIR.3 0 1 P7OUT.3 P7SEL.3 P7IN.3 DVSS 0 DVCC 1 1 P7DS.3 0: Low drive 1: High drive Bus Keeper P7.3/XT2OUT PIN NAME (P5.x) P7.2/XT2IN P7.3/XT2OUT Table 62. Port P7 (P7.2 and P7.3) Pin Functions x FUNCTION P7DIR.x CONTROL BITS/SIGNALS(1) P7SEL.2 P7SEL.3 2 P7.2 (I/O) XT2IN crystal mode(2) XT2IN bypass mode(2) I: 0; O: 1 0 X X 1 X X 1 X 3 P7.3 (I/O) XT2OUT crystal mode(3) P7.3 (I/O)(3) I: 0; O: 1 0 X X 1 X X 1 X XT2BYPASS X 0 1 X 0 1 (1) X = Don't care (2) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal mode or bypass mode. (3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as general-purpose I/O. 94 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger Dvss From DAC12_A To ADC12 INCHx = y 0 1 2 0 if DAC12AMPx=0 1 if DAC12AMPx=1 2 if DAC12AMPx>1 To Comparator_B From Comparator_B CBPD.x DAC12AMPx>0 DAC12OPS P7REN.x P7DIR.x DVSS 0 DVCC 1 Pad Logic 1 P7OUT.x P7SEL.x P7IN.x P7DS.x 0: Low drive 1: High drive Bus Keeper P7.4/CB8/A12 P7.5/CB9/A13 P7.6/CB10/A14/DAC0 P7.7/CB11/A15/DAC1 Copyright © 2010–2012, Texas Instruments Incorporated 95 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn Table 63. Port P7 (P7.4 to P7.7) Pin Functions PIN NAME (P7.x) x FUNCTION P7DIR.x CONTROL BITS/SIGNALS(1) P7SEL.x CBPD.x DAC12OPS DAC12AMPx P7.4/CB8/A12 4 P7.4 (I/O) I: 0; O: 1 0 0 n/a n/a Comparator_B input CB8 X X 1 n/a n/a A12 (2) (3) X 1 X n/a n/a P7.5/CB9/A13 5 P7.5 (I/O) I: 0; O: 1 0 0 n/a n/a Comparator_B input CB9 X X 1 n/a n/a A13 (2) (3) X 1 X n/a n/a P7.6/CB10/A14/DAC0 6 P7.6 (I/O) I: 0; O: 1 0 0 X 0 Comparator_B input CB10 X X 1 X 0 A14 (2) (3) X 1 X X 0 DAC12_A output DAC0 X X X 1 >1 P7.7/CB11/A15/DAC1 7 P7.7 (I/O) I: 0; O: 1 0 0 X 0 Comparator_B input CB11 X X 1 X 0 A15 (2) (3) X 1 X X 0 DAC12_A output DAC1 X X X 1 >1 (1) X = Don't care (2) Setting the P7SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) The ADC12_A channel Ax is connected internally to AVSS if not selected via the respective INCHx bits. 96 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger S8...S15 LCDS8...LCDS15 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pad Logic P8REN.x P8DIR.x 0 From module 1 P8OUT.x Module X OUT P8SEL.x P8IN.x Module X IN 0 1 EN D Direction 0: Input 1: Output DVSS 0 DVCC 1 1 P8DS.x 0: Low drive 1: High drive Bus Keeper P8.0/TB0CLK/S15 P8.1/UCB1STE/UCA1CLK/S14 P8.2/UCA1TXD/UCA1SIMO/S13 P8.3/UCA1RXD/UCA1SOMI/S12 P8.4/UCB1CLK/UCA1STE/S11 P8.5/UCB1SIMO//UCB1SDA/S10 P8.6/UCB1SOMI/UCB1SCL/S9 P8.7/S8 Copyright © 2010–2012, Texas Instruments Incorporated 97 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 www.ti.com.cn PIN NAME (P9.x) P8.0/TB0CLK/S15 P8.1/UCB1STE/UCA1CLK/S14 P8.2/UCA1TXD/UCA1SIMO/S13 P8.3/UCA1RXD/UCA1SOMI/S12 P8.4/UCB1CLK/UCA1STE/S11 P8.5/UCB1SIMO/UCB1SDA/S10 P8.6/UCB1SOMI/UCB1SCL/S9 P8.7/S8 (1) X = Don't care Table 64. Port P8 (P8.0 to P8.7) Pin Functions x FUNCTION CONTROL BITS/SIGNALS(1) P8DIR.x P8SEL.x LCDS8...16 0 P8.0 (I/O) I: 0; O: 1 0 0 Timer TB0.TB0CLK clock input 0 1 0 S15 X X 1 1 P8.1 (I/O) I: 0; O: 1 0 0 UCB1STE/UCA1CLK X 1 0 S14 X X 1 2 P8.2 (I/O) I: 0; O: 1 0 0 UCA1TXD/UCA1SIMO X 1 0 S13 X X 1 3 P8.3 (I/O) I: 0; O: 1 0 0 UCA1RXD/UCA1SOMI X 1 0 S12 X X 1 4 P8.4 (I/O) I: 0; O: 1 0 0 UCB1CLK/UCA1STE X 1 0 S11 X X 1 5 P8.5 (I/O) I: 0; O: 1 0 0 UCB1SIMO/UCB1SDA X 1 0 S10 X X 1 6 P8.6 (I/O) I: 0; O: 1 0 0 UCB1SOMI/UCB1SCL X 1 0 S9 X X 1 7 P8.7 (I/O) I: 0; O: 1 0 0 S8 X X 1 98 Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger S0...S7 LCDS0...LCDS7 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Pad Logic P9REN.x P9DIR.x P9OUT.x P9IN.x Direction 0: Input 1: Output DVSS 0 DVCC 1 1 P9DS.x 0: Low drive 1: High drive Bus Keeper P9.0/S7 P9.1/S6 P9.2/S5 P9.3/S4 P9.4/S3 P9.5/S2 P9.6/S1 P9.7/S0 PIN NAME (P9.x) P9.0/S7 P9.1/S6 P9.2/S5 P9.3/S4 P9.4/S3 P9.5/S2 P9.6/S1 P9.7/S0 (1) X = Don't care Table 65. Port P9 (P9.0 to P9.7) Pin Functions x FUNCTION CONTROL BITS/SIGNALS(1) P9DIR.x P9SEL.x LCDS0...7 0 P9.0 (I/O) I: 0; O: 1 0 0 S7 X X 1 1 P9.1 (I/O) I: 0; O: 1 0 0 S6 X X 1 2 P9.2 (I/O) I: 0; O: 1 0 0 S5 X X 1 3 P9.3 (I/O) I: 0; O: 1 0 0 S4 X X 1 4 P9.4 (I/O) I: 0; O: 1 0 0 S3 X X 1 5 P9.5 (I/O) I: 0; O: 1 0 0 S2 X X 1 6 P9.6 (I/O) I: 0; O: 1 0 0 S1 X X 1 7 P9.7 (I/O) I: 0; O: 1 0 0 S0 X X 1 Copyright © 2010–2012, Texas Instruments Incorporated 99 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Port PU.0/DP, PU.1/DM, PUR USB Ports PUSEL PUOPE 0 USB output enable 1 PUOUT0 0 USB DP output 1 PUIN0 USB DP input PUIPE . PUIN1 USB DM input PUOUT1 0 USB DM output 1 PUREN PUSEL PURIN VUSB VSSU Pad Logic VUSB VSSU Pad Logic “1” www.ti.com.cn PU.0/ DP PU.1/ DM PUR PUSEL 0 0 0 0 0 1 100 Table 66. Port PU.0/DP, PU.1/DM Output Functions CONTROL BITS PUDIR PUOUT1 0 X 1 0 1 0 1 1 1 1 X X PUOUT0 X 0 1 0 1 X PIN NAME PU.1/DM PU.0/DP Hi-Z Hi-Z 0 0 0 1 1 0 1 1 DM DP FUNCTION Outputs off Outputs enabled Outputs enabled Outputs enabled Outputs enabled Direction set by USB module Table 67. Port PUR Input Functions CONTROL BITS PUSEL PUREN 0 0 FUNCTION Input disabled Pullup disabled Copyright © 2010–2012, Texas Instruments Incorporated www.ti.com.cn MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 67. Port PUR Input Functions (continued) CONTROL BITS PUSEL PUREN 0 1 1 0 1 1 FUNCTION Input disabled Pullup enabled Input enabled Pullup disabled Input enabled Pullup enabled Copyright © 2010–2012, Texas Instruments Incorporated 101 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Port J, J.0 JTAG pin TDO, Input/Output With Schmitt Trigger or Output PJREN.0 Pad Logic www.ti.com.cn PJDIR.0 0 DVCC 1 DVSS 0 DVCC 1 1 PJOUT.0 From JTAG From JTAG PJIN.0 0 1 EN D PJDS.0 0: Low drive 1: High drive PJ.0/TDO Port J, J.1 to J.3 JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output PJREN.x Pad Logic PJDIR.x DVSS PJOUT.x From JTAG From JTAG PJIN.x To JTAG 0 1 0 1 EN D DVSS 0 DVCC 1 1 PJDS.x 0: Low drive 1: High drive PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK 102 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn ZHCS409C – JUNE 2010 – REVISED APRIL 2012 Table 68. Port PJ (PJ.0 to PJ.3) Pin Functions PIN NAME (PJ.x) x FUNCTION PJ.0/TDO PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK 0 PJ.0 (I/O)(2) TDO (3) 1 PJ.1 (I/O)(2) TDI/TCLK(3) (4) 2 PJ.2 (I/O)(2) TMS(3) (4) 3 PJ.3 (I/O)(2) TCK (3) (4) (1) X = Don't care (2) Default condition (3) The pin direction is controlled by the JTAG module. (4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care. CONTROL BITS/ SIGNALS (1) PJDIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X Copyright © 2010–2012, Texas Instruments Incorporated 103 MSP430F663x ZHCS409C – JUNE 2010 – REVISED APRIL 2012 DEVICE DESCRIPTORS www.ti.com.cn Table 69 list the complete contents of the device descriptor tag-length-value (TLV) structure for each device type. Table 69. MSP430F663x Device Descriptor Table(1) Info Block Die Record ADC12 Calibration Description Info length CRC length CRC value Device ID Hardware revision Firmware revision Die Record Tag Die Record length Lot/Wafer ID Die X position Die Y position Test results Address Size bytes 01A00h 1 01A01h 1 01A02h 2 01A04h 2 01A06h 1 01A07h 1 01A08h 1 01A09h 1 01A0Ah 4 01A0Eh 2 01A10h 2 01A12h 2 F6638 Value 06h 06h per unit 801Ch per unit per unit 08h 0Ah per unit per unit per unit per unit ADC12 Calibration Tag 01A14h 1 11h ADC12 Calibration length 01A15h 1 10h ADC Gain Factor 01A16h 2 per unit ADC Offset 01A18h 2 per unit ADC 1.5-V Reference Temp. Sensor 30°C 01A1Ah 2 per unit ADC 1.5-V Reference Temp. Sensor 85°C 01A1Ch 2 per unit ADC 2.0-V Reference Temp. Sensor 30°C 01A1Eh 2 per unit ADC 2.0-V Reference Temp. Sensor 85°C 01A20h 2 per unit ADC 2.5-V Reference Temp. Sensor 30°C 01A22h 2 per unit ADC 2.5-V Reference Temp. Sensor 85°C 01A24h 2 per unit F6637 Value 06h 06h per unit 801Ah per unit per unit 08h 0Ah per unit per unit per unit per unit 11h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6636 Value 06h 06h per unit 8018h per unit per unit 08h 0Ah per unit per unit per unit per unit 11h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6635 Value 06h 06h per unit 8016h per unit per unit 08h 0Ah per unit per unit per unit per unit 11h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6634 Value 06h 06h per unit 804Eh per unit per unit 08h 0Ah per unit per unit per unit per unit 11h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6633 Value 06h 06h per unit 804Ch per unit per unit 08h 0Ah per unit per unit per unit per unit 11h 10h per unit per unit per unit per unit per unit per unit per unit per unit F6632 Value 06h 06h per unit 804Ah per unit per unit 08h 0Ah per unit per unit per unit per unit 05h 10h N/A N/A N/A N/A N/A N/A N/A N/A F6631 Value 06h 06h per unit 8048h per unit per unit 08h 0Ah per unit per unit per unit per unit 05h 10h N/A N/A N/A N/A N/A N/A N/A N/A F6630 Value 06h 06h per unit 8046h per unit per unit 08h 0Ah per unit per unit per unit per unit 05h 10h N/A N/A N/A N/A N/A N/A N/A N/A (1) NA = Not applicable 104 Copyright © 2010–2012, Texas Instruments Incorporated MSP430F663x www.ti.com.cn REVISION HISTORY ZHCS409C – JUNE 2010 – REVISED APRIL 2012 REVISION SLAS566 SLAS566A SLAS566B SLAS566C COMMENTS Product Preview release Updated Product Preview including electrical specifications Production Data release Changed description of ACLK and PUR in Terminal Functions. Changed typos to Interrupt Flag names on Timer TA2 rows in Table 6. Changed SYSRSTIV, System Reset offset 1Ch to Reserved in Table 14. Corrected names of SVMLVLRIFG and SVMHVLRIFG bits in Table 14. Added note regarding evaluation of PUR in USB BSL. Changed notes on REF, Built-In Reference. Changed tSENSOR(sample) MIN to 100 µs in 12-Bit ADC, Temperature Sensor and Built-In VMID. Changed note (2) in 12-Bit ADC, Temperature Sensor and Built-In VMID. Editorial changes throughout. Copyright © 2010–2012, Texas Instruments Incorporated 105 www.ti.com PACKAGING INFORMATION Orderable Device MSP430F6630IPZ MSP430F6630IPZR MSP430F6630IZQWR MSP430F6630ZQWT MSP430F6631IPZ MSP430F6631IPZR MSP430F6631IZQWR MSP430F6631ZQWT MSP430F6632IPZ MSP430F6632IPZR MSP430F6632IZQWR MSP430F6632ZQWT MSP430F6633IPZ MSP430F6633IPZR PACKAGE OPTION ADDENDUM 29-Dec-2012 Status Package Type Package Pins Package Qty (1) Drawing Eco Plan Lead/Ball Finish MSL Peak Temp (2) (3) ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE BGA ZQW 113 MICROSTAR JUNIOR 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ACTIVE BGA ZQW 100 MICROSTAR JUNIOR TBD Call TI Call TI ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE BGA ZQW 113 MICROSTAR JUNIOR 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ACTIVE BGA ZQW 100 MICROSTAR JUNIOR TBD Call TI Call TI ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE BGA ZQW 113 MICROSTAR JUNIOR 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ACTIVE BGA ZQW 100 MICROSTAR JUNIOR TBD Call TI Call TI ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) Samples (Requires Login) Addendum-Page 1 www.ti.com Orderable Device MSP430F6633IZQWR MSP430F6633ZQWT MSP430F6634IPZ MSP430F6634IPZR MSP430F6634IZQWR MSP430F6634ZQWT MSP430F6635IPZ MSP430F6635IPZR MSP430F6635IZQWR MSP430F6635ZQWT MSP430F6636IPZ MSP430F6636IPZR MSP430F6636IZQWR MSP430F6636ZQWT PACKAGE OPTION ADDENDUM 29-Dec-2012 Status Package Type Package Pins Package Qty (1) Drawing Eco Plan Lead/Ball Finish MSL Peak Temp (2) (3) ACTIVE BGA ZQW 113 MICROSTAR JUNIOR 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ACTIVE BGA ZQW 100 MICROSTAR JUNIOR TBD Call TI Call TI ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE BGA ZQW 113 MICROSTAR JUNIOR 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ACTIVE BGA ZQW 100 MICROSTAR JUNIOR TBD Call TI Call TI ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE BGA ZQW 113 MICROSTAR JUNIOR 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ACTIVE BGA ZQW 100 MICROSTAR JUNIOR TBD Call TI Call TI ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE BGA ZQW 113 MICROSTAR JUNIOR 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ACTIVE BGA ZQW 100 MICROSTAR JUNIOR TBD Call TI Call TI Samples (Requires Login) Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 29-Dec-2012 Orderable Device MSP430F6637IPZ MSP430F6637IPZR MSP430F6637IZQWR MSP430F6637IZQWT MSP430F6638CY MSP430F6638CYS MSP430F6638IPZ MSP430F6638IPZR MSP430F6638IZQWR MSP430F6638IZQWT Status Package Type Package Pins Package Qty (1) Drawing Eco Plan Lead/Ball Finish MSL Peak Temp (2) (3) ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE BGA ZQW 113 MICROSTAR JUNIOR 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ACTIVE BGA ZQW 113 250 Green (RoHS SNAGCU Level-3-260C-168 HR MICROSTAR & no Sb/Br) JUNIOR ACTIVE Green (RoHS & no Sb/Br) Call TI N / A for Pkg Type ACTIVE WAFERSALE YS 0 1 TBD Call TI Call TI ACTIVE LQFP PZ 100 90 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE LQFP PZ 100 1000 Green (RoHS CU NIPDAU Level-3-260C-168 HR & no Sb/Br) ACTIVE BGA ZQW 113 MICROSTAR JUNIOR 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR ACTIVE BGA ZQW 113 250 Green (RoHS SNAGCU Level-3-260C-168 HR MICROSTAR & no Sb/Br) JUNIOR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Samples (Requires Login) (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 29-Dec-2012 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 4 www.ti.com TAPE AND REEL INFORMATION PACKAGE MATERIALS INFORMATION 29-Dec-2012 *All dimensions are nominal Device Package Package Pins Type Drawing MSP430F6632IPZR LQFP PZ 100 MSP430F6633IPZR LQFP PZ 100 MSP430F6633IZQWR BGA MI ZQW 113 CROSTA R JUNI OR MSP430F6634IZQWR BGA MI ZQW 113 CROSTA R JUNI OR MSP430F6635IPZR LQFP PZ 100 MSP430F6635IZQWR BGA MI ZQW 113 CROSTA R JUNI OR MSP430F6636IZQWR BGA MI ZQW 113 CROSTA R JUNI OR MSP430F6637IZQWT BGA MI ZQW 113 CROSTA R JUNI SPQ 1000 1000 2500 Reel Reel A0 B0 K0 P1 W Pin1 Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 Pack Materials-Page 1 www.ti.com PACKAGE MATERIALS INFORMATION 29-Dec-2012 Device Package Package Pins Type Drawing OR MSP430F6638IPZR LQFP PZ 100 MSP430F6638IZQWR BGA MI ZQW 113 CROSTA R JUNI OR MSP430F6638IZQWT BGA MI ZQW 113 CROSTA R JUNI OR SPQ Reel Reel A0 B0 K0 P1 W Pin1 Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) 1000 330.0 24.4 17.0 17.0 2.1 20.0 24.0 Q2 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1 *All dimensions are nominal Device Package Type Package Drawing Pins MSP430F6632IPZR LQFP PZ 100 MSP430F6633IPZR LQFP PZ 100 MSP430F6633IZQWR BGA MICROSTAR ZQW 113 JUNIOR MSP430F6634IZQWR BGA MICROSTAR ZQW 113 JUNIOR MSP430F6635IPZR LQFP PZ 100 MSP430F6635IZQWR BGA MICROSTAR ZQW 113 JUNIOR SPQ 1000 1000 2500 2500 1000 2500 Length (mm) 367.0 367.0 336.6 Width (mm) 367.0 367.0 336.6 Height (mm) 45.0 45.0 28.6 336.6 336.6 28.6 367.0 367.0 45.0 336.6 336.6 28.6 Pack Materials-Page 2 www.ti.com PACKAGE MATERIALS INFORMATION 29-Dec-2012 Device MSP430F6636IZQWR MSP430F6637IZQWT MSP430F6638IPZR MSP430F6638IZQWR MSP430F6638IZQWT Package Type Package Drawing Pins BGA MICROSTAR ZQW 113 JUNIOR BGA MICROSTAR ZQW 113 JUNIOR LQFP PZ 100 BGA MICROSTAR ZQW 113 JUNIOR BGA MICROSTAR ZQW 113 JUNIOR SPQ 2500 Length (mm) Width (mm) Height (mm) 336.6 336.6 28.6 250 336.6 336.6 28.6 1000 367.0 367.0 45.0 2500 336.6 336.6 28.6 250 336.6 336.6 28.6 Pack Materials-Page 3 PZ (S-PQFP-G100) 0,50 75 76 MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PLASTIC QUAD FLATPACK 0,27 0,17 51 0,08 M 50 100 1 1,45 1,35 1,60 MAX 25 12,00 TYP 14,20 13,80 SQ 16,20 15,80 SQ NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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