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s3c6410裸机程序。tiny6410开发板

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    工具是RVDS2.2 开发板是Tiny6410,本人亲测可用的。启动文件,和主函数可以自己写,关键是 mlcd.c文件! 启动文件中的 s3c6410.inc image_cfg.inc 和MemParam_mDDR.inc 比较大放在了最后面。 请自建一人main.c 文件,并在 Extern LCD_Init(); Extern LCD_DrewPixel(int x,int y,int color); void main(){ LCD_Init(); LCD_DrawPixel(100,100, 0x00);}就可以打一个点了。源程序来自网络! /************************************************************************ **************启动文件strartup.s 跳到void mian函数****************************** ***********/ INCLUDE s3c6410.inc INCLUDE image_cfg.inc INCLUDE MemParam_mDDR.inc IMPORT main ; C entrypoint for Steppingstone loader. ; AREA |.astart|,ALIGN=2,CODE ;AreaName SETS "|.astart|" ;------------------------------------------------------------------------------ ; ; Memory Start Entry ; ; 内存里直接启动时入口 ; ;------------------------------------------------------------------------------ PRESERVE8 AREA |C$$code|, CODE, READONLY global MemStart MemStart ;------------------------------------ ; Disable WatchDog Timer ;------------------------------------ ldr r0, =WTCON ldr r1, =0x0 str r1, [r0] ;------------------------------------ ; Enable VIC Port @Andrew Huang ;------------------------------------ mrc p15,0,r0,c1,c0,0 orr r0,r0,#(1<<24) mcr p15,0,r0,c1,c0,0 b main DCB "ABCDabcd" ; END /************************************************************************************mlcd.c 文件********调用LCD_Init();就可完成初始化,调用LCD_DrawPixel就可以在自定义的x,y 打一个color 颜色的点************/ //mlcd.c文件 #include "s3c6410_addr.h" #include "utils.h" #include "mlcd.h" #define LCD_YSIZE (272) #define LCD_XSIZE (480) #ifdef LCD volatile unsigned int LCD_BUFFER[272][480]; unsigned int addr = (unsigned int)LCD_BUFFER; void LCD_DrawPixel(unsigned int x, unsigned int y, unsigned int color) { if((x<480) && (y<272)) LCD_BUFFER[y][x] = color; } void LCD_Init(void) { //(1)将J管脚的第二功能设为LCD VD、HSYNC 、VSYNC 、VDEN 、VCLK,将I管脚的第二功能设为LCD VD //init gpio func for LCD + rGPECON = 0x00011111; //GPE0: for LCD Backlight ON-OFF. GPE1~4 is GPIO. rGPEDAT = 0x00000001; //Backlight ON (some LCD(3.5) need it ,but NEC 4.3 not) rGPEPUD = 0x00000000; //gpio->GPECONSLP = 0x00000000; //gpio->GPEPUDSLP = 0x00000000; rGPFCON = 0x96AAAAAA; //PWM1: for Backlight Dimming. GPF13 is USB_PWR. GPF0~12 is CAM I/F. // PWM0 Control Buzzer,but now we config it as OUTPUT!!! rGPFDAT = 0x00002000; //USB_PWR ON . Buzzer OFF . rGPFPUD = 0x00000000; //gpio->GPFCONSLP = 0x00000000; //gpio->GPFPUDSLP = 0x00000000; rGPICON = 0xAAAAAAAA; rGPIPUD = 0x00000000; //gpio->GPICONSLP = 0x00000000; //gpio->GPIPUDSLP = 0x00000000; rGPJCON = 0x00AAAAAA; rGPJPUD = 0x00000000; //gpio->GPJCONSLP = 0x00000000; //gpio->GPJPUDSLP = 0x00000000; //init gpio func for LCD - //LCD rSPCON = rSPCON & ~(0x3) | 1; rMIFPCON &= ~(1<<3); rVIDCON0 = (0<<29)|(0<<26)|(0<<17)|(0<<16)|(9<<6)|(0<<5)|(1<<4)|(0<<2); //(0<<29)|(0<<26)|(0<<17)|(1<<16)|(5<<6)|(0<<5)|(1<<4)|(0<<2); rVIDCON1 = 1<<7;//1=RGB 类型LCD 设备在VCLK 上升沿得到视频数据 //+设置屏的时序 rVIDTCON0 = (0x03<<16)|(0x02<<8)|(0x02<<0); rVIDTCON1 = (0x2d<<16)|(0x04<<8)|(0x06<<0); rVIDTCON2 = (271<<11)|(479<<0); //- rWINCON0 = 11<<2;//窗口格式控制 11 24显示 8 16位 //+VIDOSDxA ,VIDOSDxB:窗口位置控制 rVIDOSD0A = (0<<11)|(0); rVIDOSD0B = (479<<11)|(271<<0); rVIDOSD0C = (((480*272)&0xFFFFFF)<<0); //- rVIDW00ADD0B0 = ((addr>>24)<<24)|(addr&0xffffff); rVIDW00ADD1B0 = (addr&0xffffff + 480*272); rVIDW00ADD2 = (0<<13)|(480); rDITHMODE=(1<<5)|(1<<3)|(1<<1); //+开显示 rVIDCON0 |= 3; rWINCON0 |= 1; //- } //***************************************** //s3c6410.inc文件 //****************************************** ; ; Copyright (c) Microsoft Corporation. All rights reserved. ; ; ; Use of this source code is subject to the terms of the Microsoft end-user ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT. ; If you did not accept the terms of the EULA, you are not authorized to use ; this source code. For a copy of the EULA, please see the LICENSE.RTF on your ; install media. ; ;------------------------------------------------------------------------------- ; ; Header: s3c6410.inc ; ; This header file defines only those registers required by the startup ; code. All addresses are based off the physical addresses (PA) defined ; in s3c6410_base_reg.h (s3c6410_base_reg.inc). ; ;------------------------------------------------------------------------------- ;------------------------------------------------- ; CPU Revision Definition ( S3C6410 Has EVT0, EVT1 ;------------------------------------------------- EVT0 EQU (36410100) EVT1 EQU (36410101) ;------------------------------------------------- ; System Clock Definition ;------------------------------------------------- CLK_66_5MHZ EQU 66500000 CLK_133MHZ EQU 133000000 CLK_150MHZ EQU 150000000 CLK_200MHZ EQU 200000000 CLK_266MHZ EQU 266000000 CLK_300MHZ EQU 300000000 CLK_400MHZ EQU 400000000 CLK_450MHZ EQU 450000000 CLK_532MHZ EQU 532000000 CLK_600MHZ EQU 600000000 CLK_666MHZ EQU 666000000 ; Sync CLK_667MHZ EQU 667000000 ; ASync CLK_798MHZ EQU 798000000 ; Sync CLK_800MHZ EQU 800000000 ; ASync CLK_900MHZ EQU 900000000 CLK_1332MHZ EQU 1332000000 ECLK_96MHZ EQU 96000000 ECLK_84MHZ EQU 84666667 ; for IIS 44.1 KHz ECLK_92MHZ EQU 92160000 ; for IIS 48 KHz GBLA CPU_REVISION GBLA TARGET_ARM_CLK GBLA S3C6410_ECLK GBLL CHANGE_PLL_CLKDIV_ON_EBOOT GBLL CHANGE_PLL_CLKDIV_ON_KERNEL GBLL CLEAR_DRAM_ON_EBOOT GBLL CLEAR_DRAM_ON_KERNEL CHANGE_PLL_CLKDIV_ON_EBOOT SETL {TRUE} CHANGE_PLL_CLKDIV_ON_KERNEL SETL {TRUE} CLEAR_DRAM_ON_EBOOT SETL {FALSE} CLEAR_DRAM_ON_KERNEL SETL {FALSE} ;------------------------------------------------------------------------------ ; Define: SYNCMODE ; ; SYNCMODE used to set cpu operation mode to syncronous mode or asyncronous mode ;------------------------------------------------------------------------------ GBLL SYNCMODE SYNCMODE SETL {TRUE} ;------------------------------------------------- ; Change CPU Revision (S3C6410 HAS EVT0, EVT1) ;------------------------------------------------- CPU_REVISION SETA EVT1 ;------------------------------------------------- ;------------------------------------------------- ; Change TARGET_ARM_CLK definition for StartUp code ;------------------------------------------------- ;TARGET_ARM_CLK SETA CLK_66_5MHZ ; Sync 66.5:66.5:66.5 ;TARGET_ARM_CLK SETA CLK_133MHZ ; Sync 133:133:66.5 ;TARGET_ARM_CLK SETA CLK_266MHZ ; Sync 266:133:66.5 ;TARGET_ARM_CLK SETA CLK_400MHZ ; Sync 400:100:50 ;TARGET_ARM_CLK SETA CLK_450MHZ ; Sync 450:150:65 TARGET_ARM_CLK SETA CLK_532MHZ ; Sync 532:133:66.5 ;TARGET_ARM_CLK SETA CLK_600MHZ ; Sync 600:150:75 ;TARGET_ARM_CLK SETA CLK_666MHZ ; Sync 666:133.4:66.5 ;TARGET_ARM_CLK SETA CLK_798MHZ ; Sync 798:133:66.5 ;TARGET_ARM_CLK SETA CLK_800MHZ ; Sync 800:133.33:66.66 ;TARGET_ARM_CLK SETA CLK_900MHZ ; Sync 900:150:75 FIN EQU 12000000 ;------------------------------------------------- ; Include the base register definitions ; Fout = MDIV*Fin/(PDIV*2^SDIV) ; Fvco = MDIV*Fin/PDIV INCLUDE s3c6410_base_regs.inc ;------------------------------------------------- ; Change S3C6410_ECLK definition for EPLL Fout ;------------------------------------------------- ;S3C6410_ECLK SETA ECLK_96MHZ S3C6410_ECLK SETA ECLK_84MHZ ;S3C6410_ECLK SETA ECLK_92MHZ ;------------------------------------------------- ;------------------------------------------------- ; Set Clock Source : MPLL, APLL ;------------------------------------------------- ; MPLL Setting ; 400:100:25 (Asyncronous Mode) [ (TARGET_ARM_CLK = CLK_400MHZ) ;Fvco=800MHz, Fout=200MHz MPLL_MVAL EQU (400) MPLL_PVAL EQU (6) MPLL_SVAL EQU (2) | ; Other Clock use 266Mhz for mDDR in Asynchronous mode ;Fvco=1064MHz, Fout=266MHz MPLL_MVAL EQU (266) MPLL_PVAL EQU (3) MPLL_SVAL EQU (2) ] MPLL_CLK EQU (((FIN>>MPLL_SVAL)/MPLL_PVAL)*MPLL_MVAL) ; MPLL Clock ; APLL Setting [ (TARGET_ARM_CLK = CLK_400MHZ) ;Fvco=800MHz, Fout=400MHz APLL_MVAL EQU (400) APLL_PVAL EQU (6) APLL_SVAL EQU (1) ] [ (TARGET_ARM_CLK = CLK_532MHZ):LOR:(TARGET_ARM_CLK = CLK_266MHZ):LOR:(TARGET_ARM_CLK = CLK_133MHZ):LOR:(TARGET_ARM_CLK = CLK_66_5MHZ) ;Fvco=1064MHz, Fout=532MHz APLL_MVAL EQU (266) APLL_PVAL EQU (3) APLL_SVAL EQU (1) ] [ (TARGET_ARM_CLK = CLK_600MHZ):LAND:(SYNCMODE) ;Fvco=1200MHz, Fout=600MHz APLL_MVAL EQU (300) APLL_PVAL EQU (3) APLL_SVAL EQU (1) ] [ (TARGET_ARM_CLK = CLK_666MHZ) [ (SYNCMODE):LAND:(CPU_REVISION = EVT1) ;Fvco=1332MHz, Fout=1332MHz APLL_MVAL EQU (333) APLL_PVAL EQU (3) APLL_SVAL EQU (0) | ;Fvco=1332MHz, Fout=666MHz APLL_MVAL EQU (333) APLL_PVAL EQU (3) APLL_SVAL EQU (1) ] ] [ (TARGET_ARM_CLK = CLK_798MHZ):LAND:(SYNCMODE) ;Fvco=1596MHz, Fout=798MHz APLL_MVAL EQU (399) APLL_PVAL EQU (3) APLL_SVAL EQU (1) ] [ (TARGET_ARM_CLK = CLK_800MHZ) ;Fvco=1600MHz, Fout=800MHz APLL_MVAL EQU (400) APLL_PVAL EQU (3) APLL_SVAL EQU (1) ] [ ((TARGET_ARM_CLK = CLK_900MHZ):LAND:(SYNCMODE)):LOR:(TARGET_ARM_CLK = CLK_450MHZ) ;Fvco=900MHz, Fout=900MHz APLL_MVAL EQU (225) APLL_PVAL EQU (3) APLL_SVAL EQU (0) ] APLL_CLK EQU (((FIN>>APLL_SVAL)/APLL_PVAL)*APLL_MVAL) ; APLL Clock ;------------------------------------------------- ; Set Clock Dividers ;------------------------------------------------- MPLL_DIV EQU (2-1) ; DOUT_MPLL = MPLL_Fout/2 [ (TARGET_ARM_CLK = CLK_450MHZ):LOR:(TARGET_ARM_CLK = CLK_666MHZ):LOR:(TARGET_ARM_CLK = CLK_266MHZ) APLL_DIV EQU (2-1) ; ARM_CLK = APLL_CLK/2 | [ (TARGET_ARM_CLK = CLK_133MHZ) APLL_DIV EQU (4-1) ; ARM_CLK = APLL_CLK/4 | [ (TARGET_ARM_CLK = CLK_66_5MHZ) APLL_DIV EQU (8-1) ; ARM_CLK = APLL_CLK/8 | APLL_DIV EQU (1-1) ; ARM_CLK = APLL_CLK ] ] ] HCLK_DIV EQU (2-1) ; AHB_CLK = HCLKx2/2 [ (TARGET_ARM_CLK = CLK_66_5MHZ) PCLK_DIV EQU (2-1) ; PCLK = HCLKx2/2 | PCLK_DIV EQU (4-1) ; PCLK = HCLKx2/4 ] [ (SYNCMODE) ; Use APLL as Memory Clock Source [ (TARGET_ARM_CLK = CLK_532MHZ):LOR:(TARGET_ARM_CLK = CLK_600MHZ):LOR:(TARGET_ARM_CLK = CLK_266MHZ):LOR:(TARGET_ARM_CLK = CLK_133MHZ) ; ARM:AHB:APB = 4:2:1, HCLKx2 = APLL_CLK/2 HCLKx2_DIV EQU (2-1) ; HCLKx2 = APLL_CLK/2 ] [ (TARGET_ARM_CLK = CLK_666MHZ):LAND:(CPU_REVISION = EVT1) ; This setting requires enabling MISC_CON[19] HCLKx2_DIV EQU (5-1) ; HCLKx2 = APLL_CLK/5 = 266.4MHz(Hard wired-PreDivider on EVT1) ] [ (TARGET_ARM_CLK = CLK_798MHZ):LOR:(TARGET_ARM_CLK = CLK_900MHZ):LOR:(TARGET_ARM_CLK = CLK_450MHZ):LOR:(TARGET_ARM_CLK = CLK_800MHZ) ; ARM:AHB:APB = 12:2:1, HCLKx2 = APLL_CLK/3 HCLKx2_DIV EQU (3-1) ; HCLKx2 = APLL_CLK/3 ] [ (TARGET_ARM_CLK = CLK_66_5MHZ) HCLKx2_DIV EQU (4-1) ; HCLKx2 = APLL_CLK/4 ] | ; Use MPLL as Memory Clock Source [ (TARGET_ARM_CLK = CLK_400MHZ):LOR:(TARGET_ARM_CLK = CLK_532MHZ):LOR:(TARGET_ARM_CLK = CLK_666MHZ) ; ARM:AHB:APB = 4:(2:1), HCLKx2 = MPLL HCLKx2_DIV EQU (1-1) ; HCLKx2 = MPLL_CLK ] ] ; (SYNCMODE) ARM_CLK EQU (APLL_CLK/(APLL_DIV+1)) [ (SYNCMODE) HCLK EQU (APLL_CLK/(HCLKx2_DIV+1)/(HCLK_DIV+1)) | HCLK EQU (MPLL_CLK/(HCLKx2_DIV+1)/(HCLK_DIV+1)) ] ; EPLL Fout 96 MHz [ S3C6410_ECLK = ECLK_96MHZ ;Fout=96MHz EPLL_MVAL EQU (32) EPLL_PVAL EQU (1) EPLL_SVAL EQU (2) EPLL_KVAL EQU (0) ] ; 96 MHz ; EPLL Fout 84.666667 MHz [ S3C6410_ECLK = ECLK_84MHZ ;Fout=84.67MHz EPLL_MVAL EQU (254) EPLL_PVAL EQU (9) EPLL_SVAL EQU (2) EPLL_KVAL EQU (0) ] ; 84.666667 MHz ; EPLL Fout 92,160,000 Hz [ S3C6410_ECLK = ECLK_92MHZ ;Fout=92.16MHz EPLL_MVAL EQU (192) EPLL_PVAL EQU (25) EPLL_SVAL EQU (0) EPLL_KVAL EQU (0) ] ; 92.16 MHz ;--------------------------- ; CPSR Mode Bit Definition ;--------------------------- Mode_USR EQU (0x10) Mode_FIQ EQU (0x11) Mode_IRQ EQU (0x12) Mode_SVC EQU (0x13) Mode_ABT EQU (0x17) Mode_UND EQU (0x1B) Mode_SYS EQU (0x1F) Mode_MASK EQU (0x1F) NOINT EQU (0xC0) I_Bit EQU (0x80) F_Bit EQU (0x40) ;--------------------------- ; CP15 Mode Bit Definition ;--------------------------- R1_iA EQU (1<<31) R1_nF EQU (1<<30) R1_VE EQU (1<<24) R1_I EQU (1<<12) R1_BP EQU (1<<11) ; Z bit R1_C EQU (1<<2) R1_A EQU (1<<1) R1_M EQU (1<<0) ;--------------------------- ; Miscellaneous defines ;--------------------------- WORD_SIZE EQU (4) DW8 EQU (0x0) DW16 EQU (0x1) DW32 EQU (0x2) WAIT EQU (0x1<<2) UBLB EQU (0x1<<3) ;--------------------------- ; ; SFR Address ; ;--------------------------- ;--------------------------- ; SysCon ;--------------------------- APLL_LOCK EQU (0x7e00f000) MPLL_LOCK EQU (0x7e00f004) APLL_CON EQU (0x7e00f00c) MPLL_CON EQU (0x7e00f010) EPLL_CON0 EQU (0x7e00f014) EPLL_CON1 EQU (0x7e00f018) CLK_SRC EQU (0x7e00f01c) CLK_DIV0 EQU (0x7e00f020) CLK_OUT EQU (0x7e00f02c) MEM_SYS_CFG EQU (0x7e00f120) OTHERS EQU (0x7e00f900) RST_STAT EQU (0x7E00F904) INFORM0 EQU (0x7E00FA00) INFORM1 EQU (0x7E00FA04) INFORM2 EQU (0x7E00FA08) INFORM3 EQU (0x7E00FA0C) vPWR_CFG EQU (0xB2A0F804) vSLEEP_CFG EQU (0xB2A0F818) vOSC_STABLE EQU (0xB2A0F824) vPWR_STABLE EQU (0xB2A0F828) vRST_STAT EQU (0xB2A0F904) vINFORM0 EQU (0xB2A0FA00) vINFORM1 EQU (0xB2A0FA04) vINFORM2 EQU (0xB2A0FA08) vINFORM3 EQU (0xB2A0FA0C) ;--------------------------- ; GPIO ;--------------------------- GPACON EQU (S3C6410_BASE_REG_PA_GPIO + 0x000) ;GPHCON0 EQU (S3C6410_BASE_REG_PA_IOPORT + 0x0E0) ;GPHCON1 EQU (S3C6410_BASE_REG_PA_IOPORT + 0x0E4) ;GPHDAT EQU (S3C6410_BASE_REG_PA_IOPORT + 0x0E8) ;GPHPUD EQU (S3C6410_BASE_REG_PA_IOPORT + 0x0EC) ;GPH_OneND EQU 0x2 GPNCON EQU (S3C6410_BASE_REG_PA_GPIO + 0x830) GPNDAT EQU (S3C6410_BASE_REG_PA_GPIO + 0x834) GPNPUD EQU (S3C6410_BASE_REG_PA_GPIO + 0x838) MEM1DRVCON EQU (S3C6410_BASE_REG_PA_GPIO + 0x1D4) ;// 0x7F000000 -> 0x92B00000 ;vGPHCON0 EQU (0xB2B08000 + 0x0E0) ;vGPHCON1 EQU (0xB2B08000 + 0x0E4) ;vGPHDAT EQU (0xB2B08000 + 0x0E8) ;vGPHPUD EQU (0xB2B08000 + 0x0EC) vGPNCON EQU (0xB2B08000 + 0x830) vGPNDAT EQU (0xB2B08000 + 0x834) vGPNPUD EQU (0xB2B08000 + 0x838) ;vGPNCON EQU (0xB2B08830) vEINT0CON0 EQU (0xB2B08900) ;--------------------------- ; VIC ;--------------------------- VIC0INTENCLEAR EQU (S3C6410_BASE_REG_PA_VIC0 + 0x14) VIC1INTENCLEAR EQU (S3C6410_BASE_REG_PA_VIC1 + 0x14) vVIC0INTENABLE EQU (0xB0600010) ; VIC0 vVIC0INTENCLEAR EQU (0xB0600014) ; VIC0 vVIC1INTENABLE EQU (0xB0700010) ; VIC1 vVIC1INTENCLEAR EQU (0xB0700014) ; VIC1 NFDATA EQU 0x70200010 ; NAND Flash data register ;----------------------------------- ; Watch Dog Timer ;----------------------------------- WTCON EQU (0x7e004000) ;================= ; SMC ;================= SMBIDCYR0 EQU 0x70000000 SMBWSTRDR0 EQU 0x70000004 SMBWSTWRR0 EQU 0x70000008 SMBWSTOENR0 EQU 0x7000000c SMBWSTWENR0 EQU 0x70000010 SMBCR0 EQU 0x70000014 SMBSR0 EQU 0x70000018 SMBWSTBRDR0 EQU 0x7000001c SMBIDCYR1 EQU 0x70000020 SMBWSTRDR1 EQU 0x70000024 SMBWSTWRR1 EQU 0x70000028 SMBWSTOENR1 EQU 0x7000002c SMBWSTWENR1 EQU 0x70000030 SMBCR1 EQU 0x70000034 SMBSR1 EQU 0x70000038 SMBWSTBRDR1 EQU 0x7000003c SMBIDCYR2 EQU 0x70000040 SMBWSTRDR2 EQU 0x70000044 SMBWSTWRR2 EQU 0x70000048 SMBWSTOENR2 EQU 0x7000004c SMBWSTWENR2 EQU 0x70000050 SMBCR2 EQU 0x70000054 SMBSR2 EQU 0x70000058 SMBWSTBRDR2 EQU 0x7000005c SMBIDCYR3 EQU 0x70000060 SMBWSTRDR3 EQU 0x70000064 SMBWSTWRR3 EQU 0x70000068 SMBWSTOENR3 EQU 0x7000006c SMBWSTWENR3 EQU 0x70000070 SMBCR3 EQU 0x70000074 SMBSR3 EQU 0x70000078 SMBWSTBRDR3 EQU 0x7000007c SMBIDCYR4 EQU 0x70000080 SMBWSTRDR4 EQU 0x70000084 SMBWSTWRR4 EQU 0x70000088 SMBWSTOENR4 EQU 0x7000008c SMBWSTWENR4 EQU 0x70000090 SMBCR4 EQU 0x70000094 SMBSR4 EQU 0x70000098 SMBWSTBRDR4 EQU 0x7000009c SMBIDCYR5 EQU 0x700000a0 SMBWSTRDR5 EQU 0x700000a4 SMBWSTWRR5 EQU 0x700000a8 SMBWSTOENR5 EQU 0x700000ac SMBWSTWENR5 EQU 0x700000b0 SMBCR5 EQU 0x700000b4 SMBSR5 EQU 0x700000b8 SMBWSTBRDR5 EQU 0x700000bc SMBIDCYR6 EQU 0x700000c0 SMBWSTRDR6 EQU 0x700000c4 SMBWSTWRR6 EQU 0x700000c8 SMBWSTOENR6 EQU 0x700000cc SMBWSTWENR6 EQU 0x700000d0 SMBCR6 EQU 0x700000d4 SMBSR6 EQU 0x700000d8 SMBWSTBRDR6 EQU 0x700000dc SMBIDCYR7 EQU 0x700000e0 SMBWSTRDR7 EQU 0x700000e4 SMBWSTWRR7 EQU 0x700000e8 SMBWSTOENR7 EQU 0x700000ec SMBWSTWENR7 EQU 0x700000f0 SMBCR7 EQU 0x700000f4 SMBSR7 EQU 0x700000f8 SMBWSTBRDR7 EQU 0x700000fc ;================= ; DMC ;================= DMC0_BASE EQU 0x7e000000 DMC1_BASE EQU 0x7e001000 INDEX_MEMSTAT EQU 0x0 INDEX_MEMCCMD EQU 0x4 INDEX_DIRECTCMD EQU 0x8 INDEX_MEMCFG EQU 0xc INDEX_REFRESH EQU 0x10 INDEX_CASLAT EQU 0x14 INDEX_T_DQSS EQU 0x18 INDEX_T_MRD EQU 0x1c INDEX_T_RAS EQU 0x20 INDEX_T_RC EQU 0x24 INDEX_T_RCD EQU 0x28 INDEX_T_RFC EQU 0x2c INDEX_T_RP EQU 0x30 INDEX_T_RRD EQU 0x34 INDEX_T_WR EQU 0x38 INDEX_T_WTR EQU 0x3c INDEX_T_XP EQU 0x40 INDEX_T_XSR EQU 0x44 INDEX_T_ESR EQU 0x48 INDEX_MEMCFG2 EQU 0x4c INDEX_ID_0_CFG EQU 0x100 INDEX_ID_1_CFG EQU 0x104 INDEX_ID_2_CFG EQU 0x108 INDEX_ID_3_CFG EQU 0x10c INDEX_ID_4_CFG EQU 0x110 INDEX_ID_5_CFG EQU 0x114 INDEX_ID_6_CFG EQU 0x118 INDEX_ID_7_CFG EQU 0x11c INDEX_ID_8_CFG EQU 0x120 INDEX_ID_9_CFG EQU 0x124 INDEX_ID_10_CFG EQU 0x128 INDEX_ID_11_CFG EQU 0x12c INDEX_ID_12_CFG EQU 0x130 INDEX_ID_13_CFG EQU 0x134 INDEX_ID_14_CFG EQU 0x138 INDEX_ID_15_CFG EQU 0x13c INDEX_CHIP0_CFG EQU 0x200 INDEX_CHIP1_CFG EQU 0x204 INDEX_USER_STAT EQU 0x300 INDEX_USER_CFG EQU 0x304 ;------------------------------------------------------------------------------- ; Memory Chip direct command ;------------------------------------------------------------------------------- DMC_NOP0 EQU 0x0c0000 DMC_NOP1 EQU 0x1c0000 DMC_PA0 EQU 0x000000 ; Precharge all DMC_PA1 EQU 0x100000 DMC_AR0 EQU 0x040000 ; Autorefresh DMC_AR1 EQU 0x140000 DMC_SDR_MR0 EQU 0x080032 ; MRS, CAS 3, Burst Length 4 DMC_SDR_MR1 EQU 0x180032 DMC_DDR_MR0 EQU 0x080162 DMC_DDR_MR1 EQU 0x180162 DMC_mDDR_MR0 EQU 0x080032 ; CAS 3, Burst Length 4 DMC_mDDR_MR1 EQU 0x180032 DMC_mSDR_EMR0 EQU 0x0a0000 ; EMRS, DS:Full, PASR:Full Array DMC_mSDR_EMR1 EQU 0x1a0000 DMC_DDR_EMR0 EQU 0x090000 DMC_DDR_EMR1 EQU 0x190000 DMC_mDDR_EMR0 EQU 0x0a0000 ; DS:Full, PASR:Full Array DMC_mDDR_EMR1 EQU 0x1a0000 END /************************************************* //image_cfg.inc 文件 /************************************************* ;//------------------------------------------------------------------------------ ;// NAMING CONVENTION ;// ;// The IMAGE_ naming convention ... ;// ;// IMAGE__
    __[OFFSET|SIZE|START|END] ;// ;// - WINCE, BOOT, SHARE ;//
    - section name: user defined ;// - the memory device the block resides on ;// OFFSET - number of bytes from memory device start address ;// SIZE - maximum size of the block ;// START - start address of block (device address + offset) ;// END - end address of block (start address + size - 1) ;// ;//------------------------------------------------------------------------------ ;// DRAM Base Address DRAM_BASE_PA_START EQU (0x50000000) DRAM_BASE_CA_START EQU (0x80000000) DRAM_BASE_UA_START EQU (0xA0000000) DRAM_SIZE EQU (0x08000000) ;//------------------------------------------------------------------------------ ;// Steploader Area IMAGE_STEPLOADER_PA_START EQU (0x00000000) IMAGE_STEPLOADER_SIZE EQU (0x00001000) ;//------------------------------------------------------------------------------ ;// Eboot Area IMAGE_EBOOT_OFFSET EQU (0x00030000) IMAGE_EBOOT_PA_START EQU (DRAM_BASE_PA_START+IMAGE_EBOOT_OFFSET) IMAGE_EBOOT_CA_START EQU (DRAM_BASE_CA_START+IMAGE_EBOOT_OFFSET) IMAGE_EBOOT_UA_START EQU (DRAM_BASE_UA_START+IMAGE_EBOOT_OFFSET) IMAGE_EBOOT_SIZE EQU (0x00080000) EBOOT_BINFS_BUFFER_OFFSET EQU (0x000C0000) EBOOT_BINFS_BUFFER_PA_START EQU (DRAM_BASE_PA_START+EBOOT_BINFS_BUFFER_OFFSET) EBOOT_BINFS_BUFFER_CA_START EQU (DRAM_BASE_CA_START+EBOOT_BINFS_BUFFER_OFFSET) EBOOT_BINFS_BUFFER_UA_START EQU (DRAM_BASE_UA_START+EBOOT_BINFS_BUFFER_OFFSET) EBOOT_BINFS_BUFFER_SIZE EQU (0x00030000) EBOOT_USB_BUFFER_OFFSET EQU (0x04000000) EBOOT_USB_BUFFER_PA_START EQU (DRAM_BASE_PA_START+EBOOT_USB_BUFFER_OFFSET) EBOOT_USB_BUFFER_CA_START EQU (DRAM_BASE_CA_START+EBOOT_USB_BUFFER_OFFSET) EBOOT_USB_BUFFER_UA_START EQU (DRAM_BASE_UA_START+EBOOT_USB_BUFFER_OFFSET) ;//------------------------------------------------------------------------------ ;// NK Area IMAGE_NK_OFFSET EQU (0x00100000) IMAGE_NK_PA_START EQU (DRAM_BASE_PA_START+IMAGE_NK_OFFSET) IMAGE_NK_CA_START EQU (DRAM_BASE_CA_START+IMAGE_NK_OFFSET) IMAGE_NK_UA_START EQU (DRAM_BASE_UA_START+IMAGE_NK_OFFSET) ;gao0129 ;IMAGE_NK_SIZE EQU (0x03F00000) ; Set Max size, This will be tailored automatically. IMAGE_NK_SIZE EQU (0x02800000) ;//------------------------------------------------------------------------------ ;// BSP ARGs Area IMAGE_SHARE_ARGS_OFFSET EQU (0x00020800) IMAGE_SHARE_ARGS_PA_START EQU (DRAM_BASE_PA_START+IMAGE_SHARE_ARGS_OFFSET) IMAGE_SHARE_ARGS_CA_START EQU (DRAM_BASE_CA_START+IMAGE_SHARE_ARGS_OFFSET) IMAGE_SHARE_ARGS_UA_START EQU (DRAM_BASE_UA_START+IMAGE_SHARE_ARGS_OFFSET) IMAGE_SHARE_ARGS_SIZE EQU (0x00000800) ;//------------------------------------------------------------------------------ ;// Sleep Data Area IMAGE_SLEEP_DATA_OFFSET EQU (0x00028000) IMAGE_SLEEP_DATA_PA_START EQU (DRAM_BASE_PA_START+IMAGE_SLEEP_DATA_OFFSET) IMAGE_SLEEP_DATA_CA_START EQU (DRAM_BASE_CA_START+IMAGE_SLEEP_DATA_OFFSET) IMAGE_SLEEP_DATA_UA_START EQU (DRAM_BASE_UA_START+IMAGE_SLEEP_DATA_OFFSET) IMAGE_SLEEP_DATA_SIZE EQU (0x00002000) ;//------------------------------------------------------------------------------ ;------------------------------------------------------------------------------ ; OEM Stack Layout ; EBOOT, STEPLOADER also use this value ;------------------------------------------------------------------------------ TOP_OF_STACKS_PHYSICAL EQU (DRAM_BASE_PA_START+IMAGE_NK_OFFSET) ; Stack Top is in front of NK Image TOP_OF_STACKS_VIRTUAL EQU (DRAM_BASE_CA_START+IMAGE_NK_OFFSET) ; Stack Size of Each Mode FIQStackSize EQU 256 IRQStackSize EQU 256 AbortStackSize EQU 256 UndefStackSize EQU 256 SVCStackSize EQU 1024 ;UserStackSize EQU 2048 ; Stack Location of Each Mode (in Physical Address) FIQStack_PA EQU (TOP_OF_STACKS_PHYSICAL - 0x0) IRQStack_PA EQU (FIQStack_PA - FIQStackSize) AbortStack_PA EQU (IRQStack_PA - IRQStackSize) UndefStack_PA EQU (AbortStack_PA - AbortStackSize) SVCStack_PA EQU (UndefStack_PA - UndefStackSize) UserStack_PA EQU (SVCStack_PA - SVCStackSize) ; Stack Location of Each Mode (in Virtual Address) FIQStack_VA EQU (TOP_OF_STACKS_VIRTUAL - 0x0) IRQStack_VA EQU (FIQStack_VA - FIQStackSize) AbortStack_VA EQU (IRQStack_VA - IRQStackSize) UndefStack_VA EQU (AbortStack_VA - AbortStackSize) SVCStack_VA EQU (UndefStack_VA - UndefStackSize) UserStack_VA EQU (SVCStack_VA - SVCStackSize) ;------------------------------------------------------------------------------ ; Sleep Data Layout ;------------------------------------------------------------------------------ SleepState_Data_Start EQU (0) SleepState_WakeAddr EQU (SleepState_Data_Start) SleepState_SYSCTL EQU (SleepState_WakeAddr + WORD_SIZE ) SleepState_MMUTTB0 EQU (SleepState_SYSCTL + WORD_SIZE ) SleepState_MMUTTB1 EQU (SleepState_MMUTTB0 + WORD_SIZE ) SleepState_MMUTTBCTL EQU (SleepState_MMUTTB1 + WORD_SIZE ) SleepState_MMUDOMAIN EQU (SleepState_MMUTTBCTL + WORD_SIZE ) SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE ) SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE ) SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE ) SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE ) SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE ) SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE ) SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE ) SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE ) SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE ) SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE ) SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE ) SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE ) SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE ) SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE ) SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE ) SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE ) SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE ) SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE ) SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE ) SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE ) SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE ) SleepState_VFP_FPSCR EQU (SleepState_SYS_LR + WORD_SIZE) SleepState_VFP_FPEXC EQU (SleepState_VFP_FPSCR + WORD_SIZE) SleepState_VFP_FPINST EQU (SleepState_VFP_FPEXC + WORD_SIZE) SleepState_VFP_FPINST2 EQU (SleepState_VFP_FPINST + WORD_SIZE) SleepState_VFP_S0 EQU (SleepState_VFP_FPINST2 + WORD_SIZE) SleepState_VFP_S1 EQU (SleepState_VFP_S0 + WORD_SIZE) SleepState_VFP_S2 EQU (SleepState_VFP_S1 + WORD_SIZE) SleepState_VFP_S3 EQU (SleepState_VFP_S2 + WORD_SIZE) SleepState_VFP_S4 EQU (SleepState_VFP_S3 + WORD_SIZE) SleepState_VFP_S5 EQU (SleepState_VFP_S4 + WORD_SIZE) SleepState_VFP_S6 EQU (SleepState_VFP_S5 + WORD_SIZE) SleepState_VFP_S7 EQU (SleepState_VFP_S6 + WORD_SIZE) SleepState_VFP_S8 EQU (SleepState_VFP_S7 + WORD_SIZE) SleepState_VFP_S9 EQU (SleepState_VFP_S8 + WORD_SIZE) SleepState_VFP_S10 EQU (SleepState_VFP_S9 + WORD_SIZE) SleepState_VFP_S11 EQU (SleepState_VFP_S10 + WORD_SIZE) SleepState_VFP_S12 EQU (SleepState_VFP_S11 + WORD_SIZE) SleepState_VFP_S13 EQU (SleepState_VFP_S12 + WORD_SIZE) SleepState_VFP_S14 EQU (SleepState_VFP_S13 + WORD_SIZE) SleepState_VFP_S15 EQU (SleepState_VFP_S14 + WORD_SIZE) SleepState_VFP_S16 EQU (SleepState_VFP_S15 + WORD_SIZE) SleepState_VFP_S17 EQU (SleepState_VFP_S16 + WORD_SIZE) SleepState_VFP_S18 EQU (SleepState_VFP_S17 + WORD_SIZE) SleepState_VFP_S19 EQU (SleepState_VFP_S18 + WORD_SIZE) SleepState_VFP_S20 EQU (SleepState_VFP_S19 + WORD_SIZE) SleepState_VFP_S21 EQU (SleepState_VFP_S20 + WORD_SIZE) SleepState_VFP_S22 EQU (SleepState_VFP_S21 + WORD_SIZE) SleepState_VFP_S23 EQU (SleepState_VFP_S22 + WORD_SIZE) SleepState_VFP_S24 EQU (SleepState_VFP_S23 + WORD_SIZE) SleepState_VFP_S25 EQU (SleepState_VFP_S24 + WORD_SIZE) SleepState_VFP_S26 EQU (SleepState_VFP_S25 + WORD_SIZE) SleepState_VFP_S27 EQU (SleepState_VFP_S26 + WORD_SIZE) SleepState_VFP_S28 EQU (SleepState_VFP_S27 + WORD_SIZE) SleepState_VFP_S29 EQU (SleepState_VFP_S28 + WORD_SIZE) SleepState_VFP_S30 EQU (SleepState_VFP_S29 + WORD_SIZE) SleepState_VFP_S31 EQU (SleepState_VFP_S30 + WORD_SIZE) SleepState_Data_End EQU (SleepState_VFP_S31 + WORD_SIZE ) SLEEPDATA_SIZE EQU ((SleepState_Data_End - SleepState_Data_Start) / 4) ;//------------------------------------------------------------------------------ END //*********************************************************** //MemParam_mDDR.inc 文件 //************************************************************ ; ; Copyright (c) Microsoft Corporation. All rights reserved. ; ; ; Use of this source code is subject to the terms of the Microsoft end-user ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT. ; If you did not accept the terms of the EULA, you are not authorized to use ; this source code. For a copy of the EULA, please see the LICENSE.RTF on your ; install media. ; ;------------------------------------------------------------------------------- ; ; Header: MemParam_mDDR.inc ; ; This header file defines only those registers required by the startup ; code. All addresses are based off the physical addresses (PA) defined ; in s3c6410_base_reg.h (s3c6410_base_reg.inc). ; ;------------------------------------------------------------------------------- ; Include the system definitions ; INCLUDE s3c6410.inc GBLL USE_DMC0 GBLL USE_DMC0_CHIP0 GBLL USE_DMC0_CHIP1 GBLL USE_DMC1 GBLL USE_DMC1_CHIP0 GBLL USE_DMC1_CHIP1 ;------------------------------------------------------------------------------- ; DDR Timing Parameter ;------------------------------------------------------------------------------- DDR_tREFRESH EQU 7800 ; ns 7800 DDR_tRAS EQU 45 ; ns (min: 45ns) DDR_tRC EQU 68 ; ns (min: 67.5ns) DDR_tRCD EQU 23 ; ns (min: 22.5ns) DDR_tRFC EQU 80 ; ns (min: 80ns) DDR_tRP EQU 23 ; ns (min: 22.5ns) DDR_tRRD EQU 15 ; ns (min: 15ns) DDR_tWR EQU 15 ; ns (min: 15ns) DDR_tXSR EQU 120 ; ns (min: 120ns) DDR_CASL EQU 3 ; CAS Latency 3 ;------------------------------------------------------------------------------- ; Definitions for memory configuration ;------------------------------------------------------------------------------- USE_DMC0 SETL {FALSE} USE_DMC0_CHIP0 SETL {FALSE} USE_DMC0_CHIP1 SETL {FALSE} USE_DMC1 SETL {TRUE} USE_DMC1_CHIP0 SETL {TRUE} USE_DMC1_CHIP1 SETL {FALSE} ;------------------------------------------------------------------------------- ; Memory Configuration Register ; CKE_Ctrl[31], Active_Chip[22:21], Qos_master[20:18], Burst[17:15], Stop_mem_clock[14] ; Auto_power_down[13], Pwr_down_prd[12:7], AP bit[6], Row bit[5:3], Column bit[2:0] ; CKE_Ctrl : 1'b0(One CKE Ctrl), 1'b1(Individual CKE Ctrl) ; Active Chip : 2'b00 (1chip), 2'b01(2chips) ; Memory Burst: 3'b000 (Burst1), 3'b001(Burst2), 3'b010(Burst4), 3'b011(Burst8), 3'b100(Burst16) ; 31th register in P1MEMCFG shoud be set as '0' to support one cke control DMC1_MEM_CFG EQU ((1<<30)+(0<<21)+(0<<18)+(2<<15)+(0<<14)+(0<<13)+(0<<7)+(0<<6)+(2<<3)+(2<<0)) ; colum A0~A9 ;DMC1_MEM_CFG EQU 0x80010012 ;------------------------------------------------------------------------------- ; Memory Configuration 2 Register ; Read Delay[12:11], Memory Type[10:8], Memory Width[7:6], Bank bits[5:4], DQM init[2], Clock[1:0] ; Read Delay : 2'b00 (SDRAM), 2'b01 (DDR,mDDR), 2'b10 = Read Delay 2 cycle ; Memory Type: 3'b000(SDRAM), 3'b001(DDR), 3'b011(mDDR), 3'b010(Embedded DRAM) ; Memory Width : 2'b00 (16bit), 2'b01(32bit) ; DQM init : DQM state at reset ; Clock Config: AXI and Memory Clock are sync. DMC1_MEM_CFG2 EQU ((1<<11)+(3<<8)+(1<<6)+(0<<4)+(0<<2)+(1<<0)) ;DMC1_MEM_CFG2 EQU 0xB41 ;------------------------------------------------------------------------------- ; CHIP Configuration Register ; BRC_RBC[16], Addr_match[15:8], Addr_Mask[7:0] ; BRC_RBC: 1'b0 (Row-Bank-Column), 1'b1 (Bank-Row-Column) ; Addr_match: AXI_addr[31:24], Ex) 0x5000_0000, Set 0x50 ; Addr_Mask : AXI_addr[31:24], Ex) 0x57ff_ffff, Set 0xF8 DMC1_CHIP0_CFG EQU ((1<<16)+(0x50<<8)+(0xF8<<0)) ; BRC (Linear Address Mapping) ;DMC1_CHIP0_CFG EQU ((0<<16)+(0x50<<8)+(0xF8<<0)) ; RBC (4K Unit Permute) ;DMC1_CHIP0_CFG EQU 0x150F8 ; User Configuration Register ; DQS3[7:6], DQS2[5:4], DQS1[3:2], DQS0[1:0] DMC1_USER_CFG EQU 0x0 ;------------------------------------------------------------------------------- ; Memory Configurations for DMC ; (HCLK: DMC Clock) ;------------------------------------------------------------------------------- ;--------------------------- ; mDDR Memory Configuration ;--------------------------- [ {TRUE} DMC_DDR_BA_EMRS EQU (2) DMC_DDR_MEM_CASLAT EQU (3) DMC_DDR_CAS_LATENCY EQU (DDR_CASL<<1) ; 6 Set Cas Latency to 3 DMC_DDR_t_DQSS EQU (1) ; Min 0.75 ~ 1.25 DMC_DDR_t_MRD EQU (2) ; Min 2 tck DMC_DDR_t_RAS EQU (((HCLK/1000*DDR_tRAS)+500000)/1000000+1) ; 7, Min 45ns DMC_DDR_t_RC EQU (((HCLK/1000*DDR_tRC)+500000)/1000000+1) ; 10, Min 67.5ns DMC_DDR_t_RCD EQU (((HCLK/1000*DDR_tRCD)+500000)/1000000+1) ; 4,5(TRM), Min 22.5ns DMC_DDR_schedule_RCD EQU ((DMC_DDR_t_RCD -3) <<3); DMC_DDR_t_RFC EQU (((HCLK/1000*DDR_tRFC)+500000)/1000000+1) ; 11,18(TRM) Min 80ns DMC_DDR_schedule_RFC EQU ((DMC_DDR_t_RFC -3) <<5); DMC_DDR_t_RP EQU (((HCLK/1000*DDR_tRP)+500000)/1000000+1) ; 4, 5(TRM) Min 22.5ns DMC_DDR_schedule_RP EQU ((DMC_DDR_t_RP -3) <<3); DMC_DDR_t_RRD EQU (((HCLK/1000*DDR_tRRD)+500000)/1000000+1) ; 3, Min 15ns DMC_DDR_t_WR EQU (((HCLK/1000*DDR_tWR)+500000)/1000000+1) ; Min 15ns DMC_DDR_t_WTR EQU (2) DMC_DDR_t_XP EQU (2) ; 1tck + tIS(1.5ns) DMC_DDR_t_XSR EQU (((HCLK/1000*DDR_tXSR)+500000)/1000000+1) ; 17, Min 120ns DMC_DDR_t_ESR EQU (DMC_DDR_t_XSR) DMC_DDR_REFRESH_PRD EQU (((HCLK/1000*DDR_tREFRESH)+500000)/1000000) ; TRM 2656 DMC_DDR_REFRESH_PRD_DVS EQU (DMC_DDR_REFRESH_PRD/2) ; HCLK can be divided by 2 | [ {TRUE} ;HCLK=133MHZ DMC_DDR_REFRESH_PRD EQU (0x40D) ; TRM 2656 DMC_DDR_REFRESH_PRD_DVS EQU (0x40D) ; HCLK can be divided by 2 DMC_DDR_CAS_LATENCY EQU (0x6) ; 6 Set Cas Latency to 3 DMC_DDR_t_DQSS EQU (0x1) ; Min 0.75 ~ 1.25 DMC_DDR_t_MRD EQU (0x2) ; Min 2 tck DMC_DDR_t_RAS EQU (0x6) ; 7, Min 45ns DMC_DDR_t_RC EQU (0xA) ; 11 Changed ; 10, Min 67.5ns DMC_DDR_t_RCD EQU (0xC) ; 4,5(TRM), Min 22.5ns DMC_DDR_t_RFC EQU (0x10B) ; DMC_DDR_t_RP EQU (0xC) ; 4, 5(TRM) Min 22.5ns DMC_DDR_t_RRD EQU (0x2) ; 3, Min 15ns DMC_DDR_t_WR EQU (0x2) ; Min 15ns DMC_DDR_t_WTR EQU (0x2) DMC_DDR_t_XP EQU (0x2) ; 1tck + tIS(1.5ns) DMC_DDR_t_XSR EQU (0x10) ;18 ; 17, Min 120ns DMC_DDR_t_ESR EQU (DMC_DDR_t_XSR) ] [ {FALSE} ;HCLK=150MHZ DMC_DDR_REFRESH_PRD EQU (0x491) ; TRM 2656 DMC_DDR_REFRESH_PRD_DVS EQU (0x491) ; HCLK can be divided by 2 DMC_DDR_CAS_LATENCY EQU (0x6) ; 6 Set Cas Latency to 3 DMC_DDR_t_DQSS EQU (0x1) ; Min 0.75 ~ 1.25 DMC_DDR_t_MRD EQU (0x2) ; Min 2 tck DMC_DDR_t_RAS EQU (0x7) ; 7, Min 45ns DMC_DDR_t_RC EQU (0xB) ; 11 Changed ; 10, Min 67.5ns DMC_DDR_t_RCD EQU (0xC) ; 4,5(TRM), Min 22.5ns DMC_DDR_t_RFC EQU (0x12C) ; DMC_DDR_t_RP EQU (0xC) ; 4, 5(TRM) Min 22.5ns DMC_DDR_t_RRD EQU (0x3) ; 3, Min 15ns DMC_DDR_t_WR EQU (0x3) ; Min 15ns DMC_DDR_t_WTR EQU (0x2) DMC_DDR_t_XP EQU (0x2) ; 1tck + tIS(1.5ns) DMC_DDR_t_XSR EQU (0x12) ;18 ; 17, Min 120ns DMC_DDR_t_ESR EQU (DMC_DDR_t_XSR) ] ] END

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