首页资源分类嵌入式处理器其它 > tlc5615的数据手册

tlc5615的数据手册

已有 445117个资源

下载专区

上传者其他资源

    文档信息举报收藏

    标    签:tlc5615手册

    分    享:

    文档简介

    tlc数据手册 10位串行dac芯片,易于与单片机等微处理器接口。

    文档预览

    TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 10-BIT DIGITAL-TO-ANALOG CONVERTERS FEATURES • 10-Bit CMOS Voltage Output DAC in an 8-Terminal Package • 5V Single Supply Operation • 3-Wire Serial Interface • High-Impedance Reference Inputs • Voltage Output Range: 2 Times the Reference Input Voltage • Internal Power-On Reset • Low Power Consumption: 1.75mW Max • Update Rate of 1.21MHz • Settling Time to 0.5LSB: 12.5µs Typ • Monotonic Over Temperature • Pin-Compatible With the Maxim MAX515 APPLICATIONS • Battery-Powered Test Instruments • Digital Offset and Gain Adjustment • Battery Operated/Remote Industrial Controls • Machine and Motion Control Devices • Cellular Telephones DESCRIPTION The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is monotonic. The device is simple to use, running from a single supply of 5V. A power-on-reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to produce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include the SPI™, QSPI™, and Microwire™ standards. The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications. The TLC5615C is characterized for operation from 0°C to +70°C. The TLC5615I is characterized for operation from –40°C to +85°C. D, P, OR DGK PACKAGE (TOP VIEW) DIN 1 SCLK 2 CS 3 DOUT 4 8 VDD 7 OUT 6 REFIN 5 AGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996–2007, Texas Instruments Incorporated TLC5615C, TLC5615I SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM REFIN AGND _ + Power-ON Reset DAC R + _2 R OUT (Voltage Output) CS SCLK DIN Control Logic 10-Bit DAC Register 2 (LSB) (MSB) 4 0s Dummy 10 Data Bits Bits 16-Bit Shift Register DOUT TERMINAL NAME NO. DIN 1 SCLK 2 CS 3 DOUT 4 AGND 5 REFIN 6 OUT 7 VDD 8 Terminal Functions I/O DESCRIPTION I Serial data input I Serial clock input I Chip select, active low O Serial data output for daisy chaining Analog ground I Reference input O DAC analog voltage output Positive power supply PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 Submit Documentation Feedback TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted)(1) Supply voltage (VDD to AGND) Digital input voltage range to AGND Reference input voltage range to AGND Output voltage at OUT from external source Continuous current at any terminal Operating free-air temperature range, TA TLC5615C TLC5615I Storage temperature range, Tstg Lead temperature 1,6mm (1/16 inch) from case for 10 seconds UNIT 7V –0.3V to VDD + 0.3V –0.3V to VDD + 0.3V VDD + 0.3V ±20mA 0°C to +70°C –40°C to +85°C –65°C to +150°C +260°C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Supply voltage, VDD High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REFIN terminal Load resistance, RL Operating free-air temperature, TA TLC5615C TLC5615I MIN NOM 4.5 5 2.4 2 2.048 2 0 40 MAX 5.5 0.8 VDD–2 70 85 UNIT V V V V kΩ °C °C ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, VDD = 5V ± 5%, Vref = 2.048V (unless otherwise noted) STATIC DAC SPECIFICATIONS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution Integral nonlinearity, end point adjusted (INL) Differential nonlinearity (DNL) EZS Zero-scale error (offset error at zero scale) Zero-scale-error temperature coefficient EG Gain error Gain-error temperature coefficient PSRR Power-supply rejection ratio Zero scale Gain Vref = 2.048V, Vref = 2.048V, Vref = 2.048V, Vref = 2.048V, Vref = 2.048V, Vref = 2.048V, See (7) (8) See (1) See (2) See (3) See (4) See (5) See (6) 10 ±0.1 3 1 80 80 bits ±1 LSB ±0.5 LSB ±3 LSB ppm/°C ±3 LSB ppm/°C dB Analog full scale output RL = 100kΩ 2Vref(1023/1024) V (1) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). Tested from code 3 to code 1024. (2) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Tested from code 3 to code 1024. (3) Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text). (4) Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax– Tmin). (5) Gain error is the deviation from the ideal output (Vref – 1LSB) with an output load of 10kΩ excluding the effects of the zero-scale error. (6) Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax– Tmin). (7) Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5V to 5.5V dc and measuring the proportion of this signal imposed on the zero-code output voltage. (8) Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5V to 5.5V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero-scale change. Submit Documentation Feedback 3 TLC5615C, TLC5615I SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 VOLTAGE OUTPUT (OUT) PARAMETER TEST CONDITIONS VO Voltage output range Output load regulation accuracy IOSC Output short circuit current VOL(low) Output voltage, low-level VOH(high) Output voltage, high-level REFERENCE INPUT (REFIN) RL= 10kΩ VO(OUT) = 2V, OUT to VDD or AGND IO(OUT)≤ 5mA IO(OUT)≤– 5mA RL = 2kΩ VI Input voltage ri Input resistance Ci Input capacitance DIGITAL INPUTS (DIN, SCLK, CS) VIH High-level digital input voltage VIL Low-level digital input voltage IIH High-level digital input current IIL Low-level digital input current Ci Input capacitance DIGITAL OUTPUT (DOUT) VI = VDD VI = 0 VOH Output voltage, high-level VOL Output voltage, low-level POWER SUPPLY IO = –2mA IO = 2mA VDD Supply voltage IDD Power supply current VDD = 5.5V, No load, All inputs = 0V or VDD VDD= 5.5V, No load, All inputs = 0V or VDD ANALOG OUTPUT DYNAMIC PERFORMANCE Vref = 0 Vref = 2.048V Signal-to-noise + distortion, S/(N+D) Vref = 1VPP at 1kHz + 2.048Vdc, code = 11 1111 1111(1) (1) The limiting frequency value at 1VPP is determined by the output-amplifier slew rate. DIGITAL INPUT TIMING REQUIREMENTS (See Figure 1) tsu(DS) th(DH) tsu(CSS) tsu(CS1) th(CSH0) th(CSH1) tw(CS) tw(CL) tw(CH) PARAMETER Setup time, DIN before SCLK high Hold time, DIN valid after SCLK high Setup time, CS low to SCLK high Setup time, CS high to SCLK high Hold time, SCLK low to CS low Hold time, SCLK low to CS high Pulse duration, minimum chip select pulse width high Pulse duration, SCLK low Pulse duration, SCLK high OUTPUT SWITCHING CHARACTERISTICS tpd(DOUT) PARAMETER Propagation delay time, DOUT CL = 50pF TEST CONDITIONS www.ti.com MIN TYP MAX UNIT 0 VDD–0.4 V 0.5 LSB 20 mA 0.25 V 4.75 V 0 VDD–2 V 10 MΩ 5 pF 2.4 8 V 0.8 V ±1 µA ±1 µA pF VDD–1 V 0.4 V 4.5 5 150 230 5.5 V 250 µA 350 µA 60 dB MIN NOM MAX UNIT 45 ns 0 ns 1 ns 50 ns 1 ns 0 ns 20 ns 25 ns 25 ns MIN NOM MAX UNIT 50 ns 4 Submit Documentation Feedback TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 OPERATING CHARACTERISTICS over recommended operating free-air temperature range, VDD = 5V ±5%, Vref = 2.048V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX ANALOG OUTPUT DYNAMIC PERFORMANCE SR Output slew rate ts Output settling time Glitch energy CL = 100pF, TA= +25°C To 0.5LSB, RL = 10kΩ, DIN = All 0s to all 1s RL = 10kΩ, CL = 100pF, (1) 0.3 0.5 12.5 5 REFERENCE INPUT (REFIN) Reference feedthrough REFIN = 1VPP at 1kHz + 2.048Vdc (2) –80 Reference input bandwidth (f–3dB) REFIN = 0.2VPP + 2.048Vdc 30 UNIT V/µs µs nV-s dB kHz (1) Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change of 000 hex to 3FF hex or 3FF hex to 000 hex. (2) Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048Vdc + 1Vpp at 1kHz. PARAMETER MEASUREMENT INFORMATION CS th(CSH0) ÎÎÎÎÎÎÎÎÎ SCLK ÎÎÎ See Note A ÎÎÎÎÎ tsu(DS) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DIN tsu(CSS) tw(CH) th(DH) tw(CL) ÎÎÎÎ th(CSH1) tw(CS) tsu(CS1) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SeeNoteC SeeNoteA tpd(DOUT) DOUT Previous LSB See Note B MSB LSB NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough. B. Data input from preceeding conversion cycle. C. Sixteenth SCLK falling edge Figure 1. Timing Diagram Submit Documentation Feedback 5 TLC5615C, TLC5615I SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS www.ti.com IO - Output Sink Current - mA OUTPUT SINK CURRENT vs OUTPUT PULLDOWN VOLTAGE 20 18 VDD = 5 V VREFIN = 2.048 V 16 TA = 25°C 14 12 10 8 6 4 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 VO - Output Pulldown Voltage - V Figure 2. SUPPLY CURRENT vs TEMPERATURE 280 240 200 160 120 80 40 VDD = 5 V VREFIN = 2.048 V TA = 25°C 0 - 60 - 40 - 20 0 20 40 60 80 t - Temperature - °C 100 120 140 Figure 4. G - Relative Gain - dB IO - Output Source Current - mA OUTPUT SOURCE CURRENT vs OUTPUT PULLUP VOLTAGE 30 VDD = 5 V 25 VREFIN = 2.048 V TA = 25°C 20 15 10 5 0 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 VO - Output Pullup Voltage - V Figure 3. VREFIN TO V(OUT) RELATIVE GAIN vs INPUT FREQUENCY 4 VDD = 5 V 2 VREFIN = 0.2 VPP + 2.048 V dc TA = 25°C 0 -2 -4 -6 -8 - 10 - 12 - 14 1 100 1k 10 k fI - Input Frequency - Hz Figure 5. 100 k IDD - Supply Current - µ A 6 Submit Documentation Feedback www.ti.com 0.2 0.15 0.1 0.05 0 –0.05 –0.1 –0.15 –0.2 0 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 Integral Nonlinearity – LSB Differential Nonlinearity – LSB Signal-To-Noise + Distortion - dB TLC5615C, TLC5615I SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY AT REFIN 70 VDD = 5 V 60 TA = 25°C VREFIN = 4 VPP 50 40 30 20 10 0 1k 10 k 100 k Frequency - Hz Figure 6. 300 k 255 511 767 Input Code Figure 7. Differential Nonlinearity With Input Code 1023 255 511 767 Input Code Figure 8. Integral Nonlinearity With Input Code Submit Documentation Feedback 1023 7 TLC5615C, TLC5615I SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 APPLICATION INFORMATION www.ti.com GENERAL FUNCTION The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the same polarity as the reference input (see Table 1). An internal circuit resets the DAC register to all zeros on power up. DIN SCLK CS DOUT REFIN + _ Resistor + String _ DAC R OUT R AGND VDD 5V 0.1 µF Figure 9. TLC5615 Typical Operating Circuit Table 1. Binary Code Table (0V to 2VREFINOutput), Gain = 2 INPUT (1) OUTPUT 1111 1111 : 11(00) ǒ Ǔ 2 VREFIN 1023 1024 : 1000 0000 01(00) ǒ Ǔ 2 VREFIN 513 1024 1000 0000 00(00) ǒ Ǔ 2 VREFIN 512 1024 + VREFIN 0111 1111 : 11(00) 2ǒVREFINǓ 511 1024 : 0000 0000 0000 0000 01(00) 00(00) 2ǒVREFINǓ 1 1024 0V (1) A 10-bit data word with two bits below the LSB bit (sub-LSB) with 0 values must be written since the DAC input latch is 12 bits wide. 8 Submit Documentation Feedback TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 BUFFER AMPLIFIER The output buffer has a rail-to-rail output with short circuit protection and can drive a 2kΩ load with a 100pF load capacitance. Settling time is 12.5µs typical to within 0.5LSB of final value. EXTERNAL REFERENCE The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore, the REFIN input resistance is 10MΩ and the REFIN input capacitance is typically 5pF independent of input code. The reference voltage determines the DAC full-scale output. LOGIC INTERFACE The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic levels. SERIAL CLOCK AND UPDATE RATE Figure 1 shows the TLC5615 timing. The maximum serial clock rate is: f(SCLK)max + 1 twǒCHǓ ) twǒCLǓ or approximately 14MHz. The digital update rate is limited by the chip-select period, which is: ǒ Ǔ tp(CS) + 16 twǒCHǓ ) twǒCLǓ ) twǒCSǓ and is equal to 820ns which is a 1.21MHz update rate. However, the DAC settling time to 10 bits of 12.5µs limits the update rate to 80kHz for full-scale input step transitions. SERIAL INTERFACE When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most significant bit first. The rising edge of the SLCK input shifts the data into the input register. The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be clocked into the input register. All CS transitions should occur when the SCLK input is low. If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data sequence with the MSB first can be used as shown in Figure 10: 12 Bits MSB x = don’t care 10 Data Bits LSB Figure 10. 12-Bit Input Data Sequence x x 2 Extra (Sub-LSB) Bits or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first. 16 Bits 4 Upper Dummy Bits x = don’t care MSB 10 Data Bits LSB Figure 11. 16-Bit Input Data Sequence x x 2 Extra (Sub-LSB) Bits Submit Documentation Feedback 9 TLC5615C, TLC5615I SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 www.ti.com The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width. When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT terminal (see Figure 1). The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit data converter transfers. The TLC5615 three-wire interface is compatible with the SPI, QSPI, and Microwire serial standards. The hardware connections are shown in Figure 12 and Figure 13. The SPI and Microwire interfaces transfer data in 8-bit bytes; therefore, two write cycles are required to input data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC input register in one write cycle. SCLK SK DIN TLC5615 CS SO Microwire Port I/O DOUT SI NOTE A: The DOUT-SI connection is not required for writing to the TLC5615 but may be used for verifying data transfer if desired. Figure 12. Microwire Connection SCLK SCK DIN TLC5615 CS MOSI SPI/QSPI I/O Port DOUT MISO CPOL = 0, CPHA = 0 NOTE A: The DOUT-MISO connection is not required for writing to the TLC5615 but may be used for verifying data transfer. Figure 13. SPI/QSPI Connection DAISY-CHAINING DEVICES DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in the chain, providing that the setup time, tsu(CSS) (CS low to SCLK high), is greater than the sum of the setup time, tsu(DS), plus the propagation delay time, tpd(DOUT), for proper timing (see digital input timing requirements section). The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a totem-poled output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high, DOUT remains at the value of the last data bit and does not go into a high-impedance state. LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE-ENDED SUPPLIES When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. 10 Submit Documentation Feedback TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0V Negative Offset DAC Code Figure 14. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs '0') and full-scale code (all inputs '1') after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. For the TLC5615, the zero-scale (offset) error is ±3LSB maximum. The code is calculated from the maximum specification for the negative offset. POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT Printed circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 15 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 µF Figure 15. Power-Supply Bypassing SAVING POWER Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output load when the system is not using the DAC. Submit Documentation Feedback 11 TLC5615C, TLC5615I SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 AC CONSIDERATIONS www.ti.com Digital Feedthrough Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT. Analog Feedthrough Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to REFIN, and monitoring the DAC output. 12 Submit Documentation Feedback TLC5615C, TLC5615I www.ti.com SLAS142E – OCTOBER 1996 – REVISED JUNE 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from D Revision (August 2003) to E Revision ............................................................................................... Page • Added ESD statement. ......................................................................................................................................................... 2 • Changed —moved package option table from front page. ................................................................................................... 2 Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device TLC5615CD TLC5615CDG4 TLC5615CDGK TLC5615CDGKG4 TLC5615CDGKR TLC5615CDR TLC5615CDRG4 TLC5615CP TLC5615ID TLC5615IDG4 TLC5615IDGK TLC5615IDGKG4 TLC5615IDR TLC5615IDRG4 TLC5615IP TLC5615IPE4 Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Pb-Free (RoHS) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) ACTIVE PDIP P 8 50 Pb-Free (RoHS) ACTIVE PDIP P 8 50 Pb-Free (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Lead/Ball Finish (6) CU NIPDAU CU NIPDAU CU NIPDAUAG CU NIPDAUAG CU NIPDAUAG CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAUAG CU NIPDAUAG CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp Op Temp (°C) (3) Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 N / A for Pkg Type 0 to 70 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 Level-1-260C-UNLIM -40 to 85 N / A for Pkg Type -40 to 85 N / A for Pkg Type -40 to 85 Addendum-Page 1 Device Marking (4/5) 5615C 5615C AEM AEM AEM 5615C 5615C TLC5615CP 5615I 5615I AEN AEN 5615I 5615I TLC5615IP TLC5615IP Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 www.ti.com TAPE AND REEL INFORMATION PACKAGE MATERIALS INFORMATION 16-Aug-2012 *All dimensions are nominal Device Package Package Pins Type Drawing TLC5615CDGKR TLC5615CDR TLC5615CDR TLC5615IDR TLC5615IDR VSSOP DGK 8 SOIC D 8 SOIC D 8 SOIC D 8 SOIC D 8 SPQ 2500 2500 2500 2500 2500 Reel Reel A0 B0 K0 P1 W Pin1 Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 www.ti.com PACKAGE MATERIALS INFORMATION 16-Aug-2012 *All dimensions are nominal Device TLC5615CDGKR TLC5615CDR TLC5615CDR TLC5615IDR TLC5615IDR Package Type VSSOP SOIC SOIC SOIC SOIC Package Drawing Pins DGK 8 D 8 D 8 D 8 D 8 SPQ 2500 2500 2500 2500 2500 Length (mm) 367.0 367.0 340.5 340.5 367.0 Width (mm) 367.0 367.0 338.1 338.1 367.0 Height (mm) 35.0 35.0 20.6 20.6 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated

    Top_arrow
    回到顶部
    EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。