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EP3C25开发板官方原理图 (1)

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EP3C25开发板官方原理图 (1)

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5 4 3 2 Cyclone III Starter Board D SCHEMATIC TOP EP3C25 IN/OUT C MEMORY POWER USB BLASTER CONTENT COVER PAGE, TOP EP3C25 BANK1..BANK8, POWER, CONFIG CLOCK, LEVEL SHIFT, KEY, CONNECT, HSMC DDR, SSRAM, FLASH POWER USB BLASTER B 1 D PAGE 01 ~ 03 04 ~ 08 09 ~ 11 12 ~ 14 C 15 ~ 16 17 ~ 17 B A A Title Altera Cyclone III Eval Board Size Document Number B COVER PAGE Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 1 of 17 5 4 3 2 1 5 4 3 2 1 D D C C B B A A Title Altera Cyclone III Eval Board Size Document Number B PLACEMENT Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 2 of 17 5 4 3 2 1 5 4 3 2 1 D D Memory PAGE 12-14 EP3C25 PAGE 4-8 DDR_CLK_p DDR_CLK_n DDR_CKE DDR_BA0 DDR_BA1 DDR_WE_n DDR_CAS_n DDR_RAS_n DDR_CS_n DDR_DM0 DDR_DM1 DDR_DQS0 DDR_DQS1 DDR_A[0..12] DDR_CLK_p DDR_CLK_n DDR_CKE DDR_BA0 DDR_BA1 DDR_WE_n DDR_CAS_n DDR_RAS_n DDR_CS_n DDR_DM0 DDR_DM1 DDR_DQS0 DDR_DQS1 DDR_A[0..12] DDR_DQ[0..15] DDR_DQ[0..15] DDR_CLK_p DDR_CLK_n DDR_CKE DDR_BA0 DDR_BA1 DDR_WE_n DDR_CAS_n DDR_RAS_n DDR_CS_n DDR_DM0 DDR_DM1 DDR_DQS0 DDR_DQS1 DDR_A[0..12] DDR_DQ[0..15] DDR_CLK_p DDR_CLK_n DDR_CKE DDR_BA0 DDR_BA1 DDR_WE_n DDR_CAS_n DDR_RAS_n DDR_CS_n DDR_DM0 DDR_DM1 DDR_DQS0 DDR_DQS1 DDR_A[0..12] DDR_DQ[0..15] Clock, LED, Tact SW, HSMC PAGE 9-11 SRAM_CLK SRAM_CLK 50MHZ SRAM_WE_n SRAM_CLK SRAM_WE_n SRAM_CLK 50MHZ C SRAM_CE1_n SRAM_WE_n SRAM_CE1_n SRAM_WE_n LED[0..3] LED[0..3] KEY[0..3] C SRAM_OE_n SRAM_CE1_n FLASH_SRAM_DQ[0..31] SRAM_OE_n SRAM_CE1_n LED[0..3] CONF LED[0..3] KEY[0..3] SRAM_ADSC_n SRAM_OE_nFLASH_SRAM_DQ[0..31] SRAM_ADSC_n SRAM_OE_n KEY[0..3] CONF nCONFIG SRAM_BE_n[0..3] SRAM_ADSC_n SRAM_BE_n[0..3] SRAM_ADSC_n KEY[0..3] nCONFIG CPU_RST_n SRAM_BE_n[0..3] SRAM_BE_n[0..3] CPU_RST_n CPU_RST_n CPU_RST_n JTAG_TDO CIII_TDI FLASH_SRAM_A[1..25] FLASH_SRAM_A[1..25] LF_TDI LF_TDO TMS FLASH_SRAM_A[1..25] FLASH_SRAM_DQ[0..31] FLASH_SRAM_A[1..25] LF_TMS TCK FLASH_CLK FLASH_RESET_n FLASH_CLK FLASH_CLK FLASH_SRAM_DQ[0..31] HSMC_SCL HSMC_SDA HSMC_SCL HSMC_SDA HSMC_SDA HSMC_SDA LF_TCK HSMC_SCL HSMC_SCL FLASH_WE_n FLASH_CE_n FLASH_RESET_n FLASH_WE_n FLASH_RESET_n FLASH_WE_n FLASH_CLK FLASH_RESET_n HSMC_CLKIN0 HSMC_CLKIN0 HSMC_CLKIN_p[1..2] HSMC_CLKOUT0 HSMC_CLKOUT_p[1..2] HSMC_CLKOUT0 HSMC_CLKIN0 HSMC_CLKIN0 HSMC_CLKIN_p[1..2] FLASH_OE_n FLASH_CE_n FLASH_CE_n FLASH_WE_n HSMC_CLKIN_p[1..2] HSMC_CLKIN_n[1..2] HSMC_CLKOUT_n[1..2] HSMC_CLKOUT_p[1..2] HSMC_CLKIN_p[1..2] HSMC_CLKIN_n[1..2] FLASH_ADV_n FLASH_OE_n FLASH_OE_n FLASH_CE_n HSMC_CLKIN_n[1..2] HSMC_CLKOUT_n[1..2] HSMC_CLKIN_n[1..2] FLASH_WAIT FLASH_ADV_n FLASH_ADV_n FLASH_OE_n HSMC_CLKOUT0 HSMC_RX_p[4..16] HSMC_TX_p[4..16] FLASH_WAIT FLASH_ADV_n HSMC_CLKOUT0 HSMC_CLKOUT_p[1..2] HSMC_RX_n[4..16] HSMC_RX_p[4..16] HSMC_TX_p[4..16] HSMC_TX_n[4..16] FLASH_WAIT HSMC_CLKOUT_p[1..2] HSMC_CLKOUT_n[1..2] HSMC_RX_n[4..16] HSMC_TX_n[4..16] FLASH_WAIT HSMC_CLKOUT_n[1..2] HSMC_D[0..19] HSMC_TX_p[4..16] HSMC_D[0..19] HSMC_TX_p[4..16] HSMC_TX_n[4..16] HSMC_TX_n[4..16] B USB BLASTER PAGE 17 CIII_TDO FLASH_CE_n JTAG_TDI FLASH_CE_n JTAG_TDO JTAG_TMS JTAG_TCK nCE CONF CONF_DONE nSTATUS JTAG_TDO TMS TCK nCE CONF CONF_DONE nSTATUS CIII_TDI CIII_TDO TMS TCK nCE nCONFIG CONF_DONE nSTATUS LINK_D0 LINK_D1 LINK_D2 LINK_D3 CIII_TDI CIII_TDO CIII_TMS CIII_TCK nCE nCONFIG CONF_DONE nSTATUS LINK_D0 LINK_D1 LINK_D2 LINK_D3 HSMC_RX_p[4..16] HSMC_RX_n[4..16] HSMC_D[0..19] HSMC_RX_p[4..16] HSMC_RX_n[4..16] HSMC_D[0..19] B Power PAGE 15-16 LINK_D3 LINK_D3 LINK_D0 LINK_D1 LINK_D2 LINK_D0 LINK_D1 LINK_D2 50MHZ 50MHz A A Title Altera Cyclone III Eval Board Size Document Number B TOP LEVEL Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 3 of 17 5 4 3 2 1 5 4 3 2 1 D D HSMC_TX_p[4..16] HSMC_TX_n[4..16] HSMC_RX_p[4..16] HSMC_RX_n[4..16] FLASH_SRAM_DQ[0..31] HSMC_D[0..19] KEY[0..1] U1A U1B C HSMC_RX_p5 H2 LVDSL_6P/DQS0L HSMC_TX_p4 HSMC_RX_n4 FLASH_SRAM_DQ19 HSMC_SDA HSMC_TX_p5 HSMC_TX_n5 B2 C1 D2 E1 G2 G1 LVDSL_1P/DQ1L0 LVDSL_2N/DQ1L1 LVDSL_3P/DQ1L2 LVDSL_4N/DQ1L3 LVDSL_5P/DQ1L4 LVDSL_5N/DQ1L5 HSMC_D1 D3 DQS2L BANK 1 HSMC_TX_n4 HSMC_RX_p4 FLASH_SRAM_DQ1 FLASH_CE_n IO/nRESET C3 B1 C2 LVDSL_1N LVDSL_2P IO1_0 H6 D1 E2 LVDSL_3N/DATA1 CLK0/LVDSCLK0p LVDSL_4P/FLASH_nCE CLK1/LVDSCLK0n F2 F1 FLASH_RESET_n HSMC_D0 KEY1 KEY0 HSMC_TX_p6 HSMC_TX_n6 HSMC_RX_p6 HSMC_TX_p8 HSMC_TX_p7 HSMC_TX_n7 HSMC_RX_p7 HSMC_RX_n7 HSMC_RX_p8 HSMC_RX_n8 HSMC_TX_p9 HSMC_RX_p9 HSMC_RX_n9 HSMC_D2 HSMC_RX_n6 K2 K1 K5 LVDSL_7P/DQ1L6 LVDSL_7N/DQ1L7 LVDSL_8P/DQ1L8 LVDSL_11N M1 LVDSL_13N R1 M2 LVDSL_11P/DQS1L LVDSL_15P R5 L2 L1 L4 L3 P2 P1 R2 T3 R3 M5 L5 LVDSL_9P/DQ3L0 LVDSL_9N/DQ3L1 LVDSL_10P/DQ3L2 LVDSL_10N/DQ3L3 LVDSL_12P/DQ3L4 LVDSL_12N/DQ3L5 BANK 2 LVDSL_13P/DQ3L6 IO2_0 LVDSL_14P/DQ3L7 LVDSL_14N/DQ3L8 IO/RUP1 IO/RDN1 DQS3L CLK2/LVDSCLK1p LVDSL_8N/DM1L CLK3/LVDSCLK1n L6 T2 T1 N2 N1 HSMC_TX_n8 HSMC_TX_n9 HSMC_TX_p15 HSMC_D3 HSMC_D7 HSMC_D4 CPU_RST_n C HSMC_RX_n5 H1 LVDSL_6N IO/VREF0B1 F3 HSMC_SCL HSMC_TX_n15 R4 LVDSL_15N/DM3L IO/VREF0B2 M3 HSMC_D5 EP3C25F324 EP3C25F324 B B A A Title Altera Cyclone III Eval Board Size Document Number B EP2C35 BANK1(I/O : 2.5V) and BANK 2(I/O : 2.5V) Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 4 of 17 5 4 3 2 1 5 4 3 2 1 D D LED[0..3] DDR_DQ[0..15] DDR_A[0..12] HSMC_D[0..19] HSMC_RX_p[4..16] HSMC_RX_n[4..16] U1C U1D C DDR_A6 DDR_A3 DDR_DQ7 DDR_DQ6 DDR_DQ5 DDR_DQ4 DDR_DQ2 DDR_DQ3 DDR_DQ1 DDR_DQ0 DDR_DQS0 DDR_DQS1 P6 DQS1B U8 V7 V6 U6 P9 R8 V5 V4 U4 LVDSB_12P/DQ3B0 LVDSB_11N/DQ3B1 LVDSB_10N/DQ3B2 LVDSB_10P/DQ3B3 LVDSB_9N/DQ3B4 LVDSB_8P/DQ3B5 LVDSB_7N/DQ3B6 LVDSB_6N/DQ3B7 LVDSB_6P/DQ3B8 U3 LVDSB_5P/DQS3B T8 LVDSB_8N/DQS5B LVDSB_11P U7 DDR_A2 DDR_CKE R13 LVDSB_23N/DQS0B LED1 P12 DQS2B DDR_A9 V13 LVDSB_16N/DQS4B DDR_RAS_n DDR_DQ13 DDR_DQ11 DDR_DQ15 DDR_DQ12 DDR_DQ14 DDR_DQ8 DDR_DQ9 DDR_DQ10 V16 R11 V15 V14 U14 P10 U13 U12 U11 LVDSB_20N/DQ5B0 DQ5B1 LVDSB_19N/DQ5B2 LVDSB_18N/DQ5B3 LVDSB_18P/DQ5B4 LVDSB_17P/DQ5B5 LVDSB_16P/DQ5B6 LVDSB_14P/DQ5B7 LVDSB_13P/DQ5B8 LVDSB_24N LVDSB_25P LVDSB_25N N12 M13 N13 LED2 HSMC_RX_p16 HSMC_RX_n16 C DDR_DM0 V3 LVDSB_5N/DM3B BANK 3 DDR_BA0 V11 LVDSB_13N BANK 4 DDR_DM1 V8 LVDSB_12N/DM5B DDR_BA1 V12 LVDSB_14N DDR_A0 DDR_CS_n HSMC_RX_p15 HSMC_RX_n15 DDR_CAS_n HSMC_D6 DDR_A1 U1 V1 M6 N6 T4 LVDSB_1P LVDSB_1N LVDSB_2P LVDSB_2N LVDSB_3P N7 LVDSB_4N U5 LVDSB_7P IO3_0 IO3_1 IO3_2 N8 N9 P7 CLK15/LVDSCLK6p CLK14/LVDSCLK6n U9 V9 PLL1_OUTp PLL1_OUTn U2 V2 HSMC_D8 LED3 DDR_A5 LINK_D0 50MHz DDR_CLK_p DDR_CLK_n HSMC_D18 DDR_WE_n DDR_A12 HSMC_D12 HSMC_D14 DDR_A10 DDR_A11 P11 LVDSB_17N U15 LVDSB_19P U16 LVDSB_20P N10 N11 U17 V17 LVDSB_21P LVDSB_21N LVDSB_22P LVDSB_22N IO/RUP2 IO/RDN2 T13 T14 DDR_A8 DDR_A7 CLK13/LVDSCLK7p CLK12/LVDSCLK7n U10 V10 LINK_D1 LINK_D2 PLL4_OUTp PLL4_OUTn U18 V18 HSMC_CLKOUT_p2 HSMC_CLKOUT_n2 DDR_A4 P8 LVDSB_9P IO/VREF0B3 T6 VCC125 LED0 P13 LVDSB_24P IO/VREF0B4 T11 VCC125 B B EP3C25F324 EP3C25F324 LED3 TP 0 LINK_D3 A 5 VCC125 BC1 BC2 0.001U 0.1U 4 3 VCC125 BC3 BC4 0.001U 0.1U A Title Altera Cyclone III Eval Board Size Document Number B EP2C35 BANK3(I/O : 2.5V) and BANK 4(I/O : 3.3V) Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 5 of 17 2 1 5 4 3 2 1 D D HSMC_D[0..19] FLASH_SRAM_A[1..25] HSMC_CLKIN_p[1..2] HSMC_CLKIN_n[1..2] HSMC_RX_p[4..16] HSMC_RX_n[4..16] HSMC_TX_p[4..16] HSMC_TX_n[4..16] U1E U1F C HSMC_D16 K17 HSMC_RX_p12 L16 HSMC_RX_p11 K18 HSMC_RX_n12 M17 HSMC_TX_p13 L14 HSMC_TX_n13 L15 HSMC_RX_p13 L13 HSMC_RX_n13 M14 HSMC_TX_p14 P17 HSMC_TX_n14 P18 HSMC_TX_p16 T17 HSMC_D19 T16 HSMC_TX_n16 T18 HSMC_D15 N15 LVDSR_7N/DQ1R8 LVDSR_9P/GLOBNRS LVDSR_9N/GLOBNZ LVDSR_10P/DQS1R LVDSR_14P LVDSR_8P/DM1R LVDSR_14N LVDSR_10N/DQ3R0 LVDSR_11P/DQ3R1 LVDSR_11N/DQ3R2 LVDSR_12P/DQ3R3 LVDSR_12N/DQ3R4 BANK 5 LVDSR_13P/DQ3R5 LVDSR_13N/DQ3R6 LVDSR_15P/DQ3R7 RUP3/DQ3R8 IO/RDN3 LVDSR_15N/DQS3R CLK6/LVDSCLK3p DM3R CLK7/LVDSCLK3n L17 HSMC_TX_p12 M18 HSMC_TX_n12 R17 HSMC_RX_p14 R18 HSMC_RX_n14 R16 HSMC_D17 N17 HSMC_CLKIN_p2 N18 HSMC_CLKIN_n2 FLASH_SRAM_A22 C17 FLASH_SRAM_A23 C18 FLASH_SRAM_A24 G14 FLASH_WAIT H13 FLASH_ADV_n H14 FLASH_OE_n D17 FLASH_WE_n D18 HSMC_TX_p11 H17 HSMC_D11 H16 FLASH_SRAM_A21 B18 FLASH_SRAM_A25 B17 HSMC_TX_p10 E17 HSMC_TX_n10 E18 HSMC_RX_p10 G17 HSMC_RX_n10 G18 LVDSR_2P/PADD21/DQ1R0 LVDSR_2N/PADD22/DQ1R1 PADD23/DQ1R2 RDY/DQ1R3 nAVD/DQ1R4 LVDSR_3P/nOE/DQ1R5 LVDSR_3N/nWE/DQ1R6 LVDSR_6P/DQ1R7 DQS0R BANK 6 LVDSR_1N/PADD20/DQS2R LVDSR_1P LVDSR_4P/CLKUSR IO6_0 LVDSR_4N/nCEO LVDSR_5P/CRC_ERRORCLK4/LVDSCLK2p LVDSR_5N/INIT_DONE CLK5/LVDSCLK2n J13 HSMC_D10 F17 HSMC_CLKIN_p1 F18 HSMC_CLKIN_n1 C HSMC_RX_n11 L18 LVDSR_8N IO/VREF0B5 N16 HSMC_D13 HSMC_TX_n11 H18 LVDSR_6N IO/VREF0B6 H15 HSMC_D9 EP3C25F324 EP3C25F324 B B A A Title Altera Cyclone III Eval Board Size Document Number B EP2C35 BANK5 AND BANK 6(to HSMC, I/O Optional) Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 6 of 17 5 4 3 2 1 5 4 3 2 1 D D FLASH_SRAM_A[1..25] SRAM_BE_n[0..3] FLASH_SRAM_DQ[0..31] KEY[2..3] U1G U1H C FLASH_SRAM_DQ23 D16 FLASH_SRAM_A5 B15 FLASH_SRAM_A13 B11 FLASH_SRAM_DQ25 A18 FLASH_SRAM_A1 E12 FLASH_SRAM_A3 B16 FLASH_SRAM_A4 A15 FLASH_SRAM_A7 B14 FLASH_SRAM_A6 A14 FLASH_SRAM_A9 B13 FLASH_SRAM_A10 A12 FLASH_SRAM_A12 A11 LVDST_23P/DQS0T LVDST_17P/PADD4/DQS2T LVDST_23N LVDST_24P LVDST_24N LVDST_13P/PADD12/DQS4T LVDST_22N/DQ5T0 LVDST_20P/PADD0/DQ5T1 LVDST_19P/PADD2/DQ5T2 LVDST_17N/PADD3/DQ5T3 LVDST_16P/PADD6/DQ5T5 LVDST_16N/PADD5/DQ5T4 LVDST_15P/PADD8/DQ5T6 LVDST_14N/PADD9/DQ5T7 LVDST_13N/PADD11/DQ5T8 C16 FLASH_SRAM_DQ16 G13 SRAM_WE_n F13 SRAM_BE_n3 FLASH_SRAM_DQ12 D5 DATA12/DQS1T FLASH_SRAM_A17 FLASH_SRAM_DQ2 FLASH_SRAM_A19 FLASH_SRAM_DQ4 FLASH_SRAM_A20 FLASH_SRAM_DQ5 FLASH_SRAM_DQ6 FLASH_SRAM_DQ7 FLASH_SRAM_DQ9 C9 A8 A7 B7 A6 C5 E8 A4 E7 LVDST_11N/PADD16/DQ3T0 LVDST_10N/DATA2/DQ3T1 LVDST_9N/PADD18/DQ3T2 LVDST_9P/DATA4/DQ3T3 LVDST_8N/PADD19/DQ3T4 DATA5/DQ3T5 LVDST_6P/DATA6/DQ3T6 LVDST_5N/DATA7/DQ3T7 LVDST_4N/DATA9/DQ3T8 FLASH_SRAM_DQ14 A5 LVDST_7N/DATA14/DQS3T FLASH_SRAM_DQ10 A3 LVDST_3N/DATA10/DM3T C FLASH_SRAM_A14 C10 BANK 7 LVDST_12N/PADD13/DM5T FLASH_SRAM_A18 D9 LVDST_11P/PADD17/DQS5T B FLASH_SRAM_A15 D10 LVDST_12P/PADD14 FLASH_SRAM_A11 B12 LVDST_14P/PADD10 FLASH_SRAM_A8 A13 LVDST_15N/PADD7 SRAM_BE_n0 SRAM_BE_n1 F10 F11 LVDST_18P LVDST_18N FLASH_SRAM_A2 A16 LVDST_19N/PADD1 SRAM_BE_n2 F12 LVDST_21P IO/RUP4 IO/RDN4 IO7_0 IO7_1 CLK9/LVDSCLK5p CLK8/LVDSCLK5n PLL2_OUTp PLL2_OUTn E14 FLASH_SRAM_DQ21 E13 FLASH_SRAM_DQ20 C12 FLASH_SRAM_DQ24 E11 FLASH_SRAM_DQ18 B10 KEY3 A10 KEY2 D14 HSMC_CLKOUT_p1 C14 HSMC_CLKOUT_n1 SRAM_ADSC_n FLASH_SRAM_DQ29 FLASH_SRAM_DQ11 FLASH_SRAM_DQ26 FLASH_SRAM_DQ8 SRAM_CE1_n FLASH_SRAM_DQ13 FLASH_SRAM_DQ15 F7 E6 B3 F8 B4 F9 B5 B6 LVDST_2P BANK 8 IO/PADD15 LVDST_2N LVDST_3P/DATA11 IO8_0 IO8_1 LVDST_4P IO8_2 IO8_3 LVDST_5P/DATA8 CLK11LVDSCLK4p LVDST_6N CLK10/LVDSCLK4n LVDST_7P/DATA13 PLL3_OUTp LVDST_8P/DATA15 PLL3_OUTn E10 FLASH_SRAM_A16 D7 FLASH_SRAM_DQ27 E9 SRAM_OE_n F6 FLASH_SRAM_DQ28 G6 FLASH_SRAM_DQ30 B9 50MHz A9 HSMC_CLKIN0 A2 SRAM_CLK A1 HSMC_CLKOUT0 B FLASH_SRAM_DQ22 A17 LVDST_22P IO/VREF0B7 D12 FLASH_SRAM_DQ17 FLASH_SRAM_DQ3 B8 LVDST_10P/DATA3 IO/VREF0B8 C7 FLASH_SRAM_DQ31 EP3C25F324 EP3C25F324 A A Title Altera Cyclone III Eval Board Size Document Number B EP2C35 BANK7 AND BANK 8 Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 7 of 17 5 4 3 2 1 5 4 3 2 1 VCC25 D4 D6 D8 D11 D13 D15 F16 G15 J15 K15 M15 R15 R10 R12 R14 R6 R7 R9 K4 M4 N4 F4 G4 J4 D U1I D VCC12 VCCIO8 VCCIO8 VCCIO8 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 VCCIO5 VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO1 VCCIO1 VCCIO1 VCC12 VCC12 P4 E15 F5 P15 VCCD1 VCCD2 VCCD3 VCCD4 G7 VCCINT VSSN VSSN VSSN VSSN VSSN VSSN C4 C6 C8 C11 C13 C15 C1 100U BC5 0.1U BC6 0.1U BC7 0.1U BC8 0.1U BC9 0.1U BC10 0.1U BC11 0.1U BC12 0.1U BC13 0.1U BC14 0.1U BC15 0.1U G8 VCCINT VSSN E3 C G10 G11 G12 H7 H12 J7 J12 K7 K12 L7 L12 M7 M8 M9 M11 M12 VCC25 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT EP3C25F324 VSSN VSSN VSSN VSSN E16 G3 G16 J3 VSSN VSSN VSSN VSSN VSSN VSSN VSSN VSSN VSSN VSSN VSSN VSSN VSSN J16 K3 K16 M16 N3 P3 P16 T5 T7 T9 T10 T12 T15 VCC25 BC16 BC17 BC18 BC19 BC20 BC21 BC22 BC23 BC24 BC25 BC26 BC27 BC28 BC29 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U C N5 F14 E4 N14 VCCA1 VCCA2 VCCA3 VCCA4 VSSA1 VSSA2 VSSA3 VSSA4 P5 F15 E5 P14 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS G9 H8 H9 H10 H11 J8 J9 J10 J11 K8 K9 K10 K11 L8 L9 L10 L11 M10 B CIII_TCK CIII_TMS CIII_TDI CIII_TDO FLASH_CLK nSTATUS nCONFIG nCE U1J J1 J2 J6 J5 TCK TMS TDI TDO H4 DCLK G5 nSTATUS H5 nCONFIG K6 nCE VCC25 MSEL0 MSEL1 MSEL2 MSEL3 K13 J18 J17 J14 IO/DATA0 H3 CONF_DONE K14 FLASH_SRAM_DQ0 CONF_DONE EP3C25F324 A 5 4 3 B A Title Altera Cyclone III Eval Board Size Document Number B EP2C35 POWER AND CONFIG Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 8 of 17 2 1 5 D C B 4 3 2 VCC33 BC30 1U BC31 0.1U BC32 0.01U Y1 1 EN VCC 4 2 GND OUT 3 50MHZ 50MHZ 1 VCC25 R2 5.1K JP2 SIP2 JTAG_TDO CIII_TDI JP1 SIP2 VCC25 LF_TCK LF_TMS LF_TDI LF_TDO CLOE : HSMC Programmable Disable 1 2 6 9 VCC33 U2 1 VCCA VCCB 14 2 13 3 12 4 11 5 10 8 EN NC GND 7 ADG3304 HSMC_TCK HSMC_TMS HSMC_TDI HSMC_TDO 1 D C B 2 A A Title Altera Cyclone III Eval Board Size Document Number A CLOCK and Level Shift Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 9 of 17 5 4 3 2 1 5 D LED[0..3] C RN3 120 LED0 5 4 LED1 6 3 LED2 7 2 LED3 8 1 B A 5 4 3 2 1 VCC25 5 6 7 8 KEY[0..3] Button1 4 3 1 2 TACT SW LEDB VCC33 LED1 LEDB LED2 LEDB LED3 LEDB LED4 Button2 4 3 1 2 TACT SW Button3 4 3 1 2 TACT SW VCC25 Button4 4 3 1 2 TACT SW R1 100K CPU_RESET 4 3 1 2 TACT SW Reconfigure 4 3 1 2 TACT SW RST_n CONF C37 C38 1U 1U 4 1 2 RN1 D 100K 4 3 C2 C3 C4 C5 1U 1U 1U 1U U3 GND OE 10 19 KEYIN0 KEYIN1 KEYIN2 KEYIN3 RST_n CONF 9 8 7 6 A8 A7 A6 A5 5 4 3 2 A4 A3 A2 A1 B8 B7 B6 B5 11 12 13 14 B4 B3 B2 B1 15 16 17 18 VCC25 1 20 DIR VCC 74HC245 CPU_RST_n nCONFIG C RN2 4 3 2 1 120 5 6 7 8 KEY0 KEY1 KEY2 KEY3 R60 100K CPU_RST_n R61 100K nCONFIG B A Title Altera Cyclone III Eval Board Size Document Number A LED and TACT SW Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 10 of 17 3 2 1 5 D C B A 5 4 3 2 1 J1 HSMC_TCK HSMC_TDO HSMC_SDA HSMC_CLKOUT0 1 3 1 3 5 7 5 7 9 11 9 11 13 15 13 15 17 19 17 19 21 23 21 23 25 27 25 27 29 31 29 31 33 35 33 35 37 39 37 39 164 163 162 161 2 4 2 4 6 8 6 8 10 12 10 12 14 16 14 16 18 20 18 20 22 24 22 24 26 28 26 28 30 32 30 32 34 36 34 36 38 40 38 40 HSMC_SCL HSMC_CLKIN0 HSMC_TMS HSMC_TDI VCC33 HSMC_D0 HSMC_D2 HSMC_D4 HSMC_D6 HSMC_D8 HSMC_D10 HSMC_D12 HSMC_D14 HSMC_D16 HSMC_D18 HSMC_TX_p4 HSMC_TX_n4 HSMC_TX_p5 HSMC_TX_n5 HSMC_TX_p6 HSMC_TX_n6 HSMC_TX_p7 HSMC_TX_n7 HSMC_CLKOUT_p1 HSMC_CLKOUT_n1 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 169 170 171 172 169 170 171 172 HSMC_TX_p8 101 HSMC_TX_n8 103 105 HSMC_TX_p9 107 HSMC_TX_n9 109 111 HSMC_TX_p10 113 HSMC_TX_n10 115 117 HSMC_TX_p11 119 HSMC_TX_n11 121 123 HSMC_TX_p12 125 HSMC_TX_n12 127 129 HSMC_TX_p13 131 HSMC_TX_n13 133 135 HSMC_TX_p14 137 HSMC_TX_n14 139 141 HSMC_TX_p15 143 HSMC_TX_n15 145 147 HSMC_TX_p16 149 HSMC_TX_n16 151 153 HSMC_CLKOUT_p2 155 HSMC_CLKOUT_n2 157 159 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 172 171 170 169 168 167 166 165 161 162 163 164 161 162 163 164 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 HSMC_D1 HSMC_D3 HSMC_D5 12V HSMC_D7 HSMC_D9 HSMC_D11 HSMC_D13 HSMC_D15 HSMC_D17 HSMC_D19 HSMC_RX_p4 HSMC_RX_n4 HSMC_RX_p5 HSMC_RX_n5 HSMC_RX_p6 HSMC_RX_n6 HSMC_RX_p7 HSMC_RX_n7 HSMC_CLKIN_p1 HSMC_CLKIN_n1 165 166 167 168 165 166 167 168 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 HSMC_RX_p8 HSMC_RX_n8 HSMC_RX_p9 HSMC_RX_n9 HSMC_RX_p10 HSMC_RX_n10 HSMC_RX_p11 HSMC_RX_n11 HSMC_RX_p12 HSMC_RX_n12 HSMC_RX_p13 HSMC_RX_n13 HSMC_RX_p14 HSMC_RX_n14 HSMC_RX_p15 HSMC_RX_n15 HSMC_RX_p16 HSMC_RX_n16 HSMC_CLKIN_p2 HSMC_CLKIN_n2 HSMC_PSNT_n QSH-090-ALTERA 4 3 D HSMC_D[0..19] HSMC_TX_p[4..16] HSMC_TX_n[4..16] HSMC_RX_p[4..16] HSMC_RX_n[4..16] HSMC_CLKOUT_p[1..2] HSMC_CLKOUT_n[1..2] HSMC_CLKIN_p[1..2] HSMC_CLKIN_n[1..2] C HSMC_CLKIN_p1 R3 100 HSMC_CLKIN_n1 HSMC_CLKIN_p2 R4 100 HSMC_CLKIN_n2 VCC33 B R5 120 HSMC_PSNT_n LINK LEDB HSMC_SDA HSMC_SCL SDA SIP SCL SIP 12V 12V TC1 C6 47U/16V 10U BC33 0.1U BC34 0.1U BC35 0.1U BC36 0.001U BC37 0.001U BC38 0.001U VCC33 C7 100U BC39 0.1U BC40 0.1U BC41 0.1U BC42 0.001U BC43 0.001U BC44 0.001U A Title Altera Cyclone III Eval Board Size Document Number C High Speed Mezzanine (HSM) Interface and GPIO Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 11 of 17 2 1 5 4 3 2 1 Place these resistors as Place the pull up resistors just DDR_CLK_p R6 24.9 DDR_CK_p R8 100 close to the PLD U2 as past U2 so that each trace DDR_CLK_n R7 24.9 DDR_CK_n possible tags the pin that it is routed to and then goes through the resistor to VTT_DDR D D VCC125 VCC125 VCC25 DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 RN4 16 15 14 13 12 11 10 9 10 1 2 3 4 5 6 7 8 DDR_data0 DDR_data1 DDR_data2 DDR_data3 DDR_data4 DDR_data5 DDR_data6 DDR_data7 RN9 16 15 14 13 12 11 10 9 56 1 2 3 4 5 6 7 8 1 8 2 7 3 6 4 5 CN1 0.1U DDR_DQ[0..15] DDR_A[0..12] RN5 10 RN10 56 VCC125 DDR_DQ8 9 8 DDR_data8 9 8 3 9 15 55 61 1 18 33 DDR_DQ9 10 7 DDR_data9 10 7 5 6 7 8 U4 DDR_DQ10 11 6 DDR_data10 11 6 C VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ DDR_addr0 DDR_addr1 DDR_addr2 DDR_addr3 DDR_addr4 DDR_addr5 DDR_addr6 DDR_addr7 DDR_addr8 DDR_addr9 DDR_addr10 DDR_addr11 DDR_addr12 DDR_CK_p DDR_CK_n 29 30 31 32 35 36 37 38 39 40 28 41 42 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 45 46 CK CK_n DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 DDR_data0 DDR_data1 DDR_data2 DDR_data3 DDR_data4 DDR_data5 DDR_data6 DDR_data7 DDR_data8 DDR_data9 DDR_data10 DDR_data11 DDR_data12 DDR_data13 DDR_data14 DDR_data15 DDR_DQ11 12 5 DDR_data11 12 5 DDR_DQ12 13 4 DDR_data12 13 4 DDR_DQ13 14 3 DDR_data13 14 3 DDR_DQ14 15 2 DDR_data14 15 2 DDR_DQ15 16 1 DDR_data15 16 1 DDR_A12 DDR_A11 DDR_A9 DDR_A8 DDR_A7 DDR_A6 DDR_A5 DDR_A4 RN6 16 15 14 13 12 11 10 9 22 1 2 3 4 5 6 7 8 DDR_addr12 DDR_addr11 DDR_addr9 DDR_addr8 DDR_addr7 DDR_addr6 DDR_addr5 DDR_addr4 RN11 56 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 1 8 1 2 7 2 3 6 3 4 5 4 CN2 0.1U VCC125 CN3 0.1U C R9 10K DDR_CLKEN 44 DDR_WRITE_n 21 DDR_COL_n 22 DDR_ROW_n 23 DDR_CHIPSEL_n 24 CKE WE_n CAS_n A2S56D40CTP-G5PP RAS_n CS_n DDR_CS_n DDR_BA0 RN7 22 RN12 56 16 1 DDR_CHIPSEL_n 16 1 15 2 DDR_BANK0 15 2 VCC125 DDR_LDMASK DDR_UDMASK DDR_LSTROBE DDR_USTROBE 20 47 16 51 LDM UDM LDQS UDQS B 5 6 7 8 DDR_BA1 14 3 DDR_BANK1 14 3 DDR_A10 13 4 DDR_addr10 13 4 DDR_A0 12 5 DDR_addr0 12 5 CN4 DDR_A1 11 6 DDR_addr1 11 6 DDR_A2 10 7 DDR_addr2 10 7 0.1U B DDR_BANK0 DDR_BANK1 VCC125 26 27 BA0 BA1 19 50 DNU1 DNU0 49 VREF1 NC0 NC1 NC2 NC3 NC4 14 17 25 43 53 DDR_A3 9 8 DDR_addr3 9 8 DDR_RAS_n DDR_CAS_n DDR_WE_n RN8 9 10 11 22 8 7 6 DDR_ROW_n DDR_COL_n DDR_WRITE_n RN13 56 9 8 10 7 11 6 1 2 3 VCC125 4 VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS 5 6 7 8 BC45 BC46 0.001U 0.1U DDR 4Mx16x4 34 48 66 6 12 52 58 64 DDR_DM1 12 5 DDR_UDMASK 12 5 DDR_DQS0 13 4 DDR_LSTROBE 13 4 DDR_CKE 14 3 DDR_CLKEN 14 3 DDR_DM0 15 2 DDR_LDMASK 15 2 CN5 0.1U DDR_DQS1 16 1 DDR_USTROBE 16 1 4 3 2 1 VCC25 VCC25 A C8 BC47 BC48 BC49 BC50 BC51 BC52 BC53 BC54 10U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 5 4 3 A Title Altera Cyclone III Eval Board Size Document Number B DDR SDRAM Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 12 of 17 2 1 5 4 3 2 1 D FLASH_SRAM_DQ[0..31] FLASH_SRAM_A[2..22] SRAM_BE_n[0..3] VCC33 VCC25 RN14 22 SRAM_data0 16 SRAM_data1 15 1 FLASH_SRAM_DQ0 2 FLASH_SRAM_DQ1 SRAM_data2 14 SRAM_data3 13 SRAM_data4 12 SRAM_data5 11 SRAM_data6 10 SRAM_data7 9 3 FLASH_SRAM_DQ2 4 FLASH_SRAM_DQ3 5 FLASH_SRAM_DQ4 6 FLASH_SRAM_DQ5 7 FLASH_SRAM_DQ6 8 FLASH_SRAM_DQ7 Place these terminations in the middle of the line RN15 22 SRAM_data8 16 SRAM_data9 15 SRAM_data10 14 SRAM_data11 13 SRAM_data12 12 SRAM_data13 11 SRAM_data14 10 SRAM_data15 9 1 FLASH_SRAM_DQ8 2 FLASH_SRAM_DQ9 3 FLASH_SRAM_DQ10 4 FLASH_SRAM_DQ11 5 FLASH_SRAM_DQ12 6 FLASH_SRAM_DQ13 7 FLASH_SRAM_DQ14 8 FLASH_SRAM_DQ15 RN18 22 SRAM_addr21 9 8 FLASH_SRAM_A21 SRAM_addr22 10 7 FLASH_SRAM_A22 SRAM_addr2 11 6 FLASH_SRAM_A2 SRAM_addr3 12 5 FLASH_SRAM_A3 SRAM_addr4 13 4 FLASH_SRAM_A4 SRAM_addr5 14 3 FLASH_SRAM_A5 SRAM_addr6 15 2 FLASH_SRAM_A6 SRAM_addr7 16 1 FLASH_SRAM_A7 D RN19 22 SRAM_addr14 9 8 SRAM_addr13 10 7 SRAM_addr12 11 6 SRAM_addr11 12 5 SRAM_addr10 13 4 SRAM_addr9 14 3 SRAM_addr8 15 2 SRAM_addr19 16 1 FLASH_SRAM_A14 FLASH_SRAM_A13 FLASH_SRAM_A12 FLASH_SRAM_A11 FLASH_SRAM_A10 FLASH_SRAM_A9 FLASH_SRAM_A8 FLASH_SRAM_A19 Place these terminations in the middle of the line 4 11 20 27 54 61 70 77 15 41 65 91 U5 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDD VDD VDD VDD RN16 22 RN20 22 C B SRAM_addr2 37 SRAM_addr3 36 SRAM_addr4 35 SRAM_addr5 34 SRAM_addr6 33 SRAM_addr7 32 SRAM_addr8 44 SRAM_addr9 45 SRAM_addr10 46 SRAM_addr11 47 SRAM_addr12 48 SRAM_addr13 49 SRAM_addr14 50 SRAM_addr15 81 SRAM_addr16 82 SRAM_addr17 99 SRAM_addr18 100 SRAM_addr19 43 SRAM_addr20 42 SRAM_addr21 39 SRAM_addr22 38 SRAM_mode 31 SRAM_zz 64 SRAM_outen_n 86 SRAM_clock 89 SRAM_globalw_n 88 SRAM_writeen_n 87 SRAM_advance_n 83 SRAM_adsconttroler_n85 SRAM_adsprocessor_n84 SRAM_chipen1_n 98 SRAM_chipen2 97 SRAM_chipen3_n 92 SRAM_byteen_n0 93 SRAM_byteen_n1 94 SRAM_byteen_n2 95 SRAM_byteen_n3 96 14 16 66 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 NC/A19 NC/A20 SSRAM 256Kx36 IS61LPS25636A-200TQLI MODE ZZ OE_n CLK GW_n BWE_n ADV_n ADSC_n ADSP_n CE1_n CE2 CE3_n BWA_n BWB_n BWC_n BWD_n NC0 NC1 NC2 DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQPA 52 53 56 57 58 59 62 63 51 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQPB 68 69 72 73 74 75 78 79 80 DQC0 DQC1 DQC2 DQC3 DQC4 DQC5 DQC6 DQC7 DQPC 2 3 6 7 8 9 12 13 1 DQD0 DQD1 DQD2 DQD3 DQD4 DQD5 DQD6 DQD7 DQPD 18 19 22 23 24 25 28 29 30 SRAM_data0 SRAM_data1 SRAM_data2 SRAM_data3 SRAM_data4 SRAM_data5 SRAM_data6 SRAM_data7 SRAM_data8 SRAM_data9 SRAM_data10 SRAM_data11 SRAM_data12 SRAM_data13 SRAM_data14 SRAM_data15 SRAM_data16 SRAM_data17 SRAM_data18 SRAM_data19 SRAM_data20 SRAM_data21 SRAM_data22 SRAM_data23 SRAM_data24 SRAM_data25 SRAM_data26 SRAM_data27 SRAM_data28 SRAM_data29 SRAM_data30 SRAM_data31 SRAM_data16 8 SRAM_data17 7 SRAM_data18 6 SRAM_data19 5 SRAM_data20 4 SRAM_data21 3 SRAM_data22 2 SRAM_data23 1 9 FLASH_SRAM_DQ16 10 FLASH_SRAM_DQ17 11 FLASH_SRAM_DQ18 12 FLASH_SRAM_DQ19 13 FLASH_SRAM_DQ20 14 FLASH_SRAM_DQ21 15 FLASH_SRAM_DQ22 16 FLASH_SRAM_DQ23 RN17 22 SRAM_data24 8 SRAM_data25 7 SRAM_data26 6 SRAM_data27 5 SRAM_data28 4 SRAM_data29 3 SRAM_data30 2 SRAM_data31 1 9 FLASH_SRAM_DQ24 10 FLASH_SRAM_DQ25 11 FLASH_SRAM_DQ26 12 FLASH_SRAM_DQ27 13 FLASH_SRAM_DQ28 14 FLASH_SRAM_DQ29 15 FLASH_SRAM_DQ30 16 FLASH_SRAM_DQ31 SRAM_byteen_n0 8 SRAM_byteen_n1 7 SRAM_byteen_n2 6 SRAM_byteen_n3 5 4 SRAM_chipen1_n 3 SRAM_addr17 2 SRAM_addr18 1 9 SRAM_BE_n0 10 SRAM_BE_n1 11 SRAM_BE_n2 12 SRAM_BE_n3 13 14 SRAM_CE1_n 15 FLASH_SRAM_A17 16 FLASH_SRAM_A18 RN21 22 SRAM_addr15 8 SRAM_addr16 7 9 FLASH_SRAM_A15 10 FLASH_SRAM_A16 6 11 5 SRAM_adsconttroler_n 4 SRAM_outen_n 3 SRAM_writeen_n 2 SRAM_clock 1 12 13 SRAM_ADSC_n 14 SRAM_OE_n 15 SRAM_WE_n 16 SRAM_CLK SRAM_addr20 R10 22 FLASH_SRAM_A20 SRAM_chipen2 SRAM_globalw_n VCC25 R11 5.1K R12 5.1K C B VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS SRAM_mode SRAM_zz 5 10 21 26 55 60 71 76 17 40 67 90 SRAM_chipen3_n R13 5.1K R14 5.1K R15 5.1K VCC33 A VCC25 VCC33 BC55 BC56 BC57 BC58 BC59 BC60 BC61 BC62 BC63 BC64 BC65 BC66 C9 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 10U SRAM_OE_n R16 SRAM_CE1_n R17 SRAM_advance_n R18 5.1K 5.1K 5.1K VCC25 SRAM_adsprocessor_n R19 5.1K 5 4 3 A Title Altera Cyclone III Eval Board Size Document Number B SSRAM 512Kx36bit Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 13 of 17 2 1 5 4 3 2 1 VCC18 VCC25 FLASH_SRAM_DQ[0..15] A6 H3 D5 D6 G4 FLASH_SRAM_A[1..25] U6 VCC VCC VCCQ VCCQ VCCQ D C VCC25 FLASH_SRAM_A1 A1 FLASH_SRAM_A2 B1 FLASH_SRAM_A3 C1 FLASH_SRAM_A4 D1 FLASH_SRAM_A5 D2 FLASH_SRAM_A6 A2 FLASH_SRAM_A7 C2 FLASH_SRAM_A8 A3 FLASH_SRAM_A9 B3 FLASH_SRAM_A10 C3 FLASH_SRAM_A11 D3 FLASH_SRAM_A12 C4 FLASH_SRAM_A13 A5 FLASH_SRAM_A14 B5 FLASH_SRAM_A15 C5 FLASH_SRAM_A16 D7 FLASH_SRAM_A17 D8 FLASH_SRAM_A18 A7 FLASH_SRAM_A19 B7 FLASH_SRAM_A20 C7 FLASH_SRAM_A21 C8 FLASH_SRAM_A22 A8 FLASH_SRAM_A23 G1 FLASH_SRAM_A24 H8 FLASH_SRAM_A25 B6 A1 DQ0 A2 DQ1 A3 DQ2 A4 DQ3 A5 DQ4 A6 DQ5 A7 DQ6 A8 DQ7 A9 DQ8 A10 DQ9 A11 DQ10 A12 DQ11 A13 DQ12 A14 DQ13 A15 DQ14 A16 DQ15 A17 A18 A19 FLASH 32Mx16 A20 A21 A22 PC28F256P30B85 A23 A24 A25 F2 E2 G3 E4 E5 G5 G6 H7 E1 E3 F3 F4 F5 H5 G7 E7 FLASH_SRAM_DQ0 FLASH_SRAM_DQ1 FLASH_SRAM_DQ2 FLASH_SRAM_DQ3 FLASH_SRAM_DQ4 FLASH_SRAM_DQ5 FLASH_SRAM_DQ6 FLASH_SRAM_DQ7 FLASH_SRAM_DQ8 FLASH_SRAM_DQ9 FLASH_SRAM_DQ10 FLASH_SRAM_DQ11 FLASH_SRAM_DQ12 FLASH_SRAM_DQ13 FLASH_SRAM_DQ14 FLASH_SRAM_DQ15 D C B FLASH_CE_n R20 5.1K FLASH_WAIT FLASH_WP_n FLASH_CLK FLASH_RESET_n RN22 5.1K 8 1 7 2 6 3 5 4 VCC18 FLASH_CLK E6 FLASH_WAIT F7 FLASH_RESET_n D4 FLASH_ADV_n F6 FLASH_WE_n G8 FLASH_WP_n C6 FLASH_CE_n B4 FLASH_OE_n F8 FLASH_VPP A4 CLK WAIT RST# ADV# WE# WP# CE# OE# VPP RFU0 RFU1 RFU2 RFU3 RFU4 B8 E8 F1 G2 H1 B VSS VSS VSS VSS FLASH_ADV_n R21 5.1K B2 H2 H4 H6 A 5 VCC18 VCC25 VCC18 BC67 0.1U BC68 0.1U BC69 0.1U BC70 0.1U BC71 0.1U C10 10U 4 3 Title Size A Date: Altera Cyclone III Eval Board Document Number Intel FLASH 32Mx16bit Tuesday, April 17, 2007 2 Sheet 14 of 1 A Rev 1.2 17 5 4 3 2 1 SW1 12V 1 5 6 2V5 VCC25 4 2 D J2 D1 SM340A 3 REG1 1 2 D2 SM340A 3 POWER SW VIN VOUT DC_12V D3 SM340A C11 C12 C13 INTVCC R22 100K G12 PGOOD PLLIN A8 JP3 SIP2 1 2 D 2V5 RS1 10m VCC25 C14 C15 2.5V/6A D4 SM340A 10U 10U 10U R23 392K A12 MPGM A9 TRACK/SS BC72 OPT AGND 100U 100U AGND A7 INTVCC RUN A10 R26 100K 12V INTVCC E12 DRVCC R27 C12 MARG0 LTM4603EV-1 24K D12 MARG1 R24 OPT B12 FSET VOSNS-/NC1 M12 BC73 OPT A11 COMP VOSNS+/NC2 J12 Voltage setting R25 19.1K F12 VFB K12 DIFFVOUT_NC3 PGND SGND BC74 47P BC75 OPT L12 VO_LCL C 2V5 C AGND H12 AGND 2V5 1V25 VCC125 L1 0.47UH REG2 LTC3413 JP4 C16 C17 R28 4.7M R29 100K PVin SW 1 2 VCC125 10U 10U 1 SVin 2 4 Vfb C19 C20 SIP2 100U 100U 1.25V/500mA B PGood 7 Ith 3 Run/SS S B SGND PGND C18 330P 6 Vref RT 5 R31 5.1K SGND C22 S S R30 SGND SGND 309K C21 100P 2.2N S SGND A 5 FID1 FID2 FID3 FID4 FID5 FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FID6 FID7 FID8 FID9 FID10 FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL FIDUCIAL 4 GND1 GND2 GND3 GND4 GND5 MH1 MH2 MH3 MH4 MH5 MH6 GND GND GND GND GND GND GND GND GND GND GND 3 2 A Title Altera Cyclone III Eval Board Size Document Number B LTM4603EV-1 : 2.5V/6A, LTC3413EFE:1.25V +/-0.5A Date: Tuesday, April 17, 2007 Sheet 1 15 of Rev 1.2 17 5 D C B A 5 4 3 2 1 12V 4 4 GND BOOST 2 D D5 BAT54S 1 3 2 3V3 VCC33 C23 REG3 LT1959 L2 6.8UH 0.68U JP5 1 VIN Vsw 8 1 2 VCC33 6 SHDN 7 SYNC C24 FB 3 VC 5 R32 4.32K D6 R33 C25 2.49K C26 SIP2 TC2 R34 3.3V/3A 120 10U 1.5N SM340A 10U 220U/6.3V POWER LEDB 4 GND BOOST 2 C D7 BAT54S 2 3 1 REG4 1 VIN LT1959 Vsw 8 C27 L3 0.68U 6.8UH 1V2 VCC12 JP6 1 2 VCC12 6 SHDN 7 SYNC C28 FB 3 VC 5 D8 C29 R35 2.49K SIP2 RS2 10m 1.2V/3A C30 TC3 10U 1.5N SM340A 10U 220U/6.3V 4 GND BOOST 2 D9 BAT54S B 2 3 1 1V8 VCC18 C31 REG5 LT1959 L4 6.8UH 0.68U JP7 1 VIN Vsw 8 1 2 VCC18 6 SHDN FB 3 R36 1.21K SIP2 1.8V/1.5A 7 SYNC C32 VC 5 D10 R37 C33 2.49K TC4 10U 1.5N SM340A 220U/6.3V A Title Altera Cyclone III Eval Board Size Document Number B LT1959 : 3.3V/3A, 1.2V/3A, 1.8V/1.5A Rev 1.2 Date: Tuesday, April 17, 2007 Sheet 16 of 17 3 2 1 5 4 3 2 1 JP8 CLOSE: USB-Blaster Disable USB5V BC76 USB5V BC77 PWRON USBON 24MHz FP3V FLASH_CEn FLASH_CE_n LEDB R47 120 VCC33 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 L5 BEAD R38 330 0.1U 0.1U FP3V U7 L6 BEAD LOAD FP3V IO-A2 IO-A3 IO-A4 IO-A5 IO-A6 GNDIO IO-A7 IO-A8 IO-A9 VCCINT INPUT/OE2/GCLK2 INPUT/GCLRn INPUT/OE1 INPUT/GCLK1 GNDINT IO-H8 IO-H7 IO-H6 VCCIO IO-H5 IO-H4 IO-H3 GNDIO IO-H2 IO-H1 D BC78 BC79 BC80 BC81 D 5 6 1 3 2 1 3 2 J3 D+ D- 3 2 1 GND VBUS 4 USB B-TYPE 0.1U USB_DP USB_DM L7 BEAD D11 BAT54S 0.1U 0.1U 0.1U U8 13 30 3 26 FP3V R45 VCCIO AVCC VCC VCC R39 1.5K R40 22 R41 22 D12 BAT54S USB5V R43 6 3V3OUT 5 RSTOUT# 7 USBDP 8 USBDM 100K nRESET 27 XTIN FT245BL 28 XTOUT 4 RESET# D0 D1 D2 D3 D4 D5 D6 D7 25 24 23 22 21 20 19 18 RD# WR TXE# RXF# 16 15 14 12 120 ULED 6MHz LEDB ISP_TDI UD0 UD1 UD2 UD3 UD4 UD5 GND UD6 UD7 ISP_TMS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IO-A1 IO-A0 VCCIO TDI IO-B8 IO-B7 IO-B6 IO-B5 IO-B4 IO-B3 GNDIO IO-B2 IO-B1 IO-B0 15 16 17 18 19 TMS IO-C8 IO-C7 VCCIO IO-C6 EPM3128AT IO-H0 GNDIO TDO IO-G7 IO-G6 IO-G5 IO-G4 IO-G3 IO-G2 VCCIO GNDIO IO-G1 IO-G0 TCK 75 74 73 72 71 70 69 68 67 66 65 64 63 62 IO-F7 IO-F6 GNDIO IO-F5 IO-F4 61 60 59 58 57 ISP_TDO ISP_TCK BC82 0.1U USB5V USB5V C 6MHz R42 22 C35 2 1 32 31 EEDATA EESK EECS TEST SI/WU PWREN# 11 10 URD UWR TXE RXF 20 21 22 23 24 25 IO-C5 IO-C4 IO-C3 IO-C2 IO-C1 IO-C0 IO-F3 IO-F2 IO-F1 GNDIO IO-F0 VCCIO 56 55 54 53 52 51 C GNDIO IO-D8 IO-D7 IO-D6 IO-D5 IO-D4 IO-D3 GNDIO VCCIO IO-D2 IO-D1 IO-D0 GNDINT VCCINT IO-E0 IO-E1 IO-E2 GNDIO IO-E3 IO-E4 IO-E5 IO-E6 IO-E7 IO-E8 IO-E9 AGND GND GND 47P 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 29 9 17 1 ADJ/GND USB5V REG6 3 IN BC83 0.1U LT1117CST-3.3 VOUT OUT 4 2 USB3V C36 BC84 BC85 BC86 10U 0.1U 0.1U 0.1U RN23 U9 1 2 3 R44 1.5K 4 8 7 6 5 EEP_CS EEP_CLK EEP_DI EEP_DO 1 2 3 4 CS VCC CLK NC DI ORG DO GND 8 7 6 5 120 93LC46B USB5V BC87 0.1U FP3V R46 1.5K VCC33 TRGT_TCK TRGT_TDO TRGT_TMS TRGT_TDI FP_nCSO FP_TDI FP_nST FP_TCK VCC33 B RN25 VCC25 CONF_DONE 5 4 CONF 6 3 nSTATUS 7 2 nCE 8 1 10K USB3V R59 LF_EN JP8 10K 1 2 SIP2 A 5 VCC25 U10 JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO LINK_D1 LINK_D0 LINK_D3 LINK_D2 LF_EN 1 VCCA VCCB 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 EN GND 11 FP3V TRGT_TCK TRGT_TDO TRGT_TMS TRGT_TDI FP_nCSO FP_TDI FP_nST FP_TCK CONF_DONE R48 10K R49 R50 10K 120 Q5 8050 Q6 8050 CONF_DONE LEDB Q1 VCC33 VCC33 R51 2.2K ADG3308 JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO J4 1 2 3 4 5 6 7 8 9 10 JTAG USB3V VCC25 RN24 8 1 7 2 6 3 5 4 10K EEP_DI ISP_TCK ISP_TDO ISP_TMS EEP_DO ISP_TDI J5 12 34 56 78 9 10 CPLD ISP EEP_CLK EEP_CS FP3V VCC33 USB5V USB3V R52 1K FP3V 24MHz Y2 4 VCC EN 1 3 OUT GND 2 24MHZ BC96 0.1U BC88 0.1U BC89 0.1U BC90 0.1U BC91 0.1U BC92 0.1U BC93 0.1U BC94 0.1U 8550 FP3V USB3V Q3 8550 FP3V R53 R54 1K 10K PWRON Q2 8050 USB5V R55 4.7K R56 1K R57 R58 1K 10K USBON Q4 8050 BC95 Title 0.1U Altera Cyclone III Eval Board Size Document Number B USB BLASTER Date: Tuesday, April 17, 2007 Sheet 17 of 4 3 2 1 B A Rev 1.2 17

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