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    Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – 8K Bytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1K Byte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – Programming Lock for Software Security • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Three PWM Channels – 8-channel ADC in TQFP and QFN/MLF package Eight Channels 10-bit Accuracy – 6-channel ADC in PDIP package Six Channels 10-bit Accuracy – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and Packages – 23 Programmable I/O Lines – 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V (ATmega8L) – 4.5 - 5.5V (ATmega8) • Speed Grades – 0 - 8 MHz (ATmega8L) – 0 - 16 MHz (ATmega8) • Power Consumption at 4 Mhz, 3V, 25°C – Active: 3.6 mA – Idle Mode: 1.0 mA – Power-down Mode: 0.5 µA 8-bit with 8K Bytes In-System Programmable Flash ATmega8 ATmega8L Pin Configurations PDIP (RESET) PC6 1 (RXD) PD0 2 (TXD) PD1 3 (INT0) PD2 4 (INT1) PD3 5 (XCK/T0) PD4 6 VCC 7 GND 8 (XTAL1/TOSC1) PB6 9 (XTAL2/TOSC2) PB7 10 (T1) PD5 11 (AIN0) PD6 12 (AIN1) PD7 13 (ICP1) PB0 14 28 PC5 (ADC5/SCL) 27 PC4 (ADC4/SDA) 26 PC3 (ADC3) 25 PC2 (ADC2) 24 PC1 (ADC1) 23 PC0 (ADC0) 22 GND 21 AREF 20 AVCC 19 PB5 (SCK) 18 PB4 (MISO) 17 PB3 (MOSI/OC2) 16 PB2 (SS/OC1B) 15 PB1 (OC1A) TQFP Top View 32 PD2 (INT0) 31 PD1 (TXD) 30 PD0 (RXD) 29 PC6 (RESET) 28 PC5 (ADC5/SCL) 27 PC4 (ADC4/SDA) 26 PC3 (ADC3) 25 PC2 (ADC2) (INT1) PD3 1 (XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (XTAL1/TOSC1) PB6 7 (XTAL2/TOSC2) PB7 8 24 PC1 (ADC1) 23 PC0 (ADC0) 22 ADC7 21 GND 20 AREF 19 ADC6 18 AVCC 17 PB5 (SCK) (T1) PD5 9 (AIN0) PD6 10 (AIN1) PD7 11 (ICP1) PB0 12 (OC1A) PB1 13 (SS/OC1B) PB2 14 (MOSI/OC2) PB3 15 (MISO) PB4 16 MLF Top View 32 PD2 (INT0) 31 PD1 (TXD) 30 PD0 (RXD) 29 PC6 (RESET) 28 PC5 (ADC5/SCL) 27 PC4 (ADC4/SDA) 26 PC3 (ADC3) 25 PC2 (ADC2) (INT1) PD3 1 (XCK/T0) PD4 2 GND 3 VCC 4 GND 5 VCC 6 (XTAL1/TOSC1) PB6 7 (XTAL2/TOSC2) PB7 8 2 ATmega8(L) (T1) PD5 9 (AIN0) PD6 10 (AIN1) PD7 11 (ICP1) PB0 12 (OC1A) PB1 13 (SS/OC1B) PB2 14 (MOSI/OC2) PB3 15 (MISO) PB4 16 24 PC1 (ADC1) 23 PC0 (ADC0) 22 ADC7 21 GND 20 AREF 19 ADC6 18 AVCC 17 PB5 (SCK) NOTE: The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB. 2486T–AVR–05/08 ATmega8(L) Overview Block Diagram The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Figure 1. Block Diagram RESET VCC PC0 - PC6 PB0 - PB7 XTAL1 XTAL2 PORTC DRIVERS/BUFFERS PORTB DRIVERS/BUFFERS GND PORTC DIGITAL INTERFACE PORTB DIGITAL INTERFACE AGND AREF MUX & ADC ADC INTERFACE PROGRAM COUNTER STACK POINTER PROGRAM FLASH SRAM INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES AVR CPU GENERAL PURPOSE REGISTERS X Y Z ALU STATUS REGISTER PROGRAMMING LOGIC SPI + COMP. - INTERFACE TWI TIMERS/ COUNTERS OSCILLATOR INTERNAL OSCILLATOR WATCHDOG TIMER MCU CTRL. & TIMING INTERRUPT UNIT OSCILLATOR EEPROM USART PORTD DIGITAL INTERFACE PORTD DRIVERS/BUFFERS PD0 - PD7 3 2486T–AVR–05/08 Disclaimer The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Twowire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega8 AVR is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 4 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Pin Descriptions VCC Digital supply voltage. GND Ground. Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/ TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 58 and “System Clock and Clock Options” on page 25. Port C (PC5..PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated on page 61. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8 as listed on page 63. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed to generate a reset. 5 2486T–AVR–05/08 AVCC AREF ADC7..6 (TQFP and QFN/MLF Package Only) AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC. AREF is the analog reference pin for the A/D Converter. In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 6 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 7 2486T–AVR–05/08 About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 8 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) AVR CPU Core Introduction Architectural Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 2. Block Diagram of the AVR MCU Architecture Data Bus 8-bit Flash Program Memory Instruction Register Instruction Decoder Control Lines Program Counter Status and Control 32 x 8 General Purpose Registrers ALU Interrupt Unit SPI Unit Watchdog Timer Analog Comparator Direct Addressing Indirect Addressing Data SRAM EEPROM i/O Module1 i/O Module 2 i/O Module n I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers 9 2486T–AVR–05/08 can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 10 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Arithmetic Logic Unit – ALU Status Register The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as: Bit Read/Write Initial Value 7 6 5 4 3 2 1 0 I T H S V N Z C SREG R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the Instruction Set Reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 11 2486T–AVR–05/08 General Purpose Register File • Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input. • Two 8-bit output operands and one 8-bit result input. • Two 8-bit output operands and one 16-bit result input. • One 16-bit output operand and one 16-bit result input. Figure 3 shows the structure of the 32 general purpose working registers in the CPU. Figure 3. AVR CPU General Purpose Working Registers General Purpose Working Registers 7 0 R0 R1 R2 … R13 R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 3, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file. 12 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) The X-register, Y- The registers R26..R31 have some added functions to their general purpose usage. These reg- register and Z-register isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as described in Figure 4. Figure 4. The X-, Y- and Z-Registers 15 XH XL 0 X-register 7 07 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 07 0 R29 (0x1D) R28 (0x1C) Z-register 15 ZH 7 0 R31 (0x1F) ZL 0 7 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details). Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when address is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. 13 2486T–AVR–05/08 Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 6. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 222 for details. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of Vectors is shown in “Interrupts” on page 46. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 46 for more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – ReadWhile-Write Self-Programming” on page 209. 14 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< xxx ... ... ... 47 2486T–AVR–05/08 When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments $000 ; rjmp RESET ; Reset handler $001 RESET:ldi r16,high(RAMEND); Main program start $002 out SPH,r16 ; Set Stack Pointer to top of RAM $003 ldi r16,low(RAMEND) $004 out SPL,r16 $005 sei ; Enable interrupts $006 xxx ; .org $c01 $c01 rjmp EXT_INT0 ; IRQ0 Handler $c02 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; $c12 rjmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments .org $001 $001 rjmp EXT_INT0 ; IRQ0 Handler $002 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; $012 rjmp SPM_RDY ; Store Program Memory Ready Handler ; .org $c00 $c00 ; rjmp RESET ; Reset handler $c01 RESET:ldi r16,high(RAMEND); Main program start $c02 out SPH,r16 ; Set Stack Pointer to top of RAM $c03 ldi r16,low(RAMEND) $c04 out SPL,r16 $c05 sei ; Enable interrupts $c06 xxx 48 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes, and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments ; .org $c00 $c00 $c01 rjmp RESET rjmp EXT_INT0 ; Reset handler ; IRQ0 Handler $c02 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; $c12 rjmp SPM_RDY ; Store Program Memory Ready Handler $c13 RESET: ldi r16,high(RAMEND); Main program start $c14 out SPH,r16 ; Set Stack Pointer to top of RAM $c15 ldi r16,low(RAMEND) $c16 out SPL,r16 $c17 sei ; Enable interrupts $c18 xxx The General Interrupt Control Register controls the placement of the Interrupt Vector table. Bit 7 6 5 4 3 2 1 0 INT1 INT0 – – – – IVSEL IVCE GICR Read/Write R/W R/W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the boot Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 209 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 209 for details on Boot Lock Bits. 49 2486T–AVR–05/08 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 30 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 30. T1/T0 Pin Sampling Tn clkI/O DQ LE DQ Synchronization DQ Tn_sync (To Clock Select Logic) Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses 74 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 31. Prescaler for Timer/Counter0 and Timer/Counter1(1) clkI/O Clear PSR10 T0 Synchronization T1 Synchronization Special Function IO Register – SFIOR clkT1 clkT0 Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 30. Bit 7 6 5 4 3 2 1 0 – – – – ACME PUD PSR2 PSR10 SFIOR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. 75 2486T–AVR–05/08 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., allows 16-bit PWM) • Two Independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period • Frequency Generator • External Event Counter • Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1) Overview Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 32. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 96. 76 ATmega8(L) 2486T–AVR–05/08 Registers 2486T–AVR–05/08 ATmega8(L) Figure 32. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction Control Logic clkTn Timer/Counter TCNTn TOP BOTTOM = =0 DATA BUS = OCRnA = OCRnB ICRn TCCRnA Fixed TOP Values ICFn (Int.Req.) Edge Detector TCCRnB TOVn (Int. Req.) Clock Select Edge Detector Tn ( From Prescaler ) OCFnA (Int. Req.) Waveform Generation OCnA OCFnB (Int.Req.) Waveform Generation OCnB ( From Analog Comparator Ouput ) Noise Canceler ICPn Note: 1. Refer to “Pin Configurations” on page 2, Table 22 on page 58, and Table 28 on page 63 for Timer/Counter1 pin placement and description. The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page 79. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT1). The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). See “Output Compare Units” on page 84. The Compare Match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. 77 Definitions Compatibility The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see “Analog Comparator” on page 193). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output. The following definitions are used extensively throughout the document: Table 35. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation. The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. • Interrupt Vectors. The following control bits have changed name, but have same functionality and register location: • PWM10 is changed to WGM10. • PWM11 is changed to WGM11. • CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. 78 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. The 16-bit timer has a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the 16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High byte stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the same clock cycle. When the Low byte of a 16-bit register is read by the CPU, the High byte of the 16-bit register is copied into the temporary register in the same clock cycle as the Low byte is read. Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16bit registers does not involve using the temporary register. To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte must be read before the High byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Assembly Code Example(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Example(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: 1. See “About Code Examples” on page 8. The assembly code example returns the TCNT1 value in the r17:r16 Register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. 79 2486T–AVR–05/08 The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example(1) TIM16_ReadTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore Global Interrupt Flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore Global Interrupt Flag */ SREG = sreg; return i; } Note: 1. See “About Code Examples” on page 8. The assembly code example returns the TCNT1 value in the r17:r16 Register pair. 80 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example(1) TIM16_WriteTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore Global Interrupt Flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore Global Interrupt Flag */ SREG = sreg; } Note: 1. See “About Code Examples” on page 8. The assembly code example requires that the r17:r16 Register pair contains the value to be written to TCNT1. Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the High byte is the same for all registers written, then the High byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. 81 2486T–AVR–05/08 Timer/Counter Clock Sources Counter Unit The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 74. The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 33 shows a block diagram of the counter and its surroundings. Figure 33. Counter Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) TOVn (Int. Req.) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) count clear Control Logic direction clkTn TOP BOTTOM Clock Select Edge Detector Tn ( From Prescaler ) Signal description (internal signals): count Increment or decrement TCNT1 by 1. direction Select between increment and decrement. clear Clear TCNT1 (set all bits to zero). clkT1 TOP Timer/Counter clock. Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the High byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms 82 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) are generated on the Output Compare Outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 88. The Timer/Counter Overflow (TOV1) fLag is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 34. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 34. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) WRITE ICRn (16-bit Register) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) 2486T–AVR–05/08 ICPn ACO* Analog Comparator ACIC* ICNC Noise Canceler ICES Edge Detector ICFn (Int. Req.) When a change of the logic level (an event) occurs on the Input Capture Pin (ICP1), alternatively on the Analog Comparator Output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (TICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte (ICR1L) and then the High byte (ICR1H). When the Low byte is read the High byte is copied into the High byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- 83 Input Capture Pin Source Noise Canceler Using the Input Capture Unit Output Compare Units tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the High byte must be written to the ICR1H I/O location before the Low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 79. The main trigger source for the Input Capture unit is the Input Capture Pin (ICP1). Timer/Counter 1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 30 on page 74). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ- 84 ATmega8(L) 2486T–AVR–05/08 2486T–AVR–05/08 ATmega8(L) ing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 88.) A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e. counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator. Figure 35 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 35. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator OCnx WGMn3:0 COMnx1:0 The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the High byte temporary register (TEMP). However, it is a good practice to read the Low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16-bit is done continuously. The High byte (OCR1xH) has to be 85 Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit written first. When the High byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the Low byte (OCR1xL) is written to the lower eight bits, the High byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 79. In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real Compare Match had occurred (the COM1x1:0 bits settings define whether the OC1x pin is set, cleared or toggled). All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the Compare Match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting. The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 86 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 36 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a System Reset occur, the OC1x Register is reset to “0”. Figure 36. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator DQ 1 OCnx 0 DQ OCnx Pin DATABUS PORT DQ clkI/O DDR The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 36, Table 37 and Table 38 for details. The design of the Output Compare Pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “16-bit Timer/Counter Register Description” on page 96. The COM1x1:0 bits have no effect on the Input Capture unit. 87 2486T–AVR–05/08 Compare Output Mode and Waveform Generation The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the OC1x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 36 on page 97. For fast PWM mode refer to Table 37 on page 97, and for phase correct and phase and frequency correct PWM refer to Table 38 on page 98. A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a Compare Match. See “Compare Match Output Unit” on page 87. For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 95. Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 37. The counter value (TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. 88 ATmega8(L) 2486T–AVR–05/08 Figure 37. CTC Mode, Timing Diagram ATmega8(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Fast PWM Mode 2486T–AVR–05/08 TCNTn OCnA (Toggle) Period 1 2 3 4 (COMnA1:0 = 1) An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum fre- quency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation: fOCnA = ------------------f-c---l-k--_---I-/--O------------------2 ⋅ N ⋅ (1 + OCRnA) The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare Output mode output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- 89 imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: RFPWM = -l-o---g----(-l-o-T--g-O---(--P-2---)-+-----1----) In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 38. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 38. Fast PWM Mode, Timing Diagram OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 56 7 8 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OCF1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the Compare Match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. The OCR1A Register, however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. 90 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Phase Correct PWM Mode Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 37 on page 97. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: fOCnxPWM = ----------f--c--l-k--_---I-/--O----------N ⋅ (1 + TOP) The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each Compare Match (COM1A1:0 = 1). This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: RPCPWM = l--o---g----(---T---O-----P-----+-----1----) log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 39. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The 91 2486T–AVR–05/08 diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 39. Phase Correct PWM Mode, Timing Diagram OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 39 illustrates, changing the TOP actively while the Timer/Counter is running in the Phase Correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 38 on page 98. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when 92 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: fOCnxPCPWM = 2-----⋅-f--cN---l-k--⋅_---IT-/-O--O----P-- The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WMG13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 39 and Figure 40). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: RPFCPWM = -l-o---g----(-l-o-T--g-O---(--P-2---)-+-----1----) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 40. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. 93 2486T–AVR–05/08 Figure 40. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x. As Figure 40 shows the output generated is, in contrast to the Phase Correct mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM wave- forms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 38 on page 98. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter incre- ments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: fOCnxPFCPWM = ------f--c---l-k--_---I-/-O-------2 ⋅ N ⋅ TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the 94 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 41 shows a timing diagram for the setting of OCF1x. Figure 41. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling clkI/O clkTn (clkI/O/1) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 42 shows the same timing data, but with the prescaler enabled. Figure 42. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 43 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams 95 2486T–AVR–05/08 will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 43. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O/1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TOP - 1 TOP - 1 TOP TOP Old OCRnx Value BOTTOM TOP - 1 BOTTOM + 1 TOP - 2 New OCRnx Value Figure 44 shows the same timing data, but with the prescaler enabled. Figure 44. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TOP - 1 TOP - 1 TOP TOP Old OCRnx Value BOTTOM BOTTOM + 1 TOP - 1 TOP - 2 New OCRnx Value 16-bit Timer/Counter Register Description Timer/Counter 1 Control Register A – TCCR1A Bit Read/Write 7 COM1A1 R/W 6 COM1A0 R/W 5 COM1B1 R/W 4 COM1B0 R/W 3 FOC1A W 2 FOC1B W 1 WGM11 R/W 0 WGM10 R/W TCCR1A 96 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Initial Value 0 0 0 0 0 0 0 0 • Bit 7:6 – COM1A1:0: Compare Output Mode for channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for channel B The COM1A1:0 and COM1B1:0 control the Output Compare Pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 36 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). Table 36. Compare Output Mode, Non-PWM COM1A1/ COM1B1 0 0 1 1 COM1A0/ COM1B0 0 1 0 1 Description Normal port operation, OC1A/OC1B disconnected. Toggle OC1A/OC1B on Compare Match Clear OC1A/OC1B on Compare Match (Set output to low level) Set OC1A/OC1B on Compare Match (Set output to high level) Table 37 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 37. Compare Output Mode, Fast PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM, (non-inverting mode) 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM, (inverting mode) Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 89. for more details. 97 2486T–AVR–05/08 Table 38 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 38. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/ COM1A0/ COM1B1 COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match when up-counting. Set OC1A/OC1B on Compare Match when downcounting. 1 1 Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B on Compare Match when downcounting. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See “Phase Correct PWM Mode” on page 91. for more details. • Bit 3 – FOC1A: Force Output Compare for channel A • Bit 2 – FOC1B: Force Output Compare for channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 39. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 88.) Table 39. Waveform Generation Mode Bit Description WGM12 WGM11 WGM10 Timer/Counter Mode of Mode WGM13 (CTC1) (PWM11) (PWM10) Operation(1) 0 0 0 0 0 Normal 1 0 0 0 1 PWM, Phase Correct, 8-bit 2 0 0 1 0 PWM, Phase Correct, 9-bit 3 0 0 1 1 PWM, Phase Correct, 10-bit 4 0 1 0 0 CTC 5 0 1 0 1 Fast PWM, 8-bit 6 0 1 1 0 Fast PWM, 9-bit TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCR1A 0x00FF 0x01FF Update of OCR1x Immediate TOP TOP TOP Immediate BOTTOM BOTTOM TOV1 Flag Set on MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP 98 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Table 39. Waveform Generation Mode Bit Description WGM12 WGM11 WGM10 Timer/Counter Mode of Mode WGM13 (CTC1) (PWM11) (PWM10) Operation(1) TOP Update of TOV1 Flag OCR1x Set on 7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 (Reserved) – – – 14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP 15 Note: 1 1 1 1 Fast PWM OCR1A BOTTOM TOP 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. 99 2486T–AVR–05/08 Timer/Counter 1 Control Register B – TCCR1B Bit Read/Write Initial Value 7 ICNC1 R/W 0 6 ICES1 R/W 0 5 4 3 2 1 0 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B R R/W R/W R/W R/W R/W 0 0 0 0 0 0 • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description. • Bit 2:0 – CS12:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 41 and Figure 42. Table 40. Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source. (Timer/Counter stopped) 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 100 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Timer/Counter 1 – TCNT1H and TCNT1L Bit Read/Write Initial Value 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and Low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 79. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a Compare Match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the Compare Match on the following timer clock for all compare units. Output Compare Register 1 A – Bit OCR1AH and OCR1AL Read/Write Initial Value 7 6 5 R/W R/W R/W 0 0 0 4 3 2 OCR1A[15:8] OCR1A[7:0] R/W R/W R/W 0 0 0 1 0 OCR1AH OCR1AL R/W R/W 0 0 Output Compare Register 1 B – Bit OCR1BH and OCR1BL Read/Write Initial Value 7 6 5 R/W R/W R/W 0 0 0 4 3 2 OCR1B[15:8] OCR1B[7:0] R/W R/W R/W 0 0 0 1 0 OCR1BH OCR1BL R/W R/W 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare Interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 79. 2486T–AVR–05/08 101 Input Capture Register 1 – ICR1H and ICR1L Bit Read/Write Initial Value 7 6 5 R/W R/W R/W 0 0 0 4 3 2 ICR1[15:8] ICR1[7:0] R/W R/W R/W 0 0 0 1 0 ICR1H ICR1L R/W R/W 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 79. Timer/Counter Interrupt Mask Register – TIMSK(1) Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. • Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the ICF1 Flag, located in TIFR, is set. • Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the OCF1A Flag, located in TIFR, is set. • Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the OCF1B Flag, located in TIFR, is set. • Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the TOV1 Flag, located in TIFR, is set. Timer/Counter Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 – TIFR(1) OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag 102 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. • Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. • Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. • Bit 2 – TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Table 39 on page 98 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 2486T–AVR–05/08 103 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) • Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 45. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on page 117. Figure 45. 8-bit Timer/Counter Block Diagram TCCRn count clear direction Control Logic BOTTOM TOP Timer/Counter TCNTn = 0 = 0xFF = clkTn Prescaler OCn (Int. Req.) Waveform Generation TOVn (Int. Req.) T/C Oscillator TOSC1 TOSC2 clkI/O OCn OCRn DATA BUS Status Flags Synchronized Status Flags Synchronization Unit ASSRn asynchronous Mode Select (ASn) clkI/O clkASY Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). 104 ATmega8(L) 2486T–AVR–05/08 Definitions Timer/Counter Clock Sources ATmega8(L) All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC2). For details, see “Output Compare Unit” on page 107. The Compare Match event will also set the Compare Flag (OCF2) which can be used to generate an Output Compare interrupt request. Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2 counter value and so on). The definitions in Table 41 are also used extensively throughout the document. Table 41. Definitions BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation. The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Status Register – ASSR” on page 119. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 123. 2486T–AVR–05/08 105 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 46 shows a block diagram of the counter and its surrounding environment. Figure 46. Counter Unit Block Diagram DATA BUS TOVn (Int. Req.) TCNTn count clear Control Logic direction clk Tn Prescaler T/C Oscillator TOSC1 TOSC2 BOTTOM TOP clk I/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 TOP Timer/Counter clock. Signalizes that TCNT2 has reached maximum value. BOTTOM Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Output OC2. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 110. The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. 106 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF2 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see “Modes of Operation” on page 110). Figure 47 shows a block diagram of the Output Compare unit. Figure 47. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn TOP BOTTOM FOCn = (8-bit Comparator ) Waveform Generator OCFn (Int. Req.) OCxy WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. 2486T–AVR–05/08 107 Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled). All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between waveform generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. 108 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 48 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. Figure 48. Compare Match Output Unit, Schematic COMn1 COMn0 FOCn Waveform Generator DQ 1 OCn 0 OCn Pin DQ DATABUS PORT DQ clkI/O DDR The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 117. 2486T–AVR–05/08 109 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the nonPWM modes refer to Table 43 on page 118. For fast PWM mode, refer to Table 44 on page 118, and for phase correct PWM refer to Table 45 on page 118. A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits. Modes of Operation The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (see “Compare Match Output Unit” on page 109). For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 114. Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 110 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 49. The counter value (TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared. Figure 49. CTC Mode, Timing Diagram OCn Interrupt Flag Set TCNTn OCn (Toggle) Period 1 2 3 4 (COMn1:0 = 1) An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: fOCn = -2----⋅---N------⋅--f-(c--1-l-k--_-+--I-/--OO-----C----R----n---)- The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 2486T–AVR–05/08 111 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 50. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 50. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update and TOVn Interrupt Flag Set TCNTn OCn OCn (COMn1:0 = 2) (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0 to 3 (see Table 44 on page 118). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: fOCnPWM = -f--c---l-k--_---I-/-O--N ⋅ 256 112 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Phase Correct PWM Mode The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 51. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 51. Phase Correct PWM Mode, Timing Diagram OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set 2486T–AVR–05/08 TCNTn OCn OCn Period (COMn1:0 = 2) (COMn1:0 = 3) 1 2 3 113 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM out- put can be generated by setting the COM21:0 to 3 (see Table 45 on page 118). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the follow- ing equation: fOCnPCPWM = -f--c---l-k--_---I-/-O--N ⋅ 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 51 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match: • OCR2A changes its value from MAX, like in Figure 51. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. Timer/Counter Timing Diagrams The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In Asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 52 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 52. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O/1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn 114 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 53 shows the same timing data, but with the prescaler enabled. Figure 53. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn MAX - 1 MAX BOTTOM TOVn BOTTOM + 1 Figure 54 shows the setting of OCF2 in all modes except CTC mode. Figure 54. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn OCRn - 1 OCRn OCRn + 1 OCRn + 2 OCRn OCRn Value OCFn Figure 55 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. 2486T–AVR–05/08 115 Figure 55. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC) OCRn TOP - 1 TOP BOTTOM TOP BOTTOM + 1 OCFn 116 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR2 Bit Read/Write Initial Value 7 FOC2 W 0 6 WGM20 R/W 0 5 COM21 R/W 0 4 COM20 R/W 0 3 WGM21 R/W 0 2 CS22 R/W 0 1 CS21 R/W 0 0 CS20 R/W 0 TCCR2 • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero. • Bit 6,3 – WGM21:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 42 and “Modes of Operation” on page 110. Table 42. Waveform Generation Mode Bit Description WGM21 WGM20 Timer/Counter Mode Mode (CTC2) (PWM2) of Operation(1) TOP Update of TOV2 Flag OCR2 Set 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. • Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 43 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). 2486T–AVR–05/08 117 Table 43. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Toggle OC2 on Compare Match 1 0 Clear OC2 on Compare Match 1 1 Set OC2 on Compare Match Table 44 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 44. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM, (non-inverting mode) 1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM, (inverting mode) Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 112 for more details. Table 45 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Table 45. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when downcounting. 1 Note: 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when downcounting. 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 113 for more details. 118 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Timer/Counter Register – TCNT2 Output Compare Register – OCR2 • Bit 2:0 – CS22:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Table 46. Table 46. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkT2S/(No prescaling) 0 1 0 clkT2S/8 (From prescaler) 0 1 1 clkT2S/32 (From prescaler) 1 0 0 clkT2S/64 (From prescaler) 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) Bit Read/Write Initial Value 7 6 5 4 3 2 1 0 TCNT2[7:0] TCNT2 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register. Bit Read/Write Initial Value 7 6 5 4 3 2 1 0 OCR2[7:0] OCR2 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2 pin. Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Bit 7 6 5 4 3 2 1 0 – – – – AS2 TCN2UB OCR2UB TCR2UB ASSR Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscil- lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted. 2486T–AVR–05/08 119 Asynchronous Operation of Timer/Counter2 • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 1 – OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set. When OCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value. • Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set. When TCCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read. When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2, and TCCR2. 4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. • The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. • When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented. • When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up. • If Timer/Counter2 is used to wake the device up from Power-save mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one 120 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2, TCNT2, or OCR2. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or Extended Standby mode. • When the asynchronous operation is selected, the 32.768 kHZ Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or Wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after Power-up or Wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon startup, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Powersave mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Write any value to either of the registers OCR2 or TCCR2. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. • During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock. 2486T–AVR–05/08 121 Timer/Counter Interrupt Mask Register – TIMSK Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs (i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR). • Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR). Timer/Counter Interrupt Flag Register Bit – TIFR 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed. • Bit 6 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 122 ATmega8(L) 2486T–AVR–05/08 Timer/Counter Prescaler ATmega8(L) Figure 56. Prescaler for Timer/Counter2 clkI/O TOSC1 clkT2S Clear 10-BIT T/C PRESCALER AS2 clkT2S/8 clkT2S/32 clkT2S/64 clkT2S/128 clkT2S/256 clkT2S/1024 PSR2 0 CS20 CS21 CS22 Special Function IO Register – SFIOR TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not recommended. For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. Bit 7 6 5 4 3 2 1 0 – – – – ACME PUD PSR2 PSR10 SFIOR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset. 2486T–AVR–05/08 123 Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8 and peripheral devices or between several AVR devices. The ATmega8 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode Figure 57. SPI Block Diagram(1) DIVIDER /2/4/8/16/32/64/128 SPI2X SPI2X Note: 1. Refer to “Pin Configurations” on page 2, and Table 22 on page 58 for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in Figure 58. The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. 124 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 58. SPI Master-Slave Interconnection MSB MASTER LSB 8 BIT SHIFT REGISTER MISO MISO MSB SLAVE LSB 8 BIT SHIFT REGISTER MOSI MOSI SPI CLOCK GENERATOR SCK SS VCC SCK SS SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles High period: longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 47. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 56. Table 47. SPI Pin Overrides(1) Pin Direction, Master SPI MOSI User Defined Direction, Slave SPI Input 2486T–AVR–05/08 125 Table 47. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See “Port B Pins Alternate Functions” on page 58 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 126 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. See “About Code Examples” on page 8. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 145 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates. Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (PE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRA. The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR Flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity error when received. If parity check is not enabled the PE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 138 and “Parity Checker” on page 147. 146 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a parity error. The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost Flushing the Receive Buffer The Receiver buffer FIFO will be flushed when the Receiver is disabled (i.e., the buffer will be emptied of its contents). Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is cleared. The following code example shows how to flush the receive buffer. Assembly Code Example(1) USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz 2486T–AVR–05/08 237 Serial Programming Algorithm When writing serial data to the ATmega8, data is clocked on the rising edge of SCK. When reading data from the ATmega8, data is clocked on the falling edge of SCK. See Figure 113 for timing details. To program and verify the ATmega8 in the Serial Programming mode, the following sequence is recommended (See four byte instruction formats in Table 98): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable Serial Programming by sending the Programming Enable serial instruction to pin MOSI. 3. The Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The page size is found in Table 89 on page 225. The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data Low byte must be loaded before data High byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 7 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 97). Note: If other commands than polling (read) are applied before any write operation (FLASH, EEPROM, Lock Bits, Fuses) is completed, it may result in incorrect programming. 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 97 on page 239). In a chip erased device, no 0xFFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 97 for tWD_FLASH value. Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for 238 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is Re-programmed without chip-erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 97 for tWD_EEPROM value. Table 97. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FUSE tWD_FLASH tWD_EEPROM tWD_ERASE 4.5 ms 4.5 ms 9.0 ms 9.0 ms Figure 113. Serial Programming Waveforms SERIAL DATA INPUT MSB LSB (MOSI) SERIAL DATA OUTPUT MSB LSB (MISO) SERIAL CLOCK INPUT (SCK) SAMPLE 2486T–AVR–05/08 239 Table 98. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Programming Enable 1010 1100 0101 0011 xxxx xxxx Chip Erase Read Program Memory 1010 1100 0010 H000 100x xxxx 0000 aaaa xxxx xxxx bbbb bbbb Load Program Memory Page 0100 H000 0000 xxxx xxxb bbbb Write Program Memory Page Read EEPROM Memory 0100 1100 0000 aaaa bbbx xxxx 1010 0000 00xx xxxa bbbb bbbb Write EEPROM Memory 1100 0000 00xx xxxa bbbb bbbb Read Lock Bits 0101 1000 0000 0000 xxxx xxxx Write Lock Bits 1010 1100 111x xxxx xxxx xxxx Read Signature Byte Write Fuse Bits 0011 0000 00xx xxxx xxxx xxbb 1010 1100 1010 0000 xxxx xxxx Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx Read Fuse High Bits 0101 1000 0000 1000 xxxx xxxx Read Calibration Byte 0011 1000 Note: a = address high bits b = address low bits H = 0 – Low byte, 1 – High byte o = data out i = data in x = don’t care 00xx xxxx 0000 00bb Byte4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii xxxx xxxx oooo oooo iiii iiii xxoo oooo 11ii iiii oooo oooo iiii iiii iiii iiii oooo oooo oooo oooo oooo oooo Operation Enable Serial Programming after RESET goes low. Chip Erase EEPROM and Flash. Read H (high or low) data o from Program memory at word address a:b. Write H (high or low) data i to Program memory page at word address b. Data Low byte must be loaded before Data High byte is applied within the same address. Write Program memory Page at address a:b. Read data o from EEPROM memory at address a:b. Write data i to EEPROM memory at address a:b. Read Lock Bits. “0” = programmed, “1” = unprogrammed. See Table 85 on page 222 for details. Write Lock Bits. Set bits = “0” to program Lock Bits. See Table 85 on page 222 for details. Read Signature Byte o at address b. Set bits = “0” to program, “1” to unprogram. See Table 88 on page 224 for details. Set bits = “0” to program, “1” to unprogram. See Table 87 on page 223 for details. Read Fuse Bits. “0” = programmed, “1” = unprogrammed. See Table 88 on page 224 for details. Read Fuse high bits. “0” = programmed, “1” = unprogrammed. See Table 87 on page 223 for details. Read Calibration Byte 240 ATmega8(L) 2486T–AVR–05/08 SPI Serial Programming Characteristics ATmega8(L) For characteristics of the SPI module, see “SPI Timing Characteristics” on page 246. 2486T–AVR–05/08 241 Electrical Characteristics Note: Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 300.0 mA DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition VIL Input Low Voltage except XTAL1 and RESET pins VCC = 2.7V - 5.5V VIH Input High Voltage except XTAL1 and RESET pins VCC = 2.7V - 5.5V Input Low Voltage VIL1 XTAL1 pin VCC = 2.7V - 5.5V Input High Voltage VIH1 XTAL 1 pin VCC = 2.7V - 5.5V Input Low Voltage VIL2 RESET pin VCC = 2.7V - 5.5V Input High Voltage VIH2 RESET pin VCC = 2.7V - 5.5V Input Low Voltage VIL3 RESET pin as I/O VCC = 2.7V - 5.5V Input High Voltage VIH3 RESET pin as I/O VCC = 2.7V - 5.5V VOL Output Low Voltage(3) (Ports B,C,D) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V VOH Output High Voltage(4) (Ports B,C,D) IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) RRST Reset Pull-up Resistor Min Typ Max Units -0.5 0.2 VCC(1) V 0.6 VCC(2) VCC + 0.5 V -0.5 0.1 VCC(1) V 0.8 VCC(2) VCC + 0.5 V -0.5 0.9 VCC(2) 0.2 VCC V VCC + 0.5 V -0.5 0.6 VCC(2) 0.7 VCC(2) 4.2 2.2 0.2 VCC V VCC + 0.5 V 0.7 V 0.5 V V V 1 µA 1 µA 30 80 kΩ 242 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Units Rpu I/O Pin Pull-up Resistor Active 4 MHz, VCC = 3V (ATmega8L) 20 50 kΩ 5 mA Active 8 MHz, VCC = 5V (ATmega8) Power Supply Current ICC Idle 4 MHz, VCC = 3V (ATmega8L) 15 mA 2 mA Idle 8 MHz, VCC = 5V (ATmega8) 7 mA Power-down mode(5) WDT enabled, VCC = 3V WDT disabled, VCC = 3V 28 µA 3 µA VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 5.0V Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low 750 500 ns 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP, TQFP, and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 300 mA. 2] The sum of all IOL, for ports C0 - C5 should not exceed 100 mA. 3] The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP, TQFP, and QFN/MLF Package: 1] The sum of all IOH, for all ports, should not exceed 300 mA. 2] The sum of all IOH, for port C0 - C5, should not exceed 100 mA. 3] The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V. 2486T–AVR–05/08 243 External Clock Figure 114. External Clock Drive Waveforms Drive Waveforms VIH1 VIL1 External Clock Drive Table 99. External Clock Drive Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL ΔtCLCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Change in period from one clock cycle to the next VCC = 2.7V to 5.5V Min Max 0 8 125 50 50 1.6 1.6 VCC = 4.5V to 5.5V Min Max 0 16 62.5 25 25 0.5 0.5 Units MHz ns ns ns μs μs 2 2 % Table 100. External RC Oscillator, Typical Frequencies R [kΩ](1) C [pF] f(2) 33 22 650 kHz Notes: 10 22 2.0 MHz 1. R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout. 244 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Two-wire Serial Interface Characteristics Table 101 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 115. Table 101. Two-wire Serial Bus Requirements Symbol VIL VIH Vhys(1) VOL(1) tr(1) tof(1) tSP(1) Ii Ci(1) fSCL Parameter Input Low-voltage Input High-voltage Hysteresis of Schmitt Trigger Inputs Output Low-voltage Rise Time for both SDA and SCL Output Fall Time from VIHmin to VILmax Spikes Suppressed by Input Filter Input Current each I/O Pin Capacitance for each I/O Pin SCL Clock Frequency Rp Value of Pull-up resistor Condition 3 mA sink current 10 pF < Cb < 400 pF(3) 0.1VCC < Vi < 0.9VCC fCK(4) > max(16fSCL, 250kHz)(5) fSCL ≤ 100 kHz fSCL > 100 kHz tHD;STA Hold Time (repeated) START Condition fSCL ≤ 100 kHz fSCL > 100 kHz tLOW Low Period of the SCL Clock fSCL ≤ 100 kHz(6) fSCL > 100 kHz(7) tHIGH High period of the SCL clock fSCL ≤ 100 kHz fSCL > 100 kHz tSU;STA Set-up time for a repeated START condition fSCL ≤ 100 kHz fSCL > 100 kHz tHD;DAT Data hold time fSCL ≤ 100 kHz fSCL > 100 kHz tSU;DAT Data setup time fSCL ≤ 100 kHz fSCL > 100 kHz tSU;STO Setup time for STOP condition fSCL ≤ 100 kHz fSCL > 100 kHz tBUF Notes: Bus free time between a STOP and START fSCL ≤ 100 kHz condition fSCL > 100 kHz 1. In ATmega8, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100 kHz. 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency Min -0.5 0.7 VCC 0.05 VCC(2) 0 20 + 0.1Cb(3)(2) 20 + 0.1Cb(3)(2) 0 -10 – 0 -V---C----C----–-----0---,--4---V--3mA -V---C----C----–-----0---,--4---V--3mA 4.0 0.6 4.7 1.3 4.0 0.6 4.7 0.6 0 0 250 100 4.0 0.6 4.7 1.3 Max 0.3 VCC VCC + 0.5 – 0.4 300 250 50(2) 10 10 400 1----0---0----0---n---s-Cb 3----0---0----n---sCb – – – – – – – – 3.45 0.9 – – – – – – Units V V V V ns ns ns µA pF kHz Ω Ω µs µs µs µs µs µs µs µs µs µs ns ns µs µs µs µs 2486T–AVR–05/08 245 SPI Timing Characteristics 5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz. 7. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega8 devices connected to the bus may communicate at full speed (400 kHz) with other ATmega8 devices, as well as any other device with a proper tLOW acceptance margin. Figure 115. Two-wire Serial Bus Timing SCL SDA tSU;STA tof tLOW tHD;STA tHIGH tLOW tHD;DAT tSU;DAT tr tSU;STO tBUF See Figure 116 and Figure 117 for details. Table 102. SPI Timing Parameters Description Mode 1 SCK period Master 2 SCK high/low Master 3 Rise/Fall time Master 4 Setup Master 5 Hold Master 6 Out to SCK Master 7 SCK to out Master 8 SCK to out high Master 9 SS low to out Slave 10 SCK period 11 SCK high/low(1) Slave Slave 12 Rise/Fall time Slave 13 Setup Slave 14 Hold Slave 15 SCK to out Slave 16 SCK to SS high Slave 17 SS high to tri-state Slave 18 SS low to SCK Salve Min 4 • tck 2 • tck 10 10 20 2 • tck Typ Max See Table 50 50% duty cycle 3.6 10 10 0.5 • tSCK 10 10 15 ns 1.6 15 10 Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2tCLCL for fCK < 12 MHz - 3tCLCL for fCK > 12 MHz 246 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 116. SPI interface timing requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 45 3 MISO (Data Input) MSB ... 7 LSB 8 MOSI (Data Output) MSB ... LSB Figure 117. SPI interface timing requirements (Slave Mode) 18 SS 9 SCK (CPOL = 0) 11 SCK (CPOL = 1) 13 14 MOSI (Data Input) MSB ... 15 MISO (Data Output) MSB ... 10 16 11 12 LSB 17 LSB X 2486T–AVR–05/08 247 ADC Characteristics Table 103. ADC Characteristics Symbol Parameter Condition Resolution Single Ended Conversion Absolute accuracy (Including INL, DNL, Quantization Error, Gain, and Offset Error) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz Integral Non-linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Differential Non-linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Gain Error Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Offset Error Conversion Time(4) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Free Running Conversion Clock Frequency AVCC VREF VIN Analog Supply Voltage Reference Voltage Input voltage Input bandwidth VINT Internal Voltage Reference RREF Reference Input Resistance RAIN Analog Input Resistance Notes: 1. Values are guidelines only. 2. Minimum for AVCC is 2.7V. 3. Maximum for AVCC is 5.5V. 4. Maximum conversion time is 1/50kHz*25 = 0.5 ms. Min(1) 13 50 VCC - 0.3(2) 2.0 GND 2.3 55 Typ(1) 10 1.75 3 0.75 0.5 1 1 38.5 2.56 32 100 Max(1) 260 1000 VCC + 0.3(3) AVCC VREF 2.7 Units Bits LSB LSB LSB LSB LSB LSB µs kHz V V V kHz V kΩ MΩ 248 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) ATmega8 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with Rail-to-Rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. Active Supply Current Figure 118. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ICC (mA) 3 2.5 2 1.5 1 0.5 0 0 ACTIVE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Frequency (MHz) 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V 1 2486T–AVR–05/08 249 Figure 119. Active Supply Current vs. Frequency (1 - 20 MHz) ICC (mA) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 30 5.5V 25 5.0V 4.5V 20 15 10 3.3V 5 3.0V 2.7V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 120. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ICC (mA) 18 16 14 12 10 8 6 4 2 0 2.5 ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 250 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 121. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) ICC (mA) 12 10 8 6 4 2 0 2.5 ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 Figure 122. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) ICC (mA) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 6 25°C 5 -40°C 85°C 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2486T–AVR–05/08 251 Figure 123. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ICC (mA) 3.5 3 2.5 2 1.5 1 0.5 0 2.5 ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 25°C -40°C 85°C 3 3.5 4 4.5 5 5.5 VCC (V) Figure 124. Active Supply Current vs. VCC (32 kHz External Oscillator) ICC (uA) 120 100 80 60 40 20 0 2.5 ACTIVE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 3 3.5 4 4.5 5 VCC (V) 25°C 5.5 252 ATmega8(L) 2486T–AVR–05/08 Idle Supply Current Figure 125. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) ATmega8(L) ICC (mA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Frequency (MHz) 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V 1 Figure 126. Idle Supply Current vs. Frequency (1 - 20 MHz) ICC (mA) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 4 3.3V 3.0V 2 2.7V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 2486T–AVR–05/08 253 Figure 127. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ICC (mA) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 8 -40°C 7 25°C 85°C 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 128. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) ICC (mA) 4 3.5 3 2.5 2 1.5 1 0.5 0 2.5 IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 254 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 129. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) ICC (mA) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.5 IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 3 3.5 4 4.5 5 VCC (V) -40°C 85°C 25°C 5.5 Figure 130. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ICC (mA) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 3 3.5 4 4.5 5 VCC (V) 85°C 25°C -40°C 5.5 2486T–AVR–05/08 255 Figure 131. Idle Supply Current vs. VCC (32 kHz External Oscillator) ICC (uA) 40 35 30 25 20 15 10 5 0 2.5 IDLE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 3 3.5 4 4.5 5 VCC (V) 25°C 5.5 Power-down Supply Current Figure 132. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) ICC (uA) 2.5 2 1.5 1 0.5 0 2.5 POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 3 3.5 4 4.5 5 VCC (V) 85°C -40°C 25°C 5.5 256 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 133. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) ICC (uA) 80 70 60 50 40 30 20 10 0 2.5 POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 3 3.5 4 4.5 5 VCC (V) 85°C 25°C -40°C 5.5 Power-save Supply Current Figure 134. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) ICC (uA) 25 20 15 10 5 0 2.5 POWER-SAVE SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 3 3.5 4 4.5 5 VCC (V) 25°C 5.5 2486T–AVR–05/08 257 Standby Supply Current Figure 135. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer Disabled) ICC (uA) STANDBY SUPPLY CURRENT vs. VCC 455 kHz RESONATOR, WATCHDOG TIMER DISABLED 80 70 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 136. Standby Supply Current vs. VCC (1 MHz Resonator, Watchdog Timer Disabled) ICC (uA) STANDBY SUPPLY CURRENT vs. VCC 1 MHz RESONATOR, WATCHDOG TIMER DISABLED 70 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 258 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 137. Standby Supply Current vs. VCC (2 MHz Resonator, Watchdog Timer Disabled) ICC (uA) STANDBY SUPPLY CURRENT vs. VCC 2 MHz RESONATOR, WATCHDOG TIMER DISABLED 90 80 70 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 138. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled) ICC (uA) STANDBY SUPPLY CURRENT vs. VCC 2 MHz XTAL, WATCHDOG TIMER DISABLED 90 80 70 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2486T–AVR–05/08 259 Figure 139. Standby Supply Current vs. VCC (4 MHz Resonator, Watchdog Timer Disabled) ICC (uA) STANDBY SUPPLY CURRENT vs. VCC 4 MHz RESONATOR, WATCHDOG TIMER DISABLED 140 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 140. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled) ICC (uA) STANDBY SUPPLY CURRENT vs. VCC 4 MHz XTAL, WATCHDOG TIMER DISABLED 140 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 260 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 141. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog Timer Disabled) ICC (uA) STANDBY SUPPLY CURRENT vs. VCC 6 MHz RESONATOR, WATCHDOG TIMER DISABLED 160 140 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 142. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled) ICC (uA) STANDBY SUPPLY CURRENT vs. VCC 6 MHz XTAL, WATCHDOG TIMER DISABLED 200 180 160 140 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2486T–AVR–05/08 261 Pin Pull-up Figure 143. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 85°C 140 120 100 I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 25°C -40°C IIO (uA) 80 60 40 20 0 0 1 2 3 4 5 6 VOP (V) Figure 144. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 90 80 85°C 70 60 25°C -40°C IIO (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) 262 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 145. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) IRESET (uA) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 100 - 40°C 80 60 25°C 85°C 40 20 0 0 1 2 VRESET (V) Figure 146. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 45 -40°C40 35 30 RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 25°C 85°C IRESET (uA) 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VRESET (V) 2486T–AVR–05/08 263 Pin Driver Strength Figure 147. I/O Pin Source Current vs. Output Voltage (VCC = 5V) IOH (mA) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 80 -40°C 70 25°C 60 85°C 50 40 30 20 10 0 VOH (V) Figure 148. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) IOH (mA) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 -40°C 25 25°C 20 85°C 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) 264 ATmega8(L) 2486T–AVR–05/08 Figure 149. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) ATmega8(L) IOL (mA) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 80 -40°C 70 25°C 60 85°C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 150. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) IOL (mA) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 35 -40°C 30 25°C 25 85°C 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) 2486T–AVR–05/08 265 Figure 151. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 5V) Current (mA) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 4 3.5 -40°C 3 25°C 2.5 85°C 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 VOH (V) Figure 152. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 2.7V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 5 4.5 25°C 4 -40°C 3.5 Current (mA) 3 2.5 85°C 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 VOH (V) 266 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 153. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 5V) Current (mA) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 14 -40°C 12 25°C 10 85°C 8 6 4 2 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 154. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 2.7V) Current (mA) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V -40°C 25°C 85°C 0.5 1 1.5 2 2.5 VOL (V) 2486T–AVR–05/08 267 Pin Thresholds and Hysteresis Figure 155. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) Threshold (V) 2.5 2 1.5 1 0.5 0 2.5 I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3 3.5 4 4.5 5 VCC (V) -40°C 85°C 25°C 5.5 Figure 156. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) Threshold (V) 2 1.5 1 0.5 0 2.5 I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 268 ATmega8(L) 2486T–AVR–05/08 Figure 157. I/O Pin Input Hysteresis vs. VCC ATmega8(L) Input Hysteresis (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 I/O PIN INPUT HYSTERESIS vs. VCC 3 3.5 4 4.5 5 VCC (V) 85°C -40°C 25°C 5.5 Figure 158. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) Threshold (V) 4 3.5 3 2.5 2 1.5 1 0.5 0 2.5 RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' -40°C 85°C 25°C 3 3.5 4 4.5 5 5.5 VCC (V) 2486T–AVR–05/08 269 Figure 159. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) Threshold (V) 2.5 2 1.5 1 0.5 0 2.5 RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 85°C 25°C -40°C 3 3.5 4 4.5 5 5.5 VCC (V) Figure 160. Reset Pin as I/O – Pin Hysteresis vs. VCC Input Hysteresis (V) 2 1.5 1 0.5 0 2.5 RESET PIN AS I/O - PIN HYSTERESIS vs. VCC 3 3.5 4 4.5 5 VCC (V) -40°C 85°C 25°C 5.5 270 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 161. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) Threshold (V) 2.5 2 1.5 1 0.5 0 2.5 RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 Figure 162. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) Threshold (V) 2.5 2 1.5 1 0.5 0 2.5 RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 3 3.5 4 4.5 5 VCC (V) 85°C 25°C -40°C 5.5 2486T–AVR–05/08 271 Figure 163. Reset Input Pin Hysteresis vs. VCC Input Hysteresis (V) RESET INPUT PIN HYSTERESIS vs. VCC 1 0.8 -40°C 0.6 25°C 0.4 85°C 0.2 0 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Bod Thresholds and Analog Comparator Offset Figure 164. BOD Thresholds vs. Temperature (BOD Level is 4.0V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.0V 4.3 4.2 Rising VCC 4.1 Threshold (V) 4 Falling VCC 3.9 3.8 3.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (˚C) 272 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 165. BOD Thresholds vs. Temperature (BOD Level is 2.7v) Threshold (V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.8 2.7 Rising VCC 2.6 Falling VCC 2.5 2.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (˚C) Figure 166. Bandgap Voltage vs. VCC Bandgap Voltage (V) 1.315 BANDGAP VOLTAGE vs. VCC 1.31 1.305 1.3 -40° 85° 25° 1.295 1.29 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 2486T–AVR–05/08 273 Figure 167. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) Comparator Offset Voltage (V) 0.003 ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5V 0.002 0.001 0 -0.001 85° -0.002 -0.003 -0.004 25°C -0.005 -40° -0.006 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 168. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) Comparator Offset Voltage (V) 0.003 ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7V 0.002 0.001 0 -0.001 85° -0.002 25° -0.003 -0.004 -40° -0.005 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) 274 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Internal Oscillator Speed Figure 169. Watchdog Oscillator Frequency vs. VCC FRC (kHz) 1260 1240 1220 1200 1180 1160 1140 1120 1100 2.5 WATCHDOG OSCILLATOR FREQUENCY vs. VCC 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 Figure 170. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature FRC (MHz) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.5 5.5V 8.3 8.1 4.0V 7.9 7.7 7.5 2.7V 7.3 7.1 6.9 6.7 6.5 -60 -40 -20 0 20 40 60 80 100 Temperature (˚C) 2486T–AVR–05/08 275 Figure 171. Calibrated 8 MHz RC Oscillator Frequency vs. VCC FRC (MHz) 8.5 8.3 8.1 7.9 7.7 7.5 7.3 7.1 6.9 6.7 6.5 2.5 CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 Figure 172. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 16 14 12 10 8 6 4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE FRC (MHz) 276 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 173. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature FRC (MHz) CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.2 5.5V 4.1 4.0V 4 3.9 2.7V 3.8 3.7 3.6 3.5 -60 -40 -20 0 20 40 60 80 100 Temperature (˚C) Figure 174. Calibrated 4 MHz RC Oscillator Frequency vs. VCC FRC (MHz) 4.2 4.1 4 3.9 3.8 3.7 3.6 3.5 2.5 CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. VCC 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 2486T–AVR–05/08 277 Figure 175. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 8 7 6 5 4 3 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE FRC (MHz) Figure 176. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.1 5.5V 2.05 4.0V 2 FRC (MHz) 1.95 2.7V 1.9 1.85 1.8 -60 -40 -20 0 20 40 60 80 100 Temperature (˚C) 278 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 177. Calibrated 2 MHz RC Oscillator Frequency vs. VCC CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. VCC 2.2 2.1 2 FRC (MHz) 1.9 1.8 1.7 2.5 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 Figure 178. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value FRC (MHz) CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 3.8 3.3 2.8 2.3 1.8 1.3 0.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE 2486T–AVR–05/08 279 Figure 179. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature FRC (MHz) CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.04 5.5V 1.02 4.0V 1 0.98 2.7V 0.96 0.94 0.92 0.9 -60 -40 -20 0 20 40 60 80 100 Temperature (˚C) Figure 180. Calibrated 1 MHz RC Oscillator Frequency vs. VCC CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. VCC 1.1 FRC (MHz) 1.05 -40°C 25°C 1 85°C 0.95 0.9 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 280 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 181. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value FRC (MHz) CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Current Consumption Figure 182. Brown-out Detector Current vs. VCC of Peripheral Units BROWN-OUT DETECTOR CURRENT vs. VCC 30 25 20 ICC (uA) 15 10 5 0 2.5 3 3.5 4 4.5 5 VCC (V) -40°C 25°C 85°C 5.5 2486T–AVR–05/08 281 Figure 183. ADC Current vs. VCC (AREF = AVCC) ICC (uA) ADC CURRENT vs. VCC AREF = AVCC 450 400 25°C -40°C 350 85°C 300 250 200 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 184. AREF External Reference Current vs. VCC ICC (uA) 250 200 150 100 50 0 2.5 AREF EXTERNAL REFERENCE CURRENT vs. VCC 25°C -40°C 3 3.5 4 4.5 5 VCC (V) 85°C 5.5 282 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Figure 185. 32 kHz TOSC Current vs. VCC (Watchdog Timer Disabled) 32 kHz TOSC CURRENT vs. VCC WATCHDOG TIMER DISABLED 25 20 25°C 15 ICC (uA) 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 186. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 80 70 85°C 25°C 60 -40°C 50 ICC (uA) 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2486T–AVR–05/08 283 Figure 187. Analog Comparator Current vs. VCC ICC (uA) 100 90 80 70 60 50 40 30 20 10 0 2.5 ANALOG COMPARATOR CURRENT vs. VCC 3 3.5 4 4.5 5 VCC (V) Figure 188. Programming Current vs. VCC ICC (mA) PROGRAMMING CURRENT vs. VCC 7 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 VCC (V) 85°C 25°C -40°C 5.5 -40°C 25°C 85°C 5.5 284 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Current Consumption in Reset and Reset Pulsewidth Figure 189. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) ICC (mA) 4 3.5 3 2.5 2 1.5 1 0.5 0 0 RESET SUPPLY CURRENT vs. VCC 0.1 - 1 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Frequency (MHz) 5.5V 5.0V 4.5V 4.0V 3.3V 3.0V 2.7V 1 Figure 190. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up) ICC (mA) 25 20 15 10 5 0 0 RESET SUPPLY CURRENT vs. VCC 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 5.5V 5.0V 4.5V 2.7V 3.0V 3.3V 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) 2486T–AVR–05/08 285 Figure 191. Reset Pulse Width vs. VCC Pulsewidth (ns) RESET PULSE WIDTH vs. VCC 1400 1200 1000 800 600 400 200 0 2.5 3 3.5 4 4.5 5 VCC (V) 85°C 25°C -40°C 5.5 286 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) Register Summary Address 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20(1) (0x40)(1) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) Name SREG SPH SPL Reserved GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR Bit 7 I – SP7 INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SE – – – COM1A1 ICNC1 FOC2 – – URSEL URSEL – EEAR7 – PORTB7 DDB7 PINB7 – – – PORTD7 DDD7 PIND7 SPIF SPIE RXC RXCIE ACD REFS1 ADEN TWA6 Bit 6 T – SP6 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SM2 – – – COM1A0 ICES1 WGM20 – – – UMSEL – EEAR6 – PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC TXCIE ACBG REFS0 ADSC TWA5 Bit 5 H – SP5 Bit 4 S – SP4 Bit 3 V – SP3 Bit 2 N SP10 SP2 Bit 1 Z SP9 SP1 – – – – IVSEL – – – – – TICIE1 OCIE1A OCIE1B TOIE1 – ICF1 OCF1A OCF1B TOV1 – – RWWSRE BLBSET PGWRT PGERS TWSTA TWSTO TWWC TWEN – SM1 SM0 ISC11 ISC10 ISC01 – – WDRF BORF EXTRF – – – CS02 CS01 Timer/Counter0 (8 Bits) Oscillator Calibration Register – – ACME PUD PSR2 COM1B1 COM1B0 FOC1A FOC1B WGM11 – WGM13 WGM12 CS12 CS11 Timer/Counter1 – Counter Register High byte Timer/Counter1 – Counter Register Low byte Timer/Counter1 – Output Compare Register A High byte Timer/Counter1 – Output Compare Register A Low byte Timer/Counter1 – Output Compare Register B High byte Timer/Counter1 – Output Compare Register B Low byte Timer/Counter1 – Input Capture Register High byte Timer/Counter1 – Input Capture Register Low byte COM21 COM20 WGM21 CS22 CS21 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register – – AS2 TCN2UB OCR2UB – WDCE WDE WDP2 WDP1 – – UBRR[11:8] UPM1 UPM0 USBS UCSZ1 UCSZ0 – – – – – EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEPROM Data Register – – EERIE EEMWE EEWE PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 – DORD UDRE UDRIE ACO ADLAR ADFR TWA4 PORTB4 PORTB3 PORTB2 DDB4 DDB3 DDB2 PINB4 PINB3 PINB2 PORTC4 PORTC3 PORTC2 DDC4 DDC3 DDC2 PINC4 PINC3 PINC2 PORTD4 PORTD3 PORTD2 DDD4 DDD3 DDD2 PIND4 PIND3 PIND2 SPI Data Register – – – MSTR CPOL CPHA USART I/O Data Register FE DOR PE RXEN TXEN UCSZ2 USART Baud Rate Register Low byte ACI ACIE ACIC – MUX3 MUX2 ADIF ADIE ADPS2 ADC Data Register High byte ADC Data Register Low byte Two-wire Serial Interface Data Register TWA3 TWA2 TWA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 – SPR1 U2X RXB8 ACIS1 MUX1 ADPS1 TWA0 Bit 0 C SP8 SP0 IVCE – TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00 PSR10 WGM10 CS10 CS20 TCR2UB WDP0 UCPOL EEAR8 EEAR0 EERE PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 TWGCE Page 11 13 13 49, 67 68 72, 102, 122 73, 102, 122 213 171 33, 66 41 72 72 31 58, 75, 123, 193 96 100 101 101 101 101 101 101 102 102 117 119 119 119 43 158 156 20 20 20 20 65 65 65 65 65 65 65 65 65 131 131 129 153 154 155 158 194 205 207 208 208 173 174 2486T–AVR–05/08 287 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 173 0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register 171 Notes: 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 288 ATmega8(L) 2486T–AVR–05/08 Instruction Set Summary Mnemonics Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. SBIW Rdl,K Subtract Immediate from Word AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One’s Complement NEG Rd Two’s Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register MUL Rd, Rr Multiply Unsigned MULS Rd, Rr Multiply Signed MULSU Rd, Rr Multiply Signed with Unsigned FMUL Rd, Rr Fractional Multiply Unsigned FMULS Rd, Rr Fractional Multiply Signed FMULSU Rd, Rr Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP Indirect Jump to (Z) RCALL k Relative Subroutine Call ICALL Indirect Call to (Z) RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared Mnemonics Operands Description 2486T–AVR–05/08 ATmega8(L) Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 PC ← PC + k + 1 PC ← Z PC ← PC + k + 1 PC ← Z PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None Flags #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 #Clocks 289 Instruction Set Summary (Continued) BRIE k BRID k DATA TRANSFER INSTRUCTIONS MOV Rd, Rr MOVW Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LPM LPM Rd, Z LPM Rd, Z+ SPM IN Rd, P OUT P, Rr PUSH Rr POP Rd BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET Mnemonics Operands Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Description 290 ATmega8(L) if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X), X ← X + 1 X ← X - 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y - 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (Z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Rd ← STACK I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 Operation None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T Flags 1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 #Clocks 2486T–AVR–05/08 Instruction Set Summary (Continued) CLT SEH CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset ATmega8(L) T←0 H←1 H←0 T 1 H 1 H 1 None 1 (see specific descr. for Sleep function) None 1 (see specific descr. for WDR/timer) None 1 2486T–AVR–05/08 291 Ordering Information Speed (MHz) Power Supply 8 2.7 - 5.5 16 4.5 - 5.5 Ordering Code ATmega8L-8AU(2) ATmega8L-8PU(2) ATmega8L-8MU(2) ATmega8-16AU(2) ATmega8-16PU(2) ATmega8-16MU(2) Package(1) 32A 28P3 32M1-A 32A 28P3 32M1-A Operation Range Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 32A 28P3 32M1-A Package Type 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 292 ATmega8(L) 2486T–AVR–05/08 Packaging Information 32A ATmega8(L) PIN 1 e PIN 1 IDENTIFIER B E1 E D1 D C 0˚~7˚ A1 A2 L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.05 A2 0.95 D 8.75 D1 6.90 E 8.75 E1 6.90 B 0.30 C 0.09 L 0.45 e NOM – – 1.00 9.00 7.00 9.00 7.00 – – – 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 10/5/2001 DRAWING NO. REV. 32A B 2486T–AVR–05/08 293 28P3 D PIN 1 E1 A SEATING PLANE L e A1 B2 B1 B (4 PLACES) E C 0º ~ 15º REF eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A – A1 0.508 D 34.544 E 7.620 E1 7.112 B 0.381 B1 1.143 B2 0.762 L 3.175 C 0.203 eB – e NOM MAX NOTE – 4.5724 – – – 34.798 Note 1 – 8.255 – 7.493 Note 1 – 0.533 – 1.397 – 1.143 – 3.429 – 0.356 – 10.160 2.540 TYP TITLE 2325 Orchard Parkway 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual R San Jose, CA 95131 Inline Package (PDIP) 09/28/01 DRAWING NO. REV. 28P3 B 294 ATmega8(L) 2486T–AVR–05/08 32M1-A D D1 1 2 3 Pin 1 ID ATmega8(L) 0 E1 E SIDE VIEW P P TOP VIEW A2 K A D2 Pin #1 Notch (0.20 R) 1 2 3 E2 K b e L BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. A3 A1 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e L P 0 K MIN 0.80 – – 0.18 4.90 4.70 2.95 4.90 4.70 2.95 0.30 – – 0.20 NOM 0.90 0.02 0.65 0.20 REF 0.23 5.00 4.75 3.10 5.00 4.75 3.10 0.50 BSC 0.40 – – – MAX 1.00 0.05 1.00 0.30 5.10 4.80 3.25 5.10 4.80 3.25 0.50 0.60 12o – NOTE TITLE 2325 Orchard Parkway 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, R San Jose, CA 95131 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) 5/25/06 DRAWING NO. REV. 32M1-A E 2486T–AVR–05/08 295 Errata ATmega8 Rev. D to I The revision letter in this section refers to the revision of the ATmega8 device. • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • Signature may be Erased in Serial Programming Mode • CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 • Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix / Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. Problem Fix / Workaround Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 3. Signature may be Erased in Serial Programming Mode If the signature bytes are read before a chiperase command is completed, the signature may be erased causing the device ID and calibration bytes to disappear. This is critical, especially, if the part is running on internal RC oscillator. Problem Fix / Workaround: Ensure that the chiperase command has exceeded before applying the next command. 4. CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 When the internal RC Oscillator is used as the main clock source, it is possible to run the Timer/Counter2 asynchronously by connecting a 32 KHz Oscillator between XTAL1/TOSC1 and XTAL2/TOSC2. But when the internal RC Oscillator is selected as the main clock source, the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and XTAL2/TOSC2. As long as there are no capacitors connected to XTAL1/TOSC1 and XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed. Problem Fix / Workaround Use external capacitors in the range of 20 - 36 pF on XTAL1/TOSC1 and XTAL2/TOSC2. This will be fixed in ATmega8 Rev. G where the CKOPT Fuse will control internal capacitors also when internal RC Oscillator is selected as main clock source. For ATmega8 Rev. G, CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. Customers who want compatibility between Rev. G and older revisions, must ensure that CKOPT is unprogrammed (CKOPT = 1). 5. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. 296 ATmega8(L) 2486T–AVR–05/08 Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. ATmega8(L) 2486T–AVR–05/08 297 Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 1. Updated Table 98 on page 240. 2486S- 08/07 to Rev. 2486T- 05/08 2. Updated “Ordering Information” on page 292. - Commercial Ordering Code removed. - No Pb-free packaging option removed. Changes from Rev. 1. Updated “Features” on page 1. 2486R- 07/07 to Rev. 2486S- 08/07 2. Added “Data Retention” on page 7. 3. Updated “Errata” on page 296. 4. Updated “Slave Mode” on page 129. Changes from Rev. 1. Added text to Table 81 on page 218. 2486Q- 10/06 to Rev. 2486R- 07/07 2. Fixed typo in “Peripheral Features” on page 1. 3. Updated Table 16 on page 42. 4. Updated Table 75 on page 206. 5. Removed redundancy and updated typo in Notes section of “DC Characteristics” on page 242. Changes from Rev. 1. Updated “Timer/Counter Oscillator” on page 32. 2486P- 02/06 to Rev. 2486Q- 10/06 2. Updated “Fast PWM Mode” on page 89. 3. Updated code example in “USART Initialization” on page 138. 4. Updated Table 37 on page 97, Table 39 on page 98, Table 42 on page 117, Table 44 on page 118, and Table 98 on page 240. 5. Updated “Errata” on page 296. Changes from Rev. 1. Added “Resources” on page 7. 2486O-10/04 to Rev. 2486P- 02/06 2. Updated “External Clock” on page 32. 3. Updated “Serial Peripheral Interface – SPI” on page 124. 4. Updated Code Example in “USART Initialization” on page 138. 298 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) 5. Updated Note in “Bit Rate Generator Unit” on page 170. 6. Updated Table 98 on page 240. 7. Updated Note in Table 103 on page 248. 8. Updated “Errata” on page 296. Changes from Rev. 1. Removed to instances of “analog ground”. Replaced by “ground”. 2486N-09/04 to Rev. 2486O-10/04 2. Updated Table 7 on page 29, Table 15 on page 38, and Table 100 on page 244. 3. Updated “Calibrated Internal RC Oscillator” on page 30 with the 1 MHz default value. 4. Table 89 on page 225 and Table 90 on page 225 moved to new section “Page Size” on page 225. 5. Updated descripton for bit 4 in “Store Program Memory Control Register – SPMCR” on page 213. 6. Updated “Ordering Information” on page 292. Changes from Rev. 1. Added note to MLF package in “Pin Configurations” on page 2. 2486M-12/03 to Rev. 2486N-09/04 2. Updated “Internal Voltage Reference Characteristics” on page 42. 3. Updated “DC Characteristics” on page 242. 4. ADC4 and ADC5 support 10-bit accuracy. Document updated to reflect this. Updated features in “Analog-to-Digital Converter” on page 196. Updated “ADC Characteristics” on page 248. 5. Removed reference to “External RC Oscillator application note” from “External RC Oscillator” on page 28. Changes from Rev. 1. Updated “Calibrated Internal RC Oscillator” on page 30. 2486L-10/03 to Rev. 2486M-12/03 Changes from Rev. 1. Removed “Preliminary” and TBDs from the datasheet. 2486K-08/03 to Rev. 2486L-10/03 2. Renamed ICP to ICP1 in the datasheet. 3. Removed instructions CALL and JMP from the datasheet. 4. Updated tRST in Table 15 on page 38, VBG in Table 16 on page 42, Table 100 on page 244 and Table 102 on page 246. 5. Replaced text “XTAL1 and XTAL2 should be left unconnected (NC)” after Table 9 in “Calibrated Internal RC Oscillator” on page 30. Added text regarding XTAL1/XTAL2 and CKOPT Fuse in “Timer/Counter Oscillator” on page 32. 2486T–AVR–05/08 299 6. Updated Watchdog Timer code examples in “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45. 7. Removed bit 4, ADHSM, from “Special Function IO Register – SFIOR” on page 58. 8. Added note 2 to Figure 103 on page 215. 9. Updated item 4 in the “Serial Programming Algorithm” on page 238. 10. Added tWD_FUSE to Table 97 on page 239 and updated Read Calibration Byte, Byte 3, in Table 98 on page 240. 11. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics” on page 242. Changes from Rev. 1. Updated VBOT values in Table 15 on page 38. 2486J-02/03 to Rev. 2486K-08/03 2. Updated “ADC Characteristics” on page 248. 3. Updated “ATmega8 Typical Characteristics” on page 249. 4. Updated “Errata” on page 296. Changes from Rev. 1. Improved the description of “Asynchronous Timer Clock – clkASY” on page 26. 2486I-12/02 to Rev. 2486J-02/03 2. Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz Crystal Oscillator” application note, which do not exist. 3. Corrected OCn waveforms in Figure 38 on page 90. 4. Various minor Timer 1 corrections. 5. Various minor TWI corrections. 6. Added note under “Filling the Temporary Buffer (Page Loading)” on page 216 about writing to the EEPROM during an SPM Page load. 7. Removed ADHSM completely. 8. Added section “EEPROM Write during Power-down Sleep Mode” on page 23. 9. Removed XTAL1 and XTAL2 description on page 5 because they were already described as part of “Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/TOSC2” on page 5. 10. Improved the table under “SPI Timing Characteristics” on page 246 and removed the table under “SPI Serial Programming Characteristics” on page 241. 11. Corrected PC6 in “Alternate Functions of Port C” on page 61. 12. Corrected PB6 and PB7 in “Alternate Functions of Port B” on page 58. 13. Corrected 230.4 Mbps to 230.4 kbps under “Examples of Baud Rate Setting” on page 159. 300 ATmega8(L) 2486T–AVR–05/08 ATmega8(L) 14. Added information about PWM symmetry for Timer 2 in “Phase Correct PWM Mode” on page 113. 15. Added thick lines around accessible registers in Figure 76 on page 169. 16. Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits under “Performing a Page Write” on page 216. 17. Added note for RSTDISBL Fuse in Table 87 on page 223. 18. Updated drawings in “Packaging Information” on page 293. Changes from Rev. 1. Added errata for Rev D, E, and F on page 296. 2486H-09/02 to Rev. 2486I-12/02 Changes from Rev. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. 2486G-09/02 to Rev. 2486H-09/02 Changes from Rev. 1. Updated Table 103, “ADC Characteristics,” on page 248. 2486F-07/02 to Rev. 2486G-09/02 Changes from Rev. 1. Changes in “Digital Input Enable and Sleep Modes” on page 55. 2486E-06/02 to Rev. 2486F-07/02 2. Addition of OCS2 in “MOSI/OC2 – Port B, Bit 3” on page 59. 3. The following tables have been updated: Table 51, “CPOL and CPHA Functionality,” on page 132, Table 59, “UCPOL Bit Settings,” on page 158, Table 72, “Analog Comparator Multiplexed Input(1),” on page 195, Table 73, “ADC Conversion Time,” on page 200, Table 75, “Input Channel Selections,” on page 206, and Table 84, “Explanation of Different Variables used in Figure 103 and the Mapping to the Z-pointer,” on page 221. 4. Changes in “Reading the Calibration Byte” on page 234. 5. Corrected Errors in Cross References. Changes from Rev. 1. Updated Some Preliminary Test Limits and Characterization Data 2486D-03/02 to The following tables have been updated: Rev. 2486E-06/02 Table 15, “Reset Characteristics,” on page 38, Table 16, “Internal Voltage Reference Char- acteristics,” on page 42, DC Characteristics on page 242, Table , “ADC Characteristics,” on page 248. 2. Changes in External Clock Frequency Added the description at the end of “External Clock” on page 32. Added period changing data in Table 99, “External Clock Drive,” on page 244. 3. Updated TWI Chapter 2486T–AVR–05/08 301 More details regarding use of the TWI bit rate prescaler and a Table 65, “TWI Bit Rate Prescaler,” on page 173. Changes from Rev. 1. Updated Typical Start-up Times. 2486C-03/02 to The following tables has been updated: Rev. 2486D-03/02 Table 5, “Start-up Times for the Crystal Oscillator Clock Selection,” on page 28, Table 6, “Start-up Times for the Low-frequency Crystal Oscillator Clock Selection,” on page 28, Table 8, “Start-up Times for the External RC Oscillator Clock Selection,” on page 29, and Table 12, “Start-up Times for the External Clock Selection,” on page 32. 2. Added “ATmega8 Typical Characteristics” on page 249. Changes from Rev. 1. Updated TWI Chapter. 2486B-12/01 to More details regarding use of the TWI Power-down operation and using the TWI as Master Rev. 2486C-03/02 with low TWBRR values are added into the datasheet. Added the note at the end of the “Bit Rate Generator Unit” on page 170. Added the description at the end of “Address Match Unit” on page 170. 2. Updated Description of OSCCAL Calibration Byte. In the datasheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: Improved description of “Oscillator Calibration Register – OSCCAL” on page 31 and “Calibration Byte” on page 225. 3. Added Some Preliminary Test Limits and Characterization Data. Removed some of the TBD’s in the following tables and pages: Table 3 on page 26, Table 15 on page 38, Table 16 on page 42, Table 17 on page 44, “TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)” on page 242, Table 99 on page 244, and Table 102 on page 246. 4. Updated Programming Figures. Figure 104 on page 226 and Figure 112 on page 237 are updated to also reflect that AVCC must be connected during Programming mode. 5. Added a Description on how to Enter Parallel Programming Mode if RESET Pin is Disabled or if External Oscillators are Selected. Added a note in section “Enter Programming Mode” on page 228. 302 ATmega8(L) 2486T–AVR–05/08 Table of Contents Features 1 Pin Configurations 2 Overview 3 Block Diagram 3 Disclaimer 4 Pin Descriptions 5 Resources 7 Data Retention 7 About Code Examples 8 AVR CPU Core 9 Introduction 9 Architectural Overview 9 Arithmetic Logic Unit – ALU 11 Status Register 11 General Purpose Register File 12 Stack Pointer 13 Instruction Execution Timing 13 Reset and Interrupt Handling 14 AVR ATmega8 Memories 17 In-System Reprogrammable Flash Program Memory 17 SRAM Data Memory 18 Data Memory Access Times 19 EEPROM Data Memory 19 I/O Memory 24 System Clock and Clock Options 25 Clock Systems and their Distribution 25 Clock Sources 26 Crystal Oscillator 27 Low-frequency Crystal Oscillator 28 External RC Oscillator 28 Calibrated Internal RC Oscillator 30 External Clock 32 Timer/Counter Oscillator 32 Power Management and Sleep Modes 33 Idle Mode 34 2486T–AVR–05/08 ATmega8(L) i ADC Noise Reduction Mode 34 Power-down Mode 34 Power-save Mode 34 Standby Mode 35 Minimizing Power Consumption 35 System Control and Reset 37 Internal Voltage Reference 42 Watchdog Timer 43 Timed Sequences for Changing the Configuration of the Watchdog Timer 45 Interrupts 46 Interrupt Vectors in ATmega8 46 I/O Ports 51 Introduction 51 Ports as General Digital I/O 51 Alternate Port Functions 56 Register Description for I/O Ports 65 External Interrupts 66 8-bit Timer/Counter0 69 Overview 69 Timer/Counter Clock Sources 70 Counter Unit 70 Operation 70 Timer/Counter Timing Diagrams 71 8-bit Timer/Counter Register Description 72 Timer/Counter0 and Timer/Counter1 Prescalers 74 16-bit Timer/Counter1 76 Overview 76 Accessing 16-bit Registers 79 Timer/Counter Clock Sources 82 Counter Unit 82 Input Capture Unit 83 Output Compare Units 84 Compare Match Output Unit 87 Modes of Operation 88 Timer/Counter Timing Diagrams 95 16-bit Timer/Counter Register Description 96 8-bit Timer/Counter2 with PWM and Asynchronous Operation 104 Overview 104 ii ATmega8(L) 2486T–AVR–05/08 2486T–AVR–05/08 ATmega8(L) Timer/Counter Clock Sources 105 Counter Unit 106 Output Compare Unit 107 Compare Match Output Unit 109 Modes of Operation 110 Timer/Counter Timing Diagrams 114 8-bit Timer/Counter Register Description 117 Asynchronous Operation of the Timer/Counter 119 Timer/Counter Prescaler 123 Serial Peripheral Interface – SPI 124 SS Pin Functionality 129 Data Modes 132 USART 133 Overview 133 Clock Generation 134 Frame Formats 137 USART Initialization 138 Data Transmission – The USART Transmitter 140 Data Reception – The USART Receiver 143 Asynchronous Data Reception 147 Multi-processor Communication Mode 151 Accessing UBRRH/UCSRC Registers 152 USART Register Description 153 Examples of Baud Rate Setting 159 Two-wire Serial Interface 163 Features 163 Two-wire Serial Interface Bus Definition 163 Data Transfer and Frame Format 164 Multi-master Bus Systems, Arbitration and Synchronization 167 Overview of the TWI Module 169 TWI Register Description 171 Using the TWI 174 Transmission Modes 178 Multi-master Systems and Arbitration 191 Analog Comparator 193 Analog Comparator Multiplexed Input 195 Analog-to-Digital Converter 196 Features 196 Starting a Conversion 198 Prescaling and Conversion Timing 198 Changing Channel or Reference Selection 200 iii ADC Noise Canceler 201 ADC Conversion Result 205 Boot Loader Support – Read-While-Write Self-Programming 209 Boot Loader Features 209 Application and Boot Loader Flash Sections 209 Read-While-Write and No Read-While-Write Flash Sections 209 Boot Loader Lock Bits 211 Entering the Boot Loader Program 212 Addressing the Flash During Self-Programming 214 Self-Programming the Flash 215 Memory Programming 222 Program And Data Memory Lock Bits 222 Fuse Bits 223 Signature Bytes 225 Calibration Byte 225 Page Size 225 Parallel Programming Parameters, Pin Mapping, and Commands 226 Parallel Programming 228 Serial Downloading 237 Serial Programming Pin Mapping 237 Electrical Characteristics 242 Absolute Maximum Ratings* 242 DC Characteristics 242 External Clock Drive Waveforms 244 External Clock Drive 244 Two-wire Serial Interface Characteristics 245 SPI Timing Characteristics 246 ADC Characteristics 248 ATmega8 Typical Characteristics 249 Register Summary 287 Instruction Set Summary 289 Ordering Information 292 Packaging Information 293 32A 293 28P3 294 32M1-A 295 Errata 296 iv ATmega8(L) 2486T–AVR–05/08 ATmega8(L) ATmega8 Rev. D to I 296 Datasheet Revision History 298 Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08 298 Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07 298 Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07 298 Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06 298 Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06 298 Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04 299 Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04 299 Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03 299 Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03 299 Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03 300 Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03 300 Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02 301 Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02 301 Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02 301 Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02 301 Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02 301 Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02 302 Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02 302 Table of Contents i v 2486T–AVR–05/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, AVR® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 2486T–AVR–05/08

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