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A 10-b 20-Msample Low-Power CMOS ADC

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    514 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 5, MAY 1995 A 10-b 20-Msample/s Low-Power CMOS ADC Won-Chul Song, Hae-Wook Choi, Sung-Ung Kwak,and Bang-Sup Song, Senior Member, ZEEE Absfruct- A single-ended input but internally differential 10 b, 20 Msamplds pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer ampliers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly1.2 pm CMOS technology exhibits a DNL of f0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm’. I. INTRODUCTION IN RECENT YEARS, digital processing power has grown as technologies are scaled down, but analog processing power has not kept up with the fast-growing demand in areas such as high-definition video reproduction, computer graphics, Xray and medical imaging, digital instrumentation, and data communications. The future trend of portable computers, wireless, and multimedia demands that analog front ends be designed for low-power battery operation. Furthermore, applications of digital signal processing to video signals for products such as digital camcorder, digital copy machine, digital VCR, and digital TV have created a need for low-power 10-b ADC’s in low-cost IC package. For 10-b applications, parallel flash-type A/D converters are useful but require large chip area and high power consumption. As a result, many alternative low-power solutions have been developed based on multistep pipelined or subranging architectures, which usually trade speed for small area and low power. Monolithic 10-b video ADC’s have been demonstrated to operate at 20-300 MHz using either bipolar or BiCMOS [1]-[8], but the conversion speed achievable with CMOS has been limited to 50 MHz [9]-[17]. Although bipolar or BiCMOS converters have been reported to be faster than CMOS converters, they also tend to consume high power. Recently, a CMOS 10-b ADC was demonstrated to operate at 20 MHz with only 30 mW using a 2.5 V single supply [ 131, but Manuscript received June 20, 1994; revised October 11, 1994. This work was supported in part by the National Science Foundation under Grant MIP93 12671. W.-C. Song and H.-W. Choi are with the Electronics and Telecommunications Research Institute, Daejeon, Korea. S.-U. Kwak and B.-S. Song are with the Coordinated Science Laboratory, Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL 61801 USA. IEEE Log Number 9408448. the interpolated pipelining technique using CMOS inverters suffers from noise coupling due to its single-ended implementation. To date, fully-differential 10-b CMOS ADC’s, that are known to be less sensitive to noise, have been demonstrated with 135 to 250 mW [lo], [ll], [16], [17]. This work proves the feasibility of implementing a 10-b 20 Msample/s singleended input but internally differential ADC with 50 mW. A recent work with a similar goal to reduce power of differential pipelined ADC’s was also reported independently [181. The pipelined ADC architecture, due to its simplicity, can potentially achieve high resolution at high conversion rates [19], [20]. Coupled with digital correction [21], video-rate ADC’s has been demonstrated using low-resolution comparator [l 11. The prototype is based on this pipelined architecture, but designed with a power budget of 50 mW using a single 5 V supply. Although the ADC is internally differential, it accepts a 0-2 V single-ended input, and owes its low-power high-speed performance to several circuit techniques refined for this prototype as highlighted in the following. Source-follower buffered op amp to use large input devices for high speed settling. Self-biased biasing circuit for cascode stages. Dynamic comparator with no static power consumption PI. Capacitive reference voltage divider in place of resistorstring DAC. In Section 11, design issues related to high-speed pipelined ADC’s are reviewed, and requirements of capacitor matching and op amp dc gain are defined through analysis and behavioral simulations. In Sections I11 and IV, system features and circuits refined for this prototype are described, and experimental results are summarized. 11. DESIGNCONSIDERATIONS FOR PIPELINED ADC In general, multistage ADC’s are made of cascaded lowresolution ADC’s. Each low-resolution ADC stage provides a residue voltage for the subsequent stage, and the accuracy of the residue voltage limits the resolution of the converter if digital correction based on redundancy is applied. One of the residue amplifiers commonly used is a switched-capacitor multiplying digital-to-analog converter (MDAC), whose connections during 2 clock phases are illustrated in Fig. 1 for an N-b case. An extra capacitor C is usually added to double the feedback capacitor size so that the residue voltage may remain within the full-scale range for digital correction. For a 10-b ADC, the number of bits per stage (N) can range from 2 to 5. Fig. 2 shows an MDAC during the amplification phase in a simplified multiply-by-2 case. This residue amplifier has 0018-9200/95$04.00 0 1995 IEEE SONG et al.: A 10-b 20-MSAMPLEJS LOW-POWER CMOS ADC 515 L Digital inputs I t I/: i J Fig. 1. 8 General N-b residue amplifier: (a) Sampling phase and (b) multiply-b~-2a~mplification phase. 8 9 10 11 12 13 14 15 ADC Linesdty (bits) Fig. 3. Cumulative distributions obtained by Monte Carlo simulations for different capacitormismatches. Cases of a 9-stage pipelined ADC ( N = 2) and a 2-step ADC ( N = 5). Fig. 2. A 2-b residue amplifier during multiply-by-2 amplification phase. C, is the parasitic capacitance. This gain error should be smaller than 1 LSB of the subsequent ADC stages. Furthermore, the op amp settles with a longer time constant of + c1+c2 7% c, x -, 1 (3) c2 2rfunity an output of if the op amp has an infinite gain [19]. Since the reference voltage appearing at the output of this residue amplifier should match the reference voltage of the subsequent stage within 1 LSB, the matching of capacitors C1 and C2 becomes a fundamental limit. If a large number of bits are resolved per stage (N > a), the capacitor matching requirement is reduced [23]. The behavioral model simulation results of Fig. 3 show the matching requirements for two different N’s for comparison. The y-axis represents a cumulative distribution, and the z-axis is an ADC linearity calculated in terms of the worst-case DNL or endpoint INL, whichever is larger. Two cumulative distributions shown on the left are obtained using a standard deviation of 0.2% and 0.1%, respectively, in capacitor matching for a 9stage pipelined ADC (N = 2), but two on the right for a 2-step ADC ( N = 5). High op amp gain is used in the Monte Carlo simulations to separate the capacitor mismatch effect from the op amp gain effect. If N is increased, capacitors do not need to be matched precisely as shown in Fig. 3, but op amp should settle with a lower feedback factor. If op amp gain is finite, the parasitic capacitance, C,, at the summing node of the op amp has a significant effect on gain and settling of the residue amplifier. With a finite dc gain of A,, the residue output of (1) has a gain error of L 6 x - cl + cz + cp Kef. (2) (72 A0 where funity is the open-loop unity-gain bandwidth of the op amp ~ 4 1 . The main source of the parasitic capacitance C, is the op amp input device usually made large for wide bandwidth in video-rate ADC’s. The situation gets worse since capacitor sizes are scaled down for the same reason to achieve wide bandwidth. The typical size of op amp input capacitance is on the order of 0.5 to 1 pF including input device Miller capacitance. As a result, the gain-of-2 feedback of Fig. 2 using small capacitors, C1 and C2,of 0.1 pF ends up with a feedback factor of 0.1 to 0.2 if C, is considered. This implies that op amp gain should be well over 70 dB for typical pipelined 10-b ADC’s. The high-gain requirement of (2) can be reduced by canceling,the op amp input Miller capacitance with a negative Miller capacitance [25], but the narrowbanding effect of (3) is not improved by this negative Miller capacitance method since the Miller effect diminishes as op amp gain decreases at high frequencies. The reduced gain and narrowbanding effects due to the parasitic capacitance are less stringent in the case of N > 2 because the feedback factor is lower and the parasitic effect decreases in proportion. The same Monte Carlo simulations as in Fig. 3 are repeated in Fig. 4 using 0.1% capacitor mismatch and two finite dc gains of 70 dB and 80 dB. As is shown in Figs. 3 and 4, both the capacitor matching and gain requirements are reduced if N increases, but the op amp feedback loop bandwidth shrinks. It is possible to achieve a wider feedback loop bandwidth with smaller N, but the narrowbanding effect of (3) due to the parasitic capacitance becomes more severe. Therefore, the question of what is the optimum number of bits per stage boils down to op amp design 516 I loo - I I I I I .---I I e- 8- 2f - 5 0 8- 0 I I I I I I I I IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 5 , MAY 1995 A simple way to do this conversion is to use a commonmode rejection property of a differential amplifier unless a wideband voltage inverter is used. In switched-capacitor circuits, the voltage mapping given by (4)is done as shown in Fig. 6. During the first sampling phase shown in Fig. 6(a), the single-ended input signal is applied to the one of the sampling capacitors and the other sampling capacitor is precharged to the most negative supply voltage, 0 V. To simultaneously shift the input common-mode voltage up by 2.5 V and the output differential voltage down by -1 V during the amplification phase, Vref-and Vrefa+re applied to the holding capacitors, where Kef- and Vrefa+re 2 V and 3 V, respectively, in this single 5 V system. During the subsequent holding phase, the issue, and still leaves room for debate. This work addresses an issue of using a source-follower buffered op amp in the next section. figure). Fully-differential bottom-plate open-loop sampling has been demonstrated to exhibit a 12 b linearity at a 50 MHz sampling rate [26], but there are many problems in single-ended sam- 111. TECHNIQUES FOR LOW-POWERPIPELINED ADC pling. Two of the problems are input common-mode voltage swing and signal dependent feedthrough. In the single-ended- Most switched-capacitor ADC’s are implemented differen- to-differential conversion process, the op amp input commontially. However, in reality, the standard NTSC video signal in mode voltage does not change if the switch connecting two TV, VCR, and camcorder is a 1 VP-,single-ended signal. To bottom plates is an ideal switch. However, nonideal MOS make an ADC with a single-ended input, the prototype has a single-in differential-out S/H circuit at the front, followed by 8 identical unscaled pipelined subconverter stages [111, each containing a 2-b flash ADC and a 2-b MDAC. The switch, due to its channel capacitance, draws charges from the bottom plates of the two input capacitors and changes the input common-mode voltage by capacitive coupling. This common-mode voltage swing becomes large as capacitors last of the chain is a 3-b flash ADC. Each 2-b flash ADC are made small and switches are made large for high-speed produces an extra redundant bit for digital correction. This operation. Although common-mode input swing has no effect pipelined architecture using 2-phase nonoverlapping clocks on differential amplifiers in principle, cascoded input stages plus an additional early turn-off clock is well known, and typically used in pipelined ADC’s do not have room for input no further descriptions on the architecture will be given in common-mode swing. In typical differential implementations, this paper. Therefore, the discussion is limited only to design issues for low power and several circuit refinements made for this work. As is common in switched-capacitor circuits, the top plate of a 0.1 pF unit capacitor is switched by an NMOS the bottom plates are switched to the input common-mode voltage to reduce this common-mode voltage swing. Similarly, in the single-ended case, the input voltage can be sampled and divided by 2 to provide the input common-mode voltage switch (611.2) only, but the bottom plate is switched by both for the bottom plates using an extra buffer amplifier. In NMOS (1211.2) and PMOS (3611.2) switches. this low-power implementation, the input differential pair is biased carefully so that the op amp can tolerate the worst-case common-mode voltage swing for the 0 to 2 V single-ended A. Single-Ended Input But Internally Differential Architecture signal. The signal-dependent feedthrough problem is more The ADC is designed to take a 0 to 2 V single-ended severe in the single-ended sampling due to the dependence input with a single 5 V supply. As shown in Fig. 5(a), the of the switch on-resistance on the input signal magnitude 0 V single-ended input is mapped to differential -1 V with a although the standard technique to turn off the top plate first common-mode voltage of 2.5 V. Similarly, the 1 V and 2 V is used [27]. inputs are mapped to differential 0 V and 1 V as explained in Fig. 5(b) and (c), respectively. That is, the input S/H converts the single-ended input Kn into the differential output V0, B. Source Follower Buffered Op Amp with using Self-Biased Biasing Circuit Vout = V n - Kef, where Vref= 1 V. (4) As explained using (l)-(3), the parasitic capacitance C, at the op amp summing node is a dominant factor limiting accuracy and settling of the residue amplifier in the 9-stage SONG et al.: A 10-b 20-MSAMF'LWS LOW-POWER CMOS ADC 517 5v ...................... ...................... ...................... 4v .............................. p 3v ............... Vout- ........... vo"t+ 2v 1v .............................. ...................... ...................... %- Vout+ ...................... -1 ........... ...................... -Y -1 ........... - vout+ Vout- 0 ...................... ov - I @! ........... ...................... ...................... (a) @) (C) Fig. 5. Voltage level conversion from single-ended to differential system: (a) 0 V, (b) 1 V, and (c) 2 V. +IC '1 O Vref- VDD - Bias6 1 1 GND Fig. 7. Source-followerbuffered triple-cascodeop amp. (b) Fig. 6. Input S/H converting single-ended input to differential signal. (a) Sampling phase and (b) amplification phase. pipelined ADC. In this video-rate ADC, the unit capacitor size is scaled down to 0.1 pF, and the W/L ratio of 200A.2 is used for the op amp input devices. As a result, settling is severely slowed due to the narrowbanding effect. The solution to this narrowbanding problem is either to use a preamplifier or to use a source follower at the op amp input. The former approach, though promising, introduces a nondominant pole due to the gain of the preamplifier, which will decrease the phase margin of the feedback amplifier and will slow the settling process even marginally. The latter approach has a wider bandwidth because the source follower has a gain close to unity while effectively reducing the input capacitance of the op amp. The input buffered op amp is shown in Fig. 7, where the source follower with W/L of 120/1.2drives the input Miller capacitance of the triple-cascode differential pair. Due to several levels of cascoding in the triple-cascode op amp, stable biasing of the amplifier is of paramount inter- est. m i c a l cascode biasing circuits do not have accurately matched bias currents for NMOS and PMOS cascodes because of gain error in the current mirrors. The shorter the channel of the current mirror devices, the more gain error results from channel length modulation. The self-biased circuit shown in Fig. 8 operates each cascode biasing transistor in the same condition as its counterpart in the actual triple-cascode op -- -__-_-_-- --- - amIn.Fnr eram~nl*e- ,the him 1-11 v1n-l- tn_mbI-=lx -A,-' and -AP- f-n--r N-.M-.-O-S- and PMOS devices as well as the threshold voltages of cascode devices are replicated to trac-k p-ower supply variation. A sma-~ll transistor named M p is a leaky transistor to start th~ e self- biased circuit. Without the self-biasing feedback, A, and Ap are generated with different bias conditions, and are more sensitive to supply variation. The input and output common- mode voltages of the op amp are internally buffered using a unity-gain buffer made of a single-stage differential pair. This buffer guarantees an exponential settling of switching transients of the common-mode bias lines. Two internal class- A buffers consume a considerable portion of the total power of the prototype ADC. 518 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 5, MAY 1995 VDD Fig. 8. Self-biased biasing circuit for triple cascode op amp. C. Dynamic Comparator Consuming No Static comparator consumes power only during transients. As shown Power with Capacitive Reference Divider A is a key block in data At a circuit level, many efforts have been made to reduce op amp power, but power consumption of comparators has been rela- tively neglected. In general, comparators need a preamplifier to amplify a small seed signal to a level high enough to latch. Although most comparators differ from one another depending on their resolution, the simplest is a positive-feedback latch made of two inverters connected back to back. This latch-type comparator consumes a considerable amount of power either in the SPICE output of Fig. 10, the su. pp_ l.y current of the existing comparator (dotted line) still flows after latched since either MN3 or MN4 is conducting. However, the proposed one (solid line) completely shuts off the supply current. All devices in the latch are sized as 4A.2 except for MP1 and M E , which are made 4 times larger for fast pull-up. The latch output flips in 2 ns for a 2 mV input in SPICE simulations. Most flash-type ADC’s generate fractions of the reference voltage using a resistor-string voltage divider, called a resistor- string DAC. The resistor-string DAC increasingly power if small resistor value is used to reduce the RC when it seed for Or when time constant for fast conversion. Since the pipelined converter the Output flips to One state. The power is not a does not require accurately divided reference voltages, this major if Only One Or two comparators are used, but work uses a dynamic capacitive reference divider 1151 as in pipelined ADC’s, power consumption in comparators is not shown in ~ i 11~so t.hat the sampled input may be compared One of the advantages of the Pipelined ADC with to Vref/4. During the initialization phase, all capacitors are digital Correction iS the Use Of lOW-reSOlUtiOn Comparator such discharged as in Fig. 1l(a). When the input is applied during as a positive-feedback latch. the subsequent phase as in Fig. ll(b), the larger capacitor C Fig. 9 shows two comparators. One is a typical dynamic takes the input, but the smaller capacitor C/4 is connected to comparator frequently used in recent works [281, and the other -VIef. Then the top plate voltage of the two-capacitor DAC is the proposed one that does not consume static power [22]. becomes Two comparators differ from each other in the way that the input devices MN3 and MN4 are connected. In the existing comparator of Fig. 9(a), these input devices are connected in parallel with the latch, but in the proposed comparator of Fig. 9(b), they are inserted into two branches of the latch. Both (..-?), + vtop = 1.25C C, (5) where c p is the Parasitic capacitance at the top Plate. This seed signal applied differentially to the input of the comparator Can comparators are identical in operation except for the power be latched using a dynamic comparator discussed- consumption in the latched state. If the Latch pulse is low, the supply current is cut off in both comparators, and the outputs I v . EXPERIMENTRAELSULTS are connected to VDD. Then the input transistors MN3 and An experimental prototype pipelined ADC based on the MN4 are in triode mode. If a seed signal is applied to these two concepts described in the previous section is implemented MOS gates differentially and the Latch pulse goes high, the using a 1.2 ,um double-poly double-metal CMOS technology. output of the stronger side of MN3 and MN4 is pulled down As discussed, the system is made of a S/H plus 8 identical more strongly than the other side. This will cause the latch to unscaled pipelined stages with digital correction. In the pro- flip to one of the two stable states. The proposed comparator posed pipelined converter, static power is consumed only in of Fig. 9(b) shuts off power supply current, while the existing the op amp of Fig. 7, where each branch is biased with 200 one of Fig. 9(a) does not. Like a CMOS inverter, the proposed PA. The reference voltages for the last 3-b ADC are also SONG et al.: A 10-b 20-MSAMPLEJS LOW-POWER CMOS ADC 519 VDD GND T i e (nsec) Fig. 10. Power supply current of two comparators during 2 clock phases: Existing one (dotted line) and proposed one (solid line). Latch VDD H+ tn+ yLatch GND (b) Fig. 9. Latch-type comparators: (a) Existing one [28] and (b) proposed one WI. (b) generated dynamically using capacitor reference dividers to save power. Excluding power consumed in the digital part and the output pad drivers, the static power budget of the chip was 36 mW for the 9 identical stages and 14 mW for two common-mode internal buffer drivers and a bias generator, and the total power used in testing was close to 50 mW as designed for 20 MHz operation. With a 20 MHz clock, power consumed in the digital part was about 50 mW. The high level of digital power in testing mainly results from short currents in undersized clock and pad drivers. The chip uses 0 V and 5 V supplies, and ill common-mode voltages are internally generated. Two reference voltages of 2 and 3 V are externally supplied. The die picture of the chip is shown in Fig. 12, and the die area is 3.5 mm by 3.7 mm. The prototype chip exhibits a DNL of f0.65 LSB and an INL of +2/-2.6 LSB as shown in Figs. 13 and 14, respectively. The poor INL and THD limited by even-order distortion seem to result from single-ended sampling and input Fig. 11. Capacitive reference voltage divider: (a) Initialization phase and (b) comparison phase. Fig. 12. Die photo of the prototype ADC. common-mode swing as discussed. Differential ADC's usually exhibit an odd symmetry in transfer characteristics. The signal- 520 IEEE JOURNAL OF SOLID-STATE CIRCUlTS, VOL. 30, NO. 5 , MAY 1995 2.0 1 ,5 .......................................... - 1.0 .......................... ........................ i......................................................... c........................... i............................. -1.0 -1.5 ....... ............... -2.0 0 258 512 788 Code Number 1024 Fig. 13. DNL at a 10-b level. TABLE I S m m y OF THE MEASUREDPERFORMANCE Technology Sampling rate Resolution Differential nonlinearity (DNL) Integral nonlinearity (INL) THD SNDR SFDR Power consumption Input range Reference voltages Input capacitance Supply voltage Chip area 1.2 pm double-poly CMOS 20 Msamplek 10-b f 0 . 6 5 LSB +2/-2.6 LSB -59 dB 54 dB 61 dB 50 mW 0 to 2 V single-ended 2v,3v 0.2 pF 5v 1 3 m 2 (3.5“ x 3.7mm) I I I 0 256 512 760 1024 Code Number Fig. 14. INL at a 10-b level. ADC consumes only 4 mW per stage and a total of 36 mW for 9 stages. The low-power and high-speed performance results from several power-saving circuit refinements such as a purely dynamic comparator that consumes no static power, a capacitive reference voltage divider in place of a power-consuming resistor-string DAC, and a source-follower buffered op amp tightly biased with a self-biased biasing circuit. I ACKNOWLEDGMENT The authors express their best thanks to C. 3. Oh, J. R. Lee, 6’ O0 K. S. Song of ETRI for their help. Fig. 15. SNDR versus input frequencies. to-noise-and-distortion ratio (SNDR), when sampling at 20 MHz, is plotted in Fig. 15 as a function of input frequency. The measured SNDR at low frequencies was 54 dB, but decreased noticeably for input frequencies above a few MHz. The measured spurious-free dynamic range (SFDR)was about 61 dB. The ADC performance measured at a 20 MHz sampling rate using a histogram test method is summarized in Table I. An approximately 330 kHz sinusoidal source with a fullscale 2 V&, magnitude was used as a single-ended input for measurements listed in Table I. V. CONCLUSIONS A 10-b, 20 Msampleh single-ended input but internally differential CMOS ADC is designed and prototyped with an analog power budget of 50 mW. The unscaled pipelined REFERENCES A. Matsuzawa, T. Takemoto, M. Inoue, H. Sadamatsu, and K. Tsuji, “A fully-parallel 10-bit A/D converter with video speed,” ZEEE J. Solid-state Circuits, vol. SC-17, pp. 1133-1 138, Dec. 1982. T. Shimizu, M. Hotta, K.Maio, and S. Ueda, “A IO-bit 20 MHz two-step parallel A/D converter with internal SRI,” ZEEE J. Solid-state Circuits, vol. 24, pp. 13-20, Feb. 1989. D. Robertson, P. Real, and C. Mangelsdorf, “A wideband 10-bit, 20 Msps pipelined ADC using cmnt-mode signals,” in Dig. ZEEE Znt. Solid-state Circuits Cont. Feb. 1990, pp. 160-161. A. Matsuzawa, M. Kagawa, M. Kanoh, K. Tatehara, T. Yamaoka, and K. Shimizu, “A 10-b 30 MHz two-step parallel BiCMOS ADC with internal SRI,” in Dig. ZEEE Inr. Solid-State Circuits Cont. Feb. 1990, pp. 162-163. P. Vorenkamp and J. Verdaasdonk, “A 10-b 50 MHz pipelined ADC,” in Dig. ZEEE Znr. Solid-Stare Circuits Con&, Feb. 1992, pp. 32-33. H. Kimura, A. Matsuzawa, T. Nakamura, and S. Sawada, “A 10-b 300 MHz interpolated-parallel A/D converter,” ZEEE J. Solid-state Circuits, vol. 28, pp. 438446, Apr. 1993. K. Sone, Y. Nishida, and N. Nakadai, “A 10-b 100 Msamplds pipelined subranging BiCMOS ADC,” ZEEE J. Solid-state Circuits, vol. 28, pp. 1180-1 186, Dec. 1993. W.Colleran and A. Abidi, “A 10-b, 75 MHz two-stage pipelined bipolar A/Dconverter.” IEEE J. Solid-state Circuits, vol. 28, pp. 1187-1 199, Dec. 1993. J. Doernberg, P. Gray,and D. Hodges, “A IO-bit 5 Msample/s CMOS two-step flash ADC,” IEEE J. Solid-state Circuits, vol. 24, pp. 241-249, Apr. 1989. B. Song, S. Lee, and M. Tompsett, “A 10-b 15 MHz CMOS recycling two-step A/D converter,’’ ZEEE J. Solid-state Circuits, vol. 25, pp. 1328-1338, Dec. 1990. S. Lewis, H. Fetterman, G. Gross, Jr., R. Ramachandran, and T. Viswanathan, “A 10-b 20 Msample/s analog-to-digital converter,” ZEEE J. Solid-state Circuits, vol. 27, pp 351-358, Mar. 1992. T. Matsuura, M. Hotta. K. Usui, E. Imaizumi, and S. Ueda,” A 95 mW, 10-b 15 MHz low-power CMOS ADC using analog double-sampled pipelining scheme,” in Dig. Symp.VUZ Circuits, June 1992, pp. 98-99. SONG er al.: A 10-b 2O-MSAMF’LWS LOW-POWERCMOS ADC 521 [13] K. Kusumoto, A. Matsuzawa, and K. Murata, “A 10-b 20 MHz 30 mW pipelined interpolating CMOS ADC,” IEEE J. Solid-state Circuits, vol. 28, pp. 1200-1206, Dec. 1993. [14] M. Yotsuyanagi, T. Etoh, and K. Hirata, “A 10-b 50 MHz pipelined CMOS AID converter with S/H,” IEEE J. Solid-State Circuits, vol. 28, pp. 292-300, Mar. 1993. [15] C. Mangelsdorf, H. M a l i S . Lee, S . Hisano, and M. Martin, “A two- residue architecture for multistage ADCs,” in Dig. IEEE Int. Solid-State Circuits Con$, Feb. 1993, pp. 64-65. [16] C. Mangelsdorf, S . Lee, M. Martin, H. Malik, T. Fukuda, and H. Matsumoto, “Design for testability in digitally-correcteda s , ” in Dig. IEEE Int. Solid-State Circuits Con$, Feb. 1993, pp. 70-71. [17] M. Ito, T. Miki, S . Hosotani, T, Kumamoto, Y. YmShita, M. %Jim& and K. ohda, “A 10-b 20 3 V supply CMOS converter for integration into system VLSIs,” in Dig. IEEE Inr. Solid-State Circuits Con$, Feb. 1994, pp. 48-49. [18] T. Cho and P. Gray, “A 10-bit, 20 MS/s, 35 mW pipelined AID converter,” in Proc. IEEE Custom Integrated Circuits Con$, May 1994, pp. 499-502. [19] B. Song, M. Tompsett, and K. Lakshmikumar, “A 12 bit 1 Msamplds capacitor error averaging pipelined A/D converter,” IEEE J. Solid-State Circuits, vol. 23, pp. 1324-1333, Dec. 1988. [20] A. Karanidas, H. Lee, and K. Bacrania, “A 15 b 1 Msamplds digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, pp. 1207-1215, Dec. 1993. [21] H. Schmid, Electronic AnulogDigital Conversion Techniques. New York Van Nostrand, 1970, pp. 323-325. [22] W. Song et al., “A low-power dynamic comparator,” Korean Patent pending, File No. 26314, Dec. 3, 1993. [23] S . Lewis, “Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications,” IEEE Trans. Circuits and System-II, vol. 39, pp. 516-523, Aug. 1992. [24] C. Conroy, D. Cline, and P. Gray, “An 8 b 85 MS/s parallel pipeline AID converter in 1pm CMOS,” IEEE J. Solid-State Circuits, vol. 28, pp. 447-454, Apr. 1993. [25] K. Matsui, T. Matsuura, S . Fukasawa, Y. Izawa, Y. Toba, N. Miyake, and K. Nagasawa, “CMOS video filters using switched capacitor 14 MHz circuits,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1096-1 102, Dec. 1985. [26] B. Brandt and B. Wooley, “A 50 MHz multibit sigmadelta modulator for 12 b 2 MHz A/Dconversion,” IEEE J. Solid-State Circuits, vol. 26, pp. 1746-1756, Dec. 1991. [27] P. Li, M. Chin, P. Gray, and R. Castello, “A ratio-independent algorith- mic analog-to-digital converter technique,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 828-836, Dec. 1984. [28] A. Yukawa, “A CMOS 8 bit high-speed A/D converter IC,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 775-779, June 1985. data converters, high-r mixed IC’s. Won-Chul Song was bom in Chung-nam, Korea, on February 9, 1955. He received the B.S. degree in electrical engineering from Seoul National University, Korea, in 1977, and the M.S. degree in electronics engineering from Korea Advanced Institute of Science, Korea, in 1980. Since February 1981, he has been with the Electronics and Telecommunications Research Institute at Taejon, where he is a principal engineer. He designed VTR IC’s, audio IC’s, and dynamic RAM. His current interest is in IC design of high-speed xd PLL, low-noise preamplifier, and analog/digital Hae-Wook Choi received the B.S. degree in electronics engineering from Seoul National University, Seoul, Korea, in 1973, and the Ph.D. degree in computer sciences from the Institut National Polytechnique de Grenoble, Grenoble, France, in 1984. From 1981 to 1984, he was a research staff member at Thomson Semiconductor, Grenoble, France, working on telecommunication IC designs. Since 1984 he has been with the Semiconductor Technology Division of the Electronics and Telecommunications Research Institute, Taejon, Korea, where he is now a Technical Consultant. His current interest is in analog IC’s for high-speed precision data converters, high-speed application specific DSP architectures and testabilities, and wireless LAN protocol processors. Sung-Ung Kwak was bom in Seoul, Korea, in 1965. He received the B.S. and M.S. degrees in electrical and computer engineering from the University of Illinois, Urbana-Champaign, in 1991 and 1993, respectively. Since 1992, he has been a Graduate Research Assistant in the Department of Electrical and Computer Engineering and Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, while working on analog-to-digital converters as a candidate for Ph.D. degree. From June to August in 1993 and 1994, he was a Research Intem at Harris Semiconductor, Melboume, FL, where he was responsible for the design of low-power high resolution video-speed CMOS A/D converters. Bang-Sup Song (S’79-M183-SM’88) received the B.S.E.E. from the Seoul National University in 1973, the M.S.E.E. from the Korea Advanced Institute of Science in 1975, and the Ph.D.E.E. from the University of California, Berkeley, in 1983. From 1975 to 1978, he was a research staff at Agency for Defense Development, Korea, working on fire-control radars and spread spectrum communications. From 1983 to 1986, he was a member of technical staff at AT&T Bell Laboratories, Murray Hill, and was also a visiting faculty member in the Department of Electrical Engineering, Rutgers University. Since 1986, he has been with the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, where he is an Associate Professor. His current interest is in analog IC’s for high-speed precision data converters, high-frequency filters, radio transceivers, disk drivers, video signal processing, and data communications. Dr. Song has served as an Associate Editor of IEEE TRANSACTIOONNS CIRCUITS AND SYSTEMSand as a Guest Editor of the 1990 December Analog Special Issue of IEEE JOURNALOF SOLID-STATECIRCUITS. He has served as a program committee member of IEEE Intemational Solid-state Circuits Conferencefrom 1988to 1992 and is back on the same committee from 1994. He is also serving as a Coordinator of Track I Analog Circuits and Analog Signal Processing of the 1995 IEEE Intemational Symposium on Cicuits and Systems. He received a Distinguished Technical Staff Award from AT&T Bell Laboratories in 1986. I-

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