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AN1998datasheet

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AN1998 An FM/IF system for DECT and other high-speed GFSK applications Rev. 3 — 24 July 2014 Application note Document information Info Content Keywords High-speed digital wireless PCS applications, Digital European Cordless Telephone (DECT), FM/IF system Abstract An NXP low-voltage high-performance monolithic FM/IF system, the SA639 is introduced to meet the increasing demand for high-speed digital wireless PCS applications. In order to assist the system design, a SA639-based performance evaluation board has been developed according to the Digital European Cordless Telephone (DECT) specifications. This application note presents detailed descriptions of the SA639 FM/IF system, evaluation board, and design information including circuit diagram, component list, and the board layout. The experimental performance evaluation procedures, measured bit error rate (BER), sensitivity to frequency offset, and sensitivity to FM deviation variation of this system are also presented. Results indicate that the low-voltage SA639 FM/IF system provides superior performance for high-speed digital wireless applications. NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications Revision history Rev Date 3.0 20140724 2.0 20040114 1.0 19970820 Description Application note; third release • The format of this application note has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. Application note; second release Application note; initial release Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications 1. Introduction To achieve the goal of wireless personal communications, allowing users access to the capabilities of the global communications network at any time without regard to location and mobility, cellular and cordless telephony have been taken as two major approaches. Cellular systems are evolving towards smaller cells (micro cells) and lower power levels to provide higher overall capacity. Cordless telephones have evolved from home appliances towards widespread ‘universal’ low-power personal communications systems. With the advent of digital cordless telephony, cordless systems with enhanced functionality have been developed that can support higher data rates and more sophisticated applications such as wireless private branch exchanges (WPBX) and public-access Telepoint systems. One of the first digital cordless standards is the Digital European Cordless Telecommunications (DECT) system, a pan-European standard designed to connect all of Europe with a common digital cordless system. DECT is also a flexible standard for providing a wide range of services in small cells. In this application note, the SA639, an NXP low-voltage FM/IF system with several important features such as post filter amplifier and active data switch, is proposed for DECT and other high-speed digital wireless applications. A SA639-based DECT receiver evaluation board has been developed. Detailed description of the SA639 FM/IF system, structure of the evaluation board, design information, and experimental evaluation results are presented. 2. Review of DECT standard DECT is designed as a flexible interface to provide cost-effective communications services to high user densities in small cells. This standard is intended for the applications such as domestic cordless telephony, Telepoint, cordless PBXs, and Radio Local Loop (RLL). It supports multiple bearer channels for speech and data transmission (which can be set up and released during a call), hand over, location registration, and paging. Functionally, DECT is closer to a cellular system than to a classical cordless telephone. However, the interface to PSTN or ISDN remains the same as for a PBX or corded telephone. Table 1 is a summary of the key specifications of DECT and other digital cordless telephone systems. DECT is based on Time Division Duplex (TDD) and Time Division Multiple Access (TDMA) with 10 carriers in the 1880 MHz to 1900 MHz band. Figure 1 illustrates the DECT TDD/TDMA frame structure. The completed frame is 10 ms in duration with 24 time slots. The first 12 slots are allocated for the transmission from base station to handsets, and the other 12 slots are for the transmission from handsets to base station. Each slot is 417 μs long with 480 bits. The first 32 bits is a ‘1010...’ sequence for synchronization. The 32 kbit/s ADPCM CODEC is used for speech coding in DECT, which provides 320 bits during each 10 ms frame. When a call is made, two slots (one is in the first 12 slots, the other is in the last 12 slots) are assigned to the user for transmit and receive. AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications Table 1. Summary of digital cordless standards Standard CT2/CT2+ Region Europe/Canada Frequency band (MHz) CT2: 864 - 868 CT2+: 944 - 948 Duplex TDD Multiple access TDMA Number of channels 40 Channel spacing 100 (kHz) Users/channel 1 Modulation GFSK (FM dev: 14 kHz to 25 kHz) Bit rate 72 kbit/s Speech coding 32 kbit/s ADPCM Frame duration 2 ms Peak power 10 mW DECT Europe 1880 - 1900 TDD TDMA 10 1728 12 GFSK (FM dev: 288 kHz) 1.152 Mbit/s 32 kbit/s ADPCM 10 ms 250 mW PHS Japan 1895 - 1918 TDD TDMA 77 300 4 π/4-DQPSK 32 kbit/s ADPCM 32 kbit/s ADPCM 5 ms 80 mW PACS USA Tx: 1850 - 1910 Rx: 1930 - 1990 FDD TDMA 16 pairs 300 8/pair π/4-DQPSK 32 kbit/s ADPCM 32 kbit/s ADPCM 2.5 ms 200 mW frequency Ch 10 1897 MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Ch 1 1881 MHz 24-slot frame (10 ms: 11520 bits at 1.152 Mbit/s) base-to-handsets handsets-to-base 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 time one slot (417 μs: 480 bits at 1.152 Mbit/s) 32 bits 64 bits synchronization signaling 320 bits information 4 error control 60 bits guard space Fig 1. DECT TDD/TDMA frame structure aaa-014182 AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 4 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications Gaussian filtered FSK (GFSK) modulation scheme is employed in DECT. GFSK is a premodulation Gaussian filtered digital FM scheme. Figure 2 shows the block diagram of a GFSK modulator. The advantages of GFSK can be summarized as follows: Constant envelope nature — This allows GFSK modulated signal to be operated with class-C power amplifier without introducing spectrum regeneration. Therefore, lower power consumption and higher power efficiency can be achieved. Narrow power spectrum — Narrow main lobe and low spectral tails keep the adjacent channel interference to low levels and achieve higher spectral efficiency. Non-coherent detection — GFSK modulated signal can be demodulated by the limiter/discriminator receiver as shown in Figure 3. This simple structure leads to low-cost GFSK receivers. GAUSSIAN fb = 1.152 Mbit/s LPF BTb = 0.5 Mbit/s GFSK modulated FM signal for DECT MODULATOR ∆f = 288 kHz aaa-014203 Fig 2. Block diagram of GFSK modulator GFSK modulated signal for DECT LIMITER FM DISCRIMINATOR Fig 3. Block diagram of GFSK demodulator fb = 1.152 Mbit/s aaa-014204 AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications 3. The SA639 FM/IF system The SA639 is a low-voltage high performance monolithic FM/IF system with high-speed RSSI incorporating a mixer/oscillator, two limiting intermediate frequency amplifiers, quadrature detector, fast RSSI op amps, post detection filter amplifier, and a data switch. The block diagram of SA639 is presented in Figure 4. The SA639 was designed specially for high data rate portable communications applications and functions down to 2.7 V. The data output provides a minimum bandwidth of 1 MHz to demodulate high-speed data, such as in DECT applications. Figure 5 presents the quad tank S-curve of SA639, which indicates the linear range to be about 2 MHz. The measured RSSI characteristic of SA639 is presented in Figure 6. With more than 75 dB dynamic range, the SA639 RSSI rise/fall time is 0.8/2.0 ms at −45 dBm RF level. 14 QUADRATURE_IN 13 SWITCH_OUT 16 LIMITER_DECOUPL 15 LIMITER_OUT LIMITER_DECOUPL LIMITER_IN GND 20 IF_AMP_OUT IF_AMP_DECOUPL IF_AMP_IN IF_AMP_DECOUPL MIXER_OUT 17 18 19 21 22 23 24 mixer IF amp OSC VCC EB FAST RSSI limiter quad RSSI POWER DOWN data RF_IN 1 RF_BYPASS 2 OSC_OUT 3 OSC_IN 4 VCC 5 RSSI_FEEDBACK 6 RSSI_OUT 7 POWER_DOWN_CTRL 8 DATA_OUT 9 POSTAMP_IN 10 POSTAMP_OUT 11 SWITCH_CTRL 12 Fig 4. Block diagram of the SA639 FM/IF system 002aag706 AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 6 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications AN1998 Application note output DC level (V) aaa-014183 2.5 2.0 1.5 1.0 0.5 0 −1.2 −1.0 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 frequency offset from 110.592 MHz (MHz) Fig 5. Quad tank S-curve of SA639 board RSSI 1.4 (V) 1.2 aaa-014184 1.0 0.8 0.6 0.4 0.2 0 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 RF level (dBm) Fig 6. Measured RSSI characteristics of SA639 The post-detection amplifier may be used to realize a group delay optimized low-pass filter. To keep its frequency response influence on the filter group delay characteristics at a minimum, the filter amplifier provides 0 dB gain and has a 3 dB bandwidth of at least 4 MHz. It can be configured for Sallen and Key low-pass with Bessel characteristic and a 3 dB cut frequency of about 800 kHz. The SA639 incorporates an active data switch to derive the data comparator reference voltage by means of routing a portion of data signal to an external integration circuit. The data switch is typically closed for 10 ms in the course of 32-bit synchronization sequence, and is open otherwise. The time constant of the external integration circuit is about 5 ms to 10 ms. This active switch provides excellent tracking behavior over a DC input range of 1.2 V to 2.0 V. The slew rate is better than 1 V/ms. When the switch is opened, the output is in a 3-state mode with a leakage current of less than 100 nA. This reduces the discharge of the external integration circuit. As compared to other similar FM/IF chips, another advantage of SA639 is that during power-down mode (between data bursts) the data switch outputs a reference of about 1.6 V to maintain a charge on the external RC circuit. This idea helps extract the reference voltage for the external capacitor in a shorter time and improves the accuracy of the voltage on the capacitor. The overall system is suited for battery operated high-quality products in digital wireless personal communications. Detailed specifications of SA639 can be found in Ref. 3. All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications 4. Structure of the SA639 evaluation board A SA639-based evaluation board has been developed based on DECT specifications. The structure of this board is illustrated in Figure 7 together with a VCO/FM discriminator-based GFSK modem (modulator/demodulator). The demo board contains the entire demodulator as well as the Gaussian low-pass filter (LPF) for the modulator. The DECT modulated signal, therefore, can be generated either by a standard DECT signal generator, or by sending a 1.152 Mbit/s data stream to the on-board Gaussian LPF (BTb = 0.5), then applying the filtered baseband waveform to an FM signal generator with a modulation index of 0.5. The output is then the GFSK modulated signal (DECT). The schematic of the Gaussian LPF can be found in Figure 14. Baseband eye-diagram at the output of the Gaussian LPF is presented in Figure 8. ∆f = 288 kHz FM MODULATOR fc = 110.592 MHz fb = 1.152 Mbit/s GAUSSIAN LPF BTb = 0.5 FM DETECTOR SA639 LO fLO = 120.392 MHz BER COMP. LPF Fig 7. Structure of the SA639 GFSK evaluation board aaa-014185 AN1998 Application note stopped Display norm avg env Persistence infinite # of screens 1 24 −2.4000 μs 100.0 ns 500 ns/div 2.6000 μs repetitive off frame axes grid connect dots off on aaa-014186 Fig 8. Measured eye-diagram at the output of Tx Gaussian LPF At the output of the limit/frequency discriminator, the post-detection amplifier is configured as a Sallen and Key LPF to eliminate noise. For the convenience of operation, the evaluation board is designed in such a way that the reference voltage for the data comparator can be obtained either from the switch controlled DC extraction circuit, or directly from the power supply. If the DECT Burst Mode Control circuit is available, the active data switch can be used to extract and track DC level during the synchronization sequence. Otherwise the DC reference can be obtained from the power supply and manually adjusted for the comparator operation. All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 8 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications A two-level threshold detector with sampling time adjustment circuit is implemented on the board for data regeneration. The phase of data clock can be adjusted manually through a monostable multivibrator (74HC123) to achieve the optimal sampling time. The demo board is initially adjusted for a bit rate of 1.152 Mbit/s. If a different data rate is used, the sampling time must be re-adjusted. The output of the threshold detector is the regenerated binary data, which can be sent to a data error analyzer to evaluate the BER performance. The symbol timing recovery (STR) circuit is not implemented on this evaluation board. Transmit data clock either hard-wire connected from the transmitter or from a separate STR circuit is required for the operation. The performance measurements presented in this application note were conducted with hard-wire connected data clock. However, BER degradation caused by STR should not be more than 1 dB (Ref. 6). This SA639-based GFSK demo board is designed with DECT specifications at RF frequency of 110.592 MHz, LO frequency of 120.392 MHz, and intermediate frequency of 9.8 MHz. For different frequency plan applications, the step-by-step matching circuit design procedure can be found in Ref. 1. Table 2 and Table 3 present the SA639 RF/LO input impedance and mixer/limiter output impedance over frequency, respectively. Table 2. SA639 RF/LO input impedance over frequency Frequency RF input LO input 50 MHz 846 Ω || 4.52 pF 6900 Ω || 4.07 pF 110 MHz 687 Ω || 3.84 pF 4900 Ω || 4.09 pF 240 MHz 510 Ω || 3.69 pF 1900 Ω || 4.22 pF 500 MHz 190 Ω || 4.21 pF 245 Ω || 4.98 pF Table 3. SA639 mixer/limiter output impedance over frequency Frequency RF input LO input 0.5 MHz 395 Ω || 20.2 pF 438 Ω || 14.5 pF 10 MHz 350 Ω || 6.67 pF 383 Ω || 3.5 pF 21 MHz 339 Ω || 4.58 pF 393 Ω || 2.04 pF 50 MHz 326 Ω || 3.44 pF 391 Ω || 1.35 pF AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications 5. Performance evaluation Performance of this SA639 based DECT GFSK system including BER and sensitivity to frequency off-set and FM deviation variation is experimentally evaluated. Measurement procedures and the measured results are presented in this section. Figure 9 illustrates the measurement set-up with the SA639 DECT evaluation board. A data error analyzer is employed to generate a pseudo random binary sequence (PRBS) with length of 109−1 at a data rate of 1.152 Mbit/s. This data sequence is sent to a DECT signal generator to generate a standard DECT modulated signal at 110.592 MHz. Another signal generator is employed to provide an LO signal at 120.392 MHz for the FM/IF system detection. The reference DC voltage for the data comparator is obtained from power supply for this evaluation. Data clock signal is directly from the data error analyzer. The sampling time is manually adjusted at the center of baseband eye diagram. Recovered data sequence is fed back to the Data Error Analyzer for BER measurement. AN1998 Application note fb = 1.152 Mbit/s BER ANALYZER data output fc = 110.592 MHz ∆f = 288 kHz DECT GENERATOR fLO = 120.392 MHz SIGNAL GENERATOR data input clock output clock input BTb = 0.5 GAUSSIAN LPF data clock input TIMING ADJUSTMENT RFIN LOIN FM DETECTOR SA639 Rx data output COMP. LPF aaa-014187 Fig 9. Block diagram of the BER evaluation setup The BER measurement procedures can be summarized as follows: • Build the measurement setup as shown in Figure 9. • Measure SINAD at the data output of SA639: – RF = 110.592 MHz, fm = 1 kHz, Df = 288 kHz – LO = 120.392 MHz, −10 dBm – the typical sensitivity for 12 dB SINAD should be about −97 dBm • Check SA639 output level: tune the quad tank circuit to have the least distorted eye-diagrams at the post op amp output. The DC level should be about 1.4 V to 1.7 V. • Check the DC reference for the comparator: set the reference voltage at the DC level of the op amp output by adjusting VR1 in Figure 14. • Adjust sampling position: set the up edge of the clock at pin 11 of 74HC74 to be at the center of the eye-diagram at pin 2 of LM311B by adjusting VR2 in Figure 14. • Measure BER with high RF level: set RF input signal level at −60 dBm; LO signal level at −10 dBm: error free. All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications • Measure BER versus RF input level curve: – RF level: −76 dBm ~ −86 dBm – LO level: −10 dBm, at each point, at least 100 errors must be measured The recovered baseband eye-diagram is shown in Figure 10, and the measured BER versus RF input level is presented in Figure 11. It can be seen that about −83 dBm RF power is needed to achieve the bit error rate of 10−3. Since a typical front-end circuit has a better noise figure than FM/IF system, it is common to achieve more than 5 dB signal-to-noise ratio gain by the front-end circuit. Therefore, with the SA639 FM/IF the overall system sensitivity could be better than −88 dBm for the BER of 10−3. Based on our measurements, by applying the Philips UAA2077AM 2 GHz image rejecting front-end to the SA639 FM/IF system, the overall system sensitivity is −91 dBm for the BER of 10−3. This performance compares very well to the DECT specifications for public access equipment (−86 dBm for 10−3 BER). stopped −2.5800 μs −80.00 ns 500 ns/div 2.4200 μs realtime Horizontal 500 ns/div Delay -60.00 ns Reference left center right Repetitive realtime sequential off on record length 512 auto adjust 100 Msa/s sample clock aaa-014188 Fig 10. Recovered eye-diagram at the output of SA639 10−1 BER 10−2 10−3 10−4 aaa-014189 AN1998 Application note 10−5 −87 −86 −85 −84 −83 −82 RF = 110.592 MHz; LO = 120.392 MHz; fb = 1.152 Mbit/s Fig 11. BER of the SA639 DECT demo board −81 −80 RF input (dBm) All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications The performance degradation caused by frequency off-set and the sensitivity to FM deviation variation of this system are also evaluated. Figure 12 presents the measured BER versus frequency offset. Even with 50 kHz offset, only minor degradation can be observed, and −82 dBm RF level is enough for 10−3 BER. The sensitivity of this system to FM deviation variation is illustrated in Figure 13. Even with 10 % deviation reduction (259 kHz), less than −82 dBm RF signal is needed to achieve the BER of 10−3. These results indicate that the NXP SA639 FM/IF system provides superior performance for DECT and other high data rate GFSK applications. 10−1 BER 10−2 aaa-014190 10−3 10−4 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 frequency offset from 110.592 MHz (kHz) RF = −82 dBm Fig 12. BER degradation caused by frequency offset 10−1 BER 10−2 10−3 10−4 10−5 317 288 259 RF = 110.592 MHz, −82 dBm; fb = 1.152 Mbit/s Fig 13. BER versus FM deviation aaa-014191 202 166 FM deviation (kHz) AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 20 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors AN1998 Application note AN1998 An FM/IF system for DECT and other high-speed GFSK applications All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 RF_IN J1 110.592 kHz ±288 kHz C2 15 pF C1 5 pF to 30 pF C3 10 nF L1 180 nH LO in C5 J2 120.392 MHz 5 pF to 30 pF C4 at −10 dBm 1 nF C6 39 pF VCC R1 10 Ω L2 120 nH C8 15 μF C7 100 nF R2 22 kΩ RSSI OUT GND R3 33 kΩ DATA OUT SK IN GND C10 22 pF POST AMP IN POSTAMP OUT SW CTRL SW OUT R4 0Ω R6 5.6 kΩ R5 5.6 kΩ C9 33 pF L5 680 nH U1 FM/IF C26 68 pF 1 2 3 4 5 6 7 8 9 10 11 12 RF_IN MIXER_OUT RF_BYPASS IF_AMP_DECCOUPL OSC_IN (E) IF_AMP_IN OSC_OUT (B) IF_AMP_DECOUPL VCC IF_AMP_OUT RSSI_FB GND RSSI_OUT LIMITER_IN POWER_DOWN_CTRL LIMITER_DECOUPL DATA_OUT LIMITER_DECOUPL POSTAMP_IN LIMITER_OUT POSTAMP_OUT QUADRATURE_IN SWITCH_CTRL SWITCH_OUT 24 23 22 21 20 19 18 17 16 15 14 13 SA639DH/01 R7 510 Ω C12 1 nF C25 330 pF C23 100 nF C22 100 nF C24 68 pF C20 C21 100 pF 47 pF C17 100 nF C16 100 nF C18 C19 100 pF 330 pF L4 680 nH C14 6.8 pF C13 5 pF to 30 pF C11 10 nF R8 1.3 kΩ C15 15 pF L3 4.7 μH L6 6.8 μH L7 1.8 μH R14 1.2 kΩ R15 39 Ω R11 5.1 kΩ VR1 20 kΩ SW1 R9 10 kΩ 1 2 GND IN+ 3 4 IN− V− 8 VCC OUT 7 STE BAL 6 5 LM311B 1 2 3 4 5 6 7 1RD 1D 1CT 1SD 1Q1 1Q2 GND VCC 2RD 2D 2CT 2SD 2Q1 2Q2 14 13 12 11 10 9 8 74HC74 C35 100 nF R12 1 kΩ C34 15 μF THRESHOLD DETECTOR 1 1A VCC 16 2 1B 1REXT 15 3 1RD 1CEXT 14 4 1Q/L 1Q 13 5 2Q 2Q/L 12 6 7 8 2CEXT 2REXT GND 2RD 2B 2A 11 10 9 74HC123 C31 18 nF Fig 14. Schematic C27 2.2 nF C28 220 pF C29 10 nF C30 2.2 nF J3 DATA IN L8 10 μH L9 2.7 μH J4 Tx DATA OUT R16 220 Ω R17 24 Ω C32 100 nF C33 15 μF VCC VR2 500 kΩ J5 DATA CLOCK IN J6 Rx DATA OUT J7 Rx DATA OUT aaa-014205 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications Top View Bottom View R14 C28 C27 Lo in RF in Data in C16 C17 R15 C2 L1 C6 Vcc Gnd RSSI Data Gnd Amp out Sw Ctrl Sw out R1 C25 L5 C5 L2 C3 C1 C7 C8 C4 C23 C26 C21 C19 L4 C24 C22 C20 C18 R13 R3 R2 U1 C10 R4 C9 R5 R6 SW1 C12 C14 C13 C11 R7 R8 C15 L3 VR1 R11 C35 C34 R16 C30 C29 L6 L7 L8 Tx Data out L9 R17 R12 R9 C31 C32 C33 SA639 DECT DC10639 U2 Rx Data out U4 U3 CLK in Rx Data out VR2 Components Layout Fig 15. Board layout Via Layer aaa-014192 AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications Table 4. Customer application component list for GMSK/GFSK demo board Quantity Value Voltage Component Description Vendor Manufacturer Part number Surface mount capacitors 1 6.8 pF 50 V C14 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG689C9BB2 2 15 pF 50 V C2, C15 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG150J9BB2 1 18 pF 50 V C31 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG180J9BB2 1 22 pF 50 V C10 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG220J9BB2 1 33 pF 50 V C9 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG330J9BB2 1 39 pF 50 V C6 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG390J9BB2 1 47 pF 50 V C21 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG470J9BB2 2 68 pF 50 V C24, C26 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG680J9BB2 2 100 pF 50 V C18, C20 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG101J9BB2 1 220 pF 50 V C28 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG221J9BB2 2 330 pF 50 V C19, C25 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG331J9BB2 2 1000 pF 50 V C4, C12 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG102J9BB2 2 2200 pF 50 V C27, C30 cap. cer. 1206 NPO ± 5 % Garrett Philips 1206CG222J9BB2 3 0.01 μF 50 V C3, C11, cer. cap. 1206 X7R ± 10 % Garrett Philips 12062R103K9BB2 C29 7 0.1 μF 50 V C7, C16, cer. cap. 1206 X7R ± 10 % Garrett Philips 12062R104K9BB2 C17, C22, C23, C32, C35 3 15 μF 10 V C8, C33, tantalum capacitor chips Garrett Philips 49MC106C006KOAS C34 Surface mount variable capacitors 3 5 pF to 30 pF C1, C5, C13 trimmer capacitor Kent Elect Kyocera CTZ3S-30C-W1 Surface mount resistors 1 0Ω 50 V R4 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW000E 1 10 Ω 50 V R1 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW100E 1 24 Ω 50 V R17 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW240E 1 39 Ω 50 V R15 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW390 1 220 Ω 50 V R16 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW221E 1 510 Ω 50 V R7 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW511E 1 560 Ω 50 V R13 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW561E 1 1 kΩ 50 V R12 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW102E 1 1.2 kΩ 50 V R14 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW122E 1 1.3 kΩ 50 V R8 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW132E 1 5.1 kΩ 50 V R11 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW512E 2 5.6 kΩ 50 V R5, R6 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW562E 1 10 kΩ 50 V R9 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW223E 1 22 kΩ 50 V R2 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW223E 1 33 kΩ 50 V R3 Res. chip 1206 ± 5 % Garrett ROHM MCR18JW333E AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 15 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications Table 4. Customer application component list for GMSK/GFSK demo board …continued Quantity Value Voltage Component Description Vendor Manufacturer Part number Surface mount variable resistors 1 20 kΩ 50 V VR1 trimmer resistor 0.25 W ± 20 % Garrett Philips ST-4TA203 1 500 kΩ 50 V VR2 trimmer resistor 0.25 W ± 20 % Garrett Philips ST-4TA504 Surface mount switch 1 SPDT SW1 4 mm selector switch Garret Philips CS-412YTA Surface mount inductors 1 120 nH L2 chip inductor 1008 ± 10 % Coilcraft Coilcraft 1008CS-331XKBB 1 180 nH L1 chip inductor 1008 ± 10 % Coilcraft Coilcraft 1008CS-331XKBB 2 680 nH L4, L5 chip inductor 1008 ± 10 % Digikey TOKO 380NB-R68M 1 1.8 μH L7 chip inductor 1210 ± 10 % Garrett J.W. Miller PM20-1R8K 1 2.7 μH L9 chip inductor 1210 ± 10 % Garrett J.W. Miller PM20-2R7K 1 4.7 μH L3 chip inductor 1210 ± 10 % Garrett J.W. Miller PM20-4R7K 1 6.8 μH L6 chip inductor 1210 ± 10 % Garrett J.W. Miller PM20-6R8K 1 10 μH L8 chip inductor 1210 ± 10 % Garrett J.W. Miller PM20-100K Surface mount integrated circuits 1 5V U1 FM IF with filter switch NXP NXP SA639 1 5V U2 voltage comparator NXP NXP LM311B 1 5V U3 dual D-type flip-flop NXP NXP 74HC74 1 5V U4 dual retriggerable NXP NXP 74HC123 multivibrator Miscellaneous 7 J1, J2, J3, SMA gold connector Newark EF Johnson 142-0701-801 J4, J5, J6, J7 1 JP1 8-pin header straight Mouser Molex 538-22-03-2081 1 Printed-circuit board Excel Philips DC10639 AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 16 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications 6. Conclusions An NXP low-voltage high-performance FM/IF system (SA639) based GFSK modem evaluation board is presented. Experimental performance evaluation including bit error rate (BER), sensitivity to frequency offset, and sensitivity to FM deviation variation of this system has been conducted based on DECT specifications. Results indicate that a superior performance can be achieved with the NXP FM/IF systems for high-speed digital wireless applications. 7. Abbreviations Table 5. Abbreviations Acronym Description ADPCM Adaptive Differential Pulse Code Modulation BER Bit Error Rate CODEC COder-DECoder DECT Digital European Cordless Telephone DQPSK Differential Quadrature Phase Shift Keying FDD Frequency Division Duplex FM Frequency Modulation GFSK Gaussian filtered Frequency Shift Keying IF Intermediate Frequency ISDN Integrated Service Digital Network LO Local Oscillator LPF Low-Pass Filter PACS Personal Access Communications System PBX Public Branch eXchange PCS Physical Coding Sublayer PHS Personal Handyphone System PRBS Pseudo Random Binary Sequence PSTN Public Switched Telephone Network RC Resistor-Capacitor network RLL Radio Local Loop RSSI Received Signal Strength Indicator SINAD Signal-to-Noise And Distortion ratio STR Symbol Timing Recovery TDD Time Division Duplex TDMA Time Division Multiple Access VCO Voltage Controlled Oscillator WPBX Wireless Public Branch eXchange AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 17 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications 8. References [1] AN1994, “Reviewing key areas when designing with the SA605” — application note; NXP Semiconductors [2] AN1996, “Demodulation at 10.7 MHz IF with SA605/SA625” — application note; NXP Semiconductors [3] SA639, Low voltage mixer FM IF system with filter amplifier and data switch — Product data sheet; NXP Semiconductors; www.nxp.com/documents/data_sheet/SA639.pdf [4] AN1997, “NXP FM/IF systems for GMSK/GFSK receivers — application note; NXP Semiconductors [5] “GMSK modulation for digital mobile radio telephony” — K. Murota and K. Hirade; IEEE Transactions on Communications; July 1981 [6] “Digital Communications, Satellite/Earth Station Engineering” — Prentice Hall; 1983 AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 18 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications 9. Legal information 9.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 9.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 9.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. AN1998 Application note All information provided in this document is subject to legal disclaimers. Rev. 3 — 24 July 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 19 of 20 NXP Semiconductors AN1998 An FM/IF system for DECT and other high-speed GFSK applications 10. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Review of DECT standard . . . . . . . . . . . . . . . . . 3 3 The SA639 FM/IF system. . . . . . . . . . . . . . . . . . 6 4 Structure of the SA639 evaluation board . . . . 8 5 Performance evaluation . . . . . . . . . . . . . . . . . 10 6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 9.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.3 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 July 2014 Document identifier: AN1998

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