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tlv2471系列的参数

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    标    签:tlv2471系列参数

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    TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA

    FAMILY OF 600−μA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT

    HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN

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    TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED DECEMBER 2003 D CMOS Rail-To-Rail Input/Output D Input Bias Current . . . 2.5 pA D Low Supply Current . . . 600 µA/Channel D Ultra-Low Power Shutdown Mode - IDD(SHDN) . . . 350 nA/ch at 3 V - IDD(SHDN) . . . 1000 nA/ch at 5 V D Gain-Bandwidth Product . . . 2.8 MHz D High Output Drive Capability - ±10 mA at 180 mV - ±35 mA at 500 mV D Input Offset Voltage . . . 250 µV (typ) D Supply Voltage Range . . . 2.7 V to 6 V D Ultra Small Packaging - 5 or 6 Pin SOT-23 (TLV2470/1) - 8 or 10 Pin MSOP (TLV2472/3) description TLV2470 DBV PACKAGE (TOP VIEW) OUT 1 6 VDD GND 2 5 SHDN IN+ 3 4 IN - The TLV247x is a family of CMOS rail-to-rail input/output operational amplifiers that establishes a new performance point for supply current versus ac performance. These devices consume just 600 µA/channel while offering 2.8 MHz of gain-bandwidth product. Along with increased ac performance, the amplifier provides high output drive capability, solving a major shortcoming of older micropower operational amplifiers. The TLV247x can swing to within 180 mV of each supply rail while driving a 10-mA load. For non-RRO applications, the TLV247x can supply ±35 mA at 500 mV off the rail. Both the inputs and outputs swing rail-to-rail for increased dynamic range in low-voltage applications. This performance makes the TLV247x family ideal for sensor interface, portable medical equipment, and other data acquisition circuits. DEVICE TLV2470 TLV2471 TLV2472 TLV2473 TLV2474 TLV2475 NUMBER OF CHANNELS 1 1 2 2 4 4 PDIP 8 8 8 14 14 16 FAMILY PACKAGE TABLE PACKAGE TYPES SOIC SOT-23 TSSOP MSOP 8 6 — — 8 5 — — 8 — — 8 14 — — 10 14 — 14 — 16 — 16 — UNIVERSAL EVM SHUTDOWN BOARD Yes — — Refer to the EVM Selection Guide Yes (Lit# SLOU060) — Yes A SELECTION OF SINGLE-SUPPLY OPERATIONAL AMPLIFIER PRODUCTS† DEVICE VDD (V) VIO BW SLEW RATE IDD (per channel) OUTPUT (µV) (MHz) (V/µs) (µA) DRIVE TLV247X 2.7 - 6.0 250 2.8 1.5 600 ±35 mA TLV245X 2.7 - 6.0 20 0.22 0.11 23 ±10 mA TLV246X 2.7 - 6.0 150 6.4 1.6 550 ±90 mA TLV277X 2.5 - 6.0 360 5.1 10.5 † All specifications measured at 5 V. 1000 ±10 mA RAIL-TO-RAIL I/O I/O I/O O Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  1999 - 2003, Texas Instruments Incorporated • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 TLV2470 and TLV2471 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE SOT-23 PLASTIC DIP (D)† (DBV)† SYMBOL (P) 0°C to 70°C TLV2470CD TLV2471CD TLV2470CDBV TLV2471CDBV VAUC VAVC TLV2470CP TLV2471CP - 40°C to 125°C TLV2470ID TLV2471ID TLV2470AID TLV2471AID TLV2470IDBV TLV2471IDBV — — VAUI VAVI — — TLV2470IP TLV2471IP TLV2470AIP TLV2471AIP † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2470CDR). TLV2472 AND TLV2473 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE MSOP MSOP PLASTIC DIP PLASTIC DIP (D)† (DGN)† SYMBOL‡ (DGQ)† SYMBOL‡ (N) (P) 0°C to 70°C TLV2472CD TLV2472CDGN xxTIABU — — TLV2473CD — — TLV2473CDGQ xxTIABW — TLV2472CP TLV2473CN — - 40°C to 125°C TLV2472ID TLV2473ID TLV2472AID TLV2473AID TLV2472IDGN — — — xxTIABV — — — — TLV2473IDGQ — — — xxTIABX — — — TLV2473IN — TLV2473AIN TLV2472IP — TLV2472AIP — † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2472CDR). ‡ xx represents the device date code. TLV2474 and TLV2475 AVAILABLE OPTIONS PACKAGED DEVICES TA SMALL OUTLINE PLASTIC DIP TSSOP (D)† (N) (PWP)† 0°C to 70°C TLV2474CD TLV2475CD TLV2474CN TLV2475CN TLV2474CPWP TLV2475CPWP - 40°C to 125°C TLV2474ID TLV2475ID TLV2474AID TLV2475AID TLV2474IN TLV2475IN TLV2474AIN TLV2475AIN TLV2474IPWP TLV2475IPWP TLV2474AIPWP TLV2475AIPWP † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2474CDR). 2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 TLV247x PACKAGE PINOUTS(1) TLV2470 DBV PACKAGE (TOP VIEW) OUT 1 6 VDD GND 2 5 SHDN IN+ 3 4 IN - TLV2470 D OR P PACKAGE (TOP VIEW) NC 1 8 SHDN IN - 2 7 VDD IN + 3 6 OUT GND 4 5 NC TLV2471 DBV PACKAGE (TOP VIEW) OUT 1 5 VDD GND 2 IN+ 3 4 IN - TLV2471 D OR P PACKAGE (TOP VIEW) NC 1 8 NC IN - 2 7 VDD IN + 3 6 OUT GND 4 5 NC TLV2473 D OR N PACKAGE (TOP VIEW) 1OUT 1IN 1IN+ GND NC 1SHDN NC 1 14 VDD 2 13 2OUT 3 12 2IN - 4 11 2IN+ 5 10 NC 6 9 2SHDN 7 8 NC NC - No internal connection TLV2472 D, DGN, OR P PACKAGE (TOP VIEW) 1OUT 1 8 VDD 1IN - 2 7 2OUT 1IN + 3 6 2IN - GND 4 5 2IN+ TLV2474 D, N, OR PWP PACKAGE (TOP VIEW) 1OUT 1 14 4OUT 1IN - 2 13 4IN - 1IN+ 3 12 4IN+ VDD 4 11 GND 2IN+ 5 10 3IN+ 2IN - 6 9 3IN - 2OUT 7 8 3OUT 1OUT 1IN 1IN+ GND 1SHDN TLV2473 DGQ PACKAGE (TOP VIEW) 1 10 VDD 2 9 2OUT 3 8 2IN - 4 7 2IN+ 5 6 2SHDN TLV2475 D, N, OR PWP PACKAGE (TOP VIEW) 1OUT 1 1IN - 2 1IN+ 3 VDD 4 2IN+ 5 2IN - 6 2OUT 7 1/2SHDN 8 16 4OUT 15 4IN 14 4IN+ 13 GND 12 3IN + 11 3IN 10 3OUT 9 3/4SHDN TYPICAL PIN 1 INDICATORS Pin 1 Printed or Molded Dot Pin 1 Stripe Pin 1 Bevel Edges Pin 1 Molded ”U” Shape • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 description (continued) Three members of the family (TLV2470/3/5) offer a shutdown terminal for conserving battery life in portable applications. During shutdown, the outputs are placed in a high-impedance state and the amplifier consumes only 350 nA/channel. The family is fully specified at 3 V and 5 V across an expanded industrial temperature range ( - 40°C to 125°C). The singles and duals are available in the SOT23 and MSOP packages, while the quads are available in TSSOP. The TLV2470 offers an amplifier with shutdown functionality all in a 6-pin SOT23 package, making it perfect for high density power-sensitive circuits. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40°C to 125°C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltage values, except differential voltages, are with respect to GND. PACKAGE D (8) D (14) D (16) DBV (5) DBV (6) DGN (8) DGQ (10) N (14, 16) P (8) PWP (14) PWP (16) DISSIPATION RATING TABLE θJC (°C/W) θJA (°C/W) 38.3 176 26.9 122.3 25.7 114.7 55 324.1 55 294.3 4.7 52.7 4.7 52.3 32 78 41 104 2.07 30.7 2.07 29.7 TA ≤ 25°C POWER RATING 710 mW 1022 mW 1090 mW 385 mW 425 mW 2.37 W 2.39 W 1600 mW 1200 mW 4.07 W 4.21 W recommended operating conditions Supply voltage, VDD Common-mode input voltage range, VICR Operating free-air temperature, TA Shutdown on/off voltage level‡ ‡ Relative to GND Single supply Split supply C-suffix I-suffix VIH VIL MIN 2.7 ±1.35 0 0 - 40 2 MAX 6 ±3 VDD 70 125 0.8 UNIT V V °C V 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER VIO Input offset voltage TEST CONDITIONS TLV247x TLV247xA TA† 25°C MIN TYP MAX UNIT 250 2200 Full range 25°C 2400 µV 250 1600 Full range 1800 αVIO IIO Temperature coefficient of input offset voltage Input offset current VIC = VDD/2, VO = VDD/2, RS = 50 Ω TLV247xC TLV247xI 25°C Full range Full range 25°C 0.4 µV/°C 1.5 50 100 300 pA 2 50 IIB Input bias current TLV247xC Full range 100 TLV247xI Full range 300 25°C 2.85 2.94 IOH = - 2.5 mA Full range 2.8 VOH High-level output voltage VIC = VDD/2 V 25°C 2.6 2.74 IOH = - 10 mA Full range 2.5 VOL Low-level output voltage VIC = VDD/2 IOL = 2.5 mA IOL = 10 mA 25°C Full range 25°C Full range 0.07 0.15 0.2 V 0.2 0.35 0.5 Sourcing 25°C 30 Full range 20 25°C 62 Sourcing, Outside of rails‡ TLV247xC Full range 60 TLV247xI Full range 59 IOS Short-circuit output current mA 25°C 30 Sinking Full range 20 Sinking, Outside of rails‡ TLV247xC TLV247xI 25°C 62 Full range 60 Full range 59 IO Output current VO = 0.5 V from rail 25°C ±22 mA Large-signal differential voltage 25°C 90 116 AVD amplification VO(PP) = 1 V, RL = 10 kΩ Full range 88 dB ri(d) Differential input resistance 25°C 1012 Ω CIC Common-mode input capacitance f = 10 kHz 25°C 19.3 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 2 Ω † Full range is 0°C to 70°C for C suffix and - 40°C to 125°C for I suffix. If not specified, full range is - 40°C to 125°C. ‡ Depending on package dissipation rating • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) (continued) CMRR PARAMETER Common-mode rejection ratio TEST CONDITIONS VIC = 0 to 3 V, RS = 50 Ω TLV247xC TLV247xI TA† 25°C Full range Full range MIN TYP 61 78 59 58 kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 6 V, No load VDD = 3 V to 5 V, No load VIC = VDD /2, VIC = VDD /2, 25°C 74 90 Full range 66 25°C 77 92 Full range 68 25°C 550 IDD Supply current (per channel) VO = 1.5 V, No load Full range Supply current in shutdown mode 25°C 350 IDD(SHDN) (TLV2470, TLV2473, TLV2475) (per channel) SHDN = 0 V TLV247xC TLV247xI Full range Full range † Full range is 0°C to 70°C for C suffix and - 40°C to 125°C for I suffix. If not specified, full range is - 40°C to 125°C. MAX 750 800 1500 2000 4000 UNIT dB dB µA nA operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER SR Slew rate at unity gain TEST CONDITIONS VO(PP) = 0.8 V, RL = 10 kΩ CL = 150 pF, TA† MIN 25°C 1.1 Full range 0.6 TYP MAX UNIT 1.4 V/µs f = 100 Hz Vn Equivalent input noise voltage f = 1 kHz 25°C 25°C 28 nV/√Hz 15 In Equivalent input noise current f = 1 kHz THD + N Total harmonic distortion plus noise VO(PP) = 2 V, RL = 10 kΩ, f = 1 kHz t(on) Amplifier turnon time t(off) Amplifier turnoff time Gain-bandwidth product RL = OPEN‡ f = 10 kHz, AV = 1 AV = 10 AV = 100 RL = 600 Ω 25°C 25°C 25°C 25°C 25°C 0.405 0.02% 0.1% 0.5% 5 250 2.8 pA /√Hz µs ns MHz ts Settling time V(STEP)PP = 2 V, AV = - 1, CL = 10 pF, RL = 10 kΩ V(STEP)PP = 2 V, AV = - 1, CL = 56 pF, RL = 10 kΩ 0.1% 0.01% 0.1% 0.01% 25°C 1.5 3.9 µs 1.6 4 φm Phase margin RL = 10 kΩ, CL = 1000 pF 25°C 61° Gain margin RL = 10 kΩ, CL = 1000 pF 25°C 15 dB † Full range is 0°C to 70°C for C suffix and - 40°C to 125°C for I suffix. If not specified, full range is - 40°C to 125°C. ‡ Depending on package dissipation rating 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER VIO Input offset voltage TEST CONDITIONS TLV247x TLV247xA TA† 25°C MIN TYP MAX UNIT 250 2200 Full range 25°C 2400 µV 250 1600 Full range 2000 αVIO IIO Temperature coefficient of input offset voltage Input offset current VIC = VDD/2, VO = VDD/2, RS = 50 Ω TLV247xC TLV247xI 25°C Full range Full range 25°C 0.4 µV/°C 1.7 50 100 300 pA 2.5 50 IIB Input bias current TLV247xC Full range 100 TLV247xI Full range 300 25°C 4.85 4.96 IOH = - 2.5 mA Full range 4.8 VOH High-level output voltage VIC = VDD/2 V 25°C 4.72 4.82 IOH = - 10 mA Full range 4.65 VOL Low-level output voltage VIC = VDD/2 IOL = 2.5 mA IOL = 10 mA 25°C Full range 25°C Full range 0.07 0.15 0.2 V 0.178 0.28 0.35 Sourcing 25°C 110 Full range 60 25°C 63 Sourcing, Outside of rails‡ TLV247xC Full range 61 TLV247xI Full range 58 IOS Short-circuit output current mA 25°C 90 Sinking Full range 60 Sinking, Outside of rails‡ TLV247xC TLV247xI 25°C 63 Full range 61 Full range 58 IO Output current VO = 0.5 V from rail 25°C ±35 mA Large-signal differential voltage 25°C 92 120 AVD amplification VO(PP) = 3 V, RL = 10 kΩ Full range 91 dB ri(d) Differential input resistance 25°C 1012 Ω CIC Common-mode input capacitance f = 10 kHz 25°C 18.9 pF zo Closed-loop output impedance f = 10 kHz, AV = 10 25°C 1.8 Ω † Full range is 0°C to 70°C for C suffix and - 40°C to 125°C for I suffix. If not specified, full range is - 40°C to 125°C. ‡ Depending on package dissipation rating • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) CMRR PARAMETER Common-mode rejection ratio TEST CONDITIONS VIC = 0 to 5 V, RS = 50 Ω TLV247xC TLV247xI TA† 25°C Full range Full range MIN TYP 64 84 63 58 kSVR Supply voltage rejection ratio (∆VDD /∆VIO) VDD = 2.7 V to 6 V, No load VDD = 3 V to 5 V, No load VIC = VDD /2, VIC = VDD /2, 25°C 74 90 Full range 66 25°C 77 92 Full range 66 25°C 600 IDD Supply current (per channel) VO = 2.5 V, No load Full range IDD(SHDN) Supply current in shutdown mode (TLV2470, TLV2473, TLV2475) (per channel) SHDN = 0 V TLV247xC TLV247xI 25°C Full range Full range † Full range is 0°C to 70°C for C suffix and - 40°C to 125°C for I suffix. If not specified, full range is - 40°C to 125°C. 1000 MAX 900 1000 2500 3000 6000 UNIT dB dB µA nA nA operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER SR Slew rate at unity gain TEST CONDITIONS VO(PP) = 2 V, RL = 10 kΩ CL = 150 pF, TA† MIN 25°C 1.1 Full range 0.7 TYP MAX UNIT 1.5 V/µs f = 100 Hz Vn Equivalent input noise voltage f = 1 kHz 25°C 25°C 28 nV/√Hz 15 In Equivalent input noise current f = 1 kHz THD + N Total harmonic distortion plus noise VO(PP) = 4 V, RL = 10 kΩ, f = 1 kHz t(on) Amplifier turnon time t(off) Amplifier turnoff time Gain-bandwidth product RL = OPEN‡ f = 10 kHz, AV = 1 AV = 10 AV = 100 RL = 600 Ω 25°C 25°C 25°C 25°C 25°C 0.39 0.01% 0.05% 0.3% 5 250 2.8 pA /√Hz µs ns MHz ts Settling time V(STEP)PP = 2 V, AV = - 1, CL = 10 pF, RL = 10 kΩ V(STEP)PP = 2 V, AV = - 1, CL = 56 pF, RL = 10 kΩ 0.1% 0.01% 0.1% 0.01% 25°C 1.8 3.3 µs 1.7 3 φm Phase margin RL = 10 kΩ, CL = 1000 pF 25°C 68° Gain margin RL = 10 kΩ, CL = 1000 pF 25°C 23 dB † Full range is 0°C to 70°C for C suffix and - 40°C to 125°C for I suffix. If not specified, full range is - 40°C to 125°C. ‡ Disable and enable time are defined as the interval between application of logic signal to SHDN and the point at which the supply current has reached half its final value. 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 VIO IIB IIO VOH VOL Zo IDD PSRR CMRR Vn VO(PP) AVD φm SR THD+N VO IDD(SHDN) IDD(SHDN) IDD(SHDN) TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 TYPICAL CHARACTERISTICS Table of Graphs Input offset voltage Input bias current Input offset current High-level output voltage Low-level output voltage Output impedance Supply current Power supply rejection ratio Common-mode rejection ratio Equivalent input noise voltage Maximum peak-to-peak output voltage Differential voltage gain and phase Phase margin Gain margin Gain-bandwidth product Slew rate Crosstalk Total harmonic distortion + noise Large and small signal follower Shutdown pulse response Shutdown forward and reverse isolation Shutdown supply current Shutdown supply current Shutdown pulse current vs Common-mode input voltage vs Free-air temperature vs High-level output current vs Low-level output current vs Frequency vs Supply voltage vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Load capacitance vs Load capacitance vs Supply voltage vs Supply voltage vs Free-air temperature vs Frequency vs Frequency vs Time vs Time vs Frequency vs Supply voltage vs Free-air temperature vs Time FIGURE 1, 2 3, 4 5, 7 6, 8 9 10 11 12 13 14, 15 16, 17 18, 19 20, 21 22 23 24, 25 26 27, 28 29 - 32 33, 34 35, 36 37 38 39, 40 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 TYPICAL CHARACTERISTICS VIO - Input Offset Voltage - µV INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 600 400 VDD=3 V TA=25° C 200 0 - 200 - 400 - 600 - 800 - 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VICR - Common-Mode Input Voltage - V Figure 1 INPUT BIAS AND INPUT OFFSET CURRENTS vs FREE-AIR TEMPERATURE 50 VDD=5 V 40 30 20 IIB 10 0 IIO - 10 - 55 - 35 - 15 5 25 45 65 85 105 125 TA - Free-Air Temperature - °C Figure 4 V OH - High-Level Output Voltage - V VIO - Input Offset Voltage - µV INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 600 400 VDD=5 V TA=25 °C 200 0 - 200 - 400 - 600 - 800 - 0.5 0.5 1.5 2.5 3.5 4.5 5.5 VICR - Common-Mode Input Voltage - V Figure 2 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 3.0 VDD=3 V 2.5 2.0 1.5 TA=125°C TA=85°C 1.0 0.5 TA=25°C TA= - 40°C 0.0 0 10 20 30 40 50 60 IOH - High-Level Output Current - mA Figure 5 VOL - Low-Level Output Voltage - V I IB - Input Bias Current - pA I IO - Input Offset Current - pA INPUT BIAS AND INPUT OFFSET CURRENTS vs FREE-AIR TEMPERATURE 50 VDD=3 V 40 30 IIB 20 10 0 IIO - 10 - 55 - 35 - 15 5 25 45 65 85 105 125 TA - Free-Air Temperature - °C Figure 3 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3.0 VDD=3 V 2.5 TA=125°C 2.0 TA=85°C 1.5 TA=25°C TA= - 40°C 1.0 0.5 0.0 0 10 20 30 40 50 IOL - Low-Level Output Current - mA Figure 6 I IB - Input Bias Current - pA I IO - Input Offset Current - pA V OH - High-Level Output Voltage - V HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 5.5 5.0 VDD=5 V 4.5 4.0 3.5 3.0 2.5 TA=125°C 2.0 TA=85°C 1.5 1.0 TA=25°C 0.5 TA= - 40°C 0.0 0 20 40 60 80 100 120 140 160 IOH - High-Level Output Current - mA Figure 7 VOL - Low-Level Output Voltage - V LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 5.0 4.5 TA=125°C 4.0 TA=85°C 3.5 TA=25°C 3.0 TA= - 40°C 2.5 2.0 1.5 1.0 0.5 0.0 0 VDD=5 V 20 40 60 80 100 120 140 IOL - Low-Level Output Current - mA Figure 8 Z o - Output Impedance - Ω OUTPUT IMPEDANCE vs FREQUENCY 1000 100 VDD=3 & 5 V TA=25°C AV=100 10 AV=10 1 AV=1 0.1 0.01 100 1k 10k 100k 1M 10M f - Frequency - Hz Figure 9 10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 I DD - Supply Current - mA V n - Equivalent Input Noise Voltage - nV/ Hz TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE 1.0 0.9 TA=85°C 0.8 TA=125°C 0.7 0.6 TA=25°C 0.5 0.4 TA= - 40°C 0.3 0.2 AV= 1 0.1 SHDN= VDD Per Channel 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD - Supply Voltage - V Figure 10 PSRR - Power Supply Rejection Ratio - dB POWER SUPPLY REJECTION RATIO vs FREQUENCY 100 PSRR+ 90 80 PSRR - VDD=3 & 5 V RF=5 kΩ RI=50 Ω TA=25°C 70 60 50 40 30 10 100 1k 10k 100k 1M 10M f - Frequency - Hz Figure 11 CMRR - Common-Mode Rejection Ratio - dB COMMON-MODE REJECTION RATIO vs FREQUENCY 130 120 110 100 VDD=5 V 90 VIC=2.5 V 80 70 VDD=3 V VIC=1.5 V 60 50 100 1k 10k 100k 1M 10M f - Frequency - Hz Figure 12 EQUIVALENT NOISE VOLTAGE vs FREQUENCY 80 VDD=3 & 5 V 70 AV= 10 VIN= VDD/2 60 TA=25°C 50 40 30 20 10 0 10 100 1k 10k 100k f - Frequency - Hz Figure 13 V O(PP) - Maximum Peak-To-Peak Output Voltage - V MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 5.5 5.0 4.5 VO(PP)=5 V THD+N ≤ 2.0% RL=10 kΩ TA=25°C 4.0 3.5 3.0 2.5 VO(PP)=3 V 2.0 1.5 1.0 0.5 0.0 10k 100k 1M f - Frequency - Hz Figure 14 V O(PP) - Maximum Peak-To-Peak Output Voltage - V MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 5.5 5.0 THD+N ≤ 2.0% RL=600 Ω 4.5 TA=25°C 4.0 VO(PP)=5 V 3.5 3.0 2.5 2.0 VO(PP)=3 V 1.5 1.0 0.5 0.0 10k 100k 1M f - Frequency - Hz Figure 15 DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY 100 45 VDD=±3 80 RL=600 Ω 0 CL=0 60 TA=25°C - 45 DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY 100 45 80 VDD=±5 RL=600 Ω 0 CL=0 60 TA=25°C - 45 Phase - ° Phase - ° 40 - 90 40 - 90 20 - 135 20 - 135 AVD - Differential Voltage Gain - dB AVD - Differential Voltage Gain - dB 0 - 180 0 - 180 - 20 - 225 - 20 - 225 - 40 - 270 100 1k 10k 100k 1M 10M 100M Frequency - Hz Figure 16 - 40 - 270 100 1k 10k 100k 1M 10M 100M Frequency - Hz Figure 17 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 TYPICAL CHARACTERISTICS PHASE MARGIN vs LOAD CAPACITANCE PHASE MARGIN vs LOAD CAPACITANCE GAIN MARGIN vs LOAD CAPACITANCE φ m - Phase Margin - ° 90 VDD=3 V 80 RL=10 kΩ TA=25°C 70 See Figure 42 Rnull=50 60 Rnull=100 50 40 Rnull=20 30 20 10 Rnull=0 0 100 1k 10k CL - Load Capacitance - pF Figure 18 100k φ m - Phase Margin - ° 100 90 VDD=5V RL=10 kΩ 80 TA=25°C See Figure 42 70 Rnull=100 60 Rnull=50 50 40 30 Rnull=20 20 10 Rnull=0 0 100 1k 10k CL - Load Capacitance - pF Figure 19 100k Gain Margin - dB 0 VDD=3V RL=10 kΩ 5 TA=25°C 10 Rnull=0 15 Rnull=100 Rnull=20 20 25 30 100 Rnull=50 1k 10k CL - Load Capacitance - pF Figure 20 100k Gain Margin - dB GAIN MARGIN vs LOAD CAPACITANCE 0 5 Rnull=0 10 15 Rnull=20 20 25 Rnull=50 Rnull=100 30 35 100 VDD=5V RL=10 kΩ TA=25°C 1k 10k CL - Load Capacitance - pF Figure 21 100k Gain-Bandwidth Product - MHz GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 4.0 3.5 RL=10 kΩ 3.0 2.5 RL=600 Ω 2.0 1.5 CL=11 pF 1.0 f=10 kHz TA=25°C 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD - Supply Voltage - V Figure 22 SR - Slew Rate - V/µs SLEW RATE vs SUPPLY VOLTAGE 2.0 1.8 SR - 1.6 1.4 SR+ 1.2 1.0 0.8 0.6 0.4 VO(PP)=1.5 V AV= - 1 0.2 RL=10 kΩ CL=150 pF 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD - Supply Voltage - V Figure 23 SLEW RATE vs FREE-AIR TEMPERATURE SLEW RATE vs FREE-AIR TEMPERATURE SR - Slew Rate - V/µs SR - Slew Rate - V/µs 2.00 1.75 1.50 SR+ SR 1.25 1.00 0.75 0.50 0.25 0.00 VDD=3 V RL=10 kΩ CL=150 pF AV= - 1 - 55 - 35 - 15 5 25 45 65 85 105 125 TA - Free-Air Temperature - °C Figure 24 2.00 1.75 SR - 1.50 SR+ 1.25 1.00 0.75 0.50 0.25 VDD=5 V RL=10 kΩ CL=150 pF AV= - 1 0.00 - 55 - 35 - 15 5 25 45 65 85 105 125 TA - Free-Air Temperature - °C Figure 25 12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Crosstalk - dB TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 TYPICAL CHARACTERISTICS CROSSTALK vs FREQUENCY 0 VDD = 3V & 5V - 20 AV = 1 RL= 600Ω - 40 VI(PP)=2V All Channels - 60 - 80 - 100 - 120 - 140 - 160 10 100 1k 10 k f - Frequency - Hz Figure 26 100 k THD+N - Total Harmonic Distortion + Noise TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 1 AV = 100 AV = 10 0.1 AV = 1 0.01 VDD = 3 V RL = 10 kΩ V0 = 2 VPP TA = 25°C 0.001 10 100 1k 10k f - Frequency - Hz Figure 27 100k THD+N - Total Harmonic Distortion + Noise TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 1 AV = 100 0.1 AV = 10 AV = 1 0.01 VDD = 5 V RL = 10 kΩ V0 = 4 VPP TA = 25°C 0.001 10 100 1k 10k f - Frequency - Hz Figure 28 100k LARGE SIGNAL FOLLOWER PULSE RESPONSE vs TIME VI (2 V/DIV) VO (1 V/DIV) VDD = 3 V RL = 10 kΩ CL = 8 pF f = 85 kHz TA = 25°C 0 1 2 3 4 5 6 7 8 9 10 t - Time - µs Figure 29 V O - Output Voltage LARGE SIGNAL FOLLOWER PULSE RESPONSE vs TIME VI (2 V/DIV) VO (1 V/DIV) VDD = 5 V RL = 10 kΩ CL = 8 pF f = 85 kHz TA = 25°C 0 1 2 3 4 5 6 7 8 9 10 t - Time - µs Figure 30 V O - Output Voltage SMALL SIGNAL FOLLOWER PULSE RESPONSE vs TIME VDD = 3 V RL = 10 kΩ CL = 8 pF f = 1 MHz TA = 25°C VI (50 mV/DIV) VO (50 mV/DIV) 0 100 200 300 400 500 t - Time - µs Figure 31 SMALL SIGNAL FOLLOWER PULSE RESPONSE vs TIME VI (50 mV/DIV) VDD = 5 V RL = 10 kΩ CL = 8 pF f = 1 MHz TA = 25°C SHUTDOWN (ON AND OFF) PULSE RESPONSE vs TIME VSHDN (2 V/DIV) RL = 600 Ω RL = 10 kΩ SHUTDOWN (ON AND OFF) PULSE RESPONSE vs TIME VSHDN (2 V/DIV) RL = 600 Ω RL = 10 kΩ V O - Output Voltage V O - Output Voltage VO (50 mV/DIV) 0 100 200 300 400 500 t - Time - µs Figure 32 VDD = 3 V CL = 8 pF TA = 25°C VO (500 mV/DIV) 0 2 4 6 8 10 12 14 16 t - Time - µs Figure 33 VO (1 V/DIV) VDD = 5 V CL = 8 pF TA = 25°C 02 4 6 8 10 12 14 16 18 t - Time - µs Figure 34 V O - Output Voltage V O - Output Voltage • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 13 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 TYPICAL CHARACTERISTICS Shutdown Forward Isolation - dB SHUTDOWN FORWARD ISOLATION vs FREQUENCY 120 VDD = 3 & 5 V 100 CL=0 pF AV = 1 VI(PP)=0.1, 1.5, 3 V 80 RL=600 Ω 60 RL=10 kΩ 40 20 0 100 1k 10k 100k 1M 10M f - Frequency - Hz Figure 35 Shutdown Forward Isolation - dB SHUTDOWN REVERSE ISOLATION vs FREQUENCY 120 VDD = 3 & 5 V RL=10 kΩ 100 CL=0 pF AV = 1 80 VIN=0.1, 1.5, 3 Vp-p 60 RL=10 kΩ RL=600 Ω 40 20 0 100 1k 10k 100k 1M 10M f - Frequency - Hz Figure 36 I DD(SHDN) - Shutdown Supply Current - µA SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE 2.0 1.8 1.6 1.4 TA=125 1.2 TA=85 1.0 TA=25 0.8 TA= - 40 0.6 0.4 0.2 0.0 2.5 Shutdown On RL=OPEN VI=VDD/2 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD - Supply Voltage - V Figure 37 I DD - Shutdown Supply Current - µ A SHUTDOWN SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.6 SD MODE Channel 1 & 2 1.4 AV = 1 RL= OPEN 1.2 VIN=VDD/2 1.0 VDD=5 V 0.8 0.6 0.4 VDD=3 V 0.2 0.0 - 55 - 35 - 15 5 25 45 65 85 105 125 TA - Free-Air Temperature - °C Figure 38 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 - 0.25 - 0.5 SHUTDOWN PULSE CURRENT vs TIME 4 Shutdown Pulse 3 2 1 IDD RL=10 kΩ 0 -1 -2 IDD RL=600Ω -3 -4 04 -5 VDD = 3 V -6 CL=8 pF TA=25°C -7 -8 8 12 16 20 24 28 30 t - Time - µs Figure 39 Shutdown Pulse - V I DD - Supply Current - mA 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 - 0.25 - 0.5 SHUTDOWN PULSE CURRENT vs TIME 6 Shutdown Pulse 4 2 0 IDD RL=10 kΩ -2 -4 IDD RL=600 Ω -6 04 VDD = 5 V CL=8 pF TA=25°C 8 12 16 20 t - Time - µs Figure 40 -8 - 10 - 12 24 28 30 Shutdown Pulse - V I DD - Supply Current - mA 14 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION _ Rnull + RL CL Figure 41 APPLICATION INFORMATION driving a capacitive load When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in Figure 42. A minimum value of 20 Ω should work well for most applications. RF RG Input _ + RNULL Output CLOAD Figure 42. Driving a Capacitive Load offset voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB RG + - VI + VO RS IIB+ ǒ ǒ ǓǓ ǒ ǒ ǓǓ VOO + VIO 1) RF RG " IIB) RS 1) RF RG " IIB– RF Figure 43. Output Offset Voltage Model • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 15 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 APPLICATION INFORMATION general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 44). RG RF VI R1 - + VO C1 f–3dB + 1 2pR1C1 ǒ Ǔǒ Ǔ VO VI + 1 ) RF RG 1 1 ) sR1C1 Figure 44. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 VI R1 + R2 _ C2 RF RG R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) f–3dB + 1 2pRC ( ) RG = RF 1 2- Q Figure 45. 2-Pole Low-Pass Sallen-Key Filter shutdown function Three members of the TLV247x family (TLV2470/3/5) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 350 nA/channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2. Therefore, when operating the device with split supply voltages (e.g. ± 2.5 V), the shutdown terminal needs to be pulled to VDD - (not GND) to disable the operational amplifier. 16 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 APPLICATION INFORMATION shutdown function (continued) The amplifier’s output with a shutdown pulse is shown in Figures 33 and 34. The amplifier is powered with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. Figures 35 and 36 show the amplifier’s forward and reverse isolation in shutdown. The operational amplifier is powered by ±1.35-V supplies and configured as a voltage follower (AV = 1). The isolation performance is plotted across frequency using 0.1-VPP, 1.5-VPP, and 2.5-VPP input signals. During normal operation, the amplifier would not be able to handle a 2.5-VPP input signal with a supply voltage of ±1.35 V since it exceeds the common-mode input voltage range (VICR). However, this curve illustrates that the amplifier remains in shutdown even under a worst case scenario. circuit layout considerations To achieve the levels of high performance of the TLV247x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. D Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling - Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. D Sockets - Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements - Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. D Surface-mount passive components - Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 17 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 APPLICATION INFORMATION general PowerPAD design considerations The TLV247x is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 46(a) and Figure 46(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 46(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 46. Views of Thermally Enhanced DGN Package Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. Thermal Pad Area Single or Dual Quad 68 mils x 70 mils) with 5 vias (Via diameter = 13 mils 78 mils x 94 mils) with 9 vias (Via diameter = 13 mils) Figure 47. PowerPAD PCB Etch and Via Pattern PowerPAD is a trademark of Texas Instruments Incorporated. 18 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 APPLICATION INFORMATION general PowerPAD design considerations (continued) 1. Prepare the PCB with a top side etch pattern as shown in Figure 47. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLV247x IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLV247x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the TLV247x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given θJA, the maximum power dissipation is shown in Figure 48 and is calculated by the following formula: ǒ Ǔ PD + TMAX–TA qJA Where: PD = Maximum power dissipation of TLV247x IC (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case θCA = Thermal coefficient from case to ambient air (°C/W) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 19 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 APPLICATION INFORMATION general PowerPAD design considerations (continued) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 7 PWP Package Low-K Test PCB TJ = 150°C 6 θJA = 29.7°C/W SOT-23 Package 5 DGN Package Low-K Test PCB θJA = 324°C/W Low-K Test PCB 4 θJA = 52.3°C/W SOIC Package Low-K Test PCB 3 PDIP Package θJA = 176°C/W Low-K Test PCB 2 θJA = 104°C/W Maximum Power Dissipation - W 1 0 - 55 - 40 - 25 - 10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - °C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 48. Maximum Power Dissipation vs Free-Air Temperature The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 49 to Figure 54 show this effect, along with the quiescent heat, with an ambient air temperature of 70°C and 125°C. When using VDD = 3 V, there is generally not a heat problem with an ambient air temperature of 70°C. But, when using VDD = 5 V, the packages are severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper package. 20 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 APPLICATION INFORMATION general PowerPAD design considerations (continued) TLV2470, TLV2471† MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 Maximum Output 160 Current Limit Line TLV2470, TLV2471† MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 Maximum Output 160 Current Limit Line | IO | - Maximum RMS Output Current - mA | IO | - Maximum RMS Output Current - mA 140 C Packages With 120 θJA ≤ 110°C/W at TA = 125°C 100 B or θJA ≤ 355°C/W 80 A at TA = 70°C 60 Safe Operating Area 40 VDD = ± 3 V 20 TJ = 150°C TA = 125°C 0 0 0.25 0.5 0.75 1 1.25 1.5 | VO | - RMS Output Voltage - V Figure 49 140 G C 120 B 100 A 80 Packages With 60 θJA ≤ 210°C/W 40 at TA = 70°C 20 VDD = ± 5 V TJ = 150°C 0 TA = 125°C Safe Operating Area 0 0.5 1 1.5 2 2.5 | VO | - RMS Output Voltage - V Figure 50 TLV2472, TLV2473† MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 Maximum Output 160 Current Limit Line TLV2472, TLV2473† MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 Maximum Output 160 Current Limit Line | IO | - Maximum RMS Output Current - mA | IO | - Maximum RMS Output Current - mA 140 G H 120 D 100 80 60 C Packages With θJA ≤ 55°C/W at TA = 125°C or θJA ≤ 178°C/W at TA = 70°C 40 VDD = ± 3 V 20 TJ = 150°C TA = 125°C 0 0 0.25 0.5 Safe Operating Area 0.75 1 1.25 1.5 | VO | - RMS Output Voltage - V Figure 51 140 120 100 80 60 40 20 0 0 F G H D C Packages With VDD = ± 5 V TJ = 150°C TA = 125°C θJA ≤ 105°C/W at TA = 70°C Safe Operating Area 0.5 1 1.5 2 2.5 | VO | - RMS Output Voltage - V Figure 52 † A - SOT23(5); B - SOT23 (6); C - SOIC (8); D - SOIC (14); E - SOIC (16); F - MSOP PP (8); G - PDIP (8); H - PDIP (14); I - PDIP (16); J - TSSOP PP (14/16) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 21 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 APPLICATION INFORMATION general PowerPAD design considerations (continued) TLV2474, TLV2475† MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 Maximum Output 160 Current Limit Line TLV2474, TLV2475† MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS 180 Maximum Output 160 Current Limit Line | IO | - Maximum RMS Output Current - mA | IO | - Maximum RMS Output Current - mA 140 J 120 H and I 140 J 120 100 100 E H and I 80 Packages With 80 60 D θJA ≤ 88°C/W at TA = 70°C VDD = ± 5 V 60 TJ = 150°C E D TA = 125°C 40 VDD = ±3 V 20 TJ = 150°C 0 TA = 125°C 0 0.25 0.5 Safe Operating Area 0.75 1 1.25 1.5 40 20 0 0 Safe Operating Area Packages With θJA ≤ 52°C/W at TA = 70°C 0.5 1 1.5 2 2.5 | VO | - RMS Output Voltage - V Figure 53 | VO | - RMS Output Voltage - V Figure 54 † A - SOT23(5); B - SOT23 (6); C - SOIC (8); D - SOIC (14); E - SOIC (16); F - MSOP PP (8); G - PDIP (8); H - PDIP (14); I - PDIP (16); J - TSSOP PP (14/16) 22 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 TLV2470, TLV2471, TLV2472, TLV2473, TLV2474, TLV2475, TLV247xA FAMILY OF 600−µA/Ch 2.8−MHz RAIL−TO−RAIL INPUT/OUTPUT HIGH−DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN SLOS232C - JUNE 1999 - REVISED AUGUST 2003 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 55 are generated using the TLV247x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): D Maximum positive output voltage swing D Maximum negative output voltage swing D Slew rate D Quiescent power dissipation D Input bias current D Open-loop voltage amplification D Unity-gain frequency D Common-mode rejection ratio D Phase margin D DC output resistance D AC output resistance D Short-circuit output current limit NOTE 1: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 3 VDD 99 + rp 1 IN+ 2 IN - rd1 rd2 c1 11 12 DD G G rss + vc 53 css egnd fb - 9 r2 + vb - c2 6 gcm ioff ro2 7 + vlim 8 ga ro1 S S dp 10 91 dlp 90 dln 92 OUT 5 iss dc GND 4 - + 54 ve de * TLV247x operational amplifier ”macromodel” subcircuit * created using Parts release 8.0 on 4/27/99 at 14:31 * Parts is a MicroSim product. * * connections: non - inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | || .subckt TLV247x 1 2 3 4 5 * c1 11 12 1.1094E- 12 c2 6 7 5.5000E- 12 css 10 99 556.53E- 15 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 + 39.614E6 - 1E3 1E3 40E6 - 40E6 ga 6 0 11 12 79.828E - 6 gcm 0 6 10 99 32.483E - 9 + vlp - + hlim - vln + iss 10 4 dc 10.714E- 6 hlim 90 0 vlim 1K ioff 0 6 dc 75E- 9 j1 11 2 10 jx1 j2 12 1 10 jx2 r2 6 9 100.00E3 rd1 3 11 12.527E3 rd2 3 12 12.527E3 ro1 8 5 10 ro2 7 99 10 rp 3 4 3.8023E3 rss 10 99 18.667E6 vb 9 0 dc 0 vc 3 53 dc .842 ve 54 4 dc .842 vlim 7 8 dc 0 vlp 91 0 dc 110 vln 0 92 dc 110 .model dx D(Is=800.00E- 18) .model dy D(Is=800.00E- 18 Rs=1m Cjo=10p) .model jx1 NJF(Is=1.0825E- 12 Beta=594.78E - 06 + Vto= - 1) .model jx2 NJF(Is=1.0825E- 12 Beta=594.78E - 06 + Vto= - 1) .ends *$ Figure 55. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 23 P (R-PDIP-T8) 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 MECHANICAL DATA MPDI001A – JANUARY 1995 – REVISED JUNE 1999 PLASTIC DUAL-IN-LINE 0.325 (8,26) 0.300 (7,62) 0.430 (10,92) MAX 0.015 (0,38) Gage Plane 0.010 (0,25) NOM 4040082/D 05/98 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 MECHANICAL DATA D (R-PDSO-G**) 8 PINS SHOWN 0.050 (1,27) 8 0.020 (0,51) 0.014 (0,35) 5 MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 PLASTIC SMALL-OUTLINE PACKAGE 0.010 (0,25) 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 1 4 A 0.008 (0,20) NOM Gage Plane 0°– 8° 0.010 (0,25) 0.044 (1,12) 0.016 (0,40) 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) Seating Plane 0.004 (0,10) PINS ** 8 DIM A MAX A MIN 0.197 (5,00) 0.189 (4,80) 14 16 0.344 (8,75) 0.337 (8,55) 0.394 (10,00) 0.386 (9,80) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012 4040047/E 09/01 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 PW (R-PDSO-G**) 14 PINS SHOWN 0,65 14 0,30 0,19 8 0,10 M 4,50 6,60 4,30 6,20 1 7 A MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PLASTIC SMALL-OUTLINE PACKAGE 0,15 NOM Gage Plane 0°– 8° 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 PINS ** 8 DIM 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 4040064/F 01/97 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 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