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Datasheet RL78/G13 R01DS0131EJ0310 RENESAS MCU Rev.3.10 Nov 15, 2013 True Low Power Platform (as low as 66 µA/MHz, and 0.57 µA for RTC + LVD), 1.6 V to 5.5 V operation, 16 to 512 Kbyte Flash, 41 DMIPS at 32 MHz, for General Purpose Applications 1. OUTLINE 1.1 Features Ultra-Low Power Technology • 1.6 V to 5.5 V operation from a single supply • Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA • Halt (RTC + LVD): 0.57 µA • Snooze: 0.70 mA (UART), 1.20 mA (ADC) • Operating: 66 µA/MHz 16-bit RL78 CPU Core • Delivers 41 DMIPS at maximum operating frequency of 32 MHz • Instruction Execution: 86% of instructions can be executed in 1 to 2 clock cycles • CISC Architecture (Harvard) with 3-stage pipeline • Multiply Signed & Unsigned: 16 x 16 to 32-bit result in 1 clock cycle • MAC: 16 x 16 to 32-bit result in 2 clock cycles • 16-bit barrel shifter for shift & rotate in 1 clock cycle • 1-wire on-chip debug function Main Flash Memory • Density: 16 KB to 512 KB • Block size: 1 KB • On-chip single voltage flash memory with protection from block erase/writing • Self-programming with secure boot swap function and flash shield window function Data Flash Memory • Data Flash with background operation • Data flash size: 4 KB to 8 KB size options • Erase Cycles: 1 Million (typ.) • Erase/programming voltage: 1.8 V to 5.5 V RAM • 2 KB to 32 KB size options • Supports operands or instructions • Back-up retention in all modes High-speed On-chip Oscillator • 32 MHz with +/− 1% accuracy over voltage (1.8 V to 5.5 V) and temperature (−20 °C to 85 °C) • Pre-configured settings: 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz Reset and Supply Management • Power-on reset (POR) monitor/generator • Low voltage detection (LVD) with 14 setting options (Interrupt and/or reset function) Data Memory Access (DMA) Controller • Up to 4 fully programmable channels • Transfer unit: 8- or 16-bit Multiple Communication Interfaces • Up to 8 x I2C master • Up to 2 x I2C multi-master • Up to 8 x CSI/SPI (7-, 8-bit) • Up to 4 x UART (7-, 8-, 9-bit) • Up to 1 x LIN Extended-Function Timers • Multi-function 16-bit timers: Up to 16 channels • Real-time clock (RTC): 1 channel (full calendar and alarm function with watch correction function) • Interval Timer: 12-bit, 1 channel • 15 kHz watchdog timer : 1 channel (window function) Rich Analog • ADC: Up to 26 channels, 10-bit resolution, 2.1 µs conversion time • Supports 1.6 V • Internal voltage reference (1.45 V) • On-chip temperature sensor Safety Features (IEC or UL 60730 compliance) • Flash memory CRC calculation • RAM parity error check • RAM write protection • SFR write protection • Illegal memory access detection • Clock stop/ frequency detection • ADC self-test General Purpose I/O • 5V tolerant, high-current (up to 20 mA per pin) • Open-Drain, Internal Pull-up support • Different potential interface support: Can connect to a 1.8/2.5/3 V device Operating Ambient Temperature • Standard: −40 °C to +85 °C • Extended: −40 °C to +105 °C Package Type and Pin Count From 3mm x 3mm to 14mm x 20mm QFP: 44, 48, 52, 64, 80, 100, 128 QFN: 24, 32, 40, 48 SSOP: 20, 30 LGA: 25, 36 BGA: 64 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 1 of 194 RL78/G13 1. OUTLINE  ROM, RAM capacities Flash Data RAM ROM 128 KB 96 KB flash 8 KB − 8 KB − 12 KB 8 KB 20 pins − − − − 64 4 KB 4 KB R5F1006E KB − Note 1 R5F1016E 48 4 KB 3 KB KB − R5F1006D R5F1016D 32 4 KB 2 KB KB − 16 4 KB 2 KB KB − R5F1006C R5F1016C R5F1006A R5F1016A 24 pins − − − − R5F1007E R5F1017E R5F1007D R5F1017D R5F1007C R5F1017C R5F1007A R5F1017A RL78/G13 25 pins − − − 30 pins R5F100AG R5F101AG R5F100AF − R5F1008E R5F1018E R5F1008D R5F101AF R5F100AE R5F101AE R5F100AD R5F1018D R5F101AD R5F1008C R5F1018C R5F1008A R5F100AC R5F101AC R5F100AA R5F1018A R5F101AA 32 pins R5F100BG R5F101BG R5F100BF R5F101BF R5F100BE R5F101BE R5F100BD R5F101BD R5F100BC R5F101BC R5F100BA R5F101BA 36 pins R5F100CG R5F101CG R5F100CF R5F101CF R5F100CE R5F101CE R5F100CD R5F101CD R5F100CC R5F101CC R5F100CA R5F101CA Flash Data RAM RL78/G13 ROM 512 KB flash 8 KB − 32 KB Note 3 40 pins − − 44 pins 48 pins 52 pins 64 pins 80 pins 100 pins 128 pins R5F100FL R5F100GL R5F100JL R5F100LL R5F100ML R5F100PL R5F100SL R5F101FL R5F101GL R5F101JL R5F101LL R5F101ML R5F101PL R5F101SL 384 8 KB 24 KB − R5F100FK R5F100GK R5F100JK R5F100LK R5F100MK R5F100PK R5F100SK KB − − R5F101FK R5F101GK R5F101JK R5F101LK R5F101MK R5F101PK R5F101SK 256 8 KB 20 KB − R5F100FJ R5F100GJ R5F100JJ R5F100LJ R5F100MJ R5F100PJ R5F100SJ KB Note 2 − − R5F101FJ R5F101GJ R5F101JJ R5F101LJ R5F101MJ R5F101PJ R5F101SJ 192 8 KB 16 KB R5F100EH R5F100FH R5F100GH R5F100JH R5F100LH R5F100MH R5F100PH R5F100SH KB − R5F101EH R5F101FH R5F101GH R5F101JH R5F101LH R5F101MH R5F101PH R5F101SH 128 8 KB 12 KB R5F100EG R5F100FG R5F100GG R5F100JG R5F100LG R5F100MG R5F100PG − KB − R5F101EG R5F101FG R5F101GG R5F101JG R5F101LG R5F101MG R5F101PG − 96 8 KB 8 KB R5F100EF R5F100FF R5F100GF R5F100JF R5F100LF R5F100MF R5F100PF − KB − R5F101EF R5F101FF R5F101GF R5F101JF R5F101LF R5F101MF R5F101PF − 64 4 KB 4 KB R5F100EE R5F100FE R5F100GE R5F100JE R5F100LE − − − KB Note 1 − R5F101EE R5F101FE R5F101GE R5F101JE R5F101LE − − − 48 4 KB 3 KB R5F100ED R5F100FD R5F100GD R5F100JD R5F100LD − − − KB − R5F101ED R5F101FD R5F101GD R5F101JD R5F101LD − − − 32 4 KB 2 KB R5F100EC R5F100FC R5F100GC R5F100JC R5F100LC − − − KB − R5F101EC R5F101FC R5F101GC R5F101JC R5F101LC − − − 16 4 KB 2 KB R5F100EA R5F100FA R5F100GA − − − − − KB − R5F101EA R5F101FA R5F101GA − − − − − Notes 1. 2. 3. This is about 3 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/G13 User’s Manual Hardware) This is about 19 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/G13 User’s Manual Hardware) This is about 31 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/G13 User’s Manual Hardware) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 2 of 194 RL78/G13 1. OUTLINE 1.2 List of Part Numbers Figure 1-1. Part Number, Memory Size, and Package of RL78/G13 Part No. R 5 F 1 0 0 L E A x x x F B #V0 Packaging specification #U0 : Tray (HWQFN,VFBGA,WFLGA) #V0 : Tray (LFQFP,LQFP,LSSOP) #W0 : Embossed Tape (HWQFN,VFBGA,WFLGA) #X0 : Embossed Tape (LFQFP, LQFP, LSSOP) Package type: SP: LSSOP, 0.65 mm pitch FP : LFQFP, 0.80 mm pitch FA : LFQFP, 0.65 mm pitch FB : LFQFP, 0.50 mm pitch NA : HWQFN, 0.50 mm pitch LA : WFLGA, 0.50 mm pitchNote 1 BG : VFBGA, 0.40 mm pitch Note 1 ROM number (Omitted with blank products) Fields of application: A : Consumer applications, operating ambient temperature : -40˚C to +85˚C D : Industrial applications, operating ambient temperature : -40˚C to +85˚C G : Industrial applications, operating ambient temperature : -40˚C to +105˚C ROM capacity: A : 16 KB C : 32 KB D : 48 KB E : 64 KB F : 96 KB G : 128 KB H : 192 KB J : 256 KB K : 384 KBNote 2 L : 512 KBNote 2 Pin count: 6 : 20-pin 7 : 24-pin 8 : 25-pinNote 1 A : 30-pin B : 32-pin C : 36-pinNote 1 E : 40-pin F : 44-pin G : 48-pin J : 52-pin L : 64-pin M : 80-pin P : 100-pin S : 128-pinNote 2 RL78/G13 group Note 2 Memory type: F : Flash memory Renesas MCU Renesas semiconductor product Notes 1. Products only for “A: Consumer applications (TA = −40 to +85°C)” 2. Products only for “A: Consumer applications (TA = −40 to +85°C)”, and ” D: Industrial applications (TA = −40 to +85°C) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 3 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (1/12) 20 pins 20-pin plastic LSSOP Mounted A (7.62 mm (300), 0.65 mm pitch) D G Not A mounted D 24 pins 24-pin plastic HWQFN (4 × 4mm, 0.5 mm pitch) Mounted A D G Not A mounted D R5F1006AASP#V0, R5F1006CASP#V0, R5F1006DASP#V0, R5F1006EASP#V0 R5F1006AASP#X0, R5F1006CASP#X0, R5F1006DASP#X0, R5F1006EASP#X0 R5F1006ADSP#V0, R5F1006CDSP#V0, R5F1006DDSP#V0, R5F1006EDSP#V0 R5F1006ADSP#X0, R5F1006CDSP#X0, R5F1006DDSP#X0, R5F1006EDSP#X0 R5F1006AGSP#V0, R5F1006CGSP#V0, R5F1006DGSP#V0, R5F1006EGSP#V0 R5F1006AGSP#X0, R5F1006CGSP#X0, R5F1006DGSP#X0, R5F1006EGSP#X0 R5F1016AASP#V0, R5F1016CASP#V0, R5F1016DASP#V0, R5F1016EASP#V0 R5F1016AASP#X0, R5F1016CASP#X0, R5F1016DASP#X0, R5F1016EASP#X0 R5F1016ADSP#V0, R5F1016CDSP#V0, R5F1016DDSP#V0, R5F1016EDSP#V0 R5F1016ADSP#X0, R5F1016CDSP#X0, R5F1016DDSP#X0, R5F1016EDSP#X0 R5F1007AANA#U0, R5F1007CANA#U0, R5F1007DANA#U0, R5F1007EANA#U0 R5F1007AANA#W0, R5F1007CANA#W0, R5F1007DANA#W0, R5F1007EANA#W0 R5F1007ADNA#U0, R5F1007CDNA#U0, R5F1007DDNA#U0, R5F1007EDNA#U0 R5F1007ADNA#W0, R5F1007CDNA#W0, R5F1007DDNA#W0, R5F1007EDNA#W0 R5F1007AGNA#U0, R5F1007CGNA#U0, R5F1007DGNA#U0, R5F1007EGNA#U0 R5F1007AGNA#W0, R5F1007CGNA#W0, R5F1007DGNA#W0, R5F1007EGNA#W0 R5F1017AANA#U0, R5F1017CANA#U0, R5F1017DANA#U0, R5F1017EANA#U0 R5F1017AANA#W0, R5F1017CANA#W0, R5F1017DANA#W0, R5F1017EANA#W0 R5F1017ADNA#U0, R5F1017CDNA#U0, R5F1017DDNA#U0, R5F1017EDNA#U0 R5F1017ADNA#W0, R5F1017CDNA#W0, R5F1017DDNA#W0, R5F1017EDNA#W0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 4 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (2/12) 25 pins 25-pin plastic WFLGA (3 × 3 mm, 0.5 mm pitch) Mounted A Not A mounted 30 pins 30-pin plastic LSSOP Mounted A (7.62 mm (300), 0.65 mm pitch) D G Not A mounted D 32 pins 32-pin plastic HWQFN (5 × 5 mm, 0.5 mm pitch) Mounted A D G Not A mounted D R5F1008AALA#U0, R5F1008CALA#U0, R5F1008DALA#U0, R5F1008EALA#U0 R5F1008AALA#W0, R5F1008CALA#W0, R5F1008DALA#W0, R5F1008EALA#W0 R5F1018AALA#U0, R5F1018CALA#U0, R5F1018DALA#U0, R5F1018EALA#U0 R5F1018AALA#W0, R5F1018CALA#W0, R5F1018DALA#W0, R5F1018EALA#W0 R5F100AAASP#V0, R5F100ACASP#V0, R5F100ADASP#V0, R5F100AEASP#V0, R5F100AFASP#V0, R5F100AGASP#V0 R5F100AAASP#X0, R5F100ACASP#X0, R5F100ADASP#X0 R5F100AEASP#X0, R5F100AFASP#X0, R5F100AGASP#X0 R5F100AADSP#V0, R5F100ACDSP#V0, R5F100ADDSP#V0, R5F100AEDSP#V0, R5F100AFDSP#V0, R5F100AGDSP#V0 R5F100AADSP#X0, R5F100ACDSP#X0, R5F100ADDSP#X0, R5F100AEDSP#X0, R5F100AFDSP#X0, R5F100AGDSP#X0 R5F100AAGSP#V0, R5F100ACGSP#V0, R5F100ADGSP#V0,R5F100AEGSP#V0, R5F100AFGSP#V0, R5F100AGGSP#V0 R5F100AAGSP#X0, R5F100ACGSP#X0, R5F100ADGSP#X0,R5F100AEGSP#X0, R5F100AFGSP#X0, R5F100AGGSP#X0 R5F101AAASP#V0, R5F101ACASP#V0, R5F101ADASP#V0, R5F101AEASP#V0, R5F101AFASP#V0, R5F101AGASP#V0 R5F101AAASP#X0, R5F101ACASP#X0, R5F101ADASP#X0, R5F101AEASP#X0, R5F101AFASP#X0, R5F101AGASP#X0 R5F101AADSP#V0, R5F101ACDSP#V0, R5F101ADDSP#V0, R5F101AEDSP#V0, R5F101AFDSP#V0, R5F101AGDSP#V0 R5F101AADSP#X0, R5F101ACDSP#X0, R5F101ADDSP#X0, R5F101AEDSP#X0, R5F101AFDSP#X0, R5F101AGDSP#X0 R5F100BAANA#U0, R5F100BCANA#U0, R5F100BDANA#U0, R5F100BEANA#U0, R5F100BFANA#U0, R5F100BGANA#U0 R5F100BAANA#W0, R5F100BCANA#W0, R5F100BDANA#W0, R5F100BEANA#W0, R5F100BFANA#W0, R5F100BGANA#W0 R5F100BADNA#U0, R5F100BCDNA#U0, R5F100BDDNA#U0, R5F100BEDNA#U0, R5F100BFDNA#U0, R5F100BGDNA#U0 R5F100BADNA#W0, R5F100BCDNA#W0, R5F100BDDNA#W0, R5F100BEDNA#W0, R5F100BFDNA#W0, R5F100BGDNA#W0 R5F100BAGNA#U0, R5F100BCGNA#U0, R5F100BDGNA#U0, R5F100BEGNA#U0, R5F100BFGNA#U0, R5F100BGGNA#U0 R5F100BAGNA#W0, R5F100BCGNA#W0, R5F100BDGNA#W0, R5F100BEGNA#W0, R5F100BFGNA#W0, R5F100BGGNA#W0 R5F101BAANA#U0, R5F101BCANA#U0, R5F101BDANA#U0, R5F101BEANA#U0, R5F101BFANA#U0, R5F101BGANA#U0 R5F101BAANA#W0, R5F101BCANA#W0, R5F101BDANA#W0, R5F101BEANA#W0, R5F101BFANA#W0, R5F101BGANA#W0 R5F101BADNA#U0, R5F101BCDNA#U0, R5F101BDDNA#U0, R5F101BEDNA#U0, R5F101BFDNA#U0, R5F101BGDNA#U0 R5F101BADNA#W0, R5F101BCDNA#W0, R5F101BDDNA#W0, R5F101BEDNA#W0, R5F101BFDNA#W0, R5F101BGDNA#W0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 5 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (3/12) 36 pins 36-pin plastic WFLGA (4 × 4 mm, 0.5 mm pitch) Mounted A Not A mounted 40 pins 40-pin plastic HWQFN (6 × 6 mm, 0.5 mm pitch) Mounted A D G Not A mounted D R5F100CAALA#U0, R5F100CCALA#U0, R5F100CDALA#U0, R5F100CEALA#U0, R5F100CFALA#U0, R5F100CGALA#U0 R5F100CAALA#W0, R5F100CCALA#W0, R5F100CDALA#W0, R5F100CEALA#W0, R5F100CFALA#W0, R5F100CGALA#W0 R5F101CAALA#U0, R5F101CCALA#U0, R5F101CDALA#U0, R5F101CEALA#U0, R5F101CFALA#U0, R5F101CGALA#U0 R5F101CAALA#W0, R5F101CCALA#W0, R5F101CDALA#W0, R5F101CEALA#W0, R5F101CFALA#W0, R5F101CGALA#W0 R5F100EAANA#U0, R5F100ECANA#U0, R5F100EDANA#U0, R5F100EEANA#U0, R5F100EFANA#U0, R5F100EGANA#U0, R5F100EHANA#U0 R5F100EAANA#W0, R5F100ECANA#W0, R5F100EDANA#W0, R5F100EEANA#W0, R5F100EFANA#W0, R5F100EGANA#W0, R5F100EHANA#W0 R5F100EADNA#U0, R5F100ECDNA#U0, R5F100EDDNA#U0, R5F100EEDNA#U0, R5F100EFDNA#U0, R5F100EGDNA#U0, R5F100EHDNA#U0 R5F100EADNA#W0, R5F100ECDNA#W0, R5F100EDDNA#W0, R5F100EEDNA#W0, R5F100EFDNA#W0, R5F100EGDNA#W0, R5F100EHDNA#W0 R5F100EAGNA#U0, R5F100ECGNA#U0, R5F100EDGNA#U0, R5F100EEGNA#U0, R5F100EFGNA#U0, R5F100EGGNA#U0, R5F100EHGNA#U0 R5F100EAGNA#W0, R5F100ECGNA#W0, R5F100EDGNA#W0, R5F100EEGNA#W0, R5F100EFGNA#W0, R5F100EGGNA#W0, R5F100EHGNA#W0 R5F101EAANA#U0, R5F101ECANA#U0, R5F101EDANA#U0, R5F101EEANA#U0, R5F101EFANA#U0, R5F101EGANA#U0, R5F101EHANA#U0 R5F101EAANA#W0, R5F101ECANA#W0, R5F101EDANA#W0, R5F101EEANA#W0, R5F101EFANA#W0, R5F101EGANA#W0, R5F101EHANA#W0 R5F101EADNA#U0, R5F101ECDNA#U0, R5F101EDDNA#U0, R5F101EEDNA#U0, R5F101EFDNA#U0, R5F101EGDNA#U0, R5F101EHDNA#U0 R5F101EADNA#W0, R5F101ECDNA#W0, R5F101EDDNA#W0, R5F101EEDNA#W0, R5F101EFDNA#W0, R5F101EGDNA#W0, R5F101EHDNA#W0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 6 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (4/12) 44 pins 44-pin plastic LQFP Mounted A (10 × 10 mm, 0.8 mm pitch) D G Not A mounted D R5F100FAAFP#V0, R5F100FCAFP#V0, R5F100FDAFP#V0, R5F100FEAFP#V0, R5F100FFAFP#V0, R5F100FGAFP#V0, R5F100FHAFP#V0, R5F100FJAFP#V0, R5F100FKAFP#V0, R5F100FLAFP#V0 R5F100FAAFP#X0, R5F100FCAFP#X0, R5F100FDAFP#X0, R5F100FEAFP#X0, R5F100FFAFP#X0, R5F100FGAFP#X0, R5F100FHAFP#X0, R5F100FJAFP#X0, R5F100FKAFP#X0, R5F100FLAFP#X0 R5F100FADFP#V0, R5F100FCDFP#V0, R5F100FDDFP#V0, R5F100FEDFP#V0, R5F100FFDFP#V0, R5F100FGDFP#V0, R5F100FHDFP#V0, R5F100FJDFP#V0, R5F100FKDFP#V0, R5F100FLDFP#V0 R5F100FADFP#X0, R5F100FCDFP#X0, R5F100FDDFP#X0, R5F100FEDFP#X0, R5F100FFDFP#X0, R5F100FGDFP#X0, R5F100FHDFP#X0, R5F100FJDFP#X0, R5F100FKDFP#X0, R5F100FLDFP#X0 R5F100FAGFP#V0, R5F100FCGFP#V0, R5F100FDGFP#V0, R5F100FEGFP#V0, R5F100FFGFP#V0, R5F100FGGFP#V0, R5F100FHGFP#V0, R5F100FJGFP#V0 R5F100FAGFP#X0, R5F100FCGFP#X0, R5F100FDGFP#X0, R5F100FEGFP#X0, R5F100FFGFP#X0, R5F100FGGFP#X0, R5F100FHGFP#X0, R5F100FJGFP#X0 R5F101FAAFP#V0, R5F101FCAFP#V0, R5F101FDAFP#V0, R5F101FEAFP#V0, R5F101FFAFP#V0, R5F101FGAFP#V0, R5F101FHAFP#V0, R5F101FJAFP#V0, R5F101FKAFP#V0, R5F101FLAFP#V0 R5F101FAAFP#X0, R5F101FCAFP#X0, R5F101FDAFP#X0, R5F101FEAFP#X0, R5F101FFAFP#X0, R5F101FGAFP#X0, R5F101FHAFP#X0, R5F101FJAFP#X0, R5F101FKAFP#X0, R5F101FLAFP#X0 R5F101FADFP#V0, R5F101FCDFP#V0, R5F101FDDFP#V0, R5F101FEDFP#V0, R5F101FFDFP#V0, R5F101FGDFP#V0, R5F101FHDFP#V0, R5F101FJDFP#V0, R5F101FKDFP#V0, R5F101FLDFP#V0 R5F101FADFP#X0, R5F101FCDFP#X0, R5F101FDDFP#X0, R5F101FEDFP#X0, R5F101FFDFP#X0, R5F101FGDFP#X0, R5F101FHDFP#X0, R5F101FJDFP#X0, R5F101FKDFP#X0, R5F101FLDFP#X0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 7 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (5/12) 48 pins 48-pin plastic LFQFP Mounted A (7 × 7 mm, 0.5 mm pitch) D G Not A mounted D R5F100GAAFB#V0, R5F100GCAFB#V0, R5F100GDAFB#V0, R5F100GEAFB#V0, R5F100GFAFB#V0, R5F100GGAFB#V0, R5F100GHAFB#V0, R5F100GJAFB#V0, R5F100GKAFB#V0, R5F100GLAFB#V0 R5F100GAAFB#X0, R5F100GCAFB#X0, R5F100GDAFB#X0, R5F100GEAFB#X0, R5F100GFAFB#X0, R5F100GGAFB#X0, R5F100GHAFB#X0, R5F100GJAFB#X0, R5F100GKAFB#X0, R5F100GLAFB#X0 R5F100GADFB#V0, R5F100GCDFB#V0, R5F100GDDFB#V0, R5F100GEDFB#V0, R5F100GFDFB#V0, R5F100GGDFB#V0, R5F100GHDFB#V0, R5F100GJDFB#V0, R5F100GKDFB#V0, R5F100GLDFB#V0 R5F100GADFB#X0, R5F100GCDFB#X0, R5F100GDDFB#X0, R5F100GEDFB#X0, R5F100GFDFB#X0, R5F100GGDFB#X0, R5F100GHDFB#X0, R5F100GJDFB#X0, R5F100GKDFB#X0, R5F100GLDFB#X0 R5F100GAGFB#V0, R5F100GCGFB#V0, R5F100GDGFB#V0, R5F100GEGFB#V0, R5F100GFGFB#V0, R5F100GGGFB#V0, R5F100GHGFB#V0, R5F100GJGFB#V0 R5F100GAGFB#X0, R5F100GCGFB#X0, R5F100GDGFB#X0, R5F100GEGFB#X0, R5F100GFGFB#X0, R5F100GGGFB#X0, R5F100GHGFB#X0, R5F100GJGFB#X0 R5F101GAAFB#V0, R5F101GCAFB#V0, R5F101GDAFB#V0, R5F101GEAFB#V0, R5F101GFAFB#V0, R5F101GGAFB#V0, R5F101GHAFB#V0, R5F101GJAFB#V0, R5F101GKAFB#V0, R5F101GLAFB#V0 R5F101GAAFB#X0, R5F101GCAFB#X0, R5F101GDAFB#X0, R5F101GEAFB#X0, R5F101GFAFB#X0, R5F101GGAFB#X0, R5F101GHAFB#X0, R5F101GJAFB#X0, R5F101GKAFB#X0, R5F101GLAFB#X0 R5F101GADFB#V0, R5F101GCDFB#V0, R5F101GDDFB#V0, R5F101GEDFB#V0, R5F101GFDFB#V0, R5F101GGDFB#V0, R5F101GHDFB#V0, R5F101GJDFB#V0, R5F101GKDFB#V0, R5F101GLDFB#V0 R5F101GADFB#X0, R5F101GCDFB#X0, R5F101GDDFB#X0, R5F101GEDFB#X0, R5F101GFDFB#X0, R5F101GGDFB#X0, R5F101GHDFB#X0, R5F101GJDFB#X0, R5F101GKDFB#X0, R5F101GLDFB#X0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 8 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (6/12) 48 pins 48-pin plastic Mounted A HWQFN (7 × 7 mm, 0.5 mm pitch) D G Not A mounted D R5F100GAANA#U0, R5F100GCANA#U0, R5F100GDANA#U0, R5F100GEANA#U0, R5F100GFANA#U0, R5F100GGANA#U0, R5F100GHANA#U0, R5F100GJANA#U0, R5F100GKANA#U0, R5F100GLANA#U0 R5F100GAANA#W0, R5F100GCANA#W0, R5F100GDANA#W0, R5F100GEANA#W0, R5F100GFANA#W0, R5F100GGANA#W0, R5F100GHANA#W0, R5F100GJANA#W0, R5F100GKANA#W0, R5F100GLANA#W0 R5F100GADNA#U0, R5F100GCDNA#U0, R5F100GDDNA#U0, R5F100GEDNA#U0, R5F100GFDNA#U0, R5F100GGDNA#U0, R5F100GHDNA#U0, R5F100GJDNA#U0, R5F100GKDNA#U0, R5F100GLDNA#U0 R5F100GADNA#W0, R5F100GCDNA#W0, R5F100GDDNA#W0, R5F100GEDNA#W0, R5F100GFDNA#W0, R5F100GGDNA#W0, R5F100GHDNA#W0, R5F100GJDNA#W0, R5F100GKDNA#W0, R5F100GLDNA#W0 R5F100GAGNA#U0, R5F100GCGNA#U0, R5F100GDGNA#U0, R5F100GEGNA#U0, R5F100GFGNA#U0, R5F100GGGNA#U0, R5F100GHGNA#U0, R5F100GJGNA#U0 R5F100GAGNA#W0, R5F100GCGNA#W0, R5F100GDGNA#W0, R5F100GEGNA#W0, R5F100GFGNA#W0, R5F100GGGNA#W0, R5F100GHGNA#W0, R5F100GJGNA#W0 R5F101GAANA#U0, R5F101GCANA#U0, R5F101GDANA#U0, R5F101GEANA#U0, R5F101GFANA#U0, R5F101GGANA#U0, R5F101GHANA#U0, R5F101GJANA#U0, R5F101GKANA#U0, R5F101GLANA#U0 R5F101GAANA#W0, R5F101GCANA#W0, R5F101GDANA#W0, R5F101GEANA#W0, R5F101GFANA#W0, R5F101GGANA#W0, R5F101GHANA#W0, R5F101GJANA#W0, R5F101GKANA#W0, R5F101GLANA#W0 R5F101GADNA#U0, R5F101GCDNA#U0, R5F101GDDNA#U0, R5F101GEDNA#U0, R5F101GFDNA#U0, R5F101GGDNA#U0, R5F101GHDNA#U0, R5F101GJDNA#U0, R5F101GKDNA#U0, R5F101GLDNA#U0 R5F101GADNA#W0, R5F101GCDNA#W0, R5F101GDDNA#W0, R5F101GEDNA#W0, R5F101GFDNA#W0, R5F101GGDNA#W0, R5F101GHDNA#W0, R5F101GJDNA#W0, R5F101GKDNA#W0, R5F101GLDNA#W0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 9 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (7/12) 52 pins 52-pin plastic LQFP Mounted A (10 × 10 mm, 0.65 mm pitch) D G Not A mounted D R5F100JCAFA#V0, R5F100JDAFA#V0, R5F100JEAFA#V0, R5F100JFAFA#V0, R5F100JGAFA#V0, R5F100JHAFA#V0, R5F100JJAFA#V0, R5F100JKAFA#V0, R5F100JLAFA#V0 R5F100JCAFA#X0, R5F100JDAFA#X0, R5F100JEAFA#X0, R5F100JFAFA#X0, R5F100JGAFA#X0, R5F100JHAFA#X0, R5F100JJAFA#X0, R5F100JKAFA#X0, R5F100JLAFA#X0 R5F100JCDFA#V0, R5F100JDDFA#V0, R5F100JEDFA#V0, R5F100JFDFA#V0, R5F100JGDFA#V0, R5F100JHDFA#V0, R5F100JJDFA#V0, R5F100JKDFA#V0, R5F100JLDFA#V0 R5F100JCDFA#X0, R5F100JDDFA#X0, R5F100JEDFA#X0, R5F100JFDFA#X0, R5F100JGDFA#X0, R5F100JHDFA#X0, R5F100JJDFA#X0, R5F100JKDFA#X0, R5F100JLDFA#X0 R5F100JCGFA#V0, R5F100JDGFA#V0, R5F100JEGFA#V0, R5F100JFGFA#V0,R5F100JGGFA#V0, R5F100JHGFA#V0, R5F100JJGFA#V0 R5F100JCGFA#X0, R5F100JDGFA#X0, R5F100JEGFA#X0, R5F100JFGFA#X0,R5F100JGGFA#X0, R5F100JHGFA#X0, R5F100JJGFA#X0 R5F101JCAFA#V0, R5F101JDAFA#V0, R5F101JEAFA#V0, R5F101JFAFA#V0, R5F101JGAFA#V0, R5F101JHAFA#V0, R5F101JJAFA#V0, R5F101JKAFA#V0, R5F101JLAFA#V0 R5F101JCAFA#X0, R5F101JDAFA#X0, R5F101JEAFA#X0, R5F101JFAFA#X0, R5F101JGAFA#X0, R5F101JHAFA#X0, R5F101JJAFA#X0, R5F101JKAFA#X0, R5F101JLAFA#X0 R5F101JCDFA#V0, R5F101JDDFA#V0, R5F101JEDFA#V0, R5F101JFDFA#V0, R5F101JGDFA#V0, R5F101JHDFA#V0, R5F101JJDFA#V0, R5F101JKDFA#V0, R5F101JLDFA#V0 R5F101JCDFA#X0, R5F101JDDFA#X0, R5F101JEDFA#X0, R5F101JFDFA#X0, R5F101JGDFA#X0, R5F101JHDFA#X0, R5F101JJDFA#X0, R5F101JKDFA#X0, R5F101JLDFA#X0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 10 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (8/12) 64 pins 64-pin plastic LQFP (12 × 12 mm, 0.65 mm pitch) Mounted A D G Not A mounted D R5F100LCAFA#V0, R5F100LDAFA#V0, R5F100LEAFA#V0, R5F100LFAFA#V0, R5F100LGAFA#V0, R5F100LHAFA#V0, R5F100LJAFA#V0, R5F100LKAFA#V0, R5F100LLAFA#V0 R5F100LCAFA#X0, R5F100LDAFA#X0, R5F100LEAFA#X0, R5F100LFAFA#X0, R5F100LGAFA#X0, R5F100LHAFA#X0, R5F100LJAFA#X0, R5F100LKAFA#X0, R5F100LLAFA#X0 R5F100LCDFA#V0, R5F100LDDFA#V0, R5F100LEDFA#V0, R5F100LFDFA#V0, R5F100LGDFA#V0, R5F100LHDFA#V0, R5F100LJDFA#V0, R5F100LKDFA#V0, R5F100LLDFA#V0 R5F100LCDFA#X0, R5F100LDDFA#X0, R5F100LEDFA#X0, R5F100LFDFA#X0, R5F100LGDFA#X0, R5F100LHDFA#X0, R5F100LJDFA#X0, R5F100LKDFA#X0, R5F100LLDFA#X0 R5F100LCGFA#V0, R5F100LDGFA#V0, R5F100LEGFA#V0, R5F100LFGFA#V0 R5F100LGGFA#V0, R5F100LHGFA#V0, R5F100LJGFA#V0 R5F100LCGFA#X0, R5F100LDGFA#X0, R5F100LEGFA#X0, R5F100LFGFA#X0 R5F100LGGFA#X0, R5F100LHGFA#X0, R5F100LJGFA#X0 R5F101LCAFA#V0, R5F101LDAFA#V0, R5F101LEAFA#V0, R5F101LFAFA#V0, R5F101LGAFA#V0, R5F101LHAFA#V0, R5F101LJAFA#V0, R5F101LKAFA#V0, R5F101LLAFA#V0 R5F101LCAFA#X0, R5F101LDAFA#X0, R5F101LEAFA#X0, R5F101LFAFA#X0, R5F101LGAFA#X0, R5F101LHAFA#X0, R5F101LJAFA#X0, R5F101LKAFA#X0, R5F101LLAFA#X0 R5F101LCDFA#V0, R5F101LDDFA#V0, R5F101LEDFA#V0, R5F101LFDFA#V0, R5F101LGDFA#V0, R5F101LHDFA#V0, R5F101LJDFA#V0, R5F101LKDFA#V0, R5F101LLDFA#V0 R5F101LCDFA#X0, R5F101LDDFA#X0, R5F101LEDFA#X0, R5F101LFDFA#X0, R5F101LGDFA#X0, R5F101LHDFA#X0, R5F101LJDFA#X0, R5F101LKDFA#X0, R5F101LLDFA#X0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 11 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (9/12) 64 pins 64-pin plastic LFQFP Mounted A (10 × 10 mm, 0.5 mm pitch) D G Not A mounted D R5F100LCAFB#V0, R5F100LDAFB#V0, R5F100LEAFB#V0, R5F100LFAFB#V0, R5F100LGAFB#V0, R5F100LHAFB#V0, R5F100LJAFB#V0, R5F100LKAFB#V0, R5F100LLAFB#V0 R5F100LCAFB#X0, R5F100LDAFB#X0, R5F100LEAFB#X0, R5F100LFAFB#X0, R5F100LGAFB#X0, R5F100LHAFB#X0, R5F100LJAFB#X0, R5F100LKAFB#X0, R5F100LLAFB#X0 R5F100LCDFB#V0, R5F100LDDFB#V0, R5F100LEDFB#V0, R5F100LFDFB#V0, R5F100LGDFB#V0, R5F100LHDFB#V0, R5F100LJDFB#V0, R5F100LKDFB#V0, R5F100LLDFB#V0 R5F100LCDFB#X0, R5F100LDDFB#X0, R5F100LEDFB#X0, R5F100LFDFB#X0, R5F100LGDFB#X0, R5F100LHDFB#X0, R5F100LJDFB#X0, R5F100LKDFB#X0, R5F100LLDFB#X0 R5F100LCGFB#V0, R5F100LDGFB#V0, R5F100LEGFB#V0, R5F100LFGFB#V0 R5F100LGGFB#V0, R5F100LHGFB#V0, R5F100LJGFB#V0 R5F100LCGFB#X0, R5F100LDGFB#X0, R5F100LEGFB#X0, R5F100LFGFB#X0 R5F100LGGFB#X0, R5F100LHGFB#X0, R5F100LJGFB#X0 R5F101LCAFB#V0, R5F101LDAFB#V0, R5F101LEAFB#V0, R5F101LFAFB#V0, R5F101LGAFB#V0, R5F101LHAFB#V0, R5F101LJAFB#V0, R5F101LKAFB#V0, R5F101LLAFB#V0 R5F101LCAFB#X0, R5F101LDAFB#X0, R5F101LEAFB#X0, R5F101LFAFB#X0, R5F101LGAFB#X0, R5F101LHAFB#X0, R5F101LJAFB#X0, R5F101LKAFB#X0, R5F101LLAFB#X0 R5F101LCDFB#V0, R5F101LDDFB#V0, R5F101LEDFB#V0, R5F101LFDFB#V0, R5F101LGDFB#V0, R5F101LHDFB#V0, R5F101LJDFB#V0, R5F101LKDFB#V0, R5F101LLDFB#V0 R5F101LCDFB#X0, R5F101LDDFB#X0, R5F101LEDFB#X0, R5F101LFDFB#X0, R5F101LGDFB#X0, R5F101LHDFB#X0, R5F101LJDFB#X0, R5F101LKDFB#X0, R5F101LLDFB#X0 64-pin plastic VFBGA Mounted A (4 × 4 mm, 0.4 mm pitch) Not A mounted R5F100LCABG#U0, R5F100LDABG#U0, R5F100LEABG#U0, R5F100LFABG#U0, R5F100LGABG#U0, R5F100LHABG#U0, R5F100LJABG#U0 R5F100LCABG#W0, R5F100LDABG#W0, R5F100LEABG#W0, R5F100LFABG#W0, R5F100LGABG#W0, R5F100LHABG#W0, R5F100LJABG#W0 R5F101LCABG#U0, R5F101LDABG#U0, R5F101LEABG#U0, R5F101LFABG#U0, R5F101LGABG#U0, R5F101LHABG#U0, R5F101LJABG#U0 R5F101LCABG#W0, R5F101LDABG#W0, R5F101LEABG#W0, R5F101LFABG#W0, R5F101LGABG#W0, R5F101LHABG#W0, R5F101LJABG#W0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 12 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (10/12) 80 pins 80-pin plastic Mounted A LQFP (14 × 14 mm, 0.65 mm pitch) D G R5F100MFAFA#V0, R5F100MGAFA#V0, R5F100MHAFA#V0, R5F100MJAFA#V0, R5F100MKAFA#V0, R5F100MLAFA#V0 R5F100MFAFA#X0, R5F100MGAFA#X0, R5F100MHAFA#X0, R5F100MJAFA#X0, R5F100MKAFA#X0, R5F100MLAFA#X0 R5F100MFDFA#V0, R5F100MGDFA#V0, R5F100MHDFA#V0, R5F100MJDFA#V0, R5F100MKDFA#V0, R5F100MLDFA#V0 R5F100MFDFA#X0, R5F100MGDFA#X0, R5F100MHDFA#X0, R5F100MJDFA#X0, R5F100MKDFA#X0, R5F100MLDFA#X0 R5F100MFGFA#V0, R5F100MGGFA#V0, R5F100MHGFA#V0, R5F100MJGFA#V0 R5F100MFGFA#X0, R5F100MGGFA#X0, R5F100MHGFA#X0, R5F100MJGFA#X0 Not A mounted D 80-pin plastic Mounted A LFQFP (12 × 12 mm, 0.5 mm pitch) D G Not A mounted D R5F101MFAFA#V0, R5F101MGAFA#V0, R5F101MHAFA#V0, R5F101MJAFA#V0, R5F101MKAFA#V0, R5F101MLAFA#V0 R5F101MFAFA#X0, R5F101MGAFA#X0, R5F101MHAFA#X0, R5F101MJAFA#X0, R5F101MKAFA#X0, R5F101MLAFA#X0 R5F101MFDFA#V0, R5F101MGDFA#V0, R5F101MHDFA#V0, R5F101MJDFA#V0, R5F101MKDFA#V0, R5F101MLDFA#V0 R5F101MFDFA#X0, R5F101MGDFA#X0, R5F101MHDFA#X0, R5F101MJDFA#X0, R5F101MKDFA#X0, R5F101MLDFA#X0 R5F100MFAFB#V0, R5F100MGAFB#V0, R5F100MHAFB#V0, R5F100MJAFB#V0, R5F100MKAFB#V0, R5F100MLAFB#V0 R5F100MFAFB#X0, R5F100MGAFB#X0, R5F100MHAFB#X0, R5F100MJAFB#X0, R5F100MKAFB#X0, R5F100MLAFB#X0 R5F100MFDFB#V0, R5F100MGDFB#V0, R5F100MHDFB#V0, R5F100MJDFB#V0, R5F100MKDFB#V0, R5F100MLDFB#V0 R5F100MFDFB#X0, R5F100MGDFB#X0, R5F100MHDFB#X0, R5F100MJDFB#X0, R5F100MKDFB#X0, R5F100MLDFB#X0 R5F100MFGFB#V0, R5F100MGGFB#V0, R5F100MHGFB#V0, R5F100MJGFB#V0 R5F100MFGFB#X0, R5F100MGGFB#X0, R5F100MHGFB#X0, R5F100MJGFB#X0 R5F101MFAFB#V0, R5F101MGAFB#V0, R5F101MHAFB#V0, R5F101MJAFB#V0, R5F101MKAFB#V0, R5F101MLAFB#V0 R5F101MFAFB#X0, R5F101MGAFB#X0, R5F101MHAFB#X0, R5F101MJAFB#X0, R5F101MKAFB#X0, R5F101MLAFB#X0 R5F101MFDFB#V0, R5F101MGDFB#V0, R5F101MHDFB#V0, R5F101MJDFB#V0, R5F101MKDFB#V0, R5F101MLDFB#V0 R5F101MFDFB#X0, R5F101MGDFB#X0, R5F101MHDFB#X0, R5F101MJDFB#X0, R5F101MKDFB#X0, R5F101MLDFB#X0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 13 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (11/12) 100 pins 100-pin plastic Mounted A LFQFP (14 × 14 mm, 0.65 mm pitch) D G Not mounted A D 100-pin plastic Mounted A LQFP (14 × 20 mm, 0.65 mm pitch) D G Not mounted A D R5F100PFAFB#V0, R5F100PGAFB#V0, R5F100PHAFB#V0, R5F100PJAFB#V0, R5F100PKAFB#V0, R5F100PLAFB#V0 R5F100PFAFB#X0, R5F100PGAFB#X0, R5F100PHAFB#X0, R5F100PJAFB#X0, R5F100PKAFB#X0, R5F100PLAFB#X0 R5F100PFDFB#V0, R5F100PGDFB#V0, R5F100PHDFB#V0, R5F100PJDFB#V0, R5F100PKDFB#V0, R5F100PLDFB#V0 R5F100PFDFB#X0, R5F100PGDFB#X0, R5F100PHDFB#X0, R5F100PJDFB#X0, R5F100PKDFB#X0, R5F100PLDFB#X0 R5F100PFGFB#V0, R5F100PGGFB#V0, R5F100PHGFB#V0, R5F100PJGFB#V0 R5F100PFGFB#X0, R5F100PGGFB#X0, R5F100PHGFB#X0, R5F100PJGFB#X0 R5F101PFAFB#V0, R5F101PGAFB#V0, R5F101PHAFB#V0, R5F101PJAFB#V0, R5F101PKAFB#V0, R5F101PLAFB#V0 R5F101PFAFB#X0, R5F101PGAFB#X0, R5F101PHAFB#X0, R5F101PJAFB#X0, R5F101PKAFB#X0, R5F101PLAFB#X0 R5F101PFDFB#V0, R5F101PGDFB#V0, R5F101PHDFB#V0, R5F101PJDFB#V0, R5F101PKDFB#V0, R5F101PLDFB#V0 R5F101PFDFB#X0, R5F101PGDFB#X0, R5F101PHDFB#X0, R5F101PJDFB#X0, R5F101PKDFB#X0, R5F101PLDFB#X0 R5F100PFAFA#V0, R5F100PGAFA#V0, R5F100PHAFA#V0, R5F100PJAFA#V0, R5F100PKAFA#V0, R5F100PLAFA#V0 R5F100PFAFA#X0, R5F100PGAFA#X0, R5F100PHAFA#X0, R5F100PJAFA#X0, R5F100PKAFA#X0, R5F100PLAFA#X0 R5F100PFDFA#V0, R5F100PGDFA#V0, R5F100PHDFA#V0, R5F100PJDFA#V0, R5F100PKDFA#V0, R5F100PLDFA#V0 R5F100PFDFA#X0, R5F100PGDFA#X0, R5F100PHDFA#X0, R5F100PJDFA#X0, R5F100PKDFA#X0, R5F100PLDFA#X0 R5F100PFGFA#V0, R5F100PGGFA#V0, R5F100PHGFA#V0, R5F100PJGFA#V0 R5F100PFGFA#X0, R5F100PGGFA#X0, R5F100PHGFA#X0, R5F100PJGFA#X0 R5F101PFAFA#V0, R5F101PGAFA#V0, R5F101PHAFA#V0, R5F101PJAFA#V0, R5F101PKAFA#V0, R5F101PLAFA#V0 R5F101PFAFA#X0, R5F101PGAFA#X0, R5F101PHAFA#X0, R5F101PJAFA#X0, R5F101PKAFA#X0, R5F101PLAFA#X0 R5F101PFDFA#V0, R5F101PGDFA#V0, R5F101PHDFA#V0, R5F101PJDFA#V0, R5F101PKDFA#V0, R5F101PLDFA#V0 R5F101PFDFA#X0, R5F101PGDFA#X0, R5F101PHDFA#X0, R5F101PJDFA#X0, R5F101PKDFA#X0, R5F101PLDFA#X0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 14 of 194 RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers Pin count Package Data flash Fields of Application Note Ordering Part Number (12/12) 128 pins 128-pin plastic LFQFP Mounted A (14 × 20 mm, 0.5 mm pitch) D Not A mounted D R5F100SHAFB#V0, R5F100SJAFB#V0, R5F100SKAFB#V0, R5F100SLAFB#V0 R5F100SHAFB#X0, R5F100SJAFB#X0, R5F100SKAFB#X0, R5F100SLAFB#X0 R5F100SHDFB#V0, R5F100SJDFB#V0, R5F100SKDFB#V0, R5F100SLDFB#V0 R5F100SHDFB#X0, R5F100SJDFB#X0, R5F100SKDFB#X0, R5F100SLDFB#X0 R5F101SHAFB#V0, R5F101SJAFB#V0, R5F101SKAFB#V0, R5F101SLAFB#V0 R5F101SHAFB#X0, R5F101SJAFB#X0, R5F101SKAFB#X0, R5F101SLAFB#X0 R5F101SHDFB#V0, R5F101SJDFB#V0, R5F101SKDFB#V0, R5F101SLDFB#V0 R5F101SHDFB#X0, R5F101SJDFB#X0, R5F101SKDFB#X0, R5F101SLDFB#X0 Note For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 15 of 194 RL78/G13 1.3 Pin Configuration (Top View) 1.3.1 20-pin products • 20-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) 1. OUTLINE P01/ANI16/TO00/RxD1 1 P00/ANI17/TI00/TxD1 2 P40/TOOL0 3 RESET 4 P137/INTP0 5 P122/X2/EXCLK 6 P121/X1 7 REGC 8 VSS 9 VDD 10 20 P20/ANI0/AVREFP 19 P21/ANI1/AVREFM 18 P22/ANI2 17 P147/ANI18 16 P10/SCK00/SCL00 15 P11/SI00/RxD0/TOOLRxD/SDA00 14 P12/SO00/TxD0/TOOLTxD 13 P16/TI01/TO01/INTP5/SO11 12 P17/TI02/TO02/SI11/SDA11 11 P30/INTP3/SCK11/SCL11 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remark For pin identification, see 1.4 Pin Identification. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 16 of 194 RL78/G13 1.3.2 24-pin products • 24-pin plastic HWQFN (4 × 4 mm, 0.5 mm pitch) 1. OUTLINE P22/ANI2 P147/ANI18 P10/SCK00/SCL00 P11/SI00/RxD0/TOOLRxD/SDA00 P12/SO00/TxD0/TOOLTxD P16/TI01/TO01/INTP5 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P40/TOOL0 RESET INDEX MARK exposed die pad 18 17 16 15 14 13 19 12 20 11 21 10 22 9 23 8 24 7 1234 5 6 P17/TI02/TO02/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/SCK11/SCL11 P31/TI03/TO03/INTP4/PCLBUZ0 P61/SDAA0 P60/SCLA0 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. It is recommended to connect an exposed die pad to Vss. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 17 of 194 RL78/G13 1.3.3 25-pin products • 25-pin plastic WFLGA (3 × 3 mm, 0.50 mm pitch) Top View 5 4 3 2 1 ABCDE INDEX MARK Bottom View EDCBA INDEX MARK 1. OUTLINE A P40/TOOL0 5 B RESET C P01/ANI16/ TO00/RxD1 D P22/ANI2 E P147/ANI18 5 P122/X2/ 4 EXCLK P137/INTP0 P00/ANI17/ TI00/TxD1 P21/ANI1/ AVREFM P10/SCK00/ SCL00 4 P121/X1 VDD 3 REGC VSS 2 P20/ANI0/ P12/SO00/ P11/SI00/ AVREFP TxD0/ TOOLTxD RxD0/ TOOLRxD/ 3 SDA00 P30/INTP3/ P17/TI02/ P50/INTP1/ SCK11/SCL11 TO02/SO11 SI11/SDA11 2 P60/SCLA0 P61/SDAA0 P31/TI03/ P16/TI01/ P130 1 TO03/INTP4/ PCLBUZ0 TO01/INTP5 1 A B C D E Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remark For pin identification, see 1.4 Pin Identification. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 18 of 194 RL78/G13 1.3.4 30-pin products • 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) 1. OUTLINE P20/ANI0/AVREFP 1 P01/ANI16/TO00/RxD1 2 P00/ANI17/TI00/TxD1 3 P120/ANI19 4 P40/TOOL0 5 RESET 6 P137/INTP0 7 P122/X2/EXCLK 8 P121/X1 9 REGC 10 VSS 11 VDD 12 P60/SCLA0 13 P61/SDAA0 14 P31/TI03/TO03/INTP4/PCLBUZ0 15 30 P21/ANI1/AVREFM 29 P22/ANI2 28 P23/ANI3 27 P147/ANI18 26 P10/SCK00/SCL00/(TI07)/(TO07) 25 P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) 24 P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) 23 P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) 22 P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) 21 P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) 20 P16/TI01/TO01/INTP5/(RXD0) 19 P17/TI02/TO02/(TXD0) 18 P51/INTP2/SO11 17 P50/INTP1/SI11/SDA11 16 P30/INTP3/SCK11/SCL11 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 19 of 194 RL78/G13 1.3.5 32-pin products • 32-pin plastic HWQFN (5 × 5 mm, 0.5 mm pitch) 1. OUTLINE P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P147/ANI18 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P120/ANI19 INDEX MARK 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 123456 78 exposed die pad P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/SCK11/SCL11 P70 P31/TI03/TO03/INTP4/PCLBUZ0 P62 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. 3. It is recommended to connect an exposed die pad to Vss. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 20 of 194 RL78/G13 1.3.6 36-pin products • 36-pin plastic WFLGA (4 × 4 mm, 0.5 mm pitch) Top View 6 5 4 3 2 1 ABCDEF INDEX MARK 1. OUTLINE Bottom View FEDCBA A P60/SCLA0 6 B VDD C P121/X1 D E F P122/X2/EXCLK P137/INTP0 P40/TOOL0 6 P62 5 P61/SDAA0 VSS REGC RESET P120/ANI19 5 P72/SO21 4 P50/INTP1/ 3 SI11/SDA11 P30/INTP3/ 2 SCK11/SCL11 P51/INTP2/ 1 SO11 A P71/SI21/ SDA21 P70/SCK21/ SCL21 P16/TI01/TO01/ INTP5/(RxD0) P17/TI02/TO02/ (TxD0) B P14/RxD2/SI20/ SDA20/(SCLA0) /(TI03)/(TO03) P15/PCLBUZ1/ SCK20/SCL20/ (TI02)/(TO02) P12/SO00/ TxD0/TOOLTxD /(TI05)/(TO05) P13/TxD2/ SO20/(SDAA0)/ (TI04)/(TO04) C P31/TI03/TO03/ INTP4/ PCLBUZ0 P22/ANI2 P11/SI00/RxD0/ TOOLRxD/ SDA00/(TI06)/ (TO06) P10/SCK00/ SCL00/(TI07)/ (TO07) D P00/TI00/TxD1 P20/ANI0/ AVREFP P24/ANI4 P147/ANI18 E P01/TO00/RxD1 4 P21/ANI1/ AVREFM 3 P23/ANI3 2 P25/ANI5 1 F Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 21 of 194 RL78/G13 1.3.7 40-pin products • 40-pin plastic HWQFN (6 × 6 mm, 0.5 mm pitch) 1. OUTLINE P147/ANI18 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1 P00/TI00/TxD1 P120/ANI19 INDEX MARK 30 29 28 27 26 25 24 23 22 21 31 20 32 exposed die pad 19 33 18 34 17 35 16 36 15 37 14 38 13 39 12 40 11 1 2 3 4 5 6 7 8 9 10 P50/INTP1/SI11/SDA11 P30/INTP3/RTC1HZ/SCK11/SCL11 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0 P62 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. 3. It is recommended to connect an exposed die pad to Vss. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 22 of 194 RL78/G13 1.3.8 44-pin products • 44-pin plastic LQFP (10 × 10 mm, 0.8 mm pitch) 1. OUTLINE P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1 P00/TI00/TxD1 P120/ANI19 33 32 31 30 29 28 27 26 25 24 23 34 22 35 21 36 20 37 19 38 18 39 17 40 16 41 15 42 14 43 13 44 12 1 2 3 4 5 6 7 8 9 10 11 P50/INTP1/SI11/SDA11 P30/INTP3/RTC1HZ/SCK11/SCL11 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0 P63 P62 P61/SDAA0 P60/SCLA0 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 23 of 194 RL78/G13 1.3.9 48-pin products • 48-pin plastic LFQFP (7 × 7 mm, 0.5 mm pitch) 1. OUTLINE P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P120/ANI19 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4/(PCLBUZ0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK11/SCL11 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 24 of 194 RL78/G13 • 48-pin plastic HWQFN (7 × 7 mm, 0.5 mm pitch) 1. OUTLINE P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P120/ANI19 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD INDEX MARK 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 exposed die pad 23 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4/(PCLBUZ0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK11/SCL11 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. 3. It is recommended to connect an exposed die pad to Vss. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 25 of 194 RL78/G13 1.3.10 52-pin products • 52-pin plastic LQFP (10 × 10 mm, 0.65 mm pitch) 1. OUTLINE P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/RTC1HZ/SCK11/SCL11 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P03/ANI16/RxD1 P02/ANI17/TxD1 P01/TO00 P00/TI00 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 25 42 24 43 23 44 22 45 21 46 20 47 19 48 18 49 17 50 16 51 15 52 14 1 2 3 4 5 6 7 8 9 10 11 12 13 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P31/TI03/TO03/INTP4/(PCLBUZ0) P63 P62 P61/SDAA0 P60/SCLA0 P140/PCLBUZ0/INTP6 P120/ANI19 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 26 of 194 RL78/G13 1.3.11 64-pin products • 64-pin plastic LQFP (12 × 12 mm, 0.65 mm pitch) • 64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch) 1. OUTLINE P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P55/(PCLBUZ1)/(SCK00) P54 P53/(INTP11) P52/(INTP10) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 12345 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 6 7 8 9 10 11 12 13 14 15 16 P30/INTP3/RTC1HZ/SCK11/SCL11 P05/TI05/TO05 P06/TI06/TO06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P31/TI03/TO03/INTP4/(PCLBUZ0) P63 P62 P61/SDAA0 P60/SCLA0 P120/ANI19 P43 P42/TI04/TO04 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 Cautions 1. Make EVSS0 pin the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 27 of 194 RL78/G13 • 64-pin plastic VFBGA (4 × 4 mm, 0.4 mm pitch) Top View Bottom View 1. OUTLINE 8 7 6 5 4 3 2 1 A B CDE F GH H G FED CBA Index mark Pin No. Name A1 P05/TI05/TO05 A2 P30/INTP3/RTC1HZ /SCK11/SCL11 A3 P70/KR0/SCK21 /SCL21 A4 P75/KR5/INTP9 /SCK01/SCL01 A5 P77/KR7/INTP11/ (TxD2) A6 P61/SDAA0 A7 P60/SCLA0 A8 EVDD0 B1 P50/INTP1/SI11 /SDA11 B2 P72/KR2/SO21 B3 P73/KR3/SO01 B4 P76/KR6/INTP10/ (RxD2) B5 P31/TI03/TO03 /INTP4/(PCLBUZ0) B6 P62 B7 VDD B8 EVSS0 Pin No. Name Pin No. Name Pin No. Name C1 P51/INTP2/SO11 E1 P13/TxD2/SO20/ G1 P146 (SDAA0)/(TI04)/(TO04) C2 P71/KR1/SI21/SDA21 E2 P14/RxD2/SI20/SDA20 G2 P25/ANI5 /(SCLA0)/(TI03)/(TO03) C3 P74/KR4/INTP8/SI01 E3 P15/SCK20/SCL20/ G3 P24/ANI4 /SDA01 (TI02)/(TO02) C4 P52/(INTP10) E4 P16/TI01/TO01/INTP5 G4 P22/ANI2 /(SI00)/(RxD0) C5 P53/(INTP11) E5 P03/ANI16/SI10/RxD1 G5 P130 /SDA10 C6 P63 E6 P41/TI07/TO07 G6 P02/ANI17/SO10/TxD1 C7 VSS E7 RESET G7 P00/TI00 C8 P121/X1 E8 P137/INTP0 G8 P124/XT2/EXCLKS D1 P55/(PCLBUZ1)/ (SCK00) F1 P10/SCK00/SCL00/ H1 P147/ANI18 (TI07)/(TO07) D2 P06/TI06/TO06 F2 P11/SI00/RxD0 H2 P27/ANI7 /TOOLRxD/SDA00/ (TI06)/(TO06) D3 P17/TI02/TO02/ (SO00)/(TxD0) F3 P12/SO00/TxD0 H3 P26/ANI6 /TOOLTxD/(INTP5)/ (TI05)/(TO05) D4 P54 F4 P21/ANI1/AVREFM H4 P23/ANI3 D5 P42/TI04/TO04 F5 P04/SCK10/SCL10 H5 P20/ANI0/AVREFP D6 P40/TOOL0 D7 REGC D8 P122/X2/EXCLK F6 P43 F7 P01/TO00 F8 P123/XT1 H6 P141/PCLBUZ1/INTP7 H7 P140/PCLBUZ0/INTP6 H8 P120/ANI19 Cautions 1. Make EVSS0 pin the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 28 of 194 RL78/G13 1.3.12 80-pin products • 80-pin plastic LQFP (14 × 14 mm, 0.65 mm pitch) • 80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch) 1. OUTLINE P153/ANI11 P100/ANI20 P147/ANI18 P146 P111/(INTP11) P110/(INTP10) P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P142/SCK30/SCL30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 39 63 38 64 37 65 36 66 35 67 34 68 33 69 32 70 31 71 30 72 29 73 28 74 27 75 26 76 25 77 24 78 23 79 22 80 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P30/INTP3/RTC1HZ/SCK11/SCL11 P05/TI05/TO05 P06/TI06/TO06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0) P63/SDAA1 P62/SCLA1 P61/SDAA0 P60/SCLA0 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 Cautions 1. Make EVSS0 pin the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 29 of 194 RL78/G13 1.3.13 100-pin products • 100-pin plastic LQFP (14 × 14 mm, 0.65 mm pitch) 1. OUTLINE P100/ANI20 P147/ANI18 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO11 P50/SI11/SDA11 EVDD1 P30/INTP3/RTC1HZ/SCK11/SCL11 P87/(INTP9) P156/ANI14 P155/ANI13 P154/ANI12 P153/ANI11 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P102/TI06/TO06 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P145/TI07/TO07 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 87 39 88 38 89 37 90 36 91 35 92 34 93 33 94 32 95 31 96 30 97 29 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P86/(INTP8) P85/(INTP7) P84/(INTP6) P83 P82/(SO10)/(TXD1) P81/(SI10)/(RXD1)/(SDA10) P80/(SCK10)/(SCL10) EVSS1 P05 P06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0) P63/SDAA1 P62/SCLA1 P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 P60/SCLA0 P61/SDAA0 Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1). 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 30 of 194 RL78/G13 • 100-pin plastic LQFP (14 × 20 mm, 0.65 mm pitch) 1. OUTLINE P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P142/SCK30/SCL30 P143/SI30/RxD3/SDA30 P144/SO30/TxD3 P145/TI07/TO07 P00/TI00 P01/TO00 P02/ANI17/SO10/TxD1 P03/ANI16/SI10/RxD1/SDA10 P04/SCK10/SCL10 P102/TI06/TO06 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P150/ANI8 P151/ANI9 P152/ANI10 P153/ANI11 P154/ANI12 P155/ANI13 P156/ANI14 P100/ANI20 P147/ANI18 P120/ANI19 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 50 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 90 41 91 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO11 P50/SI11/SDA11 P60/SCLA0 P61/SDAA0 P62/SCLA1 P63/SDAA1 P31/TI03/TO03/INTP4/(PCLBUZ0) P64/TI10/TO10 P65/TI11/TO11 P66/TI12/TO12 P67/TI13/TO13 P77/KR7/INTP11/(TXD2) P76/KR6/INTP10/(RXD2) P75/KR5/INTP9 P74/KR4/INTP8 P73/KR3 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P06 P05 EVSS1 P80/(SCK10)/(SCL10) P81/(SI10)/(RXD1)/(SDA10) P82/(SO10)/(TXD1) P83 P84/(INTP6) P85/(INTP7) P86/(INTP8) P87/(INTP9) P30/INTP3/RTC1HZ/SCK11/SCL11 EVDD1 Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1). 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 31 of 194 RL78/G13 1.3.14 128-pin products • 128-pin plastic LFQFP (14 × 20 mm, 0.5 mm pitch) 1. OUTLINE P100/ANI20 P147/ANI18 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P117/ANI24 P116/ANI25 P115/ANI26 P114 P113 P112 P97/SO11 P96/SI11/SDA11 P95/SCK11/SCL11 P94 P93 P92 P91 P90 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51 P50 P30/INTP3/RTC1HZ P87/(INTP9) P156/ANI14 P155/ANI13 P154/ANI12 P153/ANI11 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P102/TI06/TO06 P07 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P145/TI07/TO07 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 64 104 63 105 62 106 61 107 60 108 59 109 58 110 57 111 56 112 55 113 54 114 53 115 52 116 51 117 50 118 49 119 48 120 47 121 46 122 45 123 44 124 43 125 42 126 41 127 40 128 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P86/(INTP8) P85/(INTP7) P84/(INTP6) P83 P82/(SO10)/(TXD1) P81/(SI10)/(RXD1)/(SDA10) P80/(SCK10)/(SCL10) EVDD1 EVSS1 P05 P06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0) P63/SDAA1 P62/SCLA1 P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19 P37/ANI21 P36/ANI22 P35/ANI23 P34 P33 P32 P106/TI17/TO17 P105/TI16/TO16 P104/TI15/TO15 P103/TI14/TO14 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 P127 P126 P125 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 P60/SCLA0 P61/SDAA0 Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1). 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 32 of 194 RL78/G13 1.4 Pin Identification 1. OUTLINE ANI0 to ANI14, REGC: Regulator capacitance ANI16 to ANI26: Analog input RESET: Reset AVREFM: A/D converter reference RTC1HZ: Real-time clock correction clock potential (− side) input (1 Hz) output AVREFP: A/D converter reference RxD0 to RxD3: Receive data potential (+ side) input SCK00, SCK01, SCK10, EVDD0, EVDD1: Power supply for port SCK11, SCK20, SCK21, EVSS0, EVSS1: Ground for port SCLA0, SCLA1: Serial clock input/output EXCLK: External clock input (Main SCLA0, SCLA1, SCL00, system clock) SCL01, SCL10, SCL11, EXCLKS: External clock input SCL20,SCL21, SCL30, (Subsystem clock) SCL31: Serial clock output INTP0 to INTP11: Interrupt request from SDAA0, SDAA1, SDA00, peripheral SDA01,SDA10, SDA11, KR0 to KR7: Key return SDA20,SDA21, SDA30, P00 to P07: Port 0 SDA31: Serial data input/output P10 to P17: Port 1 SI00, SI01, SI10, SI11, P20 to P27: Port 2 SI20, SI21, SI30, SI31: Serial data input P30 to P37: Port 3 SO00, SO01, SO10, P40 to P47: Port 4 SO11, SO20, SO21, P50 to P57: Port 5 SO30, SO31: Serial data output P60 to P67: Port 6 TI00 to TI07, P70 to P77: Port 7 TI10 to TI17: Timer input P80 to P87: Port 8 TO00 to TO07, P90 to P97: Port 9 TO10 to TO17: Timer output P100 to P106: Port 10 TOOL0: Data input/output for tool P110 to P117: Port 11 TOOLRxD, TOOLTxD: Data input/output for external device P120 to P127: Port 12 TxD0 to TxD3: Transmit data P130, P137: Port 13 VDD: Power supply P140 to P147: Port 14 VSS: Ground P150 to P156: Port 15 X1, X2: Crystal oscillator (main system clock) PCLBUZ0, PCLBUZ1: Programmable clock XT1, XT2: Crystal oscillator (subsystem clock) output/buzzer output R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 33 of 194 RL78/G13 1.5 Block Diagram 1.5.1 20-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 LOW-SPEED ON-CHIP OSCILLATOR RxD0/P11 TxD0/P12 RxD1/P01 TxD1/P00 SCK00/P10 SI00/P11 SO00/P12 SCK11/P30 SI11/P17 SO11/P16 SCL00/P10 SDA00/P11 SCL11/P30 SDA11/P17 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI11 IIC00 IIC11 1. OUTLINE RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT CRC PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 12 2 P00, P01 5 P10 to P12, P16, P17 3 P20 to P22 P30 P40 2 P121, P122 PORT 13 P137 PORT 14 A/D CONVERTER P147 3 ANI0/P20 to ANI2/P22 3 ANI16/P01, ANI17/P00, ANI18/P147 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL TOOL0/P40 RESET X1/P121 X2/EXCLK/P122 REGC INTP0/P137 INTP3/P30 INTP5/P16 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 34 of 194 RL78/G13 1.5.2 24-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 LOW-SPEED ON-CHIP OSCILLATOR WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK RxD0/P11 TxD0/P12 RxD1/P01 TxD1/P00 SCK00/P10 SI00/P11 SO00/P12 SCK11/P30 SI11/P50 SO11/P17 SCL00/P10 SDA00/P11 SCL11/P30 SDA11/P50 SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI11 IIC00 IIC11 DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL INTERFACE IICA0 BUZZER OUTPUT CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR SDAA0/P61 SCLA0/P60 PCLBUZ0/P31 CRC 1. OUTLINE PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 2 P00, P01 5 P10 to P12, P16, P17 3 P20 to P22 2 P30, P31 P40 P50 PORT 6 2 P60, P61 PORT 12 2 P121, P122 PORT 13 P137 PORT 14 P147 A/D CONVERTER 3 ANI0/P20 to ANI2/P22 3 ANI16/P01, ANI17/P00, ANI18/P147 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR TOOL0/P40 RESET X1/P121 X2/EXCLK/P122 REGC INTERRUPT CONTROL INTP0/P137 INTP1/P50 INTP3/P30, 2 INTP4/P31 INTP5/P16 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 35 of 194 RL78/G13 1.5.3 25-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 TI03/TO03/P31 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 LOW-SPEED ON-CHIP OSCILLATOR WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK RxD0/P11 TxD0/P12 RxD1/P01 TxD1/P00 SCK00/P10 SI00/P11 SO00/P12 SCK11/P30 SI11/P50 SO11/P17 SCL00/P10 SDA00/P11 SCL11/P30 SDA11/P50 SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI11 IIC00 IIC11 DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL INTERFACE IICA0 BUZZER OUTPUT CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR SDAA0/P61 SCLA0/P60 PCLBUZ0/P31 CRC 1. OUTLINE PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 2 P00, P01 5 P10 to P12, P16, P17 3 P20 to P22 2 P30, P31 P40 P50 PORT 6 2 P60, P61 PORT 12 2 P121, P122 PORT 13 PORT 14 P130 P137 P147 A/D CONVERTER 3 ANI0/P20 to ANI2/P22 3 ANI16/P01, ANI17/P00, ANI18/P147 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR TOOL0/P40 RESET X1/P121 X2/EXCLK/P122 REGC INTERRUPT CONTROL INTP0/P137 INTP1/P50 INTP3/P30, 2 INTP4/P31 INTP5/P16 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 36 of 194 RL78/G13 1.5.4 30-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) (TI07/TO07/P10) RxD2/P14 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 LOW-SPEED ON-CHIP OSCILLATOR RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P01 TxD1/P00 SCK00/P10 SI00/P11 SO00/P12 SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL11/P30 SDA11/P50 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI11 IIC00 IIC11 RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCL20/P15 SDA20/P14 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL CSI20 IIC20 1. OUTLINE PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 12 PORT 13 PORT 14 2 P00, P01 8 P10 to P17 4 P20 to P23 2 P30, P31 P40 2 P50, P51 2 P60, P61 P120 2 P121, P122 P137 P147 RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) BUZZER OUTPUT 2 PCLBUZ0/P31, PCLBUZ1/P15 CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT A/D CONVERTER 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RESET X1/P121 X2/EXCLK/P122 VOLTAGE REGULATOR INTERRUPT CONTROL REGC RxD2/P14 INTP0/P137 INTP1/P50, 2 INTP2/P51 INTP3/P30, 2 INTP4/P31 INTP5/P16 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 37 of 194 RL78/G13 1.5.5 32-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) (TI07/TO07/P10) RxD2/P14 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 LOW-SPEED ON-CHIP OSCILLATOR RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P01 TxD1/P00 SCK00/P10 SI00/P11 SO00/P12 SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL11/P30 SDA11/P50 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI11 IIC00 IIC11 RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCL20/P15 SDA20/P14 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL CSI20 IIC20 1. OUTLINE RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) BUZZER OUTPUT 2 PCLBUZ0/P31, PCLBUZ1/P15 CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT PORT 0 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 4 P20 to P23 PORT 3 2 P30, P31 PORT 4 P40 PORT 5 2 P50, P51 PORT 6 3 P60 to P62 PORT 7 PORT 12 PORT 13 P70 P120 2 P121, P122 P137 PORT 14 P147 A/D CONVERTER 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR RESET X1/P121 X2/EXCLK/P122 VOLTAGE REGULATOR INTERRUPT CONTROL REGC RxD2/P14 INTP0/P137 INTP1/P50, 2 INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 38 of 194 RL78/G13 1.5.6 36-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) (TI07/TO07/P10) RxD2/P14 LOW-SPEED ON-CHIP OSCILLATOR RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P01 TxD1/P00 SCK00/P10 SI00/P11 SO00/P12 SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL11/P30 SDA11/P50 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI11 IIC00 IIC11 RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL CSI20 CSI21 IIC20 IIC21 1. OUTLINE RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) BUZZER OUTPUT CLOCK OUTPUT 2 PCLBUZ0/P31, PCLBUZ1/P15 CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT PORT 0 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 6 P20 to P25 PORT 3 2 P30, P31 PORT 4 PORT 5 P40 2 P50, P51 PORT 6 3 P60 to P62 PORT 7 PORT 12 PORT 13 3 P70 to P72 P120 2 P121, P122 P137 PORT 14 P147 A/D CONVERTER 6 ANI0/P20 to ANI5/P25 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 REGC RxD2/P14 INTP0/P137 INTP1/P50, 2 INTP2/P51 INTP3/P30, 2 INTP4/P31 INTP5/P16 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 39 of 194 RL78/G13 1.5.7 40-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) (TI07/TO07/P10) RxD2/P14 LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P01 TxD1/P00 SCK00/P10 SI00/P11 SO00/P12 SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL11/P30 SDA11/P50 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI11 IIC00 IIC11 RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL CSI20 CSI21 IIC20 IIC21 1. OUTLINE RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) BUZZER OUTPUT CLOCK OUTPUT 2 PCLBUZ0/P31, PCLBUZ1/P15 CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT PORT 0 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 7 P20 to P26 PORT 3 2 P30, P31 PORT 4 P40 PORT 5 2 P50, P51 PORT 6 3 P60 to P62 PORT 7 PORT 12 PORT 13 4 P70 to P73 P120 4 P121 to P124 P137 PORT 14 P147 A/D CONVERTER 7 ANI0/P20 to ANI6/P26 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 KEY RETURN 4 KR0/P70 to KR3/P73 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 REGC RxD2/P14 INTP0/P137 INTP1/P50, 2 INTP2/P51 INTP3/P30, 2 INTP4/P31 INTP5/P16 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 40 of 194 RL78/G13 1.5.8 44-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P01 TxD1/P00 SCK00/P10 SI00/P11 SO00/P12 SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL11/P30 SDA11/P50 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI11 IIC00 IIC11 RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL CSI20 CSI21 IIC20 IIC21 1. OUTLINE RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) BUZZER OUTPUT CLOCK OUTPUT 2 PCLBUZ0/P31, PCLBUZ1/P15 CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT PORT 0 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 PORT 5 2 P40, P41 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 PORT 12 PORT 13 4 P70 to P73 P120 4 P121 to P124 P137 PORT 14 2 P146, P147 A/D CONVERTER 8 ANI0/P20 to ANI7/P27 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 KEY RETURN 4 KR0/P70 to KR3/P73 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 REGC RxD2/P14 INTP0/P137 INTP1/P50, 2 INTP2/P51 INTP3/P30, 2 INTP4/P31 INTP5/P16 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 41 of 194 RL78/G13 1.5.9 48-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P01 TxD1/P00 SCK00/P10 SI00/P11 SO00/P12 SCK01/P75 SI01/P74 SO01/P73 SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL01/P75 SDA01/P74 SCL11/P30 SDA11/P50 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI01 CSI11 IIC00 IIC01 IIC11 RxD2/P14 TxD2/P13 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL CSI20 CSI21 IIC20 IIC21 1. OUTLINE RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 2 (PCLBUZ0/P31), PCLBUZ1/P15 MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT PORT 0 2 P00, P01 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 PORT 5 2 P40, P41 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 6 P70 to P75 PORT 12 PORT 13 PORT 14 P120 4 P121 to P124 P130 P137 3 P140, P146, P147 A/D CONVERTER 8 ANI0/P20 to ANI7/P27 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 KEY RETURN 6 KR0/P70 to KR5/P75 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 REGC RxD2/P14 INTP0/P137 INTP1/P50, 2 INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 INTP6/P140 2 INTP8/P74, INTP9/P75 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 42 of 194 RL78/G13 1.5.10 52-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) (TI04/TO04/P13) (TI05/TO05/P12) (TI06/TO06/P11) TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P03 TxD1/P02 SCK00/P10 SI00/P11 SO00/P12 SCK01/P75 SI01/P74 SO01/P73 SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL01/P75 SDA01/P74 SCL11/P30 SDA11/P50 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI01 CSI11 IIC00 IIC01 IIC11 RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL CSI20 CSI21 IIC20 IIC21 1. OUTLINE RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD VSS TOOLRxD/P11, TOOLTxD/P12 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) BUZZER OUTPUT PCLBUZ0/P140 2 (PCLBUZ0/P31), CLOCK OUTPUT PCLBUZ1/P15 CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT PORT 0 4 P00 to P03 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 PORT 5 2 P40, P41 2 P50, P51 PORT 6 4 P60 to P63 PORT 7 8 P70 to P77 PORT 12 PORT 13 PORT 14 P120 4 P121 to P124 P130 P137 3 P140, P146, P147 A/D CONVERTER 8 ANI0/P20 to ANI7/P27 4 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 KEY RETURN 8 KR0/P70 to KR7/P77 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 REGC RxD2/P14 (RxD2/P76) INTP0/P137 INTP1/P50, 2 INTP2/P51 INTP3/P30, 2 INTP4/P31 INTP5/P16 INTP6/P140 4 INTP8/P74 to INTP11/P77 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 43 of 194 RL78/G13 1.5.11 64-pin products 1. OUTLINE TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) TI04/TO04/P42 (TI04/TO04/P13) TI05/TO05/P05 (TI05/TO05/P12) TI06/TO06/P06 (TI06/TO06/P11) TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P03 TxD1/P02 SCK00/P10(SCK00/P55) SI00/P11(SI00/P16) SO00/P12(SO00/P17) SCK01/P75 SI01/P74 SO01/P73 SCK10/P04 SI10/P03 SO10/P02 SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL01/P75 SDA01/P74 SCL10/P04 SDA10/P03 SCL11/P30 SDA11/P50 RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 TIMER ARRAY UNIT (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI01 CSI10 CSI11 IIC00 IIC01 IIC10 IIC11 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL CSI20 CSI21 IIC20 IIC21 RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD, VSS, TOOLRxD/P11, EVDD0 EVSS0 TOOLTxD/P12 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 2 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT PORT 0 7 P00 to P06 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 PORT 5 4 P40 to P43 6 P50 to P55 PORT 6 4 P60 to P63 PORT 7 8 P70 to P77 PORT 12 PORT 13 PORT 14 P120 4 P121 to P124 P130 P137 4 P140, P141, P146, P147 A/D CONVERTER 8 ANI0/P20 to ANI7/P27 4 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 KEY RETURN 8 KR0/P70 to KR7/P77 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 REGC RxD2/P14 (RxD2/P76) INTP0/P137 INTP1/P50, 2 INTP2/P51 INTP3/P30, 2 INTP4/P31 INTP5/P16(INTP5/P12) INTP6/P140, 2 INTP7/P141 2 INTP8/P74, INTP9/P75 2 INTP10/P76(INTP10/P52), INTP11/P77(INTP11/P53) Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 44 of 194 RL78/G13 1. OUTLINE 1.5.12 80-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) TI04/TO04/P42 (TI04/TO04/P13) TI05/TO05/P05 (TI05/TO05/P12) TI06/TO06/P06 (TI06/TO06/P11) TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P03 TxD1/P02 SCK00/P10(SCK00/P55) SI00/P11(SI00/P16) SO00/P12(SO00/P17) SCK01/P43 SI01/P44 SO01/P45 SCK10/P04 SI10/P03 SO10/P02 SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL01/P43 SDA01/P44 SCL10/P04 SDA10/P03 SCL11/P30 SDA11/P50 RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) RxD3/P143 TxD3/P144 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCK30/P142 SI30/P143 SO30/P144 SCK31/P54 SI31/P53 SO31/P52 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SCL30/P142 SDA30/P143 SCL31/P54 SDA31/P53 TIMER ARRAY UNIT0 (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI01 CSI10 CSI11 IIC00 IIC01 IIC10 IIC11 SERIAL ARRAY UNIT1 (4ch) UART2 LINSEL UART3 CSI20 CSI21 CSI30 CSI31 IIC20 IIC21 IIC30 IIC31 TIMER ARRAY UNIT1 (4ch) ch0 ch1 ch2 ch3 TI10/TO10/P64 TI11/TO11/P65 TI12/TO12/P66 TI13/TO13/P67 A/D CONVERTER 8 ANI0/P20 to ANI7/P27 4 ANI8/P150 to ANI11/P153 5 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 AVREFP/P20 AVREFM/P21 RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD, VSS, TOOLRxD/P11, EVDD0 EVSS0 TOOLTxD/P12 SERIAL INTERFACE IICA0 SERIAL INTERFACE IICA1 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) SDAA1/P63 SCLA1/P62 BUZZER OUTPUT CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR PCLBUZ0/P140 2 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 7 P00 to P06 8 P10 to P17 8 P20 to P27 2 P30, P31 6 P40 to P45 6 P50 to P55 8 P60 to P67 8 P70 to P77 PORT 10 PORT 11 PORT 12 PORT 13 PORT 14 PORT 15 P100 2 P110, P111 P120 4 P121 to P124 P130 P137 7 P140 to P144, P146, P147 4 P150 to P153 KEY RETURN 8 KR0/P70 to KR7/P77 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 REGC RxD2/P14 (RxD2/P76) INTP0/P137 INTP1/P50, 2 INTP2/P51 INTP3/P30, 2 INTP4/P31 INTP5/P16(INTP5/P12) INTP6/P140, 2 INTP7/P141 2 INTP8/P74, INTP9/P75 2 INTP10/P76(INTP10/P110), INTP11/P77(INTP11/P111) Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 45 of 194 RL78/G13 1. OUTLINE 1.5.13 100-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) TI04/TO04/P42 (TI04/TO04/P13) TI05/TO05/P46 (TI05/TO05/P12) TI06/TO06/P102 (TI06/TO06/P11) TI07/TO07/P145 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P03(RxD1/P81) TxD1/P02(TxD1/P82) SCK00/P10(SCK00/P55) SI00/P11(SI00/P16) SO00/P12(SO00/P17) SCK01/P43 SI01/P44 SO01/P45 SCK10/P04(SCK10/P80) SI10/P03(SI10/P81) SO10/P02(SO10/P82) SCK11/P30 SI11/P50 SO11/P51 SCL00/P10 SDA00/P11 SCL01/P43 SDA01/P44 SCL10/P04(SCL10/P80) SDA10/P03(SDA10/P81) SCL11/P30 SDA11/P50 RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) RxD3/P143 TxD3/P144 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCK30/P142 SI30/P143 SO30/P144 SCK31/P54 SI31/P53 SO31/P52 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SCL30/P142 SDA30/P143 SCL31/P54 SDA31/P53 TIMER ARRAY UNIT0 (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI01 CSI10 CSI11 IIC00 IIC01 IIC10 IIC11 SERIAL ARRAY UNIT1 (4ch) UART2 LINSEL UART3 CSI20 CSI21 CSI30 CSI31 IIC20 IIC21 IIC30 IIC31 TIMER ARRAY UNIT1 (4ch) ch0 ch1 ch2 ch3 TI10/TO10/P64 TI11/TO11/P65 TI12/TO12/P66 TI13/TO13/P67 A/D CONVERTER 8 ANI0/P20 to ANI7/P27 7 ANI8/P150 to ANI14/P156 5 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 AVREFP/P20 AVREFM/P21 RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD, VSS, TOOLRxD/P11, EVDD0, EVSS0, TOOLTxD/P12 EVDD1 EVSS1 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) SERIAL INTERFACE IICA1 SDAA1/P63 SCLA1/P62 BUZZER OUTPUT CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR PCLBUZ0/P140 2 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 8 7 P00 to P06 8 P10 to P17 8 P20 to P27 2 P30, P31 8 P40 to P47 8 P50 to P57 8 P60 to P67 8 P70 to P77 8 P80 to P87 PORT 10 PORT 11 PORT 12 PORT 13 PORT 14 PORT 15 3 P100 to P102 2 P110, P111 P120 4 P121 to P124 P130 P137 8 P140 to P147 7 P150 to P156 KEY RETURN 8 KR0/P70 to KR7/P77 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 REGC RxD2/P14 (RxD2/P76) INTP0/P137 INTP1/P46(INTP1/P56), 2 INTP2/P47 INTP3/P30(INTP3/P57), 2 INTP4/P31(INTP4/P146) INTP5/P16(INTP5/P12) 2 INTP6/P140(INTP6/P84), INTP7/P141(INTP7/P85) 2 INTP8/P74(INTP8/P86), INTP9/P75(INTP9/P87) 2 INTP10/P76(INTP10/P110), INTP11/P77(INTP11/P111) Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 46 of 194 RL78/G13 1. OUTLINE 1.5.14 128-pin products TI00/P00 TO00/P01 TI01/TO01/P16 TI02/TO02/P17 (TI02/TO02/P15) TI03/TO03/P31 (TI03/TO03/P14) TI04/TO04/P42 (TI04/TO04/P13) TI05/TO05/P46 (TI05/TO05/P12) TI06/TO06/P102 (TI06/TO06/P11) TI07/TO07/P145 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD1/P03(RxD1/P81) TxD1/P02(TxD1/P82) SCK00/P10(SCK00/P55) SI00/P11(SI00/P16) SO00/P12(SO00/P17) SCK01/P43 SI01/P44 SO01/P45 SCK10/P04(SCK10/P80) SI10/P03(SI10/P81) SO10/P02(SO10/P82) SCK11/P95 SI11/P96 SO11/P97 SCL00/P10 SDA00/P11 SCL01/P43 SDA01/P44 SCL10/P04(SCL10/P80) SDA10/P03(SDA10/P81) SCL11/P95 SDA11/P96 RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) RxD3/P143 TxD3/P144 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 SCK30/P142 SI30/P143 SO30/P144 SCK31/P54 SI31/P53 SO31/P52 SCL20/P15 SDA20/P14 SCL21/P70 SDA21/P71 SCL30/P142 SDA30/P143 SCL31/P54 SDA31/P53 TIMER ARRAY UNIT0 (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 SERIAL ARRAY UNIT0 (4ch) UART0 UART1 CSI00 CSI01 CSI10 CSI11 IIC00 IIC01 IIC10 IIC11 SERIAL ARRAY UNIT1 (4ch) UART2 LINSEL UART3 CSI20 CSI21 CSI30 CSI31 IIC20 IIC21 IIC30 IIC31 TIMER ARRAY UNIT1 (8ch) ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 TI10/TO10/P64 TI11/TO11/P65 TI12/TO12/P66 TI13/TO13/P67 TI14/TO14/P103 TI15/TO15/P104 TI16/TO16/P105 TI17/TO17/P106 A/D CONVERTER 8 ANI0/P20 to ANI7/P27 7 ANI8/P150 to ANI14/P156 11 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100, ANI21/37, ANI22/P36, ANI23/P35, ANI24/P117, ANI25/P116, ANI26/P115 AVREFP/P20 AVREFM/P21 RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY RAM VDD, VSS, TOOLRxD/P11, EVDD0, EVSS0, TOOLTxD/P12 EVDD1 EVSS1 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) SERIAL INTERFACE IICA1 SDAA1/P63 SCLA1/P62 BUZZER OUTPUT CLOCK OUTPUT CONTROL PCLBUZ0/P140 2 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) MULTIPLIER& DIVIDER, MULITIPLY- ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 WINDOW WATCHDOG TIMER 12-BIT INTERVAL TIMER REAL-TIME CLOCK PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 8 PORT 9 PORT 10 PORT 11 PORT 12 PORT 13 PORT 14 PORT 15 8 P00 to P07 8 P10 to P17 8 P20 to P27 8 P30 to P37 8 P40 to P47 8 P50 to P57 8 P60 to P67 8 P70 to P77 8 P80 to P87 8 P90 to P97 7 P100 to P106 8 P110 to P117 4 P120, P125 to P127 4 P121 to P124 P130 P137 8 P140 to P147 7 P150 to P156 KEY RETURN 8 KR0/P70 to KR7/P77 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RESET CONTROL ON-CHIP DEBUG TOOL0/P40 SYSTEM CONTROL HIGH-SPEED ON-CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 REGC RxD2/P14 (RxD2/P76) INTP0/P137 INTP1/P46 (INTP1/P56), 2 INTP2/P47 INTP3/P30 (INTP3/P57), 2 INTP4/P31 (INTP4/P146) INTP5/P16 (INTP5/P12) INTP6/P140 (INTP6/P84), 2 INTP7/P141 (INTP7/P85) 2 INTP8/P74 (INTP8/P86), INTP9/P75 (INTP9/P87) 2 INTP10/P76 (INTP10/P110), INTP11/P77 (INTP11/P111) Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR) in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 47 of 194 RL78/G13 1. OUTLINE 1.6 Outline of Functions [20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin R5F101Cx R5F100Cx R5F101Bx R5F100Bx R5F101Ax R5F100Ax R5F1018x R5F1008x R5F1017x R5F1007x R5F1016x R5F1006x Code flash memory (KB) 16 to 64 16 to 64 16 to 64 16 to 128 16 to 128 16 to 128 Data flash memory (KB) RAM (KB) 4 − 2 to 4Note1 4 − 2 to 4Note1 4 − 2 to 4Note1 4 to 8 − 2 to 12Note1 4 to 8 − 2 to 12Note1 4 to 8 − 2 to 12Note1 Address space 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip oscillator HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock − Low-speed on-chip oscillator 15 kHz (TYP.) General-purpose registers (8-bit register × 8) × 4 banks Minimum instruction execution time 0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation) 0.05 μs (High-speed system clock: fMX = 20 MHz operation) Instruction set • Data transfer (8/16 bits) • Adder and subtractor/logical operation (8/16 bits) • Multiplication (8 bits × 8 bits) • Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 16 20 21 26 28 32 CMOS I/O CMOS input 13 (N-ch O.D. I/O [VDD withstand voltage]: 5) 3 15 (N-ch O.D. I/O [VDD withstand voltage]: 6) 3 15 (N-ch O.D. I/O [VDD withstand voltage]: 6) 3 21 (N-ch O.D. I/O [VDD withstand voltage]: 9) 3 22 (N-ch O.D. I/O [VDD withstand voltage]: 9) 3 26 (N-ch O.D. I/O [VDD withstand voltage]: 10) 3 CMOS output − − 1 − − − N-ch O.D. I/O − 2 2 2 3 3 (withstand voltage: 6 V) Timer 16-bit timer 8 channels Watchdog timer Real-time clock (RTC) 1 channel 1 channel Note 2 12-bit interval timer (IT) Timer output 3 channels (PWM outputs: 2 Note 3) 4 channels (PWM outputs: 3 Note 3) 1 channel 4 channels (PWM outputs: 3 Note 3), 8 channels (PWM outputs: 7 Note 3) Note 4 Notes 1. 2. 3. 4. RTC output − In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/G13 User’s Manual Hardware) Only the constant-period interrupt function when the low-speed on-chip oscillator clock (fIL) is selected The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). (6.9.3 Operation as multiple PWM output function in the RL78/G13 User’s Manual Hardware) When setting to PIOR = 1 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 48 of 194 R5F101Cx R5F100Cx R5F101Bx R5F100Bx R5F101Ax R5F100Ax R5F1018x R5F1008x R5F1017x R5F1007x R5F1016x R5F1006x RL78/G13 Item 20-pin 24-pin 25-pin 30-pin 1. OUTLINE 32-pin (2/2) 36-pin Clock output/buzzer output − 1 1 2 2 2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) 8/10-bit resolution A/D converter 6 channels 6 channels 6 channels 8 channels 8 channels 8 channels Serial interface [20-pin, 24-pin, 25-pin products] • CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel • CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel [30-pin, 32-pin products] • CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel • CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel • CSI: 1 channel/simplified I2C: 1 channel/UART (UART supporting LIN-bus): 1 channel I2C bus [36-pin products] • CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel • CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel • CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel − 1 channel 1 channel 1 channel 1 channel 1 channel Multiplier and divider/multiplyaccumulator • 16 bits × 16 bits = 32 bits (Unsigned or signed) • 32 bits ÷ 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 2 channels Vectored interrupt Internal sources External 23 24 24 27 27 27 3 5 5 6 6 6 Key interrupt − Reset • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 V (TYP.) • Power-down-reset: 1.50 V (TYP.) Voltage detector • Rising edge : • Falling edge : 1.67 V to 4.06 V (14 stages) 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = 40 to +85°C (A: Consumer applications, D: Industrial applications ) TA = 40 to +105°C (G: Industrial applications) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 49 of 194 RL78/G13 1. OUTLINE [40-pin, 44-pin, 48-pin, 52-pin, 64-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 40-pin 44-pin 48-pin 52-pin 64-pin R5F101Lx R5F100Lx R5F101Jx R5F100Jx R5F101Gx R5F100Gx R5F101Fx R5F100Fx R5F101Ex R5F100Ex Code flash memory (KB) 16 to 192 16 to 512 16 to 512 32 to 512 32 to 512 Data flash memory (KB) RAM (KB) 4 to 8 − 2 to 16Note1 4 to 8 − 2 to 32Note1 4 to 8 − 2 to 32Note1 4 to 8 − 2 to 32Note1 4 to 8 − 2 to 32Note1 Address space 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip oscillator HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator 15 kHz (TYP.) General-purpose registers (8-bit register × 8) × 4 banks Minimum instruction execution time 0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation) 0.05 μs (High-speed system clock: fMX = 20 MHz operation) 30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits) • Adder and subtractor/logical operation (8/16 bits) • Multiplication (8 bits × 8 bits) • Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 36 40 44 48 58 CMOS I/O 28 (N-ch O.D. I/O [VDD withstand voltage]: 10) 31 (N-ch O.D. I/O [VDD withstand voltage]: 10) 34 (N-ch O.D. I/O [VDD withstand voltage]: 11) 38 (N-ch O.D. I/O [VDD withstand voltage]: 13) 48 (N-ch O.D. I/O [VDD withstand voltage]: 15) CMOS input 5 5 5 5 5 CMOS output − − 1 1 1 N-ch O.D. I/O 3 4 4 4 4 (withstand voltage: 6 V) Timer 16-bit timer 8 channels Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer (IT) Timer output 4 channels (PWM outputs: 3 Note 2), 8 channels (PWM outputs: 7 Note 2)Note 3 1 channel 5 channels (PWM outputs: 4 Note 2), 8 channels (PWM outputs: 7 Note 2) Note 3 8 channels (PWM outputs: 7 Note 2) RTC output 1 channel • 1 Hz (subsystem clock: fSUB = 32.768 kHz) Notes 1. 2. 3. In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/G13 User’s Manual Hardware) In the case of the 20 KB, this is about 19 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/G13 User’s Manual Hardware) In the case of the 32 KB, this is about 31 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/G13 User’s Manual Hardware) The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves) . (6.9.3 Operation as multiple PWM output function in the RL78/G13 User’s Manual Hardware) When setting to PIOR = 1 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 50 of 194 RL78/G13 Item 40-pin 44-pin 48-pin 52-pin 1. OUTLINE (2/2) 64-pin R5F101Lx R5F100Lx R5F101Jx R5F100Jx R5F101Gx R5F100Gx R5F101Fx R5F100Fx R5F101Ex R5F100Ex Clock output/buzzer output 2 2 2 2 2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 9 channels 10 channels 10 channels 12 channels 12 channels Serial interface I2C bus [40-pin, 44-pin products] • CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel • CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel • CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel [48-pin, 52-pin products] • CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel • CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel • CSI: 2 channels/simplified I2C: 2 channesl/UART (UART supporting LIN-bus): 1 channel [64-pin products] • CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel • CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel • CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel Multiplier and divider/multiplyaccumulator • 16 bits × 16 bits = 32 bits (Unsigned or signed) • 32 bits ÷ 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 2 channels Vectored Internal 27 27 27 27 27 interrupt sources External 7 7 10 12 13 Key interrupt 4 4 6 8 8 Reset • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 V (TYP.) • Power-down-reset: 1.50 V (TYP.) Voltage detector • Rising edge : • Falling edge : 1.67 V to 4.06 V (14 stages) 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = 40 to +85°C (A: Consumer applications, D: Industrial applications ) TA = 40 to +105°C (G: Industrial applications) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 51 of 194 RL78/G13 1. OUTLINE [80-pin, 100-pin, 128-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 80-pin 100-pin 128-pin R5F100Mx R5F101Mx R5F100Px R5F101Px R5F100Sx R5F101Sx Code flash memory (KB) 96 to 512 96 to 512 192 to 512 Data flash memory (KB) RAM (KB) 8 − 8 to 32 Note 1 8 − 8 to 32 Note 1 8 − 16 to 32 Note 1 Address space 1 MB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) clock clock 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip oscillator HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz Low-speed on-chip oscillator 15 kHz (TYP.) General-purpose register (8-bit register × 8) × 4 banks Minimum instruction execution time 0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation) 0.05 μs (High-speed system clock: fMX = 20 MHz operation) 30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation) Instruction set • Data transfer (8/16 bits) • Adder and subtractor/logical operation (8/16 bits) • Multiplication (8 bits × 8 bits) • Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. I/O port Total 74 92 120 CMOS I/O 64 82 110 (N-ch O.D. I/O [EVDD withstand (N-ch O.D. I/O [EVDD withstand (N-ch O.D. I/O [EVDD withstand voltage]: 21) voltage]: 24) voltage]: 25) CMOS input 5 5 5 CMOS output 1 1 1 N-ch O.D. I/O 4 4 4 (withstand voltage: 6 V) Timer 16-bit timer 12 channels 12 channels 16 channels Watchdog timer 1 channel 1 channel 1 channel Real-time clock (RTC) 1 channel 1 channel 1 channel 12-bit interval timer (IT) 1 channel 1 channel 1 channel Timer output 12 channels (PWM outputs: 10 Note 2) 12 channels (PWM outputs: 10 Note 2) 16 channels (PWM outputs: 14 Note 2) RTC output 1 channel • 1 Hz (subsystem clock: fSUB = 32.768 kHz) Notes 1. 2. In the case of the 20 KB, this is about 19 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/G13 User’s Manual Hardware) In the case of the 32 KB, this is about 31 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3 in the RL78/G13 User’s Manual Hardware) The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves) . (6.9.3 Operation as multiple PWM output function in the RL78/G13 User’s Manual Hardware) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 52 of 194 RL78/G13 1. OUTLINE (2/2) Item 80-pin 100-pin 128-pin R5F100Mx R5F101Mx R5F100Px R5F101Px R5F100Sx R5F101Sx Clock output/buzzer output 2 2 2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 17 channels 20 channels 26 channels Serial interface I2C bus [80-pin, 100-pin, 128-pin products] • CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel • CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel • CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel • CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel 2 channels 2 channels 2 channels Multiplier and divider/multiplyaccumulator • 16 bits × 16 bits = 32 bits (Unsigned or signed) • 32 bits ÷ 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 4 channels Vectored Internal 37 37 41 interrupt sources External 13 13 13 Key interrupt 8 8 8 Reset • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 V (TYP.) • Power-down-reset: 1.50 V (TYP.) Voltage detector • Rising edge : • Falling edge : 1.67 V to 4.06 V (14 stages) 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = 40 to +85°C (A: Consumer applications, D: Industrial applications ) TA = 40 to +105°C (G: Industrial applications) Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 53 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) This chapter describes the electrical specifications for the products "A: Consumer applications (TA = -40 to +85°C)" and "D: Industrial applications (TA = -40 to +85°C)". Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. 3. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 With functions for each product in the RL78/G13 User’s Manual Hardware. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 54 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Symbols Conditions Ratings Unit Supply voltage VDD −0.5 to +6.5 V EVDD0, EVDD1 EVDD0 = EVDD1 −0.5 to +6.5 V EVSS0, EVSS1 EVSS0 = EVSS1 −0.5 to +0.3 V REGC pin input voltage VIREGC REGC −0.3 to +2.8 V and −0.3 to VDD +0.3Note 1 Input voltage VI1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, −0.3 to EVDD0 +0.3 V P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, and −0.3 to VDD +0.3Note 2 P125 to P127, P140 to P147 VI2 P60 to P63 (N-ch open-drain) −0.3 to +6.5 V VI3 P20 to P27, P121 to P124, P137, P150 to P156, −0.3 to VDD +0.3Note 2 V EXCLK, EXCLKS, RESET Output voltage VO1 VO2 P00 to P07, P10 to P17, P30 to P37, P40 to P47, −0.3 to EVDD0 +0.3 V P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, and −0.3 to VDD +0.3 Note 2 P125 to P127, P130, P140 to P147 P20 to P27, P150 to P156 −0.3 to VDD +0.3 Note 2 V Analog input voltage VAI1 ANI16 to ANI26 −0.3 to EVDD0 +0.3 V and −0.3 to AVREF(+) +0.3Notes 2, 3 VAI2 ANI0 to ANI14 −0.3 to VDD +0.3 V and −0.3 to AVREF(+) +0.3Notes 2, 3 Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. 2. 3. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. AVREF (+) : + side reference voltage of the A/D converter. VSS : Reference voltage R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 55 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Symbols Conditions Ratings Unit Output current, high IOH1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 −40 mA Total of all pins P00 to P04, P07, P32 to P37, −70 mA −170 mA P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 P05, P06, P10 to P17, P30, P31, −100 mA P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 IOH2 Per pin P20 to P27, P150 to P156 −0.5 mA Total of all pins −2 mA Output current, low IOL1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 40 mA Total of all pins P00 to P04, P07, P32 to P37, 70 mA 170 mA P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 P05, P06, P10 to P17, P30, P31, 100 mA P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 IOL2 Per pin P20 to P27, P150 to P156 1 mA Total of all pins 5 mA Operating ambient TA temperature In normal operation mode In flash memory programming mode −40 to +85 °C Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 56 of 194 RL78/G13 2.2 Oscillator Characteristics 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.2.1 X1, XT1 oscillator characteristics (TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter X1 clock oscillation frequency (fX)Note Resonator Ceramic resonator/ crystal resonator XT1 clock oscillation Crystal resonator frequency (fX)Note Conditions 2.7 V ≤ VDD ≤ 5.5 V 2.4 V ≤ VDD < 2.7 V 1.8 V ≤ VDD < 2.4 V 1.6 V ≤ VDD < 1.8 V MIN. 1.0 1.0 1.0 1.0 32 TYP. 32.768 MAX. 20.0 16.0 8.0 4.0 35 Unit MHz MHz MHz MHz kHz Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator in the RL78/G13 User’s Manual Hardware. 2.2.2 On-chip oscillator characteristics (TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator fIH clock frequency Notes 1, 2 1 32 MHz High-speed on-chip oscillator clock frequency accuracy −20 to +85 °C 1.8 V ≤ VDD ≤ 5.5 V 1.6 V ≤ VDD < 1.8 V −1.0 +1.0 % −5.0 +5.0 % −40 to −20 °C 1.8 V ≤ VDD ≤ 5.5 V −1.5 +1.5 % 1.6 V ≤ VDD < 1.8 V −5.5 +5.5 % Low-speed on-chip oscillator fIL clock frequency 15 kHz Low-speed on-chip oscillator clock frequency accuracy −15 +15 % Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 57 of 194 RL78/G13 2.3 DC Characteristics 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.3.1 Pin characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, IOH1 highNote 1 Per pin for P00 to P07, P10 to P17, 1.6 V ≤ EVDD0 ≤ 5.5 V P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 −10.0 mA Note 2 Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 < 4.0 V 1.8 V ≤ EVDD0 < 2.7 V 1.6 V ≤ EVDD0 < 1.8 V −55.0 mA −10.0 mA −5.0 mA −2.5 mA Total of P05, P06, P10 to P17, P30, P31, 4.0 V ≤ EVDD0 ≤ 5.5 V P50 to P57, P64 to P67, P70 to P77, P80 2.7 V ≤ EVDD0 < 4.0 V to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 1.8 V ≤ EVDD0 < 2.7 V (When duty ≤ 70% Note 3) 1.6 V ≤ EVDD0 < 1.8 V −80.0 mA −19.0 mA −10.0 mA −5.0 mA Total of all pins (When duty ≤ 70% Note 3) 1.6 V ≤ EVDD0 ≤ 5.5 V IOH2 Per pin for P20 to P27, P150 to P156 1.6 V ≤ VDD ≤ 5.5 V −135.0 mA Note 4 −0.1Note mA 2 Total of all pins (When duty ≤ 70% Note 3) 1.6 V ≤ VDD ≤ 5.5 V −1.5 mA Notes 1. 2. 3. 4. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to an output pin. However, do not exceed the total current value. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (IOH × 0.7)/(n × 0.01) Where n = 80% and IOH = −10.0 mA Total output current of pins = (−10.0 × 0.7)/(80 × 0.01) ≅ −8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. The applied current for the products for industrial application (R5F100xxDxx, R5F101xxDxx) is −100 mA. Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 58 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5) Items Output current, lowNote 1 Symbol IOL1 Conditions Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 Per pin for P60 to P63 Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 < 4.0 V 1.8 V ≤ EVDD0 < 2.7 V 1.6 V ≤ EVDD0 < 1.8 V Total of P05, P06, P10 to P17, P30, 4.0 V ≤ EVDD0 ≤ 5.5 V P31, P50 to P57, P60 to P67, 2.7 V ≤ EVDD0 < 4.0 V P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, 1.8 V ≤ EVDD0 < 2.7 V P147 (When duty ≤ 70% Note 3) 1.6 V ≤ EVDD0 < 1.8 V MIN. TYP. MAX. Unit 20.0 Note 2 mA 15.0 Note 2 mA 70.0 mA 15.0 mA 9.0 mA 4.5 mA 80.0 mA 35.0 mA 20.0 mA 10.0 mA Total of all pins (When duty ≤ 70% Note 3) IOL2 Per pin for P20 to P27, P150 to P156 Total of all pins (When duty ≤ 70%Note 3) 1.6 V ≤ VDD ≤ 5.5 V 150.0 mA 0.4 Note 2 mA 5.0 mA Notes 1. 2. 3. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0, EVSS1 and VSS pin. However, do not exceed the total current value. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (IOL × 0.7)/(n × 0.01) Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≅ 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 59 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, VIH1 high VIH2 VIH3 VIH4 VIH5 Input voltage, VIL1 low VIL2 VIL3 VIL4 VIL5 P00 to P07, P10 to P17, P30 to P37, Normal input buffer P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 0.8EVDD0 P01, P03, P04, P10, P11, TTL input buffer 2.2 P13 to P17, P43, P44, P53 to P55, 4.0 V ≤ EVDD0 ≤ 5.5 V P80, P81, P142, P143 TTL input buffer 2.0 3.3 V ≤ EVDD0 < 4.0 V TTL input buffer 1.5 1.6 V ≤ EVDD0 < 3.3 V P20 to P27, P150 to P156 0.7VDD P60 to P63 0.7EVDD0 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD P00 to P07, P10 to P17, P30 to P37, Normal input buffer 0 P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 P01, P03, P04, P10, P11, TTL input buffer 0 P13 to P17, P43, P44, P53 to P55, 4.0 V ≤ EVDD0 ≤ 5.5 V P80, P81, P142, P143 TTL input buffer 0 3.3 V ≤ EVDD0 < 4.0 V TTL input buffer 0 1.6 V ≤ EVDD0 < 3.3 V P20 to P27, P150 to P156 0 P60 to P63 0 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 EVDD0 V EVDD0 V EVDD0 V EVDD0 V VDD V 6.0 V VDD V 0.2EVDD0 V 0.8 V 0.5 V 0.32 V 0.3VDD V 0.3EVDD0 V 0.2VDD V Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 60 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, VOH1 high VOH2 Output voltage, VOL1 low VOL2 VOL3 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD0 ≤ 5.5 V, EVDD0 − IOH1 = −10.0 mA 1.5 4.0 V ≤ EVDD0 ≤ 5.5 V, EVDD0 − IOH1 = −3.0 mA 0.7 2.7 V ≤ EVDD0 ≤ 5.5 V, EVDD0 − IOH1 = −2.0 mA 0.6 1.8 V ≤ EVDD0 ≤ 5.5 V, EVDD0 − IOH1 = −1.5 mA 0.5 1.6 V ≤ EVDD0 < 5.5 V, EVDD0 − IOH1 = −1.0 mA 0.5 P20 to P27, P150 to P156 1.6 V ≤ VDD ≤ 5.5 V, VDD − 0.5 IOH2 = −100 μ A P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 20 mA 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 8.5 mA 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 3.0 mA 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 1.5 mA 1.8 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 0.6 mA 1.6 V ≤ EVDD0 < 5.5 V, IOL1 = 0.3 mA P20 to P27, P150 to P156 1.6 V ≤ VDD ≤ 5.5 V, IOL2 = 400 μ A P60 to P63 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 15.0 mA 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 5.0 mA 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 3.0 mA 1.8 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 2.0 mA 1.6 V ≤ EVDD0 < 5.5 V, IOL3 = 1.0 mA V V V V V V 1.3 V 0.7 V 0.6 V 0.4 V 0.4 V 0.4 V 0.4 V 2.0 V 0.4 V 0.4 V 0.4 V 0.4 V Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 61 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage ILIH1 current, high P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 VI = EVDD0 1 μA ILIH2 P20 to P27, P137, P150 to P156, RESET VI = VDD 1 μA ILIH3 P121 to P124 VI = VDD In input port or (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input 1 μA In resonator connection 10 μA Input leakage ILIL1 current, low P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 VI = EVSS0 −1 μA ILIL2 P20 to P27, P137, P150 to P156, RESET VI = VSS −1 μA ILIL3 P121 to P124 VI = VSS In input port or (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input −1 μA In resonator connection −10 μA On-chip pll-up RU resistance P00 to P07, P10 to P17, VI = EVSS0, In input port 10 20 100 kΩ P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 62 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.3.2 Supply current characteristics (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (1/2) Parameter Supply current Note 1 Symbol IDD1 Operating mode HS (high- speed main) mode Note 5 Conditions fIH = 32 MHz Note 3 Basic operation Normal operation fIH = 24 MHz Note 3 Normal operation fIH = 16 MHz Note 3 Normal operation LS (low- speed main) mode Note 5 fIH = 8 MHz Note 3 LV (low- voltage main) mode Note 5 fIH = 4 MHz Note 3 Normal operation Normal operation VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 3.0 V VDD = 2.0 V VDD = 3.0 V VDD = 2.0 V MIN. TYP. MAX. Unit 2.1 mA 2.1 mA 4.6 7.0 mA 4.6 7.0 mA 3.7 5.5 mA 3.7 5.5 mA 2.7 4.0 mA 2.7 4.0 mA 1.2 1.8 mA 1.2 1.8 mA 1.2 1.7 mA 1.2 1.7 mA HS (high- speed main) mode Note 5 fMX = 20 MHzNote 2, VDD = 5.0 V fMX = 20 MHzNote 2, VDD = 3.0 V fMX = 10 MHzNote 2, VDD = 5.0 V fMX = 10 MHzNote 2, VDD = 3.0 V LS (low- fMX = 8 MHzNote 2, speed main) mode Note 5 VDD = 3.0 V fMX = 8 MHzNote 2, VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHz Note 4 TA = −40°C fSUB = 32.768 kHz Note 4 TA = +25°C fSUB = 32.768 kHz Note 4 TA = +50°C fSUB = 32.768 kHz Note 4 TA = +70°C fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection 3.0 4.6 mA 3.2 4.8 mA 3.0 4.6 mA 3.2 4.8 mA 1.9 2.7 mA 1.9 2.7 mA 1.9 2.7 mA 1.9 2.7 mA 1.1 1.7 mA 1.1 1.7 mA 1.1 1.7 mA 1.1 1.7 mA 4.1 4.9 μA 4.2 5.0 μA 4.1 4.9 μA 4.2 5.0 μA 4.2 5.5 μA 4.3 5.6 μA 4.3 6.3 μA 4.4 6.4 μA 4.6 7.7 μA 4.7 7.8 μA (Notes and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 63 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12bit interval timer, and watchdog timer. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 64 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply current Note 1 IDD2 Note 2 HALT mode HS (high- speed main) mode Note 7 fIH = 32 MHz Note 4 fIH = 24 MHz Note 4 VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V 0.54 1.63 mA 0.54 1.63 mA 0.44 1.28 mA fIH = 16 MHz Note 4 VDD = 3.0 V VDD = 5.0 V 0.44 1.28 mA 0.40 1.00 mA LS (low- speed main) mode Note 7 fIH = 8 MHz Note 4 LV (low- voltage main) mode Note 7 fIH = 4 MHz Note 4 VDD = 3.0 V VDD = 3.0 V VDD = 2.0 V VDD = 3.0 V VDD = 2.0 V 0.40 1.00 mA 260 530 μA 260 530 μA 420 640 μA 420 640 μA HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V fMX = 20 MHzNote 3, Square wave input Resonator connection Square wave input VDD = 3.0 V fMX = 10 MHzNote 3, Resonator connection Square wave input VDD = 5.0 V fMX = 10 MHzNote 3, Resonator connection Square wave input VDD = 3.0 V LS (low- speed main) mode Note 7 fMX = 8 MHzNote 3, VDD = 3.0 V fMX = 8 MHzNote 3, Resonator connection Square wave input Resonator connection Square wave input Subsystem clock operation VDD = 2.0 V fSUB = 32.768 kHzNote 5 TA = −40°C fSUB = 32.768 kHzNote 5 Resonator connection Square wave input Resonator connection Square wave input TA = +25°C Resonator connection fSUB = 32.768 kHzNote 5 Square wave input TA = +50°C Resonator connection fSUB = 32.768 kHzNote 5 Square wave input TA = +70°C Resonator connection fSUB = 32.768 kHzNote 5 Square wave input TA = +85°C IDD3Note 6 STOP TA = −40°C modeNote 8 TA = +25°C Resonator connection TA = +50°C TA = +70°C TA = +85°C (Notes and Remarks are listed on the next page.) 0.28 1.00 mA 0.45 1.17 mA 0.28 1.00 mA 0.45 1.17 mA 0.19 0.60 mA 0.26 0.67 mA 0.19 0.60 mA 0.26 0.67 mA 95 330 μA 145 380 μA 95 330 μA 145 380 μA 0.25 0.57 μA 0.44 0.76 μA 0.30 0.57 μA 0.49 0.76 μA 0.37 1.17 μA 0.56 1.36 μA 0.53 1.97 μA 0.72 2.16 μA 0.82 3.37 μA 1.01 3.56 μA 0.18 0.50 μA 0.23 0.50 μA 0.30 1.10 μA 0.46 1.90 μA 0.75 3.30 μA R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 65 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 66 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Supply IDD1 currentNote 1 Operating mode HS (high- speed main) mode Note 5 Conditions fIH = 32 MHz Note 3 fIH = 24 MHz Note 3 fIH = 16 MHz Note 3 LS (lowspeed main) mode Note 5 LV (lowvoltage main) mode Note 5 fIH = 8 MHz Note 3 fIH = 4 MHz Note 3 Basic VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 3.0 V operation VDD = 2.0 V Normal VDD = 3.0 V operation VDD = 2.0 V MIN. TYP. MAX. Unit 2.3 mA 2.3 mA 5.2 8.5 mA 5.2 8.5 mA 4.1 6.6 mA 4.1 6.6 mA 3.0 4.7 mA 3.0 4.7 mA 1.3 2.1 mA 1.3 2.1 mA 1.3 1.8 mA 1.3 1.8 mA HS (highspeed main) mode Note 5 LS (lowspeed main) mode Note 5 Subsystem clock operation fMX = 20 MHzNote 2, VDD = 5.0 V fMX = 20 MHzNote 2, VDD = 3.0 V fMX = 10 MHzNote 2, VDD = 5.0 V fMX = 10 MHzNote 2, VDD = 3.0 V fMX = 8 MHzNote 2, VDD = 3.0 V fMX = 8 MHzNote 2, VDD = 2.0 V fSUB = 32.768 kHz Note 4 TA = −40°C fSUB = 32.768 kHz Note 4 TA = +25°C fSUB = 32.768 kHz Note 4 TA = +50°C fSUB = 32.768 kHz Note 4 TA = +70°C fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection 3.4 5.5 mA 3.6 5.7 mA 3.4 5.5 mA 3.6 5.7 mA 2.1 3.2 mA 2.1 3.2 mA 2.1 3.2 mA 2.1 3.2 mA 1.2 2.0 mA 1.2 2.0 mA 1.2 2.0 mA 1.2 2.0 mA 4.8 5.9 μA 4.9 6.0 μA 4.9 5.9 μA 5.0 6.0 μA 5.0 7.6 μA 5.1 7.7 μA 5.2 9.3 μA 5.3 9.4 μA 5.7 13.3 μA 5.8 13.4 μA (Notes and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 67 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the 12-bit interval timer and watchdog timer. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 68 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Supply current Note 1 IDD2 Note 2 HALT mode HS (high- speed main) mode Note 7 Conditions fIH = 32 MHz Note 4 fIH = 24 MHz Note 4 fIH = 16 MHz Note 4 LS (lowspeed main) mode Note 7 LV (lowvoltage main) mode Note 7 fIH = 8 MHz Note 4 fIH = 4 MHz Note 4 VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 3.0 V VDD = 2.0 V VDD = 3.0 V VDD = 2.0 V MIN. TYP. MAX. Unit 0.62 1.86 mA 0.62 1.86 mA 0.50 1.45 mA 0.50 1.45 mA 0.44 1.11 mA 0.44 1.11 mA 290 620 μA 290 620 μA 440 680 μA 440 680 μA HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V fMX = 20 MHzNote 3, VDD = 3.0 V fMX = 10 MHzNote 3, VDD = 5.0 V fMX = 10 MHzNote 3, VDD = 3.0 V LS (low- speed main) mode Note 7 fMX = 8 MHzNote 3, VDD = 3.0 V fMX = 8 MHzNote 3, VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHzNote 5 TA = −40°C fSUB = 32.768 kHzNote 5 TA = +25°C fSUB = 32.768 kHzNote 5 TA = +50°C fSUB = 32.768 kHzNote 5 TA = +70°C fSUB = 32.768 kHzNote 5 TA = +85°C IDD3Note 6 STOP TA = −40°C modeNote 8 TA = +25°C TA = +50°C TA = +70°C TA = +85°C Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection 0.31 1.08 mA 0.48 1.28 mA 0.31 1.08 mA 0.48 1.28 mA 0.21 0.63 mA 0.28 0.71 mA 0.21 0.63 mA 0.28 0.71 mA 110 360 μA 160 420 μA 110 360 μA 160 420 μA 0.28 0.61 μA 0.47 0.80 μA 0.34 0.61 μA 0.53 0.80 μA 0.41 2.30 μA 0.60 2.49 μA 0.64 4.03 μA 0.83 4.22 μA 1.09 8.04 μA 1.28 8.23 μA 0.19 0.52 μA 0.25 0.52 μA 0.32 2.21 μA 0.55 3.94 μA 1.00 7.95 μA (Notes and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 69 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current . However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 70 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Supply current Note 1 Symbol IDD1 Operating mode HS (high- speed main) mode Note 5 Conditions fIH = 32 MHz Note 3 Basic operation Normal operation fIH = 24 MHz Note 3 Normal operation fIH = 16 MHz Note 3 Normal operation LS (low- speed main) mode Note 5 fIH = 8 MHz Note 3 LV (low- voltage main) mode Note 5 fIH = 4 MHz Note 3 Normal operation Normal operation VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 3.0 V VDD = 2.0 V VDD = 3.0 V VDD = 2.0 V MIN. TYP. MAX. Unit 2.6 mA 2.6 mA 6.1 9.5 mA 6.1 9.5 mA 4.8 7.4 mA 4.8 7.4 mA 3.5 5.3 mA 3.5 5.3 mA 1.5 2.3 mA 1.5 2.3 mA 1.5 2.0 mA 1.5 2.0 mA HS (high- fMX = 20 MHzNote 2, Normal speed main) mode Note 5 VDD = 5.0 V operation fMX = 20 MHzNote 2, Normal VDD = 3.0 V operation fMX = 10 MHzNote 2, Normal VDD = 5.0 V operation fMX = 10 MHzNote 2, Normal VDD = 3.0 V operation LS (low- fMX = 8 MHzNote 2, speed main) mode Note 5 VDD = 3.0 V Normal operation fMX = 8 MHzNote 2, Normal VDD = 2.0 V operation Subsystem clock operation fSUB = 32.768 kHz Note 4 TA = −40°C fSUB = 32.768 kHz Note 4 TA = +25°C fSUB = 32.768 kHz Note 4 TA = +50°C fSUB = 32.768 kHz Note 4 TA = +70°C fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation Normal operation Normal operation Normal operation Normal operation Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection 3.9 6.1 mA 4.1 6.3 mA 3.9 6.1 mA 4.1 6.3 mA 2.5 3.7 mA 2.5 3.7 mA 2.5 3.7 mA 2.5 3.7 mA 1.4 2.2 mA 1.4 2.2 mA 1.4 2.2 mA 1.4 2.2 mA 5.4 6.5 μA 5.5 6.6 μA 5.5 6.5 μA 5.6 6.6 μA 5.6 9.4 μA 5.7 9.5 μA 5.9 12.0 μA 6.0 12.1 μA 6.6 16.3 μA 6.7 16.4 μA (Notes and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 71 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V @1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 72 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Supply current Note 1 IDD2 Note 2 HALT mode HS (high- speed main) mode Note 7 Conditions fIH = 32 MHz Note 4 fIH = 24 MHz Note 4 fIH = 16 MHz Note 4 LS (lowspeed main) mode Note 7 LV (lowvoltage main) mode Note 7 fIH = 8 MHz Note 4 fIH = 4 MHz Note 4 VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 3.0 V VDD = 2.0 V VDD = 3.0 V VDD = 2.0 V MIN. TYP. MAX. Unit 0.62 1.89 mA 0.62 1.89 mA 0.50 1.48 mA 0.50 1.48 mA 0.44 1.12 mA 0.44 1.12 mA 290 620 μA 290 620 μA 460 700 μA 460 700 μA HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V fMX = 20 MHzNote 3, VDD = 3.0 V fMX = 10 MHzNote 3, VDD = 5.0 V fMX = 10 MHzNote 3, VDD = 3.0 V LS (low- speed main) mode Note 7 fMX = 8 MHzNote 3, VDD = 3.0 V fMX = 8 MHzNote 3, VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHzNote 5 TA = −40°C fSUB = 32.768 kHzNote 5 TA = +25°C fSUB = 32.768 kHzNote 5 TA = +50°C fSUB = 32.768 kHzNote 5 TA = +70°C fSUB = 32.768 kHzNote 5 TA = +85°C IDD3Note 6 STOP modeNote 8 TA = −40°C TA = +25°C TA = +50°C TA = +70°C TA = +85°C Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection 0.31 1.14 mA 0.48 1.34 mA 0.31 1.14 mA 0.48 1.34 mA 0.21 0.68 mA 0.28 0.76 mA 0.21 0.68 mA 0.28 0.76 mA 110 390 μA 160 450 μA 110 390 μA 160 450 μA 0.31 0.66 μA 0.50 0.85 μA 0.38 0.66 μA 0.57 0.85 μA 0.47 3.49 μA 0.66 3.68 μA 0.80 6.10 μA 0.99 6.29 μA 1.52 10.46 μA 1.71 10.65 μA 0.19 0.54 μA 0.26 0.54 μA 0.35 3.37 μA 0.68 5.98 μA 1.40 10.34 μA (Notes and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 73 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current . However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V @1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V ≤ VDD ≤ 5.5 V@1 MHz to 4 MHz 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 74 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (4) Peripheral Functions (Common to all products) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Low-speed onchip oscillator operating current RTC operating current Symbol IFILNote 1 I Notes 1, 2, 3 RTC Conditions MIN. TYP. MAX. Unit 0.20 μA 0.02 μA 12-bit interval timer operating current I Notes 1, 2, 4 IT Watchdog timer operating current I Notes 1, 2, 5 WDT A/D converter operating current I Notes 1, 6 ADC A/D converter reference voltage current Temperature sensor operating current LVD operating current Selfprogramming operating current BGO operating current SNOOZE operating current I Note 1 ADREF I Note 1 TMPS I Notes 1, 7 LVD I Notes 1, 9 FSP I Notes 1, 8 BGO I Note 1 SNOZ fIL = 15 kHz When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V Low voltage mode, AVREFP = VDD = 3.0 V ADC operation The mode is performed Note 10 The A/D conversion operations are performed, Low voltage mode, AVREFP = VDD = 3.0 V 0.02 μA 0.22 μA 1.3 1.7 mA 0.5 0.7 mA 75.0 μA 75.0 μA 0.08 μA 2.50 12.20 mA 2.50 12.20 mA 0.50 0.60 mA 1.20 1.44 mA CSI/UART operation 0.70 0.84 mA Notes 1. Current flowing to VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed onchip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 75 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10.For shift time to the SNOOZE mode, see 18.3.3 SNOOZE mode in the RL78/G13 User’s Manual Hardware. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 76 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.4 AC Characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY External system clock fEX frequency fEXS External system clock input tEXH, tEXL high-level width, low-level width tEXHS, tEXLS TI00 to TI07, TI10 to TI17 input tTIH, high-level width, low-level width tTIL TO00 to TO07, TO10 to TO17 fTO output frequency PCLBUZ0, PCLBUZ1 output fPCL frequency Interrupt input high-level width, tINTH, low-level width tINTL Key interrupt input low-level tKR width RESET low-level width tRSL Conditions MIN. Main system clock (fMAIN) operation HS (highspeed main) mode 2.7 V ≤ VDD ≤ 5.5 V 0.03125 2.4 V ≤ VDD < 2.7 V 0.0625 LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V 0.125 main) mode LV (low- 1.6 V ≤ VDD ≤ 5.5 V voltage main) mode 0.25 Subsystem clock (fSUB) 1.8 V ≤ VDD ≤ 5.5 V 28.5 operation In the self HS (high- programming speed main) mode mode 2.7 V ≤ VDD ≤ 5.5 V 0.03125 2.4 V ≤ VDD < 2.7 V 0.0625 LS (low-speed 1.8 V ≤ VDD ≤ 5.5 V 0.125 main) mode LV (low- 1.8 V ≤ VDD ≤ 5.5 V voltage main) mode 0.25 2.7 V ≤ VDD ≤ 5.5 V 1.0 2.4 V ≤ VDD < 2.7 V 1.0 1.8 V ≤ VDD < 2.4 V 1.0 1.6 V ≤ VDD < 1.8 V 1.0 32 2.7 V ≤ VDD ≤ 5.5 V 24 2.4 V ≤ VDD < 2.7 V 30 1.8 V ≤ VDD < 2.4 V 60 1.6 V ≤ VDD < 1.8 V 120 13.7 1/fMCK+10 HS (high-speed main) mode 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 < 4.0 V 1.8 V ≤ EVDD0 < 2.7 V 1.6 V ≤ EVDD0 < 1.8 V LS (low-speed main) mode 1.8 V ≤ EVDD0 ≤ 5.5 V 1.6 V ≤ EVDD0 < 1.8 V LV (low-voltage main) mode 1.6 V ≤ EVDD0 ≤ 5.5 V HS (high-speed main) mode 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 < 4.0 V 1.8 V ≤ EVDD0 < 2.7 V 1.6 V ≤ EVDD0 < 1.8 V LS (low-speed main) mode 1.8 V ≤ EVDD0 ≤ 5.5 V 1.6 V ≤ EVDD0 < 1.8 V LV (low-voltage main) mode 1.8 V ≤ EVDD0 ≤ 5.5 V 1.6 V ≤ EVDD0 < 1.8 V INTP0 1.6 V ≤ VDD ≤ 5.5 V 1 INTP1 to INTP11 1.6 V ≤ EVDD0 ≤ 5.5 V 1 KR0 to KR7 1.8 V ≤ EVDD0 ≤ 5.5 V 250 1.6 V ≤ EVDD0 < 1.8 V 1 10 TYP. 30.5 (Note and Remark are listed on the next page.) MAX. 1 1 1 1 31.3 1 1 1 1 20.0 16.0 8.0 4.0 35 16 8 4 2 4 2 2 16 8 4 2 4 2 4 2 Unit μs μs μs μs μs μs μs μs μs MHz MHz MHz MHz kHz ns ns ns ns μs nsNote MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz μs μs ns μs μs R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 77 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Note The following conditions are required for low voltage interface when EVDD0 < VDD 1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns 1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 Cycle time TCY [µs] 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.03125 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.4 2.7 Supply voltage VDD [V] R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 78 of 194 RL78/G13 10 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) TCY vs VDD (LS (low-speed main) mode) Cycle time TCY [µs] 1.0 0.125 0.1 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.01 0 10 1.0 2.0 3.0 4.0 1.8 Supply voltage VDD [V] 5.0 5.5 6.0 TCY vs VDD (LV (low-voltage main) mode) Cycle time TCY [µs] 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.25 0.1 0.01 0 1.0 2.0 3.0 4.0 1.6 1.8 Supply voltage VDD [V] 5.0 5.5 6.0 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 79 of 194 RL78/G13 AC Timing Test Points VIH/VOH VIL/VOL External System Clock Timing EXCLK/EXCLKS TI/TO Timing TI00 to TI07, TI10 to TI17 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Test points VIH/VOH VIL/VOL tEXL/ tEXLS 1/fEX/ 1/fEXS tEXH/ tEXHS tTIL tTIH TO00 to TO07, TO10 to TO17 Interrupt Request Input Timing INTP0 to INTP11 Key Interrupt Input Timing KR0 to KR7 RESET Input Timing RESET R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 1/fTO tINTL tINTH tKR tRSL Page 80 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIL/VOL Test points VIH/VOH VIL/VOL 2.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode Transfer rate Note 1 2.4 V≤ EVDD0 ≤ 5.5 V MIN. MAX. MIN. MAX. MIN. MAX. fMCK/6 Note 2 fMCK/6 fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.8 V ≤ EVDD0 ≤ 5.5 V 5.3 fMCK/6 Note 2 1.3 fMCK/6 0.6 Mbps fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.7 V ≤ EVDD0 ≤ 5.5 V 5.3 fMCK/6 Note 2 1.3 fMCK/6 Note 2 0.6 Mbps fMCK/6 bps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.6 V ≤ EVDD0 ≤ 5.5 V 5.3 ⎯ 1.3 fMCK/6 Note 2 0.6 Mbps fMCK/6 bps Theoretical value of the ⎯ 1.3 maximum transfer rate fMCK = fCLK Note 3 Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V ≤ EVDD0 < 1.8 V : MAX. 0.6 Mbps 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) 0.6 Mbps Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 81 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) UART mode connection diagram (during communication at same potential) TxDq RL78 microcontroller RxDq Rx User device Tx TxDq RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 82 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V 62.5 250 500 ns 2.7 V ≤ EVDD0 ≤ 5.5 V 83.3 250 500 ns SCKp high-/low-level width tKH1, tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 7 50 50 2.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 10 50 50 SIp setup time (to SCKp↑) tSIK1 Note 1 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 23 110 110 ns 33 110 110 ns SIp hold time (from tKSI1 SCKp↑) Note 2 Delay time from SCKp↓ to tKSO1 SOp output Note 3 2.7 V ≤ EVDD0 ≤ 5.5 V C = 20 pF Note 4 10 10 10 ns 10 10 10 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. 3. This value is valid only when CSI00’s peripheral I/O redirect function is not used. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 83 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ EVDD0 ≤ 5.5 125 500 1000 ns V 2.4 V ≤ EVDD0 ≤ 5.5 250 500 1000 ns V 1.8 V ≤ EVDD0 ≤ 5.5 500 500 1000 ns V 1.7 V ≤ EVDD0 ≤ 5.5 1000 1000 1000 ns V 1.6 V ≤ EVDD0 ≤ 5.5 ⎯ 1000 1000 ns V SCKp high-/low-level tKH1, 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − tKCY1/2 − tKCY1/2 − ns width tKL1 12 50 50 2.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 18 50 50 2.4 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 38 50 50 1.8 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 50 50 50 1.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 100 100 100 1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ tKCY1/2 − tKCY1/2 − ns 100 100 SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 2.4 V ≤ EVDD0 ≤ 5.5 V 44 110 110 ns 44 110 110 ns 75 110 110 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 110 110 110 ns 1.7 V ≤ EVDD0 ≤ 5.5 V 220 220 220 ns 1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ 220 220 ns SIp hold time tKSI1 (from SCKp↑) Note 2 1.7 V ≤ EVDD0 ≤ 5.5 V 1.6 V ≤ EVDD0 ≤ 5.5 V 19 19 ⎯ 19 19 ns 19 ns Delay time from SCKp↓ to SOp output Note 3 tKSO1 1.7 V ≤ EVDD0 ≤ 5.5 V C = 30 pFNote 4 1.6 V ≤ EVDD0 ≤ 5.5 V C = 30 pFNote 4 25 25 25 ns ⎯ 25 25 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 84 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Remarks 1. 2. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (1/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed LV (low-voltage Unit main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time tKCY2 Note 5 4.0 V ≤ EVDD0 ≤ 5.5 V 20 MHz < fMCK fMCK ≤ 20 MHz 8/fMCK 6/fMCK ⎯ ⎯ ns 6/fMCK 6/fMCK ns 2.7 V ≤ EVDD0 ≤ 5.5 V 16 MHz < fMCK fMCK ≤ 16 MHz 8/fMCK 6/fMCK ⎯ ⎯ ns 6/fMCK 6/fMCK ns 2.4 V ≤ EVDD0 ≤ 5.5 V 6/fMCK and 500 6/fMCK 6/fMCK ns and and 500 500 1.8 V ≤ EVDD0 ≤ 5.5 V 6/fMCK and 750 6/fMCK 6/fMCK ns and and 750 750 1.7 V ≤ EVDD0 ≤ 5.5 V 6/fMCK and 1500 6/fMCK 6/fMCK ns and and 1500 1500 1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ 6/fMCK 6/fMCK ns and and 1500 1500 SCKp high-/low- tKH2, level width tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 − 7 tKCY2/2 tKCY2/2 ns −7 −7 2.7 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 − 8 tKCY2/2 tKCY2/2 ns −8 −8 1.8 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 − 18 tKCY2/2 tKCY2/2 ns − 18 − 18 1.7 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 − 66 tKCY2/2 tKCY2/2 ns − 66 − 66 1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ tKCY2/2 tKCY2/2 ns − 66 − 66 (Notes, Caution, and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 85 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (2/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed main) LV (low-voltage main) Unit main) Mode Mode Mode MIN. MAX. MIN. MAX. MIN. MAX. SIp setup time tSIK2 2.7 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+2 1/fMCK+30 1/fMCK+3 ns (to SCKp↑) Note 0 0 1 1.8 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+3 1/fMCK+30 1/fMCK+3 ns 0 0 1.7 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+4 1/fMCK+40 1/fMCK+4 ns 0 0 1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ 1/fMCK+40 1/fMCK+4 ns 0 SIp hold time tKSI2 1.8 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+3 1/fMCK+31 1/fMCK+3 ns (from SCKp↑) Note 2 1.7 V ≤ EVDD0 ≤ 5.5 V 1 1/fMCK+ 1/fMCK+ 1 1/fMCK+ ns 250 250 250 1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ 1/fMCK+ 250 1/fMCK+ ns 250 Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 2.7 V ≤ EVDD0 ≤ 5.5 V pF Note 4 2.4 V ≤ EVDD0 ≤ 5.5 V 2/fMCK+ 44 2/fMCK+ 75 2/fMCK+ 110 2/fMCK+ 110 2/fMCK+ ns 110 2/fMCK+ ns 110 1.8 V ≤ EVDD0 ≤ 5.5 V 2/fMCK+ 110 2/fMCK+ 110 2/fMCK+ ns 110 1.7 V ≤ EVDD0 ≤ 5.5 V 2/fMCK+ 220 2/fMCK+ 220 2/fMCK+ ns 220 1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ 2/fMCK+ 220 2/fMCK+ ns 220 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 86 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode connection diagram (during communication at same potential) SCKp RL78 SIp microcontroller SOp SCK SO User device SI CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKL1, 2 tKCY1, 2 tKH1, 2 SCKp SIp tKSO1, 2 tSIK1, 2 tKSI1, 2 Input data SOp Output data CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKH1, 2 tKCY1, 2 tKL1, 2 SCKp SIp SOp tKSO1, 2 tSIK1, 2 tKSI1, 2 Input data Output data R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 87 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) (5) During communication at same potential (simplified I2C mode) (1/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SCLr clock frequency fSCL 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 400 Note 1 400 Note 1 kHz 1.8 V ≤ EVDD0 ≤ 5.5 V, Cb = 100 pF, Rb = 3 kΩ 400 Note 1 400 Note 1 400 Note 1 kHz 1.8 V ≤ EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 kΩ 300 Note 1 300 Note 1 300 Note 1 kHz 1.7 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ 250 Note 1 250 Note 1 250 Note 1 kHz 1.6 V ≤ EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 kΩ ⎯ 250 250 kHz Note 1 Note 1 Hold time when SCLr = “L” tLOW 2.7 V ≤ EVDD0 ≤ 5.5 V, 475 1150 1150 ns Cb = 50 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 ≤ 5.5 V, 1150 1150 1150 ns Cb = 100 pF, Rb = 3 kΩ 1.8 V ≤ EVDD0 < 2.7 V, 1550 1550 1550 ns Cb = 100 pF, Rb = 5 kΩ 1.7 V ≤ EVDD0 < 1.8 V, 1850 1850 1850 ns Cb = 100 pF, Rb = 5 kΩ 1.6 V ≤ EVDD0 < 1.8 V, ⎯ 1850 1850 ns Cb = 100 pF, Rb = 5 kΩ Hold time when SCLr = “H” tHIGH 2.7 V ≤ EVDD0 ≤ 5.5 V, 475 1150 1150 ns Cb = 50 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 ≤ 5.5 V, 1150 1150 1150 ns Cb = 100 pF, Rb = 3 kΩ 1.8 V ≤ EVDD0 < 2.7 V, 1550 1550 1550 ns Cb = 100 pF, Rb = 5 kΩ 1.7 V ≤ EVDD0 < 1.8 V, 1850 1850 1850 ns Cb = 100 pF, Rb = 5 kΩ 1.6 V ≤ EVDD0 < 1.8 V, ⎯ 1850 1850 ns Cb = 100 pF, Rb = 5 kΩ (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 88 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (5) During communication at same potential (simplified I2C mode) (2/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, 1/fMCK 1/fMCK 1/fMCK ns Cb = 50 pF, Rb = 2.7 kΩ + 85 Note2 + 145 Note2 + 145 Note2 1.8 V ≤ EVDD0 ≤ 5.5 V, 1/fMCK 1/fMCK 1/fMCK ns Cb = 100 pF, Rb = 3 kΩ + 145 Note2 + 145 Note2 + 145 Note2 1.8 V ≤ EVDD0 < 2.7 V, 1/fMCK 1/fMCK 1/fMCK ns Cb = 100 pF, Rb = 5 kΩ + 230 Note2 + 230 Note2 + 230 Note2 1.7 V ≤ EVDD0 < 1.8 V, 1/fMCK 1/fMCK 1/fMCK ns Cb = 100 pF, Rb = 5 kΩ + 290 Note2 + 290 Note2 + 290 Note2 1.6 V ≤ EVDD0 < 1.8 V, ⎯ 1/fMCK 1/fMCK ns Cb = 100 pF, Rb = 5 kΩ + 290 Note2 + 290 Note2 Data hold time (transmission) tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, 0 305 0 305 0 305 ns Cb = 50 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 ≤ 5.5 V, 0 355 0 355 0 355 ns Cb = 100 pF, Rb = 3 kΩ 1.8 V ≤ EVDD0 < 2.7 V, 0 405 0 405 0 405 ns Cb = 100 pF, Rb = 5 kΩ 1.7 V ≤ EVDD0 < 1.8 V, 0 405 0 405 0 405 ns Cb = 100 pF, Rb = 5 kΩ 1.6 V ≤ EVDD0 < 1.8 V, ⎯ 0 405 0 405 ns Cb = 100 pF, Rb = 5 kΩ Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 89 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Simplified I2C mode mode connection diagram (during communication at same potential) SDAr VDD Rb SDA RL78 microcontroller User device SCLr SCL SCLr Simplified I2C mode serial transfer timing (during communication at same potential) tLOW 1/fSCL tHIGH SDAr tHD:DAT tSU:DAT Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14), h: POM number (g = 0, 1, 4, 5, 7 to 9, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 90 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (low- Unit speed main) main) Mode voltage main) Mode Mode MIN. MAX. MIN. MAX. MIN. MAX. Transfer rate Reception 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 4 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 4 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V fMCK/6 Note 1 5.3 fMCK/6 Note 1 1.3 fMCK/6 Note 1 5.3 fMCK/6 Note 1 1.3 fMCK/6 Notes 1 to 3 fMCK/6 Notes 1, 2 Theoretical value 5.3 1.3 of the maximum transfer rate fMCK = fCLK Note 4 Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. Use it with EVDD0≥Vb. 3. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V ≤ EVDD0 < 2.4 V : MAX. 1.3 Mbps 4. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 32 MHz (2.7 V ≤ VDD ≤ 5.5 V) 16 MHz (2.4 V ≤ VDD ≤ 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V ≤ VDD ≤ 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V ≤ VDD ≤ 5.5 V) fMCK/6 bps Note 1 0.6 Mbps fMCK/6 bps Note 1 0.6 Mbps fMCK/6 bps Notes 1, 2 0.6 Mbps Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. 2. 3. Vb[V]: Communication line voltage q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 91 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high- LS (low- LV (low- Unit speed main) speed main) voltage Mode Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. Transfer rate Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V Note 1 2.8 Note 2 Note 1 2.8 Note 2 Note bps 1 2.8 Mbps Note 2 Note 3 1.2 Note 4 Note 3 1.2 Note 4 Note bps 3 1.2 Mbps Note 4 Notes 5, 6 0.43 Note 7 Notes 5, 6 0.43 Note 7 Notes bps 5, 6 0.43 Mbps Note 7 Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ EVDD0 ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Maximum transfer rate = 1 {−Cb × Rb × ln (1 − 2.2 Vb )} × 3 [bps] Baud rate error (theoretical value) = 1 Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2 Vb )} ( 1 Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 92 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V Maximum transfer rate = 1 {−Cb × Rb × ln (1 − 2.0 Vb )} × 3 [bps] Baud rate error (theoretical value) = 1 Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.0 Vb )} ( 1 Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. Use it with EVDD0 ≥ Vb. 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V Maximum transfer rate = 1 {−Cb × Rb × ln (1 − 1.5 Vb )} × 3 [bps] Baud rate error (theoretical value) = 1 Transfer rate × 2 − {−Cb × Rb × ln (1 − 1.5 Vb )} ( 1 Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 7. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) TxDq RL78 microcontroller Vb Rb Rx User device RxDq Tx R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 93 of 194 RL78/G13 TxDq 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance RxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance Remarks 1. 2. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 94 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (1/2) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, 200 1150 1150 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 300 1150 1150 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ SCKp high-level tKH1 width 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 50 50 50 Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 120 120 120 SCKp low-level tKL1 width 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 7 50 50 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 10 50 50 SIp setup time tSIK1 (to SCKp↑) Note 1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 58 479 479 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 121 479 479 ns SIp hold time tKSI1 (from SCKp↑) Note 1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 10 10 10 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 10 10 10 ns Delay time from SCKp↓ to SOp output Note 1 tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 60 60 60 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ 130 130 130 ns (Notes, Caution, and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 95 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (2/2) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SIp setup time tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, 23 110 110 ns (to SCKp↓) Note 2 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 33 110 110 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ SIp hold time tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, 10 10 10 ns (from SCKp↓) Note 2 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 10 10 10 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ Delay time from SCKp↑ tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, 10 10 10 ns to SOp output Note 2 2.7 V ≤ Vb ≤ 4.0 V, Cb = 20 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 10 10 10 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 20 pF, Rb = 2.7 kΩ Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. This value is valid only when CSI00’s peripheral I/O redirect function is not used. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 96 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage Unit main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, 300 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 1150 1150 ns 2.7 V ≤ EVDD0 < 4.0 V, 500 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1150 1150 ns 1.8 V ≤ EVDD0 < 3.3 V, 1150 1150 1150 ns 1.6 V ≤ Vb ≤ 2.0 V Note, Cb = 30 pF, Rb = 5.5 kΩ SCKp high-level tKH1 width 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 75 75 75 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 170 170 170 Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, Cb = 30 pF, Rb = 5.5 kΩ tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 458 458 458 SCKp low-level tKL1 width 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 12 50 50 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 18 50 50 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note, tKCY1/2 − tKCY1/2 − tKCY1/2 − ns 50 50 50 Cb = 30 pF, Rb = 5.5 kΩ Note Use it with EVDD0 ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed two pages after the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 97 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage Unit main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, 81 2.7 V ≤ Vb ≤ 4.0 V, 479 479 ns Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 177 479 479 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 479 479 479 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ SIp hold time tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, 19 19 19 ns (from SCKp↑) Note 1 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 19 19 19 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 19 19 19 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ Delay time from SCKp↓ tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, 100 100 100 ns to 2.7 V ≤ Vb ≤ 4.0 V, SOp output Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 195 195 195 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 483 483 483 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. Use it with EVDD0 ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 98 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage Unit main) Mode MIN. MAX. MIN. MAX. MIN. MAX. SIp setup time (to SCKp↓) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, 44 2.7 V ≤ Vb ≤ 4.0 V, 110 110 ns Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 44 2.3 V ≤ Vb ≤ 2.7 V, 110 110 ns Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 110 110 110 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ SIp hold time tKSI1 4.0 V ≤ EVDD0 ≤ 5.5 V, 19 19 19 ns (from SCKp↓) Note 1 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 19 19 19 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 19 19 19 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ Delay time from SCKp↑ tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, 25 25 25 ns to 2.7 V ≤ Vb ≤ 4.0 V, SOp output Note 1 Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 25 25 25 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 25 25 25 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ Notes 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. Use it with EVDD0 ≥ Vb. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 99 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode connection diagram (during communication at different potential) SCKp RL78 SIp microcontroller SOp Vb Rb Vb Rb SCK SO User device SI Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 100 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp SIp tSIK1 tKSI1 Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKH1 tKCY1 tKL1 SCKp SIp tSIK1 tKSI1 Input data tKSO1 SOp Output data Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 101 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions HS (high- LS (low-speed LV (low-voltage Unit speed main) main) Mode main) Mode Mode SCKp cycle time Note 1 tKCY2 MIN. MAX. MIN. MAX. MIN. MAX. 4.0 V ≤ EVDD0 ≤ 5.5 V, 24 MHz < fMCK 14/ ⎯ 2.7 V ≤ Vb ≤ 4.0 V fMCK 20 MHz < fMCK ≤ 24 MHz 12/ ⎯ fMCK ⎯ ns ⎯ ns 8 MHz < fMCK ≤ 20 MHz 10/ ⎯ fMCK ⎯ ns 4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/ ⎯ ns fMCK fMCK ≤ 4 MHz 6/fMCK 10/ 10/ ns fMCK fMCK 2.7 V ≤ EVDD0 < 4.0 V, 24 MHz < fMCK 20/ ⎯ 2.3 V ≤ Vb ≤ 2.7 V fMCK 20 MHz < fMCK ≤ 24 MHz 16/ ⎯ fMCK ⎯ ns ⎯ ns 16 MHz < fMCK ≤ 20 MHz 14/ ⎯ fMCK ⎯ ns 8 MHz < fMCK ≤ 16 MHz 12/ ⎯ fMCK ⎯ ns 4 MHz < fMCK ≤ 8 MHz 8/fMCK 16/ ⎯ ns fMCK fMCK ≤ 4 MHz 6/fMCK 10/ 10/ ns fMCK fMCK 1.8 V ≤ EVDD0 < 3.3 V, 24 MHz < fMCK 48/ ⎯ 1.6 V ≤ Vb ≤ 2.0 V Note fMCK 2 20 MHz < fMCK ≤ 24 MHz 36/ ⎯ fMCK ⎯ ns ⎯ ns 16 MHz < fMCK ≤ 20 MHz 32/ ⎯ fMCK ⎯ ns 8 MHz < fMCK ≤ 16 MHz 26/ ⎯ fMCK ⎯ ns 4 MHz < fMCK ≤ 8 MHz 16/ 16/ ⎯ ns fMCK fMCK fMCK ≤ 4 MHz 10/ 10/ 10/ ns fMCK fMCK fMCK (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 102 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions HS (high- LS (low-speed LV (low-voltage Unit speed main) main) Mode main) Mode Mode MIN. MAX. MIN. MAX. MIN. MAX. SCKp high-/low-level tKH2, width tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 tKCY2/2 tKCY2/2 ns − 12 − 50 − 50 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 tKCY2/2 tKCY2/2 ns − 18 − 50 − 50 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 tKCY2/2 tKCY2/2 tKCY2/2 ns − 50 − 50 − 50 SIp setup time (to SCKp↑) Note 3 tSIK2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 1/fMCK 1/fMCK 1/fMCK ns + 20 + 30 + 30 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 1/fMCK 1/fMCK 1/fMCK ns + 20 + 30 + 30 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 1/fMCK 1/fMCK 1/fMCK ns + 30 + 30 + 30 SIp hold time tKSI2 (from SCKp↑) Note 4 1/fMCK + 1/fMCK 1/fMCK ns 31 + 31 + 31 Delay time from tKSO2 SCKp↓ to SOp output Note 5 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2/fMCK + 120 2/fMCK + 573 2/fMCK ns + 573 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2/fMCK + 214 2/fMCK + 573 2/fMCK ns + 573 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 kΩ 2/fMCK + 573 2/fMCK + 573 2/fMCK ns + 573 Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. Use it with EVDD0 ≥ Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 103 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode connection diagram (during communication at different potential) SCKp RL78 microcontroller SIp Vb Rb SCK SO User device SOp SI Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13)) 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 104 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp SIp tSIK2 tKSI2 Input data tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp SIp SOp tSIK2 tKSI2 Input data tKSO2 Output data Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 105 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode SCLr clock frequency fSCL Hold time when SCLr tLOW = “L” Hold time when SCLr tHIGH = “H” MIN. MAX. MIN. MAX. MIN. MAX. 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 300 Note 1 300 Note 1 kHz 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 1000 Note 1 300 Note 1 300 Note 1 kHz 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 400 Note 1 300 Note 1 300 Note 1 kHz 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 400 Note 1 300 Note 1 300 kHz ote 1 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 300 Note 1 300 Note 1 300 Note 1 kHz 4.0 V ≤ EVDD0 ≤ 5.5 V, 475 1550 1550 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 475 1550 1550 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 1150 1550 1550 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 1150 1550 1550 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 1550 1550 1550 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 245 610 610 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 200 610 610 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 675 610 610 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 600 610 610 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 610 610 610 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 106 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode Data setup time (reception) Data hold time (transmission) MIN. MAX. MIN. MAX. MIN. MAX. tSU:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 kHz 2.7 V ≤ EVDD0 < 4.0 V, 1/fMCK + 1/fMCK 1/fMCK kHz 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 135 Note 3 + 190 Note 3 + 190 Note 3 4.0 V ≤ EVDD0 ≤ 5.5 V, 1/fMCK + 1/fMCK 1/fMCK kHz 2.7 V ≤ Vb ≤ 4.0 V, 190 Note Cb = 100 pF, Rb = 2.8 kΩ 3 + 190 Note 3 + 190 Note 3 2.7 V ≤ EVDD0 < 4.0 V, 1/fMCK + 1/fMCK 1/fMCK kHz 2.3 V ≤ Vb ≤ 2.7 V, 190 Note Cb = 100 pF, Rb = 2.7 kΩ 3 + 190 Note 3 + 190 Note 3 1.8 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 kHz tHD:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, 0 305 0 305 0 305 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 0 305 0 305 0 305 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 0 355 0 355 0 355 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 0 355 0 355 0 355 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 < 3.3 V, 0 405 0 405 0 405 ns 1.6 V ≤ Vb ≤ 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 kΩ Notes 1. The value must also be equal to or less than fMCK/4. 2. Use it with EVDD0 ≥ Vb. 3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 107 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Simplified I2C mode connection diagram (during communication at different potential) SDAr RL78 microcontroller SCLr Vb Rb Vb Rb SDA User device SCL Simplified I2C mode serial transfer timing (during communication at different potential) tLOW 1/fSCL tHIGH SCLr SDAr tHD:DAT tSU:DAT Remarks 1. Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 108 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.5.2 Serial interface IICA (1) I2C standard mode (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode SCLA0 clock frequency fSCL MIN. MAX. MIN. MAX. MIN. MAX. Standard 2.7 V ≤ EVDD0 ≤ 5.5 V 0 100 0 100 0 100 kHz mode: fCLK ≥ 1 MHz 1.8 V ≤ EVDD0 ≤ 5.5 V 0 100 0 100 0 100 kHz 1.7 V ≤ EVDD0 ≤ 5.5 V 0 100 0 100 0 100 kHz Setup time of restart condition tSU:STA 1.6 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V ⎯ 4.7 4.7 0 100 0 100 kHz 4.7 4.7 μs 4.7 4.7 μs Hold timeNote 1 1.7 V ≤ EVDD0 ≤ 5.5 V 1.6 V ≤ EVDD0 ≤ 5.5 V tHD:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 4.7 4.7 4.7 μs ⎯ 4.7 4.7 μs 4.0 4.0 4.0 μs 1.8 V ≤ EVDD0 ≤ 5.5 V 1.7 V ≤ EVDD0 ≤ 5.5 V 1.6 V ≤ EVDD0 ≤ 5.5 V 4.0 4.0 4.0 μs 4.0 4.0 4.0 μs ⎯ 4.0 4.0 μs Hold time when SCLA0 = tLOW “L” 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V 4.7 4.7 4.7 μs 4.7 4.7 4.7 μs 1.7 V ≤ EVDD0 ≤ 5.5 V 4.7 4.7 4.7 μs Hold time when SCLA0 = tHIGH “H” 1.6 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V ⎯ 4.7 4.7 μs 4.0 4.0 4.0 μs 4.0 4.0 4.0 μs 1.7 V ≤ EVDD0 ≤ 5.5 V 1.6 V ≤ EVDD0 ≤ 5.5 V 4.0 4.0 4.0 μs ⎯ 4.0 4.0 μs Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V 250 250 250 ns 250 250 250 ns 1.7 V ≤ EVDD0 ≤ 5.5 V 250 250 250 ns Data hold time (transmission)Note 2 1.6 V ≤ EVDD0 ≤ 5.5 V tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V ⎯ 250 250 ns 0 3.45 0 3.45 0 3.45 μs 0 3.45 0 3.45 0 3.45 μs 1.7 V ≤ EVDD0 ≤ 5.5 V 0 3.45 0 3.45 0 3.45 μs Setup time of stop condition 1.6 V ≤ EVDD0 ≤ 5.5 V tSU:STO 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V 1.7 V ≤ EVDD0 ≤ 5.5 V 1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ 4.0 4.0 4.0 ⎯ 0 3.45 0 3.45 μs 4.0 4.0 μs 4.0 4.0 μs 4.0 4.0 μs 4.0 4.0 μs Bus-free time tBUF 2.7 V ≤ EVDD0 ≤ 5.5 V 4.7 4.7 4.7 μs 1.8 V ≤ EVDD0 ≤ 5.5 V 1.7 V ≤ EVDD0 ≤ 5.5 V 4.7 4.7 4.7 μs 4.7 4.7 4.7 μs 1.6 V ≤ EVDD0 ≤ 5.5 V ⎯ 4.7 4.7 μs (Notes, Caution and Remark are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 109 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 110 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (2) I2C fast mode (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode SCLA0 clock frequency Setup time of restart condition Hold timeNote 1 MIN. MAX. MIN. MAX. MIN. MAX. fSCL Fast mode: 2.7 V ≤ EVDD0 ≤ 5.5 V 0 400 0 400 0 400 kHz fCLK ≥ 3.5 MHz 1.8 V ≤ EVDD0 ≤ 5.5 V 0 400 0 400 0 400 kHz tSU:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.6 0.6 0.6 μs 1.8 V ≤ EVDD0 ≤ 5.5 V 0.6 0.6 0.6 μs tHD:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.6 0.6 0.6 μs Hold time when SCLA0 = “L” Hold time when SCLA0 = “H” Data setup time (reception) Data hold time (transmission)Note 2 Setup time of stop condition Bus-free time tLOW tHIGH tSU:DAT tHD:DAT tSU:STO tBUF 1.8 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 1.8 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V 0.6 0.6 0.6 μs 1.3 1.3 1.3 μs 1.3 1.3 1.3 μs 0.6 0.6 0.6 μs 0.6 0.6 0.6 μs 100 100 100 μs 100 100 100 μs 0 0.9 0 0.9 0 0.9 μs 0 0.9 0 0.9 0 0.9 μs 0.6 0.6 0.6 μs 0.6 0.6 0.6 μs 1.3 1.3 1.3 μs 1.8 V ≤ EVDD0 ≤ 5.5 V 1.3 1.3 1.3 μs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 kΩ R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 111 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (3) I2C fast mode plus (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode SCLA0 clock frequency Setup time of restart condition Hold timeNote 1 MIN. MAX. MIN. MAX. MIN. MAX. fSCL Fast mode plus: 2.7 V ≤ EVDD0 ≤ 5.5 V 0 1000 ⎯ fCLK ≥ 10 MHz ⎯ kHz tSU:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 ⎯ ⎯ μs tHD:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 ⎯ ⎯ μs Hold time when SCLA0 = tLOW “L” 2.7 V ≤ EVDD0 ≤ 5.5 V 0.5 ⎯ ⎯ μs Hold time when SCLA0 = tHIGH “H” 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 ⎯ ⎯ μs Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 50 ⎯ ⎯ μs Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 0 0.45 ⎯ ⎯ μs Setup time of stop condition tSU:STO 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 ⎯ ⎯ μs Bus-free time tBUF 2.7 V ≤ EVDD0 ≤ 5.5 V 0.5 ⎯ ⎯ μs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ tLOW tR IICA serial transfer timing SCLAn tHD:DAT tHD:STA tHIGH tF tSU:DAT tSU:STA tHD:STA tSU:STO SDAAn tBUF Stop Start condition condition Remark n = 0, 1 Restart condition Stop condition R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 112 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.6 Analog Characteristics 2.6.1 A/D converter characteristics Classification of A/D converter characteristics Input channel ANI0 to ANI14 ANI16 to ANI26 Internal reference voltage Temperature sensor output voltage Reference voltage (+) = AVREFP Reference voltage (−) = AVREFM Refer to 2.6.1 (1). Refer to 2.6.1 (2). Refer to 2.6.1 (1). Reference Voltage Reference voltage (+) = VDD Reference voltage (−) = VSS Refer to 2.6.1 (3). Reference voltage (+) = VBGR Reference voltage (−) = AVREFM Refer to 2.6.1 (4). − (1) When reference voltage (+)= AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage (TA = −40 to +85°C, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution Overall errorNote 1 Conversion time Zero-scale errorNotes 1, 2 Full-scale errorNotes 1, 2 RES 8 AINL 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V 1.2 AVREFP = VDD Note 3 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 1.2 tCONV 10-bit resolution Target pin: ANI2 to ANI14 3.6 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD ≤ 5.5 V 2.125 3.1875 17 1.6 V ≤ VDD ≤ 5.5 V 57 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V Target pin: Internal 2.7 V ≤ VDD ≤ 5.5 V reference voltage, and temperature sensor 2.4 V ≤ VDD ≤ 5.5 V output voltage (HS (high-speed main) mode) 2.375 3.5625 17 EZS 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V AVREFP = VDD Note 3 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 EFS 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V AVREFP = VDD Note 3 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 10 bit ±3.5 LSB ±7.0 LSB 39 μs 39 μs 39 μs 95 μs 39 μs 39 μs 39 μs ±0.25 ±0.50 ±0.25 ±0.50 %FSR %FSR %FSR %FSR Integral linearity errorNote 1 ILE Differential linearity error DLE Note 1 Analog input voltage VAIN 10-bit resolution AVREFP = VDD Note 3 1.8 V ≤ AVREFP ≤ 5.5 V 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 10-bit resolution AVREFP = VDD Note 3 1.8 V ≤ AVREFP ≤ 5.5 V 1.6 V ≤ AVREFP ≤ 5.5 V Note 4 ANI2 to ANI14 Internal reference voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) ±2.5 ±5.0 ±1.5 ±2.0 0 AVREFP VBGR Note 5 V Note 5 TMPS25 LSB LSB LSB LSB V V V (Notes are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 113 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. Values when the conversion time is set to 57 μs (min.) and 95 μs (max.). 5. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 114 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI26 (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Resolution Overall errorNote 1 Symbol Conditions RES AINL 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V EVDD0 = AVREFP = VDD Notes 3, 1.6 V ≤ AVREFP ≤ 5.5 V 4 Note 5 MIN. TYP. MAX. Unit 8 10 bit 1.2 ±5.0 LSB 1.2 ±8.5 LSB Conversion time tCONV Zero-scale errorNotes 1, 2 EZS Full-scale errorNotes 1, 2 EFS Integral linearity errorNote ILE 1 10-bit resolution Target ANI pin : ANI16 to ANI26 10-bit resolution EVDD0 = AVREFP = VDD Notes 3, 4 3.6 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD ≤ 5.5 V 1.6 V ≤ VDD ≤ 5.5 V 1.8 V ≤ AVREFP ≤ 5.5 V 1.6 V ≤ AVREFP ≤ 5.5 V Note 5 10-bit resolution EVDD0 = AVREFP = VDD Notes 3, 4 1.8 V ≤ AVREFP ≤ 5.5 V 1.6 V ≤ AVREFP ≤ 5.5 V Note 5 10-bit resolution EVDD0 = AVREFP = VDD Notes 3, 4 1.8 V ≤ AVREFP ≤ 5.5 V 1.6 V ≤ AVREFP ≤ 5.5 V Note 5 2.125 3.1875 17 57 39 39 39 95 ±0.35 ±0.60 μs μs μs μs %FSR %FSR ±0.35 ±0.60 %FSR %FSR ±3.5 LSB ±6.0 LSB Differential linearity error Note 1 DLE 10-bit resolution 1.8 V ≤ AVREFP ≤ 5.5 V EVDD0 = AVREFP = VDD Notes 3, 1.6 V ≤ AVREFP ≤ 5.5 V 4 Note 5 ±2.0 LSB ±2.5 LSB Analog input voltage VAIN ANI16 to ANI26 0 AVREFP V and EVDD0 Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. When AVREFP < EVDD0 ≤ VDD, the MAX. values are as follows. Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD. 5. When the conversion time is set to 57 μs (min.) and 95 μs (max.). R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 115 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0), target pin : ANI0 to ANI14, ANI16 to ANI26, internal reference voltage, and temperature sensor output voltage (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS) Parameter Resolution Overall errorNote 1 Symbol Conditions MIN. TYP. MAX. Unit RES 8 10 bit AINL 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.2 ±7.0 LSB 1.6 V ≤ VDD ≤ 5.5 V Note 3 1.2 ±10.5 LSB Conversion time tCONV Conversion time tCONV Zero-scale errorNotes 1, 2 EZS Full-scale errorNotes 1, 2 EFS Integral linearity errorNote 1 ILE Differential linearity error Note DLE 1 10-bit resolution Target pin: ANI0 to ANI14, ANI16 to ANI26 3.6 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 1.8 V ≤ VDD ≤ 5.5 V 2.125 3.1875 17 1.6 V ≤ VDD ≤ 5.5 V 57 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) 3.6 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 2.4 V ≤ VDD ≤ 5.5 V 2.375 3.5625 17 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.6 V ≤ VDD ≤ 5.5 V Note 3 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.6 V ≤ VDD ≤ 5.5 V Note 3 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.6 V ≤ VDD ≤ 5.5 V Note 3 10-bit resolution 1.8 V ≤ VDD ≤ 5.5 V 1.6 V ≤ VDD ≤ 5.5 V Note 3 39 μs 39 μs 39 μs 95 μs 39 μs 39 μs 39 μs ±0.60 ±0.85 %FSR %FSR ±0.60 ±0.85 %FSR %FSR ±4.0 LSB ±6.5 LSB ±2.0 LSB ±2.5 LSB Analog input voltage VAIN ANI0 to ANI14 0 VDD V ANI16 to ANI26 0 EVDD0 V Internal reference voltage VBGR Note 4 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage V Note 4 TMPS25 V (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When the conversion time is set to 57 μs (min.) and 95 μs (max.). 4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 116 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI26 (TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (−) = AVREFM = 0 V Note 4, HS (high-speed main) mode) Parameter Resolution Conversion time Zero-scale errorNotes 1, 2 Integral linearity errorNote 1 Differential linearity error Note 1 Analog input voltage Symbol Conditions RES tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V VAIN MIN. 17 0 TYP. MAX. Unit 8 bit 39 μs ±0.60 %FSR ±2.0 LSB ±1.0 VBGR Note 3 LSB V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (−) = VSS, the MAX. values are as follows. Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (−) = AVREFM. Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (−) = AVREFM. Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (−) = AVREFM. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 117 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.6.2 Temperature sensor/internal reference voltage characteristics (TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the temperature Operation stabilization wait time tAMP MIN. 1.38 5 TYP. 1.05 1.45 −3.6 MAX. 1.5 Unit V V mV/°C μs 2.6.3 POR circuit characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Detection voltage Minimum pulse widthNote Symbol Conditions VPOR Power supply rise time VPDR Power supply fall time TPW MIN. TYP. MAX. Unit 1.47 1.51 1.55 V 1.46 1.50 1.54 V 300 μs Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 118 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Detection voltage Parameter Supply voltage level Minimum pulse width Detection delay time Symbol Conditions VLVD0 Power supply rise time Power supply fall time VLVD1 Power supply rise time Power supply fall time VLVD2 Power supply rise time Power supply fall time VLVD3 Power supply rise time Power supply fall time VLVD4 Power supply rise time Power supply fall time VLVD5 Power supply rise time Power supply fall time VLVD6 Power supply rise time Power supply fall time VLVD7 Power supply rise time Power supply fall time VLVD8 Power supply rise time Power supply fall time VLVD9 Power supply rise time Power supply fall time VLVD10 Power supply rise time Power supply fall time VLVD11 Power supply rise time Power supply fall time VLVD12 Power supply rise time Power supply fall time VLVD13 Power supply rise time Power supply fall time tLW MIN. TYP. MAX. Unit 3.98 4.06 4.14 V 3.90 3.98 4.06 V 3.68 3.75 3.82 V 3.60 3.67 3.74 V 3.07 3.13 3.19 V 3.00 3.06 3.12 V 2.96 3.02 3.08 V 2.90 2.96 3.02 V 2.86 2.92 2.97 V 2.80 2.86 2.91 V 2.76 2.81 2.87 V 2.70 2.75 2.81 V 2.66 2.71 2.76 V 2.60 2.65 2.70 V 2.56 2.61 2.66 V 2.50 2.55 2.60 V 2.45 2.50 2.55 V 2.40 2.45 2.50 V 2.05 2.09 2.13 V 2.00 2.04 2.08 V 1.94 1.98 2.02 V 1.90 1.94 1.98 V 1.84 1.88 1.91 V 1.80 1.84 1.87 V 1.74 1.77 1.81 V 1.70 1.73 1.77 V 1.64 1.67 1.70 V 1.60 1.63 1.66 V 300 μs 300 μs R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 119 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions Interrupt and reset VLVDA0 mode VLVDA1 VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVDA2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVDA3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage VLVDB0 VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage VLVDB1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVDB2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVDB3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage VLVDC0 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage VLVDC1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVDC2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVDC3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage MIN. TYP. MAX. Unit 1.60 1.63 1.66 V 1.74 1.77 1.81 V 1.70 1.73 1.77 V 1.84 1.88 1.91 V 1.80 1.84 1.87 V 2.86 2.92 2.97 V 2.80 2.86 2.91 V 1.80 1.84 1.87 V 1.94 1.98 2.02 V 1.90 1.94 1.98 V 2.05 2.09 2.13 V 2.00 2.04 2.08 V 3.07 3.13 3.19 V 3.00 3.06 3.12 V 2.40 2.45 2.50 V 2.56 2.61 2.66 V 2.50 2.55 2.60 V 2.66 2.71 2.76 V 2.60 2.65 2.70 V 3.68 3.75 3.82 V 3.60 3.67 3.74 V 2.70 2.75 2.81 V 2.86 2.92 2.97 V 2.80 2.86 2.91 V 2.96 3.02 3.08 V 2.90 2.96 3.02 V 3.98 4.06 4.14 V 3.90 3.98 4.06 V 2.6.5 Power supply voltage rising slope characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 2.4 AC Characteristics. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 120 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Data retention supply voltage Symbol VDDDR Conditions MIN. TYP. MAX. Unit 1.46Note 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected. STOP mode Data retention mode Operation mode VDD STOP instruction execution Standby release signal (interrupt request) VDDDR 2.8 Flash Memory Programming Characteristics (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions CPU/peripheral hardware clock fCLK frequency 1.8 V ≤ VDD ≤ 5.5 V Number of code flash rewrites Notes 1, 2, 3 Cerwr Retained for 20 years MIN. 1 TA = 85°C 1,000 TYP. MAX. 32 Unit MHz Times Number of data flash rewrites Notes 1, 2, 3 Retained for 1 years Retained for 5 years TA = 25°C TA = 85°C 1,000,000 100,000 Retained for 20 years TA = 85°C 10,000 Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self programming library 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 2.9 Dedicated Flash Memory Programmer Communication (UART) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Transfer rate Symbol Conditions During serial programming MIN. TYP. MAX. Unit 115,200 1,000,000 bps R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 121 of 194 RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.10 Timing Specs for Switching Flash Memory Programming Modes (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released tSUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset tSU POR and LVD reset must be released before 10 μs after the TOOL0 pin is set to the the external reset is released. low level Time to hold the TOOL0 pin at tHD POR and LVD reset must be released before 1 ms the low level after the external the external reset is released. reset is released (excluding the processing time of the firmware to control the flash memory) <1> <2> <3> <4> RESET TOOL0 723 µs + tHD processing time 00H reception (TOOLRxD, TOOLTxD mode) tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released during this period. tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 122 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) This chapter describes the electrical specifications for the products "G: Industrial applications (TA = -40 to +105C)". Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. 3. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 With functions for each product in the RL78/G13 User’s Manual Hardware. 4. Please contact Renesas Electronics sales office for derating of operation under TA = +85C to +105C. Derating is the systematic reduction of load for the sake of improved reliability. There are following differences between the products "G: Industrial applications (TA = -40 to +105C)" and the products “A: Consumer applications, and D: Industrial applications”. Parameter Operating ambient temperature Operating mode Operating voltage range High-speed on-chip oscillator clock accuracy Serial array unit IICA Voltage detector (Remark is listed on the next page.) Application A: Consumer applications, G: Industrial applications D: Industrial applications TA = -40 to +85C TA = -40 to +105C HS (high-speed main) mode: HS (high-speed main) mode only: 2.7 V  VDD  5.5 V@1 MHz to 32 MHz 2.4 V  VDD  5.5 V@1 MHz to 16 MHz 2.7 V  VDD  5.5 V@1 MHz to 32 MHz 2.4 V  VDD  5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V  VDD  5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V  VDD  5.5 V@1 MHz to 4 MHz 1.8 V  VDD  5.5 V 1.0%@ TA = -20 to +85C 2.4 V  VDD  5.5 V 2.0%@ TA = +85 to +105C 1.5%@ TA = -40 to -20C 1.0%@ TA = -20 to +85C 1.6 V  VDD < 1.8 V 5.0%@ TA = -20 to +85C 5.5%@ TA = -40 to -20C 1.5%@ TA = -40 to -20C UART UART CSI: fCLK/2 (supporting 16 Mbps), fCLK/4 Simplified I2C communication CSI: fCLK/4 Simplified I2C communication Normal mode Normal mode Fast mode Fast mode Fast mode plus Rise detection voltage: 1.67 V to 4.06 V Rise detection voltage: 2.61 V to 4.06 V (14 levels) (8 levels) Fall detection voltage: 1.63 V to 3.98 V Fall detection voltage: 2.55 V to 3.98 V (14 levels) (8 levels) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 123 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to +105°C) are different from those of the products “A: Consumer applications, and D: Industrial applications”. For details, refer to 3.1 to 3.10. 3.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Symbols Conditions Ratings Unit Supply voltage VDD −0.5 to +6.5 V EVDD0, EVDD1 EVDD0 = EVDD1 −0.5 to +6.5 V EVSS0, EVSS1 EVSS0 = EVSS1 −0.5 to +0.3 V REGC pin input voltage VIREGC REGC −0.3 to +2.8 V and −0.3 to VDD +0.3Note 1 Input voltage VI1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, −0.3 to EVDD0 +0.3 V P50 to P57, P64 to P67, P70 to P77, P80 to P87, and −0.3 to VDD +0.3Note 2 P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 VI2 P60 to P63 (N-ch open-drain) −0.3 to +6.5 V VI3 P20 to P27, P121 to P124, P137, P150 to P156, −0.3 to VDD +0.3Note 2 V EXCLK, EXCLKS, RESET Output voltage VO1 VO2 P00 to P07, P10 to P17, P30 to P37, P40 to P47, −0.3 to EVDD0 +0.3 V P50 to P57, P60 to P67, P70 to P77, P80 to P87, and −0.3 to VDD +0.3 Note 2 P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 P20 to P27, P150 to P156 −0.3 to VDD +0.3 Note 2 V Analog input voltage VAI1 ANI16 to ANI26 −0.3 to EVDD0 +0.3 V and −0.3 to AVREF(+) +0.3Notes 2, 3 VAI2 ANI0 to ANI14 −0.3 to VDD +0.3 V and −0.3 to AVREF(+) +0.3Notes 2, 3 Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. Must be 6.5 V or lower. 3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. 2. 3. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. AVREF (+) : + side reference voltage of the A/D converter. VSS : Reference voltage R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 124 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Symbols Conditions Ratings Unit Output current, high IOH1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 −40 mA Total of all pins P00 to P04, P07, P32 to P37, −70 mA −170 mA P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 P05, P06, P10 to P17, P30, P31, −100 mA P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 IOH2 Per pin P20 to P27, P150 to P156 −0.5 mA Total of all pins −2 mA Output current, low IOL1 Per pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 40 mA Total of all pins P00 to P04, P07, P32 to P37, 70 mA 170 mA P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 P05, P06, P10 to P17, P30, P31, 100 mA P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 IOL2 Per pin P20 to P27, P150 to P156 1 mA Total of all pins 5 mA Operating ambient TA temperature In normal operation mode In flash memory programming mode −40 to +105 °C Storage temperature Tstg −65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 125 of 194 RL78/G13 3.2 Oscillator Characteristics 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.2.1 X1, XT1 oscillator characteristics (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Resonator Conditions X1 clock oscillation frequency (fX)Note Ceramic resonator/ crystal resonator XT1 clock oscillation Crystal resonator frequency (fX)Note 2.7 V ≤ VDD ≤ 5.5 V 2.4 V ≤ VDD < 2.7 V MIN. 1.0 1.0 32 TYP. 32.768 MAX. 20.0 16.0 35 Unit MHz MHz kHz Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator. 3.2.2 On-chip oscillator characteristics (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator fIH clock frequency Notes 1, 2 1 32 MHz High-speed on-chip oscillator clock frequency accuracy −20 to +85 °C −40 to −20 °C 2.4 V ≤ VDD ≤ 5.5 V 2.4 V ≤ VDD ≤ 5.5 V −1.0 +1.0 % −1.5 +1.5 % +85 to +105 °C 2.4 V ≤ VDD ≤ 5.5 V −2.0 +2.0 % Low-speed on-chip oscillator fIL clock frequency 15 kHz Low-speed on-chip oscillator clock frequency accuracy −15 +15 % Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of HOCODIV register. 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 126 of 194 RL78/G13 3.3 DC Characteristics 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.3.1 Pin characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output current, IOH1 highNote 1 Per pin for P00 to P07, P10 to P17, 2.4 V ≤ EVDD0 ≤ 5.5 V P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 -3.0 Note 2 mA Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 < 4.0 V 2.4 V ≤ EVDD0 < 2.7 V -30.0 mA −10.0 mA −5.0 mA Total of P05, P06, P10 to P17, P30, P31, 4.0 V ≤ EVDD0 ≤ 5.5 V P50 to P57, P64 to P67, P70 to P77, P80 2.7 V ≤ EVDD0 < 4.0 V to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 2.4 V ≤ EVDD0 < 2.7 V (When duty ≤ 70% Note 3) -30.0 mA −19.0 mA −10.0 mA Total of all pins (When duty ≤ 70%Note 3) 2.4 V ≤ EVDD0 ≤ 5.5 V -60.0 mA IOH2 Per pin for P20 to P27, P150 to P156 2,4 V ≤ VDD ≤ 5.5 V −0.1Note 2 mA Total of all pins (When duty ≤ 70%Note 3) 2.4 V ≤ VDD ≤ 5.5 V −1.5 mA Notes 1. 2. 3. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to an output pin. Do not exceed the total current value. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (IOH × 0.7)/(n × 0.01) Where n = 80% and IOH = −10.0 mA Total output current of pins = (−10.0 × 0.7)/(80 × 0.01) ≅ −8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 127 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5) Items Output current, lowNote 1 Symbol IOL1 Conditions Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 Per pin for P60 to P63 MIN. TYP. MAX. Unit 8.5 Note 2 mA 15.0 Note 2 mA Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 (When duty ≤ 70% Note 3) 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 < 4.0 V 2.4 V ≤ EVDD0 < 2.7 V 40.0 mA 15.0 mA 9.0 mA Total of P05, P06, P10 to P17, P30, 4.0 V ≤ EVDD0 ≤ 5.5 V P31, P50 to P57, P60 to P67, 2.7 V ≤ EVDD0 < 4.0 V P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, 2,4 V ≤ EVDD0 < 2.7 V P147 (When duty ≤ 70% Note 3) 40.0 mA 35.0 mA 20.0 mA Total of all pins (When duty ≤ 70% Note 3) IOL2 Per pin for P20 to P27, P150 to P156 80.0 mA 0.4 Note 2 mA Total of all pins (When duty ≤ 70%Note 3) 2,4 V ≤ VDD ≤ 5.5 V 5.0 mA Notes 1. 2. 3. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0, EVSS1 and VSS pin. Do not exceed the total current value. Specification under conditions where the duty factor ≤ 70%. The output current value that has changed to the duty factor > 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). • Total output current of pins = (IOL × 0.7)/(n × 0.01) Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 × 0.7)/(80 × 0.01) ≅ 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 128 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input voltage, VIH1 high P00 to P07, P10 to P17, P30 to P37, Normal input buffer P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 0.8EVDD0 EVDD0 V VIH2 P01, P03, P04, P10, P11, TTL input buffer 2.2 P13 to P17, P43, P44, P53 to P55, 4.0 V ≤ EVDD0 ≤ 5.5 V P80, P81, P142, P143 TTL input buffer 2.0 3.3 V ≤ EVDD0 < 4.0 V EVDD0 V EVDD0 V TTL input buffer 1.5 2.4 V ≤ EVDD0 < 3.3 V EVDD0 V VIH3 P20 to P27, P150 to P156 0.7VDD VDD V VIH4 P60 to P63 0.7EVDD0 6.0 V VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8VDD VDD V Input voltage, VIL1 low P00 to P07, P10 to P17, P30 to P37, Normal input buffer 0 P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 0.2EVDD0 V VIL2 P01, P03, P04, P10, P11, TTL input buffer 0 P13 to P17, P43, P44, P53 to P55, 4.0 V ≤ EVDD0 ≤ 5.5 V P80, P81, P142, P143 TTL input buffer 0 3.3 V ≤ EVDD0 < 4.0 V 0.8 V 0.5 V TTL input buffer 0 2.4 V ≤ EVDD0 < 3.3 V 0.32 V VIL3 P20 to P27, P150 to P156 0 0.3VDD V VIL4 P60 to P63 0 0.3EVDD0 V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 129 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5) Items Symbol Conditions MIN. TYP. MAX. Unit Output voltage, VOH1 P00 to P07, P10 to P17, P30 to 4.0 V ≤ EVDD0 ≤ 5.5 V, EVDD0 − V high P37, P40 to P47, P50 to P57, P64 IOH1 = −3.0 mA 0.7 to P67, P70 to P77, P80 to P87, 2.7 V ≤ EVDD0 ≤ 5.5 V, EVDD0 − V P90 to P97, P100 to P106, P110 to IOH1 = −2.0 mA 0.6 P117, P120, P125 to P127, P130, P140 to P147 2.4 V ≤ EVDD0 ≤ 5.5 V, EVDD0 − V IOH1 = −1.5 mA 0.5 VOH2 P20 to P27, P150 to P156 2.4 V ≤ VDD ≤ 5.5 V, VDD − 0.5 V IOH2 = −100 μ A Output voltage, VOL1 low P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 8.5 mA 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 3.0 mA 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 1.5 mA 0.7 V 0.6 V 0.4 V 2.4 V ≤ EVDD0 ≤ 5.5 V, IOL1 = 0.6 mA 0.4 V VOL2 P20 to P27, P150 to P156 2.4 V ≤ VDD ≤ 5.5 V, IOL2 = 400 μ A 0.4 V VOL3 P60 to P63 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 15.0 mA 2.0 V 4.0 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 5.0 mA 0.4 V 2.7 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 3.0 mA 0.4 V 2.4 V ≤ EVDD0 ≤ 5.5 V, IOL3 = 2.0 mA 0.4 V Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 130 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5) Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage ILIH1 current, high P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 VI = EVDD0 1 μA ILIH2 P20 to P27, P137, P150 to P156, RESET VI = VDD 1 μA ILIH3 P121 to P124 VI = VDD In input port or (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input 1 μA In resonator connection 10 μA Input leakage ILIL1 current, low P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 VI = EVSS0 −1 μA ILIL2 P20 to P27, P137, P150 to P156, RESET VI = VSS −1 μA ILIL3 P121 to P124 VI = VSS In input port or (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input −1 μA In resonator connection −10 μA On-chip pll-up RU resistance P00 to P07, P10 to P17, VI = EVSS0, In input port 10 20 100 kΩ P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 131 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.3.2 Supply current characteristics (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (1/2) Parameter Supply current Note 1 Symbol IDD1 Operating mode HS (high- speed main) mode Note 5 Conditions fIH = 32 MHz Note 3 Basic operation Normal operation fIH = 24 MHz Note 3 Normal operation fIH = 16 MHz Note 3 Normal operation HS (high- speed main) mode Note 5 fMX = 20 MHzNote 2, VDD = 5.0 V Normal operation fMX = 20 MHzNote 2, VDD = 3.0 V Normal operation fMX = 10 MHzNote 2, VDD = 5.0 V Normal operation fMX = 10 MHzNote 2, VDD = 3.0 V Normal operation Subsystem clock operation fSUB = 32.768 kHz Note 4 TA = −40°C Normal operation fSUB = 32.768 kHz Note 4 TA = +25°C Normal operation fSUB = 32.768 kHz Normal Note 4 operation TA = +50°C fSUB = 32.768 kHz Normal Note 4 operation TA = +70°C fSUB = 32.768 kHz Normal Note 4 operation TA = +85°C fSUB = 32.768 kHz Normal Note 4 operation TA = +105°C VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection MIN. TYP. MAX. Unit 2.1 mA 2.1 mA 4.6 7.5 mA 4.6 7.5 mA 3.7 5.8 mA 3.7 5.8 mA 2.7 4.2 mA 2.7 4.2 mA 3.0 4.9 mA 3.2 5.0 mA 3.0 4.9 mA 3.2 5.0 mA 1.9 2.9 mA 1.9 2.9 mA 1.9 2.9 mA 1.9 2.9 mA 4.1 4.9 μA 4.2 5.0 μA 4.1 4.9 μA 4.2 5.0 μA 4.2 5.5 μA 4.3 5.6 μA 4.3 6.3 μA 4.4 6.4 μA 4.6 7.7 μA 4.7 7.8 μA 6.9 19.7 μA 7.0 19.8 μA (Notes and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 132 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12bit interval timer, and watchdog timer. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 133 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (2/2) Parameter Symbol Supply current Note 1 IDD2 Note 2 HALT mode Conditions HS (high- speed main) mode Note 7 fIH = 32 MHz Note 4 fIH = 24 MHz Note 4 VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V MIN. TYP. MAX. Unit 0.54 2.90 mA 0.54 2.90 mA 0.44 2.30 mA fIH = 16 MHz Note 4 VDD = 3.0 V VDD = 5.0 V 0.44 2.30 mA 0.40 1.70 mA HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V fMX = 20 MHzNote 3, VDD = 3.0 V Square wave input Resonator connection Square wave input 0.40 1.70 mA 0.28 1.90 mA 0.45 2.00 mA 0.28 1.90 mA VDD = 3.0 V fMX = 10 MHzNote 3, Resonator connection Square wave input 0.45 2.00 mA 0.19 1.02 mA VDD = 5.0 V fMX = 10 MHzNote 3, Resonator connection Square wave input 0.26 1.10 mA 0.19 1.02 mA Subsystem clock operation VDD = 3.0 V fSUB = 32.768 kHzNote 5 TA = −40°C fSUB = 32.768 kHzNote 5 Resonator connection Square wave input Resonator connection Square wave input 0.26 1.10 mA 0.25 0.57 μA 0.44 0.76 μA 0.30 0.57 μA TA = +25°C Resonator connection fSUB = 32.768 kHzNote 5 Square wave input 0.49 0.76 μA 0.37 1.17 μA TA = +50°C Resonator connection fSUB = 32.768 kHzNote 5 Square wave input 0.56 1.36 μA 0.53 1.97 μA TA = +70°C Resonator connection fSUB = 32.768 kHzNote 5 Square wave input 0.72 2.16 μA 0.82 3.37 μA TA = +85°C Resonator connection fSUB = 32.768 kHzNote 5 Square wave input 1.01 3.56 μA 3.01 15.37 μA TA = +105°C IDD3Note 6 STOP TA = −40°C modeNote 8 TA = +25°C Resonator connection 3.20 15.56 μA 0.18 0.50 μA 0.23 0.50 μA TA = +50°C 0.30 1.10 μA TA = +70°C 0.46 1.90 μA TA = +85°C 0.75 3.30 μA TA = +105°C 2.94 15.30 μA (Notes and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 134 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz 8. Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 135 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Supply IDD1 current Note 1 Operating mode Conditions HS (high- fIH = 32 MHz Note 3 speed main) mode Note 5 Basic operation Normal operation fIH = 24 MHz Note 3 Normal operation fIH = 16 MHz Note 3 Normal operation HS (high- speed main) mode Note 5 fMX = 20 MHzNote 2, VDD = 5.0 V Normal operation fMX = 20 MHzNote 2, VDD = 3.0 V Normal operation fMX = 10 MHzNote 2, VDD = 5.0 V Normal operation fMX = 10 MHzNote 2, VDD = 3.0 V Normal operation Subsystem clock operation fSUB = 32.768 kHz Note 4 TA = −40°C Normal operation fSUB = 32.768 kHz Note 4 TA = +25°C Normal operation fSUB = 32.768 kHz Note 4 TA = +50°C Normal operation fSUB = 32.768 kHz Note 4 TA = +70°C Normal operation fSUB = 32.768 kHz Note 4 TA = +85°C Normal operation fSUB = 32.768 kHz Note 4 TA = +105°C Normal operation VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection MIN. TYP. MAX. Unit 2.3 mA 2.3 mA 5.2 9.2 mA 5.2 9.2 mA 4.1 7.0 mA 4.1 7.0 mA 3.0 5.0 mA 3.0 5.0 mA 3.4 5.9 mA 3.6 6.0 mA 3.4 5.9 mA 3.6 6.0 mA 2.1 3.5 mA 2.1 3.5 mA 2.1 3.5 mA 2.1 3.5 mA 4.8 5.9 μA 4.9 6.0 μA 4.9 5.9 μA 5.0 6.0 μA 5.0 7.6 μA 5.1 7.7 μA 5.2 9.3 μA 5.3 9.4 μA 5.7 13.3 μA 5.8 13.4 μA 10.0 46.0 μA 10.0 46.0 μA (Notes and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 136 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). However, not including the current flowing into the 12-bit interval timer and watchdog timer. 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 137 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Supply current Note 1 IDD2 Note 2 HALT mode HS (high- speed main) mode Note 7 Conditions fIH = 32 MHz Note 4 fIH = 24 MHz Note 4 fIH = 16 MHz Note 4 HS (high- speed main) mode Note 7 fMX = 20 MHzNote 3, VDD = 5.0 V fMX = 20 MHzNote 3, VDD = 3.0 V fMX = 10 MHzNote 3, VDD = 5.0 V fMX = 10 MHzNote 3, VDD = 3.0 V Subsystem clock operation fSUB = 32.768 kHzNote 5 TA = −40°C fSUB = 32.768 kHzNote 5 TA = +25°C fSUB = 32.768 kHzNote 5 TA = +50°C fSUB = 32.768 kHzNote 5 TA = +70°C fSUB = 32.768 kHzNote 5 TA = +85°C fSUB = 32.768 kHzNote 5 TA = +105°C IDD3Note 6 STOP TA = −40°C modeNote 8 TA = +25°C TA = +50°C TA = +70°C TA = +85°C TA = +105°C VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection Square wave input Resonator connection MIN. TYP. MAX. Unit 0.62 3.40 mA 0.62 3.40 mA 0.50 2.70 mA 0.50 2.70 mA 0.44 1.90 mA 0.44 1.90 mA 0.31 2.10 mA 0.48 2.20 mA 0.31 2.10 mA 0.48 2.20 mA 0.21 1.10 mA 0.28 1.20 mA 0.21 1.10 mA 0.28 1.20 mA 0.28 0.61 μA 0.47 0.80 μA 0.34 0.61 μA 0.53 0.80 μA 0.41 2.30 μA 0.60 2.49 μA 0.64 4.03 μA 0.83 4.22 μA 1.09 8.04 μA 1.28 8.23 μA 5.50 41.00 μA 5.50 41.00 μA 0.19 0.52 μA 0.25 0.52 μA 0.32 2.21 μA 0.55 3.94 μA 1.00 7.95 μA 5.00 40.00 μA (Notes and Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 138 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current flowing into the 12-bit interval timer and watchdog timer. 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer. 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 32 MHz 2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz 8. Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT mode. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 139 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) Peripheral Functions (Common to all products) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Low-speed onchip oscillator operating current RTC operating current Symbol IFILNote 1 IRTC Notes 1, 2, 3 Conditions MIN. TYP. MAX. Unit 0.20 μA 0.02 μA 12-bit interval timer operating current I Notes 1, 2, IT 4 Watchdog timer operating current A/D converter operating current A/D converter reference voltage current Temperature sensor operating current LVD operating current Self programming operating current BGO operating current IWDT Notes 1, 2, 5 IADC Notes 1, 6 I Note ADREF 1 I Note 1 TMPS I Notes 1, LVD 7 I Notes 1, FSP 9 IBGO Notes 1, 8 fIL = 15 kHz When conversion at maximum speed Normal mode, AVREFP = VDD = 5.0 V Low voltage mode, AVREFP = VDD = 3.0 V SNOOZE operating current I Note 1 SNOZ ADC operation The mode is performed Note 10 The A/D conversion operations are performed, Loe voltage mode, AVREFP = VDD = 3.0 V CSI/UART operation 0.02 μA 0.22 μA 1.3 1.7 mA 0.5 0.7 mA 75.0 μA 75.0 μA 0.08 μA 2.50 12.20 mA 2.50 12.20 mA 0.50 1.10 mA 1.20 2.04 mA 0.70 1.54 mA Notes 1. Current flowing to the VDD. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed onchip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock. 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer operates. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 140 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter is in operation. 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10. For shift time to the SNOOZE mode, see 18.3.3 SNOOZE mode in the RL78/G13 User’s Manual Hardware. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25°C R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 141 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.4 AC Characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Conditions MIN. TYP. Instruction cycle (minimum instruction execution time) External system clock frequency External system clock input highlevel width, low-level width TI00 to TI07, TI10 to TI17 input high-level width, low-level width TO00 to TO07, TO10 to TO17 output frequency PCLBUZ0, PCLBUZ1 output frequency Interrupt input high-level width, low-level width Key interrupt input low-level width RESET low-level width TCY fEX fEXS tEXH, tEXL tEXHS, tEXLS tTIH, tTIL fTO fPCL tINTH, tINTL tKR tRSL Main system clock (fMAIN) operation HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.03125 main) mode 2.4 V ≤ VDD < 2.7 V 0.0625 Subsystem clock (fSUB) 2.4 V ≤ VDD ≤ 5.5 V 28.5 operation In the self HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.03125 programming main) mode 2.4 V ≤ VDD < 2.7 V 0.0625 mode 2.7 V ≤ VDD ≤ 5.5 V 1.0 2.4 V ≤ VDD < 2.7 V 1.0 32 2.7 V ≤ VDD ≤ 5.5 V 24 2.4 V ≤ VDD < 2.7 V 30 13.7 1/fMCK+10 HS (high-speed main) mode 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 < 4.0 V 2.4 V ≤ EVDD0 < 2.7 V HS (high-speed main) mode 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 < 4.0 V 2.4 V ≤ EVDD0 < 2.7 V INTP0 2.4 V ≤ VDD ≤ 5.5 V 1 INTP1 to INTP11 2.4 V ≤ EVDD0 ≤ 5.5 V 1 KR0 to KR7 2.4 V ≤ EVDD0 ≤ 5.5 V 250 10 30.5 MAX. 1 1 31.3 1 1 20.0 16.0 35 16 8 4 16 8 4 Unit μs μs μs μs μs MHz MHz kHz ns ns μs nsNote MHz MHz MHz MHz MHz MHz μs μs ns μs Note The following conditions are required for low voltage interface when EVDD0 < VDD 2.4V ≤ EVDD0 < 2.7 V : MIN. 125 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 142 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 Cycle time TCY [µs] 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.03125 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.4 2.7 Supply voltage VDD [V] AC Timing Test Points VIH/VOH VIL/VOL Test points External System Clock Timing EXCLK/EXCLKS tEXL/ tEXLS 1/fEX/ 1/fEXS VIH/VOH VIL/VOL tEXH/ tEXHS R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 143 of 194 RL78/G13 TI/TO Timing TI00 to TI07, TI10 to TI17 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) tTIL tTIH TO00 to TO07, TO10 to TO17 Interrupt Request Input Timing INTP0 to INTP11 Key Interrupt Input Timing KR0 to KR7 RESET Input Timing RESET 1/fTO tINTL tINTH tKR tRSL R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 144 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIL/VOL Test points VIH/VOH VIL/VOL 3.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Transfer rate Note 1 MIN. MAX. fMCK/12 Note 2 Theoretical value of the 2.6 maximum transfer rate fCLK = 32 MHz, fMCK = fCLK Unit bps Mbps Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 1.3 Mbps Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). UART mode connection diagram (during communication at same potential) TxDq RL78 microcontroller RxDq Rx User device Tx TxDq RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 145 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 2.7 V ≤ EVDD0 ≤ 5.5 V 250 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 500 ns SCKp high-/low-level width tKH1, 4.0 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − 24 ns tKL1 2.7 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − 36 ns 2.4 V ≤ EVDD0 ≤ 5.5 V tKCY1/2 − 76 ns SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V 66 ns 2.7 V ≤ EVDD0 ≤ 5.5 V 66 ns SIp hold time (from SCKp↑) Note 2 tKSI1 Delay time from SCKp↓ to SOp output Note 3 tKSO1 2.4 V ≤ EVDD0 ≤ 5.5 V C = 30 pF Note 4 113 ns 38 ns 50 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 146 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit SCKp cycle time Note 5 tKCY2 4.0 V ≤ EVDD0 ≤ 5.5 V 20 MHz < fMCK fMCK ≤ 20 MHz MIN. 16/fMCK 12/fMCK MAX. ns ns 2.7 V ≤ EVDD0 ≤ 5.5 16 MHz < fMCK 16/fMCK ns V fMCK ≤ 16 MHz 12/fMCK ns 2.4 V ≤ EVDD0 ≤ 5.5 V 16/fMCK ns 12/fMCK and 1000 ns SCKp high-/low-level tKH2, width tKL2 4.0 V ≤ EVDD0 ≤ 5.5 V 2.7 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 − 14 ns tKCY2/2 − 16 ns 2.4 V ≤ EVDD0 ≤ 5.5 V tKCY2/2 − 36 ns SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V ≤ EVDD0 ≤ 5.5 V 2.4 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+40 ns 1/fMCK+60 ns SIp hold time (from SCKp↑) Note 2 Delay time from SCKp↓ to SOp output Note 3 tKSI2 tKSO2 2.4 V ≤ EVDD0 ≤ 5.5 V C = 30 pF Note 4 2.7 V ≤ EVDD0 ≤ 5.5 V 2.4 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+62 ns 2/fMCK+66 ns 2/fMCK+113 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) CSI mode connection diagram (during communication at same potential) SCKp RL78 microcontroller SIp SOp R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 SCK SO User device SI Page 147 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKL1, 2 tKCY1, 2 tKH1, 2 SCKp SIp tKSO1, 2 tSIK1, 2 tKSI1, 2 Input data SOp Output data CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKH1, 2 tKCY1, 2 tKL1, 2 SCKp SIp tKSO1, 2 tSIK1, 2 tKSI1, 2 Input data SOp Output data Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 148 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (4) During communication at same potential (simplified I2C mode) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Unit Mode SCLr clock frequency Hold time when SCLr = “L” Hold time when SCLr = “H” Data setup time (reception) Data hold time (transmission) MIN. MAX. fSCL 2.7 V ≤ EVDD0 ≤ 5.5 V, 400 Note1 kHz Cb = 50 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 ≤ 5.5 V, 100 Note1 kHz Cb = 100 pF, Rb = 3 kΩ tLOW 2.7 V ≤ EVDD0 ≤ 5.5 V, 1200 ns Cb = 50 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 ≤ 5.5 V, 4600 ns Cb = 100 pF, Rb = 3 kΩ tHIGH 2.7 V ≤ EVDD0 ≤ 5.5 V, 1200 ns Cb = 50 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 ≤ 5.5 V, 4600 ns Cb = 100 pF, Rb = 3 kΩ tSU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, 1/fMCK + 220 ns Note2 Cb = 50 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 ≤ 5.5 V, 1/fMCK + 580 ns Note2 Cb = 100 pF, Rb = 3 kΩ tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V, 0 770 ns Cb = 50 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 ≤ 5.5 V, 0 1420 ns Cb = 100 pF, Rb = 3 kΩ Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). (Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 149 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Simplified I2C mode mode connection diagram (during communication at same potential) SDAr RL78 microcontroller SCLr VDD Rb SDA User device SCL SCLr Simplified I2C mode serial transfer timing (during communication at same potential) tLOW 1/fSCL tHIGH SDAr tHD:DAT tSU:DAT Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14), h: POM number (g = 0, 1, 4, 5, 7 to 9, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 150 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Transfer rate Reception 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 2.7 V ≤ EVDD0 < 4.0 V, Theoretical value of the 2.3 V ≤ Vb ≤ 2.7 V maximum transfer rate fCLK = 32 MHz, fMCK = fCLK MIN. MAX. fMCK/12 Note 1 2.6 fMCK/12 Note 1 2.6 2.4 V ≤ EVDD0 < 3.3 V, fMCK/12 Notes 1,2 1.6 V ≤ Vb ≤ 2.0 V Theoretical value of the 2.6 maximum transfer rate fCLK = 32 MHz, fMCK = fCLK Unit bps Mbps bps Mbps bps Mbps Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only. 2. The following conditions are required for low voltage interface when EVDD0 < VDD. 2.4 V ≤ EVDD0 < 2.7 V : MAX. 1.3 Mbps Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. 2. 3. Vb[V]: Communication line voltage q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 151 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. Transfer rate Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the maximum transfer rate Note 1 2.6 Note 2 bps Mbps Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.7 V ≤ EVDD0 < 4.0 V, Theoretical value of the 2.3 V ≤ Vb ≤ 2.7 V maximum transfer rate Note 3 1.2 Note 4 bps Mbps Cb = 50 pF, Rb = 2.7 kΩ, Vb = 2.3 V 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Theoretical value of the maximum transfer rate Note 5 0.43 Note 6 bps Mbps Cb = 50 pF, Rb = 5.5 kΩ, Vb = 1.6 V Notes 1. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V ≤ EVDD0 ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V Maximum transfer rate = 1 {−Cb × Rb × ln (1 − 2.2 Vb )} × 3 [bps] Baud rate error (theoretical value) = 1 Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2 Vb )} ( 1 Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 3. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 < 4.0 V and 2.4 V ≤ Vb ≤ 2.7 V Maximum transfer rate = 1 {−Cb × Rb × ln (1 − 2.0 Vb )} × 3 [bps] Baud rate error (theoretical value) = 1 Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.0 Vb )} ( 1 Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 152 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 5. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V Maximum transfer rate = 1 {−Cb × Rb × ln (1 − 1.5 Vb )} × 3 [bps] Baud rate error (theoretical value) = 1 Transfer rate × 2 − {−Cb × Rb × ln (1 − 1.5 Vb )} ( 1 Transfer rate ) × Number of transferred bits × 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 6. This value as an example is calculated when the conditions described in the “Conditions” column are met. Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. UART mode connection diagram (during communication at different potential) TxDq RL78 microcontroller Vb Rb Rx User device RxDq Tx R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 153 of 194 RL78/G13 TxDq 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance RxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance Remarks 1. 2. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 154 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. MAX. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 600 ns V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 1000 ns V, Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 2300 ns V, Cb = 30 pF, Rb = 5.5 kΩ SCKp high-level width tKH1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 150 ns Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 340 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 − 916 ns Cb = 30 pF, Rb = 5.5 kΩ SCKp low-level width tKL1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 24 ns Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 36 ns Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 − 100 ns Cb = 30 pF, Rb = 5.5 kΩ Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed two pages after the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 155 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit SIp setup time tSIK1 (to SCKp↑) Note SIp hold time tKSI1 (from SCKp↑) Note Delay time from SCKp↓ to SOp output Note tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ MIN. 162 354 958 38 38 38 MAX. ns ns ns ns ns ns 200 ns 390 ns 966 ns Note When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 156 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit SIp setup time tSIK1 (to SCKp↓) Note SIp hold time tKSI1 (from SCKp↓) Note Delay time from SCKp↑ to SOp output Note tKSO1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, Cb = 30 pF, Rb = 5.5 kΩ MIN. 88 88 220 38 38 38 MAX. ns ns ns ns ns ns 50 ns 50 ns 50 ns Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 157 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode connection diagram (during communication at different potential) SCKp RL78 SIp microcontroller SOp Vb Rb Vb Rb SCK SO User device SI Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 158 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp SIp tSIK1 tKSI1 Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKH1 tKCY1 tKL1 SCKp SIp tSIK1 tKSI1 Input data tKSO1 SOp Output data Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 00, 01, 02, 10, 12, 13), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 159 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit SCKp cycle time Note 1 tKCY2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 24 MHz < fMCK 20 MHz < fMCK ≤ 24 MHz 8 MHz < fMCK ≤ 20 MHz MIN. 28/fMCK 24/fMCK 20/fMCK MAX. ns ns ns 4 MHz < fMCK ≤ 8 MHz 16/fMCK ns fMCK ≤ 4 MHz 12/fMCK ns 2.7 V ≤ EVDD0 < 4.0 24 MHz < fMCK 40/fMCK ns V, 20 MHz < fMCK ≤ 24 MHz 32/fMCK ns 2.3 V ≤ Vb ≤ 2.7 V 16 MHz < fMCK ≤ 20 MHz 28/fMCK ns 8 MHz < fMCK ≤ 16 MHz 24/fMCK ns 4 MHz < fMCK ≤ 8 MHz 16/fMCK ns fMCK ≤ 4 MHz 12/fMCK ns 2.4 V ≤ EVDD0 < 3.3 24 MHz < fMCK 96/fMCK ns V, 20 MHz < fMCK ≤ 24 MHz 72/fMCK ns 1.6 V ≤ Vb ≤ 2.0 V 16 MHz < fMCK ≤ 20 MHz 64/fMCK ns 8 MHz < fMCK ≤ 16 MHz 52/fMCK ns 4 MHz < fMCK ≤ 8 MHz 32/fMCK ns fMCK ≤ 4 MHz 20/fMCK ns SCKp high-/low-level tKH2, 4.0 V ≤ EVDD0 ≤ 5.5 V, width tKL2 2.7 V ≤ Vb ≤ 4.0 V tKCY2/2 − 24 ns 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V tKCY2/2 − 36 ns 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Note 2 tKCY2/2 − 100 ns SIp setup time (to SCKp↑) Note2 tSIK2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V SIp hold time tKSI2 (from SCKp↑) Note 3 Delay time from SCKp↓ to SOp output Note 4 tKSO2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 30 pF, Rb = 1.4 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 30 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V Cb = 30 pF, Rb = 5.5 kΩ (Notes, Caution and Remarks are listed on the next page.) 1/fMCK + 40 ns 1/fMCK + 40 ns 1/fMCK + 60 ns 1/fMCK + 62 ns 2/fMCK + 240 ns 2/fMCK + 428 ns 2/fMCK + 1146 ns R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 160 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) SCKp RL78 microcontroller SIp SOp Vb Rb SCK SO User device SI Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13)) 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 161 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp SIp tSIK2 tKSI2 Input data tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp SIp tSIK2 tKSI2 Input data tKSO2 SOp Output data Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 162 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Unit Mode SCLr clock frequency Hold time when SCLr = “L” Hold time when SCLr = “H” MIN. MAX. fSCL 4.0 V ≤ EVDD0 ≤ 5.5 V, 400 Note 1 kHz 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 400 Note 1 kHz 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 100 Note 1 kHz 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 100 Note 1 kHz 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 100 Note 1 kHz 1.6 V ≤ Vb ≤ 2.0 V, Cb = 100 pF, Rb = 5.5 kΩ tLOW 4.0 V ≤ EVDD0 ≤ 5.5 V, 1200 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 1200 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 4600 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 4600 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 4650 ns 1.6 V ≤ Vb ≤ 2.0 V, Cb = 100 pF, Rb = 5.5 kΩ tHIGH 4.0 V ≤ EVDD0 ≤ 5.5 V, 620 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 500 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 2700 ns 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 2400 ns 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1830 ns 1.6 V ≤ Vb ≤ 2.0 V, Cb = 100 pF, Rb = 5.5 kΩ (Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 163 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Unit Mode MIN. MAX. Data setup time (reception) Data hold time (transmission) tSU:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, 1/fMCK + 340 ns 2.7 V ≤ Vb ≤ 4.0 V, Note 2 Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 1/fMCK + 340 ns 2.3 V ≤ Vb ≤ 2.7 V, Note 2 Cb = 50 pF, Rb = 2.7 kΩ 4.0 V ≤ EVDD0 ≤ 5.5 V, 1/fMCK + 760 ns 2.7 V ≤ Vb ≤ 4.0 V, Note 2 Cb = 100 pF, Rb = 2.8 kΩ 2.7 V ≤ EVDD0 < 4.0 V, 1/fMCK + 760 ns 2.3 V ≤ Vb ≤ 2.7 V, Note 2 Cb = 100 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 < 3.3 V, 1/fMCK + 570 ns 1.6 V ≤ Vb ≤ 2.0 V, Note 2 Cb = 100 pF, Rb = 5.5 kΩ tHD:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, 0 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 770 ns 2.7 V ≤ EVDD0 < 4.0 V, 0 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 770 ns 4.0 V ≤ EVDD0 ≤ 5.5 V, 0 2.7 V ≤ Vb ≤ 4.0 V, Cb = 100 pF, Rb = 2.8 kΩ 1420 ns 2.7 V ≤ EVDD0 < 4.0 V, 0 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.7 kΩ 1420 ns 2.4 V ≤ EVDD0 < 3.3 V, 0 1.6 V ≤ Vb ≤ 2.0 V, Cb = 100 pF, Rb = 5.5 kΩ 1215 ns Notes 1. The value must also be equal to or less than fMCK/4. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 164 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Simplified I2C mode connection diagram (during communication at different potential) SDAr RL78 microcontroller SCLr Vb Rb Vb Rb SDA User device SCL Simplified I2C mode serial transfer timing (during communication at different potential) tLOW 1/fSCL tHIGH SCLr SDAr tHD:DAT tSU:DAT Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 100pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remarks 1. Rb[Ω]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 165 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.5.2 Serial interface IICA (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit Standard Mode Fast Mode MIN. MAX. MIN. MAX. SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz − − 0 400 kHz Standard mode: fCLK ≥ 1 MHz 0 100 − − kHz Setup time of restart condition Hold timeNote 1 tSU:STA tHD:STA 4.7 0.6 μs 4.0 0.6 μs Hold time when SCLA0 = “L” tLOW 4.7 1.3 μs Hold time when SCLA0 = “H” tHIGH 4.0 0.6 μs Data setup time (reception) Data hold time (transmission)Note 2 tSU:DAT tHD:DAT 250 100 ns 0 3.45 0 0.9 μs Setup time of stop condition tSU:STO 4.0 0.6 μs Bus-free time tBUF 4.7 1.3 μs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 kΩ Fast mode: Cb = 320 pF, Rb = 1.1 kΩ SCLAn tLOW tR tHD:DAT tHD:STA SDAAn tBUF Stop Start condition condition Remark n = 0, 1 IICA serial transfer timing tHIGH tF tSU:DAT tSU:STA tHD:STA Restart condition tSU:STO Stop condition R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 166 of 194 RL78/G13 3.6 Analog Characteristics 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Reference voltage (+) = AVREFP Reference voltage (−) = Reference voltage (+) = VDD Input channel AVREFM Reference voltage (−) = VSS ANI0 to ANI14 Refer to 3.6.1 (1). Refer to 3.6.1 (3). ANI16 to ANI26 Refer to 3.6.1 (2). Internal reference voltage Refer to 3.6.1 (1). Temperature sensor output voltage Reference voltage (+) = VBGR Reference voltage (−) = AVREFM Refer to 3.6.1 (4). − (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI2 to ANI14, internal reference voltage, and temperature sensor output voltage (TA = −40 to +105°C, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Resolution Overall errorNote 1 Symbol RES AINL 10-bit resolution AVREFP = VDD Note 3 Conditions MIN. 8 2.4 V ≤ AVREFP ≤ 5.5 V TYP. 1.2 MAX. 10 ±3.5 Unit bit LSB Conversion time tCONV Zero-scale errorNotes 1, 2 EZS Full-scale errorNotes 1, 2 EFS Integral linearity error ILE Note 1 Differential linearity error DLE Note 1 Analog input voltage VAIN 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.125 39 Target pin: ANI2 to ANI14 2.7 V ≤ VDD ≤ 5.5 V 3.1875 39 2.4 V ≤ VDD ≤ 5.5 V 17 39 10-bit resolution 3.6 V ≤ VDD ≤ 5.5 V 2.375 39 Target pin: Internal reference 2.7 V ≤ VDD ≤ 5.5 V 3.5625 39 voltage, and temperature sensor output voltage (HS 2.4 V ≤ VDD ≤ 5.5 V 17 39 (high-speed main) mode) 10-bit resolution AVREFP = VDD Note 3 2.4 V ≤ AVREFP ≤ 5.5 V ±0.25 10-bit resolution AVREFP = VDD Note 3 2.4 V ≤ AVREFP ≤ 5.5 V ±0.25 10-bit resolution AVREFP = VDD Note 3 2.4 V ≤ AVREFP ≤ 5.5 V ±2.5 10-bit resolution AVREFP = VDD Note 3 2.4 V ≤ AVREFP ≤ 5.5 V ±1.5 ANI2 to ANI14 Internal reference voltage output (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) 0 AVREFP VBGR Note 4 V Note 4 TMPS25 μs μs μs μs μs μs %FSR %FSR LSB LSB V V V (Notes are listed on the next page.) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 167 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 168 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI26 (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Resolution Overall errorNote 1 Symbol Conditions RES AINL 10-bit resolution 2.4 V ≤ AVREFP ≤ 5.5 EVDD0 ≤ AVREFP = VDD Notes 3, 4 V MIN. 8 Conversion time tCONV Zero-scale errorNotes 1, 2 EZS 10-bit resolution Target pin : ANI16 to ANI26 10-bit resolution EVDD0 ≤ AVREFP = VDD Notes 3, 4 3.6 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 2.4 V ≤ VDD ≤ 5.5 V 2.4 V ≤ AVREFP ≤ 5.5 V 2.125 3.1875 17 Full-scale errorNotes 1, 2 EFS 10-bit resolution EVDD0 ≤ AVREFP = VDD Notes 3, 4 2.4 V ≤ AVREFP ≤ 5.5 V Integral linearity errorNote ILE 1 10-bit resolution 2.4 V ≤ AVREFP ≤ 5.5 EVDD0 ≤ AVREFP = VDD Notes 3, 4 V Differential linearity error DLE Note 1 10-bit resolution 2.4 V ≤ AVREFP ≤ 5.5 EVDD0 ≤ AVREFP = VDD Notes 3, 4 V Analog input voltage VAIN ANI16 to ANI26 0 TYP. 1.2 MAX. Unit 10 bit ±5.0 LSB 39 39 39 ±0.35 μs μs μs %FSR ±0.35 %FSR ±3.5 LSB ±2.0 LSB AVREFP V and EVDD0 Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. When AVREFP < EVDD0 ≤ VDD, the MAX. values are as follows. Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 169 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0), target pin : ANI0 to ANI14, ANI16 to ANI26, internal reference voltage, and temperature sensor output voltage (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS) Parameter Symbol Conditions MIN. Resolution Overall errorNote 1 RES AINL 10-bit resolution 8 2.4 V ≤ VDD ≤ 5.5 V Conversion time tCONV 10-bit resolution Target pin: ANI0 to ANI14, ANI16 to ANI26 3.6 V ≤ VDD ≤ 5.5 V 2.125 2.7 V ≤ VDD ≤ 5.5 V 3.1875 2.4 V ≤ VDD ≤ 5.5 V 17 Zero-scale errorNotes 1, 2 EZS Full-scale errorNotes 1, 2 EFS Integral linearity errorNote ILE 1 10-bit resolution Target pin: Internal reference voltage, and temperature sensor output voltage (HS (high-speed main) mode) 3.6 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 5.5 V 2.4 V ≤ VDD ≤ 5.5 V 2.375 3.5625 17 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V TYP. 1.2 MAX. Unit 10 bit ±7.0 LSB 39 μs 39 μs 39 μs 39 μs 39 μs 39 μs ±0.60 ±0.60 ±4.0 %FSR %FSR LSB Differential linearity error DLE Note 1 10-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ±2.0 LSB Analog input voltage VAIN ANI0 to ANI14 ANI16 to ANI26 Internal reference voltage output (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) Temperature sensor output voltage (2.4 V ≤ VDD ≤ 5.5 V, HS (high-speed main) mode) 0 VDD V 0 EVDD0 V VBGR Note 3 V V Note 3 TMPS25 V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 170 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI26 (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (−) = AVREFM Note 4 = 0 V, HS (high-speed main) mode) Parameter Resolution Conversion time Zero-scale errorNotes 1, 2 Integral linearity errorNote 1 Differential linearity error Note 1 Analog input voltage Symbol Conditions RES tCONV 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V EZS 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V ILE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V DLE 8-bit resolution 2.4 V ≤ VDD ≤ 5.5 V VAIN MIN. 17 0 TYP. MAX. Unit 8 bit 39 μs ±0.60 %FSR ±2.0 LSB ±1.0 VBGR Note 3 LSB V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics. 4. When reference voltage (−) = VSS, the MAX. values are as follows. Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (−) = AVREFM. Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (−) = AVREFM. Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (−) = AVREFM. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 171 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.6.2 Temperature sensor/internal reference voltage characteristics (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the temperature Operation stabilization wait time tAMP MIN. 1.38 5 TYP. 1.05 1.45 −3.6 MAX. 1.5 Unit V V mV/°C μs 3.6.3 POR circuit characteristics (TA = −40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage VPOR Power supply rise time 1.45 1.51 1.57 V VPDR Power supply fall time 1.44 1.50 1.56 V Minimum pulse width TPW 300 μs Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW Supply voltage (VDD) VPOR VPDR or 0.7 V R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 172 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = −40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Detection voltage Parameter Supply voltage level Minimum pulse width Detection delay time Symbol Conditions VLVD0 Power supply rise time Power supply fall time VLVD1 Power supply rise time Power supply fall time VLVD2 Power supply rise time Power supply fall time VLVD3 Power supply rise time Power supply fall time VLVD4 Power supply rise time Power supply fall time VLVD5 Power supply rise time Power supply fall time VLVD6 Power supply rise time Power supply fall time VLVD7 Power supply rise time Power supply fall time tLW MIN. TYP. MAX. Unit 3.90 4.06 4.22 V 3.83 3.98 4.13 V 3.60 3.75 3.90 V 3.53 3.67 3.81 V 3.01 3.13 3.25 V 2.94 3.06 3.18 V 2.90 3.02 3.14 V 2.85 2.96 3.07 V 2.81 2.92 3.03 V 2.75 2.86 2.97 V 2.70 2.81 2.92 V 2.64 2.75 2.86 V 2.61 2.71 2.81 V 2.55 2.65 2.75 V 2.51 2.61 2.71 V 2.45 2.55 2.65 V 300 μs 300 μs LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Interrupt and reset VLVDD0 mode VLVDD1 VLVDD2 VLVDD3 Conditions VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage LVIS1, LVIS0 = 1, 0 Rising release reset voltage Falling interrupt voltage LVIS1, LVIS0 = 0, 1 Rising release reset voltage Falling interrupt voltage LVIS1, LVIS0 = 0, 0 Rising release reset voltage Falling interrupt voltage MIN. TYP. MAX. Unit 2.64 2.75 2.86 V 2.81 2.92 3.03 V 2.75 2.86 2.97 V 2.90 3.02 3.14 V 2.85 2.96 3.07 V 3.90 4.06 4.22 V 3.83 3.98 4.13 V 3.6.5 Power supply voltage rising slope characteristics (TA = −40 to +105°C, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply voltage rising slope SVDD 54 V/ms Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 3.4 AC Characteristics. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 173 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +105°C, VSS = 0 V) Parameter Data retention supply voltage Symbol VDDDR Conditions MIN. TYP. MAX. Unit 1.44Note 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected. STOP mode Data retention mode Operation mode VDD STOP instruction execution Standby release signal (interrupt request) VDDDR 3.8 Flash Memory Programming Characteristics (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Symbol Conditions CPU/peripheral hardware clock fCLK frequency 2.4 V ≤ VDD ≤ 5.5 V Number of code flash rewrites Notes 1,2,3 Cerwr Retained for 20 years TA = 85°C MIN. 1 TYP. MAX. 32 Unit MHz 1,000 Times Number of data flash rewrites Notes 1,2,3 Retained for 1 years Retained for 5 years TA = 25°C TA = 85°C 1,000,000 100,000 Retained for 20 years TA = 85°C 10,000 Notes 1. 2. 3. 1 erase + 1 write after the erase is regarded as 1 rewrite.The retaining years are until next rewrite after the rewrite. When using flash memory programmer and Renesas Electronics self programming library. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. 3.9 Dedicated Flash Memory Programmer Communication (UART) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Transfer rate Symbol Conditions During serial programming MIN. TYP. MAX. Unit 115,200 1,000,000 bps R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 174 of 194 RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.10 Timing Specs for Switching Flash Memory Programming Modes (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Time to complete the communication for the initial setting after the external reset is released tSUINIT POR and LVD reset must be released before the external reset is released. 100 ms Time to release the external reset tSU POR and LVD reset must be released before 10 μs after the TOOL0 pin is set to the the external reset is released. low level Time to hold the TOOL0 pin at the tHD POR and LVD reset must be released before 1 ms low level after the external reset is the external reset is released. released (excluding the processing time of the firmware to control the flash memory) <1> <2> <3> <4> RESET TOOL0 723 µs + tHD processing time 00H reception (TOOLRxD, TOOLTxD mode) tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset is released (POR and LVD reset must be released before the external reset is released.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is released during this period. tSU: Time to release the external reset after the TOOL0 pin is set to the low level tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the processing time of the firmware to control the flash memory) R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 175 of 194 RL78/G13 4. PACKAGE DRAWINGS 4. PACKAGE DRAWINGS 4.1 20-pin Products R5F1006AASP, R5F1006CASP, R5F1006DASP, R5F1006EASP R5F1016AASP, R5F1016CASP, R5F1016DASP, R5F1016EASP R5F1006ADSP, R5F1006CDSP, R5F1006DDSP, R5F1006EDSP R5F1016ADSP, R5F1016CDSP, R5F1016DDSP, R5F1016EDSP R5F1006AGSP, R5F1006CGSP, R5F1006DGSP, R5F1006EGSP JEITA Package Code P-LSSOP20-0300-0.65 RENESAS Code PLSP0020JC-A Previous Code S20MC-65-5A4-3 MASS (TYP.) [g] 0.12 20 11 detail of lead end F G T 1 10 A P L E U H I J S NS C K D MM B NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 6.65±0.15 0.475 MAX. 0.65 (T.P.) 0.24+−00..0087 0.1±0.05 1.3±0.1 1.2 8.1±0.2 6.1±0.2 1.0±0.2 0.17±0.03 0.5 0.13 0.10 3° +5° −3° 0.25 0.6±0.15 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 176 of 194 RL78/G13 4. PACKAGE DRAWINGS 4.2 24-pin Products R5F1007AANA, R5F1007CANA, R5F1007DANA, R5F1007EANA R5F1017AANA, R5F1017CANA, R5F1017DANA, R5F1017EANA R5F1007ADNA, R5F1007CDNA, R5F1007DDNA, R5F1007EDNA R5F1017ADNA, R5F1017CDNA, R5F1017DDNA, R5F1017EDNA R5F1007AGNA, R5F1007CGNA, R5F1007DGNA, R5F1007EGNA JEITA Package Code P-HWQFN24-4x4-0.50 RENESAS Code PWQN0024KE-A Previous Code P24K8-50-CAB-1 MASS (TYP.) [g] 0.04 D DETAIL OF A PART E A S A S 1 24 B 19 18 Lp yS D2 A 6 7 EXPOSED DIE PAD E2 ITEM D E A b e Lp x y (UNIT:mm) DIMENSIONS 4.00 ±0.05 4.00 ±0.05 0.75 ±0.05 0.25 + − 0.05 0.07 0.50 0.40 ±0.10 0.05 0.05 12 13 e b x M S AB ITEM D2 E2 MIN NOM MAX MIN NOM MAX EXPOSED DIE PAD A 2.45 2.50 2.55 2.45 2.50 2.55 VARIATIONS 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 177 of 194 RL78/G13 4.3 25-pin Products R5F1008AALA, R5F1008CALA, R5F1008DALA, R5F1008EALA R5F1018AALA, R5F1018CALA, R5F1018DALA, R5F1018EALA R5F1008ADLA, R5F1008CDLA, R5F1008DDLA, R5F1008EDLA R5F1018ADLA, R5F1018CDLA, R5F1018DDLA, R5F1018EDLA 4. PACKAGE DRAWINGS JEITA Package Code P-WFLGA25-3x3-0.50 RENESAS Code PWLG0025KA-A Previous Code P25FC-50-2N2-2 MASS (TYP.) [g] 0.01 21x b x M S AB ZD D wSA ZE A e B E C 5 4 3 2.27 2 1 INDEX MARK y1 S A wSB E DCB A 2.27 D INDEX MARK S yS DETAIL OF C PART DETAIL OF D PART R0.17±0.05 0.43±0.05 R0.12±0.05 0.33±0.05 0.50±0.05 0.365±0.05 b (LAND PAD) 0.34±0.05 (APERTURE OF SOLDER RESIST) 0.365±0.05 0.50±0.05 0.33±0.05 0.43±0.05 R0.165±0.05 R0.215±0.05 ITEM D E w e A b x y y1 ZD ZE (UNIT:mm) DIMENSIONS 3.00±0.10 3.00±0.10 0.20 0.50 0.69±0.07 0.24±0.05 0.05 0.08 0.20 0.50 0.50 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 178 of 194 RL78/G13 4.4 30-pin Products 4. PACKAGE DRAWINGS R5F100AAASP, R5F100ACASP, R5F100ADASP, R5F100AEASP, R5F100AFASP, R5F100AGASP R5F101AAASP, R5F101ACASP, R5F101ADASP, R5F101AEASP, R5F101AFASP, R5F101AGASP R5F100AADSP, R5F100ACDSP, R5F100ADDSP, R5F100AEDSP, R5F100AFDSP, R5F100AGDSP R5F101AADSP, R5F101ACDSP, R5F101ADDSP, R5F101AEDSP, R5F101AFDSP, R5F101AGDSP R5F100AAGSP, R5F100ACGSP, R5F100ADGSP,R5F100AEGSP, R5F100AFGSP, R5F100AGGSP JEITA Package Code P-LSSOP30-0300-0.65 RENESAS Code PLSP0030JB-B Previous Code S30MC-65-5A4-3 MASS (TYP.) [g] 0.18 30 16 detail of lead end F G T 1 15 A P L E U S C NS B D MM K NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. H I J ITEM A B C D E F G H I J K L M N P T U MILLIMETERS 9.85±0.15 0.45 MAX. 0.65 (T.P.) 0.24+−00..0087 0.1±0.05 1.3±0.1 1.2 8.1±0.2 6.1±0.2 1.0±0.2 0.17±0.03 0.5 0.13 0.10 3° +5° −3° 0.25 0.6±0.15 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 179 of 194 RL78/G13 4.5 32-pin Products 4. PACKAGE DRAWINGS R5F100BAANA, R5F100BCANA, R5F100BDANA, R5F100BEANA, R5F100BFANA, R5F100BGANA R5F101BAANA, R5F101BCANA, R5F101BDANA, R5F101BEANA, R5F101BFANA, R5F101BGANA R5F100BADNA, R5F100BCDNA, R5F100BDDNA, R5F100BEDNA, R5F100BFDNA, R5F100BGDNA R5F101BADNA, R5F101BCDNA, R5F101BDDNA, R5F101BEDNA, R5F101BFDNA, R5F101BGDNA R5F100BAGNA, R5F100BCGNA, R5F100BDGNA,R5F100BEGNA, R5F100BFGNA, R5F100BGGNA JEITA Package Code P-HWQFN32-5x5-0.50 RENESAS Code PWQN0032KB-A Previous Code P32K8-50-3B4-3 MASS (TYP.) [g] 0.06 D E DETAIL OF A PART A S A S 1 32 B 25 24 Lp yS D2 A 8 9 EXPOSED DIE PAD E2 ITEM D E A b e Lp x y (UNIT:mm) DIMENSIONS 5.00 ±0.05 5.00 ±0.05 0.75 ±0.05 0.25 + − 0.05 0.07 0.50 0.40 ±0.10 0.05 0.05 16 17 e b x M S AB ITEM D2 E2 MIN NOM MAX MIN NOM MAX EXPOSED DIE PAD A 3.45 3.50 3.55 3.45 3.50 3.55 VARIATIONS 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 180 of 194 RL78/G13 4.6 36-pin Products 4. PACKAGE DRAWINGS R5F100CAALA, R5F100CCALA, R5F100CDALA, R5F100CEALA, R5F100CFALA, R5F100CGALA R5F101CAALA, R5F101CCALA, R5F101CDALA, R5F101CEALA, R5F101CFALA, R5F101CGALA R5F100CADLA, R5F100CCDLA, R5F100CDDLA, R5F100CEDLA, R5F100CFDLA, R5F100CGDLA R5F101CADLA, R5F101CCDLA, R5F101CDDLA, R5F101CEDLA, R5F101CFDLA, R5F101CGDLA JEITA Package Code P-WFLGA36-4x4-0.50 RENESAS Code PWLG0036KA-A Previous Code P36FC-50-AA4-2 MASS (TYP.) [g] 0.023 32x b x M S AB ZD D wSA ZE A e E INDEX MARK y1 S yS wSB A S 6 5 B 4 2.90 3 2 C 1 D F EDCB A E 2.90 DETAIL C φb (LAND PAD) φ 0.34±0.05 (APERTURE OF SOLDER RESIST) DETAIL D 0.70 ±0.05 R0.17± 0.05 0.55 ±0.05 R0.12 ±0.05 0.75 0.55 DETAIL E R0.17 ±0.05 0.70 ±0.05 R0.12 ±0.05 0.55 ±0.05 0.75 0.55 0.55 0.75 0.55 ± 0.05 0.70± 0.05 0.55 0.75 0.55 ± 0.05 0.70±0.05 R0.275 ± 0.05 R0.35 ± 0.05 ITEM D E w e A b x y y1 ZD ZE (UNIT:mm) DIMENSIONS 4.00±0.10 4.00±0.10 0.20 0.50 0.69±0.07 0.24±0.05 0.05 0.08 0.20 0.75 0.75 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 181 of 194 RL78/G13 4.7 40-pin Products 4. PACKAGE DRAWINGS R5F100EAANA, R5F100EHANA R5F101EAANA, R5F101EHANA R5F100EADNA, R5F100EHDNA R5F101EADNA, R5F101EHDNA R5F100EAGNA, R5F100EHGNA R5F100ECANA, R5F101ECANA, R5F100ECDNA, R5F101ECDNA, R5F100ECGNA, R5F100EDANA, R5F101EDANA, R5F100EDDNA, R5F101EDDNA, R5F100EDGNA, R5F100EEANA, R5F101EEANA, R5F100EEDNA, R5F101EEDNA, R5F100EEGNA, R5F100EFANA, R5F101EFANA, R5F100EFDNA, R5F101EFDNA, R5F100EFGNA, R5F100EGANA, R5F101EGANA, R5F100EGDNA, R5F101EGDNA, R5F100EGGNA, JEITA Package Code P-HWQFN40-6x6-0.50 RENESAS Code PWQN0040KC-A Previous Code P40K8-50-4B4-3 MASS (TYP.) [g] 0.09 D DETAIL OF A PART E A S 1 40 B A S yS D2 A 10 11 EXPOSED DIE PAD E2 ITEM D E A b e Lp x y (UNIT:mm) DIMENSIONS 6.00 ±0.05 6.00 ±0.05 0.75 ±0.05 0.25 + − 0.05 0.07 0.50 0.40 ±0.10 0.05 0.05 31 30 Lp 20 21 e b x M S AB R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 ITEM D2 E2 MIN NOM MAX MIN NOM MAX EXPOSED DIE PAD A 4.45 4.50 4.55 4.45 4.50 4.55 VARIATIONS 2012 Renesas Electronics Corporation. All rights reserved. Page 182 of 194 RL78/G13 4.8 44-pin Products 4. PACKAGE DRAWINGS R5F100FAAFP, R5F100FCAFP, R5F100FDAFP, R5F100FEAFP, R5F100FHAFP, R5F100FJAFP, R5F100FKAFP, R5F100FLAFP R5F101FAAFP, R5F101FCAFP, R5F101FDAFP, R5F101FEAFP, R5F101FHAFP, R5F101FJAFP, R5F101FKAFP, R5F101FLAFP R5F100FADFP, R5F100FCDFP, R5F100FDDFP, R5F100FEDFP, R5F100FHDFP, R5F100FJDFP, R5F100FKDFP, R5F100FLDFP R5F101FADFP, R5F101FCDFP, R5F101FDDFP, R5F101FEDFP, R5F101FHDFP, R5F101FJDFP, R5F101FKDFP, R5F101FLDFP R5F100FAGFP, R5F100FCGFP, R5F100FDGFP, R5F100FEGFP, R5F100FHGFP, R5F100FJGFP R5F100FFAFP, R5F101FFAFP, R5F100FFDFP, R5F101FFDFP, R5F100FFGFP, R5F100FGAFP, R5F101FGAFP, R5F100FGDFP, R5F101FGDFP, R5F100FGGFP, JEITA Package Code P-LQFP44-10x10-0.80 RENESAS Code PLQP0044GC-A Previous Code P44GB-80-UES-2 MASS (TYP.) [g] 0.36 HD D 33 34 23 22 detail of lead end A3 c E HE θ L Lp L1 44 1 ZE ZD 12 11 e b xM S yS A A2 S A1 NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. ITEM D E HD HE A A1 A2 A3 b c L Lp L1 θ e x y ZD ZE (UNIT:mm) DIMENSIONS 10.00±0.20 10.00±0.20 12.00±0.20 12.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 0.37 +0.08 −0.07 0.145 +0.055 −0.045 0.50 0.60±0.15 1.00±0.20 3° +5° −3° 0.80 0.20 0.10 1.00 1.00 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 2012 Renesas Electronics Corporation. All rights reserved. Page 183 of 194 RL78/G13 4.9 48-pin Products 4. PACKAGE DRAWINGS R5F100GAAFB, R5F100GCAFB, R5F100GDAFB, R5F100GEAFB, R5F100GHAFB, R5F100GJAFB, R5F100GKAFB, R5F100GLAFB R5F101GAAFB, R5F101GCAFB, R5F101GDAFB, R5F101GEAFB, R5F101GHAFB, R5F101GJAFB, R5F101GKAFB, R5F101GLAFB R5F100GADFB, R5F100GCDFB, R5F100GDDFB, R5F100GEDFB, R5F100GHDFB, R5F100GJDFB, R5F100GKDFB, R5F100GLDFB R5F101GADFB, R5F101GCDFB, R5F101GDDFB, R5F101GEDFB, R5F101GHDFB, R5F101GJDFB, R5F101GKDFB, R5F101GLDFB R5F100GAGFB, R5F100GCGFB, R5F100GDGFB, R5F100GEGFB, R5F100GHGFB, R5F100GJGFB R5F100GFAFB, R5F101GFAFB, R5F100GFDFB, R5F101GFDFB, R5F100GFGFB, R5F100GGAFB, R5F101GGAFB, R5F100GGDFB, R5F101GGDFB, R5F100GGGFB, JEITA Package Code P-LFQFP48-7x7-0.50 RENESAS Code PLQP0048KF-A Previous Code P48GA-50-8EU-1 MASS (TYP.) [g] 0.16 HD D 36 37 25 24 detail of lead end A3 c E HE θ L Lp L1 48 1 ZE ZD 13 12 e b xM S yS NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. A A2 A1 (UNIT:mm) ITEM D E DIMENSIONS 7.00±0.20 7.00±0.20 HD 9.00±0.20 HE 9.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 0.25 b 0.22±0.05 c 0.145 +0.055 −0.045 L 0.50 S Lp 0.60±0.15 L1 1.00±0.20 θ 3° +5° −3° e 0.50 x 0.08 y 0.08 ZD 0.75 ZE 0.75 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 184 of 194 RL78/G13 4. PACKAGE DRAWINGS R5F100GAANA, R5F100GCANA, R5F100GDANA, R5F100GEANA, R5F100GFANA, R5F100GGANA, R5F100GHANA, R5F100GJANA, R5F100GKANA, R5F100GLANA R5F101GAANA, R5F101GCANA, R5F101GDANA, R5F101GEANA, R5F101GFANA, R5F101GGANA, R5F101GHANA, R5F101GJANA, R5F101GKANA, R5F101GLANA R5F100GADNA, R5F100GCDNA, R5F100GDDNA, R5F100GEDNA, R5F100GFDNA, R5F100GGDNA, R5F100GHDNA, R5F100GJDNA, R5F100GKDNA, R5F100GLDNA R5F101GADNA, R5F101GCDNA, R5F101GDDNA, R5F101GEDNA, R5F101GFDNA, R5F101GGDNA, R5F101GHDNA, R5F101GJDNA, R5F101GKDNA, R5F101GLDNA R5F100GAGNA, R5F100GCGNA, R5F100GDGNA, R5F100GEGNA, R5F100GFGNA, R5F100GGGNA, R5F100GHGNA, R5F100GJGNA JEITA Package Code P-HWQFN48-7x7-0.50 RENESAS Code PWQN0048KB-A Previous Code P48K8-50-5B4-4 MASS (TYP.) [g] 0.13 D DETAIL OF A PART E A S 1 48 B 37 36 Lp A S yS D2 A 12 13 EXPOSED DIE PAD ITEM D E A b e Lp x y (UNIT:mm) DIMENSIONS 7.00 ±0.05 7.00 ±0.05 0.75 ±0.05 0.25 + − 0.05 0.07 0.50 0.40 ±0.10 0.05 0.05 E2 24 25 e b x M S AB ITEM D2 E2 MIN NOM MAX MIN NOM MAX EXPOSED DIE PAD A 5.45 5.50 5.55 5.45 5.50 5.55 VARIATIONS 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 185 of 194 RL78/G13 4.10 52-pin Products 4. PACKAGE DRAWINGS R5F100JCAFA, R5F100JDAFA, R5F100JEAFA, R5F100JFAFA, R5F100JGAFA, R5F100JHAFA, R5F100JJAFA, R5F100JKAFA, R5F100JLAFA R5F101JCAFA, R5F101JDAFA, R5F101JEAFA, R5F101JFAFA, R5F101JGAFA, R5F101JHAFA, R5F101JJAFA, R5F101JKAFA, R5F101JLAFA R5F100JCDFA, R5F100JDDFA, R5F100JEDFA, R5F100JFDFA, R5F100JGDFA, R5F100JHDFA, R5F100JJDFA, R5F100JKDFA, R5F100JLDFA R5F101JCDFA, R5F101JDDFA, R5F101JEDFA, R5F101JFDFA, R5F101JGDFA, R5F101JHDFA, R5F101JJDFA, R5F101JKDFA, R5F101JLDFA R5F100JCGFA, R5F100JDGFA, R5F100JEGFA, R5F100JFGFA, R5F100JGGFA, R5F100JHGFA, R5F100JJGFA JEITA Package Code P-LQFP52-10x10-0.65 RENESAS Code PLQP0052JA-A Previous Code P52GB-65-GBS-1 MASS (TYP.) [g] 0.3 HD 2 D 39 40 27 26 detail of lead end c 1 E HE L 52 1 14 13 e 3 b xM A A2 y A1 NOTE 1.Dimensions “ 1” and “ 2” do not include mold flash. 2.Dimension “ 3” does not include trim offset. ITEM D E HD HE A A1 A2 b c L e x y (UNIT:mm) DIMENSIONS 10.00±0.10 10.00±0.10 12.00±0.20 12.00±0.20 1.70 MAX. 0.10±0.05 1.40 0.32±0.05 0.145±0.055 0.50±0.15 0° to 8° 0.65 0.13 0.10 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 186 of 194 RL78/G13 4.11 64-pin Products 4. PACKAGE DRAWINGS R5F100LCAFA, R5F100LDAFA, R5F100LEAFA, R5F100LFAFA, R5F100LGAFA, R5F100LHAFA, R5F100LJAFA, R5F100LKAFA, R5F100LLAFA R5F101LCAFA, R5F101LDAFA, R5F101LEAFA, R5F101LFAFA, R5F101LGAFA, R5F101LHAFA, R5F101LJAFA, R5F101LKAFA, R5F101LLAFA R5F100LCDFA, R5F100LDDFA, R5F100LEDFA, R5F100LFDFA, R5F100LGDFA, R5F100LHDFA, R5F100LJDFA, R5F100LKDFA, R5F100LLDFA R5F101LCDFA, R5F101LDDFA, R5F101LEDFA, R5F101LFDFA, R5F101LGDFA, R5F101LHDFA, R5F101LJDFA, R5F101LKDFA, R5F101LLDFA R5F100LCGFA, R5F100LDGFA, R5F100LEGFA, R5F100LFGFA, R5F100LGGFA, R5F100LHGFA, R5F100LJGFA JEITA Package Code P-LQFP64-12x12-0.65 RENESAS Code PLQP0064JA-A Previous Code P64GK-65-UET-2 MASS (TYP.) [g] 0.51 HD D 48 49 33 32 detail of lead end A3 c E HE θ L Lp L1 64 1 ZE ZD 17 16 e b xM S yS NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. A A2 A1 (UNIT:mm) ITEM DIMENSIONS D 12.00±0.20 E 12.00±0.20 HD 14.00±0.20 HE 14.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 0.25 b 0.32 +0.08 −0.07 c 0.145 +0.055 −0.045 L 0.50 S Lp 0.60±0.15 L1 1.00±0.20 θ 3° +5° −3° e 0.65 x 0.13 y 0.10 ZD 1.125 ZE 1.125 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 2012 Renesas Electronics Corporation. All rights reserved. Page 187 of 194 RL78/G13 4. PACKAGE DRAWINGS R5F100LCAFB, R5F100LDAFB, R5F100LEAFB, R5F100LFAFB, R5F100LGAFB, R5F100LHAFB, R5F100LJAFB, R5F100LKAFB, R5F100LLAFB R5F101LCAFB, R5F101LDAFB, R5F101LEAFB, R5F101LFAFB, R5F101LGAFB, R5F101LHAFB, R5F101LJAFB, R5F101LKAFB, R5F101LLAFB R5F100LCDFB, R5F100LDDFB, R5F100LEDFB, R5F100LFDFB, R5F100LGDFB, R5F100LHDFB, R5F100LJDFB, R5F100LKDFB, R5F100LLDFB R5F101LCDFB, R5F101LDDFB, R5F101LEDFB, R5F101LFDFB, R5F101LGDFB, R5F101LHDFB, R5F101LJDFB, R5F101LKDFB, R5F101LLDFB R5F100LCGFB, R5F100LDGFB, R5F100LEGFB, R5F100LFGFB, R5F100LGGFB, R5F100LHGFB, R5F100LJGFB JEITA Package Code P-LFQFP64-10x10-0.50 RENESAS Code PLQP0064KF-A Previous Code P64GB-50-UEU-2 MASS (TYP.) [g] 0.35 HD D 48 49 33 32 detail of lead end A3 c E HE θ L Lp L1 64 1 ZE ZD 17 16 e b xM S yS NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. A A2 A1 (UNIT:mm) ITEM DIMENSIONS D 10.00±0.20 E 10.00±0.20 HD 12.00±0.20 HE 12.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 0.25 b 0.22±0.05 c 0.145 +0.055 −0.045 L 0.50 Lp 0.60±0.15 S L1 1.00±0.20 θ 3° +5° −3° e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 188 of 194 RL78/G13 4. PACKAGE DRAWINGS R5F100LCABG, R5F100LJABG R5F101LCABG, R5F101LJABG R5F100LCDBG, R5F100LJDBG R5F101LCDBG, R5F101LJDBG R5F100LDABG, R5F101LDABG, R5F100LDDBG, R5F101LDDBG, R5F100LEABG, R5F101LEABG, R5F100LEDBG, R5F101LEDBG, R5F100LFABG, R5F101LFABG, R5F100LFDBG, R5F101LFDBG, R5F100LGABG, R5F101LGABG, R5F100LGDBG, R5F101LGDBG, R5F100LHABG, R5F101LHABG, R5F100LHDBG, R5F101LHDBG, JEITA Package Code P-VFBGA64-4x4-0.40 RENESAS Code PVBG0064LA-A Previous Code P64F1-40-AA2-2 MASS (TYP.) [g] 0.03 D w S A ZE B E INDEX MARK w SB yS y1 S A A2 S e A1 b xMS AB ZD A 8 7 6 5 4 3 2 1 HGF EDCBA INDEX MARK ITEM D E w A A1 A2 e b x y y1 ZD ZE (UNIT:mm) DIMENSIONS 4.00±0.10 4.00±0.10 0.15 0.89±0.10 0.20±0.05 0.69 0.40 0.25±0.05 0.05 0.08 0.20 0.60 0.60 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 2012 Renesas Electronics Corporation. All rights reserved. Page 189 of 194 RL78/G13 4.12 80-pin Products 4. PACKAGE DRAWINGS R5F100MFAFA, R5F100MGAFA, R5F100MHAFA, R5F100MJAFA, R5F100MKAFA, R5F100MLAFA R5F101MFAFA, R5F101MGAFA, R5F101MHAFA, R5F101MJAFA, R5F101MKAFA, R5F101MLAFA R5F100MFDFA, R5F100MGDFA, R5F100MHDFA, R5F100MJDFA, R5F100MKDFA, R5F100MLDFA R5F101MFDFA, R5F101MGDFA, R5F101MHDFA, R5F101MJDFA, R5F101MKDFA, R5F101MLDFA R5F100MFGFA, R5F100MGGFA, R5F100MHGFA, R5F100MJGFA JEITA Package Code P-LQFP80-14x14-0.65 RENESAS Code PLQP0080JB-E Previous Code P80GC-65-UBT-2 MASS (TYP.) [g] 0.69 60 61 B HD D A 41 40 80 1 ZE ZD 21 20 e bp x M S AB yS detail of lead end L1 A3 c L Lp E HE Referance Dimension in Millimeters Symbol Min Nom Max D 13.80 14.00 14.20 E 13.80 14.00 14.20 HD 17.00 17.20 17.40 HE 17.00 17.20 17.40 A 1.70 A1 0.05 0.125 0.20 A2 1.35 1.40 1.45 A3 0.25 bp 0.26 0.32 0.38 c 0.10 0.145 0.20 A A2 S L 0.80 Lp 0.736 0.886 1.036 L1 1.40 1.60 1.80 0° 3° 8° e 0.65 x 0.13 A1 y 0.10 ZD 0.825 ZE 0.825 2012 Renesas ElectronicsCorporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 190 of 194 RL78/G13 4. PACKAGE DRAWINGS R5F100MFAFB, R5F100MGAFB, R5F100MHAFB, R5F100MJAFB, R5F100MKAFB, R5F100MLAFB R5F101MFAFB, R5F101MGAFB, R5F101MHAFB, R5F101MJAFB, R5F101MKAFB, R5F101MLAFB R5F100MFDFB, R5F100MGDFB, R5F100MHDFB, R5F100MJDFB, R5F100MKDFB, R5F100MLDFB R5F101MFDFB, R5F101MGDFB, R5F101MHDFB, R5F101MJDFB, R5F101MKDFB, R5F101MLDFB R5F100MFGFB, R5F100MGGFB, R5F100MHGFB, R5F100MJGFB JEITA Package Code P-LFQFP80-12x12-0.50 RENESAS Code PLQP0080KE-A Previous Code P80GK-50-8EU-2 MASS (TYP.) [g] 0.53 HD D 60 61 41 40 detail of lead end A3 c 80 1 ZE ZD 21 20 e b xM S yS NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. E HE A A2 A1 θ S L Lp L1 ITEM D E HD HE A A1 A2 A3 b c L Lp L1 θ e x y ZD ZE (UNIT:mm) DIMENSIONS 12.00±0.20 12.00±0.20 14.00±0.20 14.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 0.22±0.05 0.145 +0.055 −0.045 0.50 0.60±0.15 1.00±0.20 3° +5° −3° 0.50 0.08 0.08 1.25 1.25 2012 Renesas Electronics Corporation. All rights reserved. R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 Page 191 of 194 RL78/G13 4.13 100-pin Products 4. PACKAGE DRAWINGS R5F100PFAFB, R5F100PGAFB, R5F100PHAFB, R5F100PJAFB, R5F100PKAFB, R5F100PLAFB R5F101PFAFB, R5F101PGAFB, R5F101PHAFB, R5F101PJAFB, R5F101PKAFB, R5F101PLAFB R5F100PFDFB, R5F100PGDFB, R5F100PHDFB, R5F100PJDFB, R5F100PKDFB, R5F100PLDFB R5F101PFDFB, R5F101PGDFB, R5F101PHDFB, R5F101PJDFB, R5F101PKDFB, R5F101PLDFB R5F100PFGFB, R5F100PGGFB, R5F100PHGFB, R5F100PJGFB JEITA Package Code P-LFQFP100-14x14-0.50 RENESAS Code PLQP0100KE-A Previous Code P100GC-50-GBR-1 MASS (TYP.) [g] 0.69 HD D A 75 51 76 50 detail of lead end L1 A3 c B E HE 100 26 1 25 ZE e ZD b x M S AB A A2 S yS A1 L Lp ITEM D E HD HE A A1 A2 A3 b c L Lp L1 e x y ZD ZE (UNIT:mm) DIMENSIONS 14.00±0.20 14.00±0.20 16.00±0.20 16.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 0.22 ±0.05 0.145 + 0.055 0.045 0.50 0.60±0.15 1.00±0.20 3° + 5° 3° 0.50 0.08 0.08 1.00 1.00 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 2012 Renesas Electronics Corporation. All rights reserved. Page 192 of 194 RL78/G13 4. PACKAGE DRAWINGS R5F100PFAFA, R5F100PGAFA, R5F100PHAFA, R5F100PJAFA, R5F100PKAFA, R5F100PLAFA R5F101PFAFA, R5F101PGAFA, R5F101PHAFA, R5F101PJAFA, R5F101PKAFA, R5F101PLAFA R5F100PFDFA, R5F100PGDFA, R5F100PHDFA, R5F100PJDFA, R5F100PKDFA, R5F100PLDFA R5F101PFDFA, R5F101PGDFA, R5F101PHDFA, R5F101PJDFA, R5F101PKDFA, R5F101PLDFA R5F100PFGFA, R5F100PGGFA, R5F100PHGFA, R5F100PJGFA JEITA Package Code P-LQFP100-14x20-0.65 RENESAS Code PLQP0100JC-A Previous Code P100GF-65-GBN-1 MASS (TYP.) [g] 0.92 80 81 B HD D A 51 50 E HE 100 1 ZE ZD S b x M S AB 31 30 e A A2 yS A1 detail of lead end A3 c L Lp L1 ITEM D E HD HE A A1 A2 A3 b c L Lp L1 e x y ZD ZE (UNIT:mm) DIMENSIONS 20.00 0.20 14.00 0.20 22.00 0.20 16.00 0.20 1.60 MAX. 0.10 0.05 1.40 0.05 0.25 0.32 + 0.08 0.07 0.145 + 0.055 0.045 0.50 0.60 0.15 1.00 0.20 3 +5 3 0.65 0.13 0.10 0.575 0.825 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 2012 Renesas Electronics Corporation. All rights reserved. Page 193 of 194 RL78/G13 4.14 128-pin Products 4. PACKAGE DRAWINGS R5F100SHAFB, R5F100SJAFB, R5F100SKAFB, R5F100SLAFB R5F101SHAFB, R5F101SJAFB, R5F101SKAFB, R5F101SLAFB R5F100SHDFB, R5F100SJDFB, R5F100SKDFB, R5F100SLDFB R5F101SHDFB, R5F101SJDFB, R5F101SKDFB, R5F101SLDFB JEITA Package Code P-LFQFP128-14x20-0.50 RENESAS Code PLQP0128KD-A Previous Code P128GF-50-GBP-1 MASS (TYP.) [g] 0.92 102 103 HD D A 65 64 detail of lead end A3 c B E HE 128 1 ZE ZD S b x M S AB yS 39 38 e A A2 A1 θ L Lp L1 ITEM D E HD HE A A1 A2 A3 b c L Lp L1 θ e x y ZD ZE (UNIT:mm) DIMENSIONS 20.00±0.20 14.00±0.20 22.00±0.20 16.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 0.22 ±0.05 0.145 +0.055 −0.045 0.50 0.60±0.15 1.00±0.20 3° +5° −3° 0.50 0.08 0.08 0.75 0.75 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 2012 Renesas Electronics Corporation. All rights reserved. Page 194 of 194 Revision History RL78/G13 Data Sheet Rev. 1.00 2.00 3.00 Date Feb 29, 2012 Oct 12, 2012 Aug 02, 2013 Page 7 25 40, 42, 44 41, 43, 45 59, 63, 67 68 69 96 to 98 100 104 116 120 1 3 4 to 15 16 to 32 33 48, 50, 52 55 57 57 58 59 63 64 65 66 68 70 72 74 75 77 78, 79 80 Description Summary First Edition issued Figure 1-1. Part Number, Memory Size, and Package of RL78/G13: Pin count corrected. 1.4 Pin Identification: Description of pins INTP0 to INTP11 corrected. 1.6 Outline of Functions: Descriptions of Subsystem clock, Low-speed on-chip oscillator, and General-purpose register corrected. 1.6 Outline of Functions: Lists of Descriptions changed. Descriptions of Note 8 in a table corrected. (4) Common to RL78/G13 all products: Descriptions of Notes corrected. 2.4 AC Characteristics: Symbol of external system clock frequency corrected. 2.6.1 A/D converter characteristics: Notes of overall error corrected. 2.6.2 Temperature sensor characteristics: Parameter name corrected. 2.8 Flash Memory Programming Characteristics: Incorrect descriptions corrected. 3.10 52-pin products: Package drawings of 52-pin products corrected. 3.12 80-pin products: Package drawings of 80-pin products corrected. Modification of 1.1 Features Modification of 1.2 List of Part Numbers Modification of Table 1-1. List of Ordering Part Numbers, note, and caution Modification of package type in 1.3.1 to 1.3.14 Modification of description in 1.4 Pin Identification Modification of caution, table, and note in 1.6 Outline of Functions Modification of description in table of Absolute Maximum Ratings (TA = 25°C) Modification of table, note, caution, and remark in 2.2.1 X1, XT1 oscillator characteristics Modification of table in 2.2.2 On-chip oscillator characteristics Modification of note 3 of table (1/5) in 2.3.1 Pin characteristics Modification of note 3 of table (2/5) in 2.3.1 Pin characteristics Modification of table in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products Modification of notes 1 and 4 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products Modification of table in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products Modification of notes 1, 5, and 6 in (1) Flash ROM: 16 to 64 KB of 20- to 64pin products Modification of notes 1 and 4 in (2) Flash ROM: 96 to 256 KB of 30- to 100pin products Modification of notes 1, 5, and 6 in (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products Modification of notes 1 and 4 in (3) Flash ROM: 384 to 512 KB of 44- to 100pin products Modification of notes 1, 5, and 6 in (3) Flash ROM: 384 to 512 KB of 44- to 100-pin products Modification of (4) Peripheral Functions (Common to all products) Modification of table in 2.4 AC Characteristics Addition of Minimum Instruction Execution Time during Main System Clock Operation Modification of figures of AC Timing Test Points and External System Clock Timing C-1 Rev. 3.00 Date Aug 02, 2013 Page 81 81 83 84 85 86 88 89 91 92, 93 94 95 96 97 98 99 100 102 103 106 107 109 111 112 112 113 113 114 115 116 117 Description Summary Modification of figure of AC Timing Test Points Modification of description and note 3 in (1) During communication at same potential (UART mode) Modification of description in (2) During communication at same potential (CSI mode) Modification of description in (3) During communication at same potential (CSI mode) Modification of description in (4) During communication at same potential (CSI mode) (1/2) Modification of description in (4) During communication at same potential (CSI mode) (2/2) Modification of table in (5) During communication at same potential (simplified I2C mode) (1/2) Modification of table and caution in (5) During communication at same potential (simplified I2C mode) (2/2) Modification of table and notes 1 and 4 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) Modification of table and notes 2 to 7 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) Modification of remarks 1 to 4 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) Modification of table in (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (1/2) Modification of table and caution in (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (2/2) Modification of table in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (1/3) Modification of table, note 1, and caution in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (2/3) Modification of table, note 1, and caution in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3) Modification of remarks 3 and 4 in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3) Modification of table in (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (1/2) Modification of table and caution in (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (2/2) Modification of table in (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) Modification of table, note 1, and caution in (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) Addition of (1) I2C standard mode Addition of (2) I2C fast mode Addition of (3) I2C fast mode plus Modification of IICA serial transfer timing Addition of table in 2.6.1 A/D converter characteristics Modification of description in 2.6.1 (1) Modification of notes 3 to 5 in 2.6.1 (1) Modification of description and notes 2, 4, and 5 in 2.6.1 (2) Modification of description and notes 3 and 4 in 2.6.1 (3) Modification of description and notes 3 and 4 in 2.6.1 (4) C-2 Rev. 3.00 Date Aug 02, 2013 Page 118 118 119 120 120 122 123 124 126 126 127 128 133 135 137 139 140 142 143 143 143 145 145 146 147 149 151 152 to 154 155 156 157, 158 160, 161 Description Summary Modification of table in 2.6.2 Temperature sensor/internal reference voltage characteristics Modification of table and note in 2.6.3 POR circuit characteristics Modification of table in 2.6.4 LVD circuit characteristics Modification of table of LVD Detection Voltage of Interrupt & Reset Mode Renamed to 2.6.5 Power supply voltage rising slope characteristics Modification of table, figure, and remark in 2.10 Timing Specs for Switching Flash Memory Programming Modes Modification of caution 1 and description Modification of table and remark 3 in Absolute Maximum Ratings (TA = 25°C) Modification of table, note, caution, and remark in 3.2.1 X1, XT1 oscillator characteristics Modification of table in 3.2.2 On-chip oscillator characteristics Modification of note 3 in 3.3.1 Pin characteristics (1/5) Modification of note 3 in 3.3.1 Pin characteristics (2/5) Modification of notes 1 and 4 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (1/2) Modification of notes 1, 5, and 6 in (1) Flash ROM: 16 to 64 KB of 20- to 64pin products (2/2) Modification of notes 1 and 4 in (2) Flash ROM: 96 to 256 KB of 30- to 100pin products (1/2) Modification of notes 1, 5, and 6 in (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (2/2) Modification of (3) Peripheral Functions (Common to all products) Modification of table in 3.4 AC Characteristics Addition of Minimum Instruction Execution Time during Main System Clock Operation Modification of figure of AC Timing Test Points Modification of figure of External System Clock Timing Modification of figure of AC Timing Test Points Modification of description, note 1, and caution in (1) During communication at same potential (UART mode) Modification of description in (2) During communication at same potential (CSI mode) Modification of description in (3) During communication at same potential (CSI mode) Modification of table, note 1, and caution in (4) During communication at same potential (simplified I2C mode) Modification of table, note 1, and caution in (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) Modification of table, notes 2 to 6, caution, and remarks 1 to 4 in (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) Modification of table in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (1/3) Modification of table and caution in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (2/3) Modification of table, caution, and remarks 3 and 4 in (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3) Modification of table and caution in (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) C-3 Rev. 3.00 3.10 Date Aug 02, 2013 Nov 15, 2013 Page 163 164, 165 166 166 167 167, 168 169 170 171 172 173 173 174 175 123 125 Description Summary Modification of table in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) Modification of table, note 1, and caution in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) Modification of table in 3.5.2 Serial interface IICA Modification of IICA serial transfer timing Addition of table in 3.6.1 A/D converter characteristics Modification of table and notes 3 and 4 in 3.6.1 (1) Modification of description in 3.6.1 (2) Modification of description and note 3 in 3.6.1 (3) Modification of description and notes 3 and 4 in 3.6.1 (4) Modification of table and note in 3.6.3 POR circuit characteristics Modification of table of LVD Detection Voltage of Interrupt & Reset Mode Modification from Supply Voltage Rise Time to 3.6.5 Power supply voltage rising slope characteristics Modification of 3.9 Dedicated Flash Memory Programmer Communication (UART) Modification of table, figure, and remark in 3.10 Timing Specs for Switching Flash Memory Programming Modes Caution 4 added. Note for operating ambient temperature in 3.1 Absolute Maximum Ratings deleted. All trademarks and registered trademarks are the property of their respective owners. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. C-4 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product. 5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc. Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics. 6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. 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When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products. 11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. 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