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The Future of Analog IC Technology DESCRIPTION The MP1482 is a monolithic synchronous buck regulator. The device integrates two 130mΩ MOSFETs, and provides 2A of continuous load current over a wide input voltage of 4.75V to 18V. Current mode control provides fast transient response and cycle-by-cycle current limit. An adjustable soft-start prevents inrush current at turn-on, and in shutdown mode the supply current drops to 1µA. This device, available in an 8-pin SOIC package, provides a very compact solution with minimal external components. MP1482 2A, 18V Synchronous Rectified Step-Down Converter FEATURES  2A Output Current  Wide 4.75V to 18V Operating Input Range  Integrated 130mΩ Power MOSFET Switches  Output Adjustable from 0.923V to 15V  Up to 93% Efficiency  Programmable Soft-Start  Stable with Low ESR Ceramic Output Capacitors  Fixed 340kHz Frequency  Cycle-by-Cycle Over Current Protection  Input Under Voltage Lockout  8–Pin SOIC APPLICATIONS  Distributed Power Systems  Networking Systems  FPGA, DSP, ASIC Power Supplies  Green Electronics/ Appliances  Notebook Computers All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION INPUT 2 1 7 IN EN BS 3 SW 8 SS MP1482 5 FB GND COMP 4 6 EFFICIENCY (%) Efficiency vs Load Current 100 95 VOUT = 3.3V 90 85 VOUT = 2.5V 80 75 70 65 60 55 50 0 0.5 1.0 1.5 2.0 2.5 LOAD CURRENT (A) MP1482 Rev. 1.31 www.MonolithicPower.com 1 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER Part Number MP1482DS* ORDERING INFORMATION Package SOIC8 Top Marking MP1482DS Free Air Temperature (TA) -40C to +85C * For Tape & Reel, add suffix –Z (e.g. MP1482DS–Z); For RoHS Compliant Packaging, add suffix –LF (e.g. MP1482DS–LF–Z) PACKAGE REFERENCE TOP VIEW BS 1 IN 2 SW 3 GND 4 8 SS 7 EN 6 COMP 5 FB SOIC8 ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage VIN ........................-0.3V to +20V Switch Node Voltage VSW ............................ 21V Boost Voltage VBS ..........VSW – 0.3V to VSW + 6V All Other Pins ..................................-0.3V to +6V Junction Temperature ...............................150°C Continuous Power Dissipation (TA = +25°C)(2) SOIC8……………………………………….1.38W Lead Temperature ....................................260°C Storage Temperature .............. -65°C to +150°C Recommended Operating Conditions (3) Input Voltage VIN ............................4.75V to 18V Output Voltage VOUT.....................0.923V to 15V Operating Junct. Temp (TJ)........-40°C to +125°C Thermal Resistance (4) θJA θJC SOIC8..................................... 90 ...... 45... C/W Notes: 1) Exceeding these ratings may damage the device 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-TA)/ θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage.. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer board. MP1482 Rev. 1.31 www.MonolithicPower.com 2 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER ELECTRICAL CHARACTERISTICS VIN = 12V, TA = +25°C, unless otherwise noted. Parameter Shutdown Supply Current Supply Current Feedback Voltage Feedback Overvoltage Threshold Error Amplifier Voltage Gain (5) Error Amplifier Transconductance High-Side Switch On Resistance (5) Low-Side Switch On Resistance (5) High-Side Switch Leakage Current Upper Switch Current Limit Lower Switch Current Limit COMP to Current Sense Transconductance Oscillation Frequency Short Circuit Oscillation Frequency Maximum Duty Cycle Minimum On Time (5) EN Shutdown Threshold Voltage EN Shutdown Threshold Voltage Hysteresis EN Lockout Threshold Voltage EN Lockout Hysterisis Input Under Voltage Lockout Threshold Input Under Voltage Lockout Threshold Hysteresis Soft-Start Current Soft-Start Period Thermal Shutdown (5) Symbol Condition VEN = 0V VEN = 2.0V; VFB = 1.0V VFB 4.75V  VIN  18V AEA GEA RDS(ON)1 RDS(ON)2 IC = 10μA VEN = 0V, VSW = 0V Minimum Duty Cycle From Drain to Source GCS Fosc1 Fosc2 DMAX VFB = 0V VFB = 1.0V VEN Rising VIN Rising VSS = 0V CSS = 0.1μF Note: 5) Guaranteed by design, not tested. Min 0.900 2.4 305 1.1 2.2 3.80 Typ 1 1.3 0.923 1.1 400 800 130 130 3.4 1.1 3.5 340 100 90 220 1.5 210 2.5 210 4.10 210 6 15 160 Max 3.0 1.5 0.946 10 375 2.0 2.7 4.40 Units μA mA V V V/V μA/V mΩ mΩ μA A A A/V kHz kHz % ns V mV V mV V mV μA ms °C MP1482 Rev. 1.31 www.MonolithicPower.com 3 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER PIN FUNCTIONS SOIC8 Pin # Name Description 1 BS High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET switch. Connect a 0.01μF or greater capacitor from SW to BS to power the high side switch. Power Input. IN supplies the power to the IC, as well as the step-down converter switches. 2 IN Drive IN with a 4.75V to 18V power source. Bypass IN to GND with a suitably large capacitor to eliminate noise on the input to the IC. See Input Capacitor. Power Switching Output. SW is the switching node that supplies power to the output. Connect 3 SW the output LC filter from SW to the output load. Note that a capacitor is required from SW to BS to power the high-side switch. 4 GND Ground. Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB with a resistive 5 FB voltage divider from the output voltage. The feedback threshold is 0.923V. See Setting the Output Voltage. Compensation Node. COMP is used to compensate the regulation control loop. Connect a 6 COMP series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required. See Compensation Components. 7 EN Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Pull up with 100kΩ resistor for automatic startup. Soft-Start Control Input. SS controls the soft start period. Connect a capacitor from SS to GND 8 SS to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 15ms. To disable the soft-start feature, leave SS unconnected. MP1482 Rev. 1.31 www.MonolithicPower.com 4 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 12V, VO = 3.3V, L = 10µH, C1 = 10µF, C2 = 22µF, TA = +25°C, unless otherwise noted. Steady State Test VIN = 12V, VOUT = 3.3V IOUT = 0A, IIN= 8.2mA Startup through Enable VIN = 12V, VOUT = 3.3V IOUT = 1A (Resistance Load) Shutdown through Enable VIN = 12V, VOUT = 3.3V IOUT = 1A (Resistance Load) VIN 20mV/div. VOUT 20mV/div. IL 1A/div. VSW 10V/div. VEN 5V/div. VOUT 1V/div. IL 1A/div. VSW 10V/div. VEN 5V/div. VOUT 2V/div. IL 1A/div. VSW 10V/div. Heavy Load Operation 2A Load VIN, AC 200mV/div. VO, AC 20mV/div. IL 1A/div. VSW 10V/div. Medium Load Operation 1A Load Light Load Operation No Load VIN, AC 200mV/div. VIN, AC 20mV/div. VO, AC 20mV/div. IL 1A/div. VO, AC 20mV/div. IL 1A/div. VSW 10V/div. VSW 10V/div. Short Circuit Protection VOUT 2V/div. IL 2A/div. Short Circuit Recovery VOUT 2V/div. IL 2A/div. Load Transient VOUT 200mV/div. IL 1A/div. ILOAD 1A/div. MP1482 Rev. 1.31 www.MonolithicPower.com 5 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER OPERATION FUNCTIONAL DESCRIPTION The MP1482 is a synchronous rectified, current-mode, step-down regulator. It regulates input voltages from 4.75V to 18V down to an output voltage as low as 0.923V, and supplies up to 2A of load current. The MP1482 uses current-mode control to regulate the output voltage. The output voltage is measured at FB through a resistive voltage divider and amplified through the internal transconductance error amplifier. The voltage at the COMP pin is compared to the switch current measured internally to control the output voltage. The converter uses internal N-Channel MOSFET switches to step-down the input voltage to the regulated output voltage. Since the high side MOSFET requires a gate voltage greater than the input voltage, a boost capacitor connected between SW and BS is needed to drive the high side gate. The boost capacitor is charged from the internal 5V rail when SW is low. When the MP1482 FB pin exceeds 20% of the nominal regulation voltage of 0.923V, the over voltage comparator is tripped and the COMP pin and the SS pin are discharged to GND, forcing the high-side switch off. FB SS COMP EN + 1.1V -+ 0.3V --+ 0.923V + OVP RAMP OSCILLATOR 340KHz CLK ERROR AMPLIFIER CURRENT SENSE AMPLIFIER + -- + SQ RQ -- CURRENT COMPARATOR IN 5V BS SW -2.5V + + EN OK LOCKOUT COMPARATOR 1.2V 1.5V -- SHUTDOWN COMPARATOR Figure 1—Functional Block Diagram OVP IN < 4.1V IN INTERNAL REGULATORS GND MP1482 Rev. 1.31 www.MonolithicPower.com 6 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER APPLICATIONS INFORMATION COMPONENT SELECTION Setting the Output Voltage The output voltage is set using a resistive voltage divider from the output voltage to FB pin. The voltage divider divides the output voltage down to the feedback voltage by the ratio: VFB  VOUT R2 R1 R2 Where VFB is the feedback voltage and VOUT is the output voltage. Thus the output voltage is: VOUT  0.923  R1  R2 R2 R2 can be as high as 100kΩ, but a typical value is 10kΩ. Using the typical value for R2, R1 is determined by: R1  10.83  (VOUT  0.923) (kΩ) For example, for a 3.3V output voltage, R2 is 10kΩ, and R1 is 26.1kΩ. Inductor The inductor is required to supply constant current to the output load while being driven by the switched input voltage. A larger value inductor will result in less ripple current that will result in lower output ripple voltage. However, the larger value inductor will have a larger physical size, higher series resistance, and/or lower saturation current. A good rule for determining the inductance to use is to allow the peak-to-peak ripple current in the inductor to be approximately 30% of the maximum switch current limit. Also, make sure that the peak inductor current is below the maximum switch current limit. The inductance value can be calculated by: L  VOUT fS  IL  1  VOUT VIN  Where VOUT is the output voltage, VIN is the input voltage, fS is the switching frequency, and ΔIL is the peak-to-peak inductor ripple current. Choose an inductor that will not saturate under the maximum inductor peak current. The peak inductor current can be calculated by: ILP  ILOAD  VOUT 2  fS  L  1 VOUT VIN  Where ILOAD is the load current. The choice of which style inductor to use mainly depends on the price vs. size requirements and any EMI requirements. Optional Schottky Diode During the transition between high-side switch and low-side switch, the body diode of the lowside power MOSFET conducts the inductor current. The forward voltage of this body diode is high. An optional Schottky diode may be paralleled between the SW pin and GND pin to improve overall efficiency. Table 1 lists example Schottky diodes and their Manufacturers. Table 1—Diode Selection Guide Part Number B130 SK13 Voltage/Current Rating 30V, 1A 30V, 1A MBRS130 30V, 1A Vendor Diodes, Inc. Diodes, Inc. International Rectifier Input Capacitor The input current to the step-down converter is discontinuous, therefore a capacitor is required to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Ceramic capacitors are preferred, but tantalum or low-ESR electrolytic capacitors may also suffice. Choose X5R or X7R dielectrics when using ceramic capacitors. Since the input capacitor (C1) absorbs the input switching current it requires an adequate ripple current rating. The RMS current in the input capacitor can be estimated by: IC1  ILOAD  VOUT VIN 1  VOUT VIN    MP1482 Rev. 1.31 www.MonolithicPower.com 7 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER The worst-case condition occurs at VIN = 2VOUT, where IC1 = ILOAD/2. For simplification, choose the input capacitor whose RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum or ceramic. When using electrolytic or tantalum capacitors, a small, high quality ceramic capacitor, i.e. 0.1μF, should be placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple for low ESR capacitors can be estimated by: VIN  ILOAD C1 fS  VOUT VIN  1  VOUT VIN  Where C1 is the input capacitance value. Output Capacitor The output capacitor is required to maintain the DC output voltage. Ceramic, tantalum, or low ESR electrolytic capacitors are recommended. Low ESR capacitors are preferred to keep the output voltage ripple low. The output voltage ripple can be estimated by: VOUT  VOUT fS  L  1  VOUT VIN   RESR  8  1 fS  C2  Where C2 is the output capacitance value and RESR is the equivalent series resistance (ESR) value of the output capacitor. In the case of ceramic capacitors, the impedance at the switching frequency is dominated by the capacitance. The output voltage ripple is mainly caused by the capacitance. For simplification, the output voltage ripple can be estimated by: ΔVOUT  8  VOUT fS2  L  C2  1  VOUT VIN  In the case of tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. For simplification, the output ripple can be approximated to: ΔVOUT  VOUT fS  L  1  VOUT VIN   RESR The characteristics of the output capacitor also affect the stability of the regulation system. The MP1482 can be optimized for a wide range of capacitance and ESR values. Compensation Components MP1482 employs current mode control for easy compensation and fast transient response. The system stability and transient response are controlled through the COMP pin. COMP pin is the output of the internal transconductance error amplifier. A series capacitor-resistor combination sets a pole-zero combination to control the characteristics of the control system. The DC gain of the voltage feedback loop is given by: A VDC  RLOAD  GCS  A EA  VFB VOUT Where AVEA is the error amplifier voltage gain; GCS is the current sense transconductance and RLOAD is the load resistor value. The system has two poles of importance. One is due to the compensation capacitor (C3) and the output resistor of the error amplifier, and the other is due to the output capacitor and the load resistor. These poles are located at: fP1  GEA 2  C3  A VEA fP2  1 2  C2  RLOAD Where GEA is the error amplifier transconductance. The system has one zero of importance, due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at: fZ1  1 2  C3  R3 The system may have another zero of importance, if the output capacitor has a large capacitance and/or a high ESR value. The zero, due to the ESR and capacitance of the output capacitor, is located at: fESR  1 2  C2  RESR MP1482 Rev. 1.31 www.MonolithicPower.com 8 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER In this case (as shown in Figure 2), a third pole set by the compensation capacitor (C6) and the compensation resistor (R3) is used to compensate the effect of the ESR zero on the loop gain. This pole is located at: fP3  1 2  C6  R3 The goal of compensation design is to shape the converter transfer function to get a desired loop gain. The system crossover frequency where the feedback loop has the unity gain is important. Lower crossover frequencies result in slower line and load transient responses, while higher crossover frequencies could cause system instability. A good rule of thumb is to set the crossover frequency below one-tenth of the switching frequency. To optimize the compensation components, the following procedure can be used. 1. Choose the compensation resistor (R3) to set the desired crossover frequency. Determine the R3 value by the following equation: R3  2  C2  fC GEA  GCS  VOUT VFB  2  C2  0.1 fS GEA  GCS  VOUT VFB Where fC is the desired crossover frequency which is typically below one tenth of the switching frequency. 2. Choose the compensation capacitor (C3) to achieve the desired phase margin. For applications with typical inductor values, setting the compensation zero, fZ1, below one-forth of the crossover frequency provides sufficient phase margin. Determine the C3 value by the following equation: C3  4 2  R3  fC Where R3 is the compensation resistor. 3. Determine if the second compensation capacitor (C6) is required. It is required if the ESR zero of the output capacitor is located at less than half of the switching frequency, or the following relationship is valid: 1 2  C2  RESR  fS 2 If this is the case, then add the second compensation capacitor (C6) to set the pole fP3 at the location of the ESR zero. Determine the C6 value by the equation: C6  C2  RESR R3 External Bootstrap Diode An external bootstrap diode may enhance the efficiency of the regulator, and it will be a must if the applicable condition is:  VOUT is 5V or 3.3V, and duty cycle is high: D= VOUT >65% VIN In these cases, an external BST diode is recommended from the output of the voltage regulator to BST pin, as shown in Figure.2 BST MP1482 SW External BST Diode IN4148 CBST L + C OUT 5V or 3.3V Figure 2—Add Optional External Bootstrap Diode to Enhance Efficiency The recommended external BST diode is IN4148, and the BST cap is 0.1~1µF. MP1482 Rev. 1.31 www.MonolithicPower.com 9 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER TYPICAL APPLICATION CIRCUIT INPUT 2 1 7 IN EN BS 3 SW 8 SS MP1482 5 FB GND COMP 4 6 Figure 3—MP1482 with 3.3V Output, 22µF/6.3V Ceramic Output Capacitor MP1482 Rev. 1.31 www.MonolithicPower.com 10 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER PCB LAYOUT GUIDE PCB layout is very important to achieve stable operation. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines and take Figure 4 for reference. 1) Keep the path of switching current short and minimize the loop area formed by input cap, high-side MOSFET and low-side MOSFET. INPUT 4.75V to 18V 2) Bypass ceramic capacitors are suggested to be put close to the Vin Pin. 3) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the chip as possible. 4) Route SW away from sensitive analog areas such as FB. 5) Connect IN, SW, and especially GND respectively to a large copper area to cool the chip to improve thermal performance and long-term reliability. C5 R4 2 7 IN EN 1 BS 3 SW L1 OUTPUT MP1482 8 5 R1 C1 SS GND FB COMP 4 C4 6 C3 D1 R2 C2 (optional) R3 MP1482 Typical Application Circuit SS 8 EN 7 COMP 6 FB 5 R4 C3 R3 C4 R21 R1 PGND PGND D1 C2 SGND 1 BS 2 IN 3 SW 4 GND C5 C1 L1 Top Layer Bottom Layer Figure 4—MP1482 Typical Application Circuit and PCB Layout Guide MP1482 Rev. 1.31 www.MonolithicPower.com 11 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER PACKAGE INFORMATION 0.189(4.80) 0.197(5.00) 8 5 SOIC8 0.024(0.61) 0.063(1.60) 0.050(1.27) PIN 1 ID 0.150(3.80) 0.228(5.80) 0.157(4.00) 0.244(6.20) 0.213(5.40) 1 4 TOP VIEW RECOMMENDED LAND PATTERN 0.013(0.33) 0.020(0.51) 0.053(1.35) 0.069(1.75) SEATING PLANE 0.004(0.10) 0.010(0.25) 0.050(1.27) BSC FRONT VIEW SEE DETAIL "A" SIDE VIEW 0.0075(0.19) 0.0098(0.25) GAUGE PLANE 0.010(0.25) BSC 0.010(0.25) 0.020(0.50) x 45o 0o-8o 0.016(0.41) 0.050(1.27) DETAIL "A" NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA. 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP1482 Rev. 1.31 www.MonolithicPower.com 12 7/9/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved.

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