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    LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP FEATURES n Smallest Pin-Compatible Octal DACs: LTC2600: 16 Bits LTC2610: 14 Bits LTC2620: 12 Bits n Guaranteed 16-Bit Monotonic Over Temperature n Wide 2.5V to 5.5V Supply Range n Low Power Operation: 250μA per DAC at 3V n Individual Channel Power-Down to 1μA, Max n Ultralow Crosstalk Between DACs (<10μV) n High Rail-to-Rail Output Drive (±15mA, Min) n Double-Buffered Digital Inputs n Pin-Compatible 10-/8-Bit Versions (LTC1660/LTC1665) n Tiny 16-Lead Narrow SSOP and 20-Lead 4mm × 5mm QFN Packages APPLICATIONS n Mobile Communications n Process Control and Industrial Automation n Instrumentation n Automatic Test Equipment DESCRIPTION The LTC®2600/LTC2610/LTC2620 are octal 16-, 14- and 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in 16-lead narrow SSOP and 20-lead 4mm × 5mm QFN packages. They have built-in high performance output buffers and are guaranteed monotonic. These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive, crosstalk and load regulation in single-supply, voltage-output multiples. The parts use a simple SPI/MICROWIRE compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. Daisychain capability and a hardware CLR function are included. The LTC2600/LTC2610/LTC2620 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero-scale; and after power-up, they stay at zero-scale until a valid write and update take place. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. BLOCK DIAGRAM (20) GND 1 (1) VOUTA 2 DAC A DAC H 16 VCC (17) 15 VOUTH (16) REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER (2) VOUTB 3 DAC B DAC G 14 VOUTG (15) REGISTER REGISTER REGISTER REGISTER (3) VOUTC 4 DAC C DAC F 13 VOUTF (14) REGISTER REGISTER REGISTER REGISTER (4) VOUTD 5 (5) REF 6 (7) CS/LD 7 (8) SCK 8 DAC D DAC E 12 VOUTE (13) CONTROL LOGIC DECODE POWER-ON RESET 11 CLR (11) 10 SDO (10) 32-BIT SHIFT REGISTER NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE 9 SDI (9) 2600 BD DNL (LSB) Differential Nonlinearity (LTC2600) 1.0 VCC = 5V 0.8 VREF = 4.096V 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2600 G21 2600fe 1 LTC2600/LTC2610/LTC2620 ABSOLUTE MAXIMUM RATINGS (Note 1) Any Pin to GND ........................................... –0.3V to 6V Any Pin to VCC ............................................ –6V to 0.3V Operating Temperature Range LTC2600C/LTC2610C/LTC2620C ............. 0°C to 70°C LTC2600I/LTC2610I/LTC2620I............. –40°C to 85°C Storage Temperature Range.................. –65°C to 150°C Maximum Junction Temperature........................... 125°C Lead Temperature (Soldering, 10 sec) ................. 300°C PIN CONFIGURATION TOP VIEW GND 1 VOUTA 2 VOUTB 3 VOUTC 4 VOUTD 5 REF 6 CS/LD 7 SCK 8 16 VCC 15 VOUTH 14 VOUTG 13 VOUTF 12 VOUTE 11 CLR 10 SDO 9 SDI GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 150°C/W TOP VIEW VCC DNC DNC GND VOUTA 1 VOUTB 2 VOUTC 3 VOUTD 4 REF 5 DNC 6 20 19 18 17 16 VOUTH 15 VOUTG 14 VOUTF 21 13 VOUTE 12 DNC 11 CLR 7 8 9 10 SDO SDI SCK CS/LD UFD PACKAGE 20-LEAD (4mm s 5mm) PLASTIC QFN TJMAX = 150°C, θJA = 43°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2600CUFD#PBF LTC2600CUFD#TRPBF 2600 20-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C LTC2600IUFD#PBF LTC2600IUFD#TRPBF 2600 20-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C LTC2600CGN#PBF LTC2600CGN#TRPBF 2600 16-Lead Plastic SSOP 0°C to 70°C LTC2600IGN#PBF LTC2600IGN#TRPBF 2600I 16-Lead Plastic SSOP –40°C to 85°C LTC2610CUFD#PBF LTC2610CUFD#TRPBF 2610 20-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C LTC2610IUFD#PBF LTC2610IUFD#TRPBF 2610 20-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C LTC2610CGN#PBF LTC2610CGN#TRPBF 2610 16-Lead Plastic SSOP 0°C to 70°C LTC2610IGN#PBF LTC2610IGN#TRPBF 2610I 16-Lead Plastic SSOP –40°C to 85°C LTC2620CUFD#PBF LTC2620CUFD#TRPBF 2620 20-Lead (4mm × 5mm) Plastic DFN 0°C to 70°C LTC2620IUFD#PBF LTC2620IUFD#TRPBF 2620 20-Lead (4mm × 5mm) Plastic DFN –40°C to 85°C LTC2620CGN#PBF LTC2620CGN#TRPBF 2620 16-Lead Plastic SSOP 0°C to 70°C LTC2620IGN#PBF LTC2620IGN#TRPBF 2620I 16-Lead Plastic SSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2600fe 2 LTC2600/LTC2610/LTC2620 ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LTC2620 LTC2610 LTC2600 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DC Performance Resolution l 12 14 16 Bits Monotonicity VCC = 5V, VREF = 4.096V (Note 2) l 12 14 16 Bits DNL Differential Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) l ±0.5 ±1 ±1 LSB INL Integral Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) l ±0.75 ±4 ±3 ±16 ±12 ±64 LSB Load Regulation VREF = VCC = 5V, Mid-Scale IOUT = 0mA to 15mA Sourcing l IOUT = 0mA to 15mA Sinking l 0.025 0.125 0.025 0.125 0.1 0.5 0.1 0.5 0.3 2 LSB/mA 0.3 2 LSB/mA VREF = VCC = 2.5V, Mid-Scale IOUT = 0mA to 7.5mA Sourcing l IOUT = 0mA to 7.5mA Sinking l 0.05 0.25 0.05 0.25 0.2 1 0.2 1 0.8 4 LSB/mA 0.8 4 LSB/mA ZSE Zero-Scale Error VCC = 5V, VREF = 4.096V Code = 0 19 19 19 mV VOS Offset Error VCC = 5V, VREF = 4.096V (Note 7) ±1 ±9 ±1 ±9 ±1 ±9 mV VOS Temperature Coefficient ±3 ±3 ±3 μV/°C GE Gain Error Gain Temperature Coefficient VCC = 5V, VREF = 4.096V ±0.2 ±0.7 ±6.5 ±0.2 ±0.7 ±6.5 ±0.2 ±0.7 %FSR ±6.5 ppm/°C The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LTC2600/LTC2610/LTC2620 MIN TYP MAX UNITS PSR Power Supply Rejection ROUT DC Output Impedance DC Crosstalk (Note 4) VCC = ±10% VREF = VCC = 5V, Mid-Scale; –15mA ≤ IOUT ≤ 15mA l VREF = VCC = 2.5V, Mid-Scale; –7.5mA ≤ IOUT ≤ 7.5mA l Due to Full-Scale Output Change (Note 5) Due to Load Current Change Due to Powering Down (per Channel) –80 dB 0.025 0.15 Ω 0.030 0.15 Ω ±10 μV ±3.5 μV/mA ±7.3 μV ISC Short-Circuit Output Current VCC = 5.5V, VREF = 5.6V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND l 15 34 60 mA l 15 34 60 mA VCC = 2.5V, VREF = 5.6V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND l 7.5 18 50 mA l 7.5 24 50 mA Reference Input Input Voltage Range Resistance Normal Mode l 0 VCC V l 11 16 20 kΩ Capacitance 90 pF IREF Reference Current, Power-Down Mode All DACs Powered Down l 0.001 1 μA 2600fe 3 LTC2600/LTC2610/LTC2620 ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LTC2600/LTC2610/LTC2620 MIN TYP MAX UNITS Power Supply VCC Positive Supply Voltage ICC Supply Current Digital I/O VCC = 5V (Note 3) VCC = 3V (Note 3) All DACs Powered Down (Note 3) VCC = 5V All DACs Powered Down (Note 3) VCC = 3V l 2.5 5.5 V l 2.6 4 mA l 2.0 3.2 mA l 0.35 1 μA l 0.10 1 μA VIH Digital Input High Voltage VIL Digital Input Low Voltage VOH Digital Output High Voltage VOL Digital Output Low Voltage ILK Digital Input Leakage CIN Digital Input Capacitance VCC = 2.5V to 5.5V VCC = 2.5V to 3.6V VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V Load Current = –100μA Load Current = +100μA VIN = GND to VCC (Note 6) l 2.4 l 2.0 l l l VCC – 0.4 l l l V V 0.8 V 0.6 V V 0.4 V ±1 μA 8 pF The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LTC2620 LTC2610 LTC2600 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS AC Performance tS Settling Time (Note 8) ±0.024% (±1LSB at 12 Bits) 7 ±0.006% (±1LSB at 14 Bits) ±0.0015% (±1LSB at 16 Bits) 7 7 9 9 μs 10 μs Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits) 2.7 2.7 2.7 μs (Note 9) ±0.006% (±1LSB at 14 Bits) 4.8 4.8 μs ±0.0015% (±1LSB at 16 Bits) 5.2 μs Voltage Output Slew Rate 0.80 0.80 0.80 V/μs Capacitive Load Driving 1000 1000 1000 pF Glitch Impulse At Mid-Scale Transition 12 12 12 nV • s Multiplying Bandwidth en Output Voltage Noise Density At f = 1kHz At f = 10kHz 180 180 180 kHz 120 120 120 nV/√Hz 100 100 100 nV/√Hz Output Voltage Noise 0.1Hz to 10Hz 15 15 15 μVP-P 2600fe 4 LTC2600/LTC2610/LTC2620 TIMING CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 6) SYMBOL PARAMETER CONDITIONS LTC2600/LTC2610/LTC2620 MIN TYP MAX UNITS VCC = 2.5V to 5.5V t1 SDI Valid to SCK Setup t2 SDI Valid to SCK Hold t3 SCK High Time t4 SCK Low Time t5 CS/LD Pulse Width t6 LSB SCK High to CS/LD High t7 CS/LD Low to SCK High t8 SDO Propagation Delay from SCK Falling Edge t9 CLR Pulse Width t10 CS/LD High to SCK Positive Edge SCK Frequency CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V 50% Duty Cycle l 4 l 4 l 9 l 9 l 10 l 7 l 7 l l l 20 l 7 l ns ns ns ns ns ns ns 20 ns 45 ns ns ns 50 MHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Linearity and monotonicity are defined from code kL to code 2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: Digital inputs at 0V or VCC. Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with the measured DAC at mid-scale, unless otherwise noted. Note 5: RL = 2kΩ to GND or VCC. Note 6: Guaranteed by design and not production tested. Note 7: Inferred from measurement at code 256 (LTC2600), code 64 (LTC2610) or code 16 (LTC2620), and at full-scale. Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale and 3/4-scale to 1/4-scale. Load is 2k in parallel with 200pF to GND. Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between halfscale and half-scale – 1. Load is 2k in parallel with 200pF to GND. 2600fe 5 INL (LSB) DNL (LSB) INL (LSB) LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2600 Integral Nonlinearity (INL) 32 VCC = 5V 24 VREF = 4.096V 16 8 0 –8 –16 –24 –32 0 16384 32768 CODE 49152 65535 2600 G20 Differential Nonlinearity (DNL) 1.0 VCC = 5V 0.8 VREF = 4.096V 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 CODE 49152 65535 2600 G21 INL vs Temperature 32 24 VCC = 5V VREF = 4.096V 16 8 INL (POS) 0 –8 INL (NEG) –16 –24 –32 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2600 G22 DNL (LSB) INL (LSB) DNL (LSB) DNL vs Temperature 1.0 0.8 VCC = 5V 0.6 VREF = 4.096V 0.4 DNL (POS) 0.2 0 –0.2 DNL (NEG) –0.4 –0.6 –0.8 –1.0 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2600 G23 INL vs VREF 32 24 VCC = 5.5V 16 8 INL (POS) 0 –8 INL (NEG) –16 –24 –32 0 1 2 3 VREF (V) 4 5 2600 G24 DNL vs VREF 1.5 VCC = 5.5V 1.0 0.5 DNL (POS) 0 DNL (NEG) –0.5 –1.0 –1.5 0 1 2 3 4 5 VREF (V) 2600 G25 Settling to ±1LSB Settling of Full-Scale Step 6 VOUT 100μV/DIV CS/LD 2V/DIV 9.7μs 2μs/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2600 G26 VOUT 100μV/DIV CS/LD 2V/DIV 12.3μs 5μs/DIV SETTLING TO ±1LSB VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2600 G27 2600fe LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2610 INL (LSB) DNL (LSB) Integral Nonlinearity (INL) 8 VCC = 5V 6 VREF = 4.096V 4 2 0 –2 –4 –6 –8 0 LTC2620 4096 8192 CODE 12288 16383 2600 G28 Differential Nonlinearity (DNL) 1.0 VCC = 5V 0.8 VREF = 4.096V 0.6 Settling to ±1LSB 0.4 VOUT 0.2 100μV/DIV 0 –0.2 CS/LD –0.4 2V/DIV 8.9μs –0.6 –0.8 –1.0 0 4096 8192 CODE 12288 16383 2μs/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2600 G29 2600 G30 INL (LSB) DNL (LSB) Integral Nonlinearity (INL) 2.0 VCC = 5V 1.5 VREF = 4.096V 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 1024 2048 CODE LTC2600/LTC2610/LTC2620 3072 4095 2600 G31 Differential Nonlinearity (DNL) 1.0 VCC = 5V 0.8 VREF = 4.096V 0.6 0.4 0.2 0 Settling to ±1LSB VOUT 1mV/DIV 6.8μs –0.2 CS/LD 2V/DIV –0.4 –0.6 –0.8 –1.0 0 1024 2048 CODE 3072 4095 2μs/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2600 G32 2600 G33 $VOUT (V) $VOUT (mV) Current Limiting 0.10 CODE = MIDSCALE 0.08 VREF = VCC = 5V 0.06 VREF = VCC = 3V 0.04 0.02 0 –0.02 –0.04 –0.06 VREF = VCC = 3V VREF = VCC = 5V –0.08 –0.10 –40 –30 –20 –10 0 10 20 30 40 IOUT (mA) 2600 G01 Load Regulation 1.0 CODE = MIDSCALE 0.8 0.6 0.4 0.2 0 VREF = VCC = 5V –0.2 –0.4 –0.6 VREF = VCC = 3V –0.8 –1.0 –35 –25 –15 –5 5 15 IOUT (mA) 25 35 2600 G02 OFFSET ERROR (mV) Offset Error vs Temperature 3 2 1 0 –1 –2 –3 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2600 G03 2600fe 7 LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2600/LTC2610/LTC2620 ZERO-SCALE ERROR (mV) Zero-Scale Error vs Temperature 3 2.5 2.0 1.5 1.0 0.5 0 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2600 G04 GAIN ERROR (%FSR) Gain Error vs Temperature 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 2600 G05 OFFSET ERROR (mV) Offset Error vs VCC 3 2 1 0 –1 –2 –3 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2600 G06 GAIN ERROR (%FSR) Gain Error vs VCC 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 2.5 3 3.5 4 4.5 VCC (V) 5 5.5 2600 G07 ICC (nA) ICC Shutdown vs VCC 450 400 350 300 250 200 150 100 50 0 2.5 3 3.5 4 4.5 VCC (V) Large-Signal Response VOUT 0.5V/DIV 5 5.5 2600 G08 VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 2.5μs/DIV 2600 G09 Mid-Scale Glitch Impulse Power-On Reset Glitch VOUT 10mV/DIV CS/LD 5V/DIV 12nV-s TYP 2.5μs/DIV VCC 1V/DIV 2600 G10 VOUT 10mV/DIV 44mmVVPPEEAAKK 250μs/DIV 2600 G11 VOUT (V) Headroom at Rails vs Output Current 5.0 4.5 5V SOURCING 4.0 3.5 3V SOURCING 3.0 2.5 2.0 1.5 5V SINKING 1.0 3V SINKING 0.5 0 0 1 2 3 4 5 6 7 8 9 10 IOUT (mA) 2600 G12 2600fe 8 ICC (mA) 10mA/DIV dB 10mA/DIV LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2600/LTC2610/LTC2620 Supply Current vs Logic Voltage 2.4 VCC = 5V 2.3 SWEEP SCK, SDI AND CS/LD 2.2 0V TO VCC 2.1 2.0 1.9 1.8 1.7 1.6 1.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 LOGIC VOLTAGE (V) 2600 G13 Exiting Power-Down to Mid-Scale VCC = 5V VREF = 2V VOUT 0.5V/DIV CS/LD 5V/DIV DACs A TO G IN POWER-DOWN MODE 2.5μs/DIV 2600 G14 Hardware CLR VOUT 1V/DIV CLR 5V/DIV 1μs/DIV 2600 G15 Multiplying Bandwidth 0 –3 –6 –9 –12 –15 –18 –21 –24 –27 VCC = 5V VREF (DC) = 2V –30 VREF (AC) = 0.2VP-P –33 CODE = FULL SCALE –36 1k 10k 100k FREQUENCY (Hz) 1M 2600 G16 Output Voltage Noise, 0.1Hz to 10Hz VOUT 10μV/DIV 0 1 2 3 4 5 6 7 8 9 10 SECONDS 2600 G17 Short-Circuit Output Current vs VOUT (Sinking) Short-Circuit Output Current vs VOUT (Sourcing) 0mA 0mA VCC = 5.5V VREF = 5.6V CODE = 0 1V/DIV VOUT SWEPT 0V TO VCC 2600 G18 VCC = 5.5V 1V/DIV VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V 2600 G19 2600fe 9 LTC2600/LTC2610/LTC2620 PIN FUNCTIONS (GN/UFD) GND (Pin 1/Pin 20): Analog Ground. VOUTA to VOUTH (Pins 2-5 and 12-15/Pins 1-48 and 13-16): DAC Analog Voltage Outputs. The output range is 0 – VREF. REF (Pin 6/Pin 5): Reference Voltage Input. 0V ≤ VREF ≤ VCC. CS/LD (Pin 7/Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 8/Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 9/Pin 9): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK. The LTC2600, LTC2610 and LTC2620 accept input word lengths of either 24 or 32 bits. SDO (Pin 10/Pin 10): Serial Interface Data Output. This pin is used for daisychain operation. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. SDO is an active output and does not go high impedance, even when CS/LD is taken to a logic high level. CLR (Pin 11/Pin 11): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V. CMOS and TTL compatible. VCC (Pin 16/Pin 17): Supply Voltage Input. 2.5V ≤ VCC ≤ 5.5V. DNC (Pins 6, 12, 18, 19 UFD Only): Do Not Connect. Exposed Pad (Pin 21 UFD Only): Ground. The exposed pad must be soldered to the PCB. 2600fe 10 BLOCK DIAGRAM (20) GND 1 (1) VOUTA 2 DAC A (2) VOUTB 3 DAC B (3) VOUTC 4 DAC C (4) VOUTD 5 (5) REF 6 (7) CS/LD 7 (8) SCK 8 DAC D DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER LTC2600/LTC2610/LTC2620 DAC REGISTER INPUT REGISTER INPUT REGISTER DAC H 16 VCC (17) 15 VOUTH (16) DAC REGISTER INPUT REGISTER INPUT REGISTER DAC G 14 VOUTG (15) DAC REGISTER INPUT REGISTER INPUT REGISTER DAC F 13 VOUTF (14) DAC REGISTER INPUT REGISTER INPUT REGISTER DAC E 12 VOUTE (13) CONTROL LOGIC DECODE POWER-ON RESET 11 CLR (11) 10 SDO (10) 32-BIT SHIFT REGISTER NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE 9 SDI (9) 2600 BD02 TIMING DIAGRAM SCK t1 t2 1 SDI t5 t7 CS/LD SDO t3 t4 2 3 t8 t6 23 24 t10 2600 F01 2600fe 11 LTC2600/LTC2610/LTC2620 OPERATION Power-On Reset The LTC2600/LTC2610/LTC2620 clear the outputs to zero-scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2600/2610/2620 contain circuitry to reduce the power-on glitch: the analog outputs typically rise less than 10mV above zero-scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range –0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. Transfer Function The digital-to-analog transfer function is: VOUT(IDEAL) = ⎛ ⎝⎜ k 2N ⎞ ⎠⎟ VREF where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 6). Serial Interface The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 16-, 14- or 12-bit input code, ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits (LTC2600, LTC2610 and LTC2620 respectively). Data can only be transferred to the device when the CS/LD signal is low.The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a. The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. While the minimum input word is 24 bits, it may optionally be extended to 32 bits. To use the 32-bit word width, 8 don’t-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b shows the Table 1. COMMAND* C3 C2 C1 C0 0 0 0 0 Write to Input Register n 0 0 0 1 Update (Power Up) DAC Register n 0 0 1 0 Write to Input Register n, Update (Power Up) All n 0 0 1 1 Write to and Update (Power Up) n 0 1 0 0 Power Down n 1 1 1 1 No Operation *Command and address codes not shown are reserved and should not be used. ADDRESS (n)* A3 A2 A1 A0 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 0 1 0 0 DAC E 0 1 0 1 DAC F 0 1 1 0 DAC G 0 1 1 1 DAC H 1 1 1 1 All DACs 12 2600fe LTC2600/LTC2610/LTC2620 OPERATION INPUT WORD (LTC2600) COMMAND ADDRESS DATA (16 BITS) C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB INPUT WORD (LTC2610) LSB 2600 TBL01 COMMAND ADDRESS DATA (14 BITS + 2 DON’T-CARE BITS) C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X MSB INPUT WORD (LTC2620) LSB 2600 TBL02 COMMAND ADDRESS DATA (12 BITS + 4 DON’T-CARE BITS) C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X MSB LSB 2600 TBL03 32-bit sequence. The 32-bit word is required for daisychain operation, and is also available to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). Daisychain Operation The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a “daisychain” series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the no-operation command (1111) for the other devices in the chain. 2600fe 13 LTC2600/LTC2610/LTC2620 OPERATION Power-Down Mode For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight outputs are needed. When in power-down, the buffer amplifiers and reference inputs are disabled, and draw essentially zero current. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 90k resistors. When all eight DACs are powered down, the master bias generation circuit is also disabled. Input- and DAC-register contents are not disturbed during power-down. Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit data word is ignored. The supply and reference currents are reduced by approximately 1/8 for each DAC powered down; the effective resistance at REF (Pin 6) rises accordingly, becoming a high impedance input (typically > 1GΩ) when all eight DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. There is an initial delay as the DAC powers up before it begins its usual settling behavior. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay is 5μs. If, on the other hand, all eight DACs are powered down, then the master bias generation circuit is also disabled and must be restarted. In this case, the power-up delay is greater: 12μs for VCC = 5V, 30μs for VCC = 3V. Voltage Outputs Each of the 8 rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Load regulation is a measure of the amplifier’s ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers’ DC output impedance is 0.025Ω when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25Ω typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25Ω • 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping “signal” and “power” grounds separated internally and by reducing shared internal resistance to just 0.005Ω. 2600fe 14 LTC2600/LTC2610/LTC2620 OPERATION The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device’s ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.025Ω), and will degrade DC crosstalk. Note that the LTC2600/LTC2610/LTC2620 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC – FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 2600fe 15 LTC2600/LTC2610/LTC2620 OPERATION 2600fe 16 CS/LD SCK SDI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 COMMAND WORD ADDRESS WORD DATA WORD D2 D1 D0 YYYY F02a 24-BIT INPUT WORD Figure 2a. LTC2600 24-Bit Load Sequence (Minimum Input Word). LTC2610 SDI Data Word: 14-Bit Input Code + 2 Don’t-Care Bits; LTC2620 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits CS/LD SCK SDI SDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 X X X X X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE COMMAND WORD ADDRESS WORD DATA WORD X X X X X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PREVIOUS 32-BIT INPUT WORD t1 t2 SCK 17 18 t3 t4 SDI D15 D14 t8 SDO PREVIOUS D15 PREVIOUS D14 Figure 2b. LTC2600 32-Bit Load Sequence (Required for Daisy-Chain Operation). LTC2610 SDI/SDO Data Word: 14-Bit Input Code + 2 Don’t-Care Bits; LTC2620 SDI/SDO Data Word: 12-Bit Input Code + 4 Don’t-Care Bits CURRENT 32-BIT INPUT WORD YYYY F02b OPERATION LTC2600/LTC2610/LTC2620 VREF = VCC POSITIVE FSE VREF = VCC OUTPUT VOLTAGE 0V NEGATIVE OFFSET OUTPUT VOLTAGE INPUT CODE (c) INPUT CODE (b) 0 32, 768 65, 535 INPUT CODE (a) Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale OUTPUT VOLTAGE 2600 F03 PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 ±.005 .189 – .196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .254 MIN .150 – .165 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) .0165 ± .0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .007 – .0098 (0.178 – 0.249) .015 ± .004 (0.38 ± 0.10) × 45° 0° – 8° TYP 1 234 5678 .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES 2. DIMENSIONS ARE IN INCHES (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE .008 – .012 (0.203 – 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 2600fe 17 LTC2600/LTC2610/LTC2620 PACKAGE DESCRIPTION UFD Package 20-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1711 Rev B) 0.70 p0.05 4.50 p 0.05 1.50 REF 3.10 p 0.05 2.65 p 0.05 3.65 p 0.05 PACKAGE OUTLINE 0.25 p0.05 0.50 BSC 2.50 REF 4.10 p 0.05 5.50 p 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p 0.10 (2 SIDES) 0.75 p 0.05 PIN 1 TOP MARK (NOTE 6) R = 0.05 TYP 1.50 REF 19 20 5.00 p 0.10 (2 SIDES) 2.50 REF 3.65 p 0.10 2.65 p 0.10 PIN 1 NOTCH R = 0.20 OR C = 0.35 0.40 p 0.10 1 2 0.200 REF 0.00 – 0.05 R = 0.115 TYP (UFD20) QFN 0506 REV B 0.25 p 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2600fe 18 LTC2600/LTC2610/LTC2620 REVISION HISTORY (Revision history begins at Rev D) REV DATE DESCRIPTION D 03/10 Revise GN Part Markings in Order Information E 05/10 Changed “No Connect” pins to “Do Not Connect” in Pin Configuration and Pin Functions sections PAGE NUMBER 2 2, 10 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 2600fe 19 LTC2600/LTC2610/LTC2620 TYPICAL APPLICATION Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428 1 1 TP1 4 5 VSS SDA 3 A2 SCL 6 2 A1 WP 7 1 A0 VCC 8 U1 24LC025 TP2 C3 0.1μF 14 + + 13 12 + + 11 10 + + 9 8 ++ 7 6 ++ 5 4 ++ 3 5V 2 ++ 1 J1 HD2X7 R1, R3, R4 R1 are 4.99k, 1% R3 R4 VCC R2 7.5k 11 CLR VREF VCC C1 0.1μF 6 REF 16 VCC C2 0.1μF MOSI MISO VIN SCK CS 1 8 SCK 7 LS/LD 9 SDI 10 SDO 2 VOUTA 3 VOUTB 4 VOUTC 5 VOUTD 12 VOUTE 13 VOUTF 14 VOUTG 15 VOUTH GND 1 U2 TP16 LTC2600CGN VIN U4 LT1236ACS8-5 2 VIN 6 VOUT GND C6 4 0.1μF U5 LT1461ACS8-4 2 VIN 6 VOUT 3 SHDN GND C9 4 0.1μF 5V 4.096V VREF 1 2 3 JP2 VREF 1 TP11 VREF C7 4.7μF 6.3V 5VREF C8 REGULATOR 1μF 16V 1 2 3 JP3 VCC 5V VCC 1 1 TP12 VCC TP13 GND 1 TP3 DAC A 1 TP14 GND 1 TP4 DAC B 1 TP15 GND 1 TP5 DAC C 1 TP6 DAC D 1 TP7 DAC E VREF VCC VCC 1 TP8 DAC F 1 TP9 DAC G 1 TP10 DAC H C10 100pF C4 R5 0.1μF 7.5k R8 22Ω C5 0.1μF JP1 3 ON/OFF 2 DISABLE 7 43 MUXOUT ADCIN FSSET 28 VCC VCC 1 ADC 9 CH0 10 CH1 11 CH2 12 CH3 13 CH4 4-/8-CHANNEL MUX 14 CH5 15 CH6 17 CH7 CSADC 23 CSMUX 20 + 20-BIT ADC SCK 25 CLK 19 – LTC2424/LTC2428 DIN 21 SD0 24 5 ZSSET GND GND GND GND GND GND GND U3 1 6 16 18 22 27 28 LTC2428CG FO 26 R7 7.5k R6 7.5k CS SCK RELATED PARTS PART NUMBER DESCRIPTION LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1821 Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output DAC COMMENTS LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Programmable Speed/Power, 3.5μs/750μA, 8μs/450μA VCC = 5V(3V), Low Power, Deglitched Low Power, Deglitched, Rail-to-Rail VOUT VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling in 2μs for 10V Step 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com 2600fe LT 0510 REV E • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2003

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