首页资源分类嵌入式系统 > STM32F427XX &STM32F429XX Datasheet

STM32F427XX &STM32F429XX Datasheet

已有 445109个资源

下载专区

上传者其他资源

    文档信息举报收藏

    标    签:STM32F427XXampSTM32F429XXDatasheet

    分    享:

    文档简介

    STM32F427XX &STM32F429XX Datasheet

    文档预览

    STM32F427xx STM32F429xx ARM Cortex-M4 32b MCU+FPU, 225DMIPS, up to 2MB Flash/256+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT Datasheet - production data Features • Core: ARM® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 2 MB of Flash memory organized into two banks allowing read-while-write – Up to 256+4 KB of SRAM including 64-KB of CCM (core coupled memory) data RAM – Flexible external memory controller with up to 32-bit data bus: SRAM,PSRAM,SDRAM/LPSDR SDRAM , Compact Flash/NOR/NAND memories • LCD parallel interface, 8080/6800 modes • LCD-TFT controller up to XGA resolution with dedicated Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D) • Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – rVeBgAisTtseurspp+lyopfotiroRnaTlC4, 20×32 bit backup KB backup SRAM • 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 17 timers: up to twelve 16-bit and two 32bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode – SWD & JTAG interfaces – Cortex-M4 Trace Macrocell™ &"'! LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) UFBGA169 (7 × 7 mm) LQFP176 (24 × 24 mm) UFBGA176 (10 x 10 mm) LQFP208 (28 x 28 mm) TFBGA216 (13 x 13 mm) WLCSP143 • Up to 168 I/O ports with interrupt capability – Up to 164 fast I/Os up to 90 MHz – Up to 166 5 V-tolerant I/Os • Up to 21 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/4 UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Ufupll-tdou6pleSxPII2sS(4fo5rMabuidtsio/sc),la2sswiathccmuruaxceydvia internal audio PLL or external clock – 1 x SAI (serial audio interface) – 2 × CAN (2.0B Active) and SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • True random number generator • CRC calculation unit • RTC: subsecond accuracy, hardware calendar • 96-bit unique ID Table 1. Device summary Reference Part number STM32F427xx STM32F427VG, STM32F427ZG, STM32F427IG, STM32F427AG, STM32F427VI, STM32F427ZI, STM32F427II, STM32F427AI STM32F429xx STM32F429VG, STM32F429ZG, STM32F429IG, STM32F429BG, STM32F429NG, STM32F429AG, STM32F429VI, STM32F429ZI, STM32F429II,, STM32F429BI, STM32F429NI,STM32F429AI, STM32F429VE, STM32F429ZE, STM32F429IE, STM32F429BE, STM32F429NE February 2015 This is information on a product in full production. DocID024030 Rev 5 1/226 www.st.com Contents Contents STM32F427xx STM32F429xx 1 2 3 2/226 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 ARM® Cortex®-M4 with FPU and embedded Flash and SRAM . . . . . . . 19 3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19 3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20 3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10 LCD-TFT controller (available only on STM32F429xx) . . . . . . . . . . . . . . 22 3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 30 3.19 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 30 3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DocID024030 Rev 5 STM32F427xx STM32F429xx Contents 3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.22.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.22.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.23 Inter-integrated circuit interface ( I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 35 3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.29 Audio and LCD PLL(PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.30 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 38 3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 38 3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.33 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 39 3.34 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 39 3.35 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.36 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.37 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.38 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.39 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.40 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.41 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.42 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DocID024030 Rev 5 3/226 5 Contents STM32F427xx STM32F429xx 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 96 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 96 6.3.5 reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . 97 6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 125 6.3.13 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 6.3.15 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 131 6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3.19 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.3.20 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.3.21 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.3.24 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6.3.25 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.26 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.27 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 187 6.3.28 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 188 6.3.29 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 190 4/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Contents 6.3.30 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 216 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 B.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 217 B.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 219 B.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 DocID024030 Rev 5 5/226 5 List of tables List of tables STM32F427xx STM32F429xx Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F427xx and STM32F429xx features and peripheral counts . . . . . . . . . . . . . . . . . . 14 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 27 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32F427xx and STM32F429xx pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . 51 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STM32F427xx and STM32F429xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 73 STM32F427xx and STM32F429xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 85 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 95 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 96 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 96 reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM . . . . . . 100 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 101 Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . 102 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 103 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 103 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 104 Typical current consumption in Run mode, code with data processing running from Flash memory or RAM, regulator ON (ART accelerator enabled except prefetch), VDD=1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Typical current consumption in Run mode, code with data processing running from Flash memory, regulator OFF (ART accelerator enabled except prefetch). . . . . . . 107 Typical current consumption in Sleep mode, regulator ON, VDD=1.7 V . . . . . . . . . . . . . 108 Tyical current consumption in Sleep mode, regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . 109 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6/226 DocID024030 Rev 5 STM32F427xx STM32F429xx List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PLLISAI (audio and LCD-TFT PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 151 Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 152 Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 153 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 156 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 156 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 165 Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 167 DocID024030 Rev 5 7/226 8 List of tables STM32F427xx STM32F429xx Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 169 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 173 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data. . . . . . . . 193 WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 WLCSP143 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 196 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 UFBGA176+25 - 201-ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 216 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 8/226 DocID024030 Rev 5 STM32F427xx STM32F429xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and UFBGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 STM32F427xx and STM32F429xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F427xx and STM32F429xx Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 25 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 29 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 29 STM32F42x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STM32F42x WLCSP143 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32F42x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 STM32F42x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 STM32F42x LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 STM32F42x UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STM32F42x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STM32F42x TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . 104 Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . 105 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 DocID024030 Rev 5 9/226 11 List of figures STM32F427xx STM32F429xx Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 148 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 158 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 158 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 163 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 165 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 166 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 168 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 173 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 176 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 176 PC Card/CompactFlash controller waveforms for attribute memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 PC Card/CompactFlash controller waveforms for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 178 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 179 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 182 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 182 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 192 LQPF100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 WLCSP143 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 LQFP144-144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . . 198 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 LQFP176 - 176-pin, 24 x 24 mm low-profile quad flat package outline . . . . . . . . . . . . . . 201 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint. . . . . . . . . 203 10/226 DocID024030 Rev 5 STM32F427xx STM32F429xx List of figures Figure 91. LQFP176 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Figure 92. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline . . . . . . . . . . . . . . 205 Figure 93. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Figure 94. LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Figure 95. UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Figure 96. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Figure 97. UFBGA176+25 - 201-ball 10 x 10 mm, 0.65 mm pitch ultra thin fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Figure 98. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 99. TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Figure 100. TFBGA176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Figure 101. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 102. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 217 Figure 103. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 218 Figure 104. USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Figure 105. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 106. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 107. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 DocID024030 Rev 5 11/226 11 Introduction 1 Introduction STM32F427xx STM32F429xx This datasheet provides the description of the STM32F427xx and STM32F429xx line of microcontrollers. For more details on the whole STMicroelectronics STM32 family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F427xx and STM32F429xx datasheet should be read in conjunction with the STM32F4xx reference manual. For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming manual (PM0214), available from www.st.com. 12/226 DocID024030 Rev 5 STM32F427xx STM32F429xx 2 Description Description The STM32F427xx and STM32F429xx devices are based on the high-performance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 180 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM® singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The STM32F427xx and STM32F429xx devices incorporate high-speed embedded memories (Flash memory up to 2 Mbyte, up to 256 kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. They also feature standard and advanced communication interfaces. • Up to three I2Cs • Six SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus four UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), • Two CANs • One SAI serial audio interface • An SDIO/MMC interface • Ethernet and camera interface • LCD-TFT display controller • Chrom-ART Accelerator™. Advanced peripherals include an SDIO, a flexible memory control (FMC) interface, a camera interface for CMOS sensors. Refer to Table 2: STM32F427xx and STM32F429xx features and peripheral counts for the list of peripherals available on each part number. The STM32F427xx and STM32F429xx devices operates in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F427xx and STM32F429xx devices offer devices in 8 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen. DocID024030 Rev 5 13/226 42 Description 14/226 These features make the STM32F427xx and STM32F429xx microcontrollers suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances Figure 4 shows the general block diagram of the device family. DocID024030 Rev 5 Table 2. STM32F427xx and STM32F429xx features and peripheral counts Peripherals STM32F427 Vx STM32F429Vx STM32F427 Zx STM32F429Zx STM32F427 STM32F429 STM32F427 Ax Ax Ix STM32F429Ix STM32F429Bx STM32F429Nx Flash memory in Kbytes 1024 2048 512 1024 2048 1024 2048 512 1024 2048 1024 2048 1024 2048 1024 2048 512 1024 2048 512 1024 2048 512 1024 2048 SRAM in Kbytes System Backup FMC memory controller 256(112+16+64+64) 4 Yes(1) Ethernet Yes Generalpurpose 10 Timers Advanced -control 2 Basic 2 Random number generator Yes STM32F427xx STM32F429xx STM32F427xx STM32F429xx Table 2. STM32F427xx and STM32F429xx features and peripheral counts (continued) Peripherals STM32F427 Vx STM32F429Vx STM32F427 Zx STM32F429Zx STM32F427 STM32F429 STM32F427 Ax Ax Ix STM32F429Ix STM32F429Bx STM32F429Nx SPI / I2S I2C USART/ UART 4/2 (full duplex)(2) 6/2 (full duplex)(2) 3 4/4 USB OTG Communication FS Yes interfaces USB OTG HS Yes CAN 2 SAI 1 SDIO Yes Camera interface Yes DocID024030 Rev 5 LCD-TFT (STM32F429xx only) No Yes No Yes No Yes No Yes Chrom-ART Accelerator™ Yes GPIOs 82 114 130 140 168 12-bit ADC Number of channels 16 12-bit DAC Number of channels 3 24 Yes 2 Maximum CPU frequency Operating voltage Operating temperatures 180 MHz 1.8 to 3.6 V(3) Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C Packages LQFP100 WLCSP143 LQFP144 UFBGA169 UFBGA176 LQFP176 LQFP208 TFBGA216 Description 1. For the LQFP100 package, only FMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. For UFBGA169 package, only SDRAM, NAND and multiplexed static memories are supported. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VODFDF/)V. DDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset 15/226 Description STM32F427xx STM32F429xx 2.1 Full compatibility throughout the family The STM32F427xx and STM32F429xx devices are part of the STM32F4 family. They are fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F427xx and STM32F429xx devices maintain a close compatibility with the whole STM32F10xx family. All functional pins are pin-to-pin compatible. The STM32F427xx and STM32F429xx, however, are not drop-in replacements for the STM32F10xx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xx to the STM32F42x family remains simple as only a few pins are impacted. Figure 1, Figure 2, and Figure 3, give compatible board designs between the STM32F4xx, STM32F2xx, and STM32F10xx families. Figure 1. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package    633    633 633 633       :ª RESISTORORSOLDERINGBRIDGE PRESENTFORTHE34-&XXX CONFIGURATION NOTPRESENTINTHE 34-&XXCONFIGURATION 6$$ 633 4WO :RESISTORSCONNECTEDTO 633FORTHE34-&XX 633 6$$ 633 633FOR34-&XX 6$$FOR34-&XX 633FORTHE34-&XX 633 6$$OR.#FORTHE34-&XX AIC 16/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Description Figure 2. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package    ŸUHVLVWRURUVROGHULQJEULGJH SUHVHQWIRUWKH670)[[ 966  FRQILJXUDWLRQQRWSUHVHQWLQWKH 670)[[FRQILJXUDWLRQ   6LJQDOIURP H[WHUQDOSRZHU VXSSO\ VXSHUYLVRU  3'5B21   966 966 1RWSRSXODWHGZKHQŸ UHVLVWRURUVROGHULQJ EULGJHSUHVHQW     9'' 966 966 1RWSRSXODWHGIRU670)[[ 7ZRŸUHVLVWRUVFRQQHFWHGWR 966IRUWKH670)[[ 9669''RU1&IRUWKH670)[[ 9'' 966 966IRU670)[[ 9''IRU670)[[ 9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[ DLG Figure 3. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and UFBGA176 packages      *1'IRU670)[[ %<3$66B5(*IRU670)[[ 6LJQDOIURPH[WHUQDO SRZHUVXSSO\ VXSHUYLVRU  3'5B21     9''966 7ZRŸUHVLVWRUVFRQQHFWHGWR 9669''RU1&IRUWKH670)[[ 9''RUVLJQDOIURPH[WHUQDOSRZHUVXSSO\VXSHUYLVRUIRUWKH670)[[ 069 DocID024030 Rev 5 17/226 42 Description STM32F427xx STM32F429xx Figure 4. STM32F427xx and STM32F429xx block diagram .*4234 *4$) *4#+37#,+ *4$/37$ *4$/ 42!#%#,+ 42!#%$;= -))OR2-))AS!& -$)/AS!& $0 $- 5,0)#+ $;= $)2 340 .84 )$ 6"53 3/& ,#$?2;= ,#$?';= ,#$?";= ,#$?(39.# ,#$?639.# ,#$?$% ,#$?#,+ 0!;= 0";= 0#;= 0$;= 0%;= 0&;= 0';= 0(;= 0);= 0*;= ##-DATA2!-+" *4!'37 %4- -05 .6)# $ "53 !2-#ORTEX - -(Z ) "53 &05 3 "53 %THERNET-!# $-!  & )&/ 53" $-! /4'(3 &)&/ $-! $-! 3TREAMS &)&/ 3TREAMS &)&/ ,#$ 4&4 &)&/ #(2/- !24 &)&/ $-!$ '0)/0/24! '0)/0/24" '0)/0/24# '0)/0/24$ '0)/0/24% '0)/0/24& '0)/0/24' '0)/0/24( '0)/0/24) '0)/0/24* 0(9 !("BUS MATRIX3- !24!##%, #!#(% &)&/ &)&/ 0(9 %XTERNALMEMORYCONTROLLER&-# 32!- 3$2!- 032!- !(" ./2&LASH 0##ARD .!.$&LASH -"&LASH -"&LASH 32!-+" 32!-+" 32!-+" !("-(Z !(" -(Z 6$$! 2#(3 2#,3 0,,   2ESET -!CL.OC!K'4 CONTROL (#,+X 0#,+X 2.' #AMERA INTERFACE 53" /4'&3 6$$ 0OWERMANAGMT 6OLTAGE REGULATOR TO 6 0/2 RESET )NT 6$$ 3UPPLY SUPERVISION 0/20$2 "/2 06$ 6$$! 6$$ 84!,/3#  -(Z )7$' ,3 3TANDBY INTERFACE 6"!4 84!,K(Z 24# !75 "ACKUPREGISTER +""+032!- ,3 #,+ .%;= !;= $;= ./%. .7%. .",;= 3$#,+%;= 3$.%;= 3.$2.!73 %. #.!,3 .!$6 .7!)4.)/2$ .2%' #$ ).42 (39.# 639.# 05)8#,+ $;= $0 $)$ 6"53 3/& 6$$TO6 633 6#!0 6#!0 6$$! 633! .234 /3#?). /3#?/54 6"!4TO6 /3#?). /3#?/54 24#?!& 24#?!& 24#?(: 0+;= '0)/0/24+ 4)- B CHANNELS %42AS!& 4)- B CHANNELS %42AS!& !& $;= #-$ #+AS!& COMPLCHAN4)-?#(;=. CHAN4)-?#(;=%42 "+).AS!& COMPLCHAN4)-?#(;=. CHAN4)-?#(;= %42 "+).AS!& CHANNELSAS! & CHANNELAS!& CHANNELAS!& 28 48 #+ #43 243AS!& 28 48 #+ #43 243AS!& -/3) -)3/ 3#+ .33AS!& -/3) -)3/ 3#+ .33AS!& -/3) -)3/ 3#+ .33AS!& -/3) -)3/ 3#+ .33AS!& 3$ 3#+ &3 -#,+AS!& 6$$2%&?!$# ANALOGINPUTSCOMMON TOTHE!$#S ANALOGINPUTSCOMMON TOTHE!$# ANALOGINPUTSFOR!$# %84)47+50 3$)/--# 4)-07-B 4)-07-B 4)- B 4)- B 4)- B SIRM$!CARD53!24 SIRM$!CARD53!24 30) 30) 30) 30) 3!) 45E3M!P2ER4ATU-RE"SPESNSOR !$# !$# )& !$# 6$$! &)&/ !0" -(Z !0"-(Z &)&/ $-! $-! !("!0" !("!0" 77$' 4)- B 4)- B 6$$! $!# )4& $!# $!#?/54 $!#?/54 AS!& AS!& !0"!0-"(ZM-A(XZ &)&/ $IGITALFILTER 4)- B 4)- B 4)- B 4)- B 4)- B SMCARD 53!24 IR$! 53!24SMCIRA$R!D 5!24 5!24 5!24 5!24 30)3 30)3 )#3-"53 )#3-"53 )#3-"53 BX#!. BX#!. CHANNELS %42AS!& CHANNELS CHANNELSAS!& CHANNELAS!& CHANNELAS!& 28 48AS!& #43 243AS!& 28 48AS!& #43 243AS!& 28 48AS!& 28 48AS!& 28 48AS!& 28 48AS!& -/3)3$ -)3/3$?EXT 3#+#+ .3373 -#+AS!& -/3)3$ -)3/3$?EXT 3#+#+ .3373 -#+AS!& 3#, 3$! 3-"!AS!& 3#, 3$! 3-"!AS!& 3#, 3$! 3-"!AS!& 48 28 48 28 -36 1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. The LCD-TFT is available only on STM32F429xx devices. 18/226 DocID024030 Rev 5 STM32F427xx STM32F429xx 3 Functional overview Functional overview 3.1 Note: ARM® Cortex®-M4 with FPU and embedded Flash and SRAM The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM® Cortex®-M4 with FPU core is a 32-bit RISC processor that features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F42x family is compatible with all ARM tools and software. Figure 4 shows the general block diagram of the STM32F42x family. Cortex-M4 with FPU core is binary compatible with the Cortex-M3 core. 3.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 225 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 180 MHz. 3.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DocID024030 Rev 5 19/226 42 Functional overview STM32F427xx STM32F429xx 3.4 Embedded Flash memory The devices embed a Flash memory of up to 2 Mbytes available for storing programs and data. 3.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 3.6 Embedded SRAM All devices embed: • Up to 256Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 3.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM, FMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. 20/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview Figure 5. STM32F427xx and STM32F429xx Multi-AHB matrix .E\WH $50 &&0GDWD5$0 &RUWH[0 *3 '0$ *3 '0$ 0$& (WKHUQHW 86%27* +6 /&'7)7 &KURP$57$FFHOHUDWRU '0$' '0$' ,EXV 'EXV 6EXV '0$B3, '0$B0(0 '0$B0(0 '0$B3 (7+(51(7B0 86%B+6B0 /&'7)7B0 3.8 %XVPDWUL[6 $&&(/ ,&2'( '&2'( )ODVK PHPRU\ 65$0 .E\WH 65$0 .E\WH 65$0 .E\WH $+% SHULSKHUDOV $+% SHULSKHUDOV )0&H[WHUQDO 0HP&WO $3% $3% -36 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. DocID024030 Rev 5 21/226 42 Functional overview STM32F427xx STM32F429xx The DMA can be used with the main peripherals: • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC • SAI1. 3.9 Flexible memory controller (FMC) All devices embed an FMC. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SDRAM/LPSDR SDRAM, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • 8-,16-, 32-bit data bus width • Read FIFO for SDRAM controller • Write FIFO • Maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is 90 MHz. LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.10 LCD-TFT controller (available only on STM32F429xx) The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: • 2 displays layers with dedicated FIFO (64x32-bit) • Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer • Up to 8 Input color formats selectable per layer • Flexible blending between two layers using alpha value (per pixel or constant) • Flexible programmable parameters for each layer • Color keying (transparency color) • Up to 4 programmable interrupt events. 22/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview 3.11 Chrom-ART Accelerator™ (DMA2D) The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conversion. It supports the following functions: • Rectangle filling with a fixed color • Rectangle copy • Rectangle copy with pixel format conversion • Rectangle composition with blending and pixel format conversion. Various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. It embeds dedicated memory to store color lookup tables. An interrupt can be generated when an operation is complete or at a programmed watermark. All the operations are fully automatized and are running independently from the CPU or the DMAs. 3.12 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 91 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M4 with FPU core. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 3.13 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected to the 16 external interrupt lines. 3.14 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is DocID024030 Rev 5 23/226 42 Functional overview STM32F427xx STM32F429xx detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 180 MHz while the maximum frequency of the high-speed APB domains is 90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz. The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 3.15 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. Refer to application note AN2606 for details. 3.16 Note: Power supply schemes • VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. 3.17 3.17.1 Power supply supervisor Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other package, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is 24/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview 3.17.2 reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 6: Power supply supervisor interconnection with internal reset OFF. Figure 6. Power supply supervisor interconnection with internal reset OFF 9'' ([WHUQDO9''SRZHUVXSSO\VXSHUYLVRU ([WUHVHWFRQWUROOHUDFWLYHZKHQ 9''9 3'5B21 1567 $SSOLFDWLRQUHVHW VLJQDO RSWLRQDO 9'' 069 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 7). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry must be disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal. DocID024030 Rev 5 25/226 42 Functional overview STM32F427xx STM32F429xx Figure 7. PDR_ON control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHWE\RWKHUVRXUFHWKDQ SRZHUVXSSO\VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 069 3.18 3.18.1 Voltage regulator The regulator has four operating modes: • Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down • Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON: • MR mode used in Run/sleep modes or in Stop modes – In Run/Sleep mode The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). Different voltages scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. 26/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview 3.18.2 The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. – In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). • LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: – LPR operates in normal mode (default mode when LPR is ON) – LPR operates in under-drive mode (reduced leakage mode). • Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to Figure 22: Power supply scheme and Table 19: VCAP1/VCAP2 operating conditions. All packages have the regulator ON feature. Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. ‘-’ means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency. Refer to Table 17: General operating conditions.The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 22: Power supply scheme. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. DocID024030 Rev 5 27/226 42 Functional overview STM32F427xx STM32F429xx In regulator OFF mode, the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. • The over-drive and under-drive modes are not available. • The Standby mode is not available. Figure 8. Regulator OFF 9 ([WHUQDO9&$3BSRZHU VXSSO\VXSHUYLVRU $SSOLFDWLRQUHVHW ([WUHVHWFRQWUROOHUDFWLYH VLJQDO RSWLRQDO  ZKHQ9&$3B0LQ9 Note: 9'' 3$ 1567 9'' %<3$66B5(* 9 9&$3B 9&$3B DL9 The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9). • Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 10). • If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. The minimum value of V12 depends on the maximum frequency targeted in the application (see Table 17: General operating conditions). 28/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 3'5 9RU9 9 0LQ9 9'' 9&$3B9&$3B WLPH 1567 WLPH 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' DLI 3'5 9RU9 9 0LQ9 9&$3B9&$3B 1567 3$DVVHUWHGH[WHUQDOO\ WLPH 1. This figure is valid whatever the internal reset mode (ON or OFF). WLPH DLH DocID024030 Rev 5 29/226 42 Functional overview STM32F427xx STM32F429xx 3.18.3 Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF LQFP100 LQFP144, LQFP208 WLCSP143, LQFP176, UFBGA169, UFBGA176, TFBGA216 Yes Yes No Yes Yes BYPASS_REG set BYPASS_REG set to VSS to VDD Yes PDR_ON set to VDD No Yes PDR_ON connected to an external power supply supervisor 3.19 Real-time clock (RTC), backup SRAM and backup registers The backup domain includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 3.20: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.20: Low-power modes). 30/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.20 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator modes in stop mode): – Normal mode (default mode when MR or LPR is enabled) – Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup). Table 5. Voltage regulator modes in stop mode Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR) Normal mode Under-drive mode MR ON MR in under-drive mode LPR ON LPR in under-drive mode • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. DocID024030 Rev 5 31/226 42 Functional overview STM32F427xx STM32F429xx 3.21 Note: VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (Internal Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 3.22 Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. 32/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview Timer type Table 6. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Max Complementary interface output clock (MHz) Max timer clock (MHz) (1) Any Advanced TIM1, -control TIM8 16-bit Up, integer Down, between 1 Up/down and Yes 4 65536 Yes 90 180 Any TIM2, TIM5 32-bit Up, integer Down, between 1 Up/down and Yes 4 65536 No 45 90/180 Any TIM3, TIM4 16-bit Up, integer Down, between 1 Up/down and Yes 4 65536 No 45 90/180 Any integer TIM9 16-bit Up between 1 No 2 and General 65536 purpose Any TIM10 integer , 16-bit Up between 1 No 1 TIM11 and 65536 No 90 180 No 90 180 Any integer TIM12 16-bit Up between 1 No 2 and 65536 No 45 90/180 Any TIM13 integer , 16-bit Up between 1 No 1 TIM14 and 65536 No 45 90/180 Any Basic TIM6, TIM7 16-bit integer Up between 1 Yes and 0 65536 No 45 90/180 1. The maximum timer clock is either 90 or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. DocID024030 Rev 5 33/226 42 Functional overview STM32F427xx STM32F429xx 3.22.1 3.22.2 3.22.3 Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F42x devices (see Table 6 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F42x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 34/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview 3.22.4 3.22.5 3.22.6 Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. 3.23 Inter-integrated circuit interface ( I2C) Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the standard (up to 100 KHz), and fast (up to 400 KHz) modes. They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. The devices also include programmable analog and digital noise filters (see Table 7). Table 7. Comparison of I2C analog and digital filters Analog filter Digital filter Pulse width of suppressed spikes ≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks 3.24 Universal synchronous/asynchronous receiver transmitters (USART) The devices embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and four universal asynchronous receiver transmitters (UART4, UART5, UART7, and UART8). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to DocID024030 Rev 5 35/226 42 Functional overview STM32F427xx STM32F429xx communicate at speeds of up to 11.25 Mbit/s. The other available interfaces communicate at up to 5.62 bit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Table 8. USART feature comparison(1) USART name Standard features Modem (RTS/CTS) LIN SPI master irDA Smartcard (ISO 7816) Max. baud Max. baud rate in Mbit/s rate in Mbit/s (oversampling (oversampling by 16) by 8) APB mapping USART1 X USART2 X USART3 X UART4 X X X X X X X X X X X X X X X X - X - X - APB2 5.62 11.25 (max. 90 MHz) APB1 2.81 5.62 (max. 45 MHz) APB1 2.81 5.62 (max. 45 MHz) APB1 2.81 5.62 (max. 45 MHz) UART5 X - X - X - APB1 2.81 5.62 (max. 45 MHz) USART6 X UART7 X UART8 X X X X X X - X - X - - X - X - APB2 5.62 11.25 (max. 90 MHz) APB1 2.81 5.62 (max. 45 MHz) APB1 2.81 5.62 (max. 45 MHz) 1. X = feature supported. 3.25 Serial peripheral interface (SPI) The devices feature up to six SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 45 Mbits/s, SPI2 and SPI3 can communicate at up to 22.5 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 36/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview 3.26 Note: Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. For I2S2 full-duplex mode, I2S2_CK and I2S2_WS signals can be used only on GPIO Port B and GPIO Port D. 3.27 Serial Audio interface (SAI1) The serial audio interface (SAI1) is based on two independent audio sub-blocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks can be configured in master or in slave mode. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. The two sub-blocks can be configured in synchronous mode when full-duplex mode is required. SAI1 can be served by the DMA controller. 3.28 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output). 3.29 Audio and LCD PLL(PLLSAI) An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. The PLLSAI is also used to generate the LCD-TFT clock. DocID024030 Rev 5 37/226 42 Functional overview STM32F427xx STM32F429xx 3.30 Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 3.31 Ethernet MAC interface with dedicated DMA and IEEE 1588 support The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The microcontroller requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller. The devices include the following features: • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F4xx reference manual for details) • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time 3.32 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive 38/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 3.33 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 4 bidirectional endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected 3.34 Universal serial bus on-the-go high-speed (OTG_HS) The devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • for OTG/Host modes, a power switch is needed in case bus-powered devices are connected DocID024030 Rev 5 39/226 42 Functional overview STM32F427xx STM32F429xx 3.35 Digital camera interface (DCMI) The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image 3.36 Random number generator (RNG) All devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.37 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 90 MHz. 3.38 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 40/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Functional overview 3.39 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.40 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 10-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.41 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.42 Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F42x through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or DocID024030 Rev 5 41/226 42 Functional overview STM32F427xx STM32F429xx any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 42/226 DocID024030 Rev 5 STM32F427xx STM32F429xx 4 Pinouts and pin description Pinouts and pin description Figure 11. STM32F42x LQFP100 pinout  6$$  633  0%  0%  0"  0"  "//4  0"  0"  0"  0"  0"  0$  0$  0$  0$  0$  0$  0$  0$  0#  0#  0#  0!  0! 0!  633  6$$  0!  0!  0!  0!  0#  0#  0"  0"  0"  0%  0%  0%  0%  0%  0%  0%  0%  0%  0"  0"  6#!0?  6$$  0%  0%  0%  0%  0%  6"!4  0#  0#  0#  633  6$$  0(  0(  .234  0#  0#  0#  0#  6$$  633!  62%&  6$$!  0!  0!  0!  ,1&0 1. The above figure shows the package top view.  6$$  633  6#!0?  0!  0!  0!  0!  0!  0!  0#  0#  0#  0#  0$  0$  0$  0$  0$  0$  0$  0$  0"  0"  0"  0" AIC DocID024030 Rev 5 43/226 83 Pinouts and pin description STM32F427xx STM32F429xx Figure 12. STM32F42x WLCSP143 ballout            $ 3'5 B21 3( 3% 3% 3* 3* 3' 3' 3' 3& 9'' % 3( 3( 3% 3% 3% 3* 3' 3' 3' 3& 3$ & 9%$7 3( %227  3% 3% 3* 9'' 3' 3& 3$ 9'' ' 3& 3& 3( 3( 9'' 3* 3$ 3$ 3$ 966 9&$3 B ( 3& 9'' 3) 3( 966 9'' 3* 3& 3& 3$ 3$ ) 3) 3) 3) 3) 3) 3* 966 3' 3& 3& 3$ * 3) 3) 3) 3) 9'' 3* 3* 3* 3* 3* 9'' + 3) 3+ 1567 3& 966 3' 3' 3' 966 966 3* - 3+ 3& 3& 9'' 9'' 9'' 9'' 3( 3% 3' 3* . 3& 966$ 3$ 3$ 3% 3) 3* 3( 3% 3' 3' / 95() 9''$ 3$  0 3$ 3$ 3$ 3$ 3% 3) 3& 3) 3) 3( 3( 3( 3' 9'' 3( 3( 3% 3% 3' 1 %<3$66B 5(* 3$ 3& 3% 3) 3* 3( 3( 3% 9&$3 B 3% 1. The above figure shows the package bump view. 069 44/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Figure 13. STM32F42x LQFP144 pinout  6$$  0$2?/.  0%  0%  0"  0"  "//4  0"  0"  0"  0"  0"  0'  6$$  633  0'  0'  0'  0'  0'  0'  0$  0$  6$$  633  0$  0$  0$  0$  0$  0$  0#  0#  0#  0!   0!  0!   633  6$$  0!   0!   0!   0!   0#  0#  0"  0"  0"  0&  0&  633  6$$  0&  0&  0&  0'  0'  0%  0%  0%  633  6$$  0%  0%  0%  0%  0%  0%  0"  0"  6#!0?  6$$  0%  0%  0%  0%  0%  6"!4  0#  0#  0#  0&  0&  0&  0&  0&  0&  633  6$$  0&  0&  0&  0&  0&  0(  0(  .234  0#  0#  0#  0#  6$$  633!  62%&  6$$!  0!   0!   0!   ,1&0 1. The above figure shows the package top view.  6$$  633  6#!0?  0!   0!   0!   0!   0!   0!   0#  0#  0#  0#  6$$   633 0'  0'  0'  0'  0'  0'  0'  0$  0$  6$$  633  0$  0$  0$  0$  0$  0$  0"  0"  0"  0" AIB DocID024030 Rev 5 45/226 83 Pinouts and pin description STM32F427xx STM32F429xx Figure 14. STM32F42x LQFP176 pinout  0)  0)  0)  0)  6$$  0$2?/.  0%  0%  0"  0"  "//4  0"  0"  0"  0"  0"  0'  6$$  633  0'  0'  0'  0'  0'  0'  0$  0$  6$$  633  0$  0$  0$  0$  0$  0$  0#  0#  0#  0!  0!  6$$  633  0)  0) 0%  0%  0%  0%  0%  6"!4  0)  0#  0#  0#  0)  0)  0)  633  6$$  0&  0&  0&  0&  0&  0&  633  6$$  0&  0&  0&  0&  0&  0(  0(  .234  0#  0#  0#  0#  6$$  633!  62%&  6$$!  0!  0!  0!  0(  0(  ,1&0  0)  0)  0(  0(  0(  6$$  633  6#!0?  0!  0!  0!  0!  0!  0!  0#  0#  0#  0#  6$$  633  0'  0'  0'  0'  0'  0'  0'  0$  0$  6$$  633  0$  0$  0$  0$  0$  0$  0"  0"  0"  0"  6$$  633  0( 0(  0(  0!  "90!33?2%'  6$$  0!  0!  0!  0!  0#  0#  0"  0"  0"  0&  0&  633  6$$  0&  0&  0&  0'  0'  0%  0%  0%  633  6$$  0%  0%  0%  0%  0%  0%  0"  0"  6#!0?  6$$  0(  0(  0(  0(  0(  0(  1. The above figure shows the package top view. -36 46/226 DocID024030 Rev 5 47/226 DocID024030 Rev 5 0!  0!  0!  0!  0#  0#  6$$  633  0"  0"  0"  0)  0*  0*  0*  0*  0*  0&  0&  633  6$$  0&  0&  0&  0'  0'  0%  0%  0%  633  6$$  0%  0%  0%  0%  0%  0%  0"  0"  6#!0  633  6$$  0*  0(  0(  0(  0(  0(  0(  0(  6$$  0"   0)  0)  0)  0)  6$$  0$2?/.  633  0%  0%  0"  0"  "//4  0"  0"  0"  0"  0"  0'  0+  0+  0+  0+  0+  6$$  633  0'  0'  0'  0'  0'  0'  0*  0*  0*  0*  0$  0$  6$$  633  0$  0$  0$  0$  0$  0$  0#  0#  0#  0!  0!  6$$  0) Figure 15. STM32F42x LQFP208 pinout 0%  0%  0%  0%  0%  6"!4  0)  0#  0#  0#  0)  0)  0)  633  6$$  0&  0&  0&  0)  0)  0)  0&  0&  0&  633  6$$  0&  0&  0&  0&  0&  0(  0(  .234  0#  0#  0#  0#  6$$  633!  62%&  6$$!  0!  0!  0!  0(  0(  0(  0(  0!  633  6$$  1. The above figure shows the package top view. ,1&0  0)  0)  0)  0(  0(  0(  6$$  633  6#!0  0!  0!  0!  0!  0!  0!  0#  0#  0#  0#  6$$  633  0'  0'  0'  0'  0'  0'  0'  0+  0+  0+  633  6$$  0*  0*  0*  0*  0*  0*  0$  0$  6$$  633  0$  0$  0$  0$  0$  0$  0"  0"  0" -36 Pinouts and pin description STM32F427xx STM32F429xx Pinouts and pin description STM32F427xx STM32F429xx Figure 16. STM32F42x UFBGA169 ballout              ! 0) 0) 0% "//4 0" 0' 0$ 0$ 0# 0! 0) " 0) 0% 0) 0% 0" 0" 0' 0$ 0$ 0# 0! 0) 0) # 0% 0% 0$2 ?/. 0" 0" 0' 0' 0$ 0$ 0# 0) 0( 0( $ 0% 0% 6$$ 0" 0" 6$$ 633 0$ 0$ 6$$ 633 6#!0 0( ? % 0# 0) 0) 0# 6"!4 6$$ 633 0! 0! 0! 0! 0! 0! & 0# 0& 0& 6$$ 633 633 6$$ 6$$ 0# 0# 0# 0# 0' ' 0( 0( 0& 0& 0& 0# 633 6$$ 633 6$$ 0' 0' 0' ( 0& .234 0& 6$$ 0# 0# 0# 6$$ 0% 0$ 0$ 0' 0' * 633! 62%& 62%& 6$$! 0! 633 633 0% 0% 633 6$$ 0$ 0$ + 0! 0! 0! 0! 0" 6$$ 0& 0% 0% 0( 0$ 0$ 0$ , 0( 0( 0( 0# 0" 6$$ 0& 0% 0" 0( 0( 0$ 0" - "90!33 ?2%' 0( 0! 0# 0& 0& 0' 0% 0" 0( 0( 0" 0" . 0! 0! 0" 0& 0' 0% 0% 6#!0 ? 0( 0( 0" -36 1. The above figure shows the package top view. 2. The 4 corners balls, A1,A13, N1 and N13, are not bonded internally and should be left not connected on the PCB. 48/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Figure 17. STM32F42x UFBGA176 ballout                ! 0% 0% 0% 0% 0" 0" 0' 0' 0" 0" 0$ 0# 0! 0! 0! " 0% 0% 0% 0" 0" 0" 0' 0' 0' 0' 0$ 0$ 0# 0# 0! # 6"!4 0) 0) 0) 6$$ 0$2?/. 6$$ 6$$ 6$$ 0' 0$ 0$ 0) 0) 0! $ 0# 0) 0) 0) 633 "//4 633 633 633 0$ 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0( 0( 0) 0!  & 0# 633 6$$ 0( 633 633 633 633 633 633 6#!0 0# 0!  ' 0( 633 6$$ 0( 633 633 633 633 633 633 6$$ 0# 0# ( 0( 0& 0& 0( 633 633 633 633 633 633 6$$ 0' 0# * .234 0& 0& 0( 633 633 633 633 633 6$$ 6$$ 0' 0' + 0& 0& 0& 6$$ 633 633 633 633 633 0( 0' 0' 0' , 0& 0& 0& "90!33? 2%' 0( 0( 0$ 0' - 633! 0# 0# 0# 0# 0" 0' 633 633 6#!0? 0( 0( 0( 0$ 0$ . 62%& 0! 0! 0! 0# 0& 0' 6$$ 6$$ 6$$ 0% 0( 0$ 0$ 0$ 0 62%& 0! 0! 0! 0# 0& 0& 0% 0% 0% 0% 0" 0" 0$ 0$ 2 6$$! 0!  0! 0" 0" 0& 0& 0% 0% 0% 0% 0" 0" 0" 0" 1. The above figure shows the package top view. AIC DocID024030 Rev 5 49/226 83 Pinouts and pin description STM32F427xx STM32F429xx Figure 18. STM32F42x TFBGA216 ballout      ! 0% 0% 0% 0' 0%           0% 0" 0" 0" 0" 0$ 0# 0! 0! 0! " 0% 0% 0' 0" 0" 0" 0' 0' 0* 0* 0$ 0$ 0# 0# 0! # 6"!4 0) 0) 0+ 0+ 0+ 0' 0' 0* 0$ 0$ 0$ 0) 0) 0! $ 0# 0& 0) 0) 0) 0) 0+ 0+ 0' 0* 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0$2? "//4 6$$ /. 6$$ 6$$ 6$$ 6#!0 0( 0( 0) 0! & 0# 633 0) 6$$ 6$$ 633 633 633 633 633 6$$ 0+ 0+ 0# 0! ' 0( 0& 0) 0) 6$$ 633 633 6$$ 0* 0+ 0# 0# ( 0( 0& 0) 0( 6$$ 633 633 6$$ 0* 0* 0' 0# * .234 0& 0( 0( 6$$ 633 633 6$$ 0* 0* 0' 0' + 0& 0& 0& 0( 6$$ 633 633 633 633 633 6$$ 0* 0$ 0" 0$ , 0& 0& 0& 0# "90!33 2%' 633 6$$ 6$$ 6$$ 6$$ 6#!0 0$ 0" 0$ 0$ - 633! 0# 0# 0# 0" 0& 0' 0& 0* 0$ 0$ 0' 0' 0* 0( . 62%& 0! 0! 0! 0# 0& 0' 0* 0% 0$ 0' 0' 0( 0( 0( 0 62%& 0! 0! 0! 0# 0& 0* 0& 0% 0% 0% 0" 0( 0( 0( 2 6$$! 0! 0! 0" 0" 0* 0* 0% 0% 0% 0% 0% 0" 0" 0" 1. The above figure shows the package top view. -36 50/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Name Pin name Pin type I/O structure Notes Alternate functions Table 9. Legend/abbreviations used in the pinout table Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT0 pin RST Bidirectional reset pin with weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 10. STM32F427xx and STM32F429xx pin and ball definitions Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 1 1 B2 A2 1 D8 1 A3 2 2 C1 A1 2 C10 2 A2 3 3 C2 B1 3 B11 3 A1 TRACECLK, SPI4_SCK, PE2 I/O FT SAI1_MCLK_A, ETH_MII_TXD3, FMC_A23, EVENTOUT TRACED0, PE3 I/O FT SAI1_SD_B, FMC_A19, EVENTOUT TRACED1, SPI4_NSS, PE4 I/O FT SAI1_FS_A, FMC_A20, DCMI_D4, LCD_B0, EVENTOUT DocID024030 Rev 5 51/226 83 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 4 4 D1 B2 4 D9 4 B1 5 5 D2 B3 5 E8 5 B2 -- - - - - - G6 -- - - - - - F5 6 6 E5 C1 6 C11 6 C1 - - NC (2) D2 7 - 7 C2 7 7 E4 D1 8 D10 8 D1 PE5 PE6 VSS VDD VBAT PI8 PC13 I/O FT TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, DCMI_D6, LCD_G0, EVENTOUT I/O FT TRACED3, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, FMC_A22, DCMI_D7, LCD_G1, EVENTOUT S S S (3) I/O FT (4) EVENTOUT (3) I/O FT (4) EVENTOUT TAMP_2 TAMP_1 PC14- (3) 8 8 E1 E1 9 D11 9 E1 OSC32_IN I/O FT (4) (PC14) EVENTOUT OSC32_IN (5) PC15- (3) 9 9 F1 F1 10 E11 10 F1 OSC32_OUT I/O FT (4) (PC15) EVENTOUT OSC32_ OUT(5) -- - - - - - G5 - - E2 D3 11 - 11 E4 VDD S CAN1_RX, FMC_D30, PI9 I/O FT LCD_VSYNC, EVENTOUT - - E3 E3 12 - 12 D5 PI10 I/O FT ETH_MII_RX_ER, FMC_D31, LCD_HSYNC, EVENTOUT - - NC (2) E4 13 - 13 F3 PI11 I/O FT OTG_HS_ULPI_DIR, EVENTOUT - - F6 F2 14 E7 14 F2 VSS S - - F4 F3 15 E10 15 F4 VDD S 52/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes - 10 F2 E2 16 F11 16 D2 - 11 F3 H3 17 E9 17 E2 - 12 G5 H2 18 F10 18 G2 -- - - - - 19 E3 -- - - - - 20 G3 -- - - - - 21 H3 - 13 G4 J2 19 G11 22 H2 - 14 G3 J3 20 F9 23 J2 - 15 H3 K3 21 F8 24 K3 10 16 G7 G2 22 H7 25 H6 11 17 G8 G3 23 - 26 H5 - 18 NC (2) K2 24 G10 27 K2 - 19 NC (2) K1 25 F7 28 K1 - 20 NC (2) L3 26 H11 29 L3 PF0 PF1 PF2 PI12 PI13 PI14 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 I/O FT I2C2_SDA, FMC_A0, EVENTOUT I/O FT I2C2_SCL, FMC_A1, EVENTOUT I/O FT I2C2_SMBA, FMC_A2, EVENTOUT I/O FT LCD_HSYNC, EVENTOUT I/O FT LCD_VSYNC, EVENTOUT I/O FT LCD_CLK, EVENTOUT I/O FT (5) FMC_A3, EVENTOUT ADC3_IN9 I/O FT (5) FMC_A4, EVENTOUT ADC3_ IN14 I/O FT (5) FMC_A5, EVENTOUT ADC3_ IN15 S S I/O FT (5) TIM10_CH1, SPI5_NSS, SAI1_SD_B, UART7_Rx, FMC_NIORD, EVENTOUT ADC3_IN4 I/O FT (5) TIM11_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_Tx, FMC_NREG, EVENTOUT ADC3_IN5 I/O FT (5) SPI5_MISO, SAI1_SCK_B, TIM13_CH1, FMC_NIOWR, EVENTOUT ADC3_IN6 DocID024030 Rev 5 53/226 83 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes - 21 NC (2) L2 27 G8 30 L2 SPI5_MOSI, PF9 I/O FT (5) SAI1_FS_B, TIM14_CH1, FMC_CD, ADC3_IN7 EVENTOUT - 22 H1 L1 28 G9 31 L1 PF10 I/O FT (5) FMC_INTR, DCMI_D11, LCD_DE, EVENTOUT ADC3_IN8 12 23 G2 G1 29 J11 32 G1 PH0-OSC_IN (PH0) I/O FT EVENTOUT OSC_IN(5) 13 24 G1 H1 30 H10 33 H1 PH1OSC_OUT (PH1) I/O FT EVENTOUT OSC_OUT (5) 14 25 H2 J1 31 H9 34 J1 NRST I/O RS T 15 26 G6 M2 32 H8 35 M2 PC0 I/O FT (5) OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT ADC123_ IN10 16 27 H5 M3 33 K11 36 M3 PC1 I/O FT (5) ETH_MDC, EVENTOUT ADC123_ IN11 17 28 H6 M4 34 J10 37 M4 SPI2_MISO, I2S2ext_SD, PC2 I/O FT (5) OTG_HS_ULPI_DIR, ETH_MII_TXD2, ADC123_ IN12 FMC_SDNE0, EVENTOUT 18 29 H7 M5 35 J9 38 L4 SPI2_MOSI/I2S2_SD, PC3 I/O FT (5) OTG_HS_ULPI_NXT, ETH_MII_TX_CLK, FMC_SDCKE0, ADC123_ IN13 EVENTOUT 19 30 - - 36 G7 39 J5 VDD S -- - - - - - J6 VSS S 20 31 J1 M1 37 K10 40 M1 VSSA S - - J2 N1 - - - N1 VREF– S 21 32 J3 P1 38 L11 41 P1 VREF+ S 54/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 22 33 J4 R1 39 L10 42 R1 23 34 J5 N3 40 K9 43 N3 24 35 K1 N2 41 K8 44 N2 25 36 K2 P2 42 L9 45 P2 - - L2 F4 43 - 46 K4 - - L1 G4 44 - 47 J4 - - M2 H4 45 - 48 H4 - - L3 J4 46 - 49 J3 26 37 K3 R2 47 M11 50 R2 27 38 - - - 51 K6 VDDA PA0-WKUP (PA0) PA1 PA2 PH2 PH3 PH4 PH5 PA3 VSS S TIM2_CH1/TIM2_ETR, I/O FT TIM5_CH1, TIM8_ETR, (6) USART2_CTS, UART4_TX, ADC123_ IN0/WKUP (5) ETH_MII_CRS, EVENTOUT TIM2_CH2, TIM5_CH2, USART2_RTS, I/O FT (5) UART4_RX, ETH_MII_RX_CLK/ETH ADC123_ IN1 _RMII_REF_CLK, EVENTOUT TIM2_CH3, TIM5_CH3, I/O FT (5) TIM9_CH1, USART2_TX, ETH_MDIO, EVENTOUT ADC123_ IN2 I/O FT ETH_MII_CRS, FMC_SDCKE0, LCD_R0, EVENTOUT I/O FT ETH_MII_COL, FMC_SDNE0, LCD_R1, EVENTOUT I/O FT I2C2_SCL, OTG_HS_ULPI_NXT, EVENTOUT I/O FT I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT TIM2_CH4, TIM5_CH4, TIM9_CH2, I/O FT (5) USART2_RX, OTG_HS_ULPI_D0, ETH_MII_COL, LCD_B5, EVENTOUT ADC123_ IN3 S DocID024030 Rev 5 55/226 83 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes - - M1 L4 48 N11 - L5 28 39 J11 K4 49 J8 52 K5 29 40 N2 N4 50 M10 53 N4 30 41 M3 P4 51 M9 54 P4 31 42 N3 P3 52 N10 55 P3 32 43 K4 R3 53 L8 56 R3 33 44 L4 N5 54 M8 57 N5 34 45 M4 P5 55 N9 58 P5 -- -- - - - J7 59 L7 - - - 60 L6 BYPASS_ REG VDD PA4 PA5 PA6 PA7 PC4 PC5 VDD VSS I FT S I/O TTa (5) SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, DCMI_HSYNC, LCD_VSYNC, EVENTOUT ADC12_ IN4 /DAC_ OUT1 I/O TTa (5) TIM2_CH1/TIM2_ETR, TIM8_CH1N, SPI1_SCK, OTG_HS_ULPI_CK, EVENTOUT ADC12_ IN5/DAC_ OUT2 TIM1_BKIN, TIM3_CH1, I/O FT (5) TIM8_BKIN, SPI1_MISO, TIM13_CH1, DCMI_PIXCLK, LCD_G2, EVENTOUT ADC12_ IN6 TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I/O FT (5) SPI1_MOSI, TIM14_CH1, ETH_MII_RX_DV/ETH_ RMII_CRS_DV, EVENTOUT ADC12_ IN7 ETH_MII_RXD0/ETH_ I/O FT (5) RMII_RXD0, EVENTOUT ADC12_ IN14 ETH_MII_RXD1/ETH_ I/O FT (5) RMII_RXD1, EVENTOUT ADC12_ IN15 S S 56/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 35 46 N4 R5 56 N8 61 R5 36 47 K5 R4 57 K7 62 R4 37 48 L5 M6 58 L7 63 M5 -- -- -- -- -- -- - - - - 64 G4 - - - 65 R6 - - - 66 R7 - - - 67 P7 - - - 68 N8 - - - 69 M9 - 49 M5 R6 59 M7 70 P8 - 50 N5 P6 60 N7 71 M6 - 51 G9 M8 61 - 72 K7 - 52 D10 N8 62 - 73 L8 - 53 M6 N6 63 K6 74 N6 - 54 K7 R7 64 L6 75 P6 - 55 L7 P7 65 M6 76 M8 - 56 N6 N7 66 N6 77 N7 - 57 M7 M7 67 K5 78 M7 PB0 PB1 PB2-BOOT1 (PB2) PI15 PJ0 PJ1 PJ2 PJ3 PJ4 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 TIM1_CH2N, TIM3_CH3, I/O FT (5) TIM8_CH2N, LCD_R3, OTG_HS_ULPI_D1, ETH_MII_RXD2, EVENTOUT TIM1_CH3N, TIM3_CH4, I/O FT (5) TIM8_CH3N, LCD_R6, OTG_HS_ULPI_D2, ETH_MII_RXD3, EVENTOUT I/O FT EVENTOUT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT LCD_R0, EVENTOUT LCD_R1, EVENTOUT LCD_R2, EVENTOUT LCD_R3, EVENTOUT LCD_R4, EVENTOUT LCD_R5, EVENTOUT SPI5_MOSI, FMC_SDNRAS, DCMI_D12, EVENTOUT FMC_A6, EVENTOUT FMC_A7, EVENTOUT FMC_A8, EVENTOUT FMC_A9, EVENTOUT FMC_A10, EVENTOUT FMC_A11, EVENTOUT ADC12_ IN8 ADC12_ IN9 DocID024030 Rev 5 57/226 83 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 38 58 N7 R8 68 L5 79 R8 39 59 J8 P8 69 M5 80 N9 40 60 K8 P9 70 N5 81 P9 - 61 J6 M9 71 H3 82 K8 - 62 G10 N9 72 J5 83 L9 41 63 L8 R9 73 J4 84 R9 42 64 M8 P10 74 K4 85 P10 43 65 N8 R10 75 L4 86 R10 44 66 H9 N11 76 N4 87 R12 45 67 J9 P11 77 M4 88 P11 46 68 K9 R11 78 L3 89 R11 47 69 L9 R12 79 M3 90 P12 48 70 M9 R13 80 N3 91 R13 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT TIM1_ETR, UART7_Rx, FMC_D4, EVENTOUT TIM1_CH1N, UART7_Tx, FMC_D5, EVENTOUT TIM1_CH1, FMC_D6, EVENTOUT TIM1_CH2N, FMC_D7, EVENTOUT TIM1_CH2, SPI4_NSS, FMC_D8, LCD_G3, EVENTOUT TIM1_CH3N, SPI4_SCK, FMC_D9, LCD_B4, EVENTOUT TIM1_CH3, SPI4_MISO, FMC_D10, LCD_DE, EVENTOUT TIM1_CH4, SPI4_MOSI, FMC_D11, LCD_CLK, EVENTOUT TIM1_BKIN, FMC_D12, LCD_R7, EVENTOUT TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER, LCD_G4, EVENTOUT TIM2_CH4, I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN/ETH_ RMII_TX_EN, LCD_G5, EVENTOUT 58/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 49 71 N9 M10 81 N2 92 L11 -- - - - H2 93 K9 50 72 F8 N10 82 J6 94 L10 -- - - - - 95 M14 - - N10 M11 83 - 96 P13 - - M10 N12 84 - 97 N13 - - L10 M12 85 - 98 P14 - - K10 M13 86 - 99 N14 - - N11 L13 87 - 100 P15 - - M11 L12 88 - 101 N15 - - L11 K12 89 - 102 M15 - - E7 H12 90 - - K10 - - H8 J12 91 - 103 K11 VCAP_1 S VSS S VDD S PJ5 I/O PH6 I/O FT PH7 I/O FT PH8 I/O FT PH9 I/O FT PH10 I/O FT PH11 I/O FT PH12 VSS VDD I/O FT S S LCD_R6, EVENTOUT I2C2_SMBA, SPI5_SCK, TIM12_CH1, ETH_MII_RXD2, FMC_SDNE1, DCMI_D8, EVENTOUT I2C3_SCL, SPI5_MISO, ETH_MII_RXD3, FMC_SDCKE1, DCMI_D9, EVENTOUT I2C3_SDA, FMC_D16, DCMI_HSYNC, LCD_R2, EVENTOUT I2C3_SMBA, TIM12_CH2, FMC_D17, DCMI_D0, LCD_R3, EVENTOUT TIM5_CH1, FMC_D18, DCMI_D1, LCD_R4, EVENTOUT TIM5_CH2, FMC_D19, DCMI_D2, LCD_R5, EVENTOUT TIM5_CH3, FMC_D20, DCMI_D3, LCD_R6, EVENTOUT DocID024030 Rev 5 59/226 83 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 51 73 N12 P12 92 M2 104 L13 52 74 M12 P13 93 N1 105 K14 53 75 M13 R14 94 K3 106 R14 54 76 L13 R15 95 J3 107 R15 55 77 L12 P15 96 L2 108 L15 56 78 K13 P14 97 M1 109 L14 57 79 K11 N15 98 H4 110 K15 PB12 PB13 PB14 PB15 PD8 PD9 PD10 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, CAN2_RX, OTG_HS_ULPI_D5, ETH_MII_TXD0/ETH_R MII_TXD0, OTG_HS_ID, EVENTOUT TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, CAN2_TX, OTG_HS_ULPI_D6, ETH_MII_TXD1/ETH_R MII_TXD1, EVENTOUT OTG_HS_ VBUS TIM1_CH2N, TIM8_CH2N, SPI2_MISO, I2S2ext_SD, USART3_RTS, TIM12_CH1, OTG_HS_DM, EVENTOUT RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, OTG_HS_DP, EVENTOUT USART3_TX, FMC_D13, EVENTOUT USART3_RX, FMC_D14, EVENTOUT USART3_CK, FMC_D15, LCD_B3, EVENTOUT 60/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 58 80 H10 N14 99 K2 111 N10 59 81 J13 N13 100 H6 112 M10 60 82 K12 M15 101 H5 113 M11 - 83 - - 102 - 114 J10 - 84 F7 J13 103 L1 115 J11 61 85 H11 M14 104 J2 116 L12 62 86 J12 L14 105 K1 117 K13 -- - - - - 118 K12 -- - - - - 119 J12 -- - - - - 120 H12 -- - - - - 121 J13 -- - - - - 122 H13 -- - - - - 123 G12 -- - - - - 124 H11 -- - - - - 125 H10 -- - - - - 126 G13 -- - - - - 127 F12 -- - - - - 128 F13 - 87 H13 L15 106 J1 129 M13 - 88 NC (2) K15 107 G3 130 M12 - 89 H12 K14 108 G5 131 N12 - 90 G13 K13 109 G6 132 N11 PD11 PD12 PD13 VSS VDD PD14 PD15 PJ6 PJ7 PJ8 PJ9 PJ10 PJ11 VDD VSS PK0 PK1 PK2 PG2 PG3 PG4 PG5 I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT USART3_CTS, FMC_A16, EVENTOUT TIM4_CH1, USART3_RTS, FMC_A17, EVENTOUT TIM4_CH2, FMC_A18, EVENTOUT TIM4_CH3, FMC_D0, EVENTOUT TIM4_CH4, FMC_D1, EVENTOUT LCD_R7, EVENTOUT LCD_G0, EVENTOUT LCD_G1, EVENTOUT LCD_G2, EVENTOUT LCD_G3, EVENTOUT LCD_G4, EVENTOUT LCD_G5, EVENTOUT LCD_G6, EVENTOUT LCD_G7, EVENTOUT FMC_A12, EVENTOUT FMC_A13, EVENTOUT FMC_A14/FMC_BA0, EVENTOUT FMC_A15/FMC_BA1, EVENTOUT DocID024030 Rev 5 61/226 83 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes - 91 G11 J15 110 G4 133 J15 - 92 G12 J14 111 H1 134 J14 - 93 F13 H14 112 G2 135 H14 - 94 J7 G12 113 D2 136 G10 - 95 E6 H13 114 G1 137 G11 63 96 F9 H15 115 F2 138 H15 64 97 F10 G15 116 F3 139 G15 65 98 F11 G14 117 E4 140 G14 66 99 F12 F14 118 E3 141 F14 67 100 E13 F15 119 F1 142 F15 PG6 PG7 PG8 VSS VDD PC6 PC7 PC8 PC9 PA8 I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT FMC_INT2, DCMI_D12, LCD_R7, EVENTOUT USART6_CK, FMC_INT3, DCMI_D13, LCD_CLK, EVENTOUT SPI6_NSS, USART6_RTS, ETH_PPS_OUT, FMC_SDCLK, EVENTOUT TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDIO_D6, DCMI_D0, LCD_HSYNC, EVENTOUT TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDIO_D7, DCMI_D1, LCD_G6, EVENTOUT TIM3_CH3, TIM8_CH3, USART6_CK, SDIO_D0, DCMI_D2, EVENTOUT MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, SDIO_D1, DCMI_D3, EVENTOUT MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, LCD_R6, EVENTOUT 62/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 68 101 E8 E15 120 E2 143 E15 PA9 I/O FT 69 102 E9 D15 121 D5 144 D15 PA10 I/O FT 70 103 E10 C15 122 D4 145 C15 PA11 I/O FT 71 104 E11 B15 123 E1 146 B15 PA12 I/O FT 72 105 E12 A15 124 D3 147 A15 73 106 D12 F13 125 D1 148 E11 74 107 J10 F12 126 D2 149 F10 75 108 H4 G13 127 C1 150 F11 - - D13 E12 128 - 151 E12 PA13 (JTMSSWDIO) VCAP_2 VSS VDD PH13 I/O FT S S S I/O FT - - C13 E13 129 - 152 E13 PH14 I/O FT - - C12 D13 130 - 153 D13 PH15 I/O FT - - B13 E14 131 - 154 E14 PI0 I/O FT TIM1_CH2, I2C3_SMBA, USART1_TX, DCMI_D0, EVENTOUT OTG_FS_ VBUS TIM1_CH3, USART1_RX, OTG_FS_ID, DCMI_D1, EVENTOUT TIM1_CH4, USART1_CTS, CAN1_RX, LCD_R4, OTG_FS_DM, EVENTOUT TIM1_ETR, USART1_RTS, CAN1_TX, LCD_R5, OTG_FS_DP, EVENTOUT JTMS-SWDIO, EVENTOUT TIM8_CH1N, CAN1_TX, FMC_D21, LCD_G2, EVENTOUT TIM8_CH2N, FMC_D22, DCMI_D4, LCD_G3, EVENTOUT TIM8_CH3N, FMC_D23, DCMI_D11, LCD_G4, EVENTOUT TIM5_CH4, SPI2_NSS/I2S2_WS(7), FMC_D24, DCMI_D13, LCD_G5, EVENTOUT DocID024030 Rev 5 63/226 83 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes - - C11 D14 132 - 155 D14 PI1 I/O FT - - B12 C14 133 - 156 C14 PI2 I/O FT - - A12 C13 134 - 157 C13 PI3 I/O FT - - D11 D9 135 F5 - F9 - - D3 C9 136 A1 158 E10 76 109 A11 A14 137 B1 159 A14 VSS VDD PA14 (JTCKSWCLK) S S I/O FT 77 110 B11 A13 138 C2 160 A13 PA15 (JTDI) I/O FT 78 111 C10 B14 139 A2 161 B14 PC10 I/O FT 79 112 B10 B13 140 B2 162 B13 PC11 I/O FT 80 113 A10 A12 141 C3 163 A12 PC12 I/O FT 81 114 D9 B12 142 B3 164 B12 PD0 I/O FT SPI2_SCK/I2S2_CK(7), FMC_D25, DCMI_D8, LCD_G6, EVENTOUT TIM8_CH4, SPI2_MISO, I2S2ext_SD, FMC_D26, DCMI_D9, LCD_G7, EVENTOUT TIM8_ETR, SPI2_MOSI/I2S2_SD, FMC_D27, DCMI_D10, EVENTOUT JTCK-SWCLK/ EVENTOUT JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS, SPI3_NSS/I2S3_WS, EVENTOUT SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, SDIO_D2, DCMI_D8, LCD_R2, EVENTOUT I2S3ext_SD, SPI3_MISO, USART3_RX, UART4_RX, SDIO_D3, DCMI_D4, EVENTOUT SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDIO_CK, DCMI_D9, EVENTOUT CAN1_RX, FMC_D2, EVENTOUT 64/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 82 115 C9 C12 143 C4 165 C12 83 116 B9 D12 144 A3 166 D12 84 117 A9 D11 145 B4 167 C11 85 118 D8 D10 146 B5 168 D11 86 119 C8 C11 147 A4 169 C10 - 120 - D8 148 - 170 F8 - 121 D6 C8 149 C5 171 E9 87 122 B8 B11 150 F4 172 B11 88 123 A8 A11 151 A5 173 A11 -- -- -- -- - - - - 174 B10 - - - 175 B9 - - - 176 C9 - - - 177 D10 - 124 NC (2) C10 152 E5 178 D9 PD1 PD2 PD3 PD4 PD5 VSS VDD PD6 PD7 PJ12 PJ13 PJ14 PJ15 PG9 I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT CAN1_TX, FMC_D3, EVENTOUT TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11, EVENTOUT SPI2_SCK/I2S2_CK, USART2_CTS, FMC_CLK, DCMI_D5, LCD_G7, EVENTOUT USART2_RTS, FMC_NOE, EVENTOUT USART2_TX, FMC_NWE, EVENTOUT SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, FMC_NWAIT, DCMI_D10, LCD_B2, EVENTOUT USART2_CK, FMC_NE1/FMC_NCE2, EVENTOUT LCD_B0, EVENTOUT LCD_B1, EVENTOUT LCD_B2, EVENTOUT LCD_B3, EVENTOUT USART6_RX, FMC_NE2/FMC_NCE3, DCMI_VSYNC(8), EVENTOUT DocID024030 Rev 5 65/226 83 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes - 125 C7 B10 153 C6 179 C8 - 126 B7 B9 154 B6 180 B8 - 127 A7 B8 155 A6 181 C7 - 128 NC (2) A8 156 D6 182 B3 - 129 NC (2) A7 157 F6 183 A4 - 130 D7 D7 158 - 184 F7 - 131 L6 C7 159 E6 185 E8 -- - - - - 186 D8 -- - - - - 187 D7 -- - - - - 188 C6 -- - - - - 189 C5 -- - - - - 190 C4 - 132 C6 B7 160 A7 191 B7 PG10 PG11 PG12 PG13 PG14 VSS VDD PK3 PK4 PK5 PK6 PK7 PG15 I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT LCD_G3, FMC_NCE4_1/FMC_N E3, DCMI_D2, LCD_B2, EVENTOUT ETH_MII_TX_EN/ETH_ RMII_TX_EN, FMC_NCE4_2, DCMI_D3, LCD_B3, EVENTOUT SPI6_MISO, USART6_RTS, LCD_B4, FMC_NE4, LCD_B1, EVENTOUT SPI6_SCK, USART6_CTS, ETH_MII_TXD0/ETH_R MII_TXD0, FMC_A24, EVENTOUT SPI6_MOSI, USART6_TX, ETH_MII_TXD1/ETH_R MII_TXD1, FMC_A25, EVENTOUT LCD_B4, EVENTOUT LCD_B5, EVENTOUT LCD_B6, EVENTOUT LCD_B7, EVENTOUT LCD_DE, EVENTOUT USART6_CTS, FMC_SDNCAS, DCMI_D13, EVENTOUT 66/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes PB3 89 133 B6 A10 161 B7 192 A10 (JTDO/TRACE I/O FT SWO) 90 134 A6 A9 162 C7 193 A9 PB4 (NJTRST) I/O FT 91 135 D5 A6 163 C8 194 A8 PB5 I/O FT 92 136 C5 B6 164 A8 195 B6 PB6 I/O FT 93 137 B5 B5 165 B8 196 B5 PB7 I/O FT 94 138 A5 D6 166 C9 197 E6 BOOT0 IB 95 139 D4 A5 167 A9 198 A7 PB8 I/O FT JTDO/TRACESWO, TIM2_CH2, SPI1_SCK, SPI3_SCK/I2S3_CK, EVENTOUT NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, EVENTOUT TIM3_CH2, I2C1_SMBA, SPI1_MOSI, SPI3_MOSI/I2S3_SD, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, FMC_SDCKE1, DCMI_D10, EVENTOUT TIM4_CH1, I2C1_SCL, USART1_TX, CAN2_TX, FMC_SDNE1, DCMI_D5, EVENTOUT TIM4_CH2, I2C1_SDA, USART1_RX, FMC_NL, DCMI_VSYNC, EVENTOUT VPP TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, ETH_MII_TXD3, SDIO_D4, DCMI_D6, LCD_B6, EVENTOUT DocID024030 Rev 5 67/226 83 Pinouts and pin description STM32F427xx STM32F429xx Table 10. STM32F427xx and STM32F429xx pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Alternate functions Additional functions LQFP100 LQFP144 UFBGA169 UFBGA176 LQFP176 WLCSP143 LQFP208 TFBGA216 Pin type I / O structure Notes 96 140 C4 B4 168 B9 199 B4 TIM4_CH4, TIM11_CH1, I2C1_SDA, PB9 I/O FT SPI2_NSS/I2S2_WS, CAN1_TX, SDIO_D5, DCMI_D7, LCD_B7, EVENTOUT 97 141 B4 A4 169 B10 200 A6 TIM4_ETR, PE0 I/O FT UART8_RX, FMC_NBL0, DCMI_D2, EVENTOUT 98 142 A4 A3 170 A10 201 A5 UART8_Tx, PE1 I/O FT FMC_NBL1, DCMI_D3, EVENTOUT 99 - F5 D5 - - 202 F6 VSS S - 143 C3 C6 171 A11 203 E5 PDR_ON S 100 144 K6 C5 172 D7 204 E7 - - B3 D4 173 - 205 C3 VDD S TIM8_BKIN, PI4 I/O FT FMC_NBL2, DCMI_D5, LCD_B4, EVENTOUT - - A3 C4 174 - 206 D3 TIM8_CH1, PI5 I/O FT FMC_NBL3, DCMI_VSYNC, LCD_B5, EVENTOUT - - A2 C3 175 - 207 D6 TIM8_CH2, FMC_D28, PI6 I/O FT DCMI_D6, LCD_B6, EVENTOUT - - B1 C2 176 - 208 D4 TIM8_CH3, FMC_D29, PI7 I/O FT DCMI_D7, LCD_B7, EVENTOUT 1. Function availability depends on the chosen device. 2. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid extra current consumption in low power modes. 3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 68/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description 4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 6. If the device is delivered in an WLCSP143, UFBGA169, UFBGA176, LQFP176 or TFBGA216 package, and the BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0 is used as an internal Reset (active low). 7. PI0 and PI1 cannot be used for I2S2 full-duplex mode. 8. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3. DocID024030 Rev 5 69/226 83 Pinouts and pin description STM32F427xx STM32F429xx Pin name PF0 PF1 PF2 PF3 PF4 PF5 PF12 PF13 PF14 PF15 PG0 PG1 PG2 PG3 PG4 PG5 PD11 PD12 PD13 PE3 PE4 PE5 PE6 PE2 PG13 PG14 PD14 PD15 PD0 PD1 PE7 PE8 PE9 PE10 Table 11. FMC pin definition CF NOR/PSRAM/ NOR/PSRAM SRAM Mux NAND16 A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 A8 A8 A9 A9 A10 A10 A11 A12 A13 A14 A15 A16 A16 CLE A17 A17 ALE A18 A18 A19 A19 A20 A20 A21 A21 A22 A22 A23 A23 A24 A24 A25 A25 D0 D0 DA0 D0 D1 D1 DA1 D1 D2 D2 DA2 D2 D3 D3 DA3 D3 D4 D4 DA4 D4 D5 D5 DA5 D5 D6 D6 DA6 D6 D7 D7 DA7 D7 SDRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 D0 D1 D2 D3 D4 D5 D6 D7 70/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Pinouts and pin description Pin name PE11 PE12 PE13 PE14 PE15 PD8 PD9 PD10 PH8 PH9 PH10 PH11 PH12 PH13 PH14 PH15 PI0 PI1 PI2 PI3 PI6 PI7 PI9 PI10 PD7 PG9 PG10 PG11 PG12 PD3 PD4 PD5 PD6 PB7 Table 11. FMC pin definition (continued) CF NOR/PSRAM/ NOR/PSRAM SRAM Mux NAND16 D8 D8 DA8 D8 D9 D9 DA9 D9 D10 D10 DA10 D10 D11 D11 DA11 D11 D12 D12 DA12 D12 D13 D13 DA13 D13 D14 D14 DA14 D14 D15 D15 DA15 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 NE1 NE2 NCE4_1 NE3 NCE4_2 NE1 NCE2 NE2 NCE3 NE3 NE4 NE4 NOE NWE NWAIT CLK NOE NWE NWAIT CLK NOE NWE NWAIT NOE NWE NWAIT NL(NADV) NL(NADV) SDRAM D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DocID024030 Rev 5 71/226 83 Pinouts and pin description STM32F427xx STM32F429xx Pin name PF6 PF7 PF8 PF9 PF10 PG6 PG7 PE0 PE1 PI4 PI5 PG8 PC0 PF11 PG15 PH2 PH3 PH6 PH7 PH5 PC2 PC3 PB5 PB6 Table 11. FMC pin definition (continued) CF NOR/PSRAM/ NOR/PSRAM SRAM Mux NAND16 NIORD NREG NIOWR CD INTR INT2 NBL0 NBL1 NBL2 NBL0 NBL1 INT3 NBL3 SDRAM NBL0 NBL1 NBL2 NBL3 SDCLK SDNWE SDNRAS SDNCAS SDCKE0 SDNE0 SDNE1 SDCKE1 SDNWE SDNE0 SDCKE0 SDCKE1 SDNE1 72/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Table 12. STM32F427xx and STM32F429xx alternate function mapping AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS ETH FMC/SDIO /OTG2_FS DCMI LCD SYS DocID024030 Rev 5 PA0 - TIM2_ CH1/TIM2 _ETR TIM5_ CH1 PA1 - TIM2_ CH2 TIM5_ CH2 PA2 - PA3 - TIM2_ CH3 TIM2_ CH4 TIM5_ CH3 TIM5_ CH4 PA4 - - - PA5 Port A PA6 TIM2_ - CH1/TIM2 - _ETR - TIM1_ BKIN TIM3_ CH1 PA7 - TIM1_ CH1N TIM3_ CH2 PA8 MCO1 TIM1_ CH1 - PA9 - TIM1_ CH2 - PA10 - TIM1_ CH3 - PA11 - TIM1_ CH4 - PA12 - TIM1_ ETR - TIM8_ ETR - - - USART2_ CTS UART4_TX - - ETH_MII_ CRS - - - EVEN TOUT - - - - USART2_ RTS UART4_RX - ETH_MII_ - RX_CLK/E TH_RMII_ - REF_CLK - - EVEN TOUT TIM9_ CH1 - - - USART2_ TX - - - ETH_ MDIO - - - EVEN TOUT TIM9_ CH2 - - - USART2_ RX - - OTG_HS_ ETH_MII_ ULPI_D0 COL - - LCD_B5 EVEN TOUT - - SPI1_ NSS SPI3_ NSS/ I2S3_WS USART2_ CK - - - - OTG_HS_ DCMI_ LCD_ EVEN SOF HSYNC VSYNC TOUT TIM8_ CH1N - SPI1_ SCK - - - - OTG_HS_ ULPI_CK - - - - EVEN TOUT TIM8_ BKIN - SPI1_ MISO - - - TIM13_CH1 - - - DCMI_ PIXCLK LCD_G2 EVEN TOUT TIM8_ CH1N - SPI1_ MOSI - - ETH_MII_ - TIM14_CH1 - RX_DV/ ETH_RMII - _CRS_DV - - EVEN TOUT - I2C3_ SCL - - USART1_ CK - - OTG_FS_ SOF - - - LCD_R6 EVEN TOUT - I2C3_ SMBA - - USART1_ TX - - - - - DCMI_ D0 - EVEN TOUT - - - - USART1_ RX - - OTG_FS_ ID - - DCMI_ D1 - EVEN TOUT - - - - USART1_ CTS - CAN1_RX OTG_FS_ DM - - - LCD_R4 EVEN TOUT - - - - USART1_ RTS - CAN1_TX OTG_FS_ DP - - - LCD_R5 EVEN TOUT Pinouts and pin description 73/226 Pinouts and pin description 74/226 Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS ETH FMC/SDIO /OTG2_FS DCMI LCD SYS DocID024030 Rev 5 JTMS- PA13 SWDI - - - - - - - - O JTCK- Port A PA14 SWCL - - - - - - - - K TIM2_ PA15 JTDI CH1/TIM2 - _ETR - - SPI1_ NSS SPI3_ NSS/ I2S3_WS - - PB0 - TIM1_ CH2N TIM3_ CH3 TIM8_ CH2N - - - - - PB1 - TIM1_ CH3N TIM3_ CH4 TIM8_ CH3N - - - - - PB2 - - - - - - - - - JTDO/ PB3 TRAC ESWO TIM2_ CH2 - - - SPI1_ SCK SPI3_ SCK/ I2S3_CK - - PB4 NJTR ST - TIM3_ CH1 - - SPI1_ MISO SPI3_ MISO I2S3ext_ SD - Port B PB5 - - TIM3_ CH2 - I2C1_ SMBA SPI1_ MOSI SPI3_ MOSI/ I2S3_SD - - PB6 - - TIM4_ CH1 - I2C1_ SCL - - USART1_ TX - PB7 - - TIM4_ CH2 - I2C1_ SDA - - USART1_ RX - PB8 - - TIM4_ CH3 TIM10_ I2C1_ CH1 SCL - - - - PB9 - - TIM4_ CH4 TIM11_ CH1 I2C1_ SDA SPI2_ NSS/I2 S2_WS - - - PB10 - TIM2_ CH3 - - I2C2_ SCL SPI2_ SCK/I2 S2_CK - USART3_ TX - - - - - - - EVEN TOUT - - - - - - EVEN TOUT - - - - - - EVEN TOUT LCD_R3 OTG_HS_ ETH_MII_ ULPI_D1 RXD2 - LCD_R6 OTG_HS_ ETH_MII_ ULPI_D2 RXD3 - - - - - - - EVEN TOUT - - EVEN TOUT - - EVEN TOUT - - - - - - EVEN TOUT - - - - - - EVEN TOUT CAN2_RX OTG_HS_ ETH_PPS ULPI_D7 _OUT FMC_ SDCKE1 DCMI_ D10 - EVEN TOUT CAN2_TX - CAN1_RX - - FMC_ SDNE1 DCMI_ D5 - EVEN TOUT - - FMC_NL DCMI_ VSYNC - EVEN TOUT - ETH_MII_ TXD3 SDIO_D4 DCMI_ D6 LCD_B6 EVEN TOUT CAN1_TX - - SDIO_D5 DCMI_ D7 LCD_B7 EVEN TOUT - OTG_HS_ ETH_MII_ ULPI_D3 RX_ER - - LCD_G4 EVEN TOUT STM32F427xx STM32F429xx STM32F427xx STM32F429xx Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS ETH FMC/SDIO /OTG2_FS DCMI LCD SYS DocID024030 Rev 5 PB11 - TIM2_ CH4 PB12 - TIM1_ BKIN Port B PB13 - TIM1_ CH1N PB14 - TIM1_ CH2N PB15 RTC_ REFIN TIM1_ CH3N PC0 - - PC1 - - PC2 - - PC3 - - Port C PC4 - - PC5 - - PC6 - - PC7 - - - - - - - TIM3_ CH1 TIM3_ CH2 - - - TIM8_ CH2N TIM8_ CH3N - - - - TIM8_ CH1 TIM8_ CH2 I2C2_ SDA - - USART3_ RX - I2C2_ SMBA SPI2_ NSS/I2 S2_WS - USART3_ CK - SPI2_ - SCK/I2 S2_CK - USART3_ CTS - - SPI2_ I2S2ext_ USART3_ MISO SD RTS - SPI2_ - MOSI/I2 - - - S2_SD - - - - - - - - - - - SPI2_ I2S2ext_ MISO SD - - SPI2_ - MOSI/I2 - - - S2_SD - - - - - - - - - I2S2_ MCK - - - I2S3_ MCK - - - USART6_ TX - USART6_ RX ETH_MII_ - OTG_HS_ TX_EN/ ULPI_D4 ETH_RMII - _TX_EN CAN2_RX OTG_HS_ ULPI_D5 ETH_MII_ TXD0/ETH _RMII_ TXD0 OTG_HS_ ID ETH_MII_ CAN2_TX OTG_HS_ TXD1/ETH ULPI_D6 _RMII_TX - D1 TIM12_CH1 - - OTG_HS_ DM TIM12_CH2 - - OTG_HS_ DP - OTG_HS_ ULPI_STP - FMC_SDN WE - - ETH_MDC - - OTG_HS_ ETH_MII_ ULPI_DIR TXD2 FMC_ SDNE0 - OTG_HS_ ETH_MII_ FMC_ ULPI_NXT TX_CLK SDCKE0 ETH_MII_ - - RXD0/ETH _RMII_ - RXD0 ETH_MII_ - - RXD1/ETH _RMII_ - RXD1 - - - SDIO_D6 - - - SDIO_D7 - - - - - DCMI_ D0 DCMI_ D1 LCD_G5 EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT LCD_ EVEN HSYNC TOUT LCD_G6 EVEN TOUT Pinouts and pin description 75/226 DocID024030 Rev 5 76/226 Port AF0 SYS PC8 - PC9 MCO2 PC10 - PC11 - Port C PC12 - PC13 - PC14 - PC15 - PD0 - PD1 - PD2 - Port PD3 - D PD4 - PD5 - PD6 - AF1 TIM1/2 - Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS TIM3_ CH3 TIM8_ CH3 - - - - USART6_ CK - - TIM3_ CH4 TIM8_ I2C3_ I2S_ CH4 SDA CKIN - - - - - - - - - SPI3_ SCK/I2S 3_CK USART3_ TX UART4_TX - - - - - I2S3ext _SD SPI3_ MISO USART3_ RX UART4_RX - - - - - - SPI3_ MOSI/I2 S3_SD USART3_ CK UART5_TX - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CAN1_RX - - - TIM3_ ETR - - - - - - - - - - - - - - CAN1_TX - - - - - UART5_RX - - SPI2_S - CK/I 2S2_CK - USART2_ CTS - - - - USART2_ RTS - - - - USART2_ TX - - SPI3_ MOSI/I2 S3_SD SAI1_ SD_A USART2_ RX - - - - - - - - - ETH - FMC/SDIO /OTG2_FS DCMI LCD SYS SDIO_D0 SDIO_D1 DCMI_ D2 DCMI_ D3 - EVEN TOUT - EVEN TOUT SDIO_D2 DCMI_ D8 LCD_R2 EVEN TOUT SDIO_D3 DCMI_ D4 - EVEN TOUT SDIO_CK DCMI_ D9 - EVEN TOUT - - - - - - FMC_D2 - FMC_D3 - SDIO_ CMD DCMI_ D11 - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT - EVEN TOUT FMC_CLK DCMI_ D5 LCD_G7 EVEN TOUT FMC_NOE - FMC_NWE - - EVEN TOUT - EVEN TOUT FMC_ NWAIT DCMI_ D10 LCD_B2 EVEN TOUT STM32F427xx STM32F429xx Pinouts and pin description 77/226 DocID024030 Rev 5 Port AF0 SYS PD7 - PD8 - PD9 - PD10 - Port D PD11 - PD12 - PD13 - PD14 - PD15 - PE0 - PE1 - PE2 Port E PE3 PE4 PE5 PE6 TRAC ECLK TRAC ED0 TRAC ED1 TRAC ED2 TRAC ED3 Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 TIM1/2 - TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS ETH FMC/SDIO /OTG2_FS DCMI LCD SYS - - - - - USART2_ CK - - - - - - - - - - - - - - - - - - TIM4_ CH1 - - - TIM4_ CH2 - - - TIM4_ CH3 - - - TIM4_ CH4 - - - TIM4_ ETR - - - - USART3_ TX - - - USART3_ RX - - - USART3_ CK - - - USART3_ CTS - - - USART3_ RTS - - - - - - - - - - - - - - - - UART8_Rx - - - - - - - UART8_Tx - - - - SPI4_ SAI1_ SCK MCLK_A - - - - - - - SAI1_ SD_B - - - - - - SPI4_ NSS SAI1_ FS_A - - - - TIM9_ CH1 - SPI4_M SAI1_ ISO SCK_A - - - - TIM9_ CH2 - SPI4_ MOSI SAI1_ SD_A - - - - FMC_NE1/ - FMC_ - NCE2 - EVEN TOUT - - FMC_D13 - - EVEN TOUT - - FMC_D14 - - EVEN TOUT - - FMC_D15 - LCD_B3 EVEN TOUT - - FMC_A16 - - EVEN TOUT - - FMC_A17 - - EVEN TOUT - - FMC_A18 - - EVEN TOUT - - FMC_D0 - - EVEN TOUT - - FMC_D1 - - EVEN TOUT - - FMC_ NBL0 DCMI_ D2 - EVEN TOUT - - FMC_ NBL1 DCMI_ D3 - EVEN TOUT - ETH_MII_ TXD3 FMC_A23 - - EVEN TOUT - - FMC_A19 - - EVEN TOUT - - FMC_A20 DCMI_ D4 LCD_B0 EVEN TOUT - - FMC_A21 DCMI_ D6 LCD_G0 EVEN TOUT - - FMC_A22 DCMI_ D7 LCD_G1 EVEN TOUT Pinouts and pin description STM32F427xx STM32F429xx DocID024030 Rev 5 78/226 Port AF0 SYS PE7 - PE8 - PE9 - PE10 - Port E PE11 - PE12 - PE13 - PE14 - PE15 - PF0 - PF1 - PF2 - PF3 - Port F PF4 - PF5 - PF6 - PF7 - Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 TIM1/2 TIM1_ ETR TIM1_ CH1N TIM1_ CH1 TIM1_ CH2N TIM1_ CH2 TIM1_ CH3N TIM1_ CH3 TIM1_ CH4 TIM1_ BKIN - - - TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS - - - - - - UART7_Rx - - - - - - - - UART7_Tx - - - - - - - - - - - - - - - - - - - - - - - SPI4_ NSS - - - - - - SPI4_ SCK - - - - - - SPI4_ MISO - - - - - - SPI4_ MOSI - - - - - - - - - - - - - - - - - - - - - I2C2_ SDA - - - - - - I2C2_ SCL - - - - - - - - I2C2_ SMBA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - TIM10_ CH1 - SPI5_ NSS SAI1_ SD_B - UART7_Rx - - - - TIM11_ CH1 - SPI5_ SAI1_ SCK MCLK_B - UART7_Tx - - ETH - FMC/SDIO /OTG2_FS DCMI LCD SYS FMC_D4 - - EVEN TOUT FMC_D5 - - EVEN TOUT FMC_D6 - - EVEN TOUT FMC_D7 - - EVEN TOUT FMC_D8 - LCD_G3 EVEN TOUT FMC_D9 - LCD_B4 EVEN TOUT FMC_D10 - LCD_DE EVEN TOUT FMC_D11 - LCD_ EVEN CLK TOUT FMC_D12 - LCD_R7 EVEN TOUT FMC_A0 - - EVEN TOUT FMC_A1 - - EVEN TOUT FMC_A2 - - EVEN TOUT FMC_A3 - - EVEN TOUT FMC_A4 - - EVEN TOUT FMC_A5 - - EVEN TOUT FMC_ NIORD - - EVEN TOUT FMC_ NREG - - EVEN TOUT STM32F427xx STM32F429xx Pinouts and pin description 79/226 DocID024030 Rev 5 Port AF0 SYS PF8 - PF9 - PF10 - PF11 - Port F PF12 - PF13 - PF14 - PF15 - PG0 - PG1 - PG2 - PG3 - Port G PG4 - PG5 - PG6 - PG7 - PG8 - Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 TIM1/2 - TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS ETH FMC/SDIO /OTG2_FS DCMI LCD SYS - - - SPI5_ SAI1_ MISO SCK_B - - TIM13_CH1 - - FMC_ NIOWR - - EVEN TOUT - - - SPI5_ MOSI SAI1_ FS_B - - TIM14_CH1 - - FMC_CD - - EVEN TOUT - - - - - - - - - - FMC_INTR DCMI_ D11 LCD_DE EVEN TOUT - - - SPI5_ MOSI - - - - - - FMC_ DCMI_ SDNRAS D12 - EVEN TOUT - - - - - - - - - - FMC_A6 - - EVEN TOUT - - - - - - - - - - FMC_A7 - - EVEN TOUT - - - - - - - - - - FMC_A8 - - EVEN TOUT - - - - - - - - - - FMC_A9 - - EVEN TOUT - - - - - - - - - - FMC_A10 - - EVEN TOUT - - - - - - - - - - FMC_A11 - - EVEN TOUT - - - - - - - - - - FMC_A12 - - EVEN TOUT - - - - - - - - - - FMC_A13 - - EVEN TOUT - - - - - - - - - - FMC_A14/ FMC_BA0 - - EVEN TOUT - - - - - - - - - - FMC_A15/ FMC_BA1 - - EVEN TOUT - - - - - - - - - - FMC_INT2 DCMI_ D12 LCD_R7 EVEN TOUT - - - - - - USART6_ CK - - - FMC_INT3 DCMI_ D13 LCD_ EVEN CLK TOUT - - - SPI6_ NSS - - USART6_ RTS - - ETH_PPS FMC_SDC _OUT LK - - EVEN TOUT Pinouts and pin description STM32F427xx STM32F429xx DocID024030 Rev 5 80/226 Port AF0 SYS PG9 - PG10 - PG11 - Port G PG12 - PG13 - PG14 - PG15 - PH0 - PH1 - PH2 - Port H PH3 - PH4 - PH5 - PH6 - Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 TIM1/2 - - - TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS ETH FMC/SDIO /OTG2_FS DCMI LCD SYS - - - - - - USART6_ RX - - - FMC_NE2/ FMC_ NCE3 DCMI_ VSYNC (1) - EVEN TOUT - - - - - - - LCD_G3 - - FMC_ NCE4_1/ FMC_NE3 DCMI_ D2 LCD_B2 EVEN TOUT - - - - - - - ETH_MII_ - - TX_EN/ FMC_ ETH_RMII NCE4_2 DCMI_ D3 LCD_B3 EVEN TOUT _TX_EN - - - SPI6_ MISO - - USART6_ RTS LCD_B4 - - FMC_NE4 - LCD_B1 EVEN TOUT - - - SPI6_ SCK - - USART6_ CTS - ETH_MII_ - TXD0/ ETH_RMII FMC_A24 - _TXD0 - EVEN TOUT - - - SPI6_ MOSI - - USART6_ TX - ETH_MII_ - TXD1/ ETH_RMII FMC_A25 - _TXD1 - EVEN TOUT - - - - - - USART6_ CTS - - - FMC_ DCMI_ SDNCAS D13 - EVEN TOUT - - - - - - - - - - - - - EVEN TOUT - - - - - - - - - - - - - EVEN TOUT - - - - - - - - - ETH_MII_ FMC_ CRS SDCKE0 - LCD_R0 EVEN TOUT - - - - - - - - - ETH_MII_ FMC_SDN COL E0 - LCD_R1 EVEN TOUT - - I2C2_ SCL - - - - - OTG_HS_ ULPI_NXT - - - - EVEN TOUT - - I2C2_ SPI5_N SDA SS - - - - - - FMC_SDN WE - - EVEN TOUT - - I2C2_ SPI5_ SMBA SCK - - - TIM12_CH1 - - FMC_ SDNE1 DCMI_ D8 - - STM32F427xx STM32F429xx Pinouts and pin description 81/226 DocID024030 Rev 5 Port AF0 SYS PH7 - PH8 - PH9 - PH10 - Port H PH11 - PH12 - PH13 - PH14 - PH15 - PI0 - PI1 - PI2 - Port I PI3 - PI4 - PI5 - PI6 - Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 TIM1/2 - - TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS ETH FMC/SDIO /OTG2_FS DCMI LCD SYS - - I2C3_ SPI5_ SCL MISO - - - - I2C3_ SDA - - - - - I2C3_ SMBA - - - TIM5_ CH1 - - - - - TIM5_ CH2 - - - - - TIM5_ CH3 - - - - - - TIM8_ CH1N - - - - - TIM8_ CH2N - - - - - TIM8_ CH3N - - - - TIM5_ CH4 - SPI2_ - NSS/I2 - S2_WS - SPI2_ - - - SCK/I2 - - S2_CK - TIM8_ CH4 - SPI2_ I2S2ext_ MISO SD - - TIM8_ ETR SPI2_M - OSI/I2S 2_SD - TIM8_ BKIN - - - - - TIM8_ CH1 - - - - - TIM8_ CH2 - - - - - - - ETH_MII_ FMC_ RXD3 SDCKE1 DCMI_ D9 - - - - - - FMC_D16 DCMI_ HSYNC LCD_R2 EVEN TOUT - TIM12_CH2 - - FMC_D17 DCMI_ D0 LCD_R3 EVEN TOUT - - - - FMC_D18 DCMI_ D1 LCD_R4 EVEN TOUT - - - - FMC_D19 DCMI_ D2 LCD_R5 EVEN TOUT - - - - FMC_D20 DCMI_ D3 LCD_R6 EVEN TOUT - CAN1_TX - - FMC_D21 - LCD_G2 EVEN TOUT - - - - FMC_D22 DCMI_ D4 LCD_G3 EVEN TOUT - - - - FMC_D23 DCMI_ D11 LCD_G4 EVEN TOUT - - - - FMC_D24 DCMI_ D13 LCD_G5 EVEN TOUT - - - - FMC_D25 DCMI_ D8 LCD_G6 EVEN TOUT - - - - FMC_D26 DCMI_ D9 LCD_G7 EVEN TOUT FMC_D27 DCMI_D 10 EVEN TOUT - - - - FMC_ NBL2 DCMI_D 5 LCD_B4 EVEN TOUT - - - - FMC_ NBL3 DCMI_ VSYNC LCD_B5 EVEN TOUT - - - - FMC_D28 DCMI_ D6 LCD_B6 EVEN TOUT Pinouts and pin description STM32F427xx STM32F429xx DocID024030 Rev 5 82/226 Port AF0 SYS PI7 - PI8 - PI9 - PI10 - Port I PI11 - PI12 - PI13 - PI14 - PI15 - PJ0 - PJ1 - PJ2 - PJ3 - Port J PJ4 - PJ5 - PJ6 - PJ7 - Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 TIM1/2 - TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS ETH FMC/SDIO /OTG2_FS DCMI LCD SYS - TIM8_ CH3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - FMC_D29 DCMI_ D7 LCD_B7 EVEN TOUT - - - - - - - EVEN TOUT - CAN1_RX - - FMC_D30 - LCD_ EVEN VSYNC TOUT - - - ETH_MII_ RX_ER FMC_D31 - LCD_ EVEN HSYNC TOUT - - OTG_HS_ ULPI_DIR - - - - EVEN TOUT - - - - - - LCD_ EVEN HSYNC TOUT - - - - - - LCD_ EVEN VSYNC TOUT - - - - - - LCD_ EVEN CLK TOUT - - - - - - LCD_R0 EVEN TOUT - - - - - - LCD_R1 EVEN TOUT - - - - - - LCD_R2 EVEN TOUT - - - - - - LCD_R3 EVEN TOUT - - - - - - LCD_R4 EVEN TOUT - - - - - - LCD_R5 EVEN TOUT - - - - - - LCD_R6 EVEN TOUT - - - - - - LCD_R7 EVEN TOUT - - - - - - LCD_G0 EVEN TOUT STM32F427xx STM32F429xx Pinouts and pin description STM32F427xx STM32F429xx Table 12. STM32F427xx and STM32F429xx alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port SYS TIM1/2 TIM3/4/5 TIM8/9/ 10/11 I2C1/ 2/3 SPI1/2/ 3/4/5/6 SPI2/3/ SAI1 SPI3/ USART6/ CAN1/2/ OTG2_HS USART1/ UART4/5/7 TIM12/13/14 /OTG1_ 2/3 /8 /LCD FS ETH FMC/SDIO /OTG2_FS DCMI LCD SYS DocID024030 Rev 5 PJ8 - - - - - - - - - - - - - - LCD_G1 EVEN TOUT PJ9 - - - - - - - - - - - - - - LCD_G2 EVEN TOUT PJ10 - - - - - - - - - - - - - - LCD_G3 EVEN TOUT PJ11 - - - - - - - - - Port J PJ12 - - - - - - - - - - - - - - LCD_G4 EVEN TOUT - - - - - LCD_B0 EVEN TOUT PJ13 - - - - - - - - - - - - - - LCD_B1 EVEN TOUT PJ14 - - - - - - - - - - - - - - LCD_B2 EVEN TOUT PJ15 - - - - - - - - - - - - - - LCD_B3 EVEN TOUT PK0 - - - - - - - - - - - - - - LCD_G5 EVEN TOUT PK1 - - - - - - - - - - - - - - LCD_G6 EVEN TOUT PK2 - - - - - - - - - - - - - - LCD_G7 EVEN TOUT PK3 - - - - - - - - - Port K PK4 - - - - - - - - - - - - - - LCD_B4 EVEN TOUT - - - - - LCD_B5 EVEN TOUT PK5 - - - - - - - - - - - - - - LCD_B6 EVEN TOUT PK6 - - - - - - - - - - - - - - LCD_B7 EVEN TOUT PK7 - - - - - - - - - - - - - - LCD_DE EVEN TOUT 1. The DCMI_VSYNC alternate function on PG9 is only available on silicon revision 3. Pinouts and pin description 83/226 Memory mapping 5 Memory mapping STM32F427xx STM32F429xx The memory map is shown in Figure 19. Figure 19. Memory map [)))))))) 0E\WH %ORFN &RUWH[0 ,QWHUQDO SHULSKHUDOV [( ['))))))) [' [&))))))) 0E\WH %ORFN )0& 0E\WH %ORFN )0& [$ [))))))) [ [))))))) [ [))))))) 0E\WH %ORFN )0&EDQNWR EDQN 0E\WH %ORFN )0&EDQNWR EDQN [ [))))))) [ [))))))) [ 0E\WH %ORFN 3HULSKHUDOV 0E\WH %ORFN 65$0 0E\WH %ORFN 65$0 5HVHUYHG &RUWH[0LQWHUQDO SHULSKHUDOV $+% 5HVHUYHG $+% [([)))))))) [([())))) [['))))))) [&[))))))) [%)) 5HVHUYHG [ [[))))))) [)))) $+% 5HVHUYHG [ [&[)))) [%)) $3% 5HVHUYHG 65$0 .%DOLDVHG %\ELWEDQGLQJ 65$0 .%DOLDVHG %\ELWEDQGLQJ 65$0 .%DOLDVHG %\ELWEDQGLQJ 5HVHUYHG 2SWLRQ%\WHV 5HVHUYHG 6\VWHPPHPRU\ 5HVHUYHG 2SWLRQE\WHV 5HVHUYHG &&0GDWD5$0  .%GDWD65$0 5HVHUYHG )ODVKPHPRU\ 5HVHUYHG $OLDVHGWR)ODVKV\VWHP PHPRU\RU65$0GHSHQGLQJ RQWKH%227SLQV [[))))))) [[)))) [&[)))) [[%))) [)))&)[))))))) [)))&[)))& [)))$[)))))) [)))[)))$) [))(&)[))()))) [))(&[))(& [[))(%))) [[)))) [[))))))) [[))))) [[)))))) [[))))) 5HVHUYHG $3% [ [[)))) [))) [ 069 84/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Memory mapping Table 13. STM32F427xx and STM32F429xx register boundary addresses Bus Boundary address Peripheral Cortex-M4 0xE00F FFFF - 0xFFFF FFFF 0xE000 0000 - 0xE00F FFFF 0xD000 0000 - 0xDFFF FFFF 0xC000 0000 - 0xCFFF FFFF Reserved Cortex-M4 internal peripherals FMC bank 6 FMC bank 5 0xA000 1000 - 0xBFFF FFFF Reserved AHB3 0xA000 0000- 0xA000 0FFF 0x9000 0000 - 0x9FFF FFFF 0x8000 0000 - 0x8FFF FFFF 0x7000 0000 - 0x7FFF FFFF FMC control register FMC bank 4 FMC bank 3 FMC bank 2 0x6000 0000 - 0x6FFF FFFF 0x5006 0C00- 0x5FFF FFFF 0x5006 0800 - 0X5006 0BFF 0x5005 0400 - X5006 07FF FMC bank 1 Reserved RNG Reserved AHB2 0x5005 0000 - 0X5005 03FF DCMI 0x5004 0000- 0x5004 FFFF 0x5000 0000 - 0X5003 FFFF Reserved USB OTG FS DocID024030 Rev 5 85/226 88 Memory mapping STM32F427xx STM32F429xx Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued) Bus Boundary address Peripheral 0x4008 0000- 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 BC00- 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF DMA2D 0x4002 9400 - 0x4002 AFFF Reserved 0x4002 9000 - 0x4002 93FF 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF ETHERNET MAC 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0X4002 5000 - 0X4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM AHB1 0x4002 3C00 - 0x4002 3FFF 0x4002 3800 - 0x4002 3BFF Flash interface register RCC 0X4002 3400 - 0X4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF GPIOK 0x4002 2400 - 0x4002 27FF GPIOJ 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0X4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA 86/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Memory mapping Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued) Bus Boundary address Peripheral 0x4001 6C00- 0x4001 FFFF Reserved 0x4001 6800 - 0x4001 6BFF LCD-TFT 0x4001 5C00 - 0x4001 67FF Reserved 0x4001 5800 - 0x4001 5BFF SAI1 0x4001 5400 - 0x4001 57FF SPI6 0x4001 5000 - 0x4001 53FF SPI5 0x4001 5400 - 0x4001 57FF SPI6 0x4001 5000 - 0x4001 53FF SPI5 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 APB2 0x4001 3C00 - 0x4001 3FFF 0x4001 3800 - 0x4001 3BFF EXTI SYSCFG 0x4001 3400 - 0x4001 37FF SPI4 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 DocID024030 Rev 5 87/226 88 Memory mapping STM32F427xx STM32F429xx Table 13. STM32F427xx and STM32F429xx register boundary addresses (continued) Bus Boundary address Peripheral 0x4000 8000- 0x4000 FFFF Reserved 0x4000 7C00 - 0x4000 7FFF UART8 0x4000 7800 - 0x4000 7BFF UART7 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 APB1 0x4000 4000 - 0x4000 43FF 0x4000 3C00 - 0x4000 3FFF I2S3ext SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 88/226 DocID024030 Rev 5 STM32F427xx STM32F429xx 6 Electrical characteristics Electrical characteristics 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ). Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ). Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 20. Pin input voltage The input voltage measurement on a pin of the device is described in Figure 21. Figure 20. Pin loading conditions Figure 21. Pin input voltage #P& -#5PIN -#5PIN 6). -36 DocID024030 Rev 5 -36 89/226 191 Electrical characteristics STM32F427xx STM32F429xx 6.1.6 Power supply scheme Figure 22. Power supply scheme 9%$7 WR9 9%$7 3RZHU VZLWFK %DFNXSFLUFXLWU\ 26&.57& :DNHXSORJLF %DFNXSUHJLVWHUV EDFNXS5$0 /HYHOVKLIWHU *3,2V î—) 9&$3B 9&$3B 9'' îQ) î—) 9''  966  %<3$66B5(* 9'' 3'5B21 9''$ 95() 95() Q) Q) —) —) 95() 966$ 287 ,1 ,2 /RJLF 9ROWDJH UHJXODWRU .HUQHOORJLF &38GLJLWDO 5$0  5HVHW FRQWUROOHU )ODVKPHPRU\ $'& $QDORJ 5&V 3// 069 1. To connect BYPASS_REG and PDR_ON pins, refer to Section 3.17: Power supply supervisor and Section 3.18: Voltage regulator 2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin. 4. VDDA=VDD and VSSA=VSS. Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 90/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics 6.1.7 Current consumption measurement Figure 23. Current consumption measurement scheme )$$?6"!4 6"!4 6.2 )$$ 6$$ 6$$! AI Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics, and Table 16: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 14. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS External VBAT)(1) main supply voltage (including VDDA, VDD and − 0.3 4.0 Input voltage on FT pins(2) Input voltage on TTa pins VIN Input voltage on any other pin VSS − 0.3 VDD+4.0 VSS − 0.3 4.0 V VSS − 0.3 4.0 Input voltage on BOOT0 pin VSS 9.0 |ΔVDDx| Variations between different VDD power pins |VSSX −VSS| Variations between all the different ground pins - 50 mV - 50 VESD(HBM) Electrostatic discharge voltage (human body model) see Section 6.3.15: Absolute maximum ratings (electrical sensitivity) 1. sAullpmplayi,ninpothweepr e(VrmDiDtt,eVdDrDaAn)gaen. d ground (VSS, VSSA) pins must always be connected to the external power 2. iVnIjNecmteadxicmuurrmenvt.alue must always be respected. Refer to Table 15 for the values of the maximum allowed DocID024030 Rev 5 91/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 15. Current characteristics Symbol Ratings Max. Unit ΣIVDD Σ IVSS IVDD IVSS Total current into sum of all VDD_x power lines (source)(1) Total current out of sum of all VSS_x ground lines (sink)(1) Maximum current into each VDD_x power line (source)(1) Maximum current out of each VSS_x ground line (sink)(1) 270 − 270 100 − 100 Output current sunk by any I/O and control pin IIO Output current sourced by any I/Os and control pin Total output current sunk by sum of all I/O and control pins (2) ΣIIO Total output current sourced by sum of all I/Os and control pins(2) 25 − 25 120 mA − 120 IINJ(PIN) (3) Injected current on FT pins (4) Injected current on NRST and BOOT0 pins (4) − 5/+0 Injected current on TTa pins(5) ±5 ΣIINJ(PIN)(5) Total injected current (sum of all I/O and control pins)(6) ±25 1. Apellrmmaittinedporawnegre(.VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.21: 12-bit ADC characteristics. 4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 5. A positive injection exceeded. Refer to iTsainbdleu1ce4dfobrythVeINv>aVluDeDsAowf hthilee a negative injection is induced by maximum allowed input voltage. VIN5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of – 5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 55. Symbol Table 55. I/O current injection susceptibility(1) Functional susceptibility Description Negative Positive Unit injection injection Injected current on BOOT0 pin −0 Injected current on NRST pin −0 IINJ Injected current on PA0, PA1, PA2, PA3, PA6, PA7, PB0, PC0, PC1, PC2, PC3, PC4, PC5, PH1, PH2, PH3, PH4, PH5 −0 Injected current on TTa pins: PA4 and PA5 −0 Injected current on any other FT pin −5 1. NA = not applicable. NA NA NA mA +5 NA Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.17 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 56: I/O static characteristics are derived from tests performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL compliant. Symbol Parameter Table 56. I/O static characteristics Conditions Min FT, TTa and NRST I/O input low level voltage 1.7 V≤ VDD≤ 3.6 V - VIL BOOT0 I/O input low level 1.75 V≤ VDD ≤ 3.6 V, –40 °C≤ TA ≤ 105 °C - voltage 1.7 V≤ VDD ≤ 3.6 V, 0 °C≤ TA ≤ 105 °C - Typ Max Unit - 0.35VD(1D) − 0.04 0.3VDD(2) V - 0.1VDD+0.1(1) - 132/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 56. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ FT, TTa and NRST I/O input high level voltage(5) 1.7 V≤ VDD≤ 3.6 V 0.45VDD+0.3(1) 0.7VDD(2) - VIH BOOT0 I/O input high level voltage 1.75 V≤ VDD ≤ 3.6 V, –40 °C≤ TA ≤ 105 °C 1.7 V≤ VDD ≤ 3.6 V, 0.17VDD+0.7(1) - 0 °C≤ TA ≤ 105 °C FT, TTa and NRST I/O input hysteresis 1.7 V≤ VDD≤ 3.6 V 10%VDD(3) - VHYS BOOT0 I/O input hysteresis 1.75 V≤ VDD ≤ 3.6 V, –40 °C≤ TA ≤ 105 °C 0.1 - 1.7 V≤ VDD ≤ 3.6 V, 0 °C≤ TA ≤ 105 °C I/O input leakage current (4) VSS ≤ VIN ≤ VDD - - Ilkg I/O FT input leakage current (5) VIN = 5 V - - Max Unit - V - - V - ±1 µA 3 All pins except for PA10/PB12 (OTG_FS_ID Weak pull-up ,OTG_HS_ID RPU equivalent resistor(6) ) PA10/PB12 (OTG_FS_ID ,OTG_HS_ID ) Weak pull- RPD down equivalent resistor(7) All pins except for PA10/PB12 (OTG_FS_ID ,OTG_HS_ID ) PA10/PB12 (OTG_FS_ID ,OTG_HS_ID ) VIN = VSS VIN = VDD 30 40 50 7 10 14 kΩ 30 40 50 7 10 14 CIO(8) I/O pin capacitance - - 5 - pF 1. Guaranteed by design, not tested in production. 2. Tested in production. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 55: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 55: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). DocID024030 Rev 5 133/226 191 Electrical characteristics STM32F427xx STM32F429xx 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 35. Figure 35. FT I/O input characteristics 9,/9,+ 9           %D7VHHVGWHRGQ%LQ'DSVHUHVRLGJGQXRFQVWLGLPR'HQ$XHOWVDUHLW&HJLRU0QDQP2VV6QLLP9QUR,XH7+HTWOD7PGXW/LLLUQRHUQPHV7THQX799WL/U,9,9/H+,U'+PPHPP'TDHLLX[QQQLWUH9P,/9H9PQ'9DW''['  9 7HVWHGLQSURGXFWLRQ&026UHTXLUHPHQW9,/PD[ 9''       9'' 9 069 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which can sink or source up to ±3mA. When using the PC13 to PC15 and PI8 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 15). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating ΣIVSS (see Table 15). 134/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 57 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. All I/Os are CMOS and TTL compliant. Table 57. Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL(1) Output low level voltage for an I/O pin CMOS port(2) - 0.4 VOH(3) Output high level voltage for an I/O pin IIO = +8 mA 2.7 V ≤ VDD ≤ 3.6 V VDD − 0.4 - V VOL (1) Output low level voltage for an I/O pin TTL port(2) - VOH (3) Output high level voltage for an I/O pin IIO =+ 8mA 2.7 V ≤ VDD ≤ 3.6 V 2.4 0.4 V - VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin IIO = +20 mA - 1.3(4) 2.7 V ≤ VDD ≤ 3.6 V VDD − 1.3(4) - V VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin IIO = +6 mA - 0.4(4) 1.8 V ≤ VDD ≤ 3.6 V VDD − 0.4(4) - V VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin IIO = +4 mA - 0.4(5) 1.7 V ≤ VDD ≤ 3.6V VDD − 0.4(5) - V 1. The and tIhIOecsuurmrenotf sunk by IIO (I/O the device must always respect ports and control pins) must not the absolute maximum exceed IVSS. rating specified in Table 15. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. TTahbeleIIO15cuarnredntthseosuurcmedofbIyIOth(Ie/Odepvoirctes must always respect the absolute maximum and control pins) must not exceed IVDD. rating specified in 4. Based on characterization data. 5. Guaranteed by design, not tested in production. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 36 and Table 58, respectively. Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. DocID024030 Rev 5 135/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 58. I/O AC characteristics(1)(2) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit CL = 50 pF, VDD ≥ 2.7 V - - 4 fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD ≥ 1.7 V - - CL = 10 pF, VDD ≥ 2.7 V - - 2 8 MHz 00 CL = 10 pF, VDD ≥ 1.8 V - - 4 CL = 10 pF, VDD ≥ 1.7 V - - 3 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 50 pF, VDD = 1.7 V to 3.6 V - - 100 ns CL = 50 pF, VDD≥ 2.7 V - - 25 CL = 50 pF, VDD≥ 1.8 V - - 12.5 fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD≥ 1.7 V - - 10 MHz CL = 10 pF, VDD ≥ 2.7 V - - 50 01 CL = 10 pF, VDD≥ 1.8 V - - 20 CL = 10 pF, VDD≥ 1.7 V - - 12.5 CL = 50 pF, VDD ≥ 2.7 V - - 10 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 10 pF, VDD ≥ 2.7 V CL = 50 pF, VDD ≥ 1.7 V - - 6 ns 20 fmax(IO)out Maximum frequency(3) CL = 10 pF, VDD ≥ 1.7 V - CL = 40 pF, VDD ≥ 2.7 V - CL = 10 pF, VDD ≥ 2.7 V - CL = 40 pF, VDD ≥ 1.7 V - - 10 - 50(4) - 100(4) - 25 MHz CL = 10 pF, VDD ≥ 1.8 V - - 50 10 CL = 10 pF, VDD ≥ 1.7 V - - 42.5 CL = 40 pF, VDD ≥2.7 V - - 6 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 10 pF, VDD ≥ 2.7 V CL = 40 pF, VDD ≥ 1.7 V - - 4 ns 10 CL = 10 pF, VDD ≥ 1.7 V - - 6 136/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 58. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit CL = 30 pF, VDD ≥ 2.7 V - - 100(4) CL = 30 pF, VDD ≥ 1.8 V - - 50 fmax(IO)out Maximum frequency(3) CL = 30 pF, VDD ≥ 1.7 V - CL = 10 pF, VDD≥ 2.7 V - - 42.5 - 180(4) MHz CL = 10 pF, VDD ≥ 1.8 V - - 100 11 CL = 10 pF, VDD ≥ 1.7 V - - 72.5 CL = 30 pF, VDD ≥ 2.7 V - - 4 CL = 30 pF, VDD ≥1.8 V - - 6 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time CL = 30 pF, VDD ≥1.7 V CL = 10 pF, VDD ≥ 2.7 V - - 7 ns - 2.5 CL = 10 pF, VDD ≥1.8 V - - 3.5 CL = 10 pF, VDD ≥1.7 V - - 4 Pulse width of external signals - tEXTIpw detected by the EXTI controller 10 - - ns 1. Guaranteed by design, not tested in production. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 36. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. Figure 36. I/O AC characteristics definition       (;7(51$/ 287387 21&/ WU ,2 RXW WI ,2 RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLI WUWI ”  7DQGLIWKHGXW\F\FOHLV   ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´  DLG DocID024030 Rev 5 137/226 191 Electrical characteristics STM32F427xx STM32F429xx 6.3.18 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 56: I/O static characteristics). Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 59. NRST pin characteristics Symbol Parameter Conditions Min Typ Max RPU Weak pull-up equivalent resistor(1) VF(NRST)(2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse VIN = VSS VDD > 2.7 V 30 40 50 - - 100 300 - - TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - 1. The pull-up is resistance must dbeesmiginnimedumwi(t~h1a0%truoerdreesr)is.tance in series with a switchable PMOS. This PMOS contribution to the series 2. Guaranteed by design, not tested in production. Unit kΩ ns ns µs Figure 37. Recommended NRST pin protection ([WHUQDO UHVHWFLUFXLW  9'' 1567  538 —) ,QWHUQDO5HVHW )LOWHU 670) DLF 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level Table 59. Otherwise the reset is not on the NRST pin can go below the taken into account by the device. VIL(NRST) max level specified in 138/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics 6.3.19 6.3.20 TIM timer characteristics The parameters given in Table 60 are guaranteed by design. Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 60. TIMx characteristics(1)(2) Symbol Parameter Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 1 tres(TIM) Timer resolution time 180 MHz AHB/APBx prescaler>4, fTIMxCLK = 90 MHz 1 fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 180 MHz 0 ResTIM Timer resolution - tMAX_COUNT Maximum possible count with 32-bit counter - - tTIMxCLK - tTIMxCLK fTIMxCLK/2 MHz 16/32 65536 × 65536 bit tTIMxCLK 1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers. 2. Guaranteed by design, not tested in production. 3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise TIMxCLK = 4x PCLKx. Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0090 reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the Section 6.3.17: I/O port I/O pin and VDD is characteristics for disabled, but is more details on still the present. Refer to I2C I/O characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: Symbol Table 61. I2C analog filter characteristics(1) Parameter Min Max Unit Maximum pulse width of spikes tAF that are suppressed by the analog 50(2) 260(3) ns filter DocID024030 Rev 5 139/226 191 Electrical characteristics STM32F427xx STM32F429xx 1. Guaranteed by design, not tested in production. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered SPI interface characteristics Unless otherwise specified, the parameters given in Table 62 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 62. SPI dynamic characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK 1/tc(SCK) Duty(SCK) tw(SCKH) tw(SCKL) tsu(NSS) th(NSS) tsu(MI) tsu(SI) th(MI) th(SI) ta(SO) tdis(SO) Master mode, SPI1/4/5/6, 2.7 V≤VDD≤3.6 V Slave mode, Receiver - SPI1/4/5/6, SPI clock frequency 2.7 V≤VDD≤3.6 V Transmitter/ full-duplex Master mode, SPI1/2/3/4/5/6, 1.7 V≤VDD≤3.6 V - Slave mode, SPI1/2/3/4/5/6, 1.7 V≤VDD≤3.6 V Duty cycle of SPI clock frequency Slave mode 30 SCK high and low time NSS setup time Master mode, SPI presc = 2, 2.7 V≤VDD≤3.6 V Master mode, SPI presc = 2, 1.7 V≤VDD≤3.6 V Slave mode, SPI presc = 2 NSS hold time Slave mode, SPI presc = 2 Master mode Data input setup time Slave mode TPCLK − 0.5 TPCLK − 2 4TPCLK 2TPCLK 3 0 Master mode 0.5 Data input hold time Slave mode 2 Data output access time Slave mode, SPI presc = 2 0 Slave mode, SPI1/4/5/6, Data output disable time 2.7 V≤VDD≤3.6 V 0 Slave mode, SPI1/2/3/4/5/6 and 1.7 V≤VDD≤3.6 V 0 - - 50 TPCLK TPCLK - 45 45 38(2) 22.5 MHz 22.5 70 % TPCLK+0.5 TPCLK+2 - - - ns - - 4TPCLK 8.5 16.5 140/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 62. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Slave mode (after enable edge), SPI1/4/5/6 and 2.7V ≤ VDD ≤ 3.6V - 11 13 tv(SO) th(SO) Data output valid/hold time Slave mode (after enable edge), SPI2/3, 2.7 V≤VDD≤3.6 V Slave mode (after enable edge), SPI1/4/5/6, 1.7 V≤VDD≤3.6 V - 14 15 - 15.5 19 Slave mode (after enable edge), SPI2/3, 1.7 V≤VDD≤3.6 V - 15.5 17.5 ns tv(MO) Data output valid time Master mode (after enable edge), SPI1/4/5/6, 2.7 V≤VDD≤3.6 V Master mode (after enable edge), SPI1/2/3/4/5/6, 1.7 V≤VDD≤3.6 V - - 2.5 - 4.5 th(MO) Data output hold time Master mode (after enable edge) 0 - - 1. Guaranteed by characterization results, not tested in production. 2. Maximum frequency in Slave transmitter high phase preceding the SCK sampling mode edge. is determined by the sum of This value can be achieved twv(hSeOn) and the StsPu(IMcIo) wmhmicuhnhicaastetso fit into with a SCK low master or having tsu(MI) = 0 while Duty(SCK) = 50% Figure 38. SPI timing diagram - slave mode and CPHA = 0 SCK Input NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tSU(NSS) tc(SCK) tw(SCKH) tw(SCKL) ta(SO) MISO OUT P UT MOSI I NPUT tsu(SI) tv(SO) MS B O UT M SB IN th(SI) th(SO) BI T6 OUT B I T1 IN th(NSS) tr(SCK) tf(SCK) tdis(SO) LSB OUT LSB IN ai14134c DocID024030 Rev 5 141/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 39. SPI timing diagram - slave mode and CPHA = 1(1) SCK Input NSS input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) MISO OUT P UT MOSI I NPUT ta(SO) tsu(SI) tc(SCK) tv(SO) MS B O UT th(SI) M SB IN th(SO) BI T6 OUT B I T1 IN th(NSS) tr(SCK) tf(SCK) tdis(SO) LSB OUT LSB IN High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 Figure 40. SPI timing diagram - master mode(1) tc(SCK) ai14135 SCK Input SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO INP UT tsu(MI) MOSI OUTPU T tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) BI T6 IN B I T1 OUT th(MO) tr(SCK) tf(SCK) LSB IN LSB OUT ai14136 142/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 63 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 63. I2S dynamic characteristics(1) Symbol Parameter Conditions Min fMCK fCK I2S Main clock output I2S clock frequency Master data: 32 bits Slave data: 32 bits DCK tv(WS) th(WS) tsu(WS) th(WS) tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) th(SD_ST) tv(SD_MT) I2S clock frequency duty cycle WS valid time WS hold time WS setup time WS hold time Data input setup time Data input hold time Data output valid time Slave receiver Master mode Master mode Slave mode Slave mode Master receiver Slave receiver Master receiver Slave receiver Slave transmitter (after enable edge) Master transmitter (after enable edge) 256x8K 30 0 0 1 0 7.5 2 0 0 - - th(SD_MT) Data output hold time Master transmitter (after enable edge) 2.5 Max 256xFs(2) 64xFs 64xFs 70 6 - 27 20 - Unit MHz MHz % ns 1. Guaranteed by characterization results, not tested in production. 2. The maximum value of 256xFs is 45 MHz (APB1 maximum frequency). Note: Refer to the I2S section of RM0090 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. DocID024030 Rev 5 143/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 41. I2S slave timing diagram (Philips protocol)(1) CPOL = 0 tc(CK) CK Input CPOL = 1 WS input SDtransmit SDreceive tw(CKH) tw(CKL) th(WS) tsu(WS) LSB transmit(2) tsu(SD_SR) LSB receive(2) MSB transmit MSB receive tv(SD_ST) Bitn transmit th(SD_SR) Bitn receive th(SD_ST) LSB transmit LSB receive ai14881b 1. .LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 42. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output CPOL = 0 CPOL = 1 WS output SDtransmit SDreceive tc(CK) tw(CKH) tv(WS) tw(CKL) th(WS) tv(SD_MT) LSB transmit(2) MSB transmit Bitn transmit tsu(SD_MR) LSB receive(2) MSB receive th(SD_MR) Bitn receive th(SD_MT) LSB transmit LSB receive ai14884b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 144/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 64 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 64. SAI characteristics(1) Symbol Parameter Conditions fMCKL FSCK DSCK tv(FS) tsu(FS) th(FS) tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) th(SD_ST) tv(SD_MT) th(SD_MT) SAI Main clock output SAI clock frequency SAI clock frequency duty cycle FS valid time FS setup time FS hold time Data input setup time Data input hold time Data output valid time Data output hold time Master data: 32 bits Slave data: 32 bits Slave receiver Master mode Slave mode Master mode Slave mode Master receiver Slave receiver Master receiver Slave receiver Slave transmitter (after enable edge) Master transmitter (after enable edge) Master transmitter (after enable edge) 1. Guaranteed by characterization results, not tested in production. 2. 256xFs maximum corresponds to 45 MHz (APB2 xaximum frequency) Min 256 x 8K - 30 8 2 8 0 5 3 0 0 - - 8 Max 256xFs(2) 64xFs 64xFs 70 22 - 22 20 - Unit MHz MHz % ns DocID024030 Rev 5 145/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 43. SAI master timing waveforms F3#+ 3!)?3#+?8 TH&3 3!)?&3?8 OUTPUT 3!)?3$?8 TRANSMIT TV&3 3!)?3$?8 RECEIVE TSU3$?-2 TV3$?-4 3LOTN TH3$?-2 3LOTN  3LOTN Figure 44. SAI slave timing waveforms F3#+ TH3$?-4 -36 3!)?3#+?8 TW#+(?8 3!)?&3?8 INPUT 3!)?3$?8 TRANSMIT TSU&3 3!)?3$?8 RECEIVE TW#+,?8 TH&3 TSU3$?32 TV3$?34 3LOTN TH3$?32 3LOTN 3LOTN  TH3$?34 -36 146/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Note: USB OTG full speed (FS) characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 65. USB OTG full speed startup time Symbol Parameter Max Unit tSTARTUP(1) USB OTG full speed transceiver startup time 1 µs 1. Guaranteed by design, not tested in production. Table 66. USB OTG full speed DC electrical characteristics Symbol Parameter Conditions Min.(1) Typ. Max.(1) Unit USB OTG full speed VDD transceiver operating voltage 3.0(2) - 3.6 V Input VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - levels VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 V VSE(3) Single ended receiver threshold 1.3 - 2.0 Output VOL Static output level low levels VOH Static output level high RL of 1.5 kΩ to 3.6 V(4) RL of 15 kΩ to VSS(4) 2.8 - 0.3 3.6 V PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) RPD PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VDD 17 21 24 0.65 1.1 2.0 kΩ PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 RPU PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 1. All the voltages are measured from the local ground potential. 2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design, not tested in production. 4. RL is the load connected on the USB OTG full speed drivers. When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state (floating input), not as alternate function. A typical 200 µA current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 and PB13 when the feature is enabled. DocID024030 Rev 5 147/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 45. USB OTG full speed timings: definition of data signal rise and fall time Differen tial Data L ines VCR S Crossover points VS S tf tr ai14137 Table 67. USB OTG full speed electrical characteristics(1) Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) tf Fall time(2) CL = 50 pF 4 CL = 50 pF 4 20 ns 20 ns trfm Rise/ fall time matching tr/tf 90 110 % VCRS Output signal crossover voltage 1.3 2.0 V ZDRV Output driver impedance(3) Driving high or low 28 44 Ω 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver. USB high speed (HS) characteristics Unless otherwise specified, the parameters given in Table 70 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 69 and VDD supply voltage conditions summarized in Table 68, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10, unless otherwise specified • Capacitive load C = 30 pF, unless otherwise specified • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Symbol Table 68. USB HS DC electrical characteristics Parameter Min.(1) Input level VDD USB OTG HS operating voltage 1.7 1. All the voltages are measured from the local ground potential. Max.(1) 3.6 Unit V 148/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 69. USB HS clock timing parameters(1) Symbol Parameter Min Typ fHCLK value to guarantee proper operation of USB HS interface 30 - FSTART_8BIT Frequency (first transition) 8-bit ±10% 54 60 FSTEADY Frequency (steady state) ±500 ppm 59.97 60 DSTART_8BIT Duty cycle (first transition) 8-bit ±10% 40 50 DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 tSTEADY Time to reach the steady state frequency and duty cycle after the first transition - - tSTART_DEV Clock startup time after the Peripheral - - tSTART_HOST de-assertion of SuspendM Host - - tPREP PHY preparation time after the first transition of the input clock - - 1. Guaranteed by design, not tested in production. Max Unit - MHz 66 60.03 60 50.025 MHz MHz % % 1.4 ms 5.6 ms - - µs Figure 46. ULPI timing diagram #LOCK T3# #ONTROL)N 5,0)?$)2 5,0)?.84 T3$ DATA)N  BIT #ONTROLOUT 5,0)?340 DATAOUT  BIT T(# T($ T$# T$$ T$# AIC DocID024030 Rev 5 149/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 70. Dynamic characteristics: USB ULPI(1) Symbol Parameter Conditions Min. tSC Control in (ULPI_DIR, ULPI_NXT) setup time 2 tHC Control in (ULPI_DIR, ULPI_NXT) hold time 0.5 tSD Data in setup time 1.5 tHD Data in hold time 2 2.7 V < VDD < 3.6 V, CL = 15 pF and - OSPEEDRy[1:0] = 11 tDC/tDD Data/control output delay 2.7 V < VDD < 3.6 V, CL = 20 pF and - OSPEEDRy[1:0] = 10 1.7 V < VDD < 3.6 V, CL = 15 pF and - OSPEEDRy[1:0] = 11 1. Guaranteed by characterization results, not tested in production. Typ. 9 12 Max. Unit - 9.5 ns 15 150/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Ethernet characteristics Unless otherwise specified, the parameters given in Table 72, Table 73 and Table 74 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 17 and VDD supply voltage conditions summarized in Table 71, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Symbol Table 71. Ethernet DC electrical characteristics Parameter Min.(1) Input level VDD Ethernet operating voltage 2.7 1. All the voltages are measured from the local ground potential. Max.(1) 3.6 Unit V Table 72 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 47 shows the corresponding timing diagram. (7+B0'& Figure 47. Ethernet SMI timing diagram W0'& WG 0',2 (7+B0',2 2 (7+B0',2 , WVX 0',2 WK 0',2 069 Table 72. Dynamics characteristics: Ethernet MAC signals for SMI(1) Symbol Parameter Min Typ Max Unit tMDC MDC cycle time(2.38 MHz) 411 Td(MDIO) Write data valid time 6 tsu(MDIO) Read data setup time 12 th(MDIO) Read data hold time 0 1. Guaranteed by characterization results, not tested in production. 420 425 10 13 ns - - - - Table 73 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the corresponding timing diagram. DocID024030 Rev 5 151/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 48. Ethernet RMII timing diagram RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tsu(CRS) RMII_RXD[1:0] RMII_CRS_DV td(TXEN) td(TXD) tih(RXD) tih(CRS) ai15667 Table 73. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 1.5 tih(RXD) Receive data hold time 0 tsu(CRS) Carrier sense setup time 1 tih(CRS) Carrier sense hold time 1 td(TXEN) Transmit enable valid delay time 0 td(TXD) Transmit data valid delay time 0 1. Guaranteed by characterization results, not tested in production. - - - - - - - - 10.5 12 11 12.5 Unit ns Table 74 gives the list of Ethernet MAC signals for MII and Figure 48 shows the corresponding timing diagram. Figure 49. Ethernet MII timing diagram MII_RX_CLK tsu(RXD) tsu(ER) tsu(DV) MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] tih(RXD) tih(ER) tih(DV) td(TXEN) td(TXD) ai15668 152/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 74. Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 9 tih(RXD) Receive data hold time 10 tsu(DV) Data valid setup time 9 tih(DV) Data valid hold time 8 tsu(ER) Error setup time 6 tih(ER) Error hold time 8 td(TXEN) Transmit enable valid delay time 0 td(TXD) Transmit data valid delay time 0 1. Guaranteed by characterization results, not tested in production. - - - - - - 10 14 10 15 Unit ns CAN (controller area network) interface Refer to Section 6.3.17: I/O port characteristics for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX). 6.3.21 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 75 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 17. Table 75. ADC characteristics Symbol Parameter Conditions Min Typ VDDA VREF+ Power supply Positive reference voltage VDDA − VREF+ < 1.2 V 1.7(1) 1.7(1) - fADC ADC clock frequency VDDA = 1.7(1) to 2.4 V 0.6 15 VDDA = 2.4 to 3.6 V 0.6 30 fTRIG(2) External trigger frequency fADC = 30 MHz, 12-bit resolution - - - - VAIN Conversion voltage range(3) 0 (VSSA or VREF- - tied to ground) RAIN(2) External input impedance See Equation 1 for details - - RADC(2)(4) Sampling switch resistance - - CADC(2) Internal sample and hold capacitor - 4 tlat(2) Injection trigger conversion latency fADC = 30 MHz - - - - Max 3.6 VDDA 18 36 Unit V V MHz MHz 1764 kHz 17 1/fADC VREF+ V 50 kΩ 6 kΩ 7 pF 0.100 3(5) µs 1/fADC DocID024030 Rev 5 153/226 191 Electrical characteristics STM32F427xx STM32F429xx Symbol Table 75. ADC characteristics (continued) Parameter Conditions Min Typ Max Unit tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 - - 2(5) tS(2) Sampling time tSTAB(2) Power-up time fADC = 30 MHz fADC = 30 MHz 12-bit resolution 0.100 3 - 0.50 - 16 - 480 2 3 - 16.40 fADC = 30 MHz 10-bit resolution 0.43 - 16.34 tCONV(2) Total conversion time (including sampling time) fADC = 30 MHz 8-bit resolution 0.37 - 16.27 fADC = 30 MHz 6-bit resolution 0.30 - 16.20 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 12-bit resolution Single ADC - - 2 Sampling rate fS(2) (fADC = 30 MHz, and tS = 3 ADC cycles) 12-bit resolution Interleave Dual ADC - mode 12-bit resolution Interleave Triple ADC - mode - 3.75 - 6 IVREF+(2) ADC VREF DC current consumption in conversion mode - 300 500 IVDDA(2) ADC VDDA DC current consumption in conversion mode - 1.6 1.8 µs 1/fADC µs 1/fADC µs µs µs µs µs 1/fADC Msps Msps Msps µA mA 1. IVnDteDrAnaml irneimseutmOFvaFl)u.e of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: 2. Based on characterization, not tested in production. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 75. Equation 1: RAIN max formula RAIN = -------------------(--k------–-----0----,--5-----)------------------- fADC × CADC × ln (2N + 2) – RADC 154/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Symbol Table 76. ADC static accuracy at fADC = 18 MHz(1) Parameter Test conditions Typ Max(2) Unit ET Total unadjusted error ±3 ±4 EO Offset error EG Gain error fADC =18 MHz VDDA = 1.7 to 3.6 V ±2 ±3 VREF = 1.7 to 3.6 V ±1 ±3 ED Differential linearity error VDDA − VREF < 1.2 V ±1 ±2 EL Integral linearity error ±2 ±3 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Based on characterization, not tested in production. LSB a Symbol Table 77. ADC static accuracy at fADC = 30 MHz(1) Parameter Test conditions Typ Max(2) ET Total unadjusted error ±2 ±5 EO Offset error fADC = 30 MHz, RAIN < 10 kΩ, ±1.5 ±2.5 EG Gain error VDDA = 2.4 to 3.6 V, ±1.5 ±3 ED Differential linearity error VREF = 1.7 to 3.6 V, VDDA − VREF < 1.2 V ±1 ±2 EL Integral linearity error ±1.5 ±3 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Based on characterization, not tested in production. Unit LSB Symbol Table 78. ADC static accuracy at fADC = 36 MHz(1) Parameter Test conditions Typ Max(2) ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V ±4 ±7 ±2 ±3 ±3 ±6 ±2 ±3 ±3 ±6 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2. Based on characterization, not tested in production. Unit LSB DocID024030 Rev 5 155/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 79. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions Min Typ Max Unit ENOB SINAD SNR THD Effective number of bits Signal-to-noise and distortion ratio fADC =18 MHz VDDA = VREF+= 1.7 V 10.3 10.4 - bits 64 64.2 - Signal-to-noise ratio Input Frequency = 20 KHz 64 65 - dB Total harmonic distortion Temperature = 25 °C − 67 − 72 - 1. Guaranteed by characterization results, not tested in production. Table 80. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions Min Typ Max Unit ENOB SINAD SNR THD Effective number of bits Signal-to noise and distortion ratio Signal-to noise ratio Total harmonic distortion fADC =36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 KHz Temperature = 25 °C 1. Guaranteed by characterization results, not tested in production. 10.6 66 64 − 70 10.8 67 68 − 72 - bits - - dB - Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.17 does not affect the ADC accuracy. 156/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Figure 50. ADC accuracy characteristics           ;,3" )$%!,62%& OR6$$!DEPENDINGONPACKAGE  =  %4  %/ %, %$ , 3")$%!, %'       633!      6$$! 1. See also Table 77. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. EEOT ==TOoftfasleUt nEarrdojur:sdteedviEatriroonr:bmetawxeimenumthedefivrisattiaocntubaelttwraenesnittiohne actual and the ideal transfer and the first ideal one. curves. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. AIC Figure 51. Typical connection diagram using the ADC 5$,1  $,1[ 9$,1 &SDUDVLWLF 9'' 97 9 97 9 670) 6DPSOHDQGKROG$'& FRQYHUWHU 5$'&  ELW FRQYHUWHU ,/“—$ &$'&  DL 1. Refer to Table 75 for the values of RAIN, RADC and CADC. 2. pCapdaracsaitpicarceitparnecseen(rtsouthgehlcya5papcFit)a. nAcheigohf fADC should be reduced. the PCB Cparasitic (dependent on soldering and PCB layout value downgrades conversion accuracy. quality) plus the To remedy this, DocID024030 Rev 5 157/226 191 Electrical characteristics STM32F427xx STM32F429xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F V REF+ (See note 1) 1 µF // 10 nF 1 µF // 10 nF V DDA V SSA/V REF(See note 1) ai17535 1. VanRdEFL+QaFnPd1V7R6E. FW– hinepnuVtsRaErFe+baontdh aVvRaEiFla–balereonnoUt FaBvaGilAab1l7e6, .thVeRyEFa+reisinatlesronaavllyaiclaobnleneocnteLdQtFoPV1D0D0A, LQFP144, and VSSA. Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai17536 1. VanRdEFL+QaFnPd1V7R6E. FW– hinepnuVtsRaErFe+baontdh aVvRaEiFla–balereonnoUt FaBvaGilAab1l7e6, .thVeRyEFa+reisinatlesronaavllyaiclaobnleneocnteLdQtFoPV1D0D0A, LQFP144, and VSSA. 158/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics 6.3.22 Temperature sensor characteristics Table 81. Temperature sensor characteristics Symbol Parameter Min TL(1) VSENSE linearity with temperature - Avg_Slope(1) Average slope - V25(1) Voltage at 25 °C - tSTART(2) Startup time - TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. Typ ±1 2.5 0.76 6 - Max ±2 10 - Unit °C mV/°C V µs µs Symbol TS_CAL1 TS_CAL2 Table 82. Temperature sensor calibration values Parameter Memory address TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F 6.3.23 VBAT monitoring characteristics Symbol Table 83. VBAT monitoring characteristics Parameter Min Typ R Q Er(1) TS_vbat(2)(2) Resistor bridge for VBAT Ratio on VBAT measurement Error on Q ADC sampling time when reading the VBAT 1 mV accuracy - 50 - 4 –1 - 5 - 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. Max +1 - Unit KΩ % µs 6.3.24 Reference voltage The parameters given in Table 84 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. Table 84. internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT TS_vrefint(1) Internal reference voltage ADC sampling time when reading the internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V 10 - - µs VRERINT_s(2) Internal reference voltage spread over the temperature range VDD = 3V ± 10mV - 3 5 mV DocID024030 Rev 5 159/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 84. internal reference voltage (continued) Symbol Parameter Conditions TCoeff(2) tSTART(2) Temperature coefficient Startup time 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production Min Typ - 30 - 6 Max Unit 50 ppm/°C 10 µs Table 85. Internal reference voltage calibration values Symbol Parameter Memory address VREFIN_CAL Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B 6.3.25 DAC electrical characteristics Symbol Parameter Table 86. DAC characteristics Min Typ Max Unit Comments VDDA Analog supply voltage 1.7(1) - VREF+ Reference supply voltage 1.7(1) - VSSA Ground 0 - RLOAD(2) Resistive load with buffer ON 5 - RO(2) Impedance output with buffer OFF - - CLOAD(2) Capacitive load - - 3.6 V 3.6 V VREF+ ≤ VDDA 0 V - kΩ When the buffer is OFF, the Minimum 15 kΩ resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT Lower DAC_OUT voltage min(2) with buffer ON DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON DAC_OUT Lower DAC_OUT voltage min(2) with buffer OFF DAC_OUT Higher DAC_OUT voltage max(2) with buffer OFF IVREF+(4) DAC DC VREF current consumption in quiescent mode (Standby mode) 0.2 - It gives the maximum output excursion of - V the DAC. It corresponds to 12-bit input code - - VDDA − 0.2 (0x0E0) to (0xF1C) at VREF+ = 3.6 V and V (0x1C7) to (0xE38) at VREF+ = 1.7 V - 0.5 - mV It gives the maximum output excursion of - - VREF+ − 1LSB the DAC. V With no load, worst code (0x800) at - 170 240 VREF+ = 3.6 V in terms of DC consumption on the inputs µA With no load, worst code (0xF1C) at - 50 75 VREF+ = 3.6 V in terms of DC consumption on the inputs 160/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 86. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments IDDA(4) DAC DC VDDA current consumption in quiescent mode(3) - 280 380 µA With no load, middle code (0x800) on the inputs With no load, worst code (0xF1C) at - 475 625 µA VREF+ = 3.6 V in terms of DC consumption on the inputs DNL(4) Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. Integral non linearity - - ±1 LSB Given for the DAC in 10-bit configuration. (difference between INL(4) measured value at Code i and the value at Code i on a - - ±4 LSB Given for the DAC in 12-bit configuration. line drawn between Code 0 and last Code 1023) Offset error - (difference between Offset(4) measured value at Code - (0x800) and the ideal value = VREF+/2) - - ±10 mV Given for the DAC in 12-bit configuration - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error(4) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration Settling time (full scale: for a 10-bit input code transition tSETTLING(4) between the lowest highest input codes and the when - 3 DAC_OUT reaches final value ±4LSB 6 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ THD(4) Total Harmonic Distortion Buffer ON - - Max frequency for a correct Update DAC_OUT change when rate(2) small variation in the input - - code (from code i to i+1LSB) - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ - 6.5 10 µs input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC - –67 –40 dB No RLOAD, CLOAD = 50 pF measurement) 1. IVnDteDrAnaml irneimseutmOFvaFl)u.e of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: 2. Guaranteed by design, not tested in production. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization, not tested in production. DocID024030 Rev 5 161/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 54. 12-bit buffered /non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& ELW GLJLWDOWR DQDORJ FRQYHUWHU %XIIHU  '$&[B287 5 /2$' & /2$' DL 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.26 FMC characteristics Unless otherwise specified, the parameters given in Table 87 to Table 102 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 except at VDD range 1.7 to 2.1V where OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 87 through Table 94 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • AddressSetupTime = 0x1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5) • BusTurnAroundDuration = 0x0 • For SDRAM memories, VDD ranges from 2.7 to 3.6 V and maximum frequency FMC_SDCLK = 90 MHz • For Mobile LPSDR SDRAM memories, VDD ranges from 1.7 to 1.95 V and maximum frequency FMC_SDCLK = 84 MHz 162/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms &-#?.% TV./%?.% &-#?./% TW.% T W./% T H.%?./% &-#?.7% &-#?!;= &-#?.",;= &-#?$;= &-#?.!$6  TV!?.% TV",?.% T V.!$6?.% TW.!$6 !DDRESS T H!?./% T H",?./% TSU$ATA?./% TSU$ATA?.% $ATA T H$ATA?.% TH$ATA?./% &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. -36 Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 2THCLK − 0.5 2 THCLK+0.5 ns tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 1 ns tw(NOE) FMC_NOE low time 2THCLK 2THCLK+ 0.5 ns th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 - ns tv(A_NE) FMC_NEx low to FMC_A valid - 2 ns th(A_NOE) Address hold time after FMC_NOE high 0 - ns tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 ns th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - ns tsu(Data_NE) Data to FMC_NEx high setup time THCLK + 2.5 - ns tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK +2 - ns DocID024030 Rev 5 163/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 87. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) (continued) Symbol Parameter Min Max th(Data_NOE) Data hold time after FMC_NOE high th(Data_NE) Data hold time after FMC_NEx high tv(NADV_NE) FMC_NEx low to FMC_NADV low tw(NADV) FMC_NADV low time 1. CL = 30 pF. 2. Based on characterization, not tested in production. 0 - 0 - - 0 - THCLK +1 Unit ns ns ns ns Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR read NWAIT timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 7THCLK+0.5 7THCLK+1 tw(NOE) FMC_NWE low time 5THCLK − 1.5 5THCLK +2 ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 - 1. CL = 30 pF. 2. Based on characterization, not tested in production. 164/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms &-#?.%X TW.% &-#?./% &-#?.7% &-#?!;= &-#?.",;= &-#?$;= &-#?.!$6  TV.7%?.% TW.7% TV!?.% TV",?.% TV$ATA?.% T V.!$6?.% TW.!$6 TH!?.7% !DDRESS TH",?.7% .", TH$ATA?.7% $ATA T H.%?.7% &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. -36 Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) th(A_NWE) tv(BL_NE) th(BL_NWE) tv(Data_NE) th(Data_NWE) tv(NADV_NE) tw(NADV) FMC_NE low time FMC_NEx low to FMC_NWE low FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid Address hold time after FMC_NWE high FMC_NEx low to FMC_BL valid FMC_BL hold time after FMC_NWE high Data to FMC_NEx low to Data valid Data hold time after FMC_NWE high FMC_NEx low to FMC_NADV low FMC_NADV low time 1. CL = 30 pF. 2. Based on characterization, not tested in production. Min 3THCLK THCLK − 0.5 THCLK THCLK +1.5 THCLK+0.5 THCLK+0.5 THCLK+0.5 - Max 3THCLK+1 THCLK+ 0.5 THCLK+ 0.5 0 1.5 THCLK+ 2 0.5 THCLK+ 0.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns DocID024030 Rev 5 165/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time tw(NWE) tsu(NWAIT_NE) th(NE_NWAIT) FMC_NWE low time FMC_NWAIT valid before FMC_NEx high FMC_NEx hold time after FMC_NWAIT invalid 1. CL = 30 pF. 2. Based on characterization, not tested in production. 8THCLK+1 8THCLK+2 ns 6THCLK − 1 6THCLK+2 ns 6THCLK+1.5 - ns 4THCLK+1 ns Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms &-#? .% TV./%?.% TW.% T H.%?./% &-#?./% &-#?.7% T W./% &-#? !;= &-#? .",;= &-#? !$;= T V.!$6?.% TV!?.% TV",?.% !DDRESS .", TH!?./% TH",?./% T V!?.% !DDRESS TSU$ATA?.% TSU$ATA?./% $ATA TH!$?.!$6 TW.!$6 TH$ATA?.% TH$ATA?./% &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 166/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 91. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time FMC_NOE high to FMC_NE high hold time 3THCLK − 1 2THCLK − 0.5 THCLK − 1 1 3THCLK+0.5 2THCLK THCLK+1 - FMC_NEx low to FMC_A valid - 2 FMC_NEx low to FMC_NADV low 0 2 FMC_NADV low time FMC_AD(address) valid hold time after FMC_NADV high) THCLK − 0.5 THCLK+0.5 0 - th(A_NOE) Address hold time after FMC_NOE high THCLK − 0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 tsu(Data_NE) Data to FMC_NEx high setup time THCLK+1.5 - tsu(Data_NOE) Data to FMC_NOE high setup time THCLK+1 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - 1. CL = 30 pF. 2. Based on characterization, not tested in production. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 92. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 8THCLK+0.5 8THCLK+2 ns tw(NOE) FMC_NWE low time 5THCLK − 1 5THCLK +1.5 ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK +1.5 - ns th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+1 ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. DocID024030 Rev 5 167/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms &-#? .%X TW.% 168/226 &-#?./% &-#?.7% &-#? !;= &-#? .",;= &-#? !$;= T V.!$6?.% &-#?.!$6 TV.7%?.% TW.7% TV!?.% TV",?.% T V!?.% !DDRESS TW.!$6 TH!?.7% !DDRESS TH",?.7% .", T V$ATA?.!$6 $ATA TH!$?.!$6 T H.%?.7% TH$ATA?.7% &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 Table 93. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) th(A_NWE) th(BL_NWE) tv(BL_NE) tv(Data_NADV) th(Data_NWE) FMC_NE low time FMC_NEx low to FMC_NWE low FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid FMC_NEx low to FMC_NADV low FMC_NADV low time FMC_AD(adress) valid hold time after FMC_NADV high) Address hold time after FMC_NWE high FMC_BL hold time after FMC_NWE high FMC_NEx low to FMC_BL valid FMC_NADV high to Data valid Data hold time after FMC_NWE high 4THCLK 4THCLK+0.5 ns THCLK − 1 THCLK+0.5 ns 2THCLK 2THCLK+0.5 ns THCLK - ns - 0 ns 0.5 1 ns THCLK − 0.5 THCLK+ 0.5 ns THCLK − 2 - ns THCLK - ns THCLK − 2 - ns - 2 ns - THCLK +1.5 ns THCLK +0.5 - ns DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 94. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time tw(NWE) tsu(NWAIT_NE) th(NE_NWAIT) FMC_NWE low time FMC_NWAIT valid before FMC_NEx high FMC_NEx hold time after FMC_NWAIT invalid 1. CL = 30 pF. 2. Based on characterization, not tested in production. 9THCLK 9THCLK+0.5 ns 7THCLK 7THCLK+2 ns 6THCLK+1.5 - ns 4THCLK–1 - ns Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms and Table 95 through Table 98 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable; • MemoryType = FMC_MemoryType_CRAM; • WriteBurst = FMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F4xx reference manual : RM0090) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FMC_CLK = 90 MHz). DocID024030 Rev 5 169/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 59. Synchronous multiplexed NOR/PSRAM read timings TW#,+ TW#,+ "53452. &-#?#,+ &-#?.%X T D#,+, .!$6, $ATALATENCY TD#,+, .%X, TD#,+, .!$6( TD#,+( .%X( &-#?.!$6 &-#?!;= TD#,+, !6 TD#,+, ./%, TD#,+( !)6 TD#,+( ./%( &-#?./% TD#,+, !$6 &-#?!$;= &-#?.7!)4 7!)4#&'B 7!)40/, B &-#?.7!)4 7!)4#&'B 7!)40/, B TD#,+, !$)6 TSU!$6 #,+( !$;= TSU.7!)46 #,+( TH#,+( !$6 TSU!$6 #,+( $ $ TH#,+( !$6 TH#,+( .7!)46 TSU.7!)46 #,+( TH#,+( .7!)46 TSU.7!)46 #,+( TH#,+( .7!)46 -36 Table 95. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FMC_CLK period 2THCLK − 1 - ns td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 0 ns td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) THCLK - ns td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0 ns td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - ns td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 0 ns td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 - ns td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - THCLK+0.5 ns td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK − 0.5 - ns td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 0.5 ns td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - ns 170/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 95. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 5 th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 0 tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 1. CL = 30 pF. 2. Based on characterization, not tested in production. - ns - ns - ns - ns Figure 60. Synchronous multiplexed PSRAM write timings TW#,+ TW#,+ "53452. &-#?#,+ &-#?.%X TD#,+, .!$6, $ATALATENCY TD#,+, .%X, TD#,+, .!$6( TD#,+( .%X( &-#?.!$6 &-#?!;= TD#,+, !6 TD#,+, .7%, TD#,+( !)6 TD#,+( .7%( &-#?.7% TD#,+, !$6 TD#,+, !$)6 TD#,+, $ATA TD#,+, $ATA &-#?!$;= !$;= $ $ &-#?.7!)4 7!)4#&'B 7!)40/, B &-#?.", TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+( .",( -36 DocID024030 Rev 5 171/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 96. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max tw(CLK) FMC_CLK period, VDD range= 2.7 to 3.6 V td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low td(CLKL-NADVH) FMC_CLK low to FMC_NADV high td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low t(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low td(CLKL-NBLL) FMC_CLK low to FMC_NBL low td(CLKH-NBLH) FMC_CLK high to FMC_NBL high tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 1. CL = 30 pF. 2. Based on characterization, not tested in production. 2THCLK − 1 - - 1.5 THCLK - - 0 0 - - 0 THCLK - - 0 THCLK − 0.5 - - 3 0 - - 3 0 - THCLK − 0.5 - 4 - 0 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 172/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings TW#,+ &-#?#,+ TD#,+, .%X, &-#?.%X TD#,+, .!$6, TW#,+ $ATALATENCY TD#,+, .!$6( TD#,+( .%X( &-#?.!$6 &-#?!;= TD#,+, !6 TD#,+( !)6 TD#,+, ./%, TD#,+( ./%( &-#?./% &-#?$;= &-#?.7!)4 7!)4#&'B 7!)40/, B &-#?.7!)4 7!)4#&'B 7!)40/, B TSU$6 #,+( TSU.7!)46 #,+( TH#,+( $6 TSU$6 #,+( $ $ TH#,+( $6 TH#,+( .7!)46 TSU.7!)46 #,+( T H#,+( .7!)46 TSU.7!)46 #,+( TH#,+( .7!)46 -36 Table 97. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max tw(CLK) FMC_CLK period t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH- NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL- NADVL) FMC_CLK low to FMC_NADV low td(CLKL- NADVH) FMC_CLK low to FMC_NADV high td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH- NOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 2THCLK − 1 - - 0.5 THCLK - - 0 0 - THCLK − 0.5 - THCLK − 0.5 5 0 THCLK+2 - - Unit ns ns ns ns ns ns ns ns ns ns DocID024030 Rev 5 173/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 97. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 0 - ns t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 th(CLKH- FMC_NWAIT valid after FMC_CLK high 0 NWAIT) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Figure 62. Synchronous non-multiplexed PSRAM write timings TW#,+ &-#?#,+ TW#,+ TD#,+, .%X, &-#?.%X $ATALATENCY TD#,+( .%X( TD#,+, .!$6, &-#?.!$6 &-#?!;= TD#,+, .!$6( TD#,+, !6 TD#,+( !)6 &-#?.7% TD#,+, .7%, TD#,+( .7%( &-#?$;= TD#,+, $ATA TD#,+, $ATA $ $ &-#?.7!)4 7!)4#&'B 7!)40/, B TSU.7!)46 #,+( &-#?.", TD#,+( .",( TH#,+( .7!)46 -36 Table 98. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit t(CLK) FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low td(CLKL-NADVH) FMC_CLK low to FMC_NADV high td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) 2THCLK − 1 - ns - 0.5 ns THCLK - - ns 0 ns 0 - ns - 0 ns 174/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 98. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued) Symbol Parameter Min Max Unit td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) 0 - ns td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 0 ns td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK − 0.5 - ns td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 2.5 ns td(CLKL-NBLL) FMC_CLK low to FMC_NBL low 0 - ns td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK − 0.5 - ns tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 4 th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 0 1. CL = 30 pF. 2. Based on characterization, not tested in production. PC Card/CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms, and Table 99 and Table 100 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x04; • COM.FMC_WaitSetupTime = 0x07; • COM.FMC_HoldSetupTime = 0x04; • COM.FMC_HiZSetupTime = 0x00; • ATT.FMC_SetupTime = 0x04; • ATT.FMC_WaitSetupTime = 0x07; • ATT.FMC_HoldSetupTime = 0x04; • ATT.FMC_HiZSetupTime = 0x00; • IO.FMC_SetupTime = 0x04; • IO.FMC_WaitSetupTime = 0x07; • IO.FMC_HoldSetupTime = 0x04; • IO.FMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. DocID024030 Rev 5 175/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 63. PC Card/CompactFlash controller waveforms for common memory read access &-#?.#%? &-#?.#%? &-#?!;= TV.#%X ! TH.#%X !) &-#?.2%' &-#?.)/72 &-#?.)/2$ TD.2%' .#%X TD.)/2$ .#%X TH.#%X .2%' TH.#%X .)/2$ TH.#%X .)/72 &-#?.7% TD.#%? ./% &-#?./% TW./% &-#?$;= TSU$ ./% TH./% $ 1. FMC_NCE4_2 remains high (inactive during 8-bit access. -36 Figure 64. PC Card/CompactFlash controller waveforms for common memory write access &-#?.#%? &-#?.#%? (IGH &-#?!;= TV.#%? ! &-#?.2%' &-#?.)/72 &-#?.)/2$ TD.#%? .7% &-#?.7% TD.2%' .#%? TD.)/2$ .#%? TW.7% TH.#%? !) TH.#%? .2%' TH.#%? .)/2$ TH.#%? .)/72 TD.7% .#%? &-#?./% &-#?$;= -%-X(): TD$ .7% TV.7% $ TH.7% $ 176/226 DocID024030 Rev 5 -36 STM32F427xx STM32F429xx Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access &-#?.#%? &-#?.#%? (IGH TV.#%? ! TH.#%? !) &-#?!;= &-#?.)/72 &-#?.)/2$ &-#?.2%' TD.2%' .#%? TH.#%? .2%' &-#?.7% TD.#%? ./% &-#?./% &-#?$;= TW./% TSU$ ./% TD./% .#%? TH./% $ 1. Only data bits 0...7 are read (bits 8...15 are disregarded). -36 DocID024030 Rev 5 177/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access &-#?.#%? &-#?.#%? (IGH &-#?!;= TV.#%? ! TH.#%? !) &-#?.)/72 &-#?.)/2$ TD.2%' .#%? TH.#%? .2%' &-#?.2%' TD.#%? .7% &-#?.7% &-#?./% &-#?$;= TW.7% TD.7% .#%? TV.7% $ 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). -36 Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access &-#?.#%? &-#?.#%? &-#?!;= &-#?.2%' &-#?.7% &-#?./% TV.#%X ! TH.#%? !) &-#?.)/72 TD.)/2$ .#%? &-#?.)/2$ &-#?$;= TSU$ .)/2$ TW.)/2$ TD.)/2$ $ -36 178/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access &-#?.#%? &-#?.#%? &-#?!;= TV.#%X ! TH.#%? !) &-#?.2%' &-#?.7% &-#?./% &-#?.)/2$ T D.#%? .)/72 &-#?.)/72 !44X(): &-#?$;= TW.)/72 TV.)/72 $ TH.)/72 $ -36 Table 99. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FMC_Ncex low to FMC_Ay valid th(NCEx_AI) FMC_NCEx high to FMC_Ax invalid td(NREG-NCEx) FMC_NCEx low to FMC_NREG valid th(NCEx-NREG) FMC_NCEx high to FMC_NREG invalid td(NCEx-NWE) FMC_NCEx low to FMC_NWE low tw(NWE) FMC_NWE low width td(NWE_NCEx) FMC_NWE high to FMC_NCEx high tV(NWE-D) FMC_NWE low to FMC_D[15:0] valid th(NWE-D) FMC_NWE high to FMC_D[15:0] invalid td(D-NWE) FMC_D[15:0] valid before FMC_NWE high td(NCEx-NOE) FMC_NCEx low to FMC_NOE low tw(NOE) FMC_NOE low width td(NOE_NCEx) FMC_NOE high to FMC_NCEx high tsu (D-NOE) FMC_D[15:0] valid data before FMC_NOE high th(NOE-D) FMC_NOE high to FMC_D[15:0] invalid 1. CL = 30 pF. 2. Based on characterization, not tested in production. - 0 ns 0 - ns - 1 ns THCLK − 2 - ns - 5THCLK ns 8THCLK − 0.5 8THCLK+0.5 ns 5THCLK+1 - ns - 0 ns 9THCLK − 0.5 - ns 13THCLK − 3 ns - 5THCLK ns 8 THCLK − 0.5 8 THCLK+0.5 ns 5THCLK − 1 - ns THCLK - ns 0 - ns DocID024030 Rev 5 179/226 191 Electrical characteristics STM32F427xx STM32F429xx Table 100. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter Min Max Unit tw(NIOWR) FMC_NIOWR low width tv(NIOWR-D) FMC_NIOWR low to FMC_D[15:0] valid th(NIOWR-D) FMC_NIOWR high to FMC_D[15:0] invalid td(NCE4_1-NIOWR) FMC_NCE4_1 low to FMC_NIOWR valid th(NCEx-NIOWR) FMC_NCEx high to FMC_NIOWR invalid td(NIORD-NCEx) FMC_NCEx low to FMC_NIORD valid th(NCEx-NIORD) FMC_NCEx high to FMC_NIORD) valid tw(NIORD) FMC_NIORD low width tsu(D-NIORD) FMC_D[15:0] valid before FMC_NIORD high td(NIORD-D) FMC_D[15:0] valid after FMC_NIORD high 8THCLK − 0.5 - ns - 0 ns 9THCLK − 2 - ns - 5THCLK ns 5THCLK - ns - 5THCLK ns 6THCLK+2 - ns 8THCLK − 0.5 8THCLK+0.5 ns THCLK - ns 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. NAND controller waveforms and timings Figure 69 through Figure 72 represent synchronous waveforms, and Table 101 and Table 102 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01; • COM.FMC_WaitSetupTime = 0x03; • COM.FMC_HoldSetupTime = 0x02; • COM.FMC_HiZSetupTime = 0x01; • ATT.FMC_SetupTime = 0x01; • ATT.FMC_WaitSetupTime = 0x03; • ATT.FMC_HoldSetupTime = 0x02; • ATT.FMC_HiZSetupTime = 0x01; • Bank = FMC_Bank_NAND; • MemoryDataWidth = FMC_MemoryDataWidth_16b; • ECC = FMC_ECC_Enable; • ECCPageSize = FMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. 180/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Figure 69. NAND controller waveforms for read access &-#?.#%X !,%&-#?! #,%&-#?! &-#?.7% &-#?./%.2% &-#?$;= TD!,% ./% TSU$ ./% TH./% !,% TH./% $ -36 Figure 70. NAND controller waveforms for write access &-#?.#%X !,%&-#?! #,%&-#?! &-#?.7% TD!,% .7% TH.7% !,% &-#?./%.2% &-#?$;= TV.7% $ TH.7% $ -36 DocID024030 Rev 5 181/226 191 Electrical characteristics STM32F427xx STM32F429xx Figure 71. NAND controller waveforms for common memory read access &-#?.#%X !,%&-#?! #,%&-#?! &-#?.7% &-#?./% &-#?$;= TD!,% ./% TW./% TSU$ ./% TH./% !,% TH./% $ -36 Figure 72. NAND controller waveforms for common memory write access &-#?.#%X !,%&-#?! #,%&-#?! TD!,% ./% &-#?.7% TW.7% TH./% !,% &-#?. /% &-#?$;= TD$ .7% TV.7% $ TH.7% $ -36 Table 101. Switching characteristics for NAND Flash read cycles(1) Symbol Parameter Min Max Unit tw(N0E) FMC_NOE low width 4THCLK − 0.5 4THCLK+0.5 ns tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 9 - ns th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3THCLK − 0.5 ns th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 3THCLK − 2 - ns 1. CL = 30 pF. 182/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Table 102. Switching characteristics for NAND Flash write cycles(1) Symbol Parameter Min Max Unit tw(NWE) tv(NWE-D) th(NWE-D) td(D-NWE) td(ALE-NWE) th(NWE-ALE) 1. CL = 30 pF. FMC_NWE low width FMC_NWE low to FMC_D[15-0] valid FMC_NWE high to FMC_D[15-0] invalid FMC_D[15-0] valid before FMC_NWE high FMC_ALE valid before FMC_NWE low FMC_NWE high to FMC_ALE invalid 4THCLK 0 4THCLK+1 ns - ns 3THCLK − 1 - ns 5THCLK − 3 - ns - 3THCLK−0.5 ns 3THCLK − 1 - ns SDRAM waveforms and timings Figure 73. SDRAM read access waveforms (CL = 1) &-#?3$#,+ TD3$#,+,?!DD2 &-#?!>@ &-#?3$.%;= TD3$#,+,?.2!3 &-#?3$.2!3 &-#?3$.#!3 TD3$#,+,?!DD# TH3$#,+,?!DD2 2OWN #OL #OL #OLI #OLN TH3$#,+,?!DD# TD3$#,+,?3.$% TH3$#,+,?3.$% TH3$#,+,?.2!3 TD3$#,+,?.#!3 TH3$#,+,?.#!3 &-#?3$.7% &-#?$;= TSU3$#,+(?$ATA TH3$#,+(?$ATA $ATA $ATA $ATAI $ATAN -36 DocID024030 Rev 5 183/226 191 Electrical characteristics STM32F427xx STM32F429xx Symbol Table 103. SDRAM read timings(1)(2) Parameter Min tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 tsu(SDCLKH _Data) Data input setup time 2 th(SDCLKH_Data) Data input hold time 0 td(SDCLKL_Add) Address valid time - td(SDCLKL- SDNE) Chip select valid time - th(SDCLKL_SDNE) Chip select hold time 0 td(SDCLKL_SDNRAS) SDNRAS valid time - th(SDCLKL_SDNRAS) SDNRAS hold time 0 td(SDCLKL_SDNCAS) SDNCAS valid time - th(SDCLKL_SDNCAS) SDNCAS hold time 0 1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK. 2. Guaranteed by characterization results, not tested in production. Max 2THCLK+0.5 1.5 0.5 0.5 0.5 - Unit ns Symbol Table 104. LPSDR SDRAM read timings(1)(2) Parameter Min Max tW(SDCLK) FMC_SDCLK period 2THCLK − 0.5 tsu(SDCLKH_Data) Data input setup time 2.5 th(SDCLKH_Data) Data input hold time 0 td(SDCLKL_Add) Address valid time - td(SDCLKL_SDNE) Chip select valid time - th(SDCLKL_SDNE) Chip select hold time 1 td(SDCLKL_SDNRAS SDNRAS valid time - th(SDCLKL_SDNRAS) SDNRAS hold time 1 td(SDCLKL_SDNCAS) SDNCAS valid time - th(SDCLKL_SDNCAS) SDNCAS hold time 1 1. CL = 10 pF. 2. Guaranteed by characterization results, not tested in production. 2THCLK+0.5 1 1 1 1 - Unit ns 184/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Figure 74. SDRAM write access waveforms &-#?3$#,+ TD3$#,+,?!DD2 &-#?!>@ TD3$#,+,?!DD# TH3$#,+,?!DD2 2OWN #OL #OL #OLI #OLN TH3$#,+,?!DD# TD3$#,+,?3.$% &-#?3$.%;= TD3$#,+,?.2!3 TH3$#,+,?.2!3 &-#?3$.2!3 &-#?3$.#!3 TD3$#,+,?.#!3 TD3$#,+,?.7% &-#?3$.7% TD3$#,+,?$ATA &-#?$;= TD3$#,+,?.", &-#?.",;= $ATA $ATA $ATAI $ATAN TH3$#,+,?$ATA TH3$#,+,?3.$% TH3$#,+,?.#!3 TH3$#,+,?.7% -36 DocID024030 Rev 5 185/226 191 Electrical characteristics STM32F427xx STM32F429xx Symbol Table 105. SDRAM write timings(1)(2) Parameter Min tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 td(SDCLKL _Data) Data output valid time - th(SDCLKL _Data) Data output hold time 3.5 td(SDCLKL_Add) Address valid time - td(SDCLKL_SDNWE) SDNWE valid time - th(SDCLKL_SDNWE) SDNWE hold time 0 td(SDCLKL_ SDNE) Chip select valid time - th(SDCLKL-_SDNE) Chip select hold time 0 td(SDCLKL_SDNRAS) SDNRAS valid time - th(SDCLKL_SDNRAS) SDNRAS hold time 0 td(SDCLKL_SDNCAS) SDNCAS valid time - td(SDCLKL_SDNCAS) SDNCAS hold time 0 td(SDCLKL_NBL) NBL valid time - th(SDCLKL_NBL) NBLoutput time 0 1. CL = 30 pF on data and address lines. CL=15pF on FMC_SDCLK. 2. Guaranteed by characterization results, not tested in production. Max 2THCLK+0.5 2.5 - 1.5 1 0.5 2 0.5 0.5 - Unit ns Symbol Table 106. LPSDR SDRAM write timings(1)(2) Parameter Min Max tw(SDCLK) td(SDCLKL _Data) th(SDCLKL _Data) td(SDCLKL_Add) td(SDCLKL-SDNWE) th(SDCLKL-SDNWE) td(SDCLKL- SDNE) th(SDCLKL- SDNE) td(SDCLKL-SDNRAS) th(SDCLKL-SDNRAS) td(SDCLKL-SDNCAS) td(SDCLKL-SDNCAS) td(SDCLKL_NBL) th(SDCLKL-NBL) 1. CL = 10 pF. FMC_SDCLK period Data output valid time Data output hold time Address valid time SDNWE valid time SDNWE hold time Chip select valid time Chip select hold time SDNRAS valid time SDNRAS hold time SDNCAS valid time SDNCAS hold time NBL valid time NBL output time 2THCLK − 0.5 2 1 1 - 1.5 - 1.5 - 1.5 2THCLK+0.5 5 2.8 2 1.5 1.5 1.5 1.5 - Unit ns 186/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics 6.3.27 2. Guaranteed by characterization results, not tested in production. Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 107 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data formats: 14 bits Table 107. DCMI characteristics Symbol Parameter Min Frequency ratio DCMI_PIXCLK/fHCLK - DCMI_PIXCLK Pixel clock input - DPixel Pixel clock input duty cycle 30 tsu(DATA) Data input setup time 2 th(DATA) Data input hold time 2.5 tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 0.5 th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 1 Max 0.4 54 70 - - - Unit MHz % ns Figure 75. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. '&0,B+6<1& '&0,B96<1& '$7$>@ WVX +6<1& WVX 96<1& WVX '$7$ WK '$7$ WK +6<1& WK +6<1& 069 DocID024030 Rev 5 187/226 191 Electrical characteristics STM32F427xx STM32F429xx 6.3.28 LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 108 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • LCD_CLK polarity: high • LCD_DE polarity : low • LCD_VSYNC and LCD_HSYNC polarity: high • Pixel formats: 24 bits Symbol fCLK DCLK tw(CLKH) tw(CLKL) tv(DATA) th(DATA) tv(HSYNC) tv(VSYNC) tv(DE) th(HSYNC) th(VSYNC) th(DE) Table 108. LTDC characteristics Parameter Min Max LTDC clock output frequency - 42 LTDC clock output duty cycle 45 55 Clock High time, low time tw(CLK)/2 − 0.5 tw(CLK)/2+0.5 Data output valid time - 3.5 Data output hold time 1.5 - Unit MHz % HSYNC/VSYNC/DE output valid time - 2.5 ns HSYNC/VSYNC/DE output hold time 2 - 188/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Figure 76. LCD-TFT horizontal timing diagram W&/. /&'B&/. /&'B96<1& WY +6<1& WY +6<1& /&'B+6<1& WY '( WK '( /&'B'( /&'B5>@ /&'B*>@ /&'B%>@ WY '$7$ 1JYFM 1JYFM  1JYFM / WK '$7$ +6<1& +RUL]RQWDO ZLGWK EDFNSRUFK $FWLYHZLGWK +RUL]RQWDO EDFNSRUFK 2QHOLQH Figure 77. LCD-TFT vertical timing diagram W&/. /&'B&/. WY 96<1& WY 96<1& 069 /&'B96<1& /&'B5>@ /&'B*>@ /&'B%>@ -LINESDATA 96<1& 9HUWLFDO ZLGWK EDFNSRUFK $FWLYHZLGWK 2QHIUDPH 9HUWLFDO EDFNSRUFK 069 DocID024030 Rev 5 189/226 191 Electrical characteristics STM32F427xx STM32F429xx 6.3.29 SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 109 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.17: I/O port characteristics for more details on the input/output characteristics. Figure 78. SDIO high-speed mode TF TR T7#+( #+ $ #-$ OUTPUT $ #-$ INPUT T# T/6 T7#+, T/( T)35 T)( Figure 79. SD default mode #+ $ #-$ OUTPUT T/6$ T/($ AI AI 190/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Electrical characteristics Symbol Table 109. Dynamic characteristics: SD / MMC characteristics(1)(2) Parameter Conditions Min Typ Max fPP Clock frequency in data transfer mode - SDIO_CK/fPCLK2 frequency ratio 0 48 - - 8/3 tW(CKL) tW(CKH) Clock low time Clock high time fpp =48 MHz 8.5 9 - fpp =48 MHz 8.3 10 - CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp =48 MHz 3.5 - - tIH Input hold time HS fpp =48 MHz 0 - - CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp =48 MHz - 4.5 7 tOH Output hold time HS fpp =48 MHz 3 - - CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp =24 MHz 1.5 - - tIHD Input hold time SD fpp =24 MHz 0.5 - - CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp =24 MHz - 4.5 6.5 tOHD Output hold default time SD fpp =24 MHz 3.5 - - 1. Guaranteed by characterization results, not tested in production. 2. VDD = 2.7 to 3.6 V. Unit MHz ns ns ns ns ns 6.3.30 RTC characteristics Table 110. RTC characteristics Symbol Parameter Conditions Min Max - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4 - DocID024030 Rev 5 191/226 191 Package characteristics 7 Package characteristics STM32F427xx STM32F429xx 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 80. LQFP100 -100-pin, 14 x 14 mm low-profile quad flat package outline 3%!4).'0,!.% # ! ! ! CCC # $ $ $     MM '!5'%0,!.% , , C % % % ! + B  0).  )$%.4)&)#!4)/. 1. Drawing is not to scale.   E ,?-%?6 192/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Package characteristics Table 111. LQPF100 100-pin, 14 x 14 mm low-profile quad flat package mechanical data Symbol millimeters Min Typ Max inches(1) Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID024030 Rev 5 193/226 221 Package characteristics STM32F427xx STM32F429xx Figure 81. LQPF100 recommended footprint                1. Dimensions are expressed in millimeters. Device marking for LQFP100 AIC The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 82. LQFP100 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ  45.' 7*53 5HYLVLRQFRGH 3LQ LGHQWLILHU 67ORJR 'DWHFRGH \HDUZHHN :88 DLG 1. Samples identified with a marking beginning with "ES" or ‘E’ or accompanied by a specific notification are to be considered as “Engineering Samples": i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production. Only if ST has authorized in writing the customer qualification Engineering Samples can be used for reliability qualification trials. 194/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Package characteristics Figure 83. WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline $EDOOORFDWLRQ H EEE ) * 'HWDLO$ H H H %RWWRPYLHZ %XPSVLGH ' $ $ $ 6LGHYLHZ %XPS $ ( $RULHQWDWLRQ UHIHUHQFH HHH $ E FFF = ; < 6HDWLQJ GGG = SODQH 'HWDLO$ 5RWDWHGƒ 7RSYLHZ DDD :DIHUEDFNVLGH 1. Drawing is not to scale. $:(B0(B9 Table 112. WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data Symbol millimeters Min Typ Max inches(1) Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 A3(2) b(3) 0.220 0.380 0.025 0.250 0.280 0.0087 0.0150 0.0010 0.0098 0.0110 DocID024030 Rev 5 195/226 221 Package characteristics STM32F427xx STM32F429xx Table 112. WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) Symbol millimeters Min Typ Max inches(1) Min Typ Max D 4.486 4.521 4.556 0.1766 0.1780 0.1794 E 5.512 5.547 5.582 0.2170 0.2184 0.2198 e - 0.400 - - 0.0157 - e1 - 4.000 - - 0.1575 - e2 - 4.800 - - 0.1890 - F - 0.2605 - - 0.0103 - G - 0.3735 - - 0.0147 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 84. WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint 'SDG 'VP 069 Table 113. WLCSP143 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 Dpad 260 µm max. (circular) 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed. 196/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Package characteristics Device marking for WLCSP143 The following figure gives an example of topside marking orientation versus ball A 1 identifier location. Figure 85. WLCSP143 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ  EDOO$ (6)=,< 'DWHFRGH 1.7 V in Table 58: I/O AC characteristics. Updated conditions in Table 62: SPI dynamic characteristics. Added ZDRV in Table 67: USB OTG full speed electrical characteristics Removed note 3 in Table 81: Temperature sensor characteristics. Added Figure 82: LQFP100 marking example (package top view), Figure 85: WLCSP143 marking example (package top view), Figure 88: LQFP144 marking example (package top view), Figure 91: LQFP176 marking (package top view), Figure 94: LQFP208 marking example (package top view), Figure 96: UFBGA169 marking example (package top view) and Figure 98: UFBGA176+25 marking example (package top view). Added Appendix A: Recommendations when using internal reset OFF. Removed Internal reset OFF hardware connection appendix. 224/226 DocID024030 Rev 5 STM32F427xx STM32F429xx Revision history Date 19-Feb-2015 Table 123. Document revision history Revision Changes Update SPI/IS2 in Table 2: STM32F427xx and STM32F429xx features and peripheral counts. Updated LQFP208 in Table 4: Regulator ON/OFF and internal reset ON/OFF availability. Updated Figure 19: Memory map. Changed PLS[2:0]=101 (falling edge) maximum value in Table 22: reset and power control block characteristics. Updated current consumption with all peripherals disabled in Table 24: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled except prefetch) or RAM. Updated note 1. in Table 28: Typical and maximum current consumptions in Standby mode. Updated tWUSTOP in Table 36: Low-power mode wakeup timings. Updated ESD standards and Table 53: ESD absolute maximum ratings. Updated Table 56: I/O static characteristics. Section : I2C interface characteristics: updated section introduction, removed Table I2C characteristics, Figure I2C bus AC waveforms and measurement circuit and Table SCL frequency; added Table 61: I2C analog filter characteristics. Updated measurement conditions in Table 62: SPI dynamic characteristics. 5 Updated Figure 51: Typical connection diagram using the ADC. Updated Section : Device marking for LQFP100. Updated Figure 83: WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package outline and Table 112: WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale package mechanical data; added Figure 84: WLCSP143 - 143-pin, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale recommended footprint and Table 113: WLCSP143 recommended PCB design rules (0.4 mm pitch). Updated Figure 85: WLCSP143 marking example (package top view) and related note. Updated Section : Device marking for WLCSP143. Updated Section : Device marking for LQFP144. Updated Section : Device marking for LQFP176. Updated Figure 92: LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline; Updated Section : Device marking for LQFP208. Modified UFBGA169 pitch, updated Figure 95: UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package outline and Table 117: UFBGA169 - 169-ball 7 x 7 mm 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data; updated Section : Device marking for LQFP208. updated Section : Device marking for UFBGA169, Section : Device marking for UFBGA176+25 and Section : Device marking for TFBGA176. Updated Z pin count in Table 121: Ordering information scheme. DocID024030 Rev 5 225/226 225 STM32F427xx STM32F429xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 226/226 DocID024030 Rev 5

    Top_arrow
    回到顶部
    EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。