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    DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 16-BIT, 500-MSPS, 2×–16× INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER FEATURES 1 •234 500-MSPS Maximum-Update-Rate DAC • WCDMA ACPR – 1 Carrier: 76 dB Centered at 30.72-MHz IF, 245.76 MSPS – 1 Carrier: 73 dB Centered at 61.44-MHz IF, 245.76 MSPS – 2 Carrier: 72 dB Centered at 30.72-MHz IF, 245.76 MSPS – 4 Carrier: 64 dB Centered at 92.16-MHz IF, 491.52 MSPS • Selectable 2×, 4×, 8×, and 16× Interpolation – Linear Phase – 0.05-dB Pass-Band Ripple – 80-dB Stop-Band Attenuation – Stop-Band Transition 0.4–0.6 fDATA • 32-Bit Programmable NCO • On-Chip 2×–16× PLL Clock Multiplier With Bypass Mode • Differential Scalable Current Outputs: 2 mA to 20 mA • On-Chip 1.2-V Reference • 1.8-V Digital and 3.3-V Analog Supplies • 1.8-V/3.3-V CMOS-Compatible Interface • Power Dissipation: 950 mW at Full Maximum Operating Conditions • Package: 100-Pin HTQFP APPLICATIONS • Cellular Base Transceiver Station Transmit Channel – CDMA: W-CDMA, CDMA2000, IS-95 – TDMA: GSM, IS-136, EDGE/UWC-136 • Baseband I and Q Transmit • Input Interface: Quadrature Modulation for Interfacing With Baseband Complex Mixing ASICs • Single-Sideband Up-Conversion • Diversity Transmit • Cable Modem Termination System DESCRIPTION The DAC5686 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2×, 4×, 8×, and 16× interpolation filters, a numerically controlled oscillator (NCO), onboard clock multiplier, and on-chip voltage reference. The DAC5686 has been specifically designed to allow for low input data rates between the DAC and ASIC, or FPGA, and high output transmit intermediate frequencies (IF). Target applications include high-speed digital data transmission in wired and wireless communication systems and high-frequency direct-digital synthesis DDS. The DAC5686 provides three modes of operation: dual-channel, single-sideband, and quadrature modulation. In dual-channel mode, interpolation filtering increases the DAC update rate, which reduces sinx/x rolloff and enables the use of relaxed analog post-filtering. Single-sideband mode provides an alternative interface to the analog quadrature modulators. Channel carrier selection is performed at baseband by mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are input to the DAC5686, which in turn performs a complex mix resulting in Hilbert transform pairs at the outputs of the DAC5686's two DACs. An external RF quadrature modulator then performs the final single-sideband up-conversion. The DAC5686's complex mixing frequencies are flexibly chosen with the 32-bit programmable NCO. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. 2 Excel is a trademark of Microsoft Corporation. 3 All other trademarks are the property of their respective owners. 4 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local oscillator feedthrough. Each DAC in the DAC5686 has an 11-bit offset adjustment and 12-bit gain adjustment, which compensate for quadrature modulator input imbalances, thus reducing RF filtering requirements. In quadrature modulation mode, on-chip mixing provides baseband-to-IF up-conversion. Mixing frequencies are flexibly chosen with a 32-bit programmable NCO. Channel carrier selection is performed at baseband by complex mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are input to the DAC5686, which interpolates the low data-rate signal to higher data rates. The single DAC output from the DAC5686 is the final IF single-sideband spectrum presented to RF. The 2×, 4×, 8×, and 16× interpolation filters are implemented as a cascade of half-band 2× interpolation filters. Unused filters for interpolation rates of less than 16× are shut off to reduce power consumption. The DAC5686 provides a full bypass mode, which enables the user to bypass all the interpolation and mixing. The DAC5686 PLL clock multiplier controls all internal clocks for the digital filters and the DAC cores. The differential clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock divider of the PLL ensures that the digital filters operate at the correct clock frequencies. The DAC5686 operates with an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. Digital I/Os are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 950 mW at maximum operating conditions. The DAC5686 provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The device has been specifically designed for a differential transformer-coupled output with a 50-Ω doubly terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported. The DAC5686 operational modes are configured by programming registers through a serial interface. The serial interface can be configured to either a 3- or 4-pin interface allowing it to communicate with many industry-standard microprocessors and microcontrollers. Data (I and Q) can be input to the DAC5686 as separate parallel streams on two data buses, or as a single interleaved data stream on one data bus. An accurate on-chip 1.2-V temperature-compensated band-gap reference and control amplifier allows the user to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage can be applied for maximum flexibility. The device features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby minimizing the system power consumption. The DAC5686 is available in a 100-pin HTQFP package. The device is characterized for operation over the industrial temperature range of –40C to 85C. ORDERING INFORMATION TA –40C to 85C PACKAGE DEVICES 100 HTQFP(1) (PZP) PowerPAD™ plastic quad flatpack DAC5686IPZP (1) Thermal pad size: 6 mm × 6 mm 2 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 FUNCTIONAL BLOCK DIAGRAM Block Diagram of the DAC5686 CLKVDD CLKGND PLLLOCK LPF PLLGND PLLVDD PHSTR SLEEP DVDD DGND CLK1 CLK1C CLK2 CLK2C fDATA DEMUX DA[15:0] FIR1 y2 Internal Clock Generation 2y–16y PLL Clock Multiplier FIR2 y2 FIR3 y2 FIR4 y2 2y–16y fDATA 1.2-V Reference FIR5 x sin(x) A Offset A Gain 16-Bit DAC EXTIO EXTLO BIASJ IOUTA1 IOUTA2 DB[15:0] TXENABLE RESETB QFLAG y2 y2 y2 y2 cos sin SIF NCO SDIO SDO SDENB SCLK x sin(x) 16-Bit DAC IOUTB1 IOUTB2 B Offset B Gain IOGND IOVDD 100-Pin HTQFP AVDD AGND B0019-01 Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 3 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com PIN ASSIGNMENTS FOR THE DAC5686 PZP PACKAGE (TOP VIEW) DB15 (MSB or LSB) DB5 DB6 DB7 IOGND IOVDD DGND DVDD DB8 DB9 DB10 DB11 DB12 DGND DVDD DB13 DB14 DGND PHSTR RESETB SLEEP TESTMODE QFLAG DGND DVDD 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 AGND 1 AVDD 2 AVDD 3 AGND 4 IOUTB1 5 IOUTB2 6 AGND 7 AVDD 8 AGND 9 AVDD 10 EXTIO 11 AGND 12 BIASJ 13 AVDD 14 EXTLO 15 AVDD 16 AGND 17 AVDD 18 AGND 19 IOUTA2 20 IOUTA1 21 AGND 22 AVDD 23 AVDD 24 AGND 25 DAC5686 75 DB4 74 DB3 73 DB2 72 DB1 71 DB0 (LSB or MSB) 70 PLLLOCK 69 DGND 68 DVDD 67 PLLVDD 66 LPF 65 PLLGND 64 CLKGND 63 CLK2C 62 CLK2 61 CLKVDD 60 CLK1C 59 CLK1 58 CLKGND 57 DGND 56 DVDD 55 DA0 (LSB or MSB) 54 DA1 53 DA2 52 DA3 51 DA4 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DA5 DA6 DA7 IOGND IOVDD DGND DVDD DA8 DA9 DA10 DA11 DA12 DGND DVDD DA13 DA14 DA15 (MSB or LSB) TXENABLE DVDD SDO SDIO SCLK SDENB DGND DVDD P0011-01 4 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 DEVICE INFORMATION TERMINAL NAME NO. AGND 1, 4, 7, 9, 12, 17, 19, 22, 25 AVDD 2, 3, 8, 10, 14, 16, 18, 23, 24 BIASJ 13 CLK1 59 CLK1C 60 CLK2 62 CLK2C 63 CLKGND 58, 64 CLKVDD 61 DA[15:0] 34–36, 39–43, 48–55 DB[15:0] 92–90, 87–83, 78–71 DGND DVDD EXTIO 27, 38, 45, 57, 69, 81, 88, 93, 99 26, 32, 37, 44, 56, 68, 82, 89, 100 11 EXTLO IOUTA1 IOUTA2 IOUTB1 IOUTB2 IOGND IOVDD LPF PHSTR 15 21 20 5 6 47, 79 46, 80 66 94 PLLGND 65 PLLVDD 67 PLLLOCK 70 QFLAG 98 RESETB 95 SCLK 29 SDENB 28 Terminal Functions I/O I Analog ground return DESCRIPTION I Analog supply voltage I/O Full-scale output current bias I External clock input; data clock input I Complementary external clock input; data clock input I External clock input; sample clock for the DAC (optional if PLL disabled) I Complementary external clock input; sample clock for the DAC (optional if PLL disabled) Ground return for internal clock buffer Internal clock buffer supply voltage I A-channel data bits 0 through 15 DA15 is most significant data bit (MSB). DA0 is least significant data bit (LSB). Internal pulldown I B-channel data bits 0 through 15 DB15 is most significant data bit (MSB). DB0 is least significant data bit (LSB). Internal pulldown Note: The order of the B data bus can be reversed by register rev_bbus. Digital ground return Digital supply voltage I Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD). Used as internal reference output when EXTLO = AGND, requires a 0.1-µF decoupling capacitor to AGND when used as reference output I Internal reference ground. Connect to AVDD to disable the internal reference O A-channel DAC current output. Full scale when all input bits are set to 1 O A-channel DAC complementary current output. Full scale when all input bits are set to 0 O B-channel DAC current output. Full scale when all input bits are set to 1 O B-channel DAC complementary current output. Full scale when all input bits are set to 0 Digital I/O ground return Digital I/O supply voltage I/O PLL loop filter connection. Can be left open or connected to GND if PLL is not used (PLLVDD = 0 V). I The PHSTR pin has two functions. When the sync_phstr register is 0, a high on the PHSTR pin resets the NCO phase accumulator. When the sync_phstr register is 1, a PHSTR pin low-to-high transition sets the divided clock phase in external clock mode, and a high on the PHSTR pin resets the NCO phase accumulator. Internal pulldown Ground return for internal PLL PLL supply voltage. When PLLVDD is 0 V, the PLL is disabled. O PLL lock status bit. In PLL clock mode, PLLLOCK is high when PLL is locked to the input clock. In external clock mode, PLLLOCK outputs the input rate clock. I Used in the interleaved data input mode: When the qflag register bit is 1, the QFLAG pin is used as an input to identify the interleaved data sequence. QFLAG high identifies the data as channel B. Pin can be left open when not used. Internal pulldown I Resets the chip when low. Internal pullup I Serial interface clock. Internal pulldown I Active-low serial data enable, always an input to the DAC5686. Internal pulldown Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 5 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com TERMINAL NAME NO. SDIO 30 SDO 31 SLEEP 96 TESTMODE 97 TxENABLE 33 Terminal Functions (continued) I/O DESCRIPTION I/O Bidirectional serial-port data in the three-pin serial interface mode. Input-only serial data in the four-pin serial interface mode. Internal pulldown O High-impedance state (the pin is not used) in the three-pin serial interface mode. Serial-port output data in the four-pin serial interface mode. I Asynchronous hardware power-down input. Active high. Internal pulldown I TESTMODE is DGND for the user. I TxENABLE is used in interleaved mode. The rising edge of TxENABLE synchronizes the data of channels A and B. The first data after the rising edge of TxENABLE is treated as A data, while the next data is treated as B data and so on. In any mode, TxENABLE being low sets DAC outputs to midscale. Internal pulldown ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range AVDD (2) DVDD (3) CLKVDD (2) IOVDD (2) PLLVDD (2) Voltage between AGND, DGND, CLKGND, PLLGND, and IOGND Supply voltage range AVDD to DVDD DA[15:0] (3) DB[15:0] (3) SLEEP (3) CLK1, CLK2, CLK1C, CLK2C(3) RESETB (3) LPF (3) IOUT1, IOUT2(2) EXTIO, BIASJ(2) EXTLO (2) Peak input current (any input) Operating free-air temperature range, TA: DAC5686I Storage temperature range Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds UNIT –0.5 V to 4 V –0.5 V to 2.3 V –0.5 V to 4 V –0.5 V to 4 V –0.5 V to 4 V –0.5 V to 0.5 V –0.5 V to 2.6 V –0.5 V to IOVDD + 0.5 V –0.5 V to IOVDD + 0.5 V –0.5 V to IOVDD + 0.5 V –0.5 V to CLKVDD + 0.5 V –0.5 V to IOVDD + 0.5 V –0.5 V to PLLVDD + 0.5 V –1 V to AVDD + 0.5 V –0.5 V to AVDD + 0.5 V –0.5 V to IOVDD + 0.5 V 20 mA –40C to 85C –65C to 150C 260C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Measured with respect to AGND (3) Measured with respect to DGND 6 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS)(1) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Resolution DC Accuracy(2) INL Integral nonlinearity 1 LSB = IOUTFS/216, TMIN to TMAX 16 12 1.84e–4 DNL Differential nonlinearity 9 1.37e–4 Analog Output Coarse gain linearity (INL) LSB = 1/10th of full scale 0.016 Fine gain linearity (INL) 3 Offset error Mid-code offset 0.003 Without internal reference 0.7 Gain error With internal reference 0.7 Gain mismatch Full-scale output current(3) Output compliance range(4) Output resistance With internal reference, dual DAC, SSB mode IOUTFS = 20 mA –2 2 AVDD – 0.5 2 20 AVDD + 0.5 300 Output capacitance 5 Reference Output Reference voltage Reference output current(5) 1.14 1.2 1.26 100 Reference Input VEXTIO Input voltage range Input resistance 0.1 1.25 1 Small-signal bandwidth 2.5 Input capacitance 100 Temperature Coefficients Offset drift 3 Without internal reference 15 Gain drift With internal reference 40 Reference voltage drift 25 UNIT LSB IOUTFS LSB IOUTFS LSB LSB %FSR %FSR %FSR mA V kΩ pF V nA V MΩ kHz pF ppm of FSR/C ppm of FSR/C ppm/C (1) Specifications subject to change without notice. (2) Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25 Ω each to AVDD (3) Nominal full-scale current, IOUTFS , equals 16× the IBIAS current. (4) The upper limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5686 device. The lower limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity. (5) Use an external buffer amplifier with high-impedance input to drive any external load. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 7 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (continued) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Power Supply AVDD Analog supply voltage 3 3.3 3.6 DVDD Digital supply voltage 1.65 1.8 1.95 CLKVDD Clock supply voltage 3 3.3 3.6 IOVDD I/O supply voltage 1.65 3.6 PLLVDD PLL supply voltage 3 3.3 3.6 IAVDD Analog supply current Single (quad) DAC mode; including output current through load resistor, mode 7 Dual DAC mode; including output current through load resistor, mode 11 30 55 IDVDD Digital supply current 242 ICLKVDD Clock supply current fDATA = 125 MSPS, SSB mode, 10 IPLLVDD PLL supply current fDAC = 500 MSPS, 40-MHz IF 28 IIOVDD IO supply current <3 IAVDD Sleep mode, AVDD supply current 1 IDVDD Sleep mode, DVDD supply current 4 ICLKVDD Sleep mode, CLKVDD supply current Sleep mode 2 IPLLVDD Sleep mode, PLLVDD supply 0.5 current IIOVDD PD Sleep mode, IOVDD supply current Power dissipation Mode 1(6) AVDD = 3.3 V, DVDD = 1.8 V Mode 2(7) AVDD = 3.3 V, DVDD = 1.8 V Mode 5(8) AVDD = 3.3 V, DVDD = 1.8 V Mode 7(9) AVDD = 3.3 V, DVDD = 1.8 V Mode 9(10) AVDD = 3.3 V, DVDD = 1.8 V Mode 11(11) AVDD = 3.3 V, DVDD = 1.8 V 0.25 215 495 445 754 547 855 950 APSRR Power supply rejection ratio –0.2 0.2 DPSRR Power supply rejection ratio –0.2 0.2 UNIT V V V V V mA mA mA mA mA mA mA mA mA mA mW %FSR/V %FSR/V (6) Mode 1: Dual DAC mode, fully bypassed, fDAC = 160 MSPS, fOUT = 20 MHz (7) Mode 2: Dual DAC mode, 2× interpolation, fDAC = 320 MSPS, fOUT = 20 MHz (8) Mode 5: Quadrature modulation mode, 4× interpolation, fDAC/4 mixing, fDAC = 320 MSPS, fOUT = 100 MHz (9) Mode 7: Quadrature modulation mode, 4× interpolation, NCO running at 320 MHz, fDAC = 320 MSPS, fOUT = 100 MHz (10) Mode 9: SSB modulation mode, 4× interpolation, fDAC/4 mixing, fDAC = 320 MSPS, fOUT = 100 MHz (11) Mode 11: SSB modulation mode, 4× interpolation, NCO running at 320 MHz, fOUT = 100 MHz, maximum operating condition 8 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS)(1) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 20 mA, external clock mode, differential transformer-coupled output, 50-Ω doubly terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS Analog Output fCLK Maximum output update rate ts(DAC) Output settling time to 0.1% Mid-scale transition tpd tr(IOUT) (2) tf(IOUT) (2) Output propagation delay Output rise time 10% to 90% Output fall time 90% to 10% AC Performance—1:1 Impedance-Ratio Transformer First Nyquist zone < fDATA/2(3), 4× interpolation, dual DAC mode, fDATA = 52 MSPS, fOUT = 14 MHz, TA = 25C, IOVDD = 1.8 V SFDR Spurious free dynamic range First Nyquist zone < fDATA/2(3), 4× interpolation, dual DAC mode, fDATA = 160 MSPS, fOUT = 20 MHz, full bypass, TA = TMIN to TMAX and PLLVDD = 3.3 V for MIN, 25C for TYP, IOVDD = 1.8 V for TYP First Nyquist zone < fDATA/2(3), 2× interpolation, dual DAC mode, fDATA = 160 MSPS, fOUT = 41 MHz, TA = 25C, IOVDD = 1.8 V First Nyquist zone < fDATA/2(3), 2× interpolation, dual DAC mode, fDATA = 160 MSPS, fOUT = 61 MHz, TA = 25C, IOVDD = 1.8 V SNR Signal-to-noise ratio ACLR Adjacent-channel power ratio First Nyquist zone < fDATA/2, fDATA = 100 MSPS, fOUT = 5 MHz, IOVDD = 1.8 V, fDAC = 400 MSPS First Nyquist zone < fDATA/2, fDATA = 78 MSPS, fOUT = 15.6 MHz, 15.8 MHz, 16.2 MHz, 16.4 MHz, IOVDD = 1.8 V, fDAC = 314 MSPS Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, TESTMODEL 1, 10 ms, fDATA = 122.88 MSPS, baseband, dual DAC, 2× interpolation, fOUT = 245 MSPS Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, TESTMODEL 1, 10 ms, fDATA = 76.8 MSPS, IF = 19.2 MHz, dual DAC, 2× interpolation, fOUT = 153.6 MSPS Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, TESTMODEL 1, 10 ms, fDATA = 122.88 MSPS, IF = 30.72 MHz, dual DAC, 2× interpolation, fDAC = 245 MSPS Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, TESTMODEL 1, 10 ms, fDATA = 61.44 MSPS, IF = 61.44 MHz, quad mode, fDAC/4, 4× interpolation, fDAC = 245 MSPS Two-carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, TESTMODEL 1, 10 ms, fDATA = 122.88 MSPS, IF = 30.72 MHz, dual DAC, 2× interpolation, fDAC = 245 MSPS Four-carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, TESTMODEL 1, 10 ms, fDATA = 121.88 MSPS, complex IF - 30.72 MHz, quad mode, fDAC/4, 4× interpolation, IF = 92.16 MHz MIN TYP MAX UNIT 500 12 2.5 2.5 2.5 MSPS ns ns ns ns 89 68 79 dBc 72 68 80 dB 72 72 77 76 dB 73 72 64 (1) Specifications subject to change without notice (2) Measured single-ended into 50-Ω load (3) See the Non-Harmonic Clock-Related Spurious Signals section for information on spurious products out of band (> fDATA/2). Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): DAC5686 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (continued) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 20 mA, external clock mode, differential transformer-coupled output, 50-Ω doubly terminated load (unless otherwise noted) IMD3 IMD PARAMETER Third-order two-tone intermodulation Four-tone intermodulation TEST CONDITIONS fDATA = 160 MSPS, fOUT = 60.1 and 61.1 MHz, 2× interpolation, 320 MSPS, IOVDD = 1.8 V, each tone at –6 dBFS fDATA = 100 MSPS, fOUT = 15.1 and 16.1 MHz, 2× interpolation, 200 MSPS, IOVDD = 1.8 V, each tone at –6 dBFS fDATA = 100 MSPS, fOUT = 15.6 MHz, 15.8 MHz, 16.2 MHz, 16.4 MHz, 4× interpolation, 400 MSPS, IOVDD = 1.8 V, each tone at –12 dBFS MIN TYP MAX UNIT 74 dBc 84 85 dBc ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS)(1) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMOS Interface VIH High-level input voltage VIL Low-level input voltage IIH High-level input current IIL Low-level input current Input capacitance 2 3 0 0 –40 –40 5 V 0.8 V 40 A 40 A pF VOH VOL PLL (2) High-level output voltage, PLLLOCK, SDO, SDIO (I/O) Low-level output voltage, PLLLOCK, SDO, SDIO (I/O) IL = –100 A IL = –8 mA IL = 100 A IL = 8 mA IOVDD – 0.2 0.8 × IOVDD V 0.2 V 0.22 × IOVDD Input data rate supported 1 160 MSPS Phase noise At 600-kHz offset, measured at DAC output, 25-MHz 0-dBFS tone, 128 fDATA = 125 MSPS, 4× interpolation At 6-MHz offset, measured at DAC output, 25-MHz 0-dBFS tone, fDATA 151 = 125 MSPS, 4× interpolation dBc/Hz VCO minimum frequency PLL_rng = 00 (nominal) 120 MHz VCO maximum frequency PLL_rng = 00 (nominal) 500 MHz NCO NCO clock (DAC update rate) 320 MHz Serial Port Timing tsu(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns tsu(SDIO) Setup time, SDIO valid to rising edge of SCLK 10 ns th(SDIO) Hold time, SDIO valid to rising edge of SCLK 5 ns tSCLK tSCLKH tSCLKL Period of SCLK High time of SCLK Low time of SCLK 100 ns 40 ns 40 ns (1) Specifications subject to change without notice. (2) See the Non-Harmonic Clock-Related Spurious Signals section for information on spurious products generated in PLL clock mode. 10 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued) over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(DATA) Data output delay after falling edge of SCLK 10 ns Parallel Data Input Timing, CLK1 Latching (PLL Mode and Dual Clock Mode) tsu(DATA) Setup time, data valid to rising edge of CLK1 0.3 –0.4 ns th(DATA) Hold time, data valid after rising edge of CLK1 1.2 0.6 ns Timing Parallel Data Input (External Clock Mode, CLK2 Input) tsu(DATA) Setup time, DATA valid to rising edge of PLLLOCK High-impedance load on PLLLOCK. Note that tsu increases with a lower-impedance load. 4.6 3 ns High-impedance load on PLLLOCK. th(DATA) Hold time, DATA valid after rising Note that th decreases (becomes edge of PLLLOCK more negative) with a –0.8 –2.4 ns lower-impedance load. td(PLLLock) Delay from CLK2 rising edge to PLLLOCK rising edge High-impedance load on PLLLOCK. Note that PLLLOCK delay increases with a lower-impedance load. 2.5 4.2 6.5 ns INL – Integral Nonlinearity Error – LSB 10 8 6 4 2 0 –2 –4 –6 –8 –10 0 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY ERROR vs INPUT CODE 10000 20000 30000 40000 Input Code Figure 1. 50000 60000 70000 G001 Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 11 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com DNL – Differential Nonlinearity Error – LSB TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL NONLINEARITY ERROR vs INPUT CODE 15 13 11 9 7 5 3 1 –1 0 10000 20000 30000 40000 50000 60000 70000 Input Code G002 Figure 2. SFDR – In-Band Spurious-Free Dynamic Range – dBc SINGLE-TONE SPECTRUM 10 fDATA = 125 MSPS 0 fIN = 20 MHz Dual DAC Mode −10 4y Interpolation PLLVDD = 0 V −20 −30 IN-BAND SPURIOUS-FREE DYNAMIC RANGE vs OUTPUT FREQUENCY 90 85 80 0 dBfS 75 –12 dBfS –6 dBfS Power – dBm −40 −50 −60 −70 −80 −90 0 50 100 150 200 f – Frequency – MHz Figure 3. 250 G003 70 65 60 fDATA = 125 MSPS Dual DAC Mode 55 4y Interpolation In-band = 0–62.5 MHz PLLVDD = 0 V 50 10 15 20 25 30 35 40 45 fO – Output Frequency – MHz Figure 4. 50 G004 12 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS (continued) SFDR – Out-of-Band Spurious-Free Dynamic Range – dBc OUT-OF-BAND SPURIOUS-FREE DYNAMIC RANGE vs OUTPUT FREQUENCY 80 75 70 0 dBfS 65 60 55 –12 dBfS –6 dBfS 50 fDATA = 125 MSPS Dual DAC Mode 45 4y Interpolation Out-of-Band = 62.5–250 MHz PLLVDD = 0 V 40 10 15 20 25 30 35 40 45 fO – Output Frequency – MHz Figure 5. TWO-TONE IMD3 vs OUTPUT FREQUENCY 95 50 G005 90 ± 0.5 MHz 85 80 ± 2 MHz 75 fDATA = 150 MSPS 70 Dual DAC Mode 2y Interpolation PLLVDD = 0 V 65 10 15 20 25 30 35 40 45 50 55 60 fO – Output Frequency – MHz G007 Figure 7. Power – dBm Power – dBm SINGLE-TONE SPECTRUM 10 fDATA = 75 MSPS 0 fIN = None NCO On −10 fOUT = 100 MHz Quad Mode −20 4y Interpolation PLLVDD = 0 V −30 −40 −50 −60 −70 −80 −90 0 25 50 75 100 125 f – Frequency – MHz Figure 6. 150 G006 TWO-TONE IMD PERFORMANCE 0 fDATA = 150 MSPS −10 fIN1 = 19.5 MHz fIN2 = 20.5 MHz −20 Dual DAC Mode 2y Interpolation −30 PLLVDD = 0 V −40 −50 −60 −70 −80 −90 −100 10 15 20 25 f – Frequency – MHz Figure 8. 30 G008 Two-Tone IMD3 – dBc Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 13 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) Two-Tone IMD3 – dBc TWO-TONE IMD3 vs OUTPUT FREQUENCY 90 fDATA = 80 MSPS NCO On 85 Quad Mode 4y Interpolation PLLVDD = 0 V 80 75 ± 0.5 MHz 70 ± 2 MHz 65 60 55 10 30 50 70 90 110 130 fO – Output Frequency – MHz Figure 9. 150 G009 Power – dBm TWO-TONE IMD PERFORMANCE 0 fDATA = 80 MSPS −10 fIN1 = –0.5 MHz fIN2 = 0.5 MHz −20 NCO = 70 MHz Quad Mode −30 4y Interpolation PLLVDD = 0 V −40 −50 −60 −70 −80 −90 −100 60 65 70 75 f – Frequency – MHz Figure 10. 80 G010 Power – dBm TWO-TONE IMD PERFORMANCE 0 fDATA = 80 MSPS −10 fIN1 = –0.5 MHz fIN2 = 0.5 MHz −20 NCO = 150 MHz Quad Mode −30 4y Interpolation PLLVDD = 0 V −40 −50 −60 −70 −80 −90 −100 140 145 150 155 f – Frequency – MHz Figure 11. 160 G011 Power – dBm WCDMA TEST MODEL 1: SINGLE CARRIER −20 fDATA = 122.88 MSPS −30 fIN = 30.72 MHz ACLR = 78.6 dB −40 4y Interpolation Dual DAC Mode −50 PLLVDD = 0 V −60 −70 −80 −90 −100 −110 −120 −130 18 22 26 30 34 38 f – Frequency – MHz Figure 12. 42 G012 14 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 TYPICAL CHARACTERISTICS (continued) Power – dBm WCDMA TEST MODEL 1: DUAL CARRIER −20 fDATA = 122.88 MSPS −30 fIN = 30.72 MHz ACLR = 71.69 dB −40 4y Interpolation Dual DAC Mode −50 PLLVDD = 0 V −60 −70 −80 −90 −100 −110 −120 −130 15 20 25 30 35 40 f – Frequency – MHz Figure 13. 45 G013 WCDMA TEST MODEL 1: FOUR CARRIER −10 fDATA = 122.88 MSPS −20 fIN = –30.72 MHz Complex ACLR = 63.29 dB −30 4y Interpolation Quad Mode −40 PLLVDD = 0 V −50 −60 −70 −80 −90 −100 −110 72 77 82 87 92 97 102 107 112 f – Frequency – MHz G015 Figure 15. Power – dBm Power – dBm WCDMA TEST MODEL 1: DUAL CARRIER −20 fDATA = 122.88 MSPS −30 fIN = Baseband Complex ACLR = 69.08 dB −40 2y Interpolation Quad Mode −50 PLLVDD = 0 V −60 −70 −80 −90 −100 −110 −120 46 51 56 61 66 71 f – Frequency – MHz Figure 14. 76 G014 WCDMA TEST MODEL 1: DUAL CARRIER −10 fDATA = 122.88 MSPS fIN = 30.72 MHz Complex ACLR = 58.58 dB −30 4y Interpolation Quad Mode PLLVDD = 0 V −50 −70 −90 −110 138 143 148 153 158 163 168 f – Frequency – MHz G016 Figure 16. Power – dBm Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 15 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) VCO GAIN vs VCO FREQUENCY 600 Boost for 0% 500 GVCO – VCO Gain – MHz/V 400 300 Boost for 45% 200 100 0 0 Boost for 30% Boost for 15% 100 200 300 400 500 600 fVCO – VCO Frequency – MHz Figure 17. 700 G017 16 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 DETAILED DESCRIPTION Dual-Channel Mode In dual-channel mode, interpolation filtering increases the DAC update rate, thereby reducing sinx/x rolloff and enabling relaxed analog post-filtering, and is useful for baseband I and Q modulation or two-channel low-IF signals. The dual-channel mode is set by mode[1:0] = 00 in the config_lsb register. Figure 18 shows the data path architecture in dual-channel mode. The A- and B-data paths, which are independent, consist of four cascaded half-band interpolation filters, followed by an optional inverse sinc filter. Interpolation filtering is selected as 2×, 4×, 8×, or 16× by sel[1:0] in the config_lsb register. Magnitude spectral responses of each filter are presented following in the section on digital filtering. Full bypass of all the interpolation filters is selected by fbypass in the config_lsb register. The inverse sinc filter is intended for use in single-sideband and quadrature modulation modes and is of limited benefit in dual-channel mode. fDATA DEMUX DA[15:0] FIR1 FIR2 FIR3 FIR4 FIR5 2fDATA y2 4fDATA 8fDATA 16fDATA x sin(x) DB[15:0] FIR1 FIR2 FIR3 FIR4 FIR5 2fDATA y2 4fDATA 8fDATA 16fDATA x sin(x) A Offset 2y–16y fDATA 16-Bit DAC A Gain B Gain 16-Bit DAC B Offset IOUTA1 IOUTA2 IOUTB1 IOUTB2 Figure 18. Data Path in Dual-Channel Mode B0020-01 Single-Sideband Mode Single-sideband (SSB) mode provides optimum interfacing to analog quadrature modulators. The SSB mode is selected by mode[1:0] = 01 in the config_lsb register. Figure 19 shows the data path architecture in single-sideband mode. Complex baseband I and Q are input to the DAC5686, which in turn performs a complex mix, resulting in Hilbert transform pairs at the outputs of the DAC5686's two DACs. NCO mixing frequencies are programmed through 32-bit freq (4 registers); 16-bit phase adjustments are programmed through phase (2 registers). The NCO operates at the DAC update rate; thus, increased amounts of interpolation allow for higher IFs. More details for the NCO are provided as follows. For mixing to fDAC/4, DAC5686 provides a specific architecture that exploits the {… –1 0 1 0 …} resultant streams from sin and cos; the NCO is shut off in this mode to conserve power. fDAC/4 mix mode is implemented by deasserting nco in register config_msb while in single-sideband or quadrature modulation mode. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 17 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com fDATA DEMUX DA[15:0] y2–y16 DB[15:0] y2–y16 cos A Offset 2y–16y fDATA + FIR5 A x sin sin(x) 16-Bit DAC IOUTA1 IOUTA2 +/− A Gain sin + B Gain B x cos sin(x) 16-Bit DAC IOUTB1 IOUTB2 + B Offset Figure 19. Data Path in SSB Mode B0021-01 Figure 20 shows the DAC5686 interfaced to an RF quadrature modulator. The outputs of the complex mixer stage can be expressed as: A(t) = I(t)cos(ωct) – Q(t)sin(ωct) = m(t) B(t) = I(t)sin(ωct) + Q(t)cos(ωct) = mh(t) where m(t) and mh(t) connote a Hilbert transform pair. Upper single-sideband up-conversion is achieved at the output of the analog quadrature modulator, whose output is expressed as: IF(t) = I(t)cos(ωc+ ωLO)t – Q(t)sin(ωc+ ωLO)t Flexibility is provided to the user by allowing for the selection of –B(t) out, which results in lower-sideband up-conversion. This option is selected by ssb in the config_msb register. Figure 21 depicts the magnitude spectrum along the signal path during single-sideband up-conversion for real input. Further flexibility is provided to the user by allowing for the inverse of sin to be used in the complex mixer by programming rspect in the config_usb register. The four combinations of rspect and ssb allow the user to select one of four complex spectral bands to input to a quadrature modulator (see Figure 22). 18 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 cos(wct) DAC5686 I + A(t) = I(t)cos(wct) – Q(t)sin(wct) sin(wct) A – DAC Q cos(wLOt) sin(wct) IF(t) = I(t)cos(wc + wLO)t – Q(t)sin(wc + wLO)t + cos(wct) + DAC B 0° sin(wLOt) 90° Quadrature Modulator LO B(t) = I(t)sin(wct) + Q(t)cos(wct) Figure 20. DAC5686 in SSB Mode With Quadrature Modulator B0022–01 Real Input Spectrum to DAC5686 0 ω Complex Input Spectrum to Quadrature Modulator 0 ωc ω Output Spectrum to Quadrature Modulator ωLO – ωc ωLO ωLO + ωc ω M0016-01 Figure 21. Spectrum After First and Second Up-Converson for Real Input Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 19 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Complex Input Spectrum to DAC5686 0 ω –ωc 0 ωc ω rspect = 0 ssb = 0 Complex Input Spectra to –ωc 0 Quadrature Modulator –ωc 0 ωc ω ωc ω rspect = 0 ssb = 1 rspect = 1 ssb = 1 –ωc 0 ωc ω Figure 22. Complex Input Spectrum and DAC Output Spectra rspect = 1 ssb = 0 M0017-01 To compensate for the sinx/x rolloff of the zero-order hold of the DACs, the DAC5686 provides an inverse sinc FIR, which provides high-frequency boost. The magnitude spectral response of this filter is presented in the Digital Filters section. DAC Gain and Offset Control Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local-oscillator feedthrough. Gain and offset imbalances between the two DACs are compensated for by programming daca_gain, dacb_gain, daca_offset, and dacb_offset in registers 0x0A through 0x0F (see the following register descriptions). The DAC gain value controls the full-scale output current. The DAC offset value adds a digital offset to the digital data before digital-to-analog conversion. Care must be taken when using the offset by restricting the dynamic range of the digital signal to prevent saturation when the offset value is added to the digital signal. Dual-Channel Real Up-Conversion With NCO Set to fDAC/2 The final interpolation filter in the DAC5686 can be converted from a low-pass filter to a high-pass filter by multiplying the interpolation filter output by the (–1)N = 1, –1, 1, –1, … sequence generated by the NCO in single-sideband mode. The high-pass filter selects a spectrally inverted image at fDAC/2 – fIF, where fIF is the center frequency of the input spectrum. Note that in this mode fDAC is limited by the 320-MHz maximum frequency for NCO operation. 20 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 The output of the mixer for the Nth sample is Aout(N) = Ain(N)cos(2π(Nf + f0)/fDAC + φ) – Bin(N)sin(2π(Nf + f0)/fDAC + φ) Bout(N) = Ain(N)sin(2π(Nf + f0)/fDAC + φ) + Bin(N)cos(2π(Nf + f0)/fDAC + φ) where f = freq × fDAC/232 and φ = phase × π/215 and f0 is the initial value of the NCO accumulator. When f = fDAC/2, f0 = 0, and φ = 0, the sine term is 0 and the equations simplify to Aout(N) = Ain(N) × (–1)N Bout(N) = Bin(N) × (–1)N resulting in two independent, real up-conversion paths. It is essential that the NCO accumulator initial value f0 = 0 to eliminate the cross-terms between the A and B channels. The accumulator is reset to 0 when the NCO is running by raising the PHSTR pin to IOVDD (when sync_phstr is set to 0). Note that the accumulator remains at 0 until the PHSTR pin is lowered to GND. The following steps ensure that the accumulator does not have a non-zero starting value: 1. Program the frequency register to 231. 2. Enable the NCO by asserting register bit nco in config_msb. 3. Raise PHSTR to IOVDD. 4. Lower PHSTR to GND. Quadrature Modulation Mode In quadrature modulation mode, on-chip mixing of complex I and Q inputs provides the final baseband-to-IF up-conversion. Quadrature modulation mode is selected by mode[1:0] = 10 in the config_lsb register. Figure 23 shows the data path architecture in quadrature modulation mode. Complex baseband I and Q from the ASIC/FPGA are input to the DAC5686, which in turn quadrature modulates I and Q to produce the final IF single-sideband spectrum. DAC A is held constant, while DAC B presents the DAC5686 quadrature modulator mode output. NCO mixing frequencies are programmed through 32-bit freq (4 registers); 16-bit phase adjustments are programmed through phase (2 registers). The NCO operates at the DAC update rate; thus, increased amounts of interpolation allow for higher IFs. More details for the NCO are provided in the NCO section. For mixing to fDAC/4, the DAC5686 provides a specific architecture that exploits the {… –1 0 1 0 …} resultant streams from sin and cos; the NCO is shut off in this mode to conserve power. The fDAC/4 mix mode is implemented by deasserting nco in register config_msb while in single-sideband or quadrature modulation mode. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 21 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com fDATA DEMUX FIR1 DA[15:0] y2 DB[15:0] FIR1 y2 FIR2 y2 FIR2 y2 FIR3 y2 FIR3 y2 cos sin FIR4 y2 FIR4 y2 + FIR5 x sin(x) +/− 2y–16y fDATA 16-Bit DAC B Offset B Gain IOUTB1 IOUTB2 sin cos Figure 23. Data Path in Quadrature Modulation Mode B0023-01 In quadrature modulation mode, only one output from the complex mixer stage is routed to the B DAC. The output can be expressed as: B(t) = I(t)sin(ωct) + Q(t)cos(ωct) or B(t) = I(t)cos(ωct) – Q(t)sin(ωct) Single-sideband up-conversion is achieved when I and Q are Hilbert transform pairs. Upper- or lower-sideband up-conversion is selected by ssb in the config_msb register, which selects the output from the mixer stage that is routed out. The offset and gain features for the B DAC, as previously described, are functional in the quadrature mode. Serial Interface The serial port of the DAC5686 is a flexible serial interface that communicates with industry-standard microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the operating modes of the DAC5686. It is compatible with most synchronous transfer formats and can be configured as a 3- or 4-pin interface by sif4 in register config_msb. In both configurations, SCLK is the serial-interface input clock and SDENB is the serial-interface enable. For the 3-pin configuration, SDIO is a bidirectional pin for both data-in and data-out. For the 4-pin configuration, SDIO is data-in only and SDO is data-out only. Each read/write operation is framed by signal SDENB (serial data enable bar) asserted low for 2 to 5 bytes, depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle, which identifies the following data transfer cycle as read or write, how many bytes to transfer, and the address to/from which to transfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a detailed description of each bit. Frame bytes 2 through 5 comprise the data to be transferred. MSB Bit 7 Table 1. Instruction Byte of the Serial Interface 6 5 4 3 2 LSB 1 0 22 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 Table 1. Instruction Byte of the Serial Interface (continued) MSB LSB Description R/W N1 N0 – A3 A2 A1 A0 R/W: Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from the DAC5686 and a low indicates a write operation to the DAC5686. N[1:0]: Identifies the number of data bytes to be transferred per Table 2. Data is transferred MSB-first. Table 2. Number of Transferred Bytes Within One Communication Frame N1 N0 0 0 0 1 1 0 1 1 DESCRIPTION Transfer 1 byte Transfer 2 bytes Transfer 3 bytes Transfer 4 bytes A4: Unused A[3:0]: Identifies the address of the register to be accessed during the read or write operation. For multibyte transfers, this address is the starting address and the address decrements. Note that the address is written to the DAC5686 MSB-first. Serial-Port Timing Diagrams Figure 24 shows the serial-interface timing diagram for a DAC5686 write operation. SCLK is the serial-interface clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial data-in. Input data to the DAC5686 is clocked on the rising edges of SCLK. SDENB Instruction Cycle Data Transfer Cycle(s) SCLK SDIO R/W N1 N0 − A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDENB SCLK ts(SDENB) t(SCLK) SDIO ts(SDIO) th(SDIO) t(SCLKL) t(SCLKH) Figure 24. Serial-Interface Write Timing Diagram T0037-01 Figure 25 shows the serial-interface timing diagram for a DAC5686 read operation. SCLK is the serial-interface Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 23 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial data-in during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the DAC5686 during the data transfer cycle(s), while SDO is in a high-impedance state. In the 4-pin configuration, SDO is data-out from the DAC5686 during the data transfer cycle(s). SDO is never placed in the high-impedance state in the four-pin configuration. SDENB Instruction Cycle Data Transfer Cycle(s) SCLK SDIO R/W N1 N0 − A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 SDO D7 D6 D5 D4 D3 D2 D1 D0 0 SDENB 4-Pin Configuration 3-Pin Configuration Output Output SCLK SDIO SDO Data n Data n−1 td(DATA) Figure 25. Serial-Interface Read Timing Diagram T0038-01 Clock Generation In the DAC5686, the internal clocks (1×, 2×, 4×, 8×, and 16×, as needed) for the logic, FIR interpolation filters, and DAC are derived from a clock at either the input data rate using an internal PLL (PLL clock mode) or the DAC output sample rate (external clock mode). Power for the internal PLL blocks (PLLVDD and PLLGND) is separate from power for the other clock generation blocks (CLKVDD and CLKGND), thus minimizing phase noise within the PLL. The DAC5686 has three clock modes for generating the internal clocks (1×, 2×, 4×, 8×, and 16×, as needed) for the logic, FIR interpolation filters, and DACs. The clock mode is set using the PLLVDD pin and dual_clk in register config_usb. A block diagram for the clock generation circuit is shown in Figure 27. 1. PLLVDD = 0 V and dual_clk = 0: EXTERNAL CLOCK MODE In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used, so the LPF circuit is not applicable. The input data rate clock and interpolation rate are selected by the registers sel[1:0], and are output through the PLLLOCK pin. It is common to use the PLLLOCK clock to drive the chip that sends the data to the DAC; otherwise, there is phase ambiguity regarding how the DAC divides down to the input sample rate clock and an external clock divider divides down. (For a divide-by-N, there are N possible phases.) The phase ambiguity can also be solved by using PHSTR pin with a synchronization signal. 2. PLLVDD = 3.3 V (dual_clk can be 0 or 1 and is ignored): PLL CLOCK MODE Power for the internal PLL blocks (PLLVDD and PLLGND) is separate from power for the other clock generation blocks (CLKVDD and CLKGND), thus minimizing PLL phase noise. 24 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 In PLL CLOCK MODE, the DAC is driven at the input sample rate (unless the data is multiplexed) through CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC generates the higher-speed DAC sample-rate clock using an internal PLL/VCO. In PLL clock mode, the user provides a differential external reference clock on CLK1/CLK1C. A type-4 phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated by dividing the VCO output by 1×, 2×, 4×, or 8× as selected by the prescaler (div[1:0]). The output of the prescaler is the DAC sample rate clock and is divided down to generate clocks at ÷2, ÷4, ÷8, and ÷16. The feedback clock is selected by the registers sel[1:0], and then is fed back to the PFD for synchronization to the input clock. Because the feedback clock is also used for the data input rate, the interpolation rate of the DAC5686 is the ratio of DAC output clock to the feedback clock. The PLLLOCK pin is an output that indicates when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user at pin LPF. See the low-pass filter section for filter-setting calculations. This is the only mode where the LPF filter applies. Use of the internal PLL/VCO generally results in higher phase noise than if an externally generated DAC clock is used. At low frequencies, such as baseband signals, use of the internal PLL/VCO likely has a minimal effect on signal quality. For higher IF frequencies, such as in single sideband or quadrature modulation mode, the PLL/VCO phase noise can result in degradation of the signal. Note that most of the DAC5686 plots and typical specifications are in external clock mode (PLLVDD = 0). Use of the DAC5686 PLL/VCO also can result in higher out-of-band spurious signals (see the Non-Harmonic Clock-Related Spurious Signals section). 3. PLLVDD = 0 V and dual_clk = 1: DUAL CLOCK MODE In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and at the input data rate through CLK1/CLK1C. The DUAL CLOCK MODE has the advantage of a clean external clock for DAC sampling without the phase ambiguity. The edges of CLK1 and CLK2 must be aligned to within talign (See Figure 26), defined as talign = 1 2fCLK 2 - 0.5 ns where fCLK2 is the clock frequency of CLK2. For example, talign = 0.5 ns at fCLK2 = 500 MHz and 1.5 ns at fCLK2 = 250 MHz. CLK2 CLK1 ∆ < talign DA[15:0] DB[15:0] th ts Figure 26. DAC and Data Clock Mode T0002−01 The CDC7005 from Texas Instruments is recommended for providing phase-aligned clocks at different frequencies for this application. Table 3 provides a summary of the clock configurations with corresponding data rate ranges. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 25 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com CLK1 CLK1C CLK2 CLK2C PLLVDD PLLGND CLKVDD CLKGND Clk Buffer PFD Clk Buffer LPF Charge Pump VCO 0 s1 DIV[1:0] PLLVDD /1 /2 /4 /8 /2 /2 /2 /2 clk_16y DAC Sample Clock clk_8y clk_4y clk_2y clk_1y Data PLLLOCK PLLVDD D[15:0] SEL[1:0] Figure 27. Clock-Generation Architecture B0024-01 Table 3. Clock-Mode Configuration CLOCK MODE PLLVDD DIV[1:0] SEL[1:0] DATA RATE (MSPS) PLLLOCK PIN FUNCTION Non-interleaved input data; internal PLL off; DA[15:0] data rate matches DB[15:0] data rate. External 2× 0V XX 00 DC to 160 External clk2/clk2c clock ÷ 2 External 4× 0V XX 01 DC to 125 External clk2/clk2c clock ÷ 4 External 8× 0V XX 10 DC to 62.5 External clk2/clk2c clock ÷ 8 External 16× 0V XX 11 DC to 31.25 External clk2/clk2c clock ÷ 16 External dual clock 2× 0V XX 00 DC to 160 None - held low External dual clock 4× 0V XX 01 DC to 125 None - held low External dual clock 8× 0V XX 10 DC to 62.5 None - held low External dual clock 16× 0V XX 11 DC to 31.25 None - held low Interleaved input data on the DA[15:0] input pins; internal PLL off External 2× 0V XX 00 DC to 80 External clk2/clk2c clock ÷ 2 External 4× 0V XX 01 DC to 80 External clk2/clk2c clock ÷ 4 External 8× 0V XX 10 DC to 62.5 External clk2/clk2c clock ÷ 8 External 16× 0V XX 11 DC to 31.25 External clk2/clk2c clock ÷ 16 External dual clock 2× 0V XX 00 DC to 80 None - held low External dual clock 4× 0V XX 01 DC to 62.5 None - held low External dual clock 8× 0V XX 10 DC to 31.25 None - held low External dual clock 16× 0V XX 11 DC to 15.625 None - held low 26 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 Table 3. Clock-Mode Configuration (continued) CLOCK MODE PLLVDD DIV[1:0] SEL[1:0] DATA RATE (MSPS) PLLLOCK PIN FUNCTION Non-interleaved input data; internal PLL on; DA[15:0] data rate matches DB[15:0] data rate. Internal 2× 3.3 V 00 00 125 to 160 Internal PLL lock indicator Internal 2× 3.3 V 01 00 62.5 to 125 Internal PLL lock indicator Internal 2× 3.3 V 10 00 31.25 to 62.5 Internal PLL lock indicator Internal 2× 3.3 V 11 00 15.63 to 31.25 Internal PLL lock indicator Internal 4× 3.3 V 00 01 62.5 to 125 Internal PLL lock indicator Internal 4× 3.3 V 01 01 31.25 to 62.5 Internal PLL lock indicator Internal 4× 3.3 V 10 01 15.63 to 31.25 Internal PLL lock indicator Internal 4× 3.3 V 11 01 7.8125 to 15.625 Internal PLL lock indicator Internal 8× 3.3 V 00 10 31.25 to 62.5 Internal PLL lock indicator Internal 8× 3.3 V 01 10 15.63 to 31.25 Internal PLL lock indicator Internal 8× 3.3 V 10 10 7.8125 to 15.625 Internal PLL lock indicator Internal 8× 3.3 V 11 10 3.9 to 7.8125 Internal PLL lock indicator Internal 16× 3.3 V 00 11 15.625 to 31.25 Internal PLL lock indicator Internal 16× 3.3 V 01 11 7.8125 to 15.625 Internal PLL lock indicator Internal 16× 3.3 V 10 11 3.9062 to 7.8125 Internal PLL lock indicator Interleaved input data on the DA[15:0] input pins; internal PLL on Internal 2× 3.3 V 00 00 Not recommended Internal PLL lock indicator Internal 2× 3.3 V 01 00 62.5 to 80 Internal PLL lock indicator Internal 2× 3.3 V 10 00 31.25 to 62.5 Internal PLL lock indicator Internal 2× 3.3 V 11 00 15.625 to 31.25 Internal PLL lock indicator Internal 4× 3.3 V 00 01 62.5 to 80 Internal PLL lock indicator Internal 4× 3.3 V 01 01 31.25 to 62.5 Internal PLL lock indicator Internal 4× 3.3 V 10 01 15.625 to 31.25 Internal PLL lock indicator Internal 4× 3.3 V 11 01 7.8125 to 15.625 Internal PLL lock indicator Internal 8× 3.3 V 00 10 31.25 to 62.5 Internal PLL lock indicator Internal 8× 3.3 V 01 10 15.625 to 31.25 Internal PLL lock indicator Internal 8× 3.3 V 10 10 7.8125 to 15.625 Internal PLL lock indicator Internal 8× 3.3 V 11 10 3.9062 to 7.8125 Internal PLL lock indicator Internal 16× 3.3 V 00 11 15.625 to 31.25 Internal PLL lock indicator Internal 16× 3.3 V 01 11 7.8125 to 15.625 Internal PLL lock indicator Internal 16× 3.3 V 10 11 3.9062 to 7.8125 Internal PLL lock indicator Internal 16× 3.3 V 11 11 1.9531 to 3.9062 Internal PLL lock indicator Non-Harmonic Clock-Related Spurious Signals In interpolating DACs, imperfect isolation between the digital and DAC clock circuits generates spurious signals at frequencies related to the DAC clock rate. The digital interpolation filters in these DACs run at sub-harmonic frequencies of the output rate clock, where these frequencies are fDAC/2N, N = 1–4. For example, for 2× interpolation there is only one interpolation filter running at fDAC/2; for 4× interpolation, on the other hand, there are two interpolation filters running at fDAC/2 and fDAC/4. These lower-speed clocks for the interpolation filter mix with the DAC clock circuit and create spurious images of the wanted signal and second Nyquist-zone image at offsets of fDAC/2N. The location of these spurious signals is determined by whether the DAC5686 output is used as a complex signal to be feed to an analog quadrature modulator or as a real IF signal. Figure 28(a) shows the location of the largest spurious signals for fDAC = 500 MSPS and 4× interpolation for a complex output signal. At the output of the analog quadrature modulator, the spurious signals with negative frequencies appear on the opposite sideband from the wanted signal. The closest spurious signal results from the wanted signal mixing with the fDAC/4 interpolation-filter clock, which in this example is 125 MHz from the wanted signal for all IF frequencies. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 27 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Figure 28(b) shows the location of the largest spurious signals for fDAC = 500 MSPS and 4× interpolation for a real output signal. With a real output signal, there is no distinction between negative and positive frequencies, and therefore the signals that appear at negative frequencies with a complex signal potentially fall near the wanted signal. In particular, at IFs near fDAC/8, fDAC/4, and fDAC × 3/4 (62.5 MHz, 125 MHz and 187.5 MHz in this example) the mixing effect results in spurious signals falling near the wanted signal, which may present a problem depending on the system application. For a frequency-symmetric signal (such as a single WCDMA or CDMA carrier), operating at exactly fDAC/8, fDAC/4 and fDAC × 3/4, the spurious signal falls completely inside the wanted signal, which produces a clean spectrum but may result in degradation of the signal quality. (a) 250 IF + fDAC/4 200 (b) 250 IF fimage − MHz fimage − MHz 150 IF 100 50 IF − fDAC/4 0 −50 −100 IF − fDAC/2 −150 −200 IF − fDAC y 3/4 −250 0 25 50 75 100 125 150 175 200 225 250 fO − Output Frequency − MHz G018 200 IF − fDAC y 3/4 150 IF + fDAC/4 100 IF − fDAC/4 50 IF − fDAC/2 0 0 25 50 75 100 125 150 175 200 225 250 fO − Output Frequency − MHz G019 Figure 28. Spurious Frequency vs IF The offset between wanted and spurious signals is maximized at low IFs (< fDAC/8) and at fDAC × 3/16, fDAC × 5/16 and fDAC × 7/16. For example, with fDATA = 122.88 MSPS and 4× interpolation, operating with IF = fDAC × 5/16 = 153.6 MHz results in spurious signals at offsets of 60 MHz from the wanted signal. Figure 29(a) shows the amplitude of each spurious signal as a function of IF in external-clock mode (CLK2 input). The dominant spurious signal is IF – fDAC/2. The amplitudes of the IF + fDAC/4 and IF – fDAC/4 are the next-highest spurious signals and are approximately at the same amplitude. Finally, at IF frequencies greater than 100 MHz, small spurious signals at IF fDAC/8 and IF – fDAC × 3/4 are measurable. Figure 29(b) shows the amplitude of each spurious signal as a function of IF in PLL clock mode (CLK1 input). Generating the DAC clock with the onboard PLL/VCO increases the IF – fDAC/2 by 10 dB and the amplitude of the IF fDAC/4 and IF – fDAC × 3/4 by 25 dB compared to the external-clock mode. The IF fDAC/8 spurs are the same as in the external-clock mode. 28 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 (a) 0 (b) 0 −10 −10 Amplitude − dBc Amplitude − dBc −20 −30 IF − fDAC/2 −40 IF ± fDAC/4 −50 IF − fDAC y 3/4 IF ± fDAC/8 −60 −20 −30 IF − fDAC/2 IF ± fDAC/4 −40 −50 IF − fDAC y 3/4 −60 IF ± fDAC/8 −70 0 25 50 75 100 125 150 fO − Output Frequency − MHz 175 G020 −70 0 25 50 75 100 125 150 fO − Output Frequency − MHz 175 G021 Figure 29. Typical Amplitude of Clock-Related Spurious Signals in (a) External-Clock Mode and (b) PLL Mode The amplitudes in Figure 29 are typical values and will vary by a few dB across different parts, supply voltages, and temperatures. Figure 28 and Figure 29 can be used to estimate the non-harmonic clock-related harmonic signals. Take the example for using the DAC5686 in external-clock mode, fDAC = 500 MHz, 4× interpolation, and IF = 85 MHz with a real output. Figure 28(b) and Figure 29(a) predict the spurious signals shown in Table 4. Table 4. Predicted Frequency and Amplitude for fDAC – 500 MHz, 4× Interpolation, IF = 85 MHz in External-Clock Mode Spurious Signal IF – fDAC/2 IF + fDAC/4 IF – fDAC/4 IF – fDAC × 3/4 Frequency (MHz) 165 210 40 > 250 Amplitude (dBc) –47 –64 –64 N/A Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 29 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Figure 30 shows the DAC5686 output spectrum for the preceding example. The amplitudes of the clock-related spurs agree quite well with the predicted amplitudes in Table 4. 0 −10 −20 Amplitude − dBc −30 IF − fDAC/2 −40 −50 IF − fDAC/4 −60 IF + fDAC/4 −70 −80 0 25 50 75 100 125 150 175 200 225 250 f − Frequency − MHz G022 Figure 30. DAC5686 Output Spectrum With fDAC = 500 MSPS, 4× Interpolation, IF = 85 MHz, and External-Clock Mode Dual-Bus Mode In dual-bus mode, two separate parallel data streams (I and Q) are input to the DAC5686 on data bus DA and data bus DB. Dual-bus mode is selected by setting INTERL to 0 in the config_msb register. Figure 31 shows the DAC5686 data path in dual-bus mode. The dual-bus mode timing diagram is shown in Figure 32 for the PLL clock mode and in Figure 33 for the external clock mode. fDATA 2y–16y fDATA DEMUX DA[15:0] FIR1 2fDATA y2 • •• 16-Bit DAC IOUTA1 IOUTA2 DB[15:0] Edge Triggered Input Latches 2fDATA • •• y2 16-Bit DAC IOUTB1 IOUTB2 Figure 31. Dual-Bus Mode Data Path B0025-01 30 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 CLK1 ts(DATA) th(DATA) DA[15:0] A0 A1 A2 A3 AN AN+1 DB[15:0] B0 B1 B2 B3 BN Figure 32. Dual-Bus Mode Timing Diagram (PLL Mode) BN+1 T0039-01 PLLLOCK CLK2 td(PLLLOCK) ts(DATA) th(DATA) DA[15:0] A0 A1 A2 A3 AN AN+1 DB[15:0] B0 B1 B2 B3 BN BN+1 Figure 33. Dual-Bus Mode Timing Diagram (External Clock Mode) T0040-01 Interleave Bus Mode In interleave bus mode, one parallel data stream with interleaved data (I and Q) is input to the DAC5686 on data bus DA. Interleave bus mode is selected by setting INTERL to 1 in the config_msb register. Figure 34 shows the DAC5686 data path in interleave bus mode. The interleave bus mode timing diagram is shown in Figure 35. DEMUX fDATA 2y–16y fDATA FIR1 2fDATA y2 • •• 16-Bit DAC IOUTA1 IOUTA2 DA[15:0] Edge Triggered Input Latches 2fDATA y2 • •• 16-Bit DAC IOUTB1 IOUTB2 Figure 34. Interleave Bus Mode Data Path B0025-02 Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 31 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com TXENABLE ts(TXENABLE) CLK1 or PLLLOCK ts(DATA) th(DATA) DA[15:0] A0 B0 A1 B1 AN BN Figure 35. Interleave Bus Mode Timing Diagram Using TxENABLE T0041-01 Interleaved user data on data bus DA is alternately multiplexed to internal data channels A and B. Data channels A and B can be synchronized using either the QFLAG pin or the TxENABLE pin. When qflag in register config_usb is 0, transitions on TxENABLE identify the interleaved data sequence. The first data after the rising edge of TxENABLE is latched with the rising edge of CLK as channel-A data. Data is then alternately distributed to B and A channels with successive rising edges of CLK. When qflag is 1, the QFLAG pin is used as an input by the user to identify the interleaved data sequence. QFLAG high identifies data as channel B (see Figure 36). QFLAG CLK1 or PLLLOCK DA[15:0] ts(DATA) th(DATA) A0 B0 A1 B1 AN BN Figure 36. Interleave Bus Mode Timing Diagram Using QFLAG T0001-01 When using interleaved input mode with the PLL enabled, the input clock CLK1 is at 2× the frequency of the input to FIR1. The divider that generates the clock for the FIR1 input cannot be synchronized between multiple DAC5686s, which can result in a one-CLK1-period output time difference between devices that have synchronized input data. Dual-clock mode is recommended in applications where multiple DAC5686s must be synchronized in interleaved input mode. The dual-clock mode is selected by setting dualclk high in the config_usb register. In this mode, the DAC5686 uses both clock inputs; CLK1/CLK1C is the input data clock, and CLK2/CLK2C is the external clock. The edges of the two input clocks must be phase-aligned within 500 ps to function properly. Clock Synchronization Using the PHSTR Pin in External Clock Mode In external clock mode, the DAC5686 is clocked at the DAC output sample frequency (CLK2 and CLK2C). For an interpolation rate N, there are N possible phases for the DAC input clock on the PLLLOCK pin (see Figure 37 for N = 4). 32 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 CLK2 CLK2C PLLLOCK Figure 37. Four Possible PLLLOCK Phases for N = 4 in External Clock Mode T0003-01 To synchronize PLLLOCK input clocks across multiple DAC5686 chips, a synchronization signal on the PHSTR pin is used. During configuration of the DAC5686 chips, address sync_phstr in config_msb is set high to enable the PHSTR input pin as a synchronization input to the clock dividers generating the input clock. A simultaneous low-to-high transition on the PHSTR pin for each DAC5686 then forces the input clock on PLLLOCK to start in phase on each DAC. See Figure 38. 1/fPLLLOCK = N/fCLK2 CLK2 CLK2C PHSTR th(PHSTR) ts(PHSTR) PLLLOCK td(CLK) DAC1 DA[15:0] DB[15:0] th ts T0004−01 Figure 38. Using PHSTR to Synchronize PLLLOCK Input Clock for Multiple DACs in External Clock Mode Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 33 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com The PHSTR transition has a setup and hold time relative to the DAC output sample clock (ts_PHSTR and th_PHSTR) equal to 50% of the DAC output sample clock period up to a maximum of 1 ns. At 500 MHz, the setup and hold times are therefore 0.5 ns. The PHSTR signal can remain high after synchronization, or can return low. A new low-to-high transition resynchronizes the input clock. Note that the PHSTR transition also resets the NCO accumulator. Digital Filters Figure 39 through Figure 42 show magnitude spectrum responses for 2×, 4×, 8×, and 16× FIR interpolation filtering. The transition band is from 0.4 to 0.6 fDATA with < 0.002-dB pass-band ripple and > 80-dB stop-band attenuation for all four configurations. The filters are linear phase. The sel field in register config_lsb selects the interpolation filtering rate as 2×, 4×, 8×, or 16×; interpolation filtering can be completely bypassed by setting fullbypass in register config_lsb. Figure 43 shows the spectral correction of the DAC sinx/x rolloff achieved with use of inverse sinc filtering. Pass-band ripple from 0 to 0.4 fDATA is < 0.03 dB. Inverse sinc filtering is enabled by sinc in register config_msb. Magnitude – dB Magnitude – dB MAGNITUDE vs FREQUENCY 20 0 −20 −40 −60 −80 −100 −120 −140 −160 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 f/fDATA G023 Figure 39. Magnitude Spectrum for 2× Interpolation (dB) MAGNITUDE vs FREQUENCY 20 0 −20 −40 −60 −80 −100 −120 −140 −160 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 f/fDATA G024 Figure 40. Magnitude Spectrum for 4× Interpolation (dB) 34 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 Magnitude – dB Magnitude – dB MAGNITUDE vs FREQUENCY 20 MAGNITUDE vs FREQUENCY 20 0 0 −20 −20 −40 −40 −60 −60 −80 −80 −100 −100 −120 −120 −140 −140 −160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 f/fDATA Figure 41. Magnitude Spectrum for 8× Interpolation (dB) 4.0 G025 −160 0 1234567 f/fDATA Figure 42. Magnitude Spectrum for 16× Interpolation (dB) Magnitude – dB MAGNITUDE vs FREQUENCY 5 4 3 FIR 2 1 Corrected 0 −1 −2 Rolloff −3 −4 −5 0.0 0.1 0.2 0.3 0.4 0.5 f/fDAC G027 Figure 43. Magnitude Spectrum for Inverse sinc Filtering 8 G026 Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 35 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com The filter taps for interpolation filters FIR1–FIR4 and inverse sinc filter FIR5 are listed in Table 5. FIR1 8 0 –24 0 58 0 –120 0 221 0 –380 0 619 0 -971 0 1490 0 –2288 0 3649 0 –6628 0 20750 32768 20750 0 –6628 0 3649 0 –2288 0 1490 0 –971 0 619 0 –380 0 221 0 –120 Table 5. Filter Taps for FIR1–FIR5 FIR2 9 0 –58 0 214 0 –638 0 2521 4096 2521 0 –638 0 214 0 –58 0 9 FIR3 31 0 –219 0 1212 2048 1212 0 –219 0 31 FIR4 -33 0 289 512 289 0 –33 FIR5 (INVSINC) 1 –3 9 –34 400 –34 9 –3 1 36 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 Table 5. Filter Taps for FIR1–FIR5 (continued) FIR1 0 58 0 –24 0 8 FIR2 FIR3 FIR4 FIR5 (INVSINC) NCO The DAC5686 uses a numerically controlled oscillator (NCO) with a 32-bit frequency register and a 16-bit phase register. The NCO is used in quadrature-modulation and single-sideband modes to provide sin and cos for mixing. The NCO tuning frequency is programmed in registers 0x1 through 0x4. Phase offset is programmed in registers 0x5 and 0x6. A block diagram of the NCO is shown in Figure 44. 32 32 Frequency Register 32 Accumulator 32 16 16 Σ Σ Look-Up Table CLK RESET fDAC PHSTR 16 Phase Register 16 sin 16 cos Figure 44. Block Diagram of the NCO B0026-01 The NCO accumulator is reset to zero when the PHSTR pin is high and remains at zero until PHSTR is set low. Frequency word freq in the frequency register is added to the accumulator every clock cycle. The output frequency of the NCO is: fNCO + freq fDAC 232 While the maximum clock frequency of the DACs is 500 MSPS, the maximum clock frequency the NCO can operate at is 320 MHz; mixing at DAC rates higher than 320 MSPS requires using the fDAC/4 mixing option. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 37 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Register Bit Allocation Map NAME chip_ver freq_lsb freq_lmidsb freq_umidsb freq_msb phase_lsb phase_msb config_lsb config_msb config_usb daca_offset_lsb daca_gain_lsb daca_offset_gain_ msb dacb_offset_lsb dacb_gain_lsb dacb_offset_gain_ msb R/W ADDRE SS R/W 0x00 R/W 0x01 R/W 0x02 R/W 0x03 R/W 0x04 R/W 0x05 R/W 0x06 R/W 0x07 R/W 0x08 R/W 0x09 R/W 0x0A R/W 0x0B R/W 0x0C BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 atest[4:0] version[2:0] read only freq_int[7:0] freq_int[15:8] freq_int[23:16] freq_int[31:24] phase_int[7:0] phase_int[15:8] mode[1:0] div[1:0] sel[1:0] counter full_ bypass ssb interl sinc dith sync_phstr nco sif4 twos dual_clk DDS_gain[1:0] rspect qflag PLL_rng[1:0] rev_bbus daca_offset[7:0] daca_gain[7:0] daca_offset[10:8] sleepa daca_gain[11:8] R/W 0x0D R/W 0x0E R/W 0x0F dacb_offset[10:8] dacb_offset[7:0] dacb_gain[7:0] sleepb dacb_gain[11:8] REGISTER DESCRIPTIONS Register Name: chip_ver MSB LSB atest[4:0] chip_ver[2:0] read only 0 0 0 0 0 1 0 1 chip_ver[3:0]: chip_ver [3:0] stores the device version, initially 0x5. The user can find out which version of the DAC5686 is in the system by reading this byte. a_test[4:0]: must be 0 for proper operation. Register Name: freq_lsb MSB LSB freq_int[7:0] 0 0 0 0 0 0 0 0 freq_int[7:0]: The lower 8 bits of the frequency register in the DDS block Register Name: freq_lmidsb MSB freq_int[15:8] 0 0 0 0 0 0 LSB 0 0 freq_int[15:8]: The lower mid 8 bits of the frequency register in the DDS block Register Name: freq_umidsb MSB freq_int[23:16] 0 0 0 0 0 0 LSB 0 0 38 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 freq_int[23:16]: The upper mid 8 bits of the frequency register in the DDS block Register Name: freq_msb MSB LSB freq_int[31:24] 0 0 1 0 0 0 0 0 freq_int[31:24]: The most significant 8 bits of the frequency register in the DDS block Register Name: phase_lsb MSB LSB phase_int[7:0] 0 0 0 0 0 0 0 0 phase_int[7:0]: The lower 8 bits of the phase register in the DDS block Register Name: phase_msb MSB phase_int[15:8] 0 0 0 0 0 0 LSB 0 0 phase_int[15:8]: The most significant 8 bits of the phase register in the DDS block Register Name: config_lsb MSB mode[1:0] 0 0 div[1:0] 0 0 sel[1:0] 0 0 counter 0 LSB Full_bypass 1 mode[1:0]: Controls the mode of the DAC5686; summarized in Table 6. Table 6. DAC5686 Modes mode[1:0] 00 01 10 11 DAC5686 MODE Dual-DAC Single-sideband Quadrature Dual-DAC div[1:0]: Controls the PLL divider value; summarized in Table 7. Table 7. PLL Divide Ratios div[1:0] 00 01 10 11 PLL DIVIDE RATIO 1× divider 2× divider 4× divider 8× divider Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 39 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com sel[1:0]: Controls the selection of interpolating filters used; summarized in Table 8. Table 8. DAC5686 Filter Configuration sel[1:0] 00 01 10 11 INTERP. FIR SETTING ×2 ×4 ×8 ×16 counter: When asserted, the DAC5686 goes into counter mode and uses an internal counter as a ramp input to the DAC. The count range is determined by the A-side input data DA[2:0], as summarized in Table 9. Table 9. DAC5686 Counter Mode Count Range DA[2:0] 000 001 010 100 COUNT RANGE All bits D[15:0] Lower 7 bits D[6:0] Mid 4 bits D[10:7] Upper 5 bits D[15:11] full_bypass: When asserted, the interpolation filters and mixer logic are bypassed, and the data inputs DA[15:0] and DB[15:0] go straight to the DAC inputs. Register Name: config_msb MSB ssb interl sinc 0 0 0 dith sync_phstr nco 0 0 0 LSB sif4 twos 0 0 ssb: In single-sideband mode, assertion inverts the B data; in quadrature modulation mode, assertion routes the A data path to DACB instead of the B data path. interl: When asserted, data input to the DAC5686 on channel DA[15:0] is interpreted as a single interleaved stream (I/Q); channel DB[15:0] is unused. sinc: Assertion enables the INVSINC filter. dith: Assertion enables dithering in the PLL. sync_phstr: Assertion enables the PHSTR input as a sync input to the clock dividers in external single-clock mode. nco: Assertion enables the NCO. sif4: When asserted, the sif interface becomes a 4-pin interface instead of a 3-pin interface. The SDIO pin becomes an input only, and the SDO is the output. twos: When asserted, the chip interprets the input data as 2s complement form instead of binary offset. Register Name: config_usb MSB dualclk 0 DDS_gain[1:0] 0 0 rspect 0 qflag 0 pll_rng[1:0] 0 0 LSB rev_bbus 0 dual_clk: When asserted, the DAC5686 uses both clock inputs; CLK1/CLK1C is the input data clock and CLK2/CLK2C is the DAC output clock. These two clocks must be phase-aligned within 500 ps to function properly. When deasserted, CLK2/CLK2C is the DAC output clock and is divided down to generate the input data clock, which is output on PLLLOCK. Dual clock mode is only available when PLLVDD = 0. DDS_gain[1:0]: Controls the gain of the DDS so that the overall gain of the DDS is unity. It is important to 40 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 ensure that max(abs(cos(ωt) + sin(ωt))) < 1. At different frequencies, the summation produces different maximum outputs and must be reduced. The simplest is fDAC/4 mode where the maximum is 1 and the gain multiply should be 1 to maintain unity. However, due to the fact that the digital logic does a divide-by-two in this summation, the gain necessary to achieve unity must be double (DDS_gain[1:0] = 01). Table 10 shows the digital gain necessary and the actual signal gain needed to make the above equation have a maximum value of 1. DDS_gain [1:0] 00 01 10 11 Table 10. Digital Gain for DDS DIGITAL GAIN 1.40625 2 1.59375 1.40625 SIGNAL GAIN FOR UNITY 0.703125 1 0.7936 0.703125 rspect: When asserted, the sin term is negated before being used in mixing. This gives the reverse spectrum in single-sideband mode. qflag: When asserted, the QFLAG pin is used by the user as an input indicator during interleaved data input mode to identify the Q sample. When deasserted, the TxENABLE pin transition is used to start an internal toggling signal, which is used to interpret the interleaved data sequence; the first sample clocked into the DAC5686 after TxENABLE goes high is routed through the A data path. PLL_rng[1:0]: Increases the PLL VCO VtoI current, summarized in Table 11. See Figure 17 for the effect on VCO gain and range. Table 11. PLL VCO Vtol Current Increase PLL_rng[1:0] 00 01 10 11 VtoI CURRENT INCREASE nominal 15% 30% 45% rev_bbus[1:0]: When asserted, pin 92 changes from DB15 to DB0, pin 91 changes from DB14 to DB1, etc., reversing the order of the DB[15:0] pins. Register Name: daca_offset_lsb (2s complement) MSB LSB daca_offset[7:0] 0 0 0 0 0 0 0 0 daca_offset[7:0]: The lower 8 bits of the DACA offset Register Name: daca_gain_lsb (2s complement) MSB LSB daca_gain[7:0] 0 0 0 0 0 0 0 0 daca_gain[7:0]: The lower 8 bits of the DACA gain control register. These lower 8 bits are for fine gain control. This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4% range. Register Name: daca_offset_gain_msb (2s complement) MSB daca_offset[10:8] sleepa 0 0 0 0 0 LSB daca_gain[11:8] 0 0 0 daca_offset[10:8]: The upper 3 bits of the DACA _offset Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 41 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com sleepa: When asserted, DACA is put into the sleep mode. daca_gain[11:8]: Coarse gain control for DACA; the full-scale output current is: ƪ Ifullscale + 16ǒVextioǓ Rbiasj ǒ Ǔƫ (GAINCODE 16 ) 1) B 1 * FINEGAIN 3072 where GAINCODE is the decimal equivalent of daca_gain [11:8] {0…15} and the FINEGAIN is daca_gain [7:0] as 2s complement {–127…128}. Register Name: dacb_offset_lsb (2s complement) MSB LSB dacb_offset[7:0] 0 0 0 0 0 0 0 0 dacb_offset[7:0]: The lower 8 bits of the DACB offset Register Name: dacb_gain_lsb (2s complement) MSB LSB dacb_gain[7:0] 0 0 0 0 0 0 0 0 dacb_gain[7:0]: The lower 8 bits of the DACB gain control register. These lower 8 bits are for fine gain control. This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4% range. Register Name: dacb_offset_gain_msb (2s complement) MSB dacb_offset[10:8] sleepb 0 0 0 0 0 LSB dacb_gain[11:8] 0 0 0 dacb_offset[10:8]: The upper 3 bits of the DACA _offset sleepb: When asserted, DACB is put into the sleep mode. dacb_gain[11:8]: Coarse gain control for DACB; the full-scale output current is: ƪ Ifullscale + 16ǒVextioǓ Rbiasj ǒ Ǔƫ (GAINCODE 16 ) 1) B 1 * FINEGAIN 3072 where GAINCODE is the decimal equivalent of dacb_gain [11:8] {0…15} and the FINEGAIN is dacb_gain [1:0] as 2s complement {–127…128}. DIGITAL INPUTS Figure 45 shows a schematic of the equivalent CMOS digital inputs of the DAC5686. DA[15:0], DB[15:0], SLEEP, PHSTR, TxENABLE, QFLAG, SDIO, SCLK, and SDENB have pulldown resistors and RESETB has a pullup resistor internal to the DAC5686. The pullup and pulldown circuitry is approximately equivalent to 100 kΩ. See the specification table for logic thresholds. 42 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 DA[15:0] DB[15:0] SLEEP PHSTR TXENABLE QFLAG SDIO SCLK SDENB IOVDD 400 W 100 kW Internal Digital In 100 kW RESETB IOVDD 400 W Internal Digital In IOGND Figure 45. CMOS/TTL Digital Equivalent Input IOGND S0027–02 CLOCK INPUT AND TIMING Figure 46 shows an equivalent circuit for the clock input. CLKVDD CLKVDD CLKVDD CLK R1 10 kΩ Internal Digital In R1 10 kΩ R2 10 kΩ R2 10 kΩ CLKC CLKGND Figure 46. Clock Input Equivalent Circuit S0028-01 Figure 47, Figure 48, and Figure 49 show various input configurations for driving the differential clock input (CLK/CLKC). Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 43 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Optional, May Be Bypassed for Sine Wave Input Swing Limitation CAC 0.1 µF 1:4 RT 200 Ω CLK CLKC Termination Resistor S0029-01 Figure 47. Preferred Clock Input Configuration TTL/CMOS Source Ropt 22 Ω CAC 0.01 µF 1:1 Optional, Reduces Clock Feedthrough CLK CLKC TTL/CMOS Source Ropt 22 Ω 0.01 µF CLK CLKC Node CLKC Internally Biased to CLKVDDń2 S0030-01 Figure 48. Driving the DAC5686 With a Single-Ended TTL/CMOS Clock Source Differential + ECL or (LV)PECL Source – RT 130 Ω RT 130 Ω RT 82.5 Ω RT 82.5 Ω CAC 0.1 µF CAC 0.1 µF 100 Ω CLK CLKC VTT S0031-01 Figure 49. Driving the DAC5686 With a Differential ECL/PECL Clock Source 44 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 DAC Transfer Function The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output current up to 20 mA. Differential current switches direct the current of each current source through either one of the complementary output nodes IOUT1 or IOUT2. Complementary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of two. The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage reference source (1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to provide a full-scale output current equal to 16 times IBIAS. The full-scale current IOUTFS can be adjusted from 20 mA down to 2 mA. The relation between IOUT1 and IOUT2 can be expressed as: IOUT1 = –IOUTFS – IOUT2 We denote current flowing into a node as – current and current flowing out of a node as + current. Because the output stage is a current sink, the current can only flow from AVDD into the IOUT1 and IOUT2 pins. If IOUT2 = –5 mA and IO(FS) = 20 mA then: IOUT1 = –20 – (–5) = –15 mA The output current flow in each pin driving a resistive load can be expressed as: IOUT1 = IOUTFS × (65535 – CODE) / 65536 IOUT2 = IOUTFS × CODE / 65536 where CODE is the decimal representation of the DAC data input word. For the case where IOUT1 and IOUT2 drive resistor loads RL directly, this translates into single ended voltages at IOUT1 and IOUT2: VOUT1 = AVDD – I IOUT1 I × RL VOUT2 = AVDD – I IOUT2 I × RL Assuming that the data is full scale (65535 in offset binary notation) and the RL is 25 Ω, the differential voltage between pins IOUT1 and IOUT2 can be expressed as: VOUT1 = AVDD – I -20 mA I x 25 Ω = 2.8 V VOUT2 = AVDD – I -0 mA I x 25 Ω = 3.3 V VDIFF = VOUT1 – VOUT2 = 0.5 V Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would lead to increased signal distortion. Reference Operation The DAC5686 comprises a band-gap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS is defined by the on-chip band-gap reference voltage and control amplifier. The full-scale output current equals 16 times this bias current. The full-scale output current IOUTFS can thus be expressed as (coarse gain = 15, fine gain = 0): IOUTFS + 16 VEXTIO RBIAS where VEXTIO is the voltage at terminal EXTIO. The band-gap reference voltage delivers an accurate voltage of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The band-gap reference additionally can be used for external reference operation. In that case, an external buffer with a high-impedance input should be used in order to limit the band-gap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may hence be omitted. Terminal EXTIO serves as either input or output node. The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing the externally applied reference voltage. The internal control amplifier has a wide input range supporting the full-scale output current range of 20 dB. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 45 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Analog Current Outputs Figure 50 shows a simplified schematic of the current source array with corresponding switches. Differential switches direct the current of each individual NMOS current source to either the positive output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of the current sources and differential switches and is typically >300 kΩ in parallel with an output capacitance of 5 pF. The external output resistors are terminated to AVDD. The maximum output compliance at nodes IOUT1 and IOUT2 is limited to AVDD + 0.5 V, determined by the CMOS process. Beyond this value, transistor breakdown can occur, resulting in reduced reliability of the DAC5686 device. The minimum output compliance voltage at nodes IOUT1 and IOUT2 equals AVDD – 0.5 V. Exceeding the minimum output compliance voltage adversely affects distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V. AVDD RLOAD IOUT1 RLOAD IOUT2 S(1) S(1)C S(2) S(2)C S(N) S(N)C Figure 50. Equivalent Analog Current Output S0032-01 The DAC5686 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF transformer. Figure 51 and Figure 52 show the 50-Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratios, respectively. Note that the center tap of the primary input of the transformer must be connected to AVDD to enable a dc current flow. Applying a 20-mA full-scale output current would lead to a 0.5-Vpp output for a 1:1 transformer and a 1-Vpp output for a 4:1 transformer. 46 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 AVDD (3.3 V) 50 Ω IOUT1 1:1 100 Ω IOUT2 RLOAD 50 Ω 50 Ω AVDD (3.3 V) S0033-01 Figure 51. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance-Ratio Transformer AVDD (3.3 V) 100 Ω IOUT1 4:1 IOUT2 RLOAD 50 Ω 100 Ω AVDD (3.3 V) S0033-02 Figure 52. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance-Ratio Transformer SLEEP MODE The DAC5686 features a power-down mode that turns off the output current and reduces the supply current to less than 5 mA over the supply range of 3 V to 3.6 V and temperature range of –40C to 85C. The power-down mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to IOVDD). An internal pulldown circuit at node SLEEP ensures that the DAC5686 is enabled if the input is left disconnected. Power-up and power-down activation times depend on the value of the external capacitor at node SLEEP. For a nominal capacitor value of 0.1 mF, it takes less than 5 ms to power down and approximately 3 ms to power up. POWER-UP SEQUENCE In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or simultaneously with PLLVDD. AVDD, CLKVDD and IOVDD can be powered simultaneously or in any order. Within AVDD, the multiple AVDD pins should be powered simultaneously. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 47 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com DAC5686 EVALUATION BOARD There is a combination EVM board for the DAC5686 digital-to-analog converter for evaluation. This board allows the user the flexibility to operate the DAC5686 in various configurations. Possible output configurations include transformer-coupled, resistor-terminated, inverting/non-inverting and differential amplifier outputs. The digital inputs are designed to be driven directly from various pattern generators with the onboard option to add a resistor network for proper load termination. APPENDIX A. PLL LOOP FILTER COMPONENTS DESIGNING THE PLL LOOP FILTER The DAC5686 contains an external loop filter to set the bandwidth and phase margin of the PLL. For the external second-order filter shown in Figure 53, the components R1, C1, and C2 are set by the user to optimize the PLL for the application. The resistance R3 = 200 Ω and the capacitance C3 = 8 pF are internal to the DAC5686. Note that the positions of R1 and C1 can be reversed, relative to each other. External Internal R3 C1 C2 C3 R1 S0006-01 Figure 53. DAC5686 Loop Filter The typical VCO gain (Gvco) (the slope of VCO frequency vs voltage) as a function of VCO frequency for the DAC5686 is shown in Figure 17. The VCO frequency range can be extended to higher frequencies by setting the pll_rng[1:0] registers to increase the VCO Vtol current (see Table 11). However, only the range for PLL_rng = 00 (nominal) is specified. For the lowest possible phase noise, the VCO frequency should be chosen so Gvco is minimized, where fvco = fdata × Interpolation × PLL Divider For example, if fdata = 125 MSPS and 2× interpolation is used, the PLL divider should be set to 2 to lock the VCO at 500 MHz for a typical Gvco of 200 MHz/V. The external loop filter components C1, C2, and R1 are determined by choosing Gvco, N = fvco/fdata, the loop phase margin φd, and the loop bandwidth ωd. Except for applications where abrupt clock frequency changes require a fast PLL lock time, it is suggested that φd be set to at least 80 degrees for stable locking and suppression of the phase-noise side lobes. Phase margins of 60 degrees or less occasionally have been sensitive to board layout and decoupling details. The optimum loop bandwidth ωd depends on both the VCO phase noise, which is largely a function of Gvco, and the application. For the example above with Gvco = 200 MHz/V, an ωd = 1 MHz would be typical, but lower or higher loop bandwidths may provide better phase noise characteristics. For a higher Gvco, for example Gvco = 400 MHz/V, an ωd ~ 7 MHz would be typical. However, it is suggested that customers experiment with varying the loop bandwidth at least from × to 2× to verify the optimum setting. 48 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated DAC5686 www.ti.com ............................................................................................................................................................ SLWS147F – APRIL 2003 – REVISED JUNE 2009 C1, C2, and R1 are then calculated by the following equations: ǒ Ǔ C1 + t1 1 * t2 t3 C2 = t1´ t2 t3 R1 + t32 t1(t3 * t2) where t1 + KdKVCO w 2 d (tan fd ) sec f d) t2 + wd(tan 1 fd ) sec fd) t3 + tan f d ) wd sec f d and Charge pump current: VCO gain: fvco/fdata: Phase detector gain: iqp = 1 mA KVCO = 2π × GVCO rad/A N = {2, 4, 8, 16, 32} Kd = iqp × (2πN)–1 A/rad An Excel™ spreadsheet is available on the TI Web site at http://www-s.ti.com/sc/psheets/scac057/scac057.zip for automatically calculating the values for C1, C2, and R1. Completing the preceding example with PARAMETER Gvco ωd N φd the component values are VALUE 2.00E+02 1.00E+00 4 80 UNIT MHz/V MHz C1 (F) 1.44E–08 C2 (F) 1.11E–10 R1 (Ω) 1.27E+02 Because the PLL characteristics are not sensitive to these components, the closest 20%-tolerance capacitor and 1%-tolerance resistor values can be used. If the calculation results in a negative value for C2 or an unrealistically large value for C1, then the phase margin must be reduced slightly. Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5686 Submit Documentation Feedback 49 DAC5686 SLWS147F – APRIL 2003 – REVISED JUNE 2009 ............................................................................................................................................................ www.ti.com Revision History Changes from Revision E (June 2006) to Revision F ..................................................................................................... Page • Changed DA[15:0] pin description ......................................................................................................................................... 5 • Changed DB[15:0] pin description ......................................................................................................................................... 5 • Changed PHSTR pin descripton............................................................................................................................................ 5 • Changed QFLAG pin description ........................................................................................................................................... 5 • Changed RESETB pin description......................................................................................................................................... 5 • Changed SCLK pin description.............................................................................................................................................. 5 • Changed SDENB pin description........................................................................................................................................... 5 • Changed SDIO pin description .............................................................................................................................................. 6 • made changes per input markup ......................................................................................................................................... 18 • Changed terms in Equation 1 .............................................................................................................................................. 18 • Changed signs of inputs and formula for lower DAC in Figure 20 ...................................................................................... 19 • Made corrections to Equation 2 and Equation 3.................................................................................................................. 21 • Added values to resistors in Figure 45 ................................................................................................................................ 43 • Swapped definitions of IOUT1 and IOUT2 in the corresponding equations........................................................................ 45 Changes from Revision D (January 2006) to Revision E ............................................................................................... Page • For QFLAG description, changed O to I and output to input ................................................................................................. 5 • Changed QFLAG description from output to input .............................................................................................................. 32 • New paragraph describing problem with synchronization in PLL clock mode with interleaved input.................................. 32 • Added "by the user as an input indicator" to first sentence of qflag register description .................................................... 41 50 Submit Documentation Feedback Product Folder Link(s): DAC5686 Copyright © 2003–2009, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 6-May-2009 PACKAGING INFORMATION Orderable Device DAC5686IPZP DAC5686IPZPG4 Status (1) ACTIVE ACTIVE Package Type HTQFP Package Drawing PZP HTQFP PZP Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Qty 100 90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) 100 90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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