首页资源分类嵌入式处理器其它 > ili9335 TFT DRIVER IC DATASHEET

ili9335 TFT DRIVER IC DATASHEET

已有 445464个资源

下载专区

上传者其他资源

文档信息举报收藏

标    签:ili9335TFTDRIVERICDATASHEET

分    享:

文档简介

ili9335 TFT DRIVER IC DATASHEET

文档预览

ILI9335 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Datasheet Version: V0.08 Document No.: ILI9335DS_V0.08.pdf ILI TECHNOLOGY CORP. 8F, No.38, Taiyuan St., Jhubei City, Hsinchu County 302, Taiwan, R.O.C Tel.886-3-5600099; Fax.886-3-5600055 http://www.ilitek.com a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Table of Contents Section Page 1. Introduction.................................................................................................................................................... 7 2. Features ........................................................................................................................................................ 8 3. Block Diagram ............................................................................................................................................. 10 4. Pin Descriptions .......................................................................................................................................... 11 5. Pad Arrangement and Coordination............................................................................................................ 15 6. Block Description ........................................................................................................................................ 25 7. System Interface ......................................................................................................................................... 27 7.1. Interface Specifications .................................................................................................................. 27 7.2. Input Interfaces .............................................................................................................................. 28 7.2.1. i80/18-bit System Interface.................................................................................................. 29 7.2.2. i80/16-bit System Interface.................................................................................................. 30 7.2.3. i80/9-bit System Interface.................................................................................................... 31 7.2.4. i80/8-bit System Interface.................................................................................................... 31 7.3. Serial Peripheral Interface (SPI) .................................................................................................... 33 7.4. VSYNC Interface............................................................................................................................ 37 7.5. RGB Input Interface ....................................................................................................................... 41 7.5.1. RGB Interface...................................................................................................................... 42 7.5.2. RGB Interface Timing .......................................................................................................... 43 7.5.3. Moving Picture Mode........................................................................................................... 45 7.5.4. 6-bit RGB Interface.............................................................................................................. 46 7.5.5. 16-bit RGB Interface............................................................................................................ 47 7.5.6. 18-bit RGB Interface............................................................................................................ 47 7.6. Interface Timing.............................................................................................................................. 49 8. Register Descriptions .................................................................................................................................. 51 8.1. Registers Access............................................................................................................................ 51 8.2. Instruction Descriptions.................................................................................................................. 54 8.2.1. Index (IR)............................................................................................................................. 56 8.2.2. ID code (R00h) .................................................................................................................... 56 8.2.3. Driver Output Control (R01h) .............................................................................................. 56 8.2.4. LCD Driving Wave Control (R02h) ...................................................................................... 58 8.2.5. Entry Mode (R03h) .............................................................................................................. 58 8.2.6. 16bits Data Format Selection (R05h) .................................................................................. 61 8.2.7. Display Control 1 (R07h) ..................................................................................................... 62 8.2.8. Display Control 2 (R08h) ..................................................................................................... 63 8.2.9. Display Control 3 (R09h) ..................................................................................................... 64 8.2.10. Display Control 4 (R0Ah)..................................................................................................... 65 8.2.11. RGB Display Interface Control 1 (R0Ch)............................................................................. 65 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 2 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.12. Frame Marker Position (R0Dh) ........................................................................................... 66 8.2.13. RGB Display Interface Control 2 (R0Fh) ............................................................................. 66 8.2.14. Power Control 1 (R10h)....................................................................................................... 67 8.2.15. Power Control 2 (R11h) ....................................................................................................... 68 8.2.16. Power Control 3 (R12h)....................................................................................................... 69 8.2.17. Power Control 4 (R13h)....................................................................................................... 70 8.2.18. GRAM Horizontal/Vertical Address Set (R20h, R21h) ........................................................ 70 8.2.19. Write Data to GRAM (R22h)................................................................................................ 71 8.2.20. Read Data from GRAM (R22h) ........................................................................................... 71 8.2.21. Power Control 7 (R29h)....................................................................................................... 73 8.2.22. Frame Rate and Color Control (R2Bh)................................................................................ 74 8.2.23. Gamma Control (R30h ~ R3Dh).......................................................................................... 74 8.2.24. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) ....................... 75 8.2.25. Gate Scan Control (R60h, R61h, R6Ah) ............................................................................. 77 8.2.26. Partial Image 1 Display Position (R80h).............................................................................. 79 8.2.27. Partial Image 1 RAM Start/End Address (R81h, R82h)....................................................... 79 8.2.28. Partial Image 2 Display Position (R83h).............................................................................. 79 8.2.29. Partial Image 2 RAM Start/End Address (R84h, R85h)....................................................... 79 8.2.30. Panel Interface Control 1 (R90h)......................................................................................... 80 8.2.31. Panel Interface Control 2 (R92h)......................................................................................... 80 8.2.32. Panel Interface Control 4 (R95h)......................................................................................... 80 8.2.33. Panel Interface Control 5 (R97h)......................................................................................... 81 8.2.34. OTP VCM Programming Control (RA1h) ............................................................................ 81 8.2.35. OTP VCM Status and Enable (RA2h) ................................................................................. 81 8.2.36. OTP Programming ID Key (RA5h) ...................................................................................... 82 8.2.37. Deep stand by control (RE6h) ............................................................................................. 82 9. OTP Programming Flow.............................................................................................................................. 84 10. GRAM Address Map & Read/Write ............................................................................................................. 85 11. Window Address Function........................................................................................................................... 90 12. Gamma Correction...................................................................................................................................... 91 13. Application................................................................................................................................................... 99 13.1. Configuration of Power Supply Circuit ........................................................................................... 99 13.2. Display ON/OFF Sequence ......................................................................................................... 101 13.3. Standby and Sleep Mode ............................................................................................................. 102 13.4. Power Supply Configuration ........................................................................................................ 103 13.5. Voltage Generation ...................................................................................................................... 104 13.6. Applied Voltage to the TFT panel................................................................................................. 105 13.7. Partial Display Function ............................................................................................................... 105 14. Electrical Characteristics........................................................................................................................... 107 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 3 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 14.1. Absolute Maximum Ratings ......................................................................................................... 107 14.2. DC Characteristics ....................................................................................................................... 108 14.3. Reset Timing Characteristics ....................................................................................................... 108 14.4. AC Characteristics ....................................................................................................................... 109 14.4.1. i80-System Interface Timing Characteristics ..................................................................... 109 14.4.2. Serial Data Transfer Interface Timing Characteristics....................................................... 110 14.4.3. RGB Interface Timing Characteristics ............................................................................... 110 15. Revision History ........................................................................................................................................ 112 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 4 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Figures FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION .................................................................................... 28 FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 29 FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 30 FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 31 FIGURE5 8-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 32 FIGURE 6 DATA FORMAT OF SPI INTERFACE..................................................................................................................... 34 FIGURE7 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) ............................................................... 35 FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI=”1” AND DFM=”10”).................... 36 FIGURE9 DATA TRANSMISSION THROUGH VSYNC INTERFACE)......................................................................................... 37 FIGURE10 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE ............................................................ 37 FIGURE11 OPERATION THROUGH VSYNC INTERFACE....................................................................................................... 38 FIGURE12 TRANSITION FLOW BETWEEN VSYNC AND INTERNAL CLOCK OPERATION MODES ............................................ 40 FIGURE13 RGB INTERFACE DATA FORMAT ...................................................................................................................... 41 FIGURE14 GRAM ACCESS AREA BY RGB INTERFACE ..................................................................................................... 42 FIGURE15 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE.................................................................. 43 FIGURE16 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE ............................................................................ 44 FIGURE17 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE.................................................................................... 45 FIGURE18 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING ................................................................... 48 FIGURE19 GRAM ACCESS BETWEEN SYSTEM INTERFACE AND RGB INTERFACE .............................................................. 48 FIGURE20 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL ..................................... 50 FIGURE21 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI)...................................................................... 51 FIGURE22 REGISTER SETTING WITH I80 SYSTEM INTERFACE ............................................................................................ 52 FIGURE 23 REGISTER READ/WRITE TIMING OF I80 SYSTEM INTERFACE ........................................................................... 53 FIGURE24 GRAM ACCESS DIRECTION SETTING ............................................................................................................... 58 FIGURE25 16-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................. 59 FIGURE26 8-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................... 60 FIGURE 27 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE.............. 72 FIGURE 28 GRAM DATA READ BACK FLOW CHART ........................................................................................................ 73 FIGURE 29 GRAM ACCESS RANGE CONFIGURATION ........................................................................................................ 76 FIGURE30 GRAM READ/WRITE TIMING OF I80-SYSTEM INTERFACE ............................................................................... 85 FIGURE31 I80-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=”0”, BGR=”0”) ................................................. 87 FIGURE32 I80-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=”0”, BGR=”0”) .............................................................. 88 FIGURE 33 I80-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS=”1”, BGR=”1”) ....................................................... 89 FIGURE 34 GRAM ACCESS WINDOW MAP ....................................................................................................................... 90 FIGURE 35 GRAYSCALE VOLTAGE GENERATION............................................................................................................... 91 FIGURE 36 GRAYSCALE VOLTAGE ADJUSTMENT .............................................................................................................. 92 FIGURE 37 GAMMA CURVE ADJUSTMENT ......................................................................................................................... 93 FIGURE 38 EXAMPLE OF RMP(N)0~5 DEFINITION............................................................................................................. 95 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 5 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 FIGURE 39 RELATIONSHIP BETWEEN SOURCE OUTPUT AND VCOM ................................................................................. 98 FIGURE 40 RELATIONSHIP BETWEEN GRAM DATA AND OUTPUT LEVEL.......................................................................... 98 FIGURE 41 POWER SUPPLY CIRCUIT BLOCK.................................................................................................................... 100 FIGURE 42 DISPLAY ON/OFF REGISTER SETTING SEQUENCE .......................................................................................... 101 FIGURE 43 STANDBY/SLEEP MODE REGISTER SETTING SEQUENCE ........................................................................... 102 FIGURE 44 POWER SUPPLY ON/OFF SEQUENCE ............................................................................................................. 103 FIGURE 45 VOLTAGE CONFIGURATION DIAGRAM ........................................................................................................... 104 FIGURE 46 VOLTAGE OUTPUT TO TFT LCD PANEL ........................................................................................................ 105 FIGURE 47 PARTIAL DISPLAY EXAMPLE.......................................................................................................................... 106 FIGURE 48 I80-SYSTEM BUS TIMING ............................................................................................................................... 109 FIGURE 49 SPI SYSTEM BUS TIMING............................................................................................................................... 110 FIGURE50 RGB INTERFACE TIMING ................................................................................................................................ 111 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 6 of 112 Version: 0.08 1. Introduction a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 ILI9335 is a 262,144-color one-chip SoC driver for a-TFT liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit. ILI9335 has four kinds of system interfaces which are i80-system MPU interface (8-/9-/16-/18-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, DB[17:0]), serial data transfer interface (SPI), RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, DB[17:0]). In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption. ILI9335 can operate with 1.65V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LCD. The ILI9335 also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the ILI9335 an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, PDA and PMP where long battery life is a major concern. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 7 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 2. Features ‹ Single chip solution for a liquid crystal QVGA TFT LCD display ‹ 240RGBx320-dot resolution capable with real 262,144 display color ‹ Support MVA (Multi-domain Vertical Alignment) wide view display ‹ Incorporate 720-channel source driver and 320-channel gate driver ‹ Internal 172,800 bytes graphic RAM ‹ System interfaces ¾ i80 system interface with 8-/ 9-/16-/18-bit bus width ¾ Serial Peripheral Interface (SPI) ¾ RGB interface with 6-/16-/18-bit bus width (VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0]) ¾ VSYNC interface (System interface + VSYNC) ‹ Internal oscillator and hardware reset ‹ Reversible source/gate driver shift direction ‹ Window address function to specify a rectangular area for internal GRAM access ‹ Bit operation function for facilitating graphics data processing ¾ Bit-unit write data mask function ¾ Pixel-unit logical/conditional write function ‹ Abundant functions for color display control ¾ γ-correction function enabling display in 262,144 colors ¾ Line-unit vertical scrolling function ‹ Partial drive function, enabling partially driving an LCD panel at positions specified by user ‹ Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) ‹ Power saving functions ¾ 8-color mode ¾ standby mode ¾ sleep mode ¾ deep stand by mode ‹ Low -power consumption architecture ¾ Low operating power supplies: ƒ IOVcc = 1.65V ~ 3.6 V (interface I/O) ƒ VCI = 2.5V ~ 3.6 V (analog) ‹ LCD Voltage drive: ¾ Source/VCOM power supply voltage ƒ DDVDH - GND = 4.5V ~ 6.0 ƒ VCL – GND = -2.0V ~ -3.0V ƒ VCI – VCL ≦ 6.0V ¾ Gate driver output voltage ƒ VGH - GND = 10V ~ 20V ƒ VGL – GND = -5V ~ -15V The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 8 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ƒ VGH – VGL ≦ 30V ¾ VCOM driver output voltage ƒ VCOMH = (VCI+0.2)V ~ (DDVDH-0.2)V ƒ VCOML = (VCL+0.2)V ~ 0V ƒ VCOMH-VCOML ≦ 6.0V ‹ a-TFT LCD storage capacitor: Cst only ILI9335 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 9 of 112 Version: 0.08 3. Block Diagram a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 IOVCC IM[3:0] nRESET nCS nWR/SCL nRD RS SDI SDO DB[17:0] HSYNC VSYNC DOTCLK ENABLE TEST1 TEST2 TEST3 TS[8:0] VCC VDDD GND DUMMY1~15 VCI VCI1 GND Index Register (IR) MPU I/F 18-bit 16-bit 9-bit 8-bit 7 18 Control Register (CR) SPI I/F RGB I/F 18-bit 16-bit 6-bit 18 Graphics 18 Operation VSYNC I/F 18 Read Latch 18 Address Counter (AC) Write Latch 18 Graphics RAM (GRAM) Regulator RC-OSC. Timing Controller LCD Source Driver S[720:1] V63 ~ 0 Grayscale Reference Voltage VREG1OUT VGS DUMMY20~27 LCD Gate Driver G[320:1] Charge-pump Power Circuit VCOM Generator VCOM C11A C11B DDVDH C12A C12B C13A C13B VCL C21A C21B C22A C22B VGH VGL VCOMH VCOML The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 10 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 4. Pin Descriptions ILI9335 Pin Name IM3, IM2, IM1, IM0/ID nCS RS nWR/SCL nRD nRESET SDI SDO DB[17:0] I/O Type Descriptions Input Interface Select the MPU system interface mode IM3 IM2 IM1 IM0 MPU-Interface Mode 0 0 0 0 Setting invalid DB Pin in use 0 0 0 1 Setting invalid 0 0 1 0 i80-system 16-bit interface DB[17:10], DB[8:1] 0 0 1 1 i80-system 8-bit interface DB[17:10] I IOVcc 0 1 0 ID Serial Peripheral Interface (SPI) SDI, SDO 0 1 1 * Setting invalid 1 0 0 0 Setting invalid 1 0 0 1 Setting invalid 1 0 1 0 i80-system 18-bit interface DB[17:0] 1 0 1 1 i80-system 9-bit interface DB[17:9] 11 * * Setting invalid When the serial peripheral interface is selected, IM0 pin is used for the device code ID setting. A chip select signal. MPU I IOVcc Low: the ILI9335 is selected and accessible High: the ILI9335 is not selected and not accessible Fix to the GND level when not in use. A register select signal. MPU I IOVcc Low: select an index or status register High: select a control register Fix to either IOVcc or GND level when not in use. A write strobe signal and enables an operation to write data when the signal is low. MPU Fix to either IOVcc or GND level when not in use. I IOVcc SPI Mode: Synchronizing clock signal in SPI mode. MPU A read strobe signal and enables an operation to read out data when the signal is low. I IOVcc Fix to either IOVcc or GND level when not in use. A reset pin. MPU I Initializes the ILI9335 with a low input. Be sure to execute a power-on reset after IOVcc supplying power. MPU SPI interface input pin. I IOVcc The data is latched on the rising edge of the SCL signal. SPI interface output pin. MPU O The data is outputted on the falling edge of the SCL signal. IOVcc Let SDO as floating when not used. An 18-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: DB[17:10] is used. 9-bit I/F: DB[17:9] is used. 16-bit I/F: DB[17:10] and DB[8:1] is used. 18-bit I/F: DB[17:0] is used. MPU I/O 18-bit parallel bi-directional data bus for RGB interface operation IOVcc 6-bit RGB I/F: DB[17:12] are used. 16-bit RGB I/F: DB[17:13] and DB[11:1] are used. 18-bit RGB I/F: DB[17:0] are used. Unused pins must be fixed to GND level. ENABLE MPU Data ENEABLE signal for RGB interface operation. I IOVcc Low: Select (access enabled) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 11 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Pin Name DOTCLK VSYNC HSYNC FMARK S720~S1 G320~G1 VCOM VCOMH VCOML VGS VCI VCC VCI1 DDVDH VGH VGL VCL C11A, C11B I/O Type Descriptions High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal. Fix to either IOVcc or GND level when not in use. Dot clock signal for RGB interface operation. MPU I IOVcc DPL = “0”: Input data on the rising edge of DOTCLK DPL = “1”: Input data on the falling edge of DOTCLK Fix to the GND level when not in use Frame synchronizing signal for RGB interface operation. MPU I IOVcc VSPL = “0”: Active low. VSPL = “1”: Active high. Fix to the GND level when not in use. Line synchronizing signal for RGB interface operation. MPU I IOVcc HSPL = “0”: Active low. HSPL = “1”: Active high. Fix to the GND level when not in use Output a frame head pulse signal. MPU O The FMARK signal is used when writing RAM data in synchronization with frame. Leave IOVcc the pin open when not in use. LCD Driving signals Source output voltage signals applied to liquid crystal. To change the shift direction of signal outputs, use the SS bit. SS = “0”, the data in the RAM address “h00000” is output from S1. O LCD SS = “1”, the data in the RAM address “h00000” is output from S720. S1, S4, S7, … display red (R), S2, S5, S8, ... display green (G), and S3, S6, S9, ... display blue (B) (SS = 0). Gate line output signals. O LCD VGH: the level selecting gate lines VGL: the level not selecting gate lines TFT common A supply voltage to the common electrode of TFT panel. O electrode VCOM is AC voltage alternating signal between the VCOMH and VCOML levels. Stabilizing O The high level of VCOM AC voltage. Connect to a stabilizing capacitor. capacitor Stabilizing The low level of VCOM AC voltage. Adjust the VCOML level with the VDV bits. O capacitor Connect to a stabilizing capacitor. GND or Reference level for the grayscale voltage generating circuit. The VGS level can be I external changed by connecting to an external resistor. resistor Charge-pump and Regulator Circuit Power A supply voltage to the analog circuit. Connect to an external power supply of 2.5 ~ I supply 3.6V. Power A supply voltage to the digital circuit. Connect to an external power supply of 2.5 ~ I supply 3.6V. An internal reference voltage for the step-up circuit1. Stabilizing The amplitude between VCI and GND is determined by the VC[2:0] bits. O capacitor Make sure to set the VCI1 voltage so that the DDVDH, VGH and VGL voltages are set within the respective specification. Stabilizing O Power supply for the source driver and Vcom drive. capacitor Stabilizing O Power supply for the gate driver. capacitor Stabilizing O Power supply for the gate driver. capacitor VCOML driver power supply. Stabilizing O capacitor VCL = 0.5 ~ –VCI . Place a stabilizing capacitor between GND I/O Step-up Capacitor connection pins for the step-up circuit 1. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 12 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Pin Name C12A, C12B C13A, C13B C21A, C21B C22A, C22B I/O Type capacitor Descriptions Step-up I/O Capacitor connection pins for the step-up circuit 2. capacitor Output voltage generated from the reference voltage. VREG1OUT Stabilizing The voltage level is set with the VRH bits. I/O capacitor VREG1OUT is (1) a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage. Connect to a stabilizing capacitor. VREG1OUT = 3.0 ~ (DDVDH – 0.5)V. Power Pads IOVCC VDD DGND AGND VGMMA1, 62 VGLDMY1~4 A supply voltage to the interface pins: IM[3:0], nRESET, nCS, nWR, nRD, RS, DB[17:0], VSYNC, HSYNC, DOTCLK, Power I ENABLE, SCL, SDI, SDO. supply IOVcc = 1.65 ~ 3.6V. In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise. Digital circuit power pad. O Power Connect these pins with the 1uF capacitor. Power DGND for the digital side: DGND = 0V. In case of COG, connect to GND on the FPC I supply to prevent noise. Power AGND for the analog side: AGND = 0V. In case of COG, connect to GND on the FPC I supply to prevent noise. Test pad. O - Leave these pins as open Unused gate O Connect unused gate lines to fix the level at VGL lines Test Pads DUMMY3, 5~27,30, - 31. DUMMYR1,2, 28, 29. - DUMMY - Dummy pad. - Leave these pins as open Short circuited within the chip for COG contact resistance measurement. DUMMYR pins are short circuited as below: - DUMMYR1 and DUMMYR29 DUMMYR2 and DUMMYR28 - Dummy pad and no output (no gold bump) IOVCCDUM AGNDDUM1~6 O O - Connect unused interface and test pins to these pins on the glass to fix voltage levels. Leave open when not used. DGNDDUM1~7 O - TESTO1~16 TEST1, 2, 3 TS0~8 TSO TEST_EN O Open Test pins. Leave them open. Test pins (internal pull low). I IOGND Connect to GND or leave these pins as open. I OPEN Test pins (internal pull low). Leave them open. O OPEN Test pins. Leave it open or short to ground. I OPEN Test pins. Leave it open or short to ground. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 13 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Liquid crystal power supply specifications Table 1 No. Item 1 TFT Source Driver 2 TFT Gate Driver 3 TFT Display’s Capacitor Structure S1 ~ S720 4 Liquid Crystal Drive Output G1 ~ G320 VCOM 5 Input Voltage IOVcc VCI DDVDH VGH VGL 6 Liquid Crystal Drive Voltages VCL VGH - VGL VCI - VCL DDVDH 7 Internal Step-up Circuits VGH VGL VCL Description 720 pins (240 x RGB) 320 pins Cst structure only (Common VCOM) V0 ~ V63 grayscales VGH - VGL VCOMH - VCOML: Amplitude = electronic volumes 1.65 ~ 3.60V 2.50 ~ 3.60V 4.5V ~ 6.0V 10V ~ 20V -5V ~ -15V -1.9V ~ -3.0V Max. 30V Max. 6.0V VCI1 x2 VCI1 x4, x5, x6 VCI1 x-3, x-4, x-5 VCI1 x-1 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 14 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 5. Pad Arrangement and Coordination ILI9335 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 15 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 NO. Pad Name X Y NO. 1 DGNDDUM1 -9065 -239 61 2 DUMMYR1 -8995 -239 62 3 DUMMYR2 -8925 -239 63 4 TESTO[1] -8855 -239 64 5 TESTO[2] -8785 -239 65 6 TESTO[3] -8715 -239 66 7 TESTO[4] -8645 -239 67 8 TESTO[5] -8575 -239 68 9 TESTO[6] -8505 -239 69 10 TESTO[7] -8435 -239 70 11 TESTO[8] -8365 -239 71 12 DUMMY -8295 -239 72 13 DUMMY -8225 -239 73 14 TESTO[9] -8155 -239 74 15 TESTO[10] -8085 -239 75 16 TESTO[11] -8015 -239 76 17 TESTO[12] -7945 -239 77 18 DGND -7875 -239 78 19 DGND -7805 -239 79 20 DGND -7735 -239 80 21 DGND -7665 -239 81 22 DGND -7595 -239 82 23 DGND -7525 -239 83 24 DGND -7455 -239 84 25 DGND -7385 -239 85 26 DGND -7315 -239 86 27 DGND -7245 -239 87 28 TESTO[13] -7175 -239 88 29 TESTO[14] -7105 -239 89 30 DGNDDUM2 -7035 -239 90 31 IM0/ID -6965 -239 91 32 IM1 -6895 -239 92 33 IM2 -6825 -239 93 34 IM3 -6755 -239 94 35 IOVCCDUM -6685 -239 95 36 TESTO[15] -6615 -239 96 37 TESTO[16] -6545 -239 97 38 TEST3 -6475 -239 98 39 TEST2 -6405 -239 99 40 TEST1 -6335 -239 100 41 DGNDDUM3 -6265 -239 101 42 FMARK -6195 -239 102 43 VSYNC -6125 -239 103 44 HSYNC -6055 -239 104 45 DOTCLK -5985 -239 105 46 ENABLE -5915 -239 106 47 TEST_EN -5845 -239 107 48 DB[17] -5775 -239 108 49 DB[16] -5705 -239 109 50 DB[15] -5635 -239 110 51 TS[8] -5565 -239 111 52 TS[7] -5495 -239 112 53 DB[14] -5425 -239 113 54 DB[13] -5355 -239 114 55 DB[12] -5285 -239 115 56 TS[6] -5215 -239 116 57 TS[5] -5145 -239 117 58 DB[11] -5075 -239 118 59 DB[10] -5005 -239 119 60 DB[9] -4935 -239 120 Pad Name IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC DB[8] DB[7] DB[6] TS[4] TS[3] DB[5] DB[4] DB[3] TS[2] TS[1] DB[2] DB[1] DB[0] TS[0] TSO DGNDDUM5 nCS RS nWR/SCL nRD nRESET SDO SDI DGNDDUM6 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DGNDDUM7 VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD DGND DGND DGND DGND DGND DGND DGND DGND X Y NO. Pad Name X Y -4865 -239 121 VGS -665 -239 -4795 -239 122 AGND -595 -239 -4725 -239 123 AGND -525 -239 -4655 -239 124 AGND -455 -239 -4585 -239 125 AGND -385 -239 -4515 -239 126 AGND -315 -239 -4445 -239 127 AGND -245 -239 -4375 -239 128 AGND -175 -239 -4305 -239 129 AGND -105 -239 -4235 -239 120 VCOMH -35 -239 -4165 -239 131 VCOMH 35 -239 -4095 -239 132 VCOMH 105 -239 -4025 -239 133 VCOMH 175 -239 -3955 -239 134 VCOMH 245 -239 -3885 -239 135 VCOMH 315 -239 -3815 -239 136 VCOM 385 -239 -3745 -239 137 VCOM 455 -239 -3675 -239 138 VCOM 525 -239 -3605 -239 139 VCOM 595 -239 -3535 -239 140 VCOM 665 -239 -3465 -239 141 VCOM 735 -239 -3395 -239 142 VCOML 805 -239 -3325 -239 143 VCOML 875 -239 -3255 -239 144 VCOML 945 -239 -3185 -239 145 VCOML 1015 -239 -3115 -239 146 VCOML 1085 -239 -3045 -239 147 VCOML 1155 -239 -2975 -239 148 VCOML 1225 -239 -2905 -239 149 C11A 1295 -239 -2835 -239 150 C11A 1365 -239 -2765 -239 151 C11A 1435 -239 -2695 -239 152 C11A 1505 -239 -2625 -239 153 C11A 1575 -239 -2555 -239 154 C11B 1645 -239 -2485 -239 155 C11B 1715 -239 -2415 -239 156 C11B 1785 -239 -2345 -239 157 C11B 1855 -239 -2275 -239 158 C11B 1925 -239 -2205 -239 159 C12B 1995 -239 -2135 -239 160 C12B 2065 -239 -2065 -239 161 C12B 2135 -239 -1995 -239 162 C12B 2205 -239 -1925 -239 163 C12B 2275 -239 -1855 -239 164 C12A 2345 -239 -1785 -239 165 C12A 2415 -239 -1715 -239 120 C12A 2485 -239 -1645 -239 167 C12A 2555 -239 -1575 -239 168 C12A 2625 -239 -1505 -239 169 DDVDH 2695 -239 -1435 -239 170 DDVDH 2765 -239 -1365 -239 171 DDVDH 2835 -239 -1295 -239 172 DDVDH 2905 -239 -1225 -239 173 DDVDH 2975 -239 -1155 -239 174 DDVDH 3045 -239 -1085 -239 175 DDVDH 3115 -239 -1015 -239 176 DDVDH 3185 -239 -945 -239 177 DDVDH 3255 -239 -875 -239 178 DDVDH 3325 -239 -805 -239 179 DUMMY10 3395 -239 -735 -239 180 VREG1OUT 3465 -239 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 16 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 NO. Pad Name X Y NO. Pad Name X Y NO. Pad Name X Y 181 DUMMY11 3535 -239 241 AGND 7735 -239 301 G[71] 8576 233 182 DUMMY12 3605 -239 242 AGND 7805 -239 302 G[73] 8560 120 183 AGNDDUM1 3675 -239 233 C21B 7875 -239 303 G[75] 8544 233 184 AGNDDUM2 3745 -239 244 C21B 7945 -239 304 G[77] 8528 120 185 VCI1 3815 -239 245 C21B 8015 -239 305 G[79] 8512 233 186 VCI1 3885 -239 246 C21A 8085 -239 306 G[81] 8496 120 187 VCI1 3955 -239 247 C21A 8155 -239 307 G[83] 8480 233 188 VCI1 4025 -239 248 C21A 8225 -239 308 G[85] 8464 120 189 VCI1 4095 -239 249 C22B 8295 -239 309 G[87] 8448 233 190 VCI1 4165 -239 250 C22B 8365 -239 310 G[89] 8432 120 191 VCI1 4235 -239 251 C22B 8435 -239 311 G[91] 8416 233 192 VCI1 4305 -239 252 C22A 8505 -239 312 G[93] 8400 120 193 VCI 4375 -239 253 C22A 8575 -239 313 G[95] 8384 233 194 VCI 4445 -239 254 C22A 8645 -239 314 G[97] 8368 120 195 VCI 4515 -239 255 DUMMY13 8715 -239 315 G[99] 8352 233 196 VCI 4585 -239 256 DUMMY14 8785 -239 316 G[101] 8336 120 197 VCI 4655 -239 257 DUMMY15 8855 -239 317 G[103] 8320 233 198 VCI 4725 -239 258 DUMMY16 8925 -239 318 G[105] 8304 120 199 VCI 4795 -239 259 DUMMY17 8995 -239 319 G[107] 8288 233 200 VCI 4865 -239 260 AGNDDUM6 9065 -239 320 G[109] 8272 120 201 VCI 4935 -239 261 DUMMY18 9216 233 321 G[111] 8256 233 202 AGNDDUM3 5005 -239 262 DUMMY19 9200 120 322 G[113] 8240 120 203 VGH 5075 -239 263 DUMMY20 9184 233 323 G[115] 8224 233 204 VGH 5145 -239 264 DUMMY21 9168 120 324 G[117] 8208 120 205 VGH 5215 -239 265 VGLDMY1 9152 233 325 G[119] 8192 233 206 VGH 5285 -239 266 G[1] 9136 120 326 G[121] 8176 120 207 VGH 5355 -239 267 G[3] 9120 233 327 G[123] 8160 233 208 VGH 5425 -239 268 G[5] 9104 120 328 G[125] 8144 120 209 AGNDDUM4 5495 -239 269 G[7] 9088 233 329 G[127] 8128 233 210 VGL 5565 -239 270 G[9] 9072 120 330 G[129] 8112 120 211 VGL 5635 -239 271 G[11] 9056 233 331 G[131] 8096 233 212 VGL 5705 -239 272 G[13] 9040 120 332 G[133] 8080 120 213 VGL 5775 -239 273 G[15] 9024 233 333 G[135] 8064 233 214 VGL 5845 -239 274 G[17] 9008 120 334 G[137] 8048 120 215 VGL 5915 -239 275 G[19] 8992 233 335 G[139] 8032 233 216 VGL 5985 -239 276 G[21] 8976 120 336 G[141] 8016 120 217 VGL 6055 -239 277 G[23] 8960 233 337 G[143] 8000 233 218 VGL 6125 -239 278 G[25] 8944 120 338 G[145] 7984 120 219 VGL 6195 -239 233 G[27] 8928 233 339 G[147] 7968 233 220 AGNDDUM5 6265 -239 280 G[29] 8912 120 340 G[149] 7952 120 221 VCL 6335 -239 281 G[31] 8896 233 341 G[151] 7936 233 222 VCL 6405 -239 282 G[33] 8880 120 342 G[153] 7920 120 223 VCL 6475 -239 283 G[35] 8864 233 343 G[155] 7904 233 224 VCL 6545 -239 284 G[37] 8848 120 344 G[157] 7888 120 225 C13B 6615 -239 285 G[39] 8832 233 345 G[159] 7872 233 226 C13B 6685 -239 286 G[41] 8816 120 346 G[161] 7856 120 227 C13B 6755 -239 287 G[43] 8800 233 347 G[163] 7840 233 228 C13B 6825 -239 288 G[45] 8784 120 348 G[165] 7824 120 229 C13A 6895 -239 289 G[47] 8768 233 349 G[167] 7808 233 230 C13A 6965 -239 290 G[49] 8752 120 350 G[169] 7792 120 231 C13A 7035 -239 291 G[51] 8736 233 351 G[171] 7776 233 232 C13A 7105 -239 292 G[53] 8720 120 352 G[173] 7760 120 233 AGND 7175 -239 293 G[55] 8704 233 353 G[175] 7744 233 234 AGND 7245 -239 294 G[57] 8688 120 354 G[177] 7728 120 235 AGND 7315 -239 295 G[59] 8672 233 355 G[179] 7712 233 236 AGND 7385 -239 296 G[61] 8656 120 356 G[181] 7696 120 237 AGND 7455 -239 297 G[63] 8640 233 357 G[183] 7680 233 238 AGND 7525 -239 298 G[65] 8624 120 358 G[185] 7664 120 239 AGND 7595 -239 299 G[67] 8608 233 359 G[187] 7648 233 240 AGND 7665 -239 300 G[69] 8592 120 360 G[189] 7632 120 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 17 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 NO. Pad Name X Y NO. Pad Name X Y NO. Pad Name X Y 361 G[191] 7616 233 421 G[311] 6656 233 481 S[669] 5520 120 362 G[193] 7600 120 422 G[313] 6640 120 482 S[668] 5504 233 363 G[195] 7584 233 423 G[315] 6624 233 483 S[667] 5488 120 364 G[197] 7568 120 424 G[317] 6608 120 484 S[666] 5472 233 365 G[199] 7552 233 425 G[319] 6592 233 485 S[665] 5456 120 366 G[201] 7536 120 426 VGLDMY2 6576 120 486 S[664] 5440 233 367 G[203] 7520 233 427 DUMMY22 6560 233 487 S[663] 5424 120 368 G[205] 7504 120 428 DUMMY23 6368 233 488 S[662] 5408 233 369 G[207] 7488 233 429 DUMMY24 6352 120 489 S[661] 5392 120 370 G[209] 7472 120 430 S[720] 6336 233 490 S[660] 5376 233 371 G[211] 7456 233 431 S[719] 6320 120 491 S[659] 5360 120 372 G[213] 7440 120 432 S[718] 6304 233 492 S[658] 5344 233 373 G[215] 7424 233 433 S[717] 6288 120 493 S[657] 5328 120 374 G[217] 7408 120 434 S[716] 6272 233 494 S[656] 5312 233 375 G[219] 7392 233 435 S[715] 6256 120 495 S[655] 5296 120 376 G[221] 7376 120 436 S[714] 6240 233 496 S[654] 5280 233 377 G[223] 7360 233 437 S[713] 6224 120 497 S[653] 5264 120 378 G[225] 7344 120 438 S[712] 6208 233 498 S[652] 5248 233 379 G[227] 7328 233 439 S[711] 6192 120 499 S[651] 5232 120 380 G[229] 7312 120 440 S[710] 6176 233 500 S[650] 5216 233 381 G[231] 7296 233 441 S[709] 6160 120 501 S[649] 5200 120 382 G[233] 7280 120 442 S[708] 6144 233 502 S[648] 5184 233 383 G[235] 7264 233 443 S[707] 6128 120 503 S[647] 5168 120 384 G[237] 7248 120 444 S[706] 6112 233 504 S[646] 5152 233 385 G[239] 7232 233 445 S[705] 6096 120 505 S[645] 5136 120 386 G[241] 7216 120 446 S[704] 6080 233 506 S[644] 5120 233 387 G[233] 7200 233 447 S[703] 6064 120 507 S[643] 5104 120 388 G[245] 7184 120 448 S[702] 6048 233 508 S[642] 5088 233 389 G[247] 7168 233 449 S[701] 6032 120 509 S[641] 5072 120 390 G[249] 7152 120 450 S[700] 6016 233 510 S[640] 5056 233 391 G[251] 7136 233 451 S[699] 6000 120 511 S[639] 5040 120 392 G[253] 7120 120 452 S[698] 5984 233 512 S[638] 5024 233 393 G[255] 7104 233 453 S[697] 5968 120 513 S[637] 5008 120 394 G[257] 7088 120 454 S[696] 5952 233 514 S[636] 4992 233 395 G[259] 7072 233 455 S[695] 5936 120 515 S[635] 4976 120 396 G[261] 7056 120 456 S[694] 5920 233 516 S[634] 4960 233 397 G[263] 7040 233 457 S[693] 5904 120 517 S[633] 4944 120 398 G[265] 7024 120 458 S[692] 5888 233 518 S[632] 4928 233 399 G[267] 7008 233 459 S[691] 5872 120 519 S[631] 4912 120 400 G[269] 6992 120 460 S[690] 5856 233 520 S[630] 4896 233 401 G[271] 6976 233 461 S[689] 5840 120 521 S[629] 4880 120 402 G[273] 6960 120 462 S[688] 5824 233 522 S[628] 4864 233 403 G[275] 6944 233 463 S[687] 5808 120 523 S[627] 4848 120 404 G[277] 6928 120 464 S[686] 5792 233 524 S[626] 4832 233 405 G[233] 6912 233 465 S[685] 5776 120 525 S[625] 4816 120 406 G[281] 6896 120 466 S[684] 5760 233 526 S[624] 4800 233 407 G[283] 6880 233 467 S[683] 5744 120 527 S[623] 4784 120 408 G[285] 6864 120 468 S[682] 5728 233 528 S[622] 4768 233 409 G[287] 6848 233 469 S[681] 5712 120 529 S[621] 4752 120 410 G[289] 6832 120 470 S[680] 5696 233 530 S[620] 4736 233 411 G[291] 6816 233 471 S[679] 5680 120 531 S[619] 4720 120 412 G[293] 6800 120 472 S[678] 5664 233 532 S[618] 4704 233 413 G[295] 6784 233 473 S[677] 5648 120 533 S[617] 4688 120 414 G[297] 6768 120 474 S[676] 5632 233 534 S[616] 4672 233 415 G[299] 6752 233 475 S[675] 5616 120 535 S[615] 4656 120 416 G[301] 6736 120 476 S[674] 5600 233 536 S[614] 4640 233 417 G[303] 6720 233 477 S[673] 5584 120 537 S[613] 4624 120 418 G[305] 6704 120 478 S[672] 5568 233 538 S[612] 4608 233 419 G[307] 6688 233 479 S[671] 5552 120 539 S[611] 4592 120 420 G[309] 6672 120 480 S[670] 5536 233 540 S[610] 4576 233 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 18 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 NO. Pad Name X Y NO. Pad Name X Y NO. Pad Name X Y 541 S[609] 4560 120 601 S[549] 3600 120 661 S[489] 2640 120 542 S[608] 4544 233 602 S[548] 3584 233 662 S[488] 2624 233 543 S[607] 4528 120 603 S[547] 3568 120 663 S[487] 2608 120 544 S[606] 4512 233 604 S[546] 3552 233 664 S[486] 2592 233 545 S[605] 4496 120 605 S[545] 3536 120 665 S[485] 2576 120 546 S[604] 4480 233 606 S[544] 3520 233 666 S[484] 2560 233 547 S[603] 4464 120 607 S[543] 3504 120 667 S[483] 2544 120 548 S[602] 4448 233 608 S[542] 3488 233 668 S[482] 2528 233 549 S[601] 4432 120 609 S[541] 3472 120 669 S[481] 2512 120 550 S[600] 4416 233 610 S[540] 3456 233 670 S[480] 2496 233 551 S[599] 4400 120 611 S[539] 3440 120 671 S[479] 2480 120 552 S[598] 4384 233 612 S[538] 3424 233 672 S[478] 2464 233 553 S[597] 4368 120 613 S[537] 3408 120 673 S[477] 2448 120 554 S[596] 4352 233 614 S[536] 3392 233 674 S[476] 2432 233 555 S[595] 4336 120 615 S[535] 3376 120 675 S[475] 2416 120 556 S[594] 4320 233 616 S[534] 3360 233 676 S[474] 2400 233 557 S[593] 4304 120 617 S[533] 3344 120 677 S[473] 2384 120 558 S[592] 4288 233 618 S[532] 3328 233 678 S[472] 2368 233 559 S[591] 4272 120 619 S[531] 3312 120 679 S[471] 2352 120 560 S[590] 4256 233 620 S[530] 3296 233 680 S[470] 2336 233 561 S[589] 4240 120 621 S[529] 3280 120 681 S[469] 2320 120 562 S[588] 4224 233 622 S[528] 3264 233 682 S[468] 2304 233 563 S[587] 4208 120 623 S[527] 3248 120 683 S[467] 2288 120 564 S[586] 4192 233 624 S[526] 3232 233 684 S[466] 2272 233 565 S[585] 4176 120 625 S[525] 3216 120 685 S[465] 2256 120 566 S[584] 4160 233 626 S[524] 3200 233 686 S[464] 2240 233 567 S[583] 4144 120 627 S[523] 3184 120 687 S[463] 2224 120 568 S[582] 4128 233 628 S[522] 3168 233 688 S[462] 2208 233 569 S[581] 4112 120 629 S[521] 3152 120 689 S[461] 2192 120 570 S[580] 4096 233 630 S[520] 3136 233 690 S[460] 2176 233 571 S[579] 4080 120 631 S[519] 3120 120 691 S[459] 2160 120 572 S[578] 4064 233 632 S[518] 3104 233 692 S[458] 2144 233 573 S[577] 4048 120 633 S[517] 3088 120 693 S[457] 2128 120 574 S[576] 4032 233 634 S[516] 3072 233 694 S[456] 2112 233 575 S[575] 4016 120 635 S[515] 3056 120 695 S[455] 2096 120 576 S[574] 4000 233 636 S[514] 3040 233 696 S[454] 2080 233 577 S[573] 3984 120 637 S[513] 3024 120 697 S[453] 2064 120 578 S[572] 3968 233 638 S[512] 3008 233 698 S[452] 2048 233 579 S[571] 3952 120 639 S[511] 2992 120 699 S[451] 2032 120 580 S[570] 3936 233 640 S[510] 2976 233 700 S[450] 2016 233 581 S[569] 3920 120 641 S[509] 2960 120 701 S[449] 2000 120 582 S[568] 3904 233 642 S[508] 2944 233 702 S[448] 1984 233 583 S[567] 3888 120 643 S[507] 2928 120 703 S[447] 1968 120 584 S[566] 3872 233 644 S[506] 2912 233 704 S[446] 1952 233 585 S[565] 3856 120 645 S[505] 2896 120 705 S[445] 1936 120 586 S[564] 3840 233 646 S[504] 2880 233 706 S[444] 1920 233 587 S[563] 3824 120 647 S[503] 2864 120 707 S[443] 1904 120 588 S[562] 3808 233 648 S[502] 2848 233 708 S[442] 1888 233 589 S[561] 3792 120 649 S[501] 2832 120 709 S[441] 1872 120 590 S[560] 3776 233 650 S[500] 2816 233 710 S[440] 1856 233 591 S[559] 3760 120 651 S[499] 2800 120 711 S[439] 1840 120 592 S[558] 3744 233 652 S[498] 2784 233 712 S[438] 1824 233 593 S[557] 3728 120 653 S[497] 2768 120 713 S[437] 1808 120 594 S[556] 3712 233 654 S[496] 2752 233 714 S[436] 1792 233 595 S[555] 3696 120 655 S[495] 2736 120 715 S[435] 1776 120 596 S[554] 3680 233 656 S[494] 2720 233 716 S[434] 1760 233 597 S[553] 3664 120 657 S[493] 2704 120 717 S[433] 1744 120 598 S[552] 3648 233 658 S[492] 2688 233 718 S[432] 1728 233 599 S[551] 3632 120 659 S[491] 2672 120 719 S[431] 1712 120 600 S[550] 3616 233 660 S[490] 2656 233 720 S[430] 1696 233 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 19 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 NO. Pad Name 721 S[429] 722 S[428] 723 S[427] 724 S[426] 725 S[425] 726 S[424] 727 S[423] 728 S[422] 729 S[421] 730 S[420] 731 S[419] 732 S[418] 733 S[417] 734 S[416] 735 S[415] 736 S[414] 737 S[413] 738 S[412] 739 S[411] 740 S[410] 741 S[409] 742 S[408] 743 S[407] 744 S[406] 745 S[405] 746 S[404] 747 S[403] 748 S[402] 749 S[401] 750 S[400] 751 S[399] 752 S[398] 753 S[397] 754 S[396] 755 S[395] 756 S[394] 757 S[393] 758 S[392] 759 S[391] 760 S[390] 761 S[389] 762 S[388] 763 S[387] 764 S[386] 765 S[385] 766 S[384] 767 S[383] 768 S[382] 769 S[381] 770 S[380] 771 S[379] 772 S[378] 773 S[377] 774 S[376] 775 S[375] 776 S[374] 777 S[373] 778 S[372] 779 S[371] 780 S[370] X Y NO. 1680 120 781 1664 233 782 1648 120 783 1632 233 784 1616 120 785 1600 233 786 1584 120 787 1568 233 788 1552 120 789 1536 233 790 1520 120 791 1504 233 792 1488 120 793 1472 233 794 1456 120 795 1440 233 796 1424 120 797 1408 233 798 1392 120 799 1376 233 800 1360 120 801 1344 233 802 1328 120 803 1312 233 804 1296 120 805 1280 233 806 1264 120 807 1248 233 808 1232 120 809 1216 233 810 1200 120 811 1184 233 812 1168 120 813 1152 233 814 1136 120 815 1120 233 816 1104 120 817 1088 233 818 1072 120 819 1056 233 820 1040 120 821 1024 233 822 1008 120 823 992 233 824 976 120 825 960 233 826 944 120 827 928 233 828 912 120 829 896 233 830 880 120 831 864 233 832 848 120 833 832 233 834 816 120 835 800 233 836 784 120 837 768 233 838 752 120 839 736 233 840 Pad Name S[369] S[368] S[367] S[366] S[365] S[364] S[363] S[362] S[361] VGMMA62 VGMMA1 S[360] S[359] S[358] S[357] S[356] S[355] S[354] S[353] S[352] S[351] S[350] S[349] S[348] S[347] S[346] S[345] S[344] S[343] S[342] S[341] S[340] S[339] S[338] S[337] S[336] S[335] S[334] S[333] S[332] S[331] S[330] S[329] S[328] S[327] S[326] S[325] S[324] S[323] S[322] S[321] S[320] S[319] S[318] S[317] S[316] S[315] S[314] S[313] S[312] X Y NO. 720 120 841 704 233 842 688 120 843 672 233 844 656 120 845 640 233 846 624 120 847 608 233 848 592 120 849 576 233 850 -576 120 851 -592 233 852 -608 120 853 -624 233 854 -640 120 855 -656 233 856 -672 120 857 -688 233 858 -704 120 859 -720 233 860 -736 120 861 -752 233 862 -768 120 863 -784 233 864 -800 120 865 -816 233 866 -832 120 867 -848 233 868 -864 120 869 -880 233 870 -896 120 871 -912 233 872 -928 120 873 -944 233 874 -960 120 875 -976 233 876 -992 120 877 -1008 233 878 -1024 120 879 -1040 233 880 -1056 120 881 -1072 233 882 -1088 120 883 -1104 233 884 -1120 120 885 -1136 233 886 -1152 120 887 -1168 233 888 -1184 120 889 -1200 233 890 -1216 120 891 -1232 233 892 -1248 120 893 -1264 233 894 -1280 120 895 -1296 233 896 -1312 120 897 -1328 233 898 -1344 120 899 -1360 233 900 Pad Name S[311] S[310] S[309] S[308] S[307] S[306] S[305] S[304] S[303] S[302] S[301] S[300] S[299] S[298] S[297] S[296] S[295] S[294] S[293] S[292] S[291] S[290] S[289] S[288] S[287] S[286] S[285] S[284] S[283] S[282] S[281] S[280] S[233] S[278] S[277] S[276] S[275] S[274] S[273] S[272] S[271] S[270] S[269] S[268] S[267] S[266] S[265] S[264] S[263] S[262] S[261] S[260] S[259] S[258] S[257] S[256] S[255] S[254] S[253] S[252] X Y -1376 120 -1392 233 -1408 120 -1424 233 -1440 120 -1456 233 -1472 120 -1488 233 -1504 120 -1520 233 -1536 120 -1552 233 -1568 120 -1584 233 -1600 120 -1616 233 -1632 120 -1648 233 -1664 120 -1680 233 -1696 120 -1712 233 -1728 120 -1744 233 -1760 120 -1776 233 -1792 120 -1808 233 -1824 120 -1840 233 -1856 120 -1872 233 -1888 120 -1904 233 -1920 120 -1936 233 -1952 120 -1968 233 -1984 120 -2000 233 -2016 120 -2032 233 -2048 120 -2064 233 -2080 120 -2096 233 -2112 120 -2128 233 -2144 120 -2160 233 -2176 120 -2192 233 -2208 120 -2224 233 -2240 120 -2256 233 -2272 120 -2288 233 -2304 120 -2320 233 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 20 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 NO. Pad Name 901 S[251] 902 S[250] 903 S[249] 904 S[248] 905 S[247] 906 S[246] 907 S[245] 908 S[244] 909 S[233] 910 S[242] 911 S[241] 912 S[240] 913 S[239] 914 S[238] 915 S[237] 916 S[236] 917 S[235] 918 S[234] 919 S[233] 920 S[232] 921 S[231] 922 S[230] 923 S[229] 924 S[228] 925 S[227] 926 S[226] 927 S[225] 928 S[224] 929 S[223] 930 S[222] 931 S[221] 932 S[220] 933 S[219] 934 S[218] 935 S[217] 936 S[216] 937 S[215] 938 S[214] 939 S[213] 940 S[212] 941 S[211] 942 S[210] 943 S[209] 944 S[208] 945 S[207] 946 S[206] 947 S[205] 948 S[204] 949 S[203] 950 S[202] 951 S[201] 952 S[200] 953 S[199] 954 S[198] 955 S[197] 956 S[196] 957 S[195] 958 S[194] 959 S[193] 960 S[192] X Y -2336 120 -2352 233 -2368 120 -2384 233 -2400 120 -2416 233 -2432 120 -2448 233 -2464 120 -2480 233 -2496 120 -2512 233 -2528 120 -2544 233 -2560 120 -2576 233 -2592 120 -2608 233 -2624 120 -2640 233 -2656 120 -2672 233 -2688 120 -2704 233 -2720 120 -2736 233 -2752 120 -2768 233 -2784 120 -2800 233 -2816 120 -2832 233 -2848 120 -2864 233 -2880 120 -2896 233 -2912 120 -2928 233 -2944 120 -2960 233 -2976 120 -2992 233 -3008 120 -3024 233 -3040 120 -3056 233 -3072 120 -3088 233 -3104 120 -3120 233 -3136 120 -3152 233 -3168 120 -3184 233 -3200 120 -3216 233 -3232 120 -3248 233 -3264 120 -3280 233 NO. 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 Pad Name S[191] S[190] S[189] S[188] S[187] S[186] S[185] S[184] S[183] S[182] S[181] S[180] S[179] S[178] S[177] S[176] S[175] S[174] S[173] S[172] S[171] S[170] S[169] S[168] S[167] S[120] S[165] S[164] S[163] S[162] S[161] S[160] S[159] S[158] S[157] S[156] S[155] S[154] S[153] S[152] S[151] S[150] S[149] S[148] S[147] S[146] S[145] S[144] S[143] S[142] S[141] S[140] S[139] S[138] S[137] S[136] S[135] S[134] S[133] S[132] X Y -3296 120 -3312 233 -3328 120 -3344 233 -3360 120 -3376 233 -3392 120 -3408 233 -3424 120 -3440 233 -3456 120 -3472 233 -3488 120 -3504 233 -3520 120 -3536 233 -3552 120 -3568 233 -3584 120 -3600 233 -3616 120 -3632 233 -3648 120 -3664 233 -3680 120 -3696 233 -3712 120 -3728 233 -3744 120 -3760 233 -3776 120 -3792 233 -3808 120 -3824 233 -3840 120 -3856 233 -3872 120 -3888 233 -3904 120 -3920 233 -3936 120 -3952 233 -3968 120 -3984 233 -4000 120 -4016 233 -4032 120 -4048 233 -4064 120 -4080 233 -4096 120 -4112 233 -4128 120 -4144 233 -4160 120 -4176 233 -4192 120 -4208 233 -4224 120 -4240 233 NO. 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 Pad Name S[131] S[120] S[129] S[128] S[127] S[126] S[125] S[124] S[123] S[122] S[121] S[120] S[119] S[118] S[117] S[116] S[115] S[114] S[113] S[112] S[111] S[110] S[109] S[108] S[107] S[106] S[105] S[104] S[103] S[102] S[101] S[100] S[99] S[98] S[97] S[96] S[95] S[94] S[93] S[92] S[91] S[90] S[89] S[88] S[87] S[86] S[85] S[84] S[83] S[82] S[81] S[80] S[79] S[78] S[77] S[76] S[75] S[74] S[73] S[72] X Y -4256 120 -4272 233 -4288 120 -4304 233 -4320 120 -4336 233 -4352 120 -4368 233 -4384 120 -4400 233 -4416 120 -4432 233 -4448 120 -4464 233 -4480 120 -4496 233 -4512 120 -4528 233 -4544 120 -4560 233 -4576 120 -4592 233 -4608 120 -4624 233 -4640 120 -4656 233 -4672 120 -4688 233 -4704 120 -4720 233 -4736 120 -4752 233 -4768 120 -4784 233 -4800 120 -4816 233 -4832 120 -4848 233 -4864 120 -4880 233 -4896 120 -4912 233 -4928 120 -4944 233 -4960 120 -4976 233 -4992 120 -5008 233 -5024 120 -5040 233 -5056 120 -5072 233 -5088 120 -5104 233 -5120 120 -5136 233 -5152 120 -5168 233 -5184 120 -5200 233 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 21 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 NO. 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1120 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 Pad Name S[71] S[70] S[69] S[68] S[67] S[66] S[65] S[64] S[63] S[62] S[61] S[60] S[59] S[58] S[57] S[56] S[55] S[54] S[53] S[52] S[51] S[50] S[49] S[48] S[47] S[46] S[45] S[44] S[43] S[42] S[41] S[40] S[39] S[38] S[37] S[36] S[35] S[34] S[33] S[32] S[31] S[30] S[29] S[28] S[27] S[26] S[25] S[24] S[23] S[22] S[21] S[20] S[19] S[18] S[17] S[16] S[15] S[14] S[13] S[12] X Y -5216 120 -5232 233 -5248 120 -5264 233 -5280 120 -5296 233 -5312 120 -5328 233 -5344 120 -5360 233 -5376 120 -5392 233 -5408 120 -5424 233 -5440 120 -5456 233 -5472 120 -5488 233 -5504 120 -5520 233 -5536 120 -5552 233 -5568 120 -5584 233 -5600 120 -5616 233 -5632 120 -5648 233 -5664 120 -5680 233 -5696 120 -5712 233 -5728 120 -5744 233 -5760 120 -5776 233 -5792 120 -5808 233 -5824 120 -5840 233 -5856 120 -5872 233 -5888 120 -5904 233 -5920 120 -5936 233 -5952 120 -5968 233 -5984 120 -6000 233 -6016 120 -6032 233 -6048 120 -6064 233 -6080 120 -6096 233 -6112 120 -6128 233 -6144 120 -6160 233 NO. 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1120 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 Pad Name S[11] S[10] S[9] S[8] S[7] S[6] S[5] S[4] S[3] S[2] S[1] DUMMY25 DUMMY26 DUMMY27 VGLDMY3 G[320] G[318] G[316] G[314] G[312] G[310] G[308] G[306] G[304] G[302] G[300] G[298] G[296] G[294] G[292] G[290] G[288] G[286] G[284] G[282] G[280] G[278] G[276] G[274] G[272] G[270] G[268] G[266] G[264] G[262] G[260] G[258] G[256] G[254] G[252] G[250] G[248] G[246] G[244] G[242] G[240] G[238] G[236] G[234] G[232] X Y -6176 120 -6192 233 -6208 120 -6224 233 -6240 120 -6256 233 -6272 120 -6288 233 -6304 120 -6320 233 -6336 120 -6352 233 -6368 120 -6560 233 -6576 120 -6592 233 -6608 120 -6624 233 -6640 120 -6656 233 -6672 120 -6688 233 -6704 120 -6720 233 -6736 120 -6752 233 -6768 120 -6784 233 -6800 120 -6816 233 -6832 120 -6848 233 -6864 120 -6880 233 -6896 120 -6912 233 -6928 120 -6944 233 -6960 120 -6976 233 -6992 120 -7008 233 -7024 120 -7040 233 -7056 120 -7072 233 -7088 120 -7104 233 -7120 120 -7136 233 -7152 120 -7168 233 -7184 120 -7200 233 -7216 120 -7232 233 -7248 120 -7264 233 -7280 120 -7296 233 NO. 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1233 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 Pad Name G[230] G[228] G[226] G[224] G[222] G[220] G[218] G[216] G[214] G[212] G[210] G[208] G[206] G[204] G[202] G[200] G[198] G[196] G[194] G[192] G[190] G[188] G[186] G[184] G[182] G[180] G[178] G[176] G[174] G[172] G[170] G[168] G[120] G[164] G[162] G[160] G[158] G[156] G[154] G[152] G[150] G[148] G[146] G[144] G[142] G[140] G[138] G[136] G[134] G[132] G[120] G[128] G[126] G[124] G[122] G[120] G[118] G[116] G[114] G[112] X Y -7312 120 -7328 233 -7344 120 -7360 233 -7376 120 -7392 233 -7408 120 -7424 233 -7440 120 -7456 233 -7472 120 -7488 233 -7504 120 -7520 233 -7536 120 -7552 233 -7568 120 -7584 233 -7600 120 -7616 233 -7632 120 -7648 233 -7664 120 -7680 233 -7696 120 -7712 233 -7728 120 -7744 233 -7760 120 -7776 233 -7792 120 -7808 233 -7824 120 -7840 233 -7856 120 -7872 233 -7888 120 -7904 233 -7920 120 -7936 233 -7952 120 -7968 233 -7984 120 -8000 233 -8016 120 -8032 233 -8048 120 -8064 233 -8080 120 -8096 233 -8112 120 -8128 233 -8144 120 -8160 233 -8176 120 -8192 233 -8208 120 -8224 233 -8240 120 -8256 233 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 22 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 NO. 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1233 1280 Pad Name G[110] G[108] G[106] G[104] G[102] G[100] G[98] G[96] G[94] G[92] G[90] G[88] G[86] G[84] G[82] G[80] G[78] G[76] G[74] G[72] X Y -8272 120 -8288 233 -8304 120 -8320 233 -8336 120 -8352 233 -8368 120 -8384 233 -8400 120 -8416 233 -8432 120 -8448 233 -8464 120 -8480 233 -8496 120 -8512 233 -8528 120 -8544 233 -8560 120 -8576 233 NO. 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1200 Pad Name G[70] G[68] G[66] G[64] G[62] G[60] G[58] G[56] G[54] G[52] G[50] G[48] G[46] G[44] G[42] G[40] G[38] G[36] G[34] G[32] X Y -8592 120 -8608 233 -8624 120 -8640 233 -8656 120 -8672 233 -8688 120 -8704 233 -8720 120 -8736 233 -8752 120 -8768 233 -8784 120 -8800 233 -8816 120 -8832 233 -8848 120 -8864 233 -8880 120 -8896 233 NO. 1201 1202 1203 1204 1205 1206 1207 1208 1209 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 Pad Name G[30] G[28] G[26] G[24] G[22] G[20] G[18] G[16] G[14] G[12] G[10] G[8] G[6] G[4] G[2] VGLDMY4 DUMMYR28 DUMMYR29 DUMMY30 DUMMY31 X Y -8912 120 -8928 233 -8944 120 -8960 233 -8976 120 -8992 233 -9008 120 -9024 233 -9040 120 -9056 233 -9072 120 -9088 233 -9104 120 -9120 233 -9136 120 -9152 233 -9168 120 -9184 233 -9200 120 -9216 233 16 16 16 94 S1 ~ S720 G1 ~ G320 DUMMY18~31 VGMMA1, 62 VGLDMY1~4 94 19 Unit: um The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 23 of 112 Version: 0.08 I/O Pads Alignment mark a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 50 20 50 ILI9335 Pad Pump Pad Pump 80 Min. 70 Unit: um 5 5 20 20 25 25 30 30 25 25 5 5 Alignment mark X Y 1 -9301 226 2 9301 226 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 24 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 6. Block Description MPU System Interface ILI9335 supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports and serial peripheral interface (SPI). The interface mode is selected by setting the IM[3:0] pins. ILI9335 has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR). The IR is the register to store index information from control registers and the internal GRAM. The WDR is the register to temporarily store data to be written to control registers and the internal GRAM. The RDR is the register to temporarily store data read from the GRAM. Data from the MPU to be written to the internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal operation. Data are read via the RDR from the internal GRAM. Therefore, invalid data are read out to the data bus when the ILI9335 read the first data from the internal GRAM. Valid data are read out after the ILI9335 performs the second read operation. Registers are written consecutively as the register execution time. Registers selection by system interface (8-/9-/16-/18-bit bus width) Function Write an index to IR register Write to control registers or the internal GRAM by WDR register. Read from the internal GRAM by RDR register. I80 RS nWR nRD 0 0 1 1 0 1 1 1 0 Registers selection by the SPI system interface Function Write an index to IR register Write to control registers or the internal GRAM by WDR register. Read from the internal GRAM by RDR register. R/W RS 0 0 0 1 1 1 Parallel RGB Interface ILI9335 supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture. When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK. In RGB interface mode, data (DB17-0) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data. In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal. Display data are written to the internal GRAM via the system interface. In this case, there are constraints in speed and method in writing data to the internal RAM. For details, see the “External Display Interface” section. The ILI9335 allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)). The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 25 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Bit Operation The ILI9335 supports a write data mask function for selectively writing data to the internal RAM in units of bits and a logical/compare operation to write data to the GRAM only when a condition is met as a result of comparing the data and the compare register bits. For details, see “Graphics Operation Functions”. Address Counter (AC) The address counter (AC) gives an address to the internal GRAM. When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC. As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM. Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 172,800 (240 x 320x 18/8) bytes with 18 bits per pixel. Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 262,144 colors. For details, see the “γ-Correction Register” section. Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM. The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other. Oscillator (OSC) ILI9335 generates RC oscillation with an internal oscillation resistor. The frame rate is adjusted by the register setting. LCD Driver Circuit The LCD driver circuit of ILI9335 consists of a 720-output source driver (S1 ~ S720) and a 320-output gate driver (G1~G320). Display pattern data are latched when the 720th bit data are input. The latched data control the source driver and generate a drive waveform. The gate driver for scanning gate lines outputs either VGH or VGL level. The shift direction of 720 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit. The scan mode by the gate driver is set with the SM bit. These bits allow setting an appropriate scan method for an LCD module. LCD Driver Power Supply Circuit The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for driving an LCD The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 26 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7. System Interface 7.1. Interface Specifications ILI9335 has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture. User can select an optimum interface to display the moving or still picture with efficient data transfer. All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred. User can only update a sub-range of GRAM by using the window address function. ILI9335 also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen. In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, DOTCLK and data bus DB[17:0]. In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC). The VSYNC interface mode enables to display the moving picture display through the system interface. In this case, there are some constraints of speed and method to write data to the internal RAM. ILI9335 operates in one of the following 4 modes. The display mode can be switched by the control register. When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces. Operation Mode Internal operating clock only (Displaying still pictures) RAM Access Setting (RM) System interface (RM = 0) RGB interface (1) (Displaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) RGB interface (RM = 1) System interface (RM = 0) VSYNC interface (Displaying moving pictures) System interface (RM = 0) Note 1) Registers are set only via the system interface. Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously. Display Operation Mode (DM[1:0]) Internal operating clock (DM[1:0] = 00) RGB interface (DM[1:0] = 01) RGB interface (DM[1:0] = 01) VSYNC interface (DM[1:0] = 01) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 27 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 System Interface System 18/16/6 RGB Interface nCS RS nWR nRD DB[17:0] ILI9335 ENABLE VSYNC HSYNC DOTCLK Figure1 System Interface and RGB Interface connection 7.2. Input Interfaces The following are the system interfaces available with the ILI9335. The interface is selected by setting the IM[3:0] pins. The system interface is used for setting registers and GRAM access. IM3 IM2 IM1 IM0/ID Interface Mode 0 0 0 0 Setting invalid 0 0 0 1 Setting invalid 0 0 1 0 i80-system 16-bit interface 0 0 1 1 i80-system 8-bit interface 0 1 0 ID Serial Peripheral Interface (SPI) 0 1 1 * Setting invalid 1 0 0 0 Setting invalid 1 0 0 1 Setting invalid 1 0 1 0 i80-system18-bit interface 1 0 1 1 i80-system 9-bit interface 1 1 * * Setting invalid DB Pin DB[17:10], DB[8:1] DB[17:10] SDI, SDO (DB[1:0]) DB[17:0] DB[17:9] The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 28 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 7.2.1. i80/18-bit System Interface The i80/18-bit system interface is selected by setting the IM[3:0] as “1010” levels. ILI9335 nCS System A2 nWR nRD D[31:0] nCS RS nWR nRD DB[17:0] 18 18-bit S ys te m Inte rfa ce (262K colors ) TRI=0, DFM[1:0]=00 Input Da ta DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Da ta Re gis te r WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure2 18-bit System Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 29 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.2.2. i80/16-bit System Interface The i80/16-bit system interface is selected by setting the IM[3:0] as “0010” levels. The 262K or 65K color can be display through the 16-bit MPU interface. When the 262K color is displayed, two transfers (1st transfer: 2 bits, 2nd transfer: 16 bits or 1st transfer: 16 bits, 2nd transfer: 2 bits) are necessary for the 16-bit CPU interface. TRI DFM 0 * 1 0 1 1 16-bit MP U S ys te m Inte rfa ce Da ta Forma t system 16-bit interface (1 transfers/pixel) 65,536 colors 1s t Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 16-bit interface (2 transfers/pixel) 262,144 colors 1s t Tra ns fe r 2nd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 16-bit interface (2 transfers/pixel) 262,144 colors 1s t Tra ns fe r 2nd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 2 1 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure3 16-bit System Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 30 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.2.3. i80/9-bit System Interface The i80/9-bit system interface is selected by setting the IM[3:0] as “1011” and the DB17~DB9 pins are used to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first. The unused DB[8:0] pins must be tied to GND. System nCS A1 nWR nRD D[8:0] nCS RS nWR nRD DB[17:9] 9 9-bit S ys te m Inte rfa ce (262K colors ) TRI=0, DFM[1:0]=00 Input Da ta 1 s t Tra ns fe r (Uppe r bits ) 2nd Tra ns fe r (Lowe r bits ) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9 Write Da ta Re gis te r WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure4 9-bit System Interface Data Format 7.2.4. i80/8-bit System Interface The i80/8-bit system interface is selected by setting the IM[3:0] as “0011” and the DB17~DB10 pins are used to transfer the data. When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first. The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first. The written data is expanded into 18 bits internally (see the figure below) and then written into GRAM. The unused DB[9:0] pins must be tied to GND. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 31 of 112 Version: 0.08 TRI DFM 0 * 1 0 1 1 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8-bit MP U S ys te m Inte rfa ce Da ta Forma t system 8-bit interface (2 transfers/pixel) 65,536 colors 1s t Tra ns fe r DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 2nd Tra ns fe r DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 8-bit interface (3 transfers/pixel) 262,144 colors 1s t Tra ns fe r 2nd Tra ns fe r 3rd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 8-bit interface (3 transfers/pixel) 262,144 colors 1s t Tra ns fe r 2nd Tra ns fe r 3rd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure5 8-bit System Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 32 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.3. Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is selected by setting the IM[3:0] pins as “010x” level. The chip select pin (nCS), the serial transfer clock pin (SCL), the serial data input pin (SDI) and the serial data output pin (SDO) are used in SPI mode. The ID pin sets the least significant bit of the identification code. The DB[17:0] pins, which are not used, must be tied to GND. The SPI interface operation enables from the falling edge of nCS and ends of data transfer on the rising edge of nCS. The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte. When the start byte is matched, the subsequent data is received by ILI9335. The seventh bit of start byte is RS bit. When RS = “0”, either index write operation or status read operation is executed. When RS = “1”, either register write operation or RAM read/write operation is executed. The eighth bit of the start byte is used to select either read or write operation (R/W bit). Data is written when the R/W bit is “0” and read back when the R/W bit is “1”. After receiving the start byte, ILI9335 starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit. All the registers of the ILI9335 are 16-bit format and receive the first and the second byte datat as the upper and the lower eight bits of the 16-bit register respectively. In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6th byte of read back data. Start Byte Format Transferred bits S 1 2 3 4 5 Start byte format Transfer start Device ID code 0 1 1 1 0 Note: ID bit is selected by setting the IM0/ID pin. 6 7 8 RS R/W ID 1/0 1/0 RS and R/W Bit Function RS R/W Function 0 0 Set an index register 0 1 Read a status 1 0 Write a register or GRAM data 1 1 Read a register or GRAM data The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 33 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 S e ria l P e riphe ra l Inte rfa ce for re gis te r a cce s s S P I Input Da ta D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 Re gis te r Da ta IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 DDDDDDDD 7 6 5 4 3 2 1 0 IB IB IB IB IB IB IB IB 7 6 5 4 3 2 1 0 S e ria l P e riphe ra l Inte rfa ce 65K colors Input Da ta D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 DDDDDDDD 7 6 5 4 3 2 1 0 Write Da ta Re gis te r WD 17 WD 16 WD 15 WD 14 WD 13 WD 12 WD 11 WD 10 WD 9 WD 8 WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 WD 0 GRAM Da ta RGB m a pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure 6 Data Format of SPI Interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 34 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 (a) Basic data transmission through SPI Start End nCS (Input) SCL (Input) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDI (Input) SDO (Output) 0 1 1 1 0 ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Start Byte Index register, registers setting, and GRAM write D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Status, registers read and GRAM read (b) Consecutive data transmission through SPI Start nCS (Input) SCL (Input) SDI (Input) 1 89 16 17 24 25 32 Start Byte Register 1 upper eight bits Register 1 lower eight bits Note: The first byte after the start byte is always the upper eight bits . Register 2 upper eight bits Register 1 execution time (c) GRAM data read transmission Start nCS (Input) Register 2 lower eight bits End SCL (Input) SDI (Input) SDO (Output) Start Byte RS=1, RW=1 Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 Note: Five bytes of invalid dummy data read after the start byte . RAM read upper byte RAM read lower byte (d) Status/registers read transmission Start End nCS (Input) SCL (Input) SDI (Input) SDO (Output) 1 89 16 17 24 Start Byte Register 1 upper eight bits Register 1 lower eight bits Note: One byte of invalid dummy data read after the start byte . Figure7 Data transmission through serial peripheral interface (SPI) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 35 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 (e) Basic data transmission through SPI Start End nCS (Input) SCL (Input) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SDI (Input) SDO (Output) 0 1 1 1 0 ID RS RW D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Start Byte GRAM data write D23 D22 D21 D120 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GRAM data read (f) GRAM data write transmission Start nCS (Input) SCL (Input) SDI (Input) SDO (Output) Start Byte RAM data 1 1st transfer RAM data 1 2nd transfer RAM data 1 3rd transfer RAM data 2 1st transfer Note: Five bytes of invalid dummy data read after the start byte. GRAM Data (1) execution time RAM data 2 2nd transfer End RAM data 2 3rd transfer GRAM Data (2) execution time (g) GRAM data read transmission Start End nCS (Input) SCL (Input) SDI (Input) SDO (Output) Start Byte RS=1, RW=1 Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 Note: Five bytes of invalid dummy data read after the start byte. RAM read 1st byte RAM read 2nd byte RAM read 3rd byte RAM data transfer in SPI mode when TRI=1 and DFM[1:0]=10. Figure8 Data transmission through serial peripheral interface (SPI), TRI=”1” and DFM=”10”) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 36 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.4. VSYNC Interface ILI9335 supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the i80 system interface. When the VSYNC interface is selected to display a moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting DM[1:0] = “10” and RM = “0”. MPU VSYNC nCS RS nWR DB[17:0] Figure9 Data transmission through VSYNC interface) In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal. All display data are stored in GRAM to minimize total data transfer required for moving picture display. VSYNC Write data to RAM through system interface Display operation synchronized with internal clocks Rewriting screen data Rewriting screen data Figure10 Moving picture data transmission through VSYNC interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 37 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color VSYNC Back porch (14 lines) RAM Write Display operation Display (320 lines) Front porch (2 lines) Black period ILI9335 Figure11 Operation through VSYNC Interface The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula. Internal clock frequency (fosc.) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (FP) + BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation. Minimum RAM write speed(HZ) 240 x DisplayLines (NL) [(BackPorch(BP)+DisplayLines(NL) - margins] x 16 (clocks) x 1/fosc Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account. An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below. [Example] Display size: 240 RGB × 320 lines Lines: 320 lines (NL = 1000111) Back porch: 14 lines (BP = 1110) Front porch: 2 lines (FP = 0010) Frame frequency: 60 Hz Frequency fluctuation: 10% Internal oscillator clock (fosc.) [Hz] = 60 x [320+ 2 + 14] x 16 clocks x (1.1/0.9) ≒ 394KHz The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 38 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration. In the above example, the calculated internal clock frequency with ±10% margin variation is considered and ensures to complete the display operation within one VSYNC cycle. The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation. Minimum speed for RAM writing [Hz] > 240 x 320 x 394K / [ (14 + 320 – 2)lines x 16clocks] ≒ 5.7 MHz The above theoretical value is calculated based on the premise that the ILI9335 starts to write data into the internal GRAM on the falling edge of VSYNC. There must at least be a margin of 2 lines between the physical display line and the GRAM line address where data writing operation is performed. The GRAM write speed of 5.7MHz or more will guarantee the completion of GRAM write operation before the ILI9335 starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker. Notes in using the VSYNC interface 1. The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration. 2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display. 3. When switching from the internal clock operation mode (DM[1:0] = “00”) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, i.e. after completing the display of the frame. 4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to “0” to transfer display data. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 39 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 System Interface Mode to VSYNC interface mode VSYNC interface mode to System Interface Mode System Interface Opeartion through VSYNC interface Set AM=0 Set GRAM Address Set DM[1:0]=10, RM=0 for VSYNC interface mode Set index register to R22h Wait more than 1 frame Write data to GRAM through VSYNC interface Display operation in synchronization with internal clocks DM[1:0], RM become enable after completion of displaying 1 frame Display operation in synchronization with VSYNC Set DM[1:0]=00, RM=0 for system interface mode Wait more than 1 frame System Interface Display operation in synchronization with VSYNC DM[1:0], RM become enable after completion of displaying 1 frame Display operation in synchronization with internal clocks Note: input VSYNC for more than 1 frame period after setting the DM, RM register. Opeartion through VSYNC interface Figure12 Transition flow between VSYNC and internal clock operation modes The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 40 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.5. RGB Input Interface The RGB Interface mode is available for ILI9335 and the interface is selected by setting the RIM[1:0] bits as following table. RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface 18-bit RGB Interface 16-bit RGB Interface 6-bit RGB Interface Setting prohibited DB pins DB[17:0] DB[17:13], DB[11:1] DB[17:12] 18-bit RGB Inte rfa ce (262K colors ) Input Da ta DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write Da ta Re gis te r WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 16-bit RGB Inte rfa ce (65K colors ) Input Da ta DB DB DB DB DB 17 16 15 14 13 DB DB DB DB DB DB DB DB DB DB DB 11 10 9 8 7 6 5 4 3 2 1 Write Da ta Re gis te r WD WD WD WD WD 17 16 15 14 13 WD WD WD WD WD WD WD WD WD WD WD 11 10 9 8 7 6 5 4 3 2 1 GRAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 6-bit RG B Inte rfa ce (262K colors ) Input Da ta 1s t Tra ns fe r 2nd Tra ns fe r 3rd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12 Write Da ta Re gis te r WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GRAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure13 RGB Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 41 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.5.1. RGB Interface The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and DOTCLK signals. The RGB interface transfers the updated data to GRAM and the update area is defined by the window address function. The back porch and front porch are used to set the RGB interface timing. VSYNC HSYNC DOTCLK ENABLE DB[17:0] RAM data display area Moving picture display area Back porch period (BP[3:0]) Display period (NL[4:0] Front porch period (FP[3:0]) Note 1: Front porch period continues until the next input of VSYNC. Note 2: Input DOTCLK throughout the operation. Note 3: Supply the VSYNC, HSYNC and DOTCLK with frequency that can meet the resolution requirement of panel. Figure14 GRAM Access Area by RGB Interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 42 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 7.5.2. RGB Interface Timing The timing chart of 18-/16-bit RGB interface mode is shown as follows. Back porch 1 frame VSYNC VLW >= 1H Front porch HSYNC DOTCLK ENABLE DB[17:0] ILI9335 HSYNC HLW >= 3 DOTCLK // 1H // DOTCLK DTST >= HLW ENABLE // DB[17:0] Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time N t 1 U th hi h d it d (HWM 1) t it d t th h th RGB i t f Figure15 Timing Chart of Signals in 18-/16-bit RGB Interface Mode The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 43 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color The timing chart of 6-bit RGB interface mode is shown as follows. Back porch 1 frame VSYNC VLW >= 1H Front porch HSYNC DOTCLK ENABLE DB[17:12] ILI9335 HSYNC HLW >= 3 DOTCLK // 1H DOTCLK ENABLE DB[17:12] // DTST >= HLW // RGB RGB // B RGB VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time Valid data Note 1) In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with DOTCLKs. Note 2) In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and ENABLE to 3 multiples of DOTCLKs. Figure16 Timing chart of signals in 6-bit RGB interface mode The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 44 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.5.3. Moving Picture Mode ILI9335 has the RGB interface to display moving picture and incorporates GRAM to store display data, which has following merits in displaying a moving picture. • The window address function defined the update area of GRAM. • Only the moving picture area of GRAM is updated. • When display the moving picture in RGB interface mode, the DB[17:0] can be switched as system interface to update still picture area and registers, such as icons. RAM access via a system interface in RGB-I/F mode ILI9335 allows GRAM access via the system interface in RGB interface mode. In RGB interface mode, data are written to the internal GRAM in synchronization with DOTCLK and ENABLE signals. When write data to the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the system interface to update the registers (RM = “0”) and the still picture of GRAM. When restart RAM access in RGB interface mode, wait one read/write cycle and then set RM = “1” and the index register to R22h to start accessing RAM via the RGB interface. If RAM accesses via two interfaces conflicts, there is no guarantee that data are written to the internal GRAM. The following figure illustrates the operation of the ILI9335 when displaying a moving picture via the RGB interface and rewriting the still picture RAM area via the system interface. VSYNC ENABLE DOTCLK DB[17:0] Update a frame Still Picture Area Moving Picture Area Update a frame Set IR to R22h Update moving picture area Set RM=0 Set AD[15:0] Set IR to R22h Update display data in other than the moving picture area Set AD[15:0] Set RM=1 Set IR to R22h Update moving picture area Figure17 Example of update the still and moving picture The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 45 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.5.4. 6-bit RGB Interface The 6-bit RGB interface is selected by setting the RIM[1:0] bits to “10”. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal GRAM in synchronization with the display operation via 6-bit RGB data bus (DB[17:12]) according to the data enable signal (ENABLE). Unused pins (DB[11:0]) must be fixed at GND level. Registers can be set by the system interface (i80/SPI). R G B in te rfa c e with 6 -b it d a ta b u s 1st Transfer 2nd Transfer 3rd Transfer Input Da ta DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12 RGB As s ignm e nt R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Data transfer synchronization in 6-bit RGB interface mode ILI9335 has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode. The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC. If a mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at the start of the frame (i.e. on the falling edge of VSYNC) to restart data transfer in the correct order from the next frame. This function is expedient for moving picture display, which requires consecutive data transfer in light of minimizing effects from failed data transfer and enabling the system to return to a normal state. Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK). Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data transfer correctly. Otherwise it will affect the display of that frame as well as the next frame. HS YNC E N ABLE DO TC LK D B[1 7 :1 2 ] 1 s t 2 nd 3 rd 1s t 2 nd 3 rd 1 s t 2 nd 3 rd 1s t 2 nd 3 rd Tra ns fe r s ynchroniza tion The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 46 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.5.5. 16-bit RGB Interface The 16-bit RGB interface is selected by setting the RIM[1:0] bits to “01”. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in synchronization with the display operation via 16-bit RGB data bus (DB17-13, DB11-1) according to the data enable signal (ENABLE). Registers are set only via the system interface. 16-bit RG B Inte rfa ce (65K colors ) Input Da ta DB DB DB DB DB 17 16 15 14 13 DB DB DB DB DB DB DB DB DB DB DB 11 10 9 8 7 6 5 4 3 2 1 Write Da ta Re gis te r WD WD WD WD WD 17 16 15 14 13 WD WD WD WD WD WD WD WD WD WD WD 11 10 9 8 7 6 5 4 3 2 1 GRAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 7.5.6. 18-bit RGB Interface The 18-bit RGB interface is selected by setting the RIM[1:0] bits to “00”. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transferred to the internal RAM in synchronization with the display operation via 18-bit RGB data bus (DB[17:0]) according to the data enable signal (ENABLE). Registers are set only via the system interface. R G B inte rfa c e with 18 -bit d a ta b us Input Da ta DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGB As s ignm e nt R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Notes in using the RGB Input Interface 1. The following are the functions not available in RGB Input Interface mode. Function Partial display Scroll function Interlaced scan Graphics operation function RGB interface Not available Not available Not available Not available I80 system interface Available Available Available Available 2. VSYNC, HSYNC, and DOTCLK signals must be supplied throughout a display operation period. 3. The periods set with the NO[1:0] bits (gate output non-overlap period), STD[1:0] bits (source output delay period) and EQ[1:0] bits (equalization period) are not based on the internal clock but based on DOTCLK in The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 47 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 RGB interface mode. 4. In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a DOTCLK input. In other words, it takes 3 DOTCLK inputs to transfer one pixel. Be sure to complete data transfer in units of 3 DOTCLK inputs in 6-bit RGB interface mode. 5. In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are transferred in units of 3 DOTCLK. Accordingly, set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC, ENABLE, DB[17:0]) to contain DOTCLK inputs of a multiple of 3 to complete data transfer in units of pixels. 6. When switching from the internal operation mode to the RGB Input Interface mode, or the other way around, follow the sequence below. 7. In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing one frame. 8. In RGB interface mode, a RAM address (AD[15:0]) is set in the address counter every frame on the falling edge of VSYNC. Figure18 Internal clock operation/RGB interface mode switching Set DM[1:0]=01, RM=0 with RGB interface mode Set AD[15;0] Set IR to R22h (GRAM data write) Write data to GRAM through system interface Write data to GRAM through system interface Set AD[15;0] Set DM[1:0]=01, RM=1 with RGB interface mode Set IR to R22h (GRAM data write) Figure19 GRAM access between system interface and RGB interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 48 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 7.6. Interface Timing The following are diagrams of interfacing timing with LCD panel control signals in internal operation and RGB interface modes. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 49 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 VS YNC HS YNC DO TC LK E NABLE DB[1 7 :0 ] // // // // // 1 2345 318 319 320 1234 F LM G1 G2 G320 S [720:1] VC O M …. . // 1 2345 318 319 320 Figure20 Relationship between RGB I/F signals and LCD Driving Signals for Panel The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 50 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8. Register Descriptions 8.1. Registers Access ILI9335 adopts 18-bit bus interface architecture for high-performance microprocessor. All the functional blocks of ILI9335 starts to work after receiving the correct instruction from the external microprocessor by the 18-, 16-, 9-, 8-bit interface. The index register (IR) stores the register address to which the instructions and display data will be written. The register selection signal (RS), the read/write signals (nRD/nWR) and data bus D17-0 are used to read/write the instructions and data of ILI9335. The registers of the ILI9335 are categorized into the following groups. 1. Specify the index of register (IR) 2. Read a status 3. Display control 4. Power management Control 5. Graphics data processing 6. Set internal GRAM address (AC) 7. Transfer data to/from the internal GRAM (R22) 8. Internal grayscale γ-correction (R30 ~ R39) Normally, the display data (GRAM) is most often updated, and in order since the ILI9335 can update internal GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the window address function, there are fewer loads on the program in the microprocessor. As the following figure shows, the way of assigning data to the 16 register bits (D[15:0]) varies for each interface. Send registers in accordance with the following data transfer format. S e ria l P e rip h e ra l In te rfa c e fo r re g is te r a c c e s s S P I Input Da ta D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 Re gis te r Da ta D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 DDDDDDDD 7 6 5 4 3 2 1 0 DDDDDDDD 7 6 5 4 3 2 1 0 Figure21 Register Setting with Serial Peripheral Interface (SPI) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 51 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 i80/M68 s ys te m 18-bit da ta bus inte rfa ce Da ta Bus (D B[1 7 :0 ]) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Re gis te r Bit (D [1 5 :0 ]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 i80/M68 s ys te m 16-bit da ta bus inte rfa ce Da ta Bus (D B[1 7 :1 0 ]), (D B[8 :1 ]) DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 Re gis te r Bit (D [1 5 :0 ]) D15 D14 D13 D12 D11 D10 D9 D8 DB DB DB DB DB DB DB DB 87654321 D7 D6 D5 D4 D3 D2 D1 D0 i80/M68 s ys te m 9-bit da ta bus inte rfa ce Da ta Bus (D B[1 7 :9 ]) 1st Tra ns fe r 2nd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9 Re gis te r Bit (D [1 5 :0 ]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 i80/M68 s ys te m 8-bit da ta bus inte rfa ce /S e ria l pe riphe ra l inte rfa ce (2/3 tra ns m is s ion) Da ta Bus (D B[1 7 :1 0 ]) 1s t Tra ns fe r DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 2nd Tra ns fe r DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 Re gis te r Bit (D [1 5 :0 ]) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure22 Register setting with i80 System Interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 52 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color i80 18-/16-bit S ys te m Bus Inte rfa ce Tim ing (a ) Write to re gis te r nCS RS nRD nWR D B [1 7 :0 ] Write re gis te r “inde x" Write re gis te r “da ta " (b) Re a d from re gis te r nCS RS nRD nWR D B [1 7 :0 ] Write re gis te r “inde x" R e a d re gis te r “da ta " ILI9335 i80 9-/8-bit S ys te m Bus Inte rfa ce Tim ing (a ) Write to re gis te r nCS RS nRD nWR D B [1 7 :1 0 ] “00 h" Write re gis te r “inde x" Write re gis te r “high byte da ta " Write re gis te r “low byte da ta " (b) Re a d from re gis te r nCS RS nRD nWR D B [1 7 :1 0 ] “00 h" Write re gis te r “inde x" R e a d re gis te r “high byte da ta " Re a d re gis te r “low byte da ta " Figure 23 Register Read/Write Timing of i80 System Interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 53 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2. Instruction Descriptions No. Registers Name R/W RS IR Index Register W0 00h Driver Code Read RO 1 01h Driver Output Control 1 W1 02h LCD Driving Control W1 03h Entry Mode W1 05h 16 bits data format control W1 07h Display Control 1 W1 08h Display Control 2 W1 09h Display Control 3 W1 0Ah Display Control 4 W1 0Ch RGB Display Interface Control 1 W 1 0Dh Frame Maker Position W1 0Fh RGB Display Interface Control 2 W 1 10h Power Control 1 W1 11h Power Control 2 W1 12h Power Control 3 W1 13h Power Control 4 W1 20h Horizontal GRAM Address Set W 1 21h Vertical GRAM Address Set W1 22h Write Data to GRAM W1 29h Power Control 7 2Bh Frame Rate and Color Control 30h Gamma Control 1 31h Gamma Control 2 32h Gamma Control 3 35h Gamma Control 4 36h Gamma Control 5 37h Gamma Control 6 38h Gamma Control 7 39h Gamma Control 8 3Ch Gamma Control 9 3Dh Gamma Control 10 50h Horizontal Address Start W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 W1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 - - - - - - - - ID7 ID6 ID5 ID4 ID3 ID2 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 0 0 0 SM 0 SS 0 0 0 0 0 0 0 0 0 0 0 0 B/C 0 0 0 0 0 0 0 TRI DFM 0 BGR 0 0 0 0 ORG 0 I/D1 I/D0 AM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTDE1 PTDE0 0 0 0 BASEE 0 0 GON DTE CL 0 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP7 BP6 BP5 BP4 BP3 BP2 0 0 0 0 0 PTS2 PTS1 PTS0 0 0 PTG1 PTG0 ISC3 ISC2 0 0 0 0 0 0 0 0 0 0 0 0 FMARKOE FMI2 0 ENC2 ENC1 ENC0 0 0 0 RM 0 0 DM1 DM0 0 0 0 0 0 0 0 0 0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 0 0 0 0 0 0 0 0 0 0 0 VSPL HSPL 0 0 0 0 SAP 0 BT2 BT1 BT0 APE AP2 AP1 AP0 0 0 0 0 0 0 0 DC12 DC11 DC10 0 DC02 DC01 DC00 0 VC2 0 0 0 0 0 0 0 0 VCIRE 0 0 0 VRH3 VRH2 0 0 0 VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD7 AD6 AD5 AD4 AD3 AD2 0 0 0 0 0 0 0 AD16 AD15 AD14 AD13 AD12 AD11 AD10 RAM write data (WD17-0) / read data (RD17-0) bits are transferred via different data bus lines according to the selected interfaces. D1 ID1 0 0 0 0 EPF1 D1 BP1 ISC1 FMI1 RIM1 FMP1 EPL SLP VC1 VRH1 0 AD1 AD9 D0 ID0 1 0 0 0 EPF0 D0 BP0 ISC0 FMI0 RIM0 FMP0 DPL STB VC0 VRH0 0 AD0 AD8 0 0 0 0 0 0 0 0 0 0 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 0 0 0 0 0 0 0 0 0 0 0 0 FRS[3] FRS[2] FRS[1] FRS[0] 0 0 0 0 0 KP1[2] KP1[1] KP1[0] 0 0 0 0 0 KP0[2] KP0[1] KP0[0] 0 0 0 0 0 KP3[2] KP3[1] KP3[0] 0 0 0 0 0 KP2[2] KP2[1] KP2[0] 0 0 0 0 0 KP5[2] KP5[1] KP5[0] 0 0 0 0 0 KP4[2] KP4[1] KP4[0] 0 0 0 0 0 RP1[2] RP1[1] RP1[0] 0 0 0 0 0 RP0[2] RP0[1] RP0[0] 0 0 0 VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[0] 0 0 0 0 VRP0[3] VRP0[2] VRP0[1] VRP0[0] 0 0 0 0 0 KN1[2] KN1[1] KN1[0] 0 0 0 0 0 KN0[2] KN0[1] KN0[0] 0 0 0 0 0 KN3[2] KN3[1] KN3[0] 0 0 0 0 0 KN2[2] KN2[1] KN2[0] 0 0 0 0 0 KN5[2] KN5[1] KN5[0] 0 0 0 0 0 KN4[2] KN4[1] KN4[0] 0 0 0 0 0 RN1[2] RN1[1] RN1[0] 0 0 0 0 0 RN0[2] RN0[1] RN0[0] 0 0 0 VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[0] 0 0 0 0 VRN0[3] VRN0[2] VRN0[1] VRN0[0] 0 0 0 0 0 0 0 0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 54 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 No. Registers Name R/W RS Position 51h Horizontal Address End Position W 1 52h Vertical Address Start Position W 1 53h Vertical Address End Position W1 60h Driver Output Control 2 W1 61h Base Image Display Control W1 6Ah Vertical Scroll Control W1 80h Partial Image 1 Display Position W 1 81h Partial Image 1 Area (Start Line) W 1 82h Partial Image 1 Area (End Line) W 1 83h Partial Image 2 Display Position W 1 84h Partial Image 2 Area (Start Line) W 1 85h Partial Image 2 Area (End Line) W 1 90h Panel Interface Control 1 W1 92h Panel Interface Control 2 W1 95h Panel Interface Control 4 97h Panel Interface Control 5 W1 W1 A1h OTP VCM Programming Control W 1 A2h OTP VCM Status and Enable W1 A5h OTP Programming ID Key W1 E6h Deep stand by mode control W1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 GS 0 NL5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGM_ CNT1 KEY 15 0 PGM_ CNT0 KEY 14 0 VCM_ D5 KEY 13 0 0 0 0 NL4 0 0 0 0 0 0 0 0 0 0 0 0 0 VCM_ D4 KEY 12 0 0 0 0 NL3 0 0 0 0 0 0 0 0 0 0 0 NOWE3 OTP_ PGM_EN VCM_ D3 KEY 11 0 0 0 0 HEA7 HEA6 HEA5 0 0 VSA8 VSA7 VSA6 VSA5 0 0 VEA8 VEA7 VEA6 VEA5 NL2 NL1 NL0 0 0 SCN5 0 0 0 0 0 0 0 0 VL8 VL7 VL6 VL5 0 0 PTDP08 PTDP07 PTDP06 PTDP05 0 0 PTSA08 PTSA07 PTSA06 PTSA05 0 0 PTEA08 PTEA07 PTEA06 PTEA05 0 0 PTDP18 PTDP17 PTDP16 PTDP15 0 0 PTSA18 PTSA17 PTSA16 PTSA15 0 0 PTEA18 PTEA17 PTEA16 PTEA15 0 DIVI1 DIVI00 0 0 0 NOWI2 NOWI1 NOWI0 0 0 0 0 DIVE1 DIVE0 0 0 0 NOWE2 NOWE1 NOWE0 0 0 0 VCM_ D2 KEY 10 0 VCM_ D1 KEY 9 0 VCM_ D0 KEY 8 0 0 0 0 KEY 7 0 0 0 0 KEY 6 0 0 VCM_ OTP5 0 KEY 5 0 HEA4 VSA4 VEA4 SCN4 0 VL4 PTDP04 PTSA04 PTEA04 PTDP14 PTSA14 PTEA14 RTNI4 0 0 0 VCM_ OTP4 0 KEY 4 0 HEA3 VSA3 VEA3 SCN3 0 VL3 PTDP03 PTSA03 PTEA03 PTDP13 PTSA13 PTEA13 RTNI3 0 0 0 VCM_ OTP3 0 KEY 3 0 HEA2 HEA1 HEA0 VSA2 VSA1 VSA0 VEA2 VEA1 VEA0 SCN2 SCN1 SCN0 NDL VLE REV VL2 VL1 VL0 PTDP02 PTDP01 PTDP00 PTSA02 PTSA01 PTSA00 PTEA02 PTEA01 PTEA00 PTDP12 PTDP11 PTDP10 PTSA12 PTSA11 PTSA10 PTEA12 PTEA11 PTEA10 RTNI2 RTNI1 RTNI0 0 0 0 0 0 0 0 VCM_ OTP2 0 KEY 2 0 0 VCM_ OTP1 0 KEY 1 0 0 VCM_ OTP0 VCM_ EN KEY 0 DSTB The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 55 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.1. Index (IR) R/W RS W 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - - ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 The index register specifies the address of register (R00h ~ RFFh) or RAM which will be accessed. 8.2.2. ID code (R00h) R/W RS RO 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 The device code “9335”h is read out when read this register. 8.2.3. Driver Output Control (R01h) R/W RS W 1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 SM 0 SS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS: Select the shift direction of outputs from the source driver. When SS = 0, the shift direction of outputs is from S1 to S720 When SS = 1, the shift direction of outputs is from S720 to S1. In addition to the shift direction, the settings for both SS and BGR bits are required to change the assignment of R, G, B dots to the source driver pins. To assign R, G, B dots to the source driver pins from S1 to S720, set SS = 0. To assign R, G, B dots to the source driver pins from S720 to S1, set SS = 1. When changing SS or BGR bits, RAM data must be rewritten. SM: Sets the gate driver pin arrangement in combination with the GS bit (R60h) to select the optimal scan mode for the module. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 56 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 SM GS 0 0 0 1 Scan Direction Odd-number G319 G317 G320 G318 TFT Panel Even-number G3 G4 G1 G2 ILI9331 Odd-number G319 G317 G320 G318 TFT Panel Even-number G3 G4 G1 G2 ILI9331 Gate Output Sequence G1, G2, G3, G4, …,G316 G317, G318, G319, G320 G320, G319, G318, …, G6, G5, G4, G3, G2, G1 1 0 G2 to G320 G1, G3, G5, G7, …,G311 G313, G315, G317, G319 G2, G4, G6, G8, …,G312 G314, G316, G318, G320 G1 to G319 1 1 G2 to G320 G320, G318, G316, …, G10, G8, G6, G4, G2 G319, G317, G315, …, G9, G78, G5, G3, G1 G1 to G319 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 57 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.4. LCD Driving Wave Control (R02h) R/W RS W 1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 B/C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .B/C 0 : Frame/Field inversion 1 : Line inversion 8.2.5. Entry Mode (R03h) R/W RS W 1 Default D15 D14 D13 D12 D11 D10 D9 TRI DFM 0 BGR 0 0 0 0 0 0 0 0 0 0 D8 D7 D6 0 ORG 0 00 0 D5 D4 D3 D2 D1 D0 I/D1 I/D0 AM 0 0 0 1 1 0000 AM Control the GRAM update direction. When AM = “0”, the address is updated in horizontal writing direction. When AM = “1”, the address is updated in vertical writing direction. When a window area is set by registers R50h ~R53h, only the addressed GRAM area is updated based on I/D[1:0] and AM bits setting. I/D[1:0] Control the address counter (AC) to automatically increase or decrease by 1 when update one pixel display data. Refer to the following figure for the details. I/D[1:0] = 00 I/D[1:0] = 01 Horizonta l : de cre m e nt Horizonta l : incre me nt Ve rtica l : de cre me nt Ve rtica l : de cre me nt I/D[1:0] = 10 I/D[1:0] = 11 Horizonta l : de cre me nt Horizonta l : incre me nt Ve rtica l : incre me nt Ve rtica l : incre me nt E AM = 0 E B B Horizonta l B B E E E AM = 1 E B B Ve rtica l B B E E Figure24 GRAM Access Direction Setting ORG Moves the origin address according to the ID setting when a window address area is made. This function is enabled when writing data with the window address area using high-speed RAM write. ORG = “0”: The origin address is not moved. In this case, specify the address to start write operation according to the GRAM address map within the window address area. ORG = “1”: The original address “00000h” moves according to the I/D[1:0] setting. Notes: 1. When ORG=1, only the origin address address”00000h” can be set in the RAM address set registers R20h, and R21h. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 58 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 2. In RAM read operation, make sure to set ORG=0. BGR Swap the R and B order of written data. BGR=”0”: Follow the RGB order to write the pixel data. BGR=”1”: Swap the RGB data to BGR in writing into GRAM. ILI9335 TRI When TRI = “1”, data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface. It is also possible to send data via the 16-bit interface or SPI in the transfer mode that realizes display in 262k colors in combination with DFM bits. When not using these interface modes, be sure to set TRI = “0”. DFM Set the mode of transferring data to the internal RAM when TRI = “1”. See the following figures for details. TRI DFM 0 * 16-bit MP U S ys te m Inte rfa ce Da ta Forma t system 16-bit interface (1 transfers/pixel) 65,536 colors 1s t Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 0 80-system 16-bit interface (2 transfers/pixel) 262,144 colors 1s t Tra ns fe r 2nd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 17 16 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 1 1 80-system 16-bit interface (2 transfers/pixel) 262,144 colors 1s t Tra ns fe r 2nd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 2 1 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure25 16-bit MPU System Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 59 of 112 Version: 0.08 TRI DFM 0 * 1 0 1 1 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8-bit MP U S ys te m Inte rfa ce Da ta Forma t system 8-bit interface (2 transfers/pixel) 65,536 colors 1s t Tra ns fe r DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 2nd Tra ns fe r DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 8-bit interface (3 transfers/pixel) 262,144 colors 1s t Tra ns fe r 2nd Tra ns fe r 3rd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 80-system 8-bit interface (3 transfers/pixel) 262,144 colors 1s t Tra ns fe r 2nd Tra ns fe r 3rd Tra ns fe r DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 17 16 15 14 13 12 17 16 15 14 13 12 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Figure26 8-bit MPU System Interface Data Format The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 60 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.6. 16bits Data Format Selection (R05h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPF1 EPF0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 61 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.7. Display Control 1 (R07h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 PTDE1 PTDE0 0 0 0 BASEE 0 0 GON DTE CL 0 D1 D0 0 0 0 0 0 00 0 00 0 0 0000 D[1:0] Set D[1:0]=”11” to turn on the display panel, and D[1:0]=”00” to turn off the display panel. A graphics display is turned on the panel when writing D1 = “1”, and is turned off when writing D1 = “0”. When writing D1 = “0”, the graphics display data is retained in the internal GRAM and the ILI9335 displays the data when writing D1 = “1”. When D1 = “0”, i.e. while no display is shown on the panel, all source outputs becomes the GND level to reduce charging/discharging current, which is generated within the LCD while driving liquid crystal with AC voltage. When the display is turned off by setting D[1:0] = “01”, the ILI9335 continues internal display operation. When the display is turned off by setting D[1:0] = “00”, the ILI9335 internal display operation is halted completely. In combination with the GON, DTE setting, the D[1:0] setting controls display ON/OFF. D1 D0 BASEE Source, VCOM Output ILI9335 internal operation 0 0 0 1 0 GND 1 GND Halt Operate 1 0 1 1 1 1 0 Non-lit display 0 Non-lit display 1 Base image display Operate Operate Operate Note: 1. data write operation from the microcontroller is performed irrespective of the setting of D[1:0] bits. 2. The D[1:0] setting is valid on both 1st and 2nd displays. 3. The non-lit display level from the source output pins is determined by instruction (PTS). CL When CL = “1”, the 8-color display mode is selected. CL Colors 0 262,144 1 8 GON and DTE Set the output level of gate driver G1 ~ G320 as follows GON 0 0 1 1 DTE 0 1 0 1 G1 ~G320 Gate Output VGH VGH VGL Normal Display BASEE Base image display enable bit. When BASEE = “0”, no base image is displayed. The ILI9335 drives liquid crystal at non-lit display level or displays only partial images. When BASEE = “1”, the base image is displayed. The D[1:0] setting has higher priority over the BASEE setting. PTDE[1:0] The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 62 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Partial image 2 and Partial image 1 enable bits PTDE1/0 = 0: turns off partial image. Only base image is displayed. PTDE1/0 = 1: turns on partial image. Set the base image display enable bit to 0 (BASEE = 0). 8.2.8. Display Control 2 (R08h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP0 BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 FP[7:0]/BP[7:0] The FP[7:0] and BP[7:0] bits specify the line number of front and back porch periods respectively. When setting the FP[7:0] and BP[7:0] value, the following conditions shall be met: BP + FP ≤ 256 lines FP ≥ 2 lines BP ≥ 2 lines FP[7:0] /BP[7:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah : 7Fh 80h 81h : FFh Number of lines for Front Porch Setting Prohibited Setting Prohibited 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines : 127 lines 128 lines Setting Prohibited : Setting Prohibited Number of lines for Back Porch Setting Prohibited Setting Prohibited 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines 10 lines : 127 lines 128 lines Setting Prohibited : Setting Prohibited VSYNC Back Porch Display Area Front Porch Note: The output timing to the LCD is delayed by 2 lines period from the input of synchronizing signal. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 63 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.9. Display Control 3 (R09h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 PTS2 PTS1 PTS0 0 0 PTG1 PTG0 ISC3 ISC2 ISC1 ISC0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 ISC[3:0]: Specify the scan cycle interval of gate driver in non-display area when PTG[1:0]=”10” to select interval scan. Then scan cycle is set as odd number from 0~29 frame periods. The polarity is inverted every scan cycle. ISC3 0 0 ISC2 0 0 ISC1 0 0 ISC0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 PTG[1:0] Set the scan mode in non-display area. Scan Cycle 0 frame 0 frame 3 frame 5 frame 7 frame 9 frame 11 frame 13 frame 15 frame 17 frame 19 frame 21 frame 23 frame 25 frame 27 frame 29 frame fFLM=60 Hz - 50ms 84ms 117ms 150ms 184ms 217ms 251ms 284ms 317ms 351ms 384ms 418ms 451ms 484ms PTG1 PTG0 Gate outputs in non-display area Source outputs in non-display area Vcom output 0 0 Normal scan Set with the PTS[2:0] bits VcomH/VcomL 0 1 Setting Prohibited - - 1 0 1 1 Interval scan Setting Prohibited Set with the PTS[2:0] bits - VcomH/VcomL - PTS[2:0] Set the source output level in non-display area drive period (front/back porch period and blank area between partial displays). When PTS[2] = 1, the operation of amplifiers which generates the grayscales other than V0 and V63 are halted. PTS[2:0] Source output level Grayscale amplifier Positive polarity Negative polarity in operation 000 V63 V0 V63 to V0 001 Setting Prohibited Setting Prohibited - 010 GND GND V63 to V0 011 Hi-Z Hi-Z V63 to V0 100 V63 V0 V63 and V0 101 Setting Prohibited Setting Prohibited - 110 GND GND V63 and V0 111 Hi-Z Hi-Z V63 and V0 Notes: 1. The power efficiency can be improved by halting grayscale amplifiers only in non-display drive period. 2. The gate output level in non-lit display area drive period is determined by PTG[1:0]. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 64 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.10. Display Control 4 (R0Ah) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 FMARKOE FMI2 FMI1 FMI0 0 0 0 0 0 0 000000 0 0 0 0 FMI[2:0] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate. FMARKOE When FMARKOE=1, ILI9335 starts to output FMARK signal in the output interval set by FMI[2:0] bits. FMI[2:0] 000 001 011 101 Others Output Interval 1 frame 2 frame 4 frame 6 frame Setting disabled 8.2.11. RGB Display Interface Control 1 (R0Ch) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 ENC2 ENC1 ENC0 0 0 0 RM 0 0 DM1 DM0 0 0 RIM1 RIM0 0 0 0 0 0 0 0 0 00 0 0 00 0 0 RIM[1:0] Select the RGB interface data width. RIM1 0 0 RIM0 0 1 RGB Interface Mode 18-bit RGB interface (1 transfer/pixel), DB[17:0] 16-bit RGB interface (1 transfer/pixel), DB[17:13] and DB[11:1] 1 0 6-bit RGB interface (3 transfers/pixel), DB[17:12] 1 1 Setting disabled Note1: Registers are set only by the system interface. Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch. DM[1:0] Select the display operation mode. DM1 0 0 DM0 0 1 Display Interface Internal system clock RGB interface 1 0 VSYNC interface 1 1 Setting disabled The DM[1:0] setting allows switching between internal clock operation mode and external display interface operation mode. However, switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited. RM Select the interface to access the GRAM. Set RM to “1” when writing display data by the RGB interface. RM Interface for RAM Access 0 System interface/VSYNC interface 1 RGB interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 65 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Display State Still pictures Operation Mode Internal clock operation Moving pictures RGB interface (1) Rewrite still picture area while RGB interface Displaying moving pictures. Moving pictures VSYNC interface RAM Access (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0) Note 1: Registers are set only via the system interface or SPI interface. Display Operation Mode (DM[1:0] Internal clock operation (DM[1:0] = 00) RGB interface (DM[1:0] = 01) RGB interface (DM[1:0] = 01) VSYNC interface (DM[1:0] = 10) Note 2: Refer to the flowcharts of “RGB Input Interface” section for the mode switch. ENC[2:0] Set the GRAM write cycle through the RGB interface ENC[2:0] 000 001 010 011 100 101 110 111 GRAM Write Cycle (Frame periods) 1 Frame 2 Frames 3 Frames 4 Frames 5 Frames 6 Frames 7 Frames 8 Frames 8.2.12. Frame Marker Position (R0Dh) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 EMP[8:0] Sets the output position of frame cycle (frame marker). When FMP[8:0]=0, a high-active pulse FMARK is output at the start of back porch period for one display line period (1H). Make sure the 9’h000 ≦ FMP ≦ BP+NL+FP FMP[8:0] 9’h000 9’h001 9’h002 9’h003 . . . 9’h175 9’h176 9’h177 FMARK Output Position 0th line 1st line 2nd line 3rd line . . . 373rd line 374th line 375th line 8.2.13. RGB Display Interface Control 2 (R0Fh) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 VSPL HSPL 0 EPL DPL 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 DPL: Sets the signal polarity of the DOTCLK pin. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 66 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 DPL = “0” The data is input on the rising edge of DOTCLK DPL = “1” The data is input on the falling edge of DOTCLK EPL: Sets the signal polarity of the ENABLE pin. EPL = “0” The data DB17-0 is written when ENABLE = “0”. Disable data write operation when ENABLE = “1”. EPL = “1” The data DB17-0 is written when ENABLE = “1”. Disable data write operation when ENABLE = “0”. HSPL: Sets the signal polarity of the HSYNC pin. HSPL = “0” Low active HSPL = “1” High active VSPL: Sets the signal polarity of the VSYNC pin. VSPL = “0” Low active VSPL = “1” High active 8.2.14. Power Control 1 (R10h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 SAP 0 BT2 BT1 BT0 APE AP2 AP1 AP0 0 0 SLP STB 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 SLP: When SLP = 1, ILI9335 enters the sleep mode and the display operation stops except the RC oscillator to reduce the power consumption. In the sleep mode, the GRAM data and instructions cannot be updated except the following instruction. a. Exit sleep mode (SLP = “0”) STB: When STB = 1, ILI9335 enters the standby mode and the display operation stops except the GRAM power supply to reduce the power consumption. In the STB mode, the GRAM data and instructions cannot be updated except the following instruction. a. Exit standby mode (STB = “0”) AP[2:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit. The larger constant current enhances the drivability of the LCD, but it also increases the current consumption. Adjust the constant current taking the trade-off into account between the display quality and the current consumption. In no-display period, set AP[2:0] = “000” to halt the operational amplifier circuits and the step-up circuits to reduce current consumption. AP[2:0] 000 001 010 011 100 101 110 111 Gamma driver amplifiers Halt 1.00 1.00 1.00 0.75 0.75 0.75 0.50 Source driver amplifiers Halt 1.00 0.75 0.50 1.00 0.75 0.50 0.50 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 67 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 SAP: Source Driver output control SAP=0, Source driver is disabled. SAP=1, Source driver is enabled. When starting the charge-pump of LCD in the Power ON stage, make sure that SAP=0, and set the SAP=1, after starting up the LCD power supply circuit. APE: Power supply enable bit. Set APE = “1” to start the generation of power supply according to the power supply startup sequence. BT[3:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating voltage. To reduce power consumption, set a smaller factor. BT[2:0] 3’h0 3’h1 3’h2 3’h3 3’h4 3’h5 3’h6 3’h7 DDVDH VCI1 x 2 VCI1 x 2 VCI1 x 2 VCI1 x 2 VCL - VCI1 - VCI1 - VCI1 - VCI1 VGH VCI1 x 6 VCI1 x 5 VCI1 x 4 VGL - VCI1 x 5 - VCI1 x 4 - VCI1 x 3 - VCI1 x 5 - VCI1 x 4 - VCI1 x 3 - VCI1 x 4 - VCI1 x 3 Notes: 1. Connect capacitors to the capacitor connection pins when generating DDVDH, VGH, VGL and VCL levels. 2. Make sure DDVDH = 6.0V (max.), 8.2.15. Power Control 2 (R11h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 DC12 DC11 DC10 0 DC02 DC01 DC00 0 VC2 VC1 VC0 0 0 0 0 0 1 1 1 0 1 1 1 00 0 0 VC[2:0] Sets the ratio factor of VCI to generate the reference voltages VCI1. VC2 VC1 VC0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 VCI1 voltage 0.95 x VCI 0.90 x VCI 0.85 x VCI 0.80 x VCI 0.75 x VCI 0.70 x VCI Disabled 1.0 x VCI DC0[2:0]: Selects the operating frequency of the step-up circuit 1. The higher step-up operating frequency The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 68 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking the trade-off between the display quality and the current consumption into account. DC1[2:0]: Selects the operating frequency of the step-up circuit 2. The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption. Adjust the frequency taking the trade-off between the display quality and the current consumption into account. DC02 0 0 0 0 1 1 1 1 DC01 0 0 1 1 0 0 1 1 DC00 0 1 0 1 0 1 0 1 Step-up circuit1 step-up frequency (fDCDC1) Fosc Fosc / 2 Fosc / 4 Fosc / 8 Fosc / 16 Fosc / 32 Fosc / 64 Halt step-up circuit 1 DC12 0 0 0 0 1 1 1 1 Note: Be sure fDCDC1≥fDCDC2 when setting DC0[2:0] and DC1[2:0]. DC11 0 0 1 1 0 0 1 1 DC10 0 1 0 1 0 1 0 1 Step-up circuit2 step-up frequency (fDCDC2) Fosc / 4 Fosc / 8 Fosc / 16 Fosc / 32 Fosc / 64 Fosc / 128 Fosc / 256 Halt step-up circuit 2 8.2.16. Power Control 3 (R12h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 VCIRE 0 0 0 VRH3 VRH2 VRH1 VRH0 0 0 0 0 0 0 00 0 000 0 0 0 0 VRH[3:0] Set the amplifying rate (1.6 ~ 1.9) of VCI applied to output the VREG1OUT level, which is a reference level for the VCOM level and the grayscale voltage level. VCIRE: Select the external reference voltage VCI or internal reference voltage VCIR. VCIRE=0 VCIRE =1 External reference voltage VCI (default) Internal reference voltage 2.5V VCIRE =0 VCIRE =1 VRH3 VRH2 VRH1 VRH0 VREG1OUT VRH3 VRH2 VRH1 VRH0 VREG1OUT 0 0 0 0 Halt 0 0 0 0 Halt 0 0 0 1 VCI x 2.00 0 0 0 1 2.5V x 2.00 = 5.000V 0 0 1 0 VCI x 2.05 0 0 1 0 2.5V x 2.05 = 5.125V 0 0 1 1 VCI x 2.10 0 0 1 1 2.5V x 2.10 = 5.250V 0 1 0 0 VCI x 2.20 0 1 0 0 2.5V x 2.20 = 5.500V 0 1 0 1 VCI x 2.30 0 1 0 1 2.5V x 2.30 = 5.750V 0 1 1 0 VCI x 2.40 0 1 1 0 2.5V x 2.40 = 6.000V 0 1 1 1 VCI x 2.40 0 1 1 1 2.5V x 2.40 = 6.000V 1 0 0 0 VCI x 1.60 1 0 0 0 2.5V x 1.60 = 4.000V 1 0 0 1 VCI x 1.65 1 0 0 1 2.5V x 1.65 = 4.125V 1 0 1 0 VCI x 1.70 1 0 1 0 2.5V x 1.70 = 4.250V 1 0 1 1 VCI x 1.75 1 0 1 1 2.5V x 1.75 = 4.375V 1 1 0 0 VCI x 1.80 1 1 0 0 2.5V x 1.80 = 4.500V 1 1 0 1 VCI x 1.85 1 1 0 1 2.5V x 1.85 = 4.625V 1 1 1 0 VCI x 1.90 1 1 1 0 2.5V x 1.90 = 4.750V 1 1 1 1 VCI x 1.95 1 1 1 1 2.5V x 1.95 = 4.875V The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 69 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color When VCI<2.5V, Internal reference voltage will be same as VCI. Make sure that VC and VRH setting restriction: VREG1OUT ≦ (DDVDH - 0.2)V. ILI9335 8.2.17. Power Control 4 (R13h) R/W RS W 1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 VDV4 VDV3 VDV2 VDV1 VDV0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 000 VDV[4:0] Select the factor of VREG1OUT to set the amplitude of Vcom alternating voltage from 0.70 to 1.24 x VREG1OUT . VDV4 VDV3 VDV2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 VDV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VDV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCOM amplitude VREG1OUT x 0.70 VREG1OUT x 0.72 VREG1OUT x 0.74 VREG1OUT x 0.76 VREG1OUT x 0.78 VREG1OUT x 0.80 VREG1OUT x 0.82 VREG1OUT x 0.84 VREG1OUT x 0.86 VREG1OUT x 0.88 VREG1OUT x 0.90 VREG1OUT x 0.92 VREG1OUT x 0.94 VREG1OUT x 0.96 VREG1OUT x 0.98 VREG1OUT x 1.00 VDV4 VDV3 VDV2 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 VDV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VDV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Set VDV[4:0] to let Vcom amplitude less than 6V. VCOM amplitude VREG1OUT x 0.94 VREG1OUT x 0.96 VREG1OUT x 0.98 VREG1OUT x 1.00 VREG1OUT x 1.02 VREG1OUT x 1.04 VREG1OUT x 1.06 VREG1OUT x 1.08 VREG1OUT x 1.10 VREG1OUT x 1.12 VREG1OUT x 1.14 VREG1OUT x 1.16 VREG1OUT x 1.18 VREG1OUT x 1.20 VREG1OUT x 1.22 VREG1OUT x 1.24 8.2.18. GRAM Horizontal/Vertical Address Set (R20h, R21h) R/W RS W1 W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 00 0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 0 0 0 0 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 0 0 0 0 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 00 0 0 00 0 0 0 0 0 AD[16:0] Set the initial value of address counter (AC). The address counter (AC) is automatically updated in accordance to the setting of the AM, I/D bits as data is written to the internal GRAM. The address counter is not automatically updated when read data from the internal GRAM. AD[16:0] 17’h00000 ~ 17’h000EF 17’h00100 ~ 17’h001EF GRAM Data Map 1st line GRAM Data 2nd line GRAM Data The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 70 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 17’h00200 ~ 17’h002EF 17’h00300 ~ 17’h003EF 3rd line GRAM Data 4th line GRAM Data 17’h13D00 ~ 17’ h13DEF 17’h13E00 ~ 17’ h13EEF 17’h13F00 ~ 17’h13FEF 318th line GRAM Data 319th line GRAM Data 320th line GRAM Data Note1: When the RGB interface is selected (RM = “1”), the address AD[16:0] is set to the address counter every frame on the falling edge of VSYNC. . 8.2.19. Write Data to GRAM (R22h) R/W RS W1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RAM write data (WD[17:0], the DB[17:0] pin assignment differs for each interface. This register is the GRAM access port. When update the display data through this register, the address counter (AC) is increased/decreased automatically. 8.2.20. Read Data from GRAM (R22h) R/W RS R1 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RAM Read Data (RD[17:0], the DB[17:0] pin assignment differs for each interface. RD[17:0] Read 18-bit data from GRAM through the read data register (RDR). The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 71 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 1 8 -bit S ys te m In te rfa c e G RAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Write Da ta Re gis te r RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Output Da ta DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 6 -bit S ys te m In te rfa c e G RAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Write Da ta Re gis te r RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Output Da ta DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 DB DB DB DB DB DB DB DB 8 7 6 5 4 3 2 1 9 -b it S ys te m In te rfa ce G RAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Write Da ta Re gis te r RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Output Da ta DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9 1s t Tra ns fe r 2nd Tra ns fe r 8 -b it S ys te m In te rfa ce / S e ria l Da ta Tra n s fe r In te rfa c e G RAM Da ta & RGB Ma pping R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Write Da ta Re gis te r RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Output Da ta DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 1s t Tra ns fe r DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 2nd Tra ns fe r Figure 27 Data Read from GRAM through Read Data Register in 18-/16-/9-/8-bit Interface Mode The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 72 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color S e t I/D AM, HAS /HEA, VS A/VEA S e t a ddre s s M Dum m y re a d (inva lid da ta ) G RAM -> R e a d da ta la tch Re a d O utput (da ta of a ddre s s M) Re a d da ta la tch -> DB[17:0] R e a d O utput (da ta of a ddre s s M+1) Re a d da ta la tch -> DB[17:0] S e t a ddre s s N Dum m y re a d (inva lid da ta ) G RAM -> R e a d da ta la tch Re a d Output (da ta of a ddre s s N) Re a d da ta la tch -> DB[17:0] ILI9335 Figure 28 GRAM Data Read Back Flow Chart 8.2.21. Power Control 7 (R29h) R/W RS W 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 VCM5 VCM4 VCM3 VCM2 VCM1 VCM0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 73 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Default 0 0 0 0 0 0 0 VCM[5:0] Set the internal VcomH voltage. VCM5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCM4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCM3 VCM2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 VCM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VCM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCOMH VREG1OUT x 0.685 VREG1OUT x 0.690 VREG1OUT x 0.695 VREG1OUT x 0.700 VREG1OUT x 0.705 VREG1OUT x 0.710 VREG1OUT x 0.715 VREG1OUT x 0.720 VREG1OUT x 0.725 VREG1OUT x 0.730 VREG1OUT x 0.735 VREG1OUT x 0.740 VREG1OUT x 0.745 VREG1OUT x 0.750 VREG1OUT x 0.755 VREG1OUT x 0.760 VREG1OUT x 0.765 VREG1OUT x 0.770 VREG1OUT x 0.775 VREG1OUT x 0.780 VREG1OUT x 0.785 VREG1OUT x 0.790 VREG1OUT x 0.795 VREG1OUT x 0.800 VREG1OUT x 0.805 VREG1OUT x 0.810 VREG1OUT x 0.815 VREG1OUT x 0.820 VREG1OUT x 0.825 VREG1OUT x 0.830 VREG1OUT x 0.835 VREG1OUT x 0.840 00 0 0 0 0 VCM5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCM4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCM3 VCM2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 VCM1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VCM0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 VCOMH VREG1OUT x 0.845 VREG1OUT x 0.850 VREG1OUT x 0.855 VREG1OUT x 0.860 VREG1OUT x 0.865 VREG1OUT x 0.870 VREG1OUT x 0.875 VREG1OUT x 0.880 VREG1OUT x 0.885 VREG1OUT x 0.890 VREG1OUT x 0.895 VREG1OUT x 0.900 VREG1OUT x 0.905 VREG1OUT x 0.910 VREG1OUT x 0.915 VREG1OUT x 0.920 VREG1OUT x 0.925 VREG1OUT x 0.930 VREG1OUT x 0.935 VREG1OUT x 0.940 VREG1OUT x 0.945 VREG1OUT x 0.950 VREG1OUT x 0.955 VREG1OUT x 0.960 VREG1OUT x 0.965 VREG1OUT x 0.970 VREG1OUT x 0.975 VREG1OUT x 0.980 VREG1OUT x 0.985 VREG1OUT x 0.990 VREG1OUT x 0.995 VREG1OUT x 1.000 8.2.22. Frame Rate and Color Control (R2Bh) R/W RS W 1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 00 0 00 0 0 0 0 FRS3 FRS2 FRS1 FRS0 0 0 0 00 0 00 0 00 0 1 0 1 1 FRS[4:0] Set the frame rate when the internal resistor is used for oscillator circuit. FRS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 FRS[3:0] 4’h0 4’h1 4’h2 4’h3 4’h4 4’h5 4’h6 4’h7 4’h8 4’h9 4’hA 4’hB 4’hC 4’hD 4’hE 4’hF Frame Rate 31 33 34 36 39 41 44 48 52 57 62 69 78 89 Setting Prohibited Setting Prohibited 8.2.23. Gamma Control (R30h ~ R3Dh) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 74 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 R30h W 1 R31h W 1 R32h W 1 R35h W 1 R36h W 1 R37h W 1 R38h W 1 R39h W 1 R3Ch W 1 R3Dh W 1 000 0 0 KP1[2] KP1[1] KP1[0] 0 0 0 0 0 KP0[2] KP0[1] KP0[0] 000 0 0 KP3[2] KP3[1] KP3[0] 0 0 0 0 0 KP2[2] KP2[1] KP2[0] 000 0 0 KP5[2] KP5[1] KP5[0] 0 0 0 0 0 KP4[2] KP4[1] KP4[0] 000 0 0 RP1[2] RP1[1] RP1[0] 0 0 0 0 0 RP0[2] RP0[1] RP0[0] 0 0 0 VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[0] 0 0 0 0 VRP0[3] VRP0[2] VRP0[1] VRP0[0] 000 0 0 KN1[2] KN1[1] KN1[0] 0 0 0 0 0 KN0[2] KN0[1] KN0[0] 000 0 0 KN3[2] KN3[1] KN3[0] 0 0 0 0 0 KN2[2] KN2[1] KN2[0] 000 0 0 KN5[2] KN5[1] KN5[0] 0 0 0 0 0 KN4[2] KN4[1] KN4[0] 000 0 0 RN1[2] RN1[1] RN1[0] 0 0 0 0 0 RN0[2] RN0[1] RN0[0] 0 0 0 VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[0] 0 0 0 0 VRN0[3] VRN0[2] VRN0[1] VRN0[0] KP5-0[2:0] : γfine adjustment register for positive polarity RP1-0[2:0] : γgradient adjustment register for positive polarity VRP1-0[4:0] : γamplitude adjustment register for positive polarity KN5-0[2:0] : γfine adjustment register for negative polarity RN1-0[2:0] : γgradient adjustment register for negative polarity VRN1-0[4:0] : γamplitude adjustment register for negative polarity For details “γ-Correction Function” section. 8.2.24. Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) R50h R51h R52h R53h R50h R51h R52h R53h R/W RS W 1 W 1 W 1 W 1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 0 0 0 0 0 0 0 0 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 0 0 0 0 0 0 0 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 0 0 0 0 0 0 0 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 1 1 1 0 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 1 0 0 1 1 1 1 1 1 HSA[7:0]/HEA[7:0] HSA[7:0] and HEA[7:0] represent the respective addresses at the start and end of the window address area in horizontal direction. By setting HSA and HEA bits, it is possible to limit the area on the GRAM horizontally for writing data. The HSA and HEA bits must be set before starting RAM write operation. In setting these bits, be sure “00”h ≤ HSA[7:0]< HEA[7:0] ≤ “EF”h. and “01”h≦HEA-HAS. VSA[8:0]/VEA[8:0] VSA[8:0] and VEA[8:0] represent the respective addresses at the start and end of the window address area in vertical direction. By setting VSA and VEA bits, it is possible to limit the area on the GRAM vertically for writing data. The VSA and VEA bits must be set before starting RAM write operation. In setting, be sure “000”h ≤ VSA[8:0]< VEA[8:0] ≤ “13F”h. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 75 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color HS A 0000h HEA VS A VE A Window Addre s s Are a GRAM Addre s s Are a 13FEFh ILI9335 Figure 29 GRAM Access Range Configuration “00”h ≤HSA[7:0] ≤HEA[7:0] ≤”EF”h “00”h ≤VSA[8:0] ≤VEA[8:0] ≤”13F”h Note1. The window address range must be within the GRAM address space. Note2. Data are written to GRAM in four-words when operating in high speed mode, the dummy write operations should be inserted depending on the window address area. For details, see the High-Speed RAM Write Function section. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 76 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.25. Gate Scan Control (R60h, R61h, R6Ah) R60h R61h R6Ah R60h R61h R6Ah R/W RS W1 W1 W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 GS 0 NL5 NL4 NL3 NL2 NL1 NL0 0 0 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0 0 0 0 0 0 0 00 0 0 0 0 0 NDL VLE REV 0 0 0 0 0 0 0 VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0 0 0 1 0 0 1 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 SCN[5:0] The ILI9335 allows to specify the gate line from which the gate driver starts to scan by setting the SCN[5:0] bits. SCN[5:0] 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h ~ 3Fh Scanning Start Position SM=0 SM=1 GS=0 GS=1 GS=0 GS=1 G1 G320 G1 G320 G9 G17 G25 G33 G41 G49 G57 G65 G73 G81 G89 G97 G105 G113 G121 G129 G137 G145 G153 G161 G169 G177 G185 G193 G201 G209 G217 G225 G233 G241 G249 G257 G265 G273 G281 G289 G297 G305 G313 Setting disabled G312 G304 G296 G288 G280 G272 G264 G256 G248 G240 G232 G224 G216 G208 G200 G192 G184 G176 G168 G160 G152 G144 G136 G128 G120 G112 G104 G96 G88 G80 G72 G64 G56 G48 G40 G32 G24 G16 G8 Setting disabled G17 G33 G49 G65 G81 G97 G113 G129 G145 G161 G177 G193 G209 G2 G18 G34 G50 G66 G82 G98 G114 G130 G146 G162 G178 G194 G114 G130 G146 G162 G178 G194 G210 G226 G242 G258 G274 G290 G306 Setting disabled G304 G288 G272 G256 G240 G224 G208 G192 G176 G160 G144 G128 G112 G96 G80 G64 G48 G32 G16 G319 G303 G287 G271 G255 G239 G223 G207 G191 G175 G159 G143 G127 G111 G95 G79 G63 G47 G31 G15 Setting disabled Note: When SM=1, it is a interlacing scanning. Please reference page 72! The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 77 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping is not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel. NL[5:0] 6’h00 6’h01 6’h02 … 6’h1D 6’h1E 6’h1F 6’h20 6’h21 6’h22 6’h23 6’h24 6’h25 6’h26 6’h27 Others LCD Drive Line 8 lines 16 lines 24lines … 240 lines 248 lines 256 lines 264 lines 272 lines 280 lines 288 lines 296 lines 304 lines 312 line 320 line Setting inhibited NDL: Sets the source driver output level in the non-display area. NDL 0 1 Positive Polarity V63 V0 Non-Display Area Negative Polarity V0 V63 GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:0] and NL[4:0]. The scan direction determined by GS = 0 can be reversed by setting GS = 1. When GS = 0, the scan direction is from G1 to G320. When GS = 1, the scan direction is from G320 to G1 REV: Enables the grayscale inversion of the image by setting REV=1. REV 0 1 GRAM Data 18’h00000 . . . 18’h3FFFF 18’h00000 . . . 18’h3FFFF Source Output in Display Area Positive polarity negative polarity V63 V0 . . . . . . V0 V63 V0 V63 . . . . . . V63 V0 VLE: Vertical scroll display enable bit. When VLE = 1, the ILI9335 starts displaying the base image from the line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling, which is the The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 78 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 number of lines to shift the start line of the display from the first line of the physical display. Note that the partial image display position is not affected by the base image scrolling. The vertical scrolling is not available in external display interface operation. In this case, make sure to set VLE = “0”. VLE Base Image Display 0 Fixed 1 Enable Scrolling VL[8:0]: Sets the scrolling amount of base image. The base image is scrolled in vertical direction and displayed from the line determined by VL[8:0]. Make sure that VL[8:0] ≦320. 8.2.26. Partial Image 1 Display Position (R80h) R/W RS W 1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 PTD PTD P0[8] P0[7] PTD P0[6] PTD P0[5] PTD P0[4] PTD P0[3] PTD P0[2] PTD P0[1] PTD P0[0] 0 0 0 0 0 000 0 0 0 0 0 0 0 0 PTDP0[8:0]: Sets the display start position of partial image 1. The display areas of the partial images 1 and 2 must not overlap each another. 8.2.27. Partial Image 1 RAM Start/End Address (R81h, R82h) R/W RS W 1 W 1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 PTS PTS A0[8] A0[7] PTS A0[6] PTS A0[5] PTS A0[4] PTS A0[3] PTS A0[2] PTS A0[1] PTS A0[0] 0 0 0 0 0 0 0 PTE PTE A0[8] A0[7] PTE A0[6] PTE A0[5] PTE A0[4] PTE A0[3] PTE A0[2] PTE A0[1] PTE A0[0] 0 0 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 PTSA0[8:0] PTEA0[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 1. Make sure PTSA0[8:0] ≤ PTEA0[8:0]. 8.2.28. Partial Image 2 Display Position (R83h) R/W RS W 1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 PTD PTD P1[8] P1[7] PTD P1[6] PTD P1[5] PTD P1[4] PTD P1[3] PTD P1[2] PTD P1[1] PTD P1[0] 0 0 0 0 0 000 0 0 0 0 0 0 0 0 PTDP1[8:0]: Sets the display start position of partial image 2 The display areas of the partial images 1 and 2 must not overlap each another. 8.2.29. Partial Image 2 RAM Start/End Address (R84h, R85h) R/W RS W 1 W 1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 PTS PTS A1[8] A1[7] PTS A1[6] PTS A1[5] PTS A1[4] PTS A1[3] PTS A1[2] PTS A1[1] PTS A1[0] 0 0 0 0 0 0 0 PTE PTE A1[8] A1[7] PTE A1[6] PTE A1[5] PTE A1[4] PTE A1[3] PTE A1[2] PTE A1[1] PTE A1[0] 0 0 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 PTSA1[8:0] PTEA1[8:0]: Sets the start line address and the end line address of the RAM area storing the data of partial image 2 Make sure PTSA1[8:0] ≤ PTEA1[8:0]. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 79 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.30. Panel Interface Control 1 (R90h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 DIVI1 DIVI0 0 0 0 RTNI4 RTNI3 RTNI2 RTNI1 0 0 0 0 0 0 0 0 000 1 0 0 0 RTNI[4:0]: Sets 1H (line) clock number of internal clock operating mode. In this mode, ILI9335 display D0 RTNI0 0 operation is synchronized with internal clock signal. RTNI[4:0] 00000~01111 10000 10001 10010 10011 10100 10101 10110 10111 Clocks/Line Setting Disabled 16 clocks 17 clocks 18 clocks 19 clocks 20 clocks 21 clocks 22 clocks 23 clocks RTNI[4:0] 11000 11001 11010 11011 11100 11101 11110 11111 Clocks/Line 24 clocks 25 clocks 26 clocks 27 clocks 28 clocks 29 clocks 30 clocks 31 clocks DIVI[1:0]: Sets the division ratio of internal clock frequency. DIVI1 0 DIVI0 0 Division Ratio 1 Internal Operation Clock Frequency fosc / 1 0 1 2 fosc / 2 1 0 4 1 1 8 fosc / 4 fosc / 8 8.2.31. Panel Interface Control 2 (R92h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 NOWI[2] NOWI[1] NOWI[0] 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0000 0 0 0 0 NOWI[2:0]: Sets the gate output non-overlap period when ILI9335 display operation is synchronized with internal clock signal. NOWI[2:0] 000 001 010 011 100 101 110 111 Gate Non-overlap Period Setting inhibited 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks Setting inhibited Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (DIVI), from the reference point. 8.2.32. Panel Interface Control 4 (R95h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 DIVE1 DIVE0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 DIVE[1:0]: Sets the division ratio of DOTCLK when ILI9335 display operation is synchronized with RGB interface signals. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 80 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 DIVE[1:0] 00 01 10 11 Division Ratio Setting Prohibited 1/4 1/8 1/16 18/16-bit RGB Interface Setting Prohibited 4 DOTCLKS 8 DOTCLKS 16 DOTCLKS DOTCLK=5MHz - 0.8 μs 1.6 μs 3.2 μs 6-bit x 3 Transfers RGB Interface Setting Prohibited 12 DOTCLKS 24 DOTCLKS 48 DOTCLKS DOTCLK=5MHz - 0.8 μs 1.6 μs 3.2 μs 8.2.33. Panel Interface Control 5 (R97h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 NOWE3 NOWE2 NOWE1 NOWE0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 NOWE[3:0]: Sets the gate output non-overlap period when the ILI9335 display operation is synchronized with RGB interface signals. NOWE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Gate Non-overlap Period Setting inhibited 1 clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks NOWE[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Gate Non-overlap Period 8 clocks 9 clocks 10 clocks Setting inhibited Setting inhibited Setting inhibited Setting inhibited Setting inhibited Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK] 8.2.34. OTP VCM Programming Control (RA1h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 OTP_ PGM_EN 0 0 0 0 0 VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ OTP5 OTP4 OTP3 OTP2 OTP1 OTP0 0 0 0 0 0 0 0000 0 0 0 0 0 0 OTP_PGM_EN: OTP programming enable. When program OTP, must set this bit. OTP data can be programmed 3 times. VCM_OTP[5:0]: OTP programming data for VCOMH voltage, the voltage refer to VCM[5:0] value. 8.2.35. OTP VCM Status and Enable (RA2h) R/W RS W1 Default D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PGM_ PGM_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ CNT1 CNT0 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 VCM_ EN 0 0 0 0 0 0 0 0 0000000 0 PGM_CNT[1:0]: OTP programmed record. These bits are read only. OTP_PGM_CNT[1:0] 00 01 10 11 Description OTP clean OTP programmed 1 time OTP programmed 2 times OTP programmed 3 times VCM_D[5:0]: OTP VCM data read value. These bits are read only. VCM_EN: OTP VCM data enable. ’1’: Set this bit to enable OTP VCM data to replace R29h VCM value. ’0’: Default value, use R29h VCM value. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 81 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 8.2.36. OTP Programming ID Key (RA5h) R/W RS W1 Default D15 KEY 15 0 D14 KEY 14 0 D13 KEY 13 0 D12 KEY 12 0 D11 KEY 11 0 D10 KEY 10 0 D9 KEY 9 0 D8 KEY 8 0 D7 KEY 7 0 D6 KEY 6 0 D5 KEY 5 0 D4 KEY 4 0 D3 KEY 3 0 D2 KEY 2 0 D1 KEY 1 0 D0 KEY 0 0 KEY[15:0]: OTP Programming ID key protection. Before writing OTP programming data RA1h, it must write RA5h with 0xAA55 value first to make OTP programming successfully. If RA5h is not written with 0xAA55, OTP programming will be fail. See OTP Programming flow. 8.2.37. Deep stand by control (RE6h) R/W RS D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 W1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTB Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTB: When DSTB = 1, the ILI9335 enters the deep standby mode. In deep standby mode, the internal logic power supply is turned off to reduce power consumption. The GRAM data and instruction setting are not maintained when the ILI9335 enters the deep standby mode, and they must be reset after exiting deep standby mode. Basic operation The basic operation modes of 9335 are as shown in the following diagram. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 82 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color CPU interface transition setting sequences Enter deep standby mode Deep Standby Mode Display Off Sequence Set RE6h:DSTB = 1 ILI9335 Release from deep standby Set nCS pin = Low, then Set nCS pin = High Set nCS pin = Low, then Set nCS pin = High Set nCS pin = Low, then Set nCS pin = High Set nCS pin = Low, then Set nCS pin = High Set nCS pin = Low, then Set nCS pin = High Set nCS pin = Low, then Set nCS pin = High Set nCS pin low to high x6 Registers set as default value ILI9335's register setting GRAM data setting Display On Sequence The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 83 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 9. OTP Programming Flow ILI9335 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 84 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 10. GRAM Address Map & Read/Write ILI9335 has an internal graphics RAM (GRAM) of 172,800 bytes to store the display data and one pixel is constructed of 18 bits. The GRAM can be accessed through the i80 system, SPI and RGB interfaces. i80 18-/16-bit S ys te m Bus Inte rfa ce Timing (a ) Write to G R AM nCS RS nRD nWR D B [1 7 :0 ] Write “0022 h "to inde x re gis te r Write G RAM “da ta " Write G R AM “da ta " Write G R AM “da ta " Write GR AM “da ta " Nth pixe l (N+1 )th pixe l (N+2 )th pixe l (N+3)th pixe l (b) R e a d from G R AM nCS RS nRD nWR D B [1 7 :0 ] Write “0022 h "to inde x re gis te r Dummy Read 1s t R e a d “da ta " Nth pixe l 2 nd R e a d “da ta " (N+1)th pixe l 3rd R e a d “da ta " (N+2 )th pixe l i80 9-/8-bit S ys te m Bus Inte rfa ce Timing (a ) Write to G R AM nCS RS nRD nWR D B [1 7 :9 ] “00h" “22h" 1s t write high byte 1s t write low byte 2nd write high byte 2nd write low byte 3 rd write high byte 3 rd write low byte Nth pixe l (N+1)th pixe l (N+2)th pixe l (b) R e a d from G R AM nCS RS nRD nWR D B [1 7 :9 ] “00h" “22h" Dummy Read 1 Dummy Read 2 1s t re a d high byte 1s t rea d low byte Nth pixe l 2nd re a d 2nd re a d high byte low byte (N+1)th pixe l Figure30 GRAM Read/Write Timing of i80-System Interface The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 85 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 GRAM address map table of SS=0, BGR=0 SS=0, BGR=0 S1…S3 S4…S6 S7…S9 S10…S12 … S517…S519 S520…S522 S523…S525 S526…S720 GS=0 GS=1 DB17…0 DB17…0 DB17…0 DB17…0 … DB17…0 DB17…0 DB17…0 DB17…0 G1 G320 “00000h” “00001h” “00002h” “00003h” … “000ECh” “000EDh” “000EEh” “000EFh” G2 G319 “00100h” “00101h” “00102h” “00103h” … “001ECh” “001EDh” “001EEh” “001EFh” G3 G318 “00200h” “00201h” “00202h” “00203h” … “002ECh” “002EDh” “002EEh” “002EFh” G4 G317 “00300h” “00301h” “00302h” “00303h” … “003ECh” “003EDh” “003EEh” “003EFh” G5 G316 “00400h” “00401h” “00402h” “00403h” … “004ECh” “004EDh” “004EEh” “004EFh” G6 G315 “00500h” “00501h” “00502h” “00503h” … “005ECh” “005EDh” “005EEh” “005EFh” G7 G314 “00600h” “00601h” “00602h” “00603h” … “006ECh” “006EDh” “006EEh” “006EFh” G8 G313 “00700h” “00701h” “00702h” “00703h” … “007ECh” “007EDh” “007EEh” “007EFh” G9 G312 “00800h” “00801h” “00802h” “00803h” … “008ECh” “008EDh” “008EEh” “008EFh” G10 G311 “00900h” “00901h” “00902h” “00903h” … “009ECh” “009EDh” “009EEh” “009EFh” . . . . . . … . . . . . . . . . . . . . . . . . . . . . . . . G311 G10 “13600h” “13601h” “13602h” “13603h” … “136ECh” “136EDh” “136EEh” “136EFh” G312 G9 “13700h” “13701h” “13702h” “13703h” … “137ECh” “137EDh” “137EEh” “137EFh” G313 G8 “13800h” “13801h” “13802h” “13803h” … “138ECh” “138EDh” “138EEh” “138EFh” G314 G7 “13900h” “13901h” “13902h” “13903h” … “139ECh” “139EDh” “139EEh” “139EFh” G315 G6 “13A00h” “13A01h” “13A02h” “13A03h” … “13AECh” “13AEDh” “13AEEh” “13AEFh” G316 G5 “13B00h” “13B01h” “13B02h” “13B03h” … “13BECh” “13BEDh” “13BEEh” “13BEFh” G317 G4 “13C00h” “13C01h” “13C02h” “13C03h” … “13CECh” “13CEDh” “13CEEh” “13CEFh” G318 G3 “13D00h” “13D01h” “13D02h” “13D03h” … “13DECh” “13DEDh” “13DEEh” “13DEFh” G319 G2 “13E00h” “13E01h” “13E02h” “13E03h” … “13EECh” “13EEDh” “13EEEh” “13EEFh” G320 G1 “13F00h” “13F01h” “13F02h” “13F03h” … “13FECh” “13FEDh” “13FEEh” “13FEFh” The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 86 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Source Output Pin S (3n+1) S (3n+2) S (3n+3) N=0 to 239 GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB DB DB DB DB DB DB DB 8 7 6 5 4 3 2 1 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Source Output Pin S (3n+1) S (3n+2) S (3n+3) N=0 to 239 1st Transfer 2nd Transfer GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 RGB Assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Source Output Pin S (3n+1) S (3n+2) S (3n+3) N=0 to 239 GRAM Data and display data of 18-/16-/9-bit system interface (SS="0", BGR="0") Figure31 i80-System Interface with 18-/16-/9-bit Data Bus (SS=”0”, BGR=”0”) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 87 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Figure32 i80-System Interface with 8-bit Data Bus (SS=”0”, BGR=”0”) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 88 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 GRAM address map table of SS=1, BGR=1 SS=1, BGR=1 S720…S718 S717…S715 S714…S712 S711…S709 … S12…S10 S9…S7 S6…S4 S3…S1 GS=0 GS=1 DB17…0 DB17…0 DB17…0 DB17…0 … DB17…0 DB17…0 DB17…0 DB17…0 G1 G320 “00000h” “00001h” “00002h” “00003h” … “000ECh” “000EDh” “000EEh” “000EFh” G2 G319 “00100h” “00101h” “00102h” “00103h” … “001ECh” “001EDh” “001EEh” “001EFh” G3 G318 “00200h” “00201h” “00202h” “00203h” … “002ECh” “002EDh” “002EEh” “002EFh” G4 G317 “00300h” “00301h” “00302h” “00303h” … “003ECh” “003EDh” “003EEh” “003EFh” G5 G316 “00400h” “00401h” “00402h” “00403h” … “004ECh” “004EDh” “004EEh” “004EFh” G6 G315 “00500h” “00501h” “00502h” “00503h” … “005ECh” “005EDh” “005EEh” “005EFh” G7 G314 “00600h” “00601h” “00602h” “00603h” … “006ECh” “006EDh” “006EEh” “006EFh” G8 G313 “00700h” “00701h” “00702h” “00703h” … “007ECh” “007EDh” “007EEh” “007EFh” G9 G312 “00800h” “00801h” “00802h” “00803h” … “008ECh” “008EDh” “008EEh” “008EFh” G10 G311 “00900h” “00901h” “00902h” “00903h” … “009ECh” “009EDh” “009EEh” “009EFh” . . . . . . … . . . . . . . . . . . . . . . . . . . . . . . . G311 G10 “13600h” “13601h” “13602h” “13603h” … “136ECh” “136EDh” “136EEh” “136EFh” G312 G9 “13700h” “13701h” “13702h” “13703h” … “137ECh” “137EDh” “137EEh” “137EFh” G313 G8 “13800h” “13801h” “13802h” “13803h” … “138ECh” “138EDh” “138EEh” “138EFh” G314 G7 “13900h” “13901h” “13902h” “13903h” … “139ECh” “139EDh” “139EEh” “139EFh” G315 G6 “13A00h” “13A01h” “13A02h” “13A03h” … “13AECh” “13AEDh” “13AEEh” “13AEFh” G316 G5 “13B00h” “13B01h” “13B02h” “13B03h” … “13BECh” “13BEDh” “13BEEh” “13BEFh” G317 G4 “13C00h” “13C01h” “13C02h” “13C03h” … “13CECh” “13CEDh” “13CEEh” “13CEFh” G318 G3 “13D00h” “13D01h” “13D02h” “13D03h” … “13DECh” “13DEDh” “13DEEh” “13DEFh” G319 G2 “13E00h” “13E01h” “13E02h” “13E03h” … “13EECh” “13EEDh” “13EEEh” “13EEFh” G320 G1 “13F00h” “13F01h” “13F02h” “13F03h” … “13FECh” “13FEDh” “13FEEh” “13FEFh” Figure 33 i80-System Interface with 18-/9-bit Data Bus (SS=”1”, BGR=”1”) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 89 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 11. Window Address Function The window address function enables writing display data consecutively in a rectangular area (a window address area) made on the internal RAM. The window address area is made by setting the horizontal address register (start: HSA[7:0], end: HEA[7:0] bits) and the vertical address register (start: VSA[8:0], end: VEA[8:0] bits). The AM bit sets the transition direction of RAM address (either increment or decrement). These bits enable the ILI9335 to write data including image data consecutively not taking data wrap positions into account. The window address area must be made within the GRAM address map area. Also, the GRAM address bits (RAM address set register) must be an address within the window address area. [Window address setting area] (Horizontal direction) 00H ≤ HSA[7:0] ≤ HEA[7:0] ≤ “EF”H (Vertical direction) 00H ≤ VSA[8:0] ≤ VEA[8:0]≤ “13F”H [RAM address, AD (an address within a window address area)]] (RAM address) HSA[7:0] ≤ AD[7:0] ≤ HEA[7:0] VSA[8:0] ≤ AD[15:8] ≤ VEA[8:0] Figure 34 GRAM Access Window Map The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 90 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 12. Gamma Correction ILI9335 incorporates the γ-correction function to display 262,144 colors for the LCD panel. The γ-correction is performed with 3 groups of registers determining eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment registers for positive and negative polarities, to make ILI9335 available with liquid crystal panels of various characteristics. VR E G 1 O UT Gra die nt Adjus tme nt Re gis te r P RP /N0 P RP /N1 Fine Adjus tm e nt Re gis te rs (6 x 3 bits ) P KP /N5 P KP /N4 P KP /N3 P KP /N2 P KP /N1 P KP /N0 Am plitude Adjus tme nt Re gis te r VRP /N0 VRP /N1 8 to 1 s e le ction …... …... …... 8 to 1 s e le ction 8 to 1 s e le ction 8 to 1 s e le ction 8 to 1 s e le ction VgP 0/VgN0 V0 VgP 1/VgN1 V1 V2 V7 VgP 8/VgN8 V8 VgP 20/VgN20 V2 0 VgP 43/VgN43 V4 3 VgP 55/VgN55 V5 5 V5 6 V6 1 VgP 62/VgN62 V6 2 VgP 63/VgN63 V6 3 …... …... 8 to 1 s e le ction VG S Figure 35 Grayscale Voltage Generation The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 91 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 VREG1OUT 1uF/10V VGS VROP0 0 ~ 30R 5R 4Rx7=28R VRCP0 0 ~ 28R Rx7=7R Rx7=7R Rx7=7R Rx7=7R VRCP1 0 ~ 28R 4Rx7=28R RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RP32 RP33 RP34 RP35 RP36 RP37 RP38 RP39 RP40 RP41 RP42 RP43 RP44 RP45 5R RP46 VROP1 0 ~ 31R 8R RP47 VRP0[3:0] VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 PRP0[2:0] VP9 VP10 VP11 VP12 VP13 VP14 VP15 VP16 VP17 VP18 VP19 VP20 VP21 VP22 VP23 VP24 VP25 VP26 VP27 VP28 VP29 VP30 VP31 VP32 VP33 VP34 VP35 VP36 VP37 VP38 VP39 VP40 PRP1[2:0] VP41 VP42 VP43 VP44 VP45 VP46 VP47 VP48 VP49 VRP1[4:0] 8 to 1 Selection 8 to 1 Selection 8 to 1 Selection 8 to 1 Selection 8 to 1 Selection 8 to 1 Selection VgP0 KP0[2:0] VgP1 KP1[2:0] VgP8 KP2[2:0] VgP20 KP3[2:0] VgP43 KP4[2:0] VgP55 KP5[2:0] VgP62 VgP63 VRON0 0 ~ 30R 5R 4Rx7=28R VRCN0 0 ~ 28R Rx7=7R Rx7=7R Rx7=7R Rx7=7R VRCN1 0 ~ 28R 4Rx7=28R RN0 RN1 RN2 RN3 RN4 RN5 RN6 RN7 RN8 RN9 RN10 RN11 RN12 RN13 RN14 RN15 RN16 RN17 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN30 RN31 RN32 RN33 RN34 RN35 RN36 RN37 RN38 RN39 RN40 RN41 RN42 RN43 RN44 RN45 5R RN46 VRON1 0 ~ 31R 8R RN47 VRN0[3:0] VN1 VN2 VN3 VN4 VN5 VN6 VN7 VN8 PRN0[2:0] VN9 VN10 VN11 VN12 VN13 VN14 VN15 VN16 VN17 VN18 VN19 VN20 VN21 VN22 VN23 VN24 VN25 VN26 VN27 VN28 VN29 VN30 VN31 VN32 VN33 VN34 VN35 VN36 VN37 VN38 VN39 VN40 PRN1[2:0] VN41 VN42 VN43 VN44 VN45 VN46 VN47 VN48 VN49 VRN1[4:0] 8 to 1 Selection 8 to 1 Selection 8 to 1 Selection 8 to 1 Selection 8 to 1 Selection 8 to 1 Selection VgN0 KN0[2:0] VgN1 KN1[2:0] VgN8 KN2[2:0] VgN20 KN3[2:0] VgN43 KN4[2:0] VgN55 KN5[2:0] VgN62 VgN63 Figure 36 Grayscale Voltage Adjustment The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 92 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 1. Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale reference voltage level. To adjust the gradient, the resistance values of variable resistors in the middle of the ladder resistor are adjusted by registers PRP0[2:0]/PRN0[2:0], PRP1[2:0]/PRN1[2:0]. The registers consist of positive and negative polarity registers, allowing asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers, VRP0[3:0]/VRN0[3:0], VRP1[4:0]/VRN1[4:0], are used to adjust the amplitude of grayscale voltages. To adjust the amplitude, the resistance values of variable resistors at the top and bottom of the ladder resistor are adjusted. Same as the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers. 3. Fine adjustment registers The fine adjustment registers are used to fine-adjust grayscale voltage levels. To fine-adjust grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register generated from the ladder resistor, in respective 8-to-1 selectors. Same with other registers, the fine adjustment registers consist of positive and negative polarity registers. G ra ys ca le vo lta ge G ra ys ca le volta g e G ra ys ca le volta g e G ra die nt a djus tme nt Amplitude a djus tm e nt Figure 37 Gamma Curve Adjustment Fine a djus tm e nt Register Groups Gradient adjustment Amplitude adjustment Fine adjustment Positive Polarity PRP0 [2:0] PRP1 [2:0] VRP0 [3:0] VRP1 [4:0] KP0 [2:0] KP1 [2:0] KP2 [2:0] KP3 [2:0] KP4 [2:0] KP5 [2:0] Negative Polarity PRN0 [2:0] PRN1 [2:0] VRN0 [3:0] VRN1 [4:0] KN0 [2:0] KN1 [2:0] KN2 [2:0] KN3 [2:0] KN4 [2:0] KN5 [2:0] Description Variable resistor VRCP0, VRCN0 Variable resistor VRCP1, VRCN1 Variable resistor VROP0, VRON0 Variable resistor VROP1, VRON1 8-to-1 selector (voltage level of grayscale 1) 8-to-1 selector (voltage level of grayscale 8) 8-to-1 selector (voltage level of grayscale 20) 8-to-1 selector (voltage level of grayscale 43) 8-to-1 selector (voltage level of grayscale 55) 8-to-1 selector (voltage level of grayscale 62) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 93 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Ladder resistors and 8-to-1 selector Block configuration The reference voltage generating block consists of two ladder resistor units including variable resistors and 8-to-1 selectors. Each 8-to-1 selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage. Both variable resistors and 8-to-1 selectors are controlled according to the γ-correction registers. This unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels. Variable resistors ILI9335 uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)0/VRCP(N)1); amplitude adjustment (1) (VROP(N)0); and the amplitude adjustment (2) (VROP(N)1). The resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows. Gradient adjustment PRP(N)0/1[2:0] VRCP(N)0/1 Register Resistance 000 0R 001 4R 010 8R 011 12R 100 16R 101 20R 110 24R 111 28R Amplitude adjustment (1) VRP(N)0[3:0] VROP(N)0 Register Resistance 0000 0R 0001 2R 0010 4R : : : : 1101 26R 1111 28R 1111 30R Amplitude adjustment (2) VRP(N)1[4:0] VROP(N)1 Register Resistance 00000 0R 00001 1R 00010 2R : : : : 11101 29R 11110 30R 11111 31R 8-to-1 selectors The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit according to the fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)1~6). The table below shows the setting in the fine adjustment register and the selected voltage levels for respective reference grayscale voltages. Register KP(N)[2:0] 000 001 010 011 100 101 110 111 VgP(N)1 VP(N)1 VP(N)2 VP(N)3 VP(N)4 VP(N)5 VP(N)6 VP(N)7 VP(N)8 Fine adjustment registers and selected voltage Selected Voltage VgP(N)8 VgP(N)20 VgP(N)43 VP(N)9 VP(N)17 VP(N)25 VP(N)10 VP(N)18 VP(N)26 VP(N)11 VP(N)19 VP(N)27 VP(N)12 VP(N)20 VP(N)28 VP(N)13 VP(N)21 VP(N)29 VP(N)14 VP(N)22 VP(N)30 VP(N)15 VP(N)23 VP(N)31 VP(N)16 VP(N)24 VP(N)32 VgP(N)55 VP(N)33 VP(N)34 VP(N)35 VP(N)36 VP(N)37 VP(N)38 VP(N)39 VP(N)40 VgP(N)62 VP(N)41 VP(N)42 VP(N)43 VP(N)44 VP(N)45 VP(N)46 VP(N)47 VP(N)48 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 94 of 112 Version: 0.08 Register KP(N)[2:0] 000 001 010 011 100 101 110 111 RMP(N)0 0R 4R 8R 12R 16R 20R 24R 28R a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Fine adjustment registers and selected resistor Selected Resistor RMP(N)1 RMP(N)2 RMP(N)3 0R 0R 0R 1R 1R 1R 2R 2R 2R 3R 3R 3R 4R 4R 4R 5R 5R 5R 6R 6R 6R 7R 7R 7R RMP(N)4 0R 1R 2R 3R 4R 5R 6R 7R RMP(N)5 0R 4R 8R 12R 16R 20R 24R 28R Figure 38 Example of RMP(N)0~5 definition The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 95 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Gamma correction resister ratio ILI9335 Data Positive polarity output voltage 00h VP0 (VgP0) 01h VP1 (VgP1) 02h VP2 (VP8+(VP1-VP8)*(30/48)) 03h VP3 (VP8+(VP1-VP8)*(23/48)) 04h VP4 (VP8+(VP1-VP8)*(16/48)) 05h VP5 (VP8+(VP1-VP8)*(12/48)) 06h VP6 (VP8+(VP1-VP8)*(8/48)) 07h VP7 (VP8+(VP1-VP8)*(4/48)) 08h VP8 (VgP8) 09h VP9 VP20+(VP8-VP20)*(22/24) 0Ah VP10 VP20+(VP8-VP20)*(20/24) 0Bh VP11 VP20+(VP8-VP20)*(18/24) 0Ch VP12 VP20+(VP8-VP20)*(16/24) 0Dh VP13 VP20+(VP8-VP20)*(14/24) 0Eh VP14 VP20+(VP8-VP20)*(12/24) 0Fh VP15 VP20+(VP8-VP20)*(10/24) 10h VP16 VP20+(VP8-VP20)*(8/24) 11h VP17 VP20+(VP8-VP20)*(6/24) 12h VP18 VP20+(VP8-VP20)*(4/24) 13h VP19 VP20+(VP8-VP20)*(2/24) 14h VP20 (VgP20) 15h VP21 (VP43+(VP20-VP43)*(22/23)) 16h VP22 (VP43+(VP20-VP43)*(21/23)) 17h VP23 (VP43+(VP20-VP43)*(20/23)) 18h VP24 (VP43+(VP20-VP43)*(19/23)) 19h VP25 (VP43+(VP20-VP43)*(18/23)) 1Ah VP26 (VP43+(VP20-VP43)*(17/23)) 1Bh VP27 (VP43+(VP20-VP43)*(16/23)) 1Ch VP28 (VP43+(VP20-VP43)*(15/23)) 1Dh VP29 (VP43+(VP20-VP43)*(14/23)) 1Eh VP30 (VP43+(VP20-VP43)*(13/23)) 1Fh VP31 (VP43+(VP20-VP43)*(12/23)) Negative polarity output voltage VN0 (VgN0) VN1 (VgN1) VN2 (VN8+(VN1-VN8)*(30/48)) VN3 (VN8+(VN1-VN8)*(23/48)) VN4 (VN8+(VN1-VN8)*(16/48)) VN5 (VN8+(VN1-VN8)*(12/48)) VN6 (VN8+(VN1-VN8)*(8/48)) VN7 (VN8+(VN1-VN8)*(4/48)) VN8 (VgN8) VN9 VN20+(VN8-VN20)*(22/24) VN10 VN20+(VN8-VN20)*(20/24) VN11 VN20+(VN8-VN20)*(18/24) VN12 VN20+(VN8-VN20)*(16/24) VN13 VN20+(VN8-VN20)*(14/24) VN14 VN20+(VN8-VN20)*(12/24) VN15 VN20+(VN8-VN20)*(10/24) VN16 VN20+(VN8-VN20)*(8/24) VN17 VN20+(VN8-VN20)*(6/24) VN18 VN20+(VN8-VN20)*(4/24) VN19 VN20+(VN8-VN20)*(2/24) VN20 (VgN20) VN21 (VN43+(VN20-VN43)*(22/23)) VN22 (VN43+(VN20-VN43)*(21/23)) VN23 (VN43+(VN20-VN43)*(20/23)) VN24 (VN43+(VN20-VN43)*(19/23)) VN25 (VN43+(VN20-VN43)*(18/23)) VN26 (VN43+(VN20-VN43)*(17/23)) VN27 (VN43+(VN20-VN43)*(16/23)) VN28 (VN43+(VN20-VN43)*(15/23)) VN29 (VN43+(VN20-VN43)*(14/23)) VN30 (VN43+(VN20-VN43)*(13/23)) VN31 (VN43+(VN20-VN43)*(12/23)) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 96 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Data 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Positive polarity output voltage VP32 (VP43+(VP20-VP43)*(11/23)) VP33 (VP43+(VP20-VP43)*(10/23)) VP34 (VP43+(VP20-VP43)*(9/23)) VP35 (VP43+(VP20-VP43)*(8/23)) VP36 (VP43+(VP20-VP43)*(7/23)) VP37 (VP43+(VP20-VP43)*(6/23)) VP38 (VP43+(VP20-VP43)*(5/23)) VP39 (VP43+(VP20-VP43)*(4/23)) VP40 (VP43+(VP20-VP43)*(3/23)) VP41 (VP43+(VP20-VP43)*(2/23)) VP42 (VP43+(VP20-VP43)*(1/23)) VP43 (VgP43) VP44 (VP55+(VP43-VP55)*(22/24)) VP45 (VP55+(VP43-VP55)*(20/24)) VP46 (VP55+(VP43-VP55)*(18/24)) VP47 (VP55+(VP43-VP55)*(16/24)) VP48 (VP55+(VP43-VP55)*(14/24)) VP49 (VP55+(VP43-VP55)*(12/24)) VP50 (VP55+(VP43-VP55)*(10/24)) VP51 (VP55+(VP43-VP55)*(8/24)) VP52 (VP55+(VP43-VP55)*(6/24)) VP53 (VP55+(VP43-VP55)*(4/24)) VP54 (VP55+(VP43-VP55)*(2/24)) VP55 (VgP55) VP56 (VP62+(VP55-VP62)*(44/48)) VP57 (VP62+(VP55-VP62)*(40/48)) VP58 (VP62+(VP55-VP62)*(36/48)) VP59 (VP62+(VP55-VP62)*(32/48)) VP60 (VP62+(VP55-VP62)*(25/48)) VP61 (VP62+(VP55-VP62)*(18/48)) VP62 (VgP62) VP63 (VgP63) Negative polarity output voltage VN32 (VN43+(VN20-VN43)*(11/23)) VN33 (VN43+(VN20-VN43)*(10/23)) VN34 (VN43+(VN20-VN43)*(9/23)) VN35 (VN43+(VN20-VN43)*(8/23)) VN36 (VN43+(VN20-VN43)*(7/23)) VN37 (VN43+(VN20-VN43)*(6/23)) VN38 (VN43+(VN20-VN43)*(5/23)) VN39 (VN43+(VN20-VN43)*(4/23)) VN40 (VN43+(VN20-VN43)*(3/23)) VN41 (VN43+(VN20-VN43)*(2/23)) VN42 (VN43+(VN20-VN43)*(1/23)) VN43 (VgN43) VN44 (VN55+(VN43-VN55)*(22/24)) VN45 (VN55+(VN43-VN55)*(20/24)) VN46 (VN55+(VN43-VN55)*(18/24)) VN47 (VN55+(VN43-VN55)*(16/24)) VN48 (VN55+(VN43-VN55)*(14/24)) VN49 (VN55+(VN43-VN55)*(12/24)) VN50 (VN55+(VN43-VN55)*(10/24)) VN51 (VN55+(VN43-VN55)*(8/24)) VN52 (VN55+(VN43-VN55)*(6/24)) VN53 (VN55+(VN43-VN55)*(4/24)) VN54 (VN55+(VN43-VN55)*(2/24)) VN55 (VgN55) VN56 (VN62+(VN55-VN62)*(44/48)) VN57 (VN62+(VN55-VN62)*(40/48)) VN58 (VN62+(VN55-VN62)*(36/48)) VN59 (VN62+(VN55-VN62)*(32/48)) VN60 (VN62+(VN55-VN62)*(25/48)) VN61 (VN62+(VN55-VN62)*(18/48)) VN62 (VgN62) VN63 (VgN63) The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 97 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 Figure 39 Relationship between Source Output and VCOM V0 N e g a tive P o la rity S o u rce O u tp u t Le ve ls P o s itiv e P o la rity V6 3 000000 G R AM Da ta 111111 Figure 40 Relationship between GRAM Data and Output Level The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 98 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 13. Application 13.1. Configuration of Power Supply Circuit ILI9335 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 99 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color Figure 41 Power Supply Circuit Block ILI9335 The following table shows specifications of external elements connected to the ILI9335’s power supply circuit. Items Capacity 1 µF (B characteristics) Recommended Specification 6.3V 10V 25V Pin connection VREG1OUT,VCI1,VDD, VCL, C11A/B, C12 A/B, C13 A/B, DDVDH, C21 A/B, C22 A/B VGH, VGL VCOMH, VCOML, The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 100 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 13.2. Display ON/OFF Sequence ILI9335 Figure 42 Display On/Off Register Setting Sequence The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 101 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 13.3. Standby and Sleep Mode ILI9335 Standby Display Off Sequence Set Standby (STB = 1) Release from Standby (STB = 0) 80ms or more Stabilizing time R10 ← 0190h Sleep Display Off Sequence Set Sleep (SLP = 1) Release from standby Release from Sleep (SLP = 0) 80ms or more Stabilizing time R10 ← 0190h Release from Sleep Display On Sequence Display On Sequence Figure 43 Standby/Sleep Mode Register Setting Sequence The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 102 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 13.4. Power Supply Configuration When supplying and cutting off power, follow the sequence below. The setting time for step-up circuits and operational amplifiers depends on external resistance and capacitance. Power Supply ON (VCC, VCI, IOVCC) VCI IOVCC GND VCI IOVCC or VCI, IOVCC Simultaneously Power On Reset and Display OFF Display OFF Setting DTE = 0 D[1:0] = 00 GON = 0 PON = 0 LCD Power Supply ON Sequence 50ms or more Stabilizing time 80ms or more Step-up circuit stabilizing time Registers setting before power supply startup Power supply initial setting Set VC[2:0], VRH[3:0], VCM[5;0], VDV[5:0], PON=0,BT[2:0] = 000 Registers setting for power supply startup Power supply operation setting Set BT[2:0],PON = 1, Set AP[2:0],APE=1, Set DC1[2:0], DC0[2:0] Operational Amplifier stabilizing time Set the other registers Display ON Sequence Display ON Set SAP=1 DTE=1 D[1:0]=11 GON=1 Normal Display Display ON Setting DTE=1 D[1:0]=11 GON=1 Display OFF Sequence Display OFF Power Supply Halt Setting SAP=0 AP[2:0] = 000 PON = 0 Power Supply OFF (VCC, VCI, IOVCC) IOVCC VCI GND IOVCC VCI Or IOVCC, VCI Simultaneously Figure 44 Power Supply ON/OFF Sequence The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 103 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 13.5. Voltage Generation The pattern diagram for setting the voltages and the waveforms of the voltages of the ILI9335 are as follows. VGH (+9 ~ 16.5V) Vci (2.5 ~ 3.3V) VLCD (4.5 ~ 5.5V) VREG1OUT (3.0 ~ (VLCD-0.5)V ) VCOMH (3.0 ~ (VLCD-0.5)V ) VCOML (VCL+0.5) ~ -1V ) VCL (0 ~ -3.3V) VGL (-4.0 ~ -16.5V) Figure 45 Voltage Configuration Diagram Note: The DDVDH, VGH, VGL, and VCL output voltage levels are lower than their theoretical levels (ideal voltage levels) due to current consumption at respective outputs. The voltage levels in the following relationships (DDVDH – VREG1OUT ) > 0.2V and (VCOML – VCL) > 0.5V are the actual voltage levels. When the alternating cycles of VCOM are set high (e.g. the polarity inverts every line cycle), current consumption is large. In this case, check the voltage before use. The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 104 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 13.6. Applied Voltage to the TFT panel ILI9335 VG H Ga te O u tp u t VCO M S ource o u tp u t VG L Figure 46 Voltage Output to TFT LCD Panel 13.7. Partial Display Function The ILI9335 allows selectively driving two partial images on the screen at arbitrary positions set in the screen drive position registers. The following example shows the setting for partial display function: BASEE NL[5:0] PTDE0 PTSA0[8:0] PTEA0[8:0] PTDP0[8:0] PTDE1 PTSA1[8:0] PTEA1[8:0] PTDP1[8:0] Base Image Display Setting 0 6’h27 Partial Image 1 Display Setting 1 9’h000 9’h00F 9’h080 Partial Image 2 Display Setting 1 9’h020 9’h02F 9’h0C0 The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 105 of 112 Version: 0.08 PTSA0=9'h000 PTEA0=9'h00F PTSA1=9'h020 PTEA1=9'h02F a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color GRAM MAP Partial Image 1 GRAM Area LCD Panel 0 (1st line) 1 (2nd line) 2 (3rd line) Partial Image 2 GRAM Area Partial Image 1 Display Area ILI9335 PTDP0=9'h080 Partial Image 2 Display Area PTDP1=9'h0C0 319 (320th line) Figure 47 Partial Display Example The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 106 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 14. Electrical Characteristics 14.1. Absolute Maximum Ratings The absolute maximum rating is listed on following table. When ILI9335 is used out of the absolute maximum ratings, the ILI9335 may be permanently damaged. To use the ILI9335 within the following electrical characteristics limit is strongly recommended for normal operation. If these electrical characteristic conditions are exceeded during normal operation, the ILI9335 will malfunction and cause poor reliability. Item Symbol Unit Value Note Power supply voltage (1) IOVCC V -0.3 ~ + 4.6 1, 2 Power supply voltage (1) VCI - GND V -0.3 ~ + 4.6 1, 4 Power supply voltage (1) DDVDH - GND V -0.3 ~ + 6.0 1, 4 Power supply voltage (1) GND -VCL V -0.3 ~ + 4.6 1 Power supply voltage (1) DDVDH - VCL V -0.3 ~ + 9.0 1, 5 Power supply voltage (1) VGH - VGL V 0.3 ~ + 30 1, 5 Input voltage Vt V -0.3 ~ VCC+ 0.3 1 Operating temperature Topr °C -40 ~ + 85 8, 9 Storage temperature Tstg °C -55 ~ + 110 8, 9 Notes: 1. GND must be maintained 2. (High) (VCC = VCC) ≥ GND (Low), (High) IOVCC ≥ GND (Low). 3. Make sure (High) VCI ≥ GND (Low). 4. Make sure (High) DDVDH ≥ GND (Low). 5. Make sure (High) DDVDH ≥ VCL (Low). 6. Make sure (High) VGH ≥ GND (Low). 7. Make sure (High) GND ≥ VGL (Low). 8. For die and wafer products, specified up to 85°C. 9. This temperature specifications apply to the TCP package The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 107 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color 14.2. DC Characteristics (VCC = VCI=2.50 ~ 3.6V, IOVCC = 1.65 ~ 3.60V, Ta= -40 ~ 85 °C) Item Symbol Unit Test Condition Input high voltage VIH V IOVCC= 1.65 ~ 3.6V Input low voltage Output high voltage(1) ( DB0-17 Pins) Output low voltage ( DB0-17 Pins) I/O leakage current Current consumption during normal operation (VCC - GND)+ (IOVCC GND ) Current consumption during standby mode (VCC - GND)+ (IOVCC GND ) VIL VOH1 VOL1 ILI IOP IST LCD Drive Power Supply Current ( DDVDH-GND ) ILCD LCD Driving Voltage ( DDVDH-GND ) Output deviation voltage DDVDH VDEV V IOVCC= 1.65 ~ 3.6V V IOH = -0.1 mA V IOVCC=1.65~3.6V µA Vin = 0 ~ VCC VCC=IOVCC=2.8V , Ta=25°C , fOSC = µA 512KHz ( Line) GRAM data = 0000h µA VCC=IOVCC=2.8V , Ta=25 °C VCI=2.8V , VREG1OUT =4.8V DDVDH=5.2V , Frame Rate: 70Hz, mA line-inversion, Ta=25 °C, GRAM data = 0000h, V - mV - Output offset voltage VOFFSET mV Note1 Note1: The Max. value is between with measure point and Gamma setting value. Min. 0.8*IOV CC -0.3 0.8*IOV CC -0.1 - - - 4.5 - ILI9335 Typ. Max. Note - IOVCC - - 0.2*IOVCC - - - - - 0.2*IOVCC - - 0.1 - TBD - - 30 50 - 5.5 - - - 6 - - 20 - - 35 - 14.3. Reset Timing Characteristics Reset Timing Characteristics (IOVCC = 1.65 ~ 3.6 V) Item Reset low-level width Reset rise time Reset high-level width Symbol tRES_L trRES tRES_H Unit ms µs ms Min. 1 50 Typ. - Max. 10 - The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 108 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 14.4. AC Characteristics 14.4.1. i80-System Interface Timing Characteristics Normal Write Mode (IOVCC = 1.65~3.6V) Item Bus cycle time Write Read Write low-level pulse width Write high-level pulse width Read low-level pulse width Read high-level pulse width Write / Read rise / fall time Setup time Write ( RS to nCS, E/nWR ) Read ( RS to nCS, RW/nRD ) Address hold time Write data set up time Write data hold time Read data delay time Read data hold time Symbol tCYCW tCYCR PWLW PWHW PWLR PWHR tWRr/tWRf tAS tAH tDSW tH tDDR tDHR Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Typ. (75) - 300 - (40) - (30 ) - 150 - 150 - - - 10 - 5 - 5 - 10 - 15 - - - 5 - Max. 500 25 100 - Test Condition - RS nCS nWR DB[17:0] (Write) nRD DB[17:0] (Read) VIH VIL tAS tcs VIH VIL tAH tchw twRf tcYcw PWLW tDSW PWHW twRr tH Valid data tAS tAH tCYCR twRf PWLR tDDR twRr tDHR PWHR Valid data Figure 48 i80-System Bus Timing The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 109 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 14.4.2. Serial Data Transfer Interface Timing Characteristics (IOVCC= 1.65 ~ 3.6V) Item Symbol Unit Min. Typ. Serial clock cycle time Serial clock high – level pulse width Serial clock low – level pulse width Serial clock rise / fall time Chip select set up time Chip select hold time Serial input data set up time Serial input data hold time Serial output data set up time Serial output data hold time Write ( received ) Read ( transmitted ) Write ( received ) Read ( transmitted ) Write ( received ) Read ( transmitted ) tSCYC µs (100) - tSCYC µs 200 - tSCH ns 40 - tSCH ns 100 - tSCL ns 40 - tSCL ns 100 - tSCr, tSCf ns - - tCSU ns 10 - tCH ns 50 - tSISU ns 20 - tSIH ns 20 - tSOD ns - - tSOH ns 5 - Max. 5 - 100 - Test Condition nCS SCL S DI S DO VIL tCS U VIH VIL tS C r VIH VIL VIH tS CYC tS CH tS Cf tS C L tC H VIH VIH VIL VIL tS IS U tS IH VIH VIL tS OD Input Da ta VIH VIL VO H VO L Output Da ta VVOOHL Input Da ta Output Da ta VO H VO L Figure 49 SPI System Bus Timing 14.4.3. RGB Interface Timing Characteristics 18/16-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.6V) Item Symbol Unit Min. Typ. Max. Test Condition VSYNC/HSYNC setup time tSYNCS ns 0 - - - ENABLE setup time tENS ns 10 - - - ENABLE hold time tENH ns 10 - - - PD Data setup time tPDS ns 10 - - - PD Data hold time tPDH ns 40 - - - DOTCLK high-level pulse width PWDH ns 40 - - - DOTCLK low-level pulse width PWDL ns 40 - - - DOTCLK cycle time tCYCD ns (150) - - - DOTCLK, VSYNC, HSYNC, rise/fall time trghr, trghf ns - - 25 - The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 110 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 6-bit Bus RGB Interface Mode (IOVCC = 1.65 ~ 3.6V) Item VSYNC/HSYNC setup time ENABLE setup time ENABLE hold time PD Data setup time PD Data hold time DOTCLK high-level pulse width DOTCLK low-level pulse width DOTCLK cycle time DOTCLK, VSYNC, HSYNC, rise/fall time Symbol tSYNCS tENS tENH tPDS tPDH PWDH PWDL tCYCD trghr, trghf Unit Min. ns 0 ns 10 ns 10 ns 10 ns 30 ns 30 ns 30 ns 80 ns - Typ. - Max. 25 Test Condition - HS YNC VS YNC HS YNC VS YNC trg b f trg b r VIH VIL tAS E tS YNCS tENS VIH VIL tENH VIH VIL trgbf VIH VIL VIH VIL P WDL tP DS trgbr VIL VIH tC YC D Write Da ta P WDH tP DH VIH VIH VIL Figure50 RGB Interface Timing The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 111 of 112 Version: 0.08 a-Si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color ILI9335 15. Revision History Version No. V0.00 V0,01 Date 2008/08/06 2008/08/14 2008/10/08 V0,02 2008/11/3 2008/11/03 V0,03 V0,04 V0,05 V0,06 V0.07 V0.08 2008/11/14 2008/11/24 2008/12/22 2008/12/30 2009/01/19 2009/02/03 Page all 104 15~24 72 96 73 100 19,20,21 82, 83 61 99 100 84 24 99,100 8,12,13, 108~111 83 110 109 40, 48, 49 13 Description new built Change condition of stand by and normal mode. Modify IC height and relative pad and alignment mark coordinate! Frame rate modified Schottky diode VCL-VGL Æ GND-VGL “04”h≦HEA-HASÆ “01”h≦HEA-HAS. Modify figure 45 Modify pad coordinate of number 674,722, 859, 907 and 931 Add deep stand by mode Add 16 bit data format Add application circuit Modify Schottky diode number and capacitor number Modify OTP flow Modify alignment mark coordinate Modify component number Modify IOVCC, VCI, VCC range to 3.6V Add wake up timing Add timing value Add timing value Delete HWM description Delete MDDI description in IOVCC The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp. Page 112 of 112 Version: 0.08

Top_arrow
回到顶部
EEWORLD下载中心所有资源均来自网友分享,如有侵权,请发送举报邮件到客服邮箱bbs_service@eeworld.com.cn 或通过站内短信息或QQ:273568022联系管理员 高进,我们会尽快处理。