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Impact of Capacitance Correlation on Yield Enhancement

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 11, NOVEMBER 2008 2097 [19] F. Brglez, D. Bryan, and K. Kozminski, “Combinational profiles of sequential benchmark circuits,” in Proc. IEEE Int. Symp. Circuits Syst., 1989, pp. 1929–1934. [20] Synopsys Test Tools,TetraMAX ATPG, 2003. [Online]. Available: http:// www.synopsys.com/products/test/tetramax_dsA4.pdf [21] Synopsys Synthesis Tools,Design Compiler, 2003. [Online]. Available: http://www.synopsys.com/products/logic/design_compiler.html Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, and Wen-Ching Wu Abstract—Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing ratio mismatch. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuits. The relationship between correlation and variation of capacitance ratio is also presented. Therefore, both mismatch and variation of capacitance ratio can be expressed in terms of capacitance correlation. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed up the time to market. Index Terms—Capacitance ratio, common centroid, mismatch, process variation, spatial correlation, yield analysis. I. INTRODUCTION As semiconductor technology continues to shrink, process variation problems will become inevitable. It is anticipated that the problem of uncontrollable process variation will become more serious. As a result, yield loss caused by process variation is becoming an important design issue. Yield loss is typically divided into the following two categories: parametric yield and defect-related yield. These losses are caused by process variation and defects, respectively. To analyze process variation in early design stages, process variation information must be input to a circuit simulator, where Monte Carlo analysis is commonly employed. More specifically, a circuit simulator applies statistical variances to device parameters and draws random values for simulations. However, statistical design and analysis processes are time consuming. The key performance of many analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold, is directly related to accurate capacitance ratios [1]. Capacitance ratio mismatch problem can be alleviated by using parallel unit capacitances [2], and the precision of the unit capacitance array can be further improved by common centroid structures [2]–[4]. These structures significantly reduce the effects of gradients and random errors in fabrication. Perfectly matched devices must satisfy the following four conditions [5]: coincidence, symmetry, dispersion, and compactness. A number of layout rules were developed to guide designers to develop an appropriate layout that meets these conditions [2]–[4]. However, the layout shape must be a rectangle to meet these four conditions. Moreover, which condition achieves better matching is generally difficult to determine without performing the time-consuming yield evaluation process. At the time of this writing, no simple rules are available in the literature to measure the degree to which the common centroid conditions are met. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuit design with the switched-capacitor (SC) technique. This paper also develops the relationship between correlation and variation of capacitance ratio. Basically, the dispersion degree of the unit capacitances for both Cs and Ct determines their degree of correlation. The results of this paper will show that the higher dispersion degree results of both Cs and Ct have higher correlation and vice versa. This directly confirms the “dispersion” condition of common centroid [5]. Thus, the correlation coefficient can be used to measure the degree to which the common centroid conditions are met without performing the yield evaluations. In general, the lower variation of capacitance ratio results in higher chip yield. A direct relationship exists between the correlation and yield enhancement, and this relationship can be used to determine whether the selected layout has the sufficient correlation (the degree of dispersion) to meet the given yield requirement. Thus, the effective process provides the degree of design quality improvement using the common centroid structures. To demonstrate the effectiveness of the proposed process for yield enhancement, a third-order sigma–delta modulator (SDM) with the SC technique is presented and implemented with 90-nm CMOS technology. The results of this study show that the yield can be enhanced by 17% without redesigning the circuit. The following section discusses the importance of device correlation to yield enhancement and reviews the spatial correlation model for capacitances. Section III addresses some important issues of capacitance correlation. Section IV presents the design and analysis of the thirdorder SDM with the SC technique. Section V provides concluding remarks. Manuscript received March 4, 2008; revised May 20, 2008 and June 30, 2008. Current version published October 22, 2008. This paper was recommended by Associate Editor H. E. Graeb. P.-W. Luo is with the Department of Electrical Engineering, National Central University, Jhongli 32001, Taiwan, and also with the SoC Technology Center, Industrial Technology Research Institute, Hsinchu 31040, Taiwan (e-mail: peiwen@itri.org.tw). J.-E. Chen and C.-L. Wey are with the Department of Electrical Engineering, National Central University, Jhongli 32001, Taiwan. L.-C. Cheng, J.-J. Chen, and W.-C. Wu are with the SoC Technology Center, Industrial Technology Research Institute, Hsinchu 31040, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAD.2008.2006139 II. SPATIAL CORRELATION MODEL Random fluctuations in process conditions change the physical properties of parameters on a chip. As a result, what you design may not be equivalent to what you get. The correlation of device parameters highly depends on their spatial locations. In general, the closer devices most likely have the similar parameter variation [6]–[8]. When the spatial correlation is taken into account, yield analysis can be achieved more accurately. Consider the nominal design of a simple RC circuit [9]. It is not difficult to derive the appropriate resistance R and capacitance C for 0278-0070/$25.00 © 2008 IEEE 2098 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 11, NOVEMBER 2008 Fig. 1. Parameter values of the RC circuit: (a) Nominal design. (b) With design centering. (c) With device correlation in design centering. its best performance. Suppose that the acceptable design region shown in Fig. 1 represents the parameter space in which any pair (R, C) selected from this region will produce acceptable performance. Once the values of R and C are selected in the nominal design, the ellipse region represents the nominal values with process variations. Yield is defined as the percentage of the pass region over the ellipse region. Thus, the yield is approximately 50%, as shown in Fig. 1(a). In practice, however, the design centering approach may be applied to enhance the yield. For simplicity, appropriate parameters R∗ and C∗ may be selected without considering the correlation between R∗ and C∗, as shown in Fig. 1(b). This approach increases the overlap region and thus improves the yield. In the real world, some correlations between devices and the systematic mismatch of devices cannot be ignored. Otherwise, situations of overkill or overpass may occur, leading to incorrect yield estimation results. Therefore, it is necessary to take the correlation of devices into consideration. With the design centering approach, the resulting overlapped region may significantly increase, and so does the chip yield, as shown in Fig. 1(c). In [10], a spatial correlation model of N -element 1-D device string, Ri, i = 1, 2, . . . , N , was proposed. The correlation coefficient of any two devices, namely, Rin and Rim, is defined as ρD(in,im)L, where 0 < ρ < 1, 0 < in, im ≤ N − 1, and L is the unit distance between the devices. Note that D(in, im) = |in − im| ∗ L is the distance between both devices. This study extends the model to 2-D capacitance arrays. Consider an N -by-N unit capacitances array Ci,j, where 0 < i and j ≤ N − 1. The correlation coefficient of any two capacitances Ci1,j1 and Ci2,j2 is defined as ρD(i,j), where 0 < ρ < 1, and the distance D(i, j) is D = (i2 − i1)2 + (j2 − j1)2L (1) where L is dependent on the process and size of devices. To simplify the experiment, this study assumes that L = 1 to observe the relationship between correlation and mismatch in this paper. III. CORRELATION COEFFICIENTS and Ct is implemented with q unit capacitances, i.e., Ct = Ct1 + Ct2 + · · · + Ctq. Let ρs(i,j), ρt(i,j), and ρst(i,j) denote the correlation coefficients between Csi and Csj, between Cti and Ctj, and between Csi and Ctj, respectively. For any two capacitances Cs and Ct, there exists a relationship between Var(Cs/Ct) and the correlation coefficients. Let ρcst denote the correlation coefficient between Cs and Ct, as described in the following property. Property 1: A higher correlation coefficient ρcst results in a smaller Var(Cs/Ct). Proof: Assume that all unit capacitances have the same variances, i.e., Var(Csi) = Var(Cu), where i = 1, . . . , p, and Cov(Csi, Csj ) = Var(Cu)∗ρs(i,j). The variation of Cs can be derived as p p−1 p Var(Cs) = Var(Csi) + 2 Cov(Csi, Csj ) i=1 i=1 j=i+1 = Var(Cu)[p + 2ScsA]. Similarly Var(Ct) = Var(Cu)[q + 2SctB] where P −1 P ScsA = ρs(i,j) i=1 j=i+1 q−1 q SctB = ρt(i,j ) . i=1 j=i+1 The covariance of Cs and Ct can be obtained as pq Cov(Cs, Ct) = Cov(Csi, Ctj ) = Var(Cu)SstD i=1 j=1 where SstD = p i=1 q j=1 ρst(i,j ) . Based on [11], the variation of (Cs/Ct) can be expressed as follows: Taking the device correlation into consideration during design centering may enhance the chip yield. This section addresses some important issues related to correlation coefficients of capacitances. The first part discusses the relationship between correlation and variation of capacitance ratio. A description of how to use this correlation as a measure of common centroid structure then follows. A. Correlation and Variation of Capacitance Ratio Consider the ratio of both capacitances Cs and Ct. Suppose that Cs is realized by p unit capacitances, i.e., Cs = Cs1 + Cs2 + · · · + Csp, Var Cs Ct = μCs μCt 2 Var(Cs μ2Cs ) + Var(Ct μ2Ct )−2Cov(Cs, Ct μCs μCt ) 1 = μ4Ct μ2Ct Var(Cs)+μ2Cs Var(Ct) − 2μCs μCt Cov(Cs, Ct) = Var(Cu) μ4Ct μ2Ct (p + 2ScsA)+μ2Cs (q +2SctB ) − 2μCs μCt SstD . (2) IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 11, NOVEMBER 2008 2099 Fig. 2. Capacitance placement illustration. (a) Layout 1. (b) Layout 2. Fig. 4. ρcst of different layout shapes. (a) ρcst = 0.533. (b) ρcst = 0.792. (c) ρcst = 0.712. (d) ρcst = 0.783. the sigma of the unit capacitances (σu) is 0.3, and the correlation coefficient of the unit capacitances (ρu) is 0.5. The capacitance Cs includes three unit capacitances, namely, Cs1, Cs2, and Cs3, while Ct consists of nine unit capacitances, namely, Ct1, Ct2, . . . , Ct9, i.e., p = 3 and q = 9. Based on the spatial correlation model with these conditions, this study uses MATLAB to generate 2000 samples of each unit capacitance for different placements (Fig. 2). Results show that Var(Cs/Ct)(a) > Var(Cs/Ct)(b) and ρcst(a) < ρcst(b), i.e., a higher correlation coefficient results in smaller Var(Cs/Ct), as shown in Fig. 3. Different layouts of Cs and Ct may result in different correlation coefficients ρcsA, ρctB, and ρstD. According to Property 1, the correlation coefficients affect the variance Var(Cs/Ct). Therefore, this paper concludes that the dispersion degree of the unit capacitances in both Cs and Ct determines the correlation coefficient ρcst. The higher dispersion degree results show that both Cs and Ct have higher correlation. This directly confirms the “dispersion” rule in common centroid [5]. Fig. 3. Relationship between Var(Cs/Ct) and ρcst of Fig. 2. (a) Result illustration. (b) Result data. The correlation coefficient ρcst can be expressed as ρcst = Cov(Cs, Ct) = Var(Cs)Var(Ct) SstD . (3) [p + 2ScsA][q + 2SctB] If X2 = p + 2ScsA and Y 2 = q + 2SctB, then the correlation coefficient ρcst can be written as SstD = ρcst(XY ). (4) By assuming that μcs = pμu and μct = qμu Var Cs Ct ∝ 1 q4 q2(p+2ScsA)+p2(q +2SctB)−2pqSstD 1 = q4 q2X2 +p2Y 2 −2pqρcst(XY ) . Since XY > 0, we have Var(Cs/Ct) ∝ −ρcst. In other words, a higher correlation coefficient ρcst results in a smaller Var(Cs/Ct). The layouts of unit capacitance arrays in Fig. 2 demonstrate Property 1. By assuming that unit capacitances (μu’s) are 1 pF, B. Correlation and Common Centroid Property 1 shows that a higher correlation leads to the lower variation in the capacitance ratio or to a higher matching capacitance ratio. On the other hand, common centroid structures alleviate the capacitance ratio mismatch problem. Thus, the correlation coefficient may be used as a measure of the quality of common centroid structures. Consider the case where a given capacitance ratio can be implemented by two different layouts, as in Fig. 4(a) and (b). Comparing both layouts in Fig. 4(a) and (b) with the common centroid conditions clearly shows that both layouts virtually have the same degrees of coincidence, symmetry, and compactness. However, the layout in Fig. 4(b) has a higher dispersion than that in Fig. 4(a). Thus, the layout quality in Fig. 4(b) is “better” than that in Fig. 4(a) as far as the common centroid structures are concerned. In fact, we can calculate the corresponding correlation coefficients as 0.533 and 0.792 for the layouts in Fig. 4(a) and (b), respectively. This supports the notion that the layout with the higher correlation results in a better quality of the common centroid structure. Common centroid structures are generally perfect squares or rectangular shapes. However, the target area may not be regular due to size limitations. The existing literature contains no simple rules for determining the quality of the common centroid structures with irregular shapes. The layouts realize the same capacitance ratios with the obstacle, as shown in Fig. 4(c) and (d). Based on the computed correlation coefficients, the layout with the best quality can be easily identified. In this example, the layout in Fig. 4(d) with the highest correlation coefficient of 0.783 will result in the lowest variation of the capacitance ratio. 2100 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 11, NOVEMBER 2008 Fig. 6. Third-order SDM [13]. Fig. 5. SC second-order sigma–delta ADC [12]. (a) Linearized model. (b) Transistor level. IV. EXPERIMENTAL RESULTS This section presents the yield enhancement of a third-order SC SDM design in 90-nm CMOS technology. This section reviews the basic modular design process with nominal design and then examines the performance variations of the modulator design with the correlation data. A. SDM Design Oversampled SDMs [7], [12], [13] are commonly used in ADCs for high-resolution applications. For instance, Fig. 5(a) and (b) shows the build blocks for developing a second-order sigma–delta ADC [12]. Once the system-level analysis process is completed, the transistorlevel design takes place. The output signal can be expressed as follows: abz−1 Y (z) = 1 + (b − 2)z−1 + (ab − b + 1)z−2 ·X (z ) + 1+ (b − (1 − z−1)2 2)z−1 + (ab − b+ 1)z−2 · E(z). The output signal is highly dependent on coefficients a and b. Both coefficients have a great impact on the modulator’s signal-to-noise (SNR) ratio. The capacitance ratios C1/C2 and C3/C2 correspond to the coefficients a and b in both stages of the modulator (Fig. 5), respectively. The capacitance mismatch may cause the variation in the coefficients. Thus, capacitance mismatch is an important factor in determining the quality of the designed modulator. B. Yield Analysis To demonstrate the impact of capacitance correlation on yield enhancement in analog design, a more complicated SC modulator is presented. As Fig. 6 shows, a1 = 0.2, a2 = 0.3, and a3 = 0.4 were assigned in the modulator [13]. A single-loop third-order modulator was implemented in 90-nm CMOS technology. Simulation results show that the designed circuit meets the design specification with an SNR of 85 dB. In this implementation, the sampling and integrating capacitances are realized by unit capacitance arrays, where the unit capacitance Fig. 7. (a) Simple layout of the third-order SDM. (b) Alternative layout of the third-order SDM. (c) Layout with obstacle for the third-order SDM. Cu = 0.5 pF and the integrating capacitance Cin = 10 pF are assumed. To realize the coefficients a1 = 0.2, a2 = 0.3, and a3 = 0.4, the corresponding sampling capacitances are Csa1 = 2 pF, Csa2 = 3 pF, and Csa3 = 4 pF. In other words, the total number of unit capacitances in this implementation is (10 ∗ 3 + 2 + 3 + 4)/0.5 or 78. Use three 6-by-5 subarrays to implement the capacitance layouts of the coefficients a1, a2, and a3, respectively, as shown in Fig. 7(a) and (b). For example, the first subarray contains 4 unit capacitances for sampling capacitance, 20 unit capacitances for integrating capacitance, and 6 dummy unit capacitances. Similarly, the second and the third subarray are the same expression. Assume that the sigma of the unit capacitances is 10%, i.e., σu = 0.5 pF ∗ 10% = 0.05 pF for Cu = 0.5 pF. Based on the foundry document for the 90-nm process node, we can derive the correlation coefficient of the unit capacitance ρu as 0.9. Using these settings and capacitance placements, this paper simulated 200 samples of each unit capacitance for the modulator at the system level. For yield evaluation, a designed circuit is marked as “PASS” if the resulting SNR exceeds 14 b. Yield is defined as the number of “PASS” marks over the total number of samples. Fig. 7(a) shows a yield of 76.5%, and the correlation coefficients for a1, a2, and a3 are ρcst(a1) = 0.892, ρcst(a2) = 0.899, and ρcst(a3) = 0.894, respectively. On the other hand, the simulation results in Fig. 7(b) show that the yield is 93.5%. In fact, the correlation coefficients of a1, a2, and a3 can be calculated as ρcst(a1) = 0.98, ρcst(a2) = 0.981, and ρcst(a3) = 0.983, respectively. This example demonstrates that the yield can be improved from 76.5% to 93.5% by rearranging the layout of the unit capacitances for IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 11, NOVEMBER 2008 2101 the ratios a1, a2, and a3, without redesigning the circuit. The layouts in Fig. 7(a) and (b) also support Property 2, where a higher correlation coefficient results in a lower variation of capacitance ratios and lower SNR variation in the SDM. Thus, the chip yield is enhanced. In the real world, however, designers may not always have the regular area in which the layout is arranged. For example, an obstacle exists behind the area, as Fig. 7(c) shows. With the use of common centroid structures, designers may encounter the following problems: 1) There are no simple rules to follow, and 2) they cannot evaluate the yield without executing the time-consuming yield analysis process. Moreover, based on Property 1, the simple process of computing correlation coefficients can be used to select an appropriate layout. Computing the correlation coefficient is much easier than computing the yield evaluation. Thus, designers can derive an appropriate layout, as shown in Fig. 7(c), which has reasonably high correlation coefficients. As in the previous two cases, 200 sample designs were simulated and tested; a yield of 90.5% was achieved. V. CONCLUSION This paper addresses the impact of capacitance correlation on yield enhancement for mixed-signal/analog integrated circuit design using the SC technique. This paper also presents the relationship between correlation and variation of capacitance ratio. Thus, the correlation coefficient can be used to measure the degree to which the common centroid conditions are met without performing the yield evaluation process. Based on the simulation results for a third-order SDM, with different layouts of the unit capacitances for the various capacitance ratios, the yield can be improved from 76.5% to 93.5% for a rearranged layout without redesigning the modulator. Unlike the conventional common centroid structures, which can be applied only for regular structures, the proposed process can be used for any structures for yield enhancement. Moreover, this paper develops a yield analysis approach at the system level which can be applied in the front-end design flow, where process variation and device mismatch can be considered simultane- ously in an early design phase. This approach makes it possible to reduce the design cost and speed up the time to market. REFERENCES [1] M. J. McNutt, S. LeMarquis, and J. L. Dunkley, “Systematic capacitance matching errors and corrective layout procedures,” IEEE J. Solid-State Circuits, vol. 29, no. 5, pp. 611–616, May 1994. [2] D. Khalil, M. Dessouky, V. Bourguet, M. M. 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