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Cadence使用参考手册

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Cadence使用参考手册。 

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Cadence 使用参考手册 目录 概 述 .....................................................................................................1 1.1 Cadence 概 述 ................................................................................................ 1 1.2 ASIC 设 计 流 程 ............................................................................................. 1 第一章 Cadence 使用基础......................................................... 5 2.1 Cadence 软 件 的 环 境 设 置 .........................................................................5 2.2 Cadence 软 件 的 启 动 方 法 ........................................................................10 2.3 库 文 件 的 管 理 .............................................................................................12 2.4 文 件 格 式 的 转 化 ........................................................................................ 13 2.5 怎 样 使 用 在 线 帮 助 ...................................................................................13 2.6 本 手 册 的 组 成 ............................................................................................14 第二章 Verilog-XL 的介绍...................................................... 15 3. 1 环 境 设 置 ................................................................................................... 15 3.2 Verilog-XL 的 启 动 .................................................................................... 15 3.3 Verilog- XL 的 界 面 ................................................................................. 17 3.4 Verilog-XL 的 使 用 示 例 ........................................................................... 18 3.5 Verilog-XL 的 有 关 帮 助 文 件 .................................................................. 19 第四章 电路图设计及电路模拟............................................... 21 4.1 电 路 图 设 计 工 具 Composer....................................................................21 4.1.1 设 置 ................................................................................................... 21 4.1.2 启 动 ................................................................................................... 22 4.1.3 用 户 界 面 及 使 用 方 法 ....................................................................22 4.1.4 使 用 示 例 .......................................................................................... 24 4.1.5 相 关 在 线 帮 助 文 档 ........................................................................ 24 4.2 电 路 模 拟 工 具 Analog Artist..................................................................24 4.2.1 设 置 ................................................................................................... 24 4.2.2 启 动 ................................................................................................... 25 4.2.3 用 户 界 面 及 使 用 方 法 ....................................................................25 4.2.5 相 关 在 线 帮 助 文 档 ........................................................................ 25 第五章 自动布局布线................................................................. 27 5.1 Cadence 中 的 自 动 布 局 布 线 流 程 .......................................................... 27 5.2 用 AutoAbgen 进 行 自 动 布 局 布 线 库 设 计 .......................................... 28 第六章 版图设计及其验证.......................................................30 6.1 版 图 设 计 大 师 Virtuoso Layout Editor................................................ 30 6.1.1 设 置 ................................................................................................... 30 6.1.2 启 动 ................................................................................................... 30 6.1.3 用 户 界 面 及 使 用 方 法 ....................................................................31 6.1.4 使 用 示 例 .......................................................................................... 31 6.1.5 相 关 在 线 帮 助 文 档 ........................................................................ 32 6.2 版 图 验 证 工 具 Dracula............................................................................ 32 6.2.1 Dracula 使 用 介 绍 ............................................................................32 6.2.2 相 关 在 线 帮 助 文 档 ........................................................................ 33 第七章 skill 语言程序设计........................................................ 34 7.1 skill 语 言 概 述 ............................................................................................ 34 7.2 skill 语 言 的 基 本 语 法 ............................................................................... 34 7.3 Skill 语 言 的 编 程 环 境 .............................................................................. 34 7.4 面 向 工 具 的 skill 语 言 编 程 ..................................................................... 35 附录 1 技术文件及显示文件示例............................................ 60 附录 2 Verilog-XL 实例文件.......................................................72 1. Test_memory.v..................................................................................... 72 2. SRAM256X8.v..................................................................................... 73 3. ram_sy1s_8052.................................................................................... 79 4. TSMC 库 文 件 ...................................................................................... 84 附录 3 Dracula 命令文件..........................................................359 Cadence 使用说明 概述 第 1 页 共 389页 z1.1 Cadence 概述 Cadence 是一 个大型 的 EDA 软件 ,它几 乎可以 完成电 子设计 的方方 面面, 包 括 ASIC 设 计 、FPGA 设 计 和 PCB 板 设 计 。与 众 所 周 知 的 EDA 软 件 Synopsys 相 比 , Cadence 的 综 合 工 具 略 为 逊 色 。 然 而 , Cadence 在 仿 真 、 电 路 图 设 计 、自 动布局布线、版图设计及验证等方面却有着绝对的优势。Cadence 与 Synopsys 的结 合可以 说是 EDA 设计 领域的 黄金搭 档。此外 ,Cadence 公司 还开发 了自己 的 编 程 语 言 skill,并 为 其 编 写 了 编 译 器 。 由 于 skill 语 言 提 供 编 程 接 口 甚 至 与 C 语言的接口,所以可以以 Cadence 为平台进行扩展,用户还可以开发自己的基 于 Cadence 的工 具 。实际 上,整个 Cadence 软件 可以 理解为 一个 搭建在 skill 语 言 平 台 上 的 可 执 行 文 件 集 。所 有 的 Cadence 工 具 都 是 用 Skill 语 言 编 写 的 ,但 同 时,由于 Cadence 的工具太多,使得 Cadence 显得有点凌乱。这给初学者带来 了更多的麻烦。 Cadence 包 含 的 工 具 较 多 ,几 乎 包 括 了 EDA 设 计 的 方 方 面 面 。本 小 册 子 旨 在 向初 学者 介绍 Cadence 的 入门 知识 ,所 以不 可 能面 面具 到, 只能 根 据 ASIC 设 计 流 程 ,介 绍 一 些 ASIC 设 计 者 常 用 的 工 具 ,例 如 仿 真 工 具 Verilog-xl,布 局 布 线 工 具 Preview 和 Silicon Ensemble, 电 路 图 设 计 工 具 Composer, 电 路 模 拟 工 具 Analog Artist,版 图 设 计 工 具 Virtuoso Layout Editor,版 图 验 证 工 具 Dracula,最 后 介绍一下 Skill 语言的编程。 1.2 ASIC 设计流程 设计流程是规范设计活动的准则,好的设计流程对于产品的成功至关重 要。本节 将通 过与 具体的 EDA 工具( Synopsys 和 Cadence)相结 合,概括 出一 个 实 际 可 行 的 ASIC 设 计 的 设 计 流 程 。图 1- 1 是 实 际 设 计 过 程 中 较 常 用 的 一 个 流程。 Cadence 使用说明 第 2 页 共 389页 (接下一页) Cadence 使用说明 第 3 页 共 389页 图 1-1 ASIC 设计流程图 这 是 深 亚 微 米 设 计 中 较 常 用 的 设 计 流 程 。在 该 设 计 流 程 中 ,高 层 次 综 合 和 底 层 的 布 局 布 线 之 间 没 有 明 显 的 界 线 ,高 层 设 计 时 必 须 考 虑 底 层 的 物 理 实 现( 高 Cadence 使用说明 第 4 页 共 389页 层 的 划 分 与 布 局 规 划 )。同 时 ,由 于 内 核( Core)的 行 为 级 模 型 有 其 物 理 实 现 的 精确的延时信息,使得设计者可在设计的早期兼顾芯片的物理实现,从而可以 较精确的估计互连的延时,以达到关键路径的延时要求。同时,布局布线后提 取的 SDF 文件将被反标到综合后的门级网表中以验证其功能和时序是否正确。 从 该 流 程 中 可 看 出 , 在 实 际 设 计 中 较 常 用 到 的 Cadence 的 工 具 有 Verilog HDL 仿 真 工 具 Verilog-XL,电 路 设 计 工 具 Composer,电 路 模 拟 工 具 Analog Artist, 版 图 设 计 工 具 Virtuoso Layout Editor,版 图 验 证 工 具 Dracula 和 Diva 以 及 自 动 布 局 布 线 工 具 Preview 和 Silicon Ensemble。本 册 子 将 对 这 些 工 具 作 一 个 初 步 介 绍 。 如果读者想进一步了解某个软件的使用,可参考本册子提供的相关在线文档以 进一步熟练。 Cadence 使用手册 基础 第二章 Cadence 使用 第一章 Cadence 使用基础 2.1 Cadence 软件的环境设置 要 使 用 Cadence,必 须 在 自 己 的 计 算 机 上 作 一 些 相 应 的 设 置 ,这 些 设 置 包 括 很多方面,而且不同的工具可能都需要进行各自的设置。读者如果遇到这方面 的 问 题 , 可 以 参 考 一 下 openbook 中 的 Configuration Guides 及 各 工 具 的 user guide 或 者 reference, 其 访 问 的 方 法 是 main menu-> System Administration-> Configuration Guides。但作 为初学者 ,只需进行 以下几项设 置: 1. .cshrc 文件的设置 首先要在自己的.cshrc 文件中设置 Cadence 软件所在的路径,所使用的 licence 文 件 等 。 下 面 的 代 码 为 .cshrc 中 设 置 的 一 个 简 单 示 例 , 其 中 Cadence 所在的 目录为 /EDA04/cds97a/。 ############################## ## Cadence # ############################## # setenv CDS_ROOT /EDA04/cds97a setenv CDS_INST_DIR /EDA04/cds97a set path = ($path $CDS_INST_DIR/tools/dfII/bin $CDS_INST_DIR/tools/bin) setenv LM_LICENSE_FILE /EDA04/cds97a/share/license/license.dat 对于某些 Cadence 中的工具也必须在.cshrc 中进行一些设置。 2. .cdsenv 文件设置 .cdsenv 文件中包含了 Cadence 软件的一些初始设置,该文件是用 Skill 语言写 成的。Cadence 可直接 执行。 3. .cdsinit 设置 与.cdsenv 一样 ,.cdsinit 中也 包含了 Cadence 软件 的一些初 始化设 置, 该 文 件 是 用 Skill 语 言 写 成 的 。 在 Cadence 启 动 时 , 会 首 先 自 动 调 用 这 Cadence 使用手册 基础 第二章 Cadence 使用 两个文件并执行其中的语句。若仅为初学,可以不编写这两个文件, Cadence 会自 动调 用隐 含的 设置 。若 想更 改设置 ,可 参考 一些 模板 文件 进 行 编 写 。 在 install_dir/tools/dfII/cdsuser 目 录 下 有 一 些 隐 含 的 模 板 文 件。下面是一个简单的.cdsinit 文件: ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; Tutorial .cdsinit file ; By: Cris Reeser/Diane Goldberg ; Created: October 10, 1995 ; ; This initialization file contains the settings necessary to ; successfully run the Cell Design tutorial. Some of these may ; be redundant, if your site uses a site initialization file. ; For further information on initialization files, read the ; comments in the /samples/local/cdsinit file. ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; Human Interface Environment Settings hiiSetFont("text" "-adobe-courier-bold-r-*-*-12-*") hiSetFormPosition(603:500) hinestLimit = 5 hiSetUndoLimit(10) hiExpertMode(nil) window(1)->useScrollbars = t window(1)->backingStore = t envSetVal("layout" "xSnapSpacing" 'float 0.5) envSetVal("layout" "ySnapSpacing" 'float 0.5) envSetVal("layout" "segSnapMode" 'string "anyAngle") envSetVal("layout" "stopLevel" 'int 20) envLoadFile("./.cdsenv") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; Cadence 使用手册 基础 第二章 Cadence 使用 ; ; Bindkey Settings load(prependInstallPath("samples/local/schBindKeys.il")) load(prependInstallPath("samples/local/leBindKeys.il")) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; RESIZE CIW ; CIW ; Note, hiFlush() is used as a workaround to display problem with ; resizing windows in SKILL. hiFlush() hiResizeWindow(window(1) list(3:3 750:200)) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; Tutorial Customization ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; setSkillPath(". techFiles") ; Welcome the user fprintf(poport "************************************************\n") fprintf(poport "Welcome to the SRAM Compiler... %s\n" getShellEnvVar("USER")) printf( " \n" ) printf( "Done with initialization.\n" ) printf("************************************************\n" ) printf( " \n" ) printf( " \n" ) 从 中可 看出 ,Skill 语 言的 语法 与 C 语 言的 较为 类 似。 经过 一 定的 学 习后 Cadence 使用手册 基础 第二章 Cadence 使用 就很容易掌握。 4. cds.lib 文件的设置 如 果 用 户 需 要 加 入 自 己 的 库 , 则 可 以 修 改 自 己 的 库 管 理 文 件 cds.lib。对 于初次使用 Cadence 的用户,Cadence 会在用户的当前目录下生成一个 cds.lib 文 件 , 用 户 通 过 CIW 生 成 一 个 库 时 , Cadence 会 自 动 将 其 加 入 cds.lib 文件中。下面是一个简单的 Cadence 库管理文件 cds.lib 的示例: DEFINE ourTechLib /EDAHOME01/students/dhf/sram/dual/ourTechLib DEFINE sram /EDAHOME01/students/dhf/sram/dual/sram DEFINE basic ${CDS_INST_DIR}/tools/dfII/etc/cdslib/basic DEFINE sample ${CDS_INST_DIR}/tools/dfII/samples/cdslib/sample DEFINE analogLib /EDA04/cds97a/tools/dfII/etc/cdslib/artist/analogLib DEFINE pCells /EDAHOME01/students/dhf/sram/dual/pCells DEFINE hhh /EDAHOME01/students/dhf/sram/dual/hhh 其中,DEFINE 为库定义的保留字 ,ourTechLib、sram 等为所定义 的库的名字,最后的字符串为保存库的实际的物理目录。 5. 技术库的生成 技 术 文 件 库 对 于 IC 设 计 而 言 是 非 常 重 要 的 , 其 中 包 含 了 很 多 设 计 中 所 必 需 的 信 息 。对 于 版 图 设 计 者 而 言 ,技 术 库 就 显 得 更 为 重 要 了 。要 生 成 技 术 文 件 库 ,必 须 先 编 写 技 术 文 件 。技 术 文 件 主 要 包 括 层 的 定 义 ,符 号 化 器 件 的 定 义 ,层 、物 理 以 及 电 学 规 则 和 一 些 针 对 特 定 的 Cadence 工 具 的 规 则 的 定 义 ,例 如 自 动 布 局 布 线 的 一 些 规 则 ,版 图 转 换 成 GDSII 时 所 用到 的层 号的 定义。 技术 文件的 编写 可参 考 openbook 中有 关技 术文 件 的 介 绍 并 参 考 相 应 的 模 板 来 进 行 。 其 访 问 顺 序 为 Main Menu->IC Tools->Design FramWork II->Technology File Help 。 附 录 1 中 有 一 个 简 单 的 技 术 文 件 示 例 。技 术 文 件 编 好 以 后 ,就 可 以 按 照 以 下 几 步 生 成 技 术 库: ( 1) 点 击 CIW 中 的 File 菜 单 选 择 其 中 的 New 项 中 的 Library 项( 如 图 2- 1 所 示 ), 弹 出 图 2- 2 所 示 的 表 格 。 ( 2) 在 Name 项 中 输 入 所 需 的 名 字 如 myTecLib。保 持 如 图 所 示 的 设 Cadence 使用手册 基础 第二章 Cadence 使用 置,点击 ok。弹出如图 2-3 所示的对话框。 ( 3) 在 对 话 框 中 输 入 编 好 的 技 术 文 件 名 如 my.tf。这 时 ,技 术 文 件 必 须在启动 Cadence 的当前目录。点击 ok。 (4) 经过一 段时间后 ,在 CIW 的显示 区会出现 一个提示 Library myTecLib is created successfully. 对于非工艺库的生成与工艺库大体相同,只是在 2-2 中选择 attach to exited technology file,并在接 下来的过 程中选择相 应的工艺库 。 图 2-1 图 2-2 Cadence 使用手册 基础 图 2-3 第二章 Cadence 使用 6. 显 示 文 件 display.drf 的 设 置 display.drf 文 件 控 制 Cadence 的 显 示 。其 基 本 语 法 可 参 考 openbook 中 的 相 应 的 介 绍 。 附 录 1 中 包 含 了 一 个 display.drf 的 示 例 。 2.2 Cadence 软件的启动方法 完 成 了 一 些 必 要 的 设 置( 对 初 学 者 只 需 设 置 .cshrc 文 件 即 可 ,其 他 设 置 都 用 隐 含 设 置 , 等 熟 练 了 一 些 之 后 , 再 进 一 步 优 化 自 己 的 使 用 环 境 ), 就 可 以 启 动 Cadence 软 件 。 启 动 Cadence 软 件 的 命 令 有 很 多 , 不 同 的 启 动 命 令 可 以 启 动 不 同的工具集,常用的启动命令有 icfb,icca 等,也可以单独启动单个工具,例如 启 动 Viruoso Layout Editor 可 以 用 layoutPlus 来 启 动 , Silicon Ensemble 可 以 用 sedsm 来 启 动 。以 icfb 为 例 ,先 在 UNIX 提 示 符 下 输 入 icfb&,再 按 回 车 ,经 过 一 段 时 间 , 就 会 出 现 如 图 2- 4 所 示 的 CIW( Command Interpreter Window) 窗 口。从 CIW 窗口就可以调用许多工具并完成许多任务。 CIW 窗 口 是 使 用 Cadence 时 遇 到 的 第 一 个 窗 口 , 是 Cadence 主 要 的 用 户 界 面。它主要包括以下几个部分: 1. Title Bar 显 示 使 用 的 软 件 名 及 log 文 件 目 录 。 如 图 2- 4 中 的 最 上 一行 icfb-log:/ EDAHOME01/students/dhf/CDS.log。 2. Menu Banner 3. Output Area 输出 Cadence 对用户 命令的反 应。 4. Input Line 可用来 输入 Skill 命令。 5. Mouse Bindings Line 显示捆 绑在鼠标 左中右三键 上的快捷键 。 6. Scrolling bar to Scroll Through the Log File Cadence 将许多常用工具集成在一块以完成一些典型的任务,图 2-5 总结 了一些常用的启动命令及其可使用的工具。用户可根据自己的需要选择最少的 命令集。 Cadence 使用手册 基础 第二章 Cadence 使用 图 2-4 CIW 窗口 图 2-5 Cadence 启动命令 2.3 库文件的管理 启 动了 Cadence 后 ,就 可 以 利用 File 菜 单建 立 自 己的 工 作库 , 点击 CIW Cadence 使用手册 基础 第二章 Cadence 使用 窗 口 上 的 File 菜 单 , 选 定 其 中 的 New lib 项 , 弹 出 如 图 2- 2 所 示 的 对 话 框 ,输 入库名并选择相应的工艺库,然后选择 ok,这时在 CIW 的显示区会出现如下提 示: The lib is created successfully! 新 建 的 库 是 一 个 空 的 库 ,里 面 什 么 也 没 有 ,用 户 可 在 库 中 生 成 自 己 所 需 的 单元。例如可以生成一个反相器单元,并为其生成一个电路及一个版图视图, 其流程如下: 1. 选 择 File 菜 单 中 的 New 项 , 并 选 择 Cellview 项 , 则 弹 出 如 图 2-6 所示的对话框,选择所需的库并输入单元名 inv,并选择视 图 类 型 Schematic,再 点 击 ok 按 钮 。则 弹 出 如 图 2- 7 所 示 的 窗 口。 2. 用 Add 菜 单 中 的 Component 命 令 调 用 analogLib 中 的 单 元 , 输 入 PMOS 和 NMOS 管以及 电源和地 。如图 2-8 所示。 3. 点击 Check and save 命令保 存。 用 同 样 的 流 程 可 生 成 inv 的 版 图 视 图 。 利 用 Tools 中 的 library manager 可 以对库进行管理。 Cadence 使用手册 基础 第二章 Cadence 使用 图 2-6 图 2-7 Cadence 使用手册 基础 第二章 Cadence 使用 2.4 文件格式的转化 图 2-8 Cadence 有 自 己 的 内 部 数 据 格 式 ,为 了 与 其 他 EDA 软 件 之 间 进 行 数 据 交 换 , Cadence 提 供 内 部 数 据 与 标 准 数 据 格 式 之 间 的 转 换 。点 击 CIW 的 File 菜 单 中 的 Import 可 将 各 种 外 部 数 据 格 式 转 换 成 Cadence 内 部 数 据 格 式 ,利 用 CIW 的 File 菜单中 的 Export 可将各 种 Cadence 内部数 据格式转 换成外部标 准数据格式 。 2.5 怎样使用在线帮助 学 习 Cadence 的 最 好 教 材 是 使 用 在 线 帮 助 , Cadence 的 在 线 帮 助 是 用 openbook 命令 来启动 的。在 UNIX 提示 符下输 入 openbook&并回 车就可 以启 动 在 线 帮 助 。要 拷 贝 在 线 帮 助 中 的 文 件 可 以 先 按 下 control 键 ,并 用 左 键 进 行 选 择 , 然后用 copy 进行拷贝。如果想要知道一些关于如何使用 openbook 的技巧,可 在系统提示符下输入 openbook help & 即可。 Cadence 使用手册 基础 2.6 本手册的组成 第二章 Cadence 使用 在 本 手 册 中 将 按 照 ASIC 设 计 流 程 分 别 在 第 三 章 介 绍 高 层 的 HDL 工 具 ,例 如 Verilog 仿 真 工 具 Verilog-xl。第 四 章 介 绍 电 路 图 设 计 工 具 Composer 及 电 路 模 拟 工 具 Analog Artist。 第 五章 介 绍 自动 布 局 布线 Preview 和 Silicon Ensemble。 第 六 章 介 绍 版 图 设 计 工 具 Virtuoso Layout Editor 和 验 证 工 具 Dracula 和 Diva 。 第七章将介绍 Skill 语言的编程。 Cadence 使用手册 介绍 第三章 Verilog-XL 的 第二章 Verilog-XL 的介绍 人们在进行电子设计时较常用的输入方法有两种,一种为硬件描述语言, 一 种 为 电 路 图 输 入。随 着 ASIC 设 计 技 术 的 发 展 ,以 HDL 作 为 输 入 的 设 计 方 法 已 成 为 ASIC 设 计 的 主 流 。目 前 较 常 用 的 硬 件 描 述 语 言 有 VHDL 和 Verilog 两 种 。 相 对 而 言 ,Verilog 在 工 业 上 用 的 较 为 平 常 。故 本 小 册 子 的 讨 论 集 中 在 Verilog 上 。 作 为 EDA 设 计 的 主 流 软 件 之 一 , Cadence 提 供 了 对 Verilog 及 VHDL 的 强 大 支 持 。 尤 其 是 Verilog,Cadence 很 早 就 引 入 了 Verilog, 并 为 其 开 发 了 一 整 套 工 具 。而 其 中 最 出 色 的 当 数 Verilog 的 仿 真 工 具 Verilog-XL 。Verilog-XL 一 直 以 其 友 好 的 用 户 界 面 及 强 大 的 功 能 而 受 到 广 大 Verilog 用 户 的 青 睐 。本 章 将 分 五 个 方 面一一对对其进行一个较为详尽的介绍。 3. 1 环境设置 对 于 一 般 的 Cadence 的 用 户 而 言 , 可 能 不 需 要 进 行 任 何 设 置 就 可 启 动 Verilog-XL。 用 户 可 输 入 下 列 命 令 看 自 己 是 否 可 访 问 Verilog-XL: which verilog 如 果 可 以 访 问 Verilog-XL,会 有 类 似 如 下 的 反 应 : /EDA04/cds97a/ tools/bin/verilog 否则, 必须在.cshrc 中用 set path 命令加 入以上路 径。 3.2 Verilog-XL 的 启 动 Verilog-XL 的 启 动 命 令 为 verilog, 它 可 以 附 带 很 多 可 选 项 , 下 面 是 其 各 选 项及其意义: Valid host command options for verilog: -f read host command arguments from file -v specify library file -y specify library directory -c compile only -s enter interactive mode immediately -i input from command file Cadence 使用手册 介绍 -r restart from a saved data structure -l set log file name -k set key file name -u convert identifiers to upper case -t set full trace -q quiet -d decompile data structure 第三章 Verilog-XL 的 Special behavioral performance options (if licensed): +turbo speed up behavioral simulation. +turbo+2 +turbo with second level optimizations. +turbo+3 +turbo+2 with third level optimizations. +listcounts generate code for maintaining information for $listcounts +no_turbo don't use a VXL-TURBO license. +noxl disable XL acceleration of gates in all modules Special environment invocation options (if licensed): +gui invoke the verilog graphical environment 下 面 是 几 个 简 单 的 使 用 示 例 , 在 UNIX 提 示 符 下 输 入 这 些 命 令 即 可 启 动 Ver i l o g - X L : Example host commands to run VERILOG: verilog sio85.v verilog f1 f2 f3 verilog -s sio85.v verilog -r save.dat -l run2.log -k run2.key verilog -r save.dat -si commands.vic verilog -dqcr save.dat 一般较常用的启动方法是: verilog –s +gui –v libname –f scriptFile sourcefilename & 其 中 ,libname 为 所 使 用 的 库 的 名 字 ,scriptFile 为 用 可 选 项 编 写 Cadence 使用手册 介绍 的命令文件。 3.3 Verilog-XL 的 界 面 第三章 Verilog-XL 的 运行以上的启动命令后,如果未发生什么错误,就会弹出下图所示的用户 界 面 , 这 就 是 Verilog-XL 的 SimControl 窗 口 ,从 该 图 形 界 面 中 , 可 控 制 仿 真 的 执行。 图 3- 1 Verilog-XL 的 图 形 界 面 Verilog-XL 的 图 形 界 面 主 要 有 以 下 几 个 窗 口 : 1. SimControl SimControl 窗 口 是 主 要 的 仿 真 控 制 窗 口 , 当 用 带 有 + gui 选 项 的 verilog 命 令 启 动 Verilog-XL 时 , 就 会 弹 出 这 个 窗 口 。 通 过 这 个 窗 口 , 用 户 可 以 显 示 设 计 的 模 块 结 构 , 运 行 Verilog-XL 命 令 , 设 置 及 显 示 断 点 , 强 行 给 变 量 赋 值等等。通过这个窗口可以实现用户与仿真的交互,从而达到对仿真的控 制。 2. Navigator 通 过 点 击 SimControl 窗 口 右 上 角 的 星 形 图 标 即 可 激 活 Navigator 窗 口 。该 窗 口可用来图形化显示设计的层次,设计中的实体及其变量。 3. Signal Flow Browser Cadence 使用手册 介绍 第三章 Verilog-XL 的 4. Watch Objects Window 5. SimWave SimWave 窗 口 可 以 用 来 显 示 已 经 选 择 并 跟 踪 了 的 信 号 的 波 形 。 3.4 Verilog-XL 的 使 用 示例 介 绍 了 Verilog-XL 的 启 动 和 用 户 界 面 后 , 下 面 我 们 将 通 过 一 个 具 体 的 实 例 来 演 示 Verilog-XL 的 使 用 。 在 附 录 2 中 有 本 示 例 所 需 的 文 件 , 在 本 示 例 中 ,将 对 一 个 SRAM 模 块 SRAM256X8.v 进 行 仿 真 。在 这 个 SRAM 模 块 中 又 包 含 了 一 个 子 模 块 ram_sy1s_8052.v。 所 调 用 的 为 TSMC 的 0.35um 的 库 。 test_bench 为 test_memory.v, 在 该 test_bench 中 首 先 对 SRAM 进 行 写 , 然 后 进 行 读 。 下 面 按 照一个简单的流程来对这个 SRAM 进行模拟: 1. 在 UNIX 提示符下输入: verilog -c -v tcb773s.v test_memory.v & 来对源文件进行调试,如果没有错误,会显示 0 Simulation events。 2. 没 有 错 误 之 后 , 就 可 以 启 动 Verilog-XL 的 图 形 界 面 : verilog –s +gui –v tcb773s.v test_memory.v & 则会弹出如图 3-2 所示的窗口。 3. 跟踪自己所需要的波形信号。 4. 按 运 行 按 钮 或 在 命 令 行 输 入 原 点 并 回 车 ,即 可 运 行 ,按 停 止 按 钮 即 可 停 止。停止后波形会自动更新。 Cadence 使用手册 介绍 第三章 Verilog-XL 的 图 3-2 3.5 Verilog-XL 的 有 关 帮助 文 件 与 Verilog-XL 有 关 的 帮 助 文 件 主 要 有 以 下 一 些 : Verilog-XL Reference Verilog-XL User Guide Verilog-XL Tutorial SimCompare User Guide SimWave User Guide VPI User Guide and Reference (formerly PLI 2.0) PLI 1.0 User Guide and Reference PLI Application Note: Back Annotation and Delay Calculation PLI Application Note: Using the Value Change Link LMC Hardware Modeling Interface Reference and User Guide Graphical Output for the Verilog Product Family Reference SDF Annotator User Guide Central Delay Calculator Algorithm Guide Cadence 使用手册 介绍 第三章 Verilog-XL 的 Timing Library Format Reference Verilog Language Sensitive Editor User Guide 可 通 过 如 下 顺 序 对 这 些 文 档 进 行 访 问 : Main menu->HDL Tools- >Verilog-XL。 Cadence 使用手册 拟 第四章 电路图设计及电路模 第四章 电路图设计及电路模拟 设 计 的 输 入 除 了 可 以 用 硬 件 描 述 语 言 ( 如 VHDL 及 Verilog ) 外 , 还 可 以 用电路 图输入。在 早期的 ASIC 设计中 ,电路图起 着更为重要 的作用,作 为流 行 的 EDA 软 件 ,Cadence 提 供 了 一 个 优 秀 的 电 路 图 编 辑 工 具 Composer。Composer 不但界面友好,操作方便,而且功能非常强大。 电路 图设计好 后,其功 能是否正 确,性能 是否优越,必须 通过电路 模拟才 能 进 行 验 证 。 Cadence 同 样 提 供 了 一 个 优 秀 的 电 路 模 拟 软 件 , Analog Artist。由 于 Analog Artist 通 过 Cadence 与 Hspice 的 接 口 调 用 Hspice 对 电 路 进 行 模 拟 。 本 章 将 介 绍 电 路 图 设 计 工 具 Composer 和 电 路 模 拟 软 件 Analog Artist 的 设 置 、 启动、界面及使用方法、简单的示例以及相关的辅助文件。以便读者能对这两 种工具有一个初步的理解。 4.1 电路图设计工具 Composer Composer 是一种设计输入的工具,逻辑或者电路设计工程师,物理设计工 程师甚至 PCB 板设计工程师可以用它来支持自己的工作。 4.1.1 设置 对 于 一 般 的 Cadence 的 用 户 而 言 , 可 能 不 需 要 进 行 任 何 设 置 就 可 启 动 Composer。但有 时必须 设置快 捷键,否则 所有的 快捷键 就会失 灵,给使 用带来 一些不便。在设计时,快捷键往往会有很大的作用。 此 外 ,在 电 路 设 计 中 可 能 需 要 用 到 一 些 符 号 库 ,例 如 sample 库 ,basic 库 , analogLib 库,只需在 cds.lib 文件中加入以下一段代码: DEFINE basic ${CDS_INST_DIR}/tools/dfII/etc/cdslib/basic DEFINE sample ${CDS_INST_DIR}/tools/dfII/samples/cdslib/sample DEFINE analogLib /EDA04/cds97a/tools/dfII/etc/cdslib/artist/analogLib Cadence 使用手册 拟 4.1.2 启动 第四章 电路图设计及电路模 Composer 的 启 动 很 简 单 ,在 启 动 Cadence 后 ,从 CIW 窗 口 中 打 开 或 新 建 一 个 单 元 的 Schematic 视 图 ,就 会 自 动 启 动 Composer 的 用 户 界 面 。用 户 即 可 在 其 中放入单元及连线,以构成电路图。 4.1.3 用户界面及使用方法 图 4- 1 是 Composer 的 图 形 界 面 ,在 该 用 户 界 面 中 ,大 部 分 面 积 是 右 下 角 的 显 示 区 。左 边 的 图 标 是 一 些 常 用 的 工 具 ,读 者 可 以 自 己 启 动 Composer,然 后 熟 悉 一 下 Composer 的 用 户 界 面 。 下 面 将 简 单 介 绍 一 下 电 路 图 设 计 及 符 号 ( Symbol) 设 计 的 简 单 流 程 。 图 4-1 Composer 的用户界面 图 4-2 是编辑电路图的一般流程为: 1. 首先用 Component 命令调 用符号库 中的元件来 添加元件, 如图的 nand3。 2. 添 加 完 所 有 的 元 件 后 就 可 以 加 入 pin,可 通 过 add 菜 单 中 的 pin 项 来 进 行 添 加。 3. 布线及标线名,可通过 wire 命令布线,通过更改其属性标上线名。 Cadence 使用手册 拟 4. 添加节点 5. 加注释 6. 加整体属性,如一些自动布局布线属性。 第四章 电路图设计及电路模 图 4-2 电路图设计的简单流程 符号是用来代表元件的简单符号,如反相器用一个三角形代替。在 Cadence 中 , 当 上 层 调 用 下 层 单 元 和 进 行 上 下 级 映 射 时 通 常 调 用 其 符 号 。所 以,符号在电路设计中起着很重要的作用。与启动 Schematic Editor 类似, 通 过 在 CIW 窗 口 中 新 建 或 打 开 一 个 单元 的 symbol 视 图 , 就 可 启 动 Symbol Editor。图 4-3 是编辑符号的一般流程,主要包括以下几步: 1. 在编辑区加入一些基本的图形。 2. 加入符号的 pin。 3. 加入连接基本图形与 pin 的线。 4. 加入符号的标记,如 inv。 5. 加入选择外框。 6. 加入文本注释 7. 更改整体属性 Cadence 使用手册 拟 第四章 电路图设计及电路模 4.1.4 使用示例 图 4-3 符号设计的简单流程 在 openbook 中有一 个关于 Composer 的教程 ,如果读者需 要经常用到电 路 图,本人建议你不妨去走一遍那个教程,对你一定会有帮助的。该教程可安如 下 顺 序 进 行 访 问 。 Main Menu-> IC Tools->Tutorials-> Composer。 4.1.5 相关在线帮助文档 Composer: Design Entry help 4.2 电路模拟工具 Analog Artist Cadence 提 供 进 行 电 路 模 拟 的 工 具 Analog Artist。 Anglog Artist 通 过 调 用 Hspice 进行电 路模拟, 然后进行各 种后续处理 并显示结 果。 4.2.1 设置 在运行 Analog Artist 之前, 必须在.cshrc 中设置 以下语句 : setenv CDS_Netlisting_Mode Analog 此 外, 最好 能 从 Cadence 的 安装 目录 的 Analog Artist 中 拷贝 与模 拟 器相 应的 初始化文件。 Cadence 使用手册 拟 4.2.2 启动 第四章 电路图设计及电路模 Analog Artist 的 启 动 方 法 有 很 多 种 ,可 以 从 Composer 的 Tools 菜 单 中 执 行 , 也 可 以 从 CIW 的 Tools 菜 单 中 执 行 。 4.2.3 用户界面及使用方法 图 4- 4 是 Analog Artist 的 用 户 界 面 ,关 于 具 体 的 使 用 方 法 请 参 考 openbook 中 的 相 应 手 册 。 但 有 一 点 想 提 醒 大 家 , 大 家 使 用 的 licence 可 能 不 允 许 使 用 Analog Artist。 如 果 在 微 所 使 用 Analog Artist 且 用 Hspice 为 模 拟 器 , 似 乎 激 励 文件用 cdsspice 格式才可调通,有兴趣的读者可以一试。 4.2.5 相关在线帮助文档 与 Analog artist 相关的在线文档有: Cadence 使用手册 拟 第四章 电路图设计及电路模 Analog Artist Simulation Help Analog Artist Microwave Design Help Analog Artist Mixed-Signal Simulation Help Analog Artist Parametric Analysis Help Analog Artist Substrate Coupling Analysis (SCA) Help Analog Artist SKILL Functions Reference Analog Expression Language Reference Cadence SPICE Reference Component Description Format User Guide Functional Block Library Reference HSPICE/SPICE Interface and SPICE 2G.6 Reference Spectre Reference Spectre User Guide SpectreHDL Reference SpectreRF Help Switched Capacitor Design System Help Analog Artist Tutorial: Switched Capacitor Design Verilog-A Reference 通过顺序 Main Menu-> IC Tools->Analog and Mixed Signal Simulation 可以访问 Cadence 使用手册 布线 第五章 自动布局 第五章 自动布局布线 5.1 Cadence 中的自动布局布线流程 从 第 一章 的 ASIC 设 计 流程 中 可 看 到, 设 计 输 入经 过 综 合 和优 化 后 , 就该 对所生成的门级网表进行自动布局布线。自动布局布线是连接逻辑设计和物理 设计之间的纽带。 在自动布局布线前必须进行布局规划(floorplan),在 Cadence 中进行布 局规划的工具为 Preview,进行自动布局布线的引擎有四种:Block Ensemble、 Cell Ensemble、Gate Ensemble 和 Silicon Ensemble。其中,Block Ensemble 适用于 宏单元的 自动布局 布线,Cell Ensemble 适用于 标准单元 或标准单 元与 宏单元相混合的布局布线,Gate Ensemble 适合于门阵列的布局布线,Silicon Ensemble 主 要 用 在 标 准 单 元 的 布 局 布 线 中 。将 Preview 与 四 种 引 擎 相 结 合 可 产 生四 种不同 的自 动布局 布线环 境和流 程。 由于 Silicon Ensemble(DSM)的功 能 很完全,几乎可以完成所有复杂的自动布局布线的任务,在考虑自动布局布线 引 擎 时 ,我 们 采 用 了 Silicon Ensemble。SRAM 编 译 器 所 生 成 的 用 于 自 动 布 局 布 线的端口模型为 Silicon Ensemble 所要求的格式。 图 5-1 为采用 Preview 和 Silicon Ensemble 进行自动布局布线的流程图。 该流程主要由以下几个主要步骤组成: (1) 准备自动布局布线库 在 进 行 自 动 布 局 布 线 之 前 ,必 须 准 备 好 相 应 的 库 。该 库 中 含 有 工 艺 数 据 、 自 动 布 局 布 线 用 的 库 单 元 及 显 示 信 息 。 库 的 格 式 必 须 为 Design Framework II 的 数 据 库 格 式 , 可 以 由 用 户 利 用 版 图 生 成 工 具 Virtuoso Layout Editor 设计产生,也可以来自一个由芯片制造厂家和 EDA 公司 提供的 LEF(Library Exchange Format)文件,或者从 GDSII 生成。 (2) 准备用来进行自动布局布线的网表 用来进行布局布线的网表可以由硬件描述语言经过综合优化或由电 路提取而来。所有网表在进行自动布局布线前都必须首先生成对应的 autoLayout 视 图 ( view)。 (3) 用 Preview 进行布局规划 Cadence 使用手册 布线 第五章 自动布局 Preview 是 Cadence 的 布 局 规 划 器 。 它 可 以 用 来 规 划 物 理 设 计 ,从 而 在 自 动 布 局 布 线 前 预 估 物 理 实 现 的 影 响 。在 Cadence 中 ,使 用 Preview 与自动布局布线引擎相结合来进行自动布局布线。 (4) 用 Silicon Ensemble 进行自动布局布线 (5) 对完成布局布线的版图进行验证 生 成 的 版 图 其 连 接 性 是 否 正 确 ,是 否 符 合 设 计 规 则 ,是 否 符 合 时 序 要求等等,必须通过验证才能确定。通过点击 Verify&Report 菜单中的 相 应 项 ,可 对 版 图 进 行 连 接 性 、设 计 规 则 验 证 ,并 可 生 成 SDF( Standard Delay Format)文 件 。通 过 反 标 SDF 文 件 可 对 原 来 的 门 级 网 表 进 行 仿 真 , 从而确定其功能和时序是否正确。 图 5-1 用 Preview 和 Silicon Ensemble 进行自动布局布线的流程 5.2 用 AutoAbgen 进行自动布局布线库设计 对 于 不 同 的 自 动 布 局 布 线 引 擎 ,对 应 的 库 的 数 据 格 式 有 所 不 同 ,用 来 生 成 库的工具也不同。本 SRAM 编译器选择 Silicon Ensemble 作为布局布线引擎, 其 对 应 的 库 生 成 工 具 为 AutoAbgen。AutoAbgen 可 以 用 来 生 成 与 用 户 设 计 的 版 图 或版图库所对应的 Abstract(即用于自动布局布线的端口模型)。 可 以 用 AutoAbgen 的 AutoAbgen Flow Sequencer form 来 生 成 Abstract(对 于 单 个 版 图 ) 和 LEF 文 件 ( 对 于 整 个 物 理 库 ), 其 基 本 流 程 如 下 : Cadence 使用手册 布线 第五章 自动布局 (1) 首 先 在 局 部 .cdsinit 中 设 置 好 AutoAbgen 运 行 的 环 境 , 即 在 .cdsinit 中 加 入 以下语句: aabsInstallPath=“/tools/autoAbgen/etc/autoAbgen” load(buildstring(list(aabsInstallPath “aaicca.ile”) “/”))。 (2) 将 AutoAbgen 的 初 始 化 文 件 .autoAbgen 拷 入 运 行 目 录 。 并 用 icfb&启 动 Cadence。 (3) 点 击 CIW 窗 口 中 的 AutoAbgen 菜 单 下 的 AutoAbgen Flow Sequencer 项 , 打 开 Flow Sequencer Form。 (4) 选择合 适的流程 。 (5) 建 立 布 局布 线 所 需 的 工 艺信 息 。 如 果 在工 艺 文 件 中 已 经包 含 布 局 布 线 的工 艺信息,可以忽略这一步。 (6) 建立 用来生成 Abstract 的版 图数据。如果 所用的版 图数据 已经是 DFII 的 版图格式,可以忽略这一步。 (7) 更 新 单 元 的 属 性 及 其 管 脚 属 性 。 由 于 AutoAbgen 对 所 操 作 的 版 图 有 些 特 殊 要求,所以在生成 Abstract 前必须对其属性进行更新,以符合 AutoAbgen 的要求。 (8) 建立一 个库单元 ,将所需建 立 Abstract 的所有 单元包括 到里面。 (9) 填 写 环 境 设 置 表格 和 运 行 选 项 表 格 。 输 入 输 出 LEF 的 文 件 名 ( 如 果是 对 库 进 行 操 作 )。 (10) 选择 Apply 运行 AutoAbgen,生成所需的 Abstract。 Cadence 使用手册 证 第六章 版图设计及其验 第六章 版图设计及其验证 如 果 有 人 问 ,“ Cadence 最 突 出 的 优 点 在 那 里 ? ”我 想 问 题 的 答 案 应 当 就 在 本 章 。可 以 说 ,Cadence 的 版 图 设 计 及 验 证 工 具 是 任 何 其 他 EDA 软 件 所 无 法 比 拟 的 。Cadence 的 版 图 设 计 工 具 是 Vituoso Layout Editor,即 为 版 图 编 辑 大 师 ,以 下 简称版图大师。版图大师不但界面很漂亮,而且操作方便,功能强大。可以完 成版图编辑的所有任务。 版 图设 计得 好坏 ,其 功能 是 否正 确, 必须 通过 验证 才 能确 定。 Cadence 中 进行 版图 验证的 工具 主要有 Dracula 和 Diva。两者 的主 要区别 是,Diva 是在 线 的 验 证 工 具 , 被 集 成 在 Design Frame Work II 中 , 可 直 接 点 击 版 图 大 师 上 的 菜 单 来 启 动 。而 Dracula 是 一 个 单 独 的 验 证 工 具 ,可 以 独 立 运 行 。相 比 之 下 ,Dracula 的功能比较强大。 6.1 版图设计大师 Virtuoso Layout Editor 版 图 设 计 大 师 是 Cadence 提 供 给 用 户 进 行 版 图 设 计 的 工 具 。其 使 用 起 来 十 分方便,下面进行一个简单介绍: 6.1.1 设置 版图 大师的 设置很 简单, 对于一般 的 Cadence 的用 户而言 ,可能 不需要 进 行任何设置就可启动版图大师。但有时必须设置快捷键,否则所有的快捷键就 会失灵,给使用带来一些不便。在设计时,快捷键往往会有很大的作用。 与电路设计不同的是,版图设计必须考虑具体的工艺实现,因此,存放版 图 的 库 必 须 是 工 艺 库 或 附 在 别 的 工 艺 库 上 的 库 。否 则 ,用 隐 含 的 库 将 没 有 版 层 , 即 LSW 窗 口 只 有一 个 黑 框 , 更无 从 画 图 了 。 因此 , 在 设 计 版图 前 必 须 先 建 立 自己的工艺库。 此外,显示对于版图设计也很重要,因此最后有自己的显示文件 d i s p l a y. d r f 。 6.1.2 启动 有 很 多 种 方 法 自 动 版 图 大 师 ,最 简 单 的 办 法 是 通 过 CIW 打 开 或 者 新 建 一 个 Cadence 使用手册 证 第六章 版图设计及其验 单元 的版图 视图, 这样就 会自动 启动版 图大师 。此外 ,也可 以用 layoutPlus 或 layout 命令启 动。 6.1.3 用户界面及使用方法 图 6- 1 Virtuoso Layout Editor 用 户 界 面 通 过 上 述 方 法 启 动 版 图 大 师 后 ,就 会 出 现 如 图 6- 1 所 示 的 用 户 界 面 及 一 个 LSW 窗口。从 LSW 窗口中选择所需的层,然后在显示区画图。具体的操作请 读者参考 openbook 中的部分。 6.1.4 使用示例 关 于 Virtuoso Layout Editor 的 具 体 使 用 ,在 此 就 不 再 赘 述 ,在 openbook 中 有 一 个 很 好 的 例 子 cell_design。建 议 所 有 学 习 Cadence 的 人 都 该 走 一 遍 该 教 程 。 该 教 程 的 访 问 顺 序 为 : Main Menu->IC Tools->Tutorials and Flow Guides-> Cell Design Tutorial。 Cadence 使用手册 证 6.1.5 相关在线帮助文档 与版图大师有关的在线文档有: Virtuoso Layout Editor help Cell Design Tutorial 6.2 版图验证工具 Dracula 第六章 版图设计及其验 6.2.1 Dracula 使用介绍 用 Virtuoso Layout Editor 编辑生成的版图是否符合设计规则、电学规 则,其 功能是否正确 必须通过版图 验证系统来 验证。Cadence 提供的 版图验证 系统有 Dracula 和 Diva。Diva 嵌入在 Cadence 的主体框架之中,使用较方便, 但 功 能 较 之 Dracula 稍 有 逊 色 。Dracula 为 独 立 的 版 图 验 证 系 统 ,可 以 进 行 DRC ( 设 计 规 则 检 查 )、 ERC( 电 学 规 则 检 查 )、 LVS( 版 图 和 电 路 比 较 )、 LPE( 版 图 寄 生 参 数 提 取 )、PRE( 寄 生 电 阻 提 取 ),其 运 算 速 度 快 ,功 能 强 大 ,能 验 证 和 提 取较大的电路,本手册着重介绍 Dracula 的使用。 使用 Dracula 和 Diva 的第一步是编写与自己的工艺一致的命令文件,包 括 DRC、ERC、LVS、LPE 甚 至 PRE 文 件 。关 于 命 令 文 件 的 编 写 ,读 者 可 参 考 openbook 中的手册,可安以下顺序找到。附录 3 中有一套 0.5um 的命令文件,读者可参 考。 假设要验证的版图为 mySRAM 库中的 sram256x8 单元,用来进行验证的当 前 目 录 为 myver,运 行 Dracula 的 命 令 文 件 为 mydrc.com。执 行 DRC、ERC 和 LPE 的流程如下: (1) 利 用 Virtuoso Layout Editor 生 成 所 需 的 版 图 sram256x8, 然 后 利 用 CIW 窗 口 中 的 Export->Stream 菜 单 , 将 单 元 sram256x8 的 版 图 转 变 成 GDSII 格式文件 sram256x8.gds,并存到运行目录 myver 下。 ( 2) 修 改 运 行 Dracula 所 需 的 命 令 文 件 mydrc.com,将 其 中 的 INDISK 文 件 改 为 sram256x8.gds,OUTDISK 改 为 任 何 自 己 喜 欢 的 文 件 , 例 如 sram256x8_out.gds , 将 WORK-DIR 改 为 当 前 的 运 行 目 录 myver , 将 PRIMARY 改为大写的单元名,即 SRAM256X8。 ( 3) 在 当 前 目 录 下 运 行 PDRACULA,即 在 UNIX 操 作 符 下 输 入 PDRACULA&,然 后 输 入 /GET mydrc.com 并 回 车 , 接 着 输 入 /fi 即 可 生 成 jxrun.com 及 Cadence 使用手册 证 第六章 版图设计及其验 jxsub.com。 (4) 在当前目录下运行 jxrun.com 或 jxsub.com。 (5) 检 查 结 果 文 件 , DRC 检 查 为 printfile_name.drc , ERC 为 printfile_name.erc , LVS 为 printfile_name.lvs 。 其 中 , printfile_name 为命令文件中 PRINTFILE 所指定的字符串。 (6) 利用 InQuery&命令启动图形界面查找并修改错误。 ( 7) 重 复 ( 1) 至 ( 6), 直 至 改 完 所 有 的 错 误 。 由 于 Dracula 的 功能 强 大 ,速 度 较快 , 可 以对 整 个 SRAM 版 图进 行 验 证, 所 以 可以确保生成的 SRAM 版图完全符合设计规则、电学规则。 6.2.2 相关在线帮助文档 与版图 验证有关 的在线文档 主要有以下 几个。InQuery 是用来 显示验证 结果的。 Diva Interactive Verification Reference Dracula Standalone Verification Reference Dracula User Guide InQuery Reference InQuery Tutorial 第七章 skill 语言程序设计 7.1 skill 语言概述 Skill 语 言 是 Cadence 公 司 自 己 开 发 的 一 种 类 似 于 leap 语 言 的 编 程 语 言 。Cadence 公司不仅开发了全套的 Skill 语言语法,还开发了一个完整的 Skill 语言的编译器。 整个 Cadence 软件都是基于 Skill 语言的,所有的 Cadence 的工具都是用 Skill 语言 编写的,甚至各种设置辅助文件都是遵从 Skill 语言的语法。此外,Cadence 公司为 其 每 个 产 品 都 提 供 Skill 语 言 访 问 函 数 ,这 使 得 用 户 可 以 通过 Skill 语 言 访 问 Cadence 的产品。由于 Skill 由于提供编程接口及与 C 语言的接口,这使得 Cadence 可以在 原有的基础上进行各种扩展,甚至允许用户开发自己的基于 Cadence 平台的工具。 因 此 ,学 习 一 些 基 本 的 Skill 语 言 的 知 识 及 基 本 的 编 程 技 巧 对 于 学 习 Cadence 是 大 有 益处的。本章将对 Skill 语言作一些简单的介绍。 7.2 skill 语言的基本语法 关 于 Skill 语 言 的 基 本 语 法 ,读 者 可 参 考 openbook 中 的 Skill Language User Guide 以 及 Skill Language Functions Reference 两 本 手 册 。 可 按 顺 序 Main Menu->Skill Language 找到。 7.3 Skill 语言的编程环境 最简单的 Skill 编程方法是利用 CIW 窗口中的命令解释行,可以将其看为 Skill 语言的行编译器。例如在其中输入 printf(“HI”); 再回车,在 CIW 的显示区就会出现 HI 字符串。除了输入单行的 Skill 命令外, 也 可 先 用 任 一 文 本 编 辑 器 将 一 系 列 命 令 组 成 一 个 skill 文 件 ,例 如 myskill.il,然 后 利 用 load 命 令 将 文 件 导 入 Skill 编 译 器 , 具 体 方 法 为 在 CIW 命 令 解 释 行 中 输 入 load( “myskill.il ”)。如 果 文 件 不 在 当 前 目 录 ,还 需 在 文 件 名 前 加 上 路 径 。如 果 为 了 保 密,可以将 Skill 文件存成 context 的形式。 实 际 上 , Cadence 提 供 了 一 套 完 整 的 编 程 工 具 , 在 CIW 的 Tools 菜 单 下 的 Skill Development 可启动该编程环境。如果读者有兴趣,可自己去摸索,在此就不在赘 述了。 7.4 面向工具的 skill 语言编程 Cadence 公 司 在 开 发 自 己 的 产 品 时 ,一 般 都 提 供 其 相 应 的 Skill 语 言 函 数,产 品 种 的 点 击 菜 单 等 动 作 都 可 用 执 行 其 相 应 的 skill 语 言 函 数 来 代 替 。这 就 该 编 程 者 提 供 了宝贵的接口。由于 Skill 由于是 script 语言,因此,熟练的用户可以通过适当的编 程 实 现 任 务 的 自 动 化 。下 面 以 面 向 用 户 界 面 的 编 程 为 例 简 单 介 绍 一 下 Skill 语 言 的 编 程。 下 面 这 段 代 码 是 本 人 编 写 的 一 个 用 户 界 面,其 中 最 主 要 用 到 的 是 Cadence 提 供 的关于用户界面设计的函数,读者可以从中研究一下。图 7-1 至 7-6 是其对应的 图形界面。 Skill 程序代码 ;SRAM Compiler main function ;Define some global variable and the default value MaxWords = 4096 MaxBits = 64 MinWords = 192 MinBits = 1 ModuleName = "SRAM256x8" SRAMWords = 256 SRAMBits = 8 SRAMPorts = 1 RowCellNum = 8 ColCellNum = 8 RowAddNum = 4 ColAddNum = 2 ColMul = 4; The multiplier of the bits PlugNum = 8 LibraryName = "mySRAM" TecLibraryName = "ourTechLib" Workpath = "." procedure( mainOpen() println("I love you!") ) procedure( mainLoadState() println("I love you!") ) procedure( mainSaveState() println("I love you!") ) procedure( mainReset() println("I love you!") ) procedure( mainReport() view("./sram_compiler/sram.rep") ) procedure( mainAbout() view("./sram_compiler/sram.ver") ) procedure( mainExit() hiCloseWindow(w) println("Thank you for your use of our SRAM Compiler, Bye:)") ) procedure( mainWordBits() ;;; creating the words field WordsField = hiCreateIntField( ?name 'WordsField ?prompt "SRAM Words(64-4096)" ?value SRAMWords ?defValue 256 ?callback "SetWordsCB( hiGetCurrentForm() ) " ?range '(64 4096) ) BitsField = hiCreateIntField( ?name 'BitsField ?prompt "SRAM Bits(1-64)" ?value SRAMBits ?defValue 16 ?callback "SetBitsCB( hiGetCurrentForm() ) " ?range '(1 64) ) ;;; creating the form SetWordsForm = hiCreateAppForm( ?name 'SetWordsForm ?formTitle "Set Words&Bits Form" ?callback "SetWordBitsFormCB( hiGetCurrentForm() ) " ?fields list( WordsField BitsField ) ?unmapAfterCB t ) procedure( SetWordsCB( theForm ) SRAMWords = theForm->WordsField->value ) ; procedure procedure( SetBitsCB( theForm ) SRAMBits = theForm->BitsField->value ) ; procedure procedure( SetWordBitsFormCB( theForm ) if( SetWordsCB( theForm ) then hiSetCallbackStatus( theForm t ) hiHighlightField( theForm 'WordsField 'background ) ; view( theForm->WordsField->value ) ; SRAMWords = theForm->WordsField->value else if( SetBitsCB( theForm ) then hiSetCallbackStatus( theForm t ) hiHighlightField( theForm 'BitsField 'background ) else hiSetCallbackStatus( theForm nil ) hiHighlightField( theForm 'WordsField 'highlight ) ) ) ; if ) ; procedure ;;; displaying the form hiDisplayForm( SetWordsForm ) ) procedure( mainModuleName() ;;; creating the File Name field ModuleNameField = hiCreateStringField( ?name 'ModuleNameField ?prompt "Module Name" ?value ModuleName ?defValue "SRAM256x8" ?callback "ModuleFieldCheckCB( hiGetCurrentForm() )" ?editable t ) procedure( ModuleFieldCheckCB( theForm ) ; if( isFile( theForm->trFileNameField->value ) ; then ModuleName = theForm->ModuleNameField->value t ; else ; println("File Does Not Exist--Try Again") ; nil ; ) ;if ) ; procedure ;;; creating the form ModuleNameForm = hiCreateAppForm( ?name 'ModuleNameForm ?formTitle "Module Name Form" ?callback 'ModuleNameFormCB ?fields list( ModuleNameField ) ?unmapAfterCB t ) procedure( ModuleNameFormCB( theForm ) if( ModuleFieldCheckCB( theForm ) then hiSetCallbackStatus( theForm t ) hiHighlightField( theForm 'ModuleNameField 'background ) ; view( theForm->ModuleNameField->value ) else hiSetCallbackStatus( theForm nil ) hiHighlightField( theForm 'ModuleNameField 'highlight ) ) ; if ) ; procedure ;;; displaying the form hiDisplayForm( ModuleNameForm ) ) procedure( mainLibrary() ;;; creating the File Name field LibraryNameField = hiCreateStringField( ?name 'LibraryNameField ?prompt "Working Library Name" ?value LibraryName ?defValue "mySRAM" ?callback "LibraryFieldCheckCB( hiGetCurrentForm() )" ?editable t ) procedure( LibraryFieldCheckCB( theForm ) ; if( isFile( theForm->trFileNameField->value ) ; then LibraryName = theForm->LibraryNameField->value t ; else ; println("File Does Not Exist--Try Again") ; nil ; ) ;if ) ; procedure ;;; creating the form LibraryNameForm = hiCreateAppForm( ?name 'LibraryNameForm ?formTitle "Working Library Name Form" ?callback 'LibraryNameFormCB ?fields list( LibraryNameField ) ?unmapAfterCB t ) procedure( LibraryNameFormCB( theForm ) if( LibraryFieldCheckCB( theForm ) then hiSetCallbackStatus( theForm t ) hiHighlightField( theForm 'LibraryNameField 'background ) ; view( theForm->ModuleNameField->value ) else hiSetCallbackStatus( theForm nil ) hiHighlightField( theForm 'LibraryNameField 'highlight ) ) ; if ) ; procedure ;;; displaying the form hiDisplayForm( LibraryNameForm ) mySRAM = dbCreateLib( LibraryName Workpath) ) procedure( mainTecLibrary() ;;; creating the File Name field TecLibraryNameField = hiCreateStringField( ?name 'TecLibraryNameField ?prompt "Technology Library Name" ?value TecLibraryName ?defValue "outTechLib" ?callback "TecLibraryFieldCheckCB( hiGetCurrentForm() )" ?editable t ) procedure( TecLibraryFieldCheckCB( theForm ) ; if( isFile( theForm->trFileNameField->value ) ; then TecLibraryName = theForm->TecLibraryNameField->value t ; else ; println("File Does Not Exist--Try Again") ; nil ; ) ;if ) ; procedure Form" ;;; creating the form TecLibraryNameForm = hiCreateAppForm( ?name 'TecLibraryNameForm ?formTitle "Technology Library Name ?callback 'TecLibraryNameFormCB ?fields list( TecLibraryNameField ) ?unmapAfterCB t ) procedure( TecLibraryNameFormCB( theForm ) if( TecLibraryFieldCheckCB( theForm ) then hiSetCallbackStatus( theForm t ) hiHighlightField( theForm 'TecLibraryNameField 'background ) ; view( theForm->ModuleNameField->value ) else hiSetCallbackStatus( theForm nil ) hiHighlightField( theForm 'TecLibraryNameField 'highlight ) ) ; if ) ; procedure ;;; displaying the form hiDisplayForm( TecLibraryNameForm ) ) procedure( mainWorkpath() ;;; creating the File Name field WorkpathField = hiCreateStringField( ?name 'WorkpathField ?prompt "Working Path" ?value Workpath ?defValue "." ?callback "WorkpathFieldCheckCB( hiGetCurrentForm() )" ?editable t ) procedure( WorkpathFieldCheckCB( theForm ) ; if( isFile( theForm->trFileNameField->value ) ; then Workpath = theForm->WorkpathField->value t ; else ; println("File Does Not Exist--Try Again") ; nil ; ) ;if ) ; procedure ;;; creating the form WorkpathForm = hiCreateAppForm( ?name 'WorkpathForm ?formTitle "Working Path Form" ?callback 'WorkpathFormCB ?fields list( WorkpathField ) ?unmapAfterCB t ) procedure( WorkpathFormCB( theForm ) if( WorkpathFieldCheckCB( theForm ) then hiSetCallbackStatus( theForm t ) hiHighlightField( theForm 'WorkpathField 'background ) ; view( theForm->ModuleNameField->value ) else hiSetCallbackStatus( theForm nil ) hiHighlightField( theForm 'WorkpathField 'highlight ) ) ; if ) ; procedure ;;; displaying the form hiDisplayForm( WorkpathForm ) mySRAM = dbCreateLib( LibraryName Workpath) ) procedure( mainPorts() PortsField = hiCreateIntField( ?name 'PortsField ?prompt "SRAM Ports(1,2,4)" ?value SRAMPorts ?defValue 1 ?callback "SetPortsCB( hiGetCurrentForm() ) " ?range '(1 4) ) ;;; creating the form SetPortsForm = hiCreateAppForm( ?name 'SetPortsForm ?formTitle "Set Ports Form" ?callback "SetPortsFormCB( hiGetCurrentForm() ) " ?fields list(PortsField) ?unmapAfterCB t ) procedure( SetPortsCB( theForm ) SRAMPorts = theForm->PortsField->value ) ; procedure procedure( SetPortsFormCB( theForm ) if( SetPortsCB( theForm ) then hiSetCallbackStatus( theForm t ) hiHighlightField( theForm 'PortsField 'background ) ; view( theForm->WordsField->value ) ; SRAMWords = theForm->WordsField->value ) ; if ) ; procedure ;;; displaying the form hiDisplayForm( SetPortsForm ) ) procedure( mainOther() ;;; creating the list of items in the cyclic field printf("It is used to extend the setting") /*trCyclicList = '( "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "20" "21" "22" ) ;;; creating the cyclic field trCyclicField = hiCreateCyclicField( ?name 'trCyclicField ?prompt "Cycle Through: " ?choices trCyclicList ?value "3" ?defValue "7" ?callback "println" ) ;;; creating the boolean button field. ;;; The callback for the trBooleanButton field dynamically ;;; retrieves the new value of the field and embeds it in a ;;; message trBooleanButton = hiCreateBooleanButton( ?name 'trBooleanButton ?buttonText "Boolean" ?value t ?defValue nil ?callback "println( hiGetCurrentForm()->trBooleanButton-> value )" ) ;;; creating the button box field trButtonBoxField = hiCreateButtonBoxField( ?name 'trButtonBoxField ?prompt "Button Box" ?choices '("Do a" "Do b" "Do c") ?callback '("println( 'a )" "println( 'b )" "println( 'c )" ) ) ;;; creating the radio field. ;;; The callback for the trConeRadioField field dynamically ;;; retrieves the new value of the field and imbeds it in a ;;; message trConeRadioField = hiCreateRadioField( ?name 'trConeRadioField ?prompt "Cone Size: " ?choices list( "small" "medium" "large" ) ?value "small" ?defValue "large" ?callback '( "printf( \"\n%s cone chosen \" hiGetCurrentForm() ->trConeRadioField->value )" ) ) ;;; creating the scale field trScaleField = hiCreateScaleField( ?name 'trScaleField ?prompt "Slide " ?value 500 ?defValue 250 ?callback "println(\"scale changed \")" ?range 0:750 ) ;;; creating the label field trLabelField = hiCreateLabel( ?name 'trLabelField ?labelText "Label" ?justification CDS_JUSTIFY_RIGHT ) ;;; creating the form hiCreateAppForm( ?name 'trSampleForm ?formTitle "Other Setting Form" ?callback "println( 'FormAction )" ?fields list( trCyclicField trBooleanButton trButtonBoxField trConeRadioField trScaleField trLabelField ) ?unmapAfterCB t ) ; hiCreateAppForm ;;; displaying the form hiDisplayForm( trSampleForm ) */ ) procedure( mainOLayout() case( SRAMPorts (1 load("./sram_compiler/layout.il") ) (2 load("./sram_compiler/layout_dual.il") ) (4 println("I love you!") ) (t println("Ports is out of range!") ) ) ) procedure( mainOAbstract() load("./sram_compiler/abstract.il") ) procedure( mainOSymbol() case( SRAMPorts (1 load("./sram_compiler/symbol.il") ) (2 load("./sram_compiler/symbol_dual.il") ) (4 println("I love you!") ) (t println("Ports is out of range!") ) ) ) procedure( mainOVerilog() load("./sram_compiler/verilog.il") ) procedure( mainOTestVec() load("./sram_compiler/testVec.il") ) procedure( mainOVhdl() load("./sram_compiler/vhdl.il") ) procedure( mainCloseProc() println("Thank you for your use of our SRAM Compiler!!!") ) Open_item = hiCreateMenuItem( ?name 'Open_item ?itemText "Open" ?callback "mainOpen()" ) Report_item = hiCreateMenuItem( ?name 'Report_item ?itemText "Result Report" ?callback "mainReport()" ) About_item = hiCreateMenuItem( ?name 'About_item ?itemText "About SRAM Compiler" ?callback "mainAbout()" ) LoadState_item = hiCreateMenuItem( ?name 'LoadState_item ?itemText "Load State" ?callback "mainLoadState()" ) SaveState_item = hiCreateMenuItem( ?name 'SaveState_item ?itemText "Save State" ?callback "mainSaveState()" ) Reset_item = hiCreateMenuItem( ?name 'Reset_item ?itemText "Open" ?callback "mainReset()" ) Exit_item = hiCreateMenuItem( ?name 'Exit_item ?itemText "Exit" ?callback "mainExit()" ) ModuleName_item = hiCreateMenuItem( ?name 'ModuleName_item ?itemText "Module Name" ?callback "mainModuleName()" ) Words_item = hiCreateMenuItem( ?name 'Words_item ?itemText "Words&Bits" ?callback "mainWordBits()" ) Library_item = hiCreateMenuItem( ?name 'Library_item ?itemText "Working Library" ?callback "mainLibrary()" ) TecLibrary_item = hiCreateMenuItem( ?name 'TecLibrary_item ?itemText "Technology Library" ?callback "mainTecLibrary()" ) Workpath_item = hiCreateMenuItem( ?name 'Workpath_item ?itemText "Working Path" ?callback "mainWorkpath()" ) Ports_item = hiCreateMenuItem( ?name 'Ports_item ?itemText "Ports" ?callback "mainPorts()" ) other_item = hiCreateMenuItem( ?name 'other_item ?itemText "other..." ?callback "mainOther()" ) OLayout_item = hiCreateMenuItem( ?name 'OLayout_item ?itemText "Layout" ?callback "mainOLayout()" ) OAbstract_item = hiCreateMenuItem( ?name 'OAbstract ?itemText "Abstract(SE)" ?callback "mainOAbstract()" ) OSymbol_item = hiCreateMenuItem( ?name 'OSymbol_item ?itemText "Symbol" ?callback "mainOSymbol()" ) OVerilog_item = hiCreateMenuItem( ?name 'OVerilog_item ?itemText "Verilog" ?callback "mainOVerilog()" ) OTestVec_item = hiCreateMenuItem( ?name 'OTestVec_item ?itemText "Test Vector" ?callback "mainOTestVec()" ) OVhdl_item = hiCreateMenuItem( ?name 'OVhdl_item ?itemText "Vhdl" ?callback "mainOVhdl()" ) hiCreatePulldownMenu( 'mainFileMenu "File" list(Exit_item) ; list(SaveState_item LoadState_item Exit_item) ) hiCreatePulldownMenu( 'mainSetUpMenu "Set Up" list( ModuleName_item Words_item Ports_item TecLibrary_item Workpath_item other_item) ) hiCreatePulldownMenu( 'mainOutputMenu "Output" list( OVhdl_item OVerilog_item OSymbol_item OAbstract_item OTestVec_item) Library_item OLayout_item ) hiCreatePulldownMenu( 'mainMiscMenu "Misc" list( Report_item About_item ) ) /* First, make the DisplayList. */ dl = dlMakeDisplayList( ) /* Now make a pen table for it. */ penTable = dlMakePenTable(5) /* Assign the penTable to the display list. */ dlSetPenTable( dl penTable) /* Define a couple of colors. */ colorIndex = hiMatchColor( nameToColor( "blue")) dlSetPenColor( 1 colorIndex penTable) /* Set this pen "filled." */ dlSetPenFillStyle( 1 "SolidFill" penTable) /* Put the objects in. */ dlAddBox( dl 1 30:30 50:50) dlAddBox( dl 2 35:35 45:45) dlAddCircle( dl 3 40:40 5) sprintf( welSpring " ***************************************************** \n Welcome to the SRAM Compiler . . . %s ! \n Copyright reserved by Tsinghua University IME \n ***************************************************** \n" getShellEnvVar("USER")) dlAddStrokeText( dl 3 40:25 welSpring "upperCenter" "roman" 2 "0" ) dlAddStrokeText( dl 3 40:43 "SRCP" "upperCenter" "roman" 3 "0" ) ;dlAddRasterText( dl 4 50:50 welSpring "roman" ) /* Make a window. Put the DisplayList into the window */ /* and set the window's icon. */ w = hiOpenWindow( ?bBox list(50:50 850:350) ?type "graphics" ; ?appType "SRAM Compiler" ?menus list('mainFileMenu icfbToolsMenu 'mainSetUpMenu 'mainOutputMenu 'mainMiscMenu) ; ?menus list('mainFileMenu 'mainSetUpMenu 'mainOutputMenu 'mainMiscMenu) ?labels list( " Copyright reserved by Tsinghua University " " IME ") ?help "SRAMCompilerHelp " ?scroll nil ; ?closeProc "mainCloseProc" ) hiSetWindowName( w "SRAM Compiler" ) hiSetIconName( w "SRAM Compiler" ) dlAttachDlistToWindow( dl w) /* Convert the dlist to an icon. */ icon = dlDlistToIcon( dl 50 50) hiSetWindowIcon( w icon) /* Save it to a file. */ dlSaveDlist( dl "save.dlist" "newDl") /* Try resizing the window. The dlist will fit inside it. */ /* Iconify the window. */ 图 7-1 SRAM 编译器的主界面 图 7-2 SRAM 编译器的 File 菜单 图 7-3 SRAM 编译器的 Tools 菜单 图 7-4 SRAM 编译器的 Set Up 菜单 图 7-5 SRAM 编译器的 Output 菜单 图 7-6SRAM 编译器的 Misc 菜单 附录 1 技术文件及显示文件示例 Technology File and Display Resource File Examples This appendix contains: Technology File Example Display Resource File Example Technology File Example The following is a example of an ASCII technology file. ; Generated on Nov 14 07:50:20 1996 ; with layoutPlus version 4.4.1 Wed Nov 13 22:29:27 PST 1996 (cds3003) ;******************************** ; Controls DEFINITION ;******************************** controls( techParams(theta 2.0) ) physicalRules( techDefineSpacingRule( (minWidth metal1 techGetParam("theta") * 2)) ) ;******************************** ; LAYER DEFINITION ;******************************** layerDefinitions( techPurposes( ;( PurposeName Purpose# Abbreviation ) ;( ----------- -------- ------------ ) ;User-Defined Purposes: ;System-Reserved Purposes: ( drawing1 241 dr1 ) ( pin 251 pin ) ) ;techPurposes techLayers( ;( LayerName Layer# Abbreviation ) ;( --------- ------ ------------ ) ;User-Defined Layers: ( ndiff 1 ndiff ) ( pwell 6 pwell ) ;System-Reserved Layers: ( Unrouted 200 unRoute ) ( Row 201 Row ) ) ;techLayers techLayerPurposePriorities( ;layers are ordered from lowest to highest priority ;( LayerName Purpose ) ;( --------- ------- ) ( nimplant drawing ) ( nwell net ) ( nwell drawing ) ) ;techLayerPurposePriorities techDisplays( ;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid ) ;( --------- ------- ------- ----- ) ( nimplant drawing ( nwell net ( nwell drawing ) ;techDisplays ------ cyan yellow yellow --- --- --------- ttttt) t t nil t nil ) ttttt) techLayerProperties( ;( PropName ( defaultWidth ( defaultWidth ) Layer1 [ Layer2 ] ndiff pdiff PropValue ) 1.000000 ) 1.000000 ) ) ;layerDefinitions ;******************************** ; LAYER RULES ;******************************** layerRules( streamLayers( ;( layer streamNumber ;( ----- ------------ ( ("ptap" "drawing") 0 ( ("ptap" "net") 0 ( ndiff 0 ) ;streamLayers dataType -------- 0 0 0 translate ) --------- ) nil ) nil ) nil ) viaLayers( ;( layer1 viaLayer layer2 ) ;( -----( poly1 ( metal1 ) ;viaLayers -------cont via ------ ) metal1 ) metal2 ) equivalentLayers( ;( list of layers ) ;( -------------- ) ( vapox metal3 ) ) ;equivalentLayers ) ;layerRules ;******************************** ; DEVICES ;******************************** devices( tcCreateCDSDeviceClass() symEnhancementDevice( ; (name sdLayer sdPurpose gateLayer gatePurpose w l sdExt gateExt ; legalRegion) (PTR pdiff drawing poly1 drawing 3 1 1.5 1 (outside pwell drawing)) ) ; ; no syDepletion devices ; symContactDevice( ; (name viaLayer viaPurpose layer1 purpose1 layer2 purpose2 ; w l (row column xPitch yPitch xBias yBias) encByLayer1 encByLayer2 legalRegion) (M1_P cont drawing metal1 drawing pdiff drawing 1 1 (1 1 1.5 1.5 center center) 0.5 0.5 _NA_) ) tfcDefineDeviceProp( ; (viewName deviceName (symbolic PTAP "substrateContact") (symbolic NTAP "substrateContact") ) propName propValue) function function symPinDevice( ; (name maskable layer1 purpose1 w1 layer2 purpose2 w2 legalRegion) (bigM1_pin t metal1 drawing 3 _NA_ _NA_ _NA_ _NA_) (pdiff_T nil pdiff drawing 1 _NA_ _NA_ _NA_ (outside pwell drawing)) (ndiff_T nil ndiff drawing 1 _NA_ _NA_ _NA_ (inside pwell drawing)) ) ; ; no ruleContact devices ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Opus Symbolic Device Class Definition ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; no other device classes ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Opus Symbolic Device Declaration ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ; no other devices ; ) ;devices ;******************************** ; PHYSICAL RULES ;******************************** physicalRules( orderedSpacingRules( ;( rule layer1 layer2 value ) ;( ---- ------ ------ ----- ) ( minEnclosure "cellBoundary" "nwell" 0.1 ) ( minEnclosure "ndiff" "cont" 0.5 ) ) ;orderedSpacingRules spacingRules( ;( rule ;( ---- ( minSpacing ( minSpacing ) ;spacingRules layer1 ------ "ndiff" "pdiff" layer2 ------ 1.0 ) 1.0 ) value ) ----- ) mfgGridResolution( ( 0.100000 ) ) ;mfgGridResolution ) ;physicalRules ;******************************** ; COMPACTOR RULES ;******************************** compactorRules( compactorLayers( ;( layer usage ) ;( ----- ----- ) ( ndiff "diffusion" ) ( pdiff "diffusion" ) ) ;compactorLayers symWires( ;(name layer [(impLayer impSpacing)] [(default min max)] [(legalRegion regionLayer)] [WLM]) ( metal2 ("metal2" "drawing") nil (0.6 nil nil) ) ( metal1 ("metal1" "drawing") nil (0.6 nil nil) ) ) ;symWires ) ;compactorRules ;******************************** ; LAS RULES ;******************************** lasRules( lasLayers( ;( layer ;( ----- ( ndiff ( pdiff usage ) ----- ) "ndiffLayer" ) "pdiffLayer" ) ( ("pwell" "drawing") ) ;lasLayers "pwellLayer" ) lasDevices( ;( cellview ;( -------) ;lasDevices Las name ) -------- ) ) ;lasRules ;******************************** ; LE RULES ;******************************** leRules( leLswLayers( ;( layer purpose ) ;( ----- ------- ) ( metal1Res drawing ) ( text drawing ) ) ;leLswLayers ) ;leRules ;******************************** ; P&R RULES ;******************************** prRules( prRoutingLayers( ;( layer ;( ----- ( poly1 preferredDirection ) ------------------ ) "halfRoute" ) ( metal1 ) ;prRoutingLayers "horizontal" ) prMastersliceLayers( ;( layers : listed in order of lowest (closest to substrate) to highest ) ;( --------------------------------------------------------- ----------- ) ( ndiff pdiff ) ) ;prMastersliceLayers ) ;prRules Display Resource File Example The following is an example of a display resource (display.drf) file. drDefineDisplay( ;( DisplayName #Colors #Stipple #LineStyles ) ( display 52 32 32 ) ( psb 32 32 32 ) ( hp8 32 32 32 ) ( versatecb 32 32 32 ) ) drDefineColor( ;( DisplayName ColorsName Red Green Blue ) ( display white 255 255 255 ) ( display yellow 255 255 0 ) ( display silver 217 230 255 ) ) drDefineStipple( ;( DisplayName StippleName Bitmap ) ( display dots ((0100010001000100 ) (0000000000000000 ) (0001000100010001 ) (0000000000000000 ) (0100010001000100 ) (0000000000000000 ) (0001000100010001 ) (0000000000000000 ) (0100010001000100 ) (0000000000000000 ) (0001000100010001 ) (0000000000000000 ) (0100010001000100 ) (0000000000000000 ) (0001000100010001 ) (0000000000000000 ) ) ) ) drDefineLineStyle( ;( DisplayName LineStyle Size Pattern ) ( display none 1 () ) ( display solid 1 (1 1 1 ) ) ) drDefinePacket( ;( DisplayName PacketName Stipple LineStyle Fill Outline ) ( display bluevZigZag vZigZag solid blue blue ) ( display whiteXBlink x solid whiteBlink whiteBlink) ) ) drDefineColor( ;( DisplayName ColorsName Red Green Blue ) ( psb white 255 255 255 ) ( psb black 0 0 0 ) ) drDefineStipple( ;( DisplayName StippleName Bitmap ) ( psb dots ((1000100010001000 ) (0000000000000000 ) (0000000000000000 ) (0000000000000000 ) (1000100010001000 ) (0000000000000000 ) (0000000000000000 ) (0000000000000000 ) (1000100010001000 ) (0000000000000000 ) (0000000000000000 ) (0000000000000000 ) (1000100010001000 ) (0000000000000000 ) (0000000000000000 ) (0000000000000000 ) ) ) ) drDefineLineStyle( ;( DisplayName LineStyle Size Pattern ) ( psb none 1 () ) ( psb solid 1 (1 1 1 ) ) ) drDefinePacket( ;( DisplayName PacketName Stipple LineStyle Fill Outline ) ( psb blackVcc2S vcc2S solid black ) ( psb blackBackSlash backSlash solid black ) ) ) drDefineStipple( ;( DisplayName StippleName Bitmap ) ) drDefineLineStyle( ;( DisplayName LineStyle Size Pattern ) ( hp8 none 1 () ) ) drDefineStipple( ;( DisplayName StippleName Bitmap ) ) drDefineLineStyle( ;( DisplayName LineStyle Size Pattern ) ( versatecb none 1 () ) ) black black drDefinePacketAlias( "psb" "metal1" drDefinePacketAlias( "psb" "metal2" drDefinePacketAlias( "psb" "net" drDefinePacketAlias( "psb" "net2" "blackChecker") "blackChecker") "blackChecker") "blackChecker") 附录 2 Verilog-XL 实例文件 1. Test _me mor y.v `timescale 1ns/10ps `include "SRAM256X8.v" module test_system; reg [7:0] SRAM_ADDR_REG; reg [7:0] SRAM_VALUE_REG; reg SRAM_OEB_REG reg SRAM_WEB_REG reg clock wire [7:0] SRAM_ADDR; wire [7:0] SRAM_VALUE; wire SRAM_OEB wire SRAM_WEB wire SRAM_OUT assign SRAM_ADDR = SRAM_ADDR_REG assign SRAM_VALUE = SRAM_VALUE_REG assign SRAM_WEB = SRAM_WEB_REG assign SRAM_OEB = SRAM_OEB_REG u_SRAM256X8 SRAM256X8(clk, SRAM_OEB, SRAM_WEB, SRAM_ADDR, SRAM_VALUE, SRAM_OUT) initial begin SRAM_ADDR_REG = 8'd0; SRAM_VALUE_REG = 8'hff; SRAM_WEB_REG = 0; SRAM_OEB_REB = 1; #1590050 ; for(i=0;i<1024;i=i+1) begin SRAM_ADDR_REG = SRAM_ADDR_REG + 1; if(SRAM_ADDR_REG > 8'h00) SRAM_reg_value = SRAM_reg_value - 1; else SRAM_reg_value = 8'hFF; #100 ; end #1000 k =0 ; SRAM_WEB_REG = 1 SRAM_OEB_REG =0; #100000 $stop; end always #50 clk = ~clk; endmodule 2.SRAM256X8.v // Technology: TCB773 (TSMC Design Rule) // Created by: -f, TSMC ASIC // Created Date: Wed Nov 19 19:36:14 CST 1997 `celldefine `suppress_faults `timescale 1 ns / 10 ps `include "ram_sy1s_8052.v" module SRAM256X8 (CEB ,OEB ,WEB ,A ,IN ,OUT); parameter numAddr = 8 ; parameter numOut = 8 ; parameter wordDepth = 256 ; input [7:0] A; input CEB; input WEB; input OEB; input [7:0] IN; output [7:0] OUT; reg notifier_CEB_WEB ; reg notifier_CEB_A ; reg notifier_CEB_IN ; reg notifier_CEB ; tri1 check_CEB_WEB ; tri1 check_CEB_A ; tri1 check_CEB_IN ; tri1 check_CEB ; wire [7:0] A_buf; wire CEB_buf; wire WEB_buf; wire OEB_buf; wire [7:0] IN_buf; wire [7:0] OUT_buf; buf (A_buf[0] , A[0] ); buf (A_buf[1] , A[1] ); buf (A_buf[2] , A[2] ); buf (A_buf[3] , A[3] ); buf (A_buf[4] , A[4] ); buf (A_buf[5] , A[5] ); buf (A_buf[6] , A[6] ); buf (A_buf[7] , A[7] ); buf (CEB_buf , CEB ); buf (WEB_buf , WEB ); buf (OEB_buf , OEB ); buf (IN_buf[0] , IN[0] ); buf (IN_buf[1] , IN[1] ); buf (IN_buf[2] , IN[2] ); buf (IN_buf[3] , IN[3] ); buf (IN_buf[4] , IN[4] ); buf (IN_buf[5] , IN[5] ); buf (IN_buf[6] , IN[6] ); buf (IN_buf[7] , IN[7] ); pmos (OUT[0] ,OUT_buf[0] ,1'b0); pmos (OUT[1] ,OUT_buf[1] ,1'b0); pmos (OUT[2] ,OUT_buf[2] ,1'b0); pmos (OUT[3] ,OUT_buf[3] ,1'b0); pmos (OUT[4] ,OUT_buf[4] ,1'b0); pmos (OUT[5] ,OUT_buf[5] ,1'b0); pmos (OUT[6] ,OUT_buf[6] ,1'b0); pmos (OUT[7] ,OUT_buf[7] ,1'b0); ram_sy1s_8052 #( numAddr , numOut , wordDepth ) core ( .EX(1'b0) , .A ( A_buf[7:0] ) , .CEB ( CEB_buf ) , .WEB ( WEB_buf ) , .OEB ( OEB_buf ) , .IN ( IN_buf[7:0] ) , .OUT ( OUT_buf[7:0] ) , .notifier_CEB_WEB ( notifier_CEB_WEB ) , .notifier_CEB_A ( notifier_CEB_A ) , .notifier_CEB_IN ( notifier_CEB_IN ) , .notifier_CEB ( notifier_CEB ) , .check_CEB_WEB ( check_CEB_WEB ) , .check_CEB_A ( check_CEB_A ) , .check_CEB_IN ( check_CEB_IN ) , .check_CEB ( check_CEB ) ); specify specparam CellType = "MEMORY"; specparam TristateDisable$OEB$OUT = "OEB", TristateEnable$OEB$OUT = "OEB"; specparam F_Prop$CEB$OUT = 4.70, F_Ramp$CEB$OUT = 0.30, R_Prop$CEB$OUT = 4.70, R_Ramp$CEB$OUT = 0.30, disable$F_Prop$OEB$OUT = 1.10, disable$F_Ramp$OEB$OUT = 0.00, disable$R_Prop$OEB$OUT = 1.10, disable$R_Ramp$OEB$OUT = 0.00, enable$F_Prop$OEB$OUT = 1.30, enable$F_Ramp$OEB$OUT = 0.30, enable$R_Prop$OEB$OUT = 1.30, enable$R_Ramp$OEB$OUT = 0.30; specparam Cap$A = 0.120, Cap$CEB = 0.040, Cap$IN = 0.020, Cap$OEB = 0.010, Cap$OUT = 0.040, Cap$WEB = 0.040; specparam cell_count specparam Transistors specparam Width specparam Height specparam Power = 0.0000; = 0; = 503.9995; = 367.0757; = 230.0000; // pin-to-pin delays (CEB *> OUT[0])=(4.70); (CEB *> OUT[1])=(4.70); (CEB *> OUT[2])=(4.70); (CEB *> OUT[3])=(4.70); (CEB *> OUT[4])=(4.70); (CEB *> OUT[5])=(4.70); (CEB *> OUT[6])=(4.70); (CEB *> OUT[7])=(4.70); (OEB *> OUT[0])=(1.30, 1.30, 1.10); (OEB *> OUT[1])=(1.30, 1.30, 1.10); (OEB *> OUT[2])=(1.30, 1.30, 1.10); (OEB *> OUT[3])=(1.30, 1.30, 1.10); (OEB *> OUT[4])=(1.30, 1.30, 1.10); (OEB *> OUT[5])=(1.30, 1.30, 1.10); (OEB *> OUT[6])=(1.30, 1.30, 1.10); (OEB *> OUT[7])=(1.30, 1.30, 1.10); // setup & hold, minimum pulse width timing checks $setup(negedge A, negedge CEB &&& check_CEB_A, 0.00, notifier_CEB_A); $setup(negedge IN, negedge CEB &&& check_CEB_IN, 0.00, notifier_CEB_IN); $setup(negedge WEB, negedge CEB &&& check_CEB_WEB, 0.00, notifier_CEB_WEB); $setup(posedge A, negedge CEB &&& check_CEB_A, 0.00, notifier_CEB_A); $setup(posedge IN, negedge CEB &&& check_CEB_IN, 0.00, notifier_CEB_IN); $setup(posedge WEB, negedge CEB &&& check_CEB_WEB, 0.00, notifier_CEB_WEB); $hold(negedge CEB, negedge A &&& check_CEB_A, 1.30, notifier_CEB_A); $hold(negedge CEB, negedge IN &&& check_CEB_IN, 4.90, notifier_CEB_IN); $hold(negedge CEB, negedge WEB &&& check_CEB_WEB, 4.90, notifier_CEB_WEB); $hold(negedge CEB, posedge A &&& check_CEB_A, 1.30, notifier_CEB_A); $hold(negedge CEB, posedge IN &&& check_CEB_IN, notifier_CEB_IN); $hold(negedge CEB, posedge WEB &&& check_CEB_WEB, notifier_CEB_WEB); $width(posedge CEB &&& check_CEB, 0.00, 0, notifier_CEB); $width(negedge CEB &&& check_CEB, 0.00, 0, notifier_CEB); endspecify 4.90, 4.90, endmodule `nosuppress_faults `endcelldefine 3.ram_sy1s_8052 /**************************************************************/ /* TSMC Verilog modle of memory cell ram_sy1s v1.1 */ /* Created by Albert Hung-Chun Li , Date 12/18/96 */ /* Revision for conditional timing check , 04/02/97 */ /* Description */ /* Synchronous one port RAM separated IO */ /* Ports */ /* A : address input buffer */ /* IN : data input port */ /* OUT : data output port */ /* CEB : chip enable */ /* WEB : write enable */ /* OEB : output enable */ /* Parameters */ /* numAddr : number of address lines */ /* numOut : number of bits per word */ /* wordDepth : number of words */ /**************************************************************/ `timescale 1ns/10ps `celldefine module ram_sy1s_8052(EX, A, CEB, WEB, OEB, IN, OUT, notifier_CEB_WEB, notifier_CEB_A, notifier_CEB_IN, notifier_CEB, check_CEB_WEB, check_CEB_A, check_CEB_IN, check_CEB); parameter numAddr = 1, numOut = 1, wordDepth = 2; input CEB, WEB, OEB, EX; input [numAddr-1:0] A; input [numOut-1:0] IN; output [numOut-1:0] OUT; input notifier_CEB_WEB, notifier_CEB_A, notifier_CEB_IN, notifier_CEB; output check_CEB_WEB, check_CEB_A, check_CEB_IN, check_CEB; `protect reg check_CEB_WEB, check_CEB_A, check_CEB_IN, check_CEB; reg [numOut-1:0] intBus; reg [numOut-1:0] memory[wordDepth-1:0]; reg wr_flag, rd_flag, lastCEB; reg [numAddr-1:0] address; initial begin check_CEB_WEB = 1'b1; check_CEB_A = 1'b1; check_CEB_IN = 1'b0; check_CEB = 1'b1; end //zab add initial #10 if(EX) $readmemb("extend_SRAM.dat", memory); else $readmemb("SRAM.dat", memory); wire[7:0] sram0 = memory[0]; wire[7:0] sram1 = memory[1]; wire[7:0] sram8 = memory[8]; assign OUT = OEB ? {numOut{1'bz}} : intBus; always @(OEB) begin if ((OEB === 1'bx) || (OEB === 1'bz)) $display("%m> OEB is unknown so output unknown %.1f",$realtime); end always @(WEB) begin if (WEB===1'b0) check_CEB_IN = 1'b1; else check_CEB_IN = 1'b0; end always @(CEB) begin if ((CEB === 1'bx) || (CEB === 1'bz)) begin $display ("%m> CEB is unknown at time %.1f", $realtime); address = {numAddr{1'bx}}; intBus = {numOut{1'bx}}; end else if ((CEB == 1'b0) && (lastCEB == 1'b1)) begin address = A; rd_flag = 0; wr_flag = 0; if (WEB == 1'b1) intBus = {numOut{1'bx}}; if (^address === 1'bx) begin //------ CHECK ADDRESS //$display("%m> Address is unknown - cannot access memory %.1f", $realtime); end else if (address >= wordDepth) begin $display("%m> Address is out of range - cannot access memory %.1f", $realtime); end else begin : rw_cycle if (WEB == 1'b1) begin //-------- READ CYCLE START rd_flag = 1; intBus = memory[address]; end else if (WEB == 1'b0) begin //-------- WRITE CYCLE START wr_flag = 1; memory[address] = IN; end else begin //-------- UNKNOWN CYCLE //$display("%m> WEB is unknown at start of output cycle %.1f", $realtime); intBus = {numOut{1'bx}}; memory[address] = {numOut{1'bx}}; end end end lastCEB = CEB ; end task MemErr; begin #0 disable rw_cycle; if (rd_flag) intBus = {numOut{1'bx}}; if (wr_flag) memory[address] = {numOut{1'bx}}; rd_flag = 0; wr_flag = 0; end endtask always @notifier_CEB_WEB begin $display ("%m> WEB setup/hold time not met so WEB unknown %.1f", $realtime); MemErr; end always @notifier_CEB_A begin $display ("%m> Address setup/hold time not met so address unknown %.1f", $realtime); MemErr; address = {numAddr{1'bx}}; end always @notifier_CEB_IN begin $display ("%m> Data setup/hold time not met so data unknown %.1f", $realtime); disable rw_cycle; if (wr_flag) memory[address] = {numOut{1'bx}}; wr_flag = 0; end always @notifier_CEB begin $display("%m> Clock cycle time too short - cycle terminated %.1f", $realtime); MemErr; end `endprotect endmodule `endcelldefine 4.TSMC 库文件 // TSMC Standard Cell Function Library Ver // Model Type: AN2Dx , Mon Nov 24 11:08:44 CST 1997 `timescale 1ns / 10ps `celldefine module AN2D1 (A1, A2, Z); input A1, A2; output Z; and (Z, A1, A2); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN2Dx , Mon Nov 24 11:08:44 CST 1997 `timescale 1ns / 10ps `celldefine module AN2D2 (A1, A2, Z); input A1, A2; output Z; and (Z, A1, A2); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN2Dx , Mon Nov 24 11:08:44 CST 1997 `timescale 1ns / 10ps `celldefine module AN2D3 (A1, A2, Z); input A1, A2; output Z; and (Z, A1, A2); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN3Dx , Mon Nov 24 11:08:44 CST 1997 `timescale 1ns / 10ps `celldefine module AN3D1 (A1, A2, A3, Z); input A1, A2, A3; output Z; and (Z, A1, A2, A3); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN3Dx , Mon Nov 24 11:08:44 CST 1997 `timescale 1ns / 10ps `celldefine module AN3D2 (A1, A2, A3, Z); input A1, A2, A3; output Z; and (Z, A1, A2, A3); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN3Dx , Mon Nov 24 11:08:44 CST 1997 `timescale 1ns / 10ps `celldefine module AN3D3 (A1, A2, A3, Z); input A1, A2, A3; output Z; and (Z, A1, A2, A3); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN4Dx , Mon Nov 24 11:08:44 CST 1997 `timescale 1ns / 10ps `celldefine module AN4D1 (A1, A2, A3, A4, Z); input A1, A2, A3, A4; output Z; and (Z, A1, A2, A3, A4); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN4Dx , Mon Nov 24 11:08:44 CST 1997 `timescale 1ns / 10ps `celldefine module AN4D2 (A1, A2, A3, A4, Z); input A1, A2, A3, A4; output Z; and (Z, A1, A2, A3, A4); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN4Dx , Mon Nov 24 11:08:44 CST 1997 `timescale 1ns / 10ps `celldefine module AN4D3 (A1, A2, A3, A4, Z); input A1, A2, A3, A4; output Z; and (Z, A1, A2, A3, A4); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN5Dx , Mon Nov 24 11:08:45 CST 1997 `timescale 1ns / 10ps `celldefine module AN5D1 (A1, A2, A3, A4, A5, Z); input A1, A2, A3, A4, A5; output Z; and (Z, A1, A2, A3, A4, A5); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN5Dx , Mon Nov 24 11:08:45 CST 1997 `timescale 1ns / 10ps `celldefine module AN5D2 (A1, A2, A3, A4, A5, Z); input A1, A2, A3, A4, A5; output Z; and (Z, A1, A2, A3, A4, A5); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN6Dx , Mon Nov 24 11:08:45 CST 1997 `timescale 1ns / 10ps `celldefine module AN6D1 (A1, A2, A3, A4, A5, A6, Z); input A1, A2, A3, A4, A5, A6; output Z; and (Z, A1, A2, A3, A4, A5, A6); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN6Dx , Mon Nov 24 11:08:45 CST 1997 `timescale 1ns / 10ps `celldefine module AN6D2 (A1, A2, A3, A4, A5, A6, Z); input A1, A2, A3, A4, A5, A6; output Z; and (Z, A1, A2, A3, A4, A5, A6); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN7Dx , Mon Nov 24 11:08:45 CST 1997 `timescale 1ns / 10ps `celldefine module AN7D1 (A1, A2, A3, A4, A5, A6, A7, Z); input A1, A2, A3, A4, A5, A6, A7; output Z; and (Z, A1, A2, A3, A4, A5, A6, A7); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN7Dx , Mon Nov 24 11:08:45 CST 1997 `timescale 1ns / 10ps `celldefine module AN7D2 (A1, A2, A3, A4, A5, A6, A7, Z); input A1, A2, A3, A4, A5, A6, A7; output Z; and (Z, A1, A2, A3, A4, A5, A6, A7); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN8Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module AN8D1 (A1, A2, A3, A4, A5, A6, A7, A8, Z); input A1, A2, A3, A4, A5, A6, A7, A8; output Z; and (Z, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); (A8 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AN8Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module AN8D2 (A1, A2, A3, A4, A5, A6, A7, A8, Z); input A1, A2, A3, A4, A5, A6, A7, A8; output Z; and (Z, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); (A8 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI211Dx , Mon Nov 24 11:09:10 CST 1997 `timescale 1ns / 10ps `celldefine module AOI211D0 (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; and (A, A1, A2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI211Dx , Mon Nov 24 11:09:10 CST 1997 `timescale 1ns / 10ps `celldefine module AOI211D1 (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; and (A, A1, A2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI211Dx , Mon Nov 24 11:09:10 CST 1997 `timescale 1ns / 10ps `celldefine module AOI211D1H (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; and (A, A1, A2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI211Dx , Mon Nov 24 11:09:10 CST 1997 `timescale 1ns / 10ps `celldefine module AOI211D2 (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; and (A, A1, A2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI211Dx , Mon Nov 24 11:09:10 CST 1997 `timescale 1ns / 10ps `celldefine module AOI211D3 (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; and (A, A1, A2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI21Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI21D0 (A1, A2, B, ZN); input A1, A2, B; output ZN; and (A, A1, A2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI21Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI21D1 (A1, A2, B, ZN); input A1, A2, B; output ZN; and (A, A1, A2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI21Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI21D1H (A1, A2, B, ZN); input A1, A2, B; output ZN; and (A, A1, A2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI21Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI21D2 (A1, A2, B, ZN); input A1, A2, B; output ZN; and (A, A1, A2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI21Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI21D3 (A1, A2, B, ZN); input A1, A2, B; output ZN; and (A, A1, A2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI221Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI221D0 (A1, A2, B1, B2, C, ZN); input A1, A2, B1, B2, C; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI221Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI221D1 (A1, A2, B1, B2, C, ZN); input A1, A2, B1, B2, C; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI221Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI221D1H (A1, A2, B1, B2, C, ZN); input A1, A2, B1, B2, C; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI221Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI221D2 (A1, A2, B1, B2, C, ZN); input A1, A2, B1, B2, C; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI221Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI221D3 (A1, A2, B1, B2, C, ZN); input A1, A2, B1, B2, C; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI222Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI222D0 (A1, A2, B1, B2, C1, C2, ZN); input A1, A2, B1, B2, C1, C2; output ZN; and (A, A1, A2); and (B, B1, B2); and (C, C1, C2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C1 => ZN)=(0, 0); (C2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI222Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI222D1 (A1, A2, B1, B2, C1, C2, ZN); input A1, A2, B1, B2, C1, C2; output ZN; and (A, A1, A2); and (B, B1, B2); and (C, C1, C2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C1 => ZN)=(0, 0); (C2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI222Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI222D1H (A1, A2, B1, B2, C1, C2, ZN); input A1, A2, B1, B2, C1, C2; output ZN; and (A, A1, A2); and (B, B1, B2); and (C, C1, C2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C1 => ZN)=(0, 0); (C2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI222Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI222D2 (A1, A2, B1, B2, C1, C2, ZN); input A1, A2, B1, B2, C1, C2; output ZN; and (A, A1, A2); and (B, B1, B2); and (C, C1, C2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C1 => ZN)=(0, 0); (C2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI222Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI222D3 (A1, A2, B1, B2, C1, C2, ZN); input A1, A2, B1, B2, C1, C2; output ZN; and (A, A1, A2); and (B, B1, B2); and (C, C1, C2); nor (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C1 => ZN)=(0, 0); (C2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI22Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI22D0 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI22Dx , Mon Nov 24 11:09:11 CST 1997 `timescale 1ns / 10ps `celldefine module AOI22D1 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI22Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI22D1H (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI22Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI22D2 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI22Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI22D3 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; and (A, A1, A2); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI31Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI31D0 (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; and (A, A1, A2, A3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI31Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI31D1 (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; and (A, A1, A2, A3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI31Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI31D1H (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; and (A, A1, A2, A3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI31Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI31D2 (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; and (A, A1, A2, A3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI31Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI31D3 (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; and (A, A1, A2, A3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI32Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI32D0 (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; and (A, A1, A2, A3); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI32Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI32D1 (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; and (A, A1, A2, A3); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI32Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI32D1H (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; and (A, A1, A2, A3); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI32Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI32D2 (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; and (A, A1, A2, A3); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI32Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI32D3 (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; and (A, A1, A2, A3); and (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI33Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI33D0 (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; and (A, A1, A2, A3); and (B, B1, B2, B3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI33Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI33D1 (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; and (A, A1, A2, A3); and (B, B1, B2, B3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI33Dx , Mon Nov 24 11:09:13 CST 1997 `timescale 1ns / 10ps `celldefine module AOI33D1H (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; and (A, A1, A2, A3); and (B, B1, B2, B3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI33Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI33D2 (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; and (A, A1, A2, A3); and (B, B1, B2, B3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AOI33Dx , Mon Nov 24 11:09:12 CST 1997 `timescale 1ns / 10ps `celldefine module AOI33D3 (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; and (A, A1, A2, A3); and (B, B1, B2, B3); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AS1Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module AS1D1 (A, B, CI, ADD, S, CO); input A, B, CI, ADD; output S, CO; xnor xor (B1, B, ADD); (S, A, B1, CI); and (n3, A, CI); and (n4, B1, CI); and (n5, A, B1); or (CO, n3, n4, n5); specify (A => CO)=(0, 0); (A => S)=(0, 0); (ADD => CO)=(0, 0); (ADD => S)=(0, 0); (B => CO)=(0, 0); (B => S)=(0, 0); (CI => CO)=(0, 0); (CI => S)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: AS1Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module AS1D2 (A, B, CI, ADD, S, CO); input A, B, CI, ADD; output S, CO; xnor xor and and (B1, B, ADD); (S, A, B1, CI); (n3, A, CI); (n4, B1, CI); and (n5, A, B1); or (CO, n3, n4, n5); specify (A => CO)=(0, 0); (A => S)=(0, 0); (ADD => CO)=(0, 0); (ADD => S)=(0, 0); (B => CO)=(0, 0); (B => S)=(0, 0); (CI => CO)=(0, 0); (CI => S)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BHDx , Mon Nov 24 11:08:38 CST 1997 `timescale 1ns / 10ps `celldefine module BHD1 (Z); inout Z; trireg (small) #(0.01, 0.01, 1.00E30) Z; endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUF1 (I, Z); input I; output Z; buf (Z, I); specify (I => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUF2 (I, Z); input I; output Z; buf (Z, I); specify (I => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUF3 (I, Z); input I; output Z; buf (Z, I); specify (I => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUF4 (I, Z); input I; output Z; buf (Z, I); specify (I => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUF5 (I, Z); input I; output Z; buf (Z, I); specify (I => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUF6 (I, Z); input I; output Z; buf (Z, I); specify (I => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUFT1 (I, OE, Z); input I, OE; output Z; bufif1 (Z, I, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUFT2 (I, OE, Z); input I, OE; output Z; bufif1 (Z, I, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUFT3 (I, OE, Z); input I, OE; output Z; bufif1 (Z, I, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUFT4 (I, OE, Z); input I, OE; output Z; bufif1 (Z, I, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module BUFT5 (I, OE, Z); input I, OE; output Z; bufif1 (Z, I, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTNx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module BUFTN1 (I, OEN, Z); input I, OEN; output Z; bufif0 (Z, I, OEN); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OEN => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTNx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module BUFTN2 (I, OEN, Z); input I, OEN; output Z; bufif0 (Z, I, OEN); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OEN => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTNx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module BUFTN3 (I, OEN, Z); input I, OEN; output Z; bufif0 (Z, I, OEN); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OEN => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTNx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module BUFTN4 (I, OEN, Z); input I, OEN; output Z; bufif0 (Z, I, OEN); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OEN => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: BUFTNx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module BUFTN5 (I, OEN, Z); input I, OEN; output Z; bufif0 (Z, I, OEN); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => Z)=(0, 0); (OEN => Z)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: CNTCNx , Mon Nov 24 11:08:57 CST 1997 `timescale 1ns / 10ps `celldefine module CNTCN1 (CI, CP, CDN, Q, QN, CO); input CI, CP, CDN; output Q, QN, CO; buf (CDN_i, CDN); reg notifier; pullup (SDN); and xor tsmc_dff buf not and (CP_check,CDN_i,SDN); (D, CI, Q_buf); (Q_buf, D, CP, CDN_i, SDN, notifier); (Q, Q_buf); (QN, Q_buf); (CO, Q_buf, CI); specify (CDN => CO)=(0, 0); (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CI => CO)=(0, 0); (CP => CO)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $setup(posedge CI , posedge CP &&& CP_check, 0, notifier); $setup(negedge CI , posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge CI &&& CP_check, 0, notifier); $hold(posedge CP ,negedge CI &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: CNTCSNx , Mon Nov 24 11:08:57 CST 1997 `timescale 1ns / 10ps `celldefine module CNTCSN1 (CI, CP, CDN, SDN, Q, QN, CO); input CI, CP, CDN, SDN; output Q, QN, CO; buf (CDN_i, CDN); buf (SDN_i, SDN); reg notifier; and (CP_check, CDN_i, SDN_i); xor (D, CI, Q_buf); tsmc_dff (Q_buf, D, CP, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); not (QNN, QN); and (CO, QNN, CI); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CDN => CO)=(0, 0); (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CI => CO)=(0, 0); (CP => CO)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => CO)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge CI, posedge CP &&& CP_check, 0, notifier); $setup(negedge CI, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge CI &&& CP_check, 0, notifier); $hold(posedge CP,negedge CI &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DEC2Dx , Mon Nov 24 11:08:58 CST 1997 `timescale 1ns / 10ps `celldefine module DEC2D1 (A0, A1, Z0N, Z1N, Z2N, Z3N); input A0, A1; output Z0N, Z1N, Z2N, Z3N; not (A0N, A0); not (A1N, A1); nand (Z0N, A1N, A0N); nand (Z1N, A1N, A0); nand (Z2N, A1, A0N); nand (Z3N, A1, A0); specify (A0 => Z0N)=(0, 0); (A0 => Z1N)=(0, 0); (A0 => Z2N)=(0, 0); (A0 => Z3N)=(0, 0); (A1 => Z0N)=(0, 0); (A1 => Z1N)=(0, 0); (A1 => Z2N)=(0, 0); (A1 => Z3N)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DEC2Dx , Mon Nov 24 11:08:58 CST 1997 `timescale 1ns / 10ps `celldefine module DEC2D2 (A0, A1, Z0N, Z1N, Z2N, Z3N); input A0, A1; output Z0N, Z1N, Z2N, Z3N; not (A0N, A0); not (A1N, A1); nand (Z0N, A1N, A0N); nand (Z1N, A1N, A0); nand (Z2N, A1, A0N); nand (Z3N, A1, A0); specify (A0 => Z0N)=(0, 0); (A0 => Z1N)=(0, 0); (A0 => Z2N)=(0, 0); (A0 => Z3N)=(0, 0); (A1 => Z0N)=(0, 0); (A1 => Z1N)=(0, 0); (A1 => Z2N)=(0, 0); (A1 => Z3N)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DEC3Dx , Mon Nov 24 11:08:58 CST 1997 `timescale 1ns / 10ps `celldefine module DEC3D0 (A0, A1, A2, Z0N, Z1N, Z2N, Z3N, Z4N, Z5N, Z6N, Z7N); input A0, A1, A2; output Z0N, Z1N, Z2N, Z3N, Z4N, Z5N, Z6N, Z7N; not (A0N, A0); not (A1N, A1); not (A2N, A2); nand (Z0N, A2N, A1N, A0N); nand (Z1N, A2N, A1N, A0); nand (Z2N, A2N, A1, A0N); nand (Z3N, A2N, A1, A0); nand (Z4N, A2, A1N, A0N); nand (Z5N, A2, A1N, A0); nand (Z6N, A2, A1, A0N); nand (Z7N, A2, A1, A0); specify (A0 => Z0N)=(0, 0); (A0 => Z1N)=(0, 0); (A0 => Z2N)=(0, 0); (A0 => Z3N)=(0, 0); (A0 => Z4N)=(0, 0); (A0 => Z5N)=(0, 0); (A0 => Z6N)=(0, 0); (A0 => Z7N)=(0, 0); (A1 => Z0N)=(0, 0); (A1 => Z1N)=(0, 0); (A1 => Z2N)=(0, 0); (A1 => Z3N)=(0, 0); (A1 => Z4N)=(0, 0); (A1 => Z5N)=(0, 0); (A1 => Z6N)=(0, 0); (A1 => Z7N)=(0, 0); (A2 => Z0N)=(0, 0); (A2 => Z1N)=(0, 0); (A2 => Z2N)=(0, 0); (A2 => Z3N)=(0, 0); (A2 => Z4N)=(0, 0); (A2 => Z5N)=(0, 0); (A2 => Z6N)=(0, 0); (A2 => Z7N)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DEC3Dx , Mon Nov 24 11:08:58 CST 1997 `timescale 1ns / 10ps `celldefine module DEC3D1 (A0, A1, A2, Z0N, Z1N, Z2N, Z3N, Z4N, Z5N, Z6N, Z7N); input A0, A1, A2; output Z0N, Z1N, Z2N, Z3N, Z4N, Z5N, Z6N, Z7N; not (A0N, A0); not (A1N, A1); not (A2N, A2); nand (Z0N, A2N, A1N, A0N); nand (Z1N, A2N, A1N, A0); nand (Z2N, A2N, A1, A0N); nand (Z3N, A2N, A1, A0); nand (Z4N, A2, A1N, A0N); nand (Z5N, A2, A1N, A0); nand (Z6N, A2, A1, A0N); nand (Z7N, A2, A1, A0); specify (A0 => Z0N)=(0, 0); (A0 => Z1N)=(0, 0); (A0 => Z2N)=(0, 0); (A0 => Z3N)=(0, 0); (A0 => Z4N)=(0, 0); (A0 => Z5N)=(0, 0); (A0 => Z6N)=(0, 0); (A0 => Z7N)=(0, 0); (A1 => Z0N)=(0, 0); (A1 => Z1N)=(0, 0); (A1 => Z2N)=(0, 0); (A1 => Z3N)=(0, 0); (A1 => Z4N)=(0, 0); (A1 => Z5N)=(0, 0); (A1 => Z6N)=(0, 0); (A1 => Z7N)=(0, 0); (A2 => Z0N)=(0, 0); (A2 => Z1N)=(0, 0); (A2 => Z2N)=(0, 0); (A2 => Z3N)=(0, 0); (A2 => Z4N)=(0, 0); (A2 => Z5N)=(0, 0); (A2 => Z6N)=(0, 0); (A2 => Z7N)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DEC3Dx , Mon Nov 24 11:08:58 CST 1997 `timescale 1ns / 10ps `celldefine module DEC3D2 (A0, A1, A2, Z0N, Z1N, Z2N, Z3N, Z4N, Z5N, Z6N, Z7N); input A0, A1, A2; output Z0N, Z1N, Z2N, Z3N, Z4N, Z5N, Z6N, Z7N; not (A0N, A0); not (A1N, A1); not (A2N, A2); nand (Z0N, A2N, A1N, A0N); nand (Z1N, A2N, A1N, A0); nand (Z2N, A2N, A1, A0N); nand (Z3N, A2N, A1, A0); nand (Z4N, A2, A1N, A0N); nand (Z5N, A2, A1N, A0); nand (Z6N, A2, A1, A0N); nand (Z7N, A2, A1, A0); specify (A0 => Z0N)=(0, 0); (A0 => Z1N)=(0, 0); (A0 => Z2N)=(0, 0); (A0 => Z3N)=(0, 0); (A0 => Z4N)=(0, 0); (A0 => Z5N)=(0, 0); (A0 => Z6N)=(0, 0); (A0 => Z7N)=(0, 0); (A1 => Z0N)=(0, 0); (A1 => Z1N)=(0, 0); (A1 => Z2N)=(0, 0); (A1 => Z3N)=(0, 0); (A1 => Z4N)=(0, 0); (A1 => Z5N)=(0, 0); (A1 => Z6N)=(0, 0); (A1 => Z7N)=(0, 0); (A2 => Z0N)=(0, 0); (A2 => Z1N)=(0, 0); (A2 => Z2N)=(0, 0); (A2 => Z3N)=(0, 0); (A2 => Z4N)=(0, 0); (A2 => Z5N)=(0, 0); (A2 => Z6N)=(0, 0); (A2 => Z7N)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DECN2Dx , Mon Nov 24 11:08:59 CST 1997 `timescale 1ns / 10ps `celldefine module DECN2D0 (A0, A1, EN, Z0N, Z1N, Z2N, Z3N); input A0, A1, EN; output Z0N, Z1N, Z2N, Z3N; not not not nand nand nand nand (A0N, A0); (A1N, A1); (ENB, EN); (Z0N, A1N, A0N, ENB); (Z1N, A1N, A0, ENB); (Z2N, A1, A0N, ENB); (Z3N, A1, A0, ENB); specify (A0 => Z0N)=(0, 0); (A0 => Z1N)=(0, 0); (A0 => Z2N)=(0, 0); (A0 => Z3N)=(0, 0); (A1 => Z0N)=(0, 0); (A1 => Z1N)=(0, 0); (A1 => Z2N)=(0, 0); (A1 => Z3N)=(0, 0); (EN => Z0N)=(0, 0); (EN => Z1N)=(0, 0); (EN => Z2N)=(0, 0); (EN => Z3N)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DECN2Dx , Mon Nov 24 11:08:59 CST 1997 `timescale 1ns / 10ps `celldefine module DECN2D1 (A0, A1, EN, Z0N, Z1N, Z2N, Z3N); input A0, A1, EN; output Z0N, Z1N, Z2N, Z3N; not not not nand nand nand (A0N, A0); (A1N, A1); (ENB, EN); (Z0N, A1N, A0N, ENB); (Z1N, A1N, A0, ENB); (Z2N, A1, A0N, ENB); nand (Z3N, A1, A0, ENB); specify (A0 => Z0N)=(0, 0); (A0 => Z1N)=(0, 0); (A0 => Z2N)=(0, 0); (A0 => Z3N)=(0, 0); (A1 => Z0N)=(0, 0); (A1 => Z1N)=(0, 0); (A1 => Z2N)=(0, 0); (A1 => Z3N)=(0, 0); (EN => Z0N)=(0, 0); (EN => Z1N)=(0, 0); (EN => Z2N)=(0, 0); (EN => Z3N)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DECN2Dx , Mon Nov 24 11:08:59 CST 1997 `timescale 1ns / 10ps `celldefine module DECN2D2 (A0, A1, EN, Z0N, Z1N, Z2N, Z3N); input A0, A1, EN; output Z0N, Z1N, Z2N, Z3N; not (A0N, A0); not (A1N, A1); not (ENB, EN); nand nand nand nand (Z0N, A1N, A0N, ENB); (Z1N, A1N, A0, ENB); (Z2N, A1, A0N, ENB); (Z3N, A1, A0, ENB); specify (A0 => Z0N)=(0, 0); (A0 => Z1N)=(0, 0); (A0 => Z2N)=(0, 0); (A0 => Z3N)=(0, 0); (A1 => Z0N)=(0, 0); (A1 => Z1N)=(0, 0); (A1 => Z2N)=(0, 0); (A1 => Z3N)=(0, 0); (EN => Z0N)=(0, 0); (EN => Z1N)=(0, 0); (EN => Z2N)=(0, 0); (EN => Z3N)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DELx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module DEL2 (I, Z); input I; output Z; buf (Z, I); specify (I => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DELx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module DEL3 (I, Z); input I; output Z; buf (Z, I); specify (I => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DELx , Mon Nov 24 11:08:39 CST 1997 `timescale 1ns / 10ps `celldefine module DEL5 (I, Z); input I; output Z; buf (Z, I); specify (I => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCNx , Mon Nov 24 11:09:02 CST 1997 `timescale 1ns / 10ps `celldefine module DFCN1 (D, CP, CDN, Q, QN); input D, CP, CDN; output Q, QN; buf (CDN_i, CDN); reg notifier; pullup (SDN); and (CP_check, CDN_i, SDN); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN , 0, notifier); $setup(posedge D , posedge CP &&& CP_check , 0, notifier); $setup(negedge D , posedge CP &&& CP_check , 0, notifier); $hold(posedge CP,posedge D &&& CP_check , 0, notifier); $hold(posedge CP,negedge D &&& CP_check , 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCNx , Mon Nov 24 11:09:02 CST 1997 `timescale 1ns / 10ps `celldefine module DFCN2 (D, CP, CDN, Q, QN); input D, CP, CDN; output Q, QN; buf (CDN_i, CDN); reg notifier; pullup (SDN); and (CP_check, CDN_i, SDN); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN , 0, notifier); $setup(posedge D , posedge CP &&& CP_check , 0, notifier); $setup(negedge D , posedge CP &&& CP_check , 0, notifier); $hold(posedge CP,posedge D &&& CP_check , 0, notifier); $hold(posedge CP,negedge D &&& CP_check , 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCNx , Mon Nov 24 11:09:02 CST 1997 `timescale 1ns / 10ps `celldefine module DFCN3 (D, CP, CDN, Q, QN); input D, CP, CDN; output Q, QN; buf (CDN_i, CDN); reg notifier; pullup (SDN); and (CP_check, CDN_i, SDN); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN , 0, notifier); $setup(posedge D , posedge CP &&& CP_check , 0, notifier); $setup(negedge D , posedge CP &&& CP_check , 0, notifier); $hold(posedge CP,posedge D &&& CP_check , 0, notifier); $hold(posedge CP,negedge D &&& CP_check , 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCNTx , Mon Nov 24 11:09:03 CST 1997 `timescale 1ns / 10ps `celldefine module DFCNT1 (D, CP, CDN, OE, Q, Z); input D, CP, CDN, OE; output Q, Z; buf (CDN_i, CDN); reg notifier; pullup (SDN); and (CP_check, CDN_i, SDN); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); buf (Q, Q_buf); bufif1 (Z, Q_buf, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (CDN => Q)=(0, 0); (CDN => Z)=(0, 0); (CP => Q)=(0, 0); (CP => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $setup(posedge D, posedge CP &&& CP_check, 0, notifier); $setup(negedge D, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge D &&& CP_check, 0, notifier); $hold(posedge CP,negedge D &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCNTx , Mon Nov 24 11:09:03 CST 1997 `timescale 1ns / 10ps `celldefine module DFCNT2 (D, CP, CDN, OE, Q, Z); input D, CP, CDN, OE; output Q, Z; buf (CDN_i, CDN); reg notifier; pullup (SDN); and (CP_check, CDN_i, SDN); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); buf (Q, Q_buf); bufif1 (Z, Q_buf, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (CDN => Q)=(0, 0); (CDN => Z)=(0, 0); (CP => Q)=(0, 0); (CP => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $setup(posedge D, posedge CP &&& CP_check, 0, notifier); $setup(negedge D, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge D &&& CP_check, 0, notifier); $hold(posedge CP,negedge D &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCSNx , Mon Nov 24 11:09:02 CST 1997 `timescale 1ns / 10ps `celldefine module DFCSN1 (D, CP, CDN, SDN, Q, QN); input D, CP, CDN, SDN; output Q, QN; reg notifier; buf buf and tsmc_dff buf not and (CDN_i, CDN); (SDN_i, SDN); (CP_check, CDN_i, SDN_i); (Q_buf, D, CP, CDN_i, SDN_i, notifier); (Q, Q_buf); (QN_buf, Q_buf); (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D , posedge CP &&& CP_check , 0, notifier); $setup(negedge D , posedge CP &&& CP_check , 0, notifier); $hold(posedge CP,posedge D &&& CP_check , 0, notifier); $hold(posedge CP,negedge D &&& CP_check , 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCSNx , Mon Nov 24 11:09:02 CST 1997 `timescale 1ns / 10ps `celldefine module DFCSN2 (D, CP, CDN, SDN, Q, QN); input D, CP, CDN, SDN; output Q, QN; reg notifier; buf buf and tsmc_dff buf not and (CDN_i, CDN); (SDN_i, SDN); (CP_check, CDN_i, SDN_i); (Q_buf, D, CP, CDN_i, SDN_i, notifier); (Q, Q_buf); (QN_buf, Q_buf); (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D , posedge CP &&& CP_check , 0, notifier); $setup(negedge D , posedge CP &&& CP_check , 0, notifier); $hold(posedge CP,posedge D &&& CP_check , 0, notifier); $hold(posedge CP,negedge D &&& CP_check , 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCSNx , Mon Nov 24 11:09:02 CST 1997 `timescale 1ns / 10ps `celldefine module DFCSN3 (D, CP, CDN, SDN, Q, QN); input D, CP, CDN, SDN; output Q, QN; reg notifier; buf buf and tsmc_dff buf not and (CDN_i, CDN); (SDN_i, SDN); (CP_check, CDN_i, SDN_i); (Q_buf, D, CP, CDN_i, SDN_i, notifier); (Q, Q_buf); (QN_buf, Q_buf); (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D , posedge CP &&& CP_check , 0, notifier); $setup(negedge D , posedge CP &&& CP_check , 0, notifier); $hold(posedge CP,posedge D &&& CP_check , 0, notifier); $hold(posedge CP,negedge D &&& CP_check , 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCSNTx , Mon Nov 24 11:09:03 CST 1997 `timescale 1ns / 10ps `celldefine module DFCSNT1 (D, CP, CDN, SDN, OE, Q, Z); input D, CP, CDN, SDN, OE; output Q, Z; buf (CDN_i, CDN); buf (SDN_i, SDN); reg notifier; and (CP_check, CDN_i, SDN_i); tsmc_dff (Q_buf, D, CP, CDN_i, SDN_i, notifier); buf (Q, Q_buf); bufif1 (Z, Q_buf, OE); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (CDN => Q)=(0, 0); (CDN => Z)=(0, 0); (CP => Q)=(0, 0); (CP => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); (SDN => Q)=(0, 0); (SDN => Z)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D, posedge CP &&& CP_check, 0, notifier); $setup(negedge D, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge D &&& CP_check, 0, notifier); $hold(posedge CP ,negedge D &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFCSNTx , Mon Nov 24 11:09:03 CST 1997 `timescale 1ns / 10ps `celldefine module DFCSNT2 (D, CP, CDN, SDN, OE, Q, Z); input D, CP, CDN, SDN, OE; output Q, Z; buf (CDN_i, CDN); buf (SDN_i, SDN); reg notifier; and (CP_check, CDN_i, SDN_i); tsmc_dff (Q_buf, D, CP, CDN_i, SDN_i, notifier); buf (Q, Q_buf); bufif1 (Z, Q_buf, OE); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (CDN => Q)=(0, 0); (CDN => Z)=(0, 0); (CP => Q)=(0, 0); (CP => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); (SDN => Q)=(0, 0); (SDN => Z)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D, posedge CP &&& CP_check, 0, notifier); $setup(negedge D, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge D &&& CP_check, 0, notifier); $hold(posedge CP ,negedge D &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFFx , Mon Nov 24 11:09:01 CST 1997 `timescale 1ns / 10ps `celldefine module DFF1 (D, CP, Q, QN); input D, CP; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); tsmc_dff (Q_buf, D, CP, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); $setup(posedge D , posedge CP, 0, notifier); $setup(negedge D , posedge CP, 0, notifier); $hold(posedge CP,posedge D , 0, notifier); $hold(posedge CP,negedge D , 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFFx , Mon Nov 24 11:09:01 CST 1997 `timescale 1ns / 10ps `celldefine module DFF2 (D, CP, Q, QN); input D, CP; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); tsmc_dff (Q_buf, D, CP, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); $setup(posedge D , posedge CP, 0, notifier); $setup(negedge D , posedge CP, 0, notifier); $hold(posedge CP,posedge D , 0, notifier); $hold(posedge CP,negedge D , 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFFx , Mon Nov 24 11:09:01 CST 1997 `timescale 1ns / 10ps `celldefine module DFF3 (D, CP, Q, QN); input D, CP; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); tsmc_dff (Q_buf, D, CP, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); $setup(posedge D , posedge CP, 0, notifier); $setup(negedge D , posedge CP, 0, notifier); $hold(posedge CP,posedge D , 0, notifier); $hold(posedge CP,negedge D , 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFSNx , Mon Nov 24 11:09:02 CST 1997 `timescale 1ns / 10ps `celldefine module DFSN1 (D, CP, SDN, Q, QN); input D, CP, SDN; output Q, QN; buf (SDN_i, SDN); reg notifier; pullup (CDN); and (CP_check, CDN, SDN_i); tsmc_dff (Q_buf, D, CP, CDN, SDN_i, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D, posedge CP &&& CP_check, 0, notifier); $setup(negedge D, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge D &&& CP_check, 0, notifier); $hold(posedge CP,negedge D &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFSNx , Mon Nov 24 11:09:02 CST 1997 `timescale 1ns / 10ps `celldefine module DFSN2 (D, CP, SDN, Q, QN); input D, CP, SDN; output Q, QN; buf (SDN_i, SDN); reg notifier; pullup (CDN); and (CP_check, CDN, SDN_i); tsmc_dff (Q_buf, D, CP, CDN, SDN_i, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D, posedge CP &&& CP_check, 0, notifier); $setup(negedge D, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge D &&& CP_check, 0, notifier); $hold(posedge CP,negedge D &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFSNx , Mon Nov 24 11:09:02 CST 1997 `timescale 1ns / 10ps `celldefine module DFSN3 (D, CP, SDN, Q, QN); input D, CP, SDN; output Q, QN; buf (SDN_i, SDN); reg notifier; pullup (CDN); and (CP_check, CDN, SDN_i); tsmc_dff (Q_buf, D, CP, CDN, SDN_i, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D, posedge CP &&& CP_check, 0, notifier); $setup(negedge D, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge D &&& CP_check, 0, notifier); $hold(posedge CP,negedge D &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFSNTx , Mon Nov 24 11:09:03 CST 1997 `timescale 1ns / 10ps `celldefine module DFSNT1 (D, CP, SDN, OE, Q, Z); input D, CP, SDN, OE; output Q, Z; buf (SDN_i, SDN); reg notifier; pullup (CDN); and (CP_check, CDN, SDN_i); tsmc_dff (Q_buf, D, CP, CDN, SDN_i, notifier); buf (Q, Q_buf); bufif1 (Z, Q_buf, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (CP => Q)=(0, 0); (CP => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); (SDN => Q)=(0, 0); (SDN => Z)=(0, 0); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D, posedge CP &&& CP_check, 0, notifier); $setup(negedge D, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge D &&& CP_check, 0, notifier); $hold(posedge CP,negedge D &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFSNTx , Mon Nov 24 11:09:03 CST 1997 `timescale 1ns / 10ps `celldefine module DFSNT2 (D, CP, SDN, OE, Q, Z); input D, CP, SDN, OE; output Q, Z; buf (SDN_i, SDN); reg notifier; pullup (CDN); and (CP_check, CDN, SDN_i); tsmc_dff (Q_buf, D, CP, CDN, SDN_i, notifier); buf (Q, Q_buf); bufif1 (Z, Q_buf, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (CP => Q)=(0, 0); (CP => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); (SDN => Q)=(0, 0); (SDN => Z)=(0, 0); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge D, posedge CP &&& CP_check, 0, notifier); $setup(negedge D, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge D &&& CP_check, 0, notifier); $hold(posedge CP,negedge D &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFTx , Mon Nov 24 11:09:03 CST 1997 `timescale 1ns / 10ps `celldefine module DFT1 (D, CP, OE, Q, Z); input D, CP, OE; output Q, Z; reg notifier; pullup (CDN); pullup (SDN); tsmc_dff (Q_buf, D, CP, CDN, SDN, notifier); buf (Q, Q_buf); bufif1 (Z, Q_buf, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (CP => Q)=(0, 0); (CP => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); $setup(posedge D, posedge CP , 0, notifier); $setup(negedge D, posedge CP , 0, notifier); $hold(posedge CP ,posedge D, 0, notifier); $hold(posedge CP ,negedge D, 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFTx , Mon Nov 24 11:09:03 CST 1997 `timescale 1ns / 10ps `celldefine module DFT2 (D, CP, OE, Q, Z); input D, CP, OE; output Q, Z; reg notifier; pullup (CDN); pullup (SDN); tsmc_dff (Q_buf, D, CP, CDN, SDN, notifier); buf (Q, Q_buf); bufif1 (Z, Q_buf, OE); always @(Z) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(Z) && (Z === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (CP => Q)=(0, 0); (CP => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); $setup(posedge D, posedge CP , 0, notifier); $setup(negedge D, posedge CP , 0, notifier); $hold(posedge CP ,posedge D, 0, notifier); $hold(posedge CP ,negedge D, 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFXx , Mon Nov 24 11:09:06 CST 1997 `timescale 1ns / 10ps `celldefine module DFX1 (DA, DB, SA, CP, Q, QN); input DA, DB, SA, CP; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); not (SB, SA); and (DA_check, CDN, SDN, SA); and (DB_check, CDN, SDN, SB); tsmc_mux (D, DB, DA, SA); tsmc_dff (Q_buf, D, CP, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); $setup(posedge DA, posedge CP &&& DA_check, 0, notifier); $setup(negedge DA, posedge CP &&& DA_check, 0, notifier); $hold(posedge CP,posedge DA &&& DA_check, 0, notifier); $hold(posedge CP,negedge DA &&& DA_check, 0, notifier); $setup(posedge DB, posedge CP &&& DB_check, 0, notifier); $setup(negedge DB, posedge CP &&& DB_check, 0, notifier); $hold(posedge CP,posedge DB &&& DB_check, 0, notifier); $hold(posedge CP,negedge DB &&& DB_check, 0, notifier); $setup(posedge SA, posedge CP, 0, notifier); $setup(negedge SA, posedge CP, 0, notifier); $hold(posedge CP,posedge SA, 0, notifier); $hold(posedge CP,negedge SA, 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFXx , Mon Nov 24 11:09:06 CST 1997 `timescale 1ns / 10ps `celldefine module DFX2 (DA, DB, SA, CP, Q, QN); input DA, DB, SA, CP; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); not (SB, SA); and and tsmc_mux tsmc_dff buf not (DA_check, CDN, SDN, SA); (DB_check, CDN, SDN, SB); (D, DB, DA, SA); (Q_buf, D, CP, CDN, SDN, notifier); (Q, Q_buf); (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); $setup(posedge DA, posedge CP &&& DA_check, 0, notifier); $setup(negedge DA, posedge CP &&& DA_check, 0, notifier); $hold(posedge CP,posedge DA &&& DA_check, 0, notifier); $hold(posedge CP,negedge DA &&& DA_check, 0, notifier); $setup(posedge DB, posedge CP &&& DB_check, 0, notifier); $setup(negedge DB, posedge CP &&& DB_check, 0, notifier); $hold(posedge CP,posedge DB &&& DB_check, 0, notifier); $hold(posedge CP,negedge DB &&& DB_check, 0, notifier); $setup(posedge SA, posedge CP, 0, notifier); $setup(negedge SA, posedge CP, 0, notifier); $hold(posedge CP,posedge SA, 0, notifier); $hold(posedge CP,negedge SA, 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFXx , Mon Nov 24 11:09:06 CST 1997 `timescale 1ns / 10ps `celldefine module DFX3 (DA, DB, SA, CP, Q, QN); input DA, DB, SA, CP; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); not (SB, SA); and (DA_check, CDN, SDN, SA); and (DB_check, CDN, SDN, SB); tsmc_mux (D, DB, DA, SA); tsmc_dff (Q_buf, D, CP, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); $setup(posedge DA, posedge CP &&& DA_check, 0, notifier); $setup(negedge DA, posedge CP &&& DA_check, 0, notifier); $hold(posedge CP,posedge DA &&& DA_check, 0, notifier); $hold(posedge CP,negedge DA &&& DA_check, 0, notifier); $setup(posedge DB, posedge CP &&& DB_check, 0, notifier); $setup(negedge DB, posedge CP &&& DB_check, 0, notifier); $hold(posedge CP,posedge DB &&& DB_check, 0, notifier); $hold(posedge CP,negedge DB &&& DB_check, 0, notifier); $setup(posedge SA, posedge CP, 0, notifier); $setup(negedge SA, posedge CP, 0, notifier); $hold(posedge CP,posedge SA, 0, notifier); $hold(posedge CP,negedge SA, 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFXCNx , Mon Nov 24 11:09:06 CST 1997 `timescale 1ns / 10ps `celldefine module DFXCN1 (DA, DB, SA, CP, CDN, Q, QN); input DA, DB, SA, CP, CDN; output Q, QN; buf (CDN_i, CDN); reg notifier; pullup (SDN); not (SB, SA); and (CP_check, CDN_i, SDN); and (DA_check, CDN_i, SDN, SA); and (DB_check, CDN_i, SDN, SB); tsmc_mux (D, DB, DA, SA); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $setup(posedge DA, posedge CP &&& DA_check, 0, notifier); $setup(negedge DA, posedge CP &&& DA_check, 0, notifier); $hold(posedge CP,posedge DA &&& DA_check, 0, notifier); $hold(posedge CP,negedge DA &&& DA_check, 0, notifier); $setup(posedge DB, posedge CP &&& DB_check, 0, notifier); $setup(negedge DB, posedge CP &&& DB_check, 0, notifier); $hold(posedge CP,posedge DB &&& DB_check, 0, notifier); $hold(posedge CP,negedge DB &&& DB_check, 0, notifier); $setup(posedge SA, posedge CP &&& CP_check, 0, notifier); $setup(negedge SA, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge SA &&& CP_check, 0, notifier); $hold(posedge CP,negedge SA &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFXCNx , Mon Nov 24 11:09:06 CST 1997 `timescale 1ns / 10ps `celldefine module DFXCN2 (DA, DB, SA, CP, CDN, Q, QN); input DA, DB, SA, CP, CDN; output Q, QN; buf (CDN_i, CDN); reg notifier; pullup (SDN); not (SB, SA); and (CP_check, CDN_i, SDN); and (DA_check, CDN_i, SDN, SA); and (DB_check, CDN_i, SDN, SB); tsmc_mux (D, DB, DA, SA); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $setup(posedge DA, posedge CP &&& DA_check, 0, notifier); $setup(negedge DA, posedge CP &&& DA_check, 0, notifier); $hold(posedge CP,posedge DA &&& DA_check, 0, notifier); $hold(posedge CP,negedge DA &&& DA_check, 0, notifier); $setup(posedge DB, posedge CP &&& DB_check, 0, notifier); $setup(negedge DB, posedge CP &&& DB_check, 0, notifier); $hold(posedge CP,posedge DB &&& DB_check, 0, notifier); $hold(posedge CP,negedge DB &&& DB_check, 0, notifier); $setup(posedge SA, posedge CP &&& CP_check, 0, notifier); $setup(negedge SA, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge SA &&& CP_check, 0, notifier); $hold(posedge CP,negedge SA &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFXCSNx , Mon Nov 24 11:09:07 CST 1997 `timescale 1ns / 10ps `celldefine module DFXCSN1 (DA, DB, SA, CP, CDN, SDN, Q, QN); input DA, DB, SA, CP, CDN, SDN; output Q, QN; buf (CDN_i, CDN); buf (SDN_i, SDN); reg notifier; not (SB, SA); and (CP_check, CDN_i, SDN_i); and (DA_check, CDN_i, SDN_i, SA); and (DB_check, CDN_i, SDN_i, SB); tsmc_mux (D, DB, DA, SA); tsmc_dff (Q_buf, D, CP, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge DA, posedge CP &&& DA_check, 0, notifier); $setup(negedge DA, posedge CP &&& DA_check, 0, notifier); $hold(posedge CP,posedge DA &&& DA_check, 0, notifier); $hold(posedge CP,negedge DA &&& DA_check, 0, notifier); $setup(posedge DB, posedge CP &&& DB_check, 0, notifier); $setup(negedge DB, posedge CP &&& DB_check, 0, notifier); $hold(posedge CP,posedge DB &&& DB_check, 0, notifier); $hold(posedge CP,negedge DB &&& DB_check, 0, notifier); $setup(posedge SA, posedge CP &&& CP_check, 0, notifier); $setup(negedge SA, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge SA &&& CP_check, 0, notifier); $hold(posedge CP,negedge SA &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFXCSNx , Mon Nov 24 11:09:07 CST 1997 `timescale 1ns / 10ps `celldefine module DFXCSN2 (DA, DB, SA, CP, CDN, SDN, Q, QN); input DA, DB, SA, CP, CDN, SDN; output Q, QN; buf (CDN_i, CDN); buf (SDN_i, SDN); reg notifier; not (SB, SA); and (CP_check, CDN_i, SDN_i); and (DA_check, CDN_i, SDN_i, SA); and (DB_check, CDN_i, SDN_i, SB); tsmc_mux (D, DB, DA, SA); tsmc_dff (Q_buf, D, CP, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge DA, posedge CP &&& DA_check, 0, notifier); $setup(negedge DA, posedge CP &&& DA_check, 0, notifier); $hold(posedge CP,posedge DA &&& DA_check, 0, notifier); $hold(posedge CP,negedge DA &&& DA_check, 0, notifier); $setup(posedge DB, posedge CP &&& DB_check, 0, notifier); $setup(negedge DB, posedge CP &&& DB_check, 0, notifier); $hold(posedge CP,posedge DB &&& DB_check, 0, notifier); $hold(posedge CP,negedge DB &&& DB_check, 0, notifier); $setup(posedge SA, posedge CP &&& CP_check, 0, notifier); $setup(negedge SA, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge SA &&& CP_check, 0, notifier); $hold(posedge CP,negedge SA &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFXSNx , Mon Nov 24 11:09:06 CST 1997 `timescale 1ns / 10ps `celldefine module DFXSN1 (DA, DB, SA, CP, SDN, Q, QN); input DA, DB, SA, CP, SDN; output Q, QN; buf (SDN_i, SDN); reg notifier; pullup (CDN); not (SB, SA); and (CP_check, CDN, SDN_i); and (DA_check, CDN, SDN_i, SA); and (DB_check, CDN, SDN_i, SB); tsmc_mux (D, DB, DA, SA); tsmc_dff (Q_buf, D, CP, CDN, SDN_i, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge DA, posedge CP &&& DA_check, 0, notifier); $setup(negedge DA, posedge CP &&& DA_check, 0, notifier); $hold(posedge CP,posedge DA &&& DA_check, 0, notifier); $hold(posedge CP,negedge DA &&& DA_check, 0, notifier); $setup(posedge DB, posedge CP &&& DB_check, 0, notifier); $setup(negedge DB, posedge CP &&& DB_check, 0, notifier); $hold(posedge CP,posedge DB &&& DB_check, 0, notifier); $hold(posedge CP,negedge DB &&& DB_check, 0, notifier); $setup(posedge SA, posedge CP &&& CP_check, 0, notifier); $setup(negedge SA, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge SA &&& CP_check, 0, notifier); $hold(posedge CP,negedge SA &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: DFXSNx , Mon Nov 24 11:09:06 CST 1997 `timescale 1ns / 10ps `celldefine module DFXSN2 (DA, DB, SA, CP, SDN, Q, QN); input DA, DB, SA, CP, SDN; output Q, QN; buf (SDN_i, SDN); reg notifier; pullup not and and and tsmc_mux tsmc_dff buf not (CDN); (SB, SA); (CP_check, CDN, SDN_i); (DA_check, CDN, SDN_i, SA); (DB_check, CDN, SDN_i, SB); (D, DB, DA, SA); (Q_buf, D, CP, CDN, SDN_i, notifier); (Q, Q_buf); (QN, Q_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $setup(posedge DA, posedge CP &&& DA_check, 0, notifier); $setup(negedge DA, posedge CP &&& DA_check, 0, notifier); $hold(posedge CP,posedge DA &&& DA_check, 0, notifier); $hold(posedge CP,negedge DA &&& DA_check, 0, notifier); $setup(posedge DB, posedge CP &&& DB_check, 0, notifier); $setup(negedge DB, posedge CP &&& DB_check, 0, notifier); $hold(posedge CP,posedge DB &&& DB_check, 0, notifier); $hold(posedge CP,negedge DB &&& DB_check, 0, notifier); $setup(posedge SA, posedge CP &&& CP_check, 0, notifier); $setup(negedge SA, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP,posedge SA &&& CP_check, 0, notifier); $hold(posedge CP,negedge SA &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: FA1Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module FA1D1 (A, B, CI, S, CO); input A, B, CI; output S, CO; xor (S, A, B, CI); and (n2, A, B); and (n3, A, CI); and (n4, B, CI); or (CO, n2, n3, n4); specify (A => CO)=(0, 0); (A => S)=(0, 0); (B => CO)=(0, 0); (B => S)=(0, 0); (CI => CO)=(0, 0); (CI => S)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: FA1Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module FA1D2 (A, B, CI, S, CO); input A, B, CI; output S, CO; xor (S, A, B, CI); and (n2, A, B); and (n3, A, CI); and (n4, B, CI); or (CO, n2, n3, n4); specify (A => CO)=(0, 0); (A => S)=(0, 0); (B => CO)=(0, 0); (B => S)=(0, 0); (CI => CO)=(0, 0); (CI => S)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ICBx , Mon Nov 24 11:08:42 CST 1997 `timescale 1ns / 10ps `celldefine module ICB0 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ICBx , Mon Nov 24 11:08:42 CST 1997 `timescale 1ns / 10ps `celldefine module ICB1 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ICBx , Mon Nov 24 11:08:42 CST 1997 `timescale 1ns / 10ps `celldefine module ICB2 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ICBSx , Mon Nov 24 11:08:43 CST 1997 `timescale 1ns / 10ps `celldefine module ICBS0 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ICBSx , Mon Nov 24 11:08:43 CST 1997 `timescale 1ns / 10ps `celldefine module ICBS1 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ICBSx , Mon Nov 24 11:08:43 CST 1997 `timescale 1ns / 10ps `celldefine module ICBS2 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: IND2Dx , Mon Nov 24 11:08:55 CST 1997 `timescale 1ns / 10ps `celldefine module IND2D0 (A1, B1, ZN); input A1, B1; output ZN; not nand (A1N, A1); (ZN, A1N, B1); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: IND2Dx , Mon Nov 24 11:08:55 CST 1997 `timescale 1ns / 10ps `celldefine module IND2D1 (A1, B1, ZN); input A1, B1; output ZN; not nand (A1N, A1); (ZN, A1N, B1); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: IND2Dx , Mon Nov 24 11:08:55 CST 1997 `timescale 1ns / 10ps `celldefine module IND2D2 (A1, B1, ZN); input A1, B1; output ZN; not nand (A1N, A1); (ZN, A1N, B1); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: IND2Dx , Mon Nov 24 11:08:55 CST 1997 `timescale 1ns / 10ps `celldefine module IND2D3 (A1, B1, ZN); input A1, B1; output ZN; not nand (A1N, A1); (ZN, A1N, B1); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: IND3Dx , Mon Nov 24 11:08:55 CST 1997 `timescale 1ns / 10ps `celldefine module IND3D0 (A1, B1, B2, ZN); input A1, B1, B2; output ZN; not nand (A1N, A1); (ZN, A1N, B1, B2); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: IND3Dx , Mon Nov 24 11:08:55 CST 1997 `timescale 1ns / 10ps `celldefine module IND3D1 (A1, B1, B2, ZN); input A1, B1, B2; output ZN; not (A1N, A1); nand (ZN, A1N, B1, B2); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: IND3Dx , Mon Nov 24 11:08:55 CST 1997 `timescale 1ns / 10ps `celldefine module IND3D2 (A1, B1, B2, ZN); input A1, B1, B2; output ZN; not nand (A1N, A1); (ZN, A1N, B1, B2); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: IND3Dx , Mon Nov 24 11:08:55 CST 1997 `timescale 1ns / 10ps `celldefine module IND3D3 (A1, B1, B2, ZN); input A1, B1, B2; output ZN; not nand (A1N, A1); (ZN, A1N, B1, B2); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INR2Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module INR2D0 (A1, B1, ZN); input A1, B1; output ZN; not (A1N, A1); nor (ZN, A1N, B1); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INR2Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module INR2D1 (A1, B1, ZN); input A1, B1; output ZN; not (A1N, A1); nor (ZN, A1N, B1); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INR2Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module INR2D2 (A1, B1, ZN); input A1, B1; output ZN; not (A1N, A1); nor (ZN, A1N, B1); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INR2Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module INR2D3 (A1, B1, ZN); input A1, B1; output ZN; not (A1N, A1); nor (ZN, A1N, B1); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INR3Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module INR3D0 (A1, B1, B2, ZN); input A1, B1, B2; output ZN; not (A1N, A1); nor (ZN, A1N, B1, B2); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INR3Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module INR3D1 (A1, B1, B2, ZN); input A1, B1, B2; output ZN; not (A1N, A1); nor (ZN, A1N, B1, B2); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INR3Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module INR3D2 (A1, B1, B2, ZN); input A1, B1, B2; output ZN; not (A1N, A1); nor (ZN, A1N, B1, B2); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INR3Dx , Mon Nov 24 11:08:56 CST 1997 `timescale 1ns / 10ps `celldefine module INR3D3 (A1, B1, B2, ZN); input A1, B1, B2; output ZN; not (A1N, A1); nor (ZN, A1N, B1, B2); specify (A1 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INV0 (I, ZN); input I; output ZN; not (ZN, I); specify (I => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INV1 (I, ZN); input I; output ZN; not (ZN, I); specify (I => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INV2 (I, ZN); input I; output ZN; not (ZN, I); specify (I => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INV3 (I, ZN); input I; output ZN; not (ZN, I); specify (I => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INV4 (I, ZN); input I; output ZN; not (ZN, I); specify (I => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INV5 (I, ZN); input I; output ZN; not (ZN, I); specify (I => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INV6 (I, ZN); input I; output ZN; not (ZN, I); specify (I => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INVT0 (I, OE, ZN); input I, OE; output ZN; notif1 (ZN, I, OE); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OE => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INVT1 (I, OE, ZN); input I, OE; output ZN; notif1 (ZN, I, OE); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OE => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTx , Mon Nov 24 11:08:40 CST 1997 `timescale 1ns / 10ps `celldefine module INVT2 (I, OE, ZN); input I, OE; output ZN; notif1 (ZN, I, OE); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OE => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTx , Mon Nov 24 11:08:41 CST 1997 `timescale 1ns / 10ps `celldefine module INVT3 (I, OE, ZN); input I, OE; output ZN; notif1 (ZN, I, OE); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OE => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTx , Mon Nov 24 11:08:41 CST 1997 `timescale 1ns / 10ps `celldefine module INVT4 (I, OE, ZN); input I, OE; output ZN; notif1 (ZN, I, OE); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OE => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTx , Mon Nov 24 11:08:41 CST 1997 `timescale 1ns / 10ps `celldefine module INVT5 (I, OE, ZN); input I, OE; output ZN; notif1 (ZN, I, OE); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OE => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTNx , Mon Nov 24 11:08:41 CST 1997 `timescale 1ns / 10ps `celldefine module INVTN1 (I, OEN, ZN); input I, OEN; output ZN; notif0 (ZN, I, OEN); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OEN => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTNx , Mon Nov 24 11:08:41 CST 1997 `timescale 1ns / 10ps `celldefine module INVTN2 (I, OEN, ZN); input I, OEN; output ZN; notif0 (ZN, I, OEN); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OEN => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTNx , Mon Nov 24 11:08:41 CST 1997 `timescale 1ns / 10ps `celldefine module INVTN3 (I, OEN, ZN); input I, OEN; output ZN; notif0 (ZN, I, OEN); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OEN => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTNx , Mon Nov 24 11:08:41 CST 1997 `timescale 1ns / 10ps `celldefine module INVTN4 (I, OEN, ZN); input I, OEN; output ZN; notif0 (ZN, I, OEN); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OEN => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: INVTNx , Mon Nov 24 11:08:41 CST 1997 `timescale 1ns / 10ps `celldefine module INVTN5 (I, OEN, ZN); input I, OEN; output ZN; notif0 (ZN, I, OEN); always @(ZN) begin if (!$test$plusargs("bus_conflict_off")) if ($countdrivers(ZN) && (ZN === 1'bx)) $display("%t ++BUS CONFLICT++ : %m", $realtime); end specify (I => ZN)=(0, 0); (OEN => ZN)=(0, 0, 0, 0, 0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ITBx , Mon Nov 24 11:08:43 CST 1997 `timescale 1ns / 10ps `celldefine module ITB0 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ITBx , Mon Nov 24 11:08:43 CST 1997 `timescale 1ns / 10ps `celldefine module ITB1 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ITBx , Mon Nov 24 11:08:43 CST 1997 `timescale 1ns / 10ps `celldefine module ITB2 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ITBSx , Mon Nov 24 11:08:43 CST 1997 `timescale 1ns / 10ps `celldefine module ITBS0 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ITBSx , Mon Nov 24 11:08:43 CST 1997 `timescale 1ns / 10ps `celldefine module ITBS1 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ITBSx , Mon Nov 24 11:08:43 CST 1997 `timescale 1ns / 10ps `celldefine module ITBS2 (C, CZ); input C; output CZ; buf (CZ, C); specify (C => CZ)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: JKFx , Mon Nov 24 11:09:04 CST 1997 `timescale 1ns / 10ps `celldefine module JKF1 (J, K, CP, Q, QN); input J, K, CP; output Q, QN; reg notifier; pullup pullup nand or not nand and tsmc_dff (CDN); (SDN); (KQ, K, Q_buf); (JQ, J, Q_buf); (JN, J); (JNK, JN, K); (D, JNK, JQ, KQ); (Q_buf, D, CP, CDN, SDN, notifier); not (QN_buf, Q_buf); buf (Q, Q_buf); buf (QN, QN_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); $setup(posedge J, posedge CP , 0, notifier); $setup(negedge J, posedge CP , 0, notifier); $hold(posedge CP ,posedge J, 0, notifier); $hold(posedge CP ,negedge J, 0, notifier); $setup(posedge K, posedge CP , 0, notifier); $setup(negedge K, posedge CP , 0, notifier); $hold(posedge CP,posedge K, 0, notifier); $hold(posedge CP,negedge K, 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: JKFx , Mon Nov 24 11:09:04 CST 1997 `timescale 1ns / 10ps `celldefine module JKF2 (J, K, CP, Q, QN); input J, K, CP; output Q, QN; reg notifier; pullup pullup nand or not nand and tsmc_dff not buf buf (CDN); (SDN); (KQ, K, Q_buf); (JQ, J, Q_buf); (JN, J); (JNK, JN, K); (D, JNK, JQ, KQ); (Q_buf, D, CP, CDN, SDN, notifier); (QN_buf, Q_buf); (Q, Q_buf); (QN, QN_buf); specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); $setup(posedge J, posedge CP , 0, notifier); $setup(negedge J, posedge CP , 0, notifier); $hold(posedge CP ,posedge J, 0, notifier); $hold(posedge CP ,negedge J, 0, notifier); $setup(posedge K, posedge CP , 0, notifier); $setup(negedge K, posedge CP , 0, notifier); $hold(posedge CP,posedge K, 0, notifier); $hold(posedge CP,negedge K, 0, notifier); $width(posedge CP, 0, 0, notifier); $width(negedge CP, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: JKFCNx , Mon Nov 24 11:09:04 CST 1997 `timescale 1ns / 10ps `celldefine module JKFCN1 (J, K, CP, CDN, Q, QN); input J, K, CP, CDN; output Q, QN; reg notifier; buf (CDN_i, CDN); pullup (SDN); and (CP_check, CDN_i, SDN); nand (KQ, K, Q_buf); or (JQ, J, Q_buf); not (JN, J); nand (JNK, JN, K); and (D, JNK, JQ, KQ); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); not (QN_buf, Q_buf); buf (Q, Q_buf); buf (QN, QN_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $setup(posedge J, posedge CP &&& CP_check, 0, notifier); $setup(negedge J, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge J &&& CP_check, 0, notifier); $hold(posedge CP ,negedge J &&& CP_check, 0, notifier); $setup(posedge K, posedge CP &&& CP_check, 0, notifier); $setup(negedge K, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge K &&& CP_check, 0, notifier); $hold(posedge CP ,negedge K &&& CP_check, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: JKFCNx , Mon Nov 24 11:09:04 CST 1997 `timescale 1ns / 10ps `celldefine module JKFCN2 (J, K, CP, CDN, Q, QN); input J, K, CP, CDN; output Q, QN; reg notifier; buf (CDN_i, CDN); pullup (SDN); and (CP_check, CDN_i, SDN); nand (KQ, K, Q_buf); or (JQ, J, Q_buf); not (JN, J); nand and tsmc_dff not buf buf (JNK, JN, K); (D, JNK, JQ, KQ); (Q_buf, D, CP, CDN_i, SDN, notifier); (QN_buf, Q_buf); (Q, Q_buf); (QN, QN_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $setup(posedge J, posedge CP &&& CP_check, 0, notifier); $setup(negedge J, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge J &&& CP_check, 0, notifier); $hold(posedge CP ,negedge J &&& CP_check, 0, notifier); $setup(posedge K, posedge CP &&& CP_check, 0, notifier); $setup(negedge K, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge K &&& CP_check, 0, notifier); $hold(posedge CP ,negedge K &&& CP_check, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: JKFCSNx , Mon Nov 24 11:09:04 CST 1997 `timescale 1ns / 10ps `celldefine module JKFCSN1 (J, K, CP, CDN, SDN, Q, QN); input J, K, CP, CDN, SDN; output Q, QN; reg notifier; buf (CDN_i, CDN); buf (SDN_i, SDN); and (CP_check, CDN_i, SDN_i); nand (KQ, K, Q_buf); or (JQ, J, Q_buf); not (JN, J); nand (JNK, JN, K); and (D, JNK, JQ, KQ); tsmc_dff (Q_buf, D, CP, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $setup(posedge J, posedge CP &&& CP_check, 0, notifier); $setup(negedge J, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge J &&& CP_check, 0, notifier); $hold(posedge CP ,negedge J &&& CP_check, 0, notifier); $setup(posedge K, posedge CP &&& CP_check, 0, notifier); $setup(negedge K, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge K &&& CP_check, 0, notifier); $hold(posedge CP ,negedge K &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: JKFCSNx , Mon Nov 24 11:09:04 CST 1997 `timescale 1ns / 10ps `celldefine module JKFCSN2 (J, K, CP, CDN, SDN, Q, QN); input J, K, CP, CDN, SDN; output Q, QN; reg notifier; buf (CDN_i, CDN); buf (SDN_i, SDN); and (CP_check, CDN_i, SDN_i); nand (KQ, K, Q_buf); or (JQ, J, Q_buf); not (JN, J); nand (JNK, JN, K); and (D, JNK, JQ, KQ); tsmc_dff (Q_buf, D, CP, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $setup(posedge J, posedge CP &&& CP_check, 0, notifier); $setup(negedge J, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge J &&& CP_check, 0, notifier); $hold(posedge CP ,negedge J &&& CP_check, 0, notifier); $setup(posedge K, posedge CP &&& CP_check, 0, notifier); $setup(negedge K, posedge CP &&& CP_check, 0, notifier); $hold(posedge CP ,posedge K &&& CP_check, 0, notifier); $hold(posedge CP ,negedge K &&& CP_check, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LHx , Mon Nov 24 11:09:07 CST 1997 `timescale 1ns / 10ps `celldefine module LH1 (D, E, Q, QN); input D, E; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); tsmc_dla (Q_buf, D, E, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (D => Q)=(0, 0); (D => QN)=(0, 0); (E => Q)=(0, 0); (E => QN)=(0, 0); $setup(posedge D, negedge E , 0, notifier); $setup(negedge D, negedge E , 0, notifier); $hold(negedge E ,posedge D, 0, notifier); $hold(negedge E ,negedge D, 0, notifier); $width(posedge E, 0, 0, notifier); $width(negedge E, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LHx , Mon Nov 24 11:09:07 CST 1997 `timescale 1ns / 10ps `celldefine module LH2 (D, E, Q, QN); input D, E; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); tsmc_dla (Q_buf, D, E, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (D => Q)=(0, 0); (D => QN)=(0, 0); (E => Q)=(0, 0); (E => QN)=(0, 0); $setup(posedge D, negedge E , 0, notifier); $setup(negedge D, negedge E , 0, notifier); $hold(negedge E ,posedge D, 0, notifier); $hold(negedge E ,negedge D, 0, notifier); $width(posedge E, 0, 0, notifier); $width(negedge E, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LHCNx , Mon Nov 24 11:09:07 CST 1997 `timescale 1ns / 10ps `celldefine module LHCN1 (D, E, CDN, Q, QN); input D, E, CDN; output Q, QN; buf (CDN_i, CDN); reg notifier; pullup (SDN); and (E_check, CDN_i, SDN); tsmc_dla (Q_buf, D, E, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (D => Q)=(0, 0); (D => QN)=(0, 0); (E => Q)=(0, 0); (E => QN)=(0, 0); $recovery(posedge CDN, negedge E, 0, notifier); $hold(negedge E , posedge CDN, 0, notifier); $setup(posedge D, negedge E &&& E_check, 0, notifier); $setup(negedge D, negedge E &&& E_check, 0, notifier); $hold(negedge E ,posedge D &&& E_check, 0, notifier); $hold(negedge E ,negedge D &&& E_check, 0, notifier); $width(posedge E &&& E_check, 0, 0, notifier); $width(negedge E &&& E_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LHCNx , Mon Nov 24 11:09:07 CST 1997 `timescale 1ns / 10ps `celldefine module LHCN2 (D, E, CDN, Q, QN); input D, E, CDN; output Q, QN; buf (CDN_i, CDN); reg notifier; pullup (SDN); and (E_check, CDN_i, SDN); tsmc_dla (Q_buf, D, E, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (D => Q)=(0, 0); (D => QN)=(0, 0); (E => Q)=(0, 0); (E => QN)=(0, 0); $recovery(posedge CDN, negedge E, 0, notifier); $hold(negedge E , posedge CDN, 0, notifier); $setup(posedge D, negedge E &&& E_check, 0, notifier); $setup(negedge D, negedge E &&& E_check, 0, notifier); $hold(negedge E ,posedge D &&& E_check, 0, notifier); $hold(negedge E ,negedge D &&& E_check, 0, notifier); $width(posedge E &&& E_check, 0, 0, notifier); $width(negedge E &&& E_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LHCNx , Mon Nov 24 11:09:07 CST 1997 `timescale 1ns / 10ps `celldefine module LHCN3 (D, E, CDN, Q, QN); input D, E, CDN; output Q, QN; buf (CDN_i, CDN); reg notifier; pullup (SDN); and (E_check, CDN_i, SDN); tsmc_dla (Q_buf, D, E, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (D => Q)=(0, 0); (D => QN)=(0, 0); (E => Q)=(0, 0); (E => QN)=(0, 0); $recovery(posedge CDN, negedge E, 0, notifier); $hold(negedge E , posedge CDN, 0, notifier); $setup(posedge D, negedge E &&& E_check, 0, notifier); $setup(negedge D, negedge E &&& E_check, 0, notifier); $hold(negedge E ,posedge D &&& E_check, 0, notifier); $hold(negedge E ,negedge D &&& E_check, 0, notifier); $width(posedge E &&& E_check, 0, 0, notifier); $width(negedge E &&& E_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LHTx , Mon Nov 24 11:09:10 CST 1997 `timescale 1ns / 10ps `celldefine module LHT1 (D, E, OE, Z); input D, E, OE; output Z; reg notifier; pullup (CDN); pullup (SDN); tsmc_dla (Q_buf, D, E, CDN, SDN, notifier); bufif1 (Z, Q_buf, OE); specify (D => Z)=(0, 0); (E => Z)=(0, 0); (OE => Z)=(0, 0, 0, 0, 0, 0); $setup(posedge D, negedge E, 0, notifier); $setup(negedge D, negedge E, 0, notifier); $hold(negedge E ,posedge D, 0, notifier); $hold(negedge E ,negedge D, 0, notifier); $width(posedge E, 0, 0, notifier); $width(negedge E, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LNx , Mon Nov 24 11:09:08 CST 1997 `timescale 1ns / 10ps `celldefine module LN1 (D, EN, Q, QN); input D, EN; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); not (E, EN); tsmc_dla (Q_buf, D, E, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (D => Q)=(0, 0); (D => QN)=(0, 0); (EN => Q)=(0, 0); (EN => QN)=(0, 0); $setup(posedge D, posedge EN , 0, notifier); $setup(negedge D, posedge EN , 0, notifier); $hold(posedge EN ,posedge D, 0, notifier); $hold(posedge EN ,negedge D, 0, notifier); $width(posedge EN, 0, 0, notifier); $width(negedge EN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LNx , Mon Nov 24 11:09:09 CST 1997 `timescale 1ns / 10ps `celldefine module LN2 (D, EN, Q, QN); input D, EN; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); not (E, EN); tsmc_dla (Q_buf, D, E, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (D => Q)=(0, 0); (D => QN)=(0, 0); (EN => Q)=(0, 0); (EN => QN)=(0, 0); $setup(posedge D, posedge EN , 0, notifier); $setup(negedge D, posedge EN , 0, notifier); $hold(posedge EN ,posedge D, 0, notifier); $hold(posedge EN ,negedge D, 0, notifier); $width(posedge EN, 0, 0, notifier); $width(negedge EN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LNx , Mon Nov 24 11:09:09 CST 1997 `timescale 1ns / 10ps `celldefine module LN3 (D, EN, Q, QN); input D, EN; output Q, QN; reg notifier; pullup (CDN); pullup (SDN); not (E, EN); tsmc_dla (Q_buf, D, E, CDN, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (D => Q)=(0, 0); (D => QN)=(0, 0); (EN => Q)=(0, 0); (EN => QN)=(0, 0); $setup(posedge D, posedge EN , 0, notifier); $setup(negedge D, posedge EN , 0, notifier); $hold(posedge EN ,posedge D, 0, notifier); $hold(posedge EN ,negedge D, 0, notifier); $width(posedge EN, 0, 0, notifier); $width(negedge EN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LNCNx , Mon Nov 24 11:09:09 CST 1997 `timescale 1ns / 10ps `celldefine module LNCN1 (D, EN, CDN, Q, QN); input D, EN, CDN; output Q, QN; reg notifier; buf (CDN_i, CDN); pullup (SDN); and (EN_check, CDN_i, SDN); not (E, EN); tsmc_dla (Q_buf, D, E, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (D => Q)=(0, 0); (D => QN)=(0, 0); (EN => Q)=(0, 0); (EN => QN)=(0, 0); $recovery(posedge CDN, posedge EN, 0, notifier); $hold(posedge EN , posedge CDN, 0, notifier); $setup(posedge D, posedge EN &&& EN_check, 0, notifier); $setup(negedge D, posedge EN &&& EN_check, 0, notifier); $hold(posedge EN,posedge D &&& EN_check, 0, notifier); $hold(posedge EN,negedge D &&& EN_check, 0, notifier); $width(posedge EN &&& EN_check, 0, 0, notifier); $width(negedge EN &&& EN_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LNCNx , Mon Nov 24 11:09:09 CST 1997 `timescale 1ns / 10ps `celldefine module LNCN2 (D, EN, CDN, Q, QN); input D, EN, CDN; output Q, QN; reg notifier; buf (CDN_i, CDN); pullup (SDN); and (EN_check, CDN_i, SDN); not (E, EN); tsmc_dla (Q_buf, D, E, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (D => Q)=(0, 0); (D => QN)=(0, 0); (EN => Q)=(0, 0); (EN => QN)=(0, 0); $recovery(posedge CDN, posedge EN, 0, notifier); $hold(posedge EN , posedge CDN, 0, notifier); $setup(posedge D, posedge EN &&& EN_check, 0, notifier); $setup(negedge D, posedge EN &&& EN_check, 0, notifier); $hold(posedge EN,posedge D &&& EN_check, 0, notifier); $hold(posedge EN,negedge D &&& EN_check, 0, notifier); $width(posedge EN &&& EN_check, 0, 0, notifier); $width(negedge EN &&& EN_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LNCNx , Mon Nov 24 11:09:09 CST 1997 `timescale 1ns / 10ps `celldefine module LNCN3 (D, EN, CDN, Q, QN); input D, EN, CDN; output Q, QN; reg notifier; buf (CDN_i, CDN); pullup (SDN); and (EN_check, CDN_i, SDN); not (E, EN); tsmc_dla (Q_buf, D, E, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN, Q_buf); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (D => Q)=(0, 0); (D => QN)=(0, 0); (EN => Q)=(0, 0); (EN => QN)=(0, 0); $recovery(posedge CDN, posedge EN, 0, notifier); $hold(posedge EN , posedge CDN, 0, notifier); $setup(posedge D, posedge EN &&& EN_check, 0, notifier); $setup(negedge D, posedge EN &&& EN_check, 0, notifier); $hold(posedge EN,posedge D &&& EN_check, 0, notifier); $hold(posedge EN,negedge D &&& EN_check, 0, notifier); $width(posedge EN &&& EN_check, 0, 0, notifier); $width(negedge EN &&& EN_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LNCSNx , Mon Nov 24 11:09:10 CST 1997 `timescale 1ns / 10ps `celldefine module LNCSN1 (D, EN, CDN, SDN, Q, QN); input D, EN, CDN, SDN; output Q, QN; reg notifier; buf (CDN_i, CDN); buf (SDN_i, SDN); and (EN_check, CDN_i, SDN_i); not (E, EN); tsmc_dla(Q_buf, D, E, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (D => Q)=(0, 0); (D => QN)=(0, 0); (EN => Q)=(0, 0); (EN => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge EN, 0, notifier); $hold(posedge EN , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge EN, 0, notifier); $hold(posedge EN , posedge SDN, 0, notifier); $setup(posedge D, posedge EN &&& EN_check , 0, notifier); $setup(negedge D, posedge EN &&& EN_check , 0, notifier); $hold(posedge EN,posedge D &&& EN_check, 0, notifier); $hold(posedge EN,negedge D &&& EN_check, 0, notifier); $width(posedge EN &&& EN_check, 0, 0, notifier); $width(negedge EN &&& EN_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LNCSNx , Mon Nov 24 11:09:10 CST 1997 `timescale 1ns / 10ps `celldefine module LNCSN2 (D, EN, CDN, SDN, Q, QN); input D, EN, CDN, SDN; output Q, QN; reg notifier; buf (CDN_i, CDN); buf (SDN_i, SDN); and (EN_check, CDN_i, SDN_i); not (E, EN); tsmc_dla(Q_buf, D, E, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (D => Q)=(0, 0); (D => QN)=(0, 0); (EN => Q)=(0, 0); (EN => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge EN, 0, notifier); $hold(posedge EN , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge EN, 0, notifier); $hold(posedge EN , posedge SDN, 0, notifier); $setup(posedge D, posedge EN &&& EN_check , 0, notifier); $setup(negedge D, posedge EN &&& EN_check , 0, notifier); $hold(posedge EN,posedge D &&& EN_check, 0, notifier); $hold(posedge EN,negedge D &&& EN_check, 0, notifier); $width(posedge EN &&& EN_check, 0, 0, notifier); $width(negedge EN &&& EN_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: LNCSNx , Mon Nov 24 11:09:10 CST 1997 `timescale 1ns / 10ps `celldefine module LNCSN3 (D, EN, CDN, SDN, Q, QN); input D, EN, CDN, SDN; output Q, QN; reg notifier; buf (CDN_i, CDN); buf (SDN_i, SDN); and (EN_check, CDN_i, SDN_i); not (E, EN); tsmc_dla(Q_buf, D, E, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (D => Q)=(0, 0); (D => QN)=(0, 0); (EN => Q)=(0, 0); (EN => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge EN, 0, notifier); $hold(posedge EN , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge EN, 0, notifier); $hold(posedge EN , posedge SDN, 0, notifier); $setup(posedge D, posedge EN &&& EN_check , 0, notifier); $setup(negedge D, posedge EN &&& EN_check , 0, notifier); $hold(posedge EN,posedge D &&& EN_check, 0, notifier); $hold(posedge EN,negedge D &&& EN_check, 0, notifier); $width(posedge EN &&& EN_check, 0, 0, notifier); $width(negedge EN &&& EN_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MAOI222Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module MAOI222D0 (A, B, C, ZN); input A, B, C; output ZN; and (AB, A, B); and (AC, A, C); and (BC, B, C); nor (ZN, AB, AC, BC); specify (A => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MAOI222Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module MAOI222D1 (A, B, C, ZN); input A, B, C; output ZN; and (AB, A, B); and (AC, A, C); and (BC, B, C); nor (ZN, AB, AC, BC); specify (A => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MAOI222Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module MAOI222D2 (A, B, C, ZN); input A, B, C; output ZN; and (AB, A, B); and (AC, A, C); and (BC, B, C); nor (ZN, AB, AC, BC); specify (A => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MAOI22Dx , Mon Nov 24 11:09:28 CST 1997 `timescale 1ns / 10ps `celldefine module MAOI22D0 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; and (A, A1, A2); nor (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MAOI22Dx , Mon Nov 24 11:09:28 CST 1997 `timescale 1ns / 10ps `celldefine module MAOI22D1 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; and (A, A1, A2); nor (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MAOI22Dx , Mon Nov 24 11:09:28 CST 1997 `timescale 1ns / 10ps `celldefine module MAOI22D2 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; and (A, A1, A2); nor (B, B1, B2); nor (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MOAI22Dx , Mon Nov 24 11:09:28 CST 1997 `timescale 1ns / 10ps `celldefine module MOAI22D0 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; or nand nand (A, A1, A2); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MOAI22Dx , Mon Nov 24 11:09:28 CST 1997 `timescale 1ns / 10ps `celldefine module MOAI22D1 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; or nand nand (A, A1, A2); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MOAI22Dx , Mon Nov 24 11:09:28 CST 1997 `timescale 1ns / 10ps `celldefine module MOAI22D2 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; or nand nand (A, A1, A2); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MUX2Dx , Wed Sep 23 08:57:35 CST 1998 `timescale 1ns / 10ps `celldefine module MUX2D1 (I0, I1, S, Z); input I0, I1, S; output Z; tsmc_mux (Z_buf, I0, I1, S); buf (Z, Z_buf); specify (I0 => Z)=(0, 0); (I1 => Z)=(0, 0); (S => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MUX2Dx , Wed Sep 23 08:57:35 CST 1998 `timescale 1ns / 10ps `celldefine module MUX2D2 (I0, I1, S, Z); input I0, I1, S; output Z; tsmc_mux (Z_buf, I0, I1, S); buf (Z, Z_buf); specify (I0 => Z)=(0, 0); (I1 => Z)=(0, 0); (S => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MUX4Dx , Wed Sep 23 08:57:35 CST 1998 `timescale 1ns / 10ps `celldefine module MUX4D1 (I0, I1, I2, I3, S0, S1, Z); input I0, I1, I2, I3, S0, S1; output Z; tsmc_mux (Z0, I0, I1, S0); tsmc_mux (Z1, I2, I3, S0); tsmc_mux (Z_buf, Z0, Z1, S1); buf (Z, Z_buf); specify (I0 => Z)=(0, 0); (I1 => Z)=(0, 0); (I2 => Z)=(0, 0); (I3 => Z)=(0, 0); (S0 => Z)=(0, 0); (S1 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MUX4Dx , Wed Sep 23 08:57:35 CST 1998 `timescale 1ns / 10ps `celldefine module MUX4D2 (I0, I1, I2, I3, S0, S1, Z); input I0, I1, I2, I3, S0, S1; output Z; tsmc_mux (Z0, I0, I1, S0); tsmc_mux (Z1, I2, I3, S0); tsmc_mux (Z_buf, Z0, Z1, S1); buf (Z, Z_buf); specify (I0 => Z)=(0, 0); (I1 => Z)=(0, 0); (I2 => Z)=(0, 0); (I3 => Z)=(0, 0); (S0 => Z)=(0, 0); (S1 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MUX8Dx , Wed Sep 23 08:57:35 CST 1998 `timescale 1ns / 10ps `celldefine module MUX8D1 (I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, Z); input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2; output Z; tsmc_mux (Z0, I0, I1, S0); tsmc_mux (Z1, I2, I3, S0); tsmc_mux (Z2, I4, I5, S0); tsmc_mux (Z3, I6, I7, S0); tsmc_mux (ZZ0, Z0, Z1, S1); tsmc_mux (ZZ1, Z2, Z3, S1); tsmc_mux (Z_buf, ZZ0, ZZ1, S2); buf (Z, Z_buf); specify (I0 => Z)=(0, 0); (I1 => Z)=(0, 0); (I2 => Z)=(0, 0); (I3 => Z)=(0, 0); (I4 => Z)=(0, 0); (I5 => Z)=(0, 0); (I6 => Z)=(0, 0); (I7 => Z)=(0, 0); (S0 => Z)=(0, 0); (S1 => Z)=(0, 0); (S2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MUX8Dx , Wed Sep 23 08:57:35 CST 1998 `timescale 1ns / 10ps `celldefine module MUX8D2 (I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, Z); input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2; output Z; tsmc_mux (Z0, I0, I1, S0); tsmc_mux (Z1, I2, I3, S0); tsmc_mux (Z2, I4, I5, S0); tsmc_mux (Z3, I6, I7, S0); tsmc_mux (ZZ0, Z0, Z1, S1); tsmc_mux (ZZ1, Z2, Z3, S1); tsmc_mux (Z_buf, ZZ0, ZZ1, S2); buf (Z, Z_buf); specify (I0 => Z)=(0, 0); (I1 => Z)=(0, 0); (I2 => Z)=(0, 0); (I3 => Z)=(0, 0); (I4 => Z)=(0, 0); (I5 => Z)=(0, 0); (I6 => Z)=(0, 0); (I7 => Z)=(0, 0); (S0 => Z)=(0, 0); (S1 => Z)=(0, 0); (S2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: MUXN4Dx , Wed Sep 23 08:57:35 CST 1998 `timescale 1ns / 10ps `celldefine module MUXN4D1 (I0, I1, I2, I3, S0, S1, EN, Z); input I0, I1, I2, I3, S0, S1, EN; output Z; not (ENB, EN); tsmc_mux (Z0, I0, I1, S0); tsmc_mux (Z1, I2, I3, S0); tsmc_mux (Z_buf, Z0, Z1, S1); and (Z, Z_buf, ENB); specify (I0 => Z)=(0, 0); (I1 => Z)=(0, 0); (I2 => Z)=(0, 0); (I3 => Z)=(0, 0); (S0 => Z)=(0, 0); (S1 => Z)=(0, 0); (EN => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND2Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND2D0 (A1, A2, ZN); input A1, A2; output ZN; nand (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND2Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND2D1 (A1, A2, ZN); input A1, A2; output ZN; nand (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND2Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND2D1H (A1, A2, ZN); input A1, A2; output ZN; nand (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND2Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND2D2 (A1, A2, ZN); input A1, A2; output ZN; nand (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND2Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND2D3 (A1, A2, ZN); input A1, A2; output ZN; nand (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND3Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND3D0 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nand (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND3Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND3D1 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nand (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND3Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND3D1H (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nand (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND3Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND3D2 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nand (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND3Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND3D3 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nand (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND4Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND4D0 (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nand (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND4Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND4D1 (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nand (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND4Dx , Mon Nov 24 11:08:47 CST 1997 `timescale 1ns / 10ps `celldefine module ND4D1H (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nand (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND4Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND4D2 (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nand (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND4Dx , Mon Nov 24 11:08:46 CST 1997 `timescale 1ns / 10ps `celldefine module ND4D3 (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nand (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND5Dx , Mon Nov 24 11:08:47 CST 1997 `timescale 1ns / 10ps `celldefine module ND5D1 (A1, A2, A3, A4, A5, ZN); input A1, A2, A3, A4, A5; output ZN; nand (ZN, A1, A2, A3, A4, A5); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND5Dx , Mon Nov 24 11:08:47 CST 1997 `timescale 1ns / 10ps `celldefine module ND5D2 (A1, A2, A3, A4, A5, ZN); input A1, A2, A3, A4, A5; output ZN; nand (ZN, A1, A2, A3, A4, A5); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND5Dx , Mon Nov 24 11:08:47 CST 1997 `timescale 1ns / 10ps `celldefine module ND5D3 (A1, A2, A3, A4, A5, ZN); input A1, A2, A3, A4, A5; output ZN; nand (ZN, A1, A2, A3, A4, A5); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND6Dx , Mon Nov 24 11:08:47 CST 1997 `timescale 1ns / 10ps `celldefine module ND6D1 (A1, A2, A3, A4, A5, A6, ZN); input A1, A2, A3, A4, A5, A6; output ZN; nand (ZN, A1, A2, A3, A4, A5, A6); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND6Dx , Mon Nov 24 11:08:47 CST 1997 `timescale 1ns / 10ps `celldefine module ND6D2 (A1, A2, A3, A4, A5, A6, ZN); input A1, A2, A3, A4, A5, A6; output ZN; nand (ZN, A1, A2, A3, A4, A5, A6); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND6Dx , Mon Nov 24 11:08:47 CST 1997 `timescale 1ns / 10ps `celldefine module ND6D3 (A1, A2, A3, A4, A5, A6, ZN); input A1, A2, A3, A4, A5, A6; output ZN; nand (ZN, A1, A2, A3, A4, A5, A6); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND7Dx , Mon Nov 24 11:08:47 CST 1997 `timescale 1ns / 10ps `celldefine module ND7D1 (A1, A2, A3, A4, A5, A6, A7, ZN); input A1, A2, A3, A4, A5, A6, A7; output ZN; nand (ZN, A1, A2, A3, A4, A5, A6, A7); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND7Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module ND7D2 (A1, A2, A3, A4, A5, A6, A7, ZN); input A1, A2, A3, A4, A5, A6, A7; output ZN; nand (ZN, A1, A2, A3, A4, A5, A6, A7); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND7Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module ND7D3 (A1, A2, A3, A4, A5, A6, A7, ZN); input A1, A2, A3, A4, A5, A6, A7; output ZN; nand (ZN, A1, A2, A3, A4, A5, A6, A7); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND8Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module ND8D1 (A1, A2, A3, A4, A5, A6, A7, A8, ZN); input A1, A2, A3, A4, A5, A6, A7, A8; output ZN; nand (ZN, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); (A8 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND8Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module ND8D2 (A1, A2, A3, A4, A5, A6, A7, A8, ZN); input A1, A2, A3, A4, A5, A6, A7, A8; output ZN; nand (ZN, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); (A8 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: ND8Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module ND8D3 (A1, A2, A3, A4, A5, A6, A7, A8, ZN); input A1, A2, A3, A4, A5, A6, A7, A8; output ZN; nand (ZN, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); (A8 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NDLx , Mon Nov 24 11:09:05 CST 1997 `timescale 1ns / 10ps `celldefine module NDL1 (RN, SN, Q, QN); input RN, SN; output Q, QN; reg notifier; tsmc_ndla (Q_buf, RN, SN, notifier); tsmc_ndla (QN_buf, SN, RN, notifier); not (Q, QN_buf); not (QN, Q_buf); specify (RN => Q)=(0, 0); (RN => QN)=(0, 0); (SN => Q)=(0, 0); (SN => QN)=(0, 0); $setup(posedge RN, posedge SN , 0, notifier); $hold(posedge SN , posedge RN, 0, notifier); $setup(posedge SN, posedge RN , 0, notifier); $hold(posedge RN , posedge SN, 0, notifier); $width(posedge RN, 0, 0, notifier); $width(negedge RN, 0, 0, notifier); $width(posedge SN, 0, 0, notifier); $width(negedge SN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NDLx , Mon Nov 24 11:09:05 CST 1997 `timescale 1ns / 10ps `celldefine module NDL2 (RN, SN, Q, QN); input RN, SN; output Q, QN; reg notifier; tsmc_ndla (Q_buf, RN, SN, notifier); tsmc_ndla (QN_buf, SN, RN, notifier); not (Q, QN_buf); not (QN, Q_buf); specify (RN => Q)=(0, 0); (RN => QN)=(0, 0); (SN => Q)=(0, 0); (SN => QN)=(0, 0); $setup(posedge RN, posedge SN , 0, notifier); $hold(posedge SN , posedge RN, 0, notifier); $setup(posedge SN, posedge RN , 0, notifier); $hold(posedge RN , posedge SN, 0, notifier); $width(posedge RN, 0, 0, notifier); $width(negedge RN, 0, 0, notifier); $width(posedge SN, 0, 0, notifier); $width(negedge SN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR2Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module NR2D0 (A1, A2, ZN); input A1, A2; output ZN; nor (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR2Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module NR2D1 (A1, A2, ZN); input A1, A2; output ZN; nor (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR2Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module NR2D1H (A1, A2, ZN); input A1, A2; output ZN; nor (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR2Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module NR2D2 (A1, A2, ZN); input A1, A2; output ZN; nor (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR2Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module NR2D3 (A1, A2, ZN); input A1, A2; output ZN; nor (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR3Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module NR3D0 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nor (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR3Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module NR3D1 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nor (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR3Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR3D1H (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nor (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR3Dx , Mon Nov 24 11:08:48 CST 1997 `timescale 1ns / 10ps `celldefine module NR3D2 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nor (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR3Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR3D3 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; nor (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR4Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR4D0 (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nor (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR4Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR4D1 (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nor (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR4Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR4D1H (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nor (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR4Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR4D2 (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nor (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR4Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR4D3 (A1, A2, A3, A4, ZN); input A1, A2, A3, A4; output ZN; nor (ZN, A1, A2, A3, A4); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR5Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR5D1 (A1, A2, A3, A4, A5, ZN); input A1, A2, A3, A4, A5; output ZN; nor (ZN, A1, A2, A3, A4, A5); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR5Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR5D2 (A1, A2, A3, A4, A5, ZN); input A1, A2, A3, A4, A5; output ZN; nor (ZN, A1, A2, A3, A4, A5); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR5Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR5D3 (A1, A2, A3, A4, A5, ZN); input A1, A2, A3, A4, A5; output ZN; nor (ZN, A1, A2, A3, A4, A5); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR6Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR6D1 (A1, A2, A3, A4, A5, A6, ZN); input A1, A2, A3, A4, A5, A6; output ZN; nor (ZN, A1, A2, A3, A4, A5, A6); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR6Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR6D2 (A1, A2, A3, A4, A5, A6, ZN); input A1, A2, A3, A4, A5, A6; output ZN; nor (ZN, A1, A2, A3, A4, A5, A6); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR6Dx , Mon Nov 24 11:08:49 CST 1997 `timescale 1ns / 10ps `celldefine module NR6D3 (A1, A2, A3, A4, A5, A6, ZN); input A1, A2, A3, A4, A5, A6; output ZN; nor (ZN, A1, A2, A3, A4, A5, A6); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR7Dx , Mon Nov 24 11:08:50 CST 1997 `timescale 1ns / 10ps `celldefine module NR7D1 (A1, A2, A3, A4, A5, A6, A7, ZN); input A1, A2, A3, A4, A5, A6, A7; output ZN; nor (ZN, A1, A2, A3, A4, A5, A6, A7); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR7Dx , Mon Nov 24 11:08:50 CST 1997 `timescale 1ns / 10ps `celldefine module NR7D2 (A1, A2, A3, A4, A5, A6, A7, ZN); input A1, A2, A3, A4, A5, A6, A7; output ZN; nor (ZN, A1, A2, A3, A4, A5, A6, A7); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR7Dx , Mon Nov 24 11:08:50 CST 1997 `timescale 1ns / 10ps `celldefine module NR7D3 (A1, A2, A3, A4, A5, A6, A7, ZN); input A1, A2, A3, A4, A5, A6, A7; output ZN; nor (ZN, A1, A2, A3, A4, A5, A6, A7); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR8Dx , Mon Nov 24 11:08:50 CST 1997 `timescale 1ns / 10ps `celldefine module NR8D1 (A1, A2, A3, A4, A5, A6, A7, A8, ZN); input A1, A2, A3, A4, A5, A6, A7, A8; output ZN; nor (ZN, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); (A8 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR8Dx , Mon Nov 24 11:08:50 CST 1997 `timescale 1ns / 10ps `celldefine module NR8D2 (A1, A2, A3, A4, A5, A6, A7, A8, ZN); input A1, A2, A3, A4, A5, A6, A7, A8; output ZN; nor (ZN, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); (A8 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NR8Dx , Mon Nov 24 11:08:50 CST 1997 `timescale 1ns / 10ps `celldefine module NR8D3 (A1, A2, A3, A4, A5, A6, A7, A8, ZN); input A1, A2, A3, A4, A5, A6, A7, A8; output ZN; nor (ZN, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (A4 => ZN)=(0, 0); (A5 => ZN)=(0, 0); (A6 => ZN)=(0, 0); (A7 => ZN)=(0, 0); (A8 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NRLx , Mon Nov 24 11:09:06 CST 1997 `timescale 1ns / 10ps `celldefine module NRL1 (R, S, Q, QN); input R, S; output Q, QN; reg notifier; tsmc_nrla (Q_buf, R, S, notifier); tsmc_nrla (QN_buf, S, R, notifier); not (Q, QN_buf); not (QN, Q_buf); specify (R => Q)=(0, 0); (R => QN)=(0, 0); (S => Q)=(0, 0); (S => QN)=(0, 0); $setup(negedge R, negedge S , 0, notifier); $hold(negedge S , negedge R, 0, notifier); $setup(negedge S, negedge R , 0, notifier); $hold(negedge R , negedge S, 0, notifier); $width(posedge R, 0, 0, notifier); $width(negedge R, 0, 0, notifier); $width(posedge S, 0, 0, notifier); $width(negedge S, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: NRLx , Mon Nov 24 11:09:06 CST 1997 `timescale 1ns / 10ps `celldefine module NRL2 (R, S, Q, QN); input R, S; output Q, QN; reg notifier; tsmc_nrla (Q_buf, R, S, notifier); tsmc_nrla (QN_buf, S, R, notifier); not (Q, QN_buf); not (QN, Q_buf); specify (R => Q)=(0, 0); (R => QN)=(0, 0); (S => Q)=(0, 0); (S => QN)=(0, 0); $setup(negedge R, negedge S , 0, notifier); $hold(negedge S , negedge R, 0, notifier); $setup(negedge S, negedge R , 0, notifier); $hold(negedge R , negedge S, 0, notifier); $width(posedge R, 0, 0, notifier); $width(negedge R, 0, 0, notifier); $width(posedge S, 0, 0, notifier); $width(negedge S, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI211Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI211D0 (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; or nand (A, A1, A2); (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI211Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI211D1 (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; or nand (A, A1, A2); (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI211Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI211D1H (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; or nand (A, A1, A2); (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI211Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI211D2 (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; or nand (A, A1, A2); (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI211Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI211D3 (A1, A2, B, C, ZN); input A1, A2, B, C; output ZN; or nand (A, A1, A2); (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI21Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI21D0 (A1, A2, B, ZN); input A1, A2, B; output ZN; or (A, A1, A2); nand (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI21Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI21D1 (A1, A2, B, ZN); input A1, A2, B; output ZN; or (A, A1, A2); nand (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI21Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI21D1H (A1, A2, B, ZN); input A1, A2, B; output ZN; or (A, A1, A2); nand (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI21Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI21D2 (A1, A2, B, ZN); input A1, A2, B; output ZN; or (A, A1, A2); nand (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI21Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI21D3 (A1, A2, B, ZN); input A1, A2, B; output ZN; or (A, A1, A2); nand (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI221Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI221D1 (A1, A2, B1, B2, C, ZN); input A1, A2, B1, B2, C; output ZN; or (A, A1, A2); or (B, B1, B2); nand (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI221Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI221D1H (A1, A2, B1, B2, C, ZN); input A1, A2, B1, B2, C; output ZN; or (A, A1, A2); or (B, B1, B2); nand (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI221Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI221D2 (A1, A2, B1, B2, C, ZN); input A1, A2, B1, B2, C; output ZN; or (A, A1, A2); or (B, B1, B2); nand (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI221Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI221D3 (A1, A2, B1, B2, C, ZN); input A1, A2, B1, B2, C; output ZN; or (A, A1, A2); or (B, B1, B2); nand (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI222Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI222D1 (A1, A2, B1, B2, C1, C2, ZN); input A1, A2, B1, B2, C1, C2; output ZN; or or or nand (A, A1, A2); (B, B1, B2); (C, C1, C2); (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C1 => ZN)=(0, 0); (C2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI222Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI222D1H (A1, A2, B1, B2, C1, C2, ZN); input A1, A2, B1, B2, C1, C2; output ZN; or or or nand (A, A1, A2); (B, B1, B2); (C, C1, C2); (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C1 => ZN)=(0, 0); (C2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI222Dx , Mon Nov 24 11:09:25 CST 1997 `timescale 1ns / 10ps `celldefine module OAI222D2 (A1, A2, B1, B2, C1, C2, ZN); input A1, A2, B1, B2, C1, C2; output ZN; or or or nand (A, A1, A2); (B, B1, B2); (C, C1, C2); (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C1 => ZN)=(0, 0); (C2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI222Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI222D3 (A1, A2, B1, B2, C1, C2, ZN); input A1, A2, B1, B2, C1, C2; output ZN; or or or nand (A, A1, A2); (B, B1, B2); (C, C1, C2); (ZN, A, B, C); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (C1 => ZN)=(0, 0); (C2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI22Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI22D0 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; or (A, A1, A2); or (B, B1, B2); nand (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI22Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI22D1 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; or or nand (A, A1, A2); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI22Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI22D1H (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; or or nand (A, A1, A2); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI22Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI22D2 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; or or nand (A, A1, A2); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI22Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI22D3 (A1, A2, B1, B2, ZN); input A1, A2, B1, B2; output ZN; or or nand (A, A1, A2); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI31Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI31D0 (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; or nand (A, A1, A2, A3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI31Dx , Mon Nov 24 11:09:26 CST 1997 `timescale 1ns / 10ps `celldefine module OAI31D1 (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; or nand (A, A1, A2, A3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI31Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI31D1H (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; or nand (A, A1, A2, A3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI31Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI31D2 (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; or nand (A, A1, A2, A3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI31Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI31D3 (A1, A2, A3, B, ZN); input A1, A2, A3, B; output ZN; or nand (A, A1, A2, A3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI32Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI32D0 (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI32Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI32D1 (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI32Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI32D1H (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI32Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI32D2 (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI32Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI32D3 (A1, A2, A3, B1, B2, ZN); input A1, A2, A3, B1, B2; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI33Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI33D0 (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2, B3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI33Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI33D1 (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2, B3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI33Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI33D1H (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2, B3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI33Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI33D2 (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2, B3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OAI33Dx , Mon Nov 24 11:09:27 CST 1997 `timescale 1ns / 10ps `celldefine module OAI33D3 (A1, A2, A3, B1, B2, B3, ZN); input A1, A2, A3, B1, B2, B3; output ZN; or or nand (A, A1, A2, A3); (B, B1, B2, B3); (ZN, A, B); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); (B1 => ZN)=(0, 0); (B2 => ZN)=(0, 0); (B3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR2Dx , Mon Nov 24 11:08:50 CST 1997 `timescale 1ns / 10ps `celldefine module OR2D1 (A1, A2, Z); input A1, A2; output Z; or (Z, A1, A2); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR2Dx , Mon Nov 24 11:08:50 CST 1997 `timescale 1ns / 10ps `celldefine module OR2D2 (A1, A2, Z); input A1, A2; output Z; or (Z, A1, A2); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR2Dx , Mon Nov 24 11:08:51 CST 1997 `timescale 1ns / 10ps `celldefine module OR2D3 (A1, A2, Z); input A1, A2; output Z; or (Z, A1, A2); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR3Dx , Mon Nov 24 11:08:51 CST 1997 `timescale 1ns / 10ps `celldefine module OR3D1 (A1, A2, A3, Z); input A1, A2, A3; output Z; or (Z, A1, A2, A3); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR3Dx , Mon Nov 24 11:08:51 CST 1997 `timescale 1ns / 10ps `celldefine module OR3D2 (A1, A2, A3, Z); input A1, A2, A3; output Z; or (Z, A1, A2, A3); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR3Dx , Mon Nov 24 11:08:51 CST 1997 `timescale 1ns / 10ps `celldefine module OR3D3 (A1, A2, A3, Z); input A1, A2, A3; output Z; or (Z, A1, A2, A3); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR4Dx , Mon Nov 24 11:08:51 CST 1997 `timescale 1ns / 10ps `celldefine module OR4D1 (A1, A2, A3, A4, Z); input A1, A2, A3, A4; output Z; or (Z, A1, A2, A3, A4); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR4Dx , Mon Nov 24 11:08:51 CST 1997 `timescale 1ns / 10ps `celldefine module OR4D2 (A1, A2, A3, A4, Z); input A1, A2, A3, A4; output Z; or (Z, A1, A2, A3, A4); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR4Dx , Mon Nov 24 11:08:51 CST 1997 `timescale 1ns / 10ps `celldefine module OR4D3 (A1, A2, A3, A4, Z); input A1, A2, A3, A4; output Z; or (Z, A1, A2, A3, A4); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR5Dx , Mon Nov 24 11:08:52 CST 1997 `timescale 1ns / 10ps `celldefine module OR5D1 (A1, A2, A3, A4, A5, Z); input A1, A2, A3, A4, A5; output Z; or (Z, A1, A2, A3, A4, A5); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR5Dx , Mon Nov 24 11:08:52 CST 1997 `timescale 1ns / 10ps `celldefine module OR5D2 (A1, A2, A3, A4, A5, Z); input A1, A2, A3, A4, A5; output Z; or (Z, A1, A2, A3, A4, A5); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR5Dx , Mon Nov 24 11:08:52 CST 1997 `timescale 1ns / 10ps `celldefine module OR5D3 (A1, A2, A3, A4, A5, Z); input A1, A2, A3, A4, A5; output Z; or (Z, A1, A2, A3, A4, A5); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR6Dx , Mon Nov 24 11:08:52 CST 1997 `timescale 1ns / 10ps `celldefine module OR6D1 (A1, A2, A3, A4, A5, A6, Z); input A1, A2, A3, A4, A5, A6; output Z; or (Z, A1, A2, A3, A4, A5, A6); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR6Dx , Mon Nov 24 11:08:52 CST 1997 `timescale 1ns / 10ps `celldefine module OR6D2 (A1, A2, A3, A4, A5, A6, Z); input A1, A2, A3, A4, A5, A6; output Z; or (Z, A1, A2, A3, A4, A5, A6); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR6Dx , Mon Nov 24 11:08:52 CST 1997 `timescale 1ns / 10ps `celldefine module OR6D3 (A1, A2, A3, A4, A5, A6, Z); input A1, A2, A3, A4, A5, A6; output Z; or (Z, A1, A2, A3, A4, A5, A6); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR7Dx , Mon Nov 24 11:08:52 CST 1997 `timescale 1ns / 10ps `celldefine module OR7D1 (A1, A2, A3, A4, A5, A6, A7, Z); input A1, A2, A3, A4, A5, A6, A7; output Z; or (Z, A1, A2, A3, A4, A5, A6, A7); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR7Dx , Mon Nov 24 11:08:52 CST 1997 `timescale 1ns / 10ps `celldefine module OR7D2 (A1, A2, A3, A4, A5, A6, A7, Z); input A1, A2, A3, A4, A5, A6, A7; output Z; or (Z, A1, A2, A3, A4, A5, A6, A7); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR7Dx , Mon Nov 24 11:08:52 CST 1997 `timescale 1ns / 10ps `celldefine module OR7D3 (A1, A2, A3, A4, A5, A6, A7, Z); input A1, A2, A3, A4, A5, A6, A7; output Z; or (Z, A1, A2, A3, A4, A5, A6, A7); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR8Dx , Mon Nov 24 11:08:53 CST 1997 `timescale 1ns / 10ps `celldefine module OR8D1 (A1, A2, A3, A4, A5, A6, A7, A8, Z); input A1, A2, A3, A4, A5, A6, A7, A8; output Z; or (Z, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); (A8 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR8Dx , Mon Nov 24 11:08:53 CST 1997 `timescale 1ns / 10ps `celldefine module OR8D2 (A1, A2, A3, A4, A5, A6, A7, A8, Z); input A1, A2, A3, A4, A5, A6, A7, A8; output Z; or (Z, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); (A8 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: OR8Dx , Mon Nov 24 11:08:53 CST 1997 `timescale 1ns / 10ps `celldefine module OR8D3 (A1, A2, A3, A4, A5, A6, A7, A8, Z); input A1, A2, A3, A4, A5, A6, A7, A8; output Z; or (Z, A1, A2, A3, A4, A5, A6, A7, A8); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); (A4 => Z)=(0, 0); (A5 => Z)=(0, 0); (A6 => Z)=(0, 0); (A7 => Z)=(0, 0); (A8 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: TFCNx , Mon Nov 24 11:09:05 CST 1997 `timescale 1ns / 10ps `celldefine module TFCN1 (CP, CDN, Q, QN); input CP, CDN; output Q, QN; reg notifier; buf (CDN_i, CDN); pullup (SDN); and (CP_check, CDN_i, SDN); not (D, Q_buf); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: TFCNx , Mon Nov 24 11:09:05 CST 1997 `timescale 1ns / 10ps `celldefine module TFCN2 (CP, CDN, Q, QN); input CP, CDN; output Q, QN; reg notifier; buf (CDN_i, CDN); pullup (SDN); and (CP_check, CDN_i, SDN); not (D, Q_buf); tsmc_dff (Q_buf, D, CP, CDN_i, SDN, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN); specify (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (CP => Q)=(0, 0); (CP => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: TFCSNx , Mon Nov 24 11:09:05 CST 1997 `timescale 1ns / 10ps `celldefine module TFCSN1 (CP, CDN, SDN, Q, QN); input CP, CDN, SDN; output Q, QN; reg notifier; buf (CDN_i, CDN); buf (SDN_i, SDN); and (CP_check, CDN_i, SDN_i); not (D, Q_buf); tsmc_dff (Q_buf, D, CP, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: TFCSNx , Mon Nov 24 11:09:05 CST 1997 `timescale 1ns / 10ps `celldefine module TFCSN2 (CP, CDN, SDN, Q, QN); input CP, CDN, SDN; output Q, QN; reg notifier; buf (CDN_i, CDN); buf (SDN_i, SDN); and (CP_check, CDN_i, SDN_i); not (D, Q_buf); tsmc_dff (Q_buf, D, CP, CDN_i, SDN_i, notifier); buf (Q, Q_buf); not (QN_buf, Q_buf); and (QN, QN_buf, SDN_i); reg flag; always @(CDN_i or SDN_i) begin if (!$test$plusargs("cdn_sdn_check_off")) begin if (flag == 1) begin if (CDN_i!==1'b0) begin $display("%m > CDN is released at time %.2fns.", $realtime); end if (SDN_i!==1'b0) begin $display("%m > SDN is released at time %.2fns.", $realtime); end end flag = ((CDN_i===1'b0)&&(SDN_i ===1'b0)); if (flag == 1) begin $display("%m > Both CDN and SDN are enabled at time %.2fns.", $realtime); end end end specify (CP => Q)=(0, 0); (CP => QN)=(0, 0); (CDN => Q)=(0, 0); (CDN => QN)=(0, 0); (SDN => Q)=(0, 0); (SDN => QN)=(0, 0); $recovery(posedge CDN, posedge CP, 0, notifier); $hold(posedge CP , posedge CDN, 0, notifier); $recovery(posedge SDN, posedge CP, 0, notifier); $hold(posedge CP , posedge SDN, 0, notifier); $width(posedge CP &&& CP_check, 0, 0, notifier); $width(negedge CP &&& CP_check, 0, 0, notifier); $width(posedge CDN, 0, 0, notifier); $width(negedge CDN, 0, 0, notifier); $width(posedge SDN, 0, 0, notifier); $width(negedge SDN, 0, 0, notifier); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XNR2Dx , Mon Nov 24 11:08:53 CST 1997 `timescale 1ns / 10ps `celldefine module XNR2D1 (A1, A2, ZN); input A1, A2; output ZN; xnor (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XNR2Dx , Mon Nov 24 11:08:53 CST 1997 `timescale 1ns / 10ps `celldefine module XNR2D2 (A1, A2, ZN); input A1, A2; output ZN; xnor (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XNR2Dx , Mon Nov 24 11:08:53 CST 1997 `timescale 1ns / 10ps `celldefine module XNR2D3 (A1, A2, ZN); input A1, A2; output ZN; xnor (ZN, A1, A2); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XNR3Dx , Mon Nov 24 11:08:53 CST 1997 `timescale 1ns / 10ps `celldefine module XNR3D1 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; xnor (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XNR3Dx , Mon Nov 24 11:08:53 CST 1997 `timescale 1ns / 10ps `celldefine module XNR3D2 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; xnor (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XNR3Dx , Mon Nov 24 11:08:53 CST 1997 `timescale 1ns / 10ps `celldefine module XNR3D3 (A1, A2, A3, ZN); input A1, A2, A3; output ZN; xnor (ZN, A1, A2, A3); specify (A1 => ZN)=(0, 0); (A2 => ZN)=(0, 0); (A3 => ZN)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XOR2Dx , Mon Nov 24 11:08:54 CST 1997 `timescale 1ns / 10ps `celldefine module XOR2D1 (A1, A2, Z); input A1, A2; output Z; xor (Z, A1, A2); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XOR2Dx , Mon Nov 24 11:08:54 CST 1997 `timescale 1ns / 10ps `celldefine module XOR2D2 (A1, A2, Z); input A1, A2; output Z; xor (Z, A1, A2); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XOR2Dx , Mon Nov 24 11:08:54 CST 1997 `timescale 1ns / 10ps `celldefine module XOR2D3 (A1, A2, Z); input A1, A2; output Z; xor (Z, A1, A2); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XOR3Dx , Mon Nov 24 11:08:54 CST 1997 `timescale 1ns / 10ps `celldefine module XOR3D1 (A1, A2, A3, Z); input A1, A2, A3; output Z; xor (Z, A1, A2, A3); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XOR3Dx , Mon Nov 24 11:08:54 CST 1997 `timescale 1ns / 10ps `celldefine module XOR3D2 (A1, A2, A3, Z); input A1, A2, A3; output Z; xor (Z, A1, A2, A3); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); endspecify endmodule `endcelldefine // TSMC Standard Cell Function Library Ver // Model Type: XOR3Dx , Mon Nov 24 11:08:54 CST 1997 `timescale 1ns / 10ps `celldefine module XOR3D3 (A1, A2, A3, Z); input A1, A2, A3; output Z; xor (Z, A1, A2, A3); specify (A1 => Z)=(0, 0); (A2 => Z)=(0, 0); (A3 => Z)=(0, 0); endspecify endmodule `endcelldefine // User-Defined Primitive Edited by Yi-an Liang of ASIC/TSMC, 05/22/1995. // Modified by Hung-Chun Li 04/30/1997. //********************************************************************** ******* // This is a positive edge triggered User-Defined D flip-flop, with an // active-low clear and an active-low set, CDN and SDN. Q will be cleared to // zero when the clear and set are simultaneously active, CDN = SDN = 0. // // The notifier is the user-defined response to timing check violations. it // propogates an x value at the output, Q, when timing check violations occur. // // Note: // ?: denotes iteration of the table entry over the values 0, 1, and x. // (vw): denotes value change from v to w, v and w can be any of 0, 1, x, ? // -: denotes no change. // *: denotes all the transitions. primitive tsmc_dff (q, d, cp, cdn, sdn, notifier); `protect output q; input d, cp, cdn, sdn, notifier; reg q; table ? ? 0 ? ? : ? : 0 ; // CDN dominate SDN ? ? 1 0 ? : ? : 1 ; // SDN is set ? ? 1 x ? : 0 : x ; // SDN affect Q (added by mcchen 97/8/1) 0 (01) ? 1 ? : ? : 0 ; // Latch 0 0 * ? 1 ? : 0 : 0 ; // Keep 0 (D==Q) 1 (01) 1 ? ? : ? : 1 ; // Latch 1 1 * 1 ? ? : 1 : 1 ; // Keep 1 (D==Q) ? (1?) 1 1 ? : ? : - ; // ignore negative edge of clock ? (?0) 1 1 ? : ? : - ; // ignore negative edge of clock ? ? (?1) ? ? : ? : - ; // ignore positive edge of CDN ? ? ? (?1) ? : ? : - ; // ignore posative edge of SDN * ? ? ? ? : ? : - ; // ignore data change on steady clock ? ? ? ? * : ? : x ; // timing check violation endtable `endprotect endprimitive primitive tsmc_dla (q, d, e, cdn, sdn, notifier); `protect output q; input d, e, cdn, sdn, notifier; reg q; table // d e cdn sdn noti : qt : qt+1 // 1 1 1 1 ? : ? : 1 ; // Latch 1 0 1 1 1 ? : ? : 0 ; // Latch 0 0 (10) 1 1 ? : ? : 0 ; // Latch 0 after falling edge 1 (10) 1 1 ? : ? : 1 ; // Latch 1 after falling edge * 0 ? ? ? : ? : - ; // no changes ? ? ? 0 ? : ? : 1 ; // preset to 1 ? 0 1 * ? :1 : 1 ; 1 ? 1 * ? :1 : 1 ; 1 * 1 ? ? :1 : 1 ; ? ? 0 1 ? : ? : 0 ; // reset to 0 ? 0 * 1 ? :0 : 0 ; 0 ? * 1 ? :0 : 0 ; 0 * ? 1 ? :0 : 0 ; ? ? ? ? * : ? : x ; // toggle notifier endtable `endprotect endprimitive // User-Defined Primitive Edited by Hung-Chun Li of ASIC/TSMC, 10/16/1996. //********************************************************************** ******* // // Note: // ?: denotes iteration of the table entry over the values 0, 1, and x. primitive tsmc_mux (q, d0, d1, s); output q; input s, d0, d1; `protect table // d0 d1 s 0?0 1?0 ?01 ?11 00x 11x endtable `endprotect :q :0; :1; :0; :1; :0; :1; endprimitive // User-Defined Primitive Edited by Yi-an Liang of ASIC/TSMC, 11/03/1994. // Modified by Hung-Chun Li 04/14/1997 //********************************************************************** ******** // This is a User-Defined unbuffered SR(2 cross-coupled NANDs) latch, with an // active-high set and active-high reset. Latch mode(SN=RN=1) may be entered // only when complement output states have been established. SN=RN=0 generates // a HIGH output on Q. // // The notifier is the user-defined response to timing check violations. it // propogates an x value at the output, Q, when timing check violations occur. // // Note: // ?: denotes iteration of the table entry over the values 0, 1, and x. // -: denotes no change. // *: denotes all the transitions. primitive tsmc_ndla (q, rn, sn, notifier); `protect output q; input rn, sn, notifier; reg q; table ? 0 ? : ? : 1 ; // Set dominate Clear 0 1 ? : ? : 0 ; // Clear // 1 ? ? : 1 : 1 ; // Hold 1 or Set // ? 1 ? : 0 : 0 ; // Hold 0 or Clear // 1 1 ? : ? : - ; // Hold original state 1 p ? : ? : - ; // Hold original state p 1 ? : ? : - ; // Hold original state ? ? * : ? : x ; // Timing check violation endtable `endprotect endprimitive // User-Defined Primitive Edited by Yi-an Liang of ASIC/TSMC, 11/03/1994. // Modified by Hung-Chun Li 04/14/1997 //********************************************************************** ******** // This is a User-Defined SR(2 cross-coupled NORs) latch, with an active-high // set and active-high reset. Latch mode(S=R=0) may be entered only when // complement output states have been established. S=R=1 generates a LOW // output on Q. // // The notifier is the user-defined response to timing check violations. it // propogates an x value at the output, Q, when timing check violations occur. // // Note: // ?: denotes iteration of the table entry over the values 0, 1, and x. // -: denotes no change. // *: denotes all the transitions. primitive tsmc_nrla (q, r, s, notifier); `protect output q; input r, s, notifier; reg q; table 1? 01 ? : ? : 0 ; // Reset dominate Set ? : ? : 1 ; // Set // ? 0 ? : 0 : 0 ; // Reset or Hold 0 // 0 ? ? : 1 : 1 ; // Set or Hold 1 // 0 0 ? : ? : - ; // Hold original state 0 n ? : ? : - ; // Hold original state n 0 ? : ? : - ; // Hold original state ? ? * : ? : x ; // Timing Check violation endtable `endprotect endprimitive 附录 3 Dracula 命令文件 1. DRC 命令文件 ;*********************************************************************** * ; ;DRC CHECKS FOR 0.5 MICRON TRIBLE METAL SINGLE POLY CMOS PROCESS OF TSMC; ; Version 1.0 ; by DENG HAIFEI MARCH 23, 1999 ; ;*********************************************************************** * *DESCRIPTION INDISK = /EDAHOME01/students/dhf/sram/drc/mux2.gds OUTDISK = /EDAHOME01/students/dhf/sram/drc/drc.gds WORK-DIR = /EDAHOME01/students/dhf/sram/drc/ PRIMARY = MUX2 SYSTEM = GDS2 SCALE = 0.001 MICRON RESOLUTION = 0.1 MICRON PRINTFILE = drcprt LISTERROR = YES PREINQUERY = YES KEEPDATA = YES CNAMES-CSEN = YES *END ; ;********************************************************** ; ; INPUT-LAYER BLOCK ; ;********************************************************** *INPUT-LAYER NDIFF = 1 PDIFF = 2 DIFF = 3 PWELL = 6 VIA2 = 7 VIA = 8 NWELL = 12 PAD = 29 POLY = 35 ESD = 44 METAL1 = 45 TEXT = 61 METAL2 = 50 METAL3 = 46 CONT = 55 TEXT = 61 SUBSTRATE = BULK 60; Layer created for reverse mask ; CONNECT-LAY = NWELL PWELL NSD PSD POLY METAL1 METAL2 METAL3 ; ; *** The conductor layer of the CMOS process *** ; *END ; ;********************************************************** ; ; OPERATION BLOCK ; CREAT THE DEVICE LAYERS AND CONDUCTOR LAYERS ; ;********************************************************** *OPERATION AND DIFF PDIFF PREGION NOT DIFF PREGION NREGION AND POLY NREGION NGATE AND POLY PREGION PGATE OR PGATE NGATE GATE NOT NREGION NGATE NSD NOT PREGION PGATE PSD OR NSD PSD SRCDRN NOT BULK PWELL NWSUB NOT NWSUB NWELL SUB AND DIFF NWELL DIFNW AND DIFF PWELL DIFPW OR DIFNW DIFPW DIFWE AND PWELL PSD PSDPW AND NWELL NSD NSDNW ;********************************************************** ; ; CONNECT OPERATION FOR CMOS PROCESS ; ;********************************************************** ; CONNECT METAL1 POLY BY CONT CONNECT METAL1 NSD BY CONT CONNECT METAL1 PSD BY CONT CONNECT PSD PWELL BY PSDPW CONNECT NSD NWELL BY NSDNW CONNECT METAL2 METAL1 BY VIA CONNECT METAL3 METAL2 BY VIA2 ; ; DRC CHECKS ; ;******************************************************************** ; NWELL RULES ;******************************************************************** WIDTH NWELL LT 2.5 OUTPUT DRC01 31 EXT NWELL LT 4.0 OUTPUT DRC01 32 ; ;********************************************************************* ; THIN OXIDE RULE ;********************************************************************* SELECT DIFWE CUT POLY DFWP WIDTH DFWP LT 0.6 OUTPUT DRC02 41 NOT DIFF DFWP IDFWP WIDTH IDFWP LT 0.5 OUTPUT DRC02 42 SELECT DIFF INSIDE NWELL DFINNW SELECT DIFF OUTSIDE NWELL DFOUNW OR DFINNW DFOUNW DFIONW EXT DFIONW LT 0.9 OUTPUT DRC02 43 AND DFINNW NDIFF NDFINNW ENC[CP] NWELL NDFINNW LT 0.3 OUTPUT DRC02 44 NOT NREGION NDFINNW NDFOUNW EXT[C] NWELL NDFOUNW LT 3.3 OUTPUT DRC02 45 SELECT PREGION INSIDE NWELL PDFINNW ENC[CP] NWELL PDFINNW LT 1.5 OUTPUT DRC02 46 NOT PREGION PDFINNW PDFOUNW EXT[C] NWELL PDFOUNW LT 0.3 OUTPUT DRC02 47 SELECT POLY CUT PREGION POPR EXT[C] POPR NREGION LT 0.6 OUTPUT DRC02 48 SELECT POLY CUT NREGION PONR EXT[C] PONR PREGION LT 0.6 OUTPUT DRC02 50 SELECT PREGION TOUCH NREGION PRTNR NOT PREGION PRTNR PRNTNR EXT[C] PRNTNR NREGION LT 0.9 OUTPUT DRC02 49 ;*************************************************************** ; POLY RULE ;*************************************************************** WIDTH PGATE LT 0.5 OUTPUT DRC03 51 WIDTH NGATE LT 0.5 OUTPUT DRC03 52 OR POPR PONR POTR NOT POLY POTR IPOLY WIDTH IPOLY LT 0.5 OUTPUT DRC03 53 EXT POLY LT 0.6 OUTPUT DRC03 54 NOT BULK DIFF OXFID SIZE GATE BY 0.26 OGATE NOT POLY OGATE NOGPOLY AND NOGPOLY OXFID POOXFI EXT[C] POOXFI DIFF LT 0.25 OUTPUT DRC03 55 ENC[CP] DIFF POLY LT 0.65 OUTPUT DRC03 56 WIDTH POOXFI LT 0.5 OUTPUT DRC03 57 ;******************************************************************* ; P+ S/D RULE ;******************************************************************** WIDTH PDIFF LT 0.75 OUTPUT DRC04 41 EXT PDIFF LT 0.75 OUTPUT DRC04 42 EXT[C] PDIFF DIFF LT 0.6 OUTPUT DRC04 43 ENC[CP] PDIFF PGATE LT 0.6 OUTPUT DRC04 44 ENC[CP] PDIFF NGATE LT 0.6 OUTPUT DRC04 48 INT[C] PDIFF DIFF LT 0.6 OUTPUT DRC04 45 ENC[CP] PDIFF PREGION LT 0.3 OUTPUT DRC04 46 EXT[C] PDIFF NDIFF LT 0.3 OUTPUT DRC04 47 ;******************************************************************* ; N+ S/D RULE ;******************************************************************** WIDTH NDIFF LT 0.75 OUTPUT DRC05 41 EXT NDIFF LT 0.75 OUTPUT DRC05 42 EXT[C] NDIFF DIFF LT 0.6 OUTPUT DRC05 43 ENC[CP] NDIFF PGATE LT 0.6 OUTPUT DRC05 44 ENC[CP] NDIFF NGATE LT 0.6 OUTPUT DRC05 48 INT[C] NDIFF DIFF LT 0.6 OUTPUT DRC05 45 ENC[CP] NDIFF NREGION LT 0.3 OUTPUT DRC05 46 EXT[C] NDIFF PDIFF LT 0.3 OUTPUT DRC05 47 ;********************************************************************** ; ESD IMPLANTATION RULE ;********************************************************************** ;IT WILL BE WRITTEN LATER. ;********************************************************************** ; CONTACT RULE ;********************************************************************** ; WIDTH CONT LT 0.5 OUTPUT DRC07 71 ; WIDTH CONT GT 0.5 OUTPUT DRC07 70 EXT CONT LT 0.5 OUTPUT DRC07 72 AND CONT DIFF CONDIF EXT[C] CONDIF GATE LT 0.4 OUTPUT DRC07 73 AND CONT POLY CONPO EXT[C] CONPO DIFF LT 0.5 OUTPUT DRC07 74 ENC[C] DIFF CONT LT 0.25 OUTPUT DRC07 75 SELECT CONT INSIDE DIFF CONINDI SIZE CONINDI BY 0.3 CONIDO SELECT CONIDO CUT DIFF CONCUDI OUTPUT DRC07 76 SELECT CONT INSIDE POLY CONINPO ENC[CP] POLY CONTINPO LT 0.3 OUTPUT DRC07 77 ENC[CP] PDIFF CONT LT 0.3 OUTPUT DRC07 78 ENC[CP] NDIFF CONT LT 0.3 OUTPUT DRC07 79 SELECT CONT CUT GATE CONGA OUTPUT DRC07 80 ;********************************************************************** ; METAL-1 RULE ;********************************************************************** WIDTH METAL1 LT 0.6 OUTPUT DRC08 81 EXT METAL1 LT 0.6 OUTPUT DRC08 82 ENC[CP] METAL1 CONT LT 0.25 OUTPUT DRC08 83 WIDTH METAL1 SELGT 10 M110 EXT[C] METAL1 M110 LT 1.0 OUTPUT DRC08 84 ;*********************************************************************** ; VIA RULE ;********************************************************************** ; WIDTH VIA LT 0.6 OUTPUT DRC09 91 ; WIDTH VIA GT 0.6 OUTPUT DRC09 98 EXT VIA LT 0.6 OUTPUT DRC09 92 ENC[C] METAL1 VIA LT 0.3 OUTPUT DRC09 95 ENC[C] M110 VIA LT 0.5 OUTPUT DRC09 96 AND VIA CONT VICON AND VICON VIA2 VIA12CO OUTPUT DRC09 97 EXT[CP] VIA2 VICON LT 0.5 OUTPUT DRC09 99 ;*********************************************************************** ; METAL2 RULE ;*********************************************************************** WIDTH METAL2 LT 0.7 OUTPUT DRC10 81 EXT METAL2 LT 0.7 OUTPUT DRC10 82 ENC[CP] METAL2 VIA LT 0.3 OUTPUT DRC10 83 WIDTH METAL2 SELGT 10 M210 ENC[CP] M210 VIA LT 0.5 OUTPUT DRC10 85 EXT[C] METAL2 M110 LT 1.0 OUTPUT DRC10 84 ;********************************************************************** ; VIA2 RULE ;*********************************************************************** ; WIDTH VIA2 LT 0.6 OUTPUT DRC11 91 ; WIDTH VIA2 GT 0.6 OUTPUT DRC11 97 EXT VIA2 LT 0.6 OUTPUT DRC11 92 ENC[C] METAL2 VIA2 LT 0.3 OUTPUT DRC11 95 ENC[C] M210 VIA2 LT 0.5 OUTPUT DRC11 96 AND VIA2 VIA VIA12 EXT[CP] VIA12 CONT LT 0.5 OUTPUT DRC11 98 ;*********************************************************************** ; METAL3 RULE ;*********************************************************************** WIDTH METAL3 LT 0.8 OUTPUT DRC12 81 EXT METAL3 LT 0.7 OUTPUT DRC12 82 ENC[CP] METAL3 VIA2 LT 0.3 OUTPUT DRC12 83 WIDTH METAL3 SELGT 10 M310 ENC[CP] M310 VIA2 LT 0.5 OUTPUT DRC12 85 EXT[C] METAL3 M310 LT 1.0 OUTPUT DRC12 84 ; *END 2. ERC 命令文件 ;*********************************************************************** * ; ;DRC CHECKS FOR 0.5 MICRON TRIBLE METAL SINGLE POLY CMOS PROCESS OF TSMC; ; Version 1.0 ; by DENG HAIFEI MARCH 23, 1999 ; ;*********************************************************************** * *DESCRIPTION INDISK = /EDAHOME01/students/dhf/sram/drc/mux2.gds OUTDISK = /EDAHOME01/students/dhf/sram/drc/drc.gds WORK-DIR = /EDAHOME01/students/dhf/sram/drc/ PRIMARY = MUX2 SYSTEM = GDS2 SCALE = 0.001 MICRON RESOLUTION = 0.1 MICRON PRINTFILE = ercprt LISTERROR = YES PREINQUERY = YES KEEPDATA = YES CNAMES-CSEN = YES *END ; ;********************************************************** ; ; INPUT-LAYER BLOCK ; ;********************************************************** *INPUT-LAYER NDIFF = 1 PDIFF = 2 DIFF = 3 PWELL = 6 VIA2 = 7 VIA = 8 NWELL = 12 PAD = 29 POLY = 35 ESD = 44 METAL1 = 45 TEXT = 61 METAL2 = 50 METAL3 = 46 CONT = 55 TEXT = 61 SUBSTRATE = BULK 60; Layer created for reverse mask ; CONNECT-LAY = NWELL PWELL NSD PSD POLY METAL1 METAL2 METAL3 ; ; *** The conductor layer of the CMOS process *** ; *END ; ;********************************************************** ; ; OPERATION BLOCK ; CREAT THE DEVICE LAYERS AND CONDUCTOR LAYERS ; ;********************************************************** *OPERATION AND DIFF PDIFF PREGION NOT DIFF PREGION NREGION AND POLY NREGION NGATE AND POLY PREGION PGATE OR PGATE NGATE GATE NOT NREGION NGATE NSD NOT PREGION PGATE PSD OR NSD PSD SRCDRN NOT BULK PWELL NWSUB NOT NWSUB NWELL SUB AND DIFF NWELL DIFNW AND DIFF PWELL DIFPW OR DIFNW DIFPW DIFWE AND PWELL PSD PSDPW AND NWELL NSD NSDNW ;********************************************************** ; ; CONNECT OPERATION FOR CMOS PROCESS ; ;********************************************************** ; CONNECT METAL1 POLY BY CONT CONNECT METAL1 NSD BY CONT CONNECT METAL1 PSD BY CONT CONNECT PSD PWELL BY PSDPW CONNECT NSD NWELL BY NSDNW CONNECT METAL2 METAL1 BY VIA CONNECT METAL3 METAL2 BY VIA2 ; ;*********************************************************************** ** ;*********************************************************************** ** ; ; DEFINE ELEMENTS OF CMOS PROCESS ; ;*********************************************************************** ** ;*********************************************************************** ** ELEMENT MOS[N] NGATE POLY NSD PWELL ELEMENT MOS[P] PGATE POLY PSD NWELL ;*********************************************************************** ** ;*********************************************************************** ** ; ; ERC CHECKS ; ;*********************************************************************** ** ;*********************************************************************** ** ; MULTILABOUTPUT SHORTS 40 SAMELAB OUTPUT OPENS 40 NDCOUNT MOS[N] NSD GT 2 OUTPUT DEVERR1 45 NDCOUNT MOS[P] PSD GT 2 OUTPUT DEVERR2 45 ELCOUNT MOS ALL EQ 0 OUTPUT FLOAT 40 ECONNECTMOS[N] NSD CONN VDD & ECONNECTMOS[N] NSD CONN VSS OUTPUT VDVSN 48 ECONNECTMOS[P] PSD CONN VDD & ECONNECTMOS[P] PSD CONN VSS OUTPUT VDVSP 48 ECONNECTMOS[P] POLY CONN VDD OUTPUT GATVDD 49 ECONNECTMOS[N] POLY CONN VSS OUTPUT GATVSS 49 ECONNECTMOS[P] PSD CONN VSS OUTPUT PSDVSS 50 ECONNECTMOS[N] NSD CONN VDD OUTPUT NSDVDD 50 ;PATHCHK LEVEL 1 OUTPUT NOVDD 40 ; PATHCHK LEVEL 2 OUTPUT NOVSS 40 ; PATHCHK LEVEL 3 OUTPUT NOPWGR 40 ; PATHCHK LEVEL 4 OUTPUT NOALL 40 ELCOUNT MOS ALL EQ 1 OUTPUT ONEDEV 40 NDCOUNT MOS[N] NSD EQ 2 & NDCOUNT MOS[N] ALL EQ 2 OUTPUT NDEPL 55 NDCOUNT MOS ALL EQ 1 OUTPUT MIXUP 56 LCONNECTPWELL DISC GND OUTPUT FLOWEL 57 LCONNECTNWELL DISC VDD OUTPUT FLOWEN 57 ; ; *END 3. LVS 命 令 文件 ;*********************************************************************** * ; ;DRC CHECKS FOR 0.5 MICRON TRIBLE METAL SINGLE POLY CMOS PROCESS OF TSMC; ; Version 1.0 ; by DENG HAIFEI MARCH 23, 1999 ; ;*********************************************************************** * *DESCRIPTION INDISK = /EDAHOME01/students/dhf/sram/drc/mux2.gds OUTDISK = /EDAHOME01/students/dhf/sram/drc/drc.gds WORK-DIR = /EDAHOME01/students/dhf/sram/drc/ PRIMARY = MUX2 MODE = EXEC NOW SYSTEM = GDS2 SCALE = 0.001 MICRON RESOLUTION = 0.1 MICRON PRINTFILE = ercprt LISTERROR = YES PREINQUERY = YES KEEPDATA = YES CNAMES-CSEN = YES SCHEMATIC =LVSLOGIC *END ; ;********************************************************** ; ; INPUT-LAYER BLOCK ; ;********************************************************** *INPUT-LAYER NDIFF = 1 PDIFF = 2 DIFF = 3 PWELL = 6 VIA2 = 7 VIA = 8 NWELL = 12 PAD = 29 POLY = 35 ESD = 44 METAL1 = 45 TEXT = 61 METAL2 = 50 METAL3 = 46 CONT = 55 TEXT = 61 SUBSTRATE = BULK 60; Layer created for reverse mask ; CONNECT-LAY = NWELL PWELL NSD PSD POLY METAL1 METAL2 METAL3 ; ; *** The conductor layer of the CMOS process *** ; *END ; ;********************************************************** ; ; OPERATION BLOCK ; CREAT THE DEVICE LAYERS AND CONDUCTOR LAYERS ; ;********************************************************** *OPERATION AND DIFF PDIFF PREGION NOT DIFF PREGION NREGION AND POLY NREGION NGATE AND POLY PREGION PGATE OR PGATE NGATE GATE NOT NREGION NGATE NSD NOT PREGION PGATE PSD OR NSD PSD SRCDRN NOT BULK PWELL NWSUB NOT NWSUB NWELL SUB AND DIFF NWELL DIFNW AND DIFF PWELL DIFPW OR DIFNW DIFPW DIFWE AND PWELL PSD PSDPW AND NWELL NSD NSDNW ;********************************************************** ; ; CONNECT OPERATION FOR CMOS PROCESS ; ;********************************************************** ; CONNECT METAL1 POLY BY CONT CONNECT METAL1 NSD BY CONT CONNECT METAL1 PSD BY CONT CONNECT PSD PWELL BY PSDPW CONNECT NSD NWELL BY NSDNW CONNECT METAL2 METAL1 BY VIA CONNECT METAL3 METAL2 BY VIA2 ; ; ; DEFINE ELEMENTS OF CMOS PROCESS ; ;*********************************************************************** ** ;*********************************************************************** ** ELEMENT MOS[N] NGATE POLY NSD PWELL ELEMENT MOS[P] PGATE POLY PSD NWELL ;*********************************************************************** ** ;*********************************************************************** ** ; ; ERC CHECKS ; ;*********************************************************************** ** ;*********************************************************************** ** ; MULTILABOUTPUT SHORTS 40 SAMELAB OUTPUT OPENS 40 NDCOUNT MOS[N] NSD GT 2 OUTPUT DEVERR1 45 NDCOUNT MOS[P] PSD GT 2 OUTPUT DEVERR2 45 ELCOUNT MOS ALL EQ 0 OUTPUT FLOAT 40 ECONNECTMOS[N] NSD CONN VDD & ECONNECTMOS[N] NSD CONN VSS OUTPUT VDVSN 48 ECONNECTMOS[P] PSD CONN VDD & ECONNECTMOS[P] PSD CONN VSS OUTPUT VDVSP 48 ECONNECTMOS[P] POLY CONN VDD OUTPUT GATVDD 49 ECONNECTMOS[N] POLY CONN VSS OUTPUT GATVSS 49 ECONNECTMOS[P] PSD CONN VSS OUTPUT PSDVSS 50 ECONNECTMOS[N] NSD CONN VDD OUTPUT NSDVDD 50 PATHCHK LEVEL 1 OUTPUT NOVDD 40 PATHCHK LEVEL 2 OUTPUT NOVSS 40 PATHCHK LEVEL 3 OUTPUT NOPWGR 40 PATHCHK LEVEL 4 OUTPUT NOALL 40 ELCOUNT MOS ALL EQ 1 OUTPUT ONEDEV 40 NDCOUNT MOS[N] NSD EQ 2 & NDCOUNT MOS[N] ALL EQ 2 OUTPUT NDEPL 55 NDCOUNT MOS ALL EQ 1 OUTPUT MIXUP 56 LCONNECTPWELL DISC VSS OUTPUT FLOWEL 57 LCONNECTNWELL DISC VDD OUTPUT FLOWEN 57 LVSCHK ; ; *END 4. LPE 命令文件 ;*********************************************************************** * ; ;DRC CHECKS FOR 0.5 MICRON TRIBLE METAL SINGLE POLY CMOS PROCESS OF TSMC; ; Version 1.0 ; by DENG HAIFEI MARCH 23, 1999 ; ;*********************************************************************** * *DESCRIPTION INDISK = /EDAHOME01/students/dhf/sram/drc/mux2.gds OUTDISK = /EDAHOME01/students/dhf/sram/drc/lpe.gds WORK-DIR = /EDAHOME01/students/dhf/sram/drc/ PRIMARY = MUX2 MODE = EXEC NOW SYSTEM = GDS2 SCALE = 0.001 MICRON RESOLUTION = 0.1 MICRON PRINTFILE = ercprt DIODESEQ = A1 P1 MODEL = MOS[N],N MOS[P],P DIO[N],N DIO[P],P UNIT = CAPACITANCE,PF LISTERROR = YES PREINQUERY = YES KEEPDATA = YES CNAMES-CSEN = YES SCHEMATIC =LVSLOGIC *END ; ;********************************************************** ; ; INPUT-LAYER BLOCK ; ;********************************************************** *INPUT-LAYER NDIFF = 1 PDIFF = 2 DIFF = 3 PWELL = 6 VIA2 = 7 VIA = 8 NWELL = 12 PAD = 29 POLY = 35 ESD = 44 METAL1 = 45 TEXT = 61 METAL2 = 50 METAL3 = 46 CONT = 55 TEXT = 61 SUBSTRATE = BULK 60; Layer created for reverse mask ; CONNECT-LAY = NWELL PWELL NSD PSD POLY METAL1 METAL2 METAL3 ; ; *** The conductor layer of the CMOS process *** ; *END ; ;********************************************************** ; ; OPERATION BLOCK ; CREAT THE DEVICE LAYERS AND CONDUCTOR LAYERS ; ;********************************************************** *OPERATION AND DIFF PDIFF PREGION NOT DIFF PREGION NREGION AND POLY NREGION NGATE AND POLY PREGION PGATE OR PGATE NGATE GATE NOT NREGION NGATE NSD NOT PREGION PGATE PSD OR NSD PSD SRCDRN NOT BULK PWELL NWSUB NOT NWSUB NWELL SUB AND DIFF NWELL DIFNW AND DIFF PWELL DIFPW OR DIFNW DIFPW DIFWE AND PWELL PSD PSDPW AND NWELL NSD NSDNW ;********************************************************** ; ; CONNECT OPERATION FOR CMOS PROCESS ; ;********************************************************** ; CONNECT METAL1 POLY BY CONT CONNECT METAL1 NSD BY CONT CONNECT METAL1 PSD BY CONT CONNECT PSD PWELL BY PSDPW CONNECT NSD NWELL BY NSDNW CONNECT METAL2 METAL1 BY VIA CONNECT METAL3 METAL2 BY VIA2 ;*********************************************************************** ** ;*********************************************************************** ** ; ; DEFINE ELEMENTS OF CMOS PROCESS ; ;*********************************************************************** ** ;*********************************************************************** ** ELEMENT MOS[N] NGATE POLY NSD PWELL ELEMENT MOS[P] PGATE POLY PSD NWELL ; ;*********************************************************************** ******* ;*********************************************************************** ******* ; LPE CHECK ;*********************************************************************** ******* ;*********************************************************************** ******* ; ;*********************************************************************** ******* ; LOGIC OPERATION DEFINING THE PARASITIC CAPACITORS AND DIODES ;*********************************************************************** ******* ; AND METAL1 POLY MPOLY ; METAL1 OT POLY CAPACITORS NOT METAL1 POLY METNP ; REMOVE POLY UNDERNEATH METAL1 AND METNP NSD MNSD ; METAL TO N+ SOURCE/DRAIN CAPACITORS AND METNP PSD MPSD ; METAL TO P+ SOURCE/DRAIN CAPACITORS NOT METNP NSD M1 NOT M1 PSD M2 AND M2 PWELL MPWELL ; METAL TO PWELL CAPACITORS AND M2 NWELL MNWELL ; METAL TO NWELL CAPACITORS ; NOT POLY GATE P2 AND P2 PWELL POWELL ;POLY TO PWELL CAPACITORS AND P2 NWELL PONW ; POLY TO NWELL CAPACITORS ; AND METAL2 METAL1 METAL12 ; METAL2 TO METAL1 CAPACITORS NOT AND NOT AND AND NOT NOT AND AND ; AND NOT AND NOT AND NOT AND AND NOT NOT AND AND ; AND NOT METAL2 METAL1 MET2N1 MET2N1 POLY M2POLY ; METAL2 OT POLY CAPACITORS MET2N1 POLY MET2NP ; REMOVE POLY UNDERNEATH METAL2 MET2NP NSD M2NSD ; METAL2 TO N+ SOURCE/DRAIN CAPACITORS MET2NP PSD M2PSD ; METAL2 TO P+ SOURCE/DRAIN CAPACITORS MET2NP NSD M21 M21 PSD M22 M22 PWELL M2PWELL ; METAL2 TO PWELL CAPACITORS M22 NWELL M2NWELL ; METAL2 TO NWELL CAPACITORS METAL3 METAL2 METAL23 ;METAL3 TO METAL2 C METAL3 METAL2 MET3N2 MET3N2 METAL1 METAL13 ; METAL3 TO METAL1 CAPACITORS MET3N2 METAL1 MET3N1 MET3N1 POLY M3POLY ; METAL3 OT POLY CAPACITORS MET3N1 POLY MET3NP ; REMOVE POLY UNDERNEATH METAL3 MET3NP NSD M3NSD ; METAL3 TO N+ SOURCE/DRAIN CAPACITORS MET3NP PSD M3PSD ; METAL3 TO P+ SOURCE/DRAIN CAPACITORS MET3NP NSD M31 M31 PSD M32 M32 PWELL M3PWELL ; METAL3 TO PWELL CAPACITORS M32 NWELL M3NWELL ; METAL3 TO NWELL CAPACITORS NSD PWELL NPDIO PSD PWELL PPDIO ;*********************************************************************** ******* ; DEFINE TRANSITORS ELEMENTS AND PARASITIC ELEMENTS ;*********************************************************************** ******* ; ELEMENT MOS[N] NGATE POLY NSD PWELL ; ELEMENT MOS[P] PGATE POLY PSD NWELL ; PARASITIC DIO[N] NPDIO PWELL NPDIO PARASITIC DIO[P] PPDIO PPDIO NWELL ; PARASITIC CAP[A] MPOLY METAL1 POLY ATTRIBUTE CAP[A] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[B] MNSD METAL1 NSD ATTRIBUTE CAP[B] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[C] MPSD METAL1 PSD ATTRIBUTE CAP[C] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[D] MPWELL METAL1 PWELL ATTRIBUTE CAP[D] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[E] MNWELL METAL1 NWELL ATTRIBUTE CAP[E] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[F] POWELL POLY PWELL ATTRIBUTE CAP[F] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[G] PONW POLY NWELL ATTRIBUTE CAP[G] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[H] MPSD METAL1 PSD ATTRIBUTE CAP[H] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; ; PARASITIC CAP[I] METAL12 METAL2 METAL1 ; ATTRIBUTE CAP[I] ; 0.00005 ; ATTRIBUTE (PF/SQ MICRON) PARASITIC CAP[J] M2POLY METAL2 POLY ATTRIBUTE CAP[J] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[K] M2NSD METAL2 NSD ATTRIBUTE CAP[K] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[L] M2PSD METAL2 PSD ATTRIBUTE CAP[L] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[M] M2PWELL METAL2 PWELL ATTRIBUTE CAP[M] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[N] M2NWELL METAL2 NWELL ATTRIBUTE CAP[N] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; ; PARASITIC CAP[O] METAL23 METAL3 METAL2 ; ; ATTRIBUTE CAP[O] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; ; PARASITIC CAP[P] METAL13 METAL3 METAL1 ; ; ATTRIBUTE CAP[P] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[Q] M3POLY METAL3 POLY ATTRIBUTE CAP[Q] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[R] M3NSD METAL3 NSD ATTRIBUTE CAP[R] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[S] M3PSD METAL3 PSD ATTRIBUTE CAP[S] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[T] M3PWELL METAL3 PWELL ATTRIBUTE CAP[T] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; PARASITIC CAP[U] M3NWELL METAL3 NWELL ATTRIBUTE CAP[U] 0.00005 ; ATTRIBUTE (PF/SQ MICRON) ; LPECHK ; LPESELECT[S] MOS[P] & LPESELECT[S] MOS[N] & LPESELECT[S] DIO[P] & LPESELECT[S] DIO[N] & LPESELECT[S] CAP[A] GT 0.0 & LPESELECT[S] CAP[B] GT 0.0 & LPESELECT[S] CAP[C] GT 0.0 & LPESELECT[S] CAP[D] GT 0.0 & LPESELECT[S] CAP[E] GT 0.0 & LPESELECT[S] CAP[F] GT 0.0 & LPESELECT[S] CAP[G] GT 0.0 & LPESELECT[S] CAP[H] GT 0.0 & ; LPESELECT[S] CAP[I] GT 0.0 & LPESELECT[S] CAP[J] GT 0.0 & LPESELECT[S] CAP[K] GT 0.0 & LPESELECT[S] CAP[L] GT 0.0 & LPESELECT[S] CAP[M] GT 0.0 & LPESELECT[S] CAP[N] GT 0.0 & ; LPESELECT[S] CAP[O] GT 0.0 & ; LPESELECT[S] CAP[P] GT 0.0 & LPESELECT[S] CAP[Q] GT 0.0 & LPESELECT[S] CAP[R] GT 0.0 & LPESELECT[S] CAP[S] GT 0.0 & LPESELECT[S] CAP[C] GT 0.0 & LPESELECT[S] CAP[U] GT 0.0 OUTPUT MYSPI ; *END

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