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ADSP-BF592芯片手册

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  • 日期: 2018-06-02
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标签: 芯片手册

ADSP-BF592芯片手册

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ADSPBF59x Blackfin Processor Hardware Reference Revision 12 February 2013 Part Number 8210010201 Analog Devices Inc One Technology Way Norwood Mass 020629106 a Copyright Information 2013 Analog Devices Inc ALL RIGHTS RESERVED This docu ment may not be reproduced in any form without prior express written consent from Analog Devices Inc Printed in the USA Disclaimer Analog Devices Inc reserves the right to change this product without prior notice Information furnished by Analog Devices is beli......

ADSP-BF59x Blackfin® Processor Hardware Reference Revision 1.2, February 2013 Part Number 82-100102-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu- ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli- cation or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-KIT Lite, and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS PREFACE Purpose of This Manual ........................................................... xxxiii Intended Audience .................................................................... xxxiii Manual Contents ...................................................................... xxxiv What’s New in This Manual ...................................................... xxxvi Technical Support .................................................................... xxxvii Supported Processors ............................................................... xxxviii Product Information ............................................................... xxxviii Analog Devices Web Site .................................................... xxxvix EngineerZone ..................................................................... xxxvix Notation Conventions .................................................................... xl Register Diagram Conventions ...................................................... xli INTRODUCTION General Description of Processor ................................................... 1-1 Portable Low-Power Architecture ............................................. 1-2 Peripherals .................................................................................... 1-3 ADSP-BF59x Blackfin Processor Hardware Reference iii Contents Memory Architecture .................................................................... 1-4 Internal Memory ..................................................................... 1-5 I/O Memory Space .................................................................. 1-6 DMA Support .............................................................................. 1-6 General-Purpose I/O (GPIO) ........................................................ 1-7 Two-Wire Interface ....................................................................... 1-9 Parallel Peripheral Interface ......................................................... 1-10 SPORT Controllers .................................................................... 1-11 Serial Peripheral Interface (SPI) Ports .......................................... 1-13 Timers ....................................................................................... 1-14 UART Port ................................................................................. 1-14 Watchdog Timer ......................................................................... 1-16 Clock Signals .............................................................................. 1-16 Dynamic Power Management ..................................................... 1-17 Full-On Mode (Maximum Performance) ................................ 1-17 Active Mode (Moderate Power Savings) ................................. 1-18 Sleep Mode (High Power Savings) ......................................... 1-18 Deep Sleep Mode (Maximum Power Savings) ........................ 1-18 Hibernate State .................................................................... 1-19 Instruction Set Description ......................................................... 1-19 Development Tools ..................................................................... 1-20 MEMORY Memory Architecture .................................................................... 2-1 L1 Instruction SRAM ................................................................... 2-2 iv ADSP-BF59x Blackfin Processor Hardware Reference Contents L1 Instruction ROM ..................................................................... 2-3 L1 Data SRAM ............................................................................. 2-3 Boot ROM ................................................................................... 2-4 External Memory .......................................................................... 2-4 Processor-Specific MMRs .............................................................. 2-5 DTEST_COMMAND Register ............................................... 2-5 ITEST_COMMAND Register ................................................. 2-6 DMEM_CONTROL Register ................................................. 2-7 IMEM_CONTROL Register ................................................... 2-7 DCPLB_DATAx Registers ....................................................... 2-8 ICPLB_DATAx Registers ......................................................... 2-9 CHIP BUS HIERARCHY Chip Bus Hierarchy Overview ....................................................... 3-1 Interface Overview ........................................................................ 3-2 Internal Clocks ........................................................................ 3-3 Core Bus Overview .................................................................. 3-3 Peripheral Access Bus (PAB) ..................................................... 3-4 PAB Arbitration .................................................................. 3-5 PAB Agents (Masters, Slaves) ............................................... 3-5 PAB Performance ................................................................ 3-6 DMA Access Bus (DAB), DMA Core Bus (DCB) ..................... 3-6 DAB and DCB Arbitration ................................................. 3-6 DAB Bus Agents (Masters) .................................................. 3-7 DAB and DCB Performance ............................................... 3-8 ADSP-BF59x Blackfin Processor Hardware Reference v
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