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开关耦合电感准Z源逆变器

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Switched-Coupled-Inductor Quasi-Z-Source Inverter Hafiz Furqan Ahmed, Honnyong Cha, Member, IEEE, Su-Han Kim, and Heung-Geun Kim, Senior Member, IEEE, Abstract— Z-source inverters have become a research hotspot because of their single-stage buck-boost inversion ability, and better immunity to EMI noises. However, their boost gains are limited because of higher component-voltage stresses and poor output power quality, which results from the tradeoff between the shoot-through interval and the modulation index. To overcome these drawbacks, a new high-voltage boost impedance-source inverter called a switched-coupled-inductor quasi-Z-source inverter (SCL-qZSI) is proposed, which integrates a switched-capacitor (SC) and a three-winding switchedcoupled-inductor (SCL) into a conventional qZSI. The proposed SCL-qZSI adds only one capacitor and two diodes to a classical qZSI, and even with a turns ratio of 1, it has a stronger voltage boost-inversion ability than existing high-voltage boost (q)ZSI topologies. Therefore, compared with other (q)ZSIs for the same input and output voltages, the proposed SCL-qZSI utilizes higher modulation index with lower component-voltage stresses, has better spectral performance, and has a lower input inductor current ripple and flux density swing or, alternately, it can reduce the number of turns or size of the input inductor. The size of the coupled-inductor and the total number of turns required for three windings are comparable to those of a single inductor in (q)ZSIs. To validate its advantages, analytical, simulation, and experimental results are also presented. Index Terms— Boost ability, switched-coupled-inductor quasi-Z-source inverter (SCL-qZSI), switch-voltage stress, Z-source inverter. I. INTRODUCTION COnventional voltage and current source inverters (VSIs and CSIs, respectively) [1], [2], despite their huge demand in industrial applications such as adjustable speed drives, distributed power systems, and hybrid electric vehicles (HEVs), suffer from some serious drawbacks, which make them less attractive. In particular, VSIs can perform only buck operations, while CSIs can perform only voltage boost inversions. Therefore, in applications that require both buck and boost operations, an additional dc-dc converter is needed, resulting in a two-stage power conversion with a higher system cost and volume, low efficiency, and complex control [3]. Moreover, the shoot-through of power switches in one leg of a This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Science, ICT and future Planning(NRF-2013R1A2A2A01069038). H. F. Ahmed, H. Cha and S.-H. Kim are with the School of Energy Engineering, Kyungpook National University, 1370 Daegu, Korea (email: furqanhmd164@gmail.com; chahonny@knu.ac.kr; zetec7@nate.com). H.-G. Kim is with the Department of Electrical Engineering, Kyungpook National University, 1370 Daegu, Korea (email: hgkim@knu.ac.kr). VSI, or an open circuit in the case of a CSI, can damage the switching devices, and is therefore prohibited. To address these limitations, Peng [4] proposed an impedance-source inverter (ZSI), which advantageously used the shoot-through of inverter-bridge arms to boost the voltage, and therefore exhibits single-stage buck-boost voltage inversion ability; it also has better output waveform quality due to the elimination of the dead time. Because of its obvious advantages, the ZSI has become a research hotspot in power electronics, with the focus being on pulse-width modulation (PWM) schemes [5], [6], modeling and control [7] ,[8], applications [3], [9]-[12], ac-ac [13], [14] and dc-dc converters [15], [16], and other ZSI topologies [17]-[34]. In [23], modified ZSIs referred to as quasi-Z-source inverters (qZSIs) were proposed, and they have advantages over ZSIs, such as continuous input current, lower component-voltage stresses, and common ground between the dc-voltage source and the inverter-bridge. One of the serious drawbacks of all the existing (q)ZSIs is that despite having theoretically infinite gains, their practical boost ability is limited by higher component-voltage stresses and low output power quality due to their low modulation index M , which is caused by the tradeoff between the shoot-through duty-cycle D and M . M 1 D (1) B VPN 1 (2) Vin 1 2D The relationship between D and M for the sinusoidal PWM control strategy is given in (1), which shows that M can have a maximum value of 1.0 when no shoot-through is used, and it decreases linearly with an increase in D . The relationship between D and the boost factor B of the traditional ZSI [4] is given by (2), which shows that D can vary between 0 to 0.5, giving a boost factor B that ranges from 1.0 to a maximum value, respectively. However, for a noticeable increase in the voltage gain, the (q)ZSI would have to operate under a longer shoot-through interval with D close to 0.5 and, hence, from (1), it can be inferred that the lower value of M for (q)ZSI may be as low as 50 % of the maximum value of 1.0. This results in poor output power quality as the fundamental component of the ac output voltage decreases linearly with M , and the magnitudes of higher-frequency harmonics (total harmonic distortion THD) increase significantly. In addition, it leads to the poor utilization of the dc-link voltage, resulting in higher voltage stresses on both the active switches and the passive components. With a larger D , 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 2 the effect of the parasitic components becomes more prominent, and the voltage gain tends to decrease drastically [35]. Many attempts have already been made to improve the boost capability of (q)ZSIs. In [5], [6], modified PWM schemes, which are referred to as maximum boost control and constant boost control, were proposed with the attempt to increase the voltage boost ability. However, these techniques can boost the voltage to only a small extent, and therefore, improvements in the circuits of conventional (q)ZSIs is the only option to further extend their boost ability. In order to enhance the boost ability of dc-dc converters, various techniques that involve switched capacitors (SCs), switched inductors (SLs), hybrid SCs/SLs [36]-[40], voltage multiplier cells [41]-[43], voltage-lift circuits [44], [45], and coupled inductors [46]-[49] have already been employed. Some of the similar techniques have been applied to (q)ZSIs to improve their boost gains [24]-[34], while retaining their single-stage nature. For example, extended-boost ZSIs, in which two diodes, one inductor, and one capacitor are added to increase the boost factor by 1/ (1 D) in the case of a diode-assisted topology or, alternately, adds two capacitors, one diode and one inductor to increase the boost factor from 1/ (1 2D) to 1/ (1 3D) in case of capacitor assisted topology [24]. However, the boost capability remains limited, and its further enhancement requires the use of multiple extensions of the same components, which increases the volume and cost of the inverters, and effect of parasitic components becomes more severe. Transformer-based (q)ZSIs are proposed in [25], [26], called T-source and trans-Z-source inverters, which increase the transformer turns ratio to extend the boost ability, without adding extra components. However, to get higher boost, larger turns ratios are needed, which requires more isolation between the windings, which will in turn cause the leakage inductance to increase manifolds. This leakage inductance is directly in series with inverter-bridge without any snubber circuit in between and, therefore, large di / dt caused by the switching of the windings currents results in large switch-voltage spikes. In [27], [28], an inductor-capacitor-capacitor-transformer ZSI (LCCT-ZSI) and an improved trans-ZSI are proposed, each of which adds one inductor and one capacitor to improve the input current profiles of the trans-ZSI inverters. Cascaded and parallel operations of trans-ZSI inverters are proposed in [29], [30], where additional components are added to enhance the boost ability without the need to increase the turns ratio of the coupled-inductor. To enhance the boost ability, [31] proposes an SL-ZSI, which replaces the inductors in the ZSI [4] with the SL from [38]. A generalization of this SL-ZSI is investigated in [32], which used multiple SL cells to obtain a higher boost factor. However, these SL-ZSI inverters have a higher component count and various other drawbacks such as discontinuous input current, large inrush current at start up, and the absence of a common ground between the dc-voltage source and the inverter-bridge. An SL-qZSI is proposed in [33], and although it overcomes the above mentioned drawbacks associated with the SL-ZSI, but at the cost of reduced boost ability, which counters its other advantages. From the above discussions, it can be concluded that all of the existing high-boost (q)ZSIs use either several additional components or coupled inductors with a high turn ratio in order to obtain higher boosting gains. D1 C2 1 L1 N2 n N3 Din 1 C3 Vin N1 D2 C1 vPN Fig. 1. Proposed switched-coupled-inductor quasi-Z-source inverter (SCL-qZSI). In this paper, a combination of switched-capacitor (SC) and a three-winding switched-coupled-inductor (SCL) is applied to the qZSI, and the topology obtained is termed as SCL-qZSI. The proposed SCL-qZSI retains all of the advantages of the classical qZSI topology such as continuous input current and a common ground between the dc-voltage source and the inverter-bridge; it can also suppress the startup inrush current. The integration of the SC with SCL is beneficial in that it significantly enhances the boost ability of the SCL-qZSI with a smaller component count and lower turn ratio. The proposed inverter adds only one capacitor and two diodes to a classical qZSI, and even with a turns ratio of 1, its voltage boost ability B is higher than that of the existing high-voltage boost (q) ZSI and trans-ZSI, which were discussed before. Therefore, for the same input and output voltages, it can use lower D and higher M , which results in lower component-voltage stresses, a better output power quality, and a lower input current ripple. II. PROPOSED SCL-QZSI Fig. 1 shows the circuit of the proposed SCL-qZSI, which is obtained by replacing inductor L2 in the classical qZSI with a combination of SC ( C3 ) and a three-windings ( N1 , N2 , and N3 ) SCL (obtained by adding winding N2 and diode D2 to the SC and the two-winding SCL cell in [47]). The proposed inverter consists of three diodes ( Din , D1 , and D2 ), three capacitors ( C1 , C2 , and C3 ), an input inductor L1 , and an SCL with three windings ( N1 , N2 , and N3 ). Windings N1 and N2 have the same number of turns ( N1 N2 ), and the turn ratio of windings N3 to N1 (or N2 ) is n , ( n N3 / N1 N3 / N2 ). The main features of the proposed SCL-qZSI are as follows: It has a continuous input current, and common ground between the dc-voltage source and the inverter-bridge. It also provides startup inrush current suppression. Compared to the T-source inverter and the trans-ZSI, where the energy stored in the leakage inductance of the coupled-inductor only causes switch voltage spikes, the leakage inductance of the SCL is effectively utilized in two ways: (1) it is in series with switched-capacitor C3 and thus reduces the inrush current of C3 ; and (2) the energy stored in the leakage inductance is absorbed by capacitor C2 , and is, therefore, recycled without creating switch voltage spikes. 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3 It adds only one capacitor and two diodes to the qZSI, and even with a turn ratio of 1, it achieves a boost factor of 3 / (1 4D) , which is higher than that of the other existing (q)ZSIs and trans-ZSIs. For the same input and output voltage conditions, compared to other (q)ZSIs, it uses a lower shoot-through duty-cycle D , and consequently, a higher modulation index M , which results in lower component-voltage stresses and better output power quality. The total number of turns for the three windings and the size of the SCL are comparable to that of a single inductor in (q)ZSIs. In addition, for the same inductance value, the same core size and the same number of turns of input inductor L1 , the input inductor current ripple, and the flux density swing are smaller than those of other (q)ZSIs. Alternately, for the same input inductor current ripple and flux density swing, the number of turns or core size of the input inductor L1 in the proposed SCL-qZSI can be reduced. Iin L1 Vin iC 2 C2 Llk 2 iN 3 N2 Llk 3 iN 2 N3 iN1 N1 C3 Llk1 C1 iC1 Lm im ish I in L1 Din Vin C1 (a) iC 2 C2 Llk 2 iN 3 N Llk 3 2 iN 2 N3 iN1 N1 C3 iPN iC1 Llk1 Lm im A. Operation principle of the SCL-qZSI The operation of the proposed inverter is similar to that of the classical (q)ZSI, having shoot-through zero states in addition to the traditional six active states and two zero states. For analytical purposes, the operating states may be simplified as shoot-through and non-shoot-through states. The equivalent circuits of the proposed inverter during these states are given in Figs. 2(a) and (b), in which a detailed SCL model is shown, including the magnetizing inductance Lm . Moreover, because of the integrated SCL with trifilar windings, there also exist three small leakage inductances Llk1 , Llk2 , and Llk3 of windings N1 , N2 , and N3 , respectively. 1) Shoot-through state: Fig. 2(a) shows the equivalent circuit of the proposed inverter during the shoot-through state, which is obtained by simultaneously turning on both switches of a phase leg in the inverter-bridge. During this state, diode Din is off while diodes D1 and D2 are on. Windings N1 and N2 are charged by C1 in parallel, while C3 obtains energy from C1 through winding N3 , which significantly enhances the boost factor. In addition, the charging current of C3 is limited by the leakage inductance of the SCL. 2) Non-shoot-through state: This consists of six active states and two zero states of the main circuit, and the equivalent circuit during this state is shown in Fig. 2(b). During this state, diode Din is on while D1 and D2 are off. Capacitors C1 and C2 are charged, whereas the windings ( N1 , N2 , and N3 ) and capacitor C3 are in series and transfer energy to the main circuit. During this state, the energy stored in the leakage inductance of the SCL is absorbed by C2 , and it is, therefore, recycled without creating switch voltage spikes. B. Boost ability of the SCL-impedance network The boost factor B of the SCL-impedance network is the ratio of the dc-link voltage of the inverter-bridge VPN to the input dc-voltage Vin . The leakage inductance of the SCL is very (b) Fig. 2. Equivalent circuit of the proposed SCL-qZSI during (a) the shoot-through state, and (b) the non-shoot-through state. vL1 Vin VC1 VC 2 vN1 vN 2 vN 3 VC3 vL1 Vin VC1 VC 2 vN1 vN 2 vN 3 VC3 VPN (a) (b) Fig. 3. Simplified equivalent circuit of the proposed inverter during, (a) shoot-through state, and (b) non-shoot-through state. small because of the trifilar windings and similar to the derivation of the boost factor for trans-ZSIs [26]-[30]; the leakage inductance is ignored in order to derive the boost factor of the SCL-qZSI. Figs. 3(a) and 3(b) show the simplified equivalent circuits of the proposed inverter during the shoot-through and non-shoot-through states, respectively. By applying KVL to the equivalent circuit in Fig. 3(a) during the shoot-through state, we obtain VL1 Vin VC2 VN1 VN 2 VC1, VN 3 nVN1 (3) VC3 VN1 VN3 (n 1)VN1 (n 1)VC1 Similarly, in the non-shoot-through states, as shown in Fig. 3(b), applying KVL gives, VL1 VPN Vin VC2 VN1 VN 2 VN3 VC2 VC3 (4) VN1 VN 2 VN3 VPN VC1 VC3 Owing to magnetic coupling, VN3 nVN2 nVN1 , and because the capacitor acts as a voltage source which means also during non-shoot-through state, VC3 (n 1)VC1 . Therefore, (4) can be modified as follows: 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 4 VN1 VC 2 2 VC3 n (5) VN1 VPN n2 VC3 n 1 (6) If D is the shoot-through duty, then DT is the shoot-through time interval and (1 D)T is the non-shoot-through time interval. Applying the voltage-second balance condition on inductor L1 from (3) and (4), gives VPN 1 1 D (Vin VC2 ) (7) Similarly, applying the voltage-second balance condition on winding N1 from (3) and (5), we obtain VC3 (n 1)(1 D) n1 D VC 2 (8) Again, applying the voltage-second balance condition on winding N1 or N2 from (3) and (6), gives VC3 (n 1)(1 n 2 D) VPN (9) Substituting (8) into (9), yields n1 D VC2 n 2 VPN (10) From (7) and (10), the dc-link voltage across the inverter-bridge can be expressed as, VPN 1 n (3 1 n)D Vin (11) Therefore, the boost factor of the proposed SCL-qZSI is given by B VPN n 2 Vin 1 (3 n)D (12) When the turn ratio n is 1, the boost factor becomes B VPN 3 (13) Vin (1 4D) For the sake of comparison, Fig. 4 shows a plot of the boost factor B versus D for the proposed SCL-qZSI, SL-ZSI [31], SL-qZSI [33], and qZSI [23]. From this figure, it can be seen that the boost ability of the proposed inverter is significantly higher than that of the other topologies. (1) ProposedSCL-qZSI (2) SL-ZSI[31] (3) SL-qZSI [33] (4) qZSI [23] (1) (1) ProposedSCL-qZSI (2) SL-ZSI[31] (3) SL-qZSI [33] (4) qZSI [23] Voltage Gain, G (4) (3) (2) (1) Modulation Index, M Fig. 5. Plot of voltage gain G versus modulation index M. For the simple boost control method, the relation between the modulation index M and shoot-through duty ratio D can be expressed as, D T0 1 M (14) T Where, T0 and T are the shoot-through time interval and time period, respectively. By substituting (14) into (13), the boost factor B of the proposed SCL-qZSI can be expressed in terms of the modulation index M as, B 3 (15) 4M 3 The output peak phase voltage vˆph of the inverter is given by, vˆ ph MVPN 2 MBVin 2 (16) From (15) and (16), the voltage gain G ( MB ) of the proposed inverter can be written as, G vˆph 3M (17) (Vin / 2) 4M 3 Fig. 5 shows a plot of the voltage gain G versus the modulation index M for the proposed SCL-qZSI, SL-ZSI [31], SL-qZSI [33], and qZSI [23]. From Fig. 5, it can be observed that the voltage gain G increases with a decrease in the modulation index, and for the same modulation index M , the proposed inverter has a higher voltage conversion ratio than the other topologies. Therefore, for the same voltage conversion ratio, the proposed SCL-qZSI makes use of the larger modulation index. C. Comparison of switch voltage stresses Boost Factor, B Duty Ratio, D Fig. 4. Plot of boost factor B versus duty ratio D . (2) (3) (4) For all of the impedance-source inverters, the voltage stress across the active switches Vsw (the same as dc-link voltage VPN ) is directly proportional to the boost factor B , i.e., Vsw VPN BVin . While the boost factor B and M have inverse relation, G MB . As discussed in the previous section, to obtain the same voltage gain G , the proposed inverter utilizes a larger M , and therefore, requires a smaller boost factor B , which results in a lower switch voltage stressVsw . 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 5 Switch voltage stress, Vsw/Vin (1) ProposedSCL-qZSI (2) SL-qZSI [33] (3) qZSI [23] (3) (2) (1) Voltage Gain, G Fig. 6. Plot of switch voltage stress Vsw versus voltage gain G. Iin Vin Diode and impedence network il S Zl vl Fig. 7. Simplified and unified equivalent circuit of impedance-type inverters [31], [33] (i.e., the proposed SCL-qZSI, SL-qZSI, and qZSI). The switch voltage stress of the proposed inverter is given in terms of the voltage gain as, Vsw BVin 4G 3 3 Vin (18) The comparison of the switch voltage stress Vsw (normalized with the input dc-voltage Vin ) versus the voltage gain G for the proposed SCL-qZSI, SL-qZSI, and qZSI is shown in Fig. 6. From this figure, it can be noticed that the switch voltage stress of the proposed inverter is the lowest among the three topologies, which makes it the best candidate for applications with high voltage-boost inversion demands. D. Summary of the stresses In order to compare the stresses of the proposed SCL-qZSI, SL-qZSI, and qZSI, all the three topologies are represented by their simplified equivalent circuits, as shown in Fig. 7 [31], [33]. An inductive load impedance ( Zl Rl sL ) is connected in parallel with an active switch S . In Fig. 7, vl and il denote the instantaneous load voltage and current, respectively, whereas Vl and Il denote the average load voltage and current, respectively, during a switching cycle in steady-state. Applying the steady-state analysis method in [11], the current and voltage stresses of the components in the main power circuit are obtained. Table I illustrates the governing equations of the three inverters under the conditions of the same input voltage Vin and the same shoot-through duty ratio D . From the table, we see that the voltage and current stresses of the proposed SCL-qZSI are higher than those of the other two inverters because of its higher voltage boost ability B . In this case, the TABLE I STRESS COMPARISON IN THE SAME Vin AND D CASE qZSI [34] SL-qZSI [44] SCL-qZSI (n=1) VPN 1 1 2D Vin VC VC1 1 D 1 2D Vin VC2 1 D 2D Vin VD VDin VPN vˆ ph (1 D) VPN 2 1 D 1 2D D2 Vin VC1 1 1 D 2D D2 Vin VC2 2D 1 2D D2 Vin VDin VPN , VD1 VC1 VD2,3 D 1 D VC1 (1 D) VPN 2 1 3 4D Vin 1 D VC1 1 4D Vin 2D VC2 1 4D Vin , VC3 2VC1 VDin VPN VD1,2 2 3 VPN (1 D) VPN 2 Il (1 D) VPN Rl I Din Iin 1 D I sh 2Iin (1 D) VPN Rl Iin 1 D 3 1 D D Iin (1 D) VPN Rl Iin 1 D 2 4D 3D Iin IL IL1,2 Iin IL1 Iin I L2,3 Iin 1 D IL1 Iin, Im Iin iN1,2 SD . 1 2D 6D Iin iN3 SD.(2iN1,2 Im) iN1,2,3 SD.(Im / 3) TABLE II STRESS COMPARISON IN THE SAME Vin AND G CASE qZSI [34] SL-qZSI [44] SCL-qZSI (n=1) G 1 D 2G 1 G 2G2 2G 1 1 G G3 4G 3 VPN (2G 1)Vin (1 G) 1 2G 2 2G2 2G 1 2G2 2G 1 Vin 4G 3 3 Vin VC VC1 GVin VC2 (G 1)Vin VC1 (1 G)1 2G 2G 2 2G2 2G2 2G 2G 1 1 Vin VC1 G 3 Vin , VC3 2VC1 VC2 (G 1)Vin VC2 (G 1)Vin vˆ ph G Vin 2 G Vin 2 G Vin 2 Il G Vin Rl G Vin Rl G Vin Rl 2G 1 I Din G Iin 1G 1 G 2G2 2G 1 Iin 4G 3 3G Iin I sh 2Iin IL IL1,2 Iin 3 2G 1 2G2 2G 1 2G2 2G 1 Iin IL1 Iin IL2,3 1 (1 G)Iin 2G2 2G 1 4G 6 G 3 Iin IL1 Iin , Im Iin iN1,2 SD. 3 6 2G 2G Iin iN3 SD.(2iN1,2 Im) iN1,2,3 SD.(Im / 3) conventional qZSI has lower current and voltage stresses owing to its lower boost ability. In the equations given in Tables I and II, SD is the shoot-through switching function, having a value of 1 during the shoot-through state and 0 during the non-shoot-through state. However, when these three inverters are used in a particular application, the input dc-voltage Vin and the output peak phase voltage vˆph are fixed, and the voltage gain G is therefore 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 6 fixed. In this case, the voltage and current stresses in terms of the voltage gain G , are given in Table II for the three inverters. Table II shows that for the same input voltage Vin and voltage gain G , the proposed SCL-qZSI has lower voltage stress across (1) ProposedSCL-qZSI (2) SL-qZSI [33] (3) qZSI [23] Normalized iL1 or B active switches, capacitors, and diode Din . The current stress of (3) the main power circuit in the proposed inverter during shoot-through interval has a rise for the same load impedance (2) Rl , which shows that it has a stronger power processing capability at higher modulation index. (1) E) Input inductor current ripple, number of turns, and size comparison All of the three inverter topologies under consideration have an input inductor L1 connected in series with the dc-voltage source Vin , and therefore, they have a continuous input current Iin . For the same input dc-voltage Vin , output peak phase ac-voltage vˆph (for the same voltage gain G ) and load Rl , all three inverters have the same average input dc-current magnitude Iin , but different current ripple and flux density swings for the same input inductor value, the same number of turns, and the core size of inductor L1 . The equations used to calculate the input inductor current ripple iL1 , and the flux density swing B are given by, iL1 VL1 L DT (19) B VL1 DT (20) NAe where, VL1 is the voltage across input inductor L1 during the shoot-through interval, T is the switching time period, L is the inductance, N is the number of turns, and Ae is the core cross-sectional area of the input inductor. The inductor voltage stress during shoot-through for the three topologies is the same ( VL1 GVin ), and the switching time period T is also the same. Therefore, in the case of the same inductor value L , the same number of turns N , and the same cross-sectional area of the core Ae , the input inductor current ripple iL1 and flux density swing B of the three topologies are directly proportional to D . For the three inverters, D is given in terms of the voltage gain G as, DqZSI 1G 1 2G DSLqZSI G 2G2 2G 1 1G (21) DSCLqZSI 3G 3 4G Equations (19) and (20) can be rewritten as, L VL1 T iL1 D (22) Voltage Gain, G Fig. 8. Comparison of normalized input inductor current ripple and flux density swing. NAe B D (23) VL1 T By substituting the values of D from (21) into (22) and (23), the normalized input current ripple and flux density swing for the three inverters in terms of the voltage gain G , are plotted in Fig. 8. From this figure, it is evident that for the same voltage gain G , the proposed inverter has a much smaller input current ripple iL1 and flux density swing B (or core loss) compared to the SL-qZSI and qZSI. Alternately, for the same input inductor current ripple and flux density swing, the proposed SCL-qZSI can use an inductor with a smaller value, and hence, for the same current handling capability, it can either reduce the N or Ae of the input inductor L1 . F. Comparison of SCL design parameters The proposed inverter uses a three-windings SCL as compared to an SL consisting of two discrete inductors L2 and L3 in the SL-qZSI and inductor L2 in the qZSI. In this section, the SCL design parameters are considered to show that its size and the total number of turns for the three windings are comparable to that of a single inductor in the qZSI or SL-qZSI. 1) Flux density swing B consideration: During the shoot-through interval, the voltage stresses of windings N1 , N2 , and N3 of the SCL-qZSI, L2 or L3 of the SL-qZSI, and L2 of the qZSI are given in terms of the input voltage Vin and voltage gain G as, VL2 _ qZSI GVin VL2,3 _ SLqZSI (1 G)(1 2G 2G2 2G 1) 2G 2 2G2 2G 1 Vin (24) VN1,2,3 _ SCLqZSI G 3 Vin 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 7 Normalized B or iL (1) ProposedSCL-qZSI (2) SL-qZSI [33] (3) qZSI [23] (3) (2) (1) (N1im ) / 2 (N1im ) / 2 12 2 1 N1iN1 23 N1im N3iN 3 3 N2iN 2 21 32 (N1im ) / 2 (N1im ) / 2 12 2 1 21 N1im 23 N3iN 3 3 N2iN 2 N1iN1 32 Voltage Gain, G Fig. 9. Comparison of normalized flux density swing and inductor current ripple for SCL of the proposed inverter, inductor L2 or L3 in the SL-qZSI, and inductor L2 in the qZSI. From (24), it can be observed that the voltage stress of the SCL windings ( N1 , N2 , and N3 ) is less than half of that for inductors L2 or L3 in the SL-qZSI and is three times smaller than the voltage stress of L2 in the qZSI. Using the D values from (21), substituting the voltage stresses of the inductors from (24) into (23), and replacing N by N / 3 for the proposed inverter, the normalized flux density swing B for the SCL, L2 and L3 of the SL-qZSI, and L2 of the qZSI are plotted in Fig. 9. From Fig. 9, it can be observed that for the same core cross-sectional area Ae , and with the same total number of turns for the three windings ( N1 , N2 , and N3 ) as that for one inductor ( L2 or L3 for the SL-qZSI and L2 for the qZSI) in the other two inverters, the SCL of the proposed inverter has a lower B , and hence, a lower core loss. 2) Inductors current-handling capability requirement and core size comparison: The other parameter that needs to be determined and compared is the magnetizing current Im through the SCL for the same voltage gain G , compared to the current flowing through the inductors of the other two topologies under consideration. From the equivalent circuit of the proposed inverter during the shoot-through state (see Fig. 3(a)), windings N1 and N2 are in parallel and are directly coupled, whereas winding N3 is inversely coupled. Therefore, for n = 1, the magnetizing current Im is given by, Im iN1 iN 2 iN3 (25) The current flowing through capacitor C2 during the shoot-through state is given as, (a) (b) Fig. 10. Reluctance model of the SCL during (a) shoot-through state and (b) non-shoot-through state. Fig. 10(a) shows the equivalent reluctance model of the SCL during the shoot-through state when all three windings are placed in the center leg of an EE core. From Fig. 10(a), we see that the flux 3 produced by iN3 cancels a part of the sum of the fluxes ( 1 and 2 ) produced by iN1 and iN 2 and, hence, the resultant flux m produced by the magnetizing current Im is given by, N1Im N1iN1 N2iN2 N3iN3 (27) m 1 2 3 (28) During the shoot-through interval, winding currents and their corresponding fluxes are very large as compared to that in the non-shoot-through interval. Therefore, the partial cancellation of the fluxes during this interval is very important as it lowers down the net flux through the core, and, hence, decreases the inductor current-handling requirement. From the equivalent circuit of the proposed inverter during non-shoot-through interval shown in Fig. 3(b), it can be seen that all three windings are in series and are directly coupled. Therefore, for n = 1, the magnetizing current Im is given as, Im iN1 iN2 iN3 3iN1,2,3 (29) By applying KCL in the equivalent circuit during the shoot-through interval, the current flowing through capacitor C2 is given as, iC2 iN1,2,3 iPN (30) where, iPN is the current flowing through the inverter-bridge during the non-shoot-through state and is given by, iC2 Iin (26) iPN 1 4D 3(1 D) Iin (31) 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 8 During this interval, the fluxes created by the current flowing through each of the three windings are summed, as shown in Fig. 10(b), and the resultant flux produced by the magnetizing current Im is given by, N1Im N1iN1 N2iN2 N3iN3 3N1iN1,2,3 (32) m 1 2 3 1,2,3 (33) In this interval, the winding currents and their corresponding fluxes are very small as compared to those in the shoot-through-interval and, hence, their addition does not increase the inductor current-handling requirement. Applying charge balance (ampere-second) condition on capacitor C2 using (26) and (30), and substituting the value of iPN from (31), the winding current during the non-shoot-through interval is given as, iN1,2,3 Iin 3 (33) From (29) and (33), we can obtain Im Iin (34) Therefore, the magnetizing current Im of the SCL (current handling requirement) in the proposed inverter is the same as that of inductor L2 in the qZSI and is close to that of a single inductor L2 or L3 in the SL-qZSI. Using the D values from (21), substituting the voltage stresses of the inductors from (24) in (22), and replacing N by N / 3 and L by L / 3 for the proposed inverter, Fig. 9 also shows normalized inductor current ripple for the SCL of the proposed inverter, L2 and L3 of the SL-qZSI, and L2 of the qZSI. From Fig. 9, it can be noticed that with the magnetizing inductance Lm being 1/3 of that for a single inductor in the other two inverters, the SCL still has a lower current ripple. From the above discussion, it is clear that the magnetizing current Im (or current-handling requirement) of the SCL is Iin , which is the same as that of a single inductor in the other two inverters. Furthermore, with the same total number of turns for the three windings and with the magnetizing inductance Lm being 1/3 of the value for a single inductor in the other two inverters, the SCL has a lower magnetizing current ripple and flux density swing. Therefore, it can be concluded that even with three windings on one core, the SCL has a similar size and the total number of turns requirement as that of a single inductor in the other two inverters. III. COMPARISON OF COMPONENT STRESSES AND SIZES When comparing different power converter topologies, one of the important parameters is the size of passive components, especially inductors [50]. In this section, the stresses and sizes of components for the proposed SCL-qZSI are compared to those of the qZSI and SL-qZSI, under the condition of the same Vin and G. 1) The parameters which determine the size of the inductor are the current handling capability requirement, inductor current ripple iL and flux density swing B (core losses). All of the three inverters under comparison have the input inductor L1 with same current handling requirement Iin . From Fig. 8, for the same gain G, Ae and N, the L1 in the proposed inverter has much smaller B and iL compared with that of SL-qZSI and qZSI. For example at G=4.5, the B and iL of L1 for the qZSI and SL-qZSI are 4.4 and 3.4 times larger than that of L1 for the SCL-qZSI, respectively. Therefore, for the same B and iL , the Ae or N of the L1 for SCL-qZSI can be made 1/4.4 and 1/3.4 times smaller than that for L1 of the qZSI and SL-qZSI, respectively. The SCL in the proposed inverter and L2 in the qZSI have same current handling requirement Iin while each of the inductors L2 and L3 in SL-qZSI has a smaller current handling requirement Iin / (1 D) . However, for the same Ae and N ( N is the number of turns for L2 in qZSI, for single inductor L2 or L3 in SL-qZSI, and for all three windings N1 , N2 and N3 in SCL-qZSI ), the SCL has much lower B and iL for same G, compared with the inductors under comparison. Therefore, for the same B and iL , the size of the SCL-qZSI and single inductor L2 or L3 in the SL-qZSI are comparable (while SL-qZSI uses one extra inductor), and the L2 in qZSI will have larger size. From above discussion, it can be concluded that the total magnetic volume used in the proposed inverter can be made much smaller than that in qZSI and SL-qZSI. 2) The main parameters which determine the size of the capacitors are their voltage stress VC and maximum allowable voltage ripple vC which can be expressed as, vC iC C DT (35) where, C is the capacitance of the capacitor and iC is current flowing through capacitor during shoot-through interval DT. For the same G, the capacitor C2 in the three topologies have the same voltage stress VC and same current Iin flows through them during shoot-through. Therefore, the capacitance value required for C2 to maintain same vC for the three topologies are directly proportional to the shoot-through duty D. The proposed inverter because of its much smaller shoot-through duty utilization for the same G, requires much smaller C2 value to maintain the same vC than the capacitors C2 in qZSI and SL-qZSI. For example at G=4.5, the capacitance value for C2 in the SCL can be 1/4.4 and 1/3.4 times smaller than that for the qZSI and SL-qZSI, respectively, to get the same vC which results in much smaller size of C2 for the proposed inverter. The proposed inverter uses two 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 9 capacitors C1 and C3 instead of one capacitor C1 in other two inverters. However, the combined voltage stress of C1 and C3 in SCL-qZSI is equal to that of C1 in the qZSI inverter, with C1 and C3 voltage stresses being 1/3 and 2/3 of that for C1 in qZSI, respectively. The current flowing through C1 and C3 in SCL-qZSI are higher than that through C1 in shoot-through interval, but the shoot-through duty D for the SCL-qZSI is very small compared with that for qZSI at same gain G. At G=4.5, capacitance requirement for C1 and C3 in SCL-qZSI to maintain the same voltage ripple are roughly twice and less than that of C1 in qZSI, respectively. The voltage stress of C1 and C3 in SCL-qZSI are less than 1/2 and less than that of C1 in SL-qZSI, respectively. To maintain the same voltage ripple, the capacitance value for C1 in SCL-qZSI is slightly greater and for C3 is roughly half of that for C1 in SL-qZSI. From above discussion, it can be concluded that the total voltage stress of C1 , C2 and C3 in SCL-qZSI is same as that of C1 and C2 in qZSI, while the total capacitance requirement for the SCL-qZSI is close to that for qZSI. The total voltage stress of C1 , C2 and C3 in SCL-qZSI is larger than that for SL-qZSI and total capacitance requirement for both inverters is comparable. Therefore, the total capacitor sizes for the SCL-qZSI are close to that of qZSI and larger than that of SL-qZSI. 3) All of the three topologies have diode Din with voltage stress same as VPN (switch voltage stress) and current stress of Iin / (1 D) . For the same voltage gain G, the Din in SCL-qZSI has smaller voltage and current stresses than that in qZSI and SL-qZSI inverters. Compared to qZSI with only one diode Din , the SCL-qZSI uses two extra diodes D1 and D2 while the SL-qZSI uses three extra diodes D1 , D2 and D3 . The D1 and D2 in the SCL-qZSI have lower voltage stress compared to that of diode D3 , while higher voltage and current stress compared to that of D1 and D2 in SL-qZSI. The total size of diodes in proposed inverter will be larger than that of qZSI and will be smaller than that of SL-qZSI. TABLE III ELECTRICAL SPECIFICATIONS OF THE PROPOSED INVERTER Input voltage Output voltage Z-source capacitor ( C1 , C2 , C3 ) Z-source Inductor, L1 Coupled inductor ( n 1 ) LN1 , LN 2 , LN 3 Output filter inductor ( L f ) Output filter capacitor ( C f ) Switching frequency Three phase resistive load 82 Vdc 220 Vrms (line-line) 100μF 760μH Lm=200μH, Llk =.2μH 660μH 100μF 10 kHz 30 Ω/phase (a) IV. SIMULATION RESULTS In order to verify the aforementioned theoretical analysis, simulations are performed for the proposed SCL-qZSI to produce output ac-voltage of 220 Vrms (line-to-line) from the input dc-voltage of 82 V. The simulation parameters selected are L1=760μH , C1 C2 C3 100μH , and the magnetizing and leakage inductances of the SCL are 200μH and 0.2 μH , respectively. The simulation used a resistive load of 30 / phase and a switching frequency of 10 kHz. These simulation parameters are also listed in Table III. When simple boost control method is used, a voltage conversion ratio G of 4.5 is needed. From Table II, the values of the various parameters are determined as D 0.1, B 5 , VPN 410 V , (b) Fig. 11. Simulation results of the proposed SCL-qZSI for M = 0.9. From top to bottom: (a) Three-phase output line-to-line ac-voltage and input dc-voltage. (b) Capacitor voltages and dc-link voltage. VC1 123V ,VC2 287 V , and VC3 246 V . Fig. 11(a), (b), and Fig. 12(a), (b) and (c) show the simulation results of the proposed inverter for M 0.9 , which are identically matching to the theoretical analysis. The voltages across capacitors C1 , C2 , and C3 are boosted to 122 V, 285 V, and 244 V, respectively, whereas the dc-link voltage VPN is boosted to 406 V. For the same simulation parameters 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 10 Im Iin ish (a) iN 3 iN 2 iN1 (b) iDin iD1 iD2 (c) Fig. 12. Simulation results of the proposed SCL-qZSI for M = 0.9. (a) Input inductor current, magnetizing current, and shoot-through current. (b) Winding currents. (c) Diode currents. of the input voltage Vin and boost gain G , the qZSI and SL-qZSI require higher D values of 0.44 and 0.34, respectively. In addition, compared to the modulation index of 0.9 and switch voltage stress (same as VPN ) of 410 V in the case of the SCL-qZSI, the qZSI and SL-qZSI can only utilize smaller modulation index values of 0.56 and 0.66, which results in higher switch voltage stresses of 656 V and 561 V, respectively. V. COMPARISON OF INVERTERS LOSSES AND EFFICIENCY The main losses of the inverters comes from the core losses and winding resistance of inductors, the ESR of capacitors, the diode conduction losses, and conduction and switching losses of semiconductor switches. Among them, the most prominent are the semiconductor losses with switching losses being the largest [28]. The inductor losses consisting of core and winding resistance losses in the three inverters are the second major losses after that of the semiconductor switching devices. For the same core losses (same B and Ae ) of L1 in three topologies, the number of turns and consequently winding resistance of L1 in SCL-qZSI is 1/4.4 and 1/3.4 times smaller than that of the L1 in qZSI and SL-qZSI, respectively. Since the same current Iin flows through L1 in all three inverters which is also very high because of high gain operation, the winding loss in L1 of SCL-qZSI and voltage drop across it are very small compared to that in L1 of the other two inverters. The total winding resistance of all three windings of SCL in proposed inverter is 1/4.4 and 1/2.6 times smaller than that of the inductor L2 in qZSI and a single inductor L2 or L3 in the SCL-qZSI, for the same core losses. Although higher current flow through the windings of SCL during shoot-through compared to that in L2 of qZSI and in L2 and L3 of SL-qZSI, the rms current is still comparable because of much smaller shoot-through interval of SCL-qZSI for the same G. Also during shoot-through interval, all three windings are in parallel and therefore the resistance experienced by current flowing through each winding is 1/13.2 and 1/7.8 times smaller than that of L2 in qZSI and L2 or L3 in SL-qZSI, which make the winding losses much smaller in SCL. For the same ESR of capacitors, the SCL-qZSI has lower ESR conduction loss in C2 than that in other two inverters, comparable loss in C3 and higher loss in C1 compared to that in C1 of qZSI and SL-qZSI. However, the ESR of film capacitors is very small (only 2.5 m for 100 uF /450 V) compared to winding resistance of inductors and therefore, ESR losses of capacitors are negligible compared to the winding losses [24]. The SCL-qZSI has lower losses in Din than that in qZSI and SL-qZSI, and higher losses in D2 and D3 compared to that in D1 , D2 and D3 of the SL-qZSI. The proposed inverter because of its higher boost ability has smaller shoot-through interval and higher current which is equally divided in three switching legs. Because of the much smaller shoot-through interval of SCL-qZSI, the rms current through switches and hence their conduction losses are still comparable to that in qZSI and SL-qZSI. The major losses in all (q)ZSI and trans-ZSIs are switching losses consisting of switch turn on losses at the start of shoot-through interval and turn off losses at the end of shoot-through interval. Despite their lower switch voltage stress, the existing high gain (q)ZSI and trans-ZSI inverters have higher shoot-through current, resulting in higher switching losses. Even with the higher shoot-through current, however, the switching losses in the proposed inverter can be made much smaller compared to the existing (q)ZSI and trans-ZSI because of the following reasons; the proposed inverter has smaller switch voltage stresses and also compared to the (q)ZSI and SL-qZSI in which the shoot-through current from switches is instantaneously rises to 2Iin and 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 11 TABLE IV PARAMETERS FOR EFFICIENCY CALCULATION IGBT module (6-pack) SEMiX151GD066HDs Diodes CS240650, 150EBU04 Core Copper wire resistivity ( ) Capacitor EE 110/114/36 1.724 106Ω-cm MKP1848710454Y5 (100uF/450V) ESR=2.5 mΩ Iin (3 D) / (1 D) (ignoring inductor current ripple) causing high switching losses, the shoot-through current in the proposed inverter which is combination of L1 current Iin and three winding currents ( iN1 , iN 2 and iN3 ), has instantaneous rise to only Iin from L1 and then increase gradually because of sinusoidal winding currents ( iN1 , iN 2 and iN3 ) resulted from LC resonance between leakage inductance of SCL and capacitors C1 and C3 . By properly selecting the leakage inductance of SCL and capacitors C1 and C3 such that the positive half of sinusoidal current through windings is completed before the end of shoot-through interval, the total current through switches at the end of shoot-through interval will only be the current Iin from inductor L1 as the windings currents already become zero. Therefore, smaller voltage stress across switches together with smaller current Iin at the end of shoot-through interval results in much smaller turn-off switching losses for the SCL-qZSI, compared to the (q)ZSI and SL-qZSI in which higher turn off switching losses occur because of their larger switch voltage stresses and larger current ( 2Iin for qZSI and Iin (3 D) / (1 D) for SL-qZSI, ignoring the current ripple) at the end of shoot-through interval. In [51]-[53], the same LC resonance is used to significantly reduce the switching losses of the converter. The only difference in the operation of proposed inverter during shoot-through and the converters in [51]-[53], is that the dc offset current Iin from L1 is also added with the sinusoidal current through windings (which is same as resonant current in [51]-[53]). Moreover, the proposed inverter can use 600 V IGBT having three to four times smaller switching losses compared to 1200 V IGBT [50], which has to be used for qZSI and SL-qZSI. To compare the efficiencies of three inverters, the method adopted in [28], [54] is used and PSIM simulations are performed by considering some loss related parameters as given in Table IV. Same 600 V rating SEMiX151GD066HDs IGBT module is used for all three inverters as 1200 V IGBT was not available in device data base of PSIM , while diode CS240650 (600 V) is used for Din in three inverters and 150EBU04 (400 V) are used for D1 , D2 and D3 in SL-qZSI and SCL-qZSI inverters. All the inductors in three inverters are designed using same EE 110/114/36 ferrite core under the condition of same inductor current ripple iL and same core losses (same B ). All of the three inverters use the same 100uF/450V film capacitors. 92 90 88 Efficiency [%] 86 84 qZSI SCL-qZSI 82 SL-qZSI 80 78 0 1000 2000 3000 4000 5000 6000 Output Power [W] Fig. 13. Efficiency Comparison of the proposed inverter to the qZSI and SL-qZSI. The efficiencies of the three inverters are plotted in Fig. 13, which are simulated under the operating conditions given in table III. From Fig. 13, it can be seen that the proposed SCL-qZSI despite its higher shoot-through current, has higher efficiency than the qZSI and SL-qZSI. This is because of much smaller switching losses and inductor winding losses of the proposed inverter, both of which have major contribution to the overall inverter losses. VI. EXPERIMENTAL RESULTS A hardware prototype circuit of the proposed SCL-qZSI is fabricated using the same parameters as given in Table III, and a DSP-kit TMS320F28335 is used to generate control signals for simple boost control. A SCL was also fabricated by trifilar windings of copper foil on the center leg of the EE-7066 core using copper foil. Fig. 14(a), (b) and Fig. 15(a), (b) and (c) show the experimental results of the proposed SCL-qZSI when M 0.9 . All of these experimental results are in good agreement with the previous analytical and simulation results, and therefore, validate the strong boost ability of the proposed inverter. Fig. 16 shows the decrease in the dc-link VPN voltage across inverter-bridge with increase in the input current Iin , when the load power is increased. At Iin = 4 A, the measured VPN is 402 V compared to the calculated value of 410 V, and decreases to 385 V at Iin = 22 A. This reduction in gain is due to increased losses and voltage drop across components with load power. In this experiment non-optimized input inductor with high winding resistance is used, and 1200 V IGBT is used even for switch voltage stress of 410 V, as the 600 V IGBT was not available. Use of optimized inductor with less winding resistance and 600 V high current rated IGBT will decrease the overall losses and improve the voltage gain of the proposed inverter. 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 12 Vab,bc,ca [200V / div] i [100 A / div] sh Vin [50V / div] (a) t [4 ms / div] I [10 A / div] L1 (a) t [10s / div] VC2 [200V / div] V [200V / div] C3 V [200V / div] C1 i [50 A / div] N3 iN 2 [50 A / div] V [200V / div] PN t [20s / div] (b) Fig. 14. Experimental results of the proposed SCL-qZSI for M = 0.9. From top to bottom: (a) Three-phase output line-to-line ac-voltage and input dc-voltage. (b) Capacitors voltages and dc-link voltage. 400 300 SCL-qZSI (Calculated) SCL-qZSI (Measured) 200 i [50 A / div] N1 (b) i [20 A / div] Din i [100 A / div] D1 i [100 A / div] D2 t [10s / div] Vpn (V) 100 0 2 4 6 8 10 12 14 16 18 20 22 24 I in (A) Fig. 16. Variation of VPN with input dc current Iin for the proposed SCL-qZSI. t [10s / div] (c) Fig. 15. Experimental results of the proposed SCL-qZSI for M = 0.9. (a) Input inductor current and shoot-through current. (b) Winding currents. (c) Diode currents. VII. CONCLUSIONS This paper presented a new high-voltage boost impedance-source inverter called a switched-coupled-inductor quasi-Z-source inverter (SCL-qZSI), which can overcome the boost limitations of (q)ZSIs caused by higher component-voltage stresses and poor output power quality, which are attributed to the use of a lower modulation index. The proposed topology is obtained by combining the switched-capacitor SC and a three-winding SCL into the classical qZSI. The charging of the SC through the SCL significantly enhances the boost ability of the proposed inverter, without increasing the turn ratio of the SCL. The proposed inverter also retains all the advantages of the qZSI over the ZSI 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2015.2414971, IEEE Transactions on Power Electronics > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 13 topology, such as a continuous input current, common ground between the dc-voltage source and the inverter-bridge, lower voltage stress on capacitors, and startup inrush current suppression. The proposed SCL-qZSI adds only one capacitor and two diodes into the classical qZSI, and even with a turn ratio of 1, compared to the other (q)ZSI and SL-(q)ZSI topologies for the same input and output voltage conditions, it has a lower voltage stress on active switches and passive components, better output power quality, and reduced current ripple and flux density swing in the input inductor. The size of the coupled-inductor and the total number of turns for the three windings are also comparable to those of a single inductor in the qZSI and SL-qZSI topologies. The proposed inverter is best suited for applications that require a single-stage high step-up boost inversion of low dc-voltage sources such as fuel cells and PV systems. A comprehensive theoretical analysis of the proposed inverter was performed, and we successfully verified its performance through simulations and experimental results. REFERENCES [1] R. R. Errabelli, and P. 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Hafiz Furqan Ahmed received his B.S. in Electronics Engineering from National University of Sciences and Technology (NUST), Pakistan, in 2012. He is currently working towards his MS leading to Ph.D degree in the School of Energy Engineering, Kyungpook National University, Korea. His current research interests include high efficiency bidirectional dc-dc converters, Z-source inverters, and high reliable ac-ac converters without commutation problem. Research Institute (KERI), Changwon, Korea. In 2011, he joined Kyungpook National University as an Assistant Professor in the School of Energy Engineering. His current research interests include high power dc-dc converters, dc–ac inverters, Z-source inverters, and power conversion for electric vehicles and wind power generation. Su-Han Kim received his B.S. in Electrical Engineering from Hankyung University, Korea, in 2009, and his M.S. in Electronics Engineering from Kyungpook National University, Daegu, Korea, in 2012. He is currently working towards his Ph.D degree in the School of Energy Engineering at Kyungpook National University, Korea. His current research interests include novel power conversion system using MR fluid-gap variable inductor, Z-Source inverters, and dual-active bridge (DAB) dc-dc converters. Heung-Geun Kim (S’82–M’88–SM’12) was born in Korea in 1956. He received his B.S., M.S., and Ph.D. degrees in Electrical Engineering from Seoul National University in 1980, 1982 and 1988, respectively. Since 1984, he has been with the Department of Electrical Engineering at Kyungpook National University, where he is currently a full professor and the director of the Microgrid Research Center. He was a Visiting Scholar at the Department of Electrical and Computer Engineering in the University of Wisconsin-Madison from 1990 to 1991, and at the Department of Electrical Engineering in the Michigan State University, USA from 2006 to 2007. His current research interests are ac machine control, PV power generation, and micro-grid system. Honnyong Cha (S’08-M’10) received his B.S. and M.S. in Electronics Engineering from Kyungpook National University, Daegu, Korea, in 1999 and 2001, respectively, and his Ph.D. in Electrical Engineering from Michigan State University, East Lansing, Michigan, in 2009. From 2001 to 2003, he was a Research Engineer with the Power System Technology (PSTEK) Company, An-san, Korea. From 2010 to 2011, he worked as a Senior Researcher at the Korea Electrotechnology 0885-8993 (c) 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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