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CMOS 300 MSPS Quadrature Complete DDS AD9854 FEATURES 300 MHz internal clock rate FSK, BPSK, PSK, chirp, AM operation Dual integrated 12-bit digital-to-analog converters (DACs) Ultrahigh speed comparator, 3 ps rms jitter Excellent dynamic performance 80 dB SFDR at 100 MHz (±1 MHz) AOUT 4× to 20× programmable reference clock multiplier Dual 48-bit programmable frequency registers Dual 14-bit programmable phase offset registers 12-bit programmable amplitude modulation and on/off output shaped keying function Single-pin FSK and BPSK data interfaces PSK capability via input/output interface Linear or nonlinear FM chirp functions with single-pin frequency hold function Frequency-ramped FSK <25 ps rms total jitter in clock generator mode Automatic bidirectional frequency sweeping Sin(x)/x correction Simplified control interfaces 10 MHz serial 2- or 3-wire SPI compatible 100 MHz parallel 8-bit programming 3.3 V single supply Multiple power-down functions Single-ended or differential input reference clock Small, 80-lead LQFP or TQFP with exposed pad APPLICATIONS Agile, quadrature LO frequency synthesis Programmable clock generators FM chirp source for radar and scanning systems Test and measurement equipment Commercial and amateur RF exciters FUNCTIONAL BLOCK DIAGRAM REFERENCE CLOCK IN DIFF/SINGLE SELECT FSK/BPSK/HOLD DATA IN REF CLK BUFFER SYSTEM CLOCK 4× TO 20× REF CLK MULTIPLIER 48 48 MUX SYSTEM CLOCK 48 DEMUX 3 MUX DELTA FREQUENCY RATE TIMER MUX FREQUENCY ACCUMULATOR ACC 1 PHASE ACCUMULATOR ACC 2 PHASE-TOAMPLITUDE CONVERTER DDS CORE 17 17 14 MUX 12 I 12 Q INV DIGITAL MULTIPLIERS SINC 12 FILTER MUX 12-BIT I DAC MUX INV SINC FILTER MUX SYSTEM CLOCK MUX 12 12-BIT Q DAC OR CONTROL DAC SYSTEM CLOCK 12 12 PROGRAMMABLE AMPLITUDE AND RATE CONTROL ANALOG OUT DAC RSET ANALOG OUT ANALOG IN 2 48 SYSTEM 48 CLOCK DELTA FREQUENCY WORD FREQUENCY TUNING WORD 1 48 14 14 12 12 FREQUENCY FIRST 14-BIT SECOND 14-BIT I AND Q 12-BIT 12-BIT DC TUNING PHASE/OFFSET PHASE/OFFSET AM MODULATION CONTROL WORD 2 WORD WORD COMPARATOR CLOCK OUT BIDIRECTIONAL INTERNAL/EXTERNAL I/O UPDATE CLOCK MODE SELECT SYSTEM CLOCK INT CK Q D EXT PROGRAMMING REGISTERS SYSTEM ÷2 CLOCK AD9854 INTERNAL PROGRAMMABLE UPDATE CLOCK BUS I/O PORT BUFFERS OSK GND +VS READ WRITE SERIAL/ PARALLEL SELECT Figure 1. 6-BIT ADDRESS OR SERIAL PROGRAMMING LINES 8-BIT PARALLEL LOAD MASTER RESET 00636-001 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved. AD9854 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 Explanation of Test Levels ........................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 12 Typical Applications ....................................................................... 16 Theory of Operation ...................................................................... 19 Modes of Operation ................................................................... 19 Using the AD9854 .......................................................................... 29 Internal and External Update Clock ........................................ 29 On/Off Output Shaped Keying (OSK) .................................... 29 I and Q DACs.............................................................................. 30 Control DAC ............................................................................... 30 Inverse Sinc Function ................................................................ 31 REFCLK Multiplier .................................................................... 31 Programming the AD9854............................................................ 32 MASTER RESET ........................................................................ 32 Parallel I/O Operation ............................................................... 34 Serial Port I/O Operation.......................................................... 34 General Operation of the Serial Interface ................................... 36 Instruction Byte .......................................................................... 37 Serial Interface Port Pin Descriptions ..................................... 37 Notes on Serial Port Operation ................................................ 37 MSB/LSB Transfers......................................................................... 38 Control Register Description.................................................... 38 Power Dissipation and Thermal Considerations ....................... 40 Thermal Impedance................................................................... 40 Junction Temperature Considerations .................................... 40 Evaluation of Operating Conditions........................................ 41 Thermally Enhanced Package Mounting Guidelines ................ 41 Evaluation Board ............................................................................ 42 Evaluation Board Instructions.................................................. 42 General Operating Instructions ............................................... 42 Using the Provided Software .................................................... 44 Support ........................................................................................ 44 Outline Dimensions ....................................................................... 52 Ordering Guide .......................................................................... 52 Rev. E | Page 2 of 52 REVISION HISTORY 7/07—Rev. D to Rev. E Changed AD9854ASQ to AD9854ASVZ ....................... Universal Changed AD9854AST to AD9854ASTZ......................... Universal Changes to General Description .....................................................4 Changes to Table 1 Endnotes...........................................................7 Changes to Absolute Maximum Ratings Section..........................8 Changes to Power Dissipation Section.........................................40 Changes to Thermally Enhanced Package Mounting Guidelines Section......................................................................41 Changes to Figure 64 ......................................................................47 Changes to Outline Dimensions ...................................................52 Changes to Ordering Guide...........................................................52 11/06—Rev. C to Rev. D Changes to General Description Section .......................................4 Changes to Endnotes in the Power Supply Parameter .................7 Changes to Absolute Maximum Ratings Section..........................8 Added Endnotes to Table 2 ..............................................................8 Changes to Figure 50 ......................................................................29 Changes to Power Dissipation Section.........................................39 Changes to Figure 68 ......................................................................45 Updated Outline Dimensions........................................................51 Changes to Ordering Guide...........................................................51 9/04—Rev. B to Rev. C Updated Format.................................................................. Universal Changes to Table 1 ............................................................................4 Changes to Footnote 2 ......................................................................7 Changes to Explanation of Test Levels Section .............................8 Changes to Theory of Operation Section ....................................17 Changes to Single Tone (Mode 000) Section...............................17 AD9854 Changes to Ramped FSK (Mode 010) Section............................18 Changes to Basic FM Chirp Programming Steps Section .........23 Changes to Figure 50 ......................................................................27 Changes to Evaluation Board Operating Instructions Section.40 Changes to Filtered IOUT1 and the Filtered IOUT2 Section ...41 Changes to Using the Provided Software Section.......................42 Changes to Figure 68 ......................................................................45 Changes to Figure 69 ......................................................................46 Updated Outline Dimensions........................................................50 Changes to Ordering Guide...........................................................50 3/02—Rev. A to Rev. B Updated Format ................................................................. Universal Renumbered Figures and Tables ...................................... Universal Changes to General Description Section.......................................1 Changes to Functional Block Diagram ..........................................1 Changes to Specifications Section ..................................................4 Changes to Absolute Maximum Ratings Section .........................7 Changes to Pin Function Descriptions ..........................................8 Changes to Figure 3 ........................................................................10 Deleted two Typical Performance Characteristics Graphs........11 Changes to Inverse SINC Function Section ................................28 Changes to Differential REFCLK Enable Section.......................28 Changes to Figure 52 ......................................................................30 Changes to Parallel I/O Operation Section .................................32 Changes to General Operation of the Serial Interface Section .33 Changes to Figure 57 ......................................................................34 Replaced Operating Instructions Section ....................................40 Changes to Figure 68 ......................................................................44 Changes to Figure 69 ......................................................................45 Changes to Customer Evaluation Board Table............................46 Rev. E | Page 3 of 52 AD9854 GENERAL DESCRIPTION The AD9854 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with two internal high speed, high performance quadrature DACs to form a digitally programmable I and Q synthesizer function. When referenced to an accurate clock source, the AD9854 generates highly stable, frequency-phase, amplitude-programmable sine and cosine outputs that can be used as an agile LO in communications, radar, and many other applications. The innovative high speed DDS core of the AD9854 provides 48-bit frequency resolution (1 μHz tuning resolution with 300 MHz SYSCLK). Maintaining 17 bits ensures excellent SFDR. The circuit architecture of the AD9854 allows the generation of simultaneous quadrature output signals at frequencies up to 150 MHz, which can be digitally tuned at a rate of up to 100 million new frequencies per second. The sine wave output (externally filtered) can be converted to a square wave by the internal comparator for agile clock generator applications. The device provides two 14-bit phase registers and a single pin for BPSK operation. For higher-order PSK operation, the I/O interface can be used for phase changes. The 12-bit I and Q DACs, coupled with the innovative DDS architecture, provide excellent wideband and narrow-band output SFDR. The Q DAC can also be configured as a user-programmable control DAC if the quadrature function is not desired. When configured with the comparator, the 12-bit control DAC facilitates static duty cycle control in high speed clock generator applications. Two 12-bit digital multipliers permit programmable amplitude modulation, on/off output shaped keying, and precise amplitude control of the quadrature output. Chirp functionality is also included to facilitate wide bandwidth frequency sweeping applications. The programmable 4× to 20× REFCLK multiplier circuit of the AD9854 internally generates the 300 MHz system clock from an external lower frequency reference clock. This saves the user the expense and difficulty of implementing a 300 MHz system clock source. Direct 300 MHz clocking is also accommodated with either singleended or differential inputs. Single-pin conventional FSK and the enhanced spectral qualities of ramped FSK are supported. The AD9854 uses advanced 0.35 μm CMOS technology to provide a high level of functionality on a single 3.3 V supply. The AD9854 is pin-for-pin compatible with the AD9852 singletone synthesizer. It is specified to operate over the extended industrial temperature range of −40°C to +85°C. Rev. E | Page 4 of 52 AD9854 SPECIFICATIONS VS = 3.3 V ± 5%, RSET = 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASVZ, external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9854ASTZ, unless otherwise noted. Table 1. Parameter REFERENCE CLOCK INPUT CHARACTERISTICS1 Internal System Clock Frequency Range REFCLK Multiplier Enabled REFCLK Multiplier Disabled External Reference Clock Frequency Range REFCLK Multiplier Enabled REFCLK Multiplier Disabled Duty Cycle Input Capacitance Input Impedance Differential Mode Common-Mode Voltage Range Minimum Signal Amplitude2 Common-Mode Range VIH (Single-Ended Mode) VIL (Single-Ended Mode) DAC STATIC OUTPUT CHARACTERISTICS Output Update Speed Resolution I and Q Full-Scale Output Current I and Q DAC DC Gain Imbalance3 Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Impedance Voltage Compliance Range DAC DYNAMIC OUTPUT CHARACTERISTICS I and Q DAC Quadrature Phase Error DAC Wideband SFDR 1 MHz to 20 MHz AOUT 20 MHz to 40 MHz AOUT 40 MHz to 60 MHz AOUT 60 MHz to 80 MHz AOUT 80 MHz to 100 MHz AOUT 100 MHz to 120 MHz AOUT DAC Narrow-Band SFDR 10 MHz AOUT (±1 MHz) 10 MHz AOUT (±250 kHz) 10 MHz AOUT (±50 kHz) 41 MHz AOUT (±1 MHz) 41 MHz AOUT (±250 kHz) 41 MHz AOUT (±50 kHz) 119 MHz AOUT (±1 MHz) 119 MHz AOUT (±250 kHz) 119 MHz AOUT (±50 kHz) Test AD9854ASVZ AD9854ASTZ Temp Level Min Typ Max Min Typ Max Unit Full VI Full VI Full VI Full VI 25°C IV 25°C IV 25°C IV 25°C IV 25°C IV 25°C IV 25°C IV Full I 25°C IV 25°C IV 25°C I 25°C I 25°C I 25°C I 25°C I 25°C IV 25°C I 25°C IV 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 20 300 20 200 MHz DC 300 DC 200 MHz 5 75 5 50 MHz DC 300 DC 200 MHz 45 50 55 45 50 55 % 3 3 pF 100 100 kΩ 400 1.6 1.75 1.9 2.3 1 400 1.6 1.75 1.9 2.3 1 mV p-p V V V 300 200 MSPS 12 12 Bits 5 10 20 5 10 20 mA −0.5 +0.15 +0.5 −0.5 +0.15 +0.5 dB −6 +2.25 −6 +2.25 % FS 2 2 μA 0.3 1.25 0.3 1.25 LSB 0.6 1.66 0.6 1.66 LSB 100 100 kΩ −0.5 +1.0 −0.5 +1.0 V 0.2 1 0.2 1 Degrees 58 58 dBc 56 56 dBc 52 52 dBc 48 48 dBc 48 48 dBc 48 48 dBc 83 83 dBc 83 83 dBc 91 91 dBc 82 82 dBc 84 84 dBc 89 89 dBc 71 71 dBc 77 77 dBc 83 83 dBc Rev. E | Page 5 of 52 AD9854 Parameter Residual Phase Noise (AOUT = 5 MHz, External Clock = 30 MHz REFCLK Multiplier Engaged at 10×) 1 kHz Offset 10 kHz Offset 100 kHz Offset (AOUT = 5 MHz, External Clock = 300 MHz, REFCLK Multiplier Bypassed) 1 kHz Offset 10 kHz Offset 100 kHz Offset PIPELINE DELAYS4, 5, 6 DDS Core (Phase Accumulator and Phase-to-Amp Converter) Frequency Accumulator Inverse Sinc Filter Digital Multiplier DAC I/O Update Clock (Internal Mode) I/O Update Clock (External Mode) MASTER RESET DURATION COMPARATOR INPUT CHARACTERISTICS Input Capacitance Input Resistance Input Current Hysteresis COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage, High-Z Load Logic 0 Voltage, High-Z Load Output Power, 50 Ω Load, 120 MHz Toggle Rate Propagation Delay Output Duty Cycle Error7 Rise/Fall Times, 5 pF Load Toggle Rate, High-Z Load Toggle Rate, 50 Ω Load Output Cycle-to-Cycle Jitter8 COMPARATOR NARROW-BAND SFDR9 10 MHz (±1 MHz) 10 MHz (±250 MHz) 10 MHz (±50 MHz) 41 MHz (±1 MHz) 41 MHz (±250 MHz) 41 MHz (±50 MHz) 119 MHz (±1 MHz) 119 MHz (±250 MHz) 119 MHz (±50 MHz) CLOCK GENERATOR OUTPUT JITTER9 5 MHz AOUT 40 MHz AOUT 100 MHz AOUT Test AD9854ASVZ AD9854ASTZ Temp Level Min Typ Max Min Typ Max Unit 25°C V 140 25°C V 138 25°C V 142 140 dBc/Hz 138 dBc/Hz 142 dBc/Hz 25°C V 25°C V 25°C V 25°C IV 25°C IV 25°C IV 25°C IV 25°C IV 25°C IV 25°C IV 25°C IV 25°C V 25°C IV 25°C I 25°C IV Full VI Full VI 25°C I 25°C IV 25°C I 25°C V 25°C IV 25°C IV IV 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 25°C V 142 142 dBc/Hz 148 148 dBc/Hz 152 152 dBc/Hz 33 26 16 9 1 2 3 10 33 26 16 9 1 2 3 10 SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles 3 500 ±1 ±5 10 20 3 500 ±1 ±5 10 20 pF kΩ μA mV p-p 3.1 9 11 3 −10 ±1 2 300 350 375 400 3.1 0.16 9 11 3 +10 −10 ±1 2 300 350 375 400 4.0 V 0.16 V dBm ns +10 % ns MHz MHz 4.0 ps rms 84 84 dBc 84 84 dBc 92 92 dBc 76 76 dBc 82 82 dBc 89 89 dBc 73 dBc 73 dBc 83 dBc 23 23 ps rms 12 12 ps rms 7 7 ps rms Rev. E | Page 6 of 52 AD9854 Parameter PARALLEL I/O TIMING CHARACTERISTICS tASU (Address Setup Time to WR Signal Active) tADHW (Address Hold Time to WR Signal Inactive) tDSU (Data Setup Time to WR Signal Inactive) tDHD (Data Hold Time to WR Signal Inactive) tWRLOW (WR Signal Minimum Low Time) tWRHIGH (WR Signal Minimum High Time) tWR (Minimum WR Time) tADV (Address to Data Valid Time) tADHR (Address Hold Time to RD Signal Inactive) tRDLOV (RD Low to Output Valid) tRDHOZ (RD High to Data Three-State) SERIAL I/O TIMING CHARACTERISTICS tPRE (CS Setup Time) tSCLK (Period of Serial Data Clock) tDSU (Serial Data Setup Time) tSCLKPWH (Serial Data Clock Pulse Width High) tSCLKPWL (Serial Data Clock Pulse Width Low) tDHLD (Serial Data Hold Time) tDV (Data Valid Time) CMOS LOGIC INPUTS10 Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance POWER SUPPLY11, 15 VS Current11, 12, 15 VS Current11, 13, 15 VS Current14 PDISS11, 12, 15 PDISS11, 13, 15 PDISS14 PDISS Power-Down Mode Test AD9854ASVZ AD9854ASTZ Temp Level Min Typ Max Min Typ Max Unit Full IV Full IV Full IV Full IV Full IV Full IV Full IV Full V Full IV Full IV Full IV 8.0 7.5 8.0 7.5 ns 0 0 ns 3.0 1.6 3.0 1.6 ns 0 0 ns 2.5 1.8 2.5 1.8 ns 7 7 ns 10.5 10.5 ns 15 15 15 15 ns 5 5 ns 15 15 ns 10 10 ns Full IV 30 30 ns Full IV 100 100 ns Full IV 30 30 ns Full IV 40 40 ns Full IV 40 40 ns Full IV 0 0 ns Full V 30 30 ns 25°C I 25°C I 25°C IV 25°C IV 25°C V 2.2 3 2.2 0.8 ±5 ±5 3 V 0.8 V ±12 μA ±12 μA pF 25°C I 25°C I 25°C I 25°C I 25°C I 25°C I 25°C I 1050 710 600 3.475 2.345 1.975 1 1210 816 685 4.190 2.825 2.375 50 755 865 mA 515 585 mA 435 495 mA 2.490 3.000 W 1.700 2.025 W 1.435 1.715 W 1 50 mW 1 The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine wave centered at one-half the applied VDD or a 3 V TTL-level pulse input. 2 An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins. 3 The I and Q gain imbalance is digitally adjustable to less than 0.01 dB. 4 Pipeline delays of each individual block are fixed; however, if the first eight MSBs of a tuning word are 0s, the delay appears longer. This is due to insufficient phase accumulation per system clock period to produce enough LSB amplitude to the DAC. 5 If a feature such as the inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount. 6 The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks. 7 Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold. 8 Represents the comparator’s inherent cycle-to-cycle jitter contribution. The input signal is a 1 V, 40 MHz square wave, and the measurement device is a Wavecrest DTS-2075. 9 Comparator input originates from the analog output section via the external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 Ω. 10 Avoid overdriving digital inputs. (Refer to the equivalent circuits in Figure 3.) 11 If all device functions are enabled, it is not recommended to simultaneously operate the device at the maximum ambient temperature of 85°C and at the maximum internal clock frequency. This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal Considerations section for derating and thermal management information. 12 All functions engaged. 13 All functions except inverse sinc engaged. 14 All functions except inverse sinc and digital multipliers engaged. 15 In most cases, disabling the inverse sinc filter reduces power consumption by approximately 30%. Rev. E | Page 7 of 52 AD9854 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature VS Digital Inputs Digital Output Current Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Maximum Clock Frequency (ASVZ) Maximum Clock Frequency (ASTZ) Rating 150°C 4V −0.7 V to +VS 5 mA −65°C to +150°C −40°C to +85°C 300°C 300 MHz 200 MHz Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The heat sink of the AD9854ASVZ 80-lead TQFP package must be soldered to the PCB. Table 3. Thermal Characteristic θJA (0 m/sec airflow)1, 2, 3 θJMA (1.0 m/sec airflow)2, 3, 4, 5 θJMA (2.5 m/sec airflow)2, 3, 4, 5 ΨJT1, 2 θJC6, 7 TQFP 16.2°C/W 13.7°C/W 12.8°C/W 0.3°C/W 2.0°C/W LQFP 38°C/W 1 Per JEDEC JESD51-2 (heat sink soldered to PCB). 2 2S2P JEDEC test board. 3 Values of θJA are provided for package comparison and PCB design considerations. 4 Per JEDEC JESD51-6 (heat sink soldered to PCB). 5 Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the more metal that is directly in contact with the package leads from metal traces through holes, ground, and power planes, the more θJA is reduced. 6 Per MIL-Std 883, Method 1012.1. 7 Values of θJC are provided for package comparison and PCB design considerations when an external heat sink is required. To determine the junction temperature on the application PCB use the following equation: TJ = Tcase + (ΨJT × PD) where: TJ is the junction temperature expressed in degrees Celsius. Tcase is the case temperature expressed in degrees Celsius, as measured by the user at the top center of the package. ΨJT = 0.3°C/W. PD is the power dissipation (PD); see the Power Dissipation and Thermal Considerations section for the method to calculate PD. EXPLANATION OF TEST LEVELS Table 3. Test Level I III IV V VI Description 100% production tested. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. Devices are 100% production tested at 25°C and guaranteed by design and characterization testing for industrial operating temperature range. ESD CAUTION Rev. E | Page 8 of 52 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9854 DVDD DVDD DGND DGND DGND DGND DVDD DVDD DGND MASTER RESET S/P SELECT REFCLK REFCLK AGND AGND AVDD DIFF CLK ENABLE NC AGND PLL FILTER 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 DVDD 9 DVDD 10 DGND 11 DGND 12 NC 13 A5 14 A4 15 A3 16 A2/IO RESET 17 A1/SDO 18 A0/SDIO 19 I/O UD CLK 20 PIN 1 INDICATOR AD9854 TOP VIEW (Not to Scale) 60 AVDD 59 AGND 58 NC 57 NC 56 DAC RSET 55 DACBP 54 AVDD 53 AGND 52 IOUT2 51 IOUT2 50 AVDD 49 IOUT1 48 IOUT1 47 AGND 46 AGND 45 AGND 44 AVDD 43 VINN 42 VINP 41 AGND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 WR/SCLK RD/CS DVDD DVDD DVDD DGND DGND DGND FSK/BPSK/HOLD OSK AVDD AVDD AGND AGND NC VOUT AVDD AVDD AGND AGND 00636-002 NC = NO CONNECT Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic 1 to 8 D7 to D0 9, 10, 23, 24, 25, 73, 74, 79, 80 DVDD 11, 12, 26, 27, 28, DGND 72, 75 to 78 13, 35, 57, 58, 63 NC 14 to 16 A5 to A3 17 A2/IO RESET 18 A1/SDO 19 A0/SDIO Description 8-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode. Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND and DGND. Connections for the Digital Circuitry Ground Return. Same potential as AGND. No Internal Connection. Parallel Address Inputs for Program Registers (Part of 6-Bit Parallel Address Inputs for Program Register, A5:A0). Used only in parallel programming mode. Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program Register, A5:A0)/IO Reset. A2 is used only in parallel programming mode. IO RESET is used when the serial programming mode is selected, allowing an IO RESET of the serial communication bus that is unresponsive due to improper programming protocol. Resetting the serial bus in this manner does not affect previous programming, nor does it invoke the default programming values listed in Table 8. Active high. Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program Register, A5:A0)/Unidirectional Serial Data Output. A1 is used only in parallel programming mode. SDO is used in 3-wire serial communication mode when the serial programming mode is selected. Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program Register, A5:A0)/Bidirectional Serial Data I/O. A0 is used only in parallel programming mode. SDIO is used in 2-wire serial communication mode. Rev. E | Page 9 of 52 AD9854 Pin No. 20 21 22 29 Mnemonic I/O UD CLK WR/SCLK RD/CS FSK/BPSK/HOLD 30 OSK 31, 32, 37, 38, 44, 50, 54, 60, 65 33, 34, 39, 40, 41, 45, 46, 47, 53, 59, 62, 66, 67 36 AVDD AGND VOUT 42 VINP 43 VINN 48 IOUT1 49 IOUT1 51 IOUT2 52 IOUT2 55 DACBP 56 DAC RSET 61 PLL FILTER 64 DIFF CLK ENABLE 68 REFCLK 69 REFCLK 70 S/P SELECT 71 MASTER RESET Description Bidirectional I/O Update Clock. Direction is selected in control register. If this pin is selected as an input, a rising edge transfers the contents of the I/O port buffers to the programming registers. If I/O UD CLK is selected as an output (default), an output pulse (low to high) with a duration of eight system clock cycles indicates that an internal frequency update has occurred. Write Parallel Data to I/O Port Buffers. Shared function with SCLK. Serial clock signal associated with the serial programming bus. Data is registered on the rising edge. This pin is shared with WR when the parallel mode is selected. The mode is dependent on Pin 70 (S/P SELECT). Read Parallel Data from Programming Registers. Shared function with CS. Chip-select signal associated with the serial programming bus. Active low. This pin is shared with RD when the parallel mode is selected. Multifunction pin according to the mode of operation selected in the programming control register. In FSK mode, logic low selects F1 and logic high selects F2. In BPSK mode, logic low selects Phase 1 and logic high selects Phase 2. In chirp mode, logic high engages the hold function, causing the frequency accumulator to halt at its current location. To resume or commence chirp mode, logic low is asserted. Output Shaped Keying. Must first be selected in the programming control register to function. A logic high causes the I and Q DAC outputs to ramp up from zero-scale to full-scale amplitude at a preprogrammed rate. Logic low causes the full-scale output to ramp down to zero scale at the preprogrammed rate. Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND and DGND. Connections for Analog Circuitry Ground Return. Same potential as DGND. Noninverted Output of the Internal High Speed Comparator. Designed to drive 10 dBm to 50 Ω load as well as standard CMOS logic levels. Voltage Input Positive. The noninverting input of the internal high speed comparator. Voltage Input Negative. The inverting input of the internal high speed comparator. Unipolar Current Output of I, or the Cosine DAC. (Refer to Figure 3.) Complementary Unipolar Current Output of I, or the Cosine DAC. Complementary Unipolar Current Output of Q, or the Sine DAC. Unipolar Current Output of Q, or the Sine DAC. This DAC can be programmed to accept external 12-bit data in lieu of internal sine data, allowing the AD9854 to emulate the AD9852 control DAC function. Common Bypass Capacitor Connection for Both I and Q DACs. A 0.01 μF chip capacitor from this pin to AVDD improves harmonic distortion and SFDR slightly. No connect is permissible, but results in a slight degradation in SFDR. Common Connection for Both I and Q DACs. Used to set the full-scale output current. RSET = 39.9/IOUT. Normal RSET range is from 8 kΩ (5 mA) to 2 kΩ (20 mA). Connection for the External Zero-Compensation Network of the REFCLK Multiplier’s PLL Loop Filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF capacitor. The other side of the network should be connected to AVDD as close as possible to Pin 60. For optimum phase noise performance, the REFCLK multiplier can be bypassed by setting the bypass PLL bit in Control Register 1E hex. Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK and REFCLK (Pin 69 and Pin 68, respectively). Complementary (180° Out of Phase) Differential Clock Signal. User should tie this pin high or low when single-ended clock mode is selected. Same signal levels as REFCLK. Single-Ended Reference Clock Input (CMOS Logic Levels Required) or One of Two Differential Clock Signals. In differential reference clock mode, both inputs can be CMOS logic levels or have greater than 400 mV p-p square or sine waves centered about 1.6 V dc. Selects serial programming mode (logic low) or parallel programming mode (logic high). Initializes the serial/parallel programming bus to prepare for user programming; sets programming registers to a do-nothing state defined by the default values listed in Table 8. Active on logic high. Asserting this pin is essential for proper operation upon power-up. Rev. E | Page 10 of 52 AVDD AVDD AD9854 DVDD AVDD DIGITAL IN 00636-003 IOUT IOUTB MUST TERMINATE OUTPUTS FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING. A. DAC OUTPUTS COMPARATOR OUT VINP/ VINN B. COMPARATOR OUTPUT C. COMPARATOR INPUT Figure 3. Equivalent Input and Output Circuits AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS. D. DIGITAL INPUTS Rev. E | Page 11 of 52 AD9854 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9854 from 19.1 MHz to 119.1 MHz fundamental output, reference clock = 30 MHz, REFCLK multiplier = 10×. Each graph is plotted from 0 MHz to 150 MHz (Nyquist). 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 15MHz/ STOP 150MHz Figure 4. Wideband SFDR, 19.1 MHz 00636-004 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 15MHz/ STOP 150MHz Figure 7. Wideband SFDR, 79.1 MHz 00636-007 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 15MHz/ STOP 150MHz Figure 5. Wideband SFDR, 39.1 MHz 00636-005 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 15MHz/ STOP 150MHz Figure 8. Wideband SFDR, 99.1 MHz 00636-008 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 15MHz/ STOP 150MHz Figure 6. Wideband SFDR, 59.1 MHz 00636-006 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 15MHz/ STOP 150MHz Figure 9. Wideband SFDR, 119.1 MHz 00636-009 Rev. E | Page 12 of 52 AD9854 Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare the noise floor of Figure 11 and Figure 12 with that of Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 12 is a direct result of sampling the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider bandwidth, which effectively lowers the noise floor. 0 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 00636-012 00636-010 –100 CENTER 39.1MHz 100kHz/ SPAN 1MHz Figure 10. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW, 300 MHz REFCLK with REFCLK Multiplier Bypassed –100 CENTER 39.1MHz 100kHz/ SPAN 1MHz Figure 13. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW, 30 MHz REFCLK with REFCLK Multiplier = 10× 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 39.1MHz 5kHz/ SPAN 50kHz Figure 11. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, 300 MHz REFCLK with REFCLK Multiplier Bypassed 00636-011 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 39.1MHz 5kHz/ SPAN 50kHz Figure 14. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, 30 MHz REFCLK with REFCLK Multiplier = 10× 00636-013 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 39.1MHz 5kHz/ SPAN 50kHz Figure 12. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, 100 MHz REFCLK with REFCLK Multiplier Bypassed 00636-014 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 39.1MHz 5kHz/ SPAN 50kHz Figure 15. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, 10 MHz REFCLK with REFCLK Multiplier = 10× 00636-015 Rev. E | Page 13 of 52 00636-019 AD9854 Figure 16 and Figure 17 show the narrow-band performance of the AD9854 when operating with a 200 MHz reference clock with the REFCLK multiplier bypassed vs. a 20 MHz reference clock and the REFCLK multiplier enabled at 10×. 0 –90 –10 –100 –20 –30 –110 AOUT = 80MHz 00636-016 PHASE NOISE (dBc/Hz) –40 –120 –50 –130 –60 –70 –80 –90 –100 CENTER 39.1MHz 5kHz/ SPAN 50kHz Figure 16. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, 200 MHz REFCLK with REFCLK Multiplier Bypassed –140 –150 AOUT = 5MHz –160 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 19. Residual Phase Noise, 30 MHz REFCLK with REFCLK Multiplier = 10× 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 39.1MHz 5kHz/ SPAN 50kHz Figure 17. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW, 20 MHz REFCLK with REFCLK Multiplier = 10× –100 –110 –120 –130 AOUT = 80MHz –140 –150 –160 AOUT = 5MHz –170 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 18. Residual Phase Noise, 300 MHz REFCLK with REFCLK Multiplier Bypassed 00636-018 SUPPLY CURRENT (mA) 00636-017 SFDR (dBc) 55 54 53 52 51 50 49 48 0 5 10 15 20 25 DAC CURRENT (mA) Figure 20. SFDR vs. DAC Current, 59.1 AOUT, 300 MHz REFCLK with REFCLK Multiplier Bypassed 00636-020 620 615 610 605 600 595 590 0 20 40 60 80 100 120 140 FREQUENCY (MHz) Figure 21. Supply Current vs. Output Frequency (Variation Is Minimal, Expressed as a Percentage, and Heavily Dependent on Tuning Word) PHASE NOISE (dBc/Hz) 00636-021 Rev. E | Page 14 of 52 RISE TIME 1.04ns JITTER [10.6ps RMS] 500ps/DIV –33ps 232mV/DIV 0ps +33ps 50Ω INPUT Figure 22. Typical Comparator Output Jitter, 40 MHz AOUT, 300 MHz RFCLK with REFCLK Multiplier Bypassed REF1 RISE 1.174ns C1 FALL 1.286ns 00636-022 AMPLITUDE (mV p-p) AD9854 1200 1000 MINIMUM COMPARATOR INPUT DRIVE VCM = 0.5V 800 600 400 200 0 0 100 200 300 400 500 FREQUENCY (MHz) Figure 24. Comparator Toggle Voltage Requirement 00636-024 00636-023 CH1 500mVΩ M 500ps CH1 980mV Figure 23. Comparator Rise/Fall Times Rev. E | Page 15 of 52 AD9854 TYPICAL APPLICATIONS RF/IF INPUT LPF I BASEBAND AD9854 REFCLK LPF COS CHANNEL SELECT LPF FILTERS SIN LPF Figure 25. Quadrature Downconversion Q BASEBAND 00636-025 I BASEBAND AD9854 REFCLK LPF COS LPF SIN RF OUTPUT Q BASEBAND Figure 26. Direct Conversion Quadrature Upconverter 00636-026 Rx RF IN VCA I/Q MIXER I AND LOW-PASS Q FILTER 8 DUAL DIGITAL 8-/10-BIT ADC 8 DEMODULATOR ADC CLOCK FREQUENCY LOCKED TO Tx CHIP/ SYMBOL/PN RATE ADC ENCODE AGC REFERENCE CLOCK AD9854 CLOCK GENERATOR 48 CHIP/SYMBOL/PN RATE DATA Rx BASEBAND DIGITAL DATA OUT Figure 27. Chip Rate Generator in Spread Spectrum Application AD9854 IOUT 50Ω BAND-PASS FILTER AMPLIFIER 50Ω AD9854 SPECTRUM FUNDAMENTAL FC – FO IMAGE FC + FO IMAGE FCLK FINAL OUTPUT SPECTRUM FC + FO IMAGE BAND-PASS FILTER Figure 28. Using an Aliased Image to Generate a High Frequency 00636-028 00636-027 Rev. E | Page 16 of 52 REFERENCE CLOCK PHASE COMPARATOR FILTER LOOP FILTER RF FREQUENCY OUT VCO DAC OUT AD9854 DDS TUNING WORD REF CLK IN PROGRAMMABLE DIVIDE-BY-N FUNCTION (WHERE N = 248/TUNING WORD) Figure 29. Programmable Fractional Divide-by-N Synthesizer 00636-029 REF CLOCK AD9854 DDS FILTER PHASE LOOP COMPARATOR FILTER RF FREQUENCY OUT VCO TUNING WORD DIVIDE-BY-N Figure 30. Agile High Frequency Synthesizer 00636-030 36dB TYPICAL SSB REJECTION AD8346 QUADRATURE MODULATOR 50Ω VOUT Σ LO 90 PHASE SPLITTER 0 LO COSINE (DC TO 70MHz) 0.8 TO 2.5GHz AD9854 QUADRATURE DDS SINE (DC TO 70MHz) DDS – LO LO DDS + LO NOTES 1. FLIP DDS QUADRATURE SIGNALS TO SELECT ALTERNATE SIDEBAND. ADJUST DDS SINE OR COSINE SIGNAL AMPLITUDE FOR GREATEST SIDEBAND SUPPRESSION. DDS DAC OUTPUTS MUST BE LOW-PASS FILTERED PRIOR TO USE WITH THE AD8346. Figure 31. Single Sideband Upconversion REFERENCE CLOCK DIFFERENTIAL TRANSFORMER-COUPLED IOUT OUTPUT FILTER DDS 50Ω AD9854 IOUT 00636-032 50Ω 1:1 TRANSFORMER (Mini-Circuits® T1-1T) Figure 32. Differential Output Connection for Reduction of Common-Mode Signals 00636-031 AD9854 Rev. E | Page 17 of 52 AD9854 REFERENCE CLOCK AOUT = 100MHz LPF AD9854 LPF SIN COS COMPARATORS Figure 33. Clock Frequency Doubler CLOCK OUT = 200MHz 00636-033 µPROCESSOR/ CONTROLLER FPGA, ETC. REFERENCE CLOCK 2kΩ AD9854 8-BIT PARALLEL OR SERIAL PROGRAMMING DATA AND CONTROL SIGNALS 300MHz MAX DIRECT MODE OR 15MHz TO 75MHz MAX IN THE 4× TO 20× CLOCK MULTIPLIER MODE I DAC Q DAC OR CONTROL DAC + RSET LOW-PASS FILTER 1 LOW-PASS FILTER 2 NOTES 1. IOUT = APPROX 20mA MAX WHEN RSET = 2kΩ. 2. SWITCH POSITION 1 PROVIDES COMPLEMENTARY SINUSOIDAL SIGNALS TO THE COMPARATOR TO PRODUCE A FIXED 50% DUTY CYCLE FROM THE COMPARATOR. 3. SWITCH POSITION 2 PROVIDES THE SAME DUTY CYCLE USING QUADRATURE SINUSOIDAL SIGNALS TO THE COMPARATOR OR A DC THRESHOLD VOLTAGE TO ALLOW SETTING OF THE COMPARATOR DUTY CYCLE (DEPENDS ON THE CONFIGURATION OF THE Q DAC). CMOS LOGIC CLOCK OUT Figure 34. Frequency Agile Clock Generator Applications for the AD9854 00636-034 Rev. E | Page 18 of 52 THEORY OF OPERATION The AD9854 quadrature output digital synthesizer is a highly flexible device that addresses a wide range of applications. The device consists of an NCO with a 48-bit phase accumulator, a programmable reference clock multiplier, inverse sinc filters, digital multipliers, two 12-bit/300 MHz DACs, a high speed analog comparator, and interface logic. This highly integrated device can be configured to serve as a synthesized LO, an agile clock generator, or an FSK/BPSK modulator. Analog Devices, Inc., provides a technical tutorial about the operational theory of the functional blocks of the device. The tutorial includes a technical description of the signal flow through a DDS device and provides basic applications information for a variety of digital synthesis implementations. The document, A Technical Tutorial on Digital Signal Synthesis, is available from the DDS Technical Library, on the Analog Devices DDS website at www.analog.com/dds. MODES OF OPERATION The AD9854 has five programmable operational modes. To select a mode, three bits in the control register (parallel Address 1F hex) must be programmed, as described in Table 5. Table 5. Mode Selection Table Mode 2 Mode 1 Mode 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 Result Single tone FSK Ramped FSK Chirp BPSK AD9854 In each mode, some functions may be prohibited. Table 6 lists the functions and their availability for each mode. Single Tone (Mode 000) This is the default mode when the MASTER RESET pin is asserted. It can also be accessed if the user programs this mode into the control register. The phase accumulator, responsible for generating an output frequency, is presented with a 48-bit value from the Frequency Tuning Word 1 registers that have default values of 0. Default values from the remaining applicable registers further define the single-tone output signal qualities. The default values after a master reset configure the device with an output signal of 0 Hz and zero phase. At power-up and reset, the output from the I and Q DACs is a dc value equal to the midscale output current. This is the default mode amplitude setting of 0. See the On/Off Output Shaped Keying (OSK) section for more details about the output amplitude control. All or some of the 28 program registers must be programmed to produce a user-defined output signal. Figure 35 shows the transition from the default condition (0 Hz) to a user-defined output frequency (F1). Table 6. Functions Available for Modes Function Phase Adjust 1 Phase Adjust 2 Single-Pin FSK/BPSK or HOLD Single-Pin Shaped Keying Phase Offset or Modulation Amplitude Control or Modulation Inverse Sinc Filter Frequency Tuning Word 1 Frequency Tuning Word 2 Automatic Frequency Sweep Single Tone FSK ● ● ● ● ● ● ● ● ● ● ● ● ● ● Mode Ramped FSK ● ● ● ● ● ● ● ● ● Chirp ● ● ● ● ● ● ● ● BPSK ● ● ● ● ● ● ● Rev. E | Page 19 of 52 AD9854 FREQUENCY 00636-035 F1 0 MODE 000 (DEFAULT) TW1 0 MASTER RESET 000 (SINGLE TONE) F1 I/O UD CLK Figure 35. Default State to User-Defined Output Transition As with all Analog Devices DDS devices, the value of the frequency tuning word is determined by FTW = (Desired Output Frequency × 2N)/SYSCLK where: N is the phase accumulator resolution (48 bits in this instance). Desired Output Frequency is expressed in hertz. FTW (frequency tuning word) is a decimal number. After a decimal number has been calculated, it must be rounded to an integer and then converted to binary format, that is, a series of 48 binary-weighted 1s and 0s. The fundamental sine wave DAC output frequency range is from dc to one-half SYSCLK. Changes in frequency are phase continuous, meaning that the first sampled phase value of the new frequency is referenced from the time of the last sampled phase value of the previous frequency. The I and Q DACs of the AD9854 are always 90° out of phase. The 14-bit phase registers do not independently adjust the phase of each DAC output. Instead, both DACs are affected equally by a change in phase offset. The single-tone mode allows the user to control the following signal qualities: • Output frequency to 48-bit accuracy • Output amplitude to 12-bit accuracy • Fixed, user-defined amplitude control • Variable, programmable amplitude control • Automatic, programmable, single-pin-controlled on/off output shaped keying • Output phase to 14-bit accuracy These qualities can be changed or modulated via the 8-bit parallel programming port at a 100 MHz parallel byte rate or at a 10 MHz serial rate. Incorporating this attribute permits FM, AM, PM, FSK, PSK, and ASK operation in single-tone mode. Unramped FSK (Mode 001) When the unramped FSK mode is selected, the output frequency of the DDS is a function of the values loaded into Frequency Tuning Word Register 1 and Frequency Tuning Word Register 2 and the logic level of Pin 29 (FSK/BPSK/HOLD). A logic low on Pin 29 chooses F1 (Frequency Tuning Word 1, Parallel Address 4 hex to Parallel Address 9 hex), and a logic high chooses F2 (Frequency Tuning Word 2, Parallel Register Address A hex to Parallel Register Address F hex). Changes in frequency are phase continuous and are internally coincident with the FSK data pin (Pin 29); however, there is deterministic pipeline delay between the FSK data signal and the DAC output. (Refer to the pipeline delays in Table 1.) The unramped FSK mode, shown in Figure 36, represents traditional FSK, radio teletype (RTTY), or teletype (TTY) transmission of digital data. FSK is a very reliable means of digital communication; however, it makes inefficient use of the bandwidth in the RF spectrum. Ramped FSK, shown in Figure 37, is a method of conserving bandwidth. Ramped FSK (Mode 010) This mode is a method of FSK whereby changes from F1 to F2 are not instantaneous, but are accomplished in a frequency sweep or ramped fashion (the ramped notation implies that the sweep is linear). Although linear sweeping, or frequency ramping, is easily and automatically accomplished, it is only one of many schemes. Other frequency transition schemes can be implemented by changing the ramp rate and ramp step size on the fly in a piecewise fashion. Rev. E | Page 20 of 52 F2 FREQUENCY F1 0 MODE 000 (DEFAULT) 001 (FSK NO RAMP) TW1 0 F1 TW2 0 F2 I/O UD CLK FSK DATA (PIN 29) Figure 36. Unramped (Traditional) FSK Mode F2 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 0 TW2 0 DFW I/O UD CLK FSK DATA (PIN 29) 010 (RAMPED FSK) F1 F2 REQUIRES A POSITIVE TWOS COMPLEMENT VALUE RAMP RATE Figure 37. Ramped FSK Mode (Start at F1) F2 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 0 TW2 0 I/O UD CLK FSK DATA 010 (RAMPED FSK) F1 F2 Figure 38. Ramped FSK Mode (Start at F2) Rev. E | Page 21 of 52 00636-038 00636-037 00636-036 AD9854 AD9854 Frequency ramping, whether linear or nonlinear, necessitates that many intermediate frequencies between F1 and F2 are output in addition to the primary F1 and F2 frequencies. Figure 37 and Figure 38 depict the frequency vs. time characteristics of a linear ramped FSK signal. Note that in ramped FSK mode, the delta frequency word (DFW) is required to be programmed as a positive twos complement value. Another requirement is that the lowest frequency (F1) be programmed in the Frequency Tuning Word 1 register. The purpose of ramped FSK is to provide better bandwidth containment than traditional FSK by replacing the instantaneous frequency changes with more gradual, user-defined frequency changes. The dwell time at F1 and F2 can be equal to or much greater than the time spent at each intermediate frequency. The user controls the dwell time at F1 and F2, the number of intermediate frequencies, and the time spent at each frequency. Unlike unramped FSK, ramped FSK requires the lowest frequency to be loaded into F1 registers and the highest frequency to be loaded into F2 registers. Several registers must be programmed to instruct the DDS on the resolution of intermediate frequency steps (48 bits) and the time spent at each step (20 bits). Furthermore, the CLR ACC1 bit in the control register should be toggled (low-high-low) prior to operation to ensure that the frequency accumulator is starting from an all 0s output condition. For piecewise, nonlinear frequency transitions, it is necessary to reprogram the registers while the frequency transition is in progress to affect the desired response. Parallel Register Address 1A hex to Parallel Register Address 1C hex comprise the 20-bit ramp rate clock registers. This is a countdown counter that outputs a single pulse whenever the count reaches 0. The counter is activated when a logic level change occurs on the FSK input, Pin 29. This counter is run at the system clock rate, 300 MHz maximum. The time period between each output pulse is given as (N + 1) × System Clock Period where N is the 20-bit ramp rate clock value programmed by the user. The allowable range of N is from 1 to (220 − 1). The output of this counter clocks the 48-bit frequency accumulator shown in Figure 39. The ramp rate clock determines the amount of time spent at each intermediate frequency between F1 and F2. The counter stops automatically when the destination frequency is achieved. The dwell time spent at F1 and F2 is determined by the duration that the FSK input, Pin 29, is held high or low after the destination frequency has been reached. FREQUENCY ACCUMUL ATOR 48-BIT DELTA FREQUENCY WORD (TWOS COMPLEMENT) PHASE ADDER ACCUMULATOR FSK (PIN 29) INSTANTANEOUS PHASE OUT FREQUENCY TUNING WORD 1 FREQUENCY TUNING WORD 2 20-BIT RAMP RATE CLOCK SYSTEM CLOCK Figure 39. Block Diagram of Ramped FSK Function Parallel Register Address 10 hex to Parallel Register Address 15 hex comprise the 48-bit, twos complement, delta frequency word registers. This 48-bit word is accumulated (added to the accumulator’s output) every time it receives a clock pulse from the ramp rate counter. The output of this accumulator is added to or subtracted from the F1 or F2 frequency word, which is then fed into the input of the 48-bit phase accumulator that forms the numerical phase steps for the sine and cosine wave outputs. In this fashion, the output frequency is ramped up and down in frequency according to the logic state of Pin 29. This ramping rate is a function of the 20-bit ramp rate clock. When the destination frequency is achieved, the ramp rate clock is stopped, halting the frequency accumulation process. Generally speaking, the delta frequency word is a much smaller value compared with the value of the F1 or F2 tuning word. For example, if F1 and F2 are 1 kHz apart at 13 MHz, the delta frequency word might be only 25 Hz. 00636-039 Rev. E | Page 22 of 52 AD9854 F2 FREQUENCY F1 0 MODE 010 (RAMPED FSK) TW1 F1 TW2 F2 FSK DATA TRIANGLE BIT I/O UD CLK Figure 40. Effect of Triangle Bit in Ramped FSK Mode F2 00636-040 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 0 TW2 0 I/O UD CLK FSK DATA 010 (RAMPED FSK) F1 F2 Figure 41. Effect of Premature Ramped FSK Data 00636-041 Figure 41 shows that premature toggling causes the ramp to immediately reverse itself and proceed at the same rate and resolution until the original frequency is reached. to the logic level on Pin 29 (FSK input pin) when the triangle bit’s rising edge occurs (Figure 42). If the FSK data bit is high instead of low, F2, rather than F1, is chosen as the start frequency. The control register contains a triangle bit at Parallel Register Address 1F hex. Setting this bit high in Mode 010 causes an automatic ramp-up and ramp-down between F1 and F2 to occur without toggling Pin 29, as shown in Figure 40. The logic state of Pin 29 has no effect once the triangle bit is set high. This function uses the ramp rate clock time period and the step size of the delta frequency word to form a continuously sweeping linear ramp from F1 to F2 and back to F1 with equal dwell times at every frequency. Use this function to automatically sweep between any two frequencies from dc to Nyquist. In the ramped FSK mode with the triangle bit set high, an Additional flexibility in the ramped FSK mode is provided by the AD9854’s ability to respond to changes in the 48-bit delta frequency word and/or the 20-bit ramp rate counter at any time during the ramping from F1 to F2 or vice versa. To create these nonlinear frequency changes, it is necessary to combine several linear ramps with different slopes in a piecewise fashion. This is done by programming and executing a linear ramp at a rate or slope and then altering the slope (by changing the ramp rate clock or delta frequency word, or both). Changes in slope can be made as often as needed before the destination frequency has been reached to form the desired nonlinear frequency sweep response. These piecewise changes can be precisely timed using automatic frequency sweep begins at either F1 or F2, according Rev. E | Page 23 of 52 AD9854 the 32-bit internal update clock (see the Internal and External Update Clock section). Nonlinear ramped FSK has the appearance of the chirp function shown in Figure 43. The difference between a ramped FSK function and a chirp function is that FSK is limited to operation between F1 and F2, whereas chirp operation has no F2 limit frequency. Two additional control bits (CLR ACC1 and CLR ACC2) are available in the ramped FSK mode that allow more options. If CLR ACC1 (Register Address 1F hex) is set high, it clears the 48-bit frequency accumulator (ACC1) output with a retriggerable one-shot pulse of one system clock duration. If the CLR ACC1 bit is left high, a one-shot pulse is delivered on the rising edge of every update clock. The effect is to interrupt the current ramp, reset the frequency to the start point (F1 or F2), and then continue to ramp up (or down) at the previous rate. This occurs even when a static F1 or F2 destination frequency has been achieved. Alternatively, the CLR ACC2 control bit (Register Address 1F hex) is available to clear both the frequency accumulator (ACC1) and the phase accumulator (ACC2). When this bit is set high, the output of the phase accumulator results in 0 Hz output from the DDS. As long as this bit is set high, the frequency and phase accumulators are cleared, resulting in 0 Hz output. To return to previous DDS operation, CLR ACC2 must be set to logic low. Chirp (Mode 011) This mode is also known as pulsed FM. Most chirp systems use a linear FM sweep pattern, but the AD9854 can also support nonlinear patterns. In radar applications, use of chirp or pulsed FM allows operators to significantly reduce the output power needed to achieve the result that a single-frequency radar system would produce. Figure 43 shows a very low resolution nonlinear chirp, demonstrating the different slopes that are created by varying the time steps (ramp rate) and frequency steps (delta frequency word). F2 FREQUENCY F1 0 MODE 000 (DEFAULT) 010 (RAMPED FSK) TW1 0 F1 TW2 0 F2 FSK DATA TRIANGLE BIT Figure 42. Automatic Linear Ramping Using the Triangle Bit 00636-042 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 0 DFW RAMP RATE I/O UD CLK 010 (RAMPED FSK) F1 Figure 43. Example of a Nonlinear Chirp Rev. E | Page 24 of 52 00636-043 The AD9854 permits precise, internally generated linear, or externally programmed nonlinear, pulsed or continuous FM over the complete frequency range, duration, frequency resolution, and sweep direction(s). All of these are user programmable. Figure 44 shows a block diagram of the FM chirp components. 00636-044 ADDER PHASE ACCUMULATOR OUT FREQUENCY ACCUMULATOR 48-BIT DELTA FREQUENCY WORD (TWOS COMPLEMENT) CLR ACC1 FREQUENCY TUNING WORD 1 CLR ACC2 HOLD 20-BIT RAMP RATE CLOCK SYSTEM CLOCK Figure 44. FM Chirp Components Basic FM Chirp Programming Steps 1. Program a start frequency into Frequency Tuning Word 1 (FTW1) at Parallel Register Address 4 hex to Parallel Register Address 9 hex. 2. Program the frequency step resolution into the 48-bit, twos complement delta frequency word (Parallel Register Address 10 hex to Parallel Register Address 15 hex). 3. Program the rate of change (time at each frequency) into the 20-bit ramp rate clock (Parallel Register Address 1A hex to Parallel Register Address 1C hex). When programming is complete, an I/O update pulse at Pin 20 engages the program commands. The necessity for a twos complement delta frequency word is to define the direction in which the FM chirp moves. If the 48-bit delta frequency word is negative (MSB is high), the incremental frequency changes are in a negative direction from FTW1. If the 48-bit word is positive (MSB is low), the incremental frequency changes are in a positive direction from FTW1. It is important to note that FTW1 is only a starting point for FM chirp. There is no built-in restraint requiring a return to FTW1. Once the FM chirp begins, it is free to move (under program control) within the Nyquist bandwidth (dc to one-half the system clock). However, instant return to FTW1 can be easily achieved. AD9854 Two control bits (CLR ACC1 and CLR ACC2) are available in the FM chirp mode that allow the return to the beginning frequency, FTW1, or to 0 Hz. When the CLR ACC1 bit (Register Address 1F hex) is set high, the 48-bit frequency accumulator (ACC1) output is cleared with a retriggerable one-shot pulse of one system clock duration. The 48-bit delta frequency word input to the accumulator is unaffected by the CLR ACC1 bit. If the CLR ACC1 bit is held high, a one-shot pulse is delivered to the frequency accumulator (ACC1) on every rising edge of the I/O update clock. The effect is to interrupt the current chirp, reset the frequency to that programmed into FTW1, and continue the chirp at the previously programmed rate and direction. Clearing the output of the frequency accumulator in the chirp mode is illustrated in Figure 45. Shown in the diagram is the I/O update clock, which is either user supplied or internally generated. Alternatively, the CLR ACC2 control bit (Register Address 1F hex) is available to clear both the frequency accumulator (ACC1) and the phase accumulator (ACC2). When this bit is set high, the output of the phase accumulator results in 0 Hz output from the DDS. As long as this bit is set high, the frequency and phase accumulators are cleared, resulting in 0 Hz output. To return to the previous DDS operation, CLR ACC2 must be set to logic low. This bit is useful in generating pulsed FM. Figure 46 illustrates the effect of the CLR ACC2 bit on the DDS output frequency. Note that reprogramming the registers while the CLR ACC2 bit is high allows a new FTW1 frequency and slope to be loaded. Another function that is available only in chirp mode is the HOLD pin (Pin 29). This function stops the clock signal to the ramp rate counter, halting any further clocking pulses to the frequency accumulator, ACC1. The effect is to halt the chirp at the frequency existing just before the HOLD pin is pulled high. When Pin 29 is returned low, the clock and chirp resumes. During a hold condition, the user can change the programming registers; however, the ramp rate counter must resume operation at its previous rate until a count of 0 is obtained before a new ramp rate count can be loaded. Figure 47 shows the effect of the hold function on the DDS output frequency. Rev. E | Page 25 of 52 00636-045 AD9854 FREQUENCY MODE F1 0 000 (DEFAULT) FTW1 0 DFW RAMP RATE 011 (CHIRP) F1 DELTA FREQUENCY WORD RAMP RATE I/O UD CLK CLR ACC1 Figure 45. Effect of CLR ACC1 in FM Chirp Mode FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 0 DPW RAMP RATE CLR ACC2 I/O UD CLK 011 (CHIRP) Figure 46. Effect of CLR ACC2 in Chirp Mode 00636-046 Rev. E | Page 26 of 52 AD9854 FREQUENCY F1 0 MODE 000 (DEFAULT) TW1 0 DFW RAMP RATE HOLD I/O UD CLK 360 011 (CHIRP) F1 DELTA FREQUENCY WORD RAMP RATE Figure 47. Example of Hold Function 00636-047 PHASE 0 MODE 000 (DEFAULT) FTW1 0 PHASE ADJUST 1 PHASE ADJUST 2 BPSK DATA I/O UD CLK 100 (BPSK) F1 270° 90° Figure 48. BPSK Mode 00636-048 The 32-bit automatic I/O update counter can be used to construct complex chirp or ramped FSK sequences. Because this internal counter is synchronized with the AD9854 system clock, precisely timed program changes are possible. For such changes, the user need only reprogram the desired registers before the automatic I/O update clock is generated. In chirp mode, the destination frequency is not directly specified. If the user fails to control the chirp, the DDS automatically confines itself to the frequency range between dc and Nyquist. Unless terminated by the user, the chirp continues until power is removed. When the chirp destination frequency is reached, the user can choose any of the following actions: • Stop at the destination frequency by using the HOLD pin or by loading all 0s into the delta frequency word registers of the frequency accumulator (ACC1). • Use the HOLD pin function to stop the chirp, and then ramp down the output amplitude by using the digital multiplier stages and the output shaped keying pin (Pin 30), or by using the program register control (Address 21 to Address 24 hex). • Abruptly end the transmission with the CLR ACC2 bit. • Continue chirp by reversing direction and returning to the previous or another destination frequency in a linear or user-directed manner. If this involves reducing the frequency, a negative 48-bit delta frequency word (the MSB is set to 1) must be loaded into Register 10 hex to Register 15 hex. Any decreasing frequency step of the delta frequency word requires the MSB to be set to logic high. Rev. E | Page 27 of 52 AD9854 • Continue chirp by immediately returning to the beginning frequency (F1) in a sawtooth fashion, and then repeating the previous chirp process using the CLR ACC1 control bit. An automatic, repeating chirp can be set up by using the 32-bit update clock to issue the CLR ACC1 command at precise time intervals. Adjusting the timing intervals or changing the delta frequency word changes the chirp range. It is incumbent upon the user to balance the chirp duration and frequency resolution to achieve the proper frequency range. BPSK (Mode 100) Binary, biphase, or bipolar phase shift keying is a means to rapidly select between two preprogrammed 14-bit output phase offsets that equally affect both the I and Q outputs of the AD9854. The logic state of Pin 29, the BPSK pin, controls the selection of Phase Adjust Register 1 or Phase Adjust Register 2. When low, Pin 29 selects Phase Adjust Register 1; when high, it selects Phase Adjust Register 2. Figure 48 illustrates phase changes made to four cycles of an output carrier. Basic BPSK Programming Steps 1. Program a carrier frequency into Frequency Tuning Word 1. 2. Program the appropriate 14-bit phase words into Phase Adjust Register 1 and Phase Adjust Register 2. 3. Attach the BPSK data source to Pin 29. 4. Activate the I/O update clock when ready. Note that for higher-order PSK modulation, the user can select the single-tone mode and program Phase Adjust Register 1 using the serial or high speed parallel programming bus. Rev. E | Page 28 of 52 USING THE AD9854 INTERNAL AND EXTERNAL UPDATE CLOCK This update clock function is comprised of a bidirectional I/O pin (Pin 20) and a programmable 32-bit down-counter. To program changes that are to be transferred from the I/O buffer registers to the active core of the DDS, a clock signal (low-tohigh edge) must be externally supplied to Pin 20 or internally generated by the 32-bit update clock. When the user provides an external update clock, it is internally synchronized with the system clock to prevent a partial transfer of program register information due to a violation of data setup or hold time. This mode allows the user to completely control when updated program information becomes effective. The default mode for the update clock is internal (the internal update clock control register bit is logic high). To switch to external update clock mode, the internal update clock control register bit must be set to logic low. The internal update mode generates automatic, periodic update pulses at intervals set by the user. An internally generated update clock can be established by programming the 32-bit update clock registers (Address 16 hex to Address 19 hex) and setting the internal update clock control register bit (Address 1F hex) to logic high. The update clock down-counter function operates at half the rate of the system clock (150 MHz maximum) and counts down from a 32-bit binary value (programmed by the user). When the count reaches 0, an automatic I/O update of the DDS output or functions is generated. The update clock is internally and externally routed to Pin 20 to allow users to synchronize the programming of update information with the update clock rate. The time between update pulses is given as (N + 1)(System Clock Period × 2) where N is the 32-bit value programmed by the user, and the allowable range of N is from 1 to (232 − 1). The internally generated update pulse that is output from Pin 20 has a fixed high time of eight system clock cycles. Programming the update clock register to a value less than five causes the I/O UD CLK pin to remain high. Although the update clock can function in this state, it cannot be used to indicate when data is transferring. This is an effect of the minimum high pulse time when I/O UD CLK functions as an output. AD9854 ON/OFF OUTPUT SHAPED KEYING (OSK) The on/off OSK feature allows the user to control the amplitude vs. time slope of the I and Q DAC output signals. This function is used in burst transmissions of digital data to reduce the adverse spectral impact of short, abrupt bursts of data. Users must first enable the digital multipliers by setting the OSK EN bit (Control Register Address 20 hex) to logic high in the control register. Otherwise, if the OSK EN bit is set low, the digital multipliers responsible for amplitude control are bypassed and the I and Q DAC outputs are set to full-scale amplitude. In addition to setting the OSK EN bit, a second control bit, OSK INT (also at Address 20 hex), must be set to logic high. Logic high selects the linear internal control of the output ramp-up or rampdown function. A logic low in the OSK INT bit switches control of the digital multipliers to user-programmable 12-bit registers, allowing users to dynamically shape the amplitude transition in practically any fashion. These 12-bit registers, labeled Output Shape Key I and Output Shape Key Q, are located at Address 21 hex through Address 24 hex, as listed in Table 8. The maximum output amplitude is a function of the RSET resistor and is not programmable when OSK INT is enabled. ABRUPT ON/OFF KEYING ZERO SCALE FULL SCALE ZERO SCALE FULL SCALE 00636-049 SHAPED ON/OFF KEYING Figure 49. On/Off Output Shaped Keying The transition time from zero scale to full scale must also be programmed. The transition time is a function of two fixed elements and one variable. The variable element is the programmable 8-bit ramp rate counter. This is a down-counter that is clocked at the system clock rate (300 MHz maximum) and that generates one pulse whenever the counter reaches 0. This pulse is routed to a 12-bit counter that increments with each pulse received. The outputs of the 12-bit counter are connected to the 12-bit digital multiplier. When the digital multiplier has a value of all 0s at its inputs, the input signal is multiplied by 0, producing zero scale. When the multiplier has a value of all 1s, the input signal is multiplied by a value of 4095 or 4096, producing nearly full scale. There are 4094 remaining fractional multiplier values that produce output amplitudes scaled according to their binary values. Rev. E | Page 29 of 52 AD9854 DDS DIGITAL OUTPUT DIGITAL SIGNAL IN (BYPASS MULTIPLIER) OSK EN = 0 12 12-BIT DIGITAL MULTIPLIER OSK EN = 0 12 OSK EN = 1 OSK EN = 1 SINE DAC USER-PROGRAMMABLE 12-BIT Q CHANNEL MULTIPLIER OUTPUT SHAPED KEYING Q MULTIPLIER REGISTER 12 12 OSK INT = 0 OSK INT = 0 12 12-BIT 1 UP/DOWN COUNTER 8-BIT RAMP RATE COUNTER SYSTEM CLOCK 00636-050 ON/OFF OUTPUT SHAPED KEYING PIN Figure 50. Block Diagram of Q DAC Pathway of the Digital Multiplier Section Responsible for the Output Shaped Keying Function The two fixed elements of the transition time are the period of the system clock (which drives the ramp rate counter) and the number of amplitude steps (4096). For example, if the system clock of the AD9854 is 100 MHz (10 ns period) and the ramp rate counter is programmed for a minimum count of 3, the transition takes two system clock periods (one rising edge loads the countdown value, and the next edge decrements the counter from 3 to 2). If the countdown value is less than 3, the ramp rate counter stalls and therefore produces a constant scaling value to the digital multipliers. This stall condition may have an application for the user. The relationship of the 8-bit countdown value to the time between output pulses is given as (N + 1) × System Clock Period where N is the 8-bit countdown value. It takes 4096 of these pulses to advance the 12-bit up-counter from zero scale to full scale. Therefore, the minimum output shaped keying ramp time for a 100 MHz system clock is 4096 × 4 × 10 ns ≈ 164 μs The maximum ramp time is 4096 × 256 × 10 ns ≈ 10.5 ms Finally, changing the logic state of Pin 30, output shaped keying automatically performs the programmed output envelope functions when OSK INT is high. A logic high on Pin 30 causes the outputs to linearly ramp up to full-scale amplitude and to hold until the logic level is changed to low, causing the outputs to ramp down to zero scale. I AND Q DACS The sine and cosine outputs of the DDS drive the Q and I DACs, respectively (300 MSPS maximum). The maximum amplitudes of these output are set by the DAC RSET resistor at Pin 56. These are current-output DACs with a full-scale maximum output of 20 mA; however, a nominal 10 mA output current provides the best spurious-free dynamic range (SFDR) performance. The value of RSET is 39.93/IOUT, where IOUT is expressed in amps. DAC output compliance specifications limit the maximum voltage developed at the outputs to −0.5 V to +1 V. Voltages developed beyond this limitation cause excessive DAC distortion and possibly permanent damage. The user must choose a proper load impedance to limit the output voltage swing to the compliance limits. Both DAC outputs should be terminated equally for best SFDR, especially at higher output frequencies, where harmonic distortion errors are more prominent. Both DACs are preceded by inverse sin(x)/x filters (also called inverse sinc filters) that precompensate for DAC output amplitude variations over frequency to achieve flat amplitude response from dc to Nyquist. Both DACs can be powered down when not needed by setting the DAC PD bit high (Address 1D hex of the control register). I DAC outputs are designated as IOUT1 and IOUT1, Pin 48 and Pin 49, respectively. Q DAC outputs are designated as IOUT2 and IOUT2, Pin 52 and Pin 51, respectively. CONTROL DAC The 12-bit Q DAC can be reconfigured to perform as a control or auxiliary DAC. The control DAC output can provide dc control levels to external circuitry, generate ac signals, or enable duty cycle control of the on-board comparator. When the SRC Q DAC bit in the control register (Parallel Address 1F hex) is set high, the Q DAC inputs are switched from internal 12-bit Q data source (default setting) to external 12-bit, twos complement data supplied by the user. Data is channeled through the serial or parallel interface to the 12-bit Q DAC register (Address 26 hex and Address 27 hex) at a maximum data rate of 100 MHz. This DAC is clocked at the system clock, 300 MSPS (maximum), and has the same maximum output current capability as that of the I DAC. The single RSET resistor on the AD9854 sets the full-scale output current for both DACs. When not needed, the control DAC can be separately powered down to conserve power by setting the Q DAC power-down bit high (Address 1D hex). Control DAC outputs are designated as IOUT2 and IOUT2, Pin 52 and Pin 51, respectively. Rev. E | Page 30 of 52 INVERSE SINC FUNCTION The inverse sinc function precompensates input data to both DACs for the sin(x)/x roll-off characteristic inherent in the DAC’s output spectrum. This allows wide bandwidth signals (such as QPSK) to be output from the DACs without appreciable amplitude variations as a function of frequency. The inverse sinc function can be bypassed to reduce power consumption significantly, especially at higher clock speeds. When the Q DAC is configured as a control DAC, the inverse sinc function does not apply to the Q path. Inverse sinc is engaged by default and is bypassed by bringing the bypass inverse sinc bit high in Control Register 20 hex, as noted in Table 8. MAGNITUDE (dB) 00636-051 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 0 ISF SYSTEM SINC 0.1 0.2 0.3 0.4 0.5 FREQUENCY NORMALIZED TO SAMPLE RATE Figure 51. Inverse Sinc Filter Response REFCLK MULTIPLIER The REFCLK multiplier is a programmable PLL-based reference clock multiplier that allows the user to select an integer clock multiplying value over the range of 4× to 20×. With this function, users can input as little as 15 MHz at the REFCLK input to produce a 300 MHz internal system clock. Five bits in Control Register 1E hex set the multiplier value, as detailed in Table 7. The REFCLK multiplier function can be bypassed to allow direct clocking of the AD9854 from an external clock source. The system clock for the AD9854 is either the output of the REFCLK multiplier (if it is engaged) or the REFCLK inputs. REFCLK can be either a single-ended or differential input by setting Pin 64, DIFF CLK ENABLE, low or high, respectively. PLL Range Bit The PLL range bit selects the frequency range of the REFCLK multiplier PLL. For operation from 200 MHz to 300 MHz (internal system clock rate), the PLL range bit should be set to Logic 1. For operation below 200 MHz, the PLL range bit AD9854 should be set to Logic 0. The PLL range bit adjusts the PLL loop parameters for best phase noise performance within each range. PLL Filter The PLL FILTER pin (Pin 61) provides the connection for the external zero-compensation network of the PLL loop filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF capacitor. The other side of the network should be connected as close as possible to Pin 60, AVDD. For optimum phase noise performance, the clock multiplier can be bypassed by setting the bypass PLL bit in Control Register Address 1E hex. Differential REFCLK Enable A high level on the DIFF CLK ENABLE pin enables the differential clock inputs, REFCLK and REFCLK (Pin 69 and Pin 68, respectively). The minimum differential signal amplitude required is 400 mV p-p at the REFCLK input pins. The center point or common-mode range of the differential signal can range from 1.6 V to 1.9 V. When Pin 64 (DIFF CLK ENABLE) is tied low, REFCLK (Pin 69) is the only active clock input. This is referred to as single-ended mode. In this mode, Pin 68 (REFCLK) should be tied low or high. High Speed Comparator The comparator is optimized for high speed and has a toggle rate greater than 300 MHz, low jitter, sensitive input, and built-in hysteresis. It also has an output level of 1 V p-p minimum into 50 Ω or CMOS logic levels into high impedance loads. The comparator can be powered down separately to conserve power. This comparator is used in clock-generator applications to square up the filtered sine wave generated by the DDS. Power-Down The programming registers allow several individual stages to be powered down to reduce power consumption while maintaining the functionality of the desired stages. These stages are identified in Table 8, Address 1D hex. Power-down is achieved by setting the specified bits to logic high. A logic low indicates that the stages are powered up. Furthermore, and perhaps most significantly, the inverse sinc filters and the digital multiplier stages can be bypassed to achieve significant power reduction by programming the control registers in Address 20 hex. Again, logic high causes the stage to be bypassed. Of particular importance is the inverse sinc filter; this stage consumes a significant amount of power. A full power-down occurs when all four PD bits in Control Register 1D hex are set to logic high. This reduces power consumption to approximately 10 mW (3 mA). Rev. E | Page 31 of 52 AD9854 PROGRAMMING THE AD9854 The AD9854 register layout table (Table 8) contains information for programming the chip for the desired functionality. Although many applications require very little programming to configure the AD9854, some use all 12 accessible register banks. The AD9854 supports an 8-bit parallel I/O operation or an SPI®compatible serial I/O operation. All accessible registers can be written and read back in either I/O operating mode. S/P SELECT (Pin 70) is used to configure the I/O mode. Systems that use the parallel I/O mode must connect the S/P SELECT pin to VDD. Systems that operate in the serial I/O mode must tie the S/P SELECT pin to GND. Regardless of the mode, the I/O port data is written to a buffer memory and only affects operation of the part after the contents of the buffer memory are transferred to the register banks. This transfer of information occurs synchronously to the system clock in one of two ways: • Internally, at a rate programmable by the user. • Externally, by the user. I/O operations can occur in the absence of REFCLK, but the data cannot be moved from the buffer memory to the register bank without REFCLK. (See the Internal and External Update Clock section for more details.) MASTER RESET The MASTER RESET pin must be held at logic high active for a minimum of 10 system clock cycles. This initializes the communications bus and loads the default values listed in the Table 8 section. Table 7. REFCLK Multiplier Control Register Values Reference Multiplier Multiplier Value Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4 0 0 1 0 0 5 0 0 1 0 1 6 0 0 1 1 0 7 0 0 1 1 1 8 0 1 0 0 0 9 0 1 0 0 1 10 0 1 0 1 0 11 0 1 0 1 1 12 0 1 1 0 0 13 0 1 1 0 1 14 0 1 1 1 0 15 0 1 1 1 1 16 1 0 0 0 0 17 1 0 0 0 1 18 1 0 0 1 0 19 1 0 0 1 1 20 1 0 1 0 0 Rev. E | Page 32 of 52 AD9854 Table 8. Register Layout1 Parallel Serial Address Address (Hex) (Hex) Bit 7 Bit 6 Bit 5 AD9854 Register Layout Bit 4 Bit 3 Bit 2 00 0 Phase Adjust Register 1 <13:8> (Bits 15, 14, don’t care) Phase 1 01 Phase Adjust Register 1 <7:0> 02 1 Phase Adjust Register 2 <13:8> (Bits 15, 14, don’t care) Phase 2 03 Phase Adjust Register 2 <7:0> 04 2 Frequency Tuning Word 1 <47:40> Freq 1 05 Frequency Tuning Word 1 <39:32> 06 Frequency Tuning Word 1 <31:24> 07 Frequency Tuning Word 1 <23:16> 08 Frequency Tuning Word 1 <15:8> 09 Frequency Tuning Word 1 <7:0> 0A 3 Frequency Tuning Word 2 <47:40> 0B Frequency Tuning Word 2 <39:32> 0C Frequency Tuning Word 2 <31:24> 0D Frequency Tuning Word 2 <23:16> 0E Frequency Tuning Word 2 <15:8> 0F Frequency Tuning Word 2 <7:0> 10 4 Delta frequency word <47:40> 11 Delta frequency word <39:32> 12 Delta frequency word <31:24> 13 Delta frequency word <23:16> 14 Delta frequency word <15:8> 15 Delta frequency word <7:0> 16 5 Update clock <31:24> 17 Update clock <23:16> 18 Update clock <15:8> 19 Update clock <7:0> 1A 6 Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don’t care) 1B Ramp rate clock <15:8> 1C Ramp rate clock <7:0> 1D 7 Don’t care CR [31] Don’t care Don’t care Comp Reserved, PD always low QDAC PD 1E Don’t PLL Bypass Ref Ref Mult 3 Ref Mult 2 care range PLL Mult 4 1F CLR CLR Triangle SRC Mode 2 Mode 1 ACC 1 ACC 2 QDAC 20 Don’t Bypass OSK EN OSK Don’t care Don’t care care inv sinc INT 21 8 Output shaped keying I multiplier <11:8> (Bits 15, 14, 13, 12 don’t care) 22 Output shaped keying I multiplier <7:0> 23 9 Output shaped keying Q multiplier <11:8> (Bits 15, 14, 13, 12 don’t care) 24 Output shaped keying Q multiplier <7:0> 25 A Output shaped keying ramp rate <7:0> 26 B QDAC <11:8> (Bits 15, 14, 13, 12 don’t care) 27 QDAC <7:0> (data is required to be in twos complement format) Bit 1 DAC PD Ref Mult 1 Mode 0 LSB first Bit 0 DIG PD Default Value (Hex) 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 00 00 10 Ref Mult 0 64 Internal/external 01 update clock SDO active CR [0] 20 00 00 00 00 80 00 1 The shaded sections comprise the control register. Rev. E | Page 33 of 52 AD9854 PARALLEL I/O OPERATION With the S/P SELECT pin tied high, the parallel I/O mode is active. The I/O port is compatible with industry-standard DSPs and microcontrollers. Six address bits, eight bidirectional data bits, and separate write/read control inputs comprise the I/O port pins. Parallel I/O operation allows write access to each byte of any register in a single I/O operation of up to one per 10.5 ns. Readback capability for each register is included to ease designing with the AD9854. (Reads are not guaranteed at 100 MHz because they are intended for software debugging only.) Parallel I/O operation timing diagrams are shown in Figure 52 and Figure 53. SERIAL PORT I/O OPERATION With the S/P SELECT pin tied low, the serial I/O mode is active. The serial port is a flexible, synchronous, serial communication port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola® 6905/11 SPI and Intel® 8051 SSR protocols. The interface allows read/write access to all 12 registers that configure the AD9854 and can be configured as a single-pin I/O (SDIO) or two unidirectional pins for input and output (SDIO/SDO). Data transfers are supported in MSB-or the LSB-first format for up to 10 MHz. When configured for serial I/O operation, most AD9854 parallel port pins are inactive; only some pins are used for the serial I/O operation. Table 9 describes pin requirements for serial I/O operation. Note that when operating the device in serial I/O mode, it is best to use the external I/O update clock mode to avoid an update occurring during a serial communication cycle. Such an occurrence may cause incorrect programming due to a partial data transfer. To exit the default internal update mode, program the device for external update operation at power-up before starting the REFCLK signal but after a master reset. Starting the REFCLK causes this information to transfer to the register bank, forcing the device to switch to external update mode. Table 9. Serial I/O Pin Requirements Pin Number Mnemonic 1 to 8 D [7:0] 14 to 16 A [5:3] 17 A2/IO RESET 18 A1/SDO 19 A0/SDIO 20 I/O UD CLK 21 WR/SCLK 22 RD/CS Serial I/O Description The parallel data pins are not active; tie to VDD or GND. The A5, A4, and A3 parallel address pins are not active; tie these pins to VDD or GND. IO RESET. SDO. SDIO. Update Clock. Same functionality for serial mode as parallel mode. SCLK. CS—Chip Select. Rev. E | Page 34 of 52 A<5:0> D<7:0> RD A<5:0> D<7:0> WR A1 A2 A3 D1 D2 D3 t RDHOZ t RDLOV t AHD t ADV SPECIFICATION t ADV t AHD t RDLOV t RDHOZ VALUE 15ns 5ns 15ns 10ns DESCRIPTION ADDRESS TO DATA VALID TIME (MAXIMUM) ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM) RD LOW TO OUTPUT VALID (MAXIMUM) RD HIGH TO DATA THREE-STATE (MAXIMUM) Figure 52. Parallel Port Read Timing Diagram t WR A1 A2 A3 D1 D2 D3 tASU tWRHIGH tDSU tWRLOW tAHD tDHD SPECIFICATION tASU tDSU tADH tDHD tWRLOW tWRHIGH tWR VALUE DESCRIPTION 8.0ns 3.0ns 0ns 0ns 2.5ns 7ns 10.5ns ADDRESS SETUP TIME TO WR SIGNAL ACTIVE DATA SETUP TIME TO WR SIGNAL ACTIVE ADDRESS HOLD TIME TO WR SIGNAL INACTIVE DATA HOLD TIME TO WR SIGNAL INACTIVE WR SIGNAL MINIMUM LOW TIME WR SIGNAL MINIMUM HIGH TIME MINIMUM WRITE TIME Figure 53. Parallel Port Write Timing Diagram 00636-053 00636-052 AD9854 Rev. E | Page 35 of 52 AD9854 GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases of a serial communication cycle with the AD9854. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9854 coincident with the first eight SCLK rising edges. The instruction byte provides the AD9854 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write and the register address to be acted upon. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9854. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9854 and the system controller. The number of data bytes transferred in Phase 2 of the communication cycle is a function of the register address. (Table 10 describes how many bytes must be transferred.) The AD9854 internal serial I/O controller expects every byte of the register being accessed to be transferred. Therefore, the user should write between I/O update clocks. At the completion of a communication cycle, the AD9854 serial port controller expects the subsequent eight rising SCLK edges to be the instruction byte of the next communication cycle. In addition, an active high input on the IO RESET pin immediately terminates the current communication cycle. After IO RESET returns low, the AD9854 serial port controller requires the subsequent eight rising SCLK edges to be the instruction byte of the next communication cycle. All data input to the AD9854 is registered on the rising edge of SCLK, and all data is driven out of the AD9854 on the falling edge of SCLK. Figure 54 and Figure 55 show the general operation of the AD9854 serial port. Table 10. Register Address vs. Data Bytes Transferred Serial Register Address Register Name 0 Phase Offset Tuning Word Register 1 1 Phase Offset Tuning Word Register 2 2 Frequency Tuning Word 1 3 Frequency Tuning Word 2 4 Delta frequency register 5 Update clock rate register 6 Ramp rate clock register 7 Control register 8 I path digital multiplier register 9 Q path digital multiplier register A Shaped on/off keying ramp rate register B Q DAC register Number of Bytes Transferred 2 2 6 6 6 4 3 4 2 2 1 2 00636-054 CS SDIO INSTRUCTION BYTE DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 INSTRUCTION CYCLE DATA TRANSFER Figure 54. Using SDIO as a Read/Write Transfer CS SDIO SDO INSTRUCTION BYTE INSTRUCTION DATA TRANSFER CYCLE DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 DATA TRANSFER Figure 55. Using SDIO as an Input and SDO as an Output Rev. E | Page 36 of 52 00636-055 AD9854 INSTRUCTION BYTE The instruction byte contains the following information: MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 R/W X X X A3 A2 A1 A0 R/W—Bit 7 determines whether a read or write data transfer occurs following the instruction byte. Logic high indicates read operation. Logic 0 indicates a write operation. Bit 6, Bit 5, and Bit 4 are dummy bits (don’t care). A3, A2, A1, A0—Bit 3, Bit 2, Bit 1, and Bit 0 determine which register is accessed during the data transfer portion of the communication cycle (see Table 8 for register address details). SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK Serial Clock (Pin 21). The serial clock pin is used to synchronize data to and from the AD9854 and to run the internal state machines. The SCLK maximum frequency is 10 MHz. CS Chip Select (Pin 22). Active low input that allows more than one device on the same serial communication line. The SDO and SDIO pins go to a high impedance state when this input is high. If this pin is driven high during a communication cycle, the cycle is suspended until CS is reactivated low. The chip select pin can be tied low in systems that maintain control of SCLK. SDIO Serial Data I/O (Pin 19). Data is always written to the AD9854 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 0 of Register Address 20 hex. The default is Logic 0, which configures the SDIO pin as bidirectional. SDO Serial Data Out (Pin 18). Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9854 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. IO RESET Synchronize I/O Port (Pin 17). Synchronizes the I/O port state machines without affecting the contents of the addressable registers. An active high input on the IO RESET pin causes the current communication cycle to terminate. After the IO RESET pin returns low (Logic 0), another communication cycle can begin, starting with the instruction byte. NOTES ON SERIAL PORT OPERATION The AD9854 serial port configuration bits reside in Bit 1 and Bit 0 of Register Address 20 hex. It is important to note that the configuration changes immediately upon a valid I/O update. For multibyte transfers, writing to this register can occur during the middle of a communication cycle. The user must compensate for this new configuration for the remainder of the current communication cycle. The system must maintain synchronization with the AD9854; otherwise, the internal control logic is not able to recognize further instructions. For example, if the system sends the instruction to write a 2-byte register and then pulses the SCLK pin for a 3-byte register (24 additional SCLK rising edges), communication synchronization is lost. In this case, the first 16 SCLK rising edges after the instruction cycle properly write the first two data bytes into the AD9854, but the subsequent eight rising SCLK edges are interpreted as the next instruction byte, not the final byte of the previous communication cycle. In the case where synchronization is lost between the system and the AD9854, the IO RESET pin provides a means to reestablish synchronization without reinitializing the entire chip. Asserting the IO RESET pin (active high) resets the AD9854 serial port state machine, terminating the current I/O operation and forcing the device into a state in which the next eight SCLK rising edges are understood to be an instruction byte. The IO RESET pin must be deasserted (low) before the next instruction byte write can begin. Any information written to the AD9854 registers during a valid communication cycle prior to loss of synchronization remains intact. t PRE t SCLK CS t DSU t SCLKPWH t SCLKPWL SCLK SDIO t DHLD FIRST BIT SECOND BIT SYMBOL t PRE t SCLK t DSU t SCLKPWH t SCLKPWL t DHLD MIN 30ns 100ns 30ns 40ns 40ns 0ns DEFINITION CS SETUP TIME PERIOD OF SERIAL DATA CLOCK SERIAL DATA SETUP TIME SERIAL DATA CLOCK PULSE WIDTH HIGH SERIAL DATA CLOCK PULSE WIDTH LOW SERIAL DATA HOLD TIME Figure 56. Timing Diagram for Data Write to AD9854 CS SDIO SDO INSTRUCTION BYTE INSTRUCTION DATA TRANSFER CYCLE DATA BYTE 1 DATA BYTE 2 DATA BYTE 3 DATA TRANSFER Figure 57. Timing Diagram for Read from AD9854 Rev. E | Page 37 of 52 00636-056 00636-057 AD9854 MSB/LSB TRANSFERS The AD9854 serial port can support MSB- and LSB-first data formats. This functionality is controlled by Bit 1 of Serial Register Bank 20 hex. When this bit is set active high, the AD9854 serial port is in LSB-first format. This bit defaults low, to the MSB-first format. The instruction byte must be written in the format indicated by Bit 1 of Serial Register Bank 20 hex. Therefore, if the AD9854 is in LSB-first mode, the instruction byte must be written from least significant bit to most significant bit. CONTROL REGISTER DESCRIPTION The control register is located in the shaded portion of Table 8 at Address 1D to Address 20 hex. It is composed of 32 bits. Bit 31 is located at the top left position, and Bit 0 is located in the lower right position of the shaded portion. In the text that follows, the register descriptions have been subdivided to make it easier to locate the text associated with specific control categories. CR [31:29] are open. CR [28] is the comparator power-down bit. When this bit is set (Logic 1), its signal indicates to the comparator that a powerdown mode is active. This bit is an output of the digital section and is an input to the analog section. CR [27] must always be written to Logic 0. Writing this bit to Logic 1 causes the AD9854 to stop functioning until a master reset is applied. CR [26] is the Q DAC power-down bit. When this bit is set (Logic 1), it indicates to the Q DAC that a power-down mode is active. CR [25] is the full DAC power-down bit. When this bit is set (Logic 1), it indicates to both the I and Q DACs, as well as the reference, that a power-down mode is active. CR [24] is the digital power-down bit. When this bit is set (Logic 1), its signal indicates to the digital section that a powerdown mode is active. Within the digital section, the clocks are forced to dc, effectively powering down the digital section. In this state, the PLL still accepts the REFCLK signal and continues to output the higher frequency. CR [23] is reserved. Write to 0. CR [22] is the PLL range bit, which controls the VCO gain. The power-up state of the PLL range bit is Logic 1; a higher gain is required for frequencies greater than 200 MHz. CR [21] is the bypass PLL bit, active high. When this bit is active, the PLL is powered down and the REFCLK input is used to drive the system clock signal. The power-up state of the bypass PLL bit is Logic 1 with PLL bypassed. CR [20:16] bits are the PLL multiplier factor. These bits are the REFCLK multiplication factor unless the bypass PLL bit is set. The PLL multiplier valid range is from 4 to 20, inclusive. CR [15] is the Clear Accumulator 1 bit. This bit has a one-shot type of function. When this bit is written active (Logic 1), a Clear Accumulator 1 signal is sent to the DDS logic, resetting the accumulator value to 0. The bit is then automatically reset, but the buffer memory is not reset. This bit allows the user to easily create a sawtooth frequency sweep pattern with minimal intervention. This bit is intended for chirp mode only, but its function is still retained in other modes. CR [14] is the clear accumulator bit. When this bit is active high, it holds both the Accumulator 1 and Accumulator 2 values at 0 for as long as the bit is active. This allows the DDS phase to be initialized via the I/O port. CR [13] is the triangle bit. When this bit is set, the AD9854 automatically performs a continuous frequency sweep from F1 to F2 frequencies and back. This results in a triangular frequency sweep. When this bit is set, the operating mode must be set to ramped FSK. CR [12] is the source Q DAC bit. When this bit is set high, the Q path DAC accepts data from the Q DAC register. CR [11:9] are the three bits that describe the five operating modes of the AD9854: 0x0 = single-tone mode 0x1 = FSK mode 0x2 = ramped FSK mode 0x3 = chirp mode 0x4 = BPSK mode Rev. E | Page 38 of 52 CS SCLK SDIO INSTRUCTION CYCLE DATA TRANSFER CYCLE I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 58. Serial Port Write Timing Clock Stall Low 00636-058 AD9854 CS SCLK SDIO I7 SDO INSTRUCTION CYCLE DATA TRANSFER CYCLE I6 I5 I4 I3 I2 I1 I0 DON'T CARE DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Figure 59. 3-Wire Serial Port Read Timing Clock Stall Low 00636-059 CS SCLK SDIO INSTRUCTION CYCLE DATA TRANSFER CYCLE I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 Figure 60. Serial Port Write Timing Clock Stall High D3 D2 D1 D0 00636-060 CS SCLK SDIO INSTRUCTION CYCLE DATA TRANSFER CYCLE I7 I6 I5 I4 I3 I2 I1 I0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Figure 61. 2-Wire Serial Port Read Timing Clock Stall High 00636-061 CR [8] is the internal update active bit. When this bit is set to Logic 1, the I/O UD CLK pin is an output and the AD9854 generates the I/O UD CLK signal. When this bit is set to Logic 0, external I/O UD CLK functionality is performed and the I/O UD CLK pin is configured as an input. CR [7] is reserved. Write to 0. CR [6] is the inverse sinc filter bypass bit. When this bit is set, the data from the DDS block goes directly to the output shaped keying logic, and the clock to the inverse sinc filter is stopped. Default is clear with the filter enabled. CR [5] is the shaped keying enable bit. When this bit is set, the output ramping function is enabled and is performed in accordance with the CR [4] bit requirements. CR [4] is the internal/external output shaped keying control bit. When this bit is set to Logic 1, the output shaped keying factor is internally generated and applied to both the I and Q paths. When this bit is cleared (default), the output shaped keying function is externally controlled by the user, and the ouput shaped keying factor is the value of the I and Q output shaped keying factor register. The two registers that are the output shaped keying factors also default low such that the output is off at power-up until the device is programmed by the user. CR [3:2] are reserved. Write to 0. CR [1] is the serial port MSB-/LSB-first bit. Default is low, MSB first. CR [0] is the serial port SDO active bit. Default is low, inactive. Rev. E | Page 39 of 52 AD9854 POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9854 is a multifunctional, high speed device that targets a wide variety of synthesizer and agile clock applications. The numerous innovative features contained in the device each consume incremental power. If enabled in combination, the safe thermal operating conditions of the device may be exceeded. Careful analysis and consideration of power dissipation and thermal management is a critical element in the successful application of the AD9854. However, in most cases, disabling the inverse sinc filter prevents exceeding the maximum die temperature, because the inverse sinc filter consumes approximately 30% of the total power. The AD9854 is specified to operate within the industrial temperature range of −40°C to +85°C. This specification is conditional, however, such that the absolute maximum junction temperature of 150°C is not exceeded. At high operating temperatures, extreme care must be taken when operating the device to avoid exceeding the junction temperature and potentially damaging the device. Many variables contribute to the operating junction temperature within the device, including • Package style • Selected mode of operation • Internal system clock speed • Supply voltage • Ambient temperature The combination of these variables determines the junction temperature within the AD9854 for a given set of operating conditions. The AD9854 is available in two package styles: a thermally enhanced surface-mount package with an exposed heat sink and a standard (nonthermally enhanced) surface-mount package. The thermal impedance of these packages is 16.2°C/W and 38°C/W, respectively, measured under still air conditions. THERMAL IMPEDANCE The thermal impedance of a package can be thought of as a thermal resistor that exists between the semiconductor surface and the ambient air. The thermal impedance is determined by the package material and the physical dimensions of the package. The dissipation of the heat from the package is directly dependent on the ambient air conditions and the physical connection made between the IC package and the PCB. Adequate dissipation of heat from the AD9854 relies on all power and ground pins of the device being soldered directly to a copper plane on a PCB. In addition, the thermally enhanced package of the AD9854ASVZ has an exposed paddle on the bottom of the package that must be soldered to a large copper plane, which, for convenience, can be the ground plane. Sockets for either package style of the device are not recommended. JUNCTION TEMPERATURE CONSIDERATIONS The power dissipation (PDISS) of the AD9854 in a given application is determined by many operating conditions. Some of the conditions have a direct relationship with PDISS, such as supply voltage and clock speed, but others are less deterministic. The total power dissipation within the device and its effect on the junction temperature must be considered when using the device. The junction temperature of the device is given by (Thermal Impedance × Power Consumption) + Ambient Temperature The maximum ambient temperature combined with the maximum junction temperature establishes the following power consumption limits for each package: 4.06 W for ASVZ models and 1.71 W for ASTZ models. Supply Voltage The supply voltage affects power dissipation and junction temperature because PDISS = V × I. Users should design for 3.3 V nominal; however, the device is guaranteed to meet specifications over the full temperature range and over the supply voltage range of 3.135 V to 3.465 V. Clock Speed Clock speed directly and linearly influences the total power dissipation of the device and therefore the junction temperature. As a rule, to minimize power dissipation, the user should select the lowest possible internal clock speed to support a given application. Typically, the usable frequency output bandwidth from a DDS is limited to 40% of the clock rate to ensure that the requirements of the output low-pass filter are reasonable. For a typical DDS application, the system clock frequency should be 2.5 times the highest desired output frequency. Mode of Operation The selected mode of operation of the AD9854 significantly influences the total power consumption. Although the AD9854 offers many features targeting a wide variety of applications, the device is designed to operate with only a few features enabled at once for a given application. If multiple features are enabled at higher clock speeds, the maximum junction temperature of the die may be exceeded, severely limiting the long-term reliability of the device. Figure 62 and Figure 63 show the power requirements associated with each feature of the AD9854. These graphs should be used as a guide in determining power consumption for specific feature sets. Figure 62 shows the supply current consumed by the AD9854 over a range of frequencies for two possible configurations. All circuits enabled means that the output scaling multipliers, the inverse sinc filter, the Q DAC, and the on-board comparator are enabled. Basic configuration means that the output scaling Rev. E | Page 40 of 52 multipliers, the inverse sinc filter, the Q DAC, and the on-board comparator are disabled. 1400 1200 1000 ALL CIRCUITS ENABLED SUPPLY CURRENT (mA) 800 600 400 200 0 20 BASIC CONFIGURATION 60 100 140 180 220 260 300 FREQUENCY (MHz) NOTES THIS GRAPH ASSUMES THAT THE AD9854 DEVICE IS SOLDERED TO A MULTILAYER PCB PER THE RECOMMENDED BEST MANUFACTURING PRACTICES AND PROCEDURES FOR THE GIVEN PACKAGE TYPE. Figure 62. Current Consumption vs. Clock Frequency 00636-062 Figure 63 shows the approximate current consumed by each of four functions. 500 450 INVERSE SINC FILTER 400 350 300 SUPPLY CURRENT (mA) 250 200 OUTPUT SCALING MULTIPLIERS 150 100 Q DAC COMPARATOR 50 0 20 60 100 140 180 220 260 300 FREQUENCY (MHz) 00636-063 NOTES THIS GRAPH ASSUMES THAT THE AD9854 DEVICE IS SOLDERED TO A MULTILAYER PCB PER THE RECOMMENDED BEST MANUFACTURING PRACTICES AND PROCEDURES FOR THE GIVEN PACKAGE TYPE. Figure 63. Current Consumption by Function vs. Clock Frequency AD9854 EVALUATION OF OPERATING CONDITIONS The first step in applying the AD9854 is to select the internal clock frequency. Clock frequency selections greater than 200 MHz require the use of the thermally enhanced package (AD9854ASVZ); other clock frequencies may allow the use of the standard plastic surface-mount package, but more information is needed to make that determination. The second evaluation step is to determine the maximum required operating temperature for the AD9854 in a given application. Subtract this value from 150°C, which is the maximum junction temperature allowed for the AD9854. For the extended industrial temperature range, the maximum operating temperature is 85°C, which results in a difference of 65°C. This is the maximum temperature gradient that the device can experience due to power dissipation. The third evaluation step is to divide the maximum temperature gradient by the thermal impedance to determine the maximum power dissipation allowed for the application. For example, 65°C divided by the thermal impedance of the package being used yields the total power dissipation limit (4.06 W for the ASVZ models and 1.71 W for the ASTZ models). Therefore, for a 3.3 V nominal power supply voltage, the current consumed by the device with full operating conditions must not exceed 515 mA for the standard plastic package and 1242 mA for the thermally enhanced package. The total set of enabled functions and operating conditions of the AD9854 application must support these current consumption limits. To determine the suitability of a given AD9854 application in terms of the power dissipation requirements use Figure 62 and Figure 63. These graphs assume that the AD9854 device is soldered to a multilayer PCB per the recommended best manufacturing practices and procedures for the given package type. This ensures that the specified thermal impedance specifications are achieved. THERMALLY ENHANCED PACKAGE MOUNTING GUIDELINES Refer to the AN-772 Application Note for details on mounting devices with an exposed paddle. Rev. E | Page 41 of 52 AD9854 EVALUATION BOARD An evaluation board package is available for the AD9854 DDS Hardware Preparation device. This package consists of a PCB, software, and documentation to facilitate bench analysis of the device’s performance. To ensure optimum dynamic performance from the device, users should familiarize themselves with the operation and performance capabilities of the AD9854 with the evaluation board and use the evaluation board as a PCB reference design. EVALUATION BOARD INSTRUCTIONS Use the schematics (see Figure 64 and Figure 65) in conjunction with these instructions to become acquainted with the electrical functioning of the evaluation board. Attach power wires to the connector labeled TB1 using the screw-down terminals. This connector is plastic and press-fits over a 4-pin header soldered to the board. Table 11 lists the connections to each pin. The AD9852/AD9854 Revision E evaluation board includes either an AD9852ASVZ or AD9854ASVZ IC. Table 11. Power Requirements for DUT Pins1 The ASVZ package permits 300 MHz operation by virtue of its thermally enhanced design. This package has a bottom-side heat slug that must be soldered to the ground plane of the PCB directly beneath the IC. In this manner, the evaluation board AVDD 3.3 V For all DUT analog pins DVDD 3.3 V For all DUT digital pins 1 DUT = device under test. VCC 3.3 V For all other devices Ground For all devices PCB ground plane layer extracts heat from the AD9852 or AD9854 IC package. If device operation is limited to 200 MHz Clock Input, J25 or less, the ASTZ package can be used without a heat slug in customer installations over the full temperature range. Attach REFCLK to the clock input, J25. This is a single-ended input that is routed to the MC100LVEL16D for conversion to Evaluation boards for both the AD9852 and AD9854 are identical except for the installed IC. differential PECL output. This is accomplished by attaching a 2 V p-p clock or sine wave source to J25. Note that this is a 50 Ω impedance point set by R13. The input signal is ac-coupled and To assist in proper placement of the pin header shorting jumpers, the instructions refer to direction (left, right, top, bottom) as well as header pins to be shorted. Pin 1 for each 3-pin header is marked on the PCB corresponding with the then biased to the center-switching threshold of the MC100LVEL16D. To engage the differential clocking mode of the AD9854, Pin 2 and Pin 3 (the bottom two pins) of W3 must be connected with a shorting jumper. schematic diagram. When following these instructions, position the PCB so that the PCB text can be read from left to right. The board is shipped with the pin headers configuring the board as follows: The signal arriving at the AD9854 is called the reference clock. When engaging the on-chip PLL clock multiplier, this signal is the reference clock for the PLL and the multiplied PLL output becomes the system clock. If the PLL clock multiplier is to be • REFCLK for the AD9852 or AD9854 is configured as differential. The differential clock signals are provided by bypassed, the reference clock supplied by the user directly operates the AD9854 and is therefore the system clock. the MC100LVEL16D differential receiver. • The input clock for the MC100LVEL16D is single ended via J25. This signal may be 3.3 V CMOS or a 2 V p-p sine wave capable of driving 50 Ω (R13). • Both DAC outputs from the AD9852 or AD9854 are Three-State Control The W9, W11, W12, W13, W14, and W15 switch headers must be shorted to allow the provided software to control the AD9854 evaluation board via the printer port connector, J11. routed through the two 120 MHz elliptical LP filters, and their outputs are connected to J7 (Q, or control DAC) and J6 (I, or cosine DAC). • The board is set up for software control via the printer port connector. • The output currents of the DAC are configured for 10 mA. Programming If programming of the AD9854 is not to be provided by the user’s PC and Analog Devices software, the W9, W11, W12, W13, W14, and W15 headers should be opened (shorting jumpers removed). This effectively detaches the PC interface and allows J10 (the 40-pin header) and J1 to assume control GENERAL OPERATING INSTRUCTIONS Load the CD software onto your PC’s hard disk. The current without bus contention. Input signals on J10 and J1 going to the AD9854 should be 3.3 V CMOS logic levels. software (Version 1.72) supports Windows® 95, Windows 98, Low-Pass Filter Testing Windows 2000, Windows NT®, and Windows XP. The purpose of the 2-pin W7 and W10 headers (associated with Connect a printer cable from the PC to the AD9854 evaluation board printer port connector labeled J11. J4 and J5) is to allow the two 50 Ω, 120 MHz filters to be tested during PCB assembly without interference from other circuitry attached to the filter inputs. Typically, a shorting jumper is Rev. E | Page 42 of 52 AD9854 attached to each header to allow the DAC signals to be routed to the filters. If the user wishes to test the filters, the shorting jumpers at W7 and W10 should be removed and 50 Ω test signals should be applied at the J4 and J5 inputs to the 50 Ω elliptic filters. Users should refer to the schematic provided and to the following sections to properly position the remaining shorting jumpers. The resulting I and Q signals appear as nearly pure sine waves and 90° out of phase with each other. These filters are designed with the assumption that the system clock speed is at or near its maximum speed (300 MHz). If the system clock speed is much less than 300 MHz, for example 200 MHz, it is possible, or inevitable, that unwanted DAC products other than the fundamental signal will be passed by the low-pass filters. Observing the Unfiltered IOUT1 and the Unfiltered IOUT2 DAC Signals The unfiltered DAC outputs can be observed at J5 (the I, or cosine DAC, signal) and J4 (the Q, or control DAC, signal). Use the following procedure to route the two 50 Ω terminated analog DAC outputs to the SMB connectors and to disconnect any other circuitry: 1. Install shorting jumpers at W7 and W10. 2. Remove the shorting jumper at W16. 3. Remove the shorting jumper from the 3-pin W1 header. 4. Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins) of the 3-pin W4 header. The raw DAC outputs may appear as a series of quantized (stepped) output levels that may not resemble a sine wave until they are filtered. The default 10 mA output current develops a 0.5 V p-p signal across the on-board 50 Ω termination. If the observation equipment offers 50 Ω inputs, the DAC develops only 0.25 V p-p due to the double termination. If using the AD9852 evaluation board, the user can control IOUT2 (the control DAC output) by using the serial or parallel ports. The 12-bit, twos complement value(s) is/are written to the control DAC register that sets the IOUT2 output to a static dc level. Allowable hexadecimal values are 7FF (maximum) to 800 (minimum), with all 0s being midscale. Rapidly changing the contents of the control DAC register (up to 100 MSPS) allows IOUT2 to assume any waveform that can be programmed. Observing the Filtered IOUT1 and the Filtered IOUT2 The filtered I (cosine DAC) and Q (control DAC) outputs can be observed at J6 (for the I signal) and J7 (for the Q signal). Use the following procedure to route the 50 Ω (input and output Z) low-pass filters into the pathways of the I and Q signals to remove images, aliased harmonics, and other spurious signals that are greater than approximately 120 MHz: 1. Install shorting jumpers at W7 and W10. 2. Install a shorting jumper at W16. 3. Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins) of the 3-pin W1 header. 4. Install a shorting jumper on Pin 1 and Pin 2 (bottom two pins) of the 3-pin W4 header. 5. Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins) of the 3-pin W2 and W8 headers. If the AD9852 evaluation board is used, any reference to the Q signal should be interpreted as meaning the control DAC. Observing the Filtered IOUT1 and the Filtered IOUT1 The filtered I DAC outputs can be observed at J6 (the true signal) and J7 (the complementary signal). Use the following procedure to route the 120 MHz low-pass filters in the true and complementary output paths of the I DAC to remove images, aliased harmonics, and other spurious signals that are greater than approximately 120 MHz: 1. Install shorting jumpers at W7 and W10. 2. Install a shorting jumper at W16. 3. Install a shorting jumper on Pin 2 and Pin 3 (top two pins) of the 3-pin W1 header. 4. Install a shorting jumper on Pin 2 and Pin 3 (top two pins) of the 3-pin W4 header. 5. Install a shorting jumper on Pin 2 and Pin 3 (bottom two pins) of the 3-pin W2 and W8 headers. The resulting signals appear as nearly pure sine waves and 180° out of phase with each other. If the system clock speed is much less than 300 MHz, for example 200 MHz, it is possible, or inevitable, that unwanted DAC products other than the fundamental signal will be passed by the low-pass filters. Connecting the High Speed Comparator To connect the high speed comparator to the DAC output signals use either the quadrature filtered output configuration (for AD9854 only) or the complementary filtered output configuration outlined in the previous section (for both the AD9854 and the AD9852). Follow Step 1 through Step 4 in either the Observing the Filtered IOUT1 and the Filtered IOUT2 section or the Observing the Filtered IOUT1 and the Filtered IOUT1 section. Then install a shorting jumper on Pin 1 and Pin 2 (top two pins) of the 3-pin W2 and W8 headers. This reroutes the filtered signals away from the output connectors (J6 and J7) and to the 100 Ω configured comparator inputs. This sets up the comparator for differential input without affecting the comparator output duty cycle, which should be approximately 50% in this configuration. The user can change the value of RSET Resistor R2 from 3.9 kΩ to 1.95 kΩ to receive more robust signals at the comparator inputs. This decreases jitter and extends the operating range of the comparator. To implement this change install a shorting jumper at W6, which provides a second 3.9 kΩ chip resistor (R20) in parallel with that provided by R2. This boosts the DAC Rev. E | Page 43 of 52 AD9854 output current from 10 mA to 20 mA and doubles the peak-topeak output voltage developed across the loads, thus resulting in more robust signals at the comparator inputs. Single-Ended Configuration To connect the high speed comparator in a single-ended configuration so that the duty cycle or pulse width can be controlled, a dc threshold voltage must be present at one of the comparator inputs. The user can supply this voltage using the control DAC. A 12-bit, twos complement value is written to the control DAC register that sets the IOUT2 output to a static dc level. Allowable hexadecimal values are 7FF (maximum) to 800 (minimum), with all 0s being midscale. The IOUT1 channel continues to output a filtered sine wave programmed by the user. These two signals are routed to the comparator by using the 3-pin W2 and W8 header switches. Use of the configuration described in the Observing the Filtered IOUT1 and the Filtered IOUT2 section is required. Follow Step 1 through Step 4 in this section, and then install a shorting jumper on Pin 1 and Pin 2 (top two pins) of the 3-pin W2 and W8 headers. The user can change the value of RSET Resistor R2 from 3.9 kΩ to 1.95 kΩ to receive more robust signals at the comparator inputs. This decreases jitter and extends the operating range of the comparator. To implement this change install a shorting jumper at W6, which provides a second 3.9 kΩ chip resistor (R20) in parallel with that provided by R2. USING THE PROVIDED SOFTWARE The evaluation software is provided on a CD, along with a brief set of instructions. Use the instructions in conjunction with the AD9852 or AD9854 data sheet and the AD9852 or AD9854 evaluation board schematic. The CD contains the following: • The AD9852/AD9854 evaluation software • AD9854 evaluation board instructions • AD9854 data sheet • AD9854 evaluation board schematics • AD9854 PCB layout Several numerical entries, such as frequency and phase information, require pressing Enter to register the information. For example, if a new frequency is input but does not take effect when Load is clicked, the user probably neglected to press Enter after typing the new frequency information. Normal operation of the AD9852/AD9854 evaluation board begins with a master reset. After this reset, many of the default register values are depicted in the software control panel. The reset command sets the DDS output amplitude to minimum and 0 Hz, zero phase offset, as well as other states that are listed in the Register Layout table (Table 8 for AD9854). The next programming block should be the reference clock and multiplier because this information is used to determine the proper 48-bit frequency tuning words that are entered and later calculated. The output amplitude defaults to the 12-bit, straight binary multiplier values of the I (cosine DAC) multiplier register of 000 hex; no output (dc) should be seen from the DAC. Set the multiplier amplitude in the Output Amplitude dialog box to a substantial value, such as FFF hex. The digital multiplier can be bypassed by selecting Output Amplitude is always Full Scale, but this usually does not result in the best spurious-free dynamic range (SFDR). The best SFDR, achieving improvements of up to 11 dB, is obtained by routing the signal through the digital multiplier and then reducing the multiplier amplitude. For instance, FC0 hex produces less spurious signal amplitude than FFF hex. If SFDR must be maximized, this exploitable and repeatable phenomenon should be investigated in the given application. This phenomenon is more readily observed at higher output frequencies, where good SFDR becomes more difficult to achieve. Refer to this data sheet and the evaluation board schematic to understand the available functions of the AD9854 and how the software responds to programming commands. SUPPORT Applications assistance is available for the AD9854, the AD9854 PCB evaluation board, and all other Analog Devices products. Call 1-800-ANALOGD or visit www.analog.com/dds. Rev. E | Page 44 of 52 AD9854 Table 12. AD9854 Customer Evaluation Board (AD9854 PCB > U1 = AD9854ASVZ) Reference Item Qty Designator Device Package Value Min Tol Manufacturer 1 3 C1, C2, C45 Capacitor 0805 805 0.01 μF, 10% Kemet Corp. 50 V, X7R 2 21 C7, C8, C9, C10, Capacitor 0603 603 C11, C12, C13, C14, C16, C17, C18, C19, C20, C22, C23, C24, C26, C27, C28, C29, C44 0.1 μF, 10% Murata 50 V, X7R Manufacturing Co., Ltd. 3 2 C4, C37 Capacitor 1206 1206 27 pF, 5% 50 V, NPO Yageo Corporation 4 2 C5, C38 Capacitor 1206 1206 47 pF, 5% 50 V, NPO Yageo Corporation 5 3 C6, C21, C25 Capacitor TAJC TAJC 10 μF, 16 V, TAJ 10% AVX 6 2 C30, C39 Capacitor 1206 1206 39 pF, 5% 50 V, NPO Yageo Corporation 7 2 C31, C40 Capacitor 1206 1206 22 pF, 5% 50 V, NPO Yageo Corporation 8 2 C32, C41 Capacitor 1206 1206 2.2 pF, 0.25 Yageo Corporation 50 V, NPO pF 9 2 C33, C42 Capacitor 1206 1206 12 pF, 5% 50 V, NPO Yageo Corporation 10 2 C34, C43 Capacitor 1206 1206 8.2 pF, 0.5 50 V, NPO pF Yageo Corporation 11 9 J1, J2, J3, J4, J5, SMB J6, J7, J25, J26 STR-PC MNT N/A N/A Emerson/Johnson 12 1 J10 40-pin header Header 40 N/A N/A Samtec, Inc. 13 4 L1, L2, L3, L5 Inductor coil 1008CS 68 nH 2% Coilcraft, Inc. 14 2 L4, L6 Inductor coil 1008CS 82 nH 2% Coilcraft, Inc. 15 2 R1, R5 RES_SM 1206 49.9 Ω, ¼W 1% Panasonic-ECG 16 2 R2, R20 RES_SM 1206 3.92 kΩ, 1% Panasonic-ECG ¼W 17 2 R3, R7 RES_SM 1206 24.9 Ω, ¼W 1% Panasonic-ECG 18 1 R4 RES_SM 1206 1.3 kΩ, ¼W 1% Panasonic-ECG 19 4 R6, R11, R12, R13 RES_SM 1206 49.9 Ω, ¼W 1% Panasonic-ECG 20 1 R8 RES_SM 1206 2 kΩ, ¼W 1% Panasonic-ECG 21 2 R9, R10 RES_SM 1206 100 Ω, ¼W 1% Panasonic-ECG 22 4 R15, R16, R17, R18 RES_SM 1206 10 kΩ, ¼W 1% Panasonic-ECG 23 1 RP1 Resistor network SIP-10P 10 kΩ 2% Bourns 24 1 TB1 TB4 4-position N/A N/A Wieland Electric, Inc. terminal 25 1 U1 AD9854 SV-80 N/A N/A Analog Devices, Inc. 26 1 U2 74HC125D 14 SOIC N/A N/A Texas Instruments Incorporated Manufacturer Part No. C0805C103K5RACTU GRM188R71H104KA93D CC1206JRNPO9BN270 CC1206JRNPO9BN470 TAJC106K016R CC1206JRNPO9BN390 CC1206JRNPO9BN220 CC1206CRNPO9BN2R2 1206CG120J9B200 CC1206DRNPO9BN8R2 131-3701-261 TSW-120-23-L-D 1008CS-680XGLB 1008CS-820XGLB ERJ-8ENF49R9V ERJ-8ENF3921V ERJ-8ENF24R9 ERJ-8ENF1301V ERJ-8ENF49R9V ERJ-8ENF2001V ERJ-8ENF1000V ERJ-8ENF1002V 4610X-101-103LF Plug: 25.602.2453.0; terminal strip: Z5.530.3425.0 AD9854ASVZ SN74HC125DR Rev. E | Page 45 of 52 AD9854 Reference Item Qty Designator 27 1 U3 Device Primary Secondary Package 8 SOIC 8 SOIC Value N/A N/A 28 4 U4, U5, U6, U7 74HC14 14 SOIC N/A 29 3 U8, U9, U10 74HC574 20 SOIC N/A 30 1 J11 C36CRPX 36CRP N/A 31 6 W1, W2, W3, W4, 3-pin header SIP-3P N/A W8, W17 32 10 W6, W7, W9, 2-pin header SIP-2P N/A W10, W11, W12, W13, W14, W15, W16 33 6 W1, W2, W3, W4, Jumpers N/A W8, W17 Black 34 10 W6, W7, W9, Jumpers N/A W10, W11, W12, W13, W14, W15, W16 Black 35 2 N/A Self-tapping screw 4–40, Phillips N/A pan head 36 4 N/A Adhesive feet N/A Black 37 1 AD9852/54 PCB N/A N/A N/A 38 2 R14, R19 RES_SM 1206 0 Ω, ¼W 39 4 N/A Pin socket (open end) 40 1 Y1 XTAL COSC N/A Min Tol Manufacturer Manufacturer Part No. N/A ON Semiconductor Primary: MC10EP16DGOS N/A ON Semiconductor Secondary: MC100LVEL16DGOS N/A Texas Instruments SN74HC14DR Incorporated N/A Texas Instruments SN74HC574DWR Incorporated N/A Tyco Electronics Corporation 5552742-1 N/A Samtec, Inc. TSW-103-07-S-S N/A Samtec, Inc. TSW-102-07-S-S N/A Samtec, Inc. N/A Samtec, Inc. SNT-100-BK-G SNT-100-BK-G N/A N/A 3M N/A 5% Panasonic-ECG Tyco Electronics Corporation N/A Optional 90410A107 SJ-5518 GS02669 REV. E ERJ-8GEY0R00V 5-5330808-6 Optional Rev. E | Page 46 of 52 20 40 19 39 18 38 17 37 16 36 15 35 14 34 13 33 12 32 11 31 10 30 9 29 8 28 7 27 6 26 5 25 4 24 3 23 2 22 1 21 D7 D6 D5 D4 D3 D2 D1 D0 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 UDCLK WR RD PMODE OSK RESET DVDD DVDD RESET PMODE CLK CLK8 AVDD AD9854 Figure 64. Evaluation Board Schematic Rev. E | Page 47 of 52 D7 D6 D5 D4 D3 D2 D1 D0 DVDD DVDD GND GND A5 A4 A3 A2/IO RESET A1/SDO A0/SDIO I/O UD CLK J10 GND GND GND DVDD W3 J15 J16 GND GND 1 GND J17 GND AVDD J18 R4 C1 J19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1.3kΩ 0.01µF J20 J22 J24 J8 J6 GND J11 J12 J13 J14 J21 J23 DVDD9 DVDD8 DGND9 DGND8 DGND7 DGND6 DVDD7 DVDD6 OPTGND MRESET SPSELECT REFCLK REFCLK GND4 CLKGND CLKVDD DIFFCLKEN NC5 GND3 PLLFLT 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 PLLVDD 60 PLLGND 59 NC4 58 NC3 57 RSET 56 DACBYPASS 55 AVDD GND W6 R20 3.92kΩ R2 3.92kΩ R1 49.9Ω AVDD GND GND J4 120MHz LOW-PASS FILTER C32 C33 C34 2.2pF 12pF 8.2pF L4 82nH L5 68nH L2 1 68nH J6 W2 GND 7 D1 8 D0 9 DVDD1 10 DVDD2 11 DGND1 12 DGND2 U1 AD9854 TOP VIEW (Not to Scale) AVDD2 54 AGND2 53 IOUT2 52 IOUT2 51 AVDD 50 IOUT1 49 AVDD C45 0.01µF GND R3 AVDD 24.9Ω GND 13 NC IOUT1 48 J5 WR RD DVDD3 DVDD4 DVDD5 DGND3 DGND4 DGND5 FSK/BPSK/HOLD OSK DACDVDD DACDVDD2 DACDGND DACDGND2 NC2 VOUT COUTVDD COUTVDD2 COUTGND COUTGND2 14 ADDR5 15 ADDR4 16 ADDR3 17 ADDR2 18 ADDR1 19 ADDR0 20 UPDCLK AGND 47 GND2 46 COMPGND 45 COMPVDD 44 VINN 43 VINP 42 GND 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND GND GND AVDD W10 R5 49.9Ω GND GND R9 100Ω GND NC = NO CONNECT R10 100Ω AVDD AVDD GND GND WR/SCLK RD/CS DVDD DVDD DVDD GND GND GND OSK AVDD AVDD GND GND GND J1 J26 C4 C5 C30 C31 W7 GND 27pF 47pF 39pF 22pF 1 W1 GND GND GND GND W4 1 R7 R6 GND 24.9Ω 49.9Ω W16 GND GND 120MHz LOW-PASS FILTER C41 2.2pF C42 12pF C43 8.2pF L6 82nH L3 68nH L1 1 68nH J7 W8 GND C37 27pF C38 47pF C39 39pF C40 22pF GND GND GND GND J25 GND 1 W17 R13 C2 GND 49.9Ω 0.01µF Y1 8 7 OUT GND DVDD 14 3.3V NC 1 GND U3 2D Q7 R8 3 D Q6 2kΩ MC100LVEL16DGOS CLKB R19 0Ω J3 GND FDATA GND GND DVDD C25 10µF C24 0.1µF C23 0.1µF C22 0.1µF C27 0.1µF C8 0.1µF C44 0.1µF VEE VBB VCC GND 5 48 GND DVDD R11 49.9Ω R14 0Ω CLK R12 49.9Ω J2 GND TB1 1 2 3 4 VCC C21 10µF AVDD C20 0.1µF C19 0.1µF C18 0.1µF C17 0.1µF C16 0.1µF C14 C26 C28 0.1µF 0.1µF 0.1µF DVDD VCC GND AVDD C6 10µF C7 0.1µF C29 0.1µF C9 0.1µF C10 0.1µF C11 0.1µF C12 0.1µF C13 0.1µF GND GND GND 00636-068 AD9854 Figure 65. Evaluation Board Schematic Rev. E | Page 48 of 52 VCC RP1 10kΩ 1 2 3 4 5 6 7 8 9 10 1 C0 A0 2 A1 3 A2 4 A3 5 A4 6 7 A5 A6 8 A7 9 J11 36PINCONN GND:[19:30] B6 10 11 B7 B5 12 B4 13 14 C1 R15 10kΩ VCC U5 1 1A 1Y 2 3 2A 2Y 4 5 3A 3Y 6 9 4A 4Y 8 11 5A 5Y 10 13 6A 6Y 12 74HC14 VCC GND 14 7 VCC GND VCC U6 1 1A 1Y 2 3 2A 2Y 4 5 3A 3Y 6 9 4A 4Y 8 11 5A 5Y 10 13 6A 6Y 12 74HC14 VCC GND 14 7 VCC GND VCC R16 10kΩ C2 31 B3 32 36 C3 VCC R17 10kΩ VCC VCC U7 1 1A 1Y 2 3 2A 2Y 4 5 3A 3Y 6 9 4A 11 5A 4Y 8 5Y 10 13 6A 6Y 12 74HC14 VCC GND 14 7 VCC GND U8 1 EN VCC: 20 11 C1 GND: 10 74HC574 9 8D 12 D0 8 13 D1 7 14 D2 6 15 D3 5 16 D4 4 17 D5 3 18 D6 2 1D 19 D7 U9 1 EN 11 C1 74HC574 9 8D 8 7 6 5 4 3 2 1D VCC: 20 GND: 10 12 ADDR5 13 ADDR4 14 ADDR3 15 ADDR2 16 17 18 19 VCC VCC R18 10kΩ W15 GND U10 1 EN 11 C1 74HC574 9 8D 8 7 6 5 4 3 2 1D VCC: 20 GND: 10 12 WR 13 RD 14 RESET 15 UDCLK 16 W12 PMODE 17 18 W13 ORAMP 19 W9 FDATA U4 1 1A 3 2A 5 3A 9 4A 11 5A 13 6A 1Y 2 2Y 4 3Y 6 4Y 8 5Y 10 6Y 12 74HC14 VCC VCC GND 14 7 VCC GND ADDR1 W11 ADDR0 W14 U2 1 1G 2 1A 3 1Y 4 2G 5 2A 6 2Y 7 GND VCC 14 4G 13 4A 12 4Y 11 3G 10 3A 9 3Y 8 GND 74HC125D VCC 00636-069 00636-070 AD9854 Figure 66. Assembly Drawing Figure 67. Top Routing Layer, Layer 1 Rev. E | Page 49 of 52 00636-071 00636-072 AD9854 Figure 68. Power Plane Layer, Layer 3 Figure 69. Ground Plane Layer, Layer 2 Rev. E | Page 50 of 52 00636-073 00636-074 AD9854 Figure 70. Bottom Routing Layer, Layer 4 Rev. E | Page 51 of 52 AD9854 OUTLINE DIMENSIONS 0.75 1.20 0.60 MAX 0.45 16.20 16.00 SQ 15.80 80 1 PIN 1 14.20 14.00 SQ 13.80 61 61 60 60 80 1 TOP VIEW (PINS DOWN) EXPOSED PAD 9.50 SQ 091506-A 1.05 1.00 0.95 0.15 0.05 0° MIN 0.20 0.09 7° 3.5° SEATING PLANE 0° 0.08 MAX COPLANARITY 20 21 VIEW A 41 40 41 40 BOTTOM VIEW (PINS UP) 0.65 BSC 0.27 LEAD PITCH 0.22 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-AEC-HD Figure 71. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-80-4) Dimensions shown in millimeters 0.75 0.60 0.45 1.60 MAX 16.20 16.00 SQ 15.80 80 1 PIN 1 61 60 20 21 1.45 1.40 1.35 0.15 0.05 SE ATING PLANE 0.20 0.09 7° 3.5° 0° 0.10 COPLANARITY VIEW A ROTATED 90° CCW TOP VIEW (PINS DOWN) 14.20 14.00 SQ 13.80 20 21 VIEW A 0.65 0.38 BSC LEAD PITCH 0.32 0.22 41 40 051706-A ORDERING GUIDE Model Temperature Range AD9854ASVZ1 −40°C to +85°C AD9854AST −40°C to +85°C AD9854ASTZ1 −40°C to +85°C AD9854/PCB 1 Z = RoHS Compliant Part. COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 72. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters Package Description 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Package Option SV-80-4 ST-80-2 ST-80-2 ©2002–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00636-0-7/07(E) Rev. E | Page 52 of 52

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