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LT8511EX  Datasheet

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Lontium Semiconductor LT8511EX_Datasheet_R1.6 LONTIUM SEMICONDUCTOR CORPORATION ClearedEdge Technology LT8511EX HDMI/DP-VGA/YPbPr Converter Data Sheet We produce mixed-signal products for a better digital world! Confidential 1 Lontium Semiconductor LT8511EX_Datasheet_R1.6 Table of Contents 1. Revision History ......................................................................... 3 .2. General Description ................................................................... 4 2.1 Features .............................................................................................................. 4 2.2 LT8511EX Pin Diagram .................................................................................... 5 2.3 Functional Description ...................................................................................... 6 2.3.1 HDMI RX PHY ........................................................................................ 6 2.3.2 HDCP Engine.......................................................................................... 6 2.3.3 Video Decoder ........................................................................................ 7 2.3.4 Audio Decode ......................................................................................... 7 2.3.5 Info Frame Data...................................................................................... 7 2.3.6 Application Diagram............................................................................... 7 2.4 Pin Descriptions ................................................................................................. 8 2.5 DC Electrical Characteristics ......................................................................... 11 2.5.1 Absolute Maximum Conditions .......................................................... 11 2.5.2 Normal Operating Conditions ............................................................. 11 2.5.3 Digtal I/O Specifications ...................................................................... 12 2.5.4 DC Specifications ................................................................................. 12 2.6 AC Specifications ........................................................................................... 12 2.6.1 TMDS Input Timing Diagrams............................................................ 12 2.6.2 I2S Output Timings ............................................................................... 13 2.6.3 S/PDIF Output port Timing ................................................................. 14 2.6.4 Audio Crystal Timings.......................................................................... 14 2.6.6 RESET# Minimum Timings ................................................................ 15 2.6.7 Power Supply Sequencing.................................................................. 16 3. Package .................................................................................... 17 3.1 LT8511EX-QFN64L(0909x0.85).............................................................. 17 Confidential 2 Lontium Semiconductor 1. Revision History LT8511EX_Datasheet_R1.6 Version Owner Preliminary DSRen Preliminary NWang 1.0 XHGuo 1.1 DSRen 1.2 FChen 1.3 DSRen 1.4 NWang 1.5 NWang 1.6 DSRen Content Date Initial datasheet creation Update package information Update power consumption Update pin description Add dual-mode feature Update VGA output RGB name and order for compliant with LT8511 Check package information Add package die pad information Add ESD information 03/17/2014 03/20/2014 05/12/2014 06/05/2014 06/09/2014 06/10/2014 07/14/2014 11/11/2014 07/27/2016 Confidential 3 Lontium Semiconductor LT8511EX_Datasheet_R1.6 .2. General Description LT8511EX is a low cost, high performance, single port HDMI and dual-mode Displayport receiver which is compliant with HDMI 1.4. The RX can receive 4Kx2K (up to 3.4Gbps data rate) input. Besides, it supports analog video output (VGA or YPbPr) up to 4Kx2K, 1920x1200, and 1080p with three high resolution DACs. The chip integrates dual-mode receiver front end with equalizer, HDMI core and HDCP engine in a single chip. 2.1 Features  HDMI and dual-mode DP receiver equipped with equalizer, supports 4Kx2K, 1920x1200 and 1080p 8/10/12bit deep color, up to 3.4GHz data rate.  Receiver core compliant with HDMI1.4 specification.  HDCP engine compliant with HDCP1.4 spec.  HDCP key stored in MCU for BOM cost reduction.  Supports analog video output (VGA or YPbPr) up to 4Kx2K, 1920x1200, and 1080p with three on chip DACs.  On-chip audio decoder supports 2-channel IIS and SPDIF audio outputs.  Supports audio software mute.  YCC422 to YCC444 conversion.  YCC to RGB and RGB to YCC conversion in ITU-R BT.601 and 709 color space.  Supports separate sync output and SOG/SOY.  Flexible interrupt registers with interrupt pin.  Link on and valid DE detection.  Offered in 64-pin QFN package, and operates over -40°C to +85°C temperature range Confidential 4 Lontium Semiconductor LT8511EX_Datasheet_R1.6 2.2 LT8511EX Pin Diagram 64 pin QFN package, it is named as LT8511EX. Pin diagram is shown as figure1a. VCC33 VSS33 VCC33 VSS33 VDD VSS VSSA33 DAC_R VCCA33 DAC_G VSSA33 DAC_B VCCA33 DAC_REF NC NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PVCC18 1 PVSS18 2 RXC- 3 RXC+ 4 VTERM 5 RX0- 6 RX0+ 7 VSSA33 8 VCCA33 9 RX1- 10 RX1+ 11 VTERM 12 RX2- 13 RX2+ 14 VSSA18 15 VCCA18 16 48 NC 47 DAC_DE 46 DAC_HS 45 DAC_VS 44 DAC_FIELD 43 VSS 42 VDD 41 INT_B 40 S_SCL 39 S_SDA 38 HDCP_M_SCL 37 HDCP_M_SDA 36 RX_DDC_SCL 35 RX_DDC_SDA 34 VSS33 33 VCC33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC VSS VDD VSS33 VCC33 MCLK IIS_SCK IIS_WS IIS_SD0 SPDIF MUTE XTALO XTALI VSS VDD RESET_N Figure 1a: LT8511EX Pin Diagram Confidential 5 Lontium Semiconductor LT8511EX_Datasheet_R1.6 2.3 Functional Description The LT8511EX provides a complete solution for converting HDMI to analog VGA/YPbPr. Figure 2: Function Block Diagram Figure 2 shows the functional blocks of the chip. HDMI or dual-mode data is received by RX PHY, and then decrypted by HDCP engine. The decrypted data is splitted to video and audio data channels. Video channel transfers RGB signal or YCbCr signal according to the type of the display device. A PLL provides an audio clock refer to crystal oscillator, and output audio signal is synchronized with video frame by TMDS clock. 2.3.1 HDMI/Dual-mode DP RX PHY The receiver PHY can support HDMI or dual-mode DP signals, which meets more consumer requirement. And the receiver has built-in equalizer which enables the port to receiver HDMI or dual-mode DP signals through longer cable, and ensures the signal can be recovered better. The receiver is compliant with HDMI 1.4. The receiver front-end can be programmed so the termination voltage is set different from 3.3V for better DP signal detection. The front-end and entire receiver support video resolution up to 4Kx2K , 1920x1200 and 1080p. The chip also integrates on-die-terminations (ODTs), and employs the ODT management circuitry for cost-efficient system design and enhanced performance. 2.3.2 HDCP Engine The LT8511EX includes HDCP 1.4(High‐Bandwidth Digital Content Protection) module with internal memory to store a unique HDCP device key. The HDCP protocol ensures protection from unauthorized duplication of copyrighted media content. The LT8511EX employs a HDCP decryption engine. It contains the decryption logic for all HDMI data (audio, video, and control). Hardware‐implemented HDCP authentication and decryption for audio and video reduces external micro‐controller overhead. HDCP Confidential 6 Lontium Semiconductor LT8511EX_Datasheet_R1.6 decryption and authentication is performed automatically following device initialization. Pre‐programmed HDCP keys and Key Selector Vectors (KSV) are stored in embedded ROM for the decryption process, also provide highest level of security. 2.3.3 Video Decoder Video data is decoded to RGB or YCbCr format through data decoder according to register setting for different application. Output video data supports both separated sync and SOG. When in Sync-On-Green mode, it outputs video data stream to three 10-bit DACs, and the sync signal is composite into the G channel at the DAC by the sync/blanking control module. 2.3.4 Audio Decode Audio data is extracted and decoded from HDMI data stream. The decoded audio data is buffered in audio FIFO. Audio PLL is used to regenerate audio clock from the outside crystal oscillator. Digital audio signals in both IIS and SPDIF format are generated based on this regenerated clock. 2.3.5 InfoFrame Data All types of Packet/InfoFrame data can be extracted, and decoded from HDMI data stream and stored in the internal registers. The AVI (Auxiliary Video Information), Audio and MS (MPEG Source) InfoFrames are always extracted and put in dedicated buffers. Other Packet/InfoFrame type can be selectively extracted and stored in 2 shared packet buffers. Whenever an InfoFrame is received, an interrupt flag is set in internal register and INT_B pin (active low) is asserted. The MCU can read the InfoFrame content through IIC bus. 2.3.6 Application Diagram Figure 3 shows the application of the chip. Graphics Card or Video Decoder LT8511EX Monitor Figure 3: Application Diagram Confidential 7 Lontium Semiconductor LT8511EX_Datasheet_R1.6 2.4 Pin Descriptions (I/O description: A=Analog, I=Input, O=Output, P=Power, G=Ground) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME PVCC18 PVSS18 RXCRXC+ VTERM RX0RX0+ VSSA33 VCCA33 RX1RX1+ VTERM RX2RX2+ VSSA18 VCCA18 17 RESET_N 18 VDD 19 VSS 20 XTALI 21 XTALO 22 MUTE 23 SPDIF 24 I2S_O0 25 WS_O 26 SCLK_O I/O FUNCTION HDMI RX Pins AP Power supply pins for HDMI receiver PLL AG Ground supply pins for HDMI receiver PLL AI HDMI receiver clock negative analog input AI HDMI receiver clock positive analog input AP Terminal power supply AI HDMI receiver channel 0 negative analog input AI HDMI receiver channel 0 positive analog input AG 3.3V ground supply pins for HDMI Receiver AP 3.3V power supply pins for HDMI Receiver AI HDMI receiver channel 1 negative analog input AI HDMI receiver channel 1 positive analog input AP Terminal power supply AI HDMI receiver channel 2 negative analog input AI HDMI receiver channel 2 positive analog input AG 1.8V ground supply pins for HDMI receiver AP 1.8V power supply pins for HDMI receiver Control Pins I Global reset, active low Power Ground Pins P Power supply pins for digital G Ground supply pins for digital Crystal Pins I Crystal oscillator input O Crystal oscillator output Audio Pins O Mute output for audio ports O SPDIF output O I2S serial data output O I2S word select output O I2S serial clock output NOTES 1.8V 3.3V 3.3V 3.3V 1.8V 1.8V 25MHZ Confidential 8 Lontium Semiconductor LT8511EX_Datasheet_R1.6 27 MCLK_O O I2S audio master clock output Power Ground Pins 28 VCC33 P Power supply pins for IO 3.3V 29 VSS33 G Ground supply pins for IO 30 VDD P Power supply pins for digital 1.8V 31 VSS G Ground supply pins for digital 32 NC 33 VCC33 P Power supply pins for IO 3.3V 34 VSS33 G Ground supply pins for IO Control Pins 35 RX_DDC_SDA IO HDMI receiver DDC data 5V-tolerant, channel internal pull-up 36 RX_DDC_SCL IO HDMI receiver DDC clock 5V-tolerant, channel internal pull-up 37 HDCP_M_SDA IO Master I2C data channel 5V-tolerant 38 HDCP_M_SCL IO Master I2C clock channel 5V-tolerant 39 S_SDA IO Slave I2C data channel 5V-tolerant 40 S_SCL IO Slave I2C clock channel 5V-tolerant 41 INT_B O Chip interrupt output, active low Power Ground Pins 42 VDD P Power supply pins for digital 1.8V 43 VSS G Ground supply pins for digital DAC Control Pins 44 DAC_FIELD O Field output to indicate 1st field or 2nd field in an interlaced video output. The polarity can be program by register 45 DAC_VS O VGA vertical sync output 46 DAC_HS O VGA horizontal sync output 47 DAC_DE O Video data enable output. When asserted, the data presented on D0/D1/D2 pins is valid. 48 NC Power Ground Pins 49 VCC33 P Power supply pins for IO 3.3V 50 VSS33 G Ground supply pins for IO 51 VCC33 P Power supply pins for IO 3.3V 52 VSS33 G Ground supply pins for IO 53 VDD P Power supply pins for digital 1.8V 54 VSS G Ground supply pins for digital 55 NC 56 NC DAC Pins 57 VSSA33 AG 3.3V ground supply pins for DAC 58 DAC_R AO VGA R channel or YPbPr Pr channel analog output 59 VCCA33 AP 3.3V power supply pins for DAC 3.3V Confidential 9 Lontium Semiconductor LT8511EX_Datasheet_R1.6 60 DAC_G AO VGA G channel or YPbPr Y channel analog output 61 VSSA33 AG 3.3V ground supply pins for DAC 62 DAC_B AO VGA B channel or YPbPr Pb channel analog output 63 VCCA33 AP 3.3V power supply pins for DAC 3.3V 64 DAC_REF AI DAC reference Confidential 10 Lontium Semiconductor LT8511EX_Datasheet_R1.6 2.5 DC Electrical Characteristics 2.5.1 Absolute Maximum Conditions Symbol Parameter Min Typ Max Units VCC33 3.3V Supply Voltage -0.3 4.0 V VCC18 1.8V Supply Voltage -0.3 2.5 V VI Input Voltage -0.3 VCC33+0.3 V Vo Output Voltage -0.3 VCC33+0.3 V TSTG Storage Temperature -55 125 ºC DIFF33 Difference between two 3.3V power pins 1.0 V DIFF18 Difference between two 1.8V power pins 1.0 V Difference between any DIFF3318 3.3V power pins and 1.8V -1.0 2.0 V power pins Notes: 1. Permanent device damage may occur if absolute maximum conditions are exceeded. 2. Function operation should be restricted to the conditions described under Normal Operating Conditions. 2.5.2 Normal Operating Conditions Symbol Parameter Min Typ VCC33 3.3V Supply Voltage 3.0 3.3 VCC18 1.8V Supply Voltage 1.62 1.8 VCCN Supply Voltage Noise TA Ambient Temperature (with power applied) -40 25 VESD Electrostatic Discharge Max 3.6 1.98 100 85 ±4 Units V V mVp-p ºC kV Confidential 11 Lontium Semiconductor LT8511EX_Datasheet_R1.6 2.5.3 Digtal I/O Specifications Digital I/O spec follows LVTTL spec under normal operating conditions. 2.5.4 DC Specifications Under normal operating conditions unless otherwise specified Symbol Description Conditions Min VID Deferential input voltage, single ended amplitude 150 TMDS clk 1.8V =27M 3.3V ICC Operating current TMDS clk 1.8V =74.25M 3.3V TMDS clk 1.8V =148.5M 3.3V TMDS clk 1.8V =225M 3.3V 2.6 AC Specifications 2.6.1 TMDS Input Timing Diagrams Typ Max Units 700 mV 58 mA 97 mA 82 mA 97 mA 121 mA 97 mA 163 mA 97 mA RX0 RX1 RX2 Tccs VDIFF=0V Figure4: TMDS Channel-to-Channel Skew Timing Symbol Parameter Conditions Min Typ Max Units FRXC Differential Input Clock Frequency 25 340 MHz Confidential 12 Lontium Semiconductor TDPS TCCS TIJIT Intra-Pair(+to-) Differential Input Skew Channel to Channel Differential Input Skew Differential Input Clock Jitter Tolerance LT8511EX_Datasheet_R1.6 0.4Tbit ps 2Tbit ps 0.3Tbit ps 2.6.2 I2S Output Timings T TSCKDUTY tHC SCK 2*TSCK2SD thtr tLC tdtr SD WS Figure5: I2S Output Timings VH VL Symbol Parameter Ttr SCK Clock Period(TX) THC SCK Clock HIGH Time TLC SCK Clock LOW Time Tdtr SCK to SD and WS Thtr Hold Time SCK to SD and WS TSCKDUTY SCK Duty Cycle TSCK2SD SCK-to-SD Delay TAUDDLY Audio Pipeline Delay Conditions Min Typ Max Units CL=10pF 1.0 Ttr CL=10pF 0.35 Ttr CL=10pF 0.35 Ttr CL=10pF 0.8 Ttr CL=10pF 0 Ttr CL=10pF 40% CL=10pF -5 60% Ttr ﹢5 ns 40 75 us Confidential 13 Lontium Semiconductor LT8511EX_Datasheet_R1.6 2.6.3 S/PDIF Output port Timing TSPCYC,TSPDUTY TSPCYC,TSPDUTY SPDIF MCLK TMCLKCYC TMCLKCYC 50% 90% 50% 10% 50% Figure6: S/PDIF Output port Timings Symbol TSPCYC TSPDIF TSPDUTY TMCLKCYC FMCLK TMCLKDUTY TAUDDLY Parameter Conditions Min Typ Max SPDIF Cycle Time CL=10pF 1.0 SPDIF Frequency 4 24 SPDIF Duty Cycle CL=10pF 90% 110% MCLK Cycle Time CL=10pF 10 MCLK Frequency CL=10pF 98 MCLK Duty Cycle CL=10pF 40% 60% Audio Pipeline Delay 40 75 Units UI MHz UI ns MHz TMCLKCYC us 2.6.4 Audio Crystal Timings Symbol Parameter Conditions Min Typ Max Units FXTAL External Crystal Freq 25 27 28.322 MHz Confidential 14 Lontium Semiconductor LT8511EX_Datasheet_R1.6 2.6.5 Miscellaneous Timings Symbol Parameter Conditions Min Typ Max Units T12CDVD SDA Data Valid delay from SCL falling edge CL=400pF 300 ns TRESET RESET# Signal Low Time for valid reset 45 us THDCPINIT HDCP Initialization from stable input 35 ms 2.6.6 RESET# Minimum Timings VCCmax VCCmin VCC RESET# TRESET RESET# TRESET Figure7: RESET# Minimum Timings Confidential 15 Lontium Semiconductor LT8511EX_Datasheet_R1.6 2.6.7 Power Supply Sequencing VCCA33 VCCDA33 VCC33 maximum 3.3v excursion DIFF33max Minimum 3.3v excursion DIFF3318max maximum 1.8v VDD excursion VCCA18 VCCTP18 VCCAP18 DIFF18max Minimum 1.8v excursion Figure8: Power Supply Sequencing Symbol Parameter Min Typ DIFF33 Difference between two 3.3V power pins DIFF18 Difference between two 1.8V power pins Difference between any DIFF3318 3.3V power pins and 1.8V -1.0 power pins Max Units 1.0 V 1.0 V 2.0 V Confidential 16 Lontium Semiconductor 3. Package LT8511EX_Datasheet_R1.6 3.1 LT8511EX-QFN64L(0909x0.85) The ePad must not be electrically connected to any other voltage level except ground (GND). The dimension of ePad in PCB should be 5.6x5.6mm. And a clearance of at least 0.25mm should be designed on the PCB between the edge of the ePad and the inner edges of the lead pads to avoid any electrical shorts. Confidential 17 Lontium Semiconductor LT8511EX_Datasheet_R1.6 Copyright © 2014 Lontium Semiconductor Corporation, All rights reserved. Lontium Semiconductor Proprietary & Confidential This document and the information it contains belong to Lontium Semiconductor. Any review, use, dissemination, distribution or copying of this document or its information outside the scope of a signed agreement with Lontium is strictly prohibited. LONTIUM DISCLAIMS ALL WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING THOSE OF NONINFRINGEMENT, MERCHANTABILITY, TITLE AND FITNESS FOR A PARTICULAR PURPOSE. CUSTOMERS EXPRESSLY ASSUME THEIR OWN RISH IN RELYING ON THIS DOCUMENT. LONTIUM PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN LIFE SUPPORT APPLIANCES, DEVICES OR SYSTEMS WHERE A MALFUNCTION OF A LONTIUM DEVICE COULD RESULT IN A PERSONAL INJURY OR LOSS OF LIFE. Lontium assumes no responsibility for any errors in this document, and makes no commitment to update the information contained herein. Lontium reserves the right to change or discontinue this document and the products it describes at any time, without notice. Other than as set forth in a separate, signed, written agreement, Lontium grants the user of this document no right, title or interest in the document, the information it contains or the intellectual property in embodies. Trademarks Lontium™ 龙迅™ and ClearedEdge™ is a registered trademark of Lontium Semiconductor. All Other brand names, product names, trademarks, and registered trademarks contained herein are the property of their respective owners. Visit our corporate web page at: www.lontiumsemi.com Confidential 18

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