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AGC介紹與理論...............

Analog Circuits and Signal Processing Series Editors Mohammed Ismail Mohamad Sawan For further volumes: http://www.springer.com/series/7381 Juan Pablo Alegre Pérez€•Â€Santiago Celma Pueyo Belén Calvo López Automatic Gain Control Techniques and Architectures for RF Receivers 1  3 Juan Pablo Alegre Pérez LSI Corporation Madrid Spain Juan.Alegre@lsi.com Santiago Celma Pueyo University of Zaragoza Zaragoza Spain scelma@unizar.es Belén Calvo López University of Zaragoza Zaragoza Spain becalvo@unizar.es ISBN 978-1-4614-0166-7â•…â•…â•…â•… e-ISBN 978-1-4614-0167-4 DOI 10.1007/978-1-4614-0167-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011933911 © Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Preface Receivers have been a basic block in telecommunication systems since the invention of the radio in the late 19th century, acquiring an essential role in what has been called the third Communication Revolution where information is transferred via controlled waves and electronic signals. Their main function is to recover the information from the transmitted wave and convert it to electronic signals that can be understood by the succeeding electronic processing signal systems. Since the Internet revolution, new receivers appeared to connect computers one to another or to the World Wide Web, such as wireless systems, have been gaining more and more popularity over the last few years. Thus, great investments in time, effort and money from both academia and industry have been made in the development of these receivers in order to achieve fully integrated solutions in form of ASICs meeting the demand for ever increasing high performance with low cost, low voltage supply, low power consumption and reduced surface area. The design of one of these receivers include different blocks such as filters, low noise amplifiers, gain controlled amplifiers, mixers and analog to digital converters. This book is precisely focused on the analysis and design of automatic gain control, AGC, circuits with wireless receivers as the main target application. In this context, the general function of the AGC circuitry is to automatically adjust the output signal of a variable gain amplifier to an optimal rated level, for different input signal strengths. This function is essential to guarantee that the system dynamic range is neither saturated with large signals nor makes the system fall below a tolerable noise level. Specifically, some wireless applications, such as WLAN or Bluetooth, must be able to handle packets-based data transmission and orthogonal frequency division multiplexing which introduce stringent settling-time constraints. Thus, fast AGCs are primordial in those systems. It is under these conditions that feedforward AGCs present their greatest advantages as an alternative to conventional feedback AGCs. Thus, all through this book we offer a detailed study about feedforward AGCs design—both at basic AGC cells and system level—, their main characteristics and performances. v vi Preface The starting point is a complete review and theoretical analysis of both feedforward and feedback configurations and their behavioural modelling, issues addressed in Chap.€2. Next, basic components in gain control function, i.e., variable/programmable gain amplifiers, peak detectors and control voltage generation circuits are examined. These basic blocks must be carefully chosen as they will limit the full AGC performance, so their specifications have to guarantee those required by the corresponding application. Thus, the main challenges and solutions encountered during the design of such high performance cells are summarized in Chap.€3 and different high performance integrated proposals that will be next employed in specific AGCs are described and characterized considering low voltage low power constraints. To achieve low power consumption and ease any future scale to shorter transistor channel length technologies, low voltage power supplies have been employed: this requires greater effort in the design, but guarantees the validity of the achieved results in current submicron process technologies. To close, the work is focused on the complete characterization of few different gain control loops required to implement a complete AGC system making use of some previously studied cells. Three complete AGC proposals are fully designed and evaluated in Chap.€4: a general purpose digital feedforward CMOS AGC operating at 100€MHz, a fully analogue feedforward AGC for an 802.11a WLAN receiver in SiGe BiCMOS technology and a combined feedforward/feedback CMOS AGC for operating frequencies up to 250€MHz. These novel AGC contributions, more than competitive with those already presented in the literature, prove that feedforward AGCs are a fine alternative in wireless receiver applications, evidencing that this class of circuits will take an important role in upcoming applications where the stringent time constraints preclude the use of conventional closed-loop AGCs. Contents 1â•…Introduction ����������������������������������尓������������������������������������尓������������������������� ╇╅ 1 1.1â•…AGC Design Strategies ����������������������������������尓������������������������������������尓 ╇╅ 3 1.2â•…AGC Architectures for RF Receivers ����������������������������������尓��������������� ╇╅ 6 1.3â•…Outline of the Work ����������������������������������尓������������������������������������尓������ ╇╅ 8 References ����������������������������������尓������������������������������������尓����������������������������� â•… 10 2â•…AGC Fundamentals ����������������������������������尓������������������������������������尓������������ â•… 13 2.1â•…AGC Loop Fundamentals ����������������������������������尓��������������������������������� â•… 14 2.1.1â•…AGC with Feedback Loop ����������������������������������尓�������������������� â•… 14 2.1.2â•…AGC with Feedforward Loop ����������������������������������尓��������������� â•… 20 2.2â•…Matlab Simulations ����������������������������������尓������������������������������������尓������ â•… 21 2.2.1â•…AGC with Feedback Loop ����������������������������������尓�������������������� â•… 21 2.2.2â•…AGC with Feedforward Loop ����������������������������������尓��������������� â•… 25 2.3â•…Conclusions ����������������������������������尓������������������������������������尓������������������ â•… 26 References ����������������������������������尓������������������������������������尓����������������������������� â•… 27 3â•…Basic AGC Cells ����������������������������������尓������������������������������������尓������������������ â•… 29 3.1â•…Variable Gain Amplifiers ����������������������������������尓���������������������������������� â•… 29 3.1.1â•…Degeneration Based VGA Structures. Proposed VGA1 ��������� â•… 32 3.1.2â•…Multiplier-Based VGA Structures. Proposed VGA2 and VGA3 ����������������������������������尓������������������������������������尓��������� â•… 35 3.1.3â•…Complete VGA Architecture Design Considerations ������������� â•… 51 3.1.4â•…Conclusions ����������������������������������尓������������������������������������尓������ â•… 52 3.2â•…Peak Detectors ����������������������������������尓������������������������������������尓�������������� â•… 54 3.2.1â•…Basic Peak Detector Topologies ����������������������������������尓����������� â•… 55 3.2.2â•…Open-Loop Envelope Detectors. Proposed PD1 and PD2 ����������������������������������尓������������������������������������尓������������ â•… 57 3.2.3â•…Closed-Loop Envelope Detectors. Proposed PD3 and PD4 ����������������������������������尓������������������������������������尓������������ â•… 66 3.2.4â•…S/H Based Envelope Detector. Proposed PD5 ����������������������� â•… 70 3.2.5â•…Conclusions ����������������������������������尓������������������������������������尓������ â•… 76 vii viii Contents 3.3â•…Control Voltage Generation Circuit ����������������������������������尓���������������� ╇╅ 78 3.3.1â•…Digital Control ����������������������������������尓������������������������������������尓 ╇╅ 78 3.3.2â•…Analog Control ����������������������������������尓����������������������������������� ╇╅ 79 3.3.3â•…Conclusions ����������������������������������尓������������������������������������尓���� ╇╅ 82 References ����������������������������������尓������������������������������������尓��������������������������� ╇╅ 82 4â•…AGC Systems ����������������������������������尓������������������������������������尓��������������������� ╇╅ 87 4.1â•…CMOS Feedforward Digital AGC Circuit ����������������������������������尓������ ╇╅ 87 4.1.1â•…System Architecture ����������������������������������尓���������������������������� ╇╅ 88 4.1.2â•…Performances ����������������������������������尓������������������������������������尓�� ╇╅ 91 4.2â•…SiGe BiCMOS Analog AGC Circuit ����������������������������������尓�������������� ╇╅ 93 4.2.1â•…System Architecture ����������������������������������尓���������������������������� ╇╅ 94 4.2.2â•…Performances ����������������������������������尓������������������������������������尓�� ╇╅ 98 4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit ������������������������ â•… 101 4.3.1â•…System Architecture ����������������������������������尓���������������������������� â•… 102 4.3.2â•…Performances ����������������������������������尓������������������������������������尓�� â•… 109 4.4â•…Conclusions ����������������������������������尓������������������������������������尓���������������� â•… 112 References ����������������������������������尓������������������������������������尓��������������������������� â•… 114 5â•…Conclusions ����������������������������������尓������������������������������������尓������������������������ â•… 117 5.1â•…General Conclusions ����������������������������������尓������������������������������������尓�� â•… 117 5.2â•…Further Research Directions ����������������������������������尓��������������������������� â•… 119 Appendix A: Layout and Experimental Techniques ����������������������������������尓 â•… 121 Appendix B: Acronym List����������������������������������尓������������������������������������尓����� â•… 127 Appendix C: Parameter Glossary����������������������������������尓������������������������������ â•… 129 Appendix D: Process Parameters����������������������������������尓������������������������������� â•… 131 Index ����������������������������������尓������������������������������������尓������������������������������������尓����� â•… 133 List of Tables Table 2.1↜渀̀ Summary of main AGC loop control characteristics������������������� â•… 14 Table 3.1↜渀̀ Summary of VGA1 performances����������������������������������尓�������������� â•… 35 Table 3.2↜渀̀ VGA2 transistors sizes����������������������������������尓������������������������������� â•… 41 Table 3.3↜渀̀ Simulation and measurement data of the VGA2�������������������������� â•… 44 Table 3.4↜渀̀ VGA3 transistor sizes����������������������������������尓��������������������������������� â•… 48 Table 3.5↜渀̀ Comparison of several VGAs����������������������������������尓��������������������� â•… 53 Table 3.6↜渀̀ PD1 devices sizes����������������������������������尓������������������������������������尓��� â•… 59 Table 3.7↜渀̀ Comparison of principal characteristics for simulation and measurements of the open-loop peak detector���������������������� â•… 61 Table 3.8↜渀̀ Comparison summary between PD1 and PD2 for 10 MHz��������� â•… 65 Table 3.9↜渀̀ PD5 transistor sizes����������������������������������尓������������������������������������尓 â•… 75 Table 3.10↜渀 Comparison of proposed envelope detectors������������������������������� â•… 77 Table 4.1↜渀̀ Comparison of literature and proposed AGCs����������������������������� ╇ 113 Table D.1↜渀̀ T echnology: AMS 0.35€μm CMOS P-Substrate, N-Well, 4-Metal, 2-Poly����������������������������������尓���������������������������� ╇ 131 Table D.2↜渀 Technology: IHP 0.25€μm SiGe:C BiCMOS with High-Voltage Devices, 5-metal����������������������������������尓������������������ ╇ 132 ix List of Figures Fig. 1.1↜渀̀ Estimated wireless subscribers from 1985 to 2009��������������������������� â•… 2 Fig. 1.2↜渀̀ WLAN and Bluetooth receiver block diagram��������������������������������� â•… 2 Fig. 1.3↜渀̀ Feedback (âl†œeft) and feedforward (âr†œ igth) AGC architectures������������� â•… 4 Fig. 1.4↜渀̀ IF strip example����������������������������������尓������������������������������������尓����������� â•… 6 Fig. 1.5↜渀̀ OFDM preamble symbols transient response����������������������������������尓� â•… 7 Fig. 1.6↜渀̀ Feedback closed-loop AGC block diagram����������������������������������尓����� â•… 7 Fig. 1.7↜渀̀ Feedback open-loop AGC block diagram����������������������������������尓������� â•… 8 Fig. 2.1↜渀̕܀ÈS• implified block diagrams of feedback (a) and feedforward (b) AGCs����������������������������������尓������������������������ ╇ 14 Fig. 2.2↜渀̀ Common block diagram of feedback AGC����������������������������������尓����� ╇ 15 Fig. 2.3↜渀̀ Model of generalized feedback AGC����������������������������������尓�������������� ╇ 16 Fig. 2.4↜渀̀ Equivalent AGC loop diagram����������������������������������尓������������������������ ╇ 19 Fig. 2.5↜渀̀ Common block diagram of feedforward AGC����������������������������������尓 ╇ 21 Fig. 2.6↜渀̀ AGC1: Simulink model����������������������������������尓����������������������������������� ╇ 22 Fig. 2.7↜渀̀ Convergence response of AGC1 for different stepwise changes������ ╇ 22 Fig. 2.8↜渀̀ AGC2: Simulink model����������������������������������尓����������������������������������� ╇ 23 Fig. 2.9↜渀̀ Convergence response of AGC2 for different stepwise changes������ ╇ 23 Fig. 2.10↜渀 AGC3: Simulink model����������������������������������尓����������������������������������� ╇ 24 Fig. 2.11↜渀ÌS• ettling-time versus reference voltage for different input signal steps����������������������������������尓������������������������������������尓��������� ╇ 24 Fig. 2.12↜渀 AGC4: Simulink model����������������������������������尓����������������������������������� ╇ 25 Fig. 2.13↜渀 Convergence response of AGC4 for different stepwise changes������ ╇ 26 Fig. 2.14↜渀 AGC5: Simulink model����������������������������������尓����������������������������������� ╇ 26 Fig. 2.15↜渀 Convergence response of AGC5 for a stepwise change�������������������� ╇ 27 Fig. 3.1↜渀̀Èa• Programmable resistor and fixed gain amplifier based PGA and b high gain amplifier with resistor network feedback based PGA����������������������������������尓������������������������� ╇ 31 Fig. 3.2↜渀̀ Differential pair transconductor with degenerative resistor�������������� ╇ 32 Fig. 3.3↜渀̀ Schematic view of the PGA proposed in [10]����������������������������������尓� ╇ 34 Fig. 3.4↜渀̀ PGA frequency response����������������������������������尓��������������������������������� ╇ 36 Fig. 3.5↜渀̕܀ÈT• HD levels at 10€MHz for all gain settings versus output voltage Vout����������������������������������尓�������������������������������� ╇ 36 xi xii List of Figures Fig. 3.6↜渀̀ a Conceptual multiplier scheme. b Gilbert cell�������������������������������� ╇ 38 Fig. 3.7↜渀̀ Multiplier cell proposed in [14]����������������������������������尓���������������������� ╇ 39 Fig. 3.8↜渀̀ Complete scheme of the proposed VGA����������������������������������尓��������� ╇ 40 Fig. 3.9↜渀̀ VGA2 chip photograph (a) and measurement setup (b)������������������� ╇ 42 Fig. 3.10↜渀ÌV• GA gain frequency response: simulated (dashed) and measured (âs†œ olid)����������������������������������尓������������������������������������尓��� ╇ 43 Fig. 3.11↜渀ÌI•M3 levels versus peak-to-peak differential input voltage (Vp-p) at 50€MHz for different gain settings����������������������������������尓���� ╇ 43 Fig. 3.12↜渀 VGA IM3 versus frequencies at 0.4 and 0.8 Vp-p output������������������� ╇ 43 Fig. 3.13↜渀 Measured HD3 for different gain settings at 100€kHz���������������������� ╇ 44 Fig. 3.14↜渀 Classical CMOS pseudo-differential transconductor������������������������ ╇ 45 Fig. 3.15↜渀ÌC• MOS pseudo-differential transconductor: a Core of the proposed topology and b Output DC current for different Vdâ• ›= â•V› Gâ•−› â•V› CM values����������������������������������尓������������������� ╇ 46 Fig. 3.16↜渀ÌP• roposed CMOS pseudo-differential VGA with 3-bit rough gain adjustment, CMFF (a) and selfbias common-mode feedback loop (b)����������������������������������尓������������������������������������尓�������� ╇ 47 Fig. 3.17↜渀 VGA cell photograph����������������������������������尓������������������������������������尓�� ╇ 49 Fig. 3.18↜渀ÌS• imulated (âd†œ ashed) and measured (âs†œ olid) VGA frequency response for different gain settings����������������������������������尓����������������� ╇ 50 Fig. 3.19↜渀ÌP• GA plus buffer simulated (âb†œ lack) and experimental (âg†œ rey) IM3 for outputs signals of 0.4 and 0.8€Vp-p at 100€MHz������������������� ╇ 50 Fig. 3.20↜渀 Typical multiple cell VGA AGC structure����������������������������������尓������ ╇ 51 Fig. 3.21↜渀 Rough/fine gain based VGA structure����������������������������������尓������������ ╇ 52 Fig. 3.22↜渀ÌI•deal charge/discharge behaviour in a peak detector with load capacitor, C, and resistor, R����������������������������������������������� ╇ 54 Fig. 3.23↜渀 Diode-RC peak detector topology����������������������������������尓������������������� ╇ 55 Fig. 3.24↜渀 Op-amp plus diode based peak detector topology���������������������������� ╇ 56 Fig. 3.25↜渀 Op-amp plus source follower based peak detector topology������������ ╇ 56 Fig. 3.26↜渀 Open-loop peak detector topology����������������������������������尓������������������ ╇ 57 Fig. 3.27↜渀 Schematic diagram of the full-wave precision rectifier block���������� ╇ 58 Fig. 3.28↜渀 Schematic diagram of the mirrored cascode OTA���������������������������� ╇ 58 Fig. 3.29↜渀 Schematic diagram of the peak detector block��������������������������������� ╇ 59 Fig. 3.30↜渀 Chip photograph of the peak detector PD1����������������������������������尓����� ╇ 60 Fig. 3.31↜渀 Measured and ideal linearity performance����������������������������������尓������ ╇ 60 Fig. 3.32↜渀ÌM• easured tracking (âs†œ olid grey line) of the open-loop envelope detectors for a 500€kHz square signal (âs†œ olid black line) and simulation results (âd†œ ashed grey line) for a 71€MHz sinusoidal signal with a stepwise change (âd†œ ashed black line)����������������������������������尓������������������������������������尓������ ╇ 60 Fig. 3.33↜渀 Fast-settling open-loop envelope detector block diagram���������������� ╇ 62 Fig. 3.34↜渀 Schematic of the peak hold block����������������������������������尓������������������� ╇ 62 Fig. 3.35↜渀ÌE• nvelope detector operation. Peak holder both output signals (âg†œ rey and black) and input signal (--) (âu†œ p). Below VC1 control signal����������������������������������尓������������������������������������尓��������������� ╇ 63 List of Figures xiii Fig. 3.36↜渀 Schematic diagram of the control path����������������������������������尓������������ ╇ 63 Fig. 3.37↜渀ÌR• ipple of the conventional (--) and the proposed (―) envelope detectors for an input voltage of 300€mV at 10€MHz and a total capacitance of 3.2€pF����������������������������������尓��������������������� ╇ 64 Fig. 3.38↜渀ÌT• racking of (--) ideal, (-.) conventional and (―) proposed envelope detectors for a step signal at 10€MHz and ripple of 1%����� ╇ 65 Fig. 3.39↜渀ÌD• C (o) and 10€MHz (-) transfer characteristic for the conventional and the proposed envelope detector����������������� ╇ 65 Fig. 3.40↜渀 OTA plus current mirror closed-loop topology��������������������������������� ╇ 66 Fig. 3.41↜渀 Schematic of a high-Gm OTA/current mirror based peak detector���� ╇ 67 Fig. 3.42↜渀 Peak detector input-output performance����������������������������������尓��������� ╇ 68 Fig. 3.43↜渀ÌP• eak detector convergence performance for an input sinusoidal 100€MHz stepwise signal����������������������������������尓�������������������������������� ╇ 68 Fig. 3.44↜渀 Schematic of the fast-settling OTA/current mirror PD��������������������� ╇ 69 Fig. 3.45↜渀 Chip photograph����������������������������������尓������������������������������������尓���������� ╇ 70 Fig. 3.46↜渀 Measured and ideal input-output performance��������������������������������� ╇ 70 Fig. 3.47↜渀ÌS• imulated (âu†œ p) and measured (âd†œ own) convergence performance with a 20€MHz input sinusoidal signal modulated by a 400€kHz square signal����������������������������������尓����������������������������� ╇ 71 Fig. 3.48↜渀 S/H based detector conceptual scheme����������������������������������尓����������� ╇ 72 Fig. 3.49↜渀 Schematic of the control block����������������������������������尓������������������������ ╇ 72 Fig. 3.50↜渀 Schematic diagram of the peak holder����������������������������������尓������������ ╇ 73 Fig. 3.51↜渀 Schematic diagram of the telescopic OTA����������������������������������尓������ ╇ 73 Fig. 3.52↜渀ÌT• racking of ideal (–), conventional (-.) and proposed (–) envelope detectors for a step signal at 10€MHz and ripple of 1%����� ╇ 75 Fig. 3.53↜渀 Envelope detection of a frequency modulated input signal�������������� ╇ 76 Fig. 3.54↜渀Ì1• 0€MHz input output performance for different envelope detectors����������������������������������尓������������������������������������尓������� ╇ 76 Fig. 3.55↜渀 Comparator bank cell employed in [57]����������������������������������尓���������� ╇ 79 Fig. 3.56↜渀 Piece-wise linear approximation based logarithmic amplifier���������� ╇ 81 Fig. 3.57↜渀 Circuit to implement inverse of exponential function����������������������� ╇ 81 Fig. 3.58↜渀 Simple divider����������������������������������尓������������������������������������尓������������� ╇ 82 Fig. 4.1↜渀̀ IF 71€MHz strip����������������������������������尓������������������������������������尓����������� ╇ 88 Fig. 4.2↜渀̀ Programmable gain amplifier cell����������������������������������尓������������������� ╇ 89 Fig. 4.3↜渀̀ Comparator bank cell����������������������������������尓������������������������������������尓�� ╇ 90 Fig. 4.4↜渀̀ AGC1 chip photograph����������������������������������尓����������������������������������� ╇ 91 Fig. 4.5↜渀̀ÈM• easured PGA frequency response: solid line, Kâ• ›= â•1› ; dashed line, Kâ• ›= â•1› .5����������������������������������尓������������������������������������尓����������������� ╇ 92 Fig. 4.6↜渀̕܀ÈS• imulated THD levels at 71€MHz for the main gain settings versus output voltage Vout����������������������������������尓�������������������������������� ╇ 92 Fig. 4.7↜渀̀ Measured input-output linearity of the peak detector����������������������� ╇ 93 Fig. 4.8↜渀̕܀ÈM• easured peak detector convergence response for a 21 dB abrupt stepwise change����������������������������������尓������������������������������ ╇ 93 Fig. 4.9↜渀̀ Simulated worst case AGC output����������������������������������尓������������������ ╇ 94 xiv List of Figures Fig. 4.10↜渀 Complete AGC architecture����������������������������������尓�������������������������� â•… 95 Fig. 4.11↜渀 Schematic of the peak detector����������������������������������尓���������������������� â•… 98 Fig. 4.12↜渀 Die photo of the full AGC����������������������������������尓����������������������������� â•… 99 Fig. 4.13↜渀 Measurement test-bench PCB����������������������������������尓����������������������� â•… 99 Fig. 4.14↜渀ÌF• requency response of the full VGA for several VC with fixed amplifiers VGA1 and VGA2 switched off (âb†œ lack) and for VCâ• ›= â•1› 20€mV with VGA1 “on” (âg†œ rey). Results are the mean value of 100 measurements����������������������������������尓����� ╇ 100 Fig. 4.15↜渀 Input-output linearity for the peak detector����������������������������������尓�� ╇ 100 Fig. 4.16↜渀 Control voltage (âV†œ C,diffâ•)› versus peak detector output Vpd���������������� ╇ 100 Fig. 4.17↜渀ÌM• easured peak detector settling-time with a 20€MHz sinusoidal wave modulated with a 400€kHz square signal�������������� ╇ 101 Fig. 4.18↜渀ÌS• imulated AGC output signal, Vout, with an OFDM input signal for highest gain adjustment (18€dB) from lowest input level����������������������������������尓������������������������������������尓������������������ ╇ 101 Fig. 4.19↜渀 AGC3 system schematic (âd†œ own) and VGA3 (âu†œ p)��������������������������� ╇ 104 Fig. 4.20↜渀 Block schematic of feedforward loop����������������������������������尓����������� ╇ 105 Fig. 4.21↜渀 Inverter based comparator schematic����������������������������������尓������������ ╇ 106 Fig. 4.22↜渀 Peak detector schematic����������������������������������尓�������������������������������� ╇ 107 Fig. 4.23↜渀 Peak detector comparator����������������������������������尓������������������������������ ╇ 107 Fig. 4.24↜渀ÌE• quation€(4.7) for arbitrary constants and fitting curve obtained by Matlab Curve Fitting Toolbox����������������������������������尓��� ╇ 108 Fig. 4.25↜渀 Chip photograph����������������������������������尓������������������������������������尓�������� ╇ 109 Fig. 4.26↜渀 Measurement test circuitry����������������������������������尓���������������������������� ╇ 109 Fig. 4.27↜渀 Gain vs. input amplitude for an input signal at 100€MHz��������������� ╇ 110 Fig. 4.28↜渀ÌA• GC convergence with a square modulation at 300€KHz and a carrier at 250€MHz for simulation (âu†œ p) and 20€MHz for measurements (âd†œ own) are offered����������������������������������尓����������� ╇ 111 Fig. A.1↜渀 Measurement scheme����������������������������������尓������������������������������������尓 ╇ 123 Fig. A.2â•… CMOS test-buffer schematic����������������������������������尓������������������������� ╇ 124 Fig. A.3â•… Test buffer chip photograph����������������������������������尓��������������������������� ╇ 124 Fig. A.4↜渀 PCBs for each chip����������������������������������尓������������������������������������尓���� ╇ 125 Chapter 1 Introduction Receivers have been a basic block in telecommunication systems since the invention of the radio in the late nineteenth century, acquiring an essential role in what has been called the third Communication Revolution where information is transferred via controlled waves and electronic signals. Their main function is to recover the information from the transmitted wave and convert it to electronic signals that can be understood by the succeeding electronic processing signal systems. Following the Internet revolution which started in 1980s, new systems appeared designed either to connect computers one to another or to the World Wide Web. Among those new communication systems, wireless systems, such as wireless local area network (WLAN) and Bluetooth, have been gaining more and more popularity over the last few years. Figure€1.1 shows estimated wireless subscribers between 2006 and 2009. Thus, great investments in time, effort and money from both academia and industry have been made in the development of these receivers in order to achieve fully integrated systems meeting the demand for ever increasing high performance with low cost, low power consumption and reduced surface area. The design of one of these receivers is usually carried out by several specialists, as it is made up of different blocks such as filters, low noise amplifiers (LNA), gain controlled amplifiers, mixers and analog to digital converters (ADC), see Fig.€1.2. This book is precisely focused on the analysis and design of automatic gain control (AGC) circuits. Although the designed AGCs could serve other applications, the main target applications are wireless receivers. Therefore, the proposed AGCs must be able to handle a packets-based data transmission, orthogonal frequency division multiplexing (OFDM) and stringent settling-time constraints [1]. For the last two decades the expansion of ASICs (Application Specific Integrated Circuits) among many electronic applications has been spectacular. Wireless receivers are not an exception to this tendency. The main advantages of integrating mixed digital/analog functions into the same chip are the full system area reduction, improved operating speed, parasitic and contacts failure reduction, higher versatility of the design and reduced cost, etc. In the design of digital circuits, which make up over 90% of the whole electronic system, CMOS technology is very superior to the other technologies such as bipolar due to its lower power consumption, high performance, higher integration density J. P. Alegre Pérez et al., Automatic Gain Control, Analog Circuits and Signal Processing, 1 DOI 10.1007/978-1-4614-0167-4_1, ©Â€Springer Science+Business Media, LLC 2011                                                   1XPEHURIVXEVFULEHUV 2        (VWLPDWHG:LUHOHVV6XEVFULEHUV â•1› 0€ kΩ are required if good linearity and gain ac- curacy are required. At the same time, load resistors must be increased to achieve enough gain range, but then the frequency response of the circuit is limited. Hence, a trade-off exists for this structure between consumption, frequency response, lin- earity, gain range and accuracy. A possible solution to this trade-off is the use of gm-boosting techniques. Although different solutions have been published in the literature [6, 8, 9], they can be classi- fied into only two groups depending whether they are based on positive or negative feedback techniques. The latter solution is the most commonly used. It boots gm by a factor which depends on the feedback amplifier gain, but has its drawbacks due to the intrinsic complexity of designing a stable loop, increased power consumption and the dynamic range restriction related to the use of a high gain amplifier. Alternatively, the positive feedback based approach also offers an increase in gm through parameter compensation techniques. As this effect can be achieved with lower gain they do not have the above mentioned drawbacks for the negative coun- terparts. In contrast, stability conditions must be considered carefully. 3.1.1.1â•…Proposed VGA1: Degenerated OTA with gm-Boosting The first studied VGA scheme is shown in Fig.€3.3a. It is based on a very simple negative feedback gm-boosted differential pair with output resistive loads [10]. The gain is varied by a switchable array of source degenerating hybrid polysilicon-MOS (Fig.€3.3b). Focusing on the transconductor core, transistors M1-M2 form a two-pole negative-feedback loop that boosts the equivalent transconductance of the input pair transistors M1 up to approximately [11]:  gm ≈ gm1ro1gm2, (3.4) where gmi and roi are respectively the transconductance and the output conductance of transistor Mi. Now, for a source-degenerated pair exploiting this approach, the differential transconductance can be expressed as α  Gm = , R (3.5) where R denotes one-half of the degeneration resistance and α denotes the M1 gateto-source DC voltage gain, which is somewhat less than unity due to the body 34 3â•… Basic AGC Cells 5/ 9RXW 0 0 ,% 9LQ 0 9FDV 5 0 ,% ,% 0 9LQ± 9FDV 0 5/ 9RXW± 0 0 D 5 N: DL D :/  D  :/ D :/   :/ 0VL 5L 0VL 5L 5L E  :/  :/ Fig. 3.3↜渀 Schematic view of the PGA proposed in [10] effect of the input pair transistors—NMOS in a P-substrate single well CMOS technology:  α≈ gm1 . gm1 + gmb1 (3.6) Next, the linearized differential signal current, copied out by loading each M2 gate terminal with a matched NMOS device, is converted to voltage through load resis- tors RL. Thereby, the differential gain of the full VGA is given by  Gain = Gm · RL = α RL R . (3.7) For high-frequency applications, noise specifications limit the value of the load and degeneration resistors to the kΩ range. Further, high resistivity polysilicon (HRP) loads RL will be implemented to avoid degrading the linearity performance. 3.1â•… Variable Gain Amplifiers Table 3.1↜渀 Summary of VGA1 performances Design parameter Technology Supply voltage Frequency response Gain range THD@ 10€MHz, 0.2€Vp-p out In-band noise @ 0€dB Power consumption 35 Value 0.35€µm CMOS 1.8€V 100€MHz 0–18€dB in 6€dB steps <â•−› â•7› 0€dB 51€nV/√Hz 0.42€mW A variable degeneration resistor can be created using a resistor bank or ladder with CMOS switches to obtain selectable taps. In our case, in order to preserve good linearity, moderate area consumption and, at the same time, facilitate digital gain control, we settled for an approach which merges, in equal parts, HRP resistors and MOS transistors biased in the triode region. These act simultaneously as resistors and switches. The minimum gain setting is imposed by a fixed high resistivity polysilicon (HRP) resistor R0. The gain is then digitally increased by adding in parallel a new linear resistor in series with two MSi NMOS switches biased in the triode region, whose on-resistance is one half of the total conversion impedance. Fine gain tuning can be performed if necessary by applying slight gate voltage variations for the switching transistors in order to improve accuracy. In particular, for this design the programmable degeneration impedance consists of a 3-bit array of hybrid NMOS-HRP resistors in parallel, which are weighted to obtain a logarithmic gain distribution ranging from 0 to 18€dB in 6€dB steps through a thermometer code control. Higher accuracy would be easily obtained just by increasing the bit number of the comparator bank. An additional current source, IQ, is introduced to guarantee a suitable common-mode output voltage, equal to that of the input. This PGA cell has been designed in the AMS 0.35€μm CMOS technology. Transistor sizes (W/L in μm) are M1â• ›= â•1› 0/0.5 and M2â• ›= â•4› /0.5; bias current IBâ• ›= â•4› 0€μA and RLâ• ›= â•1› 0€kΩ. The circuit consumes less than 0.5€mW from a single voltage of 1.8€V with a common-mode voltage of 1.3€V. Its main performances are summarized in Table€3.1. The bandwidth is kept constant around 100€MHz assuming capacitive loads of 150€fF at the two outputs, see Fig.€3.4. The total harmonic distortion (THD) behaviour for a signal frequency of 10€MHz is depicted in Fig.€3.5 considering constant differential output levels. Figures are below −â•7› 0€dB over all the gain setting range with a differential output signal level of 0.2€Vp-p, value that increases to −â•6› 0€dB for 0.4€Vp-p. This circuit has been selected as it offers a good trade off between power consumption, maximum operating frequency and linearity. 3.1.2  Multiplier-Based VGA Structures. Proposed   VGA2 and VGA3 Among the VGAs whose gain is changed by varying the bias current are multiplierbased cells. This is a very versatile architecture which is employed not only as a 36 Fig. 3.4↜渀 PGA frequency response 24 18 C=‘111’ 12 C=‘011’ Gain 6 (dB) 0 C=‘001’ C=‘000’ ¯6 ¯12 ¯18106 Fig. 3.5↜渀 THD levels at 10€MHz for all gain settings ¯50 versus output voltage Vout ¯60 THD, 10 MHz (dB) ¯70 3â•… Basic AGC Cells 107 108 109 Frequency (Hz) 0 dB 18 dB 12 dB 6 dB ¯80 0.0 0.2 0.4 0.6 0.8 differential output (Vpp) computational building block but also as a programming element in systems such as filters, neural networks, and communication systems where they are used to implement mixers and modulators [4]. In this book we are only interested in its possible application as a VGA. Since the function of a multiplier is simply to multiply two signals, we will in our case multiply the input signal by the control signal generated by the AGC loop. Thus, a linear VGA is obtained by employing any multiplier cell, which, combined with an exponential converter, gives us the possibility to use it as a linear-in-dB VGA. This demonstrates that the multiplier cell is also a valid option a priori. 3.1â•… Variable Gain Amplifiers 37 To understand the basic idea of the multiplier implementation, consider two signals, v1(ât†œ) and v2(ât†œ), applied to a nonlinear device. The output of this device can be characterized by a high-order polynomial function, which is composed of terms like v12(ât†œ), v22(ât†œ), v13(ât†œ), v23(ât†œ), v12(ât†œ)*v2(ât†œ) and many others besides the desired v1(ât†œ)*v2(ât†œ). It is then required to cancel the undesired components. This is accomplished by a cancellation circuit configuration. Typically, a multiplier-based VGA is realized using variable transconductance components, which are programmed by the bias current. Ideally, the output current of a transconductance amplifier is simply given by  where io = Gm1v1,  Gm1 = Gm1(Ibias1). For a CMOS transconductor, Gm1 becomes  Gm1 = 2K1Ibias1, (3.8) (3.9a) (3.9b) where K1 is the transconductance factor. Then, a small signal i2 from a second transconductor is added to the bias current Ibias1. If we introduce the new expression in (3.9b), and since i2â•<› <â•I› bias1, applying the Taylor series approximation, the transconductance can be rewritten as  Gm1 ≈ 2K√1(Ibias1 + i2) . 2K1Ibias1 (3.9c) At the same time, as well as in (3.8), i2(ât†œ)â• ›= â•G› m2v2(ât†œ). Thus, the output current yields  io(t ) = Gm1v1 = 2K1 Ibias1 (Ibias1 + Gm2v2(t)) v1(t), (3.10a) io(t) = 2K1 Ibias1 Gm2v2 (t )v1(t ) + 2K1 Ibias1 Ibias 1v1(t )  = 2K1 K2 Ibi Ibi as as 2 1 v2 (t )v1(t ) + 2K1 Ibias1 Ibi a s 1 v1 (t ) or  io(t ) = k1v2(t )v1(t ) + k2v1(t), where k1 = 2K K Ibias2 1 2 Ibias1 and k2 = 2K1 Ibias1 Ibias1. (3.10b) (3.10c) 38 v1 G¯ m1 + v2 G¯ m2 + Ibias2 i2 Ibias1 i2 v1 G¯ m1 + a Iout+ Vx+ io Vy+ b Vx¯ IL GND Fig. 3.6↜渀 a Conceptual multiplier scheme. b Gilbert cell 3â•… Basic AGC Cells Iout¯ Vx+ Vy¯ Thus, io(ât†œ) represents the multiplication of two signals v1(ât†œ) and v2(ât†œ) plus an unwanted component k2v1(ât†œ). This component can be eliminated by using a third transconductor equal to the first one Gm1 so that the whole transconductor group forms a conceptual multiplier cell. Furthermore, better cancellation is achieved when the second transconductor becomes a fully differential transconductor, and v1(ât†œ) and v2(ât†œ) are fully differential inputs. Thus, the following result is obtained:  io(t) = 2k1v2(t)v1(t). (3.11) The complete conceptual multiplier can be illustrated as in Fig.€3.6a. It is the basic operation principle of a Gilbert cell [12, 13], shown in Fig.€3.6b. Although this cell is one of the most popular multipliers, the MOS version has several setbacks which limit its application as a variable gain amplifier. After the analysis given between (3.8) and (3.11), the most obvious problem is the approximation required to obtain a linear response as in (3.9c). Furthermore, once second order effects are introduced, the linearity offered by the Gilbert cell shows poor performance. On the other hand, the MOS transistor length reduction that has been given during recent years and the popularity obtained by low power portable devices make it necessary to use low voltage configurations. However, the classical Gilbert cell requires at least 4 transistors in cascade, making it an unsuitable structure for low voltage implementation. Moreover, the only way to improve the inherently poor linearity of this cell is by increasing the bias current and consequently, increasing the power consumption. As a result, a highly linear multiplier structure, adequate for low voltage is required in order to employ a multiplier as a variable gain amplifier in present-day applications. 3.1.2.1â•…Proposed VGA2: Multiplier-Based VGA The proposed VGA is an improved adaptation of the multiplier cell proposed by Liu and Hwang [14] shown in Fig.€3.7, which offers the best performance accord- 3.1â•… Variable Gain Amplifiers 39 ,RXW 9LQ $Ā 0 0 9& 9 , , 0 0 9LQ± 9LQ 9&Ā 9&Ā ,RXWĀ $ 0 0 , , 0 0 9LQ± 9& *1' Fig. 3.7↜渀 Multiplier cell proposed in [14] ing to the comparison criteria established by Han and Sánchez-Sinencio in [15], including parameters such as linearity, minimum power supply and noise perfor- mance. Focussing on the core of this circuit in Fig.€3.7, the control voltage and the input signal are introduced through transistors M1 and M2, respectively. Transistors M2 works in the saturation region while transistors M1 operate in the triode region. Consequently, drain currents of both transistors are given approximately by:  ID = 2K1 (VGS1 − VTH1)VDS1 − VD2S1/2 ID = K2(VGS2 − VTH2)2, (3.12) where Kiâ• ›= â•1› /2µCoxWi/Li is the transconductance parameter and VTHi is the threshold voltage for both types of transistors iâ• ›= â•1› , 2. Assuming VTH1â• ›= â•V› TH2â• ›= â•V› TH and using these equations to obtain the expression for I1, a routine circuit analysis yields:  I1 = K2(Vin − V1 − VT H )2, (3.13) where V1 = Vin + VC − 2VT H  and, (VC − VT H )2 + 2(VC − VT H )(Vin − VT H ) − (Vin − VT H )2 2 (3.14)  Vin± = VCM,in ± vin/2 VC± = VCM,C ± vC , (3.15) 40 3â•… Basic AGC Cells M4 B:1 M3 M8 ¯out CL Vin¯ VC+ RL A¯ M2 M2 I3 I4 M1 M1 CC /2 VDD CC /2 M7 Vin+ M7 Iref Vin+ VC¯ M5 VC+ M8 M3 1:B M4 A+ M2 M2 I1 I2 M1 M1 Vin¯ +out VC¯ RL CL GND Fig. 3.8↜渀 Complete scheme of the proposed VGA where vin is the differential input voltage and vC is the control voltage. If vin, vCâ•<› <â•V› TH, (3.13) can be approximated by I1 = K2 √ Vin − VC 2 − 2(Vin − VC )VTH 2 2  × 1− VC VTH + VinVC 2VT2H + VC2 − Vi2n 4VT2H + VT2H 2 1 − VC VTH + VinVC 2VT2H + VC2 − Vi2n 4VT2H 2 . (3.16) Following a straightforward analysis with the remaining currents, the differential output current is approximately given by:  I0 = (I1 + I2) − (I3 + I4) ≈ 4K2vCvin, (3.17) where K2 is the transconductance constant of transistor M2. As a result, by K2, we can control the bias current through transistors M1 and M2 (3.12) and the maximum gain (3.17), so that both increase in parallel. Next, we built a VGA based on this core [16] converting the output current into voltage by load resistors RL (see Fig.€3.8 in solid lines). Since all the bias current of the core (0.5€mA) is transmitted to the outputs, the maximum RL maintaining M4 in saturation operation is 2.5€kΩ for Bâ•›â• ›= â•1› . Thus, the results obtained are: a gain band- width product, GBW, of 570€MHz for a maximum gain of 3€dB (âv†œ Câ• ›= â•4› 00€mV); an output RMS noise of 240€µV and an IM3 of −â•4› 6€dB for a differential output signal of 0.4€Vp-p at 50€MHz. In order to improve linearity and achieve higher gain than the original cir- cuit, a feedback loop is introduced into the circuit as shown in Fig.€3.8 in dashed lines. The negative feedback path, which consists of transistors M5-8, controls the common-mode current through load resistors. When this current increases, output 3.1â•… Variable Gain Amplifiers Table 3.2↜渀 VGA2 transistors sizes M1 M2 M3 M4 M5 M7 M8 41 W/L (μm/μm) 10/0.35 30/0.35 10/0.5 30/0.5 2.5/0.4 1/0.5 40/0.5 common-mode voltage, VCM,out, increases, then the drain current in transistor M5 increases and is transmitted through transistor M8 which draws the current surplus to the total current throughout M3, so the output current is reduced. Therefore, VCM,out is now controlled and fixed to 0.9€V by current source Irefâ•.› In consequence, with this technique output common mode current is controlled and thus, higher load resistances are possible (âR†œ Lâ• ›= â•5› €kΩ), higher gain can be achieved through the current mirror (Bâ• ›= â•3› , gain 18€dB, GBWâ• ›= â•1› .6€GHz) and lower power consump- tion is required. Furthermore, it moderates the variations of the common-mode current sensed by transistors M5 due to gain variation. In this way, linearity is also improved, offering distortion levels (IM3) below −â•6› 8€dB for a 0.4€Vp-p 50€MHz differential output signal. The feedback loop includes a capacitor, CC, to guarantee circuit stability. The VGA was simulated using Spectre AMS 0.35€μm CMOS level 49 device parameters. Transistor sizes are shown in Table€3.2. The chip was built in the same AMS technology, see picture in Fig.€3.9a and measured with a PCB as shown in Fig.€3.9b. In simulation, the load capacitors, CL, are 50€fF (simulating the input capacitance of the next stage) while the load resis- tors, RL, are 5€kΩ. The feedback loop capacitor, CC, is 2€pF. The circuit consumes 2.7€mW with a supply voltage of 1.8€V. Both, input common-mode and control volt- age levels are 0.9 and 1.4€V, respectively. These values have been chosen so that the control voltage input range can be maximized up to ±â•4› 00€mV, while the maximum differential input signal can swing up to 400€mVp-p. Measurements were taken using a buffer after the VGA to reduce external parasitic capacitance influence and CC was chosen external to save chip area. Post-layout simulations provide a maximum gain range of 36€dB (from −18 to 18€dB) for an almost constant bandwidth of 200€MHz, while measurements verify a similar performance offering a 190€MHz bandwidth and a minimum gain range from 0 to 18€dB. It was not possible to measure attenua- tion range due to device intrinsic noise. The gain can be continuously adjusted with a linearity error below 1€dB in both cases. Good correspondence between simula- tion and measurement can be seen in Fig.€3.10. The third-order intermodulation distortion (IM3) is simulated with two equal input signals, V1 and V2, at 50 and 51€MHz respectively. IM3 curves are shown in Fig.€3.11 over the whole input range voltage for different gain settings. Fig- ure€3.12 shows the simulated IM3 of the VGA at different frequencies when the output is 0.4 and 0.8€Vp-p. Measurements were taken at a low frequency because 42 3â•… Basic AGC Cells Fig. 3.9↜渀 VGA2 chip photograph (a) and measurement setup (b) employed buffer attenuates the signal too much making it impossible to measure distortion properly. Results are shown in Fig.€ 3.13. As can be seen, agreement is quite good compared with simulation except for input signals above 0.4€Vp-p. The sensitivity of the circuit to large input signals was known from the reference [14], however, lower sensitivity was expected from simulations. The VGA still offers very good performance for lower input signals and in spite of this limitation it continues to be a viable choice for consideration. Furthermore, future work could be to find a solution to this problem by dynamic biasing. The input-referred noise spectral density under maximum gain setting and 200€MHz bandwidth is 12€nV/√Hz only. 3.1â•… Variable Gain Amplifiers Fig. 3.10↜渀 VGA gain 25 frequency response: simulated (dashed) and 20 measured (âs†œ olid) 15 Gain (dB) 10 5 0 ¯5 105 43 Vc = 840/880mV Vc = 440mV Vc = 240mV Vc = 120mV 106 107 108 Frequency (Hz) Fig. 3.11↜渀 IM3 levels versus peak-to-peak differential input voltage (Vp-p) at 50€MHz for different gain settings IM3@50MHz (dB) ¯45 ¯50 ¯18 dB 0 dB 6 dB ¯55 12 dB ¯60 18 dB IM3 for an output voltage of 0.4 Vp-p. ¯65 ¯70 ¯75 ¯80 ¯85 ¯900.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 Input signal (Vp-p) Fig. 3.12↜渀 VGA IM3 versus frequencies at 0.4 and 0.8 ¯45 0 dB Vp-p output 18 dB ¯50 ¯55 Vo = 0.8 Vp-p Vout IM3 (dB) ¯60 ¯65 Vo = 0.4 Vp-p ¯70 ¯75 20 40 60 80 100 Frequency (MHz) 44 3â•… Basic AGC Cells Fig. 3.13↜渀 Measured HD3 for different gain settings at 100€kHz Vout HD3 (dB) ¯40 0 dB ¯45 6 dB ¯50 12 dB 18 dB ¯55 ¯60 ¯65 ¯70 ¯75 ¯80 ¯850.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Vout (Vp-p) Table 3.3↜渀 Simulation and measurement data of the VGA2 Design Simulated CMOS process (µm) Supply voltage (V) Power (mW) Intrinsic bandwidth (MHz) Gain range (dB) Gain error (dB) Mode setting Distortion (IM3) â•… 10€MHz â•… 50€MHz √ Input referred noise (nV/ Hz) 0.35 1.8 2.7 200 −18−18 <1€dB Continuous <â•−› â•7› 0(0.4€Vp-p) <â•−› â•6› 8(0.4€Vp-p) 12 a HD3 at 100 kHz Measured 0.35 1.8 2.7 190 <0−18 1€dB Continuous <â•−› â•6› 0(0.4€Vp-p)a ― ― The main performances of the proposed design are shown in Table€ 3.3. The proposed VGA offers considerably low power consumption, great bandwidth and gain range, while distortion levels and noise performance obtain acceptable values. Furthermore, it offers a continuous gain variation and so features the possibility of a fine, smooth automatic gain control. Thus, a continuously variable linear gain amplifier is obtained, without the glitches introduced by the digital control required by programmable gain amplifiers and with a good trade-off between bandwidth, gain range, power consumption, linearity and noise performance. And in spite of being a linear gain amplifier, it is possible to obtain a linear-in-dB gain amplifier using an exponential converter, like the one proposed in [17], increasing the power consumption by only 0.2€mW. 3.1.2.2â•…Proposed VGA3: Linearly Tuneable VGA with CMFF In the literature, there are also VGAs which were not originally designed as multipliers, but make use of the same principle of varying the gain through the trans- 3.1â•… Variable Gain Amplifiers Fig. 3.14↜渀 Classical CMOS pseudo-differential transconductor 9&0  YLQ  ,RXW ,RXW± 0 0 45 9&0 ±   YLQ conductance. We will now take a look at one of these VGAs [18] which also offers a good trade-off between operating frequency, gain range, and power consumption, and which the author has therefore found suitable for application in one of the AGCs presented in Chap.€4. The proposed CMOS VGA is based on a Gm cell which is a new version of the ground referred differential pair using transistors in the saturation region with balanced input signals shown in Fig.€3.14. This simple transconductor meets the currently demanded low voltage requirement. High transconductance values can also be obtained, thus being an appealing choice for high frequency operation. However, the only way to tune the transconductance necessary for compensation of fabrication tolerances and to achieve programmability of VGA characteristic parameters is through the input common mode bias voltage VCMâ•,› see (3.18).  IO = Io+ut − Io−ut = 2K (VCM − VTH )Vin. (3.18) This modifies the biasing point of the pair transistors and directly affects the trans- conductor linearity performance, since the third harmonic distortion is inversely proportional to the pair transistors gate overdrive voltage Vodâ• ›= â•V› CMâ•−› â•V› TH [19]. In addition, this issue is critical for low voltage applications where the signal swing, inherently constrained to a small headroom voltage, would be further limited due to common-mode voltage variations. On the other hand, for a VGA section consisting of cascaded Gm cells, the transconductance tuning through the input common mode voltage makes direct coupling impossible. To overcome the aforementioned disadvantages derived from changing VCM for tuning purposes, the pseudo-differential stage shown in Fig.€3.15a is proposed. Each transistor M1-M2 has been split into common-source transistors M1A-M1B and M2A-M2B. Fully balanced input signals are applied to M1A and M2A respectively, which act as improved voltage followers thanks to the negative feedback introduced through M3: M1(2)A-M3 that form a two-pole shunt negative-feedback loop. This reduces the equivalent M1(2)A source resistance down to 50€Ω, a value approximately given by 1/gm1Aro1Agm3, where parameters have their usual meaning [20]. These voltage followers: first, set the MA-MB common source quiescent voltage VS and second, accurately translate input signals to the source of MB transistors, leading, as shown in Fig.€3.15a, to source voltages VSâ•+› â•(› 1/2)Vin, VSâ•−› â•(› 1/2)Vin. Both M1B and M2B transistor gates are controlled through a bias voltage VG. Therefore, the DC current through M1B (M2B) will replicate the current through M1A (M2A), with a gain which depends on the transistor MA-MB size ratio and on the 46 3â•… Basic AGC Cells 9&& ,RXW± 9* 9&09JDLQ 9&0   YLQ 0% ,% 0$ ,% 0$ 9&0±   YLQ 0% ,RXW 9* 9&09JDLQ 0 0 D   ,RXW X$   ,%   E Ā Ā   9JDLQ 9  Fig. 3.15↜渀 CMOS pseudo-differential transconductor: a Core of the proposed topology and b Output DC current for different Vdâ• ›= â•V› Gâ•−› â•V› CM values value of the DC voltage VG with respect to VCM. For instance, given that M1A and M1B are equally sized, for VGâ• ›= â•V› CM, the current I1 through M1B will be equal to the current through M1A, which remains constant to the value IB set by the bias current. For VGâ•>› â•V› CM, I1 will be higher than IB and the contrary for the complementary case. Figure€3.15b shows, for MAâ• ›= â•M› Bâ• ›= â•1› 2/0.5€µm/µm and IBâ• ›= â•5› 0€µA, the I1 (âI†œ 2) output current DC transfer characteristic versus Vdâ• ›= â•V› Gâ•−› â•V› CM. Transistor M3 takes in M1B (M2B) current changes. Straightforward analysis of this stage shows that the output differential current is given by  Io = I2 − I1 = 2K(VGS − VT H )Vin, (3.19) 3.1â•… Variable Gain Amplifiers 47 Fig. 3.16↜渀 Proposed CMOS pseudo-differential VGA with 3-bit rough gain adjustment, CMFF (a) and selfbias common-mode feedback loop (b) where VTH and VGS are, respectively, the threshold voltage and the gate-to-source voltage of MB transistors and Kâ• ›= â•(› 1/2)μCOX(âW†œ /L)B. According to the expression in (3.19), this simple scheme makes it possible to preserve the input common mode voltage VCM constant, keeping it separate from the transconductance adjustment DC control voltage VG while, as will be shown next, linearity is independent of VG for a moderate transconductance tuning range. Another important issue is that, since a pseudo-differential structure has the same transconductance for both differential and common mode signals, the use of this solution requires a careful control of the common mode behaviour of the circuit. The common-mode control task can be performed efficiently by adopting a common-mode feedforward (CMFF) technique taking advantage of its own cell structure. As shown in Fig.€3.16a in dashed lines, CMFF cancellation is inherently achieved using the same differential transconductance by making copies of the individual currents and drawing the common-mode current at the output. Note that, at the same time, this structure sets the adequate output adaptive DC current over the whole VG tuning range. This latter feature is particularly useful as it avoids using extra circuitry, so the resulting topology is very simple and compact. In addition, this 48 Table 3.4↜渀 VGA3 transistor sizes M1 M2 M3 M4 M5A M5B M6 M7 M8 3â•… Basic AGC Cells W/L (μm/μm) 12/0.5 12/0.5 8/0.5 20/0.5 6/0.4 3/0.4 20/0.5 2/0.5 40/0.5 feedforward approach—in contrast with the alternative based on the use of a separate transconductance for the common-mode detection—adds no more load to the driving stage as it keeps the input capacitance constant. Finally, although CMFF improves the rejection to the common-mode components at the output, it is incapable of properly fixing the DC common-mode output voltage. However, the control of the common-mode output voltage is easily had by employing floating resistors and fixing the common-mode voltage with a simple selfbias feedback loop which first, senses the output nodes, adds and filters both outputs and then, compares the result with a reference to fix the voltage at the floating node (see Fig.€3.16b). Since control is regulated outside the signal path, frequency response is not affected. One of the advantages of this selfbias loop is that it avoids the use of other calibration circuitry. For the proposed VGA in Fig.€3.16,  Io1 = −Io2 = I2 − I1 = 2K(VGS − VT H )Vin and thus the transfer characteristic is (3.20)  Iod = Io1 − Io2 = 4K(VGS − VT H )Vin = GmVin, (3.21) where parameters have the same meaning as in (3.19). The circuit of Fig.€ 3.16 has been designed in 0.35€ µm CMOS technology by Austria Microsystems (AMS). Transistor sizes are shown in Table€3.4. The bias current IB has been implemented through high-swing cascode current mirrors to maximize signal swing while improving mirroring. Its value is fixed at IBâ• ›= â•5› 0€ μA. Passive component values are: C1â• ›= â•2› .4€ pF, R2â• ›= â•2› 6€ kΩ, R1â• ›= â•1› 0€ kΩ and RL1,2â• ›= â•2› €kΩ. The photograph is shown in Fig.€3.17. The corresponding layout for this structure has been carefully realized taking into account matching between transistors and symmetry between sections in order to minimize second order dis- tortion components due to mismatches [21]. In order to demonstrate the low-voltage operation, the proposed transconductor with common-mode feedforward is biased with a single supply voltage of 1.8€V. The common mode voltage VCM has been set to 1.3€V. Since the value for the bias current IB has been fixed to 50€µA, for VGâ• ›= â•V› CMâ• ›= â•1› .3€V, the current I1 (âI†œ 2) through output transistors will ideally be also equal to 50€µA. So as to keep moderate power 3.1â•… Variable Gain Amplifiers 49 60 µm VGA3 200 µm Test Buffer Calibration Buffer 70 µm 70 µm Fig. 3.17↜渀 VGA cell photograph consumption, the maximum value for the output current I1 (âI†œ 2) that will be considered is 100€µA. Therefore, for the nominal value VGâ• ›= â•V› CMâ•â›• ›= â•1› .3€V the current through output transistors is I1â• ›= â•I› 2â•›â• ›≈ â•5› 0€µA and the experimental power dissipation is 0.65€mW. For VGâ• ›= â•1› .25, 1.35 and 1.4€V the currents through output transistors are approximately 25, 75 and 100€µA respectively, and the power consumption varies between 0.55 and 1.1€mW. In order to increase the gain range, transistors M1,2B—both in the output and the feedforward path- are composed of a switchable array of transistors so that the effective (W/L)B size is changed and, according to (3.19), gain variation is obtained. In particular, a 3-bit array has been used, achieving a gain range from 0 to 12€dB in 6€dB steps. Simulations offered a bandwidth between 570 and 700€MHz for different gain settings. A measured intrinsic bandwidth almost constant above 500€MHz over the whole tuning range is obtained. Both, simulation and measured results are shown in Fig.€3.18. The measured and simulated IM3 of the output differential voltage for VGâ• ›= â•1› .3€V is depicted in Fig.€3.19, for a signal frequency of 100€MHz and considering constant output voltage levels. It is important to note that in our experimental set-up the noise floor was at values around −â•5› 0€dB due to the high operating frequency and generator noise, so it was not possible to make accurate measurements for output signals below 0.4€Vp-p. Furthermore, IM3 was also affected by a test buffer. Consequently, simulations are also given for the combination of the IM3 due to VGA and buffer blocks together: for Voutâ• ›= â•0› .4 Vp-p, an IM3 below −â•4› 0€dB is obtained for all gain settings at 100€MHz. 50 Fig. 3.18↜渀 Simulated (âd†œ ashed) and measured (âs†œ olid) VGA frequency response for different gain settings Cell Gain (dB) 12 10 8 6 4 2 0 ¯2 ¯4 ¯6105 3â•… Basic AGC Cells Vc = 1.31, bit = 100 Vc = 1.31, bit = 010 Vc = 1.31, bit = 001 106 107 108 109 Frequency (Hz) Vout IM3 @100MHz (dB) Fig. 3.19↜渀 PGA plus buffer simulated (âb†œ lack) and experi- ¯25 mental (âg†œ rey) IM3 for outputs signals of 0.4 and 0.8€Vp-p at ¯30 100€MHz ¯35 0 dB 6 dB 12 dB ¯40 ¯45 ¯500.2 0.4 0.6 0.8 1 Vout (Vp-p) As shown, the worst case results for IM3 correspond quite closely to those ex- pected by simulations, although IM3 for 6 and 12€dB was underestimated by simu- lations. Even if it was not possible to measure VGA IM3 without a buffer, it is pos- sible to obtain a first estimation: simulations offer an IM3 for an output of 0.4€Vp-p at 100€MHz below −â•4› 9.2€dB for all gain settings. The common-mode rejection ratio at low frequencies is 37, 35 and 32€dB for VGâ• ›= â•1› .25, 1.3 and 1.4€V respectively. At 100€MHz the CMRR figures are 19, 22 and 24€dB for VGâ• ›= â•1› .25, 1.3 and 1.4€V. These values are comparable to those reported for other CMOS pseudo-differential pairs using transistors in the saturation region [22]. A limitation of this topology is the restriction in the input voltage swing, imposed by maintaining transistors MA, M3 in saturation. The input VCM has been set to 1.3€V so as to obtain a maximum voltage swing of 0.6€Vp-p on each input, or equivalently, 3.1â•… Variable Gain Amplifiers Control voltage Generator vin VGA VGA 51 Vref VGA Peak Detector vout Fig. 3.20↜渀 Typical multiple cell VGA AGC structure a maximum differential 1.2€Vp-p input swing. This value is high enough for current wireless communication applications. 3.1.3  Complete VGA Architecture Design Considerations Another important aspect to be considered is the structure of the full VGA when wide gain variation range is mandatory. Typical one cell VGAs offer a maximum gain between 12 and 40€dB depending on the bandwidth of the application, so at higher frequencies lower gain is achievable. In certain applications such as Code Division Multiple Access (CDMA) for example, 80€dB gain range and above 60€dB maximum gain VGAs are required. In these cases, it may not be possible to achieve all the specifications using a single high gain VGA. An additional problem of high gain VGAs is the DC-offset at the output. An amplifier with a maximum 60€dB gain would amplify 1€mV offset in the input to 1€V at the output and would reduce the total headroom in that point. Thus, it is mandatory to use a DC-offset cancellation circuit in such VGAs. This circuit usually consists of a low-pass filter forming a slow feedback loop from the output node to the input, so that any offset at the output will be corrected in the input [23]. Therefore, several VGA cells are employed in series. The number of cells used will be a trade-off between circuit simplicity and power consumption: employing many cells will ease the design of each one but in general the total power consumption will be higher than when using fewer cells. This trade-off is more critical when all the cells employ a different control voltage, since, to the increase of the power consumption, an increment in the AGC loop complexity must be added, see Fig.€3.20. Thus, when planning to use several VGAs in series a good trade-off is usually achieved by splitting the full VGA into no more than three. However, there 52 3â•… Basic AGC Cells &RQWURO9ROWDJH *HQHUDWRU YLQ $PS $PS  $PS YRXW 9*$ Fig. 3.21↜渀 Rough/fine gain based VGA structure is another option, as explained in [24] and shown in Fig.€ 3.21. Instead of using multiple VGAs controlled by the same AGC loop, one single VGA only is employed to introduce the fine gain and several fixed gain amplifiers set up the rough gain variation. The rough gain control can be managed by simple digital circuitry and does not greatly increase the total power consumption. Furthermore, fixed gain amplifiers can be switched off when their gain is not required, reducing the power consumption when high strength signals are received. Hence, a low gain range (12–20€dB) VGA would be enough for this application. This structure also presents some advantages for the AGC loop, since, by reducing the gain range, the effective input dynamic range in the loop is also reduced and the linearity requirements for the blocks in the fine gain control loop, such as the peak detector, are relaxed. 3.1.4  Conclusions For the purpose of this work, the study of the feedforward approach for automatic gain control circuits is necessary to have a clear knowledge and to obtain a steady gain response with the control voltage, since we can not expect the inherent autocorrection of the feedback loop case. Hence, the linear response of the multiplier based VGAs fulfils this requisite quite accurately. Another alternative is the use of programmable gain amplifiers whose response can easily be predicted too. For the latter case, the cell proposed in [10] has offered a very good trade-off. To close the study of VGAs, a summary of the characteristics of the three considered structures is offered in Table€3.5. They are also compared with some of the typical VGAs that can be found in the literature. The first conclusion of the comparison is that the proposed examples offer all low power operation while keeping a wide bandwidth. Furthermore, distortion and noise levels are competitive and different gain ranges are obtainable to suit different possible applications. On the whole, a good trade-off between the main characteristics is obtained for given examples. Thus, these cells are suitable for the applications studied in this book and consequently, will be used to implement different AGC topologies as will be explained in Chap.€4. Table 3.5↜渀 Comparison of several VGAs Design Hsu [25] CMOS process (µm) 0.35 Supply voltage (V) 3.3 Power (mW) 21 Intrinsic bandwidth (MHz) 125 Gain range (dB) Mode setting 0â•∼› â•1› 9 Discrete Distortion (IM3) â•… 10€MHz â•… 50€MHz √ Input referred noise (nV / H z) −â•7› 4 (2€Vp-p) −â•5› 5 (2€Vp-p) 8.6 a OIP3 is given: 29.2€dBm b At 100 MHz Tsou [26] 0.18 1.8 2.43 0.5â•∼› â•3› 0 −â•1› 0â•∼› â•2› 0 Discrete –a –a 11.2 Philips [27] 0.25 2.5 6.75 100 5.6â•∼› â•1› 7 Discrete −â•6› 7 (1.4€Vp-p) – <â•8› 4 VGA 1 0.35 1.8 0.42 100 0â•∼› â•1› 8 Discrete −â•6› 0 (0.4€Vp-p)b – <â•›â•5› 1 VGA 2 0.35 1.8 2.7 200 −â•1› 8â•∼› â•1› 8 Continuous −â•7› 0 (0.4€Vp-p) −â•6› 8 (0.4€Vp-p) 12 VGA 3 0.35 1.8 <â•1› .1 500 0â•∼› â•1› 2 Discreteâ•+› â•c› ontinuous −â•4› 3 (0.€ Vp-p)b 13.4 53 3.1â•… Variable Gain Amplifiers 54 3â•… Basic AGC Cells Fig. 3.22↜渀 Ideal charge/dis- 1.1 charge behaviour in a peak detector with load capacitor, 1.05 C, and resistor, R 1 0.95 slope ~ ¯1/RC Signal Amplitude (V) 0.9 0.85 0.8 0.75 18 20 22 24 26 28 t (us) 3.2â•…Peak Detectors Peak detectors or, better said in our application field, envelope detectors, are a key block in gain control and spectral energy estimation. Their main function is to detect the amplitude or strength of the processing signal and track this value throughout the time. Apart from wireless communication receivers [28], these circuits can be found in a variety of applications, such as hearing aids, cochlear implants and speech recognition front-ends [29]. Furthermore, some adaptive bias techniques for linearity enhancement and dc current reduction in RF amplifiers are based on envelope power detection [30]. The design of an accurate envelope detector is also critical for the efficient magnitude locked loop (MLL) Q-tuning method used in high-Q high-frequency continuous time filters [31]. Additionally, a new generation of dynamically varying analog circuits need high performance envelope detectors to optimize signal-to-noise ratio and power dissipation, such as dynamic gain scaling (syllabic companding) [32], dynamic impedance scaling [33], dynamic biasing [34] and dynamic structure variation [35]. This section is focused on envelope detectors applied to AGCs in wireless receivers and, more precisely, to feedforward AGCs. As explained in Chap.€2, a priori, the selection of a feedforward control structure considerably increases the envelope detector performance requirements, since its input dynamic range and, consequently, the linearity demand are enlarged. Thus, this basic cell becomes still more essential for the correct performance of feedforward AGCs, such as those presented in this book. Apart from linearity, there are some more specifications which will show the envelope detector structure required for the applications analyzed here. The two main specifications in any peak detector are droop and settling-time. Droop is a slow discharge from the hold capacitor C (Fig.€3.22). Discharge can be unintentional, through a leakage current or the path provided by the following stage, or intentional, through a big resistor R or small current source Ib. The droop rate (âd†œ Vpeak/dt) is proportional to 1/RC in the case of the big resistor, or to Ib/C for the 3.2â•…Peak Detectors Fig. 3.23↜渀 Diode-RC peak detector topology 55 Vin Vpeak CL small current source, since across the capacitor, Iâ• ›= â•C› *(âd†œ Vpeak/dt). This behaviour generates ripple at the output, so the output peak voltage deviates from the true peak value. As a consequence, droop should be reduced to increase accuracy. Settlingtime is split into attack and release time. Attack-time, defined as the time required by the circuit to respond to a positive stepwise change in the input signal envelope, is dependent on the slew rate which is an indicator of the speed of the circuit. Higher slew rate offers a higher speed charging the hold capacitor. Speed is required in order to obtain a peak detector which can accurately track an increment in the input signal amplitude. The mentioned speed fixes circuit attack-time which is one of the parameters usually given to characterize peak detector speed. High speed means low attack-time. In contrast, release-time, defined as the time required to respond to a negative stepwise change in the input signal envelope, depends on the capacitor discharge current and the capacitor size itself. This parameter defines the peak detector capacity to track a decline in the input signal amplitude. One of the main problems with envelope detectors is that droop and releasetime are correlated. Both are controlled by the capacitance plus the current source or the load resistor. Release-time is reduced choosing smaller capacitor (or bigger discharge current) while droop is reduced with a bigger capacitor (or smaller discharge current) that will discharge slowly. Therefore, there is a trade-off between fast decay-time and low droop rate in peak detector design [36]. There are more specifications, such as the sensitivity of the circuit output signal to input signal impairments [37]. This error is reduced simply by integrating several cycles before generating the output. Finally, the peak detector, as well as most IC´s, can retain minimum performance specifications considering PVT variations. The aim of delving into feedforward gain control configurations to achieve fast and accurate AGCs, requires high performance fast settling-time envelope detectors with high linearity. Next, different peak detector topologies will be analyzed, starting from the simplest and increasing complexity until previously introduced minimum requirements are achieved, following on to reach several peak detector topologies which are more appropriate for the studied applications. 3.2.1  Basic Peak Detector Topologies The conventional diode-RC circuit, shown in Fig.€3.23, is the simplest structure that can work as a peak detector. In this circuit, when the input signal is above the output signal plus the diode threshold voltage Vtd, the diode is equivalent to a resistor and the capacitor is charged by the current which flows from the input. On the other 56 Fig. 3.24↜渀 Op-amp plus diode based peak detector topology Vin ¯ OA1 + 3â•… Basic AGC Cells Vpeak ¯ OA2 Vout + CL Fig. 3.25↜渀 Op-amp plus source follower based peak detector topology Vin + OA ¯ M1 Vpeak CL hand, when the input signal is smaller, the diode is in cut off operation region and the capacitor load is slowly discharged through the resistance. In spite of, or due to its simplicity, this circuit is not practical in present-day low voltage applications, as the diode does not allow detecting input signals with a peak voltage below Vtd. In addition, the diode threshold voltage depends on the temperature and process variation, so this structure is very inaccurate. To improve the accuracy, an op-amp can be employed in feedback configuration so that the diode output is connected to the op-amp negative input, as shown in Fig.€3.24 [38, 39, 40]. This op-amp and diode based peak detector reduces the threshold voltage to Vtd/A0, where A0 is the op-amp DC gain. Hence, this circuit can closely track Vin while its value is above the capacitor voltage, Vpeak. Alternatively, when the input signal is below Vpeak, the op-amp output goes to negative saturation, the diode goes to the cut-off region and the capacitor voltage is slowly discharged in the same way as previously explained. In order to minimize uncontrolled capacitor charge/discharge currents, a second op-amp is employed as a buffer to isolate Vpeak from the next stage. Furthermore, these unwanted currents can be completely cancelled just by employing MOSFET input devices in both op-amps. The main drawback of this circuit is that op-amp and diode based envelope detectors have a problem due to high distortion during the zero crossing of the input signal. This is because the op-amps have to recover during non-conduction/conduction transition with a small finite signal dV/dt (slew rate). The envelope detector is therefore limited to a frequency performance well below the gain bandwidth product of the amplifier. A similar topology is obtained simply by employing a source follower to perform the diode function [41, 42, 43], as shown in Fig.€3.25. Its performance is similar to that explained for the op-amp plus diode topology: while Vin exceeds Vpeak, M1 is on, 3.2â•…Peak Detectors Fig. 3.26↜渀 Open-loop peak detector topology Vin¯ ¯ + OTA Vin+ + ¯ RECTIFIER 57 PEAK DETECTOR Vpeak RL which charges the capacitor C. While Vin goes below Vpeak, M1 is off and the capacitor holds the output peak voltage. A very small current source Ib can be included to discharge the capacitor for better tracking. However, as well as in the previous topology, this scheme also requires high slew rate and its frequency performance is limited. 3.2.2  Open-Loop Envelope Detectors. Proposed PD1 and PD2 As an alternative to closed loop schemes, a solution is to use an open-loop configuration [37] to achieve higher operating frequencies. This kind of circuit makes use of an OTA for voltage to current conversion followed by a precision rectifier and a current mode peak detector or a capacitor so that integration is made, see Fig.€3.26. Due to the fact that the OTA is performing the voltage to current conversion in open loop and current mode rectifiers can operate at frequencies as high as 100€ MHz [44], this circuit is capable of working at higher frequencies than diode based peak detectors. Next, we are going to evaluate several envelope detectors, all of which are suitable for wireless LAN applications. 3.2.2.1â•…Proposed PD1: Conventional Open-Loop Envelope Detectors The objective is to obtain a high performance envelope detector with a 71€ MHz performance frequency and input amplitudes above 300€mV. The precision rectifier used for this circuit is based on the configuration proposed in [44] which is shown in Fig.€3.27. This cell has been chosen due to its linearity for frequencies up to 100€MHz and input current signals above 150€µA. The bias voltage VB1 is used to bias M1 and M2 transistors to have drain currents of 2.5€µA; This bias voltage has the function of a threshold current and the rectifier does not rectify input current signals below this value. In order to overcome this limitation, an offset current is generated by the OTA with a value slightly higher than the bias current, so the signal is always above the threshold current. As high input frequencies, direct coupling and good control of the output offset current are required, the design of the OTA is started with the fully differential version of the folded cascode OTA, see Fig.€3.28. The bias voltage VC1 controls the offset current required for the next stage and indirectly, the common-mode voltage 58 Fig. 3.27↜渀 Schematic diagram of the full-wave precision rectifier block VDD VB2 M4 M1 Iin+ M2 3â•… Basic AGC Cells Iout VB1 M1 M2 Iin¯ VB3 M3 Ibias VBP + VC1 ¯ M4 Vin+ Iout+ IN2 VDD M3 M3 IP M1 M1 Vin¯ IN1 RD VC1 + ¯ M4 Iout¯ VBN M5 M2 M2 M5 VSS Fig. 3.28↜渀 Schematic diagram of the mirrored cascode OTA at the output of the OTA. Due to the direct coupling between the OTA and the recti- fier, the offset current biases the diode-like transistor at the input of the rectifier, while the rectifier’s input resistance fixes the common-mode voltage at the output of the OTA. This makes the common-mode feedback circuit unnecessary. Finally, Fig.€3.29 shows the cell of the peak detector which is suitable for opera- tion up to frequencies of 100€MHz. It consists of a slow source follower composed of M3, IL, CL and the feedback transistor M1a [29, 45]. The transistor M1b outputs a copy of the current in M1a, while transistors M2a,b are introduced to obtain a higher output resistance and thus, to minimize the offset current at the output. The source follower can follow descending signals in the input voltage rapidly because of the exponential dependence of the current of M3 on its gate voltage. However, the small current IL is slow in charging capacitor CL; as a result, during ascending signals in 3.2â•…Peak Detectors Fig. 3.29↜渀 Schematic diagram of the peak detector block M1a VDD IL CL 59 M1b M2a VBP M3 Iin Ibias VSS M2b Iout Ibias Table 3.6↜渀 PD1 devices sizes M1 M2 M3 M4 M5 W/L (μm/μm) Rectifier 2/0.4 2/0.4 30/2 5/0.4 – OTA 100/0.4 90/2 150/2 40/0.4 60/2 PD 20/0.8 5/0.4 20/0.4 – – the input, the output signal is slow to respond as discharge slope is proportional to CL/IL. In consequence, the ripple and time constant, τ, are controlled by IL and CL. This circuit was first simulated and next fabricated in AMS 0.35€ μm CMOS technology. All the blocks are powered with a single power supply of 3.3€V. Transis- tors sizes are shown in Table€3.6. Bias current, Ibias, in rectifier and in peak detector are 100 and 20€μA, respectively. IL is 1€μA, while IN1, IN2 and IP are 300, 200 and 500€μA, respectively. Finally, RD is 2.8€kΩ and CL is 1€pF. Chip photograph is shown in Fig.€3.30. Measurements were realized employing a PCB and a 500€MHz band- width oscilloscope (for further information see Appendix A). The first parameter measured was the linearity of the circuit shown in Fig.€ 3.31 for input sinusoidal signals at 71€MHz. The simulated result was up to 33 dB range for ±1€dB linearity, while the measurement offered quite a close value with 29€dB range. Next, the other two principal parameters were measured: ripple and settling- time. In this case a square signal was employed at 500€kHz with a predefined offset so that the input signal was equivalent to a 20€dB stepwise signal. Results are shown in Fig.€3.32. Simulated release-time was around 0.15€μs, but 0.6€μs was measured. The same happens with attack-time where the measured time has a similar value to the release-time. There is an easy explanation for these discordances. As mentioned, the attack-time of the presented peak detector should be incredibly fast due to the exponential behaviour of the current in transistor M3. On the other hand, release- 60 Fig. 3.30↜渀 Chip photograph of the peak detector PD1 3HDN'HWHFWRU 3â•… Basic AGC Cells 27$ 5HFWLILHU µP µP Fig. 3.31↜渀 Measured and ideal linearity performance Output signal (V) 900 800 y = 0.763*x + 80.6 700 600 500 400 300 200 100 0 0 200 400 600 Input signal (Vp-p) Ideal Measured 800 1000 Fig. 3.32↜渀 Measured tracking (âs†œ olid grey line) of the openloop envelope detectors for a 500€kHz square signal (âs†œ olid black line) and simulation results (âd†œ ashed grey line) for a 71€MHz sinusoidal signal with a stepwise change (âd†œ ashed black line) Detector Signals (V) 0.5 0.4 0.3 0.2 0.1 0 ¯0.1 ¯0.2 ¯0.3 ¯0.4 ¯0.50 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 t (s) x 10¯6 3.2â•…Peak Detectors 61 Table 3.7↜渀 Comparison of principal characteristics for simulation and measurements of the open-loop peak detector Design Supply voltage (V) Power (mW) Performance frequency (MHz) Settling time (−20€dB step) (µs) Ripple (âV†œ inâ• ›= â•4› 40 mVp–p) (mVp–p) Linearity range (╱› â•1› 0%) (dB) Simulation 3.3 6.1 71 0.15 2.5 ∼â•3› 3 Measurements 3.3 6.1 71 0.6 15 ∼â•2› 9 time is slow as it depends on the relation between CL and IL. Furthermore, as simulated parasitic capacitances (~â•7› €pF) between the chip and the PCB did not degrade the circuit performance considerably, simple buffers were kept. However, the only explanation to obtain similar settling-times in both cases is that larger parasitic capacitances than expected have degraded the performance at the output. Droop was also measured with the oscilloscope and the measured peak-to-peak ripple went up to 15€mV. A discordance appeared again as simulations had predicted a ripple of 2.5€ mV. Noise, low oscilloscope accuracy for small signals and PVT variations are possible responses to this issue. However, the lack of accuracy in settling-time measurements prevents it from being solved by making use of the known relation between both performances. Finally, a summary of circuit characteristics is given in Table€3.7 for simulation and measurement. A structure based on the high performance envelope detector topology presented here but scaled for a 10€MHz performance frequency application was also implemented in order to compare it with other peak detectors that will be introduced next. This scheme suffers from the same limitation as all the topologies introduced in Figs.€3.23, 3.24 and 3.25: the trade off between droop and settling-time that makes necessary the use of filters at the output to minimize the ripple of the envelope at the cost of higher area and power consumption. Next, a novel envelope detector, proposed in [46, 47], is developed. Then, this circuit is modified so that it overcomes the traditional trade-off present in these circuits, thus improving both the droop and the settling-time of the circuit. 3.2.2.2â•…Proposed PD2: Fast-Settling Open-Loop Envelope Detector Figure€3.33 shows the conceptual scheme of the newly proposed envelope detector. As can be seen, the circuit makes use of two peak detectors working in parallel. However, it is then shown that it is unnecessary to duplicate all the circuit; in fact, no more than a part of the peak hold circuit is duplicated, as will be shown later. In order to obtain the modified circuit, peak holders are employed instead of the peak detector to achieve a smaller ripple. The switches at the peak holders and the output are managed by a square signal provided by two control circuits. The control path changes the phase of the input signal by 90º before generating the digital signal by a few inverters. Thus, the peak holder is in hold mode just when the signal has reached its maximum value. This allows us to employ smaller load capacitance 62 3â•… Basic AGC Cells CONTROL ¯ Vin¯ ¯+ OTA Vin+ + ¯ RECTIFIER CONTROL + RL PEAK HOLDER RL Fig. 3.33↜渀 Fast-settling open-loop envelope detector block diagram Vout CO 9& 9'' 9& ,/ &/ &/ 0 0 0 9%S 0 0 0 0 ,LQ ,ELDV 966 Fig. 3.34↜渀 Schematic of the peak hold block ,RXW ,ELDV ,RXWĀ ,ELDV without spoiling the DC level obtained during the hold mode. To obtain the envelope of the signal, two peak holders work in parallel, one of them always providing a signal in hold mode at the output. The OTA and the rectifier are the same ones used for the basic topology. The following introduces the control path and the peak hold circuit shown in Fig.€3.33: Figure€ 3.34 shows the proposed peak hold block. Note that the advantage of using current mirrors in Fig.€ 3.29 makes it unnecessary to duplicate all the circuit to obtain two peak holders. Both circuits work with the same discharge path during different periods: when the first peak holder is in hold mode the second is discharging and vice versa, Fig.€3.35 clarifies this. In red and black is shown the performance of each half peak holder. The envelope of the signal is obtained by switching between both halves and transmitting to the output only the hold signal. VC1 and VC2 are the signals provided by the control path and manage the switches of the peak holds. 3.2â•…Peak Detectors 63 0.2 Amplitude (V) 0.1 0 ¯0.1 ¯0.20.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t (us) 2 1 Clock (V) 0 ¯1 ¯2 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t (us) Fig. 3.35↜渀 Envelope detector operation. Peak holder both output signals (âg†œ rey and black) and input signal (--) (âu†œ p). Below VC1 control signal Fig. 3.36↜渀 Schematic diagram of the control path CC Vin VDD Vout RC VSS The power consumption is increased by 50% at this stage. However, we must remember that over 90% of the power consumption of the complete circuit is due to the OTA and in consequence, this increase is insignificant. Furthermore, two capacitances are employed instead of one, but the total capacitance is much smaller than the original. On the other hand, this configuration has a great advantage: the release time constant is given by CL and IL, while the ripple depends on CL and the equivalent resistance of the switches when working in subthreshold. This resistance is very high and offers the possibility of using much smaller capacitances, besides obtaining smaller ripple. The control path consists of a passive RC-differentiator followed by a few inverters as shown Fig.€3.36. The major problem of this stage is that after deriving the input signal to obtain a phase delay of 90º it is necessary to amplify the signal by the inverters to obtain a signal capable of managing the switches. In consequence, noise is also amplified and dynamic range is reduced. To minimize this effect, instead of a 64 Fig. 3.37↜渀 Ripple of the conventional (--) and the proposed (―) envelope detectors for an input voltage of 300€mV at 10€MHz and a total capacitance of 3.2€pF Detector Vout (V) 0.304 0.302 0.3 0.298 0.296 0.294 0.292 0.29 0.288 0.286 4 3â•… Basic AGC Cells PD1 10MHz PD2 4.5 5 5.5 6 t (s) x 10¯6 fourth inverter, two control paths are employed and a capacitance, CO, is connected at the output (see Fig.€3.33) working as a first-order low-pass filter, thus providing a signal-to-noise ratio (SNR) not less than 60€dB. The need for a capacitance at the output could be considered a setback; nevertheless the total silicon area in this circuit is much smaller than that needed in the conventional counterpart of PD1 for 10€MHz and tracking is still much faster, as we will see. To verify the circuit performance, SPECTRE is used to simulate the proposed circuit using the AMS 0.35€ µm technology. The proposed envelope detector has been designed with the following component values: Transistors W/L relations are M1â• ›= â•2› 0/0.8, M2â• ›= â•5› /0.4, M3â• ›= â•2› 0/0.4, Ibiasâ• ›= â•2› 0€ µA, CLâ• ›= â•0› .6€ pF, CCâ• ›= â•0› .1€ pF and COâ• ›= â•1› .6€ pF; while ILâ• ›= â•1› € µA, RCâ• ›= â•1› 0€ kΩ and RLâ• ›= â•2› € kΩ. The obtained ripple is around 0.3% when Vinâ• ›= â•3› 00€mV for a total capacitance CTâ• ›= â•3› .2€pF. On the other hand, if we use an equivalent capacitance area at the conventional circuit, i.e. CLâ• ›= â•3› .2€ pF, the minimum ripple to be reached is around 3%, as depicted in Fig.€3.37, and if we use the same IL to obtain a similar release-time, then ripple is ten times that percentage. In order to compare the release time constant, the ripple is fixed at around 1%; In this case, the conventional circuit needs a huge load capaci- tance of 10€pF while the proposed circuit maintains previous values. A stepwise sig- nal at 10€MHz is employed in both circuits, which descends abruptly from a peak of 300 to 30€mV; results are shown in Fig.€3.38. As can be seen, the proposed circuit is much faster tracking the signal than the conventional one and in addition, it is pos- sible to configure the desired release time constant by IL without changing the ripple of the envelope. The release-time constants, τ, defined as the time required by the signal to respond to 99% of a 20€dB stepwise change, are in this case τâ• ›= â•2› 7.5€µs for the conventional circuit and  = â•0› .4€µs for the proposed circuit. Figure€3.39 shows DC and 10€MHz transfer characteristic. As seen, both envelope detectors are linear for amplitudes up to 300€mV. The proposed envelope detector obtains lower amplitude at high frequency since there is a gap between the input signal and the control path signal and the hold mode starts 3.2â•…Peak Detectors Fig. 3.38↜渀 Tracking of (--) ideal, (-.) conventional and (―) proposed envelope detectors for a step signal at 10€MHz and ripple of 1% Fig. 3.39↜渀 DC (o) and 10€MHz (-) transfer characteristic for the conventional and the proposed envelope detector Vout RMS (Vrms) Detector Signals (Vpk) 0.35 0.3 0.25 0.2 0.15 0.1 0.05 00 PD1 for 10MHz PD2 0.5 1 1.5 2 2.5 t (s) 65 3 3.5 x 10¯5 0.4 PD2 (10MHz) 0.35 PD2 (DC) PD1 (DC) 0.3 PD1 (10MHz) 0.25 0.2 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 Vin (Vpk) Table 3.8↜渀 Comparison summary between PD1 and PD2 for 10€MHz Ripple (CTâ• ›= â•3› .2€pF) (%)  (99%) (ripple 1%) (µs) Power consumption (mW) Conventional circuit 3 27.5 2.13 Proposed circuit 0.3 0.4 2.49 just after the signal has reached its maximum. However, this gap can be minimized with careful phase matching of both signals. Table€3.8 summarizes the main characteristics of both envelope detectors. The proposed envelope detector has 17% higher power consumption. However, in return, it obtains much better performance in keeping and tracking at the same time. This leads to simplifying the circuits required after the detector, and obtaining a faster circuit. Moreover, the capacitance area needed to obtain the same ripple is for this configuration a third of that needed by the conventional circuit. 66 Fig. 3.40↜渀 OTA plus current mirror closed-loop topology 3â•… Basic AGC Cells Vin M1 + OTA ¯ M2 Vpeak CL 3.2.3  Closed-Loop Envelope Detectors. Proposed   PD3 and PD4 Although open-loop configuration is a proven solution for achieving higher performance operation frequency, closed-loop topologies can still offer similar frequencies with the advantages that the higher linearity closed-loop configurations offer inherently. The op-amp/diode topology of Fig.€3.24 can be replaced by a transconductor plus a current mirror (M1 and M2) structure [48, 49], as shown in Fig.€3.40. When Vpeakâ•<› â•V› in and the capacitor is being charged, the behaviour of this circuit is ideally described by:  IL + Gm(Vpeak − Vin) = −CL d Vpeak dt (3.22) or  d Vpeak dt + Gm CL Vpeak = Gm CL Vin − IL , CL (3.23) where it is shown that the tracking behaviour of the peak detector can be improved just by increasing Gm/CL, instead of the slew-rate in the op-amp/diode topology. The advantage in this case is that higher values can be obtained for transconductance simply by using Gm-boosted transconductors. On the other hand, when Vpeakâ•>› â•V› in, since the current mirror is unidirectional it can not discharge the load capacitor and CL is slowly discharged by IL following these expressions:  dVpeak (t ) = dQ (t) CL = IL dt, CL (3.24) where, since IL is a constant current, the capacitor discharge is linear with IL/CL:  Vpeak(t ) = Vpeak (0) − IL t. CL (3.25) 3.2â•…Peak Detectors 67 1.8 V IB 80uA Vin+ M1 5/0.5 M2 3/0.35 IB IB M1 M4 5/0.4 M2 M3 3/0.35 M5 M5 5/0.4 Vout CL 1.5pF IL 0.5uA CL M4 IB IB IB M1 M1 Vin¯ M3 M2 M2 Fig. 3.41↜渀 Schematic of a high-Gm OTA/current mirror based peak detector As a result, peak detector settling time increases with the detected input signal amplitude and it must be calculated for the worst case, i.e. the maximum possible amplitude. 3.2.3.1â•…Proposed PD3: High-Gm Transconductor/Current Mirror Based PD The peak detector structure is a differential positive scheme where one detector is employed for each balanced signal, adding both signals at a single output. The schematic is shown in Fig.€3.41, specifying transistor sizes, component values and biasing conditions. Rather than using a simple transconductor as in [48, 49], we employ a high performance Gm-cell based on the same core cell as the PGA proposed in [34]. In this way, with a very compact design, the peak detector exhibits higher linearity at higher frequencies with lower power consumption [50]. The aforementioned positive envelope detector has been designed in AMS 0.35€ µm CMOS technology and simulated using SPECTRE with a BSIM3v3.2 level 53 transistor model. The circuit linearity and frequency response were tested introducing differential signals from 40 to 400€mVp-p at 100€MHz. The input-output performance with sinusoidal input for the implemented envelope detector is given in Fig.€ 3.42. It is found that deviations from ideal behaviour are below╱› â•0› .5€ dB for all the input range. Next, the convergence of the circuit is tested introducing a 21€dB stepwise signal. To measure the attack-time, the input signal is increased by 21€dB, and the detector converges in less than 40 ns. On the other hand, to measure the release-time the input signal is reduced. The result for the latter is shown in Fig.€3.43. The worst case settling-time is no more than 0.25€µs. This circuit presents, due to the employed Gm-boosted transconductor cell, a highly linear envelope detector. Furthermore, as a result of employing this transconductor cell, it is also suitable for Very High Frequency (VHF) applications. Finally, release-time is, as expected, the same achieved by any conventional envelope detector. 68 Fig. 3.42↜渀 Peak detector input-output performance Vout (V) 3â•… Basic AGC Cells 0.09 Ideal 0.08 Simulated 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Vin,p-p (V) Fig. 3.43↜渀 Peak detector 0.3 convergence performance for an input sinusoidal 100€MHz stepwise signal 0.2 0.1 Input & OutPD (V) 0 –0.1 –0.2 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t (us) In the same way as made for PD1, it is possible to design a fast-settling envelope detector based on the topology of PD3. This time, the new version, which is presented next, is part of the AGC proposed in [51], targeting specifically an IEEE 802.11a 5-GHz WLAN receiver application. It is implemented in SiGe technology in order to raise the range of study of this work. This technology offers advantages such as higher transconductance and consequently, higher linearity and speed, but also has some disadvantages such as the leakage current due to gate current. 3.2.3.2â•…Proposed PD4: Fast-Settling OTA/Current Mirror PD As well as the topology PD3 presented, the basic PD4 cell is a differential positive peak detector where, instead of a diode, a unidirectional current mirror is employed 3.2â•…Peak Detectors 69 9'' 6 6 9 9Ā &/ ,/ &/ 6 9SK 6 Fig. 3.44↜渀 Schematic of the fast-settling OTA/current mirror PD together with a transconductor to implement the rectifier. A significant difference is the use of source followers as buffers in order to avoid bipolar transistor base cur- rent discharging the load capacitors. Furthermore, the circuit is split into two parts. Half cell is employed to detect the positive peak of each balanced signal, V1±, and the hold value of both peaks is transmitted to the output sequentially, see Fig.€3.44. The detector makes use of switches, S1-4, so a track and hold behaviour is obtained. This characteristic allows us to employ smaller load capacitance without spoiling the DC level obtained during the hold mode. The switches are managed by a digital control signal generated by a few D flip-flops and logic gates from a single 5€MHz clock provided by the receiver. The performance of each side of the circuit can be split into three different states, depending on the position of the switches and two symbols, where a symbol is de- fined as a period of time fixed by the control signal (0.4€μs in this case). Thus, it is composed of several input signal cycles. The states are: the tracking state, which requires one full symbol, and the hold and discharge states, which together take another symbol. During the first symbol in the left side detector, switches S1,3 are “off” and the left side load capacitor is charged with the positive input signal; this is called tracking state. At the beginning of the second symbol, hold state starts and S3 is closed so that the peak detected during previous period is transmitted to the output. In the last state named discharge, S1 is closed and S3 is opened, so that the rest of the second symbol is employed to discharge the load capacitor, CL, through current IL. This performance is successively repeated during the following symbols. The right side of the detector works equivalently, but employing the even symbols for tracking state and odd symbols for hold and discharge. Thus, this technique employs half circuit to detect the peak during odd symbols and the second one for even symbols. The advantage of considering symbols is that this way, this topology is also suitable for more complex modulated signals such as orthogonal frequency division multiplexing (OFDM). The envelope detector was designed, like the AGC, in a low-cost 0.25€ μm 75€GHz SiGe BiCMOS process. It employs a single supply voltage of 2.5€V and has a total current consumption of 220€μA.. The photograph of the integrated detec- tor is shown in Fig.€3.45. The linearity performance is depicted in Fig.€3.46 for a 70 70 µm PMOS Transistors Bio. Diff. pair Current Bias Buffers Fig. 3.45↜渀 Chip photograph 3â•… Basic AGC Cells C1 440 µm Fig. 3.46↜渀 Measured and ideal input-output performance Peak Detector Output (mV) 0 ¯50 ¯100 Measured linear y = 0.495*x - 250 ¯150 ¯200 ¯250 -300 0 50 100 150 200 250 300 350 400 450 Vin+ (mVp-p) 20€MHz sinusoidal input signal. It can be seen that a 20€dB range with nonlinearities below╱› â•0› .5€dB is offered at least. The settling-time of the envelope detector was measured with a 20€MHz input sinusoidal signal modulated by a 400€kHz square signal. The result is shown in Fig.€3.47. Due to the awful modulation, release-time only can be measured, but the step response of the discharge is clear and the fast discharge is shown clearly setting in 1€μs. 3.2.4  S/H Based Envelope Detector. Proposed PD5 Many different envelope detector topologies have already been analyzed. However, they are all based on some kind of rectification and integration. In fact, track and hold based topologies are no more than a mix between sample and hold circuits and peak detectors. Therefore, it will be shown next how theoretically a basic sample and hold (S/H) circuit, where switches are controlled properly, can also be employed to track the envelope of a signal. 3.2â•…Peak Detectors 71 $PSOLWXGH 9                   W V [Ā       Ā Ā Ā Ā Ā Ā Ā Ā Ā Ā                  W V [Ā $PSOLWXGH 9 Fig. 3.47↜渀 Simulated (âu†œ p) and measured (âd†œ own) convergence performance with a 20€MHz input sinusoidal signal modulated by a 400€kHz square signal 3.2.4.1â•…Proposed PD5: S/H Based Envelope Detector The conceptual scheme of the topology presented next is shown in Fig.€3.48 [52]. In fact, this topology is almost the same as that offered in Fig.€3.33 for PD2. As well 72 9LQ %XIIHU 9LQĀ 6 Ā  3HDN+ROGHU 6  699Ā Ā Ā &RQWURO 6Ā 6 Ā Ā 3HDN+R9OG9HUĀ  6  Ā 3â•… Basic AGC Cells 9RXW 9RXWĀ Fig. 3.48↜渀 S/H based detector conceptual scheme VDD S ¯ CC Vin S+ RC VSS Fig. 3.49↜渀 Schematic of the control block as in the mentioned detector, to obtain the envelope of the signal, two peak hold circuits work in parallel, one of them always providing a signal in hold mode at the output. The switches at the peak holder and the output are managed by a square signal provided by a control circuit. The control path changes the phase of the input signal by 90º before generating the digital signal by a few inverters (see Fig.€3.49). Thus, the peak holder is in hold mode just when the signal has reached its maximum value. This allows us to employ smaller load capacitance without spoiling the DC level obtained during the hold mode. The change in the phase can be made in several ways. In this case, amplitude-shift keying (ASK) or amplitude modulation (AM) applications are targeted, so for a constant frequency input signal, a simple RC differentiator can be used. The control circuit is to be adapted to the application or signal modulation required in the circuit. For example, in the case of applications where frequency modulation must be adopted, a simple RC differentiator would not be accurate enough and an RC-CR circuit could be used for input and control signals since it offers ideally both outputs with a 90º phase shift over the whole frequency range. The main change comes in the employed peak holder block. Its schematic is shown in Fig.€3.50. The OTA, a telescopic OTA with cascode compensation, is that shown in Fig.€3.51. One of the reasons for using this basic sample and hold scheme is that it was specially designed to overcome certain drawbacks due to non-ideal effects associated with the use of switches in sample and hold circuits, which limit its dynamic range. These effects are capacitive feedthrough and, mainly, charge injection. 3.2â•…Peak Detectors Fig. 3.50↜渀 Schematic diagram of the peak holder S+ VG1 Vin+ R1 Vin¯ VG1 S+ VG2 S¯ R2 CL ¯+ OTA S¯ +¯ CL R2 VG2 VDD Vb3 V0+ M12 Co M7 M8 Vb2 Co M5 M6 Vb1 M3 M4 M10 +Vin/2 M1 M2 ¯Vin/2 M13 Vo¯ M11 73 Vout+ Vout¯ Vb0 M9 M1 4 MC1 MC2 MC3 MC4 VSS Fig. 3.51↜渀 Schematic diagram of the telescopic OTA To understand charge injection, consider a MOS switch followed by a load capacitor. When the MOS switch is on, there is a charge under the gate oxide resulting from the inverted channel. When the switch is turned off, part of this charge is injected into the load capacitor which results in a change of voltage across it [53]. This change in voltage is nonlinear with respect to the input signal and consequently 74 3â•… Basic AGC Cells makes the envelope detector nonlinear with respect to the input signal. The change in load voltage is given by:  Vload = − CoxW L(VDD − Vin 2Cload − VT H ) , where the threshold voltage, VTH, is a nonlinear function of Vin: (3.26)  VT H = VT H 0 + γ 2Vfp + Vin − 2Vfp . (3.27) The advantage of this circuit is that both sides of the switch are at virtual ground and the change in voltage is no longer dependent on the threshold voltage of the switch itself. Therefore, the charge injection will be independent of the input signal and will result as a simple offset at the output [53]. When sampling, V– is closed and V+ is opened, and the equivalent circuit is a low-pass filter with buffered input and an approximated transfer function given by.  vout = − R2 1 . (3.28) vin R1 (sR2C1 + 1) Once the hold mode starts, the output will stay constant at a value equal to the input signal. In our case, R2C1 is chosen small to obtain a fast-settling circuit. Thus, capacitor area is saved and ripple is kept low since discharge is controlled by the equivalent resistance of the switches when turned-off. A MOS transistor is employed in parallel with resistances R1 and R2. As a result, it is possible to control the total gain of the circuit with small variations of their gate voltages. This is very useful if we need to compensate for the gain factor that appears when envelope is detected in this circuit. In our particular design, gain was fixed so the relation between input signal amplitude and output signal root-meansquare was equal to one. Mismatching between both peak holders introduces a time varying DC offset in the output. However, since cross-coupling outputs are employed, this offset is the same in both outputs so it is cancelled when the differential output is considered. On the other hand, if we introduce a dc offset in the input, the balanced output does not cancel it and the performance of the detector is degraded. However, this circuit shall be considered part of a complete automatic gain control circuit where a DC offset cancellation circuit is employed, so this problem can be overlooked [49]. To verify the circuit performance, SPECTRE is used to simulate the proposed circuit using the AMS 0.35€ μm technology. The proposed envelope detector has been designed with the following component values: C1â• ›= â•0› .3€pF and CCâ• ›= â•0› .1€pF; while RCâ• ›= â•1› 0€kΩ and R1,2â• ›= â•6› €kΩ. Transistor sizes are shown in Table€3.9. Furthermore, each OTA requires two compensation capacitors of COâ• ›= â•0› .5€pF considering load capacitors of 1.6€pF. These loads together with switch transistors are employed as a simple first order low pass loop filter. Thus, the ripple is around 0.3% when 3.2â•…Peak Detectors Table 3.9↜渀 PD5 transistor sizes M1,2 M3,4 M5,6 M7,8 M9 M10,11 M12,13 M14 MC1,2 MC3,4 75 W/L (μm/μm) 4/0.4 18/0.4 4/0.4 10/1.2 11.6/0.4 90/0.4 30/1.2 30/0.4 1.9/0.4 5/0.4 Fig. 3.52↜渀 Tracking of ideal (--), conventional (-.) and proposed (─) envelope detectors for a step signal at 10€MHz and ripple of 1% Vin (Vpk) 0.35 0.3 0.25 0.2 0.15 Ideal PD5 0.1 0.05 00 0.5 1 PD1 for 10MHz 1.5 2 2.5 3 3.5 t (s) x 10¯5 Vinâ• ›= â•3› 00€mV for a total capacitance CTotalâ• ›= â•3› .3€pF. In order to check the release time constant, a 10€MHz sinusoidal signal is employed, where the amplitude descends abruptly from a peak of 300 to 30€mV. The result is shown in Fig.€3.52 and compared with the topology of PD1 for 10€MHz modified to obtain the same ripple with the same input signal. As can be seen, the proposed circuit is much faster at tracking the signal than PD1, in the same way as with PD2 in Fig.€3.38. The release time constants, τ, defined as the time required by the signal to respond to 99% of a stepwise change, is τâ• ›= â•0› .4€µs. The operation of the envelope detector can be understood in the same way as explained previously for PD2 and shown in Fig.€3.35. Figure€ 3.53 shows the circuit performance for a frequency modulated signal. Since the phase shift between the input and the control signal varies between 90 and 85º, the peak detection varies slightly for different frequencies, increasing ripple. However, as mentioned, this problem could be solved by employing an RC-CR circuit which would maintain a constant phase shift of 90º for the whole frequency range. Furthermore, we have to consider that typical frequency modulated signals variations are into a small frequency range around the IF frequency, so the differences in the phase shift will usually be negligible. 76 Fig. 3.53↜渀 Envelope detection of a frequency modulated input signal Fig. 3.54↜渀 10€MHz input output performance for different envelope detectors Amplitude (V) 3â•… Basic AGC Cells 0.2 0.15 0.1 0.05 0 ¯0.05 ¯0.1 ¯0.15 ¯0.2 0 2 4 6 8 10 t (us)  Ā ,GHDO 3' 3'DW0+] 3' 506 9RXW  9UPV Ā Ā Ā Ā Ā Ā  9LQ 9SN Although the performance obtained in keeping and tracking is similar to that obtained by the fast-settling envelope detector PD2, in this case the linearity is 20€dB higher. Figure€3.54 shows the 10€MHz transfer characteristic for the envelope detectors PD1, PD2 and PD5. In fact, linearity could be further improved, bettering gain and frequency behaviour in the control circuit, since the nonlinearity at low voltage seems to be due to the fact that the input voltage is employed to manage switches. In return for the increase in circuit complexity and consumption, this envelope detector offers high performance characteristics: much smaller release time constant, smaller ripple independent of the discharge resistor, higher linearity and consequently, higher dynamic range. 3.2.5  Conclusions To end this section, Table€3.10 summarizes the principal characteristics of evaluated envelope detectors. They all have high performance characteristics and are suitable Table 3.10↜渀 Comparison of proposed envelope detectors Design PD1 PD1 (b) Technology Supply voltage (V) Power (mW) Performance freq. (MHz) Fast-settling technique Capacitance (pF) Settling time (−â•2› 0€dB step) (µs) Ripple (Vinâ• ›= â•4› 40€mVpp) Linearity range (±â•1› €dB) (dB) CMOS 0.35€µm 3.3 6.1 71 No 1 0.6 15€mVpp ∼â•2› 9 CMOS 0.35€µm 3.3 2.13 1â•∼› â•1› 0 No 10 27.5 0.3% 30 a Power consumption due to output buffer PD2 CMOS 0.35€µm 3.3 2.49 1â•∼› â•1› 0 Yes 3.3 0.4 0.3% 22 PD3 CMOS 0.35€µm 1.8 0.864 100 No 3 0.25 – >â•2› 1 PD4 SiGe BiCMOS 2.5 0.55 0.3â•∼› â•2› 0 Yes 3.5 1 – >â•2› 0 PD5 CMOS 0.35€µm 3.3 2.98 + 1.37a 1â•∼› â•1› 0 Yes 3.3 0.4 0.3% 42 77 3.2â•…Peak Detectors 78 3â•… Basic AGC Cells for wireless LAN applications as will be shown in Chap.€4 for some of them. A wide range of performance frequencies has been considered, from 0.3 to 100€MHz. High linearity detectors have also been obtained, always above 20€dB, which is appropriate for feedforward AGC configuration. Moreover, new fast-settling configurations have been presented, which achieve very low release time and ripple at the same time, so a theoretical trade-off of these circuits has been overcome. Finally, the validity of one of the proposed topologies in a SiGe BiCMOS technology has been verified, so the range of applications has been extended to this technology market. 3.3â•…Control Voltage Generation Circuit The control voltage generator must take the output signal from the peak detector and after comparing it with a reference signal, generate the control signal VC required to adjust the gain in the VGA. The way it was explained in Sect.€2.1, multiple choices exist to generate this control signal. Furthermore, feedforward and feedback AGCs require different solutions, the feedback loop being more restrictive in the VC generation function required, while in the feedforward loop, accuracy is mandatory. Therefore, the main objective of this circuit is to generate a signal function of a reference voltage VREF and the input (or output) amplitude, depending on which loop topology is employed), such as  VC = f (AIN/OUT , VREF ), so  AOUT = g(AIN , VC ) = g(AIN , f (AIN/OUT , VREF )) ≈ constant, (3.29) (3.30) where f and g functions correspond to the VC generator block and VGA block respectively. As indicated in (3.29) and (3.30), functions f and g are correlated and thus, a different solution, f, will be required for each different VGA function g, so AOUT is constant. In this section, first, two main groups will be differentiated, namely digital and analog VC generators corresponding each one to one of the VGA main topologies: (i) programmable gain amplifiers and (ii) continuously variable gain amplifiers. In both digital and analog subsections, different solutions will be offered. 3.3.1  Digital Control Digital control approach groups mainly two options. First topology is that where the AGC loop is fully implemented inside the DSP [54]. This option requires a different type of work completely oriented to digital designers, so it will not be gone into here as we understand it is beyond the aims of this book. The second option, 3.3â•…Control Voltage Generation Circuit 79 Fig. 3.55↜渀 Comparator bank cell employed in [57] Vref +VCM Vpeak + a0 Comp ¯ + a1 Comp ¯ + a2 Comp ¯ VCM however, takes the output of the peak detector and, making use of a simple digital block, generates the digital word required to manage the PGA [55]. Thus, the latter option inside mixed-signal design is considered in this book. Many different digital solutions are available to control more or less efficiently the PGA gain. However, usually PGAs of 10–20€dB gain range per stage are enough in wireless applications and 2–3€dB gain steps are also acceptable. Therefore, the most common solution is a simple comparator bank ADC [56, 57], as shown in Fig.€3.55. 3.3.2  Analog Control Analog control is much more complicated to implement than digital. However, some applications require smooth gain variation and thus, analog solutions can provide the key. The main solutions are those analytically presented in Sect.€2.1. Since, for each VGA case employed a different analog control is required and it is not possible to offer an implementation of all the possibilities in this work. However, several solutions will be considered which could fit the VGAs presented in Sect.€3.1. Then, the generalization will be analytically explained in Sect.€2.1. VGA1 is fully programmable and in spite of it being possible to obtain a continuous gain variation using active resistors, the gain dependency would again be linear in the best case, so it offers nothing new. VGA2 is the one which offers more control options, already presented in Sect.€3.1, due to its linear dependency of gain with the control voltage. Finally, VGA3, which proposes a mixed, analog/digital, gain adjustment, presents a complex gain variation response to its control voltage, which could be considered linear at first order. Thus, VGA2 is the best candidate of 80 3â•… Basic AGC Cells all to make a study of different linear VC generation circuits for both feedforward and feedback. Other options exist in the literature, the most common being the linear in dB VGA. However, VGA2 can also be employed as a linear-in-dB VGA just by introducing an exponential block to generate VC and considering the input to this block the real control voltage. Finally, VGAs with general gain functions can also be considered [58, 59], but these cases require the generation of the opposite function, which usually involves another feedback loop inside the AGC loop. In feedback AGCs the use of another internal loop can greatly complicate the stability of the system or force making a considerable reduction in the bandwidth of the feedback loop in order to make it much slower than the internal loop. This goes against the aims of this book of studying AGCs with a fast convergence. Alternatively, in feedforward AGCs the introduction of a new feedback loop in the AGC loop does not cause more stability complications than those inherent to the loop itself. However, it does go against obtaining a fast convergence. Thus, the use of these general gain function VGAs has also been ruled out. The control voltage required by VGA2 to accomplish (3.30), is simply:  vC = k Vr ef Vpd . (3.31) where k is a constant, Vref is the desired output voltage and Vpd is the signal provided by the peak detector. The most common analog control voltage generation circuit is based on the exponential solution used to obtain a time-constant independent of bias signals in feedback loop AGCs. In these loops, it is the option of employing the exponential converter at the end of the loop alone or with a logarithmic converter just after the peak detector. The generation of both converters is feasible in BiCMOS technology due to the exponential behaviour of the bipolar transistors. However, in CMOS technology this task is much harder, since transistors present a quadratic current response (characteristics of both technologies are exposed in Appendix D). Several solutions exist in the literature for the CMOS exp-converter [60–64] or exponential VGAs [65, 66] employing pseudo-exponential functions that make the task easier. On the other hand, there are no simple solutions for the log-converter. Thus, for the latter case the need is to make use of a piece-wise linear approximation to the logarithm function, see Fig.€3.56. As explained in [67], this method consists of using many small linear functions combined together to approximate the logarithmic function. Another option is to try implementing it by using previously mentioned exponential solutions in a feedback loop as shown in Fig.€3.57. The logarithm function in the latter case is approximated when amplifier gain, A0, is much bigger than one only. From Fig.€ 3.57 we have: zâ• ›= â•A› 0(âx†œ â•›â•−› â•›â•y› ), yâ• ›= â•e› z. As mentioned if A0â•>› >â•1› , xâ•›â•≈› â•›â•y› , xâ•›â•≈› â•›â•e› z, and consequently zâ•›â•≈› â•›â•l› og(âx†œ ). Both cases cause complications in the AGC loop so in feedback loop the approach is usually preferable where a log-converter is avoided. Unfortunately, feedforward loop has no possibility of avoiding the use of the log-converter without accepting the loss of accuracy, since the relation between 3.3â•…Control Voltage Generation Circuit Vpd 81 Lim(Vout) Log(Vpd) Fig. 3.56↜渀 Piece-wise linear approximation based logarithmic amplifier Fig. 3.57↜渀 Circuit to implement inverse of exponential function Vpd + x Amp y ¯ Exp Log(Vpd) z the control voltage function and the VGA gain function must be exact. Thus, it is mandatory to generate a circuit with a logarithmic response, employing one of the solutions proposed in Figs€3.56 and 3.57. The latter solution would be preferable for small input dynamic range AGCs, while piece-wise linear approximation is a better option for a higher dynamic range. Apart from the exponential VC generator, feedforward AGC´s accept another straightforward solution. To achieve output amplitude as shown in (3.31), when using a linear multiplier, the logical solution would be to use a divider. Even if the implementation of an accurate divider in both CMOS and BiCMOS technologies can be as laborious as implementing an exponential circuit, when small dynamic range is required, simple dividers based on MOS transistors operating in triode region, as shown in Fig.€3.58, can be an acceptable solution. In this case, M2 operates in triode region so  Vout ≈ I0 K(VX − , VT H ) (3.32) where K and VTH are M2 transistor transconductance constant and threshold voltage, respectively. Thus, a division relation is obtained between the two inputs, I0 and VXâ•.› Dividers based on this simple technique can be found in several works in the lit- erature and they have been employed in the implementation of pseudo-exponential circuits [64] for example. Higher accuracy and dynamic range can be obtained em- 82 Fig. 3.58↜渀 Simple divider 3â•… Basic AGC Cells 9'' 0 0 , , 9RXW 9; 0 *1' ploying more complex circuits; however, the study of this possible solution is left for future work. 3.3.3  Conclusions In conclusion, each VGA can require a different solution, although, for example in feedback AGCs, the same exponential type solution is preferred among designers in the end, while in feedforward AGCs, PGAs and digital control are usually employed. The next chapter introduces some proposals of control voltage generators explained in this section in general terms as part of the full AGCs proposed in the book. References 1. C. Toumazou, F. J. Lidgey, and D. G. Haigh, Eds.; “Analogue IC Design: The Current-Mode Approach”; London: Peregrinus, 1990. 2. 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Fox, B.A. Myers; “Analog AGC Circuitry for a CMOS WLAN Receiver”; Solid-State Circuits, IEEE Journal of; Vol. 41, Issue 10, pp. 2291–2300, Oct. 2006. 60. Weihsing Liu, Shen-Iuan Liu and Shui-Ken Wei; “CMOS Differential-Mode Exponential Voltage-To-Current Converter”; Analog Integrated Circuits and Signal Processing; Vol. 45, Issue 2, pp. 163–168, Nov. 2005. 61. Weihsing Liu and Shen-Iuan Liu; “CMOS exponential function generator”; Electronics Letters; Vol. 39, Issue: 1, pp. 1–2, Jan. 2003. 62. A. Motamed, C. Hwang and M. Ismail; “CMOS exponential current-to-voltage converter”; Electronics Letters; Vol. 33, Issue: 12, pp. 998–1000, Jun. 1997. 63. Cheng-Chieh Chang and Shen-Iuan Liu; “Current-mode pseudo-exponential circuit with tunable input range”; Electronics Letters; Vol. 36, Issue: 16, pp. 1335–1336, Aug. 2000. 64. Q.-H. Duong, V. Krizhanovskii, H.-C. Choi, S.-J. Yun, M.-S. Yang and S.-G. Lee; “Lowvoltage, high dB-linear, exponential V-V converter”; Electronics Letters; Vol. 40, Issue: 17, pp. 1032–1034, Aug. 2004. 65. W. Liu, S.-I. Liu and S.-K. Wei; “CMOS exponential-control variable gain amplifiers”; Circuits, Devices and Systems, IEE Proceedings; Vol. 151, Issue: 2, pp. 83–86, Apr. 2004. 86 3â•… Basic AGC Cells 66. Q.-H. Duong, T.-J. Park, E.-J. Kim, and Sang-Gug Lee; “An All CMOS 743MHz Variable Gain Amplifier for UWB Systems”; Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on; 2006. 67. B. Gilbert; “Limiting-Logarithmic Amplifiers”; Electronics Laboratories Advanced Engineering Course on RF IC Design for Wireless Communication Systems; Lausanne, Switzerland, Jul. 1995. Chapter 4 AGC Systems Chapter€4 presents the final AGC circuits achieved as a result of the study and the blocks implementation carried in previous chapters. In total three novel AGC circuits are proposed. First is a CMOS feedforward digital AGC loop, AGC1. It is targeted for WLAN applications and its main strong points are its compactness and simplicity, together with its fast convergence time. The second AGC, AGC2, looks into the advantages of SiGe BiCMOS technology and offers solutions to an existing standard. Thus, a full AGC architecture is implemented to be integrated as a block of an IEEE 802.11a WLAN receiver. In this case a specific application is pursued, the main objective being to fulfil the standard requirements with a robust proposal offering minimum area and power consumption. The last AGC, AGC3, is designed to complete this chapter with a circuit capable of working at very high frequencies. The interesting field of the mixed loop AGC is also analyzed and novel unconventional level detection methods are proposed. Finally, at the end of the chapter conclusions are drawn and an interesting comparison is offered between the proposed AGC circuits and some other architectures already proposed in the literature. 4.1â•…CMOS Feedforward Digital AGC Circuit In applications such as WLAN or Bluetooth receivers, timing constraints preclude the use of closed-loop AGC schemes. Meanwhile, novel feedforward and open loop gain control techniques have proven to be adequate to shorten the settling time and reduce the acquisition time of AGCs [1–3]. Therefore, an automatic gain control circuit based on a feedforward approach to achieve very fast convergence will be presented in this section. It consists of a digitally programmable gain amplifier, a peak detector and a 4-bit flash ADC using thermometer code, offering low-voltage (1.8€V) low-power operation (1.6€mW), low-distortion (<â•›â•−› 70€dB IM3) and an inherent rapid convergence of the amplifier gain (attack-time <â•4› 0€ns and settling-time J. P. Alegre Pérez et al., Automatic Gain Control, Analog Circuits and Signal Processing, 87 DOI 10.1007/978-1-4614-0167-4_4, ©Â€Springer Science+Business Media, LLC 2011 88 IF 71MHz Vin Mixer RMS 0/21/42 dB Preamp VCO Switched Gain Control Fig. 4.1↜渀 IF 71€MHz strip 4â•… AGC Systems Channel Filter This work Peak Detector 0 to 21 dB PGA Vout D Comparator Bank Vref <â•2› 50€ns). First, the proposed AGC architecture and the circuit design of the key function blocks will be described. After that, main measured and simulated performances are summarized. 4.1.1  System Architecture The automatic gain control described in this section is the last stage of the complete IF AGC shown in Fig.€4.1. The full background AGC would consist of two coarse fixed-gain preamplifiers, controlled by simple pass-switches, with a digitally programmable gain amplifier (PGA) at the end which allows final fine gain adjustment [4]. With this common gain distribution architecture, the total input range variation at the last stage can not exceed the gain of one of the previous amplifiers: establishing Voutâ• ›= â•0› .4 Vp-p as a typical output voltage and by using preamplifiers of 21€dB as depicted in Fig.€4.1, the expected input dynamic range extends from −â•2› 5 to −â•4› €dBm (21€dBm). This range is small enough to relax the design specifications of the peak detector. To reach the desired constant output amplitude a peak detector (PD) extracts the signal amplitude at the input of the PGA, as shown in Fig.€ 4.1. This signal amplitude is then introduced in a simple comparator array –like a flash ADC– that directly generates the digital word to control the PGA gain. The circuit description and implementation of these main blocks which constitute the proposed AGC, that is, the digitally programmable gain amplifier, the peak detector and a 4-bit comparator bank, are described in the following. Programmable Gain Amplifier╇ The complete PGA scheme, specifying transistor sizes and biasing conditions, is shown in Fig.€4.2. It is based on the VGA1 scheme analyzed in Sect.€3.1, so for detailed information refer to this Section. The core circuitry consists of a very simple negative feedback gm-boosted differential pair with output resistive loads and a switchable array of source degenerating hybrid polysilicon-MOS resistors. In this design an additional gain programmability degree of freedom is provided at the output current mirrors implemented 4.1â•… CMOS Feedforward Digital AGC Circuit 89 9 P$ 5/ N: P$ P$ N: 5/ 0  P$ 9RXW P$ P$ 9&0    YLQ 0  D D 0 9&0 5 91 0¶ 0¶ 0 0     9R±XW 0 9&0 Ā   YLQ P$ P$ P$ 9&0 0 0 0 0¶ D D 0¶ 91 5 D :/ D :/  :/ D  :/  :/  :/ Fig. 4.2↜渀 Programmable gain amplifier cell through M2-M3 by adding one identical output stage in parallel, with the M3 cascode transistors acting as the switching elements [5]. Thus, the PGA total differential gain is equal to:  Gain = Kα RL , (4.1) R where K is the current mirror gain  K = (W/L)3 , (W /L)2 (4.2) R denotes one-half the degeneration resistance and α = gm1/(gm1+gmb1) the M1 gateto-source DC voltage gain. The cell, designed in a 0.35€µm CMOS process, is supplied with a single voltage of 1.8€V and the bias current value has been fixed to 40€µA. Biasing currents have been implemented through cascode configurations. HRP load resistors RLâ• ›= â•8› .3€kΩ are selected, which results in an expected intrinsic constant bandwidth in the 100€ MHz range assuming output capacitive loads of 150€ fF modelling the input capacitance of a succeeding cell based on this same topology. The programmable degeneration impedance consists of a 3-bit array [a2 a1 a0] of hybrid HRP-NMOS resistors in parallel, binary weighted to obtain a logarithmic gain distribution ranging from 0 to 18€dB in 6€dB steps through a thermometer code control. A fourth bit a3 allows the output current mirror gain K to be set either at 90 D D 9SHDN  &RPS Ā 9UHI D 9UHI9&0 9UHI9&0 9SHDN D D 9D 9UHI 9UHI 9E D D D 9UHI 9F D D D 9UHI 9G 9UHI 9UHI 9&0 9&0 Fig. 4.3↜渀 Comparator bank cell 4â•… AGC Systems  &RPS D D Ā  &RPS D D Ā  &RPS D D Ā 1 or 1.5. This enables scaling each 6€dB step, so that the scheme covers an overall 021€dB gain programmability range, in 3€dB steps, by a 4-bit discrete coarse tuning. Fine gain tuning can be performed if necessary through slight gate voltage variations for the switching transistors in order to improve accuracy. To generate a suitable common-mode output voltage, equal to that of the input (âV†œ CMâ• ›= â•1› .3€V), an additional current source, controlled through the complementary of a3, is introduced. In this way, when the output current mirror gain Kâ• ›= â•1› , the current source switches on, while when Kâ• ›= â•1› .5 it switches off, enabling the output DC current and common mode voltage to be kept constant. Peak Detector╇ The peak detector structure is the same differential positive scheme presented in Sect.€3.2 as PD3, where a unidirectional current mirror is employed together with a transconductor to implement the rectifier circuit [6]. A high performance Gm-cell is employed. In this way, with a very compact design, the peak detector exhibits higher linearity at higher frequencies with lower power consumption. One detector is employed for each balanced signal, adding both signals at a single output. Gain Computation Block╇ The output of the envelope detector is carried to a comparator bank (simple differential pairs) where it is compared to a reference level Vref, as shown in Fig.€ 4.3. In order to take into account any change in the input common-mode level VCM, and since the peak detector is not balanced, the reference level is generated with respect to VCM. The first 3€bits [a2 a1 a0] that control the degeneration resistance providing the logarithmic gain distribution ranging from 0 to 18€dB in 6€dB steps are obtained simply by comparing the detected amplitude to the reference voltages Vref0, Vref1, Vref2 derived from a resistor ladder. The 4th bit a3, that allows the 3€dB step gain resolution through the control of the output current mirror, is generated by using a single comparator which contrasts the detected amplitude to a reference voltage Vref3 obtained by using simple logic (see Fig.€4.3). 4.1â•… CMOS Feedforward Digital AGC Circuit 91 Fig. 4.4↜渀 AGC1 chip photograph PP 3' 9*$ &RPSV &RPSV%XIIHUV $*& %XIIHUV PP   Va , if a0 = 1  Vref 3 =    Vb, Vc, if if AND(a1, a0) = 1 AND(a2, a1, a0) = 1 (4.3)   Vd , if AND(a2, a1, a0) = 1. That is, Vref3 equals one of the reference voltages Va, Vb, Vc or Vd depending on the value of the first three bits. For example, should Vpeak be between Vref0 and Vref1, the corresponding digital word would be [0 0 1] and following (4.5), the comparison reference voltage Vref3 to generate a3 would be equal to Va. Two different resistor banks are employed to avoid undesired feedback which would spoil the perfor- mance of the circuit. 4.1.2  Performances The aforementioned proposed AGC has been simulated using SPECTRE with a BSIM3v3.2 level 53 transistor model and designed in AMS 0.35€µm CMOS technology. The chip photograph is shown in Fig.€4.4. The overall circuit comprising the digitally programmable gain amplifier, the peak detector and the 4-bit comparator bank consumes 1.6€mW from a single 1.8€V supply voltage: 0.504€mW the PGA, 0.86€mW the peak detector and 0.23€mW the gain control block. Through a 4-bit thermometer code control, the gain can be varied linearly in dB from 0 to 21€dB in 3€dB steps. The frequency response of the main gain settings is shown in Fig.€4.5; the −â•3› €dB bandwidth, as expected, is kept constant around 100€MHz over the whole gain range. The total harmonic distortion (THD) for sinusoidal input signals at 71€MHz is shown in Fig.€4.6 considering constant differential output levels. Figures are below 92 Fig. 4.5↜渀 Measured PGA fre- quency response: solid line, Kâ• ›= â•1› ; dashed line, Kâ• ›= â•1› .5 24 18 ‘111’ 12 ‘011’ Gain (dB) 6 ‘001’ 0 ‘000’ –6 –12 –18 106 Fig. 4.6↜渀 Simulated THD ± levels at 71€MHz for the main G% gain settings versus output G% voltage Vout ± G% G% ± 4â•… AGC Systems 107 108 109 Frequency (Hz) 7+'#0+] G% ± ± ±       9RXWSS 9 −â•6› 8€ dB over all the gain setting range with a differential output signal level of 0.2€Vp-p, a value that increases to −â•5› 8€dB for 0.4€Vp-p. Measured input-output performance with sinusoidal inputs for the implemented envelope detector is given in Fig.€4.7. It is found that deviations from ideal behaviour are below ±â•0› .5€dB for all the input range. Therefore, although the accuracy for the AGC employed in this work is 3€dB with 4€bits, if necessary it can be increased up to 1€dB by raising the bit resolution. The convergence of the AGC is tested in the worst case condition: introducing a 21€dB stepwise signal, which is the maximum change that the AGC can observe due to the switching of one of the fixed gain amplifiers just before the PGA. To measure the attack-time, the input signal is increased by 21€dB, and the AGC converges in less than 40€ns. At the same time, to measure the settling-time the input signal is reduced. The results for the latter are shown in Fig.€ 4.8. Simulated convergence time is around 0.25€µs, while readings show a result of around 0.3€µs. Thus, after measurements, the circuit still keeps a fast convergence response. 4.2â•…SiGe BiCMOS Analog AGC Circuit 93 Fig. 4.7↜渀 Measured inputoutput linearity of the peak detector 9RXWSG P9              0HDVXUHG ,GHDO           9LQ P9 Fig. 4.8↜渀 Measured peak  detector convergence 3'RXWSXW response for a 21€dB abrupt stepwise change  $*&LQSXW  $PSOLWXGH 9           W V [± Total convergence is also checked by simulations for the full AGC in Fig.€4.9. The AGC adjusts signals to the desired output level (0.4€ Vp-p) in no more than 0.25€µs: since the AGC has a feedforward loop, the settling time required by the AGC is equal to that required by the envelope detector. The same can be expected for measurement results, where total convergence should be also around 0.3€µs. 4.2â•…SiGe BiCMOS Analog AGC Circuit In wireless local-area network (WLAN) receivers one of the accepted standards is the so called “IEEE 802.11a standard”. This standard uses orthogonal frequency division multiplexing (OFDM) to allow high data rates in multipath WLAN environments. As it is known, in the IEEE 802.11a WLAN protocol, received data consists of a preamble, header and data segments. The receiver estimates the characteristics 94 Fig. 4.9↜渀 Simulated worst case AGC output Vout (V) 4â•… AGC Systems 0.3 0.2 0.1 0 ¯0.1 ¯0.2 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 t (us) for each channel during the reception of the preamble. Once fixed, these characteristics must remain constant for the whole packet reception, which lasts up to 1€ms. The preamble consists of 10 short training symbols of 0.8€μs each and 2 long training symbols of 4€μs each, which are composed of a predefined data stream [7]. These stringent time constraints preclude the use of conventional AGC schemes using a closed-loop feedback technique to settle the desired output signal amplitude [8]. As an alternative, a so-called open-loop AGC algorithm has recently been proposed [1], obtaining convergence in less than 5.6€µs. However, a quicker solution would be to employ a feedforward AGC architecture. In this section, the feasibility of this latter solution is validated through the implementation of a feedforward analog AGC circuit embedded in an IEEE 802.11a 5-GHz WLAN receiver that has a fast convergence (3.2€µs), while offering a good trade-off between the main characteristics: a gain range from 15 to 69€dB with an accuracy of ±â•1› €dB, a 9.7€dB noise figure and a total power consumption of 13.75€mW. An analog solution is adopted to reduce power consumption, allowing the DSP to sleep most of the time. The overall WLAN receiver is implemented through a direct conversion topology as its simplicity and benefits outweigh drawbacks such as DC-offset sensitivity [9]. To obtain a fully integrated system, a low-cost 0.25€μm 75€GHz SiGe BiCMOS process is used for the whole receiver and consequently for the AGC shown here. Next, the complete AGC system is presented. After that, the design and implementation of the different cells are explained. Finally, results and a summary of main characteristics are given. 4.2.1  System Architecture Figure€ 4.10 shows the proposed feedforward baseband AGC block. The required AGC design specifications in the WLAN receiver are: output voltage of 4.2â•…SiGe BiCMOS Analog AGC Circuit 6ZLWFKHG*DLQ&RQWURO *DLQ G% 9UHI ±G% %3) /1$ 3' G% 9LQ 9*$ ±G% G% 9&2 &RDUVHJDLQ 9*$$DQG9*$ G% ELW 3' FON $ G% IL[HG )LOWHU 9*$ %XIIHU G% G% ELW *P&ILOWHU 2IIVHW &DQFHOODWLRQ )LQH*DLQ&RQWURO *DLQ WRG% 9SG 3' 9& 9LQ 9RXW 9*$ WRG% FRQWLQXRXV 9'' 9'' 5/ 5/ ,2± % 9UHI /RJ 9SG /RJ  9& ([S ± 9&JHQHUDWLRQFLUFXLW )LQHJDLQ 9*$ % ,2 9RXW± 9LQ± 9LQ 9RXW 9RXW± 9LQ± $Ā 9LQ 5( , , % 9& 9&± ,UHI 9LQ 9& $ , , 9LQ± 9&± 9RXW % &F &F :/$1DUHFHLYHUVKRZLQJWKHDUFKLWHFWXUHRIWKHSURSRVHGEDVHEDQGIHHGIRUZDUG$*& LQJUH\ DQGGHWDLOHGVFKHPHVRIWKH 9*$VWDJHVIRU9*$5( IRU$DQG9*$5(≠ Fig. 4.10↜渀 Complete AGC architecture 95 96 4â•… AGC Systems 500€mVp-p,diff, noise figure below 10€dB, −â•3› €dB gain bandwidth from 100€kHz to 20€MHz, settling-time below 8€μs and a 54€dB overall gain with ±â•1› €dB accuracy, ranging from 15 to 69€dB. The main setback of relying on a feedforward technique is that the peak detectors used to set the gain require higher input dynamic range. As a trade-off between power consumption and complexity, the total amplifier gain is split into three 18€dB stages, thus limiting to 18€dB the maximum input dynamic range for each peak detector. The AGC operates in three phases: two 0/18€ dB switched coarse gain-setting phases, followed by a final 0 to 18€dB fine gain-setting phase. A fast settling chan- nel filter is embedded between the second and third VGA stages [1, 10]. The first coarse-gain stage VGA1 switches from 0 to 18€dB when the input signal Vin drops below −â•3› 2€dBm, during the first short training symbol time (tâ• ›= â•0› –0.8€μs). Simi- larly, the second coarse- gain stage VGA2 sets its gain to 0 or 18€ dB during the second short training symbol (tâ• ›= â•0› .8–1.6€μs) and it is switched on when Vin is below −â•5› 0€dBm. Finally, the last stage VGA3 provides fine-gain variation from 0 to 18€dB and its settling time is determined by the peak detector PD3 response, which requires two short training symbols to converge. As shown in the scheme, a further stage A with a 15€dB fixed gain is required to fit the targeted specifications, but this does not take part in the gain settling process. Therefore, the AGC shows an overall 15–69€dB gain range and settles to ±1€dB in 3.2€μs. The DC offset cancellation circuit consists of a Gm-C filter with two external capacitors of 500€nF. The different blocks shown in Fig.€4.10 which constitute the proposed AGC will be discussed next. All circuits were designed with fully differential circuitry. 4.2.1.1â•… Coarse Gain The coarse gain block, provides a 15/33/51€dB controllable gain through VGA1–2 and a 15€dB fixed gain amplifier A. The input stage VGA1 is implemented by a simple BJT differential pair with load resistors to keep a low noise figure. The following stages, A and VGA2, are both implemented by resistively-loaded BJT differential pairs with emitter degeneration resistances to increase the linear range for large input signals. Each VGA is managed by a 1-bit control circuit that completely switches on/off the corresponding amplifier depending on the input voltage level. The control circuit consists of a peak detector PD1(2), followed by a simple op-amp comparator and a D flip-flop, which stores the bit once the decision is taken. The structure of the peak detectors PD1,2 is based on the same principle as for PD3, which will be explained later on, but with relaxed requirements as precision for the coarse setting is not so critical. 4.2.1.2â•… Fine Gain The final AGC stage VGA3 must provide a 0–18€dB fine gain tuning by means of a continuous control voltage VC. The cells included in this block are VGA3, peak detector and VC generation circuit. 4.2â•…SiGe BiCMOS Analog AGC Circuit 97 VGA3 Architecture╇ The detailed VGA3 schematic is shown in Fig.€4.10. It is an improved BiCMOS version of the VGA2 in Sect.€ 3.1: a pseudo-differential BJT pair topology with common-mode feedforward cancellation to achieve high CMRR [6] and a negative feedback loop to increase linearity and reduce power consumption. Fully differential input signals Vin±â• ›= â•V› CM,in╱› â•v› in/2 are applied to bipolar transistors operating in the active region, while control voltages VC±â• ›= â•V› CM,C╱› â•V› C drive the gate of emitter-degeneration NMOS transistors operating in the triode region. The negative feedback path, shown in dashed lines, allows keeping constant the common-mode current transmitted through the output mirrors, while the current surplus over the whole gain range is driven through a feedback-controlled transis- tor. In consequence, since not all the common-mode current is transmitted, power consumption reduction is achieved. Furthermore, using this technique, DC-voltage variations in nodes A± are moderated and therefore linearity is improved. After a non trivial routine circuit analysis [11], the output differential current can be approximated by  IO = IO+ − IO− = B(I1 + I2) − B(I3 + I4) ≈ 4BK0VCvin, (4.4) where B is the gain in the current mirror, fixed to 2, and K0 is a constant which depends on the transistors’ intrinsic parameters. The output current in (4.6) is converted to voltage through floating output resistive loads RLâ• ›= â•5› €kΩ implemented with a high resistivity poly-silicon layer. Therefore, the differential control voltage VC needed to obtain the desired output amplitude vOâ• ›= â•V› ref independently of vin can be expressed as:  VC = k Vref Vpd , (4.5) where k is a constant and Vpd is the signal provided by the peak detector. This cell consumes a total current of 0.5€mA and can offer a continuous linear gain from −â•3› to 21€dB with an accuracy of ±1€dB. Since only 18€dB gain variation is required, this ±3€dB gain excess can be employed to fix possible process variations. Peak Detector╇ The design of the peak detector is important because, as the AGC makes use of a feedforward loop, the total settling time of VGA3 is principally due to the settling time of the peak detector. The peak detector shown here is based on that introduced in Sect.€3.2 as PD4. Consequently, a summary only is given here but for further details, the full explanation can be found in Chap.€3. The basic cell is the same differential positive peak detector employed in PD3 and PD4. One cell is employed to detect the positive peak of each balanced signal, V1±, and the mean value of both peaks is transmitted to the output, see Fig.€4.11. The detector makes use of switches, S1-4 to obtain a track and hold behaviour so that small load capacitances can be employed. The switches are managed by a digital control signal generated by a few D flip-flops and logic gates from a single 5€MHz clock. The switches split the performance of the circuit into three different periods: “tracking”, “hold” and “discharge”, which all together require two symbols. During “tracking” all switches S1-4 are “off” and the load capacitor is charged with the first 98 4â•… AGC Systems VDD S1 S2 V1+ V1– CL IL CL S3 Vph S4 Fig. 4.11↜渀 Schematic of the peak detector symbol. At the beginning of the second symbol, “hold” period starts and S3,4 are closed so that the peak detected during the first symbol is transmitted to the output. Finally, S1,2 are closed and S3,4 are opened, so that the rest of the second symbol is employed to discharge the load capacitor, CL, through current IL. This performance is successively repeated during the following symbols. In order to double the peak detector speed, a second peak detector like the one in Fig.€4.11 works in parallel, starting the “tracking” during the second symbol, and “holding” and “discharging” during the third symbol. Thus, there is one circuit to detect the peak of odd symbols and the second one for even symbols, similar to that proposed in [12]. Control Voltage Generation Circuit╇ Once the strength of the input signal is measured, the circuitry to generate the required VC control voltage can be implemented either by a divider or by using the log-domain approach. Since we are employing BiCMOS technology and, log-amplifiers can easily be implemented making use of the direct translinearity of BJT, the latter choice is preferred in this case. Furthermore, since the loop operation frequency is low and a moderate dynamic range is required, it is possible to employ simple translinear cells to implement log and exp-amplifiers [13]. Separately, the performance of these cells is very dependent on process, voltage and temperature (PVT) variations. However, when they are employed in series as shown in Fig.€4.10, the expression in (4.7) is achieved with PVT cancelled to the first order of approximation. Following the exp-amplifier, a conventional buffer stage is employed to generate the required VC±â• ›= â•V› CM,C╱› â•V› C control voltages. This buffer is also used to connect the circuit with an external capacitor which stores the control voltage, VC, after the preamble signal. 4.2.2  Performances Like the receiver, the complete AGC has been designed, in a low-cost 0.25€ μm 75€GHz SiGe BiCMOS process. It employs a single supply voltage of 2.5€V and has 4.2â•…SiGe BiCMOS Analog AGC Circuit 99 Fig. 4.12↜渀 Die photo of the full AGC PP Fig. 4.13↜渀 Measurement testbench PCB PP PP PP PP PP PP a total current consumption of 5.5€mA for all the grey shadowed blocks in Fig.€4.10. The photograph of the integrated AGC is shown in Fig.€4.12. Employed PCB for the measurement test-bench is shown in Fig.€4.13. The frequency response is given in Fig.€4.14 for several VGA3 gain settings, but with VGA1 and VGA2 disconnected. The low frequency response is controlled by DC-offset cancellation circuit. The bandwidth is constant for all the gain settings. The peak detector performance is given in Fig.€4.15, while the control voltage versus detected amplitude is shown in Fig.€4.16. Peak detector settling-time was measured with a 20€MHz sinusoidal wave modulated with a 400€kHz square signal. As shown in Fig.€4.17, convergence is achieved in three clock cycles, consistent with the required three short symbols to settle the AGC. The convergence of the post-filter AGC for an OFDM signal was simulated using SPECTRE due to the lack of instrumentation to generate this kind of modulation. The result for the worst case, high gain adjustment from low input level, is 100 Fig. 4.14↜渀 Frequency response of the full VGA for several VC with fixed amplifiers VGA1 and VGA2 switched off (âb†œ lack) and for VCâ• ›= â•1› 20€mV with VGA1 “on” (âg†œ rey). Results are the mean value of 100 measurements Fig. 4.15↜渀 Input-output linearity for the peak detector Fig. 4.16↜渀 Control voltage (âV†œ C,diffâ•)› versus peak detector output Vpd 9F P9 Vpd (mV) *DLQ G%           4â•… AGC Systems 9*$RQ9F P9 9F P9 9F P9 9F P9 9F P9     )UHTXHQF\ +] 140 Measured data 120 Fitting y = 0.68*x - 1.6 100 80 60 40 20 0 0 50 100 150 200 Vin (mV)            )LWWLQJI [ H [ 0HDVXUHG   9SG P9    4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit 101 Fig. 4.17↜渀 Measured peak detector settling-time with a 20€MHz sinusoidal wave modulated with a 400€kHz square signal Signals (V) 0.1 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.1 –0.12 –0.14 –0.16 –0.18 –0.2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 t (s) x 10¯6 Fig. 4.18↜渀 Simulated AGC output signal, Vout, with an OFDM input signal for highest gain adjustment (18€dB) from lowest input level Vout (V) 1.6 t1 t2 t3 t4 Initial gain 1.5 0 dB 1.4 1.3 1.2 1.1 1 0 0.8 1.6 2.4 3.2 t (us) shown in Fig.€4.18. Initializing VGA3 gain in 0€dB, the fine gain circuit makes use of symbols t1 and t2, so the gain is already adjusted to ±â•1› €dB in t3. Since the coarse gain stage requires 1.6€μs to set the gain, the total settling time is 3.2€μs. This time is well below the standard preamble time, 8€μs, so the rest of the preamble time is available to the digital signal processor (DSP). 4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit In Sect.€ 4.1, a feedforward digital AGC loop for 71€ MHz applications has been proposed. In Sect.€4.2, a feedforward analog AGC loop for OFDM modulation at frequencies up to 20€MHz was analyzed. To finish this chapter, we propose a very high frequency (VHF) AGC, an AGC which is suitable for IF frequencies up to 250€MHz. 102 4â•… AGC Systems As for the gain control approach, if high compression ratios are used, feedback AGCs can exhibit instabilities. Alternatively, the use of a feedforward loop can relax the compression ratio of the feedback loop [14]. In addition, the use of a digital control loop makes the output signal compression easy for high compression ratios. However, in feedback topologies, sudden steep rise in gain can reduce the stability margin. A solution is to increase the feedback loop time constant, slowing down the AGC response. Instead, digital control can be used in the feedforward loop drastically reducing the target time constant. Therefore, a combined feedforward/feedback AGC loop is chosen to take advantage of both control characteristics: high compression ratio and fast settling-time for the feedforward loop and accuracy for the feedback loop. This AGC is therefore suitable for applications such as terrestrial microwave equipment where 250€MHz IF frequency is common or television receivers where IF is between 30 and 900€MHz. Such mixed architecture however has already been proposed in the literature [15, 16], where a circuit with advantages of both loops is obtained. So the novelty of the circuit is not in the architecture, but in a couple of blocks employed in both loops. Feedforward loop includes an almost completely digital structure where the level detection is made not by a conventional peak detector, but by comparators, whereas feedback loop also employs an unconventional peak detector with an interesting response function. The system architecture and its different blocks are then described in more detail and simulation and experimental results are offered to finish off. 4.3.1  System Architecture As mentioned above, high frequency AGC is a necessary requirement. Consequently, to achieve this, the foremost characteristic of this circuit lies in simplicity. Apart from system architecture validation, this section also introduces a few novel blocks which will deal with the conventional AGC block functionality from a different angle, focused on circuit simplicity. The proposed combined feedforward/feedback AGC system is shown in Fig.€4.20. The VGA is suitable for low voltage and allows for digital and analog gain control. The gain adjustment is dealt with in two phases: first, a digital feedforward control loop, which tolerates very fast convergence of the amplifier gain, sets the output level as close as possible to the desired output amplitude. A feedback loop is then used to make the fine gain adjustment. Note that for this loop the input signal level varies within a reduced range, equal to the feedforward loop gain step. Therefore, its design can be greatly simplified. The feedforward loop is based on a novel configuration where a peak detector is not required, but keeps the same functionality as that obtained for AGC1. The feedback loop does not use a conventional peak detector, but a simple comparator followed by a charge pump and an integrator. The control voltage generation in this loop is finally accomplished through a simple Gm-C filter. The loop should 4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit 103 be completed with an exponential converter in order to maintain a constant (or almost constant) convergence time; however, this block has not been introduced here. Therefore, feedback loop convergence time will vary according to input signal level. For the feedback loop the input signal level will vary only within a range equal to the minimum feedforward loop gain step. In this case, this is equal to 6€dB. Future work is intended to introduce the exponential block and to check the difference obtained in the convergence time for both cases. To follow, different blocks will now be described. First, a summary of the performance characteristics will be offered of the employed VGA, which was presented in Chap.€3. Then feedforward loop will be analyzed and a novel digital level detection concept will be presented. Finally, feedback loop is described along with another novel level detection concept. Variable Gain Amplifier╇ The VGA within the AGC is the one introduced as VGA3 in Sect.€3.1. Only a brief summary of the circuit will be offered here but further details can be found in Chap.€3. The VGA is based on a new version of the ground referred differential pair, so low-voltage operation over the high frequency range can be achieved. A CMFF cancellation structure has been implemented to this Gm cell. The VGA cell is shown in the upper part of Fig. 4.19.€ The Gm cell consists of an improved voltage follower formed by transistors M1A and M3 that increases the structure equivalent Gm to gm1Aro1Agm3, where the parameters have their usual meaning [17]. According to previous analysis, the output differential current of the VGA is given by  Io1 = −Io2 = I2 − I1 = 2K(VGS − VTH)Vin, (4.6) where VTH and VGS are, respectively, the threshold voltage and the gate-to-source voltage of MB transistors and Kâ• ›= â•(› 1/2)COX(âW†œ /L)B. In order to demonstrate the low-voltage operation, the proposed VGA with common-mode feedforward is biased with a single supply voltage of 1.8€V. The common mode voltage VCM has been set to 1.3€V and the value for the bias current IB fixed at 50€µA. This means that for VGâ• ›= â•V› CMâ• ›= â•1› .3€V, the current I1 (âI†œ 2) through the output transistors will ideally be also equal to 50€µA and the VGA power dissipation is 0.65€mW. For VGâ• ›= â•1› .25, 1.35 and 1.4€V the currents through the output transistors are approximately 25, 75 and 100€µA respectively, and the power consumption varies between 0.55 and 1.1€mW. In order to maintain moderate power consumption, the maximum value for the output current I1 (âI†œ 2) that will be considered is 100€µA. Feedforward Loop╇ The feedforward loop is based on the concept already presented for AGC1: first, input signal level detection is realized; then, this value is compared by simple comparators with reference values; and finally, the digital word required to adjust the gain in the PGA is generated. Though already really simple, the loop from AGC1 can be simplified still further. Instead of employing a peak detector followed by comparators, high speed comparators only are used. Supposing a sinusoidal input signal, when the amplitude 104 VCC M4 VCC Io1 I2 IB I1 VCM + 1 2 vin VG M1B M1A 3-bit M3 M4 I1 M1B 3-bit M4 I2 M2B VG 3-bit VGA3 VCC IB M4 I1 IO2 M2A VCM – 1 vin 2 I2 M2B 3-bit VG VCM M3 VDD M6 M6 M7 M5A M5B Vo2 M5B Vo1 IB M8 C1 R1 Io1 Vo1 RL1,2 Vo2 R2 Io2 Vin Comps Digital Block VGA VC D Loop Filter Fig. 4.19↜渀 AGC3 system schematic (âd†œ own) and VGA3 (âu†œ p) Vout – Comp & Detector Vref + 4â•… AGC Systems 4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit Fig. 4.20↜渀 Block schematic of feedforward loop Vin± Iref1 Iref2 Iref3 Comp Comp Comp 1 Vb1 DQ clk R 1 Vb2 DQ clk R 1 Vb3 Clk DQ clk R DQ clk DQ clk DQ clk 105 3-bit Digital Word is above the reference value a pulse is generated at the comparator output. If this input level is kept constant, as the sinusoidal signal is periodic, the output pulse will become a periodic square signal. So, it is possible to use this square signal as a clock which makes a digital block changing its state from “low” to “high”. This state is also continuously reset with an internal clock, which could, for example, be provided by the DSP. This is not a special requirement as the digital circuitry usually provides a clock signal to the analog block for normal performance. Thus, if the input amplitude drops below the reference value the clock will not be generated and as soon as the digital block is reset, the gain control bit will return to the start value. As one might deduce, the feedforward loop speed is fixed by the internal clock used to reset the digital block. The block schematic of this loop is shown in Fig.€4.20. As what we require is a high frequency application, the comparator must be able to generate a pulse with a frequency equal to the input signal frequency. In this case, 250€MHz range is the target frequency. This means a very high slew rate is required. Two options were considered, the latch comparator [18] and inverter based comparator [19], both of which provide a high slew rate and fast response. The inverter based comparator however, is the simplest circuit and its power consumption in static is almost nil. Thus, it is preferred to the latch comparator, which requires more transistors and has higher power consumption. The main disadvantage of the inverter based comparator is that it is highly sensitive to process variations and so requires calibration at the start up. In this work calibration has been made externally, though it could easily be done internally and controlled by the DSP, which is also a common practice in industrial electronics. The method chosen to calibrate each comparator is to introduce different small fixed currents into the inverter NMOS in order to change the crossover point to the desired value. Then, compared to the input signal common-mode voltage, this crossover point will be equivalent to the reference voltage generated by the string resistor ladder from AGC1. After that, the signal is regenerated by a few more inverters until a square signal is obtained at the 106 VDD 3.2/0.5 Vin+ IRef Vri 2/0.5 Vin¯ VSS Fig. 4.21↜渀 Inverter based comparator schematic 4â•… AGC Systems Vout output when Vin is above the crossover point. Figure€ 4.21 shows the comparator schematic. Note that when the frequency is not so close to the technology limit, the comparator performance can be greatly relaxed, for example in this case for 1–10€MHz applications. Thus, the comparator design can also be greatly simplified and so, the savings of avoiding the use of a peak detector increase. In fact, at lower frequencies, it is possible to use the same comparators as in AGC1, so the previous peak detector is quite unnecessary. At high frequencies, the comparator will be more complex and given that as many comparators are necessary as bits, for many bits, the sum of all the comparators could make it more advisable to use a peak detector first. In this case, only three bits are employed and of course, designing a highly linear peak detector for frequencies up to 250€MHz would be very power hungry, so comparator based level detection is considered a better choice. The generated clock signal is carried on to manage a register. This register consists of two latches in series. The first latch has the input connected to logical “one” as shown in Fig.€4.20. It stores this “one” only when the clock is working and, as it is reset continuously, if the clock is not working, a “zero” will be stored. At its input, the second latch receives the first latch output, but this latch uses the reset signal inverted as a clock. Thus, the signal stored in the first latch before the reset is transmitted to the block output. The reset period is responsible for the feedforward loop speed, so a low period is required to achieve fast convergence. However, the pulse signal generated by comparators must be several times faster than the reset to guarantee that the required digital word will be processed correctly. In this case, one fifth of the input signal frequency was chosen for the reset frequency. In order to use a single power supply in the full AGC circuit, the same 1.8€V power supply is employed as in the VGA. Latches and inverters are those offered by AMS digital standard library. Feedback Loop╇ Continuing with the idea of using comparators only to obtain an approximate idea of the input signal level, the feedback loop employs a comparator 4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit Fig. 4.22↜渀 Peak detector schematic 107 VDD Vin + Comp Vref ¯ 2/0.35 2/0.35 VSS 1pF Vout 0 9UHI 9'' 0 0 0 0 9R 0  0 9R 9UHIĀ 0  0 9R 0  9RXW 9ELDV —$ 0 0 —$ 0   0 Fig. 4.23↜渀 Peak detector comparator based detector instead of conventional peak detectors such as those presented in Sect.€3.2 (see Figs.€4.22 and 4.23). In this case, the input signal is compared with a reference signal which marks the minimum expected output. This means that any input amplitude below this reference value will result in a VGA maximum gain configuration from the feedback control. Should the input amplitude rise above the reference value, a pulse will be generated at the comparator output as happened in the feedforward loop. However, this case is analog and a continuous output is required for different input amplitudes. To obtain the analog response it must be noted that the generated pulses have a different width depending on how much bigger the amplitude is than the reference value. If a charge pump is connected in series with the comparator, this variable width pulse generates current pulses proportional to the square root of the input voltage. Loading the charge pump with a 1€pF capacitor, the current pulses charge the capacitor up to a value proportional to the current introduced. The relation between the charge pump output and the input amplitude is not linear. In fact 108 4â•… AGC Systems Fig. 4.24↜渀 Equation€(4.7) for arbitrary constants and fitting curve obtained by Matlab Curve Fitting Toolbox y = 1001 - 637.3*arcsin(Vref/A) 600 y = 204.8*log(A - 94.76) - 285.8 500 Vref = 100 mV 400 y 300 200 100 0 100 120 140 160 180 200 A (mV) the relation is quite an unusual and interesting function. Straightforward analysis yields:  Vout = IoT 11 − arcsin 2π VRef A , (4.7) where Io is the charge pump current, T is the input signal period, A is the input signal amplitude and VRef is the reference voltage. This equation is only valid for Aâ•>› â•V› Refâ•,› since it must be remembered that for Aâ•≤› â•V› Ref the comparator output is zero. If we plot (4.7) for arbitrary constants using Matlab and analyze it with Curve Fitting Toolbox, it is found that another very useful function approximately fits in our application dynamic range. As Fig.€4.24 shows, for VRefâ• ›= â•0› .1€V and input amplitude, A, between 0.1 and 0.2€V, (4.7) is quite close to a logarithmic function. Thus, a peak detector with an approximate logarithmic function is obtained as long as input dynamic range is kept low enough. After the detector, the signal is simply filtered and shifted so that the required VGA control voltage is obtained. Filtration is by means of a simple RC filter which mainly reduces the ripple generated by the charge pump. The RC filter is implemented as a MOS/switch-capacitor configuration where the MOS operates in triode and its equivalent resistance is reduced by a switch in parallel, which is connected for a small time period each time the digital feedforward loop changes the digital word. Providing the time period is not too long, AGC settling-time is reduced by this technique, whereas a simple differential pair makes the function of the level shifter. As mentioned, once logarithmic conversion has been achieved by the peak detector, if an exponential converter was introduced into the loop, the dynamic response given by (2.13) would be obtained. In its place, the dynamic response given by (2.10) for linear control voltage is expected. Once again, power supply is 1.8€V, the same as for the VGA. To follow, simulation and measurement results for certain separated blocks and the full AGC are offered. 4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit 109 Fig. 4.25↜渀 Chip photograph Fig. 4.26↜渀 Measurement test circuitry 4.3.2  Performances The AGC circuit was designed in 0.35€µm CMOS technology by Austria Microsystems (AMS). The chip photograph is shown in Fig.€4.25. The corresponding layout for this structure has been carefully realized taking into account matching between transistors and symmetry between sections in order to minimize second order distortion components due to mismatches. Figure€4.26 shows the chip and the PCB used during measurement tests. Further information on the instrumentation and test probes employed is offered in Appendix A. First, VGA frequency response was measured. Simulation results obtained an almost constant bandwidth around 700€MHz. Measurements however obtained a constant bandwidth of only 500€MHz though this bandwidth is more than enough for the target application, which was expected to be around 250€MHz. Bandwidth and 110 4â•… AGC Systems Fig. 4.27↜渀 Gain vs. input 14 amplitude for an input signal at 100€MHz 12 10 8 Gain (dB) 6 4 2 0 –2 Measured response Ideal response 100 150 200 250 300 350 400 450 500 Vin (mVp-p) gain configuration measurement results are the same as those obtained by VGA3 and can be consulted in Fig.€3.18. Next, measurement results are offered for input signals though only at 100€MHz, as, due to instrumentation limitations, it was not possible to make measurements at higher frequencies. Target and achievable frequencies are not so far apart, consequently, the obtained results can give a close view of expected results for 250€MHz signals. Distortion levels at high frequencies are expected to be high. Simulation results predicted an IM3 for a Voutâ• ›= â•0› .4 Vp-p at 100€MHz below −â•4› 2€dB. Measured IM3 is below −â•4› 0€dB for all gain settings. Both results, simulated and measured, were obtained for the combination of the VGA and the buffer together and can be checked, as well as bandwidth results, in Chap.€3 (see Fig.€3.19). As shown, worst case results for IM3 correspond quite closely to those expected by simulations, although 6 and 12€dB IM3 was underestimated by simulations. A first estimation for the VGA without buffer IM3 is given by simulations which offer an IM3 for an output of 0.4€Vp-p at 100€MHz below −â•4› 9.2€dB for all gain settings. To check AGC loop linearity response, the output amplitude was measured for different inputs at 100€MHz and thus, a graph with the gain vs. input amplitude was obtained. Figure€ 4.27 shows this graph where it can be compared with the ideal response and with ±â•1› €dB error curves. As shown, the obtained gain is below ±1€dB from the ideal response for a range above the input dynamic range of 12€dB (from 100 to 400€mVp-p). Finally, convergence was checked. Simulation results predicted a convergence time for a stepwise signal at 250€MHz below 50€ns. Again, instrumentation limitations prevented the use of such a high frequency modulation; instead, measurements were made with a square modulation of 300€KHz and a carrier frequency of 20€MHz. As shown in Fig.€4.28, the AGC response to this input signal is quite fast. Therefore, although it is not possible to verify whether predicted simulations are 4.3â•…CMOS Mixed Feedback/Feedforward AGC Circuit 111 AGC Input (V) Vc (V) 1.5 0.3 0.2 1.4 0.1 1.3 0 1.2 ¯0.1 ¯0.2 1.1 0 0.5 1 1.5 2 2.5 3 3.5 4 ¯0.3 t (s) x 10¯7 0.3 0.2 0.1 0 ¯0.1 ¯0.2 ¯0.3 0 0.5 1 1.5 2 2.5 3 3.5 4 t (s) x 10¯7 AGC Output (V) 0.05 0.45 0.025 0.4 Vc (V) AGC Input (V) 0 0.35 ¯0.025 0.3 ¯0.05 0.25 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 t (s) x 10¯6 AGC Output (V) 0.03 0.02 0.01 0 ¯0.01 ¯0.02 ¯0.03 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 t (s) x 10¯6 Fig. 4.28↜渀 AGC convergence with a square modulation at 300€KHz and a carrier at 250€MHz for simulation (âu†œ p) and 20€MHz for measurements (âd†œ own) are offered good, measurement results at least offer a maximum response time below 0.8€µs which is the maximum time required to vary VC between its maximum and minimum value with a 20€MHz signal. 112 4.4â•…Conclusions 4â•… AGC Systems Section€4.1 presented a 1.8€V─0.35€µm CMOS automatic gain control circuit based on a digital feedforward approach which converges to the desired level within 0.3€µs. The proposed architecture is very simple, compact and can be implemented with basic cells, obtaining at the same time high performance characteristics. Therefore, this AGC would prove very useful in applications such as WLAN or Bluetooth receivers where the use of traditional closed loop feedback amplifiers forms a boundary due to the stringent settling time constraints. The second proposition presented is a full analogue SiGe BiCMOS AGC circuitry embedded in an IEEE 802.11a WLAN direct conversion receiver. Based on an analog feedforward gain control technique, the circuit adjusts the gain rapidly and with high accuracy, maintaining at the same time a good trade-off between simplicity and power consumption. Therefore, this analog feedforward approach which provides very fast convergence and high enough linearity performance, classifies this architecture for WLAN receiver implementation. The third and final proposed AGC is a double loop AGC for application frequencies up to 250€ MHz. The fast feedforward loop is combined with a more linear feedback loop, so it is possible to offer a fast enough AGC without gain steps that not all applications can accept. Furthermore, a novel digital level detection method is proposed for the feedforward loop and another pseudo-logarithmic peak detector has been obtained for the feedback loop. Summarizing, 0.35€µm CMOS technology has been taken to its upper frequency limitation to offer a sufficiently linear AGC implemented with some simple but novel blocks. Next, a table (Table€4.1) is offered with main characteristics of three analyzed AGCs and some more AGC proposals from the literature: For WLAN applications, the AGC proposed by Dr. Jeon ET. Al in [1] is one of the most complete AGCs to be found in the literature. Therefore, it is a key reference in this book where WLAN receivers are the target application. AGC1 and AGC2 proposals aim to improve the performances obtained in this case. AGC2 is targeted specifically for the same IEEE standard as Jeon’s work. However, the circuit proposed here obtains a faster convergence-time thanks to its feedforward loop, while other performances are similar to those obtained in [1]. The strong points of AGC1 are its simplicity and very fast response. This AGC also offers considerably lower power consumption than other options; although, it would rise a little if gain range and precision were increased. [20] is another example from the literature of an AGC implemented in BiCMOS with high bandwidth and fast response. However, it has the usual drawback in BiCMOS technologies. A higher power supply voltage is used and consequently, consumption is much higher than in other AGCs. AGC2. In spite of using BiCMOS technology, it also makes use of low voltage blocks, so it can work with the right power supply for CMOS transistors. Finally, AGC3, the proposal for high frequency applications, achieves the 243€MHz standard with moderate power consumption, while other performances are below standard for these frequencies. Table 4.1↜渀 Comparison of literature and proposed AGCs Design [20] [1] Tech process Supply voltage (V) Power (mW) Intrinsic bandwidth (MHz) AGC Gain range (dB) Gain setting AGC settling-time (μs) AGC output voltage (V) Distortion: IM3 (dB) a Attack-time b THD 0.25€μm BiCMOS 3–5.2 60–104 400 0â•∼› â•4› 5 Continuous 0.3a 0.11 — 0.18€μm CMOS 1.6–2 10.44 18 −8â•∼› â•3› 2 Continuous (±ldB) 4.2 0.5 <â•−› â•3› 7@lMHzb AGC 1 0.35€μm CMOS 1.8 1.62 100 0â•∼› â•2› 1 Discrete (3€dB) 0.25 0.4 <â•−› â•6› 0@71MHz AGC 2 0.25€μm SiGE BiCMOS 2.5 13.75 0.068–20 15â•∼› â•6› 9 Continuous (±ldB) 3.2 0.5 <â•−› â•4› 1€dB@20€MHz AGC 3 0.35€μm CMOS 1.8 2.2 250 0â•∼› â•1› 2 Discr.+Cont. (±ldB) <â•0› .8 0.4 <â•−› â•4› 2€dB 113 4.4â•…Conclusions 114 4â•… AGC Systems The AGC circuits proposed in this book are therefore highly competitive with those already presented in the literature. References ╇ 1. O. Jeon, R.M. Fox and B.A. Myers; “Analog AGC Circuitry for a CMOS WLAN Receiver”; Solid-State Circuits, IEEE Journal of; Vol. 41, Issue 10, pp. 2291–2300, Oct. 2006. ╇ 2. T. Oshima, K. Maio, W. Hioe, Y. Shibahara and T. Doi; “Automatic Tuning of RC Filters and Fast Automatic Gain Control for CMOS Low-IF Transceiver”; Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003; pp. 5–8, Sept. 2003. ╇ 3. C.-W. Lin, Y.-Z. Liu and K. Y. J. Hsu; “A Low-Distortion and Fast-Settling Automatic Gain Control in CMOS Technology”; Circuits and Systems, 2004. ISCAS ’04. Proceedings of the 2004 International Symposium on; Vol. 1, pp. 541–544, May 2004. ╇ 4. Chun-Pang Wu and Hen-Wai Tsao; “A 110-MHz 84-dB CMOS Programmable Gain Amplifier With Integrated RSSI Function”; Solid-State Circuits, IEEE Journal of; Vol. 40, Issue 6, pp. 1249–1258, Jun. 2005. ╇ 5. B. Calvo, S. Celma and M.T. Sanz; “Low-Voltage Low-Power CMOS IF Programmable Gain Amplifier”; Circuits and Systems, 2006. MWSCAS ’06. 49th IEEE International Midwest Symposium on; Vol. 2, pp. 276–280, Aug. 2006. ╇ 6. S.-B. Park, J.E. Wilson, and M. Ismail; “Peak Detectors for Multistandard Wireless Receivers”; Circuits and Devices Magazine, IEEE; Vol. 22, Issue 6, pp. 6–9, Nov.-Dec. 2006. ╇ 7. “Wireless Lan Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-Speed Physical Layer in the 5-GHz Band”; IEEE Std. 802.11a, Part11, Sep. 1999. ╇ 8. J.M. Khoury, “On the design of constant settling time AGC circuits”; Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on; Vol. 45, Issue 3, pp. 283–294, Mar. 1998. ╇ 9. M. Zargari, D.K. Su, C.P. Yue, S. Rabii, D.Weber, B.J. Kaczynski, S.S. Mehta, K. Singh, S. Mendis, and B.A. Wooley; “A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN system”; Solid-State Circuits, IEEE Journal of; Vol. 37, Issue 12, pp. 1688–1694, Dec. 2002. 10. A. Otin, S. Celma and C. Aldea; “A 40-200MHz Programmable 4th-Order Gm-C Filter with Auto-Tuning System”; Solid State Circuits Conference, 2007. ESSCIRC 2007. 33rd European; pp. 214–217, Sep. 2007. 11. S.I. Liu and Y.S. Hwang; “CMOS Four-Quadrant Multiplier Using Bias Feedback Techniques”; Solid-State Circuits, IEEE Journal of; Vol. 29, Issue 6, Jun. 1994. 12. J.P. Alegre, S. Celma, B. Calvo and J.M. García del Pozo; “Design of a Novel Envelope Detector for Fast-Settling Circuits”; Instrumentation and Measurement, IEEE Transactions on; Vol. 57, Issue 1, pp. 4–9, Jan. 2008. 13. B. Gilbert; “Limiting-Logarithmic Amplifiers”; Electronics Laboratories Advanced Engineering Course on RF IC Design for Wireless Communication Systems, Lausanne, Switzerland, Jul. 1995. 14. J. Israelsohn; “Gain control”; EDN; pp. 38–46, Aug. 2002. 15. M. Fujii, N. Kawaguchi, M. Nakamura, T. Ohsawa; “Feedforward and feedback AGC for fast fading channels”; Electronics Letters; Vol. 31, Issue 13, pp. 1029–1030, Jun. 1995. 16. Wang Wenzhao, Chen Yaqin, Zhou Qi; “Implementation of mixed feedback/feedforward analog and digital AGC”; Microwave and Millimeter Wave Technology, 2004. ICMMT 4th International Conference on, Proceedings; pp. 377–381, Aug. 2004. 17. R.G. Carvajal, J. Ramírez-Angulo, A.J. Lopez-Martin, A. Torralba, J.A.G. Galan, A. Carlosena and F.M. Chavero; “The Flipped Voltage Follower: a Useful Cell for Low-voltage Low-power Circuit Design”; Circuits and Systems I: Regular Papers, IEEE Transactions on; Vol. 52, no. 7, pp. 1276–1291, 2005. References 115 18. C.J.B. Fayomi, G.W. Roberts, M. Sawan; “Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input”; Circuits and Systems, 2000. Proceedings. ISCAS 2000; Vol. 5, pp. 653–656, May 2000. 19. J. Segura, J.L. Rossello, J. Morra, H. Sigg; “A variable threshold voltage inverter for CMOS programmable logic circuits”; Solid-State Circuits, IEEE Journal of; Vol. 33, Issue: 8, pp. 1262–1265, Aug. 1998. 20. T. Drenski, L. Desclos, M. Madihian, H. Yoshida H. Suzuki, T. Yamazaki; “A BiCMOS 300ns Attack-Time AGC Amplifier with Peak-Detect and Hold Feature for High-speed Wireless ATM Systems”; Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. IEEE International; pp. 166–167, Feb. 1999. Chapter 5 Conclusions Throughout this book, the most relevant results and main conclusions have been summarized in the concluding discussion of each chapter. In this final chapter, the most significant contributions will be reported in order to give a general overview of the work. First, the fulfilment of the main objectives presented in Sect.€1.2 will be verified, leading on to the corresponding conclusions. Further research directions will then be pointed out. Among these are the questions not considered in this book and the extra development of those already completed. These proposed investigations could well be used in future works as an extension to complement the work presented here. 5.1â•…General Conclusions Chapter€1 has been employed to introduce the framework for this book: techniques used, technology processes, active blocks, target applications, challenges and main objectives have been laid out. The second chapter offers a theoretical analysis of feedback and feedforward AGCs transfer functions and several possible solutions have been identified. Furthermore, behavioural models realized in Matlab made it possible to verify the expected performance of these solutions. The third chapter consists of three sections, one for each of the main blocks required in an AGC: VGA, peak detector and control voltage generation circuit. Section€3.1 characterizes several VGAs, some of which were classic literature proposals. We were however particularly concerned about those developed inside the design group. These were all designed in a 0.35€µm CMOS process with a single 1.8€V power supply, so that the 1.8 V–0.18€µm CMOS technology migration could easily be realized. Moreover, a multiplier based VGA was proposed (VGA2): a low-voltage constant-bandwidth VGA based on a high performance multiplier cell in a 0.35€µm CMOS technology. This consumes a mere 1.5€mA from a single 1.8€V power supply voltage. Measured results showed competitive performances, such as J. P. Alegre Pérez et al., Automatic Gain Control, Analog Circuits and Signal Processing, 117 DOI 10.1007/978-1-4614-0167-4_5, ©Â€Springer Science+Business Media, LLC 2011 118 5â•… Conclusions 190€MHz gain bandwidth, while a continuous and wide gain range of 36€dB was offered. Thus, a set of high performance VGAs with very predictable responses has been put together to be suitable for feedforward AGCs. Section€3.2 offered the evolution of peak detector cells ranging from the most basic to more complex ones. In this case, several peak detector proposals were made, all of them in 0.35€µm CMOS technology. The first, PD1 is an open loop peak detector composed of a voltage to current converter, a rectifier and a current mode peak detector, which is able to operate at high frequencies. It employs a 3.3€V single supply voltage and consumes 6.1€mW when designed for a 71€MHz bandwidth or 2.13€mW for 10€MHz bandwidth. In order to obtain a 0.3% ripple, the latter one, requires 10€pF total capacitance and worst case settling-time can be up to 27.5€µs due to the inherent trade-off between keeping and tracking. To overcome these results a new concept of envelope detector was proposed (PD2) based on a sample and hold performance controlled by the input signal. This proposal obtained similar performances to those obtained by its counterpart, but this time it only required 3.3€pF and presented a worst case of 0.4€µs settling-time. Thus, it offers the possibility of reducing the capacitance needed for the same performance, thereby achieving a great saving of circuit area and completely overcoming the inherent trade off between keeping and tracking exhibited by conventional peak detectors. Another proposal, PD3, was a differential positive peak detector where, instead of a diode, a unidirectional current mirror is employed together with a high performance transconductor. This transconductor allowed for high operation frequencies with quite low power consumption (0.9€ mW) for a moderate linearity range (21€ dB). Based on the same concept, but making use of a similar fast-settling technique as with PD2 and in SiGe BiCMOS technology, PD4 obtained very good performance tracking signals with low power consumption (0.55€ mW). As speed was limited by an external 5€MHz clock, its settling-time was lower than that of others, though still quite fast. Finally, a peak detector based on a conventional Sample & Hold structure has been presented (PD5) proving how this kind of circuit is able to detect the amplitude of certain types of signals. The advantages of such circuits are those obtained in this case: fast settling-time, low capacitance area… Furthermore, this circuit was specifically designed to cancel charge injection, so a wide dynamic range would be obtained (42€dB). In Chap.€4 all the AGC loops analysis carried out in Chap.€2 and different block proposals developed in Chap.€3 were considered and three different AGC proposals were offered. The first AGC proposal (AGC1) was based on a digital feedforward approach and offered very fast settling time. The projected architecture was very simple, implemented in 0.35€µm CMOS process with basic cells, such as VGA1, PD3 and some simple comparators. Its characteristics obtained a good trade-off of 100€MHz bandwidth, 20€dB gain range with only 1.62€mW power consumption. Furthermore, it took full advantage of feedforward structure and fast peak detector, so its settling-time was only 0.25€µs. The second proposition presented, AGC2, was implemented in a low-cost SiGe BiCMOS technology process. It is a fully analogue feedforward AGC circuit embedded in an IEEE 802.11a WLAN direct conversion receiver. This receiver had 5.2â•… Further Research Directions 119 stringent settling-time constraints, so this AGC fast tracking capability (requiring only 4 out of 10 OFDM preamble symbols to settle the worst case signal variation) was perfect for this application, improving the results obtained by other circuits in the literature. This time the AGC adjusted the gain continuously with only ±Â€1€dB measured accuracy and a range which extends from 15 to 69€dB. Thus, all specifications fixed by the receiver were satisfied and the analog feedforward approach proved itself capable of providing very fast convergence with ample linearity performance. Finally, a double loop feedforward/feedback AGC (AGC3) was proposed for application frequencies of up to 250€MHz. The fast feedforward loop was combined with a more linear feedback loop to be able to offer a fast AGC with continuously variable gain. Furthermore, a novel digital level detection method was proposed for the feedforward loop and another pseudo-logarithmic peak detector was obtained for the feedback loop. In summary, a low-cost 0.35€µm CMOS technology was taken to its upper frequency limitation and fed with a lower supply (1.8€V) to present a linear AGC which consumes 2.2€mW implemented with some simple but novel blocks. For WLAN applications, the CMOS AGC proposed by Jeon et al. (see Table€4.1 in Chap.€4) is one of the most complete AGCs to be found in the literature. Thus, it is a key reference in this book where WLAN receivers are the target application. AGC1 and AGC2 proposals aim to improve the performances obtained in this case. The strong points of AGC1 are its simplicity and very fast response. This AGC also presents considerably lower power consumption than other options; although, it would raise a little if gain range and precision were increased. AGC2 is targeted specifically for the same IEEE standard as Jeon’s work. However, the circuits proposed here obtained a faster convergence-time thanks to their feedforward loop, while other performances are within the requirements of the application. There is another BiCMOS example taken from the literature with high bandwidth and fast response (also shown in Table€4.1, Chap.€4). However, it has the usual drawback in BiCMOS technologies. It uses a higher power supply voltage and consequently, its power consumption is much higher than in other AGCs. In spite of employing BiCMOS technology, AGC2 also makes use of low voltage blocks, so it can work with the power supply corresponding to CMOS transistors. Thus, by means of these two AGCs, this book shows that mentioned AGCs are competitive with those already presented in the literature and consequently, the feedforward loop is a fine alternative in WLAN receivers. 5.2â•…Further Research Directions The fast-settling peak detectors introduced in Sect.€3.2 offer a new research line which is very advantageous in many applications such as adaptive bias techniques for linearity enhancement, dc current reduction in RF amplifiers or MLL Q-tuning method used in high-Q high-frequency continuous time filters, beyond AGC 120 5â•… Conclusions circuits. These detectors still have one or two issues to be solved such as those brought about by switches: charge injection and capacitive feedthrough. Many techniques in the literature deal with these problems, but their study was sidestepped to avoid deviating from our objectives in this book. AGC3, the proposal for high frequency applications, introduced a new field of study that should be developed still further: the feedforward/feedback dual loop. The possibility of reducing feedback loop compression ratios by feedforward loop and thus, relaxing loop stability conditions can lead to faster AGC circuits. This has been introduced through AGC3, but could require much greater work and has been set aside for future investigation lines. Finally, another issue to be investigated is the use of the pseudo-logarithmic peak detector presented in Sect.€4.3. This simple method for obtaining a logarithmic response in CMOS technologies could be combined with other simple exponential converters to design a fast analog feedforward loop in a CMOS process. Thus, the future work to be realized is clear and will be useful to complete the study carried out in this book as well as to explore new research directions. Appendix A: Layout and Experimental Techniques A.1â•… General Layout Considerations The layout of an analog IC directly influences its performance. Therefore, if we are to keep the characteristics of the designed circuits up to certain specifications despite negative effects such as crosstalk, parasitics, mismatches, noise, etc, a careful layout is mandatory. Although the layout considerations to be taken into account to minimize these effects are quite well-known and commonly used by analog designers [1–4], a reminder of them here in this work will not go amiss. A summary follows of the relevant key points to be considered in the design of the main components. A.1.1  Layout Components Transistors╇ Transistor layout was carried out using common design rules in order to achieve adequate matching. Therefore, in cases where matching between components was critical, interdigitized or common centroid structures were employed. Likewise, dummy transistors were introduced in the stack borders to guarantee obtaining similar performance for each finger. These dummies were connected to the adequate power supply, to keep them in the cutoff region. Guard rings were also included to reduce substrate noise influence in transistor signals. Capacitors╇ These are basic elements in the implementation of any integrated circuit. In this book, the main use of capacitors has been in peak detectors and in stability compensation of feedback loops. All the capacitors in 0.35€µm CMOS process were implemented by double poly structures. The main reason for choosing this type was its superior linearity and area relation. Metal-metal capacitors offer superior linearity performance, but their specific capacitance is low and requires greater area. Alternatively, MOS based capacitors can present high specific capacitance, but their linearity performance is lower. J. P. Alegre Pérez et al., Automatic Gain Control, Analog Circuits and Signal Processing, 121 DOI 10.1007/978-1-4614-0167-4, ©Â€Springer Science+Business Media, LLC 2011 122 Appendix A: Layout and Experimental Techniques With regard to circuits in 0.25€µm SiGe BiCMOS, Metal-Insulator-Metal, MIM, capacitors were employed as this technology allows only this kind of capacitor. In the circuits offered throughout this work, no critical capacitor matching requirement was found and their values were moderate, so parasitic capacitors were a second order issue. Thus, their layouts have not followed any special requirement. Resistors╇ 1. MOS based resistors: To implement the layout of MOS based transistors, the criteria explained in transistor layout has been followed: basically, transistors were interdigitized and dummy transistors were introduced in the borders of the stacks. A guard ring connected to VSS was also used in each case. 2. Polysilicon resistors: If best linearity is required, MOS based resistors are not adequate. Therefore, in high frequency amplifiers for example, load resistors were implemented in this technology. When matching was necessary, these resistors were interdigitized with dummy structures on both sides, inside an N-well and a guard ring to guarantee isolation. Pads╇ In CMOS circuits two types of pads were employed. One included a simple diode based protection system to avoid break voltages in MOS gates due to ElectroStatic Discharge. (ESD). This is a simple system, but adequate enough for our requirements. In all the other inputs/outputs simple custom pads were used to avoid degradation in frequency response. In SiGe BiCMOS circuits, there were also two pad types: one for high frequency response and the other for DC signals. Furthermore, the same simple protection system was introduced where required as in CMOS circuits. A.1.2  Full Systems Layouts In the different circuit layouts, apart from using different component matching techniques, we have tried to keep the natural circuit symmetry. Furthermore, differences in the paths of balanced signals were carefully avoided as it is absolutely necessary to obtain the benefits inherent to these signals. To avoid coupling between inputs and outputs, bondpads were distributed separately. As previously mentioned, balanced signal paths were drawn symmetrically and the same was done with bondpads. A.2â•… Experimental Considerations To verify simulation results several circuits were measured. This section introduces the techniques that were used to realize the measurements and the solutions applied to the typical small problems that crop up during the process. First of all, here is a layout of the equipment used. A.2 Experimental Considerations 123 Fig. A.1↜渀 Measurement scheme CHIP Test Vin Vout DUT Test A.2.1  Measurement Equipment Apart from the typical measuring equipment found in any laboratory, the following devices were employed: • Network analyzer: Rohde&Schwartz ZVL6 (9€kHz–6€GHz) • Digital oscilloscope: Tektronix TDS544A (500€MHz) • Signal synthesizer/generator: HP3325B (20€MHz) • Signal generator: Rohde&Schwartz SMY-01 (1.04€GHz) • RF signal generator: Rohde&Schwartz SM300 (9€kHz–3€GHz) • Spectrum analyzer: Rohde&Schwartz FS300 (9€kHz–3€GHz) A.2.2  Measurement of Integrated Circuits The first thing to take into account in the measurement of an IC is the design of PCB board required to support the chip and connect it to the measurement devices and auxiliary circuitry. The most important requirement of a PCB board in this work was to avoid as much as possible parasitic capacitances along the signal path from the generator to the chip input pads and from the output pads to the measurement devices. To do so, SMA connectors were employed, PCB paths were kept as short as possible to minimize parasitics and high frequency transformers (WBC8-1LB and WB3-1TSLB) were used. A way to facilitate tests is to introduce calibration test circuitry in the chip design or Device Under Test (DUT). This calibration circuitry is composed, for example, of a second path between inputs and outputs with the test-buffer employed to cancel pad parasitic capacitances in the middle, so that it is possible to calibrate the frequency analyzer and measure DUT frequency response. This measurement schematic is shown in Fig. A.1. The input signal is carried from the generator to the PCB in single mode. Then, it is converted to balanced currents by the transformers and again into voltage by input resistors, Rin. These resistors are chosen so that the generator sees an equivalent load resistor of 50Â€Ω to optimize energy transmission. The output buffer is loaded 124 Fig. A.2╇ CMOS test-buffer schematic Appendix A: Layout and Experimental Techniques VDD IB1 Iout+ Iout– VDD IB1 Vout+ Fig. A.3╇ Test buffer chip photograph IB2 GND Vout– Test buffer with Rout resistors, which again give an equivalent resistance equal to the measurement device input resistor: 50€Ω. The test-buffer scheme is shown in Fig. A.2. It is a two stage transconductor, which consequently, avoids inverse transmissions. The first stage is a simple source follower composed of P-transistors M1. The second stage is a simple differential pair biased by 2€mA current and loaded by external resistors. These resistors can not be very big, as together with parasitic capacitors, they would greatly reduce buffer bandwidth. Thus, 100Â€Ω resistors were employed, so, at the same time an equivalent output resistor of 50Â€Ω was obtained. In BiCMOS designs, buffers based on simple transconductors with a feedback loop were employed. As the bipolar differential pair was used instead of the MOS one, greater transconductance was obtained, so these buffers offered very good performance in spite of the feedback loop. Figure€A.3 shows a CMOS test buffer chip photograph, while Fig€A.4 shows example pictures of both the PCBs used to measure chips and of the laboratory test table. To automate some of the measurements, GPIB connectors were inserted between the measurement devices and the computer. Using Matlab, it was possible to create the adequate files to automatically measure and collect the data. References 125 Fig. A.4↜渀 PCBs for each chip References 1. Y. Tsividis; “Mixed Analog Digital VLSI Devices and Technology”; McGraw-Hill, New York, 1996 2. R.J. Baker, H.W. Li, D.E. Boyce; “CMOS Circuit Design, Layout and Simulation”; IEEE Press Series on Microelectronic Systems, 1998. 3. A. Hastings; “The Art of Analog Layout”; Prentice Hall Inc., New Jersey, 2001 4. F. Maloberti; “Analog Design for CMOS VLSI Systems”; Kluwer Academic Publishers, 2001. Appendix B: Acronym List Acronym ADC AGC AM AMS ASIC ASK BiCMOS BJT BSIM BW CCD CDMA CMFF (C)MOS CMRR DR DSP GBW GPIB HF HRP IC IEEE IF IM3 LAN LNA MLL MOSFET N/PMOS Significance Analog to Digital Converter Automatic Gain Control Amplitude Modulation Austria Micro Systems Application Specific Integrated Circuits Amplitude-Shift Keying Bipolar-CMOS Bipolar Junction Transistor Berkeley Short-channel IGFET Model Bandwidth Charge Coupled Device Code Division Multiple Access Common-Mode Feedforward (Complementary) Metal Oxide Semiconductor Common-Mode Rejection Ratio Dynamic Range Digital Signal Processor Gain Bandwidth product General Purpose Interface Bus High Frequency High Resistivity Polysilicon Integrated Circuit Institute of Electrical and Electronics Engineers Intermediate Frequency Third order Intermodulation distortion Local Area Network Low Noise Amplifier Magnitude Locked Loop Metal Oxide Semiconductor Field Effect Transistor N-channel/P-channel MOS J. P. Alegre Pérez et al., Automatic Gain Control, Analog Circuits and Signal Processing, 127 DOI 10.1007/978-1-4614-0167-4, ©Â€Springer Science+Business Media, LLC 2011 128 Appendix B: Acronym List Op-Amp OFDM OTA PCB PD PGA PH PVT variations RMS S/H SiGe BiCMOS SNR SR THD VGA VHF VLSI WLAN Operational Amplifier Orthogonal Frequency Division Multiplexing Operational Transconductance Amplifier Printed Circuit Board Peak Detector Programmable Gain Amplifier Peak Holder Process-Voltage-Temperature variations Root Mean Square Sample and Hold Silicon Germanium BiCMOS Signal-to-Noise Ratio Slew-Rate Total Harmonic Distortion Variable Gain Amplifier Very High Frequency Very Large Scale Integration Wireless LAN Appendix C: Parameter Glossary Parameter k T εox ID μn/μp μo tOX θ γ λ NSUB CJ CJW CPOX ρSH W L dW dL α K gm gmb ro VTH VTHO Vfp VDSAT Significance Boltzmann constant (1.38â•×› â•1› 0–23 J/K) Absolute temperature (in Kelvin degrees) Dielectric permittivity of SiO2 (3.4531â•×› â•1› 0–11€F/m) Total drain current of a MOS transistor Surface mobility for electrons and holes respectively Effective mobility at low electrical fields Gate-oxide thickness of a MOS transistor Mobility-reduction coefficient of a MOS transistor Body-effect coefficient of a MOS transistor Channel-length modulation factor of a MOS transistor Effective substrate doping Junction capacitance per unit area (source/drain-bulk) Sidewall junction capacitance (source/drain-bulk) Poly1-poly2 specific capacitance per unit area Sheet resistance of a high resistivity poly module Channel width of a MOS transistor Channel length of a MOS transistor Difference between W and the effective channel width Weff Difference between L and the effective channel length Leff MOS transistor gate-to-source DC voltage gain MOS transistor gain factor: Kâ•›â•=› ╛╽› €µCoxW/L MOS transistor transconductance defined as δID/δVGS MOS transistor bulk-transconductance defined as δID/δVBS MOS transistor output conductance Threshold voltage Zero-VBS value of threshold Fermi potential Drain-source saturation voltage of a MOS transistor J. P. Alegre Pérez et al., Automatic Gain Control, Analog Circuits and Signal Processing, 129 DOI 10.1007/978-1-4614-0167-4, ©Â€Springer Science+Business Media, LLC 2011 130 Appendix C: Parameter Glossary VGSâ•,› VDSâ•,› VBS COX VDD VCM IB, Ibias RL, CL CT Gm τ Gate-source, drain-source and bulk-source MOS transistor voltages MOS gate-oxide capacitance per unit area Supply voltage Common-mode voltage Bias current Load resistance and load capacitance Circuit total capacitance Differential transconductance of a system Time constant Appendix D: Process Parameters This appendix summarizes the most important parameters associated to both technologies, CMOS and SiGe BiCMOS, considered in this work. Table€ D.1 reports the parameters related to the 0.35€μm, P-substrate, N-well, 4-metal, 2-poly, Austria Microsystems (AMS); whereas Table€D.2 reports those related to SGB25V, the 0.25€µm CMOS core, SiGe:C BiCMOS with High-Voltage Devices, 5-metal, IHPmicroelectronics. Table D.1↜渀 Technology: AMS 0.35€μm CMOS P-Substrate, N-Well, 4-Metal, 2-Poly Parameter N-Transistor P-Transistor Units μCOX VTHo (10/0.35) tOX μO θ 170 0.5 7.58 370 0.264 58 −â•0› .65 7.75 126 0.258 μA/V2 V nm cm2/(Vs) 1/V dL 0.06 0.04 μm dW 0.05 0.05 μm γ 0.58 0.40 V1/2 λ NSUB COX CJ CJW CPOX ρSH CPoly 0.044 2.12â•×› â•1› 017 4.54â•×› â•1› 0–3 0.94â•×› â•1› 0–3 0.25â•×› â•1› 0–9 0.86â•×› â•1› 0–3 1200 1.1 0.178 1.01â•×› â•1› 017 4.54â•×› â•1› 0−3 1.36â•×› â•1› 0–3 0.32â•×› â•1› 0–9 0.86â•×› â•1› 0−3 1200 1/V cm–3 F/m2 F/m2 F/m F/m2 Ω/Sq fF/µm2 J. P. Alegre Pérez et al., Automatic Gain Control, Analog Circuits and Signal Processing, 131 DOI 10.1007/978-1-4614-0167-4, ©Â€Springer Science+Business Media, LLC 2011 132 Appendix D: Process Parameters Table D.2↜渀 Technology: IHP 0.25€μm SiGe:C BiCMOS with High-Voltage Devices, 5-metal CMOS Section Parameter VTH IDSAT Ioff Bipolar Section Parameter AE Peak fmax Peak fT BVCE0 BVCB0 VA ß Passives MIM Capacitor N+ Poly Resistor P+ Poly Resistor High Poly Resistor N-Transistor 0.6 540 3 P-Transistor −â•0› .56 −â•2› 30 −â•3› Standard 0.42â•×› â•0› .84 90 45 4.0 >â•1› 5 >â•8› 0 190 1 210 280 1600 Units V μA/μm pA/μm Units µm2 GHz GHz V V V fF/µm2 Ω/sq Ω/sq Ω/sq Index A active VGA, 33 AGC, 1, 3–10, 13–16, 18–27, 87, 88, 91–99, 101–103, 106, 108–114 AGC model, 15, 23 AGC stability, 19 analog AGC, 5 analog control, 79, 80 attack-time, 55, 59, 67 B balanced signals, 3 Bluetooth, 1, 2, 4, 6, 9, 87, 112 Exponential AGC, 23 exponential converter, 29, 30, 36, 44, 80 F feedback AGC, 6, 8, 9, 13, 15, 16, 19, 20, 25, 27 feedback loop, 31, 33, 40, 41, 45, 47, 48, 51, 52, 78, 80 feedforward AGC, 8, 9, 13, 20, 21, 25, 27, 94 Feedforward AGC, 101, 103, 105, 107, 109, 111 feedforward loop, 78, 80 folded cascode OTA, 57 C charge pump, 102, 107, 108 closed-loop AGC, 87 CMFF, 44, 47, 48, 103 CMOS, 1–3, 8 common-mode control, 47 Comparator bank, 35, 79, 88, 90, 91 compression ratio, 13, 102 control voltage, 13, 14, 16–20, 96–99, 102, 108 Control voltage, 98, 100 conventional AGC, 94, 102 D degenerative resistor, 32 Digital AGC, 5, 87, 101 digital control, 44, 69, 82 direct conversion, 94, 112 divider, 81, 82 droop, 54, 55, 61 E envelope detector, 54–57, 61, 62, 64, 65, 67–71, 74–76, 132 exp-amplifier, 98 G gm-boost, 33, 88 H high speed comparator, 103 I IEEE 802.11a, 6, 87, 93, 94, 112 IF strip, 6 Inverter based comparator, 105, 106 L latch comparator, 105 leakage current, 54, 68 linear AGC, 22 log-amplifier, 98 logarithmic amplifier, 81 M multiplier, 30, 36–38, 52, 81 O OFDM, 1, 6, 7, 93, 99, 101 open-loop AGC, 94 J. P. Alegre Pérez et al., Automatic Gain Control, Analog Circuits and Signal Processing, 133 DOI 10.1007/978-1-4614-0167-4, ©Â€Springer Science+Business Media, LLC 2011 134 Index P peak detector, 87, 88, 90, 91, 93, 96–103, 106–108 Peak detector, 68, 90, 107 peak holder, 61, 62, 72, 73 PGA, 30, 31, 34–36, 50, 67, 79, 88, 89, 91, 92, 103 preamplifier, 88 pseudo-logarithmic peak detector, 112 R Receivers, 1 rectifier, 57–59, 62, 69 release-time, 55, 59, 61, 64, 67, 70 resistor bank, 35 ripple, 55, 59, 61, 63–65, 74–76, 78 T telescopic OTA, 72, 73 time constant, 13, 17–20, 24, 59, 63, 64, 75, 76, 102 V VGA, 29–38, 40–45, 47–52, 78–82, 96, 100, 102, 103, 106–110 W wireless system, 1 WLAN, 1–3, 6, 8, 9, 87, 93, 94, 112 S settling-time, 29, 54, 55, 59, 61, 67, 70, 87, 92, 96, 99, 101, 102, 108, 113 SiGe BiCMOS, 3, 8 Simulink, 21–26
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