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ADV7181D 视频解码器

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  The ADV7181D is a high quality, single-chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of composite or S-Video into a digital ITU-R BT.656 format.

The ADV7181D also supports the decoding of a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. Support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, and many other HD and SMPTE standards.

Graphics digitization is also supported by the ADV7181D; it is capable of digitizing RGB graphics signals from VGA to XGA rates and converting them into a digital DDR RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ability of the ADV7181D to simultaneously process CVBS and standard definition RGB signals. The mixing of these signals is controlled by the fast blank (FB) pin.

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Data Sheet 10-Bit, 10-Channel, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer ADV7181D FEATURES Four 10-bit ADCs sampling up to 75 MHz 10 analog input channels SCART fast blank support Internal antialiasing filters NTSC, PAL, and SECAM color standards supported 525p/625p component progressive scan supported 720p/1080i component HDTV supported Digitizes RGB graphics up to 1024 × 768 at 70 Hz (XGA) 3 × 3 color space conversion matrix Industrial temperature range: −40°C to +85°C 12-bit 4:4:4 DDR, 8-/10-/16-/20-bit SDR pixel output interface Programmable interrupt request output pin Small package Low pin count Single front end for video and graphics VBI data slicer (including teletext) Qualified for automotive applications APPLICATIONS Automotive entertainment HDTVs LCD/DLP® projectors HDTV STBs with PVR DVD recorders with progressive scan input support AVR receivers GENERAL DESCRIPTION The ADV7181D is a high quality, single-chip, multiformat video decoder and graphics digitizer. This multiformat decoder supports the conversion of PAL, NTSC, and SECAM standards in the form of composite or S-Video into a digital ITU-R BT.656 format. The ADV7181D also supports the decoding of a component RGB/YPrPb video signal into a digital YCrCb or RGB pixel output stream. Support for component video includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i, and many other HD and SMPTE standards. Graphics digitization is also supported by the ADV7181D; it is capable of digitizing RGB graphics signals from VGA to XGA rates and converting them into a digital DDR RGB or YCrCb pixel output stream. SCART and overlay functionality are enabled by the ability of the ADV7181D to simultaneously process CVBS and standard definition RGB signals. The mixing of these signals is controlled by the fast blank (FB) pin. The ADV7181D contains two main processing sections. The first section is the standard definition processor (SDP), which processes all PAL, NTSC, and SECAM signal types. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADV7181D TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 Electrical Characteristics ............................................................. 4 Video Specifications ..................................................................... 5 Analog Specifications................................................................... 6 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings............................................................ 9 Reflow Solder ................................................................................ 9 Package Thermal Performance................................................... 9 Thermal Resistance ...................................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Functional Overview...................................................................... 12 Analog Front End ....................................................................... 12 REVISION HISTORY 12/11—Revision 0: Initial Version Data Sheet Standard Definition Processor (SDP) Pixel Data Output Modes........................................................................................... 12 Component Processor (CP) Pixel Data Output Modes ........ 12 Composite and S-Video Processing......................................... 12 Component Video Processing .................................................. 13 RGB Graphics Processing ......................................................... 13 General Features......................................................................... 13 Detailed Descriptions .................................................................... 14 Analog Front End....................................................................... 14 Standard Definition Processor (SDP)...................................... 14 Component Processor (CP)...................................................... 14 Analog Input Muxing ................................................................ 15 Pixel Output Formatting................................................................ 18 Recommended External Loop Filter Components.................... 19 Typical Connection Diagram ....................................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21 Automotive Products ................................................................. 21 Rev. 0 | Page 2 of 24 Figure 1. Rev. 0 | Page 3 of 24 ADV7181D AIN1 10 TO AIN10 CVBS S-VIDEO YPrPb SCART– (RGB + CVBS) GRAPHICS RGB INPUT MUX ANTICLAMP ALIASING FILTER ANTICLAMP ALIASING FILTER ANTICLAMP ALIASING FILTER ANTICLAMP ALIASING FILTER 10 ADC0 10 ADC1 10 ADC2 10 ADC3 FB SCLK SDATA SERIAL INTERFACE CONTROL AND VBI DATA ALSB DATA PREPROCESSOR 10 10 DECIMATION AND DOWNSAMPLING 10 FILTERS 10 HS_IN/ CS_IN VS_IN SOG SOY SYNC PROCESSING AND CLOCK GENERATION SSPD STDI XTAL XTAL1 COLOR SPACE CONVERSION STANDARD DEFINITION PROCESSOR MACROVISION DETECTION STANDARD AUTODETECTION VBI DATA RECOVERY CVBS/Y fSC RECOVERY CVBS C CHROMA DEMOD Cr Cb LUMA FILTER SYNC EXTRACT CHROMA FILTER LUMA RESAMPLE RESAMPLE CONTROL CHROMA RESAMPLE LUMA Y 2D COMB (5H MAX) 20 Cr CHROMA 2D COMB Cb (4H MAX) FAST BLANK OVERLAY CONTROL AND AV CODE INSERTION FB Y Cr Cb ACTIVE PEAK AND AGC COMPONENT PROCESSOR MACROVISION CGMS DATA DETECTION EXTRACTION 10 10 DIGITAL FINE 10 CLAMP GAIN CONTROL OFFSET CONTROL AV CODE 20 INSERTION OUTPUT FIFO AND FORMATTER PIXEL DATA 10 P19 TO P10 10 P9 TO P0 HS/CS VS FIELD/DE LLC SFL/ SYNC_OUT INT 09994-001 Data Sheet FUNCTIONAL BLOCK DIAGRAM ADV7181D ADV7181D Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range = 1.6 V. TMIN to TMAX = −40°C to +85°C, unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range. Table 1. Parameter1 Symbol Test Conditions/Comments Min STATIC PERFORMANCE2, 3 Resolution (Each ADC) N Integral Nonlinearity INL BSL at 27 MHz (10-bit level) BSL at 54 MHz (10-bit level) BSL at 74 MHz (10-bit level) Differential Nonlinearity DNL At 27 MHz (10-bit level) At 54 MHz (10-bit level) At 74 MHz (10-bit level) DIGITAL INPUTS Input High Voltage4 VIH 2 HS_IN, VS_IN low trigger mode 0.7 Input Low Voltage5 VIL HS_IN, VS_IN low trigger mode Input Current IIN −10 Input Capacitance6 CIN DIGITAL OUTPUTS Output High Voltage7 VOH ISOURCE = 0.4 mA 2.4 Output Low Voltage7 VOL ISINK = 3.2 mA High Impedance Leakage Current ILEAK Pin 1 All other output pins Output Capacitance6 COUT POWER REQUIREMENTS6 Digital Core Power Supply DVDD 1.65 Digital I/O Power Supply DVDDIO 3.0 PLL Power Supply PVDD 1.71 Analog Power Supply AVDD 3.15 Digital Core Supply Current IDVDD CVBS input sampling at 54 MHz Graphics RGB sampling at 75 MHz SCART RGB FB sampling at 54 MHz Digital I/O Supply Current IDVDDIO CVBS input sampling at 54 MHz Graphics RGB sampling at 75 MHz PLL Supply Current IPVDD CVBS input sampling at 54 MHz Graphics RGB sampling at 75 MHz Analog Supply Current8 IAVDD CVBS input sampling at 54 MHz Graphics RGB sampling at 75 MHz SCART RGB FB sampling at 54 MHz Power-Down Current IPWRDN Green Mode Power-Down IPWRDNG Synchronization bypass function Power-Up Time tPWRUP Typ Max Unit 10 Bits ±0.6 ±2.5 LSB −0.6/+0.7 LSB ±1.4 LSB −0.2/+0.25 −0.99/+2.5 LSB −0.2/+0.25 LSB ±0.9 LSB V V 0.8 V 0.3 V +10 μA 10 pF V 0.4 V 60 μA 10 μA 20 pF 1.8 2.0 V 3.3 3.6 V 1.8 1.89 V 3.3 3.45 V 105 mA 90 mA 106 mA 4 mA 38 mA 11 mA 12 mA 99 mA 166 mA 200 mA 2.25 mA 16 mA 20 ms 1 All specifications are obtained using the Analog Devices, Inc., recommended programming scripts. 2 All ADC linearity tests performed at input range of full scale − 12.5% and at zero scale + 12.5%. 3 Maximum INL and DNL specifications obtained with part configured for component video input. 4 To obtain specified VIH level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIH on Pin 22 is 1.2 V. 5 To obtain specified VIL level on Pin 22, program Register 0x13 (WO) with a value of 0x04. If Register 0x13 is programmed with a value of 0x00, then VIL on Pin 22 is 0.4 V. 6 Guaranteed by characterization. 7 VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4. 8 For CVBS current measurements only, ADC0 is powered up. For RGB current measurements only, ADC0, ADC1, and ADC2 are powered up. For SCART FB current measurements, all four ADCs are powered up. Rev. 0 | Page 4 of 24 Data Sheet ADV7181D VIDEO SPECIFICATIONS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C, unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range. Table 2. Parameter1 Symbol Test Conditions/Comments Min Typ Max Unit NONLINEAR SPECIFICATIONS Differential Phase DP CVBS input, modulated 5 step 0.5 Degrees Differential Gain DG CVBS input, modulated 5 step 0.5 % Luma Nonlinearity LNL CVBS input, 5 step 0.5 % NOISE SPECIFICATIONS Signal-to-Noise Ratio, Unweighted SNR Luma ramp 54 56 dB Luma flat field 58 60 dB Analog Front-End Crosstalk 60 dB LOCK TIME SPECIFICATIONS Horizontal Lock Range −5 +5 % Vertical Lock Range 40 70 Hz fSC Subcarrier Lock Range ±1.3 kHz Color Lock-In Time 60 Lines Synchronization Depth Range2 20 200 % Color Burst Range 5 200 % Vertical Lock Time 2 Fields Horizontal Lock Time 100 Lines CHROMA SPECIFICATIONS Hue Accuracy 1 Degrees Color Saturation Accuracy CL_AC 1 % Color AGC Range 5 400 % Chroma Amplitude Error 0.5 % Chroma Phase Error 0.4 Degrees Chroma Luma Intermodulation 0.2 % LUMA SPECIFICATIONS Luma Brightness Accuracy CVBS, 1 V input 1 % Luma Contrast Accuracy CVBS, 1 V input 1 % 1 Guaranteed by characterization. 2 Nominal synchronization depth is 300 mV at 100% synchronization depth range. Rev. 0 | Page 5 of 24 ADV7181D Data Sheet ANALOG SPECIFICATIONS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C, unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range. The recommended analog input video signal range is 0.5 V to 1.6 V, typically 1 V p-p. Table 3. Parameter1 CLAMP CIRCUITRY External Clamp Capacitor Input Impedance All Pins Except for Pin 32 (FB) Pin 32 (FB) Common-Mode Level (CML) ADC Full-Scale Level ADC Zero-Scale Level ADC Dynamic Range Clamp Level (When Locked) Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current Test Conditions/Comments Min Typ Max Unit 0.1 μF Clamps switched off CVBS input SCART RGB input (R, G, B signals) S-Video input (Y signal) S-Video input (C signal) Component input (Y, Pr, Pb signals) PC RGB input (R, G, B signals) SDP only SDP only SDP only SDP only 10 MΩ 20 kΩ 1.86 V CML + 0.8 V CML − 0.8 V 1.6 V CML − 0.292 V CML − 0.4 V CML − 0.292 V CML V CML − 0.3 V CML − 0.3 V 0.75 mA 0.9 mA 17 μA 17 μA 1 Guaranteed by characterization. Rev. 0 | Page 6 of 24 Data Sheet ADV7181D TIMING CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C, unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range. Table 4. Parameter1 SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency Crystal Frequency Stability Horizontal Sync Input Frequency LLC Frequency Range I2C PORT2 SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDATA Setup Time SCLK and SDATA Rise Time SCLK and SDATA Fall Time Setup Time (Stop Condition) RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC Mark-Space Ratio Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9:t10 Description Min 14.8 12.825 0.6 1.3 0.6 0.6 100 5 45:55 Typ Max 28.63636 ±50 110 75 400 300 300 0.6 55:45 DATA AND CONTROL OUTPUTS Data Output Transition Time SDR (SDP)3 t11 Negative clock edge to start of valid data 3.6 t12 End of valid data to negative clock edge 2.4 SDR (CP)4 t13 End of valid data to negative clock edge 2.8 t14 Negative clock edge to start of valid data 0.1 DDR (CP)4, 5 t15 Positive clock edge to end of valid data −4 + TLLC/4 t16 Positive clock edge to start of valid data 0.25 + TLLC/4 t17 Negative clock edge to end of valid data −2.95 + TLLC/4 t18 Negative clock edge to start of valid data −0.5 + TLLC/4 Unit MHz ppm kHz MHz kHz μs μs μs μs ns ns ns μs ms % duty cycle ns ns ns ns ns ns ns ns 1 Guaranteed by characterization. 2 TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points. 3 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4. 4 CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4. 5 DDR timing specifications dependent on LLC output pixel clock; TLLC/4 = 9.25 ns at LLC = 27 MHz. Timing Diagrams t3 SDATA t5 t3 SCLK t6 t1 t2 t7 t4 t8 Figure 2. I2C Timing 09994-002 Rev. 0 | Page 7 of 24 ADV7181D LLC t9 t10 P0 TO P19, VS, HS/CS, FIELD/DE, SFL/SYNC_OUT t11 t12 Figure 3. Pixel Port and Control SDR Output Timing (SDP Core) LLC t9 t10 P0 TO P19 t13 t14 Figure 4. Pixel Port and Control SDR Output Timing (CP Core) LLC P6 TO P19 t16 t15 t18 t17 Figure 5. Pixel Port and Control DDR Output Timing (CP Core) 09994-005 09994-003 09994-004 Data Sheet Rev. 0 | Page 8 of 24 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD to GND DVDD to GND PVDD to GND DVDDIO to GND DVDDIO to AVDD PVDD to DVDD DVDDIO to PVDD DVDDIO to DVDD AVDD to PVDD AVDD to DVDD Digital Inputs to GND Digital Outputs to GND Analog Inputs to GND Operating Temperature Range Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow, Soldering (20 sec) Rating 4V 2.2 V 2.2 V 4V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to +2 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to AVDD + 0.3 V −40°C to +85°C 125°C −65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. REFLOW SOLDER The ADV7181D is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and can withstand surface-mount soldering at up to 255°C ± 5°C. In addition, the ADV7181D is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C. ADV7181D PACKAGE THERMAL PERFORMANCE To reduce power consumption when using the part, turn off any unused ADCs. It is imperative that the recommended scripts be used for the following high current modes: SCART, 720p, 1080i, and all RGB graphic standards. Using the recommended scripts ensures correct thermal performance. These scripts are available from a local field applications engineer (FAE). The junction temperature must always stay below the maximum junction temperature (TJ MAX) of 125°C. The junction temperature can be calculated by TJ = TA MAX + (θJA × WMAX) where: TA MAX = 85°C. θJA = 20.3°C/W. WMAX = ((AVDD × IAVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO) + (PVDD × IPVDD)) THERMAL RESISTANCE Table 6 specifies the typical values for the junction-to-ambient thermal resistance (θJA) and the junction-to-case thermal resistance (θJC) for an ADV7181D soldered on a 4-layer PCB with solid ground plane. Table 6. Thermal Resistance Package Type θJA1 θJC 64-Lead LFCSP (CP-64-3) 20.3 1.2 1 In still air. Unit °C/W ESD CAUTION Rev. 0 | Page 9 of 24 ADV7181D PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Data Sheet VS FIELD/DE P16 P17 P18 P19 DVDD GND HS_IN/CS_IN VS_IN SCLK SDATA ALSB RESET SOY AIN10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 INT 1 HS/CS 2 GND 3 DVDDIO 4 P15 5 P14 6 P13 7 P12 8 SFL/SYNC_OUT 9 GND 10 DVDDIO 11 P11 12 P10 13 P9 14 P8 15 P7 16 PIN 1 ADV7181D TOP VIEW (Not to Scale) 48 AIN9 47 AIN8 46 AIN7 45 AIN6 44 CAPC2 43 CML 42 REFOUT 41 AVDD 40 CAPY2 39 CAPY1 38 AIN5 37 AIN4 36 AIN3 35 AIN2 34 AIN1 33 SOG 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P6 P5 P4 LLC XTAL1 XTAL DVDD GND P3 P2 P1 P0 PWRDWN ELPF PVDD FB 09994-006 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GND. Figure 6. Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Type 1 INT Output 2 HS/CS Output 3, 10, 24, 57 4, 11 28 to 25, 19 to 12, 8 to 5, 62 to 59 9 GND DVDDIO P0 to P19 SFL/SYNC_OUT Ground Power Output Output 20 21 22 23, 58 29 30 31 32 LLC XTAL1 XTAL DVDD PWRDWN ELPF PVDD FB Output Output Input Power Input Output Power Input Description Interrupt. This pin can be active low or active high. When SDP/CP status bits change, this pin is triggered. The set of events that triggers an interrupt is under user control. Horizontal Synchronization Output Signal (HS). Available in SDP and CP modes. Digital Composite Synchronization Signal (CS). Available in CP mode only. Ground. Digital I/O Supply Voltage (3.3 V). Video Pixel Output Port. See Table 10 and Table 11 for output configuration modes. Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder. Sliced Synchronization Output Signal (SYNC_OUT). Available in CP mode only. Line-Locked Clock Output for Pixel Data. The range is 12.825 MHz to 75 MHz. This pin should be connected to the 28.63636 MHz crystal or left unconnected if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7181D. In crystal mode, the crystal must be a fundamental crystal. Input Pin for the 28.63636 MHz Crystal. This input can be overdriven by an external 3.3 V, 28.63636 MHz clock oscillator source to clock the ADV7181D. Digital Core Supply Voltage (1.8 V). Power-Down Input. A Logic 0 on this pin places the ADV7181D in power-down mode. External Loop Filter Output. The recommended external loop filter must be connected to this pin (see the Recommended External Loop Filter Components section). PLL Supply Voltage (1.8 V). Fast Blank Input. Fast switch between CVBS and RGB analog signals. Rev. 0 | Page 10 of 24 Data Sheet ADV7181D Pin No. 33 34 to 38, 45 to 49 39, 40 Mnemonic SOG AIN1 to AIN10 CAPY1, CAPY2 Type Input Input Input 41 AVDD Power 42 REFOUT Output 43 CML Output 44 CAPC2 Input 50 SOY Input 51 RESET Input 52 ALSB Input 53 SDATA Input/ Output 54 SCLK Input 55 VS_IN Input 56 HS_IN/CS_IN Input 63 FIELD/DE Output 64 VS Output EP Exposed Pad Description Sync on Green Input. Used in embedded synchronization mode. Analog Video Input Channels. ADC Capacitor Network. See Figure 9 for a recommended capacitor network for these pins. Analog Supply Voltage (3.3 V). Internal Voltage Reference Output. See Figure 9 for a recommended capacitor network for this pin. Common-Mode Level Pin for the Internal ADCs. See Figure 9 for a recommended capacitor network for this pin. ADC Capacitor Network. See Figure 9 for a recommended capacitor network for this pin. Sync on Luma Input. Used in embedded synchronization mode. System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7181D circuitry. This pin selects the I2C address for the ADV7181D control and VBI readback ports. When set to Logic 0, this pin sets the address for a write to Control Port 0x40 and the readback address for VBI Port 0x21. When set to Logic 1, this pin sets the address for a write to Control Port 0x42 and the readback address for VBI Port 0x23. I2C Port Serial Data Input/Output Pin. I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. Vertical Synchronization Input Signal. This pin can be configured in CP mode to extract timing in a 5-wire mode. Horizontal Synchronization Input Signal (HS_IN). This pin can be configured in CP mode to extract timing in a 5-wire mode. Composite Synchronization Input Signal (CS_IN). This pin can be configured in CP mode to extract timing in a 4-wire mode. Field Synchronization Output Signal (FIELD). Used in all interlaced video modes. Data Enable Signal (DE). This pin can also be used as a data enable (DE) signal in CP mode to allow direct connection to an HDMI/DVI transmitter IC. Vertical Synchronization Output Signal (SDP and CP Modes). The exposed pad must be connected to GND. Rev. 0 | Page 11 of 24 ADV7181D FUNCTIONAL OVERVIEW This section provides a brief description of the functionality of the ADV7181D. More detailed information is available in the Detailed Descriptions section. ANALOG FRONT END The analog front end of the ADV7181D contains four high quality, 10-bit ADCs and a multiplexer (mux) with 10 analog input channels to enable multisource connection without the requirement of an external multiplexer. The analog front end also provides the following: • Four current and voltage clamp control loops to ensure that dc offsets are removed from the video signal • SCART functionality and standard definition (SD) RGB overlay on CVBS controlled by the fast blank (FB) input • Four internal antialiasing filters to remove out-of-band noise on standard definition input video signals STANDARD DEFINITION PROCESSOR (SDP) PIXEL DATA OUTPUT MODES The ADV7181D features the following SDP pixel data output modes: • 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD • 16-/20-bit 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD COMPONENT PROCESSOR (CP) PIXEL DATA OUTPUT MODES The ADV7181D features the following CP pixel data output modes for single data rate (SDR) and double data rate (DDR): • SDR 8-/10-bit 4:2:2 YCrCb for 525i and 625i • SDR 16-/20-bit 4:2:2 YCrCb for all standards • DDR 8-/10-bit 4:2:2 YCrCb for all standards • DDR 12-bit 4:4:4 RGB for graphics inputs Data Sheet COMPOSITE AND S-VIDEO PROCESSING Composite and S-Video processing features offer support for NTSC M/J, NTSC 4.43, PAL B/D/I/G/H, PAL60, PAL M, PAL N, and SECAM (B, D, G, K, and L) standards in the form of CVBS and S-Video. Superadaptive, 2D, five-line comb filters for NTSC and PAL provide superior chrominance and luminance separation for composite video. Composite and S-Video processing features also include full automatic detection and autoswitching of all worldwide standards (PAL, NTSC, and SECAM) and automatic gain control (AGC) with white peak mode to ensure that the video is always processed without loss of the video processing range. Other features include • Adaptive Digital Line Length Tracking (ADLLT™), a proprietary architecture for locking to weak, noisy, and unstable sources from VCRs and tuners • IF filter block to compensate for high frequency luma attenuation due to tuner SAW filter • Chroma transient improvement (CTI) • Luminance digital noise reduction (DNR) • Color controls including hue, brightness, saturation, contrast, and Cr and Cb offset controls • Certified Macrovision® copy protection detection on composite and S-Video for all worldwide formats (PAL/NTSC/SECAM) • 4× oversampling (54 MHz) for CVBS, S-Video, and YUV modes • Line-locked clock (LLC) output • Letterbox detection support • Free-run output mode to provide stable timing when no video input is present • Vertical blanking interval (VBI) data processor, including teletext, video programming system (VPS), vertical interval time codes (VITC), closed captioning (CC), extended data service (XDS), wide screen signaling (WSS), copy generation management system (CGMS), and compatibility with GemStar® 1×/2× electronic program guide • Clocked from a single 28.63636 MHz crystal • Subcarrier frequency lock (SFL) output for downstream video encoder • Differential gain, typically 0.5% • Differential phase, typically 0.5° Rev. 0 | Page 12 of 24 Data Sheet COMPONENT VIDEO PROCESSING Component video processing supports formats including 525i, 625i, 525p, 625p, 720p, 1080i, and many other HD formats, as well as automatic adjustments that include gain (contrast) and offset (brightness), and manual adjustment controls. Other features supported by component video processing include • Analog component YPrPb/RGB video formats with embedded synchronization or with separate HS, VS, or CS • Color space conversion matrix to support YCrCb-to-DDR RGB and RGB-to-YCrCb conversions • Standard identification (STDI) to enable system level component format detection • Synchronization source polarity detector (SSPD) to determine the source and polarity of the synchronization signals that accompany the input video • Certified Macrovision copy protection detection on component formats (525i, 625i, 525p, and 625p) • Free-run output mode to provide stable timing when no video input is present • Arbitrary pixel sampling support for nonstandard video sources RGB GRAPHICS PROCESSING RGB graphics processing offers a 75 MSPS conversion rate that supports RGB input resolutions up to 1024 × 768 at 70 Hz (XGA), automatic or manual clamp and gain controls for graphics modes, and contrast and brightness controls. Other features include • 32-phase DLL to allow optimum pixel clock sampling • Automatic detection of synchronization source and polarity by SSPD block • Standard identification enabled by the STDI block • RGB that can be color space converted to YCrCb and decimated to a 4:2:2 format for videocentric back-end IC interfacing • Data enable (DE) output signal supplied for direct connection to HDMI®/DVI transmitter IC • Arbitrary pixel sampling support for nonstandard video sources • RGB graphics supported on 12-bit DDR format ADV7181D GENERAL FEATURES The ADV7181D features HS/CS, VS, and FIELD/DE output signals with programmable position, polarity, and width, as well as a programmable interrupt request output pin, INT, that signals SDP/CP status changes. Other features include • Low power consumption: 1.8 V digital core, 3.3 V analog and digital I/O, low power, power-down mode, and green PC mode • Industrial temperature range of −40°C to +85°C • 64-lead, 9 mm × 9 mm, Pb-free LFCSP • 3.3 V ADCs giving enhanced dynamic range and performance Rev. 0 | Page 13 of 24 ADV7181D DETAILED DESCRIPTIONS ANALOG FRONT END The ADV7181D analog front end comprises four 10-bit ADCs that digitize the analog video signal before applying it to the SDP or CP. The analog front end uses differential channels to each ADC to ensure high performance in a mixed-signal application. The front end also includes a 10-channel input mux that enables multiple video signals to be applied to the ADV7181D. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping in either the CP or SDP. Optional antialiasing filters are positioned in front of each ADC. These filters can be used to band-limit standard definition video signals, removing spurious out-of-band noise. The ADCs are configured to run in 4× oversampling mode when decoding composite and S-Video inputs; 2× oversampling is performed for component 525i, 625i, 525p, and 625p sources. All other video standards are 1× oversampled. Oversampling the video signals reduces the cost and complexity of external antialiasing filters with the benefit of an increased signal-tonoise ratio (SNR). The ADV7181D can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and RGB inputs can be mixed and output under the control of the I2C registers and the fast blank (FB) pin. STANDARD DEFINITION PROCESSOR (SDP) The SDP section is capable of decoding a large selection of baseband video signals in composite, S-Video, and YUV formats. The video standards supported by the SDP include PAL B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7181D automatically detects the video standard and processes it accordingly. The SDP has a five-line, superadaptive, 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standards and signal quality with no user intervention required. The SDP has an IF filter block that compensates for attenuation in the high frequency luma spectrum due to the tuner SAW filter. The SDP has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue. The ADV7181D implements a patented ADLLT algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7181D to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. Data Sheet The SDP also contains a chroma transient improvement (CTI) processor. This processor increases the edge rate on chroma transitions, resulting in a sharper video image. The SDP can process a variety of VBI data services, such as teletext, closed captioning (CC), wide screen signaling (WSS), video programming system (VPS), vertical interval time codes (VITC), copy generation management system (CGMS), GemStar 1×/2×, and extended data service (XDS). The ADV7181D SDP section has a Macrovision 7.1 detection circuit that allows it to detect Type I, Type II, and Type III protection levels. The decoder is also fully robust to all Macrovision signal inputs. COMPONENT PROCESSOR (CP) The CP section is capable of decoding and digitizing a wide range of component video formats in any color space. Component video standards supported by the CP are 525i, 625i, 525p, 625p, 720p, 1080i, graphics up to XGA at 70 Hz, and many other standards. The CP section of the ADV7181D contains an AGC block. When no embedded synchronization is present, the video gain can be set manually. The AGC section is followed by a digital clamp circuit, which ensures that the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness); manual adjustment controls are also supported. A fixed mode graphics RGB to component output is available. A color space conversion matrix is placed between the analog front end and the CP section. This enables YCrCb-to-DDR RGB and RGB-to-YCrCb conversions. Many other standards of color space can be implemented using the color space converter. The output section of the CP is highly flexible. It can be configured in SDR mode with one data packet per clock cycle or in DDR mode where data is presented on the rising and falling edges of the clock. In SDR and DDR modes, HS/CS, VS, and FIELD/DE (where applicable) timing reference signals are provided. In SDR mode, a 20-bit 4:2:2 is possible. In DDR mode, the ADV7181D can be configured in an 8-bit or 10-bit 4:2:2 YCrCb or in a 12-bit 4:4:4 RGB pixel output interface with corresponding timing signals. The CP section contains circuitry to enable the detection of Macrovision encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals. VBI extraction of component data is performed by the CP section of the ADV7181D for interlaced, progressive, and high definition scanning rates. The data extracted can be read back over the I2C interface. Rev. 0 | Page 14 of 24 Data Sheet ADV7181D ANALOG INPUT MUXING The ADV7181D has an integrated analog muxing section, which allows more than one source of video signal to be connected to the decoder. Figure 7 outlines the overall structure of the input muxing provided in the ADV7181D. ADC_SW_MAN_EN AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 1 ADC0_SW[3:0] ADC0 1 ADC1_SW[3:0] ADC1 AIN3 AIN6 AIN7 AIN8 AIN9 AIN10 1 ADC2_SW[3:0] ADC2 AIN1 AIN6 Figure 7. Internal Pin Connections 1 ADC3_SW[3:0] ADC3 09994-007 Rev. 0 | Page 15 of 24 ADV7181D Table 8 provides the recommended ADC mapping for the ADV7181D. Table 8. Recommended ADC Mapping Mode Required ADC Mapping CVBS ADC0 Analog Input Channel CVBS = AIN1 Core SDP YC/YC Auto Y = ADC0 Y = AIN7 SDP C = ADC1 C = AIN9 Component YUV Y = ADC0 Y = AIN10 SDP U = ADC2 U = AIN8 V = ADC1 V = AIN6 Component YUV Y = ADC0 Y = AIN10 CP U = ADC2 U = AIN8 V = ADC1 V = AIN6 SCART RGB CBVS = ADC0 CVBS = AIN4 SDP G = ADC1 G = AIN10 B = ADC3 B = AIN6 R = ADC2 R = AIN8 Graphics G = ADC0 G = AIN2 CP RGB Mode B = ADC2 B = AIN3 R = ADC1 R = AIN5 1 Configuration to format follow-on blocks in correct frame. Data Sheet Configuration1 INSEL[3:0] = 0000 SDM_SEL[1:0] = 00 PRIM_MODE[3:0] = 0000 VID_STD[3:0] = 0010 INSEL[3:0] = 0000 SDM_SEL[1:0] = 11 PRIM_MODE[3:0] = 0000 VID_STD[3:0] = 0010 INSEL[3:0] = 1001 SDM_SEL[1:0] = 00 PRIM_MODE[3:0] = 0000 VID_STD[3:0] = 0010 INSEL[3:0] = 0000 SDM_SEL[1:0] = 00 PRIM_MODE[3:0] = 0000 VID_STD[3:0] = 1010 INSEL[3:0] = 0000 SDM_SEL[1:0] = 00 PRIM_MODE[3:0] = 0000 VID_STD[3:0] = 0010 INSEL[3:0] = 0000 SDM_SEL[1:0] = 00 PRIM_MODE[3:0] = 0010 VID_STD[3:0] = 1100 Rev. 0 | Page 16 of 24 Data Sheet The analog input muxes of the ADV7181D must be controlled directly. This is referred to as manual input muxing. The manual muxing is activated by setting the ADC_SW_MAN_EN bit (see Table 9). It affects only the analog switches in front of the ADCs. The INSEL, SDM_SEL, PRIM_MODE, and VID_STD bits must still be set so that the follow-on blocks process the video data in the correct format. Not every input pin can be routed to any ADC. The analog signal routing inside the IC imposes restrictions on the channel routing. See Table 9 for an overview of the routing capabilities inside the chip. The four mux sections can be controlled by the reserved control signal buses ADC0_SW[3:0], ADC1_SW[3:0], ADC2_SW[3:0], and ADC3_SW[3:0]. ADV7181D Table 9 explains the ADC mapping configuration for the following: • ADC_SW_MAN_EN, manual input muxing enable, IO map, Address C4[7] • ADC0_SW[3:0], ADC0 mux configuration, IO map, Address C3[3:0] • ADC1_SW[3:0], ADC1 mux configuration, IO map, Address C3[7:4] • ADC2_SW[3:0], ADC2 mux configuration, IO map, Address C4[3:0] • ADC3_SW[3:0], ADC3 mux configuration, IO map, Address F3[7:4] Table 9. Manual MUX Settings for All ADCs ADC0_SW[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC0 Connection N/A AIN2 AIN3 AIN5 AIN6 AIN8 AIN10 N/A N/A AIN1 N/A AIN4 N/A AIN7 AIN9 N/A ADC1_SW[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC_SW_MAN_EN = 1 ADC1 Connection ADC2_SW[3:0] N/A 0000 N/A 0001 N/A 0010 AIN5 0011 AIN6 0100 AIN8 0101 AIN10 0110 N/A 0111 N/A 1000 N/A 1001 N/A 1010 AIN4 1011 N/A 1100 AIN7 1101 AIN9 1110 N/A 1111 ADC2 Connection N/A N/A AIN3 N/A AIN6 AIN8 AIN10 N/A N/A N/A N/A N/A N/A AIN7 AIN9 N/A ADC3_SW[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC3 Connection N/A N/A N/A N/A AIN6 N/A N/A N/A N/A AIN1 N/A N/A N/A N/A N/A N/A Rev. 0 | Page 17 of 24 ADV7181D PIXEL OUTPUT FORMATTING Table 10. SDP Output Formats—SDR 4:2:2 (8-/10-/16-/20-Bit) 8-Bit SDR Pixel Output Pin ITU-R BT.656 10-Bit SDR ITU-R BT.656 P19 Y7, Cb7, Cr7 Y9, Cb9, Cr9 P18 Y6, Cb6, Cr6 Y8, Cb8, Cr8 P17 Y5, Cb5, Cr5 Y7, Cb7, Cr7 P16 Y4, Cb4, Cr4 Y6, Cb6, Cr6 P15 Y3, Cb3, Cr3 Y5, Cb5, Cr5 P14 Y2, Cb2, Cr2 Y4, Cb4, Cr4 P13 Y1, Cb1, Cr1 Y3, Cb3, Cr3 P12 Y0, Cb0, Cr0 Y2, Cb2, Cr2 P11 High-Z Y1, Cb1, Cr1 P10 High-Z Y0, Cb0, Cr0 P9 High-Z High-Z P8 High-Z High-Z P7 High-Z High-Z P6 High-Z High-Z P5 High-Z High-Z P4 High-Z High-Z P3 High-Z High-Z P2 High-Z High-Z P1 High-Z High-Z P0 High-Z High-Z 16-Bit SDR Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 High-Z High-Z Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 High-Z High-Z Data Sheet 20-Bit SDR Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb9, Cr9 Cb8, Cr8 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 Table 11. CP Output Formats—SDR 4:2:2 (16-/20-Bit) and DDR 4:4:4 (12-Bit) SDR 4:2:2 Pixel Output 16-Bit SDR 20-Bit SDR Clock Rise P19 Y7 Y9 B7-0 P18 Y6 Y8 B6-0 P17 Y5 Y7 B5-0 P16 Y4 Y6 B4-0 P15 Y3 Y5 B3-0 P14 Y2 Y4 B2-0 P13 Y1 Y3 B1-0 P12 Y0 Y2 B0-0 P11 High-Z Y1 High-Z P10 High-Z Y0 High-Z P9 Cb7, Cr7 Cb9, Cr9 G3-0 P8 Cb6, Cr6 Cb8, Cr8 G2-0 P7 Cb5, Cr5 Cb7, Cr7 G1-0 P6 Cb4, Cr4 Cb6, Cr6 G0-0 P5 Cb3, Cr3 Cb5, Cr5 High-Z P4 Cb2, Cr2 Cb4, Cr4 High-Z P3 Cb1, Cr1 Cb3, Cr3 High-Z P2 Cb0, Cr0 Cb2, Cr2 High-Z P1 High-Z Cb1, Cr1 High-Z P0 High-Z Cb0, Cr0 High-Z 1 xx-0 corresponds to data clocked at the rising edge; xx-1 corresponds to data clocked at the falling edge. 12-Bit DDR 4:4:41 Clock Fall R3-1 R2-1 R1-1 R0-1 G7-1 G6-1 G5-1 G4-1 High-Z High-Z R7-1 R6-1 R5-1 R4-1 High-Z High-Z High-Z High-Z High-Z High-Z Rev. 0 | Page 18 of 24 Data Sheet ADV7181D RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS The external loop filter components for the ELPF pin should be placed as close to the pin as possible. Figure 8 shows the recommended component values. ELPF 30 1.69kΩ 10nF 82nF PVDD = 1.8V Figure 8. ELPF Components 09994-008 Rev. 0 | Page 19 of 24 ADV7181D TYPICAL CONNECTION DIAGRAM Data Sheet 09994-009 Figure 9. Typical Connection Rev. 0 | Page 20 of 24 Data Sheet ADV7181D OUTLINE DIMENSIONS PIN 1 INDICATOR 9.00 BSC SQ TOP VIEW 0.60 MAX 0.60 MAX 49 48 64 1 PIN 1 INDICATOR 8.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 7.25 7.10 SQ 6.95 1.00 12° MAX 0.85 0.80 SEATING PLANE 0.50 0.40 33 32 0.30 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.20 REF 7.50 REF 16 17 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 10. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters 080108-C ORDERING GUIDE Model1, 2 ADV7181DBCPZ ADV7181DBCPZ-RL ADV7181DWBCPZ ADV7181DWBCPZ-RL EVAL-ADV7181DEBZ Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. Package Description 64-Lead LFCSP 64-Lead LFCSP 64-Lead LFCSP 64-Lead LFCSP Evaluation Board Package Option CP-64-3 CP-64-3 CP-64-3 CP-64-3 AUTOMOTIVE PRODUCTS The ADV7181DW models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. 0 | Page 21 of 24 ADV7181D NOTES Data Sheet Rev. 0 | Page 22 of 24 Data Sheet NOTES ADV7181D Rev. 0 | Page 23 of 24 ADV7181D NOTES Data Sheet I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09994-0-12/11(0) Rev. 0 | Page 24 of 24

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