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    DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz Check for Samples: DS92LV18 FEATURES 1 •2 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput) • Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data) • Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks • Line and Local Loopback Modes • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI • No External Coding Required • Internal PLL, No External PLL Components Required • Single +3.3V Power Supply • Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern • ±100 mV Receiver Input Threshold • Loss of Lock Detection and Reporting Pin • Industrial −40 to +85°C Temperature Range • >2.0kV HBM ESD • Compact, Standard 80-Pin LQFP Package DESCRIPTION The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side. The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Block Diagram www.ti.com Figure 1. DS92LV18 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1)(2) Supply Voltage (VCC) LVCMOS/LVTTL Input Voltage LVCMOS/LVTTL Output Voltage Bus LVDS Receiver Input Voltage Bus LVDS Driver Output Voltage Bus LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 seconds) Maximum Package Power Dissipation Capacity Package Derating: ESD Rating (HBM) 80L LQFP θJA θJC −0.3V to +4V −0.3V to (VCC +0.3V) −0.3V to (VCC +0.3V) −0.3V to +3.9V −0.3V to +3.9V 10ms +150°C −65°C to +150°C +260°C 23.2 mW/°C above +25°C 43°C/W 11.1°C/W >2.0kV (1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Recommended Operating Conditions Supply Voltage (VCC) Operating Free Air Temperature (TA) Clock Rate Supply Noise Min Nom Max Units 3.15 3.3 3.45 V −40 +25 +85 °C 15 66 MHz 100 mV (p-p) 2 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min LVCMOS/LVTTL DC Specifications VIH High Level Input Voltage DEN, TCLK, TPWDN, 2.0 VIL Low Level Input Voltage VCL Input Clamp Voltage ICL = −18 mA DIN, SYNC, RCLK_R/F, REN, REFCLK, GND IIN Input Current VIN = 0V or 3.6V RPWDN −10 VOH High Level Output Voltage IOH = −9 mA 2.3 VOL Low Level Output Voltage IOL = 9 mA ROUT, RCLK, LOCK GND IOS Output Short Circuit Current VOUT = 0V −15 PWRDN or REN = IOZ TRI-STATE Output Current 0.8V, VOUT = 0V or ROUT, RCLK −10 VCC Bus LVDS DC specifications VTH (2) VTL (2) IIN VOD (2) ΔVOD (2) Differential Threshold High Voltage Differential Threshold Low Voltage Input Current Output Differential Voltage (DO+) - (DO-) Output Differential Voltage Unbalance VCM = +1.1V VIN = +2.4V, VCC = 3.6V or 0V VIN = 0V, VCC = 3.6V or 0V Figure 19,(3), RL = 100Ω RI+, RI- −100 −10 −10 350 VOS Offset Voltage 1.05 ΔVOS Offset Voltage Unbalance DO = 0V, Din = H, DO+, DO- IOS Output Short Circuit Current TPWDN and DEN = -35 2.4V TPWDN or DEN = IOZ TRI-STATE Output Current 0.8V, DO = 0V OR -10 VDD IOX Power-Off Output Current VDD = 0V, DO = 0V or 3.6V -10 SER/DES SUPPLY CURRENT (DVDD, PVDD and AVDD pins) ICCT Total Supply Current (includes load current) CL = 15pF, RL = 100 Ω CL = 15 pF, RL = 100 Ω f = 66 MHz, PRBS-15 pattern f = 66 MHz, Worst case pattern (Checker-board pattern) ICCX Supply Current Powerdown PWRDN = 0.8V, REN = 0.8V Typ (1) Max Units -0.7 ±2 3.0 0.33 −48 ±0.4 VCC V 0.8 V −1.5 V +10 μA VCC V 0.5 V −85 mA +10 μA +100 mV mV ±5 +10 μA ±5 +10 μA 500 550 mV 2 15 mV 1.2 1.25 V 2.7 15 mV -50 -70 mA ±1 10 µA ±1 10 µA 190 mA 220 320 mA 1.5 3.0 mA (1) Typical values are given for VCC = 3.3V and TA = +25°C. (2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. (3) The VOD specification is a measurement of the difference between the single-ended VOH and VOL output voltages across a100 ohm load. Applying the formula OUT+ - OUT- to the differential outputs will result in a waveform with peak to peak amplitude equal to twice the datasheet indicated VOD. Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS92LV18 Submit Documentation Feedback 3 DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max tTCP tTCIH tTCIL tCLKT Transmit Clock Period Transmit Clock High Time Transmit Clock Low Time TCLK Input Transition Time 15.2 0.4T 0.4T T 0.5T 0.5T 3 66.7 0.6T 0.6T 6 tJIT TCLK Input Jitter See (1) 80 (1) Specified by Design (SBD) using statistical analysis. Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ tLLHT Bus LVDS Low-to-High Transition Time Figure 4,(1) 0.2 tLHLT Bus LVDS High-to-Low Transition Time RL = 100Ω, CL=10pF to GND 0.2 tDIS DIN (0-17) Setup to TCLK Figure 7,(1) 2.4 tDIH DIN (0-17) Hold from TCLK RL = 100Ω, CL=10pF to GND 0 tHZD DO ± HIGH to TRI-STATE Delay 2.3 tLZD DO ± LOW to TRI-STATE Delay Figure 8(2) RL = 100Ω, 1.9 tZHD DO ± TRI-STATE to HIGH Delay CL=10pF to GND 1.0 tZLD DO ± TRI-STATE to LOW Delay 1.0 tSPW tPLD tSD tRJIT SYNC Pulse Width Serializer PLL Lock Time Serializer Delay Random Jitter Figure 10, RL = 100Ω Figure 9, RL = 100Ω Figure 11, RL = 100Ω Room Temp., 3.3V, 66 MHz 5*tTCP 510*tTCP tTCP + 1.0 tTCP + 2.0 4.5 tDJIT Deterministic Jitter Figure 17,(1) 15 MHz 66 MHz -430 -40 Max 0.4 0.4 10 10 10 10 6*tTCP 1024*tTCP tTCP + 4.0 190 70 (1) Specified by Design (SBD) using statistical analysis. (2) Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer. Deserializer Timing Requirements for REFCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max tRFCP tRFDC tRFCP / tTCP tRFTT REFCLK Period REFCLK Duty Cycle Ratio of REFCLK to TCLK REFCLK Transition Time 15.2 T 66.7 40 50 60 0.95 1.05 6 Units ns ns ns ns ps (RMS) Units ns ns ns ns ns ns ns ns ns ns ns ps (RMS) ps ps Units ns % ns 4 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated www.ti.com DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ tRCP Receiver out Clock Period tRCP = tTCP RCLK 15.2 tRDC tCLH tCHL tROS tROH RCLK Duty Cycle CMOS/TTL Low-toHigh Transition Time CMOS/TTL High-toLow Transition Time ROUT (0-9) Setup Data to RCLK ROUT (0-9) Hold Data to RCLK CL = 15 pF Figure 5 Figure 13 RCLK ROUT(0-17), LOCK, RCLK 45 0.35*tRCP −0.35*tRCP 50 2.2 2.2 0.5*tRCP −0.5*tRCP tHZR HIGH to TRI-STATE Delay 2.2 tLZR LOW to TRI-STATE Delay tZHR TRI-STATE to HIGH Delay Figure 14 ROUT(0-17), LOCK 2.2 2.3 tZLR TRI-STATE to LOW Delay 2.9 tDD tDSR1 (1) Deserializer Delay Deserializer PLL Lock Time from Powerdown (with SYNCPAT) Figure 15, (2) (3) RCLK 15MHz 66 MHz 1.75*tRCP + 2.1 1.75*tRCP + 4.0 3.7 1.9 tDSR2 (1) Deserializer PLL Lock time from SYNCPAT Figure 16, (2) (3) 15MHz 66 MHz 1.5 0.9 tRNMI-R Ideal Deserializer Noise Margin Right Figure 18 (4) (3) 15 MHz 66 MHz tRNMI-L Ideal Deserializer Noise Margin Left Figure 18 (4) (3) 15 MHz 66 MHz tJI Total Interconnect Jitter Budget See (5) 15 MHz 66 MHz Max Units 66.7 ns 55 % 4 ns 4 ns ns ns 10 ns 10 ns 10 ns 10 ns 1.75*tRCP + 6.1 ns 10 μs 4 μs 5 μs 2 μs 1490 ps 180 ps 1460 ps 330 ps 1060 ps 160 ps (1) tDSR1 is the time required by the deserializer to obtain lock when exiting powerdown mode. tDSR1 is specified with synchronization patterns (SYNCPATs) present at the LVDS inputs (RI+ and RI-) before exiting powerdown mode. tDSR2 is the time required to obtain lock for the powered-up and enabled deserializer when the LVDS input (RI+ and RI-) conditions change from not receiving data to receiving synchronization patterns. Both tDSR1 and tDSR2 are specified with the REFCLK running and stable. (2) A sync pattern is a fixed pattern with 9-bits of data high followed by 9-bits of data low. The SYNC pattern is automatically generated by the transmitter when the SYNC pin is pulled high. (3) Specified by Design (SBD) using statistical analysis. (4) tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail. (5) Total Interconnect Jitter Budget (tJI) specifies the allowable jitter added by the interconnect assuming both transmitter and receiver are DS92LV18 circuits. tJI is GBD using statistical analysis. Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS92LV18 Submit Documentation Feedback 5 DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 AC Timing Diagrams and Test Circuits www.ti.com Figure 2. “Worst Case” Serializer ICC Test Pattern Figure 3. “Worst Case” Deserializer ICC Test Pattern Figure 4. Serializer Bus LVDS Distributed Output Load and Transition Times Figure 5. Deserializer CMOS/TTL Distributed Output Load and Transition Times Figure 6. Serializer Input Clock Transition Time 6 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated www.ti.com DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Figure 7. Serializer Setup/Hold Times Figure 8. Serializer TRI-STATE Test Circuit and Timing Figure 9. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS92LV18 Submit Documentation Feedback 7 DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Figure 10. SYNC Timing Delay Figure 11. Serializer Delay Figure 12. Deserializer Delay Figure 13. Deserializer Setup and Hold Times 8 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated www.ti.com DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Figure 14. Deserializer TRI-STATE Test Circuit and Timing Figure 15. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS92LV18 Submit Documentation Feedback 9 DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Figure 16. Deserializer PLL Lock Time from SYNCPAT Figure 17. Deterministic Jitter and Ideal Bit Position tRNMI-L is the noise margin on the left of the figure above. tRNMI-R is the noise margin on the right of the above figure. Figure 18. Deserializer Noise Margin (tRNMI) and Sampling window 10 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated www.ti.com DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 VOD = (DO+)–(DO−). Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. Figure 19. VOD Diagram CURRENT (mA) 110 90 90 3.45V 80 70 60 3.30V 3.15V 50 50 40 30 10 10 20 30 40 50 60 70 FREQUENCY (MHz) Figure 20. Typical ICC vs. Frequency with PRBS-15 Pattern (Transmitter Only) 110 110 3.45V 90 100 CURRENT (mA) 70 60 50 30 30 50 3.15V 3.30V 10 10 20 30 40 50 60 70 FREQUENCY (MHz) Figure 21. Typical ICC vs. Frequency with PRBS-15 Pattern (Receiver Only) Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS92LV18 Submit Documentation Feedback 11 DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION www.ti.com The DS92LV18 combines a serializer and deserializer onto a single chip. The serializer accepts an 18-bit LVCMOS or LVTTL data bus and transforms it into a BLVDS serial data stream with embedded clock information. The deserializer then recovers the clock and data to deliver the resulting 18-bit wide words to the output. The device has a separate transmit block and receive block that can operate independently of each other. Each has a power down control to enable efficient operation in various applications. For example, the transceiver can operate as a standby in a redundant data path but still conserve power. The part can be configured as a Serializer, Deserializer, or as a Full Duplex SER/DES. The DS92LV18 serializer and deserializer blocks each have three operating states. They are the Initialization, Data Transfer, and Resynchronization states. In addition, there are two passive states: Powerdown and TRISTATE. The following sections describe each operation mode and passive state. Initialization Before the DS92LV18 sends or receives data, it must initialize the links to and from another DS92LV18. Initialization refers to synchronizing the Serializer's and Deserializer's PLL's to local clocks. The local clocks must be the same frequency or within a specified range if from different sources. After the Serializers synchronize to the local clocks, the Deserializers synchronize to the Serializers as the second and final initialization step. Step 1: When VCC is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE and internal circuitry is disabled by on-chip power-on circuitry. When VCC reaches VCC OK (2.2V) the PLL in each device begins locking to a local clock. For the Serializer, the local clock is the transmit clock, TCLK. For the Deserializer, the local clock is applied to the REFCLK pin. A local on-board oscillator or other source provides the specified clock input to the TCLK and REFCLK pin. The Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer block is now ready to send data or synchronization patterns. If the SYNC pin is high, then the Serializer block generates and sends the synchronization patterns (sync-pattern). The Deserializer output will remain in TRI-STATE while its PLL locks to the REFCLK. Also, the Deserializer LOCK output will remain high until its PLL locks to incoming data or a sync-pattern on the RIN pins. Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. The Serializer that is generating the stream to the Deserializer must send random (non-repetitive) data patterns or sync-patterns during this step of the Initialization State. The Deserializer will lock onto sync-patterns within a specified amount of time. The lock to random data depends on the data patterns and therefore, the lock time is unspecified. In order to lock to the incoming LVDS data stream, the Deserializer identifies the rising clock edge in a syncpattern and locks to it. If the Deserializer is locking to a random data stream from the Serializer, then it performs a series of operations to identify the rising clock edge and locks to it. Because this locking procedure depends on the data pattern, it is not possible to specify how long it will take. At the point when the Deserializer's PLL locks to the embedded clock, the LOCK pin goes low and valid data appears on the output. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The user's application determines whether SYNC or lock-to-random-data mode is the preferred method for synchronization. If sync-patterns are preferred, the associated Deserializer’s LOCK pin is a convenient way to provide control of the Serializer’s SYNC pin. Data Transfer After initialization, the DS92LV18 Serializer is able to transfer data to the Deserializer. The serial data stream includes a start bit and stop bit appended by the serializer, which frames the eighteen data bits. The start bit is always high and the stop bit is always low. The start and stop bits also function as clock bits embedded in the serial stream. The Serializer block accepts data from the DIN0-DIN17 parallel inputs. The TCLK signal latches the incoming data on the rising edge. If the SYNC input is high for 6 TCLK cycles, the DS92LV18 does not latch data from DIN0-DIN17. 12 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 The Serializer transmits the data and clock bits (18+2 bits) at 20 times the TCLK frequency. For example, if TCLK is 60 MHz, the serial rate is 60 X 20= 1200 Mbps. Since only 18 bits are from input data, the serial 'payload' rate is 18 times the TCLK frequency. For instance, if TCLK = 60 MHz, the payload data rate is 60 X 18 = 1080 Mbps. TCLK is provided by the data source and must be in the range of 15 MHz to 66 MHz. When the Deserializer channel synchronizes to the input from a Serializer, it drives its LOCK pin low and synchronously delivers valid data on the output. The Deserializer locks to the embedded clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin. The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[0:17] pins. While LOCK is low, data on ROUT[0:17] is valid. Otherwise, ROUT[0:17] is invalid. ROUT[0:17], LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF total load) at a 66 MHz clock rate. This drive capacity allows bussing outputs of multiple Deserializers to multiple destination ASIC inputs. REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer. The Deserializer input pins are high impedance during receiver powerdown (RPWDN low) and power-off (VCC = 0V). Resynchronization If the Deserializer loses lock, it will automatically try to resynchronize. For example, if the embedded clock edge is not detected two times in succession, the PLL loses lock and the LOCK pin is driven high. The Deserializer then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock edge, identifies it and then proceeds through the synchronization process. The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is low, the data is valid. The system must monitor the LOCK pin to determine whether data on the ROUT is valid. Because there is a short delay in the LOCK signal’s response to the PLL losing synchronization to the incoming data stream, the system must determine the validity of data for the cycles before the LOCK signal goes high. The user can choose to resynchronize to the random data stream or to force fast synchronization by pulsing the Serializer’s SYNC pin. Lock times depend on serial data stream characteristics. The primary constraint on the "random" lock time is the initial phase relation between the incoming data and the REFCLK when the Deserializer powers up. An advantage of using the SYNC pattern to force synchronization is the ability for the user to predict the delay before the PLL regains lock. This scheme is left up to the user discretion. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer, which is the SYNC pin. If a specific pattern is repetitive, the Deserializer’s PLL will not lock in order to prevent the Deserializer from locking to the data pattern rather than the clock. We refer to such pattern as a repetitive multi-transition, RMT. This occurs when more than one Low-High transition takes places in a clock cycle over multiple cycles. This occurs when any bit, except DIN 17, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. The internal circuitry accomplishes this by detecting more than one potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming active until the RMT pattern changes. Once the RMT pattern changes and the internal circuitry recognizes the clock bits in the serial data stream, the PLL of the Deserializer will lock, which will drive the LOCK output to low and the output data ROUTn will become valid. Powerdown The Powerdown state is a low power sleep mode that the Serializer and Deserializer will occupy while waiting for initialization. You can also use TPWDN and RPWDN to reduce power when there are no pending data transfers. The Deserializer enters powerdown mode when RPWDN is driven low. In powerdown mode, the PLL stops and the outputs enter TRI-STATE, which reduces supply current to the μA range. To bring the Deserializer block out of the Powerdown state, the system drives RPWDN high. When the Deserializer exits Powerdown, it automatically enters the Initialization state. The system must then allow time for Initialization before data transfer can begin. The TPWDN pin driven low forces the Serializer block into low power consumption, where the supply current is in the μA range. The Serializer PLL stops and the output goes into a TRI-STATE condition. Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS92LV18 Submit Documentation Feedback 13 DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com To bring the Serializer block out of the powerdown state, the system drives TPWDN high. When the Serializer exits Powerdown, its PLL must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before data transfer can begin. TRI-STATE When the system drives the REN pin low, the Deserializer’s outputs enter TRI-STATE. This will TRI-STATE the receiver output pins (ROUT[0:17]) and RCLK. When the system drives REN high, the Deserializer will return to the previous state as long as all other control pins remain static (RPWDN). When the system drives the DEN pin low, the Serializer’s LVDS outputs enter TRI-STATE. When the system drives the DEN signal high, the Serializer output will return to the previous state as long as all other control and data input pins remain in the same condition before DEN was driven low. Loopback Test Operation The DS92LV18 includes two Loopback modes for testing the device functionality and the transmission line continuity. Asserting the Line Loopback control signal connects the serial data input (RIN±) to the serial data output (DO±) and to the parallel data output (ROUT[0:17]). The serial data goes through deserializer and serializer blocks. Asserting the Local Loopback control signal connects the parallel data input (DIN[0:17]) back to the parallel data output (ROUT[0:17]). The connection route includes all the functional blocks of the SER/DES Pair. The serial data output (DO±) is automatically disabled during the Local Loopback operating mode. Please note that when switching between normal, line, or loopback modes, the deserializer will need to relock. In order for the serializer and deserializer to resync, the TCLK and REFCLK frequencies must be within ±5% of each other. Application Information USING THE DS92LV18 The DS92LV18 combines a Serializer and Deserializer onto a single chip that sends 18 bits of parallel TTL data over a serial Bus LVDS link up to 1.32 Gbps. Serialization of the input data is accomplished using an on-board PLL at the Serializer which embeds two clock bits with the data. The Deserializer uses a separate reference clock (REFCLK) and an on-board PLL to extract the clock information from the incoming data stream and deserialize the data. The Deserializer monitors the incoming clock information to determine lock status and will indicate loss of lock by asserting the LOCK output high. POWER CONSIDERATIONS An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the constant current source nature of the LVDS outputs minimize the slope of the speed vs. ICC curve of CMOS designs. POWERING UP THE DESERIALIZER The REFCLK input can be running before the Deserializer is powered up and it must be running in order for the Deserializer to lock to incoming data. The Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its inputs and locks to the incoming serial data stream. NOISE MARGIN The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably recover data. Various environmental and systematic factors include: Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise) Media: ISI, VCM noise Deserializer: VCC noise For a graphical representation of noise margin, please see Figure 18. 14 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 RECOVERING FROM LOCK LOSS In the case where the Serializer loses lock during data transmission, up to 5 cycles of data that were previously received could be invalid. This is due to a delay in the lock detection circuit. The lock detect circuit requires that invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been lost, it is possible that data was also lost during these cycles. If the Deserializer LOCK pin goes low, data from at least the previous 5 cycles should be resent upon regaining lock. Lock can be regained at the Deserializer by causing the Serializer to resend SYNC patterns as described above or by random data locking which can take more time depending upon the data patterns being received. INPUT FAILSAFE In the event that the Deserializer is disconnected from the Serializer, or the Deserializer loses lock, the failsafe circuitry is designed to reject a certain amount of noise from being interpreted as data or clock. The Deserializer outputs (ROUT [0:17] and RCLK) will be asserted HIGH. HOT INSERTION All of TI’s LVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s) makes contact first, then the VCC pin(s), then the I/O pin(s). When removing, the I/O pins should be unplugged first, then VCC, then Ground. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the BLVDS devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high-frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies above approximately 50MHz, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. It is a recommended practice to use two vias at each power pin as well as at all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. Locate RF capacitors as close as possible to the supply pins, and use wide low impedance traces (not 50 Ohm traces). Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate CMOS (TTL) signals away from the LVDS lines to prevent coupling from the CMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ohms are typically recommended for LVDS interconnect. The closely-coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS92LV18 Submit Documentation Feedback 15 DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at the load end. Nominal value is 100 Ohms to match the line's differential impedance. Place the resistor as close to the receiver inputs as possible to minimize the resulting stub between the termination resistor and receiver. Additional general guidance can be found in the LVDS Owner's Manual - available in PDF format from the TI web site at: www.ti.com/lvds. Specific guidance for this device is provided next. DS92LV18 BLVDS SER/DES PAIR General device specific guidance is given below. Exact guidance can not be given as it is dictated by other board level /system level criteria. This includes the density of the board, power rails, power supply, and other integrated circuit power supply needs. DVDD = DIGITAL SECTION POWER SUPPLY These pins supply the digital portion of the device as well as the receiver output buffers. The Deserializer’s DVDD requires more bypass to power the outputs under synchronous switching conditions. The Serializer’s DVDD is less critical. The receiver’s DVDD pins power 4 outputs from each DVDD pin. An estimate of local capacitance required indicates a minimum of 22nF is required. This is calculated by taking 4 times the maximum short current (4 X 70 = 280mA), multiplying by the rise time of the part (4ns), and dividing by the maximum allowed droop in VDD (assume 50mV) yields 22.4nF. Rounding up to a standard value, 0.1uF is selected for each DVDD pin. PVDD = PLL SECTION POWER SUPPLY The PVDD pin supplies the PLL circuit. Note that the DS92LV18 has two separate PLL and supply pins. The PLL(s) require clean power for the minimization of Jitter. A supply noise frequency in the 300 kHz to 1 MHz range can cause increased output jitter. Certain power supplies may have switching frequencies or high harmonic content in this range. If this is the case, filtering of this noise spectrum may be required. A notch filter response is best to provide a stable VDD, suppression of the noise band, and good high-frequency response (clock fundamental). This may be accomplished with a pie filter (CRC or CLC). If employed, a separate pie filter is recommended for each PLL to minimize drop in potential due to the series resistance. The pie filter should be located close to the PVDD power pin. Separate power planes for the PVDD pins is typically not required. AVDD = LVDS SECTION POWER SUPPLY The AVDD pins power the LVDS portion of the circuit. The DS92LV18 has four AVDD pins. Due to the nature of the design, current draw is not excessive on these pins. A 0.1uF capacitor is sufficient for these pins. If space is available, a 0.01uF capacitor may be used in parallel with the 0.1uF capacitor for additional high frequency filtering. GROUNDS The AGND pin should be connected to the signal common in the cable for the return path of any common-mode current. Most of the LVDS current will be odd-mode and return within the interconnect pair. A small amount of current may be even-mode due to coupled noise and driver imbalances. This current should return via a low impedance known path. A solid ground plane is recommended for both DVDD, PVDD or AVDD. Using a split plane may cause ground loops or a difference in ground potential at various ground pins of the device. 16 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated DS92LV18 www.ti.com TPWDN (Pin 42) L H H H RPWDN (Pin 01) L H H H SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Truth Tables Transmitter Truth Table DEN (Pin 19) TX PLL Status (Internal) LVDS Outputs (Pins 13 and 14) X X Hi Z L X Hi Z H Not Locked Hi Z H Locked Serialized Data with Embedded Clock Receiver Truth Table REN (Pin 02) RX PLL Status (Internal) ROUTn & RCLK (See Pin Diagram) LOCK (Pin 63) X X Hi Z Hi Z L X Hi Z L = PLL Locked; H = PLL Unlocked H Not Locked H H H Locked Data & CLK Active L Footprint Changes between the DS92LV16 and the DS92LV18 Pin Number 3 18 62 80 DS92LV16 vs. DS92LV18 Footprint Changes DS92LV16 CONFIG1 CONFIG2 DVDD DGND DS92LV18 DIN17 DIN16 ROUT16 ROUT17 PCB Compatibility Between the DS92LV16 and DS92LV18 Figure 22. Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS92LV18 Submit Documentation Feedback 17 DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Pin Diagram www.ti.com Figure 23. DS92LV18 80-Pin LQFP Top View 18 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated DS92LV18 www.ti.com SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 Table 1. PIN DESCRIPTIONS Pin # 1 2 4 5, 10, 11, 15 6,9,12,16 7 8 13 14 17 19 20 3, 18,21, 22, 23, 24, 25, 26, 27, 28, 33, 34, 35, 36, 37, 38, 39, 40 29,32 30,31 41, 44, 51, 52, 59, 60, 61, 68 42 43, 50, 53, 58, 69 45, 46, 47, 48, 54, 55, 56, 57, 62, 64, 65, 66, 67, 70, 71, 72, 73, 80 49 63 74,76 75,77 78 79 Pin Name RPWDN REN REFCLK AVDD AGND RIN+ RINDO+ DOTCLK DEN SYNC DIN (0:17) PGND PVDD DGND TPWDN DVDD ROUT (0:17) RCLK LOCK PGND PVDD LINE_LE LOCAL_LE I/O CMOS, I CMOS, I CMOS, I LVDS, I LVDS, I LVDS, O LVDS, O CMOS, I CMOS, I CMOS, I CMOS, I Description RPWDN = Low will put the Receiver in low power, stand-by, mode. Note: The Receiver PLL will lose lock.(1) REN = Low will disable the Receiver outputs. Receiver PLL remains locked. (See LOCK pin description)(1) Frequency reference clock input for the receiver. Analog Voltage Supply Analog Ground Receiver LVDS True Input Receiver LVDS Inverting Input Transmitter LVDS True Output Transmitter LVDS Inverting Output Transmitter reference clock. Used to strobe data at the DIN Inputs and to drive the transmitter PLL. See TCLK Timing Requirements. DEN = Low will disable the Transmitter outputs. The transmitter PLL will remain locked.(1) SYNC = High will cause the transmitter to ignore the data inputs and send SYNC patterns to provide a locking reference to receiver(s). See Functional Description.(1) Transmitter data inputs.(1) PLL Ground. PLL Voltage supply. Digital Ground. CMOS, I TPWDN = Low will put the Transmitter in low power, stand-by mode. Note: The transmitter PLL will lose lock.(1) Digital Voltage Supplies. CMOS, O Receiver Outputs. CMOS, O Recovered Clock. Parallel data rate clock recovered from embedded clock. Used to strobe ROUT (0:17). LVCMOS Level output. CMOS, O LOCK indicates the status of the receiver PLL. LOCK = H - receiver PLL is unlocked, LOCK = L - receiver PLL is locked. PLL Grounds. PLL Voltage Supplies. CMOS, I LINE_LE = High enables the receiver loopback mode. Data received at the RIN± inputs is fed back through the DO± outputs.(1) CMOS, I LOCAL_LE = High enables the transmitter loopback mode. Data received at the DIN inputs is fed back through the ROUT outputs.(1) (1) Input defaults to "low" state when left open due to an internal on-chip pull-down circuit. Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: DS92LV18 Submit Documentation Feedback 19 DS92LV18 SNLS156E – SEPTEMBER 2003 – REVISED APRIL 2013 REVISION HISTORY www.ti.com Changes from Revision D (April 2013) to Revision E Page • Changed layout of National Data Sheet to TI format .......................................................................................................... 19 20 Submit Documentation Feedback Product Folder Links: DS92LV18 Copyright © 2003–2013, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Jan-2015 PACKAGING INFORMATION Orderable Device DS92LV18TVV/NOPB DS92LV18TVVX/NOPB Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) ACTIVE LQFP PN 80 119 Green (RoHS & no Sb/Br) ACTIVE LQFP PN 80 1000 Green (RoHS & no Sb/Br) Lead/Ball Finish (6) CU SN | Call TI CU SN | Call TI MSL Peak Temp Op Temp (°C) (3) Level-3-260C-168 HR -40 to 85 Level-3-260C-168 HR -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Device Marking (4/5) DS92LV18TVV >B DS92LV18TVV >B (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 10-Jan-2015 Addendum-Page 2 PN (S-PQFP-G80) 0,50 60 61 MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PLASTIC QUAD FLATPACK 0,27 0,17 41 0,08 M 40 0,13 NOM 80 21 1 1,45 1,35 20 9,50 TYP 12,20 11,80 SQ 14,20 13,80 SQ 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 0,25 0,05 MIN 0,75 0,45 Seating Plane 0,08 Gage Plane 0°– 7° 4040135 / B 11/96 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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