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Fundamentals of Modern VLSI Devices (2nd Edition)

Tak Ning的经典教材

s = qX + Eg 2 + qlf/IJ. (2.169) Here If/B is the difference between the Fermi potential and the intrinsic potential given by Eq. (2,48). The same definition of work function, q 0), the current is dominated by the emission from the semiconductor into the metal. For a reverse-biased diode (Vapp < 0), the current is dominated by the emission from the metal into the semiconductor. Equation (2.242) shows that, when barrier lowering effect is ignored, a Schottky barrier diode has 1- V characteristics similar to those of a p-n diode [cf. Eq. (2.102)], with an exp(q J!.,p,Jk1) dependence on Vopp in forward bias, and a saturation current that is independent of V"pp in reverse bias. • Including Barrier Lowering Effect. There is a subtle difference between a Schottky diode and a p-n diode when barrier lowering effect is included When barrier lowering effect is included, the Schottky barrier qtPBn in Fig. 2.55 and in Eqs. (2.237) to (2.242) should be replaced by an effective Schottky barrier q(tPan - I1tP). The barrier-lowering term q I1tP depends on the applied voltage through the electric field ifm [see Eq. (2.232)]. As'discussed in Section 2.4.1.4, a forward bias (J!.,pp > 0) reduces ql1tP and hence increases the effective Schottky barrier, while a reverse bias (J!.,pp < 0) increases ql1tP and hence reduces the effective Schottky barrier. Thus, replacing q¢Bn by q(¢Bn -11¢) in Eq. (2.242) suggests that the forward-bias current ofa Schottky diode increases with v"pp at a rate somewhat slower than exp(q v"pJk1). This should be compared with the forward-bias current of a p-n diode which is proportional to exp(qVupplk1) [see (2.123)]. See also Fig. 2.23. In the literature, more complex theories have been proposed for describing the trans port process in Schottky diodes. There is a diffusion emission theory which includes the effect of electron collisions within the semiconductor depletion region. There is also a theory which combines the physics involved in the simple thermionic emission process and the diffusion emission process (Crowell and Sze, 1966a). All theories result in an equation similar to Eq. (2.242), with the difference only in the pre-exponential factor. The interested reader is referred to the literature for the details (Sze, 1981; Henisch, 1984). From a device point ofview, the important I-Vcharacteristics of a Schottky barrier diode are contained in the exponential factors in Eq. (2.242), namely in the exp(-q¢B"Ik1) dependence on q¢Bn and the [exp(qVapplk1) I] dependence on qv"pp. 2.4.3.2 Field Emission and Thermionic~field Emission If the semiconductor is heavily doped, the depletion region thickness will be thin, and the electron transport can become dominated by a combination of field emission and thermionic-field emission. In this case, large currents can flow even at low applied biases. In general, when field emission and thermionic-field emission dominate the electron transport, a metal-semiconductor contact is no longer useful as a rectifYing diode. As a result, we will not consider the general theory of field emission and thermionic-field emission any further. The interested reader is referred to the literature for details (Padovani and Stratton, 1966; Crowell and Rideout, 1969). 120 2 Basic Device Physics -r E --r jq1/Jm I-#«)Y-I E ,,& ~. ~ ,""u_-;~-w)UT-U--- x ~Ef Silicon 1---;::;:; Figure 2.57. Schematic showing the energy bands appropriate for considering field emission in a metal-silicon contact. As illustrated, the Schottky diode is forward biased, as indicated by the Fermi level in the silicon being higher than that in the metal. 2.4.3.3 Schottky Barrier Diode as an Active Device A rectifYing Schottky bamer diode has /-V characteristics similar to those ofa p-n diode, but a Schottky barrier diode is a much faster device than a p-n diode because it is a majority-carner device. As a result, Schottky barrier diodes are often used as microwave diodes and as gates ofmicrowave transistors where speed is important (see e.g., Irvin and Vanderwal, 1969). Also, Schottky barrier diodes are often added to bioolar circuits as voltage clamps to improve circuit speed. 2.4.4 Ohmic Contacts Ohmic contacts are usually made with metal or metal silicide in contact with doped semiconductor. The electron transport process in this case is dominated emission. Let us first consider the tunneling of a conduction-band electron from the quasineutral semiconductor region into the metal. The band bending near the metal semiconductor contact is illustrated in Fig. 2.57. The total band bending is qV'm = q(V'hi Vapp) when a forward bias of Vapp is applied. For a given V"",p, let us assume the conduction-band starts to bend upward at x 0, and the interface is located at x Wd, where Wd is the depletion-layer thickness. Since we are considering an electron in the conduction band, it is convenient to use the conduction-band edge of the quasineutral silicon region Ec{x < 0) as the energy reference, as indicated in Fig. 2.57. II/(X) is the electrostatic potential at location x relative to E,.{x < 0), i.e., -q!p(O) Ec(x < 0), and is thc potential energy ofan electron at location x. The Poisson equation [Eq. (2.44)1 can be integrated twice to give qNdx2 I/f(X ) 2cs; q (2.243) where is semiconductor doping concentration. From Eq. (2.188), we have 2.4 Metal-Silicon Contacts 121 (2.244) In the WK.B approximation for tunneling through an energy barner, the transmission coefficient through the energy barrier represented by -qV'(x) for an electron with energy E is [-4nJW exp I I x, d ~J-qV'(x) - Edx] W -4nI =exp - ,' ~Jq-2N-dX+ 2 [ h Xi 2os; <0) EdX]' (2.245) where the lower integration limit XI is given by -q!p(xl) E. In considering an ohmic contact, we are interested in the current due to electrons tunneling from the quasineutral region of the silicon through the potential barrier into the metal at small applied voltages. These electrons have only thermal energy (kT ~ 26 meV at room temperature) which is small compared to the maximum tunneling bamer height q(l/fbi - which is approximately equal to qV'bi at small Therefore, we can assume the tunneling electrons to have an energy E ~ Ec(x < 0). For these electrons, the tunneling process starts at x I = 0 and the corresponding transmission coefficient is where = Ec(x 0 or I < O. The directions of the currents are depicted in Fig. 5.2. 5.1 Basic CMOS Circuit Elements 259 VOlt, Vdd r--- .-..., Figure 5.4. Va., versus Vm curve (transfer curve) ofa CMOS inverter. Points labeled A, C, E, D, B correspond to the steady state points of operation (circles) indicated in Fig. 5.3(c). There are two points ofoperation where both II' and where and Vdd, and point B where Yin = Vdd and v"w= O. In between, the corresponding v"w is obtained from the intersection of two curves, IMVin) and IP(Yin), as shown in Fig. 5.3(c). In this way, one can construct a v"UI versus Yin curve, ora transfer curve ofthe CMOS inverter in Fig. 5.4. For low values of Yin such as point C, v"UI is high and the nMOSFET is biased in saturation while the pMOSFET is biased in the linear region [Vi"i in Fig. 5.3(c)]. For high Yin such as point D, v"w is low and the nMOSFET is in the linear region while the pMOSFET is in saturation in Fig. 5.3(c)). For point E near Yin Vdj2 [Vin2 in Fig. 5.3(c)], both devices are in saturation. It is in a transition region where v"., changes steeply with Yin. In order for the high-to-low transition of the transfer curve to occur close to the midpoint, Vin = Vd/2, it is desiredfor Ipand INto be nearly symmetrical, as illustrated in the example in Fig. 5.3. This requires the threshold voltages of the n- and pMOSFETs to be symmetrically matched. In addition, since the pMOSFETcurrent per width, Ip = [pi WI" is inherently lower than that of the nMOSFET, In = III Wm the device width ratio in a CMOS inverter should be Wp In (5.1) Wn lp' such that Ip-:::;IN• In the long-channe-1 limit, Inllp r:x PnlPp ~ 4 from Eq. (3.28) and Figs 3.15 and 3.16, assuming matched channel lengths and threshold voltages. For short-channel devices, however, the ratio is smaller since nMOSFETs are more saturated than pMOSFETs. Typically, the current-per-width ratio IJIp is about 2-2.5 for deep-submicron CMOS technologies; therefore, W/WI! =2 is a good-choice for CMOS inverter design. 5.1.1.2 CMOS Inverter Noise Because of the nonlinear saturation characteristics of the MOSFET curves, the curve is also nonlinear_ The maximum slope ofthe high-to-Iow transition 260 5 CMOS Performance Factors Flgure5.S. _____~~lJ;,,~outl ~V;n3 V~VO"12 ........... --'4." __ _ ........... Noise Noise Noise ........... Noise Voul4 -----...... Noise A cascade chain of identical CMOS inverters. The noise voltages at the input of each stage are for the discussion of Fig. 5.7. figure 5.6. Vdd .....1 ;/t'''''' _;/t"-'" .~"" ~~ JJ 1i .. ~~ ......, .,.' .........""...... .' ')-"'-'-~- - _,>,., .' , :"'.~ HU ••••••••• ac5l .// ! '\ .' ". / " ~: \ '. : : "\ 0o·" Solid: V;nl' V!n3 .... Dashed: v..a.V..,4'·" Vdd The solid transfer curve is for odd numbered inverter stages. The flipped, dashed !ransfer curve is for even numbered stages. The connected line segments between the curves depict the trajectory of node voltages through successive inverter stages. ofthe v"UI-Vin curve, IdVQU1Idfi"l, referred to as the maximum voltage gain, is a measure of the (Exercise 4.8) ratio of the two transistors. From the condition W"l,,(Vgsm Vdsn) WpIP(Vgsp, Vdsp), it can be shown that Wngmn + Wpgmp dVin Wngdsn + Wpgdsp ! (5.2) wheregmn == aI.joVgsn, gmp -8Ipj8Vgsp(>O),gdsn == (> 0), etc. gd,p == -8lpj8Vdsp A commonly employed scheme to quantify the noise margin of a transfer curve is to consider a chain of identical inverters in cascade as shown in Fig. 5.5. The solid curve in Fig. 5.6 represents the transfer curve ofinverters #1, #3, ... , i.e., v"u,! vs. f'tnlt v"u13 vs. f'tn3, etc. A complcmentary dashed curve is generated by flipping or mirror imaging the solid curve with respect to the chained line, f'tn = v"",. It represents the inverse transfer curve of inverters #2, #4, #6, ... , i.e., f'tn2 vs.voutb f'tn4 vs. VQut4, etc. In this graphical construction, one can visualize a trajectory of alternating horizontal and vertical lines between the two curves as the node voltal1e makes its transitions through the inverter 5.1 Basic CMOS Circuit Bements 261 stages. Starting with dot il on the solid curve at coordinates (f'tnlt Vautl), the next point i2 is on the dashed curve at coordinates-(v"ut2, f'td. The line between il and i2 is horizontal. since Vin2 Voutl ' The next point i3 is back on the solid curve with coordinates (Vln3, v,,"(3), and is connected to i2 by a vertical line as fin3 =Y:;,ut2, etc. In this example, the . node voltage is pushed after each inverter stage closer and closer to the upper left comer corresponding to v,,"1 Vdd for subsequent odd stages and v"", = 0 for subsequent even stages. Ifthe starting point is below the fin == Vou, intercept such as the circle in Fig. it will be pushed in dotted line segments to the lower right comer, i.e., 0 for subsequent odd stages and v,,"1 Vdd for subsequent even stages. Such a characteristic is called "regenerative" which widens the noise margin as the node voltage is restored to one of the extremes of the binary digital states. To add noise to the above picture, we consider only two inverter stages with the transfer curves depicted in 5.7(a). A positive noise voltage at the input to inverter #1 (Fig. 5.5) kicks the starting point from il to i1' on the solid curve. Ifthere is no noise at the to inverter #2, the output after two inverter stages will end up at point i3 shown. Ifi3 is to the left of il, then there is a net gain of noise margin after the two inverters with noise. On the other hand, ifi3 is to the right of il, then there is a net loss ofnoise margin. In that case, the input voltage to the odd-numbered inverters may keep increasing through repeated cycles with noise. Finally it will cross over the fin VOUI line and the logic state is lost (flipped). The maximum noise voltage that can. be tolerated is then the one that causes i3 to fall back on top of i1. We now add a negative going noise voltage of the same magnitude to the input of inverter #2 (Fig. 5.5). Note that for this example, while a positive going noise voltage is worst at input I, a negative going noise is worst at input 2. As shown in Fig. 5.7(b), the negative noise voltage kicks the input to inverter #2 from i2 to i2' . The maximum noise magnitude that can be tolerated without eventually losing the logic state is the one that returns exactly to il after two noisy stages. Therefore, the noise margin for a given transfer curve is measured by the size ofthe maximum square that canfit between itself and its complementary curve (Hill, 1968). A different way of arriving at the same result is described in 9.7 for the noise margin ofSRAM cells. It is evident that for given n and pMOSFETs, a wider noise margin is achieved with the width ratio ofEq. (5.1) so that the high-to-Iow transition of the transfer curve happens at VdJ2. Since most ofthe noise interference in a chip environment originates from coupling of voltage transients in the neighboring lines or devices, the noise magnitude is expected to scale with the power supply voltage (except those with other natural origins such as "soft error" due to high-energy particles). Thermal noise has too Iowa magnitude ofconcern as long as Vdd» kTlq. Therefore, a relevant measure ofthe noise margin in a CMOS circuit is the normalized VNMVdd, where VNM is the side ofthe maximum square in Fig. 5.7(b). Large VN/jVdd (up to 0.5 in principle) is obtained with a highly skewed, symmetric transfer curve, i.e., one that has VOUI staying high at low to medium f'tnt then making an abrupt high-to-low transition at f'tn VdJ2. It can be seen from the construction of the transfer curve in Fig. 5.3(c) that for a given Vdd, VNljVdd improves with a higher threshold voltage, V/Vdd. In fact, the best noise margin is achieved with subthreshold operation (Frank et al., 200 I), although with poor delay performance. As Vdd is scaled 262 5 CMOS Performance Factors (a) Vdd / , ,.,.,.,. ;:;~,_ ;:;'.0i 1] i2\~''''''-'--' i1' .,..,'/ .;,' .................. - .'." /.~---" i"/'- ......, .. ot5l ,/ .' .' . ./ ... .' / .' " .'\ ' '\ \ \ '\ \ Solid: \»nl Vdd Dashed: VO"t2 -~"i:i ].. ot5l Figure 5.7. Solid: \».1 \'ad Dashed: Vout2 (a) Node voltage trajectory with noise added to the input to inverter#l. (b) Node voltage trajectory with positive noise at inverter #1 and negative noise at inverter #2. The shaded area represents the largest square that can be circumscribed in between the two transfer curves. The side of the square, VNM, is a measure of the noise margin. down, VN~Vdd is not particularly sensitive toVdd until Vdd becomes comparable to kTlq. In order to have the nonlinear I-V characteristics necessary for digital circuit function, a minimum Vdd of several kTlq, e.g., 100-200 mY, is required (Swanson and Meindl, 1972). At I V level, the choice of power supply voltage for static CMOS logic circuits is largely based on power and performance considerations discussed in Section 5.3.3, not noise margin. 5.1.1.3 CMOS Inverter Switching Characteristics We now consider the basic switching characteristics of a CMOS inverter. The simplest waveform is when the gate voltage makes an abrupt or infinitely sharp transition 5.1 Basic CMOS Circuit Elements 263 from low to high or vice versa. For example, consider the inverter biased at point A in Fig. 5.3(a) when ~n makes asreptransition from 0 to Vdd. Before the transition, the nMOSFET is off and the pMOSFET is on. After the transition, the nMOSFET is on and the pMOSFET is off. The trajectory of v.,ut from point A to point B follows the ~n = Vdd curve ofthe nMOSFET as shown in Fig. 5.3(a). lfthe total capacitance ofthe output node (including both the output capacitance ofthe switching inverter and the input capacitance of the next stage or stages it drives) is represented by two capacitors one (C) to the ground and one (C+) to the Vdd rail, as illustrated in Fig. 5.2 - then the pull-down switching characteristics are described by C + C d(Vout - Vdd) -J (V = - + dt Nm or (C_ + C+) dV"ut = Vdd ), (5.3) with the initial condition Vouit=O)= Vdd. Here C = C_ + C+ includes both the capacitance to ground and the capacitance to Vdd. For simplicity, we approximate the IN ( ~n = Vdd) curve by two piecewise continuous lines. In the saturation region (v.,ut > V~~ 07 5.5 A similar distributed network to the one in Fig. 5.21 can be used to formulate the transmission-line model of contact resistance in a planar geometry (Berger, 1972). Here we consider the current flow from a thin resistive film (diffusion with a sheet resistivity Psd) into a ground plane (metal) with an interfacial contact resistivity Pc between them (Fig. 5.16). Thus, i~Fig. 5.21, R dxcorresponds to (Psd/ W)dx, and C dx is replaced by a shunt conductance G dx, which corresponds to (W/Pc)dx. Show 316 5 CMOS Performance Factors that both the current and voltage along the current flow direction satisfy the following differential equation: d2j ==RGf= PsdJ, dx2 Pc ) wherej{x) = V(x) or /(x) defined in Fig. 5.21. 5.6 Following the above transmission-line model, with the boundary condition l(x Ie) =0 where x =0 is the leading edge and x = Ie is the far end of the contact window (Fig. 5.16), solve for V(x) and l(x) within a mUltiplying factor and show' that the total contact resistance, Reo = V(x =OY/(x= 0), is given by Eq.(5.11). 5.7 The insertion of a buffer stage (Section 5.3.2) between the inverter and the load is beneficial only ifthe load capacitance is higher than a certain value. Find, in terms of Cin and COUI, the minimum load capacitance CL above which the single-stage buffered delay given by Eq. (5.45) is shorter than the unbuffured delay given by Eq. (5.43). 5.8 Generalize Eq. (5.44) for one-stage buffered delay to n stages: if the width ratios of the successive buffer stages are kl> k2, k3, ... , kn (all >1), show that the n-stage buffered delay is 'ben) == Rsw [(n+ I)Cout + (k1 + k2 + ... + kn)Cin + klk~~. kJ 5.9 Following the previous exercise, show that for a given n, the n-stage buffered delay is a minimum, CL) l/(n+l'] 'Cbmin(n)=Rsw (n+I)Coul + (n+l)Cin ·C ' [ ( in whenkl k2 = ... =kn (CL/Cin}I/(n+1).Here'Cbmin(n),asexpected,isreduced to Eq. (5.45) if n = I. 5.10 Ifone plots the minimum n-stage buffered delay from the previous exercise versus n, it win first decrease and then increase with n. In other words, depending on the ratios of CdC" and CadCm, there is an optimum number of buffer stages for which the overall delay is the shortest. Show that this optimum n is given by the closeSt integer to In(CL/Cin ) I n Ink -, where k is a solution of k(ln k-I) = Caul Cm For typical Cou/Cjn ratios not too different from unity, kis in the range of3-5. Note that k also gives the optimum width ratio between the successive buffer stages, i.e., kl =k2 = ... = kn=k. Also show that the minimum buffered delay is given by 'Cbmin ~ kRswCin In(CL/Cin ), which only increases logarithmically with load capacitance. Exercises 317 5.11 Consider a chain of CMOS inverters with power supply Vdd. The propagation delay between the waveforms can he..expressed by Eq. (5.39) with FO =1. What is the power dissipation while the signal is propagating down the chain? If the device widths are increased or decreased by a factor of k (>lor ~~*'TY'Oh.....l'" .fA... ""'" .... '" .... h ...·..... ";"'t....? <:>""A .,.. ...............rq.... t>; ...f"'... 320 6 Bipolar Devices layer on top of the base region. Adjacent transistors are isolated from one another by p-type pockets, as illustrated in Fig. 6.1 (b), or by oxide-filled trenches. The process for fabricating a typical advanced vertical n-p-n bipolar transistor having an implanted base region is outlined in Appendix 2. Figure 6.1 (c) shows the bias condition for an n-p-n transistor in normal operation. The emitter-base diode is forward biased with a voltage VBE, and the base-collector diode is reverse biased with a voltage VCB' The corresponding energy-band diagram is shown schematically in Fig. 6.1 (d). The forward-biased emitter-base diode causes electrons to flow from the emitter into the base and holes to flow from the base into the emitter. Those electrons not recombined in the base layer arrive at the collector and give rise to a collector current. The holes injected into the emitter recombine either inside the emitter or at the emitter contact. This flow of holes gives rise to a base current. (The operation of a bipolar transistor having both the emitter-base and collector-base diodes forward biased will be discussed in Section 9.1.3 in the context of bipolar inverter circuits and memory cells.) Also illustrated in Fig. 6.1 (d) are the coordinates which we will follow in describing the flow of electrons and holes. Thus, electrons flow in the x-direction, i.e., In(x) is negative, and holes flow in the -x direction, i.e., Jp(x) is also negative. The physical junction of the emitter-base diode is assumed to be located at "x=O". However, to accommodate the finite thickness of the depletion layer of the emitter-base diode, the mathematical origin (x = 0) for the quasineutral emitter region is shifted to the left of the physical junction, as illustrated in Fig. 6.I(d). Similarly, the mathematical origin (x=0) for the quasineutral base region is shifted to the right ofthe physical junction. The emitter contact is located at x=-WE, and the quasineutral base region ends at x= WB. It should be noted that, due to the finite thickness of a junction depletion layer, the widths of the quasineutral p- and n-regions of a diode are always smaller than their corresponding physical widths. Unfortunately, in the literature as well as here, the same symbol is often used to denote both the physical width and the quasineutral width. For example, WB is used to denote the base width. Sometimes WB refers to the physical base width, and sometimes it refers to the quasineutral base width. The important point to remember is that all the carrier-transport equations for p-n diodes and for bipolar transistors refer to the quasineutral widths. In the literature, several different circuit symbols have been used for a bipolar transistor. In this book, we adopt the symbols illustrated in Fig. 6.1 (e). The arrow indicates the direction of positive current flow in the emitter. For instance, in the n-p-n transistor, the emitter current is due primarily to electrons flowing from the emitter region towards the base region. Hence, the direction of positive current flow is from the base towards the emitter terminal. Similarly, in the p-n--p transistor, the emitter current is due primarily to holes flowing from the emitter region towards the base region, thus giving rise to a positive current flow from the emitter terminal towards the base. Figure 6.2(a) illustrates the vertical doping profile of an n-p-n transistor with a diffused, or implanted and then diffused, emitter. The emitter junction depth XjE is typically 0.2 )lm or larger (Ning and Isaac, 1980). The base junction depth is XjB, and the physical base width is equal to XjB - XjE' Figure 6.2(b) illustrates the vertical doping 6.1 Jl-IH1 Transistors 321 f--- xjB ----: ,~ xjE " ------l ': IE+21 : ;;;' JE+20 E ~ c:: IE+!9 0 .~ 1: IE+18 gQ) 0 U lE+17 IE+16! ,!,'!, ,! , o 0.2 0.4 0.6 0.8 Depth ().Lm) (e) XjE -... ...-- JE+2P1o~! l"ysilico.n.!.~ ,:x'B n-type:, :, :::- IE+20 I S (.) 'c-:' 1E+19 .: 1: ..9... ~ 1E+18 n .I; "~ "" ! !1.) " (c.:) 0 U lE+17 Figure 6.2. IE+16 0 0.2 0.4 0.6 0.8 Depth (j.lm) (b) Vertical doping profiles of typical n-p-n transistors: (a) with implanted and/or diffused emitter, and (b) with poJysilicon emitter. 322 6 Bipolar Devices profile ofan n-p-n transistor with a polysilicon emitter. The polysilicon layer is typically about 0.2 llm thick, with an n+ diffusion into the single-crystal region of only about 30 nm (Nakamura and Nishizawa, 1995). That is, XjE is only about 30 nm. The base widths of most modem bipolar transistors are typically O.lllm or less. While one of the goals in bipolar transistor design is to achieve a base width as small as possible, there are tradeoffs in thin-base designs, as well as difficulties in fabricating thin-base devices. Suffice it to say that the base of a polysilicon-emitter transistor can be made much thinner than that of a diffused-emitter transistor. Details of the doping profiles of the base and collector regions are determined by the desired device dc and ac character istics and will be discussed in Chapter 7. 6.1.1 Basic Operation of a Bipolar Transistor As illustrated in Fig. 6. I (a), a bipolar transistor physically consists of two p-n diodes connected back to back. The basic operation of a bipolar transistor, therefore, can be described by the operation of two back-lo-back diodes. To tum on an n-p-n transistor, the emitter-base diode is forward biased, resulting in holes being injected from the base into the emitter, and electrons being injected from the emitter into the base. In normal operation, the base--colleclor diode is reverse biased so that there is no forward current flow in the base-collector diode. (In some circuits, e.g., in simple bipolar inverters and bipolar memory cells, a bipolar transistor may operate having both the emitter-base and collector-base diodes forward biased. Operation of such circuits is discussed in Section 9.1.3.) The bias condition and the energy-band diagram of an n-p-n transistor in normal operation are illustrated in Figs 6.l(c) and 6.1 (d). As described earlier, as the electrons injected from the emitter into the base reach the collector, they give rise to a collector current. The holes injected from the base into the emitter give rise to a base current. One basic objective in bipolar transistor design is to achieve a collector current significantly larger than the base current The current gain of a bipolar transistor is defined as the ratio of its collector current to its base current. To first order, the behavior of a bipolar transistor is determined by the characteristics of the forward-biased emitter-base diode, since the collector usually acts only as a sink for the carriers injected from the emitter into the base. The emitter-base diode. behaves like a thin-base diode. Thus, qualitatively, the current-voltage characteristics of a thin base diode discussed in Section 2.2.4 can be applied to describe the current-voltage characteristics of a bipolar transistor. 6.1.2 Modifying the Simple Diode Theory for Describing Bipolar Transistors In order to extend the simple diode theory discussed in Section 2.2 to describe the behavior of a bipolar transistor quantitatively, three important effects ignored in it must be included. These are the effects of finite electric field in a quasineutral region, heavy doping, and nonuniform energy bandgap. These effects are discussed below. 6.1 n-p-n Transistors 323 6.1.2.1 Electric Field in a Quasineutral Region with a Uniform Energy 8andgap In Section 2.2.4, the current~voltage 'characteristics of a p-n diode were derived for the case of zero electric field in the p- and n-type quasineutral regions. As will be shown below, the zero-field approximation is valid only where the majority-carrier current is zero and concentration is uniform. For bipolar transistors, as shown in Fig. 6.2(a) and (b), the doping profiles are rather nonuniform. A nonuniform doping profile means that the majority-carrier concentration is also nonuniform. Furthermore, at large emitter-base forward biases, to maintain quasineutrality the high concentration of injected minority carriers can cause significant nonuniformity in the majority-carrier concentration as well. Therefore, the effect of nonuniform majority-carrier concentration in a quasineutral region cannot be ignored in determining the current-voltage characteristics of a bipolar transistor. For a p-type region, Eq. (2.66) gives (p) = CPP !{Ii+kT- In ..!!. , (6.1) q ni where CPP is the hole quasi-Fermi potential and !{Ij is the intrinsic potential. (Note that Pp is equal to Na only for the case of low electron injection, i.e., only at low currents.) The electric field is given by Eq. (2.41), namely q ~_ d!{li kT I dpp dcpp Ii' = - dx Pp dx - dx -kT-I -dpp+ -Jp (6.2) q Pp dx qPP/-Lp' where we have used Eq. (2.64), which relates d¢p/dx to Jp. In Eq. (6.2), the intrinsic carrier concentration is assumed to be independent of x. The dependence of energy bandgap on x will be discussed later in connection with heavy-doping effects. Let us apply Eq. (6.2) to the intrinsic-base region of an n-p-n transistor with a typical current gain of 100. At a typical but high collector current density of I mA/J.l.m2, om the base current density is mNjlID2, i.e., Jp =0.0 I roNjlID2 in the base layer. As can be seen from Fig. 6.2, the base doping concentration is lyJJ.ically on the order ofl018 cm-3, and the corresponding hole mobility is about 150cm2N-s (Fig. 2.8). That is, Pp "" 1018 cm 3 andpp "" 150cm2N-s, and Jplqpppp "" 40 Vlcm, which is a negligibly small electric field in nonnal device operation. Therefore, for a p-type region Eq. (6,2) gives (6.3) Similarly, for an n-type region, ~(n-region) ~ _ kT I dnn (6.4) q nn Equations (6.3) and (6.4) show that the electricjield is negligible in a region o/uniform majority-carrier concentration. 324 6 Bipolar Devices To include the effect of finite electric field, the current-density equations (2.54) and (2.55), which include both the drift and the diffusion ~omponents. should be used. These are repeated here: In(x) = qnlln'if + qDn dn dx' (6.5) and dp lp(x) = qPllp'if qDp dx' (6.6) It should be noted that ifEq. (6.4) is substituted into Eq. (6.5), the RHS ofEq. (6.5) is equal to zero. Similarly, if Eq. (6.3) is substituted into Eq. (6.6), the RHS of Eq. (6.6) is equal to zero. What this means is that the approximations for the electric fields represented by Eqs. (6.3) and (6.4) are good approximations only for describing minority-carrier currents. The dp Idx term, although very small in a p-region, is entirely responsible for the majority-carrier current in a p-region. In fact, from Eq. (2.64), the hole current density in a p-region is lp "" -qpppd¢p Idx. Thus, for describing hole current in a p-region, Eq. (6.2), instead ofEq. (6.3), should be used for the electric field. The electron current in a p-region due to the d¢p Idx term, on the other hand, is negligible. Therefore, Eqs. (6.3) and (6.4) are good approximations for describing minority-carrier currents, i.e., for electron current in a p-region and hole current in an n-region. That is, these approximations are applicable to currents in a diode or in a bipolar transistor. • Built-in electric field in a nonuniformly doped base region. CO::lsider the electron current in the p-type base of a forward-biased emitter-base diode. Let N~) be the doping concentration in the base, and, for simplicity, all the dopants are assumed to be ionized. Quasineutrality requires that pp(x) = NB(X) + np(x). (6.7) Therefore, -ddpxp=d-dNxB+dd-nxp ' (6.8) The built-in electric field ~o is defined as the electric field from the nonuniform base dopant distribution alone, ignoring any effect of injected minority carriers. It can be obtained by substituting NB for Pp in Eq. (6.3), namely == 'f(l1p (6.9) Substituting Eq. (6.3) into Eq. (6.5), and using Eqs. (6.8) and (6.9) and the Einstein relationship, we have, for electron current in a nonuniformly doped p-type base region, lll(x) = qnplln'ifo~ + qDn (2np + NB) dl1p p+NB np+NB dx' (6.1 0) 6.1 n-p-n Transistors 325 Equation (6.10) suggests that the effective electric field 'ife!f in the p-type base can be written as 'ifo~. np+NB (6.11) It should be pointed out that Eqs. (6.1 0) and (6.11) are valid for all levels of electron injection from the emitter, Le., for all values of np • Electric field and current denSity in the low-injection limit. At low levels of electron injection from the emitter, i.e., for np « NB, 'ifeffreduces to 'if!) and Eq. (6. 10) reduces to In(X) ~ qnplln'ifo + qDn ~: ' (6.12) which simply says that the electron current flowing in the base consists of a drift component due to the built-in field from the nonuniform base dopant distrIbution, and a diffusion component from the electron concentration gradient in the base. • Electric field and current density in the high-injection limit. When the electron injection level is very high, i.e., when np »NB, 'if""becomes very small. The built in electric field is screened out by the large concentration of injected minority carriers. Therefore, the electron current component associated with the built-in field becomes negligible, and the electron current density approaches I In(x) n -N ~ ph" B dnp q2Dn -d-X · (6.13) That is, at the high-injection limit, the minority-carrier current behaves as if it were purely a diffusion current, but with a diffusion coefficient twice its low-injection value. This is known as the Webster effect (Webster, 1954). 6.1.2.2 Heavy-Doping Effect As discussed in Section 2.1.2.3, the effective ionization energy for impurities in a heavily doped semiconductor decreases with its doping concentration, resulting in a decrease in its effective energy bandgap. For a lightly doped silicon region at thermal equilibrium, Eqs. (2.13) and (2.16) give the relationship between the product Polio and the energy gap Eg . As the energy gap changes and/or as the densities of states change due the effect of heavy doping, the pono product will also change. For modeling purposes, it is convenient to define an effective intrinsic-carrier concentration n,e and lump all the heavy-doping effects into a parameter called apparent bandgap narrowing, AEg , given by the equation pQ (6.Eg )no (6.EI() n;. = nfexp(6.Eg/kT). (6. The heavy-doping effect increases the effective intrinsic carrier concentration. To include the heavy-doping effect, n; should be rep/aced by nie' Thus, including heavy-doping effect, the product pn in Eq. (2.67) becomes pn = n;eexp[q(p 11)l . kT }' (6.15) 326 6 Bipolar Devices Figure 6.3. ~ -;; 140 120 ~ _ p'type silicon .~ o I- -- - n-type silicon 100 I- - -_. Unified (p and nJ ~ 80 .gg. 60 1! 40 ;: ~ 20 IV.. .. V ..... .1.:5: o 1-;:::'.-., IE+17 IE+IS. v v v ..' _.' ..... IE+19 Doping concentration (cm-3) IE+20 Apparent bandgap narrowing as given by the empirical expressions in Eqs. (6.16H6.18). where ¢p and ¢. are the hole and electron quasi-Fermi potentials, respectively. It is extremely difficult to determine Mg experimentally and there is considerable scattering in the reported data in the literature (del Alamo et al., 1985a). Careful analyses of the reported data suggest the following empirical expressions for the apparent bandgap-narrowing parameter: , t::.Eg(Nd) 18.71n ( 7 xNd1017 ) meV (6.16) for Nd ? 7 x 10! 7 cm- 3, and zero for lower doping levels, for n-type silicon (del Alamo et al., 1985b), and t::.Eg(Na) 9(F+ ..jF2 + 0.5) meV, (6.17) where F = In(N) 1017), for No > 1017 cm-3, and zero for lower doping levels, for p-type silicon (Slotboom and de Graaff, 1976; Swirhun et al., 1986). More recently, using a new model that treats both the majority-carrier and minority-carrier mobilities in a unified manner (Klaassen, 1990), Klaassen et al. (1992) showed that the heavy-doping effect in both n-type silicon and p-type silicon can be described well by a unified apparent bandgap narrowing parameter. If N represents Nd in n-type silicon and Na in p-type silicon, then the Klaassen unified apparent bandgap narrowing parameter is given by r H M,(N) ~ 69+ (L3 :10") + L3 :10") +O+'V (6.18) Figure 6.3 is a plot of Mg a~ a function of doping concentration, as given by Eqs. (6.16) to (6.18). 6.1.2.3 Electric Field in a Quasineutral Region with a Nonuniform Energy Bandgap Aside from the heavy-doping effect, the energy bandgap can also be modified by incorporating a relatively large amount of germanium into silicon. In this case, the 6.2 Ideal Current-Voltage Characteristics 327 bandgap becomes narrower (people, 1986). If both heavy-doping effect and the effect of germanium are included in.the. parameter Mg in Eq. (6.14), then the product pn given by Eq. (6.15) can be used to describe transport in heavily-doped SiGe alloys. When the energy bandgap is nonuniform, the electric field is no longer simply given by Eqs. (6.3) and (6.4), which include only the effect of nonuniform dopant distribution. When the effect of nonuniform energy bandgap is included, the electric fields are given by (van Overstraeten et al., 1973) q~(;p-regl.O)n for a p-type region, and kTU-d- pp - "I 2dn-Te ) q p dx nie dx (6.19) '¥'( fI' n-regl.O)n = -k-T ( -1 -dn-n " 2 I dn-Te ) q nn dx nje dx (6.20) for an n-type region. Derivation ofEq. (6.19) will be shown in Section 7.2.3 in connec tion with the design of the base region of an n-p--n transistor (see Section 7.2.3). 6.2 Ideal Current-Voltage Characteristics In Section 2.2.4, the current-voltage characteristics of a p-n diode were derived assum ing implicitly that the externally applied voltage appears totally across the immediate junction. All parasitic resistances, and the associated voltage drops due to current flow, were assumed to be negligible. With these assumptions, the currents or current densities in a forward-biased diode increase exponentially with the applied voltage. These are the ideal current-voltage characteristics. In practice, the measured current-voltage characteristics of a bipolar transistor are ideal only over a certain range of applied voltage. At low voltages, the base current is larger than the ideal base current. At large voltages, both the base and the collector currents are significantly smaller than the corresponding ideal currents. In this section, the ideal current-voltage characteristics are discussed. Deviations from the ideal char acteristics are discussed in the next section. It was shown in Section 2.2.5 that, for modem bipolar transistors, the base transit time is much smaUer than the minority-carrier lifetime in the base, and there is negligible recombinadon in the ba.~e region. For an n-p-n transistor, neglecting second-order effects, such as avalanche multiplication and generation currents due to defect~ andlor surface states, the base current is due entirely to the injection ofholes from the base into the emitter. Similarly, the collector current is due entirely to the injection of electrons from the emitter into the base. (The effect ofavalanche multiplication in the base--collector junction is considered in Section 6.5, where breakdown voltages are discussed. Also, that recombi nation in the base of modem bipolar transistors is negligible is confirmed in Exercise 6.6). Referring to Fig. 6. I(a), we see that the base terminal contact is located at the. side of the base region. Therefore, the hole current :first flows horizontally from the base tenninal 328 6 Bipolar Devices into the base region and then bends upward and enters the emitter. The horizontal hole current flow causes a lateral voltage drop within the base region, which in tum causes the forward-bias voltage across the immediate emitter-base junction to vary laterally, with the emitter-base forward bias largest nearest the base contact, and smallest furthest away from the base contact This is known as emitter current-crowding effect. When emitter current crowding is significant, the base and collector current densities are not just a function of x [Fig. 6.1 (d)], but also a function of distance from the base contact. Fortunately, as shown in Appendix 16, emitter current crowding is negligible in modern bipolar d£'llices because of their narrow emitter stripe widths. Therefore, we shall ignore emitter current-crowding effect and assume both the base and collector current densities to be uniform over the entire emitter-base junction area. current-Density Equation for Electrons in a p-Type Base Let us consider the electrons injected from the emitter into the p-type base region of an n-p-n transistor. Instead of starting with Eq. (6.10), it is often convenient to reformulate the electron current density in terms of carrier concentrations (Moll and Ross, 1956). To this end, we start with the electron current density given by Eq. (2.63), namely l,,(x) = -qnpp,,, d¢in dx ' (6.21) where ¢in is the electron quasi-Fermi potential. As we shall show later, the hole current density in the p-type base is small, being smaller than the electron current density by a factor ofabout 100 (see Section 6.2.3). Also, as indicated in Fig. 6.2, the base region has a reasonably high doping concentration, typically greater than 10 18 cm- 3 for a modem bipolar transistor. Therefore, the lR drop along the electron-current flow path (which is perpendicular to the intrinsic-base layer) in the p-type base is negligible, which, as discussed in Appendix 4, implies that the hole quasi-Fermi potential ¢ip is approximately constant. That is, we have d¢ip ~ 0 dx . (6.22) in the p-type base region. Combining Eqs. (6.21) and (6.22), we obtain l,,(x) ~ qnp/tn d( VOE, the collector-base diode is reverse biased and the transistor is said to be in its normal forward-active mode of operation. All the electrons injected from the emitter into the base are collected by the collector, as recombination in the intrinsic base is negligible in modem transistors, and there is no electron injection from the collector into the base. The collector current is therefore constant, independent of VCE. The current gain is also constant, and the constant-18 curves are spaced apart by an amount deter mined by the base-current step, as illustrated in Fig. 6.4. 6.3 Characteristics of a Typical n-p-n Transistor 337 Note that the schematic in Fig. 6.4 suggests that the collector current is zero when VCE equals zero. This is only a good appn)~imation. Strictly speaking, the collector current in the saturation region has a component due to the injection of holes from the base into the collector. It will be shown later in Section 6.4.1 that in theory the electron current injected from the emitter into the base at VCE "" 0 cancels exactly the electron current injected from the collector into the base. That this cancellation is almost exact in practical transistors will be shown in Section 7:4.8. Thus, we should expect a small but finite collector current at VeE= 0 owing to the injection of holes from the base into the collector. This current is negative because the holes injected from the base are flowing out of the collector. In a linear plot ofIe versus VeE for a typical bipolar transistor, this hole current is usually too small to be noticeable (see Exercise 9.1 in Chapter 9). The measured current-voltage characteristics of typical bipolar devices are not ideal. The degree of deviation from ideal characteristics depends on the device structure, the device design, the device fabrication process, and on the bias condition of the transistor. The behavior of a typical n-p-n transistor is discussed next. 6.3 Characteristics of a Typical n-p-n Transistor Figure 6.5 is the Gummel plot of a typical n-p-n transistor. It plots both the collector current Ie and the base current IB on a logarithmic scale as a function of the forward-bias voltage VBE applied to the emitter and base terminals. The theoretical ideal base and collector currents, discussed in Section 6.2, are indicated by the dashed lines. Figure 6.5 IE-Ir'--------~~------_, IG~,' : 180 IE-2 II I Ie IE-3 fa $ lE-4 "5 IE-5 ~ U lE-6 IE-7 lE-8 AE= 9!-1Jll' Figure 6.5. IE-9[ I !It IJ 0.4 0.6 0.8 I 1.2 1.4 Emitter-base voltage (V) Gummel plot of a typical n-p--n bipolar transistor. The dashed lines represent the theoretical ideal base and collector currents. (After Ning and Tang, 1984.) 338 6 Bipolar Devices c: il~ Figure 6.6. Collector current Schematic illustration of the current gain IdIB as a function of collector current for a typical bipolar transistor, B E c p n F"1IIur8 6.7. Schematic illustrating the parasitic resistances in a typical modem n-p-n transistor. shows that the measured collector current is ideal except at large VSE, while the measured base current is ideal except at small and at large VBE·, Figure 6.6 illustrates the typical measured current gain, leiIs, as a function ofcollector current. For the voltage range where both the base and the collector currents are approximately ideal, the current gain is approximately constant. At low currents, the current gain is less than its ideal value because the base current is larger than its ideal value. At high currents, the current gain rolls off with collector current because the percentage by which the collector current is smaller than its ideal value is larger than the percentage by which the base current is smaller than its ideal value. The dominant physical mechanisms responsible' for the nonideal behavior of the base and collector currents are discussed in the subsections below. 6.3.1 Effect of Emitter and Base Series Resistances Figure 6.7 shows schematically the physical origins of the parasitic resistances in a typical n-p--n transistor. These resistances are ignored in Section 6.2 in the description of 6.3 Characteristics of a Typical n-p-n Transistor 339 the ideal current-voltage characteristics. As the currents flow through these parasitic resistors, voltage drops are developed, which tend to offset the externally applied voltages. The parasitic resistances can therefore be neglected at low currents but can be very important at large currents. In normal forward-active operation, the base-<:ollectorjunction is reverse biased. In most bipolar circuits, particularly those designed for high-speed applications, the collector--base junction is designed to remain reverse biased at all times, even at high currents. This is accomplished by employing a heavily doped subcollector layer (to reduce rd and a heavily doped reach-through (to reduce rc3) to bring the collector contact to the surface. With the base-{;ollector junction reverse biased, to first order, the collector resistance componentB shown in Fig. 6.7 have no effect on the current flows in the emitter--base diode, and only the parasitic resistances associated with the emitter and the base need to be considered. (The effect ofcollector-base voltage on collector current is discussed in the following subsection.) The emitter series resistance r. is determined primarily by the emitter contact resistance, since the resistance associated with the thin n+ emitter region is small. The base resistance rh can be separated into two components: the intrinsic-base resistance rhi, which is determined by the design of the intrinsic-base region, and the extrinsic-base resistance rbx, which includes all other resistances associated with the base terminal. The emitter-base diode voltage drop due to the flow of emitter and base currents is 1J.VSE -fer. + Isrb = Iere + Is(re + (6.59) where we have used the fact that Ie + Is + Ie O. The relation between the voltage VSE applied to the emitter and base terminals and the voltage V~E appearing across the immediate emitter--base junction is V~E = VSE -1J.Vm;· (6.60) To include the effect ofthe emitter and base series resistances, the equations in Section 6.2 for the ideal collector and base currents should be modified by replacing VBE by V~E This results in both the meaSured collector and base currents, when plotted as a function of VBE, being significantly smaller than the ideal currents at liuge VSE, as illustrated in Fig. 6.5. As can be seen- from Eq. (6.33), even in the ideal case, the collector saturation current density is a function ofthe majority-carrier concentration in the base and the base width. Therefore, the measured collector current is afunction oftfVBE as well as afunction. of the base majority-carrier concentration and the base width, which in turn depend on VBE. The dependence of Ie on VBE is very complex, as can be seen in later subsections. On the other hand, as can be seen from Eqs. (6.43) and (6.49), the base saturation current density is a function of the emitter parameters only, which, due to the emitter being very heavily doped, do not vary with the minority-carrier injection level: Therefore, at high currents, deviation of the base current from its ideal behavior is due to .t1VBE alone (Ning and Tang, 1984). The relation between the ideal base current IBo and the measured base current IB is therefore 180 = IBexp(q1J.VsdkT), (6.61) 340 6 Bipolar Devices which can be used to evaluate the emitter and base series resistances. This is shown in Appendix 15. Many other methods for detennining the emitter and base series resistances have been discussed in the literature (Schroder, 1990). Some of these are discussed in Appendix 15 as well. 6.3.2 6.3.2.1 Effect of Base-Collector Voltage on Collector Current In many transistors, particularly in modem high-speed transistors where the base width is very small, the measured collector current, and hence the measured current gain, increases as the base-collector reverse-bias voltage is increased. This is due to two effects, or a combination of them. The first effect is the dependence of the quasineutral base width on collector-base voltage. The second effect is the avalanche multiplication in the base collector junction. We shall discuss these two effects individually in this subsection. Modulation of Quasineutral Base Width by Base-Collector Voltage As the reverse bias across the base-collector junction is increased, the base-collector junction depletion-layer width increases, and hence the quasineutral base width WB decreases. This in turn causes the collector current to increase, as can be seen from Eq. (6.31). Thus, instead of as illustrated in Fig. 6.4, where the collector current is independent of collector voltage for VCE > VBE, the collector current of a typical bipolar transistor increases with collector voltage, as illustrated in Fig. 6.8. • Early voltage. For circuit modeling purposes, the collector current in the nonsaturation region is often assumed to depend linearly on the collector voltage. The collector voltage at which the linearly extrapolated lcreaches zero is denoted by -VA' As we shall show later, it is a good and useful approximation to assume that VA is independent of VBE. This is illustrated in Fig. 6.8. VA is called the Early voltage (Early, 1952). It is defined by alc -1 VA + VCE == lC(avCE) (6.62) In practice, except for transistors that tend to punch through (to be discussed later), VA is much larger than the operation range of VCEo Therefore, VA can be approximated by IBI IB2 IB3 IB4 Figure 6.8. o ~-I 'BS VCE Schematic illustrating the approximately linear dependence oflc on VCE. The linearly extrapolated Ic intersects the VcE.-axis at - VA' 6.3 Characteristics of a Typical n-p-n Transistor 341 v.~ ~Ie{(,,{:o)VJ~E)-1 (6.63) The collector current is given by Eq, (6.32), which canbe written as qAEexp(qVBslkT) Ie = AEJcOexp(qVBslkT) = F(WB) , (6.64) where, for convenience, a function F has been introduced (Kroemer, 1985) which is defined by r F(WB) q leo = Jo WD DnB(px)pn(~xe)B(x)dx. (6.65) The majority-carrier hole charge per unit area in the base is r QpB q Jo W• pp(x)dx. (6.66) Since VBE is fixed for a given IB, Eq. (6.63) can be rewritten as VA ~Ic ( -IC of -- F oVCE ) - 1 _(2 of OWB OQPB)-I - F aWBOQpBOVCE _(2 of aWB aQpB)-1 - F aWBOQpBOVcB (6.67) Notice that VCB = -VBC' As explained in Section 2.2.2.2 in the derivation ofEq. (2.83) for the depletion-layer capacitance for a p-n junction, when the p-side (base) voltage is changed relative to the n-side (collector) by fj, VBC, the p-side depletion charge changes by an amount equal to the change in the majoritychole charge AQpB in the p-side. Therefore, OQpB = OQpB C o~ o~ ~, (6 .68) where CdBC is the base-collector junction depletion-layer capacitance per unit area [cf. Eq. (2.83)]. The other two derivatives in Eq. (6.67) can be evaluated directly, namely. of --= pp(WB) 2 OWB DnB(WB)nieB(WB) and (6.69) OWB _ (OQPB)-I _ __I OQpB - oWB - qpp(WB)' (6,70) l Therefore, Eq. (6.67) gives VA ~ ~ qDnB( WB)n7eB( WB) . W ' pp(X) d ') X. C4BC 0 DnB(x)nieB(x) (6.71) 342 6 Bipolar Devices For a uniformly doped base, Eq. (6.71) reduces to VA ~ QpB CdBC' (6.72) At sufficiently low collector currents such that the base majority-carrier concentration is approximately the same as its equilibrium value, i.e.,pp ~PpO NB, Eq. (6.71) gives VA ~qDnB(WB)n;cB(WB)lWB ~ CdBC 0 NB(X) d DnB( x)ni2eB ( x) X. (6.73) Equation (6.73) is independent ofbase current, so that the slope ofthe curves in Fig. 6.8 intercept the VCE-axis at the same value, namely VA, as illustrated. It is instructive to estimate the magnitude of Eq. (6.73) for a uniformly doped base. In this case, VA ~ qWsNBICdBe. For a base of WB=O.l ~ and NB= IOIScm- 3, we have qWsNB ~ 1.6 x 1O- 6 C/cm2. For a collector of Ne =2 x 1016 cm-3, then, from Fig. 2.16, CdBC ~ 4 x 10- 8 F/cm2• Therefore, VA::; 40 V. In practice, "A can vary a lot as the transistor design is "optimized." This will be discussed further later in this section and in Chapter 7. As can be seen in Eq. (6.71), VA is a function of WB , which, as discussed earlier, is a function of the collector voltage. Therefore, strictly speaking, the Early voltage is a function of the collector voltage at which the slope is used for extrapolating to Ie =0. In other words, strictly speaking, Ie does not increase lineraly with However, the linear dependence is a good approximation and is a useful approximation for circuit analyses and modeling purposes. The Early voltage is a figure of merit for devices used in analog circuits. The larger the Early voltage, the more independent is the collector current on collector voltage. Another device figure ofmerit is the product ofthe current gain and Early voltage. Using Eqs. (6.33), (6.51), and (6.71), this product can be written as (Prinz and Sturm, 1991) (3o VA q2DnB (WB)n7eB(WB) CdBeJBQ (6.74) where the base saturated current density JBO is a function of the emitter parameters. That is, while VA is a function of the base parameters only, the product /lOVA is a function of both the emitter and the base parameters. • Emitter-collector punch-through. As shown in Eq. (6.72), the Early voltage is propor tional to the majority-carrier charge in the base. As the collector voltage is increased, the width of the quasineutral base region, and hence the majority-carrier charge in the base, is reduced. For a device with a small majority-carrier base charge or small Early voltage to start with, it does not take much increase in collector voltage before all the majority carrier base charge is depleted, or before the collector punches through to the emitter. At collector--emitter punch-through, the collector current becomes excessively large, being limi ted only by the emitter and collector series resistances. The collector current at or close to punch-through is no longer controlled adequately by the base voltage for proper device operation. Punch-through must be avoided under normal device operation, by designing the device to have a sufficiently large majority-carrier base charge. 6.3 CharacteristiCS of a Typical n-p-n Transistor 343 6.3.2.2 Base-Collector Junction Avalanche For a device with a large majority~carrier base charge or large Early voltage to hegin with, as the collector voltage is increased, usually the condition of significant base-collector junction avalanche is reached before punch-through is reached. This is certainly the case for transistors where the collector side of the base-*