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Fundamentals of Modern VLSI Devices (2nd Edition) 

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Fundamentals of Modern" VLSI Devices SECOND EDITION YUAN TAUR University of California, san Diego TAK H. NING IBM T. J. Watson Research Center, New York CAMBRIDGE UNIVERSITY PRESS CAMBRIDGE UNIVERSITY PRESS Cambridge, New York, Melbourne, Madrid, Cape Town, Singapore, Sao Paulo, Delhi Cambridge University Press The Edinburgh Building, Cambridge CB2 8RU, UK Published in the United States of America by Cambridge University Press, New York www..cambridge.org Information on this title: www.cambridge.orgl9780521832946 © Cambridge University Press 1998, 2009 This publication is in copyright. Subject to statutory exception and to the provisions of relevant collective licensing agreements, no reproduction of any part may take place without the written pennission of Cambridge University Press. First published 1998 Second edition 2009 Printed in the United Kingdom at the University Press, Cambridge A catalog recordfor this publication is availablefrom the British Library Library ofCongress Cataloging in Publication data Taur, Yuan, 1946­ Fundamentals of modem VLSI devices / Yuan Taur, Tak H. Ning. 2nd ed. p. cm. ISBN 978-0-521-83294-6 1. Metal oxide semiconductors, Complementary. 2. Bipolar transistors. 3. Integrated circuits Very large scale integration. l. Ning, Tak H., 1943- 11. Title. TK7871.99.M44T38 2009 621.39'5-dc22 2009007334 ISBN 978-0-521-83294-6 hardback Cambridge University Press has no responsibility for the persistence or accuracy of URLs for external or third-party Internet websites referred to in this publ.ication, and does not guarantee thai any content on such websites is, or will remain, accurate or appropriate. Contents Preface to the first edition Preface to the second edition Physical constants and unit conversions List ofsymbols page xi xiii xv XVI 1 Introduction 1.1 Evolution ofVLSI Device Technology 1.1.1 Historical Perspective 1.1.2 Recent Developments 4 1.2 Modern VLSI Devices 4 1.2.1 Modern CMOS Transistors 4 1.2.2 Modern Bipolar Transistors 5 1.3 Scope and Brief Description of the Book 6 2 Basic Device PhysiCS 11 2.1 Electrons and Holes in Silicon II 2.Ll Energy Bands in Silicon 11 2.1.2 n-Type and p-Type Silicon 17 2.1.3 Carrier Transport in Silicon 23 2.1.4 Basic Equations for Device Operation 27 2.2 p-n Junctions 35 2.2.1 Energy-Band Diagrams for a p-n Diode 35 2.2.2 Abrupt Junctions 38 2.2.3 The Diode Equation 46 2.2.4 Current-Voltage Characteristics 51 2.2.5 Time-Dependent and Switching Characteristics 64 2.2.6 Diffusion Capacitance 70 2.3 MOS Capacitors 72 23.1 Surface Potential: Accumulation, Depletion, and Inversion 72 2.3.2 Electrostatic Potential and Charge Distribution in Silicon 78 2.3.3 Capacitances in an MOS Structure 85 2.3.4 Polysilicon-Gate Work Function and Depletion Effects 91 2.3.5 MOS under Nonequilibrium and Gated Diodes 94 vi Contents Contents vii 2.3.6 Charge in Silicon Dioxide and at the Silicon-Oxide Interface 98 4.3 MOSFET Channel Length 242 2.3.7 Effect of Interface Traps and Oxide Charge on Device Characteristics 103 4.3.1 Various Definitions ofChannel Length 242 2.4 Metal-Silicon Contacts 108 4.3.2 Extraction ofthe Effective Channel Length 244 2.4.1 Static Characteristics of a Schottky Barrier Diode 108 4.3.3 Physical Meaning of Effective Channel Length 248 2.4.2 Current Transport in a Schottky Barrier Diode 115 4.3.4 Extraction of Channel Length by C-VMeasurements 252 2.4.3 Current-Voltage Characteristics of a Schottky Barrier Diode ll5 Exercises 254 2.4.4 Ohmic Contacts 120 2.5 High-Field Effects 122 5 CMOS Perfonnance Factors 256 2.5.1 Impact Ionization and Avalanche Breakdown 122 2.5.2 Band-to-Band Tunneling 125 2.5.3 Tunneling into and through Silicon Dioxide 127 2.5.4 Injection of Hot Carriers from Silicon into Silicon Dioxide 133 2.5.5 High-Field Effects in Gated Diodes 135 2.5.6 Dielectric Breakdown 137 Exercises 141 5.1 Basic CMOS Circuit Elements 5.1.1 CMOS Inverters 5.1.2 CMOS NAND and NOR Gates 5.1.3 Inverter and NAND Layouts 5.2 Parasitic Elements 5.2.1 Source-Drain Resistance 5.2.2 Parasitic Capacitances 256 256 266 270 273 274 277 3 MOSFET Devices 5.2.3 Gate Resistance 148 5.2.4 Interconnect R and C 280 283 3.1 Long-Channel MOSFETs 148 5.3 Sensitivity of CMOS Delay to Device Parameters 289 3.1.1 Drain-Current Model 149 5.3.1 Propagation Delay and Delay Equation 289 3.1.2 MOSFET J- V Characteristics 155 5.3.2 Delay Sensitivity to Channel Width, Length, and Gate Oxide Thickness 296 3.1.3 Subthreshold Characteristics 163 5.3.3 Sensitivity of Delay to Power-Supply and Threshold Voltage 299 3.1.4 Substrate Bias and Temperature Dependence of Threshold Voltage 166 5.3.4 Sensitivity of Delay to Parasitic Resistance and Capacitance 301 3.1.5 MOSFET Channel Mobility 169 5.3.5 Delay of Two-Way NAND and Body Effect 304 3.1.6 MOSFET Capacitances and Inversion-Layer Capacitance Effect 172 5.4 Performance Factors of Advanced CMOS Devices 307 3.2 Short-Channel MOSFETs 175 5.4.1 MOSFETs in RF Circuits 308 3.2.1 Short-Channel Effect 176 5.4.2 Effect of Transport Parameters on CMOS Performance 311 3.2.2 Velocity Saturation and High-Field Transport 186 5.4.3 Low-Temperature CMOS 312 3.2.3 Channel Length Modulation 195 Exercises 315 3.2.4 Source-Drain Series Resistance 196 3.2.5 MOSFET Degradation and Breakdown at High Fields Exercises I 196 6 201 Bipolar Devices 6.1 n-p-n Transistors 318 318 4 CMOS Device Design 204 6.1.1 Basic Operation of a Bipolar Transistor 322 6.1.2 Modifying the Simple Diode Theory for Describing Bipolar Transistors 322 4.1 MOSFET Scaling 204 6.2 Ideal Current-Voltage Characteristics 327 4.1.1 Constant-Field Scaling 204 6.2.1 Collector Current 329 4.1.2 Generalized Scaling 207 6.2.2 Base Current 330 4.1.3 Nonscaling Effects 210 6.2.3 Current Gains 334 4.2 Threshold Voltage 212 6.2.4 Ideal Characteristics 336 4.2.1 Threshold-Voltage Requirement 213 6.3 Characteristics of a Typical n-p-n Transistor 337 4.2.2 Channel Profile Design 217 6.3.1 Effect of Emitter and Base Series Resistances 338 4.2.3 Nonuniform Doping 224 6.3.2 Effect of Base-Collector Voltage on Collector Current 340 4.2.4 Quantum Effect on Threshold Voltage 234 6.3.3 Collector Current Falloff at High Currents 343 4.2.5 Discrete Dopant Effects on Threshold Voltage 239 6.3.4 Nonideal Base Current at Low Currents 347 Contents 6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses 6.4.1 Basic dc Model 6.4.2 Basic ac Model 6.4.3 Small-Signal Equivalent-Circuit Model 6.4.4 Emitter Diffusion Capacitance 6.4.5 Charge-Control Analysis 6.5 Breakdown Voltages Common-Base Current Gain in the Presence of Base-Collector Junction Avalanche 6.5.2 Saturation Currents in a Transistor 6.5.3 Relation Between BVCEO and BVCBO Exercises 352 352 355 356 359 361 366 367 369 370 371 7 Bipolar Device Design 374 7.1 Design of the Emitter Region 7.1.1 Diffused or Implanted-and-Diffused Emitter 7.1.2 Polysilicon Emitter 7.2 Design of the Base Region 7.2.1 Relationship between Base Sheet Resistivity and Collector Current Density 7.2.2 Intrinsic-Base Dopant Distribution 7.2.3 Electric Field in the Quasineutral Intrinsic Base 7.2.4 Base Transit Time 7.3 Design of the Collector Region 7.3.1 Collector Design When There Is Negligible Base Widening 7.3.2 Collector Design When There Is Appreciable Base Widening 7.4 SiGe-Base Bipolar Transistors 7.4.1 Transistors Having a Simple Linearly Graded Base Bandgap 7.4.2 Base Current When Ge Is Present in the Emitter 7.4.3 Transistors Having a Trapezoidal Ge Distribution in the Base 7.4.4 Transistors Having a Constant Ge Distribution in the Base 7.4.5 Effect of Emitter Depth Variation on Device Characteristics 7.4.6 Some Optimal Ge Profiles 7.4.7 Base-Width Modulation by VBE 7.4.8 Reverse-Mode I-V Characteristics 7.4.9 Heterojunction Nature of a SiGe-Base Bipolar Transistor 7.5 Modem Binolar Transistor Structures Isolation 7.5.2 Polysilicon Emitter 7.5.3 Self-Aligned Polysilicon Base Contact 7.5.4 Pedestal Collector 7.5.5 SiGe-Base Exercises 374 375 376 377 378 380 381 384 385 387 388 389 390 396 401 406 410 414 419 423 426 429 429 430 430 431 431 432 Contents ix 8 Bipolar Performance Factors 437 8.1 Figures of Merit of a Bipolar Transistor 8.1.1 Cutoff Frequency 8.1.2 Maximum Oscillation Frequency 8.1.3 Ring Oscillator and Gate Delay 8.2 Digital Bipolar Circuits 8.2.1 Delay Components of a Logic Gate 8.2.2 Device Structure and Layout for Digital Circuits 8.3 Bipolar Device Optimization for Digital Circuits 8.3.1 Design Points for a Digital Circuit 8.3.2 Device Optimization When There Is Significant Base Widening 8.3.3 Device Optimization When There Is Negligible Base Widening 8.3.4 Device Optimization for Small Power-Delay Product 8.3.5 Bipolar Device Optimization from Some Data Analyses 8.4 Bipolar Device Scaling for ECL Circuits 8.4.1 Device Scaling Rules 8.4.2 Limits in Bipolar Device Scaling for ECL Circuits 8.5 Bipolar Device Optimization and Scaling for RF and Analog Circuits 8.5.1 The Single-Transistor Amplifier 8.5.2 Optimizing the Individual Parameters 8.5.3 Technology for RF and Analog Bipolar Devices 8.5.4 Limits in Scaling Bipolar Transistors for RF and Analog Applications 8.6 Comparing a SiGe-Base Bipolar Transistor with a GaAs HBT Exercises 437 437 440 440 44] 442 445 447 447 448 449 453 455 457 458 460 463 463 464 467 468 469 472 9 Memory Devices 476 9.1 Static Random-Access Memory 9.1.1 CMOS SRAM Cell 9.1.2 Other Bistable MOSFET SRAM Cells 9.1.3 Bipolar SRAM Cell 9.2 Dynamic Random-Access Memory 9.2.1 Basic DRAM Cell and Its Operation 9.2.2 Device Design and Scaling Considerations for a DRAM Cell 9.3 Nonvolatile Memory 9.3.1 MOSFET Nonvolatile Memory Devices 9.3.2 Flash Memory Arrays 9.3.3 Floating-Gate Nonvolatile Memory Cells 9.3.4 Nonvolatile Memory Cells with Charge Stored in Insulator Exercise 477 478 486 487 495 496 499 500 501 507 511 514 516 x Contents 10 Silicon-on-Insulator Devices 517 10.1 SOl CMOS 517 10.1.1 Partially Depleted SOl MOSFETs 518 10.1.2 Fully Depleted SOl MOSFETs 520 10.2 Thin-Silicon SOl Bipolar 523 10.2.1 Fully Depleted Collector Mode 524 10.2.2 Partially Depleted Collector Mode 526 10.2.3 Accumulation Collector Mode 527 10.2.4 Discussion 527 10.3 Double-Gate MOSFETs 529 10.3.1 An Analytic Drain Current Model for Symmetric DG MOSFETs 529 10.3.2 The Scale Length of Double-Gate MOSFETs 533 10.3.3 Fabrication Requirements and Challenges ofDG MOSFETs 534 10.3.4 Multiple-Gate MOSFETs 536 Exercise 537 Appendix 1 CMOS Process Flow 538 Appendix 2 Outline of a Process for Fabricating Modem n-p-n Bipolar Transistors 542 Appendix 3 Einstein Relations 543 Appendix 4 Spatial Variation of Quasi-Fermi Potentials 546 Appendix 5 Generation and Recombination Processes and Space-Charge­ Region Current 553 Appendix 6 Diffusion Capacitance of a p-n Diode 562 Appendix 7 Image-Force-Induced Barrier Lowering 569 Appendix 8 Electron-Initiated and Hole-Initiated Avalanche Breakdown 573 Appendix 9 An Analytical Solution for the Short-Channel Effect in Subthreshold 575 Appendix 10 Generalized MOSFET Scale Length Model 582 Appendix 11 Drain Current Model of a Ballistic MOSFET 588 Appendix 12 Quantum-Mechanical Solution in Weak Inversion 594 Appendix 13 Power Gain of a Two-Port Network 598 Appendix 14 Frequencies of a MOSFET Transistor 601 Appendix 15 DeterminatioIJ.,ofEmitter and Base Series Resistances 605 Appendix 16 Intrinsic-Base Resistance 610 Appendix 17 Energy-Band Diagram of a Si-SiGe n-p Diode 614 Appendix 18 IT and Imax of a Bipolar Transistor 617 References 623 Index 644 Preface to the first edition It has been fifty years since the invention of the bipolar transistor, more than forty years since the invention of the integrated~circuit (IC) technology, and more than thirty-five years since the invention ofthe MOSFET. During this time, there has been a tremendous and steady progress in the development of the IC technology with a the IC industry. One distinct characteristic in the evolution ofthe IC tecnnOlogy physical feature sizes of the transistors are reduced continually over time as the litho­ graphy technologies used to define these features become available. For almost thirty years now, the minimum lithography feature size used in IC manufacturing has been reduced at a rate ofO.7x every three years. In 1997, the leading-edge IC products have a minimum feature size of 0.25 1Jll1. The basic operating principles oflarge and small transistors are the same. However, the relative importance of the various device parameters and performance factors for tran­ sistors of the l-1Jll1 and smaller generations is quite different from those for transistors of larger-dimension generations. For example, in the case of CMOS, the power-supp voltage was lowered from the standard 5 V, starting with the 0.6- to 0.8-1Jll1 generation. Since then CMOS power supply voltage has been lowered in steps once every few years as the device physical dimensions are reduced. At the same time, many physical phenomena, such as short-channel effect and velocity saturation, which are negligible in large-dimension MOSFETs, are becoming more and more important in determining the behavior ofMOSFETs of deep-submicron dimensions. In the case of bipolar devices, breakdown voltage and base-widening effects are limiting their performance, and power dissipation is limiting their level of integration on a chip. Also, the advent of SiGe­ base bipolar technology has extended the frequency capability of small-dimension bipolar transistors into the range previously reserved for GaAs and other compound­ semiconductor devices. The purpose of this book is to bring together the device fundamentals that govern the behavior of CMOS and bipolar transistors into a single text, with emphasis on those parameters and eerformance factors that are particularly important for VLSI (very-large­ scale-integration) devices of deep-submicron dimensions. The book starts with a com­ prehensive review of the properties of the silicon material, and the basic physics ofp-n junctions and MOS capacitors, as they relate to the fundamental principles of MOSFET and bipolar transistors. From there, the basic operation of MOSFET and bipolar devices, and their design and optimization for VLSI applications are developed. A great deal of the volume is devoted to in-depth discussions of the intricate interdependence and subtle tradeoffs of the various device parameters pertaining to circuit performance and manu­ facturability. The effects which are particularly important in small-dimension devices, xii Preface to the first edition e.g., quantization of the two-dimensional surface inversion layer in a MOSFET device and the heavy-doping effect in the intrinsic base of a bipolar transistor, are covered in detail. Also included in this book are extensive discussions on scaling and limitations to scaling of MOSFET and bipolar devices. This book is suitable for use as a textbook by senior undergraduate or graduate students in electrical engineering and microelectronics. The necessary background assumed is an introductory understanding of solid-state physics and semiconductor physics. For practicing engineers and scientists actively involved in research and devel­ opment in the IC industry, this book serves as a reference in providing a body of knowledge in modem VLSI devices for them to stay up to date in this field. VLSI devices are too huge a subject area to cover thoroughly in one book. We have chosen to cover only the fundamentals necessary for discussing the design and optimiza­ tion of the state-of-the-art CMOS and bipolar devices in the sub-0.5-)Jl11 regime. Even then, the specific topics covered in this book are based on our own experience ofwhat the most important device parameters and performance factors are in modem VLSI devices. Many people have contributed directly and indirectly to the topics covered in this book. We have benefited enormously from the years of collaboration and interaction we had with our colleagues at IBM, particularly in the areas of advanced silicon-device research and development. These include Douglas Buchanan, Hu Chao, T. C. Chen, Wei Chen, Kent Chuang, Peter Cook, Emmanuel Crabbe, John Cressler, Bijan Davari, Robert Dennard, Max Fischetti, David Frank, Charles Hsu, Genda Hu, Randall Isaac, Khalid G. P. Li, Shih-Hsien Lo, Yuh-Jier Mii, Edward Nowak, George Sai-Halasz, Stanley Schuster, Paul Solomon, Hans Stork, Jack Sun, Denny Tang, Lewis Terman, Clement Wann, James Warnock, Siegfried Wiedmann, Philip Wong, Matthew Wordeman, Ben Wu, and Hwa Yu. We would like to acknowledge the secretarial support of Barbara Grady and the support of our management at IBM Thomas J. Watson Research Center where this book was written. Finally, we would like to give special thanks to our families _ Adrienne, and Brenda Ning and Betty, Ying, and Hsuan Taur for their support and understanding during this seemingly endless task. Yuan Taur Tak H. Ning Yorktown Heights, New York, October, 1997 Preface to the second edition Since the publication of the first edition of Fundamentals ofModern VLSI Devices by Cambridge University Press in 1998, we received much praise and many encouraging reviews on the book. It has been adopted as a textbook for first-year graduate courses on microelectronics in many major universities in the United States and worldwide. The first edition was translated into Japanese by a team led by Professor Shibahara of Hiroshima University in 2002. During the past 10 years, the evolution and scaling of VLSI (very-Iarge-scale­ integration) technology has continued. Now, sixty years after the first invention of the transistor, the number of transistors per chip for both microprocessors and DRAM (dynamic random access memory) has increased to over one billion, and the highest clock frequency of microprocessors has reached 5 GHz. In 2007, the worldwide IC (integrated circuits) sales grew to $250 billion. In 2008, the IC industry reached the 45-nm generation, meaning that the leading-edge IC products employ a minimum lithography feature size of 45 nm. As bulk CMOS (complementary metal-oxide­ semiconductor field-effect transistor) technologies are scaled to dimensions below 100 nm, the very factor that makes CMOS technology the technology of choice for digital VLSI circuits, namely, its low standby power, can no longer be taken for granted. Not only has the off-state current gone up with the power supply voltage down scaled to the I V level, the gate leakage has also increased exponentially from quantum mechanical tunneling through gate oxides only a few atomic layers thick. Power management. both active and standby, has become a key challenge to continued increase ofclock frequency and transistor count in microprocessors. New materials and device structures are being explored to replace conventional bulk CMOS in order to extend scaling to IQnm. The purpose of writing the second edition is to update the book with additional material developed after the completion of the first edition. Key new material added includes MOSFET scale length theory and high-field transport model, and the section on SiGe-base bipolar devices has been greatly expanded. We have also expanded the discussions on basic device physics and circuits to include metal-silicon contacts, noise margin of CMOS circuits, and figures of merit for RF applications. Furthermore, two new chapters are added to the second edition. Chapter 9 is on memory devices and covers the fundamentals of read and write operations ofcommonly used SRAM, DRAM, and nonv.olatile memory arrays. Chapter 10 is on silicon-on-insulator (SOl) devices, including advanced devices of future potential. We would like to take this opportunity to thank all the friends and colleagues who gave us encouragement and valuable suggestions for improvement of the book. In particular, Professor Mark Lundstrom of Purdue University who adoptcd the first edition early on, xiv Preface to the second edition and Dr. Constantin Bulucea of National Semiconductor Corporation who suggested the treatment on diffusion capacitance. Thanks also go to Professor James Meindl ofGeorgia Institute of Technology, Professor Peter Asbeck of University of California, San Diego, and Professor Jerry Fossum of University of Florida for their support of the book. We would like to thank many of our colleagues at IBM, particularly in the areas of advanced silicon-device research and development, for their direct or indirect contribu­ tions. Yuan Taurwould like to thank many ofhis students at University ofCalifornia, San Diego, in particular Jooyoung Song and Bo Yu, for their help with the completion of the second edition. He would also like to thank Katie Kahng for her love, support, and patience during the course of the work. We would like to give special thanks to our families for their support and under­ standing during this seemingly endless task. Yuan Taur TakH. Ning June, 2008 Physical constants and unit conversions Description Electronic charge Boltzmann's constant Vacuum permittivity Silicon permittivity Oxide permittivity Velocity of light in vacuum Planck's constant Free-electron mass Thermal voltage (T= 300 K) Angstrom Nanometer Micrometer (micron) Millimeter Meter Electron-volt Energy = charge x voltage Charge = capacitance x voltage Power current x voltage Time = resistance x capacitance Current = charge/time Resistance = voltage/current Symbol q k eo f.:si eox c h rno kTlq A nm IJl1l mm m eV E=qV Q=CV P IV t=RC I= Qlt R VII Value and unit 1.6xlO-19 C 1.38 x 10-23 JIK 8.85 x 1O-14 F/cm 1.04 x 1O-12 F/cm 3.45 x 1O-13 F/cm 3 x 1010 cm/s 6.63 x 10-34 J-s 9.1 x 10-31 0.0259 V lA 1O-s cm 1nm= 10-7 cm IIJl1l = 10-4 cm 1mm=O.l em 1m= lO2cm leV= 1.6 x 10-19 J Joule = Coulomb x Volt - Coulomb = Farad x Volt Watt.= ~pere x Volt n ~econd = (ohm) x !::arad Ampere = Coulomb/second n (ohm) .:'{oltlAmpere Aword ofcaution about the length units: strictly speaking, MKS units should be used for all the equations in the book. As a matter ofconvention, electronics engineers often work with centimeter as the unit oflength. While some equations work with lengths in either meter or centimeter, not all ofthem do. It is prudent always to check for unit consistency when doing calculations. It may be necessary to convert the length unit to meter before plugging into the equations. List of symbols Symbol A a aa aF aR aT an ap BV BVCBO BVCEO BVEs'o P flo p,., c C Cd Cd,lol CdBC CdBE,/ol Cdm CD Description Area Emitter area Common-base current gain Static common-base current gain Forward common-base current gain in the Ebers-Moll model Reverse common-base current gain in the Ebers-Moll model Base transport factor Electron-initiated rate of electron-hole pair generation per unit distance Hole-initiated rate of electron-hole pair generation per unit distance Breakdown voltage Collector-base junction breakdown voltage with emitter open circuit Collector-emitter breakdown voltage with base open circuit Emitter-base junction breakdown voltage with collector open circuit Current gain Static common-emitter current gain Forward common-emitter current gain in the Ebers-Moll model Reverse common-emitter current gain in the Ebers-Moll model Velocity in vacuum (= 3 x em/s) Capacitance Depletion-layer capacitance per unit area Total depletion-layer capacitance Base·-collector diode depletion-layer capacitance per unit area Total base·-~ollector diode depletion-layer capacitance Base-emitter diode depletion-layer capacitance per unit area Total base-emitter diode depletion-layer capacitance Maximum depletion-layer capacitance (per unit area) Diffusion capacitance Unit cm2 cm2 None None None None None cm-! cm-l v V V V None None None None cm/s F F/cm2 F F F/cm2 F F (F/cm2) F List of symbols xvii CDn CDp CDE CFC Cg CG Cj Cit Cj CL Cin Cinv Cmin COUI Cov Cox Cp Csi Cw Cil d Dn DnB Dp DpE AV, AEg AEg,SiGe AI AQtotal E Ec Eo Diffusion capacitance due to excess electrons Diffusion capacitanC'ellue to excess holes Emitter diffusion capacitance Equivalent density-of-states capacitance MOS capacitance at flat band per unit area Capacitance between the floating gate and the control gate of a MOSFET nonvolatile memory device Intrinsic gate capacitance per unit area Total gate capacitance of MOSFET Inversion-layer capacitance per unit area Interface trap capacitance per unit area Junction capacitance per unit area Junction capacitance Load capacitance Equivalent input capacitance of a logic gate MOSFET capacitance in inversion per unit area Minimum MOS capacitance per unit area Equivalent output capacitance ofa logic gate Gate-to-source (-drain) overlap capacitance (per edge) Oxide capacitance per unit area Polysilicon-gate depletion-layer capacitance per unit area Silicon capacitance per unit area Wire capacitance per unit length Base-emitter capacitance in the small-signal hybrid-x equivalent-circuit model Base-collector capacitance in the small-signal hybrid-x equivalent-circuit model Width of diffusion region in a MOSFET Electron diffusion coefficient Electron diffusion coefficient in the base ofan n-p-n transistor Hole diffusion coefficient Hole diffusion coefficient in the emitter ofan n-p-n transistor Threshold voltage rolloff due to short-channel effect Apparent bandgap narrowing Bandgap-narrowing parameter in the base region Maximum bandgap narrowing due to the presence of Ge Local bandgap narrowing due to the presence ofGe Channel length modulation in MOSFET Total charge stored in a nonvolatile memory device Energy Conduction-band edge Valence-band edge Ionized-acceptor energy level F F F F/cm2 F F/cm2 F F/cm2 F/cm2 F/cm2 F F F F/cm2 F/em2 F F F/cm2 F/cm2 F/cm2 F/em F F em cm 2/s cm2/s em2/s cm2/s V J J J ] cm C J J J J xviii Ust of symbols Ionized-donor energy level J Ef Fermi energy level J Eg Energy gap of silicon J E; Intrinsic Fermi level J Fermi energy level on the n-side of a p-n diode J Efp Fermi energy level on the p-side of a p-n diode 'iff Electric field J V/cm Critical field for velocity saturation 'iffeff Effective vertical field in MOSFET 'iffox Oxide electric field V/cm Vlcm V/cm 'iffs Electric field at silicon surface Vlcm 'iffx Vertical field in silicon V/cm 'iffy Lateral field in silicon eo Vacuum permittivity (= 8.85 x 10-14 F/em) V/cm F/cm G; Permittivity of gate insulator eSi Silicon permittivity (= 1.04 x 1O-12 F/cm) eax Oxide permittivity (= 3.45 x 10-13 F/cm) F/cm F/em F/cm fD Probability that an electronic state is filled None f Frequency, clock frequency Hz fmax Unity power gain frequency Hz fr Unity current gain frequency Hz FI Fan-in None FO Fan-out None 4> Barrier height V 4>ox Silicon-silicon dioxide interface potential barrier fo~ electrons V 4>ms Work-function difference between metal and silicon V 4>0 Electron quasi-Fermi potential V 4>p Hole quasi-Fermi potential V 4>sn Schottky barrier height for electrons V 4>Bp Schottky barrier height for holes V g Number of degeneracy None gds Small-signal output conductance AIV gm Small-signal transconductance AIV GE Emitter Gummel number s/cm4 Gs Base Gummel number s/cm4 Gn Electron emission rate (also called electron generation rate) I/cm3-s Gp Hole emission rate (also called hole generation rate) lIcm3-s y Emitter injection efficiency h Planck's constant (= 6.63 x 10-34 J-8) None J-s Time-dependent current A is Time-dependent base current in a bipolar transistor A h Time-dependent small-signal base current A ie Time-dependent collector current in a bipolar transistor A Ust of symbols xix ie Time-dependent small-signal collector current A ie Time-dependent-emitter current in a bipolar transistor A I Current A IB Static base current in a bipolar transistor A Ie Static collector current in a bipolar transistor A h Static emitter current in a bipolar transistor A Is Switch current in an EeL circuit A Ig Gate current in a MOSFET A 10 MOSFET current per unit width to length ratio for threshold A definition Idsot MOSFET saturation currerit A Ion MOSFET on current A IOff MOSFET off current A In nMOSFET current per unit width Ncm Ip pMOSFET current per unit width Nem IN nMOSFET current A Ip pMOSFET current A Ids Drain-to-source current in a MOSFET A Isx Substrate current in a MOSFET A Ids,Vt MOSFET current at threshold A 100.n nMOSFET on current per device width Ncm looN nMOSFET on current A Ion.p pMOSFET on current per device width A/cm IonP pMOSFET on current A A. MOSFET scale length J Current density is Base current density ic Collector current density in Electron current density ip Hole current density k Boltzmann's constant (= 1.38 x 10-23 JIK) cm Ncm2 Ncm2 Ncm2 Ncm2 Ncm2 11K K Scaling factor (> 1) None Mean free path cm L Length, MOSFET channel length cm LD Debye length em Ln Electron diffusion length em Lp Hole diffusion length cm Lmet Metallurgical ehannellength of MOSFET cm Leff Effective channel length of MOSFET em Lw Wire length m MOSFET body-effect coefficient mo Free-electron mass (= 9.1 x 10--31 kg) cm None kg m* Electron effective mass kg xx List of symbols M mI mt I-l I-leff fl.,. I-lp n no ni nie nieB nieE n" np Na Nd Nb Nc NB Nc NE N(E) P Po Pn Pp P Pac Pojf q Q QB QB,/ol QBE QBE,/Ol QBC QBC,/o/ Avalanche multiplication factor Electron effective mass in the longitudinal direction Electron effective mass in the transverse direction Carrier mobility Effective mobility Electron mobility Hole mobility Density of free electrons Density of free electrons at thermal equilibrium Intrinsic carrier density Effective intrinsic carrier density Effective intrinsic carrier density in base ofbipolar transistor Effective intrinsic carrier density in emitter ofbipolar transistor Density of electrons in n-region Density of electrons in p-region Acceptor impurity density Donor impurity density Impurity concentration in bulk silicon Effective density of states of conduction band Effective density of states of valence band Base doping concentration Collector doping concentration Emitter doping concentration Density of electronic states per unit energy per volume Density of free holes Density of free holes at thermal equilibrium Density of holes in n-region Density of holes in p-region Power dissipation Active power dissipation Standby power dissipation Electronic charge (= 1.6 x 10- 19 C) Charge Excess minority charge per llllit area in the base Total excess minority charge in the base Excess minority charge per unit area in the base-emitter space-charge region Total excess minority charge in the base-emitter space-­ charge region Excess minority charge per llllit area in the base-collector space-charge region Total excess minority charge in the base-collector spacecharge region None kg kg cm2N-s cm2N-s cm2N-s cm2N-s cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 l/J-m3 cm-3 cm-3 cm-3 cm-3 W W W C C C/cm2 C C/cm2 C C/cm2 C List of symbols xxi QDE QE QE,to/ QpB Q$ Qd Qi Qf Qg Qm Qit Q" Qot Qox Qp r,R rb rbi rbx rc r. ro r" RL Rs ~ R" Rp Rsd Rch Rw RSbi Rsw Rswn Rswp p Psh Pen Psd Pc Total stored minority-carrier charge in a bipolar transistor biased in the .forward-active mode Excess minority charge per llllit area in the emitter Total excess minority charge in the emitter Hole charge per unit area in base of n-p-n transistor Total charge per llllit area in silicon Depletion charge per unit area Inversion charge per llllit area Fixed oxide charge per llllit area Charge on MOS gate per llllit area Mobile charge per llllit area Interface trapped charge per unit area Excess electron charge per llllit area Oxide trapped charge per llllit area Equivalent oxide charge density per llllit area Excess hole charge per unit area Resistance Base resistance Intrinsic base resistance Extrinsic base resistance Collector series resistance Emitter series resistance Output resistance in small-signal hybrid-1r equivalent-circuit model Input resistance in small-signal hybrid-1r equivalent-circuit model Load resistance in a circuit Source series resistance Drain series resistance Electron capture rate (also called electron recombination rate) Hole capture rate (also called hole recombination rate) Source-drain series resistance MOSFET channel resistance Wire resistance per llllit length Sheet'resistance of intrinsic-base layer Equivalent switching resistance of a CMOS gate Equivalent switching resistance of nMOSFET pulldown Equivalent switching resistance ofpMOSFET pullup Resistivity Sheet resistivity Sheet resistivity of MOSFET channel Sheet resistivity of source or drain region Specific contact resistivity C C/cm2 C C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 Q Q Q Q Q Q Q Q Q Q n 1/cm3-s l/cm3-s n Q ntcm nto Q n n n-cm nto nto nto n_cm2 xxii Ust of symbols Pne, Volume density of net charge C/cm3 S MOSFET inverse subthreshold current slope Vldecade Sp Surface recombination velocity for holes cm/s (h Lateral straggle of Gaussian doping profile em t Time s tB Base transit time s tE Emitter transit time s tBE Base-emitter depletion-layer transit time s tBC Base--collector depletion-layer transit time s ti Thickness of gate insulator cm tinv Equivalent oxide thickness for inversion charge calculations cm tox Oxide thickness cm tr Transit time s tw Thickness of wire cm lsi Thickness of silicon film cm ,T , Absolute temperature Lifetime Circuit delay K s s 'b Buffered delay s Lint Intrinsic, unloaded delay s 'F Forward transit time of bipolar transistor Tn Electron lifetime s Tn nMOSFET pulldown delay s 'ne Electron lifetime in base of n-p-n transistor s 'p Hole lifetime s 'p pMOSFET pullup delay s 'pE Hole lifetime in emitter ofn-p-n transistor s 'R Reverse transit time of bipolar transistor s 'w Wire RC delay s 'E Emitter delay time s fB Base delay time s 'BE Base-emitter depletion-region delay time s 'BC Base--collector depletion-region delay time U Net recombination rate s l / c m3 -s v Velocity cm/s v Small-signal voltage V V,h Thermal velocity cm/s Vd Carrier drift velocity cm/s Vsat Saturation velocity of carriers cm/s Vr Thermal injection velocity at MOSFET source cm/s V Voltage V V Quasi-Fermi potential along MOSFET channel V VA Early voltage V Ust of symbols xxiii v.,pp Va~p VeE Vec VCE VCG VFG Vdd Vds Vdsat Vjb Vox Vg Vgs Vbs V, Von "in VOUI Vx V"high v,,/ow W Wn Wp WB Wd WdBE WaBc Warn WE Ws WD w Xj Xc,Xj If' If'B IfIbi If't lfIi If's Applied voltage across p-n diode Applied voltage.appearing immediately across p-n junction (smaller than v.,pp by IR drops in series resistances) Base-ernitter bias voltage Base-<;ollector bias voltage Collector-to-emitter voltage Control gate voltage in a nonvolatile memory device Floating gate voltage in a nonvolatile memory device Power-supply voltage Source-to-drain voltage MOSFET drain saturation voltage Flat-band voltage Potential drop across oxide Gate voltage in MOS Gate-to-source voltage in a MOSFET MOSFET body bias voltage Threshold.voltage (21f1B definition) Linearly extrapolated threshold voltage Input node voltage of a logic gate Output node voltage of a logic gate Node voltage between stacked nMOSFETs of a NAND gate The higher threshold voltage ofa nonvolatile memory device The lower threshold voltage of a nonvolatile memory device Width, MOSFET width nMOSFET width pMOSFET width Intrinsic-base width Depletion-layer width Base-emitter junction depletion-layer width Base-<;ollector junction depletion-layer width Maximum depletion-layer width in MOS Emitter-layer width (thickness) Source junction depletion-layer width Drain junction depletion-layer width Angular frequency Junction depth Depth of inversion channel Potential Difference between Fermi potential and intrinsic potential Built-in potentia] Fermi potential Intrinsic potential Surface potential V V V V V V V V V V V V V V V V V V V V V V cm em cm em cm cm cm cm cm cm em radls em em V V Y V V V 1 Introduction Since the invention of the bipolar transistor in 1947, there has been an unprecedented growth ofthe semiconductor industry, with an enormous impact on the way people work and live. In the last thirty years or so, by far the strongest growth area of the semicon­ ductor industry has been in silicon very-Iarge-scale-integration (VLSI) technology. The sustained growth in VLSI technology is fueled by the continued shrinking of transistors to ever smaller dimensions. The benefits of miniaturization - higher packing densities, higher circuit speeds, and lower power dissipation - have been key in the evolutionary progress leading to today's computers, wireless units, and communication systems that offer superior performance, dramatically reduced cost per function, and much reduced physical size, in comparison with their predecessors. On the economic side, the integrated-circuit (IC) business has grown worldwide in sales from $1 billion in 1970 to $20 billion in 1984 and has reached $250 billion in 2007. The electronics industry is now among the largest industries in terms of o~tput as well as employment in many nations. The importance of microelectronics in economic, social, and even political development throughout the world will no doubt continue to ascend. The large world­ wide investment in VLSI technology constitutes a formidable driving force that will all but guarantee the continued progress in Ie integration density and speed, for as long as physical principles will allow. ._j 1.1 Evolution of VLSI Device Technology 1.1.1 Historical Perspective An excellent account of the evolution of the metal--oxide-semiconductor field-effect transistor (MOSFET), from its initial concept to VLSI applications in the mid 1980s, can be found in the paper by Sah (Sah, 1988). Figure 1.1 gives a chronology of the major milestone events in the development of VLSI techoology. The bipolar transistor technol­ ogy was developed early on and was applied to the first integrated-circuit memory in mainframe computers in the 1960s. Bipolar transistors have been used all along where raw circuit speed is most important, for bipolar circuits remain the fastest at the individual-circuit level. However, the large power dissipation of bipolar circuits has severely limited their integration level, to about 104 circuits per chip. This integration level is Quite low by today's VLSI standard. 2 1 Introduction 1.1 Evolution ofVLSI Device Technology 3 First bipolar transistor (1947) One-transistor DRAM cell invented (1968) First MOSFET (l960) VLSI era 1940 1950 1970 1980 1990 2000 2010 CMOS invented (1963) IC invented (1958) FITst micro­ processor (1971) Figure 1.1. A brief chronology of the major milestones in the development of VLSI. The idea ofmodulating the surface conductance ofa semiconductor by the application of an electric field was first reported in 1930. However, early attempts to fabricate a surface-field-controlled device were not successful because of the presence of large densities of surface states which effectively shielded the surface potential from the influence of an external field. The first MOSFET on a silicon substrate using SiOz as the gate insulator was fabricated in 1960 (Kahng and Atalla, 1960). During the 1960s and 1970s, n-channe1 and p-channel MOSFETs were widely used, along with bipolar tran­ sistors, for implementing circuit functions on a silicon chip. Although the MOSFET devices were slow compared to the bipolar devices, they had a higher layout density and were relatively simple to fabricate; the simplest MOSFETchip could be made using four masks and a single doping step. However, just like bipolar circuits, single-polarity MOSFET circuits suffered from large standby power dissipation, and hence were limited in the level of integration on a chip. The major breakthrough in the level of integration came in 1963 with the invention of CMOS (complementary MOS) (Wanlass and Sah, 1963),· in which n-channel and p-channel MOSFETs are constructed side by side on the same substrate. A CMOS circuit typically consists of an n-channel MOSFET and a p-channel MOSFET connected in series between the power-supply terminals, so that there is negligible standby power dissipation. Significant power is dissipated only during switching of the circuit (i.e., only when the circuits are active.) By cleverly designing thc "switch activities" of the circuits on a chip to minimize active power dissipation, engineers have been able to integrate hundreds of millions of CMOS .transistors on a single chip and still have the chip readily air-coolable. Until the minimum feature size of lithography reached 180 nm, the integra­ tion level of CMOS was not limited by chip-level power dissipation, but by chip fabrication technology. Another advantage of CMOS circuits comes from the ratioless, full rail-to-raillogic swing, which improves the noise margin and makes a CMOS chip easier to design. lE+l1 5 lE+10 IE+9 :.Qa. "8. IB+8 i 1E+7 'Vj .g.c.. lE+6 0 "" lE+5 lE+4 iP!Aiill IMPul 2 E 2­ "N 'Vj e 0.5 ~ 107 1600-1700 0.014 1.0 0.006 0.5 x 10-6 let N(E) dE be the number of electronic states per unit volume with an energy between E and E+ dE in the conduction band, then N(E) dE = 2g dpx dPy dp= h3 ' (2.1) where dpx dpy dpz is the volume in the momentum space within which the electron energy lies between E and E + dE, g is the number ofequivalent minima in the conduction band, and the factor of two arises from the two possible directions of electron spin. The conduction band of silicon has a sixfold degeneracy, so g = 6. Note that MKS units are used here (e.g., length must be in meters, not centimeters). If the electron kinetic energy is not too high, one can consider the energy-momentum relationship near the conduction-band minima as being parabolic and write p2 2 E Ec = + -Y +..!!L. (2.2) 2m). 2m,' where E - Ec is the electron kinetic energy, and nix, nip mz are the effective masses. The constant energy surface in momentum space is an ellipsoid with the lengths of the symmetry axes proportional to the square roots of nix, mY' and m,. For the silicon conduction band in the <100> direction, two of the effective masses are the transverse mass mt = O.19mo, and the third is the longitudinal massm,= 0.92mo, where mo is the free electron mass. The volume ofthe ellipsoid given by Eq. (2.2)in momentum space is (4m3) (8m"m..,mz)1/2(E- Ec)312. Therefore, the volume dPxdpydpz within which the electron energy lies between E and E + dE is 41t(2m"m..,mz)Jl2(E- Ee)1I2dE and Eq. (2.1) becomes 14 2 Basic Device Physics 2.1 Electrons and Holes in Silicon 15 E +E +E 1 Conduction band --­ ~ ---~·r- 1 ; Figure 2.2. j Valence :..:...:..::.=-------,------:-----­ band N(E) -1/-2 ID(E) N(E)ID(E) Schematic plots of density of states, Fermi-Dirac distribution function, and their products versus electron energy in a band diagram. (After Sze, 1981.) N(E) dE = 8ngv2m m, m7 ,-,x } - ~ y E - Ee dE = 8ngJ2m2 m[ L1 t ~ Y E - Ee dE. (2.3) The 3-D electron density of states in an energy diagram is then a parabolic function with its downward apex at the conduction-band edge, and vice versa for the hole density of states in the valence band. These are shown schematically in Fig. 2.2 (Sze, 1981). 2.1.1.3 Statistical Distribution Function The energy distribution of electrons in a solid is governed by the laws of Fermi-Dirac statistics. For a system in thermal equilibrium, the principal result of these statistics is the Fermi-Dirac distribution fimction, which gives the probability that an electronic state at energy E is occupied by an electron, !D (E) = ---=­ (2.4) Here k= 1.38 x 10-23 JIK. is Boltzmann's constant, and Tis the absolute temperature. This function contains a parameter, Eft called the Fermi level. The Fermi level is the energy at which the probability of occupation ofan energy state by an electron is exactly one-half. At absolute zero temperature, T=O K, all the states below the Fermi level are filled UD= I for E < Ef), and all the states above the Fermi level are empty UD = 0 for E > Ef). At finite temperatures, some states above the Fermi level are filled as some states below become empty. In other words, the probability distribution!D(E) makes a smooth transition from unity to zero as the energy increases across the Fermi level. The width of the transition is governed by the thermal energy, kT. This is plotted schematically in Fig. 2.2, with a Fermi level in the middle of the forbidden gap (for reasons that will soon be clear). It is important fo to keep in mind that the thermal energy at room temperature is 0.026 eV, or roughly of the silicon bandgap. In most cases when the energy is at least several kT above or below the Fermi level, Eq. (2.4) can be approximated by the simple formulas !D(E) ~ e-(E-Er)/kT for E > Ef and !D (E) ~ 1- e-(Er-E)/kT for E Ep, thenfDI(E) > fD2(E), which means that at every energy E where electronic states are available in both systems, a larger fraction of the states in system I are occupied by electrons than in system 2. Equivalently, a larger fraction of the states in system 2 are empty than in system I at energies where electronic states exist. Since the two systems in contact are free to exchange electrons, there is a higher probability for the electrons in system I to re-distribute to system 2 than vice versa. This leads to a net electron transport from system I to system 2, i.e., current flows (defined in terms ofpositive charges) from system 2 to system I. If there are no power sources connected to the systems to sustain the Fermi level imbalance, eventually the two systems will come to an equilibrium and EfJ = Ep. No further net electron flow takes place once the same fractions ofthe electronic states in the two systems are occupied at every energy E. Note that this conclusion is reached regardless of the specific density of states in each of the two systems. For example, the two systems can be two metals, a metal and a semiconductor, two semiconductors of different doping or different composition. When two systems are in thermal equilibrium with no current flow between them, their Fermi levels must be equal. A direct extension is that, for a continuous region of metals and/or semiconductors in contact, the Fermi leJJel at thermal equilibrium is flat, i.e., spatially constant, throughout the region. The role of Fermi level at the contacts when there is an applied voltage driving a steady-state current is further discussed in Section 2.1.4.5. 2.1.1.4 Carrier Concentration Since fD(E) is the probability that an electronic state at energy E is occupied by an electron, the total number ofelectrons per unit volume in the conduction band is given by n = lEro,o N(E)fD(E)dE. (2.7) Here the upper limit of integration (the top of the conduction band) is taken as infinity. Both the product N(E)fD(E) and n, p are shown schematically in Fig. 2.2. In general, Eq. (2.7) is a Fermi integral of the order 112 and must be evaluated numerically (Ghandhi, 1968). For nondegenerate silicon with a Fermi level at least 3kT/q below the edge of the 16 2 Basic Device Physics 2.1 Electrons and Holes in Silicon 17 conduction band, the Penni-Dirac distribution function can be approximated by the Maxwell-Boltzmann distribution, Eq. (2.5). Equation (2.7) then becomes r"; V n = 8ng~ E - Ece-(E-Ej)/kTdE. (2.8) hiE, With a change ofvariable, the integral can be expressed in the fonn of a gamma function, r(3/2), which equals nll2l2. The electron concentration in the conduction band is then n = Nce-(E,-Ef)/kT, (2.9) where the pre-exponential factor is defined as the effective density ofstates, Nc = 2 g V; ; ; ; 1 ;m;2/ (2nkT) h2 3(2 A similar expression can be derived for the hole density in the valence band, (2.lO) p = Nve-(Er-E,)/kT, (2.11 ) where Nv is the effective density of states of the valence band, which depends on the hole effective mass and the valence band degeneracy. Both Nc and Nvare proportional to r3J2. Their values at room temperature are listed in Table 2.1 (Green, 1990). Por an intrinsic silicon, n = p, since for every electron excited into the conduction band, a vacancy or hole is left behind in the valence band. The Penni level for intrinsic silicon, or the intrinsic Fermi level, Ei, is then obtained by equating Eq. (2.9) and Eq. (2.11) and solving for Ef £. = Ef= Ec + Ev _ kTln(Nc) I 2 2 Nv ' (2.12) By substituting Eq. (2.12) for Ef in Eq. (2.9) or Eq. (2.11), one obtains the intrinsic carrier concentration, ni = n = p: ni = VNcNve-(E,-E,,)/2kT = VNcN,.e-Eg/2kT. (2.13) Since the thennal energy, kT, is much smaller than the silicon bandgap Eg , the intrinsic Fermi level is very close to the midpoint between the conduction band and the valence band. In fact, Ei is sometimes referred to as the midgap energy level, since the error in assuming Ei to be (Ec+ Ev)/2 is only about 0.3 kT. The intrinsic carrier concentration ni at room temperature is 1.0 x 1010 cm-3, as given in Table 2.1, which is very small compared with the atomic density of silicon. Equations (2.9) and (2.11) can be rewritten in tenns of ni and Ei : n = l1ie(ErEi)/kT, (2.14) p = nie(Ei-Er)/kT (2.15) These equations give the equilibrium electron and hole densities for any Penni level position (not too close tothe.band,edges) relative to the intrinsic 'Penni level at the midgap. In the next section, we will show how the Penni level varies with the type and concentration of impurity atoms in silicon. Since any change in Ef causes reciprocal changes in nand p, a useful, general relationship is that the product pn =n~ I in equilibrium is a constant, independent ofthe Fermi level position. (2.16) 2.1.2 n-Type and p-Type Silicon Intrinsic silicon at room temperature has an extremely low free-carrier concentration; therefore, its resistivity is very high. In practice, intrinsic silicon hardly exists at room temperature, since it,would require materials with an unobtainably high purity. Most impurities in silicon introduce additional energy levels in the forbidden gap and can be easily ionized to add either electrons to the conduction band or holes to the valence band, depending on where the impurity level is (Kittel, 1976). The electrical conductivity of silicon is then dominated by the type and concentration of the impurity atoms, or dopants, and the silicon is called extrinsic. 2.1.2.1 Donors and Acceptors Silicon is a column-IV element with four valence electrons per atom. There are two types of impurities in silicon that are electrically active: those from column V such as arsenic or phosphorus, and those from column III such as boron. As is shown in Pig. 2.3, a column-V atom in a silicon lattice tends to have one extra electron loosely bonded after fonning covalent bonds with other silicon atoms. In most cases, the thennal energy at room temperature is sufficient to ionize the impurity atom and free the extra electron to the conduction band. Such types of impurities are called donors; they become positively charged when ionized. Silicon material doped with column-V impurities or donors is '0'0'0' '0'®-0' ;0 0=0: • 1 .. 1• I• • I• 1• I• •• -q• •• '0:0 0 0:6:0: :0 6:0 ',' •• O+q •• '0:0:0 0:0 0 0 0:0­ Figure 2.3. (a) (b) (c) Three basic bond pictures of silicon: (a) intrinsic Si with no impurities, (b) n-type silicon with donor (Phosphorus), (c) p-type silicon with acceptor (boron), (After Sze, 1981.) 18 2 Basic Device Physics ,_. -. Ed Ee Ef Eg E; - -Ei Ev --• • • • • _. ~f E. Ev Figure 2.4. • Free electron H o Free hole (+) (a) n-type (b) p-type Energy-band diagram representation of (a) donor level Ed and Fermi level Efin n-type silicon, (b) acceptor level Ea and Fermi level Ejin p-type silicon. called n-type silicon, and its electrical conductivity is dominated by electrons in the conduction band. On the other hand, a column-III impurity atom in a silicon lattice tends to be deficient by one electron when forming covalent bonds with other silicon atoms 2.3). Such an impurity atom can also be ionized by accepting an electron from the valence band, which leaves a free-moving hole that contributes to electrical conduction. These impurities are called acceptors; they become negatively charged when ionized. Silicon material doped with column-III impurities or acceptors is called p-type silicon, and its electrical conductivity is dominated by holes in the valence band. It should be noted that impurity atoms must be in a substitutional site (as opposed to interstitia/) in silicon in order to be electrically active. In terms ofthe energy-band diagrams in 2.4, donors add allowed electron states in the bandgap close to the conduction-band edge, while acceptors add allowed states just above the valence-band Donor levels contain positive charge when ionized (emp­ tied). Acceptor levels contain negative charge when ionized (filled). The ionization energies are denoted by Ed for donors and Ea-- Ev for acceptors, respectively. Figure 2.5 shows the donor and acceptor levels of common impurities in silicon and their ionization energies (Sze, 1981). Phosphorus and arsenic are commonly used donors, or n-type dopants, with low ionization energies on the order of 2kT, while boron is a used acceptor or p-type dopant with a comparable ionization energy. Figure 2.6 shows the solid solubility of important impurities in silicon as a function of annealing temperature (Trumbore, 1960). Arsenic, boron, and phosphorus have the highest solid solubility among all the impurities, which makes them the most important species in VLSI technology. !I -,,:10 ~I ~I< II :;:1 !:I ::; Vi I I "r1-:I I' I ;:1iMiO ~I I 0:::;, I' ~I :S10 &11 ":1 ~I ~I ~I 10 ;;':<)1'1"< I "'10 I "'10 I I ;:';~IO .~ ;:';1 ;:1i11'0 0 81 ~II ":1 :;;I~ 1:Sl ~I­ :E :E '."0, 1018 ~ Vl 1017 1016 Figure 2.6. lOIS 500 600 700 800 900 1000 11 00 1200 1300 1400 T("C) Solid solubility of various elements in silicon as a function of temperature. (Afief Trumbore, 1960.) 2.1.2.2 Fermi Level in Extrinsic Silicon In contrast to intrinsic silicon, the Fenni level in an extrinsic silicon is not located at the midgap. The Fenni level in n-type silicon moves up towards the conduction band, consistent with the increase in electron density as described by Eq. (2.9). On the other hand, the Fenni level in p-type silicon moves down towards the valence band, consistent with the increase in hole density as described by Eq. (2.11). These cases are depicted in 1:1 Fig. 2.4. The exact position ofthe Fenni level depends on both the ionization energy and the concentration of dopants. For example, for an n-type material with a donor impurity concentration N.J. the charge neutrality condition in silicon requires that n N"d +p, where N"d is the density of ionized donors given by N:; (I - N,tli - fD(Ed)] = Nd --;---',.-;0;--:::-:-;-:-::: 1+ (2.17) (2.18) 2.1 Electrons and Holes in Silicon 21 since the probability that a donor state is occupied by an electron (i.e., in the neutral state) is fD(Ed). The factor! in tlie denominator offD(Ed) arises from the spin degeneracy (up or available electronic states associated with an ionized donor level] (Ghandhi, 1968). Substituting Eq. (2.9) and Eq. (2.11) for nand pin Eq. (2.17), one obtains N ce-(E,.-E11/kT Nd + (2.19) which is an algebraic equation that can be solved for In n-type silicon, electrons are the majority current carriers, while holes are the minority current carriers, which means that the second tenn on the right-hand side (RHS) of Eq. (2.19) can be neglected. For shallow donor impurities with low to moderate concentration at room temperature, (NdiNe) exp [(Ee - Ed) Ik 11 « I, a good approximate solution for (Z:). Ec Ef = kTln (2.20) In this case, the Fenni level is at least a few kTbelow and essentially all the donor N'd levels are empty (ionized), i.e., n = n;, It was shown earlier (Eq. (2.16» that, in equilibrium, the product of majority and minority carrier densities equals independent of the dopant type and Fenni level position. The hole density in n-type silicon is then given by p=niINd. Likewise, for p-type silicon with a shallow acceptor concentration given by (Z:) - Ev = kTIn (2.21) the Fermi level is (2.22) the hole density is p N;; Nu , and the electron density is n n7lNa . (2.23) Figure 2.7 plots the Fenni-Ievel position in the energy gap versus temperature for a wide range of impurity concentration (Grove, 1967). The slight variation of the silicon bandgap with temperature is also incorporated in the figure. It is seen that as the temperature increases, the Fenni level approaches the intrinsic value near midgap. When the intrinsic carrier concentration becomes larger than the doping concentration, the silicon is intrinsic. In an intennediate range of temperature including room tempera­ ture, all the donors or acceptors are ionized. The majority carrier concentration is then given by the doping concentration, independent of temperature. For temperatures below this range, freeze-out occurs, i.e., the thennal energy is no longer sufficient to ionize all the impurity atoms even with their shallow levels 1981). In this case, the Detailed study showed that there are no other degeneracy with the electronic ground state in a donor except for spin (Ning and Sah, 1971). 22 2 Basic Device Physics 0.6 Conduction-band edge Ec 0.4 0.2 ;;­ .!', ~- 0 I "-1..... -0.2 -0.4 Figure 2.7. -0.6 L 0 100 200 300 400 500 Temperature (K) The Fenni level in silicon as a function of temperature for various impurity concentrations. (After Grove, 1967.) majority-carrier concentration is less than the doping concentration, and one would have to solve Eq. (2.19) numerically to find Efi n, and p (Shockley, 1950). Instead of using Ne, Nv and referring to and Ev, Eq. (2.20) and Eq. (2.22) can be written in a more useful form in terms of nj and Ej defined by Eq. (2.12) and Eq. (2.13): Er Ei kTln(~~) (2.24) for n-type silicon, and E; - Ef= kTln(~;') (2.25) for p-type silicon. In other words, the distance between the Fermi level and the intrinsic Fermi level near the midgap is a logarithmic function ofdoping concentration. These expressions will be used extensively throughout the book. 2.1.2.3 Fermi Level in Degenerately Doped Silicon For heavily doped silicon, the impurity concentration Nd or Na can exceed the effective density ofstates Nc or N", so that Ec or Ef ,,)/kT I . (2.67) nl It equals when tPP tPn 'IIf. Quasi-Fermi potentials are used extensively in the rest of the book for current calculations. 2.1.4.7 Continuity Equations The next set of equations are continuity equations based on the conservation of mobile charge: an _ - ~ q oaJx n R" + G" (2.68) 2 While it appears to be physically inconsistent to have half of the electron stales occupied at one energy and half oflhe electron slates empty at a different energy, quasi-Fcmli levels are defined mainly for mathematical convenience. 34 2 Basic Device Physics and ~ot ~ 0, (2.69) where Gn and Gp are the electron and hole generation rates, Rn and Rp are the electron a and hole recombination rates, and 0 J,/ox and Jlax are the net flux of mobile charges in and out of x. At thermal equilibrium, the generation rate is equal to the recombination rate and np = n;. When excess minority carriers are injected by light or other means, the recombination rate exceeds the generation rate, which establishes a tendency to return to equilibrium. In silicon, the probability ofdirect band-to-band recombination by a radiative (transfer of energy to a photon) or Auger (transfer of energy to another carrier) process is very low due to its indirect bandgap. Most of the recombination processes take place indirectly via a trap or a deep impurity level near the middle of the forbidden gap. This is often referred to as the Shockley-Read recombination (Shockley and Read, 1952). Under low-injection conditions, the recombination rate is inversely proportional to the minority-carrier time, 1:, which is in the range of 10-4 to 10-9 s, depending on the quality of the silicon crystal. The minority-carrier diffusion length, which is the average distance a minority carrier travels before it recombines with a majority carrier, is given by L '" (lh)ll2, where D is the diffusion coefficient. The diffusion length is typically a few microns to a few millimeters in silicon. (A discussion of the minority-carrier diffusion process can be found in Section 2.2.4.) Since L is much larger than the active dimensions ofa VLSI device, generation-recombination in general plays very little role in device operation. Only in a few special circumstances, such as CMOS latch-up, the SOl floating-bod effect, junction leakage current, and radiation-induced soft error, must the cr..nprnt;nn_ recombination mechanism be taken into account. More detailed discussions on generation and recombination can be found in Appendix 5. In the steady state, an/at apia! = 0. Also, the net electron reduction rate must equal the net hole reduction rate, Gn = Rp- Gp, so that there is no buildup ofnet immobile charge with time at any point. Subtracting Eq. (2.69) from Eq. (2.68) then yields (Xln +Jp)/ax = 0, or continuity ofthe total current, I n +Jp• In a device region where generation and recombi­ nation are negligible, the continuity equations in the steady state are reduced to dJ,/dx dJ/dx 0, which simply states the conservation of electron current and conservation of hole current, respectively. 2.1.4.8 Dielectric Relaxation Time In contrast to the minority-carrier lifetime discussed above, the majority-carrier response time is very short in a semiconductor. It can be estimated for a one-dimensional (I-D) homogeneous n-type silicon as follows. Suppose there is a local perturbation in the carrier density, iln. From Poisson'8 equation, the resulting charge imbalance sets up a field a'it/fu: around the point of perturbation. This, in tum, leads to according to Ohm's law,}" = 'it/Pm which tends to restore the majority carrier concentration back to its equilibrium, charge neutral value. Neglecting and Gn in the continuity equation, Eq. (2.68), one then obtains 2.2 p-n Junctions 35 o6,.n 1oJ" 1 o'it 6,.n ot q8x- qpn Pnilsi (2.70) The solution to this equation takes the form of 6,.n (t) ex where Pnesi is the majority-carrier response time, 'or dielectric relaxation time. The majority-carrier response time in silicon is typically on the order of 10-12 s, which is shorter than most device switching times. Note that Pnesi is the minimum response time for an ideal I-D case without any parasitic capacitances. In practice, the majority-carrier response time may be limited the RC delay of the specific silicon device structure and contacts. 2.2 2.2.1 p-n Junctions p-n Junctions, also called Jrn diodes, are important devices as well as important components of all MOSFET and bipolar devices. The characteristics of p-n diodes are therefore important in determining the characteristics ofVLSI devices and circuits. A p-n is formed when one region of a semiconductor substrate is doped n-type and an immediately adjacent region is doped p-type. In practice, a silicon p-n diode is usually local region ofa larger region ofdoped silicon. For instance, a region of a p-type silicon substrate or "well" can be counterdoped with n-type impurities to form the n-type region of a p--n diode. The n-type region thus formed has a donor concentration higher than its acceptor concentration. A doped semiconductor region is called compensated if it contains both donor and acceptor impurities such that neither impurity concentration is negligible compared to the other. For a compensated semiconductor region, it is the net doping concentration, Nd Na if it is n-type and Na - Nd if it is p-type, that determines its Fermi level and its mobile carrier concentration. However, for simplicity, we shall derive the char­ acteristics and behavior ofp-n diodes assuming none of the doped regions are compen­ sated, i.e., the n-sides ofthe diodes have a net donor concentration of Nd and the p-sides have a net acceptor concentration of No- The resultant equations can be extended to diodes with compensated doped regions simply by replacing Nd by Nd - Na for the n-regions and replacing No by No - Nd for the p-regions. Energy-Band Diagrams for a p-n Diode It was shown in Sections 2.1.1.3 and 2.1.4.5 that at thermal equilibrium or when there is no net electron or hole current, the Fenni level is spatially constant. Furthermore, when an extemal voltage Vupp is connected to two contacts ofa piece of silicon, the Fenni level at the lower voltage contact is shifted relative to the Fermi level at the higher voltage contact by q Vapp. In this section, we apply these results to establish the energy-band diagrams for a p-n diode under various bias conditions_ Consider a p-silicon region and an n-silicon region physically separate from each other. As discussed in Section 2.1.2.2, the Fermi level for a p-type silicon lies close to its 36 2 Basic Device Physics (a) Ec EI Ef E, p-Iype n-type ----Ec ·-·····························-·i I -----E" (0) Ec - - - - , ~ ~ ~ ~ ~ ~ '------Ev (e) ;, ~ ,V_ ,: Vapp Rgure 2.12. Energy-band diagrams for a p-n diode. (a) A p-silicon region and an n-silicon region physically separate from each other. (b) A p-n junction at thermal equilibrium. (c) A p-n diode connected to a battery, with the n-side connected to the negative end and the p-side connected to the positive end of the battery. The solid vertical bars represent the ohmic contacts of the p- and n-regions. For simplicity and clarity of the figure, Ei is not shown. valence band, and that for an n-type silicon lies close to its conduction band. The energy­ band diagrams for the two silicon pieces are illustrated schematically in Fig. 2. 12(a). Ifthe p-silicon and the n-silicon are brought together to form a p-n diode, the resulting energy-band diagram is as shown in Fig. 2.12(b). At thermal equilibrium, the Fermi level must remain flat across the entire p-n diode structure, causing the energy bands of the p-region to lie higher than those of the n-region. Near the physical junction, the energy­ bands are bent in order to maintain energy-band continuity between the p-region and the n-region. The band bending implies an electric field, 'I = -d//fJdx, in this transition region. This electric field causes a drift componcnt of electron and hole currents to flow. At thermal equilibrium, this drift-current component is exactly balanced by a diffusion component of clectron and hole currents flowing in the opposite direction caused by the large electron and hole concentration gradients across the junction. The net result is zero electron and hole currents across thc p-n junction at thermal equilibrium. On both sides of the band-bending region, the energy bands are flat and there is no electric field. These regions are referred to as the quasineutral regions. If a battery of voltage Yapp is connected to the diode, with the p-side connected to the end of the battery and the n-side connected to the negative end of the battery, the 2.2 p-n Junctions 37 Fermi level at the n-side contact becomes shifted by qVapp relative to the Fermi level at the p-side contact. This isil1us.trated in Fig. 2.12(c). 2.2.1.1 Built-in Potential Consider the energy-band diagram in Fig. 2.12(b). The difference between the energy bands on the p-side and the corresponding energy bands on the n-side is Eccp-side) - Ec q//fb;, where //fbi is the built-in potential of the p-n junction. In this subsection, we want to establish the relationship between //fbi and the p- and n-side doping concentrations. To facilitate description of both the n-side and the p-side of a diode simultaneously, when necessary for clarity, we shall distinguish the parameters on the n-side from the corresponding ones on the p-side by adding a subscript n to the symbols associated with the parameters on the n-side, and a subscript p to the symbols associated with the parameters on the p-side (Shockley, 1950). For example, Efn and E in denote the Fermi level and intrinsic Fermi level, respectively, on the n-side, and Ef'p and Eip denote the Fermi level and intrinsic Fermi level, respectively, on the p-side. Similarly, nn and Pn denote the electron concentration and hole concentration, respectively, on the n-side, and lip and Pp denote the electron concentration and hole concentration, respectively, on the p-side. Thus, lin and Pp signifY majority-carrier concentrations, while np and Pn signifY minority-carrier concentrations. Consider the n-side ofa p-n diode at thermal equilibrium. Ifthe n-side is non-degenerately doped to a concentraon of N", then the separation between its Fermi level, which is fiat across the diode, and its intrinsic Fermi level is given by (2.24), namely C:;) E;n kTln kTln (~;'), where nnO denotes the n-side electron concentration at thermal equilibrium. Similarly, for the nondegenerately doped p-side of a p-n diode at thermal equilibrium, with a doping concentration of No, we have Eli' kTlne:) kTln(~;), (2.72) where PpO is the p-side hole concentration at thermal equilibrium. The built-in potential across the p-n diode is Since Eq. q//fbi = Ein = kTln (2.73) gives nllopnO = npOppO = liT, Eq. (2.73) can also be written as q//fbi kTln(P\PPllO()) kTln(l1nO ), 111'0 (2.74) 38 2 Basic Device Physics which relates the built-in potential to the electron and hole densities on the two sides of the p-n diode. 2.2.2 2.2.2.1 Abrupt Junctions n.11alY"'" of a p-n diode is much simpler if the junction is assumed to be abrupt, i.e., the doping impurities are assumed to change abruptly from p-type on one side to n-type on the other side of the junction. The abrupt-junction approximation is reasonable for modem VLSI devices, where the use of ion implantation for doping the junctions, followed by low-thermal-cycle diffusion andlor annealing, results in junctions that are fairly abrupt. Besides, the abrupt-junction approximation often leads to closed-form solutions which render the device physics much easier.to understand. Depletion Approximation The spatial dependence of the electrostatic potential 'II;ex) is governed by Poisson's (2.44). For a diode at thermal equilibrium, the electron and hole and p(x), are given by Eqs. (2.49) and (2.50), respectively. As suggested is independent of x in the uniformly doped quasineutral regions. changes from being at the p-region end of the band-bending region to being -E;"lq at the n-region end of the band-bending region. Within the band-bending region, Eq. (2.49) suggests that the electron density drops very rapidly as 'II;(x) changes, being equal to the ionized donor density at the n­ region end and dropping lOx at room temperature for every 60 mV change in Thus, the density ofelectrons within the band-bending region is negligible compared to the density of ionized donors except for a very narrow region adjacent the quasineutral n-region where q('II; - 'II;) is less than about 3kT. Similarly, Eq. (2.50) suggests that, within the band-bending region, the density of holes is negligible compared to the density of ionized acceptors except for a very narrow region adjacent to the quasineu­ tral A closed-form solution to Poisson's equation can be obtained if the electron and hole densities are assumed to be negligible in the entire band-bending region. This is called the depletion approximation. In this case, the abrupt junction is approximated by three regions as illustrated in Fig. 2.13(a). Both the quasineutral p-region, i.e., the with x < -XI) and the quasineutral n-region, i.e., the region with x> X n, are assumed to be charge-neutral, while the transition region, the region with - xl' < X < X n, is assumed to be depleted of mobile electrons and holes. As we shall show later, the depletion-layer widths, xp and x", are dependent on the donor concentration Nd on the n-side and the acceptor concentration No (lTI the p-side, as well as on the applied voltage Vapp across the junction. The depletion approximation is quite accurate for all applied voltages except at large forward biases, where the mobile-charge densities are not negligible eompared to the ionized impurity concentrations in the transition region. The transition is often referred to as the depletion region or depletion layer. Since the transition is not charge-neutral, it is also referred to as the space-charge or space­ charge layer. 2.2 p-n Junctions 39 QuasineutraJ p-region (a) Depletion region ~ fJ,Je'(x) . -xp 0 Quasineutral n·region -qNd x x. -qNa (b) x (e) W;(X)-'h(-X p) ~ I. -Xp Figure 2.13. Depletion approximation of a electrostatic potential. V;m •x x. (a) charge distribution, (b) electric field, and (c) Poisson's equation, i.e., (2.44), for the depletion region is = d'if;' -d = i..[P(x) - n(x) + N/i(x) Xes; q N;(x)] (2.75) Gsi where is the ionized-donor concentration and is the ionized-acceptor concentra­ tion, and where the mobile-electron and -hole concentrations have been set to zero, consistent with the depletion approximation. For simplicity, we shall assume that all the donors and acceptors within the depletion region are ionized, and that the junction is abrupt and not compensated, i.e., there are no donor impurities on the p-side and no acceptor impurities on the n-side. With these assumptions, Eq. (2.75) becomes d21J1i - dx2 qN" for 0 5 x 5 Xn est (2.76) 40 2 Basic Device Physics , 2.2 p-n Junctions 41 2.2.2.2 and d 2'f1i - dx2 fisi for -Xp ::; x::; O. (2.77) the p-side is biased positively relative to the n-side, as in the case illustrated in Fig. 2.12(c). The total potential drop 'fImand.theextemally applied voltage Vapp are related by 'fIm = 'fIbi Vapp , (2.81) Integrating Eq. (2.76) once from x 0 to x = XI!, and Eq. (2.77) once from x = -xp to x = 0, subject to the boundary conditions of d'fld dx 0 at x = - xp and at x XI!, we obtain the maximum electric field, which is located at x O. That is, 'f", == = qNdxn 8si est (2.78) It is clear from (2.78) that the total space charge inside the n-side of the depletion region is equal (but opposite in sign) to the total space charge inside the p-side of the depletion region. Thus, in Fig. 2.13(a), the two charge distribution plots have the same where Vapp > 0 means the diode is forward biased and v;.pp < 0 means the diode is reverse biased. If Eq. (2.81) is used in Eq. (2.80), it the total depletion-layer width of a forward- or reverse-biased diode. A quasineutral region has a finite resistivity determined by its dopant impurity concentration Fig. 2.9). When a current flows in a region of finite resistivity, there is a corresponding voltage drop, or lR drop, along the current path. In writing Eq. (2.81), the lR drops in the quasineutral regions are assumed to be negligible so that Vapp is the same as the voltage across the space-charge region, V'app' -If IR drops in the quasineutral regions are not negligible, then Vapp should be replaced by V'app in Eq. (2.81). area. Equation (2.78) could have been obtained directly from Gauss's law, i.e., Eq. (2.43). • p-n diode as a rectifier. When a diode is forward biased, the energy barrier limiting Let 1/1_ be the total potential drop across the p--n junction, 'fIm = ['fIi(xn)­ current flow is lowered, causing electrons to be injected from the n-side into the p-side The total potential drop can be obtained by integrating twice, the second time from x -xp to X xn • That is, (2.76) and L:~ 'fIm d'fli(X) L:~ 'f(x)dx ~mWd (2.79) 2 where Wd XI! + xp is the total width ofthe depletion layer. It can be see from Eq. (2.79) that 'fIm is equal to the area in the ~(x) -x plot, i.e., Fig. 2.l3(b). Eliminating 'I ~ from Eqs. (2.78) and (2.79) gives 2esi(Na + Nd)'fIm qNaNd (2.80) This equation relates the total width of the depletion layer to the total potential drop and holes injected from the p-side into the n-side, resulting in a current flow through the diode. As we shall show in Section 2.2.4, the forward current increases exponen­ tially with V'app and hence can be very large. When a diode is reverse biased, the energy barrier limiting current flow is increased. There is no current flow due to electron and hole injection, only a relatively low background or leakage current. Thus a diode has rectifying current-voltage characteristics, being conducting when it is forward biased, and nonconducting when it is reverse biased. This is illustrated in 2.14. The equations governing the current-voltage characteristics ofa diode will be derived in Sections 2.2.3 and 2.2.4. • Depletion-layer capacitance. Consider a small change dVapp in the applied voltage. dVapp causes a charge per unit area dQ to flow into the p-side, which is equal to the change in the charge in the p-side depletion region. Since all mobile carriers are 0.08 across the junction and to the doping concentrations of the two sides of the diode. Externally Biased Junctions in the absence of any externally applied voltage, the total electrostatic potential drop 111m across a p-n diode is equal to the built-in potential 'fIbi, as indicated in 2.12(b). This built-in potential represents an energy barrier limiting the flow ofelectrons from the n-side to the p-side and the flow of holes from the p-side to the n-side. An externally applied voltage across a p--n diode shifts the Fermi level at the n-region contact relative to the Fenni level at the p-region contact. )fthe applied voltage causes 'fIm to be reduced, the diode is said to beforward biased. Ifthe applied voltage causes lI'm to be increased, the diode is said to be reverse biased. In considering a p--n diodc in the context of VLSI devices, the forward-bias characteristics are more interesting than the reverse-bias characteristics. 0.06 :? § t; ~ 0.04 '".".. r '0 0 is 0.02 01 -0.5 ,J I 1 0 0.5 Applied voltage (V) Therefore, we shall adopt the convention where a positive applied voltage also means a forward-bias voltage. Physically, this means the external voltage is connected such that Figure 2.14. A schematic linear plol of the current of a typical silicon diode as a function of its On a linear plot, the reverse current is too low to be observable. voltage. 42 2 Basic Device Physics 2.2 p-n Junctions 43 2.2.2.3 ignored in our depletion approximation, we can write the charge per unit area in the p­ side depletion region as Qip-side)= - qNaxp(Vapp) , (2.82) where we have indicated that the p-side depletion-layer width, xpo is a function of Vapp. Notice that Qd for the p-side is negative because ionized acceptors have a charge--q. LOS 1.00 '1~ 0.95 'd - _. 0.90 .1 I ,,- V ,/ i The depletion-layer capacitance pet unit area is Cd == dQ = dQdCp-side) = Ssi dVapp dVapp (2.83) That is, the depletion-layer capacitance of a diode is equivalent to a parallel-plate capacitor ofseparation Wd and dielectric constant lOs;. Physically, this is due to the fact that only the majority carriers at the edges ofthe depletion layer, not the space charge ."S­ 0.85 .ll: ~ 0.80 ,/ V ;--- 0.75 0.70 IE+14 ,,/' .. !! lE+1S lE+16 IE+17 Doping concentration (cm-3) 113+18 within the depletion region, respond to changes in the applied voltage. Figure 2.15. Built-in potential for a one-sided p-n junction versus the doping concentration of the lightly • Extending the depletion approximation to include injected currentflows in the space­ doped side. charge region. When a diode is forward biased, the electrons flowing from the n-side to the p-side and the holes flowing from the p-side to the n-side add to the space charge in the transition region of the diode. To be accurate, we cannot assume the transition region to be depleted of mobile charge carriers. However, as long as the density of it is a good approximation to assume its Fermi level to be at the conduction-band edge. Therefore, the built-in potential for an n+-p diode, from Eqs. (2.72) and (2.73), is given by mobile carriers is small compared to the densities of ionized donors and acceptors, we have a well-defined space-charge region. (When the density of mobile carriers is E E kTin + q'llbi = fn - in (~~) comparable to or larger than the densities ofionized donors or acceptors, the boundaries ofthe space-charge region are no longer well defined. This situation will be discussed ~ -Em+kTln(:;) (2.84) further in Section 6.3.3.2 in the context ofbase widening at high injection in a bipolar transistor.) For a well-defined space-charge layer of width Wd, the associated capaci­ tance per unit area is the same as a parallel-plate capacitor, namely, Eq. (2.83). In this ~ 2 +kTln(:;), case, Wd can be obtained from integrating Poisson's equation, i.e., (2.44). An example of how mobile charge carriers flowing through a space-charge region affect the space-charge-region thickness is given in Section 6.3.3.1 in the context of base widening at low injection in a bipolar transistor. where we have made a further approximation that the intrinsic Fermi level is located half way between the conduction- and valence-band edges, Ern and Evn, on the n-side. [See Eq. (2.12) and the discussion that follows.] Figure 2.15 is a plot of'llbi, as approxi­ mated by Eq. (2.84), as a function of the doping concentration ofthe lightly doped side. The depletion-layer width, from Eqs. (2.80) and (2.8\), is One-Sided Junctions In many applications, such as the source or drain junction ofa MOSFET or the ernitter-base diode of a bipolar transistor, one side of the p-n diode is degenerately doped while the other side is lightly to moderately doped. In this case, practically all the voltage drop and the .depletion layer occur across the lightly doped side of the diode. That this is the case can be inferred readily from Eq. (2.78), which implies thatXn = NaWd/(Na + Nd) and xp = N"Wd/(Na + Nd). The characteristics ofa one-sided p-n diode are therefore deter­ mined primarily by the properties ofthe lightly doped side alone. In this sub-subsection, we shall derive the equations for an n+-p diode where the characteristics are determined by the p-side. The results can be extended straightforwardly to a p+-n diode. As discussed in Section 2.1.2, for a lightly to moderately doped p-type silicon, the Fermi level is given by Eq. (2.25), and for a heavily or degenerately doped n-type silicon, Wd= 2Ssi (lfIbi - Vapp ) qNa (2.85) where Vapp > 0 if the diode is forward biased and Vapp < 0 if the diode is reverse biased. The depletion-layer capacitance per unit area is given by Eq. (2.83). Figure 2.16 is a plot of the depletion-layer width and capacitance as a function of doping concentration for Vapp O. Again, in Eg. (2.85) should be replaced by V'app whenever the IR drops in the guasineutral regions are not negligible. 2.2.2.4 Thin-i-Layer p-i-n Diodes Many modem VLSI devices operate at very high electric fields within the depletion regions of some of their p-n diodes. In fact, the junction fields are often so high that 44 2 Basic Device Physics I 1l l~ In I III gIl g 0.1 .~ ~ om lE+14 IE+1S 1E+16 IE+t7 Doping concentration (cm-3) 10 ~ -s j :u >. ~'" 0.1 .g .g£­ o om IE+lS Figure 2.16. Depletion-layer width and depletion-layer capacitane, at zero bias, as a function of doping concentration of the lightly doped side of a one-sided p-n junction. p-region Depletion region Pn" (x) n-region _I W \"!:II ... x i-layer Figure 2.17. Charge distribution in a p-i-n diode. detrimental high-field effects, such as avalanche multiplication and hot-carrier effects, limit the attainable device and circuit performance. To overcome the constraints imposed by high fields in a diode, device designers often introduce a thin but lightly doped region between the n- and the p-sides. In practice, this can be accomplished by sandwiching a lightly doped layer during epitaxial growth ofthe doped layers, or by grading the doping concentrations at or near the junction by ion implantation and/or diffusion. Analyses of such a diode structure become very simple if the lightly doped region is assumed to be intrinsic or undoped, i.e., if the lightly doped region is assumed to be an i-layer. This actually is not a bad approximation as long as the net charge concentration in the i-layer is at least several times smaller than the space-charge concentration on either side ofthe p---n junction, so that the contribution by the i-layer charge to the junction electric field is negligible. Figure 2.17 shows the charge distribution in such a p---i-n diode. The corres­ ponding Poisson equation is - qNd for d~:-./--": :~'\_'"~_:L::7:::<:::1_~>'::p:"'=-_--_-___-'__.__..... Efc , ' xn ! ,---­ -xp Ev o x p·type n-type Figure 2.18. Schematics showing the variations of the quasi-Fenni potentials, 0) with negligible lR drops in the quasineutral regions. (c) A reverse­ biased diode (Vapp < 0). In the case of reverse bias, the drops in 1' across the space-charge region increase with iVappl. and rPp are essentially constant across the space-charge region, as illustrated schema­ tically in Fig. 2.18(b). • Reverse-biased diode. In the case of reverse bias, the results in Appendix 4 show that the drops in rPn and rPp across the space-charge layer are small compared to kT/q only for small reverse bias (Iv"pplless than about 4kT/q). For larger reverse bias, the drops in rP" and rPp across the space-charge layer increase approximately linearly with increase in reverse bias. Therefore, rP. and rPp are also relatively constant across the space-charge region for the case of small reverse bias, as illustrated schematically in 2.18(c). 2.2.3.3 Relationship Between MinOrity-Carrier Density and Applied Voltage The relationship between the voltage across the space-charge region, Vlapp, and the majority-carrier quasi-Fermi potentials at the space-charge-region boundaries, and rPn(xn) is 50 2 Basic Device Physics v.pp == Vapp IR(p-side) - IR(n-sidel == Vapp [1>p(p-contact) -1>p( -xp)] 1>p(-xp) - [1>n(Xn) 1>n(n-contact)] (2.106) In Eq. (2.106), we have used the results discussed in Sections 2.1.4.5 and 2.1.4.6 which state that = (Ejn(n-contact) EiP(p-contact)l/q 1>p(p-contact) -1>n(n-contact). For forward bias and small reverse bias, the drops in the quasi-Fenni potentials across the space-charge region are small compared to kTlq, i.e., 1>p(-xp) ~ 1>p(Xn) and 4>n (-xp) ~ 1>n(xn). Therefore, Eqs. (2.102) and (2.106) can be combined,forforward bias and small reverse bias, to give the electron density on the p-side at the space-charge-Iayer edge as np(-xp) - Pp n2 (--x'-p) e xp{q[4>p(-xp) - 4>n(-xplJlkT} ~ n2 - (-'-) exp{q[4>p( -xp) - 4>n(xnl]lkT} Pp -xp = -Pp(n--2x 'p-) exp(qV.pplkT) npO(-Pxpp()p_pxop)( -xp) exp(Tq7yfapp /kT) ~ npO( -xp) exp(qv.pp/kT), (2.107) where we have used the low-injection approximation to write Pp ~ PpO. (The case ofhigh injection will be discussed later.) Similarly, we have Pn(Xn) ~ PnO(xn) exp(qv.pp/kT) forward bias and small reverse bias (2.108) is the hole density at the space-charge-layer edge on the n-side. Equations (2.107) and (2.108) are the most important boundary conditions governing a )rn diode. They relate the minority-carrier concentrations at the space-charge-region boundaries of the quasi­ neutral regions to their thermal-equilibrium values and to the voltage across the space­ charge region. For a forward-biased diode (V~pp > 0), we have an excess of minority carriers at the boundaries of the quasineutral regions. For a reverse-biased diode (V~pp <0), we have a depletion of minority carriers at the boundaries of the quasineutral regions. Equations (2.107) and (2.108) are often referred to as the Shockley diode equations (Shockley, 1950). The fact that Eqs. (2.107) and (2.108) are valid only for small reverse bias is often overlooked in the literature. It is shown in Appendix 4 that for reverse biases more negative than about -4kTlq, Eqs. (2.107) and (2.108) overestimate the degree of minority-carrier depletion at the quasineutral-region boundaries. However, it is also shown in Appendix 4 that once the. depletion of minority carriers at the boundaries has reached 90%, corresponding to IVappl ~ 3 kTlq, further depletion of minority carriers has little effect on the diode current. In other words, using Eqs. (2.107) and (2.108) for > 3kTlq does not lead to any significant error in the calculated reverse-biased diode 2.2 p-n Junctions 51 currents. Therefore, Eqs. (2.107) and (2.10&) can be used to describe the transport properties in a reverse-biased diode.as if they are valid for arbitrary reverse biases. The distinction between V'ap; and Vapp is important whenever there is significant parasitic series resistance in a forward-biased diode, for instance, in the forward-biased emitter-base diode of a bipolar transistor. In most cases, the parasitic resistance can be modeled as a lump resistor in series with the diode, allowing us to quantify the difference between V'app and Vapp readily. For simplicity in writing the equations, we shall not make the distinction between Vapp and Vlapp when we use Eqs. (2.107) and (2.108) to derive the equations for the current-voltage characteristics. The distinction between Vapp and V'app will be pointed out wherever it is important to do so. 2.2.3.4 Diode Equation at High Minority-Carrier Injection As stated in the derivation of Eqs. (2.107) and (2.108), these equations are valid at low injection. If the low-injection condition is not met, these equations are not valid and (2.102) should be used instead. At sufficiently large forward biases, the injected minority-carrier concentration, particularly on the lightly doped side of the diode, can be so large that, in order to maintain quasineutrality, the electron and hole concentrations become approximately equaL In this case, Eq. (2.1 02) gives n P Rj ~ ni exp (q V;pp/2kT). At such high levels of minority-carrier injection, the concept of a well-defined transition region is no longer valid, and the quasi-Fermi potentials do not have simple behavior in any region of the diode (Gummel, 1967). The effect of high minority-carrier injection on the measured current-voltage characteristics of a diode will be discussed further in Section 2.2.4.10. An example of how the "boundary" of a p-n junction can be "relocated" at high minority-carrier injection can be found in Section 6.3.3 in connection with the discussion of base-widening effects in a bipolar transistor. 2.2.4 Current-Voltage Characteristics As discussed in Section 2.2.1, at thermal equilibrium, the drift component ofthe current caused by the electric field in the space-charge region is exactly balanced out by the diffusion component of the current caused by the electron and hole concentration gradients across the junction, resulting in zero current flow in the diode. When an external voltage is applied, this current component balance is upset, and current will flow in the diode. If carriers are generated by light or some other means, thermal equilibrium is disturbed, and current can also flow in the diode. Here only the current flow in a diode as a result of an externally applied voltage is discussed. We first consider the current-voltage characteristics of an ideal diode govemed by the Shockley diode equations (2.107) and (2.1 08). The space-charge-region current will be added later in Section 2.2.4.10 when we consider the deviation of a practical diode from ideal behavior. Consider a forward-biased p--n diode. Electrons are injected from the n-side into the and holes are injected from the p-side .into the n-side. Since space-charge-region current is ignored, the hole current leaving the p-side is the same as the hole current 52 2 Basic Device Physics entering the n-side. Similarly, the eleGtron current leaving the n-side is equal to the electron current entering the p-side. To determine the total current flowing in the diode, all we need to do is to determine the hole current entering the n-side and the electron current entering the p-side. The starting point for describing the current-voltage characteristics is the continuity equations. For electrons, it is given by Eq. (2.68) which is repeated here: aant Rn + (2.109) where Rn and Gn are the electron recombination and generation rates, respectively. (A detailed discussion of generation and recombination processes is given in Appendix 5.) Equation (2.109) can be rewritten as q on 10Jn n - no ot = ax 'II (2.110) where n-no 'n Rn - Gn 11) is the electron lifetime, and no is the electron concentration at thermal equilibrium. Substituting Eq. (2.54) for I n into Eq. (2.110) gives I on -;:;- = nfJ-n a'l! + fJ-n ' an '(J" + Dn i:i2 n - no (2.1 ut uX uX 'n 2.2.4.1 Diodes with Uniformly Doped Regions Let us consider electrons in the p-region of a p-n diode. For simplicity, we assume the p-region to be uniformly doped so that at low electron injection currents the hole density is uniform in the p-region. As will be shown in Section 6.1.2, the electric field is zero for a region where the majority-carrier concentration is uniform. Thus, for the a lax p-region under discussion, 'I! 0 and $' = O. For electrons in this p-region, Eq. (2.112) reduces to rf2np = Dn ax2 'n (2.ll3) At steady state, Eq. (2,113) becomes -aon=tI' O=Dn which can be rewritten as -np --Tn n-pO (2.114) cPnp np - npO = 0, dx2 L"!, 2.2 p-n Junctions 53 where LII =='VTnDn = JkT~n!n (2.1 is the electron diffosion length in the p-region. It should be noted that the quantities in Eq. (2.116) are all for minority carriers, not majority carriers. In deriving the equations for minority-carrier transport, we can focus on minority electrons or minority holes. As we shall show later, the current-voltage characteristics of a one-sided diode are determined primarily by the transport of minority carriers in the lightly doped side. Forward-biased diodes are usually found in the operation of bipolar transistors. High-speed bipolar transistors are n-p-n type, instead of p-n-p type. That is, most commonly encountered one-sided forward-biased diodes are of the n+-p type, instead of -n type. Therefore, we choose to focus on minority electrons in deriving the transport equations. Also, we like to make some rearrangement to simplify the algebra in deriving the current equations. Earlier in this chapter, the physical junction of a p-n diode is assumed to be located atx=O with the p-silicon to the left side ofthe junction and the p-side depletion-layer edge located at x = -xp• The n-silicon is located to the right side of the junction. The excess electrons in the p-region of the diode are injected from the n-side. These excess electrons will then move further into the p-region, contributing to electron current and becoming recombined along the way. That is, the p-side space­ charge-region boundary is really the starting location for considering the distribution and transport of the excess electrons in the p-region. For considering the transport ofelectrons in the p-region, the algebra is simpler if we flip the p-n diode in Fig. 2.18 such that the n-region is on the left and the p-region is on the right, resulting in electrons flowing in the x-direction. The algebra can be further simplified if we shift the origin such that the quasineutral region of the p-side starts at x = 0 and ends at x = Wp- Note that in this arrangement, the electron current in the p-region has a negative sign (negative charges flowing in the x-direction). This is illustrated in Fig. 2.19 for an n+-p diode. In this rearranged coordinate system, the electron density atx = 0 is given by the Shockley diode equation, i.e., Eq. (2.107), while the electron density at:x = Wp is equal to npO, ie., np(O) npO exp(q VapplkT) (2.117) Space-c,harg,e region ~,, :~ Emitter: Base ._~__ J oI •x t'1lure 2.19. Schematic showing the coordinates u.~ed to develop the transport equations for a p-n diode. An n+-p diode is assumed with the quasineutral p-region starting at x = 0 and ending at x 54 2 Basic Device Physics and np(Wp) npo· (2.118) be accurate, Vapp should be replaced by V'app in Eq. (2.l17). For simplicity in writmg the equations, we are not making the distinction between Vapp and V'app unless there is confusion.] Solving Eq. (2.115) subject to these boundary conditions gives 1] qVapp) _ sinh[(Wp x)/Lnl. npO = npO [exp ( kT sinh(Wp/ Ln) 19) Since there is no electric field in the quasineutral p-region, there is no electron drift­ current component, only an electron diffusion-current component. The electron current density entering the p-region is (~) 1.(0) = qDn .<=0 = qDnnpO[exp(q VaEE/kT) 1] Ln tanh(Wp / Ln) qDnnHexp(qVapp/kT) -1] ppOLn tanh( Wp/ Ln) (2.120) where in writing the last equation we have used the fact that npOppO = nj. Equations (2.119) and (2.120) are valid for a p-region ofarbitrary width Wp. Note thatJn is negative in sign because electrons have a charge --q and are flowing in the x-direction. The hole density in the n-region and the hole current density entering the n-side have the same forms as Eq. (2.119) and Eq. (2.120), respectively, and can be derived in an analogous manner (cf. Exercise 2.16). The total currentflowing through a p-n diode is the sum ofthe electron cu"ent on the p-side and the hole current on the n-side. That is, the diode current density is qDnnT[exp(qVapp/kT) - IJ qDpnnexp(qVapp/kT) 1] PpOLn tanh (Wp / Ln) - nnOLp tanh( Wn / Lp) I] [NaTn qLnnr tanh(Wp/Ln) + N,rrp qLpnr ] tanh(Wn/Lp) [exp(qVapp ) kT ' (2.121) where we have assumed that all the dopants are ionized so that PpO = Na and nnO = Nd. diode current represented by Eq. (2.121) is due to the diffusion of minority carriers in the quasineutral regions. It does not include the generation-recombination current in the space-charge region, which will be discussed in Section 2.2.4.10. The total diode current is the sum ofthe diffusion current and the generation-recombination current.] The negative sign in Eq. (2.121) is due to the fact that we placed thep-region to the right of the n-region, causing electrons to flow in the +x direction and holes to flow in the -x direction. The negative sign will not be there if we place the p-region to the left of the Ignoring the (2.121) is often referred to as the Shockley diode current equation, or simply the Shockley diode equation. It is applicable to both forward bias (v"pp > 0) and reverse bias (v;,pp < 0). Figure 2.20 is a semi-log plot of the diode current 2.2 p-n Junctions 55 lE-1 ~ '''-J E - - Forward bias. -----. Reverse bias R E ~ lE-5 S .~ c "." 1E-7 C ~ B ~" 1E-9 IE-II Figure 2.20. lE-13_1 --0.5 0 0.5 Applied voltage (V) The currentdensityofan ideal diode as given by Eq. (2.121). We assumeNa = Nd= 1017 cm-3, and use the corresponding values for Land, in Fig. 2.24. WIL is assumed to be large so that tanh (WiL) = I. density given by (2.121) as a function applied voltage. It represents the I-V characteristics of an ideal diode. It is of interest to contrast Fig. 2.20 with Fig. 2.14. On a linear plot (Fig. 2.14), the rectifYing characteristics of the diode current are evident, with a tum-on voltage ofabout 0.8 V. On a semi-log plot (Fig. 2.20), only the exponential dependence of the forward-bias current on voltage and a low-level reverse-bias back­ ground current are obvious. Deviations of a practical diode from an ideal case are usually observable in a semi-log plot, but not in a linear plot, and will be discussed later in Section 2.2.4.10. At sufficiently large reverse bias, the diode will break down (not shown in Fig. 2.20). High-field effects, including avalanche breakdown of a p--n diode, will be covered in Section 2.5. 2.2.4.2 Emitter and Base of a Diode Equation (2.121) shows that the minority-carrier current is inversely proportional to the doping concentration. Thus, in a one-sided diode, the minority-carrier current in the lightly doped side is much larger than that in the heavily doped side. The diode current is dominated by the flow of minority carriers in the lightly doped side of the diode, while minority-carrier current in the heavily doped side usually can be neglected in comparison. (The effect ofheavy doping can increase the minority-current flowing in the heavily doped region substantially. Heavy-doping effect is particularly important in bipolar devices, and will be covered in Chapter 6. The effect of heavy doping on the magnitudes of the currents in a diode will be discussed as exercises.) The lightly doped side is often referred to as the base of the diode. The heavily doped side is often referred 56 2 Basic Device Physics 2.2 p-n Junctions 57 2.2.4.3 2.2.4.4 to as the emitter of the diode, since the minority carriers entering the base are emitted from it. In discussing the current-voltage characteristics of a diode, often only the minority­ carrier current flow in the base is considered, since the minority-carrier current flow in the emitter is small in comparison. (However, if the width of an emitter is not larger than its minority-carrier diffusion length, the minority-carrier current flow in the emitter may not be negligible. Diodes with such emitters will be discussed further in Section 2.2.4.9.) As a result, unless stated explicitly, the region of the diode under discussion is assumed to be the base. That is, only the term in Eq. (2.121) corresponding to the base is kept. Whenever the emitter term is not negligible, both terms in Eq. (2.121) should be kept. In the following subsections, we examine in detail the current-voltage characteristics of one-sided n+-p diodes. The equations derived can be modified readily to describe p+-n diodes by changing the parameters for electrons in p-silicon to parameters for holes in n-silicon. is the electron diffusion component of the leakage current in a reverse-biased diode. It is also referred to as the. electron.satur.ation current of a diode. The hole saturation current can be inferred from Eq. (2.121). The total diffusion leakage current in a diode is the sum of the electron and hole saturation currents. Notice that the diffusion leakage current is independent ofthe applied voltage. 2.2.4.5 Wide-Base n+-p Diodes A diode is wide-base if its base width is large compared to the minority-carrier diffusion » length in the base. For an n+-p diode, this means Wp / Ln 1. For a forward-biased wide­ base diode, Eqs. (2.122) and (2.123) reduce to np(x) - npo = npfJ exp(q Vapp/kT) exp(-xlLn) (forward, wide base) (2.126) and JnCO) qpDpfnJnL2~exp (qkVaTI'P) (forward,wl.debase). (2.127) Forward-Biased n+-p Diodes We first consider the case where the -p diode is moderately forward biased, i.e., Vapp > 0, and qVapp I kT» 1. In this case, Eqs. (2.119) and (2.120) become 5inh[( Wp - x)/ Lnl . np(x) - npfJ = npo exp(q Vapp/kT) sinh ( W / Ln) (forward bIased) p (2.122) Thus, for a forward-biased wide-base diode, the excess minority-carrier concentration decreases exponentially with distance from the depletion-region boundary, and the minority-carrier current is independent of the base width. For a reverse-biased wide-base diode, Eqs. (2.124) and (2.125) reduce to np(x) npfJ -npfJexp(-x/Ln ) (reverse, wide base) (2.128) and and JI1 (O) = qDnni exp(qVapp/kT) PpfJLn tanh( Wp / Ln) (forward biased). 123) = qDnn; (reverse, wide base). ppOLn (2.129) That is, the minority-carrier electrons in the base within a diffusion length of the That is, both the excess minority.carrier concentration and the minority-carrier cur­ depletion-region boundary diffuse towards the depletion region, with a saturation current rent increase exponentially with the applied voltage (see Fig. 2.20). density given by (2.129) which is independent of the base width. Reverse-Biased n+-p Diodes » Next we consider the case where the n+-p diode is reverse-biased, i.e., Vapp < 0, and kT. In this case, Eqs. (2.119) and (2.120) become sinh[( Wp x)/ Lnl (reverse biased) npo = -npfJ sinh(WI'/Ln) (2.124) and In(O) = -_.--=-c:-~~ (reverse biased). 125) Notice that np(x) - nl'o is negative, andJn is positive. The reverse bias causes a gradual depletion of electrons in the p-region near the depletion-region boundary, and this electron concentration gradient causes an electron current to flow from the quasineutral p-region towards the depletion region (in -x direction according to our coordinates). This 2.2.4.6 Narrow-Base n+-p Diodes A diode is called narrow-base if its base width is small compared to the minority-carrier « diffusion length in the base. In this case, this means Wp/ Ln L For a forward-biased narrow-base diode, Eqs. (2.122) and (2.123) reduce to npo npfJ exp ( kqVTapp) ( I -~Wp) (forward, narrow base) (2.130) and J (0) --qD-nenTxp (q-V-ap.p) (forward, narrow base). 11 PpoWp kT (2.131) For a reverse"biased narrow-base diode, the corresponding equations are -npo(l - ;J np(x) npD (reverse, narrow base) (2.132) 58 2 Basic Device Pltysics and In(O) = -qD-nn'2 (reverse, narrow base). ppoWp (2.133) For both forward and reverse biases, the minority-carrier current density in a narrow-base n+-p diode increases as I/Wp. That is, for a narrow-base diode, the base current increases rapidly as the base width is reduced. 2.2.4.7 Spatial Distribution of Excess Minority Carriers It can be seen from Eqs. (2.122) and (2.124) that both a forward-biased diode and a reverse-biased diode have the same sinh [(W - x)/L] spatial dependence for the distribu­ tion ofexcess minority carriers (actually depletion ofminority carriers in a reverse-biased diode). Figure 2.21 is a plot of the relative magnitude of the excess minority-carrier density as a function ofxIL with WIL as a parameter. The exp(-xlL) distribution is for the case of WIL = 00. It shows that a diode behaves like a wide-base diode for WIL> 2. For WIL < 2, the diode behavior depends strongly on W For WIL < 1, the distribution can be approximated by the I - xIW dependence of a narrow-base diode. 2.2.4.8 Dependence of Minority-Carrier Current on Base Width Figure 2.22 is a plot of the minority-carrier current density given by Eq. (2.120), normalized to its wide-base value. It shows that when WIL < 1, the minority-carrier current increases very reapidly as the diode base width decreases. 2.2.4.9 Shallow-Junction or Shallow-Emitter Diodes Thus far, we have assumed the minority-carrier current in the emitter to be negligible compared to that in the base. A diode has a shallow emitter if the minority-carrier diffusion length in the emitter is comparable to or smaller than the width of the emitter 6 i., ~ ] -Ea 0.2 *­ 0 0 0.5 1.0 1.5 2.0 2.5 3 x/L Figure 2.21. Relative magnitude of the excess minority-carrier concentration in the base ofa diode as a mnction of distance from the base depletion-layer edge, with WIL as a parameter, where L is the minority­ carrier diffusion length in the base and Wis the base-region width. The case of WIL 00 is given by exp(-xIL). 2.2 p-n Junctions 59 12 10 .~ "~ 8 't:I C ~6 "0 .~ 4 0 ~ 2 Figure 2.22. 0 0 0.5 1.0 1.5 2 W/L Relative maganitude of the minority-carrier current density in the base region of a diode as a function of WIL, normalized to the current at WIL = 00. Here L is the minority-carrier diffusion length in the base, and Wis the width of the base region. region. The width of the emitter region of a p-n diode is also referred to as the junction depth. Therefore, a shallow-emitter diode is also a p-n junction having an electrically shallow junction. Figure 2.22 applies to the emitter region as well. Thus, we see from Fig. 2.22 that when WIL < I in the emitter, the minority-carrier current in the emitter increases very rapidly as the emitter depth decreases. As can be inferred from Fig. 2.24(c), to be developed later in Section 2.2.4.12, the minority-carrier diffusion length is about 0.3 11m for a doping concentration of I x IOZo em- 3, and much larger for lower doping concentrations. This length is larger than the emitter depth ofa typical one-sided p-n diode in a modem VLSI device (e.g., the emitter of a bipolar transistor and the source and/or drain of a CMOS device). That is, typicalp-n diodes in modern VLSI devices should be treated as shallow-juncnon diodes. There are effective means for reducing the minority-carrier current in a shallow-emitter diode. For instance, a shallow emitter can be contacted using a doped polysilicon layer instead of a metal or metal silicide layer. The physics of minority-carrier transport in a shallow emitter will be covered in detail in Chapters 6 and 7 in the context of modem bipolar transistors. 2.2.4.10 Space-Charge-Region Current and Ideality Factor of a Diode Thus far, we have neglected the current originating from the generation and recombina­ tion ofelectrons and holes within the space"charge region. In practical silicon diodes, the space-charge region current can be larger than the Shockley diode current at reverse bias and at low forward bias. It is shown in Appendix 5 that the space-charge-region current can be written in the form Isc(Vapp) = ISC1l[exp(qVapp/2kT) IJ, 134) with Isco = AdiodeqniWd 'n +'p (2.135) 60 2 Basic Device Physics where Wd is the width of the space-charge region, Adiode is the cross-sectional area of the diode, and Ln and Lp are the electron and hole lifetimes, respectively. Equation (2.134) is often referred to as the Sah-Noyce-Shockley diode equation (Sah et al., 1957; Sah, From Eq. (2.121), we can write the Shockley diode current in the form IdioM = Io[exp(qVapp/kT) 1], with 10 = Adiodeqni2 ~ poL. Dn tanh(Wp/Ln) + npOLp Dp J. tanh(Wn/Lp) (2.l36) (2.137) As discussed in Section 2.2.3.4, Eq. (2.136) is valid only at low injection levels. For an n+-p diode, high injection occurs when np approaches No where Na is the acceptor concentration of the p-side. At high injection, IR drops in the quasineutral regions can be significant. Also, Idiode changes to an exp(q V~pp 12kT) dependence (see the discussion in Section 2.2.3.4). The onset of high injection can be pushed to higher voltage by increasing Na. The current measured at the diode terminals is llOtat = Idiode + Isc· (2.138) Figure 2.23 is a schematic semi-log plot of a diode current as a function of its forward­ bias terminal voltage, with series resistances neglected. A semi-log current-voltage plot exp(qVapp/2k1) IE+ll '"c- ">. ~ :a ~ i:i ~ IE+5 u" exp(qVapplkTJ Isc '''iode floral IE+2 Resistance effect ignored IE_1LU~LU~LU~LU~~~~WW~~~~~LLU 0.7 0.8 0.9 Applied voltage (V) Figure 2.23. A schematic Gummel plot of the forward-bias current of a p-n diode. Series resistance effects are ignored. [diude is the Shockley diode current. lsc is the space-charge-region current. 2.2 p-n Junctions 61 for a diode or a bipolar transistor is called a Gummel plot. The slope in a Gummel plot is often used to infer the ideality oLa. diode. That is, the forward diode current is often expressed in the form Itotat(forward) ~ exp(qVapp/mkT), (2.139) where m is called the ideality factor. Note that it is the diode terminal voltage VapP' not V' app across the space-charge region that is in Eq. (2.139). The difference between Vapp and V'app is contained in the ideality factor. When m is unity, the current is considered "ideal." Figure 2.23 suggests that a forward diode current is ideal except at very small and very large forward biases. The nonideality at small forward bias is caused by the space-charge-region current. Space-charge-region current leads to m - 2 [see Eq. (2.134)1. The nonideality with m-2 at very large forward bias is due to injection effect in the Shockley diode current (see the discussion in Section 2.2.3.4). At intermediate voltages, we have 1 < m < 2. Finite resistivity of the p- and n-regions results in voltage drops between the ohmic contacts and the junction. Finite resistivity effect is important only at very large forward biases. On a Gummel plot, finite resistivity effect can lead to m being very large. In general, when 1 < m < 2 at large forward bias, it is not easy to clearly tell ifthe nonideality is caused by series resistance or by high injection. It may be a combination of both. However, when m > 2, we know that the series resistance effect dominates because the injection effect by itself has an ideality factor of no larger than 2. Series resistance effects can be reduced by increasing the diode doping concentrations, narticularlv the doping concentration of the base side ofthe diode. As discussed earlier, concentration also delays the onset of high injection. Practical silicon can be such that it appears quite ideal for forward biases of up higher. Degradation in ideality factor is usually observable only at low forward biases and only in diodes having significant amounts of generation­ recombination centers in the space-charge region. (An example of how the ideality factor changes with forward bias can be seen in the base current of a modem bipolar transistor shown in 6.13.) 2.2.4.11 Temperature Dependence and Magnitude of Diode leakage Currents For a reverse-biased diode, the total leakage current is the sum ofthe space-charge-region saturation current Isco and the diffusion saturation current 10 given by Eqs. (2.l35) nt and (2.l37), respectively. The temperature dependence of 10 is dominated by the tem­ perature dependence of the factor, which, as shown in Eq. (2.13), is proportional to exp (- Eg / kT) where Eg is the bandgap energy. The space-charge-region leakage current Isco, being proportional to nj, has a temperature dependence ofexp( -Eg /2kT). In other words, the diffusion leakage current has an activation energy of about 1.1 eV while the generation-recombination leakage current has an activation energy of about 0.5 eV. This difference in activation energy can be used to distinguish the sources of the observed leakage current (Grove and Fitzgerald, 1966). [The diffusion leakage current is indepen­ dent of reverse-bias voltage. The space-charge-region current is proportional to the space-charge-Iayer width which increases with revt 2 x 1018cm-3) doping concentrations and about 30% lower mobilities at low « I x IOI8cm '3) doping concentrations (Klaassen et al., 1992). 22 p-n Junctions 63 800 1 ~ 1600 .. J.lrfl "/1111 ~ ~4001 .~ 1=1--LHIIII I- 1111111 "? ·igc::' 200 ~ 1~+17 lE+18 lE+19 Doping concentration (cm-3) (a) lE-4 ~ 18-5 .§ J! lE-6 "."~ IB-7 "? ·€ c lE-1l .~ ~ lB-9 300FHHi-· 100 ~ } .2 @ is IE+1S Doping concentration (cm-3) (b) Doping concentration (cm-3) (c) Figure 2.24. Minority-carrier (a) mobilities, (b) lifetimes, and (c) diffusion lengths as a function of doping concentration, calculated using the empirical equations (2.140) to (2.143). 64 2 Basic Device Physics 2.2.5 2.2.5.1 Time-Dependent and Switching Characteristics As discussed in Section 2.2.2, there is a capacitance associated with the depletion layer of a diode. As the diode is switched from off (zero-biased or reverse-biased) to on (forward­ biased), it takes some time before the diode is turned on and reaches the steady state. This time is associated with charging up the depletion-layer capacitor and filling up the p- and n-regions with excess minority carriers. Similarly, when a diode is switched from the on state to the off state, it takes some time before the diode is turned off. This time is associated with discharging the depletion-layer capacitor and discharging the excess minority carriers stored in the p- and n-regions. The majority-carrier response time, or dielectric relaxation time, is negligibly short, on the order of 10-12 s, as shown in Section 2.1.4.8. Consider the time needed to charge and discharge the depletion-layer capacitor. From Fig. 2.16, the depletion-layer capacitance Cd is typically on the order of! iF111m2• To turn a diode from offto on, and from on to off, the voltage swing Vis typically about 1 V. If the diode is connected so that it carries a current density J of 1 mA/!1ffi2, then the time associated with charging and discharging the deplection-layer capacitor is on the order of CdVIJ, which is on the order of 10-12 s. Of course, this time changes in proportion to the current density J. However, as we shall show below, the time needed to charge and discharge the depletion-layer capacitor is usually very short compared' with the time associated with charging and discharging the p- and n-regions of their minority carriers. Excess Minority Carriers in the Base and Base Charging Time Consider an n+-p diode with a p-region base width W. When a forward bias is applied to it, minority-carrier electrons are injected into the base. As discussed in Section 2.2.4, for a wide-base diode, the minority-carrier density decreases exponentially with increasing distance, and practically all the minority carriers recombine before they reach the minority-carrier sink at x W. For a narrow-base diode, on the other hand, practically all the minority carriers can travel across the base region without recombining. The total excess minority-carrier charge (electrons) per unit area in the p-type base region is QB r-q (np npO)dx. (2.144) For a wide-base diode, substituting Eqs. (2.126) and (2.127) into Eq. (2.144), we obtain Qs (wide base) npO)x=o LII = 0)1:11, where we have used 1:" L~/Dn from Eq. (2.1 For a narrow-base diode, substituting Eqs. (2.130) and (2.131) into (2.144), we obtain Qa (narrow base) -q(np npO)x=o (~ 1n (x = (2.146) 2.2 p-n Junctions 65 where the base-transit time tB is defined 'Q~ Tnarrow base) lB 1n (x 0) W2 (2.147) As will be shown below, tB is also equal to the average time for the minority carriers to traverse the narrow base region. In a wide-base diode, it takes a time equal to the minority-carrier lifetime to fill the base with minority carriers. In a narrow-base diode, it takes a time equal to the base-transit time to fill the base with minority carriers. It should be noted that the charging current, In(x''' 0), is different for wide-base and narrow-base diodes. The dependence ofIn(x '" 0) on base width is shown in Fig. 2.22. 2.2.5.2 Average Time for Traversing a Narrow Base From Eq. (2.130), the excess electron concep.tration at any base region is np - npo = (np (I - ~). x in the narrow p-type (2.148) Let vex) be the apparent velocity of these excess carriers at point x. The current density due to those excess carriers at x is then In(x) = -qv(x)(np - = -qv(x)(np - npO)x=o(l ~). (2.149) The electron current density at x= 0 is given by Eq. (2.131), i.e., I n (x 0) = (np (2.150) Assuming negligible recombination in the narrow base region, then current continuity requires In(x) to be independent ofx, i.e., Dn vex) W-x' (2.151) The average time for traversing the base is thus given by {w dx tavg Jo w2 2Dn ' (2.152) Comparison of Eqs. (2.147) and (2.152) shows that the base-transit time is equal to the average time for the minority carriers to traverse the narrow base. It is instructive to esimate the magnitude of tB' Modem n-p-n bipolar. transistors typically have base widths of about 0.1 11m, and a peak base doping concentration of about 2 x 1018 cm-3 (Nakamura and Nishizawa, 1995). The corresponding minority electron mobility, from Fig. 2.24, is about 300 cm2N-s. The base-transit time is therefore less than 1xl 0- 11 s, which is extremely short compared with the corresponding 66 2 Basic Device Physics (al VF R VR R .r­ o t (b) ----i(t-) j fF _fRIO i(t) 1<0 i(l) 1>0 •x Is ~- (c) (np-npIJ) ~~~~~....... x o Figure 2.25. Schematics showing the switching ofan n+-p diode from forward bias to reverse bias: (a) the circuit schematics, (b) the diode current as a function of time, and (c) the excess-electron distribution in the base for different times. minority-carrier lifetime on the order of 1x 10-7s. Recombination is negligible in the base layers o/modern bipolar transistors. 2.2.5.3 Discharge Time of a Forward-Biased Diode Consider an n+'-p diode in a circuit configuration shown in Fig. 2.25(a). For simplicity, let us assume the external voltage, VF or VR, driving the circuit to be large compared to the internal junction voltage, i.e., the voltage immediately across the diode depletion layer, which is typically less than 1.0 V. At t < 0, there is a forward current of lp::::: VF I R as illustrated in Fig. 2.25(b), and an excess electron distribution in the base region as illustrated in Fig. 2.25(c). At time t 0, the external bias is switched to a reverse voltage of VR . The excess electrons in the base start to diffuse back towards the depletion region ofthe diode. Those. electrons at the edge of the depletion region are swept away by the electric field in the depletion region towards the n+ emitter at a saturated velocity of about 107 cmls. As shown in Fig. 2.16, the depletion-layer width is typically on the order of 0.1 pm. The .transit time across the depletion region is typically on the order of I0-128. As we shall see later, except for diodes of very narrow base widths, this time is extremely short compared to the total time for emotving the excess electrons out of the base Thus, as long as 2.2 p-n Junctions 67 there are sufficient excess electrons in the base region, the reverse current is limited not by the diffusion ofexcess electrons but by the external resistor and has a value of1R::::: VR / R, and the slope (dnp / dx)x=o, being proportional to is approximately constant. As the excess electrons are discharged, part of the external voltage starts to appear across the p-njunction, and the junction becomes less forward biased. However, as long as there is still an appreciable amount of excess electrons stored in the base, the amount of external voltage appearing across the p-njunction remains very smalL This is evident from Eq. (2.107), which indicates that even after the excess-electron concentration at the edge of the depletion layer has decreased by a factor of 10, the junction voltage has changed by 2.3kT I q, or 60mY. This is consistent with our assumptions that the reverse current remains essentially constant. During this time, the diode remains in the on condition. At time t= ts, the excess electrons have been depleted to the point that the reverse current is limited by the diffusion ofelectrons instead ofby the external resistor. The rate of voltage change across the junction increases. Finally, when all the excess electrons are removed, the p-n diode is completely off The external reverse-bias voltage appears entirely across the junction, and the reverse current is limited by the diode leakage current. The time needed to switch off a forward-biased diode can be estimated from a charge­ control analysis (Kuno, 1964). For simplicity, we shall estimate only the time during which the reverse current is approximately constant, and during which the diode remains in the on condition. Since the junction voltage remains approximately constant during this time, charging and discharging ofthe depletion-layer capacitance ofthe junction can be ignored. Let us consider the change in the amount of charge within the p-type base region. From Eq. (2.110), the continuity equation governing the electron concentration in the base region is ot a(np npO) A diode loin (t) A np npO q -0X - diode 'tn (2.153) where in(t) is the time-dependent electron current in the base region and Adiode is the cross­ sectional area of the diode. Multiplying (2.153) by -q and integrating over the base region, we have o - Adiodeq npO) dx IW o ~ [)in d(t)x (2.154) + 'n Adiode JW (np 0 dx, or . In(O, t) = A,liode dQn (t) -d- + QB (t) Adiode - ­ + . In (W, t 'tn (2.155) where Qo(t) is the excess minority charge per unit area stored in the base region, given by (2.144). Equation (2.155) is simply the continuity equation for the base region stated in the charge-control form. in(O, t) is the electron current entering the base region. and 68 2 Basic Device Physics iiW, t) is the electron current leaving the base region. At x W, the electrons represented by in(W, t) can simply exit the base region and continue on as an electron current outside the base, which is the case for electrons exiting the base ofan n-p-n bipolar transistor (to be discussed in Chapter 6). Alternatively, the electrons represented by in{W, t) can recombine with holes at the base ohmic contact located at x W. The recombination gives rise to a current equal to iiW, t) outside the base region. In either case, the current iiW, t) is continuous across the base boundary atx = W, as required by charge conserva­ tion. The current flowing through the external resistor R is In(O, t). It is tempting to equate the current difference in (0, t) - in t) to the resistor current, but that is an inaccurate picture of current continuity. To see this, let us consider the steady-state situation when dQB(t)ldt = 0, and the special situation where recombina­ tion within the base is negligible (1'» -> 00). In this case, Eq. (2.155) gives i nCO) -i iw)= O. However, the resistor current is not zero. The resistor current is in(O), which is equal to inCW) in this special case. Consider a forward-biased diode being discharged. In this case, In(O, t) is due to electrons diffusing back towards the n+ emitter. For the coordinates system used here (see Section 2.2.4.1), these electrons travel in the -x direction. Therefore, In(O, t) is a positive quantity, and Eq. (2.155) gives Adiode dQB (t) -d- t + Adiode QB (t) -'n- + . In (W,t) h (2.156) Equation (2.156) is the continuity equation stated in the charge-control form for the base region of a diode at the initial stage of being discharged. • Discharge time for a wide-base diode. For a wide-base diode, in(W, t) =0 and the solution for Eo. (2.156) is Adiode QB (1) = lr.f. 'tn + [Adiode QB I R '1:,,] exp( -1/'t/l) , (2.157) or QB 1 I R '1:/I Adiode QB (0) [I exp(-t + exp(-tl (2.158) where QeeO) is the excess minority charge per unit area justafter the diode is switched from forward bias to reverse bias. For a wide-base diode, (2.145) gives AdiodeQB(O) -rnh· (Note the negative sign in QB, since QB is negative for elec­ trons.) Therefore, Eq. (2.158) QB IR [I QB h +exp(-( 1 Figure 2.26 is a plot ofthe charge ratio QIi(t)/QB(O) as a function of tlrn with the current ratio IR1IF as a parameter. It shows that a forward-biased wide-base diode discharges with a time constant approximately equal to the minority-carrier lifetime, unless the reverse discharge current is much larger than the forward charging current. Even for IRIh 10, the diode discharges in a time ofapproximately 'n 110 which, as can be seen 2.2 p-n Junctions 69 ell .~ 0.8 1\\ \ 'I "' '1 j o 1 'Ci ,g £ -+-1-1- - + - [RifF'" 0.5 00 0.2 0.4 0.6 0.8 Ttme/lifetime (t1r,,) Figure 2.26. Plot of charges ratio Qa(t) / Qa(0) as a function of tI,,, during the discharge of a fOlWard-biased diode, with the ratio of discharge current to charging current, 111/iF, as a parameter. from Fig. 2.24(b), is larger than 10-8 s for most diodes ofpractical doping concentrations. This time is very long compared to the typical switching delays of VLSI circuits. The important point is that it takes a long time to drain offthe excess minority ca"iers stored in a wide-base diode and turn it off It is important to minimize excess minority carriers stored in forward-biased diodes if these diodes are to be switched off fast. • Discharge time for a narrow-base diode. For a narrow-base diode, recombination can be ignored. Therefore, we have lin(O)1 = linCw)1 IF while the diode is in forward bias, and the distribution of excess electrons in the base has a constant gradient given by Eq. (2.130). At t> 0, after the diode has been switched from forward bias to reverse bias, electrons continue to flow towards and recombine at the base contact, lin(W, t)1 > O. As we shall show below, a narrow-base diode discharges in a time very small compared to Tn' That is, during the discharge of a narrow-base diode, the recombination term can be neglected, and the minority electrons are discharged only through back diffusion towards the n+ emitter and recombination at the base contact. With this approximation, (2.156) reduces to Adiode dQB(t) ---;;;- = IR . In (W,/). (2. To get an idea of how fast a narrow-base diode can be discharged, let us assume that the gradient ofthe electron distribution atx = Wremains about the same for a short time immediately after the diode is switched to reverse bias as during forward bias. That is, for a short time after switching from forward bias to reverse bias, we have W, I) ~ -h. [Note the negative sign for in(W, I). Electrons flowing in the x-direction lead to a negative current.] Also, we note that Eq. (2.146) gives AdiodeQB(O) = -IBIF for a narrow-base diode, where Is is the base transit time. With these assumptions, Eq. (2.160) gives QB (t) QB (0) ~ I (2. 70 2 Basic Device Physics for a short time after switching from on to off. Equation (2.161) shows that the discharge time for a narrow-base diode lasts approximately tB/;-/(/R + IF) which, for a large IR/IF ratio, can be much shorter than the base transit time. A complex but closed-form solution can be obtained in the large I R/h limit (Lindmayer and Wrigley, 1965), which shows that most of the charge has come out by about tB/3. The important point is that a forward-biased narrow-base diode can be switched offfast. 2.2.6 Diffusion Capacitance For a forward-biased diode, in addition to the capacitance associated with the space-charge layer, there is an important capacitance component associated with the rearrangement of the excess minority carriers in the diode in response to a change in the applied voltage. This minority-carrier capacitance is called diffitsion capacitance Consider an n+-p wide-emitter narrow-base diode, a diode where the depth or width of the n+ emitter region is large compared to its hole diffusion length and the width of the p-type base region is small compared to its electron diffusion length. (This diode is of interest because it represents the emitter-base diode of an n-p-n bipolar transistor.) When a voltage Vapp is applied across the diode, an electron current of magnitude In is injected from the emitter into the base and a hole current ofmagnitude Ip is injected from the base into the emitter. The diode current is In + Ip. Both In and Ip are proportional to exp(qVapp/kT). • Quasisteady state. In a quasisteady state, the voltage is assumed to vary slowly in time such that the minority charge distribution can respond to the applied voltage folly without any delay. In this case, the excess electron charge in the base is given by Eq. (2.146), i.e., Adiode IQn ( Vapp)tB (narrow base), (2.162) which in tum gives 6. IQn(Vapp) I Adiode---z:;:v;;;- q( ) kT In Vapp ts In(Vapp) (2~:J (narrow base), (2.163) whcre we have used Eq. (2.147) for the base transit time te. In Eq. (2.163), WB is the base width and DlIs is the electron diffusion coefficient in the base. Similarly, using (2.145) and Eq. (2.116), we have A"iode 6.IQ6p. V(aVpappp )I Ip( Vapp)rpE kqT Ip(Vapp ) (L~E) DpE emitter) (2.164) 2.2 p-n Junctions 71 for the stored holes in the n+ emitter, where LpE, DpE, and 'pE are the diffusion length, diffusion coefficient, and.lifetime, respectively, ofholes in the emitter. Equations (2.163) and (2.164) relate the change in the stored charge caused by a change in the voltage across the diode in a quasisteady state. However they do not represent the true diffusion capacitance components of a forward-biased diode, which we shall discuss next. • Diffitsion capacitance components. Consider the discharge of a forward-biased base ° region illustrated schematically in Fig. 2.25(c). When the diode is forward biased, the electron distribution is represented by the curve. When the forward bias is reduced, or when the diode is switched to reverse bias, the electron distribution evolves as a function of time, as indicated by the t> 0 curves. Part of the excess electrons diffuses to the left (back towards the emitter) and part ofthem diffuses to the right. The opposing electron currents suggest that the net charge moved through the external circuit in the discharge process is less than the total stored charge represented by the t= 0 curve in Fig. 2.25(c). When an ac voltage is applied across the diode, only those electrons iocated sufficiently close to the depletion-region boundaries can keep up with the signal and get into and out of the base. The exact amount depends on the signal frequency. These signal-following electrons give rise to in(O, t), the time­ dependent electron current at the emitter end of the quasineutral base region. As discussed in Section 2.2.5.3, inCO, t) is the electron component of the current in the external circuit. Similarly, if we consider the stored holes in the emitter, the signal­ following holes in the n+ emitter give rise to a hole current component iiD, t) at the base end ofthe emitter region and in the external circuit. These signal-following stored charges are responsible for the diffi.).sion capacitance. The exact diffusion capacitance components can be derived from a frequency­ dependent small-signal analysis of the current through a diode starting from the differential equations governing the transport of minority carriers (Shockley, 1949; Lindmayer and Wrigley, 1965; Pritchard, 1967). This is done for a wide-emitter narrow-base diode in Appendix 6. Here we simply state the results. For a wide-emitter and narrow-base n+-p diode, the low-frequency diffusion capa­ citance due to the excess electrons in the base is C DII _ - qIn k(VTapp) ( W~) 3DnB ="32 kqTIn(Vapp)tB {narrow base), (2.165) and that due to the excess holes in the emitter is C Dp qIp(kVTapp) (L~E) 2DpE 2I" kqT Ip (VapP)'pE (wide emitter). (2.166) The total diffusion capacitance is + CD CDlI C Dp . (2.167) Comparison with Eqs. (2.163) and (2.164) shows that 2/3 of the stored charge in the narrow base and \12 ofthe stored charge in the wide emitter contribute to the diffusion capacitance of a forward-biased diode. [In the case of a narrow base, a closed-fonn 72 2 Basic Device Physics solution can be obtained in the large-discharge-current limit for the transient discharge current Integration of the transient discharge current shows that 2/3 ofthe total stored charge in the narrow base diffuses back to the emitter when the base region is discharged. This fraction is the same as the fraction oftotal stored charge in the base contributing to the diffusion capacitance. In other words, one can think of the diffusion capacitance as coming from the portion ofthe stored minority charge that is "reclaimable" in the form of an ac current as the diode responds to an ac signal (Lindmayer and Wrigley, 1965).] It is instructive to examine the relative magnitude of the two capacitance compo­ nents GDn and Using the hole equivalent ofEq. (2.127) for hole current and Eq. (2.131) for electron current, and the relationship in Eq. (2.116), we have GDn (narrow base) GDp (wide ernitter) - 2 N- E W-B 3 NB LpE (2.168) The ratio NE/NB is typically about 100 for an n+-p diode. For an emitter with NE = 1 x 102ocm-3, is about 0.3 j.lm (see Fig. 2.24). Therefore, for one-sided diodes where the base width is larger than 0.03 j.lm, the ratio CDnlGDp is much larger than unity. That is, the diffusion capacitance of a one-sided p-n diode is dominated by the minority charge stored in the base of the diode. The diffusion capacitance due to the minority charge stored in the emitter is small in comparison. The effect of heavy doping, when included, will increase the amount of stored charge and hence the diffusion capacitance. Since the heavy-doping effect is larger in the more heavily doped emitter than in the I it will make the ratio CDn CDp smaller than that given by Eq. (2.168) Exercise 2.18). 2.3 MOS Capacitors The metal-oxide-semiconductor (MOS) structure is the basis of CMOS technology. The Si-Si02 MOS system has been studied extensively (Nicollian and Brews, 1982) because it is directly related to most planar devices and integrated circuits. In this section, we review the fundamental properties ofMOS capacitors and the basic equations that govern their operation. The effects ofcharges in the oxide layer and at the oxide-silicon interface are discussed in Section 2.3.6. 2.3.1 2.3.1.1 Surface Potential: Accumulation, Depletion, and Inversion Energy-Band Diagram of an MOS System The cross section of an MOS capacitor is shown in 2.27. It consists of a conducting gate electrode (metal or heavily doped polysilicon) on top of a thin layer of silicon dioxide grown on a silicon substrate. The energy band diagrams ofthe three components when separate are shown in Figure. 2.28. Before we discuss the energy band diagram of an MOS device, it is necessary to first introduce the concept electron level and work jUnction which play keyro1cs in the relative energy band placement when two different materials are brought into contact. Figure 2.28(c) shows the band diagram ofa 2.3 MOS Capacitors 73 Gate electrode (metal or polysilicon) t", Silicon substtate Silicon '"dioxide Figure 2.27. Schematic cross section of an MOS capacitor. Free · elevleel ctrol.lT Ec q,. =4.lOeV 95ev Free -,----,- electron level r :i.............I.. IE Ef 8-9 eV .Epe t _._--_. Ei 8= V qB E 1.12 e f Ev Metal (aluminum) Silicon Ev (p-type) Figure 2.28. Silicon dioxide (al (b) (c) Energy-band diagram of the three components of an MOS capacitor: (a) metal (aluminum), (b) silicon dioxide, and (c) p-type silicon. p-type silicon with the addition of the free electron level at some energy above the conduction band. The free electron level is defined as the energy level above which the electron is free, no longer bonded to the lattice.) In silicon, the free electron level is 4.05 eV above the conduction band edge, as shown in Figure. 2.28(c). In other words, an electron at the conduction band edge must gain an additional energy of 4.05 eV the electron affinity, in order to break loose from the crystal field of silicon. 2.28(b) shows the band diagram of silicon dioxide - an insulator with a large energy gap in the range of 8-9 eV. The free electron level in silicon dioxide is 0.95 eV above its conduction band. 3 In other texts, the free electron level is often referred to as the vacuum level. Here we use a dif~;rent term to avoid the implication that the vacuum level is universal. 2 Basic Device Physics Free ---.-,-""71"--.---. electron level Free __ electron level Ef Ee f.---.-I---.~~l.. Ef Ef i--·t:===== Ef SiC. SiOz (a) (b) Rgure 2.29. BanddiagramsofanMOS system under (a) theflatband condition, and (b) zero gate-voltage condition. Work function is defined as the energy difference between the free electron level and the Fermi level. For the p-type silicon example in Fig. 2.28(c), the work function, qs = qX + Eg 2 + qlf/IJ. (2.169) Here If/B is the difference between the Fermi potential and the intrinsic potential given by Eq. (2,48). The same definition of work function, qs - called theflatband voltage, with respect to the silicon substrate. This is seen in Fig. 2.29(a) as the displacement between the two Fermi levels. In general, the flatband voltage of an MOS device is given by = V (.h jb 'I'm J.. ) '1'$ - -QCox ,= .h 'I'm, - -QCox ' ox Ox (2.170) where Qox is the equivalent oxide charge per unit area at the oxide-silicon interface (defined in Section 2.3.7), and Cox is the oxide capacitance per unit area, f:.ox 1''"'0 1,..,.., \ 2.3 MOS CapaCitors 75 for an oxide film' of thickness lox and permittivity eox. In modern VLSI technologies, QoJq at the Si-Si02 interface can he.controlled to below 1010 cm-2 (pQsitive) for (100)­ oriented surfaces. Its contribution to the fiatband voltage is less than 50 mV for thin gate oxides used in I-JlIIl technology and below (tox:S 20 om). Therefore, the flatband voltage is mainly determined by the work function difference is applied, as depicted by the dashed lines in Fig. 2.30, the metal Fermi level is displaced downward from that of the fiatband condition by a total amount of Vg Vjb. Because ofthe fixed band relationship between the metal and oxide, the oxide conduction band on the metal side is also displaced downward by the same amount. This causes a field to develop in the oxide and, at the same time, a downward bending ofthe bands in the p-type silicon near the surface. The amount of band bending in silicon is defined as the surface potential, 'II" i.e., the potential at the silicon surface relative to that in the bulk substrate. Because of the fixed band relationship between the oxide and silicon, it is clear that Vg - Vjb 'lis + Vox, (2.172) where Vox is the potential drop across the oxide, as indicated in Fig. 2.30. How Vg - V;b is partitioned into 'lis and Vox depends on both the oxide thickness and the doping concentration of the p-type silicon. Based on the dielectric boundary conditions discussed in Section 2.1.4.2, a field relationship exists at the silicon-oxide interface, Cox eSi lfs , (2.173) or 'i!ox ~ 3'i!s, assuming negligible trapped charge at the interface. Note that the above equation applies to both the magnitude and the direction ofthe fields. In most cases, there is negligible net charge in the oxide and Poisson's equation becomes dlf/dx = O. Therefore, the field in the oxide is constant,4 and Vox Ifoxtox. 2.3.1.3 Accumulation, Depletion, and Inversion Figure 2.31 shows the band diagrams of p-type «a}-(d» and n-type «e}-(h» MOS capacitors under different gate bias voltages with respect to the fiatband voltage. For simplicity, the flatband voltage is taken to be zero for all cases. The fiatband condition for p-type MOS discussed before is shown in Fig. 2.31(a). There is no charge, no field, and the carrier concentration equals the ionized acceptor concentration throughout the sili­ con. Now consider the case when a negative voltage is applied to the gate of a p-type MOS capacitor, as shown in Fig. 2.31(b). This raises the metal Fermi level (i.e., electron energy) with respect to the silicon Fermi level and creates an electric field in the oxide that would accelerate a negative charge toward the silicon substrate. A field is also . induced at the silicon surface in the same direction as the oxide field. Because of the low carrier concentration in silicon (compared with metal), the bands bend upward toward the oxide interface. The Fermi level sto:ys flat within the silicon, since there is no netflow ofconduction current, as was discussed in Section 2.1.4.5. Due to the band bending, the 4 If the field in the oxide is nol constant, 'if ox in Eq. (2.173) is defined as the oxide field at the oxide-silicon interface. . 2.3 MOS Capacitors 77 p-type n-type flatband (a) (e) accumulation (b) (f) '('.-;: -: -.-f. depletion (c) L.. - Ec (g) inversion (d) ~ - Ec (h) - - - - - - _Ef "" ++++Ev E. Figure 2.31. Energy-band diagrams lor ideal (zero flatband Voltage) (a)-(d) p-type and (e)--(h) n-type MOS capacitors under different bias conditions: (a), (e), flat band; (b), (t), accumulation; (c), (g), depletion; (d), (h), inversion. (After Sze, 1981.) valence band at the surface is much closer to the Fermi level than is the valence band in the bulk silicon. This results in a hole concentration much higher at the surfuce than the equilibrium hole concentration in the bulk. Since excess holes are accumulated at the surface, this is referred to as the accumulation condition. One can think of the excess holes as being attracted toward the surface by the negative gate voltage. An equal amount of negative charge appears on the metal side of the MOS capacitor, as required for charge neutrality. On the other hand, if a positive voltage is applied ·to the gate of a p-type MOS capacitor, the metal Fermi level moves downward, which creates an oxide field in the direction of accelerating a negative charge toward the metal electrode. A similar field is induced in the silicon. which causes the bands to bend downward toward the surface, as 78 2 Basic Device Physics shown in Fig. 2.3 I(c). Since the valence band at the surface is now farther away from the Fermi level than is the valence band in the bulk, the hole concentration at the surface is lower than the concentration in the bulk. This is referred fo as the depletion oondition. One can think of the holes as being repelled away from the surface by the positive gate voltage. The situation is similar to the depletion layer in a p-n junction discussed in Section 2.2.2. The depletion of holes at the surface leaves the region with a net negative charge arising from the unbalanced acceptor ions. An equal amount of positive charge appears on the metal side of the capacitor. As the positive gate voltage increases, the band bending also increases, resulting in a wider !iepletion region and more (negative) depletion charge. This goes on until the bands bend downward so much that at the surface, the oonduction band is closerto the Fermi level than the valence band is, as shown in Fig. 2.31(d). When this happens, not only are the holes depleted from the surface, but the surface potential is such that it is energetically favorable for electrons to populate the conduction band. In other words, the surface behaves like n-type material with an electron concentration given by Eq. (2.49). Note that this n-type sUrface is formed not by doping, but instead by inverting the original p-type substrate with an applied electricfield. This condition is called inversion. The negative charge in the silicon consists of both the ionized acceptors and the thermally generated electrons in the oonduc­ tion band. Again, it is balanced by an equal amount ofpositive charge on the metal gate. The surface is inverted as soon as Ej = (Ee + Ev)/2 crosses Ef This is called weak inversion because the electron concentration remains small until Ej is considerably below E1' Ifthe gate voltage is increased further, the concentration of electrons at the surface will be equal to, and then exceed, the hole concentration in the substrate. This condition is called strong inversion. So far we have discussed the band bending for accumulation, depletion, and inversion of silicon surface in a p-type MOS capacitor. Similar conditions hold true in an n-type MOS capacitor, except that the polarities of voltage, charge, and band bending are reversed, and the roles of electrons and holes are interchanged. The band diagrams for flatband, accumuJatio~, depletion, and inversion conditions of an n-type MOS capacitor are shown in Fig. 2.3J(e)-(h), where the metal work function per electron charge 4>m is assumed to be equal to that of the n-type silicon, given 4>5 = X + - !flB, (2.174) instead of Eq. (2.169). Accumulation occurs when a positive voltage is applied to the metal gate and the silicon bands bend downward at the surface. Depletion and inversion occur when the gate voltage is negative and the bands bend upward toward the s\lrface. 2.3.2 2.3.2.1 Electrostatic Potential and Charge Distribution in Silicon Solving Poisson's Equation In this sub-subsection, the relations among the surface potential, charge, and electric field are derived by solving Poisson's equation in the surface region ofsilicon. A more detailed band diagram at the surface of a p-type silioon is shown in 2.32. The potential 2.3 MOS Capacitors 79 Silicon surface - --- Ei ----E - - - - - Ef v Oxide p-type silicon x FIgure 2.32. Energy-band diagram near the silicon surface of a p-type MOS device. The band bending '1/ is defined as positive when the bands bend downward with respect to the bulk. Accumulation occurs when '1/,< O. Depletion and inversion occur when !fI, > O. IjJ.(X) -!fl'(x =(0) is defined as the amount ofband bending at position x, wherex=O is at the silicon surface arid 1jJ,{x = (0) is the intrinsic potential in the bulk silicon. Rememberthat Ij/(x) is positive when the bands bend downward. The boundary conditions are !fl = 0 in the bulk silicon, and 1jJ= IjJ(O) = 'II. at the surface. The surface potential 1jJ. depends on the applied gate voltage, as discussed in Section 2.3.1.2. Poisson's equation, (2.44), is cPljJ -xd2 d't: dx q -es:, [P(x) - n(x) + N% (x) N~ (x)]. (2.175) For a uniformly doped p-type substrate of acceptor ooncentration Na with complete ionization, N% (x) N;; (x) - No, independent ofx. Charge neutrality condition deep in the bulk substrate requires . NId (x) - N~ (x) - Na n2 -Po +..P2o.., (2.176) where Po p(x = (0) and nfIPo n(x = (0) are the majority (holes) and minority (electrons) carrier densities in the bulk substrate, respectively. In general, p(x) and n(x) are given by Eq. (2.50) and Eq. (2.49), which can be expressed in terms of IjJ(x) using ljJ(x) ljJi(X) -ljJj(x = (0) and 'liB = IjJf 'IIi(x = (0) as defined in Fig. 2.32: p(x) = ni = Po (2.177) and n(x) = nieq!\Vi(X) \V;l/kT nieq['I'(x)-'I'Bl/kT eql(l(x)/kT. Po (2.178) Note that IjJf is independent ofx because there is no net current flow perpendicular to the surface and the Fermi level stays flat. Also note that Po = p(x (0) = ni exp(qljJB!k 1) and rif /Po = n(x = (0) = n,'Cx.p(-q!flB/kT) in the last step of the above equations. In practice, Na :$ nj, andpo""Na from Eq. (2.176). Substituting the last three equations into Eq. (2.175) and replacing Po by Na yield 80 2 Basic Device Physics J2~ I) [Na (e-qlfllkT _ ni dx Gsi Na - 1)]. (2.179) MUltiplying (dlflldx) dx on both sides of Eq. (2.179) and integrating from the bulk (Ifl = 0, dlflldx = 0) toward the surface, one obtains ldlfl1dX dlfl d(dlfl) o dx dx f.~j J: 1) _ (e-qlfllkT _ ~~2 (eqlfl/kT _ dlfl, (2.180) which gives the electric field at x, 'if; = -dlflldx, in tenus of 1fI: 'if;2 dlfl) 2 2kTNa ( dx osi + qlfl kT _ 1) 1)]. + ni (eq'fllkT _ qlfl _ N~ kT (2.181) Atx=O, we let 1fI= 1fI. and 'if; = 'if;s. From Gauss's law, Eq. (2.43), the total charge per unit area induced in the silicon (equal and opposite to the charge on the metal gate) is Qs = -8s;'l:s = ±J2SsikTNa [(e-q'!',lkT + qlfls kT - I) + ~2 (eQIfl,/kT - JV2a 1) J1/2 (2.182) This function is plotted in Fig. 2.33. At the fiat-band condition, IfIs = 0 and Q.. =0. In accumulation, IfIs < 0 (bands bending upward) and the first teon in the square brackets dominates once -q1fl/kT > 1. The accumulation charge density is then proportional n; to exp(-'QIfl/2k1) as indicated in the Fig 2.33.5 In depletion, IfIs> 0 and QIfl/kT> 1, but exp(qlfl/k1) is not large enough to make the IN~ teon appreciable. Therefore, the qlflikT teon in the square brackets dominates and the negative depletion charge density (from ionized acceptor atoms) is proportional to IfIs 112. When IfIs increases further, the (nil N~) exp(qlflslkT) teon eventually becomes larger than the qlfl/kT term and dominates the square bracket. This is when inversion occurs. The negative inversion charge density is proportional to exp(Qlfli2k1) as indicated in Fig. 2.33. A popular criterion for the onset ofstrong inversion is for the surface potential to reach a value such that (nf I N;)exp(qlflslkT) 1, i.e., 1fI.. (m. v) 21f1B 2kqT In (N-;;a; ) . (2.183) 5 These resullS stem from the Maxwell-Boltzmann approximation made in Section 2.1.1.3, which over­ estimates the occupancy of electron stales near and below the Fenni level. For accumulation and inversion layers with carrier densities in the degenerate range, i.e.• when 'l's < -0.2 Vor > 0.9 V where the Fermi level goes into the valence or the conduction band. the mOre exact Fenni-Dirac distribution gives a less steep rise of the sheet Charge density with the surface potential. 2.3 MOO Capacitors 81 1~~1- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ­ p-type Si (300 'N. 4 X lO'S 10-5 ~ Q g 10-7 exp (q [1jJ,I/2kT) (Accumulation) 1(J8 Weak inversion \0-91 II II I II -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1jJ,(V) Figure 2.33. Variation of total charge density (fixed plus mobile) in silicon as a function of surface potentiall/fs for a p-type MOS device. The labels Ev, Ej , Ec indicate the surface potential values where the valence band, the intrinsic level, and the conduction band cross the Fermi level. (After Sze, 1981.) Under this condition, the electron concentration given by Eq. (2.178) at the surface becomes equal to the depletion charge density No. After inversion takes place, even a slight increase in the su.rface potential results in a large buildup ofelectron density at the surface. The inversion layer effectively shields the silicon from further penetration ofthe gate field. Since almost all ofthe incremental charge is taken up by electrons, there is no further increase of either the depletion charge or the depletion-layer width. The expression in Eq. (2.183) is a rather weak function of the substrate doping concentration. For typical values of No = 1016-1018 cm-3, 21/fB varies only slightly. from 0.70 to 0.94 V. 2.3.2.2 Depletion Approximation In general, Eq. (2.181) must be solved numerically to obtain IfI{x). In particular cases, approximations can be made to allow the integral to be carried out analytically. For example, in the depletion region where 21f1B> 1fI> kTlq, only the qlfllkTterm in the square bracket needs to be kept and dlfl = _V2qNalfl. dx esi One can then rearrange the factors and integrate: (2.184) 82 2 Basic Device Physics -JX V2QNa fo dx 0 os; , where 1fI.. is the surface potential at x '" 0 as assumed before. Therefore, (1­ IfI 1fI. which can be written as :dr· VI = Vls(l- This is a parabolic equation with the vertex at IfI == 0, X =Wd, where (2.185) (2.186) (2.187) Wd= (2.188) is the depletion-layer width defined as the distance to which the band bending extends. The total depletion charge density in silicon, Qd, is equal to the charge per unit area of ionized acceptors in the depletion region: -V Qd = -qNaWd = 2sSiqNalfls· These results are very similar to those of the one-sided abrupt p-n junction under the depletion approximation, discussed in Section 2.2.2. In the MOS case, however, Wd reaches a maximum value Wdm at the onset of strong inversion when IfIs= 21f1B' Substituting Eq. (2.183) into Eq. (2.188) gives the maximum depletion )Vidth: Wdm= (2.190) 2.3.2.3 Strong Inversion Beyond strong inversion, the (nT/ N;;) exp(qlfl/k1) tenn representing the inversion charge in Eq. (2.181) becomes appreciable and must be kept, together with the depletion charge term: dlfl 2kTNa (qlfl + nt eQ'l'lkT). dx eSI· kT ~ (2.191) This equation can only be integrated numerically. The boundary condition is VI IfIs at x = O. After IfI(X) is solved, the electron distribution n(x) in the inversion layer can be calculated from Eq. (2.178). Examples of numerically calculated n(x) are plotted in 2.34 for two values of 1fI. with Na == 1016 cm-3. The electrons are distributed extremely close to the surface with an inversion-layer width less than 50A. A higher surface potential or field tends to confine the electrons even closer to the surface. In 2.3 MOS Capacitors 83 L2E+19 l lE+19 Na "'1016 cm-3 8E+18 d' 1\ 0 '!c 6E+l8 ~ c; 0 "e0: 4E+18 tl III fil 2E+l8 J ,,1fI$=0.88 V ,,~ 50 100 150 200 Distance from surface, x (A) Figure 2.34. Electron concentration versus distance in the inversion layer of a p-type MOS device. general, electrons in the inversion layer must be treated quantum-mechanically as a 2-D gas (Stern and Howard, 1967). According to the quantum-mechanical model, inversion­ layer electrons occupy discrete energy bands and have a peak distribution 10-20 A away from the surface. More details will be discussed in Section 4.2A. When the inversion charge density per unit area, Qt, is much greater than the depletion charge density, Eq. (2.182) can be approximated by 2.3.2.4 Since the electron concentration at the surface. is n(O) = -n..2!...eq'l',lkT Na ' (2.193) one can write = V2BsikTn(O). (2.194) The effective inversion-layer thickness (classical model) can be estimated from Qi Iqn(O) = 2eSikT I qQi, which is inversely proportional to Qi' Similar expressions also hold true for the surface charge density of extra holes under accumulation, except that the factor n7/ No is replaced by Na. Surface Potential and Charge Density as a Function of Gate Voltage In Section 2.3.2.1, charge and potential distributions in silicon were solved in terms of the surface potential IfIs as a boundary condition. IfIs is not directly measurable, but is controlled by and can be determined from thc applied gate voltage. The gate voltage 84 2 Basic Device Physics Metal, Oxide T p-type silicon (a) qVg> 0 Ef region Neutral region Inversion region Qgl o "dm (b) - - - - -tox ;c :d Q.=-Qg Figure 2.35. (a) Band diagram of a p-type MOS capacitor with a positive voltage applied to the gate (Vjb 0). (b) Charge distribution under inversion condition. equation, Eq. (2.172), relates the potential drop Vax across the oxide and the band bending If/. in silicon to the departure from the flatband condition due to the applied gate voltage Vg (Fig. 2.35(a». Assuming negligible fixed charges in the oxide, the potential drop Vax can be expressed as '!:oxtox, which equals (8./8ox)'!:stox based on the boundary condition, Eq. (2.173). Applying Gauss's law, Qs'" -8s;'!:.. the gate bias equatian becomes - c Vg ~ Vp = Vox + !fI_ = ~Qs + !fl., ox (2.195) where Qs is the total charge per unit area induced in the silicon, and Cox 80,!tox is the oxide capacitance per unit area for an oxide of thickness tox. There is a negative sign in front of Qs in Eq. (2.195) because the charge on the metal gate is always equal but opposite to the charge in silicon, i.e., Qs is negative when Vp is positive and vice versa. The charge distribution in an MOS capacitor is shown schematically in Fig. 2.35 where the total charge Qs may include both depletion and inversion components. For .discussion, oxide and interface trapped charges are ignored here. They will be discussed in detail in Sections 2.3.6 and 2.3.7. In general, (1 is a function ofIf/. given by Eq. (2.182), and plotted in Fig. 2.33. Equation (2.195) is then an implicit equation that can be solved for If/s as a function of Vg- An example ofthe numerical solution is shown in Fig. 2.36. Below the condition for strong inversion, If/s = 21f/B, If/s increases more or less linearly with Beyond If/. 21f/a, If/s nearly saturates­ 2.3 MOS Capacitors 85 1 . 2 , - - - - · · · · · ·............ lE-6 >1 "-" 0.8 ~ 0.4 ~ 0.2 ,. 0' o 2lf/B / ...-. - - '-j8E-7"'a . U~ Q /" ../ / 6E-7 :; S'. ._ • #/### ~ ,.'.,' ~··/Qi j 4E-1 ;; -" ----~ ,.:'-.,-' -...:'•-•/ ..,­ /' / -Q- - ­ - - 2E-7 U d /, 0.5 1 1.5 2 2.5 , OE+O 3.5 Gate voltage Vg (V) FigUl1l2.36. Numerical solutions of swface potential, total silicon charge density, inversion charge density, and depletion charge density from the gate voltage equation (2.195) coupled to Eq. (2.182). The MOS deviceparametersareNa = 1017 cm-3,tox = 10nm,and Vfo=O. increasing by less than 02 V while Vg increases by 2 V. After If/. is solved, Qs is calculated and plotted as a function of Vg in Fig. 2.36. By numerically evaluating the integrals in Exercise 2.6, Qs is separated into its two components, the depletion charge density Qd and the inversion charge density Q;, which are also plotted in Fig. 2.36. It is crear that before the 1fI. '" 2lf/B con.dition, the charge in the silicon is predominantly ofthe depretian type. Under such depletion conditions, (1(If/.) '" QJlf/s), an analytical expression for If/.(Vg) can be derived by solving a quadratic equation (see Eq. (2.202». After Vis 21f/s. the depletion charge no longer increases with Vg because of shielding by the inversion layer discussed before. Almost all ofthe increase ofQ.. beyond Vis '" 21f1B is taken up by ~ with a slope dQ/dVg ::::; COX' While on the linear scale it appears that Qi is zero below the If/s 2lf/B threshold, on the log scale it can be seen that Qi actually remains finite and decreases exponentially with Vg- It is the source of the subthreshold leakage current in MOSFETs­ an important design consideration further addressed in detail in Section 3.1.3.2. Under extreme accumulation and inversion conditions, ~ Vjb), since both Vg and Vox can be much larger than the silicon bandgap, 1.l2 V (for CMOS technologies with Vdd » 1V), while If/s is at most comparable to Egfq (surface potential pinned to either the valence band or the conduction band edge). 2.3.3 2.3.3.1 Capacitances in an MOS Structure Definition of Small-Signal Capacitances We now consider the capacitances in an MOS structure. In most cases, MOS capacitances are defined as small-signal differential ofcharge with respect to voltage or potential. They can easily l:>e measured by applying a small ac voltage on top of a dc bias across the device and sensing the out-of-phase ac current at the same frequency (the in-phase component gives the small-signal conductance). The total MOS capacitance per unit area is (2.196) 86 2 Basic Device Physics 2.3.3.2 If we differentiate capacitance as (2.195) with respect to -Qs and define the silicon part of the d( -Qs) ~' (2.197) we obtain -1 + Cox +-I . Cs; (2.198) In other words, the total capacitance equals the oxide capacitance and the silicon capaci­ tance connected in series. The capacitances are defined in such a way that they are all positive quantities. An equivalent circuit is shown in Fig. 2.37(a). In reality, there is also an interface trdp capacitance in parallel with It arises from charging and discharging of Si-Si02 interface traps and will be discussed in more detail in Section 2.3.7. Capacitance-Voltage Characteristics: Accumulation A typical capacitance-versus-gate-voltage (C-JI) curve of a p-type MOS capacitor is plotted in Fig. 2.38, assuming zero fiatband voltage. In fact, there are several different curves, depending on the frequency of the applied ac signal. We start with the "low­ frequency" or qUilSistatic C-V curve. When the gate voltage is negative (by more than a few kTlq) with respect to the flatband voltage, the p-type MOS capacitor is in accu­ mulation and Qs"" exp(-q'lf,l2kT), as shown in Fig. 2.33. Therefore, '" -dQ,Id'lfs (qllk1)Qs (qllk1)Co.JVg- Vjb-'lfsl, and the MOS capacitance per unit area is given by ~=_1_[1+ 2kT/q ]. Cg Cox IVg - Vjb -'If,i (2.199) Since 2kT/q ::::: 0.052 V and 'If. is limited to 0.1 to 0.3 V in accumulation, the MOS capacitance rapidly approaches Cox when the gate voltage is ~-2 V more negative than the flat-band voltage.6 2.3.3.3 Capacitance at Flat Band When the gate bias is zero in Fig. 2.38, the MOS is near the fiat-band condition; therefore, q'lf,lkT «1. The inversion charge term in Eq. (2.182) can be neglected and the first exponential term can be expanded into a power series. Keeping only the first three terms of the series, one obtains Qs'" -(£s;q2NJk1)1I2V1s. From Eq. (2.198), the fiatband capacitance per unit area is given by - I+ - Cox esi (2.200) 6 Actually, Cg approaches C"" slower than that depicted by Eq. (2.199) because ofthe Feuni-Dirac distribution at degenerate carrier densities. 2.3 MOS Capacitors 87 Gate cor T C" rGate c"" ~-'i''''-''''''Li Cd :r~-.;q:i~ Q, C. ' p-type substrate p-type substrate t n+ channel (a) (b) Figure 2.37. Equivalent circuits of an MOS capacitor. (a) All the silicon capacitances are lumped into Cs;· (b) Csj is broken up into a depletion charge capacitance Cd and an inversion-layer capacitance Cj• Cd arises from the majority carriers, which can respond to high-frequency as well as low-frequency signals. Ci arises from the minority carriers, which can only respond to low-frequency signals, unless the surface inversion channel is connected to a reservoir of minority carriers as in a gated diode configuration. The thin dotted connection in (b) is effective only at low frequencies where minority carriers can respond. where LD is the Debye length defined in Eq. (2.53). In most cases,Cjb is somewhat less than Cox. For very thin oxides and low substrate doping, Cfb can be much smaller than Cox. 2.3.3.4 Capacitance-Voltage Characteristics: Depletion When the gate voltage is slightly higher than the Hatband voltage in a p-type MOS capacitor, the surface starts to be depleted of holes; lICsi becomes appreciable and the capacitance decreases. Using the depletion approximation, one can find an analytical expression for Cg in this case. From Eq. (2.188) and Eq. (2.189), Cd d(-Qd) d'lfs = (2.201) The last expression is identical to the depletion-layer capacitance per unit area in the p--n junction case discussed in Section 2.2.2. The bias equation (2.195) becomes V V qNa Wd + V2s,;qNa'lfs + g jb C 'If, C 'lfs' ox ox (2.202) Substituting Cd from Eq. (2.201) for Cs; in Eq. (2.202)"one obtains (2.198), and eliminating 'lfs using Cg (2.203) 88 2 Basic Device Physics 1.0 I C, =Cox -. Cg = Cox 0.8 ':;,!.~ 0.6 u" 0.4 0.2 0 1 -V, +-­ en":' Semiconductor breakdown ! o V, >-----l _+Vg f'lIIure 2.38. MOS capacitance-voltage curves: (a) low frequency, (b) is assumed. (After Size, 1981.) frequency, (c) deep depletion. Vjb = 0 This equation shows how the MOS capacitance decreases with increasing Vg under the depletion condition. It selVes as a good approximation to the middle portions ofthe C-V CUlVes in 2.38, provided that the MOS capacitor is not biased near the flat-band or the inversion condition. 2.3.3.5 Low-Frequency G-VCharacteristics: Inversion As the gate voltage increases further, however, the capacitance stops decreasing when IfJs = 2lfJB (2.183)] is reached and inversion occurs. Once the inversion layerforms, the capacitance starts to increase, since Csi is now given by the variation ofthe inversion charge with respect to 1fI., which is much larger than the depletion capacitance. Assuming that the silicon charge is dominated by the inversion charge, one can carry out an approximation as in the accumulation case and show that the MOS capacitance in strong inversion is also given by Eq. (2.199). One difference is that 1ft. at inversion is in the range of 0.7 to l.0 V, significantly higher than that at accumulation. In any case, the capacitance rapidly increases back to Cox when the gate voltage is more than 2 to 3 V beyond the flat-band voltage, as shown in the low-frequency C-V curve (a) in Fig. 2.38. 2.3.3.6 High-Frequency Capacitance-Voltage Characteristics The above discussion of the low-frequency MOS capacitance assumes that the carrier, the inversion charge, is able to follow the applied ac signal. This is true only if the frequency of the applied signal is lower than the reciprocal of the minority-carrier response time. The minority-carrier response time can be estimated from the generation­ recombination current density, JR qniWJr, where r is the minority-carrier lifetime discussed in Section 2.1.4. The time it takes to generate minority carriers to 2.3 MOS Capacitors 89 replace something comparable to the depletion charge, Qd = qNaWd, is on the order of QJJR (N)n;)r (Jund arid Poirier; 1966). This is typically OJ-lOs. Therefore, for frequencies higher than 100 Hz or 80, the inversion charge cannot respond to the applied ac signal.. Only the depletion charge (majority carriers) can respond to the signal, which means that the silicon capacitance is given by Cd ofEq. (2.201) with Wd equal to its maximum value, Wd"" in (2.190). The high-frequency capacitance per unit area thus approaches a constant minimum value, Cmin, at inversion given by I = _1_ + J4kTln(Na1n;) Cox SSjq2Na (2.204) This is shown in the high-frequency C-V curve (b) in Fig. 2.38. Typically, C-V CUlVes are traced by applying a slow-varying ramp voltage to the gate with a small ac signal superimposed on it. However, if the ramp rate is fast enough that the ramping time is shorter than the minority-carrier response time, then there is insufficient time for the inversion layer to form, and the MOS capacitor is biased into deep depletion as shown by curve (c) in Fig. 2.38. In this case, the depletion width can exceed the maximum value given by Eq. (2.190), and the MOS capacitance decreases further below Crnin until impact ionization takes place (Sze, 1981). Note that deep depletion is not a steady-state condition. If an MOS capacitor is held under such bias conditions, its capacitance will gradually increase toward Croin as the thermally generated minority charge builds up in the inversion layer until an equilibrium state is established. The time it takes for an MOS capacitor to recover from deep depletion and return to equilibrium is referred to as the retention time. It is a good indicator of the defect density in the silicon wafer and is often used to qualify processing tools in a It is possible to obtain low-frequency-like C-V curves at high measutement frequen­ cies. One way is to expose the MOS capacitor to intense illumination, which generates a large number of minority carriers in the silicon. Another commonly used technique is to form an n+ region adjacent to the MOS device and connect it electrically to the p-type substrate (Grove, 1967). The n+ region then acts like a reselVoir of electrons which can exchange minority carriers freely with the inversion layer. In other words, the n+ region is connected to the surface channel of the inverted MOS device. This structure is similar to that of a gated diode, to be discussed in Section 2.3.5. Based on the equivalent circuit in Fig. 2.37(b), the total MOS capacitance per unit area is given by C _ Cox(Cd+Ci) g- C,JX+Cd+Ci' (2.205) When the MOS device is biased well into strong inversion, the inverSion-layer capaci­ tance Ci can be approximated by using Eq. (2.192). Cjd=(-- Qi- ) ~- IQ- il dlfJs 2kT/q ",~12,,206) .. The majority and minority carrier contributions to the total capacitance can be separately measured in a split C-V setup shown in Fig. 2.39(a) (Sodini et al., 1982). 90 2 Basic Device Physics (a) Vg n+ (b) 100 , - - - - - - - - - - - - - - - - , 80 f£ ~ 60 8 a.~ u 40 20 -dQ;ldYg 1/ or " ':" r -3 -2 -1 0 2 Gate voltage (V) Figure 2.39. (a) Setup of the split C-Vmeasurement. Both the dc bias and the small-signal ac voltage are applied to the gate. Small signal ac cunents are measured by two ammeters, AI and A2, connected separately as shown. (b) Measured C-V curves where the -dQ,JdVg component is obtained from AI, and the -dQ/dVg component is obtained from A2. The sum is the total capacitance per unit area, -dQ)dVg• With a small signal ac voltage applied t.o the gate, the out-of-phase ac currents are sensed by two ammeters: one (AI) connected to the p-type substrate for the hole current, and another (Al) connected to the n+ region for the electron current. Typical measured results are shown in Fig. 2.39(b). The hole contribution to the capacitance measured by Al is dQd (2.207) dVg And the electron contribution to the capacitance measured by A2 is dQ; C"xCi dVg Cox + Cd+ C;' (2.208) They add up to the total capacitance per unit area, Cg "" -dQ/dVg . Note that the -dQ) dVg curve decreases to zero soon after strong iuversion when C; (Eq. (2.206» becomes 2.3 MOS Capacitors 91 dominant (»Cox)' To put it in another way, the highly conductive inversion channel shields the majority carriers in·thebulk silicon so they do not respond to the modulation of gate field. The -dQ/dVg curve can be integrated to yield the inversion charge density as a function of the gate voltage. It is used, for example, in channel mobility measure­ ments where the inversion charge density must be determined accurately. 2.3.4 2.3.4.1 Polysilicon-Gate Work Function and Depletion Effects Work Function and Flatband Voltage of Polysilicon Gates In the mainstream CMOS VLSI technology thus far, n+-polysilicon gate has been used for nMOSFET and p+-polysilicon gate for pMOSFET to obtain threshold voltages oflow magnitude in both devices. The Fermi level of heavily doped n+ polysilicon is near the conduction band edge, so its work function is given by the electron affinity, qx. From Eq. (2.169), the work function difference for an n+ polysilicon gate on a p-type substrate of doping concentration No is ~'I'm, --~2 -!Po = -0.56 --kITn (-~) q q ni (2.209) in volts. Similarly, the work function difference for a p+ polysilicon gate on an n-type substrate of doping concentration N" is =-E2g +!PB=O.56+kT-ln (N- d) , q q ni (2.210) which is symmetric to Eq. (2.209). These relations give rise to flatband voltages with key implications on the scalability of MOSFET devices, as will be discussed in Chapter 4. The band diagram of an n+-polysilicon-gated p-type MOS capacitor at zero gate voltage is shown in Fig. 2.40(a), where the Fermi levels line up and the free electron level of the bulk p-type silicon is higher in electron energy than the free electron level of the n+ polysilicon gate. This sets up an ox.ide field in the direction of accelerating electrons toward the gate, and at the same time a downward bending of the silicon bands (depletion) toward the surface to produce a field in the same direction. The flatband condition is reached 9Y applying a negative voltage equal to the work function difference to the gate, as shown in Fig. 2.40(b). 2.3.4.2 Polysilicon-Gate Depletion Effects The use of polysilicon gates is a key advance in modem CMOS technology, since it allows the source and drain regions to be self-aligned to the gate, thus eliminating parasitics from overlay errors (Kerwin et al., 1969). However, if the polysilicon gate is not doped heavily enough, problems can arise from depletion of the gate itself. This is especially a concern with the dual n+-p+polysilicon-gate process in which the gates are doped by ion implantation (Wong et at., 1988). Gate depletion results in an additional capacitance in series with the oxide capacitance, which in tum leads to a reduced inversion-layer charge density and degradation of the MOSFET transconductance. 92 2 Basic Device Physics (a) (b) Vg = Vjb= ¢"", Ef --rIl -qNa P (x) •X L~~~-~,x t:f'>'h';;,~~"",'h",+'h'\)l -qN. Q; Q; Ee r.. __ I qt,...L ==::_ ... : • x EI E, r---~~~E;;"X Figure 2.45. raJ [bJ Comparison of charge distribution and energy-band variation of an inverted p-type region for (a) the equiUibrium case and (b) the nonequillibrium case. (After Grove, 1967.) 2.3.5.2 Band Bending and Charge Distribution of an MOS Under Nonequilibrium The above discussions are further illustrated in Fig. 2.45, where the charge distribution and band bending in a cross section perpendicular to the gate through the neutral p-type region are shown for both the equilibrium and the nonequilibrium cases. The equilibrium case is the same as that discussed in Section 2.3.2. In the nonequilibrium case, the hole quasi-Ferroi level is the same as the Fermi level in the bulk p-type silicon, but the electron quasi-Fermi level is dictated by the Fermi level in the n+ region (not shown in Fig. 2.45), which is qVR lower than the p-type Fermi level. As a result, surface inversion occurs at a band bending IJIs(inv) = VR + 21f/B, (2.217) and the maximum depletion width is a function ofthe reverse bias VR, (2.218) from Eq. (2.188). " 98 2 Basic Device Physics 1.0 I ­ I 1/J,= 0 0.2 ~ r,J tl 0.9 J "2 = No= I x 1016cm-3 tox 1.01J,m 4 0.7 1 I I -20 -10 0 7 2fJlOV I I I I 189 I 10 20 30 40 50 60 70 80 Figure 2.46. Normalized C-V characteristics of a p-type MOS capacitor with an adjacent n+ region as that shown in Fig. 2.44(c). Vg is the voltage applied to the gate with respect to the p-type substrate. A series ofC-V curves are shown for a range of VR: the reverse bias voltage applied to the n+/p junction. 2.3.6 When the surface is depleted, the gated diode behaves like an n+-p diode with depletion of the p-region extending to underneath the gate electrode. When the surface is inverted, the gated diode behaves like an n+-p diode with both the n+ region and depletion ofthe p-region extending to underneath the gate electrode. High-field effects in gated diodes are discussed in Section 2.5.5 For a p-type MOS capacitor, the effect of an adjacent reverse biased n+ region on the C-V characteristics is shown in Fig. 2.46. With increasing Vg, the surface potentiallfls also increases, as labeled under the curve. At VR = 0, the C-V curve resembles a regular low­ frequency C-V curve (curve (a) in Fig. 2.38) with inversion (sharp rise ofthe capacitance to Cox) taking place at Vg RJ 13 V where lfIs RJ 0.7 V (2lf1B)' Note that as VR increases, the onset of inversion shifts to increasingly more positive gate voltages as the MOS goes into deeper and deeper depletion (lower CmuJ. It can be seen that the value ofsurface potential at inversion increases by approximately VR, consistent with Eq. (2.217). The decrease of Cmin, the serial combination of Cox and Cd = esdWdm, with VR follows fromEq. (2.218). Charge in Silicon Dioxide and at the Silicon-Oxide Interface It is often said that the real in silicon technology lies not in the silicon crystalline material but in silicon dioxide. Silicon dioxide forms critical components of silicon devices, serves as insulation and passivation layers, and is often used as an effective masking and/or diffusion-barrier layer in device fabrication. Thus far we have treated silicon dioxide as an ideal insulator, with no space charge in or associated with it, and no charge exchange between it and the silicon it covers. The 2.3 MOS capacitors 99 K+ Na+ } Mobile ionic charge .,.- + + + + } Oxide trapped charge Si02 + + + + + Fixed ollide charge SiO. . _.)1. _.)1.- ,x· - ,)(,_.)(. -·K-·)(C-· )(C_.l« - 'oK- ,­ ' - - Interface trapped charge Si Figure 2.47. Charges and their location in thermally oxidized silicon. (After Deal, 1980.) silicon dioxide and the oxide-silicon interface in real devices are never completely electrically neutral. There can be mobile ionic charges, electrons, or holes trapped in the oxide layer. There can also be fabrication-process-induced fixed oxide charges near the oxide-silicon interface, and charges trapped at the so-called surface states at the oxide-silicon interface. Electrons and holes can make transitions from the crystalline states near the oxide-silicon interface to the surface states, and vice versa. Since every device has some regions that are covered by silicon dioxide, the electrical character­ istics ofa device are very sensitive to the density and properties ofthe charges inside its oxide regions and at its silicon-oxide interface. The nomenclature for describing the charges associated with the silicon dioxide in real devices was standardized in 1978 (Deal, 1980). The net charge per unit area is denoted by Q. Thus, Qm denotes the mobile per unit area, Qat denotes the oxide trapped charge per unit area, Qf denotes charge per unit area, and Qit denotes the interface trapped charge per unit area. The names and locations of these charges are illustrated in Fig. 2.47. The properties and characteristics of these charges are discussed further below. 2.3.6.1 Surface States and Interface Trapped Charge At the Si-Si02 interface, the lattice of bulk silicon and all the properties associated with its periodicity terminate. As a result, localized states with energy in the forbidden energy gap of silicon are introduced at or very near the Si-Si02 interface (Many et al., 1965). These localized surface states are illustrated schematically in Fig. 2.48. Interface trapped charges are electrons or holes trapped in these states. Just like impurity energy levels in bulk silicon discussed in Section 2.1.2, the prob­ ability of,occupation of a surface state by an electron or by a hole is determined by the surface-state energy relative to the Fermi leveL Thus, as the surface potential is changed, the energy level of a surface state, which is fixed relative to the energy-band edges at the surface, moves with it. This change relative to the Fermi level causes a change in the probability of occupation of the surface state by an electron. For instance, referring to Fig. 2.32, as the bands are bent downward, or as the surface potential is increased, 100 2 Basic Device Physics --_. Ec ".,- Surface states f-------E. Metal Si02 Silicon l ___ _ Agure 2.48. Schematic energy-band diagram of an MOS structure, illustrating the presence of surface states. more surfuce states move below the Fenni level and hence become occupied by elec­ trons. This change ofinterface trapped charge with a change in the surface potential gives rise to an additional silicon capacitance component, which will be discussed further in Section 2.3.7. Electrons in silicon but near an oxide--silicon interface can make transitions between the conduction-band states and the surfuce states. An electron in the conduction band can contribute readily to electrical conduction current, while an electron in a surface state, an interface trapped electron, does not contribute readily to electrical conduction current, except by hopping among the surface states or by first making a transition to the conduction band. Similarly, holes in silicon but near an oxide-silicon interface can make transitions between the valence-band states and the surface states, and trapped interface holes do not contribute readily to electrical conduction. By trapping electrons and holes, surface states can reduce the conduction current in MOSFETs. Furthermore, the trapped electrons and holes can act like charged scattering centers, located at the interface, for the mobile carriers in a surface channel, and thus lower their mobility (Sah et ai., 1972). Surfuce states can also act like localized generation-recombination centers. Depending on the surfuce potential, a surface state can first capture an electron from the conduction band, or a hole from the valence band. This captured electron can subsequently recombine with a hole from the valence band, or the captured hole can recombine with an electron from the conduction band. In this way, the surface state acts like a recombination center. Similarly, a surface state can act like a generation center by first emitting an electron followed by emitting a hole, or by first emitting a hole followed by emitting an electron. Thus, thc presence of surface states can lead to surface generation-recombination leakage currents. The density of surface states, and hence the density of interface traps, is a function of silicon substrate orientation and a strong function of the device fabrication process (EMIS, 1988; Razouk and Deal, 1979). In general, for a given device fabrication process, the dependence of the interface trap density on substrate orientation is (1 OO) < (11O) < (111). Also, a postmetallization or "final" anneal in hydrogen, or in a hydrogen-containing ambient, at temperatures around 400°C is quite effective in minimizing the density of interface traps. Consequently, (100) silicon and postmetallization anneal in hydrogen are commonly used in modern VLSI device fabrication. 2.3 MOS Capacitors 101 2.3.6.2 Fixed Oxide Charge Fixed oxide charges are positive cbarges located in the oxide layer very close to the Si-SiOz interface. In fact, for modeling purposes, the fixed oxide charges are usually assumed to be located at the Si-Si02 interface. They are primarily due to excess silicon species introduced during oxidation and during postoxidation heat treatment (Deal et at., 1967). The dependence of the density of fixed oxide charges on substrate orientation is the same as that of interface traps, namely (l00) < (llO) < The presence of fixed oxide charges at the oxide-silicon interface affects the potential in the silicon, which will be discussed in the next subsection. In addition, the fixed oxide charges act as charged scattering centers and thus reduce the mobility of the carriers in a surface inversion channel (Sah et al., 1972). 2.3.6.3 Mobile Ionic Charge Mobile ionic charges in 3i02 are usually due to sodium or potassium contamination introduced during device fabrication. Unlike fixed oxide charges, which are not mobile, Na+ and K+ ions are quite mobile in SiOz and can be moved from one end of the oxide layer to the other when an electric field is applied across the oxide layer, particularly at somewhat elevated temperatures (>200 0 (:) (Hillen and Verwey, 1986). As these posi­ tively charged ions drift close to the Si-3i02 interface, they repel holes from, and attract electrons to, the silicon surfuce, often causing unwanted surface electron current to flow among n+ diffusion regions in a p-type substrate or well. Also, when these positively charged ions come close to the silicon surface, they can act as charged scattering centers for the carriers in the surface inversion channel, thus reducing their mobility. In VLSI fabrication processes, mobile-ion contamination problems must be avoided. This is accomplished by a combination of proper passivation, usually using phospho­ silicate glass. and "clean" fabrication technology (Hillen and Verwey, 1986). 2.3.6.4 Oxide Trapped Charge If electron-hole pairs are generated in an oxide layer, e.g., by ionizing radiation, some ofthese electrons and holes can be subsequently trapped in the oxide. Also, if electrons or holes .are injected into an oxide layer, by tutmeling or by hot-carrier injection, some of them can be trapped in the oxide. Electron and hole traps in Si02 can easily be introduced by bombardment with high-energy photons or particles (Bourgoin, 1989). Since bombardment by high-energy particles and photons is involved in many steps in the fabrication of modem VLSI devices (during ion implantation, plasma or reactive-ion etching, sputtering deposition, electron-beam evaporation of metal, electron-beam and x-ray lithography, etc.), electron and hole traps are often introduced in the oxide during device fabrication. Fortunately, most ofthese traps can be eliminated with subsequent anneals at temperatures above 550°C (Ning, 1978). Also, depending on the oxidation condition, electron traps can be introduced during the oxide growth process itself (EMIS, 1988). For example, oxide growth in moisture­ containing ambient is known to introduce electron traps (Nicollian et al., 1971). 102 2 Basic Device Physics 2.3 MOS Capacitors 103 E<-TTll underestimate the amount aftraps in Si02, since the capture cross sections at such high oxide fields are much .~rnaner than those at normal device operation. 2.3.7 Effect of Interface Traps and Oxide Charge on Device Characteristics Figure 2.49. (a) (b) (c) The presence of oxide charges and interface traps has three major effects on the Schematics illustrating the potential wells of electron traps in silicon dioxide: (a) Coulomb-attractive trap, (b) neutral trap, and (c) Coulomb-repulsive trap. characteristics of devices. First, the charge in the oxide, or in the interface traps, interacts with the charge in the silicon near the surface and thus changes the silicon charge distribution and the surface potential. Second, as the density of interface trapped charge • Capture cross section. Traps are usually characterized by their capture cross sections. changes with changes in the surface potential, it gives rise to an additional capacitance Electron traps with cross sections in the range OflO- 14_1O-12 cm2 are usually Coulomb­ component in parallel with the silicon capacitance Csi discussed in Section 2.3.3. Third, attractive traps, i.e., the trap centers are positively charged prior to electron capture the interface traps can act as generation-recombination centers, or assist in the band-to­ (Ningetal., 1975; Lax, 1960). Electron traps with cross sections in the 1O-18_1O-14-cm2 band tunneling process, and thus contribute to the leakage current in a gated-diode range are usually due to neutral traps (Lax, 1960), and those with cross sections structure. These effects are discussed more quantitatively below. smaller than 10-18 cm2 are usually associated with Coulomb-repulsive traps, i.e., the trap centers are already negatively charged prior to electron capture (Balland and Barbottin, 1989). The potential wells representing these electron traps are illustrated in 2.49. Since the Coulomb-attractive and neutral centers have the largest capture cross sections, they are also the most important to include when considering the effects ofelectron traps on device characteristics. Hole traps have not been studied in as much detail as electron traps. This may be due to the fact that holes are very readily trapped when they are injected into an oxide layer (Goodman, 1966). This is consistent with the measured hole capture cross section ofabout 3 x 10-13 cm2, which is as large as the largest electron traps in Si02 (Ning, 1976a). • Temperature dependence. Consider the capture of a mobile electron into an electron trap. The trapping process has two competing components, namely, capturing the electron into some initial high-energy state of the trap center, and reemitting that same electron from the initial captured state by thennal excitation. Ifan electron in an initial captured state has a higher probability of cascading down towards the ground state of the trap center than of being reemitted, the electron becomes trapped. On the other hand, if the probability of reemission by thennal excitation from the initial captured state is high enough, trapping will not occur (Lax, 1960). The capture cross section, therefore, decreases with increasing temperature, since the probability for thermal reemission increases with temperature (Lax, 1960). 2.3.7.1 Effect of Oxide Charge on Surface Potential As discussed in Section 2.3 .2, the charge distribution in silicon is a function ofthe surface potential. Thus, the effect of oxide charge on the charge distribution in silicon can be described in terms of its effect on surface potential. In the case of an MOS structure, the effect ofoxide charge is usually described in tenns ofthe change in gate voltage, which is a readily measurable parameter, necessary to counter the effect of the oxide charge or to restore the surface potential to that of zero oxide charge. For simplicity of illustration, let us consider an MOS structure biased at flat-band condition. Let us assume that a sheet of oxide charge Q per unit area is placed at a distance x from the gate electrode, and a gate voltage (5Vg has been applied to restore the MOS structure to its original, i.e., flat-band, condition. With the surface potential restored to its original value, the sheet of oxide charge has induced no change in the charge distribution in the silicon, which is a function of the surface potential, but a charge of magnitude -Q per unit area on the gate electrode. This is illustrated in Fig. 2.50. Gauss's law in Eq. (2.43) implies that the electric field in the oxide between 0 and x due to the sheet ofoxide charge and its image charge on the gate electrode is -Q / Cox (see Exercise 2.5). This is also illustrated in Fig. 2.50. The potential difference supporting this electric field is -xQ / Cox, which is provided by the applied gate voltage. Therefore, • Fielddependence. If an electric field is applied across an oxide layer, it has the effect of increasing the energy of the carriers moving in the oxide layer. As these carriers gain liVg _ xQ Gox (2.219) energy from the oxide field, the probability oftheir being captured in some initial trap state is lowered, since the carriers now must lose more energy in the initial capture process. At the same time, an oxide field has the effect oflowering the energy barriers for the carriers trapped in a potential well, thus increasing the probability for reemitting them from their initial captured states (Lax, 1960). As a result, the capture cross section decreases with increasing oxide field (Ning, 1976b, 1978). The commonly used method of injecting carriers into SiOz by tunneling at high oxide fields tends to The gate voltage necessary to offset the effect of an aibitrary oxide charge distribution can be obtained by superposition of individual elements of the charge distribution and applying Eq. (2.219) to each element. For an oxide charge distribption of Pnet(x, VIs) = Pnet(x),+ Qi/(l/fs)6(x - tox ), which consists of an arbitrary distribution Pnet(x) that is independent of the surface potential and a delta-function distribution ofthe interface trap . charge Qit(lj/s) located at x tnx, the gate voltage necessary to offset it is 104 2 Basic Device Physics I PM/ex) Q Metal Oxide Silicon x 0 x tox II -Q 1!:(x) I 0 Ix .. x I -Qleox Figure 2.50. Schematic illustrating the effect of a sheet charge of areal density Qwithin the oxide layer of an MOS capacitor biased at flat-band condition. =-;- ~Vg ~Vg('I's) 1 XPnet(X, 'I'.)dx ox (2.220) eo.< XPnel(x)dx + Qil ('I's) tax). According to the charge nomenclature discussed in Subsection 2.3.6, Poel (x) includes the mobile charge, the oxide trapped charge, and the fixed oxide charge. It is a common practice to define an equivalent oxide charge per unit area, Qax> by Qox = Qox(lf/s) tx Pnel(X, 'l's)dx ox J= 'O' X -Pn el ( xl d x + Qit('I'.). o tox Equation (2.220) can then be rewritten in the simple form of (2.221) ~Vg('I's) = - Qo~('I's) , ox (2.222) where Cox = eox Itox is the oxide capacitance per unit area introduced in Eq. (2.195). Equation states that the effect ofan arbitrary oxide charge distribution is equivalent to an oxide sheet charge of areal density QoJ'I'.) located at the oxide-silicon interface. 2.3.7.2 Interface-Trap Capacitance In Section 2.3.3, the silicon part of the capacitance is defined without including any interface trapped charge. As the interface traps are filled and emptied in response to changes in the surface potential, they give rise to an interface-trap capacitance per unit area, Cit, defined by 2.3 MOS CapaCitors 105 dQit(",J ~ (2.223) Just as in Eq. (2.197), the - sign in Eq. (2.223) is inserted to ensure that the capacitance is always a positive quantity. In Eq. (2.223), we have indicated explicitly that the interface­ trap capacitance is a function of surface potential. To include the effect of Qox in the operation of an MOS capacitor, Eq. (2.195) should be modified by adding to its right-hand side a AVg term due to Qox. That is, Eq. (2.195) becomes Vg Vfb = ~Vg("'.) - + 'l's Qs(lf/s) + QoA'I's) + If/s' Cox (2.224) The total charge on the gate electrode is now Qs(I,II,) + Q"J'I's)' Equation (2.196) then becomes Cg = (2.225) and Eq. (2.198) becomes -I = -1+ Cg Cox C-si-+I Cit . (2.226) That is, the interface-trap capacitance is in parallel with the silicon capacitance. As discussed in the previous subsection, the probability of a surface state being filled with an electron is governed by its energy level relative to the Fermi level. Only those interface traps that can be filled and emptied at a rate faster than the capacitance­ measurement signal can contribute to Cit. Traps too slow to follow the capacitance­ measurement signal will not contribute to Cit. 2.3.7.3 C-VCurves as a MonitOring and Diagnostic Tool for Oxide and Interface Quality As discussed in Section 2.3.6, the amount ofoxide charge and surface states is a function of the silicon substrate orientation and a strong function ofthe device fabrication process. For modern MOS devices, by the time a device fabrication process is ready for manufacturing, the amount of oxide charge and surface states is usually quite low, with Q"x Iq typically about 1011 or less. For an MOS device having an oxide thickness of IOnm. the corresponding gate voltage shift according to Eq. (2.222) is only 46mY. At such low surface-state densities, the MOS C-V characteristics are quite ideal in that the measured C-V curves match well with the calculated ones (see ,Section 2.3.3 and Fig. 2.38). However, many experimental fabrication processes, particularly those involving energy plasma, reactive-ion etching, and electron or ion beams, can generate significant oxide charge and surface states in MOS devices. Unless these oxide damages can be removed by post-process thermal annealing, the amount of residual oxide charge and surface states can be appreciable. High-field stress of silicon MOS devices can also 106 2 Basic Device Physics >------ Theory Low frequency --:,::~~----' Expenment ___/ 0.9 ,,, / '' :~: 0.8 0.7 -,,t~ ~,.,i " ,,,,:--' , ,, -'' High frequency 0.6 LI-L_'-----L----'_--'-----'-_'-----L----'_--'-----'-_'---' -15 -10 -5 0 5 10 15 Gate voltage (V) figure 2.51. Comparison of experimental apd theoretical high-frequency and low-frequency C-V curves, showing typical distortion caused by intetface traps. The MOS capacitor has Na = 1016 em-3 and lox = 200 run. The symbols are explained in the text. (After Deal et al., 1969.) generate oxide charge and surface states. (High-field effects will be discussed in Section 2.5.) The presence of oxide charge and surface states can cause the measured C-V curve to appear distorted compared to the ideal C-V curve. There are two contribu­ tions to this distortion. First, Qit is a part of Qox which shifts the C-V curve along the gate voltage axis according to Eq. (2.224). The shift is distorted because Qit is a function of surface potential, which in tum is a function of gate voltage. Second, the additional capacitance due to the interface traps also distorts the measured C-V curve because Cit is a function of surface potential, which in tum is a function of gate voltage. If the amount of oxide charge and surface states is large, the distortions in the C-V curve can be quite prominent, as illustrated in Fig. 2.51 (Deal et at., 1969). The physical mechanisms responsible for the various distorted regions can be understood as follows. The distortion labeled A is where the MOS capacitor is normally in accumulation. In this gate voltage region, the valence-band edge at the silicon-oxide interface approaches or crosses the Fermi level (see 2.31). As a result, the interface states near the valence band become ionized and positively charged. (The interface states near the valence band are called donor states. They are neutral when they lie below the Fermi level and become positively charged by donating electrons when they lie above the Fermi level.) As the donor interface states become ionized, they contribute to a build up of positive interface trap charge which shifts the gate voltage in the negative direction according to (2.224). The distortion near the label B is related to interface states near the rnidgap, since it occurs at a gate voltage range where the MOS capacitor is between flatband and weak-inversion conditions (see Figs 2.31 and 2.38). The distortion labeled D is where the MOS capacitor is near weak inversion. To the right side of D, the capacitor is in inversion where the conduction-band at the silicon-oxide interface approaches or crosses the Fermi leveL In this gate voltage range, the interface states near the conduction band become ionized and nel!ativelv (The interface states near the conduction band are called acceptor above the Fermi level and become negatively charged lie below the Fermi level.) As the acceptor interface states ofne2:ative interface trap which shifts 2.3 MOS CapaCitors 107 ••••• _--\ AQ. \ 0.9 \_c,.._\'t 0.8 \\ \ \ After stres\s"'___ \ 0.7 "'.....,,\ -20 -15 -10 -5 o 5 10 Gale voltage (V) Figure 2.52. Typical high-frequency C-Vplot ofan MOS capacitor showing the distortion due to intetface traps. The MOS capacitor has Na = 1016 em-3 and tox 200 run. The oxide trapped charge and interface trapped charge are caused by subjecting the capacitor to a negative bias stress of2MV/crn at 400°C for 2 minutes. (After Deal etat., \967.) the gate voltage in the positive direction according to Eq. (2.224). This causes the low­ frequency C-V curve to shift to the right. The broadening ofthe C-V curve at its midpoint is labeled C. It is a result ofthe interface states near the conduction band (Deal et at., \969). Figure 2.52 illustrates the distortion of a typical high-frequency C-V curve of an MOS capacitor after tmpped has been created inside the oxide layer and at the oxide-silicon interface (Dea\ et at., 1967). (The creation of bulk oxide and interface traps by high electric fields will be discussed in Section 2.5.) The oxide trapped charge causes a parallel shift of the C-V curve (dotted line) to the left. The interface-trap capacitance causes the curve to be distorted and shifted to the left by an additional amount. The C-V distortions depicted in Figs 2.51 and 2.52 are for 200 nm thick oxides having significant oxide charge and surface states. It can be inferred from Eqs. (2.221) and (2.222) that the magnitude of the gate voltage shift caused by a certain areal density of interface states, Q;" is proportional to {ox. The voltage shift caused by a certain uniform volume density of oxide trapped charge, Pneh is proportional to t~x' Therefore, for the same Qit and Pne" the C-V curves of thinner oxide devices should appear less distorted~ There is a vast amount of published literature on the subject of interface states and the measurement of interface states. Interested readers are referred to the literature for a discussion on the characteristics of interface states in MOS capacitors (Deal et aI., 1969) and on the various techniques for measuring interface states (Schroder, 1990). 2.3.7.4 Surface Generation-Recombination Centers As discussed in the previous subsection, interface states can serve as gellenlticJll­ recombination centers. In the case of a gated-diode structure, the surface generation­ recombination current adds to the diode leakage current. The magnitude of the surface leakage current depends on whether or not the surface states are exposed, whether or not the silicon surface is depleted (Grove and Fitzgerald, \966). If the surface is inverted, the surface states are all filled. with minority carriers and do not function efficiently as generation centers. Similarly, if the surface is in accumulation, the surface states are all 108 2 Basic Device Physics filled with majority carriers and do not function efficiently as generation centers either. Only when the silicon surface is depleted will the surface statesfunction efficiently as generation centers. Thus, surface leakage current can be suppressed by biasing the gate to keep the silicon sutface either in inversion or in accumulation. The reader is referred to Appendix 5 for a detailed discussion ofthe physics involved in generation-recombination processes. As recombination centers, sutface states can degrade the minority-carrier lifetime of devices. Consequently, devices where long minority-carrier lifetimes are required are usually designed to confine the minority carriers in them away from the silicon surface. In addition, the device fabrication processes are usually optimized to minimize the of sutface states. 2.3.7.5 Surface-State or Trap-Asssisted Band-ta-Band Tunneling As will be discussed in Subsection 2.5.2, band-to-band tunneling occurs when the electric field across a p-n junction is sufficiently large. For a gated diode, or for a p-n diode with silicon sutface components, the presence of surface states or intetface traps in the high-field region can enhance the band-to-band tunneling current very significantly. Thus, gate-induced drain leakage currents in MOSFETs, which will be discussed in Section 2.5.5, and emitter-base diode tunneling currents in bipolar transistors, which will be discussed in Section 6.3.4, depend strongly on the density of intetface states at the oxide-silicon intetface of these devices. 2.4 2.4.1 Metal-Silicon Contacts The metal-semiconductor contact is a critically important element in all semiconductor devices and technology, As a eontact to a silicon device terminal, a metal-silicon contact should be non-rectifYing and have a small contact resistance in order to minimize the voltage drop across the contact Such contacts are usually referred to as ohmic contacts. In general, a metal-semiconductor contact has rectifying current-voltage characteristics similar to those of a p-n diode (see Section 2.2). Rectifying metal-semiconductor devices are called Schottky diodes or Schottky barrier diodes. Here we discuss the basic physics and operation of a metal-silicon contact, focusing on its current-voltage characteristics as a Schottky diode and as an ohmic contact. A brief discussion of Schottky diodes as active devices is also given. Static Characteristics of a Schottky Barrier Diode The static characteristics of a Schottky barrier diode can be inferred from those of an MOS capacitor (see Section 2.3) by letting the oxide layer thickness go to zero. Just as the sutface potential of the semiconductor in an MOS capacitor is affected by the interface trapped charge, the sutface potential of the semiconductor in a Schottky barrier diode is affected by the electron occupation of the sutface states on the semiconductor sutface. Therefore, the characteristics of a Schottky barrier diode depend on the properties of the metal and the properties of the semiconductor and its surface states. Here we first discuss 2.4 Metal-8i1icon Contacts 109 (a) Free electron (b) level -----r--c-r~· qm Ef Metal I ...... Silicon (n-type) (b) ____ ~_hy~~c~.~7 f r ······"j"l-------r qm ! qX q, --..1-- __q,p, Ef Ev Metal I .......... Ev Silicon (n-type) (c) Contact gap (d) Ef Ef@?W~ ............ Ev Metal I I Silicon (n-type) ............ Ey Metal I Silicon (n-type) Figure 2.54. Energy-band diagram ofa metal-silicon system where the silicon is assumed to have a large density of surface states. (a) When the metal and the silicon are not electrically connected as one system. Some of the interface states are filled with electrons, causing the bands to bend upward. (b) When the metal and the silicon are electrically connected to form one system, but the metal is physically separate from the silicon surface by a gap space. (c) When the metal is in contact with the silicon to form a Schottky diode. A contact gap of atomic dimension is shown. The contact-gap region is discussed in the text. (d) A simplified diagram where the contact gap is omitted. per unit area in the surface states is Qit, then overall charge neutrality of the metal-silicon system requires that QM = - (Qit + Qd). As the gap between the metal surface and the silicon surface is reduced, the electric field in the gap increases, and hence the magnitude of QM increases, requiring the magnitude of (Qit + Qd) to increase. In other words, a change in QM can cause a change in Qit andlor Qd. The Bardeen model (Bardeen, 1947) for the roles played by surface states provides a physical picture for explaining how the charges QM, Qit and Qd may change together. According to the Bardeen model, the charges involved in the charge-transfer process in the formation of a metal-semiconductor contact come from four double layers. (A double layer consists of a layer of positive charge and a layer of negative charge of the same magnitude.) These layers are: (i) a double layer of atomic dimensions at the metal 112 2 Basic Device PfIysics surface, (ii) a double layer of atomic dimensions at the semiconductor surface, ~lll) a double layer formed from the surface charges on the metal and semiconductor, both of atomic dimensions, and (iv) a double layer formed from a surface charge of atomic dimensions on the semiconductor surface and a depletion charge layer in the semi­ conductor. According to this model, QM has contributions from double layers (i) and (iii); Qit has contributions from double layers (ii), (iii) and (iv); Qd has contribution from double layer (iv). Bardeen showed that the strength of double layer (iii) is small for semiconductors where the density of surface states is small (less than about 1013 cm-2), and a change in QM is balanced by charge transfer primarily among double layers (ii) and (iv). In this case, as the physical gap in Fig. 2.54(b) is reduced, the change in QM is balanced primarily by a change in Qd, with little change in Qu. For semiconductors with suffi­ ciently high (greater than 1013 cm-2) density ofsurface states, double layer (iii) can be the primary source for any change in QM' In this case, as the physical gap in Fig. 2.54(b) is reduced, the change in QM is balanced primarily by a change in Qi" with little change in Qd' When there is little change in Qd, there is little change in the surface potential which in tum implies littlc change in the energy-band edges at the semiconductor surface relative to the Fermi level. The Fermi level at the semiconductor surface is said to be more or less pinned by the high density of surface states. When the metal makes contact with the silicon to form a Schottky diode, the energy­ band diagram is as illustrated in Fig. 2.54(c). Note that a contact gap is shown to represent the region containing the double layers (i), (ii) and (iii) in the Bardeen model. The width of the contact gap is of atomic dimensions, at least for good contacts where there is no unintended interfacial material. The contact gap is assumed to be sufficiently thin to play no role in the transport ofelectrons between the metal and the silicon. Notice that, just as in 2.54(b), the potential difference across this infinitesimal contact gap is equal to (rpm X + lfIs Eg /2q + lfI0)' In Fig. 2.54(b), before the Schottky diode is formed, the surface potential lfIs depends on the physical gap space. If there is weak Fermi-level lfIs changes with the physical gap space. If there is strong Fermi-level pinning, lfIs is relatively insensitive to the physical gap space. In Fig. 2.54(c), we have 1fI. "" -lfIbi> where IfIM is the built-in potential of the Schottky barrier diode. The electron energy barrier is qrpBn. (The contact gap is transparent to electron transport between the metal and the silicon.) Since the contact gap in a good metal-semiconductor contact is assumed to be transparent to electron transport between the metal and the semiconductor, we can omit it from the energy-band diagram completely for purposes of modeling device characte­ ristics of a Schottky diode. (As discussed in the paragraph below, we should do this with care.) The simpl{fied energy-band diagram for a Schottky diode is as illustrated In It should be noted that Fig. 2.54(c) suggests that ¢Bn 1- sp is related to the electron energy barrier qsn qen + qBp = Eg) where Eg is the energy gap ofthe semiconductor. We will focus our discussion on metal contacts to n-type silicon where the barrier height is q Bn' Metal contacts to p-type silicon where the barrier height is q Sp will not be discussed explicitly. 2.4.1.4 Effect of Electric Field on Barrier Height In Appendix 7, it is shown that the image-force effect causes the energy barrier for electron transport across a metal-silicon interface to be lowered by qt. R;: (2.232) where is the maximwn electric field in the silicon. The actual energy barrier for electron transport in a Schottky barrier diode is therefore (qBn qt.). The total band bending in the silicon is q(lf'bi - Vopp), where Vapp is the forward-bias voltage across the Schottky diode (see Fig. 2.55), and Eq. (2.184) gives sqrt[2qNd (Wbf )lesi 1for n-type silicon with a uniform doping concentration of Nd• That is, the effective energy barrier ofa Schottky barrier is smaller than that and 2.54. A forward 2.4 Metal-silicon Contacts 115 bias (v"pp > 0) across a diode reduces the electric field and hence increases the effective energy barrier, while a reverse bias Wapp < 0) increases the electric field and hence reduces the effective energy barrier. . 2.4.2 Current Transport in a Schottky Barrier Diode Consider an n-type silicon Schottky barrier diode. The energy-band diagrams illustrating the flow of electrons across the interface are shown schematically in Fig. 2.55. In modeling the transport ofan electron across the interface, we need to consider the kinetic energy ofthe electron relative to the energy barrier for current flow across the interface, as in the energy-band diagrams. For example, for an electron in the metal having an energy E = Efi it sees an energy barrier of qBn (barrier-lowering effect is ignored for simplicity of discussion). For an electron having an energy E = EI + t.E it sees an energy barrier ofqBn !:.E. Similarly, for an electron in the quasineutral silicon region having an energy of E Ee, it sees an energy barrier of q(lf'bi v"pp). For an electron having an energy !:.E above the conduction-band edge, its barrier for transport across the interface is q(lf'bi - v"pp) - !:.E. These energy barriers for current flow should not be confused with the energy barrier ofthe Schottky diode itself, which is At thermal equilibrium, there is no net electron flow in either direction in the dloae, as indicated in Fig. 2.55(a). Ifa forward voltage v"pp is applied to the diode, there will be a net electron flow from the n-silicon to the metal, but there are no holes (minority carriers) flowing into the n-silicon, as indicated in Fig. 2.55(b). Similarly, for a forward-biased p-type silicon Schottky barrier diode, there is a net flow of holes from the p-silicon into the metal, which is equivalent to a net flow of electrons from the metal into the valence band of the p-silicon. There are no excess electrons (minority carriers) injected from the metal into the conduction band of the p-silicon. That is, the current transport in a S<;hottky barrier diode is mainly due to majority carriers. This should be contrasted with a p-n diode where current transport is mainly due to minority carriers (electrons injected into the conduction band of the p-side and holes injected into the valence band of the n-side). The switching speed ofa p-n diode is limited by the time it takes to discharge the minority carriers stored in the diode during forward bias (see Section 2.2.5.3). Therefore, without minority-carrier storage, a Schottky barrier diode is inherently faster than a p-n diode. 2.4.3 Current-Voltage Characteristics of a Schottky Barrier Diode The processes by which electrons are transported from one side to the other in a Schottkv barrier diode are illustrated in Fig. 2.56. Thermionic emission refers to the electrons sufficient energy to surmount the effective (image-force effect included) energy barrier. Field emission refers to the tunneling of electrons from around the conduction-band Thermionic-field emission describes the tunneling of. electrons having energy above the conduction band but not enough energy to surmotmt the; barrier. For a diode designed to function as an active device or a circuit component, the doping concentration is usually sufficiently light, and therefore the depletion layer thickness sufficiently large, so that thermionic emission is the dominant process for electron transport. Field emission and 116 2 Basic Device Physics .-, . Thennionic emission Thennionic field emission Field emission E1 , ___________..--- Ec ....... Ev Metal I Silicon (n-type) Figure 2.56. Schematic energy-band diagram of a Schottky barrier diode illustrating the principal transport processes_ thermionic-field emission are important transport processes in metal-semiconductor contacts where the doping levels are high (e.g., in ohmic contacts, which will be discussed later). 2.4.3.1 Thermionic Emission In thermionic emission, the simplest theory is to treat the electrons as an ideal gas that follows Boltzmann statistics in energy distribution. Electron collision within the semi­ conductor depletion region is ignored, and only those electrons traveling in the direction of emission and having sufficient energy to sunnount the barrier are emitted. In the case of a multi-valley semiconductor having anisotropic effective electron masses like silicon, we should consider the emission current from each valley and then sum the currents to obtain the total current. The conduction band of silicon has six identical valleys located on the kx -, ky-, and kz- axes. Each vaHey is an ellipsoid, with a longitudinal mass of m, = 0.92 mo and a transverse mass of m,=0.19mo, where mo is the free-electron mass. The thermionic electron emission current density from an arbitrarily oriented silicon surface has been derived by Crowell (1965, 1969). The derivation is simplest for <100> silicon. Since <100> is the most commonly used silicon orientation, we shall only consider this orientation here. The reader interested in other orientations is referred to the paper by Crowell (1965). Since electron collision within the depletion region is ignored, we can consider the thermionic emission current to be due 10 electrons originating from the quasi neutral silicon region having sufficient energy to surmount the energy barrier for emission. As discussed in Section 2.1_1.2, the number of electronic states per unit volume having momenta between Px and Px + dpx, between py and py + dp)" and between pz and pz + dpz in one of the conduction-band valleys is 2 N(p"Py, pz}dPxdpydp: = dp,dpydp:. (2.233) 2.4 Metal-5i1icon Contacts 117 Note that the factor g denoting the number of equivalent minima in the conduction band is unity in Eq. (2.233) because_only. o.ne valley is being considered. The kinetic energy of an electron in the quasineutral region is E - Ee, and the relationship betweep kinetic energy and momenta is given by Eq. (2.2). In terms of Boltzmann statistics, the prob­ ability that an electronic state at energy E is occupied by an electron is exp[-(E - Ej) I kTJ [see Eq. (2.5)J. Therefore, Eq. (2.233) gives the number of electrons per unit volume having momenta betweenPx andPx + dpx) between py and py + dpy. and between pz and pz + dpz in one of the conduction-band valleys as dn(px,py,P:) -_ h23 e--(E-E.r)/kTdPxdpydp: - !e-(E'-Er)/kTe-(p~/2m,kT+i';J2m.kT+p~/2m'kT)dn dn din - h3 ,'X Y)' Y:' (2.234.) The number of electrons per unit volume having momenta between Px and Px + dpx is given by integrating Eq. (2.234) over all values ofPy and Pz. That is, Joo J"" ~ dn(px) e-(E,-Er)/kTe-p;/2m,kTdp, e-iy/2m,kTdpy e-p;/2m,kTdp. -00 -00 = 4~ nkTe-(E.-Er)/kTe-p~/2m,kTd'P . ~ x (2.235) • Ignoring Barrier Lowering Effect. In this case, when a voltage Vapp is applied to a Schottky diode, the minimum energy an electron traveling perpendicularly to the emission surfuce must have in order to surmount the emission barrier is q('fib! ­ v"pp). For <100> silicon, the emission surface is perpendicular to the kx-axis. The current density due to thermionic emission of electrons from a single conduction-band valley into the metal is J'c hs-m(Vapp) q v.,dn(p\) Pr=Prli 4~"y-h'-m'-y3-mqt r r .k".T1 'e- ( E• .-Er)lkTjOC p silicon, the two valleys on the kx-axis have my mz = m .and the four valleys on the ky- and kz-axes have my m, and mz = m" The total thenn"ionic electron emission current density from silicon into metal is In-Si< 6 = LJI,n-Sir'~m( 1 = A ( -2m-l mo + T 2e-q re-q,pBn/kTeqVapp/kT ) (2.239) where A*1/-S/< 100> A (2- m, + -4y'-ml-ml) = 2.0SA mO mO (2.240) is the Richardson constant for n-type <100> silicon. For silicon, the orientation dependence is relatively weak. For n-type silicon, the Richardson's constant is 2.15A (Crowell, 1965). In theory, the measured Richardson's constant contains information about the effective mass tensor of the semiconductor. However, the simple thermionic emission model gives only a qualitative description of experimentally measured currents in a typical Schottky barrier diode. The measured Richardson's constant should not be used to infer information about the effective mass tensor (Crowell, 1969). In practice, the Richardson's constant is often treated as an adjustable parameter for fitting experimental data (Henisch, 1984). At zero applied bias, the electron emission current from the metal into the silicon is equal in magnitude but opposite in direction to the electron emission current from the silicon into the metal. That is, JI1 -SI < = 0) -J1/-SI< 100>,Hm( Vapp 0), 100> (2.241) When the barrier lower effect is ignored, the energy barrier for electron emission fl'om metal into silicon is independent of V"pp" Therefore, we expect the electron emission current from metal into silicon to be independent of J!.,pp when barrier lowering effect is ignored. The total thermionic emission current density for an n-type <100> silicon Schottky barrier diode, when barrier lower effect is ignored, is therefore 2.4 Metai-Silicon Contacts 119 + Jthermlonic,n-Si< 100> (Vapp) = I n-8i< loo>,s_m(Vupp) In-si < lOO>,m~s(Vupp) A* ' . 1) n-8, T2e-Q 0), the current is dominated by the emission from the semiconductor into the metal. For a reverse-biased diode (Vapp < 0), the current is dominated by the emission from the metal into the semiconductor. Equation (2.242) shows that, when barrier lowering effect is ignored, a Schottky barrier diode has 1- V characteristics similar to those of a p-n diode [cf. Eq. (2.102)], with an exp(q J!.,p,Jk1) dependence on Vopp in forward bias, and a saturation current that is independent of V"pp in reverse bias. • Including Barrier Lowering Effect. There is a subtle difference between a Schottky diode and a p-n diode when barrier lowering effect is included When barrier lowering effect is included, the Schottky barrier qtPBn in Fig. 2.55 and in Eqs. (2.237) to (2.242) should be replaced by an effective Schottky barrier q(tPan - I1tP). The barrier-lowering term q I1tP depends on the applied voltage through the electric field ifm [see Eq. (2.232)]. As'discussed in Section 2.4.1.4, a forward bias (J!.,pp > 0) reduces ql1tP and hence increases the effective Schottky barrier, while a reverse bias (J!.,pp < 0) increases ql1tP and hence reduces the effective Schottky barrier. Thus, replacing q¢Bn by q(¢Bn -11¢) in Eq. (2.242) suggests that the forward-bias current ofa Schottky diode increases with v"pp at a rate somewhat slower than exp(q v"pJk1). This should be compared with the forward-bias current of a p-n diode which is proportional to exp(qVupplk1) [see (2.123)]. See also Fig. 2.23. In the literature, more complex theories have been proposed for describing the trans­ port process in Schottky diodes. There is a diffusion emission theory which includes the effect of electron collisions within the semiconductor depletion region. There is also a theory which combines the physics involved in the simple thermionic emission process and the diffusion emission process (Crowell and Sze, 1966a). All theories result in an equation similar to Eq. (2.242), with the difference only in the pre-exponential factor. The interested reader is referred to the literature for the details (Sze, 1981; Henisch, 1984). From a device point ofview, the important I-Vcharacteristics of a Schottky barrier diode are contained in the exponential factors in Eq. (2.242), namely in the exp(-q¢B"Ik1) dependence on q¢Bn and the [exp(qVapplk1) I] dependence on qv"pp. 2.4.3.2 Field Emission and Thermionic~field Emission If the semiconductor is heavily doped, the depletion region thickness will be thin, and the electron transport can become dominated by a combination of field emission and thermionic-field emission. In this case, large currents can flow even at low applied biases. In general, when field emission and thermionic-field emission dominate the electron transport, a metal-semiconductor contact is no longer useful as a rectifYing diode. As a result, we will not consider the general theory of field emission and thermionic-field emission any further. The interested reader is referred to the literature for details (Padovani and Stratton, 1966; Crowell and Rideout, 1969). 120 2 Basic Device Physics -r E --r­ jq1/Jm I-#«)Y-I E ,,& ~. ~ ,""u_-;~-w)UT-U--- x ~Ef Silicon 1---;::;:;­ Figure 2.57. Schematic showing the energy bands appropriate for considering field emission in a metal-silicon contact. As illustrated, the Schottky diode is forward biased, as indicated by the Fermi level in the silicon being higher than that in the metal. 2.4.3.3 Schottky Barrier Diode as an Active Device A rectifYing Schottky bamer diode has /-V characteristics similar to those ofa p-n diode, but a Schottky barrier diode is a much faster device than a p-n diode because it is a majority-carner device. As a result, Schottky barrier diodes are often used as microwave diodes and as gates ofmicrowave transistors where speed is important (see e.g., Irvin and Vanderwal, 1969). Also, Schottky barrier diodes are often added to bioolar circuits as voltage clamps to improve circuit speed. 2.4.4 Ohmic Contacts Ohmic contacts are usually made with metal or metal silicide in contact with doped semiconductor. The electron transport process in this case is dominated emission. Let us first consider the tunneling of a conduction-band electron from the quasineutral semiconductor region into the metal. The band bending near the metal­ semiconductor contact is illustrated in Fig. 2.57. The total band bending is qV'm = q(V'hi Vapp) when a forward bias of Vapp is applied. For a given V"",p, let us assume the conduction-band starts to bend upward at x 0, and the interface is located at x Wd, where Wd is the depletion-layer thickness. Since we are considering an electron in the conduction band, it is convenient to use the conduction-band edge of the quasineutral silicon region Ec{x < 0) as the energy reference, as indicated in Fig. 2.57. II/(X) is the electrostatic potential at location x relative to E,.{x < 0), i.e., -q!p(O) Ec(x < 0), and is thc potential energy ofan electron at location x. The Poisson equation [Eq. (2.44)1 can be integrated twice to give qNdx2 I/f(X ) 2cs; q (2.243) where is semiconductor doping concentration. From Eq. (2.188), we have 2.4 Metal-Silicon Contacts 121 (2.244) In the WK.B approximation for tunneling through an energy barner, the transmission coefficient through the energy barrier represented by -qV'(x) for an electron with energy E is [-4nJW exp I I x, d ~J-qV'(x) - Edx] W -4nI =exp - ,' ~Jq-2N-dX+ 2 [ h Xi 2os; <0) EdX]' (2.245) where the lower integration limit XI is given by -q!p(xl) E. In considering an ohmic contact, we are interested in the current due to electrons tunneling from the quasineutral region of the silicon through the potential barrier into the metal at small applied voltages. These electrons have only thermal energy (kT ~ 26 meV at room temperature) which is small compared to the maximum tunneling bamer height q(l/fbi - which is approximately equal to qV'bi at small Therefore, we can assume the tunneling electrons to have an energy E ~ Ec(x < 0). For these electrons, the tunneling process starts at x I = 0 and the corresponding transmission coefficient is where = Ec(x< 106 4.0 x 105 < 't < 6.0 x \05 7.03 x 105 1.231 x 106 6.71 x 105 1.693 >< 106 Grant 2.0 x \05 < j:!" < 2.4 x 105 2.6 x 106 1.43 x 106 2.0 x \06 1.97 x 106 2.4 >< 105 < '1< 5.3 x 105 6.2 x 105 1.08 x 106 2.0 x 106 1.97 )( 5.3 x 105<';t' 5.0)( 105 0.99 x 106 5.6 x 105 1.32 x 106 lE+6 lE+5 .!:l i"l c: lE+3 .'0" .§ Holes .9 1E+2 lE+l lE-6 2E-6 3E-6 l/~ (cm/V) 4E-6 5E-6 Figure 2.59. Impact-ionization mtes in silicon. The solid curves are data ofGrant (1973), and the dash curves are data of van Overstraeten and de Man (1970). 2.5.2 electrons. Second, the impact ionization rates increase very rapidly with electric field. For the depletion region of a p-n diode where the electric field is not constant, it is the small region surrounding the maximum-field point that contributes the most to the impact­ ionization currents. Thus, to minimize impact ionization in a p-n diode, the maximum electric field should be minimized. As mentioned in Section 2.2.2.4, doping-profile grading, or using lightly doped regions or i-layers, can effectively reduce the peak electric field in a p-n junction. Impact ionization rates decrease as temperature increases {Grant, 1973}. This is due to the increased lattice scattering at higher temperatures. The data in Table 2.2 and Fig. 2.59 are for room temperature. Band-to-Band Tunneling When the electric field across a reverse-biased p-n junction approaches 106 significant current flow can occur due to tunneling of electrons from the valence band 126 2 Basic Device Physics Tunneling distance E c - - - ..... E ____ Uu'-­ v p-region .... Ev n-region Rgure2.60. Schematic illustrating band-to-band tunneling in a p-n junction. of the p-region into the conduction band ofthe n-region. This phenomenon is illustrated schematically in Fig. 2.60. In silicon this tunneling process usually involves the emission or absorption of phonons (Kane, 1961; Chynoweth et al., 1960), and the tunneling current density is given by (Fair and v!fmiq3 '$VR exp Jb-b -- 4n:3Ji2EgIn 4v2m*e:12 ) 3q'$Ji (2.259) where '$ is the electric field, Eg is the energy bandgap, and VR is the reverse bias across the junction. An upper-bound estimate of the peak. electric field can be made assuming a one-sided junction. In this case, the analyses in Section 2.2.2 the upperbound for the electric field as ltmax = 2qNa(VR + /fbi) esi (2.260) where Na is the doping concentration of the lightly doped side (assumed p-type) of the diode and /fbi is the built-in potential of the diode. With these approximations, the band­ to-band tunneling current density is about 1 AJcm2 for Na 5 x 1018 and VR 1 V (Taur et al., 1995a). More recently, Solomon et al. (2004) showed that band-to-band tunneling current can be modeled using the concept of an effective tunneling distance. In this model, the tunneling current is assumed to be proportional to exp(- wrlAr), where Wr is the tunneling distance, illustrated schematically in Fig. 2.60, and Ar is an effective tunneling decay length. The reader is referred to Solomon's paper for the details. As will be discussed in Chapters 4 and 7, in scaling down the dimensions of a transistor, the doping concentrations increase and the junction doping profiles become more abrupt, and hence band-to-band tunneling effect increases. Once the leakage current due to band-to-band tunneling is appreciable, it increases very rapidly with electric field or reduction of the tunneling distance. For modem VLSI devices, band­ to-band tunneling is becoming one of the most important leakage-current components, for applications such as DRAM and battery-operated systems where leakage currents must be kent extremelv low. 2.5 High-Freid Effects 127 2.5.3 Tunneling into and through Silicon Dioxide Consider an MOS capacitor discussed in Section 2.3. For simplicity, the gate electrode is assumed to be heavily doped n-type polysilicon. When biased at the flatband condi­ tion, the energy-band diagram is as shown in Fig. 2.61(a), where q4Jox denotes the Si-Si02 interface energy barrier for electrons which, as indicated in Fig. 2.29, is about 3.1 eV. When a large positive bias is applied to the gate electrode, electrons in the strongly inverted surface can tunnel through the oxide layer and hence give rise to a gate current. Similarly, if a large negative voltage is applied to the gate electrode, electrons from the n+ polysilicon can tunnel through the oxide layer, and again give rise to a gate current. 2.5.3.1 Fowler-Nordheim Tunneling Fowler-Nordheim tunneling occurs when electrons tunnel into the conduction band of the oxide layer and then drift through the oxide layer. Figure 2.61(b) illustrates Fowler-Nordheim tunneling of electrons from the silicon surface inversion layer. The (a) ~_~_hh :: :: n+ silicon I '_~i~ P silicon L E v ( S i Oz) (b) I _ . _ _ Ec Ey Ec=;~ Ey (c) Ec = E,. ,....-Ec E.. Figure 2.61. Tunneling effects in an MOS capacitor structure: (a) energy-band diagram of an n-type polysilicon­ gate MOS structure at flat band; (b) Fowler-Nordheim tunneling; (c) direct tunneling. 128 2 Basic Device Physics of Fowler-Nordheim tunneling is rather complicated (Good Jr. and Muller, 1956). For the simple case, where the effects of finite temperature and image­ force barrier lowering (which is discussed in Appendix 7) are ignored, the tunneling current density is by (Lenzlinger and q2"<,-t2ox exp ( _ hN = 16n2ntPox where is the electric field in the oxide. Equation (2.261) shows that Fowler-Nordheim (J tunneling current is characterized by a straight line in a plot oflog I$'~x) versus 1/'fox. As discussed later in Section 2.5.3.3, electrons tunneling into an oXIde layer can be trapped in an oxide layer. If the tunneling current is measured at a constant voltage, then the trapped electrons in tum can cause the observed tunneling current to decrease with time. Depending on the thickness of the oxide layer and its formation process, this decrease in tunneling current can go on for some time before it reaches a more-or-Iess steady state. The tunneling currents reported in the classic paper by Lenzlinger and Snow were taken after the samples were first subjected to a current density ofabout 10-10 AJcm2 for two hours, during which time the tunneling currents decreased by about one order of magnitude from their initial values (Lenzlinger and Snow, 1969). At an oxide field of 8 MV/cm, the measured steady-state Fowler-Nordheim tunneling current density is about 5 x 10-7 A/cm2. The initial tunneling current is about ten times larger. For normal device operation, Fowler-Nordheim tunneling current is negligible. The characteristics of the tunneling currents represented by Eqs. (2.259) and (2.261) are determined primarily by their exponential factors. It should be noted that the exponents ofthe two equations are basically the same. The Fowler-Nordheim tunneling is through a triangular barrier ofheight qtPox, slope q$'oxand tunneling distance tPoxI 'tox' It is left as an exercise (Exercise 2.2 J) for the reader to show that the band-to-band tunneling exponent in Eq. (2.259) can be derived from the WKB approximation, i.e., for tunneling through a triangular barrier of height Eg, slope and tunneling distance 2.5.3.2 Direct Tunneling If the oxide layer is very thin, say 4 nm or less, then, instead of tunneling into the conduction band of the Si02 layer, electrons from the inverted silicon surface can tunnel directly through the forbidden energy gap of the Si02 layer. This is illustrated in Fig. 2.61(c). The theory of direct tunneling is even more complicated than that of Fowler-Nordheim tunneling, and there is no simple dependence of the tunneling current density on voltage or electric field (Chang et al., 1967; Scheugraf et al., J992). Direct-tunneling current can be very large for thin oxide layers. Figure 2.62 of the measured and simulated thin-oxide tunneling current versus voltage in vSilicon-gate MOSFETs et al., 1997). For the gate-voltage range shown in 2.62, the current is primarily a direct-tunneling current. Direct-tunneling current is important in MOSFETs of very small dimensions, where the gate oxide layers can approach 1nm in thickness. 2.5 High-Field Effects 129 IE+6 lE+5 lE+4 IE+3 IE+2 '" IE+I .~ lE+O -d8 lE-1 ;:: lE-2 ~ lE-3 o~ lE--4 lE-5 IE-{; :~t~~·~~~ o 1 Gate voltage (V) Figure 2.62. Measured (dots) and simulated (solid lines) tunneling currents in thin-oxide polysilicon-gate devices. The dashed line indicates a tunneling-current level of 1Ncm2• (After Lo et aI., 1997.) 2.5.3.3 Defect Generation Caused By Tunneling Current The tunneling of electrons into and through a silicon dioxide layer can cause "defects" to be generated within the oxide layer andlor at the oxide-silicon interface. These defects can take the form of electron traps, hole traps, trapped electrons, trapped holes, or interface states (DiStefano and Shatzkes, 1974; Harari, 1978; Chen et ai., 1986; DiMaria et ai., 1993). These defects govern the time dependent behavior ofthe tunneling current and play an important role in the wear-out and eventual breakdown of the oxide layer. In this subsection, we briefly discuss how these defects can influence the tunneling process. The reader is referred to the vast literature on the sublect for more details (DiMaria and Cartier, 1995, and Suehle, 2002, and the references • Tunneling into an electron trap. As electrons tunnel into an oxide layer, some of the electrons can get trapped. The trapped electrons modify the oxide field such that the field near the cathode (the electrode that acts as an electron source) is decreased, while the field near the anode (the electrode that acts as an electron sink) is increased. This is illustrated in 2.63. The reduced field near the cathode, in tum, causes the tunneling current to decrease. In a constant-voltage tunneling current measurement, electron is what causes the current to decrease with time. In a ramped-voltage (voltage increasil1lg with time at a constant rate) tunneling current measurement, electron trapping often leads to a hysteresis in the voltal!e--GUJrrellt • Hole generation, injection, and trapping. As an electron travels in the conduction band of an oxide layer, it gains energy from the oxide field. If the voltage drop across the oxide layer is larger than the bandgap energy of silicon dioxide, whic~, as indicated in Fig. 2.28, is about 9 eV, the electron can gain sufficient energy to cause impact ionization in the oxide. The holes generated by impact ionization can be trapped in the oxide. Holes can be injected indirectly into the oxide layer during electron tunneling as well. A tunneling electron arriving at the anode can cause impact 130 2 Basic Device Physics 2.5 High-Field Effects 131 • - - Ee - - Ev Ee E. Anode Cathode """--Before electron trapping Figure 2.63. Schematic illustrating the trapping of tunneling electrons. As electrons are trapped, the oxide field near the cathode (electron source) is decreased, while the oxide field near the anode (electron sink) is increased. 2.5.3.4 ionization in the anode near the oxide-anode interface. Depending on the energy ofthe tunneling electron, the hole thus generated can be from deep down in the valence band of the anode, and thus can be "hot." A hot hole in the anode near the anode-oxide interface can be injected into the oxide layer. This process is illustrated in Fig. 2.64. The injected hole can be trapped in the oxide layer as it travels towards the cathode. The trapped holes in the oxide layer cause the oxide field near the cathode to increase, which in turn causes the tunneling current to increase. This is illustrated in Fig. 2.65. Thus the trapping of holes provides a positive feedback to the electron tunneling process. In a constant-voltage tunneling current measurement, hole trapping is the primary reason the current increases with time. • Trap and interface-state generation. Traps can also be generated in the silicon dioxide layer and at the oxide-silicon interface by the electron current (Harari, 1978; DiMaria, 1987; Hsu and Ning, 1991). In addition to increasing electron and hole trapping, these traps can enhance the tunneling current by assisting in the tunneling process, as discussed in the two subsections below. Bulk-Trap-Assisted Tunneling Instead of tunneling directly through an oxide layer, an electron can first tunnel from the cathode into an electron trap in the oxide and then tunnel from the trap to the anode. Thus, traps in the oxide layer can act as stepping stones for the tumieling electrons. This is illustrated in Fig. 2.66. The enhanced tunneling current in turn can increase the genera­ tion of traps in the oxide. Thus, trap-assisted tunneling plays an important role in the degradation of an oxide under voltage stress because of the positive feedback between trap-generation and trap-assisted tunneling (DiMaria and Cartier, 1995). ...... ...)- * .... - .. ;-' Ee E. Anode - Ee ~- E" Cathode Figure 2.64. Schematic illustrating the generation of an electron-hole pair in the anode by a tunneling electron, The hole thus generated can then be injected (by tunneling in this example) into the oxide layer. After hole trapping // E. E. :rCMhOO. + + + Ee E. Anode figure 2.65. Schematic showing the trapping of holes in the oxide layer. The trapped holes enhance the electric field near the cathode, and decrease the electric field near the anode. 2.5.3.5 lnterface-Trap-Assisted Tunneling at Low Voltages Interface traps can also assist in the tunneling process. This is illustrated in Fig. 2.67. Interface states exist at both the substrate silicon-{)xide interface and the gate silicon-{)xide interface. IIi general, states above the Fenni level are empty of electrons and states below the Fermi level are filled with electrons. In Fig. 2.67(a), the gate electrode is biased 132 2 Basic Device Physics .H---- 0.--·.....-- Ee Ef Ev Ee Ev ----I n+ silicon Si02 p silicon FIg1ll'll2.66. Schematic illustrating bulk-trap-assisted tunneling in an MOS capacitor structure. (a) Ev III ~_E, Ef Ey n+ silicon Si02 p silicon (b) ..... -... -------- • ...----- Ee Ef --E v Ev .. FigIll'll2.67. Schematics illustrating interface-trap-assisted tunneling of electrons in a silicon-gate MOS structure. (a) The gate electrode has a small negative bias. The Fenni level in the p-silicon lies somewhat below that in the n+ silicon gate. (b) The gate electrode has a small positive bias. The Ferrni level in the p silicon lies somewhat above that of the n+ silicon gate. slightly negatively (towards flatband condition and surface accumulation of the p-silicon). As the surface of the p silicon is driven towards flat band and surface accumulation, more and more states at the interface become empty ofelectrons. An electron in the conduction band ofthe gate electrode can tunnel into an empty state at the p-silicon surface. Also, not shown in the figure, an electron in an occupied surfuce state ofthe gate electrode can also tunnel into an empty surface state of the p silicon. These interfuce-trap-assisted tunneling processes are in addition to the normal tunneling of electrons from the conduction band of the gate electrode into the conduction band of the p.substrate. In Fig. 2.67(b), the gate is biased somewhat positively (towards surface inversion of the p silicon). As the surface of the p silicon is driven towards inversion, more and more 2.5 High-Field Effects 133 states at the surface become filled with electrons. Until the p silicon surface is inverted, there are very few electrons.availahle to tunnel from the conduction band ofthe p silicon to the conduction band of the gate electrode. However, electrons from the filled surface states of the p silicon can tunnel into the conduction band of the gate electrode. Since interface-trap-assisted tunneling is a direct tunneling process, it is important only for thin . oxides. Also, as can be inferred from Fig. 2.67, interface-trap-assisted tunneling is effective only when the p silicon surface potential lies between inversion and weak accumulation. That is, interface-trap-assisted tunneling is important only at low voltages. lnterface-trap-assisted tunneling can enhance the low-voltage tunneling current in thin oxides whether the gate electrode is biased positively or negatively. Interface-trap­ assisted tunneling in modem CMOS devices is a widely studied subject. The reader is referred to the literature for more details (see e.g. Crupi et al., 2002, and the references therein). 2.5.4 Injection of Hot Carriers from Silicon into Silicon Dioxide If a region of sufficiently high electric field is located near the Si-Si02 interface, some electrons or holes in the region can gain enough energy from the electric field to surmount the interface barrier and enter the Si02 layer. In general, injection from Si into Si02 is much more likely for hot electrons than for hot holes because (a) electrons can gain energy from the electric fi~ld much more readily than holes due to their smaller effective mass, and (b) the Si-Si02 interface energy barrier is larger for holes (~4.6 eV) than for electrons (~ 3.1 eV), as indicated in Fig. 2.28. The process of hot-electron and hot-hole injection from silicon into silicon dioxide is much too complex to model quantitatively. Thus far, quantitative agreement has been shown only for the special case of hot electrons traveling from the silicon substrate perpendicularly towards the Si-Si02 interface, and with Monte-Carlo models that take into account the correct band structures, all the relevant scattering processes, and nonlocal transport properties (Fischetti et al., 1995). Here we discuss a simple model for the injection of hot electrons and hot holes from Si into Si02. The same model can he modified readily to describe the injection of hot holes from Si into Si02• 2.5.4.1 Energy Barrier for Hot Electron Injection The energy barrier q¢ox shown in Fig. 2.61(a) is the difference in energy between the conduction band of Si02 and the conduction band ofSi. In Appendix 7, it is shown that the image-force effect causes the barrier for injection of a hot electron from Si into Si02 to be lowered by an amount equal to qlJ.¢ = (2.262) The actual energy barrier for hot electron emission is therefore (q¢ox qlJ.¢). For iE'ox = 1 X 106 Vfcm, qlJ.¢ 0.19 eV. Thus, for practical oxide fields ofI06 Vlcm or larger, image-force barrier lowering is not negligible compared to the interface energy 134 2 Basic Device Physics E1ectrolls Ec _Ev Ec----j Ev----i p substrate Oxide Rgure 2.68. Schematic illustrating hot electrons traveling perpendicularly towards the Si-Si02 interface and being injected into the Si02 layer. barrier of3.1 eV. Image·force barrier lowering is included in the more accurate theories of Fowler-Nordheim tunneling (Lenzlinger and Snow, 1969) and direct tunneling (Chang et al., 1967). However, in the literature there are also publications questioning the validity of the concept of image potential at the interface between a semiconductor and an insulator (see e.g. Fischetti et al., 1995, and the references 2.5.4.2 The Lucky Electron Model The simple one-dimensional injection process is illustrated in Fig. 2.68. The simplest model for describing the injection process is the lucky electron model proposed by Shockley (1961). It is an empirical model, but it describes the measured data surprisingly well (Ning et al., 1977a). In this model, the probability that a hot electron at a distance d from the Si-Si02 interface will be emitted into the Si02 layer is expressed as P(d) = Aexp(-d/A.), (2.263) where A. is an effective mean free path for energy loss by hot electrons in silicon, and A is a fitting constant to the experimental data. The relation between the parameter d, the effective hot-electron emission energy and the electron potential energy, is illustrated in Fig. 2.68. The parameter d can be obtained as follows. Referring to Fig. 2.68, qV(x) is the potential energy of an electron at x. An electron at x d has just enough potential energy to overcome the effective energy barrier for emission if it can travel from x = d to the interface at x =0 without encountering any energy-losing collision. That is, qV(d) is equal to the effective energy barrier for emission. The injection of hot holes from Si into Si02 can be described by a similar lucky hole model (Selmi et al., 1993). It was determined empirically that the effective energy barrier for electron emission can be written as (2.264) 2.5 High-Field Effects 135 -= (a) (b) (c) Rgure 2.69. Schematics illustrating a gated n+ diode when the surface is (a) inverted and (b) accumulated, and (c) when the surface of the region is depleted or inverted. The dashed lines indicate the boundary of the depletion region. 2.5.5 where the first two terms are the Si-Si02 interface energy barrier and the image-force barrier lowering discussed in the previous subsection, and the third term is introduced to account for the fact that hot electrons without enough energy to surmount the image­ force-lowered energy barrier can still tunnel into the oxide layer. It was found that setting a = 1 x 1O-5e(cm2_V)1/3 and A = 2.9 fits a wide range of measured emission probabil­ ities (Ning et al., 1977a). The temperature dependence of the hot-electron injection process is contained in the temperature dependence of the effective mean free path (Crowell and Sze, 1966b) = Ao tanh(ER/2kT), (2.265) where 63 meV is the optical-phonon energy, and ilo is the low-temperature limit of l. It was found empirically that ilo=IO.8nm (Ning et al., I 977a). The mean free path associated with hot-hole injection has a comparable value (Selmi et ai., 1993). High-Field Effects In Gated Diodes Thus far, the effects of high fields have been considered for p-n diodes and MOS capacitors separately. In a gated diode structure, both the location of the peak-field region and the magnitude ofthe peak field vary with gate voltage. Let us consider a gated diode. As discussed in Section 2.3.5, when the gate is biased to invert the silicon surface, the inverted surface region has about the same potential as the n+ region, and the gated diode behaves like a large-area n+-p diode. If the p-region is uniformly doped, the depletion-layer width is about the same below the n+ silicon region as below the surface inversion region, hence the electric field is rather uniformly distributed and is abou.t the same as in a simple p-n diode. This is illustrated schematically in Fig. 2.69(a). When the gate isbiased somewhat negatively to accumulate the silicon surface, the silicon surface under the gate has about the same potential as the p-type substrate. Owing to the prese!lce of the accumulated holes at the surface, the surface behaves like a p-region more heavily doped than the substrate, causing the depletion layer at the surface 136 2 Basic Device Physics Idiode 8i surface accumulating 8i surface 8i surface depleted inverted 0' Vg Figure 2.70. Schematic illustrating an n+-p gated-diode leakage current as a function of gate voltage. to become narrower than elsewhere. This is illustrated schematically in Fig. 2.69(b). The narrowing of the depletion layer at or near the intersection of the p-n junction and the Si-Si02 interface causes field crowding, or an increase in the local electric field. When the negative gate bias is large enough, the n+ region under the gate can become depleted, and even inverted. This is illustrated in Fig. 2.69(c). In this case, the gate and the n+ region behave like an MOS capacitor with a heavily doped n-type "substrate." There is more field crowding, and the peak field increases. As the electric field in and around the gated p-n junction is increased by the gate voltage, all the high-field effects, such as avalanche mUltiplication and band-to-band tunneling, can increase very dramatically. Thus the leakage current of a reverse-biased gated diode can increase dramatically when the gate voltage begins to cause field crowding in and around the junction region. This is illustrated in Fig. 2.70 which shows the expected gated-diode leakage current as a function ofgate voltage. In 2.70, aside from the increase in current due to field crowding at negative gate voltage, the diode current is simply the sum of the leakage current from the depletion region of a diode and the leakage current from the exposed surface states (Grove and Fitzgerald, 1966). When the Si surface is in accumulation (at Vg ;:::: 0), the leakage current is from the depletion region of the bulk diode alone. When the Si surface is inverted (at large Vg), the leakage current is higher because ofthe additional leakage current coming from the depletion region of the diode formed by the surface inversion layer and the substrate. When the Si surface is depleted (at intermediate values of Vg), the leakage current is the largest because ofthe addition leakage current coming from the exposed surface states ofthe depleted silicon surface. When field crowding occurs in the drain junction of a MOSFET, the increased junction leakage current is called gate-induced drain leakage, or GIDL (Chan et aI., 1987a; Noble et aI., 1989). GIDL is an important leakage--current component that must be minimized in modern CMOS devices. It should be noted that for the n+-p diode considered here, when the gate is biased to accumulate the silicon surface, the oxide field favors the injection of hot holes from the silicon substrate into the silicon dioxide layer (Verwey, 1972). Similarly, for a gated p+-n diode, the oxide field favors the injection of hot electrons when the gate is biased to accumulate the silicon surface. Thus injection of majority instead of carriers, from the silicon substrate into the silicon dioxide layer takes place when significant gate-voltage-induced avalanche multiplication occurs in a gated diode. 2.5 High-Field Effects 137 (a) C ~ u" ."5" 0cc3 r::> Time (b) Cg ::l ~"'ccc"" r" Time Figure 2.71. Schematics illustrating the typical time dependence of the tunneling current at constant voltage in (a) a thick oxide layer and (b) a thin oxide layer. A sudden jump in tunneling current signals a dielectric breakdown event. 2.5.6 Dielectric Breakdown As discussed in Section 2.5.3, significant electron tunneling can take place when a large electric field is applied across an oxide layer. Figure 2.71 illustrates schematically the typical time dependence of the tunneling current when a constant voltage is applied across an oxide layer. A sudden jump in the tunneling current indicates that the oxide sample has suffered a dielectric breakdown event. For oxides thicker than about 10 nm, the tunneling current typically decreases gradually with time until the oxide breaks down. For these thick oxides, the voltages used to measure tunneling current are usually so large that, unless special care is taken to limit the current, a breakdown event usually leads to the oxide being physically damaged (Shatzkes et al., 1974). There is a distribution in the measured oxide breakdown time (Harari, 1978). This is illustrated in Fig. 2.7 I(a). For oxides thinner than about 5 nm, the voltages used to measure tunneling CUiTent are usually sufficiently small so that not every breakdown event leads to catastrophic breakdown. For most samples, successive breakdown events are observed before final or catastrophic breakdown (Sune et aI., 2004). This is illustrated in Fig. 2.71(b). An oxide layer ceases to be a good electrical insulator after it suffers final or catastrophic breakdown. In thin oxides, the increase in tunneling current from the first breakdown event to final breakdown can occur quite gradually. When the thin gate oxide of a modem MOS transistor in a circuit starts showing signs of breaking down, often the gate tunneling 138 2 Basic Device Physics E ~ ::l <.> ~"" FEI CD Catastrophic breakdown [faU Time Flgure2.n. Schematic illustrating the evolution of the tunneling current in a thin oxide MOS device at constant applied voltage. flail indicates the tunneling current at which the device fails to function properly in a circuit. The three stages marked 1, 2, and 3 are discussed in the text. 2.5.6.1 current can grow to a sufficiently large value to cause the circuit to fail long before the gate oxide layer suffers final breakdown (Kaczer et al., 2000; Linder et al.. 2001). Figure 2.72 is a schematic illustrating the time dependence ofthe tunneling current in a typical thin-oxide MOS device at constant voltage stress. There are roughly three stages in the evolution of the tunneling current. In the initial stage (stage 1 in Fig. 2.72), the current is relatively featureless, typically first decreasing. due to electron trapping, and then rising, due to hole trapping and trap-assisted tunneling, as a function oftime. As the current continues to rise, it becomes noisy (stage 2). Finally, the current rises much more rapidly (stage 3) for some time before final breakdown. In Fig. 2.72, Ijail denotes the tunneling-current level at which a circuit using the MOS transistor fails to function properly. In the literature, stage 1 is often referred to as the defect generation stage or stress-induced leakage current stage (DiMaria, 1987; Stathis and DiMaria, 1998); stage 2 as the soft breakdown stage (Depas etal., 1996), and stage 3 as the successive breakdown or progressive breakdown stage (Linder et al., 2002; Okada, 1997; Suiie and Wu, 2002). Breakdown Field In the literature, the ofan oxide film is often measured in terms ofthe electric field at which dielectric breakdown, usually the first breakdown event, occurs. "Good-quality" thick (> 100 nm) Si02 films typically break down at fields greater than 10 MY/em, while "good-quality" thin «lOnm) Si02 films usually show larger breakdown fields, often in excess of 15 MY/em. In bipolar transistors, because there are normally no thin oxide components, the electric fields across the oxide layers are usually so small that dielectric breakdown is not a concern. In CMOS devices, the maximum oxide field varies widely, depending on the application. For devices used in logic and memory circuits, the maximum oxide field is typically in the 3-6MY/cm range in normal operation, and can reach as high as 5-9 MY/cm in special operations (such as during a device burn-in process). For devices used in electrically programmable nonvolatile memory applica­ tions, where normal operation involves tunneling through a thin dielectric layer, the maximum electric field across the thin dielectric layer is in excess of 10 MV/cm. Dielectric breakdown is a real concern in CMOS devices. 2.5 High-Field Effects 139 Tn.. n+ ~ .. ~ Figure 2.73. Schematic illustrating the bias configuration ofan n-channel MOSFET for measuring the charge to breakdown and its hole-charge component. 2.5.6.2 TIme to Breakdown and Charge to Breakdown The breakdown characteristics of an oxide film are often described in terms of its time to breakdown, which measures the time needed for the film to reach breakdown, or its charge to breakdown, which measures the integrated total tunneling charge leading up to break­ down. In product design, we want to ensure that the gate current ofa CMOS device will not grow to the point of causing circuit failure before the product end of life. Therefore, in product design, we want to know the time to breakdown. However, it appears easier to develop physical models relating charge to breakdown to the physical mechanisms involved in the dielectric breakdown process, such as hole current, trapping, trap genera­ tion, and interface state generation (Schuegrafand Hu, 1994; DiMaria and Stathis, 1997; Stathis and DiMaria, 1998), than to develop physical models relating time to breakdown to these physical mechanisms. Most publications on the physics of dielectric breakdown discuss the breakdown process in terms of charge to breakdown instead of time to break­ down. Therefore, we will not discuss time to breakdown any further here. The reader is referred to the literature fordiscussions on time to breakdown and the breakdown statistics in the time domain (see e.g. Suiie et al., 2004, and the references therein). As discussed in Section 2.5.33, a tunneling electron current can generate a hole current. Thus, the charge to breakdown, QBD, is the sum of the charges due to electrons and holes. If an MOS capacitor structure is used to measure QeD, then, owing to the two-terminal nature of the device, only the total charge can be measured. However, if an n-channel MOSFET or an n+-p gated-diode structure is used to measure QBD, then both the total charge and the hole-charge component can be determined. For the case of an n-channel MOSFET, the bias configuration for such measurements is illustrated in Fig. 2.73. The basic concept of this charge separation method is that electron current is measurcd at the n-type terminal and hole current is measured at the p-type terminal. Integration of the gate current the total charge, and integration of the substrate current gives the charge due to the holes. It is shown that, charge for charge, hot holes are much more effective than tunnel electrons in generating defects that lead to oxide breakdown (Li et al.. 1999). 140 2 Basic Device Physics 10° ~ 10-2 i 10-4 6t: 10-<' k~ 10-8 10­ 10 25 °C 14O'C o • LOnm 110O--1124t/('~;r I , I '" ,1.°, J. L5nm .·,2-7n~J} 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Stress voltage Figure 2.74. Measured rate of increase of breakdown current for typical thin oxides. (After Linder et al., 2002.) 2.5.6.3 Progressive Breakdown and Successive Breakdown Referring to Fig. 2.72, the evolution ofthe tunneling current can be described as a process of positive feedback between defect generation and trap-assisted tunneling. When a stress voltage is applied across an oxide layer, at first there are few defects in the oxide and the tunneling current is relatively low, decreasing with time as electrons are trapped. As trapped holes start to accumulate in the oxide, the current will start increasing. The tunneling current generates defects which in tum assist in the tunneling process (DiMaria, 1987; Stathis and DiMaria, 1998). At some point, soft breakdown starts when the defects in the oxide become dense enough such that an electron can tunnel relatively easily from one defect center to another across the oxide layer. This trap­ assisted tunneling current tends to be noisy (Depas et aI., 1996). As the defect density continues to grow, hard breakdown (a breakdown event or a series ofbreakdown events) starts when there is a connected path of overlapping defects all the way across the oxide layer (Degraeve et al., 1995; Stathis, 1999). This connected path of defects acts as a low­ resistance conduction path for the electrons. Once hard breakdown starts, the electron current is completely dominated by the flow along this low-resistance path and the magnitude of the current is more-or-Iess independent of the device area. The electron current causes the diameter of the path of connected defects to grow, which in tum causes the current to grow. The current does not grow smoothly, but in a staircase manner. Each time the tunneling current jumps, it represents a breakdown event. Eventually, catastrophic breakdown ofthe oxide layer occurs. Thus, a thin oxide can go through many successive breakdown events before it breaks down catastrophically (Sune and Wu, 2002). The oxide degradation rate (the rate at which the average breakdown current increases with time) is a strong function of the stress voltage (Linder et at., 2002; Lombardo et al., 2003). Figure 2.74 is a plot of typical measured degradation rates for thin oxides. It suggests that even after hard breakdown has commenced, the tunneling current in a thin oxide at a low voltage can take a long time to grow to a value sufficiently large to cause circuitfailure. In the literature, most charge to breakdown measurements are made by integrating the tunneling current until the current shows a sudden jump in magnitude, or until the first breakdown event. For a given oxide film, the charge to breakdown QBD is often Exercises 141 107 106 '"S lOS Q ~" 10< '0 ~ !! 103 ..0 ,9 ~ IOZ ."c U 101 100 25nm .( 6.9nm to-I 2 3 45 6 1 8 9 10 11 12 Oxide voltage (V) Figure 2.75. Typical plot ofcharge to breakdown versus oxide voltage for several oxide thickness values. (After Schuegrafand Hu, 1994.) as a function of oxide voltage. Figure 2.75 is a typical plot for oxide thickness in the 2.5-JOnm range (Schuegrafand Hu, 1994). It shows that, for these relatively thick oxides, QBD decreases with increasing oxide voltage. It has also been shown that QBD is about the same for n-channe1 and p-channel MOSFETs (DiMaria and Stathis, 1997). Since these published QBD values do not take into account the progressive nature of the breakdown process, they project a lower allowed voltage for an oxide than is justified from a device reliability point of view. The progressive breakdown and the successive breakdown models, which take into account the oxide degradation rate after hard break­ down has commenced (stage 3 in Fig. 2.72), project a larger but more accurate allowed voltage (Linder et aI., 2002). The reader is referred to the literature on thin oxide reliability for more details (Degraeve et al., ]998; Suehle, 2002; Sune et at., 2004). As illustrated in Fig. 2.72, the gate leakage current of a MOSFET in a circuit has to reach a certain critical level, indicated by !rail, before the circuit ceases to function properly. Thus, in circuit applications, what designers really need to know is the time to critical current instead of time to first breakdown or charge to breakdown. Exercises 2.1 Show that the values of the Fermi-Dirac distribution function, Eq. (2.4), at a pair of + energies symmetric about the Fermi energy EJ; are complementary, Le., show that fD(Ej- t:.E) fD(Ej+ t:.E) 1, independent of temperature. 142 2 Basic Device Physics Exercises 143 2.2 For a given donor level Ed and concentration Nd of an n-type silicon, solve the Fenni energy Ef from the charge neutrality condition, Eq. (2. I9)(neglecting the hole tenn). Show that - Efapproaches the complete ionization value, Eq. (2.20), under the . condition of shallow donor level with low to moderate concentration. What happens if the condition is not satisfied? 2.3 Use the density of states N(E) derived in Section 2.1.1.2 to evaluate the average kinetic energy of electrons in the conduction band: .r; (K.E.) = J~ (E - Ec)N(E)/D(E)dE N(E)fD(E)dE (a) For a nondegenerate semiconductor in which can/D(E) be approximated by the Maxwell-Boltzmann distribution, Eq. (2.5), show that (K.E.) = ~kT. ! (b) For a degenerate semiconductor at 0 K, show that (K.E.) (Ef Ee). 2.4 The 3-D Gauss's law is obtained after a volume integration of the 3-D Poisson's equation and takes the fonn fJ'l· dS = Q, Bsj where the left-hand side is an integral of the nonnal electric field over a closed surface S, and Q is the net charge enclosed within S. Use it to derive the electric field at a distance r from a point charge Q (Coulomb's law). What is the electric potential in this case? 2.5 (a) Use Gauss's law to show that the electric field at a point above a unifonnly charged sheet ofcharge density 0., per unit area is 0./28, where B is the permittivity of the medium. (b) For two oppositely charged parallel plates with surface charge densities 0., and -Qs, show that the electric field is unifonn and equals Qs/8 in the region between the two plates and is zero in the regions outside the two plates. 2.6 The total depletion charge and inversion charge densities ofa p-type MOS capacitor r can be expressed as Qd -qNaJ~d (l - e-tJ'P/kT)dx = -qNa _1_-_-_ _ _dll/. and Q/ _q ,n.;2JWd (e'l'P/kT _ I )dx _ nJ J'P' e'l'lllkl ­ a0 q N a 0 using Eqs. (2.177) and (2.178). Here 'i -d\ll/dx is given by Eq. (2.181). Write down the expressions for the small-signal depletion capacitance, Cd -dQd/d\lls and.the..small-signaJ inversion capacitance (low frequency), Cj = -dQi/d\lls' in silicon as represented in the equivalent circuit in Fig. 2.37. (b) Show that Cd + Ci = Cst, where CSi = -dQ./dlfls is evaluated using Eq. (2.182). (c) Show that Cd ~ at the condition of strong inversion, \lis = 2\118. (This allows one to use a split C-V measurement to determine the gate voltage where \lis 2\118)' . (d) From the behavior of Cd beyond strong inversion, explain the "screening" of depletion charge (incremental) by the inversion layer. 2.7 Near the surface of an MOS capacitor biased well into strong inversion, only the exp(q\lllk1) tenn in the square-root expression of (2.191) needs to be kept (classical model). Solve \if{x) under the boundary condition \II (O) = IfIx. Express the inversion electron concentration n(x) in tenns of the surface concentration nCO) given by Eq. (2.193). 2.8 Solve the gate voltage equation (2.195) for \IIs(Vg) under the depletion condition in which Qs(\IIs) Qd(\IIs) given by (2.189). Show that for incremental changes, D.\IIx D.Vg/(1 + Cd/Cox), where Cd is the depletion charge capaci­ tance given by (2.20 I). 2.9 When the gate voltage greatly exceeds the threshold for strong inversion, a first­ order solution of IfIs{Vg) can be obtained from the coupled equations (2.195) and (2.182), by keeping only the inversion charge term. Show that \lis ~ 2 \liB + 2kT ln q (CO.«Vg Vjb - 2\118)) J2BsikT Na under these circumstances. Estimate how much higher IfIs can be over 2\118 by substituting some typical values in the logarithmic expression. 2.10 In the split C-V measurement in Fig. 2.37(b), show that the n+ channel part of the small-signal gate capacitance is dQj CasCi d Vg Cax + Ci + Cd' Sketch the functional behavior of dQ/dVg versus Vg , and from it describe the behavior of Qi versus Vg . 2.11 The multiplication factors for holes and for electrons are given by Eqs. (2.256) and (2.257), respectively. For the special case of constant ap and am show that Mp -+ 00 occurs when the depletion-layer width approaches the value of W = In(Ctn/Ctp)/(Ctn Q p ). Also show that the condition for Mn -+ 00 gives the same result for W. r d.,,) f:}1X)dX) 2.12 Prove the following mathematical identities: fix) exp (- dx 1 exp ( - and, 144 2 Basic Device Physics r r J: Ax) exp dX') dx=]- exp ( - dX). These identities are used in Appendix 8 to show that the condition for hole­ initiated avalanche breakdown, namely liMp ---> 0, is the same as that for electron­ initiated avalanche breakdown, namely liMn ...... O. 2~ 13 The depletion-layer capacitance per unit area of a uniformly doped abrupt p-n diode and its dependence on doping concentration and applied voltage are given in Eqs. (2.80), (2.81), and (2.83). Sketch I/Cl as a function of the applied reverse-bias voltage Yc,pp. Show how this olot can be used to determine N a a n d Nd · 2.14 The depletion-layer capacitance of a one-sided p-n diode is often used to deter­ mine the doping profile of the lightly doped side. Consider an n+-p diode, with a nonuniform p-side doping concentration of Nix). If QJV) is the depletion-layer charge per unit area at bias voltage V, the capacitance per unit area at bias voltage Vis C = dQd/dV. In terms of the depletion-layer width W, we have C(V) = where Wis a function of V. (For simplicity, we have dropped the subscripts in C, W, and Vhere.) Show that the doping concentration at the depletion-layer edge is given by 2 Na(W) - qes;d(I/CZ)/dV' 2.15 The charge distribution of a p-i-n diode is shown schematically in Fig 2.17. The i-layer thickness is d. The depletion-layer capacitance is given by Eq. (2.96), c,t namely = Gs;/Wd, where Wd = Xn + xp is the total depletion-layer width. Derive this result from Cd dQ,t/dV. 2.16 Consider a p-n diode. Assume the junction is located at x = 0, with the n-region to the left (i.e., x < 0) and the p-region to the right (Le., x > 0) of the junction. The distribution ofthe excess electrons is given by Eq. (2.119), and the electron current density entering the p-region is given by Eq. (2.120). Derive the equation for the distribution ofthe excess holes in the n-region and the equation for the hole current density entering the n-region. 2.17 The minimum leakage current of a reverse-biased diode is determined by its saturation current components. The saturation currents depend on the dopant concentrations of the diode, as well as on the widths of the quasineutral p- and n-regions. They also depend on whether or not heavy-doping effect is included. This exercise is designed to show the magnitude of these effects. (a) Cansider an diode, with an emitter doping concentration of 1020 cm- 3 a base doping concentration ofl0 17cm- 3• Assume both the emitter and the base to be wide compared with their corresponding minority-carrier diffusion lengths. Ignore heavy-doping effect and calculate the electron and hole satura­ tion current densities [see Eq. (2.129)]. Exerclses 145 In most modern MOSFET and bipolar devices, the n+-p diodes have the n+-region widthsmall.compared with its hole diffusion length. If we assume the quasineutral n+ region to have a width of 0.1 !ill1, again ignoring heavy­ doping effect, estimate the hole saturation current density [see Eq. (2.133)]. (c) It is discussed in Section 6.1.2 and shown in Fig 6.3 that the effect of heavy doping should be included once the doping concentration is larger than about 1017 cm- 3. Heavy-doping effect· is usually included simply by replacing the intrinsic-carrier concentration nj by an effective intrinsic-carrier concentration n;e, where nj and n;e are related by nT. = nT exp(D.Eg/kT). The empirical parameter t'illg is called the apparent bandgap narrowing due to heavy-doping effect, and its values are plotted in Fig. 6.3. Repeat (b) including the effects of heavy doping. 2.18 Consider an n+-p diode, with the n+ emitter side being wide compared with its hole diffusion length and the p base side being narrow compared with its electron diffusion length. The diffusion capacitance due to electron storage in the base is CDm and that due to hole storage in the emitter is CDp' Assume the emitter to have a doping concentration of 10-20 cm-3 and the base to have a width of 100 nm and a doping concentration of 1017 cm-l . (a) If heavy-doping effect is ignored, the capacitance ratio is (see Eq. (2.168») NE W CD" 2 B (heavy-doping effect ignored). 3 NB LpE Evaluate this ratio for the n+-p diode. When heavy-doping effect cannot be ignored, it is usually included simply by replacing the intrinsic-carrier concentration n; by an effective intrinsic-carrier concentration n;e [see part (c) ofExercise 2.17). Show that when heavy-doping effect is included, the capacitance ratio becomes C (nT'B) (NE) .. " . "" . Dn - -2 -2- - - (heavy-dopmg euect meIuded) , CDp 3 n;eE NB LpE where the subscript B denotes quantities in the base and the subscript E denotes quantities in the-emitter. Evaluate this ratio for the n+-p diode. (This exercise demonstrates that heavy-doping effects cannot be ignored in any quantitative modeling of the switching speed of a diode.) 2.19 As electrons are injected from silicon into silicon dioxide, some of these clectrons become trapped in the oxide. Let NT be the electron trap density, nT be the density of trapped electrons, andjalq be the injected electron particle current density. The rate equation goveming n~t) is dnT q a-(NT 146 2 Basic Device Physics where u is the capture cross section of the traps. If the initial condition for nT is nT(t== 0) == 0, show that the time dependence ofthe trapped electron density is given by = Nr{l- exp [-uNj"At))}, where II Ninj (t) == JG(t') dt' oq is the number of injected electrons per unit area. Assume NT == 5 x 1012 cm- 3 and cr == 1 x 10- 13 cm2, sketch a log-log plot of nT as a function of Ninj• (The capture cross section is often measured by fitting to such a 2.20 The avalanche multiplication factors Mp and Mn are given by Eqs. (2.256) and (2.257). Assume ap and an are constant, independent of distance or electric field. Show that avalanche breakdown occurs when the width Wof the high-field region (the region where impact ionization occurs) approaches [In (op1on) JI (op On). 2.21 Show that the band-to-band tunneling exponent in Eq. (2.259) can be derived from the WKB approximation, i.e. Eq. (2.245), for turtneling through a triangular barrier of height Eg. slope q'l and twmeling distance Eg/q'l. 2.22 Assume silicon, room temperature, complete ionization. An abrupt p-n junction with Na = Nd 1017 em- 3 is reversed biased at 2.0 V. Draw the band diagram. Label the Fermi levels and indicate where the voltage appears. (b) What is the total depletion layer width? What is the maximum field in the junction? 2.23 For an abrupt n+ -p diode in Si, the n+ doping is 1020 cm-3 , the p-type doping is 3 x 1016 cm-3• Assume room temperature and complete ionization. (a) Draw the band diagram at zero bias. Indicate x==O as the boundary where the doping changes from n+ to p. Also indicate where the Fermi level is with respect to the midgap. (b) Write the equation and calculate the built-in potential. (c) Write the equation and calculate the depletion width. (d) Will the built-in potential increase or decrease if the temperature goes up and why? 2.24 Sketch the C-V curve (high frequency) of an MOS capacitor consisting of n+ poly gate on n-type Si doped to 1016 . Calculate and show the fiatband voltage on the C-Y. Draw the band diagram for Vg = O. Given tox == 10 nm, what is Vox (potential across oxide) at the onset of inversion (VIs 2V1B)? Ignore quantum and poly depletion effects. 2.25 Consider an MOS device with 20 nm thick gate oxide and uniform p-type substrate of 1017 cm- 3 • The gate work function is that ofn+ Si. Exercises 147 (a) What is the flatband voltage? What is the threshold voltage for strong inversion? (b) Sketch the high frequency C-V curve. Label where the flatband voltage and threshold voltage are. (c) Calculate the maximum and the minimum capacitance (per area) values. 2.26 If the device in Exercise 2.25 is biased at zero gate voltage, determine the surface potential and the electron and hole densities at the surface. 3 MOSFET Devices 3.1 Long-Channel MOSFETs 149 The metal-oxide-semiconductor field-effect transistor (MOSFET) is the building block of VLSI circuits in microprocessors and dynamic memories. Because the current in a MOSFET is transported predominantly by carriers of one polarity only (e.g., electrons in an n-channel device), the MOSFET is usually referred to as a unipolar or majority-carrier device. Throughout this chapter, n-channel MOSFETs are used as an example to illustrate device operation and derive drain-current equations. The results can easily be extended to p-channeJ MOSFETs by exchanging the dopant types and reversing the voltage polarities. The basic structure ofa MOSFET is shown in Fig. 3.1. It is a four-terminal device with the terminals designated as gate (subscript g), source (subscript s), drain (subscript d), and substrate or body (subscript b). An n-channel MOSFET, or nMOSFET, consists ofa p-type silicon substrate into which two n+ regions, the source and the drain, are formed (e.g., by ion implantation). The gate electrode is usually made ofmetal or heavily doped polysilicon and is separated from the substrate by a thin silicon dioxide film, the gate oxide. The gate oxide is usually formed by thermal oxidation ofsilicon. In VLSI circuits, a MOSFET is surrounded by a thick oxide called the field oxide to isolate it from the adjacent devices. The surface region under the gate oxide between the source and drain is called the channel region and is critical for current conduction in a MOSFET. The basic operation ofa MOSFET device can be easily understood from the MOS capacitor discussed in Section 2.3. When there is no voltage applied to the gate or when the gate voltage is zero, the p-type silicon surface is either in accumulation or in depletion and there is no current flow between the source and drain. The MOSFET device acts like two back-to-back p-njunction diodes with only low-level leakage currents present. When a sufficiently large positive voltage is applied to the gate, the silicon surface is inverted to n-type, which forms a conducting channel between the n+ source and drain. If there is a voltage difference between them, an electron current will flow from the source to the drain. A MOSFET device therefore operates like a switch ideally suited for digital circuits. Since the gate electrode is electrically insulatedfrom the substrate, there is effectively no de gate current, and the channel is capacitiwly coupled to the gate via the electricfield in the oxide (hence the namefield-ejjecl transistor). 3.1 long-Channel MOSFETs This section describes the basic characteristics of a long~channel MOSFET, which will serve as the foundation for understanding the more important but more complex Source (s) Drain (d) Field oxide (FOX) p-type silicon substrate (b) Vbs Figure 3.1. Three-dimensional view of basic MOSFET device structure. (After Arora, 1993.) short-channel MOSFETs in Section 3.2. First, a general MOSFET current model based on the gradual channel approximation (GCA) is formulated in Section 3.1.1. TheGCA is valid for most regions of MOSFET operation except beyond the pinch-off or saturation point A charge-sheet model is then introduced to obtain implicit equations for the source-drain current. Regional approximations are applied in Section 3.1.2 to derive explicitJ-Vexpressions for the linear and parabolic regions. Current characteristics in the subthreshold region are discussed in Section 3.1.3. Section 3.1.4 addresses the threshold­ voltage dependence on substrate bias and temperature. Section 3.1.5 presents an empiri­ cal model for electron and hole mobilities in a MOSFET channeL Lastly, intrinsic MOSFET capacitances and inversion-layer capacitance effects (neglected in the regional approximation) are covered in Section 3.1.6. 3.1.1 Drain-Current Model In this subsection, we formulate a general drain-current model for a long-channel MOSFET. The model will then be simplified using charge-sheet approximation, leading to an analytical expression for the source-drain current Figure 3.2 shows the schematic cross section of an n-channel MOSFET in which the source is the n+ region on the left, and the drain is the n+ region on the right A thin oxide film separates the gate from the channel region between the source and drain. We choose an x-y coordinate system 150 3 MOSFET Devices Polysilicon gate Gate Inversion channel p-type substrate V., Figure 3.2. A schematic MOSFET cross section, showing the axes of coordinates and the bias voltages at the four terminals for the drain-current modeL 3.1.1.1 consistent with Section 2.3 on MOS capacitors, namely, the x-axis is perpendicular to the gate electrode and is pointing into the p-type substrate with x = 0 at the silicon surface. The y-axis is parallel to the channel or the current flow direction, withy= 0 at the source and y = L at the drain. L is called the channel length and is a key parameter in a MOSFET device. The MOSFET is assumed to be uniform along the z-axis over a distance called the channel width, W, determined by the boundaries of the thick field oxide. Conventionally, the source voltage is defined as the ground potential. The drain voltage is Vtis, the gate voltage is Vgs' and the p-type substrate is biased at Initially, we assume Vbs = 0, i.e., the substrate contact is grounded to the source potential. Later on, we will discuss the effect of substrate bias on MOSFET characteristics. The p-type substrate is assumed to be uniformly doped with an acceptor concentration Na• Gradual-Channel Approximation One of the key assumptions in any I-D MOSFET model is the gradual channel approximation (GCA), which assumes that the variation of the electric field in the y-direction (along the channel) is much less than the corresponding variation in the x-direction (perpendicular to the channel) (pao and Sah, 1966). This allows us to reduce the 2-D Poisson equation to I-D slices (x-component only) as in Eq. (2.175). The GCA is valid for most of the channel regions except beyond the pinch-offpoint, which will be discussed later. As defined in Section 2.3.2, tp(x, y) is the band bending, or intrinsic potential, at (x, y) with respect to the intrinsic potential of the bulk substrate. We further assume that V(y) is the electron quasi-Fermi potential at a pointy along the channel with respect to the Fermi potential of the n+ source. The assumption that V is independent of x in the direction perpendicular to the surface is justified by the consideration that current is proportional to 3.1 long-ChannelNiOSFETs 151 the gradient of the quasi-Fermi potential and that the MOSFET current flows predomi­ nantly in the source-to-drain, or.y-direction. At the source end of the channel, V(y 0) = O. At the drain end of the channel, .V(y L) =. Vtis. the reverse bias of the drain-to-substrate junction since Vbs '" O. For a vertical slice between the SQurce and drain, the channel-to­ substrate diode is reverse biased at V(y) which plays the same role as VR in Section 2.3.5 on MOS capacitors under nonequilibriurn. As depicted in Fig. A4.5 for a reverse biased p-n junction, the electron quasi-Fermi potential is essentially flat in the vertical direction across the n-type inversion layer, and is displaced by V(y) from the Fermi potential of the p-type substrate. From Eq. (2.178) and Eq. (2.214), the electron concentration at any point (x,y) is given by n(x,y) = iNne2q(Ifl-V)/kT. a (3.1) Following the same approach as in Section 2.3.2, one obtains an expression for the electric field similar to that ofEq. (2.181): (:r !i $'2(X,y) + 2k:;Na [(e-qlfl/kT I) ki)]' + ~ (e-QVlkT(eQlfllkT - 1) ­ (3.2) The condition for surface inversion, Eq. (2.217), becomes tp(O,y) V(y) + 2tpB' (33) which is a function ofy. From Eq. (2.218), the maximum depletion layer width is Wt/m(y) = 2esi[V(y) + 2tpBJ (3.4) qNa which is also a function ofy. 3.1.1.2 Pao and sah's Double Integral Under the assumption that both the hole current and the generation and recombination current are negligible, the current continuity equation can be applied to the electron current in the y-direction. In other words, the total drain-to-source current Itis is the ~e at any point along the channel. From Eq. (2.63), the electron current density at a point (x, y) is . dV(y) In(x,y) = -qpnn(x,y)T' (3.5) where n(x, y) is the electron density, and Pn is the electron mobility in the channel. The carrier mobility in the channel is generally much lower than the mobility in the bulk, due to additional surface scattering mechanisms, as will be addressed in 152 3 MOSFET Devices Section 3.1.5. With V(y) defined as the quasi-Fermi potential, i.e., playing the rDIe 0/ ¢" in Eq. (2.63), Eq. (3.5) includes bDth the drift and diffusion currents. The total current at a point y along the channel is obtained by multiplying Eq. (3.5) with the channel width Wand integrating over the depth of the current-carrying layer. The integration is carried out from x=O to X;, where Xi is a depth into the p-type substrate but not infinity: I Ids(Y) = qW Jo[" dV ,unn(x, y) dy dx. (3.6) There is a sign change, as we define Ids> 0 to be the drain-to-source current in the -y direction. Since Vis a function ofy only, dV/dy can be taken outside the integral. We also assume that lin can be taken outside the integral by defining an effective mobility, lieffi at some average gate and drain fields. What remains in the integral is the electron concen­ tration, n (x, y). Its integration over the inversion layer gives the inversion charge per unit gate area, Qj: 1"" Qj(Y) -q n(x,y)dx. (3.7) Equation (3.6) then becomes dV dV Ids(Y) = -PeflW dy Q;(y) = -,uefrW dy Qi( V). (3.8) In the last step, Qj is expressed as a function of V; V is interchangeable with y, since V is a function ofy only. Multiplying both sides ofEq. (3.8) by dyand integrating from 0 to L (source to drain) yield rV i,lsdy = liel.rW Jo ", [-Qi( V)]dV. (3.9) Current continuity requires that Ids be a constant, independent ofy. Therefore, the drain­ to-source current is r w Vd, Ill, ,lie/II.; Jo [-Qi( (3.10) An alternative form of Qi(V) can be derived if n(x, y) is expressed as a function of ('I', V) using Eq. (3.1), n(x,Y) = n('I', V) -nL2eq('JI-V)/kT Na (3.11 ) I It does not mattcr what the exact choice of Xi is. See further discussions aftcr Eq. (3.12). 3.1 Long-Channel MOSFETs 153 3.1.1.3 and substituted into Eq. (3.7): 1 Qj(V) -q . J -­ n('I', V) ~x d'l' 'JI, 'I' 'J1> (n; I Na)eq('JI-V)/kT 1 -q tl 'P( It' '1', V) d'l'. (3.12) Here, 'l's is the surface potential atx=O and 'it ('1', V) =-d'l'ldx is given by the square root of Eq. (3.2). The lower integration limit, 0, represents any small potential «kTlq, but not zero as the integral is unbounded at 'I' = 0.2 Substituting Eq. (3.12) into Eq. (3.10) yields W1 Vd' (1'J1> (n;/Na)eq('JI-V)/kT ) Ids qlieJI-L o Ii "-V)/kT] , +'I's kT (3.14) which is an implicit equation for II's(V). Equations (3.14) and (3.13) can only be solved numerically. Charge-Sheet Model Pao and Sah'8 double integral can be simplified to a single integral ifthe inversion charge density can be expressed as a function of '1'." This is accomplished by the charge-sheet model (Brews, 1978) which is based on the fact that the inversion layer is located very close to the silicon surface like a thin sheet of charge. There is an abrupt increase of the field (spatial integration of volume charge density) across the thin inversion layer, but very little change of the potential (spatial integration offield). As shown in the example in Fig. 2.36, neither the surface potential nor the depletion charge density changes much after strong inversion. The central assumption of the charge-sheet model is that Eq. (2.189) for the depletion charge density, = Qd -qNIIW,, -y'2f:siQNaV1s' (3.15) can be extended to beyond strong inversion. (Actually, once the inversion charge dominates, Qd hardly changes with 'l's. See Ex. 2.6.) Since the total silicon charge density 2 For very small,!" the integral yields Q/q of(n/INa)Lv In 'I'where Lf) is the Debye length (Eq. (2.53». This is many orders of magnitude below the level of interest even for a factor of 1010 change in ljI. But V,=O is equivalent to Xi = infinity in Eq. (3.7),.in wbich case Q, diverges. ~ t" 3 MOSFET Devices Qs is given by Eq. (3.14) or Eq. (2.195), Eq. (3.15) allows the inversion charge density to be expressed as Q; = Qs - Qd = -CoA Vgs - Vjb - 'lis) + V 2esiqNa'llS" (3.16) It should be noted that the charge sheet model does not literally assume all the inversion charge is located at the silicon surface with a zero depth. That would mean dJQ,VdVgs = Cox, which is not the case with Eq. (3.16) since 'lis also increases with Vgs as described by Eq. (3.14). The variable in the drain current integral, Eq. (3.10), can be transformed from Vto 'lis> Wi",,·d dV Ids =P.effL (-Qi('IIs))dd'lls, "',,, 'lis (3.17) where 'lis,s> 'IIs,d are the values of the surface potential at the source and the drain ends of the channel. For given Vgs and Vds, they can be solved numerically from the implicit equation (3.14) by setting V= 0 (for 'lis,s) and V= Vds (for 'IIs,d), respectively. Equation (3.14) can also be used to solve for V('IIs), V= 'lis _ kTln{Na 2 [Cox 2 ( Vgs - Vjb - 'IIs)2 _ q'lls]}, q ni 2 2esikTNa kT (3.18) and evaluate its derivative: dV 2kT Co/(VgS-Vjb-'IIs)+esiqNa -=1+ 2 2 d'lls q Cox (Vgs - Vjb - 'lis) - 2esiqNa'lls Substituting Eqs. (3.16) and (3.19) into Eq. (3.17) yields Wi"",d [ V­ Ids =l1eff1: IJI", CoAVgs - Vjb - IfIsl - (3.19) +2k-T q Co} ( CoA Vgs Vgs - Vjb Vjb - IfIs) IfIs) + f.siqNa ] + V2f.siQ Nalfls d 1fI., (3.20) which expresses the drain current in a single integral. It is too tedious to cirrry out the integral in Eq. (3.20) exactly. A second approximation is introduced in the charge sheet model (Brews, 1978) to obtain an analytical expression for the drain current. Note that the first two terms in the square bracket ofEq. (3.20) is simply -Qi' Because of the kT/q multiplier, the last term in the square brackets is usually much smaller than the first two unless Qi""O which happens when CoxCVgs -Vjb -'lis) "" V2esiqNa'lls. It is then a good approximation to apply this relation to the last term in the square brackets so that the integral can be carried out analytically: _ W{ ( k!:\ Id, - P.effL Cox Vgs - Vjb + q) 'lis -"2I Cox'lls2 -:32 V~ 2f.siqNa'lls3/2 I +-k--TqV2f.SiqNa'lls } "',.d . VIs,s (3.21 ) 3.1 Long-Channel MOSFETs 155 ~ 2.5~ ~2 oj ''::: Ei 1.5 0 0. r ~- <.) "~ ::> F VJ 0.5 ­- 21/JB + v-:--.,..,,,,/ --- / ,- /" ..', Vgs= 3V 2V IV Figure 3.3. 00 0.5 1.5 2 2.5 Electron quasi-Fermi potential, V (V) Numerical solutions of the implicit Eq. (3.14) for three values of Vgs. The dotted line represents the regional approximation used in Section 3.1.2. The MOS device parameters are Na = 10 17 cm-3, tox = lOnm, and Vjb = O. / 3.1.2 Because Eq. (3.21) covers all regions of MOSFET operation: subthreshold, linear, and saturation in a single, continuous function, it has become the basis of all surface potential based compact models for circuit (SPICE) simulations (Gildenblat et al., 2006). Many numerical methods have been developed to solve the implicit Eq. (3.14) for 'lis,s and 'IIs,d, given Vgs and Vds' They employ either explicit approximations or iterative procedures. The general behavior of the solution 'IIs(V) is shown in an example in Fig. 3.3. The device parameters are the same as those of Fig. 2.36. For Vgs= 1 V, the device is below threshold where the inversion charge is negligible, i.e., the (n/ / Na 2)eq(",,-V)/kT term in the square brackets in Eq. (3.14) is negligible. The solution 'lis depends on Vgs (see Fig, 2.36), but is totally insensitive to V. For Vgs = 2 V, the MOSFET is turned on. Here, 'lis increases more or less linearly with V when Vis not too large. As Vincreases (for large enough Vds), 'lis reaches a saturation value beyond which it becomes independent of V. This is caned the pinch-off condition !Vhere Qi given by Eq. (3.16) becomes very small. The argument of the log function in Eq. (3.18) also approaches zero. For Vgs = 3 V, the saturation value of 'lis increases while the saturation happens at a higher V (or Vds)' Because of the two simplifying approximations used, the current calculated from the charge sheet model, Eq. (3.21), deviates from that of Pao and Sah's double integral, Eq. (3.13). The error is a function of doping concentration, oxide thickness, gate and drain bias voltages. Typically, it can be ofthe order of 10% under certain conditions when biased above threshold (Kyung, 2005). The error is generally larger in subthreshold where the current levels are low and high accuracy is not a paramount issue. MOSFET I-V Characteristics In this subsection, we derive the basic 1-V characteristics of a long-channel MOSFET in the linear and parabolic regions. 156 3 MOSFET Devices 3.1.2.1 Regional Approximations To obtain explicit equations for the drain current, it is necessary to apply regional approximations to break the charge-sheet model into piecewise models. After the onset of inversion but before saturation, the surface potential can be approximated by IfIs = 21f1B + V(y), or Eq. (3.3). This relation is plotted in Fig. 3.3 (dotted line) for comparison with the more exact curves. It then follows that dVldlfls= 1 and Eq. (3.17) can be readily int~ egrated. Applying IfIs.• = 21f1B and IfIs.d 21f1B + Vd£> we obtain the drain current as a function of the gate and drain voltages: Ids =f,/.e/f Cox yW { ( v:gs - Vjb -2If1BV-2d-s) Vds _ 2~ 3Cox [(2If1B + VdS )3/2_(2If1B)3/2]}. (3.22) Equation (3.22) represents the basic I-V characteristics of a MOSFET device based on the charge-sheet modeL It indicates that, for a given Vg£> the drain current Ids first increases linearly with the drain voltage Vds (called the linear or triode region), then gradually levels offto a saturated value (parabolic region). These two distinct regions are further examined below. 3.1.2.2 Characteristics in the Linear (Triode) Region When Vds is small, one can expand Eq. (3.22) into a power series in Vds and keep only the lowest-order (first-order) terms: Ids = f,/.e/fCox yW ( Vgs - VJb 21f1B J4es;QNaIflB) Cox Vds yW PeJJ Cox (Vgs - Vt)Vds , (3.23) where VI is the threshold voltage given by V= t Vlb + 21f1B + v!4es/qNaIflB Cox (3.24) Comparing this equation with Eq. (2.202), one can see that Vt is simply the gate voltage when the sUrface potential or band bending reaches 21f1B and the silicon charge (the square root) is equal to the bulk depletion charge for thatpotential. As a reminder, 21f1B (2kT/q) In(Na/n;), which is typically 0.6-0.9 V. When Vgs is below VI> there is very little current flow and the MOSFET is said to be in the subthreshold region, to be discussed in Section 3.1.3. Equation (3.23) indicates that, in the linear region, the MOSFET simply acts like a resistor with a sheet resistivity, Psh '" 11fpeff Cox (Vg.• V,)}, modulated by the gate voltage. The threshold voltage V, can be determined by plotting Ids versus Vgs at low drain voltages, as shown in Fig. 3.4. The extrapolated intercept ofthe linear portion of the IdsCVgs) curve with the Vgs-axis gives the approximate value of Vt. In reality, such a linearly extrapolated threshold voltage (Von) is slightly 3.1 long-Channel MOSFETs ..,. IE-2 a; 1Il -OJ) 0 1E-4 >. :£e 1E-6 ,.'! ..:il IE-8 157 0.8 0.6 ~ ~ ;.; "c ' e 0.4 -;., .J .::: ~0.2 ~ Figure 3.4. V",,=V, Typical MOSFET Ids - Vgs characteristics at low drain bias voltages. The same current is plotted on both linear and logarithmic scales. The dotted line illustrates the detennination of the linearly extrapolated threshold voltage, Von. higher than the "2If1B" Vt due to inversion-layer capacitance and other effects, as seen in Fig. 2.36 and further addressed in Section 3.1.6. Low-drain Ids(Vgs) curves are also used to extract the effective channel length of a MOSFET, which is discussed in Chapter 4. 3.1.2.3 Characteristics in the Parabolic Region For larger values of Vds, the second-order terms in the power series expansion of Eq. (3.22) are also important and must be kept. A good approximation to the drain current is then W( 2) ld' peffCox L (Vgs- Vt)Vds 2m' Vds , (3.25) where m = I + JesiqN~/4lf1B Cox (3.26) is a factor greater than one, which is related to the subthreshold slope and the body effect to be discussed in Subsections 3.1.3 and 3.1.4. Equation (3.26) can be converted to several alternative expressions by using Eq. (2.201) for the bulk depletion capacitance Cdm at 1fI. 21f1B: m I + Cdm 1 +3-lo-x. Wdm (3.27) The last expression follows from Cdm £:s;lWdm , = £:0)10 .0 and £:s/£:ox;::; 3. A graphical interpretation ofm is given in Fig. 3.5. At the threshold condition, IfIs =' 21f1B, the MOSFET acts like two capacitors, Cox and Cdm, in series as the inversion charge capacitance is still 158 3 MOSFET Devices :-1rCox --- ""1­ "'r8' w " AY+g"D+~.TQI i I _ ! - A Q • x Rgure 3.5. Incremental change of potential in a MOSFET due to a gate-voltage modulation near or below threshold. Grounding ofthe body anchored the potential on the bulk side of the depletion region where AIJI O. The potential drop across the oxide, (AQ1co;r)tox> is equivalent to (AQIc,i)[(c,!eox)tox]. The factor m is defined as AVgIAlI's, which equals (Wdrn + 3tox}/W<1m. negligible. The factor m equals .1.Vg,l.1.lf/s, where .1.lf/s is the incremental change ofsurface potential due to .1.Vgs> an incremental change of gate voltage. .1.Vgs induces sheet charge densities +.1.Q at the gate and -.1.Q at the far edge of the depletion region. They cause a field change of Mf t:.Q/esi in the silicon and .1.Q/eox in the oxide, which give rise to an incremental change of potential .1.\If(x) as shown in Fig. 3.5. Here, the oxide width is expanded tOesleox '" 3 times its physical width so there is no change of slope at the silicon-oxide interface. While Eq. (3.16) is only valid for uniform bulk doping, Eq. (3.17) is more generally valid for nonuniform doping profiles to be discussed in Section 4.2.2. Since 11m is a measure of the efficiency of the gate in modulating the surface potential, m should be kept close to one, e.g., between 1.1 and 1.4, in MOSFET design. Equation (3.25) indicates that as Vds increases, Ids follows a parabolic curve, as shown in Fig. 3.6, until a maximum or saturation value is reached. This occurs when Vds = Vdsa' (Vgs V,)/m, at which W(VgS - V,)2 Ids = It/sat PeffCox L 2m (3.28) Equation (3.28) reduces to the well-known expression for the MOSFET saturation current when the bulk depletion charge is neglected (valid for low substrate doping) so m"" 1. The dashed curve in Fig. 3.6 shows the trajectory of Vasal through the various .Ids - Vds curves for different Vgs. Because of the regional approximation, V'. = 2V'B + V, used in the derivation, Eq. (3.22) and therefore Eq. (3.25) are valid only for Vas ~ Vdsat' Beyond Vdsal> one must go back to the more general Eq. (3.21) coupled with Eq. (3.14). Since IJIs.d saturates at large Vas as depicted in Fig. 3.3, Ids stays constant at ldsal' independent of Vdsfor Vas?: Vasat. 3.1 Long-Channel MOSFETs 159 (Vdsa"ldsa') ~I ~s4'-. Agure 3.6. ,, I , Vgs3 '~"~.~ .S of! ,v , gs2 .... , / VgS! ". Drain voltage Long-channel MOSFET Ids -V Vdsa" the voltage at the pinch-offpoint remains at Vdfal and the current, given by JofL' lclsdy Jo("'., Ilef/W [-Qi(V)]dV, (3.30) stays the same apart from a slight decrease in L (to L'), as shown in Fig. 3.8. This phenomenon is called channel length modulation and will be discussed in association with short-channel MOSFETs in Section 3.2. Further insight into the MOSFET behavior at pinch-off can be gained by examining the function V(y). lntegrating from 0 to y after multiplying both sides ofEq. (3.8) by dy yields lV IdsY lleffW [-Qi(V)]dV Wl- m llejJCox (Vgs VI) V 2 (3.31 ) 160 3 MOSFET Devices -Qj(V) Cox(Ygs- VI) ""Ids """.,.." ........,.•.,. Figure 3.7. o Source Vd, Drain Vdsat V m Inversion charge density as a function of the quasi-Fermi potential of a point in the channel. Before saturation, the drain current is proportional to the shaded area integrated from zero to the drain voltage. where the simplified Qi(V), Eq.(3.29), has been used. Substituting Ids from Eq. (3.25) into Eq. (3.31), one can solve for V(y): t) f VgS - VI (_V~gS_;:_V~. 2 (Vgs;: VI) Vds + ~,. (3.32) m Both V(y) and -QlmCox=(Vg., -~)lm - V(y)are plotted in Fig. 3.9 for several values of Vd\:. At low Vd" V(y) varies almost linearly between the source and drain. As Vds increases, the inversion charge density at the drain decreases due to the lowering ofthe electron quasi-Fermi level. This is accompanied by a corresponding increase of dVldy to maintain current con­ tinuity. When Vel< reaches Vd,al=(Vgs - ~)lm, we have Qi (y=L)=O and V(y) exhibits a singularity at the drain, where dV/dy = 00. This implies that the electricfield in they-direction changes more rapidly than the field in the x-direction and the gradual channel approxima­ tion breab down. In other words, beyond the pinch-offpoint, carriers are no longer confined to the surface channel, and a 2-D Poisson equation must be solved for carrier injection from the pinch-off point into the drain depletion region (EI-Mansy and Boothroyd, 1977). Strictly speaking, if Vd, > 2'1'B, Eq. (3.22) cannot be expanded into a power series in Vds' A more general form of the saturation voltage is obtained by letting Qi = 0 in Eq. (3.16) with 'I'x 2'1'B + V and solving for V= Vdsal [equivalent to solving dlddVdx = 0 by differentiating Eq. (3.22)]: - Vjb - 2'1'B + s Nil (Vo V;n + e.;~~a). (3.33) ,, ox The corresponding saturation current can be found by substituting Eq. (3.33) for Vds in Eq. (3.22). The mathematics is rather tedious (Brews, 1981). A few selected curves are in Fig. 3.10 and compared with those calculated from (3.25). It turns out that Eq. (3.25) serves as a good approximation to the drain current over a much wider range of 3.1 long-Channel MOSFETs 161 Vss > VI p-Si oy Depletion region [aJ Vg,> V, Vds= Vdsal n+ p-Si ~p~ti~n-r~i~ny Vb., [b] Vg.,>V/ Vds>Vdm, fl+ p-Si -- _.- - - - Fi!lure 3.8. Vb, [e] (a) MOSFEToperated in the linear region (low drain Voltage). (b) MOSFET operated at the onset of saturation. The pinch-off point is indicated by Y. (c) MOSFEToperated beyond saturation where the channel length is reduced to L'. (After Sze, 1981.) 162 3 MOSFET Devices Figure 3.9. o Ol~ 'd.! Source L y~ Drain Quasi-Fenni potential versus distance between the source and the drain for several Vdr-valnes from the linear region to beyond saturation. The dashed curves show the corresponding variation of inversion charge density along the channel. The dotted curves help visualize the parabolic behavior of the characteristics. 0.6, Na=5x 1015cm-3 ~ 0.5 hox=200A. -g< 0.4 I ~ ~ 0.3 / ~ ~ 0.2[ / / V~~=5V Vgs=4V Vgs=3 V 1\1 "...­ Vgs=2V L __ ~ 2 3 4 5 Drain voltage Vg, (V) Figure 3.10. lds-Vds curves calculated from the full equation (3.22) (solid curves), compared with the parabolic approximation (3.25) (dotted curves). voltages than expected. Even for a drain voltage several times greater than 21VR. the current is only slightly (;::5%) underestimated. 3.1.2.5 pMOSFET /-VCharacteristics So far we have used an n-channel device as an example to discuss MOSFET operation an.d I-V characteristics. A p-channel MOSFET operates similarly, except that it is 3.1 Long-Channel MOSFETs 163 fabricated inside an n-well with implanted p+ source and drain regions (cf. Fig. 3.2), and that the polarities of all the voltages-and currents are reversed. For example, Idr- Vdr characteristics for a pMOSFET (cr. Fig. 3.10) have negative gate and drain voltages with respect to the source terminal for a hole current to flow froUl the source to the drain. Since the source of a pMOSFET is at the highest potential compared with the other . terminals, it is usually connected to the power supply Vdd in a CMOS circuit so that all the voltages are positive (or zero). In that case, the device conducts if the gate voltage is lower than Vdd - VI' where Vt( > 0) is the magnitude of the threshold voltage of the pMOSFET. The ohmic contact to the n-well is also connected to Vdt/, in contrast to an nMOSFET, where the p-type substrate is usually tied to the ground potential. This leaves the n-well-to-p-substrate junction reverse biased. More about nMOSFETand pMOSFET bias conditions in a CMOS circuit configuration will be given in Section 5.1. 3.1.3 Subthreshold Characteristics Depending on the gate and source-drain voltages, a MOSFET device can be biased in one of the three regions shown in Fig. 3.11. Linear (including parabolic) and saturation region characteristics have been described in the previous subsection. In this subsection, we discuss the characteristics ofa MOSFET device in the subthreshold region where Vgs < V,. In Fig. 3.4, the drain current on a linear scale appears to approach zero immediately below the threshold voltage. On a logarithmic scale, however, the descending drain current remains at nonnegligible levels for several tenths of a volt below V,. This is because the inversion charge density does not drop to zero abruptly. Rather, it follows an exponential dependence on If/s or Vg, as is evident from Eq. (3.11). Subthreshold behavior is of particular importance in low-voltage, low-power applications, such as in digital logic and memory circuits, because it describes how a MOSFET device switches off. The subthreshold region immediately below VI> in which fIIB ~ fils ~ 21f/B, is also called the weak inversion region. Vds ·· ,1 1 1,, Vgs-V, ~=-m- ,, , ,, /' ' : . Saturation ,,,,' : regIOn ,/ Sub-: / thresho1d : 1 region:,,, /" , ,, / ,/ !: , /,/ ,,11/' ,/ Linear and parabolic region V, Figure 3.11. Three regions of MOSFET operation in the Vd,-Vgs plane. 164 3 MOSFET Devices lE+Or.-------------------------------. Low drain lE-l ~ bias § lE-2 ~ lE-3 ! lE-4 §C lE-5 7...?.._.._ ..._..................1;._••••..•••••••­ :t \ Diffusion component .~ lE-6 o lE-7 lE-S' ., o 0.5 1.5 2 Gate voltage (V) Figure 3.12. Drift and diffusion components of current in an ldrVgs plot. Their sum is the total current represented by the solid curve. 3.1.3.1 Drift and Diffusion Components of Drain Current Unlike the strong inversion region, in which the drift current dominates, subthreshold conduction is dominated by the diffusion .current. Both current components are included in Pao and Sah's double integral, Eq. (3.13). In general, current continuity only applies to the total current, not to its individual components. In other words, the fractional ratio between the drift and the diffusion components may vary from one point of the channel to another. At low drain bias voltages, however, it is possible to separate the drift and diffusion components using the implicit Vls(V) relation, Eq. (3.14). When qV/kT« I, only the first-order tenns of V need to be kept. In Eq. (3.8), Q.(V) can be replaced by its zeroth-order value, Q.( V= 0); hence V must vary linearly from the source to the drain, as required by current continuity. Since the total current is proportional to dV/dy and the drift current is proportional to the electric field or dVi/dy, the drift fraction of the current is given by the change of surface potential (band bending) with respect to the quasi-Fenni potential, i.e., dVi/dV. This can be evaluated from Eq. (3.19) while making use ofEq. (3.14) in the limit of V-. 0: dVis (nT/ NDeq'l',/kT dV = 1+ (nrlN'la)eq'f/,/kT + (C;;xleSiqN,,) (IQsI/Cox) , (3.34) where IQsl /Cox is the voltage drop across the oxide given by the last term ofEq. (3.14). It is clear that in wcak inversion where 1J18 < Vis < 2V18, the numerator is much less than unity and the diffusion component dominates. Conversely, beyond strong inversion, dVl/dV;:::.\ and the drift current dominates. These kinds of behavior are further illustrated in Fig. 3.12. 3.1.3.2 Subthreshold Current Expression To find an expression for the subthreshold current, we note from Eq. (3.14) that the total charge density in silicon is, 3.1 Long-Channel MOSFETs 165 /2e = - Qs esi = kTN §I,._O [-QkVTls +~eq2('I',-VJ/kT] N'la 1/2 In weak inversion, the second tenn in the brackets arising from the inversion charge density is much less than the first tenn from the depletion charge density. Equation (3.35) can then be expanded into a power series: the zeroth-order term is identified as the depletion charge density -Qd by Eq. (3.15), and the first-order term gives the inversion charge density, (k!\ -Qi esiq N" (!!!...) 2eq('f/,- VJ/kT. 2V1s q-) Na (3.36) The surface potential Vis is related to the gate voltage through Eq. (3.14). Since the inversion charge density is small, Vis is a function of Vgs only, independent of V (the case of 1V in Fig. 3.3). This also means that the electric field along the channel direction is small; hence the drift current is negligible. Substituting Qi into Eq. (3.\0) and carrying out the integration, we obtain the drain current in the subthreshold region: _ w 1~(k1\ 2(!!!...)2eq'f/JkT(1 _ Ids - fJ..jJ L' 2VI, q-) Na (3.37) Vis can be expressed in tenns of Vgs using Eq. (3.14), where only the depletion charge tenn needs to be kept: Vgs / 2eSiq NaVis +\1.1,+ Cox (3.38) It is straightforward to solve a quadratic equation for Vis. To further simplify the result, we consider Vis as only slightly deviated from the threshold value, 2V18 (Swanson and Meindl, 1972). Using the concept of m = /::"Vg//::"lJIs in Fig. 3.5, one can approximate Vgs as V, + m(Vls-21J18)' Solving for Vis and substituting it into Eq. (3.37) yield the subthreshold current as a function of L' (k1\ W !esiQ Na = J1.ejJ 4V1B 2eq(V".­ e-QV,A/kT) , (3.39) Q-) . or W (k!\q) Itls =tletlCoxL(m I) 2 -e (3.40) 3.1.3.3 - Subthreshold Slope The subthreshold current is independent of the drain voltage once Vds is larger than a few kTlq, as would be expected for diffusion-dominated current transport. The dependence on gate voltage, on the other hand, is exponential with an inverse subthreshold slope (Fig. 3.12), 166 3 MOSFET Devices CdI"), S (d(IOglO Ids)) -1 = 2.3 mkT = 2.3 kT (I + dVgs q q Cox (3.41) of typically 70-100mV/decade. Here m= 1 +(Cdm/Cox) from Eq. (3.27). If the Si-SiOz interface trap density is high, the subthreshold slope may be more graded than that given by Eq. (3.41), since the capacitance associated with the interface trap is in parallel with the depletion-layer capacitance Cdm . It should be noted that for 'fIs substantially below 2'f1B, e.g., when Vgs is a few tenths ofa volt below V" Eq. (3.41) tends to underestimate the inverse subthreshold slope by 5-10%. As a result, the subthreshold current can be 2 to 4 times higher than that given by Eq. (3.40). For VLSI circuits, a steep subthreshold slope is desirable for the ease of switching the transistor current off. In MOSFET design, therefore, the gate oxide thickness and the bulk doping concentration should be chosen such that the factor m is not too much larger than unity, e.g., between l.l and 1.4. Nevertheless, the inverse subthreshold slope has a lower bound of 2.3 kTlq, or 60mVIdecade at room temperature, that does not change with device parameters. This has significant implications on device scaling as will be discussed in Chapter 4. 3.1.4 3.1.4.1 Substrate Bias and Temperature Dependence of Threshold Voltage The threshold voltage is one ofthe key parameters ofa MOSFET device. In this subsection, we examine the dependence of threshold voltage on substrate bias and temperature. Substrate Sensitivity (Body Effect) The drain-current equation in Section 3.1.2 was derived assuming zero substrate bias (Vb.,)' If Vb" t 0, one can modify the previously discussed MOSFET equations by considering that applying Vb., to the substrate is equivalent to subtracting all other voltages (namely, gate, source, and drain voltages) by Vbs while keeping the substrate grounded. This is shown in Fig. 3.13. Using the charge-sheet model with 'fIs = 2'f1B + Vas before, Eq. (3.\6) becomes Qi = -Cox(Vg, Vbs - V/b - 2'f1B - V) + ..j2ssiqNa(2'1'B + V), (3.42) where V is the reverse bias voltage between a point in the channel and the substrate. The current is obtained by integrating Qi from V = -ViM (source) to Vds - ViM (drain): ~ ~IS) Id, =P-e[fCoX { (Vgs - Vjb 2'f1s - Vd, -=--=::....-'C [(2'f1B - Vb., + - (2'f1B - Vh.J 3/2 ]}. (3.43) At low drain voltages (linear region), the current is still given by Eq. (3.23), except that the threshold voltage is now VI = + + 2VIB ...L--=::~"::'-':--'-"'---_-'- (3.44) 3.1 Long-Channel MOSFETs 167 -...e-·· Vds L n+ Drain ~ Vb, VgrVbs c±'" J 1 _ 1 -V. Vds- Vbs 7 \.____ _. fl+ Source n+ Drain ~ figure 3.13. Equivalent circuits used to evaluate the effect of substrate bias on MOSFET I-V characteristics. 3.1.4.2 It can be seen from Eq. (3.44) that the effect ofa reverse substrate bias (Vb. < 0) is to widen the bulk depletion region and raise the threshold voltage. Figure 3.14 plots Vt as a function of - Vbs' The slope of the curve, ' dVt ..jesjqNa/[2~2'f1B - Vbs)] = d( - Vbs) Cox (3.45) is referred to as the substrate sensitivity. At Vbs 0, the slope equals Cd,jCox, or m - I [Eq. (3.26)], The substrate sensitivity is higher for a higher bulk doping concentration. It is clear from Fig. 3.14 that the substrate sensitivity decreases as the substrate reverse bias increases. From Eq. (3.41), a reverse substrate bias also makes the subthreshold slope slightly steeper, since it widens the depletion region and lowers Cd",' Temperature Dependence of Threshold Voltage Next, we examine the temperature dependence of the threshold voltage. The flat-band voltage of an nMOSFET with n+ polysilicon gate is Vjb =- E/lq-'fIs [Eq. (2.209)J, assuming there is no oxide charge. Substituting it into Eq. (3.24) yields the threshold voltage, 168 3 MOSFET Devices 1.8 ~ 1.6 :::,.- Iii, 1.4 g "0 > 1.2 ;g 0 ~ "~" 0.6 0 2 4 6 8 10 Reverse substrate bias voltage, -Vb' (V) Figure 3.14. Threshold-voltage variation with reverse substrate bias for two uniform substrate doping concentrations. VI = - + VlB + J48s;qNaVlB Cox ' (3.46) at zero substrate bias. The temperature dependence of VI is related to the temperature dependence of Eg and VIa: (I dVt _2.. dEg + + Je.,;QNaIVlB) dVlB dT 2q dT Cox' dT 2.. dEg + (2m _ I) dVlB. 2q dT dT (3.47) dVlsldT sterns from the temperature dependence of the intrinsic carrier concentration, which can be evaluated using Eq. (2.48) and Eq. dVlB_~[kTln( ,No )] dT - dT q ..jNcNvrE./2kT ~ln(..jNcNv) _ kT d,flV;Ff;, +2.. dEg . q No q..jNcNv dT 2q dT (3.48) Since both Nc and Nv are proportional to TJ1L , we have d(N,}V,,) I12ldT '" ~ (N'}vv) 112/T. Substituting Eq. (3.48) into (3.47) yields + dVI -(2m _ I) ~ [In (.JNcNI') +~] m q No 2 q From Section 2.1.1 and Table 2.1, dEg'dT"'-2.7 x 10-4 cVIK and (NcHi12 '" 3 x 1019 cm-3• For Na~1O!6 cm') and m'" 1.1, dV/dT is typically -} mVIK. Note that the temperature coefficient decreases slightly as No increases: for No ~ 1018 cm-3 and m'" 1.3, dV/dTis about -0.7 mVIK. These numbers imply that, at an elevated temperature of, for example, 100°C, the threshold voltage is 55-75 mV lower than at room temperature. Since VLSI circuits often operate at elevated temperatures due to heat generation, this effect, 3.1 long-Channel MOSFETs 169 the degradation of subthreshold slope with temperature, causes the leakage current at Vgs=O to increase considerablY..o¥er its room-temperature value. Typically, the off­ state leakage current of a MOSFET at 100 bC is 30-50 times larger than the leakage current at 25°C. These are important design considerations, to be addressed in detail in Chapter 4. 3.1.5 3.1.5.1 MOSFET Channel Mobility The carrier mobility in a MOSFET channel is significantly lower than that in bulk silicon, due to additional scattering mechanisms. Lattice or phonon scattering is aggravated by the presence of crystalline discontinuity at the surface boundary, and surface roughness scattering severely degrades mobility at high normal felds. Channel mobility is also affected by processing conditions that alter the Si-Si02 interface properties (e.g., oxide charge and interface traps, as discussed in Section 2.3.6). Effective Mobility and Effective Normal Field In Section 3.1.1, the channel was taken out of the integral by defining an effective mobility as JO~I p.nn(x)dx P.eff = JO~i n(x)dx ' (3.50) which is essentially an average value weighted by the carrier concentration in the inversion layer. Empirically, it has been found that when Peff is plotted against an effective normal field 'f;eff' there exists a universal relationship independent of the substrate bias, doping concentration, and gate oxide thickness (Sabnis and Clemens, 1979). The effective normal field is defined as the average electric field perpendicular to the Si-Si02 interface experienced by the carriers in the channel. Using Gauss's law, one can express 1feffin terms of the depletion and inversion charge densities: 1 =8,; ( IQ"I+21' (3.5\) +! where IQ ­ eN- 103 '} 1~1 No (cm-3) , 71KoooooO'l.0~4P'b'b8. ... \\ 'I:l~~\\ o 000 • •• ",'"A.e.MXgg-,. \... : '"l'" ....... o 3.9x1015 • 2.0xl016 A 7.2xl016 ... 3.0x 1017 o 7.7x 1011 '"'" : ...""~\.• 18 2.4xl0 ""..... '1;.3 ~ ;'0'0"111:r .. oocrod~It"(i.j,j~\ 'I;; 300K .. ....0\. \ .. ...... \" o ... • • QI l Effective field '¥.jf(J!INlcm) Figure 3.15. Measured electron mobility at 300 and 77 K versus effective normal field for several substrate doping concentrations. (After Takagi et al., 1988). + q> VI 0.2 Vgs V, + ((J eff -"-=,--- 3to.. 6to.. (3.54) Equation (3.54) is valid for low drain voltages. At high drain voltages, Qj decreases toward the drain end of the channel. To estimate the average effective field-in that case, the second term in Eq. (3.54) should be reduced accordingly. 3.1.5.2 Electron Mobility Data w;j/ A typical set of data on mobility versus effective normal field for nMOSFETs is shown in Fig. 3.15 (Takagi et ai., 1988). At room temperature, the mobility follows a 3 dependence below 5 x 105 V/cm. A simple, approximate expression for this case is (Baccarani and Wordeman, \983) P-.jj ~ 32500 x (3.55) Beyond 'l:ejf "" 5 x 105 Vlcm, P-ejf decreases much more rapidly with increasing '$ejf because of increased surface roughness scattering as carriers are distributed closer to the surface under high nonnal fields. For each doping concentration, there exists an effective field below which the mobility falls offthe universal curve. This is believed to be due to Coulomb (or impurity) scattering, which becomes more important when the doping 3.1 Long-Channel MOSFETs 171 103 { .3 ~ 102 I r I-I Nd (c.m-3) ~~_I ~'tb_ ~ . CC-, 0°""~A, "• 300K : .. •••••• II' are degraded signifcantly at high gate voltages because of the decrease of mobility with increasing normal field. There is a point of maximum slope or linear transconductance about 0.5 V above the threshold voltage. It is conventional to define the linearly extrapolated threshold voltage, Von> by the intercept ofa tangent through this point. For a second-order correction in Vds based on Eq. (3.25), Von is obtained by subtracting mVdJ2 from the intercept. Because of the combined inversion­ layer capacitance and mobility degradation effects, the linearly extrapolated threshold voltage, Von. is typically (2-4)kTIQ higher than the threshold voltage VI at 'l'sCinv) =' 2'1'B. One should be careful not to mix up Von with V" which is used in Eq. (3.40) for estimating subthreshold currents. At Vgs Von, the extrapolated subthreshold current (along the same subthreshold slope in a semilog plot) is about lOx ofthat at Vgs = V,. This current is rather insensitive to temperature but does depend on the technology generation. The inversion layer capacitance in Eq. (3.62) was derived assuming classical density of states with Boltzmann statistics. The inversion layer is actually deeper than the classical value due to quantum effects (Section 4.2.4) which further degrade Qi from that of Eq. (3.63). It is a common practice to lump all these effects into a parameter called tiny by defining -dQ/dVgs = Cinv = eo)tinv• In general, tiny is a function of Vgs and is 5-10 A thicker than the physical tox. A split C-V measurement like that described in Fig. 2.39 is needed to separate the tim-factor from l1effiVgs) in Eq. (3.64). 3.2 Short-Channel MOSFETs It is clear from Section 3.1 that for a given supply voltage, the MOSFETcurrent increases with decreasing channel length. The intrinsic capacitance of a short-channel MOSFET is 176 3 MOSFET Devices 1.0 >: ~ .., 0.8 tIJ) 1E 0 0.6 :> '.0-.".''=".c". 0.4 f­ 0.2 nMOSFET 0""o0----/Z,..­ £' ! o Linear threshold, r.ls=O.l V "" Saturation threshold, ':1.. =3 V V 0 0 3 4 Lef! (flm) (a) 1.0 1 ~.., -0.8~ tIJ) ~'" -0.6 ;> "0 ].'"., -0.4 f-=- -0.2 pMOSFET 1·-­ o-,&,­ ~ 0 I0/ / 0 Linear threshold, r.ls=-O.l V Ii "" Saturation threshold, ':is =-3 V "bs=O V 0 0 3 4 Lef! (/lm) [b) Figure 3.19. Short-channel threshold rolloff: Measured low- and high-drain threshold voltages ofn- and p-MOSFETs versus channel length. (After Taur et al., 1985.) 3.2.1 also lower, which makes it easier to switch. However, for a given process, the channel length cannot be arbitrarily reduced even if allowed by lithography. Short-channel MOSFETs differ in many important aspects from long-channel devices discussed in Section 3.1. This section covers the basic features of short-channel devices that are important for device design consideration. These features are: (a) short-channel effect, (b) velocity saturation, (c) channel length modulation, (d) source- 2 assures acceptable short-channel effects. Because ofthe exponentialfactor, the threshold voltage rolloffwith channel length is very sensitive to W11m + 3tox, which can be defined as the scale length;' of the MOSFET. The criterion for the minimum channel length is then Lmin ::::: U. To scale a MOSFET to shorter channel lengths with acceptable short-channel effects, the scale length;' needs to be reduced accordingly. This means scaling down both Wdm and tox by the same factor as the channel length. Note that for a uniformly doped substrate, 4esikTln(Na/1!i) Wdm q2Na (3.68) from Eq. (2.190). Wdm is plotted in Fig. 3.25 versus Na. The above Wdm is that of a long-channel device, independent of L. This is a good z: approximation for ~ 2(Wdm + 3tox). For shorter channel lengths, W<1m tends to increase as L decreases (see Fig. 3.20). When that happens, 6V, does not increase as rapidly with decreasing L as indicated by the exponential faetor in Eq. (3.67). For L::::: 1.5(Wdm + 3t",), Eq. (3.67) with the long-channel Wdm tends to over estimate the threshold rolloffby a factor of:::::1.3 (Kannan, 2005). In aggressively scaled, high-performance CMOS logic technologies, Lmin is often pushed to :::::1.5(Wdm + 3tox). For L~ Wdm + 3tox, the assump­ tion that higher order terms in UL and UR series (Section A9.2) are negligible is no longer valid. Such devices have too severe a short-channel effect to be ofpractic&l use anyway. All of the above discussions assume that the source and drain junction depth, Xj, is larger than the depletion region width, Wdrn• It led to the result that V, rollotfis controlled 184 3 MOSFET Devices by Wdm , insensitive to the junction depth. This is also the technologically relevant case since in practice it is difficult to scale down the junction depth without degrading the device current due to increased series resistance. But if a MOSFET with Xj < Wdrn can be made (e.g., by raised source-drain process), V, rolloff will be linearly improved in proportion to x/Wdm (8leva and Taur, 2005). While analytical results like Eq. (3.67) give us key insights to the short-channel effect, in general short-channel device design is carried out with a. two-dimensional device simulator for more accurate results. Further details on channel profile and threshold design are discussed in Section 4.2. 3.2.1.5 Generalized Scale Length with High-,. Gate Dielectrics When the CMOS channel length is scaled to 20-30nm, gate oxides of::.::l nm thickness (Section 4.2.3) become necessary for control of short-channel effects. While a combina­ tion of improvement in process technology and better understanding of the breakdown process ofgate oxides (Section 2.5.6) has made this possible, gate tunneling currents can be unacceptably high for such atomically thin oxides (Fig. 2.62). This problem can be mitigated using high-permittivity (high·I<) dielectrics to replace 8i02 as gate insulators. From the normal field (in silicon) and gate capacitance point of view, a high-I< gate dielectric of permittivity G; and thickness 8i ti = -lox GoX' (3.69) is equivalent to an oxide layer of permittivity Gox and thickness tox. If 1, the physical thickness of the high-I< gate dielectric t; is much thicker than tax' thus signifi­ reducing the gate tunneling current (quantum mechanical tunneling has nothing to do with the dielectric constant of the material). [n practice, it is rather difficult to develop a high-I< gate insulator with acceptable characteristics for use in CMOS products. High-K gate insulator is currently one of the intensely researched subjects in the field ofVLSI. From the one-region scale length model, one would expect that A'" Wdm + (Bs/Bi)l; for high-I< gate dielectrics. However, that is correct only for Ii « Awhen the normal fields dominate. As both G; and ti increase by the same factor, I.e., at constant capacitance tangential fields become more important for which the high dielectric constant does not help. For arbitrary gate dielectric constant and thickness, it is necessary to apply the generalized two-region scale length model described in Appendix 10. By match- the boundary conditions for both the normal and the tangential fields at the silicon­ insulator interface, an eigenvalue equation for the scale length A is obtained [Eq. (A 10.7)]: '. tan(,lC..ti) +-I: tan (lC-W,(-bn) O. 3, A lis, A (3.70) This equation has an infinite number of solutions, in descending order of;t. The lowest order eigenvalue or the longest A dominates because the short-channel potential 3.2 Short-Channel MOSFETs 185 :::: 1 J08 a 0,6 li .~ 04 j.' Figure 3.26. ] 0.2 ] ~ 01 o ~ 0.2 0.4 0,6 0.8 Nonnalized Si depletion depth, 'Wcim IA. Numerical solutions to Eq. (3.70) for different values of o;lEisi. The dotted lines at the lower right comer depict the asymptotic solution behavior, ..1. '" Wdrn + (ss;lei)t" for li« Wdm• component is proportional to eXp(-nLI2A) as in the one-region model. Equation (3.70) cannot be solved in closed forms. The numerical solution for the longest .1. is shown in normalized units in Fig. 3.26 for several representative values of B;!Gsi' The significance 0/..1. remains that it dictates the minimum channel length, Lmln z 2A, as in the one-region case discussed before. The following characteristics of the solution to Eq. (3.70) are observed in Fig. 3.26. • J.?: Wdm and .1. ?: tl, I.e., ;t is larger than the larger of Wdm , ti. • In the special case ofei '" Gs;, 1 '" Wdm + fi' the physical height of the box in Fig. Al 0.1. • In the special case of Wdm "" ti,..1. '" 2Wdm = 2t;, regardless of lOb Gs;. • If I; « Wdm (lower right comer of Fig. 3.26), J. ::.:: Wdm + (GsIG;)ti' This is the approximate solution obtained in the one-region model. • If Wdm « t; (upper left comer of Fig. 3.26), 1 ~ t; + (B;!Bs;)Wdm. While Eq. (3.70) and thus Fig. 3.26 are symmetric with respect to ti and Wdm , consideration of 6.Vg./!1lJ1s or the m-factor in Fig. 3.5 requires that t;lGi < WdmIBs;' In other words, only the). solutions in the lower right comer of Fig. 3.26 are acceptable. In that region, high-K gate dielectric helps because J. ::.:: Wdm + (es;!B,)ti and for the same Wd",!J.;S 1, higher Gi IGs; allows a larger t; 11. However, because ofthe extreme nonlinearity of the curves for B/esi» I, the..1. solution quickly departs from the above one-region, linear approximation (dotted lines in Fig. 3.26) as t;l). increases. There exists a limit of :::: Va, or). 21;, where t; is physical thickness of the insulator no matter how high the dielectric constant is. Physically, this is caused by the lateral fields which, unlike the vertical fields, are not affected by the dielectric constant ofthe material (Section 2.1.4.2). In the devices with thick, very high-" gate insulators, the short-channel effect is domi­ nated by the latcral fields such that the scale length is determined mainly by the physical thickness of the film. 186 3 MOSFET Devices 3.2 Short-Channel MOSFETs 187 Notice that for e;lesi < 1, e.g., Si02, the curvature ofthe curve in Fig. 3.26 is opposite to those of e;les; > I. This means that 1 is somewhat lower (better) than the one-region approximation, Wdm + 3too;, as tox increases. 3.2.2.1 Velocity-Field Relationship Experimental measurements show 'iliat the velocity-field relationship for electrons and holes takes the empirical form (Caughey and Thomas, 1967) 3.2.2 Velocity Saturation and High-Field Transport flef! $' 11 [I +(~/$'crllln' (3.71 ) As discussed in Section 3.1.2, when the drain voltage increases in a long-channel MOSFET, the drain current first increases, then becomes saturated at a voltage equal to where n '" 2 for electrons and n '" 1 for holes. n (2': 1) is a measure of how rapidly the Vdsat '" Vt)/m with the onset ofpinch-offat the drain. In a short-channel device, the carriers approach saturation. The parameter ~c is called the critical field. When the field saturation ofdrain cu"ent may occur at a much lower voltage due to velocity satura­ strength is comparable to or greater than $'e,velocity saturation becomes important. At tion. This causes the saturation current I dsat to deviate from the IlL dependence depicted low fields, v'" flejJ$', which is simply Ohm's law. As ~ ...... 00, v = lIsat = flejJ ~e. Therefore, in Eq. (3.28) for long-channel devices. Velocity-field relationships in bulk silicon are plotted in Fig. 2.10. Saturation velocities ofelectrons and holes in a MOSFET channel are lower than their bulk values. vsat '" 7-8 x 106 cmls for electrons and Vsat '" 6--7 x cmls for holes have been reported in the literature (Coen and Muller, 1980; Taur et al., 1993a). Figure 3.27 shows the experimentally measured Ids - Vds curves of a 0.25-1JlIl nMOSFET. The dashed curve represents the long-channel-like current given by (3.28) for Vgs '" 2.5 V. Due to velocity saturation, the drain current saturates at a drain voltage much lower than (Vgs Vt)lm, thus severely limiting the saturation current of a short-channel device. Vsat (3.72) !-leff It was discussed in Section 3.1.5 that the effective mobility flejJis a function ofthe vertical (or normal) field Since Vsat is a constant independent of $'effi the critical field ~e is a function of ~ejJ as well. More specifically,for a higher verticalfield, the effective mobility is lower, but the criticalfieldfor velocity saturation becomes higher (Sodini et al., 1984). Similarly, holes have a critical field higher than that of electrons, since hole mobilities are lower. - - - - 0.016 ,.---...,----,--.,----,-----,..----. / Long-channel / behavior ~I I 0.012 <" -..:.".:., 0.008 / I I I / O.25-J.U11 I nMOSFET I I \ Vgs =2.5V I I ~2.0V ///" 0.004 I 1/1/ LI I 1.5 V 1.0 V 0.5V I 2 3 Vd.r(V) 3.2.2.2 An Analytical Solution for n= 1 It is more important to treat velocity saturation for electrons. However, the mathematics in solving the n = 2 case is rather tedious (Taylor, 1984). An insight into the velocity saturation phenomenon in a MOSFET can be gained by analyzing the n'" 1 case, which yields a sim,ple and continuous solution. Following similar steps to those in Section 3.1.1, one replaces the low-field drifivelocity, -!-lejJdVldy, in Eq. (3.8) with Eq. (3.71) to allow for high-field velocity saturation effects (n = 1): flef!dV/ dy . Ids WQi(V) 1+ (PeU/v.wt)dV/dy (3.73) Here Vis the quasi-Fermi potential at a point y in the channel, and Qi (V) is the integrated inversion charge density at that point. Note thatdVldy -'I> 0.3 Current continuity requires that Ids be a constant, independent ofy. Rearranging Eq. (3.73). one obtains Ids WQi(V) + fl~:'dS) dV. (3.74) MUltiplying by solves for Ids: both sides and integrating from y '" 0 to L and from V'" 0 to Vd." one Figure 3.27. Experimental I-V curves of a O.25-J.IIll nMOSFET (solid lines). The device width is 9.5 J.IIll. The dashed curve shows the long-channel-like drain current expected for this channel length if there were no velocity saturation. (After Taur et al., J993a.) 3 Strictly speaking, if: = -d'l'/dy. Above the threshold, the current is dominated by the drift component; hence d'tf;ldy and dVldy are interchangeable. 188 3 MOSFET Devices - PeJj(W/L) J:'" Qj (V) dV Ids = I + (Pef! Vds/VsaI L) . (3.75) The numerator is simply the long-channel current, Eq. (3.10), without velocity saturation. It is clear that ifthe "average" field along the channel, Vd,/L, is much less than the critical field = vsa/p.g; the drain current is hardly affected by velocity saturation. When Vd,/L becomes comparable to or greater than however, the drain current is significantly reduced. If one uses the approximate expression (3.29) in the regional charge-sheet model for Qi (fI), Qj(V) = -Cox {VgS - Vt mV), (3.76) the integration in Eq. (3.75) can be carried out to yield I Pef!CfJx(W/L) [(VgS - V,)Vds (m/2) V11 ds I + (PeffVds/Vsa,L) (3.77) For a given Vgs, Ids increases with Vds until a maximum cUITent is reached. Beyond this point, the drain current is saturated. The saturation voltage, Vdsat, can be found by solving dIasfdVds 0: 2(Vgs Vt}/m Vdsal /1 + + 2Pef!(Vgs - Vt)/(mvsatL) (3.78) This expression is always less than the long-channel saturation voltage, (Vgs Substituting Eq. (3.78) into Eq. (3.77), one finds the saturation current, Vi + 2Pef!(Vgs - Vt}/(mvsat L ) /1 I Idsu' Cox WVsat(Vgs - V,} -'r===========-- + 2Peff(Vgs - Vt)/(mvsa/L) + VtVm. (3.79) Example curves of Idsal versus Vgs VI are plotted in Fig. 3.28 for several different channel lengths. In the long-channel case, the solid curve calculated from Eq. (3.79) is not too different from the dashed curve representing the drain current without velocity saturation. In fact, it can be shown that Eq. (3.79) reduces to the long-channel saturation current [Eq. (3.28)], Idsat (3.80) when Vgs - Vt «mvsatLl2p.ejf As the channel length becomes shorter, the velocity­ saturated current (solid curves) is significantly less than that ofEq. (3.80) (dashed curves) over an increasing range of gate voltage. In the limit of L --> 0, Eq. (3.79) becomes the velocity-saturation-limited current, Idsat CoxWVsat(Vgs - VI), (3.81) as indicated by the straight line labeled L = 0 in Fig. 3.28. Note that Eq. (3.81) is independent of channel length L and varies linearly with Vgs - Vt instead of 3.2 Short-Channel MOSFETs 189 0.6 t.x=lOoA '[0.5 l i:i Q.4 ~ ~ 0.3 .~ ~ 0.2 d.8 0.1 -=--:r:::= oV......,;::::~ o I 2 3 Gate overdrive, Vgr V; (V) I I I I I I I I' .v 1-"" 4 5 Figure 3.28. Saturation current calculated from Eq. (3.79) versus Vgs - VI for several different channel lengths (solid curves). The dashed curves are the corresponding "long-channel-like" saturation currents calculated from Eq. (3.80), i.e., by letting VSaf -> 00 in Eq. (3.79). The L=O line represents the limiting case imposed by velocity saturation, Eq. (3.8l). quadratically as in the long-chan.nel case. This is consistent with observations of the experimental curves in Fig. 3.27. For very short channel lengths, the saturation voltage, Eq. (3.78), can be approximately by Vdsal = /2vsatL( Vgs VI)/mP,ef!' (3.82) which decreases with channel length. It is instructive to examine the charge and field behavior at the drain end ofthe channel when Vds = Vdsal' From Eq. (3.76), Qi(Y L) = -Cox(Vgs - VI - m Vd,at). (3.83) Substituting Vdsal from Eq. (3.78), one finds Qj(y = L) -CoAVgs Vt } 7=========--- (3.84) +1 Comparison with Eq. (3.79) yields Jd,at = -Wvsat Qi(Y L), i.e., the carrier drift velocity at the drain end of the channel is equal to the saturation velocity. From Eq. (3.73), this means that the lateral field along the channel, dVldy, approaches infinity at the drain. Just as in the long-channel pinch-off situation discussed in Subsection 3.1.2, such a singu­ larity leads to the breakdown of the gradual-channel approximation which assumed that the lateral field changes slowly in comparison with the vertical field. In other words, beyond the saturation point, carriers which are travelin.g at saturation velocity are no longer confined to the surface channel. Their transport must then be described by a 2-D 190 3 MOSFET Devices 1.2 r-----------~~---_. Piecewise !I -?:. "~O~8 1 ;> 0.6 r] 4 o :z: 0.2 2 3 4 Nonnalized field, J.l", ~/v"" figure 3.29. Velocity-field relationship of various velocity saturation models plotted in nonnalized units. The rate ofapproaching satllTIltion velocity differs in different models. Poisson equation. A key difference between pinch-off in long-channel devices and velocity saturation in short-channel devices is that in the latter case, the inversion charge density at the drain, Eq. (3.84), does not vanish. 3.2.2.3 n = co Velocity Saturation Model Other than the n = 1 velocity saturation model discussed above, analytical solutions also exist in the n = co case and a piecewise model depicted in Fig. 3.29. The steepest approach to Vsat is obtained by letting n-+oo in Eq. (3.71): v Ji.ejj'if; for 'if; < Vsat / Ji.ejj' (3.85) and V Vsat for 'if; > Vsat / Ji.ejf' (3.86) For v < Vsat, the current expression is the same as the long-channel result, Eq. (3.25). In this case, however, before Vd~ reaches the pinch-off value, (Vg.< - Vt)/m, carrier velocity at the drain end of the channel reaches v = Vsat and the current saturates. If this happens at Vdv = Vd\'at, then the saturated current is L 2' 2] Idsat = Ji.ejj Cox W [(Vgs Vt ) Vdsat - m Vlisat . (3.87) On the other hand, at the drain end of the channel, It/sat WQ;vsat WCoxVsat (Vgs - Vt (3.88) where (3.29) is used for Q;. Equating Eqs. (3.87) and (3.88) allows Vdsal to be solved: 3.2 Short-Channel MOSFETs 191 Vir (~;tr v:dsal Vgs m + V L t "sac -.-' (Vgs;;; + (3.89) Substituting Vdsa! back into Eq. (3.88) yields the saturation current, ~ I.., we., '., { (Vgs _ vtf + ( mLVsat)2 _ mLVsat}. Ji.ejf Ji.ejj (3.90) Just like the n = 1 case, Eq. (3.90) is also reduced to the long-channellirnit, Eq. (3.80), and the fully velocity saturated limit, Eq. (3.81), in the limits ofvsat"""'oo and L-+O, respectively. 3.2.2.4 APiecewise-Continuous Velocity Saturation Model It was mentioned before that while electrons behave like the n = 2 model, the analytic solution is too tedious to deal with. A piecewise continuous velocity saturation model was developed instead to approximate the n=2 characteristics (Sodini et al., 1984). At low to moderate fields, the velocity varies with the field like that of an n = 1 model except that Vsat is replaced with 2vsat. At high fields, the velocity saturates at Vsat once it is reached. In other words, = v Ji.e,r'if; IJ for 'if; < + 1 CJi.eff 'if;/2vsat) (3.91) and v = Vsat for $' > 2vsat/Ji.ef/' (3.92) The piecewise-continuous model is also shown in Fig. 3.29 (dotted curve). It has been adopted in various BSIM compact models for MOSFETs. Analytic expressions for the saturation voltage and current can be readily developed for the piecewise modeL Before saturation, the drain current is like that ofEq. (3.73) with Vsat replaced by 2v,at. Going through the same derivation as before, one obtains the Ids(Vds) results ofEq. (3.77) with Vsat replaced by In particular, at Vds Vdsat when the velocity at the drain reaches Vsab Ids Idsat, i.e., Ilisat = (W--/-LI )+[(VCgJSi.e-jf Vt)Vdsat - (m/2)Vwa?) Vdsat/2vsat L) (3.93) Idvat is also related to Vdsa' by Eq. (3.88) considering velocity saturation at the drain end of the channel. Vdsat is then solved by equating Eqs. (3.93) and (3.88): V (Vgs - Vt)/m lisat I + Ji.ejJ,Vgs - VI}/(2mvsat L)' (3.94) Substituting Vdsat into Eq' (3.88) yields the saturation current (Sodini et al., 1984), 192 3 MOSFET Devices PeffCo, (W/L){Vgs - V/)2/2m Idsa' = 1 + Peff(Vgs V/)/(2mvsatL ) . (3.95) Again, Eq. (3.95) is reduced to the long-channel limit, Eq. (3.80), and the fully velocity saturated limit, Eq. (3.81), in the limits ofvsat -+ 00 and L -+ 0, respectively. Owing to the piecewise-continuous nature of this model and the n = 00 model, the resulting1ds(Vds) curves are also piecewise-continuous. That is, IdsCV is zero in the satuiation region. In contrast, the drain current of a short-channel MOSFET can still increase slightly beyond the pinch-off or the velocity saturation point with a nonzero output conductance, as is evident from the experimental curves in 3.27. This arises because oftwo factors: the short-channel effect and channel length modulation. The short­ channel effect was discussed in Section 3.2.1; when the drain voltage increases beyond saturation in a short-channel device, the threshold voltage decreases, and therefore the drain current increases. In this subsection, we describe channel According to the one-dimensional model in the preceding subsection, the electric field along the channel approaches infinity at the saturation point. In practice, the field remains finite. However, its magnitude becomes comparable to the vertical field, so that the gradual-channel approximation breaks down and carriers are no longer confined to the surface channel. As the drain voltage increases beyond the saturation voltage VtIs"b the saturation point where the surface channel collapses begins to move slightly toward the source, as shown in Fig. 3.32. The voltage at the saturation point remains constant at Vdsal, independent of Vds. The voltage difference VeLsat is dropped across the region between the saturation point and the drain. Carriers injected from the surface channel into this region travel at saturation velocity until collected by the drain junction. The distance between the saturation point and the drain, referred to as the amount of channel length modulation by the drain voltage. Since the one-dimensional model is still valid between the source and the saturation point where the voltage remains at Vtlsat, the device acts as if its channel length were shortened by AL. The drain current is then obtained simply by replacing L with L - AL in Eq. (3.79). In the long-channel limit, this increases the drain current by a factor of (l bLILrl, i.e., Idsat Id, = 1 (bLIL)" (3.101) 196 3 MOSFET Devices Since M increases with increasing drain voltage, the drain current continues to increase in the saturation region. A 2-D device simulator is needed to numerically evaluate M for a given set of device parameters and bias conditions. 3.2.4 Source-Drain Series Resistance In the discussion of MOSFET current thus far, it was assumed that the source and drain regions were perfectly conducting. In reality, as the current flows from the channel to the terminal contact, there is a small voltage drop in the source and drain regions due to the finite silicon resistivity and metal contact resistance. In a long­ channel device, the source- V, applied to the gate and Vds applied to the drain. A high-field space-charge region is established in the silicon near the drain, as illustrated in Fig. 3.33. As the electrons drift towards the drain, they gain energy from the electric field in the space-charge region and become hot. The hot electrons can cause impact ionizatiori near the drain, or they can be injected into the gate insulator (see Section 2.5.4). The secondary holes from impact ionization contribute to a substrate current (Abbas, 1974). Substrate currents at drain voltages less than the silicon bandgap voltage have been observed, suggesting that some electrons can gain additional energy from electron-electron andlor electron-phonon collisions (Chung et al., 1990). Figure 3.34 is a typical plot ofthe channel current and substrdte current as a function of the gate voltage, in this case for an n-channel MOSFET with 0.25 pm channel length having a threshold voltage, VI> of about 0.4 V (Chang et al., 1992). Notice that the substrate current increases with the gate voltage in the subthreshold region, peaking at gate voltages between about VI and 2 VI, and then decreases with further increases in the gate voltage. This complex dependence on gate voltage can be understood as follows. The electrons available for initiating impact ionization, to first order, come from the drain current. At Vgs < V;, there is no surface inversion channel and the maximum electric field in the silicon near the drain end is relatively independent of the gate voltage. As a result, the substrate current is roughly proportional to the drain current, as can be seen in Fig. 3.34. At Vgs > V" a surface inversion channel is formed. As discussed in Sections 3.1.2.3 and 3.1.2.4, for Vgs small compared with Vas> the surface channel is pinched off near the drain end. [Pinch ofIoccurs for Vas> Vdsa' (Vgs - V,)/m, where m is given by Eq. (3.27).] When the surface inversion channllUspinched off, there is a voltage drop Vdsat (drain saturation voltage) along the inversion channel between the source and the pinch-offpoint, and a voltage drop Vds Vdsa' in the space-charge region between the pinch-off point and the drain. That is, the maximum electric field in the silicon 198 3 MOSFET Devices IE-2 IE--4 Channel current $ IE-6 ~" u::! lE-8 Su bstrate current IE-IO 1E-12 LI_LL---L_"---L --0.5 0 0.5 1.5 2 2.5 Gate voltage (V) Figure 3.34. Typical plots of the channel current and substrate current of a MOSFET. The example shown here is for an n-channel FET having 0.25 !llIl channel length and IO!llIl channel width. (After Chang et al., 1992.) space-charge region is detennined by Vds - Vdsat. For a given V.m as Vgs increases, so does Vd.•a" which means the voltage drop Vds - Vdsat decreases hence the maximum electricjield in the silicon decreases. As shown in Fig. 2.59, the rate ofimpact ionization decreases rapidly with decrease in electric field. The net result is that the substrate current decreases with increasing gate voltage for larger than about 2 V;, as seen in Fig. 3.34. The reader interested in detailed models for the substrate current in a MOSFET is referred to the literature (e.g., Hu et al., 1985, and Kolhatkar and Dutta, 2000). The hot electrons injected into the gate insulator near the drain region contribute to a gate current. The gate current can cause bulk and interface traps to be generated (see Section 2.5.3.3), and some of the injected electrons can become trapped in the gate insulator near the drain. The trappe<;l electrons and the interface states cause the surface potential near the drain to shift. Since the source of the hot electrons is the channel current, this device degradation is referred to as channel hot electron (eHE) effect. The tum on characteristics of a MOSFET are detennined primarily by the surface potential near the source end of the channel (see Section 3.1.2). With the damage localized near the drain junction, a MOSFET that has suffered significant CHE damage shows a larger damage­ induced threshold voltage shift when it is operated in the source--drain-reversed mode than in the nonnal mode (Abbas and Dockerty, 1975; Ning et al., I977b). In the case of a p-channel MOSFET, the same device degradation is referred to as channel hot hole effect. In certain circuit configurations, the tenninal voltages of a MOSFET are such that V ~" 2.0 1.0 2 4 6 Drain bias (V) Figure 3.35.. Example Ids - Vds curves ofa short-channel nMOSFET showing breakdown at high drain voltages. (After Sun et ai., 1987.) is this stress mode, the device degradation or NBTI by itself relatively insensitive to channel length. However, a pMOSFET in the off state in a CMOS circuit typically has a relatively large voltage between its source and drain. Therefore, the device degradation experienced by a short-channel pMOSFET is often caused by a combination of channel hot hole effect and NBTl (La Rosa et al., 1997). NBTI must be characterized for each technology so its effect can be included in the design of circuits, particularly for CMOS circuits that depend on good matching of the threshold voltage ofp-channel MOSFETs (Rauch III, 2002). An excellent review of the current understanding of the physical mechanisms of NBTI in modem CMOS devices has been given by Schroder and Babcock (Schroder and Babcock, 2003). 3.2.5.3 MOSFET Breakdown Breakdown occurs in a short-channel MOSFET when the drain voltage exceeds a certain value, as shown in Fig. 3.35. At high drain voltages, the peak electric field in the saturation region can attain large values. When the field exceeds mid-I ri' Vkm, impact ionization (Section 2.5.1) takes place at the drain, leading to an abrupt increase of drain current. The breakdown voltage of nMOSFETs is usually lower than that of pMOSFETs because electrons have a higher rate of impact ionization (Fig. 2.59) and because n+ source and drain junctions are more abrupt than p+ junctions. There is also a weak dependence of the breakdown voltage on channel length; shorter devices have a lower breakdown voltage. The breakdown process in an nMOSFET is shown schematically in 3.36. Electrons gain energy from the field as they move down the channel. Before they lose energy through collisions, they possess high kinetic energy and are capable ofgenerating secondary electrons and holes by impact ionization. The generated electrons are attracted Exercises Impact ionization , 201 current ~"~ fs~~stra,e _I Figure 3.36. Schematic diagram showing impact ionization at the drain. to the drain, adding to the drain current, while the holes are collected by the substrate contact, resulting in a substrate current. The substrate current in turn can produce a voltage (IR) drop from the spreading resistance in the bulk, which tends to forward-bias the source junction. This lowers the threshold voltage of the MOSFET and triggers a positive feedback effect, which further enhances the channel current. Substrate current (Fig. 3.34) is usually a good indicator of hot carriers generated by low-level impact ionization before runaway breakdown occurs. Breakdown often results in permanent damage to the MOSFET as large amounts of hot carriers are injected into the oxide in the gate-to-drain overlap region. MOSFET breakdown is particularly a problem for VLSI technology during the elevated-voltage bum-in process. It can be relieved to some extent by using a lightly doped drain (LDD) structure (Ogura el al., 1982), which introduces additional series resistance and reduces the peak field in a MOSFET. However, drain current and therefore device performance are traded off as a result Ultimately, the devices should operate at a power-supply voltage far enough below the breakdown condition. This is one of the key CMOS design considerations in Chapter 4. Exercises 3.1 Consider an n-channel MOSFET with 20 nm thick gate oxide and uniform p-type substrate doping of 1017 cm-3• The gate work function is that ofn+ Si. (a) What is the threshold voltage? Sketch the band diagram at threshold condition, IPs 21PB' What is the threshold voltage if a reverse bias of 1 V is applied to tile substrate? Sketch the band diagram at threshold. (c) What is the scale length of this device and how short can the channel length be reduced to before severe short-channel effect takes place? 202 3 MOSFET Devices 3.2 Fill in the steps that lead to Eq. (3.34), the fraction ofdrift current component in the limit of V->O. 3.3 The effective field 'iffejJ·plays an important role in MOSFET channel mobility. Show that the definition 'iff J;'n(x)'iff(x)dx err Jo'" n(x)dx leads to Eq (3.51), I.e., 'iCejf = (lQdl + IQ;l/2)/8s;. Note that IQ,I q L<' n(x) dx and t, dx') 'iC(x) = ~ GSl (IQdl + q Jx n(x') from Gauss's law. The inversion-layer depth Xi is assumed to be much smaller than the bulk depletion width. 3.4 An alternative threshold definition is based on the rate ofchange of inversion charge density with gate voltage. Equation (3.61) from Fig. 2.37(b) states that dlQMdVgs is given by the serial combination of Cox and Ci == dlQ,I/dlPs' Below threshold, Cj « Cox, so that dlQ;jjdVgs R:: Ci and Qi increases exponentially with Vgs. Above threshold, C;» Cox> so that dlQ;I/ dVgs R:: Cox and Qj increases linearly with Vgs' The change of behavior occurs at an inversion charge threshold voltage, V/nv, where Cj""Cox' Show that at Vgs = v;nv one has dlQ;jjdVgs = Cox/2 and Qi R:: (2kT/q)Cox. Note that such an inversion charge threshold is independent of depletion charge and is slightly higher than the conventional 2IPs threshold. !~ 3.5 From Eq. (3.63) (neglecting the second term from inversion charge capacitance), show that the fractional loss of inversion charge due to the polysilicon depletion effect is AQ;/Qi R:: Cox /2Cp where Cp is the small-signal polysilicon-depletion capacitance defined in Eq. (2.212). Explain why there is a factor-of-two difference between the loss of charge and the loss of capacitance. 3.6 For an nMOSFET with tax"" 10 nm,. ,ueff"" 500cm2N-s, Vsat and L "" I ,urn, assume m "" I. 107 em/s, W"" IOpm, (a) Use the n = J velocity saturation model to generate Ids versus Vds (0-5 V) curves for Vgs - Vt "" 1, 2, 3,4, and 5 V. (Note: Id.' = Id.vol beyond Vdsat.) (b) Now let L vary from 0.5,um to 5,urn. Calculate and plot the saturation current for Vgs - VI = 3 V vs. L. Compare it with the long-channel saturation current (with­ out velocity saturation) for the same Vgs - VI and range ofL. 3.7 The small-signal transconductance in the saturation region is defined as gmsal=dld.w/dVgs' Derive an expression for g""a/ using Eq. (3.79) based on the n = 1velocity saturation model. Show that gmast approaches the saturation-velocity­ limited value, Eq. (3.96), when L -> O. What becomes of the expression for gmast in the long-channel limit when usa/->co? Exercises 203 3.8 From Eq. (3.79) based on the n= 1 velocity saturation model, what is the carrier velocity at the source end.ofthe channel? What are the limiting values when L---.O and when Usat~? 3.9 Following a similar approach as in the text for the n = 1velocity saturation model, derive an integral equation for the n = 2 velocity saturation model from which Ids can be solved. It is very tedious to carry out the integration analytically (Taylor, 1984). Interested readers may attempt performing it numerically on a computer. 3.10 Assuming the n = 1velocity saturation model, show that the total integrated inver­ sion charge under the gate is Qi(total) = -WLCox(Vgs ­ VI + 21leffi Vgs - Vt)/(mvsat L) +! VI + 2,ue/J,.Vgs - Vt)/(mvsat L) + 1 in the saturation region. Evaluate the intrinsic gate-to-channel capacitance, and show that it approaches Eq. (3.60) in the long-channellimit. 3.11 The generalized MOSFET scale length is given by Eq. (3.70). For esj = 11.7eo, ej= 7.8 £'0, t,= 5.0nm, and Wdm 1O.0nm, find the three longest eigenvalues AJ, A2, A3' Take V-.:: 2AI; what's the ratio between exp(--nLI2AI) and exp(--nL/2A.2)? 4 CMOS Device Design This chapter examines the key device design issues in a modern CMOS VLSI techno­ logy. It begins with an extensive review of the concept of MOSFET scaling. Two important CMOS device design parameters, threshold voltage and channel length, are then discussed in detail. 4.1 MOSFET Scaling CMOS technology evolution in the past thirty years has followed the path of device scaling for achieving density, speed, and power improvements. MOSFET scaling was propelled by the rapid advancement of lithographic techniques for delineating fine lines of 1 !Jl11 width and below. In Section 3.2.1, we discussed that reducing the source-ta-drain spacing, i.e., the channel length of a MOSFET, led to short-channel effects. For digital applications, the most undesirable short-channel effect is a reduction in the gate threshold voltage at which the device turns on, especially at high drain voltages. Full realization of the benefits of the new high-resolution lithographic techniques therefore requires the development ofnew device designs, technologies, and structures which can be optimized to keep short-channel effects under control at very small dimensions. Another necessary technological advancement for device scaling is in ion implantation, which not only allows the formation of very shallow source and drain regions but also is capable of accurately introducing a sharply profiled, low concentration of doping atoms for opti­ mum channel profile design. 4.1.1 Constant-Field Scaling In constant-field scaling (Dennard et al., 1974), it was proposed that one can keep short-channel effects under control by scaling down the vertical dimensions (gate insulator thickness, junction depth, etc.) along with the horizontal dimensions, while also proportionally decreasing the applied voltages and increasing the substrate 4.1 MOSfET Scaling 205 Original device I Ga~ll LV l n+) f,,-·· fl+ -) I \ \ source /' "\ I \ tax tdrain : I ,..... ,,\ I -------~', ~f) ,," ..... - ---i -- .,.,.." L~ Scaled device d tv/I!: JVlI!: \\.. 1'1+ ).::t\.. n+] I \ .... --~/' \ UK.... ~--"I Doping I!:N. p substmte. doping No Figure 4.1. Principles of MOSFET constant-electric-field scaling.. (After Dennard, 1986.) doping concentration (decreasing the depletion width), This is shown schematically in Fig. 4.1. The principle of constant-field scaling lies in scaling the device voltages and the device dimensions (both horizontal and vertical) by the same factor, K (> J), so that the electric field remains unchanged. This assures that the reliability of the scaled device is not worse than that of the original device. 4.1.1.1 Rules for Constant-Field Scaling Table 4.1 shows the scaling rules for various device parameters and circuit performance factors. The doping concentration must be increased by the scaling factor I(, in order to keep Poisson's equation (3.66) invariant with respect to scaling. The maximum drain depletion width, WD= 2esi(lflbi + Vdd ) qNa (4.1) from Eq. (2.85) (with Vapp=-Vdd) scales down approximately by I(, provided that the power-supply voltage Vdd is much greater than the built-in potentiallflbi' All capacitances (including wiring load) scale down by 1(" since they are proportional to area and inversely proportional to thickness. The charge per device (~C x V) scales down by 1(,2, while the inversion-layer charge density (per unit gate area), Q;, remains unchanged after scaling. Since the electric field at any given point is unchanged, the carrier velpcity (v=p ~) at any given point is also unchanged (the mobility is the same for the same vertical field). Therefore, any velocity saturation effects will be similar in the original and the scaled devices. The drift current per MOSFET width, obtained by integrating the first term of the electron current density equation (2.54) over the inversion layer thickness, is 206 4 CMOS Device Design Table 4.1 Scaling MOSFET device and circuit parameters Scaling assumptions MOSFET Device and Circuit Parameters Multiplicative Factor (K >1) Device dimensions (tox, L, Iv, Xj) Ih, Doping concentration (Na, Nd) IC Voltage (V) lIIC Derived scaling Electric field (~ behavior of device Carrier velocity (v) parameters Depletion-layer width (Wd) 11K Capacitance (e~e Alt) 11K Inversion-layer charge density (Qi) I Current, drift (I) 11K Channel resistance (Rch) Dervied scaling Circuit delay time (r ~ eVIl) 11K behavior of circuit Power dissipation per circuit (P ~ VI) 1112 parameters Power-delay product per circuit (P r) II..,) Circuit density ('" IIA) ,2 Power density (PIA) -- ldrifi Q,V Qjfl'l:, W (4.2) and is unchanged with respect to scaling. This means that the drift current scales down by K, consistent with the behavior of both the linear and the saturation MOSFET currents in Eq. (3.23) and Eq. (3.28). A key implicit assumption is that the threshold voltage also scales down by K. Note that the velocity saturated current, Eq. (3.79), also scales the same way, since both V sat and /1effare constants, independent ofscaling. However, the diffusion current per unit MOSFET width, obtained by integrating the second term of the current density equation (2.54) and given by IdifJ _ D dQ; _ kT dQ; W- n dx -flnqdX' (4.3) scales up by K, since dQ;ldx is inversely proportional to the channel length. Therefore, the diffusion current does not scale down the same way as the drift current. This has significant implications in the nonscating of MOSFET subthreshold currents, as will be discussed in Section 4.1.3. 4.1.1.2 Effect of Scaling on Circuit Parameters With both the voltage and the current scaled down by the same factor, it follows that the active channel resistance [e.g., Eq. (3.102) ] of the scaled-down device remains unchanged. It is further assumed that the parasitic resistance is either negligible or unchanged in scaling. The circuit delay, which is proportional to RC or CVIl, then scales 4.1 MOSFET Scaling 207 down by K. This is the most important conclusion ofconstant·field scaling: once the device dimensions and the power-supply voltage are scaled down, the circuit speeds up by the same factor. Moreover, power dissipation per circuit, which is proportional to VI, is reduced by K. Since the circuit density has increased by 7l-, the power density, i.e., the active power per chip area, remains unchanged in the scaled-down device. This has important technological implications in that, in contrast to bipolar devices (Chapters 6, 7, and 8), packaging of the scaled CMOS devices does not require more elaborate heat-sinking. The power-delay product of the scaled CMOS circuit shows a dramatic improvement by a factor of.,.! (Table 4.1). 4.1.1.3 Threshold Voltage It was assumed earlier that the threshold voltage should be decreased by the scaling factor, K, in proportion to the power-supply voltage. This is examined using the threshold equation (3.44) for a uniformly doped substrate: V = Vfb + 2'11B + ..j2€SiqN'a(2'11B - Vb,) t Cox (4.4) where Vbs is the substrate bias voltage. In silicon technology, the material-related parameters (energy gap, work function, etc.) do not change with scaling; hence, in general, V, does not scale. However, in a conventional process, n+.polysilicon gates are used for n-channel MOSFETs, and Vjb=-Egl2q -'liB from Eq. (2.209). It turns out that the first two terms on the RHS ofEq. (4.4) add up to approximately -- will also scale down by K. However, at very early stages of the technology development, Vbs has been reduced to zero for most logic applications, though a reverse-biased body-source junction is still used for some dynamic memory array devices. Further reduction of the 2'110- Vbs term with scaling would require a forward bias on the substrate. This is not commonly used in VLSI technologies, although it has been attempted in experimental devices (Sai-Halasz et al., 1990). In practice, nonuniform doping profiles have been employed to tailor the threshold voltage of scaled devices, as will be discussed in Section 4.2. p·channel MOSFETs with p+-polysilicon gates scale similarly to their counterparts. However, in buried-channel devices, e.g., when an n+-polysi!icon gate is used for p-channel MOSFETs, the sum ofthe first two terms in Eq. (4.4) is nearly 1V (magnitude) and therefore cannot be neglected. For this reason, it is difficult to scale buried-chaI'\nel devices to low threshold voltages. More about threshold voltage design can be found in Section 4.2. 4.1.2 Generalized Scaling Even though constant-field scaling provides a basic guideline to the design of scaled MOSFETs, the requirement of reducing the voltage by the same factor as the device 208 4 CMOS Device Design 4.1 M()SFET Scaling 209 Table 4.2 CMOS VlSI technology generations Feature size (1lll1) 2 1.2 0.8 0.5 0.35 0.25 0.1 Power-supply voltage (V) 5 5 5 3.3 3.3 2.5 1.5 Gate oxide t1iickness (A) 350 250 180 120 100 70 30 Oxide field (MY/em) 1.4 2.0 2.8 2.8 3.3 3.6 5.0 Table 4.3 Generalized MOSFET scaling '. MOSFET device and circuit parameters Scaling assumptions Derived scaling behavior of device parameters Device dimensions (to,<> L, W; Xj) Doping concentration (Na, Nd) Voltage (V) Electric field (~) Depletion-layer width (Wd) Capacitance (C=1i Ait) Inversion-layer charge density (QI) Multiplicative factor (K > I) LongCh. 11K aK alK a III( 11K a Vel. Sat. physical dimension is too restrictive. Because of subthreshold nonscaling and reluctance Carrier velocity (v) Current, drift (l) a a2 I" al" to depart from the standardized voltage levels of the previous generation, the power­ supply voltage was seldom scaled in proportion to channel length. Table 4.2 lists the supply voltage and device parameters ofseveral generations ofCMOS VLSI technology. It is clear that the oxide field has been increasing over the generations rather than staying constant. For device design purposes, therefore, it is necess,ary to develop a more general Derived scaling behavior of circuit parameters Circuit delay time (r - CV/l) Power dissipation per circuit (P - Vl) Power-delay product per circuit (P r) Circuit density (0< IIA) Power density (PIA) lIa" a3 /K2 (J? 111( a2 /,,2 a,,22 1T2 a2 set of guidelines that allows the electric field to increase. In such a generalized scaling (Baccarani et ai., 1984), it is desired that both the vertical and the lateral electric fields change by the same multiplication factor so that the shape of the electric field pattern is preserved. This asS1,II'eS that 2-D effects, such as short-channel effects, do not become worse when scaling to a smaller dimension. Higher fields, however, do cause reliability concerns as mentioned in Section 2.5. Below 0.1 !lII1 feature size, CMOS design space is severely constrained by power issues. Details of the performance-power tradeoff are current, which is proportional to WQjV, will then change by a factor of (ill(. This is consistent with the scaling behavior oflong-channel currents, Eq. (3.23) and Eq. (3.28). On the other hand, if the original device is fully velocity-saturated, the carrier velocity cannot increase any more, in spite of the higher field in the scaled device. The current in this case will change only by a factor of WI(, consistent with the velocity-saturated current, Eq. (3.81). The circuit delay scales down by a factor between I( and (J.1(, discussed in Section 4.2.2.2 with the key parameters summarized in Fig. 4.7. depending on the of velocity saturation. The most serious issue with generalized scaling is the increase ofthe power density by a factor ofa2 to (.13. This puts a great burden 4.1.2.1 Rules for Generalized Scaling Ifwe assume that the electric field intensity changes by a factor ofa, Le., 'if -> a 'if, while on VLSI packaging technology to dissipate the extra heat generated on the chip. The power.... I) in generalized scaling, the potential or voltage will change by a factor equal to the ratio WI(. Ifa= \, it reduces back to constant-field scaling. To keep Poisson's equation invariant under the transformation, (X, y) -> (x, Y)/I( and'll (WI()'11 within the depletion region, a2(a'll/"') qN~ + = - , --'''-'-.:'-='- 2 (4.5) a(y/",) csi 4.1.2.2 Constant-Voltage Scaling Even though Poisson's equation within the depletion region is invariant under general­ ized scaling, the same is not true in the inversion layer when mobile charges are present. This is because mobile charge densities are exponential functions of potential which do not scale linearly with either physical dimensions or voltage. Furthermore, even in the depletion not all the boundary conditions scale consistently under generalized N~ should be scaled to (a I()Na. In other words, the doping concentration must be scaled up by an extra factor of a to control the depletion-region depth and thus avoid increased short-channel effects due to the higher electric field. Table 4.3 shows the generalized scaling rules of other device and circuit parameters. . Since the electric field intensity is usually increased in generalized scaling, the carrier scaling. Thi.... is due to the fact that the band bending at the sourcejunction is given by the built-in potential (Appendix 9), which does not scale with voltage. Strictly speaking, the shape of the field pattern i..~ preserved only if a. =K, i.e., constant-voltage scaling. Under constant-voltage scaling, the electric field scales up by I( and the doping concentra­ tion No scales up by x? The maximum gate depletion width (long-channel) [Eq. (3.68)], velocity tends to increase as well. How much the velocity increases depends on how velocity-saturated the original device is. In the long-channel limit, carrier velocities are .~ far from saturation and will increase by the same factor, a, as the electric field. The drift -tl 4csikTln(N,,/ni) Wd", = q2Na (4.6) 210 4 CMOS Device Design 4.1 MOSFET Scaling 211 4.1.3 4.1.3.1 then scales down by 1(. Here In(NJnj} is a weak function of Na and can be treated as a constant. This allows the short-channel Vt rolloff [Eq. (3.67)], w:: Je- ~V, 24t [Vlflbi(lfIbi + Vds) - a(2If1B) .-!'.Y2.... Wdm+3Iax , (4.7) to remain unchanged, as both tox and Wdm are scaled down by the same factor as the channel length L. Both the power-supply voltage and the threshold voltage [Eq. (4.4)], V, Vjb + 2 IfIB + y'2f:s;qNa(2If1B C - Vb.) ' ox (4.8) also remain unchanged. From Eq. (2.194), the inversion-layer charge per unit area is related to the electron concentration at the silicon surface, nCO), by Qi y'2f:sikTn(0). (4.9) Since Qj scales up by I( in constant-voltage scaling, nCO) scales up by'? Therefore, the mobile charge density scales the same way as the fixed charge density Na. The inversion­ layer thickness, being proportional to Q;lqn(O), scales down by I( just like other linear dimensions. The Debye length, LD=(8sikT/q2Na)1I2, also scales down by I( under constant-voltage scaling. Although constant-voltage scaling leaves the solution of Poisson's equation for the electrostatic potential unchanged except for a constant mUltiplicative factor in the electric field, it cannot be practiced without limit, since the power density increases by a factor of ,? to '? Higher fields also cause hot-electron and oxide reliability problems. In reality, CMOS technology evolution has followed mixed steps ofconstant-voltage and constant­ field scaling, as is evident in Table 4.2. threshold voltage is held unchanged, the offcurrent per device still increases by a fact"OT of I( (from the Cox factor) when. the-physical dimensions are scaled down by 1(. This imposes a serious limitation on how low the threshold voltage can be, especially in dynamic circuits and random-access memories. The threshold voltage limitation in tum sets a lower limit on the power-supply voltage Vdd, since the circuit delay increases rapidly with the ratio V1/Vdd, as will be discussed in Section 4.2.1.3. Another nonscaling factor related to kT/q is the inversion-layer thickness, which is unchanged in constant-field scaling. Since the inversion-layer capacitance arising from the finite thickness is in series with the oxide capacitance, the total gate capacitance per unit area ofthe scaled device increases by a factor less than I( (Baccarani and Wordeman, 1983). This degrades the inversion charge density and therefore tbe current, especially at low gate voltages, as can be seen from (3.62). Because both the junction built-in potential [Eq. (2.84)] and the maximum surface potential [Eq. (2.183)] are in the range of 0.6-1.0 V and do not change significantly with device scaling, the depletion-region widths, Eq. (4.1) and Eq. (4.6), do not scale quite as much as other linear dimensions. This results in worse short-channel effects in the scaled MOSFET, as is evident from Eq. (4.7). To compensate for these effects, the doping concentration must increase more than that suggested by constant-field scaling or gener­ alized scaling. 4.1.3.2 Secondary Nonscaling Factors Because of subthreshold nonsealing, the voltage level cannot be scaled down as much as the linear dimensions, and the electric field has increased as a result. This triggers several secondary nonscaling effects. First, in our discussions so far, it was implicitly assumed that carrier mobilities are constant, independent of scaling. However, as discussed in Section 3.1.5, the mobility decreases with increasing electric field: Nonscaling Effects Peff ~ 32500~-e1j]/3 , (4.11) Primary Nonscaling Factors in units ofcm2N-s for 5 x 105 V/cm. Beyond '$eff-=5 x 105 Vlcm, the mobility From the above discussions, it is clear that although constant-field scaling provides a decreases even faster due to surface roughness scattering (Fig. 3.15). Since it is basic framework for shrinking CMOS devices to gain higher density and speed without inevitable that the electric field increases with scaling, carrier mobilities are degraded degrading reliability and power, there are several factors that scale neither with the in scaled MOSFETs. As a result, both the current and the delay improve less than the physical dimensions nor with the operating voltage. The primary reason for the non­ factors listed in Table 4.3 for generalized scaling. Furthermore, higher fields tend scaling effects is that neither the thermal voltage kT/q nor the silicon bandgap Eg to push device operation more into the velocity-saturated regime. This means that changes with scaling. The former leads to subthreshold nonscaling; i.e., the threshold the current gain and the delay improvement arc closer to the velocity-saturated voltage cannot be scaled down like other parameters. The latter leads to nonscalability of column of Table 4.3, and there is little to gain by operating at an even higher field the built-in potential, depletion-layer width, and short-channel effect. or voltage. From Eq. (3.40) , the offcurrent of a MOSFET is given by The most serious problems associated with the higher field intensity are reliability Ids (VgS 0, (k!'\q) = Vdd) W( tJ.efPoxy m - I) 2 e - qV/ t m k T • (4.10) and power. The power density increases by a factor of 0.2 to 3 0. as discussed before. Reliability problems arise from higher oxide fields, higher channel fields, and higher Because of the exponential dependence, the threshold voltage cannot be scaled down significantly without causing a substantial increase in the off current. In fact, even if the current densities. Even under the fully velocity-saturated condition, the current density increases by O.K. This aggravates the problem of electromigration in aluminum lines, which is already becoming worse under constant-field scaling (Dennard et al., 1974). 212 4 CMOS Device Design 4.2 Threshold VoRage 213 4.1.3.3 4.2 Higher fields also drive gate oxides closer to the breakdown condition, making it difficult to maintain oxide integrity. In fact, in order to curb the growing oxide field, the gate oxide thickness has been reduced less than the lateral device dimensions, e.g., the channel length, as is evident in Table 4.2. This means that the channel doping concentration must be increased more than called for in Table 4.3 to keep short-channel effects [Eq. (4.7)] under control. In other words, the maximum gate depletion width Wdm must be reduced more than the oxide thickness tox. This triggers another set of nonscaling effects, including the subthreshold slope ex m 1 + (3to./Wdm)' and the substrate sensitivity dV,Id(-Vbs)=m I [Eq. (3.45)]. These will be discussed in detail in Section 4.2.3. Other Nonscaling Factors In practice, there is yet another set of nonscaling factors encountered in CMOS techno­ logy evolution. One kind of nonscaling effect is related to the gate and source-drain doping levels. If not properly scaled up, they may lead to gate depletion and source­ drain series resistance problems. From Eq. (2.213), polysilicon gate depletion contributes a capacitance Cp= Gs,-qNpfQg in series with the oxide capacitance Cox:. As Cox increases by a factor of lC while Qg remains unchanged in constant-field scaling, Np must scale up by lC also to keep Cp in step with Cox:. In generalized scaling, Np must scale up even more (by aTe). In reality, this cannot be done because oflimitations by solid solubility. The total gate capacitance then scales up by less than Co.n leading to degradation of the inversion charge density and transconductance. Similarly, it is difficult to scale up the source­ drain doping level and make the profile more abrupt while scaling down the junction depth. In practice, the source-drain series resistance has not been reduced in proportion 4.2.1 4.2.1.1 Threshold-Voltage Requirement Various Definititlns of Threshold Voltage First, we examine the various definitions of threshold voltage and the threshold-voltage requirement from a technology point of view. There are quite a number of different ways to define the threshold voltage of a MOSFET device. In Chapter 3 we followed the most commonly used definition [V'..(inv) = 2V'B ] of V" The advantage of this definition lies in its popularity and ease of incorporation into analytical solutions. However, it is not directly measurable from experimental I-V characteristics (it can be determined from a C-V measurement; see Exercise 2.6). In Section 3.1.6, we introduced the linearly extrapolated threshold voltage, Vam determined by the intercept of a tangent through the maximum-slope (linear transconductance) point of the low-drain lds-Vgs curve. This is easily measured experimentally, but is about 3kTlq higher than the 2V'B threshold voltage, due to inversion-layer capacitance effects illustrated in Fig. 3.18. Another commonly employed definition ofthreshold voltage is based on the subthreshold lds-Vgs characteristics, Eq. (3.40). For a given constant current level 10 (say, SOuND), one can define a threshold voltage V;Uh such that Ids (Vgs V:'Ub) = Io( WIL). The advantages of such a threshold-voltage definition are twofold. First, it is easy to extract from hardware data and is therefore suitable for automated measurement of a large number of devices. Second., the device offcurrent, lor Ids(Vgs =0), can be directly calculated from 10, V:'Ub, and the subthreshold slope. In subsequent discussions, we will adhere to the 2V'B definition of V;. In general, V; depends on temperature (temperature coefficient), substrate bias (body-effect coefficient), channel length, and drain voltage (short-channel effect, or SCE). to channel resistance, Eq. (3.102). This causes loss of current drive as the parasitic component becomes a more significant fraction of the total resistance in the scaled device. Another class of nonscaling factors arises from process tolerances. The full benefit of scaling cannot be realized unless all process tolerances are reduced by the same factor as the device parameters. These include channel length tolerance, oxide thickness tolerance, 4.2.1.2 Off-current and Standby Power By definition, the off-current of a MOSF~T is the source-to-drain subthreshold leakage current when the gate-to-source voltage is zero and the drain-to-source voltage is Vdd, the power supply voltage. From Eq. (3.40), the expression for the off-current with Vds = Vdd» kTlq is threshold voltage tolerance, etc. It is a key requirement and challenge in VLSI = techno­ Jo11 Idsl vxs=0: vds--vtIJI,l)s Vte-qVdmkT , logy development to keep the tolerance to a constant percentage of the device para­ meter as the dimension is scaled down. This could be a major factor in manufacturing where (4.12) costs as one tries to control a couple of hundred angstroms of channel length or a couple of atomic layers of gate oxide. W (k!'\ L q) IdvY! f.1eJrCox (m - I) 2 (4.13) Threshold Voltage This section focuses on a key design parameter in CMOS technology: threshold voltage. Although the threshold voltage was introduced in Chapter 3, the discussions there were restricted to the case ofuniform doping. In this section, threshold-voltage requirements in terms of off- and on-currents are discussed, leading to the design of MOSFET channel with nonuniform body doping. The last two parts deal with thc effects ofquantum mechanics and dopant number fluctuations on threshold voltage. is defined as the source-to-drain current at threshold (Vg.,= V" Vds= Vdd). In the worst case, the source-drain voltage of the transistors in the off-state equals the power supply voltage Vdd. The standby power dissipation due to l,;ff is then Vd,J!o.ff For order-of­ magnitUde estimates, Vdd ::::; I V. If it is desired that the standby power of a VLSI chip containing 108 transistors be no higher than 1W, the off-current per transistor should be kept less than 10 nA. I For a small fraction of transistors on the chip or for a larger standby power bUdget, higher off-current per transistor can be allowed. 214 4 CMOS Device Design Note that 1ds,vl is rather insensitive to the temperature since fl~ffoc 1312. However, it does depend on technology. For a 0.1 p.m CMOS technology with tox:;'; 30 A, Peff:;'; 350 cm2N-s, rn:;,; 1.3, and W!L 10, Ids,vl is approximately 1 p.A (W= 1 pm). (Note that this number is fornMOSFETs. pMOSFET current is about 3 x lower due to the lower hole mobility. Also note that the extrapolated subthreshold current at the linearly extrapolated voltage VOIl is about lOx higher than this number, as discussed at the end of Subsection 3.1.6.4.) VLSI chips are usually specified for a worst-case temperature of 100°C where the off-current is much higher than that at room temperature because not only does VI decrease with temperature, but the slope of the log(Id.')-Vgs curve also degrades in proportion to q/kT. Typically, the inverse slope ofsubthreshold current is 100 mV!decade at 100°C. For the factor exp(-qVI /rnk1) in Eq. (4.12) to deliver a two-orders-of­ magnitude reduction from Ids,vl= I p.A to IOff= IOnA, VI(IOO DC) needs to be at least 0.2 V. Because Vt has a negative temperature coefficient of :;,;- 0.7 mVrC v. (Section 3.1.4.2), this means VI (25 0C) 2: 0.25 2 The above figures are acceptable for CMOS logic technologies. In a dynamic memory technology (Dennard, 1984), however, the otT-current requirement is much more strin­ gent for the access transistor in the cell: on the order of IOff ::::: 10-13 -- 10-14 A (see Section 9.2.2). This means VI(IOO°C) ::: 0.6 V for a DRAM access device with W= L= 0.1 pm. It should be noted that Eqs. (4.12) and (4.13) are analytical expressions derived under some simplifYing approximations, e.g., long channel, uniform doping, etc. They are used here for order-of-magnitude estimates. More exact values ofthe off-current for a particular design should be obtained by numerical simulations. Another consideration that may further limit how low the threshold voltage can be is the burn-in procedure. Bum-in is required in most VLSI technologies to remove early failures and ensure product reliability. It is usually carried out at elevated temperatures and over voltages to accelerate the degradation process. Both of these conditions further lower the threshold voltage and aggravate the leakage currents. Ideally, burn-in proce­ dure should be designed such that it does not require a compromise on the device performance. 4.2.1.3 On-current and MOSFET Performance While the lower bound of threshold voltage is set by standby power constraints, the upper bound is imposed by considerations of on-current and switching delay. The on-currenl of a MOSFET is defined in the saturation region as Ion (4.14) Consider an nMOSFET initially in the off state with the source grounded and the drain charged to Vds = Y:1d(e.g., in one of the CMOS inverter stales in Fig. 5.2). Ifa gate voltage Vgs Vdd is applied to tum it on, the drain node will be discharged by the current Ion (initially) and the drain voltage will decrease al a rate given Lower threshold voltages are allowed in the scenario under footnote I. 4.2 Threshold Vonage 215 1 ", ] ", 1 0.8 ....,,"'. O.ljlmCMOS Vdd=1.5V 5 '" :~g 0.6 " ....."" ~'" 0.4 ..""\, . j"a 0.2 """~."" FigUl'll4.2. 0 0 0.2 0.4 0.6 0.8 V,IVdd The reciprocal of CMOS delay in nonnalized units versus VtIVdd' The dots are from SPICE model .= simulations. The dashed line is a fitting proportional to O.6-V,IVdd• Here VI is defined as the gate voltage at which ids(Vd Vtid) equals that ofEq. (4.13). For a given linearly extrapolated, low-drain-bias threshold voltage Van. a larger DmL results in a lower VI hence higher Ioffand Ion. dVds CTt = -Ion' (4.15) where C is the total effective capacitance of the drain node. The switching delay for an incremental change of Vcb is then -CdVdIan IX I1Ian. It is evident from Chapter 3 that the lower the threshold voltage, the higher the current drive 10m hence the faster the switching speed. From a CMOS performance point of view, it is desirable to have a threshold voltage as low as possible. It will be discussed in Chapter 5 that because of the finite rise time of Vgs at the input, the current that goes into the discharge equation (4.15) is somewhat less than Ion. A circuit simulation model can be used to analyze the delay sensitivity to threshold voltage. Figure 4.2 shows a typical example of CMOS perfonnance, defined as the reciprocal of CMOS delay, versus the normalized threshold voltage, V,lVdd• For V,IVdd < 0.5, the result can be fitted to an expression proportional to 0.6 - V,lVdd• This indicates, for example, about 30% ofthe performance will be lost if V,lVdd is increased from 0.2 to 0.3. Because of such delay sensitivity, the V,lVdd ratio is usually kept:S: 0.25 for high performance CMOS circuits. 4.2.1.4 Ion versus 10ff Characteristics Since the choice of threshold voltage hinges on the tradeoff between faff and l"m it is a common practice to plot I'dl·directly against 10m thus skipping the ambiguous definition ' of threshold voltage. Figure 4.3 plots Id• versus Vgs for a constant Vcb= Vdd in both linear and logarithmic scales for the ease of reading Iaff and Ian simultaneously. In essence, adjusting the threshold voltage of the device is equivalent to parallel shifting the lcb-Vgs curves horizontally along the Vgs-axis. Note that for an incremental shift ofh.Vt > 0, Ioff decreases by a factor exp(q h.V/mk7) while lOll decreases by an amount gm h. VI, where gm = dld/dVgs is the saturation 216 4 CMOS Device Design 4.2 Threshold Voltage 217 lE-3 E I 0.8 ::l ::;;: fon ::;;: ~ lE-5 S 1g:: 0.6 'ii g ::; u <= I~ l.', ~ ::I a JE-8 [ __/ lE-9' Vdd I L L= I I + Linear scale I IVd,=Vdd ::I \) 0.4 '2 l' r1" .i!lIlI,' -0.2 0 0.2 0.4 0.6 0.8 Gate voltage (V) Figure 4.3. lds-Vgs characteristics in both linear and log scales; Vdd = 1.2 V in this example. 10000 P Oil" 65 nm control at 1000 Vdd= 1.2 V ~ 100 100 nNjlm 10 ," 1.75mNjlm Figure 4.4. O.l'IJ!l!"',lj!"ltl'_ill'llil!'!"J)I)!I'lttllt!,,jIltl,.I"II!!'!'! 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 Ion (mAljlm) An experimentall'!1J1"n plot for 65 nm nMOSFETs (Ranade et aI., 2005). transconductance or the slope of the I,l,-Vgs curve at Vgs = Vd". In this regard, the often cited IOI/I,>f{ratio is not a meaningful figure of merit because it changes constantly as AV, is adjusted. In fact, to maximize the lon/1ojJratio for a given V"", one would want to shift to as high a threshold voltage as possible so that the cntire 0 ::S Vgs::S V"" range is in the subthreshold. That is not a desired mode of operation for high performance CMOS because then 1011 would be so low that the delay is easily degraded by parasitic capaci­ tances (Chapter 5). An example of the recently published lon-loJJcharacteristics for nMOSFETs is shown in Fig. 4.4 (Ranade et at., 2005). 4.2.2 4.2.2.1 Channel Profile Design In this section, we discuss the· design of MOSFET doping profile that satisfies the threshold voltage and other device requirements. Parameters that come into play include the gate length, power supply voltage, and gate oxide thickness. The choice ofgate work function is then addressed, leading to the channel profile requirements and trends over the CMOS technology generations. CMOS Design Considerations CMOS device design involves choosing a set ofparameters that are coupled to a variety of circuit characteristics to be optimized. The choice of these device parameters is further subject to technology constraints and system compatibility requirements. Figure 4.5 shows a schematic diagram of the design process and the parameters involved. Because various circuit characteristics are interrelated through the device parameters, tradeoff's among them are often necessary. For example, reduction of Wdm improves short-channel effect, but degrades substrate sensitivity; thinner tax increases current drive, but causes reliability concerns, etc. There is no unique way of designing CMOS devices for a given technology generation. Nevertheless, we attempt here to give a general guideline of how these device parameters should be chosen. Circuit characteristics ~ Delay (V,IVdd, m) ~ Active power (Vdd ) II> Standby power (V" AV,(SCE), S) Hot carrier reliability (Vdd ) Oxide field (Vddltox) -.4it-----­ System compatibility (Vud) -..... . . .~ Design parameters (L, Vdd , I,,", Wdm , V,) ..... Figure 4.5. A CMOS design flowchart showing device parameters, technology constraints, and circuit objectives. 218 4 CMOS Device Design Wd/Il +3t",,= Ll2 3t",JWdm =m- I =0.4 Poor sub-th. slope Bt = tox Vdd/~oxJnax o Wd/n rlgUFe 4..6. A tox-Wdm design plane. Some tradeoff among the various factors can be made within the parameter space bounded by SeE, body effect, and oxide field considerations. Since threshold voltage plays a key role in determining both lOffand 10m it is important to minimize the VI tolerance, i.e., the spread between the high and low threshold voltages on the chip. The most dominant source of threshold voltage tolerances in a CMOS technology is from the short-channel effect. Channel length variations on a chip due to process imperfections give rise to threshold voltage v$rlations. From Eq. (3.67) of Section 3.2.1.4, the short-channel ~ is lower than that of the long-channel by v' t:.'vt ~.: [ I,lfbi( I,lfbi + Vtis) a(21,lfB)] e- 16) where a ~ 0.4 and Wdm is the maximum depletion width at the threshold condition, I,lfs = 21,lfo. The sensitivity of threshold voltage to channel length variations, (W,/oL, is intimately tied to 8.Vt • Since I,lfbi::-= 21,lfB::-= I V, and the worst case Vtis equals V,:ltl> the factor in the square bracket ranges between ::-= 1 and 2 V for VtId::-= I V to 5 V. The factor in front of the square bracket, 24to)Wdm = 8(m -1), is related to the factor m = 8.Vg./8.l,lfs illu­ strated in Fig. 3.5. It was discussed in Sections 3.1.2.3, 3.1.3.3, and 3.1.4.1 that from saturation current, subthreshold slope, and substrate sensitivity considerations, m should not be too much greater than unity, e.g., m :s 1.4. Because of the exponential factor in Eq. (4.16), 8.V, is very sensitive to LI(Wdm + 3tox). A good choice is L/(Wdm + 3tox) 2: 2, which gives 8.Vt :S 0.1 V for Vdd::-= 1 V and 8.V, :s 0.2 V for Vdd= 5 V, assuming a median value ofm= 1.3.3 . These considerations are captured in a plot ofthe torWtim design plane in Fig. 4.6. The intercept ofthe two lines, Wdm + 3tox = LI2 and 3to)Wdm = m -1 = 0.4, defines an upper 3 It can be shown from liV,lJL using F.q. (4.16) that this choice yields a ,lV, spread equal to !J.V, for a channel length tolerance oLlL of ± 15%. 4.2 Threshold VoHage 219 bound for the oxide thickness, tox•max ;::: L120. The lower limit of tox is imposed by technology constraints to V,d'f/ox,max, where 'lox,max is the maximum allowable oxide field from breakdown and reliability considerations. For a given Land Vd'" the allow­ able parameter space in a tox-Wdm design plane is a triangular area boundedby SeE, oxidefield, and subthreshold slope (also substrate sensitivity) requirements. In addition to the oxide field limitation, direct quantum mechanical tunneling (Fig. 2.62) also sets a lower limit to the thickness of gate oxide. Gate current density increases sharply as tox decreases below 2 nm. From Fig. 2.62, the gate tunneling current density for a 1nm thick oxide biased at 1 V is 103-104 Alcm2. Assume L ::-= 30 nm, the gate current of an individual transistor « 3 ).l.Ai1IDl) is still small compared with the typical on currents (::-= 1mAllIDl) of the preceding stage so the switching delay of active transistors is hardly affected. But consider 108 transistors each with WIL::-= 10 and L::-= 30nm, the total gate area per chip is of the order of 0.01 cm2. The standby power dissipation of all the turned-on transistors4 in the chip has reached intolerable levels of 10-100 W. Given the lox,max ::-= V20 criterion discussed above, the 1 nm tux limit translates into a channel length limit of= 20 nm for SiD}. Ifhigh-I( gate insulators become available, the scale length can be pushed to 1::-= 2t, for very high I( where ti is the insulator thickness (Section 3.2.1.5). In that case, the minimum channel length can be extended to 21 ::-= 4t" or ::-= 10 nm assuming a tunneling limited high­ I( thickness of2.5 nm. The last figure is thicker than that of Si02 because ofthe inherently lower barrier heights « 3.1 eV of Fig. 2.29) of such materials. 4.2.2.2 Trends of Power Supply Voltage and Threshold Voltage For a design window to exist in Fig. 4.6, it is required that Vdj'lox.max:S tox.max ::-= Ll20. This imposes an upper limit on the power supply voltage, namely, Vdd :S L'fox,max/20. (4.17) For L = I lim CMOS technology, the gate oxides are relatively thick and 7fox.max ;::: 3 MVlcm. Equation (4.17) requires Vdd:S 15 V. There is plenty of design room to choose the power supply and threshold voltages that satisfy both the off-current and the performance requirements discussed in Sections 4.2.1.2 and 4.2.1.3. For example, Vdd= 5 V and V,= 0.8-1.0 Vas shown in Fig. 4.7 in which the history and trends of power supply voltage, threshold voltage, and oxide thickness are plotted for CMOS logic technologies from 1.0 IIDl to 0.02 IIDl channel lengths (Taur et at., 1995a). At shorter channel lengths, Vdd must be reduced. It becomes increasingly more difficult to satisfy both the perfor­ mance and the off-current requirements. Fortunately, 'if:ox.max tends to increase for thinner oxides (see Section 2.5.6) as L is scaled down. This allows Vdd to scale at a slower rate than thc channel length. Experimentally, ~ox.max ::-= 6 MV/cm for oxides thinner than 3 nm. Equation (4.17) then requires, e.g., that Vdd :s 1.5 V for L = 50 nm CMOS technology. With such a low supply voltage, one often faees a tradeoff of circuit speed versus leakage current. Scaling down Vt causes loffto increase exponentially. Even for the 4 The worst case gate leakage occurs with nMOSFETs biased at Vg., = Vd• and V"' = 0 (electrons tunnel from the inversion channel to the gate). 220 4 CMOS Device Design ' 4.2 Threshold Vonage 221 10 5 ~2 E "> ""."0c ~ 0.5 -5 "'c>"". ]; 0.2 1jl ~ ~ -$ , 1:5 200 l"i r~50 l~\00 JI &il.: 0.1 20 10 Rgure4.7. om 0.Q2 0,05 0,\ 0,2 0,5 MOSFET channel length (1lIll) Trends of power-supply voltage, threshold voltage, and gate oxide thickness versus channel length for CMOS technologies from llllll to 0.02 J.ll11. (After Taur et aI., 1995a.) same VI' Iaffincreases since Ids, VI ofEq. (4.13) increases as the devices are scaled down - a manifestation of subthreshold nonscalability. For this reason and for compatibility with the standardized power supply voltage of earlier generation systems, the general trend is that Vdtl has not been scaled down in proportion to L, and VI has not been scaled down in proportion to Vdd, as is evident in Fig. 4.7. At L 20 nm, $'ox,max is pushed to 10 MV/cm for operation at Vdd = I V. As a result of the non-scaled Vdd, not only does the field increase over the CMOS generations, the increasing power density (Table 4.3) also becomes more difficult to manage. It is discussed in Section 5.1.1 that the active or switching power of a CMOS circuit is given by Pac = CV~dJ, (4.18) where C is the total equivalent capacitance being charged and discharged in a clock cycle, and f is the clock frequency, The power versus delay tradeoff can be represented conceptually in a VduVI design plane shown in Fig. 4.8 (Mii et at., 1994). Higher performance, i,e., shorter delay, pushes for higher Vdd and lower V" which inevitably results in higher active power or higher standby power, or both. Depending on the specific requirements of the application, CMOS technologies can be tailored to some extent by choosing an appropriate set ofpower supply and threshold voltages, High Higher . active -cv'itt "~ ~ ~ >. ]: I Higher il standby I ..~ power ~ &. --exp(-qv,lmkT) power Increasing perfonnance -{).7 - 11,1 Vdd Figure 4.8. Threshold voltage CMOS performance, active power, and standby power tradeoff in a Vda VI design plane, The performance here is defined as the reciprocal ofCMOS delay. 4.2.2.3 perfonnance CMOS usually operates at the upper left-hand comer of the design space and pushes both power limits. Low power CMOS can operate at lower supply voltages and possibly at a higher threshold voltage ifthe standby power is ofprimary concern. It is a corrunon practice in the state-of-the-art CMOS technologies to provide multiple thresh­ old voltages on a chip to allow the design flexibility ofusing different types ofdevices for different functions, e.g., in memory and logic circuits. This comes, of course, at the expense of additional process complexity and cost. Effect of Gate Work Function To realize the threshold voltages desired from the above design considerations, it is important to use a gate material with the proper work function. Gate work function (4)m) has a major impact on the threshold voltage of, e.g., nMOSFETs, VI VJb + + (4.19) since it sets the flatband voltage of the MOSFET, - ¢s = ¢m- + Eg 2q +!fIB.) . (4.20) For nMOSFETs, 2!f1B ~ 1 V and Qd < 0, so VI is easily larger than 1 V unless Vjb is negative, To achieve the low threshold voltages required in Fig. 4.7, n+-polysilicon gates have been used for n-channel MOSFETs so that Vjb=-Egl2q -!fiB' This results in near cancellation of the first and the second tenns ofEq, (4.19). VI is then largely detennined by the third tenn in proportion to the depletion charge density at the 2!f1B condition. How the channel doping profile should be designed in order to achieve the desired depletion charge density and therefore V, is discussed in the next subsection. Before p+-polysilicon gates become technologically available, n+-polysilicon gates are used for pMOSFETs as well in 1 j!m and 0.5 J.lll1 CMOS generations, This means Vjb is a small negative number (f7.Jb~-Et!2q +V's forn-type silicon) and the first two tenns ofthe 222 4 CMOS Device Design (a) Ef----~'- --------------. Vgs=O (b) Ef --- Vgs= V, • ~ - =-O.6v ----------• Er -­ (e) Figure 4.9. Band diagram of a buried-channel pMOSFET with n+-polysilicon gate. A shallow p-type layer is. implanted at the surface to lower the magnitude of threshold voltage. The gate is biased (a) in subthreshold, (b) at threshold, and (e) beyond threshold. (After Taur et al., 1985.) VI equation (the second term is 21J1B ::::-1 V for pMOS) add up to < -I V for pMOSFETs. To make VI less negative, the third term of the VI equation needs to be positive, which means p-type doping for pMOSFETs or a counterdoped channel. Since the depletion charge density is negative, the surface field at threshold is such that holes are accelerated toward the substrate, and the channel for holes is formed at a potential minimum below the surface. Such devices are called buried-channel MOSFETs. 4.9 shows the band diagrams of a buried-channel pMOSFET at several gate voltages both below and above the threshold. As the gate voltage becomes more negative than the threshold, the field changes sign and the channel moves to the surface. But the magnitude of the effective field is still lower than that ofa conventional surface-channel device. Although a buried-channel device. has higher mobilities, its short-channel effect is inherendy worse than that ofa surface-channel device (Nguyen and Plummer, 1981). This is because the counterdoping (especially boron) at the surface tends to diffuse deeper into the silicon during subsequent thermal cycles in the process. As the channel length and the power supply voltage are scaled down, a lower magnitude of threshold 4.2 Threshold Voltage 223 voltage is required. It becomes increasingly more difficult to build a buried-channel device since higher counterdoping in-the channel invariably1eads to wider gate depletion widths and poorer short-channel effects. For CMOS logic technologies of 0.25 pm channel length and below, dual polysilicon gates (n+-polysilicon for nMOSFET and p+-polysilicon for pMOSFET) are used so that both types of devices are surface­ channel devices (Wong et al., 1988). Near the limits of CMOS scaling (L :::: 10-20nm), the threshold voltages may~ become too high even with dual-polysilicon gates and extreme retrograde doping (Section 4.2.3.5). In principle, one way to further reduce the threshold magnitude is by counterdoping of the channel, as will be discussed in Section 4.2.3.6. There have been numerous research explorations (e.g., Davari et al., 1987) on using metal gates with a midgap work function. The benefits are high gate conductivity, absence ofpolysilicon depletion effects, and the simplicity ofusing a single gate material for both n- and pMOSFETs. Midgap work function gates exhibit symmetric flatband Vjb=-IJIB (p-type) for nMOSFETs and Vjb= IJIB (n-type) for pMOSFETs. The resulting threshold voltage magnitudes are in the range ofO.5-LOV [Eq. (4.19)]. This meets the VI requirements for 1 J.llIl and 0.5 J.llIl CMOS technologies in Fig. 4.7. An added benefit is that it takes much less depletion charge [the third term in Eq. (4.19)] to achieve the same VI magnitude with a midgap gate than with an n+-polysilicon gate for nMOSFETs. Less depletion charge means lower surface fields and therefore higher mobility. In reality, however, no midgap-work function gate material has been used in VLSI production because of technology issues such as compatibility material with thin gate oxides. Gate conductivity requirement has been met with self-aligned silicide technology (Section Once the CMOS technology is scaled to 0.2.5 J.llIl and below, V, malffiitudes < 0.5 V are needed (Fig. 4.7) which are difficult to achieve with a work function gate. 4.2.2.4 Channel Profile Requirement and Trends It was discussed above that with a n+-polysilicon gate for n-channel MOSFETs (and p+-poly for pMOSFETs), the first and the second terms ofEq. (4.19) essentially cancel out and VI is largely determined by the depletion charge term. For a uniform channel doping, the maximum gate depletion width at the 21J1B condition, = Wdm (4.21) and the depletion charge term of the threshold voltage, -Qd qNaWwn Cox Cox (4.22) the parameter Na, and therefore cannot be varied independently (for a given tox). In Section 4.2.2.1, we discussed that in order to control the short-channel effect, Wdm + 3tnx m Wdrn should be on the order of Ll2. The doping concentration that satisfies this requirement may not give the desired threshold voltage that satisfies the on­ and off-current requirements. 224 4 CMOS Device Design 4.2.3 4.2.3.1 For a given Wdm , it is necessary to employ nonuniform doping to adjust the depletion charge density to obtain the desired VI' Nonuniform channel doping gives the device designer an additional degree of freedom to tailor the profile for meeting both the SCE and the threshold requirements. Such an optimization is made possible by the ion implantation technology. . Channel profile trends can be inferred by expressing the threshold voltage in the uniformly doped case as J 4cs;qNa'l'B VI = V}b+2'1'B+-C-- Vp,+2'1'B+2(m 1)2'1'B' 0., (4.23) which does not scale much as neither m nor '1'8 changes significantly with channel length or doping. In fact, both m and 'l'B tend to increase slightly as the CMOS channel length scales down and higher doping is required. This is contrary to the downward trend of the V, requirement depicted in Fig. 4.7. For example, for a typical m '" 1.3, V, '" 0.6 V with n+-polysilicon gates. While this value happens to meet the Vt requirement for the 0.5 j.IJIl CMOS generation, it is too low for 1 j.IJIl CMOS and too high for CMOS generations 0.25 j.IJIl and below. It is shown in the next subsection that a high-low doping profile increases the depletion charge density for a given Wtim and therefore raises V, over the uniformly doped value, whereas a low-high profile reduces the depletion charge and lowers Vt. Nonuniform Doping In this subsection, analytic expressions for the maximum depletion width and the thresh­ old voltage are derived under nonuniform doping conditions. Specific results are given for both high-low and low-high doping profiles. Integral Solution to Poisson's Equation Mathematically the surface potential, electric field, and threshold voltage for the case of nonuniform channel doping can be solved using the depletion approximation. For a nonuniform p-tyPe doping profile N(x) in the same x-coordinate as defined in Fig. the electric field is obtained by integrating Poisson's equation once (neglecting mobile carriers in the depletion region): I,fWd If(x) = esi N(x)dx, where Wd is the depletion-layer width. Integrating again gives the surface potential, VIS =!L fWd fWd Jo C.Il j, dx'dx (4.25) Using integration by parts, one can show that Eq. (4.25) is equivalent to (Brews, 1979) jWd '1', =-q xN(x) dx. Csi 0 (4.26) The integral of xN(x) ofN(x). the center of mass ofN(x) within (0, times the integral 4.2 Threshold Voltage 225 N(x) § .~ N, ~ 8 ! Na o x, WJ x Depth Figure 4.10. A schematic diagram showing the high-low step doping profile. x=O denotes the silicon-oxide interface. The maximum depletion-layer width (long-channel) Wdm is determined by the condi­ tion 'l's=2'1'8 when Wd= Win,' The threshold voltage of a nonuniformly doped MOSFET is then determined by both the inil!gral (depletion charge density) and the center ofmass ofN(x) within (0, Wdm). 4.2.3.2 AHigh-Low Step Profile Consider the idealized step doping profile shown in Fig. 4.10 (Rideout et aI., 1975). It can be formed by making one or more low-dose, shallow implants into a unifonnly doped substrate of concentration Na. After drive-in, the implanted profile is approximated by a region of constant doping Ns that extends from the surface to a depth x,. If the entire depletion region at the threshold condition is contained within xs, the MOSFET can be considered as uniformly doped with a concentration Ns. The case of particular interest analyzed here is when the depletion width Wd exceeds x" so that part of the depletion region has a charge density Ns and part ofitNa. The integration in Eq. (4.26) can be easily carried out for this profile to yield the surface potential, or the band bending at the surface, qNs x; + 'l's 2cs; -x;). (4.27) This equation can be solved for Wd as a function of'l's: q(N, Na)X;). W" 2csi (4.28) This is less than the depletion width in the uniformly doped (Na) case for the same surface potential. The electric field at the surface is obtained by evaluating the integral in Eq. (4.24) with x=O: '#s = qNsxs + qNa( W" - xs) . csi csi (4.29) 226 4 CMOS Device Design From Gauss's law, the total depleted charge per unit area in silicon is given by Qs -esi'ls -qNsxs - qNaCWd (4.30) as would be expected from Fig. 4.10. The effect ofthe nonuniform surface doping is then to increase the depletion charge within 0 ~ x S Xs by (Ns - Na) Xs and, at the same time, reduce the depletion layer width as indicated by Eq. (4.28). Substituting Eq. (4.28) into Eq. (4.30) for Qs, the gate voltage equation (3.14) becomes Vgs =Vjb + IfIs + cI ox 2es;QNa(lfIs _ q(Ns - Na)x~) 2esi + q(Ns - C Na)xs . ax By definition, the threshold voltage is the gate voltage at which IfIs= 21f10, i.e., (4.31) VI = Vjb + 21f1B + + q(Ns Na)xs Co., 2esiqNa(2lf1B q(Ns - Na)X~) Zest (4.32) The maximum depletion width (long-channel) at threshold is given by Eq. (4.28) with IfIs = 21f10: (2 Wdm = -q2eNsui IfIB- q(Ns - Na)x;) . Zes; (4.33) There is some ambiguity as to whether21f10 is defined in terms of Ns or NQ • We adopt the convention that 21f1B is defined in terms of the p-type concentration at the depletion­ layer edge, i.e., 21f10=(2kT/q) In(NJnr). In fact, it makes very little difference which concentration we use, since 21f10 is a rather weak function of the doping concentration anyway.s Further refinement of the threshold condition would require a numerical simulation of the specific profile. In Section 3.1.3, we showed that the inverse subthreshold slope is given by 2.3mkT/q per decade where m=dVg/dlfls at IfIs = 21f1B. In the nonunifomlly doped case, m can be evaluated from Eq. (4.31): m dVgs 21f1B) d'l's 1+ ~~- (21f10 q(Ns - N(I)X;)-·1/2 2es; (4.34) 5 The "21{J8" definition of threshold voltage is only a hisll:>ricai convention. Actually, the channel "turns on" when the surface potential is within 0.1 V (a few kTlq) of the conduction band edge of the 11+ source, regardless of the p-type body doping. In that respect, the approximation 21{J8 ~ I V is frequently used in the discussions. 4.2 Threshold Voltage 227 It can be expressed in terms of Wdm using Eq. (4.33): m= 1 +E-si!-W-WI= I + Cdm 1 +3-to-x. Cox Wdm (4.35) These expressions are consistent with Eq. (3.27) for a uniformly doped channel. This is to be expected from the basic concept of m in Fig. 3.5, which applies regardless of the doping specifics. Similarly, the threshold voltage in the presence ofa substrate bias Vbs is given by Eq. (4.32) with the 21f1B term in the square root replaced by 21f1B - Vb•. Using Eq. (4.33), one can show that the substrate sensitivity is dVt d( - Vbs) (4.36) Therefore, all the previous expressions for the depletion capacitance, subthreshold slope, and body-effect coefficient in terms of Wdmfor the uniformly doped case remain validfor the nonuniformly doped case. The only difference is that the maximum depletion layerwidtb Wlim in the high-low step doping case is given by Eq. (4.33) insteadofEq. (4.21). 4.2.3.3 Generalization to a Gaussian Profile The results of the high-low step profile discussed above can be generalized to other profiles as well. As far as the threshold voltage and depletion width are concerned, the added doping density in Fig. 4.10, Ns - Na over (0, xs), is equivalent to the delta-function profile in Fig. 4.1 I (b) with an equivalent dose of D1 = Na)xs (4.37) centered atxc=xs /2. This is because both the integrals ofN(x) [Eq. (4.24)] and the center of mass of Nf.J:) [Eq. (4.26)] over (0, Wdm) are identical between the two profiles. Similar arguments apply to a general Gaussian (or other symmetric) profile in Fig. 4.1 1(a) with a dopant distribution, N(x) ~exp (_ (x - Xc)2) .,fiii(1 2(12' (4.38) where (1 is the implant straggle. The effect of such an implanted profile on threshold voltage and depletion-layer width is equivalent to that of the step doping profile dis­ cussed above, independent of (1. Substituting Eq. (4.37) and xc=x/2 into the threshold voltage equation (4.32) yields J ( V1 = V/h+ 2If1B+ I 2es;qN" 2If1BqD--IX.-C) +-qDC/ . en ox (4.39) Similarly, the maximum depletion width, (4.33), becomes Wdm (2 -2Esi 'l'BqD-P-'-c)' qN" ,[si (4.40) 228 4 CMOS Device Design N(x) 4.2 Threshold Voltage 229 Cbannel doping '~ Gate (a) N,'f, DJ '­ Electric field N. I x )I :Warn , ,"' DepletIOn edge o Xc Wain (b) Figure 4.11. Schematic diagrams showing (a) an implanted Gaussian profile and (b) a delta-function profile equivalent to (a), The electric field is proportional to the area under the depleted charge N(x) (Eq. (4.24)]. It has a step rise where the delta function doping is located. (After Brews, 1979.) For a given implanted dose Db the resulting threshold voltage shift depends on the location of the implant, XC' For shallow surface implants, Xc = 0, there is no change in the depletion width. The VtshiJt is simply given by qDiCox, as with a sheet ofcharge at the silicon-oxide interface. All other device parameters, e.g., substrate sensitivity and subthreshold slope, remain unchanged. As Xc increases for a given dose, both the maximum depletion width and the Vt shift decrease. IfXc is not too large, one can always readjust the background doping No to a lower value ~ to restore Wdm to its original value. The threshold voltage, in the meantime, is shifted by an amount less than the shallow implant case. the above analysis on nonuniform doping assumes Ns > Na, the results remain equally valid if N, < NQ • Such a profile is referred to as the retrograde channel doping, discussed in the next subsection. , - - - - - - - - - - No Ns o Xs Wdm x Figure 4.12. A schematic diagram showing the low-high (retrograde) step doping silicon--Qxide interface. x = 0 denotes the 4.2.3.4 Retrograde (Low-High) Channel Profile When the channel length is scaled to 0.25 j.IJ11 and below, higher doping concentration is needed in the channel to reduce Wdm and control short-channel effects. If a uniform profile were used, the threshold voltage [Eq. (4.23)] would be too high even with dual polysilicon gates. The problem is further aggravated by quantum effects, which, as will be discussed in Section 4.2.4, can add another 0.1-0.2 V to the threshold voltage because of the increasing fields (van Dort et al., 1994). To reduce the threshold voltage without significantly increasing the gate depletion width, a retrograde channel profile, i.e., a low-high doping profile as shown sche­ matically in Fig. 4.11, is required (Sun et al., 1987; Shahidi et al., 1989). Such a profile is formed using higher-energy implants that peak below the surface. It is assumed that the maximum gate depletion width extends into the higher-doped region. All the equations in Section 4.2.3.2 remain valid for Ns < No. For simplicity, we assume an ideal retrograde channel profile for which Ns=O. Equation (4.32) then becomes V/=Vjb+2V1B+ -4-Eq-syiV.al;B- + 2 XS qNaxs -C . ox Similarly, Eq. (4.33) gives the maximum depletion width, (4.41) Wdm + 4EsiVlB qNa (4.42) The net effect of low-high doping is that the threshold voltage is reduced, but the depletion width has increased, just opposite to that of high-low doping.· Note that (4.42) has the same form as Eq. (2.91) for a p-i-n diode discussed in Section 2.2.2. All other expressions, such as those for the subthreshold slope and the.,substrate sensitivity, in Section 42.3.2 apply with Wdm replaced by (4.42). 230 4 CMOS Device Design 4.2 Threshold Voltage 231 4.2.3.5 Extreme Retrograde Profile and Ground-Plane MOSFET BI Two limiting cases are worth discussing. If Xs « (4esi'l' qNa) 1/2, then Wdm remains essentially unchanged from the uniformly doped value [Eq. (4.42)], while VI is lowered by a net amount equal to qNaX/Cox [Eq. (4.41)]. In the other limit, Na is sufficiently high that x,::?> (4esilflBlqNa)I/2. In that case, Wdm'Z X" and the entire depletion region is undoped. All the depletion charge is concentrated at the edge ofthe depletion region. The square root term in Eq. (4.41) can be expanded into a power series to yield + + Vt = Vfb 2'1'B -=.:.:'----'-"-'-= (4.43) The last term sterns from the depletion charge density in silicon, t:sl{2'1'B Ixs), which can also be derived from Gauss's law by considering that the field in the undoped region is constant and equals 2'1'01x, at threshold. Note that the work function difference that goes into Yfb is between the gate and the p+ silicon at the edge of the depletion region. Using m = I + 3tox lWdm= 1 + 3tox lxs, one can write Eq. (4.43) as VI = Vjb + 2'1'B + (m - 1)2'1'B' (4.44) Comparison with Eq. (4.23) shows that, with the extreme retrograde profile, the depletion charge (the third) term of VI is reduced to half of the uniformly doped value. If there is a substrate bias Vbs present, the 2'1'B factor in the last term of Eq. (4.44) is replaced by (2'1'B Vb')' i.e., VI = Vjb 2m'l'o (m I)Vbs. (4.45) Since '1'0 is a weak function ofNa, the above results are independent ofthe exact value of No as long as it is high enough to satisfY x, ::?> (4e'i'l'BlqNu )1/2. All the essential device characteristics, such as SCE (Wdm ), subthreshold slope (m), and threshold voltage, are determined by the depth of the undoped layer, XS' The limiting case of retrograde channel profile therefore degenerates into a ground-plane MOSFET (Yan et ai., 1991). The band diagram and charge distribution of such a device at threshold condition are shown schematically in Fig. 4. 13. Note that the field is constant (no curvature in potential) in the undoped region between the surface and Xs' There is an abrupt change offield at x =xs, where a delta function ofdepletion charge (area = 2t:SI"l'slx,) is located. Beyond x" the bands are essentially fiat. It is desirable not to extend the p+ region under the source and drain junctions, since that will increase the parasitic capacitance. The ideal channel doping profile is then that of a low-high-low type shown in Fig. 4.14, in which the narrow p+region is used only to confine the gate depletion width. Such a profile is also referred to as pulse~shaped doping or delta doping in the literature. The integrated dose of the p+ region must be at least 2t:si'l'81qxs to provide the gate depletion charge needed. It is advisable to use somewhat higher than the minimum dose to supply additional depletion charge to temper the source­ drain fields in short-channel devices. However, too high a p+dose or concentration may result in band-to-band tunneling leakage between the source or drain and the substrate, as mentioned in Section 2.5.2. Ef n+ i-. p. poly layer! region p-type substrate xs=iWdm "'Xj QM Qi Qd Figure 4.13. Band diagram and charge distribution of an extreme retrograde-doped or ground-plane nMOSFET at threshold condition. Source Drain ~~) Figure 4.14. x x Schematic cross section of a low-high-low, or pulse-shaped, or delta-doped MOSFET. The doping concentration along the dashed line is depicted in the profile to the right. The highly doped region corresponds to the shaded area in the cross section. 4.2.3.6 Counter-Doped Channel When CMOS devices are scaled to 20 nm channel lengths and below, the field is so high and the quantum effect so strong thai even the extreme retrograde profile cannot deliver a VI 'Z 0.2 V with n+ and p+ silicon gates. Besides finding new gate materials with work functions outside ofn+ and p+ silicon, further reduction of VI can be accomplished, at least in principle, by either counterdoping the channel or forward biasing the substrate. 232 4 CMOS Device Design 4.2 Threshold Voltage 233 Electric field % Uniformly doped il:'s (""' Vox) Counter ­ I Ground doped -plane .,-: '" Uni!o~_ Ground-plane Counter--doped 01 xs=Wdm Depth x r Depletion width Figure 4.15. Graphical interpretation of uniformly doped, extreme retrograde or ground-plane, and counterdoped profiles. The band bending is given by the area under it(x) which equals 2'f1lJ at threshold for all three cases. ~~I 1/// I 21/1B Wdm Rgure4.16. Band diagrams tlfuniformly doped, ground-plane (extreme retrograde), and counter-doped MOSFETs at threshold. A forward substrate bias also helps improve short-channel effects as it effectively reduces the built-in potential, IfIbi in Eq. (3.67) , between the source- where there is no depletion charge. At the threshold condition, the shaded rectangular area for the ground-plane case is approximately the same as the triangular area under the uniformly doped ~(x) since 21f1B is a rather weak function ofNa c" and c~n be considered as a const~t for practical purposes. It is then clear that the depletIOn charge tenn of VI or the y-mtercept of the ground-plane case IS half of that of .I. the uniformly doped case exactly as indicated by Eqs. (4.44) and (4.23). i~1 ..> A specific case of the counter-doped channel is shown in Fig. 4.15. The slope d'if/ldx has the same magnitude as the uniformly doped case, but of the opposite polarity. Both the depletion width (x-intercept) and the band bending [area under $'(x)] are the same as the previous two cases. But the y-intercept ($'s) is zero which means that the net charge in silicon is zero due to cancellation ofthe counter-doped charge with the depletion charge at the edge of the depletion region. This yields a very low V,. Further counter--doping would result in $'s < 0 or a buried channel MOSFET. The band diagrams of these three doping cases at the threshold condition are further illustrated in Fig. 4.16. Both the depletion width and the band bending are kept the same for all three. But the surface fields (slopes) are very different, leading to dramatically different potential drops across the gate oxide. 4.2.3.7 Laterally Nonuniform Channel Doping So far we have discussed nonuniform channel doping in the vertical direction. Another type of nonuniform doping used in very short-channel devices is in the lateral direction. For nMOSFETs, it is achieved by a medium-dose p-type implant carried out together with the n+ source-drain implant after gate patterning. As shown in Fig. 4.17, the p-type doping peaks near the source and drain ends of the device but dips in the middle because ofblocking of the implant by the gate. Such a self-aligned, laterally nonuniform channel doping is often referred to as halo or pocket implants (Ogura e( al., 1982). Figure 4.17 shows how halo works to counteract the short-channel effect, i.e., threshold rollofftoward the shorter devices within a spread of the channel length (or gate length). At the longer end ofthe spread shown in Fig. 4.17(a), the two p+ pockets are farther apart than at the shorter end of the spread in Fig. 4.l7(b). This creates a higher average p-type 234 4 CMOS Device Design (a) Gate ~l t source) p+ ~ p+ Drain ~ ~++ (b) Gate J. t· C Source Drain p+ p+ n++ n++ Figure 4.17. Laterally nonuniform halo doping in nMOSFETs. For a given design length on the mask, there is a spread of the actual gate lengths on the wafer. The longer end of the spread is shown in (a), the shorter in (b). The sketch below each cross section shows the schematic doping variation along a horizontal cut through the source and drain regions. doping in the shorter device than in the longer device. Higher doping means higher threshold voltage. So laterally nonuniform halo doping establishes a tendency for the threshold voltage to increase toward the shorter delJices, which works to offset the short-channel effect in the opposite direction. With an optimallydesigned 2-D nonuni­ form doping profile called the superhalo, it is possible in principle to counteract the short­ channel effect and achieve nearly identical Ion and Iojf in devices of different channel . lengths within the process tolerances of a 25 nm MOSFET (Taur et al., 1998). 4.2.4 Quantum Effect on Threshold Voltage It was discussed in Section 2.3.2 that in the inversion layer of a MOSFET, carriers are confined in a potential well very close to the silicon surface. The well is formed by the oxide barrier (essentially infinite except for tunneling calculations) and the silicon conduction band, which bends down severely toward the· surface due to the applied gate field. Because of the confinement of mo~ in the direction nonnal to the surface, 4.2 Threshold Voltage 235 Erfg:2 ;; ! » ::!l IcI:>: II> gc:: ~ Electron distribution of the ~.rouIl4 state oE (g=4) E#",2) Conduction­ band edge ",CJ =p-- • x 120 Distance from surface (A) -40, _ Bottom of the well Figure 4.18. An example of quantum-mechanically calculated band bending and energy levels of inversion­ layer electrons near the surface of an MOS device. The ground state is about 40 meVabove the bottom of the conduction band at the surface. The dashed line indicates the Fermi level for 1012 electrons/cm2 in the inversion layer. (After Stern and Howard, 1967.) inversion-layer electrons must be treated quantum-mechanically as a 2-D gas (Stem and Howard, 1967), especially at high nonnal fields. Thus the ~nergy 'levels of the electrons are grouped in discrete subbands, each of which corresponds to a quantized level for motion in the normal direction, with a continuum for motion in the plane parallel to the sur:fuce. An example of the quantum-mechanical energy levels and band bending is shown in Fig. 4.18. The electron concentration peaks below the silicon-oxide interface and goes to nearly zero at the interface, as dictated by the boundary condition of the electron wave function. This is in contrast to the classical model in which the electron concentration peaks at the surface, as shown in Fig. 4.19. Quantum-mechanical behavior ofinversion-layer electrons affects MOSFET operation in two ways. First, at highfields, threshold voltage becomes higher, since more band bending is required to populate the lowest subband at some energy above the bottom ofthe conduction band. Second, once the inversion layer forms below the surface, it takes a higher gate-voltage overdrive to produce a given level ofinversion charge density. In other words, the effective gate oxide thicknes's is slightly larger than the physical thickness. This reduces the transconductance and the current drive of a MOSFET. 4.2.4.1 Triangular Potential Approximation for the Subthreshold Region A full solution of the silicon inversion layer involves numerically solving coupled Poisson's and Schrodinger's e.quations self-consistently (Stern and Howard, 1967). 236 4 CMOS Device Design 1.0 rt-----.,.------,-------,~ < IOO>Si 1501:{ = N. 1.5 X 1016 cm-3 0.8 Q/ q "" 1012 crn­ 2 0.6 ~ U 0­ S " 0.4 0.2 2 4 Depth x (nm) 6 7 Figure 4.19. Classical and quantum-mechanical electron density versus depth for a (100) silicon inversion layer. The dashed curve shows the electron density distribution for the lowest subband. (After Stern, 1974.) Under subthreshold conditions when the inversion charge density is low, band bending is solely determined by the depletion charge. It is then possible to decouple the two equations and obtain some insight into the quantum-mechanical (QM) effect on the threshold voltage. Since the inversion electrons are located in a narrow region close to the surface where the electric field is nearly constant (g',,), .it is a good approximation to consider the potential well as composed of an infinite oxide barrier for x < 0, and a triangular potential Vex) '" q't..x due to the depletion charge for x > O. The SchrOdinger equation is solved with the boundary conditions that the electron wave function goes to zeto atx= 0 and at infinity. The solutions are Airy functions with eigenvalues Ej given by (Stern, 1972) E .I [3hq't;s 4.j2m, (. J 3)]2 +4 / 3' j 0,1,2, ..., (4.46) 4.2 Threshold Voltage 237 where h = 6.63 x 10-34 J-s is Planck's constant, and mx is the effective mass of electrons in the direction ofconfinement. Note.that MKS units are used throughout this subsection (e.g., length must be in meters, rieit centimeters). The average distance from the surface for electrons in thej th subband is given by _ 2Ej Xj - 3qlFs' (4.47) For silicon in the (100) direction, there are two groups ofsubbands, or valleys. The lower valley has a twofold degeneracy (g=2) with mx =ml"'O.92mo, where mo=9.1 x 10-31 kg is the free-electron mass. These energy levels are designated as Eo, Eh .... The higher valley has a fourfold degeneracy (i =4) with m~ = mt O.l9mo. The energy levels are designated as Eo, E:, E~, ,... Note that 3)]2/ E; = [34hql~ Fs (J.+ 4 3 1 j 0,1,2, .... (4.48) At room temperature, several subbands in both valleys are occupied near threshold, with a majority of the electrons in the lowest subband of energy Eo above the bottom of the conduction band. From Appendix 12, the total inversion charge per unit area is expressed as (Stem and Howard, 1967) I: QQ, M I = - 47Ch2- qkT ( gmt In(1 +e(E;-E"'-E)lkT) . J ~ + g'(m/mt) 1/2 + In(1 e(ErE;-EJ)/kT)), (4.49) where m,= 0.19mo and (mimi) 1/2 = 0.42mo are the density-of-states effective masses of the two valleys, and Ej E: is the difference between the Fermi level and the bottom of the conduction band at the surface. It is shown in Appendix 12 that in the subthreshold region, Eq. (4.49) can be simplified to QQM I = 47CqkTnf (2m '"' -E,/kT h2N c Na I L..- e J + 4(mlmt) 1/2 e-r;:/kT) e'II".JkT, (4.50) where Nc is the effective density of states in the conduction band. 4.2.4.2 Threshold-Voltage Shift Due to Quantum Effect When 'is < 104_105 Vlcm at room temperature, both the lowest energy level Eo and the spacings between the subbands are comparable to or less than kT. A large number of subbands are occupied. It is shown in Appendix 12 that in this case, Q?M is essentially the same as the classical inversion charge density per unit area given by Eq. (3.36) for the subthreshold region, 238 4 CMOS Device Design 0.4 0.35 ~ 0.3 ¢:: ~ 0.25 Cii .~ 0.2 .&. 0.15 ~~ 0.1 <---, 0.05 r- , o IE+3 3E+3 lE+4 3E+4 1£+5 3E+5 1E+6 3E+6 lE+7 Field at silicon surface (V/cm) Figure 4.20. Additional band bending fl'll¥M (over the classical 2'1'B value) required for reaching the threshold condition as a function of the surface electric field. The dotted curve is calculated by keeping only the lowest term (twofold degeneracy) in Eq. (4.50). Qi = -k~- sT-Nn'a2 eqw /kT 1'"$ • (4.51) (The expression has been generalized to cover nonuniformly doped cases where '$',. is the electric field at the surface and Na is the doping concentration at the edge ofthe depletion layer.) When > 105 Vlcm, however, the subband spacings become greater than kTand QpM is significantly less than Qt. The QfM- /fl. curve IEq. (4.50)J exhibits a positive parallel shift with respect to the classical Q./fIs curve IEq. (4.51)] on a semilogarithmic scale, which means that additional band bending is required to achieve the same inversion charge per unit area as the cla.~sical value. The classical threshold condition, Ws=2WB. should therefore be modified to Ws 2WB + 6w9M, where QfM(Ws 2WB + 6W¥M) = Qi(Ws = 2WB)' From this definition, 6 QM kTln ( Qi(Ws = 0) ) Ws q QpM(Ws 0) (4,52) can be evaluated from the preexponential factors in Eqs. (4.51) and (4.50). Figure 4.20 shows the calculated 6W¥M as a function of ~s. Beyond 106 Vlcm, only the lowest subband is occupied by electrons and Eq. (4.52) becomes 6~QM ~ Eo q _ kTI q n (811~:qNm1'ifS) c ' (4.53) which is plotted as the dotted curve in Fig. 4.20. Knowing 6W.~M, one can easily calculate the threshold voltage shift due to the quantum effect: 6v9M I dVgs 6/J1QM dWs rs m 6 111QM '1'.<' (4.54) where m = 1+ (3toxlWdm) as before. 4.2 Threshold VoHage 239 As an example, consider a 50 nm MOSFET with a uniform doping of No =3 x 1018 M J1M cm-3, which gives Wdm =20nm fQr..control of short-channel effects. For this device, ~s :-:;: 106 V/cm, so 6w9 0.13 V from Fig. 4.20. If m = 1.3, then 6 0.17 V, resulting in a much higher threshold voltage than the Classical value. A retrograde doping J1M . profile not only reduces the depletion charge density (for a given Wdm) but also lowers the surface field hence 6 4.2.4.3 Quantum Effect on Inversion-Layer Depth After strong inversion, the inversion charge density builds up rapidly and the triangular potential-well model is no longer valid. Ifthe separation between the minimum energies ofthe lowest and the first excited subbands is large enough that only the lowest subband is populated, a variational approach leads to an approximate expression for the average distance of electrons from the surface (Stern, 1972): x~: = ( 9£sih2 ) 1/3 1611:2mxqQ* ' (4.55) +:H where Q* Qd Qi is a combination of the depletion and inversion charge per unit area in the channeL In general, the solution must be obtained numerically. Figure 4.21 shows a comparison of the classical and QM inversion-layer depths versus the effective normal field defined in Eq. (3.51) (Ohkura, 1990). The QM value is consistently larger than the classical value by about 10-12 Afor a wide range of channel doping (uniform) and effective fields. This degrades the inversion layer capacitance, -dQ;ldWs es/xav (Section 3.1.6.2),6 and therefore the inversion charge component of the gate capaci­ tance, -dQ;ldVgs 80 xltinv Effectively, the quantum-mechanical effect adds Mox = (e"x!esi)6xa• = (x£,M x;.L) /3 or about 3-4 A to tin.. causing lower current drive and transconductance in thin-oxide MOSFETs. 4.2.5 Discrete Dopant Effects on Threshold Voltage As CMOS devices are scaled down, the number of dopant atoms in the depletion region of a minimum geometry device decreases. Due to the discreteness of atoms, there is a statistical random fluctuation of the number ofdopants within a given volume around its average value. For example, in a uniformly doped W=L=O.l-J.IIIl nMOSFET, if Na = 1018cm-3 and Wdm =350 A, the average number of acceptor atoms in the depletion region is N =Na LW Wdm =350. The actual number fluctuates from device to device with a standard deviation (IN «(6N)2)1/2 = N l/2 7= 18.7, which is a significant fraction of the average number N. Since the threshold voltage of a MOSFET depends on the charge of ionized dopants in the depletion region, this translates into a threshold-voltage fluctuation which could affect the operation ofVLSI circuits. 6 Strictly speaking, the Xu. in the capacitance is the center'of mass of the differential inversion charge responding to a differential change of Y's. Here we neglect the subtle difference. 240 4 CMOS Device Design 5.0 j \r40 e 5 .fcr 3.0 "t " 1;Tc ~ .e2 'iIcI 2.0
  • 10, but could be problematic for SRAM cell transistors which have minimum widths and require 60' guard band for large arrays on a chip. 4.3 MOSFET Channel Length Channel length is a key panuneter in CMOS technology used for performance projection (circuit models), short-channel design, and modeJ:...hardware correlation. This section focuses on MOSFET channel length: its definition, extraction, and physical interpretation. 4.3.1 Various Definitions of Channel Length A number of quantities, e.g., mask length (Lmask), gate length (Lgote), metallurgical channel length (Lm,t), and effective channel length (LeJij, have been used to describe the length of a MOSFET. Even though they are all related to each other, their relation­ ships are strongly process-dependent. Figure 4.22 shows schematically how various channel lengths are defined. Lmask is the design length on the polysilicon etch mask. It is reproduced on the wafer as Lgate through lithography and etching processes. Depending on the lithography and etching biases, Lga1e can be either longer or shorter than There are also process tolerances associated with L gate• For the same Lmask design, may vary from chip to chip, wafer to wafer, and run to nm. Although Lgate is an important parameter for process control and monitoring, there is no simple way of making a large number of measurements of it. Lgate is measured with a scanning electron microscope (SEM) and only spor­ adically across the wafer. There is also an uncertainty in the precise definition of Lgate when the polysilicon etch profile is not vertical, as to whether Lgate refers to the top or to the bottom dimension of the gate. 4.3 MOSFET Channel Length 243 ! ~ ~ 1~ ~ Lmask .. : Lgate ... 1 Source ~ ~ Drain Lme! ---....j 1--- Leff -------l Figure 4.22. Schematic diagram showing the definitions of and relationship among the various notions of channel length. The physical interpretation of Leffis examined in Section 4.3.3. Lmet is defined as the distance between the metallurgical junctions of the source and drain diffusions at the silicon surface. In a modern CMOS process, the source and drain regions are self-aligned to the polysilicon gate by performing the source-drain implant after gate patterning (Kerwin et al., 1969). As a result, there is a close correlation between Lntet and Lgate. Usually, Lmet is shorter than Lgate by a certain amount due to the lateral implant straggle and the lateral source-drain diffusion in the process. Accurate physical measurement ofLnt"t in actual hardware is very difficult. Normally, Lmet is used only in 2-D models for short-channel device design. Even for that purpose, difficulties arise in Lmel when dealing with a buried-channel device or a retrograde channel profile with zero surface doping, whcre there are no metallurgical junctions at the silicon surface. The parameter Lefjis different from all other channel lengths discussed above in that it is defined through some electrical characteristics of the MOSFET device and is not a physical parameter. Basically, Legis a measure ofhow much gate-controlled current a MOSFET delivers and is therefore most suitablefor circuit models. Leffalso allows for· a large number of automated measurements, since it can be extracted from electrically measured terminal currents. The basis of the Leffdefinition lies in the fact that the channel resistance of a MOSFET in the linear or low-drain bias regiQJl is proportional to the 244 4 CMOS Device Design channel length, as indicated by Eq. (3.102) (Dennard et aI., 1974). Further details of the definition and the extraction of Lef!are given in the next subsection. For submicron CMOS technologies, it is important to distinguish among the various notions of channel length. The errors can be significant, since lithography and etching bias, junction depletion width, and lateral source-drain diffusions are all becoming an appreciable fraction of the channel length. 4.3.2 4.3.2.1 Extraction of the Effective Channel Length As discussed in the last subsection, the effective channel length Lef! is defined by its proportionality to the linear or low-drain channel resistance. That is, R Vds Lef! ch Ids ,uef~i"vW(Vgs - Von mVd./2) (4.61) from Eq. (3.102), where Van is the linearly extrapolated threshold voltage and ,uef! is the effective mobility. Cinv contains the inversion-layer capacitance effect; ,uef!is a weak function of Vgs. For different Lmash Lef!differs but is assumed to be related to Lmask by a constant channeiiength bias M: Lef! = Lnu/Sk - 11L. (4.62) All the lithography and etch biases as well as the lateral source-drain implant straggle and diffusion are lumped into M. The assumption that the channel length bias is constant is a reasonable one when the channel length is not too short. However, M can be linewidth-dependent when Lmask approaches the resolution limit of the lithography tool used in the process. This issue will be addressed later. In the simplest scheme of channel-length extraction (Dennard et ai., 1974), Rch is measured for a set of devices with different Lmask• Based on Eq. (4.61) and Eq. (4.62), a plot ofRch for a given Vgs versus Lmask should yield a straight line whose intercept with the x-axis gives M and therefore Lelf In practice, however, two issues must be addressed for short-channel devices. The first one is the source-drain series resistance. The second one is the short-channel effect (SCE), which causes Von in Eq.(4.61) to depend on Lmask• Channel-Resistance Method The effect of source--drain resistance is examined using the equivalent circuit in Fig. 4.23. A source resistance Rs and a drain resistance Rd are assumed to connect an intrinsic MOSFET to the external terminals where voltages Vds and Vgs are applied. The internal voltages are V~s and V~s for the intrinsic MOSFET. One can write the following relations: V~s = Vds (Rs + Rd)lds (4.63) and V~s = Vgs - R,Ids . (4.64) As shown in Fig. 4.23, the intrinsic part of an actual device with parasitic resistance is equivalent to an intrinsic MOSFET with a grounded source, with Vks and V:U at the 4.3 MOSFET Channel Length 245 Vgs V;s~- I ~ ---- - v';' d vd, • Ids , 9 ~g V;,S =V - RI ,ds ~J L-Ids r -R,Id' V~,=Vds-(R,+Rd)Ids Figure 4.23. Equivalent circuit of MOSFET with source and drain series resistance. The intrinsic part of the top circuit is equivalent to the bottom circuit with redefined terminal voltages. gate and the drain terminals, and with a reverse bias -RJds on the substrate. Based on Eq. (4.61), but with redefined voltage symbols on the intrinsic nodes, the channel resistance of the intrinsic device is given by _ LeJI Reh = Ids ,uef.J.~fi' nv W( V' g' Vo'n -~mVids/2) , (4.65) where V~n is the linear threshold voltage with the reverse bias on the substrate. It is related to the zero-substrate-bias threshold voltage Von by V;n = Von + (m - I)RJds, (4.66) where m 1 is the substrate sensitivity (4.36)]. In a normal CMOS process, the source and drain regions are symmetrical, and therefore R,. Rd == Rsj2, where Rsd is the total source-drain parasitic resistance. Using Eqs. (4.62)-{4.66), one can write the extemally measured total device resistance as R tot V I,: = Rsd + Rch = Rsd + ,ue~inv Lmask W( Vgs -I1L Von m Vds/2) . (4.67) 246 4 CMOS Device Design Here all the internal voltages have been replaced by the voltages at the external terminals, since V;s - V;" - mV:U/2 = Vgs - Von - mVds /2 from Eqs. (4.63), (4.64), and (4.66). Note that Von is defined in terms of the intrinsic device, i.e., the threshold that would be obtained from linear extrapolation if there were no parasitic resistances. For a set of devices with different Lm"';'k but the same W; the parameters Rsd, M, and Cinvare the same within process tolerances. It is also assumed t..l:lat Peffdoes not change with channel length. The linear threshold voltage Von> however, does depend on channel length because of short-channel effects. When comparing R,ot of devices with different Lmask, therefore, it is important to measure Von for each device and adjust Vgs so that the gate overdrive Vgs Van is the same from device to device. A plot ofR tot (at small V"") versus Lmaskfor a given Vg., - V,m will then yield a straight line thatpasses through the point (AL, Rau). An example is shown in Fig. 4.24. The slope of the line depends on the 200rl----~----~----_.----_.----_.----_.--_r_, Vd,,,,O.l V Vb,'" 0 700-A gate oxide 150 3.8x 1O"-cm-2 boron implantat 40 KeV § ~ <>:: "c(J ~ .~ 100 C ";Ee;: :"'"; 50 oI /OJI! I 2 3 4 5 6 7 8 Channel length on mask, Lma,k <11m) FIgure 4.24. Measured RIO( at a low drain voltage versus Lmask for several different values of common intercept detennines both IlL and R"i' (After Chem et al., 1980.) - Voa. The 4.3 MOSFET Channel Length 247 specific value ofthe gate overdrive. M and Rsd are determined by the common intercept of several lines, each for a different ~gs- Van (Chern et al., 1980). 4.3.2.2 Shift-and-Ratio Method Despite the simplicity ofthe channel-resistance method described above, two main issues remain. First, it is not always straightforward to find the intrinsic Von of short-channel devices. The presence ofRsd adds considerable difficulty in the usual linear extrapolation of Van from the measured lds-Vgs curve (Sun et aI., 1986). Typically, one tends to under­ estimate Van in short-channel devices, as the degradation of ld.' by Rsd is more severe at higher currents. This introduces errors in channel-length extraction. The problem is further aggravated by a strong dependence of mobility on gate voltage, for example, in low-temperature andlor O.l-f.UIl MOSFETs. The second problem with the resistance method is that the Rtot-versus-Lma.'k lines for different gate overdrives may not intersect at a common point. Significant errors may result ifonly a limited number of Vgs Van are investigated. An improved channel-length extraction algorithm, called the shift-and-ratio (S&R) method, is able to circmnvent the above problems (Taur et aI., 1992). This method is based on the same channel-resistance concept described above. It starts with a genera­ lization ofEq. (4.67) to the form R:o, (Vgs) Rsd + L~fft( Vgs - v;,n)' (4.68) where f is a general function of gate overdrive common to all the measured devices. The superscript i denotes the ith device, with an unknown effective channel length L~ff L~ask - tJ.L and linear threshold voltage v;,n' The key assumption behind Eq. (4.68) is that the effective mobility Pelf is a common function of Vgs - Von for all the measured devices. This is a reasonable assumption in view of Eq. (3.54) and Eq. (3.55). The task is to calculate Rsd, L~If' and V:", in Eq. (4.68) from the measured data on R;o/( Vgs ). The S&R algorithm simplifies the procedure by differentiating Eq. (4.68) with respect to Vgs. Since the parasitic resistance Rsd is either independent or a weak function of Vg." its derivative can be neglected: Si(V ) = dR:o, Li df(Vgs - v:,n) gs - dVgs elf dVgs . (4.69) Here dfldVgs is also a general function of gate overdrive common to all the devices measured. An important benefit of working with the derivatives is that R&d drops completely out of the picture, so it does not matter if Rsd varies from device to device as long as it is constant. An algorithm has been developed in the S&R method to take the ratio of Si(Vgs) between two different devices - typically one long and one short, by shifting one along Vg& with respect to the other. The ratio becomes nearly constant, i.e., independent of Vgs, when the shift equals the difference between v;,n of the two devices. L~1f is then determined from the rdtio of the S functions at such a shift (Taur et al., 1992). 248 4 CMOS Device Design 4.3.3 4.3.3.1 Physical Meaning of Effective Channel Length This subsection examines the physical meaning of LejJextracted from electrically mea­ sured telTIlinal currents. The effective channel length is defined through the linear channel resistance by Eq. (4.61). This equation is derived for long-channel devices and is not strictly valid for short-channel devices. By its definition, represents a measure of the effective gate-controUed resistance of the d~vice and is not associated with any fixed physical quantity. When the channel profile is reasonably uniform and the source-drain doping is not too approximately equal to (Laux, 1984). In general, however, one cannot take Lmet for granted. The more graded (laterally) the source and drain profiles are, the longer L~ff is over Lmet• This can be understood in terms of the spatial dependence of channel sheet resistivity discussed below. Sheet Resistivity in Short-Channel Devices Equation (4.61) implicitly assumes that the sheet resistivity, Pch given byEq. (3.103), is spatially unifolTIl in both the MOSFET width and length directions. If the device is wide enough, Pch can be considered unifolTIl in that direction. However, the variation ofPch in the length direction cannot be ignored in a short-channel device. From dV Id, -PejJWQb) , where the channel length direction. is a current continuity. One can define a laterally Pch(y) (4.71) Note that Qi < 0 for nMOSFETs. This expression is valid as long as the current flow is largely parallel to the y-direction and the equipotential contours are perpendicular to the silicon surface. The total resistance is given by r Vds Ids = WI }s_nPch(y)dy , ­ where the integration is carried out from the heavily doped source region to the doped drain region. 4.25 plots Pch(Y) calculated from a 2-D device simulator versus distance at different gate voltages for both an abrupt and a graded source-drain (Taur et aI., 1995b). The area under each curve gives the total source-to-drain resistance at that gate voltage. In Fig. 4.25(a) for an infinitely abrupt (laterally) source-drain junction, the sheet resistivity is modulated by the gate voltage inside the (metallurgical) channel and indepen­ dent of the gate voltage outside the (metallurgical) channeL However, in contrast to a long­ channel device, Pch(Y) is highly nonuniform, with a peak near the middle of the channel and decreasing toward the edges. This is due to SeEs from the source-drain fields, which help lower the potential barrier near the junctions and raise the local inversion 4.3 MOSFET Channel Length 249 8000 ,.----­ - - - - Long channel - - - Short channel­ e.o 6000 (abrupt S-D) LOV .i:;::: ' .'S 4000 -.;.;.; ~'" 2000 ..Q en I o 1.25 V L5V Source / I Channel I \.. I I I--- Lrnet ---I I--- Leff --I Drain (a) 8000 S.D 6000 channel channel (graded .i:;::: ' ..:..E,, 4000 ~ .e.cn: 2000 0 1 L~ -_ _ _ _ _ _ _ _~_ C __ hannel _____ _ __ L_ _ _ _ _ Drain _ _ _~ I---Lmet ---I r---- Lell ---->1 (b) Figure 4.25. Simulated channel sheet resistivity at three different gate voltages versus distance from source to drain of an Lmer =0.1 O-Jlm MOSFET. The curves in (a) are for an infinitely abrupt (laterally) source-drain which Leff =0.091 Jlm. The curves in (b) are for a graded (lateral straggle UL = 165 A) source-drain which yields Leff = 0.124 !JIll. In both cases, the dashed lines represent the ideal, uniform-sheet resistivity of a scaled long-channel device. (After Taur et at., 1995b.) charge density there (Wordeman et al., 1985). This effect is more pronounced at low gate voltages near threshold. The resultingL~ffextracted by the S&R method is slightly shorter than Lmet. Figure 4.25(b) shows similar plots for the same Lmeh but with a fmite lateral source­ drain gradient. Pch(Y) again is nonuniform inside the channel, being modulated by the gate voltage. In this case, however, a nonnegligible portion ofthe sheet resistivity outside the metallurgical channel is also gate-voltage-dependent. This is because of accumula­ tion (S~ction 2.3.1) or gate modulation ofthe series resistance associated with the finite source-drain doping gradient. according to the LejJdefinition in (4.68), any part of the sheet resistivity that is gate-voltage dependent contributes to the effective 250 4 CMOS Device Design Gate n++ Xi Doping gradient Metallurgical junction p=Na Figure 4.26. Schematic diagram showing doping distribution and current flow pattern near the end of the channel and the beginning of the source or drain. The dashed lines are contours of constant donor concentration, i.e., constant resistivity. The dark region represents the accumulation layer. (After Ng and Lynch, 1986.) channel length, the extracted Leffis substantially longer than Lmet. At the same time, the extracted Rsd, which represents the constant part of the resistance in Eq. (4.68), only accounts for a portion of the series resistance outside the metallurgical channel. 4.3.3.2 Gate-Modulated Accumulation-Layer Resistance Because of the finite lateral gradient of source-drain doping in practical devices, current injection from the surface inversion layer into the bulk source-drain region does not occur immediately at the metallurgical junction. When the gate voltage is high enough to turn on the MOSFET channel, an n+ surface accumulation layer is also formed in the gate-to-source or -drain overlap region, as shown schematically in Fig. 4.26 (Ng and Lynch, .1986). Near the metallurgical junction and away from the surface, the dODor concentration (also compensated by the p-type background) is low and the conductivity ofthe accumulation layer is higher than that of the bulk source-drain. As a result, current flow stays in the accumulation layer near the surface. This continues until the source­ drain doping becomes high enough that the bulk conductance exceeds that of the accumulation layer. The point or region of current injection into the bulk depends on the lateral source-drain doping gradient. The more graded the profile is, the farther away the injection point is from the metallurgical junction. The sheet resistivity of the accumulation layer can be estimated by applying Eq. (2.195) to the gate-to-source-drain overlap region: - C ' Qac V gs Vjb +If/s ox (4.73) where Qac < 0 is the accumulation charge (electrons) per unit area induced by the gate field, 'l's is the band bending at the surface with respect to the bulk n-type region, and Vib is the 4.3 MOSFET Channel Length 251 flat-band voltage largely determined by the work-function difference betwee~ the gate electrode and the n-type silicon. For ann+-polysilicon-gated nMOSFET, Vib =-EgI2q + IfIB, where 'l'B is given by Eq. (2.48) in terms ofthe local n-type doping concentration. The band bending in accumulation is approximately given by the distance between the n-type Fermi level and the conduction-band edge, i.e., If/s::::: E/2q -If/B' Therefore, Vib and If/s in Eq. (4.73) nearly cancel each other and one obtains Vgs ~ -QadCox' The sheet resistivity of the accumulation layer is then 1­ Pac P-acI QacI P-a-cCox Vgs ' (4.74) where Pac is the average electron mobility in the accumulation layer (Sun and Plummer, 1980). 4.3.3.3 Interpretation of Lett in Terms of Current Injection Points The dependence of Pac on Vgs in Eq. (4.74) is too similar to that of Pch in Eq. (3.103) to allow separation of the accumulation-layer resistance from the channel resistance. The region where the current flows predominantly in the accumulation layer is therefore considered as a part of Leg. The physical interpretation of Leff in terms of injection points where the sheet resistivity ofbulk source-drain equals that of the accumulation layer is consistent with 2-D device simulation results (Taur et ai., 1995b). For more graded (laterally) source-drain profiles, the injection points hence Leff can be gate voltage dependent. At low gate overdrives, the injection point is closer to the metallurgical junction edge. As the gate voltage increases, the injection point moyes out toward the more heavily doped source-drain region, resulting in a longer Leg. 4.3.3.4 Implications for Short-Channel Effects The fact that Leff can be much longer than Lmet has significant implications for the short-channel Vt rolloff curves. Figure 4.27 shows the low-drain threshold voltage rolloff versus Leff for several different source-drain doping gradients. The abrupt doping profile has the best short-channel effect. As the lateral straggle UL increases, the short-channel effect becomes progressively -worse. This can be understood from the above interpretation of LeJf Current injection from the surface layer takes place at a certain source-drain doping concentration, e.g., 1019 cm~3 for nMOSFETs. For a given Leg, the distance between the points where the doping concentration falls to 1019 em~3 is fixed. The portion of the source-drain doping below 1019 em~3 penetrates into the L<;(fregion from both ends. The more graded the source-drain profile is, the deeper such an n-type doping tail penetrates into the channel and compensates or reverses the p-type doping inside the channel. This is detrimental to the short­ channel effect, as the edge regions become more easily depleted and inverted by the gate field (opposite to the halo effect). It is theiiJore very important to reduce the width of the (laterally) graded source-drain region as the channel length is scaled down. 252 4 CMOS Device Design ~ 0.0, :::: ..s:: ".0... ~ -0. !! "0 ;;.. .."0 ".0c ~ ~ -0 :J . r I 0.05 ! 1I 0.10 I 0.20 (1L: t,. 0 o 165 A ¢ 330A II 0.50 Lett (IJ.m) Agura 4.27. Simu1l).ted short-channel threshold rolloffversus Lefffor three different lateral source-drain doping gradients. On each curve, the points are for Lmet=0.05, 0.07, 0.10, 0.15, 0.25, and 0.50 1J.ffi. (After Taur et al., 1995b.) 4.3.4 Extraction of Channel length by C-VMeasurements In an entirely different approach, another type ofchannel length has been extracted from the measured C-Vdata ofa series ofMOSFETs with differentLmask (Sheu and Ko, 1984). Capacitance measurements in general are more difficult to perform, as they require speciallydesigned test sites. It is by no means straightforward to interpret the capacitively measured channel length and apply it to circuit models for current calculations. The capacitive extraction of channel length is based on the fact that when a MOSFET is turned on, the intrinsic gate-to-channel capacitance is proportional to the channel length: Cge = Cow WLcap. (4.75) Here Leap is the capacitively defined channel length, which mayor may not be the same as Leffor Lmel• The gate-to-channel capacitance is usually measured in a split C-V setup that separates the majority-carrier response from the minority-carrier response, as shown in the inset of Fig. 4.28. The total measured capacitance consists of both the intrinsic gate-to-channel capacitance and a parasitic overlap capacitance from the gate to source­ drain which is independent of channel length: + CIOI Cg(. 2Col' = + WLcup 2Cov . (4.76) Here Cov is the overlap capacitance per gate edge (see Fig. 5.19). Typical examples of CtorVgs curves are shown in Fig. 4.28 (Guo et al., 1994). Using a large"area MOS capacitor, one can easily calibrate C;nv> taking all the polysilicon depletion and.inversion­ layer quantum effects into account. To find out Leap, it is critical to determine what 2Cov to subtract from the measured Ctol. In principle, 2eov in Eq. (4.76) is the parasitic . 4.3 MOSFET Channellengtfl 3.0 .-,~...,.-..--,...-,..--,--..,..-,--,--,-""'-,--..--.--r-,--"'-""""""""" 253 2.0 G:: '~" ,} ........ - - - - - - - / L..as.t=l.Of,1m I II ••••••.L__m•a••sk-=--0-.-8-1.J-.l-1-1--------- I/lf//~--L-"-",-sk-=O-.-7/-Ul-l ---­ 1.0 0.0 -5 -4 2 Co. ~j v, Vgs (V) 2345 Figura 4.28. Example of measured capacitance from gate to source-drain versus gate voltage for MOSFETs of different mask lengths. The inset shows the split C-V measurement setup. (After Guo etal., J994.) capacitance at a gate voltage when the MOSFET is on and Cgc is given by Eq. (4.75). In practice, 2Cov cannot be separated from Cgc, since, unlike channel resistance, channel capacitance does not vary significantly with gate voltage once the device is turned on. What is usually done is to take 2Cov as the measured capacitance when the MOSFET is off. However, from Fig. 4.28 it is clear that 2Cov varies with the gate voltage (Oh et al., 1990). There is no guarantee that 2Cov in the off state is the satpe as 2Cov in the on state. If2Cov is taken as the capacitance right below the threshold voltage, it will contain an unwanted inner-fringe term that is absent when the conducting channel is formed. If 2Cov is taken at a negative gate voltage where the substrate is accumulated to eliminate the inner-fringe component, the lightly doped source-illain in the direct overlap region will be depleted (Sheu and Ko, 1984). Any such error in 2Cov translates into a large error in Leap when dealing withs4ort-channeLdevices having small intrinsic capacitances. A better interpretation of the .capacitively extracted channel length is in terms of the gate length, Lgale (Fig. 4.22), since as the gate voltage varies, the same amount of charge per unit area is induced at the silicon surface whether it is in the inversion channel or in the source-illain overlap region under the gate. In other words, as far as the capacitance is concerned, the direct overlap length should be lumped into the channel length. This also circumvents the problem with the inner-fringe component mentioned above. One still needs to estimate the .outer fringe capacitance and subtract it from the measured capaci­ tance. But the outer fringe is smaller and can be estimated reasonably accurately using a simple formula (Section 5.2.2). 254 4 CMOS Device Design Exercises 4.1 Apply constant-field scaling rules to the long-channel currents [Eq. (3.23) for the linear region and Eq. (3.28) for the saturation region], and show that they behave as indicated in Table 4.1. 4.2 Apply constant-field scaling rules to the subthreshold current, Eq. (3.40), and show that i~stead of decreasing with scaling (l11C), it actually increases with scaling (note that Vgs < 1't in subthreshold). What if the temperature is also scaled down by the same factor T!IC)? 4.3 Apply constant-field scaling rules to the saturation current from the n"" I saturation model [Eq. (3.79)] and the fully saturation-velocity limited current (3.81 )], and show that they behave as indicated in Table 4.1. 4.4 Apply generalized scaling rules to the saturation current from the n = 1 velocity saturation model [Eq. (3.79)], and show that it behaves as indicated in Table 4.3 (between the two limits). 4.5 Consider an n-channel MOSFET with n+ polysilicon gate (neglect poly depletion effect). The gate oxide is 7 nm thick, and the p-type body (or substrate) has a retrograde doping as shown in Fig. 4.12 with Ns=O. Take 2V'B= 1 V. (a) Choose the values of Xs and No such that the maximum depletion width is Wdm=O.1 J1l11 and the threshold voltage (at 2V'B) is V,=O.3 V. (b) Following (a), what is the body effect coefficient, m, and the inverse slope of log subthreshold current versus gate voltage (long-channel device)? (c) Following (a), how short a channel length can the device be scaled to before short-channel effect becomes severe? 4.6 Nonuniform V, in the width direction. A MOSFET is nonuniformly doped in the width direction. Part of the width (WI) has a linear threshold voltage Vonl (defined in Fig. 3.18). The other part of the width (W2) has a linear threshold voltage v"n2' Show that as far as the linear region characteristics are concerned, this device is equivalent to a uniform MOSFET of width WI + Wz with a linear threshold voltage Von (WI Von I + W2 Von2)/( WI + W2). Ignore any fringing fields that may exist near the boundary between the two regions. 4.7 Nonuniform V, in the length direction. A MOSFET is nonuniformly doped in the length direction. Part ofthe length (L I ) has a linear threshold voltage v"nl' The other part of the length (L 2) has a linear threshold voltage Van2• Assume Voni ;::: and consider only the first-order terms of Von I VonZ' Show that as far as the linear region characteristics are concerned, this device is equivalent to a uniform MOSFET of LI + L2 with a linear threshold voltage Von (LI v"nl + L2 Von2)!(LI + L2)' Ignore any fringing fields that may exist ncar the boundary between the two regions. 4.8 In the top equivalent circuit of Fig. 4.23, the source-drain current can be considered either as a function of the internal voltages: Ids ( V;Sl V~J, or as a function of the. external voltages: Ids Vds)' The internal voltages are related to the external Exercises 255 voltages by Eqs. (4.63) and (4.64). Show that the transconductance of the intrinsic MOSFET can he expressed as g'm (aaVId' s) gs 1"", gm . gmRs - gds(Rs + Rd) , where gm == (aaVIgdss) Vd, is the extrinsic transconductance, and gds (aavIddss) v., is the extrinsic output conductance. 4.9 Show that in the subthreshold region and when the drain bias is low, Eq. (3.12) leads to (4.51): Q,. kTnT q",,fkT W/,N e. , a where V's is the surface potential and W/, is the surface electric field. This equation is more general than Eq. (3.36) since it is valid for nonuniform (vertically) dopings with Na being the p-type concentration at the edge of the depletion layer. (Note that the factor No merely reflects the fact in Fig. 2.32 that the band bending VIs is defined with respect to the bands of the neutral bulk region of doping No.) 4.10 In a short-channel device or in a nonuniformly doped (laterally) MOSFET, V's may vary along the channel length direction from the source to drain. Generalize the expression in Exercise 4.9 and show that r r dsV = _1_ L ~ = L No 2 W/s(y)e-q'l',(y)/kTdy Jo Jo J.lejjW Qi{Y) J.leffWkTnj for the subthreshold region at low drain biases. Since W/S (y);::: [Vgs - VJb­ is not a strong function of 11'" the exponential factor dominates. This implies that the subthreshold current is controlled by the point of highest barrier (lowest V's) in the channel. It also implies that the channel length factor entering the subthreshold current expression is different from the effective channel length defined by the linear region characteristics, Eq. (4.61). 4.11 Consider a uniformly doped nMOSFETofNa = 1018 biased at the threshold condition. Calculate the first three quantum mechanical energy levels for inver­ sion electrons in the lower valley with an effective mass of O.92mo where mo is the free electron mass. Express the answers in eV. 4.12 For an nMOSFETwith tox = lOnmand a uniform p-type doping of 10 17 c m - 3 • the gate is n+ polysilicon doped to 1020 cm- 3. Estimate the depletion layer width in the polysilicon gate at a gate voltage of3 V. 5 CMOS Periormance Factors 5.1 Basic CMOS Circuit Elements 257 (a) o-i o-i --I10ooo ~ --I10ooo p-substrate ~ The performance ofa CMOS VLSI chip is measured by its integration density, switching speed, and power dissipation. CMOS circuits have the unique characteristic ofpractically zero standby power, which enables higher integration levels and makes them the technology of choice for most VLSI applications. This chapter examines the various factors that determine the switching speed of basic CMOS circuit elements. 5.1 5.1.1 Basic CMOS Circuit Elements In a modem CMOS VLSI chip, the most important function components are CMOS static gates. In gate array circuits, CMOS static gates are used almost exclusively. In microprocessors and supporting circuits of memory chips, most of the control interface logic is implemented using CMOS static gates. Static logic gates are the most widely used CMOS circuit because of their simplicity and noise immunity. This section describes basic static CMOS circuit elements and their switching characteristics. Circuit symbols for nMOSFETs and pMOSFETs are defined in Fig. 5.1. A MOSFET is a four-terminal device, although usually only three are shown. Unless specified, the body (p-substrate) terminal ofan nMOSFET is connected to the ground (lowest voltage), while the body terminal (n-well) of a pMOSFET is connected to the power supply Vdd (highest voltage). CMOS Inverters The most basic element of digital static CMOS circuits is a CMOS inverter. A CMOS inverter is a combination ofan nMOSFET and a pMOSFET, as shown in Fig. 5.2 (Bums, The source terrninal ofthe nMOSFET is connected to the ground, while the source of the pMOSFET is connected to Vdd. The gates ofthe two MOSFETs are tied together as the input node. The two drains are tied together as the output node. In such an arrange­ ment, the complementary nature ofn- and pMOSFETs allows one and only one transistor to be conducting in one of the two stable states. For example, when the input voltage is or when Vin = Vda, the gate-to-source voltage of the nMOSFET equals Vda, which turns it on. At the same time, the gate-to-source voltage of the pMOSFET is zero, so the pMOSFET is off. The output node is then pulled down to the ground potential by currents through the conducting nMQSFET, which is referred to as the pull-down transistor. On v.. VilJ Jr 0---9 0---9 (b) --I10ooo J n-well Figure 5.1. Circuit symbols and voltage terminals of (a) nMOSFET and (b) pMOSFET. Vdd v.. Vdd j --...­ Tn p-substrate ~ Figure 5.2. Circuit diagram and schematic cross section of a CMOS inverter. the other hand, when the input voltage is low or when Vin = 0, the nMOSFET is off, slnce its gate-to-source voltage is zero. The gate-to-source voltage ofthe pMOSFET, however, is -Vad, which turns it on (a negative gate voltage turns on a pMOSFET). The output node is now pulled up to Vdd by the conducting pMOSFET, which is referred to as the pull-up transistor. Since the output voltage is always opposite to the input voltage (VOUI is when Vin is low and vice versa), this circuit is called an inverter. Notice that since only one ofthe transistors is on in the steady state, there is no static current or static power dissipation. Power dissipation occurs only during switching transients when a charging or discharging current is flowing through the circuit. 5.1.1.1 CMOS Inverter Transfer Curve In a CMOS inverter, both the current through the nMOSFET (IN> 0) and the current through the pMOSFET (Ip > 0) are functions of the input voltage to the gates, Vim 258 5 CMOS Perfonnance Factors (a) (b) IN Ip 11;.=0­ (Vc. 0 or I < O. The directions of the currents are depicted in Fig. 5.2. 5.1 Basic CMOS Circuit Elements 259 VOlt, Vdd r--- .-..., Figure 5.4. Va., versus Vm curve (transfer curve) ofa CMOS inverter. Points labeled A, C, E, D, B correspond to the steady state points of operation (circles) indicated in Fig. 5.3(c). There are two points ofoperation where both II' and where and Vdd, and point B where Yin = Vdd and v"w= O. In between, the corresponding v"w is obtained from the intersection of two curves, IMVin) and IP(Yin), as shown in Fig. 5.3(c). In this way, one can construct a v"UI versus Yin curve, ora transfer curve ofthe CMOS inverter in Fig. 5.4. For low values of Yin such as point C, v"UI is high and the nMOSFET is biased in saturation while the pMOSFET is biased in the linear region [Vi"i in Fig. 5.3(c)]. For high Yin such as point D, v"w is low and the nMOSFET is in the linear region while the pMOSFET is in saturation in Fig. 5.3(c)). For point E near Yin Vdj2 [Vin2 in Fig. 5.3(c)], both devices are in saturation. It is in a transition region where v"., changes steeply with Yin. In order for the high-to-low transition of the transfer curve to occur close to the midpoint, Vin = Vd/2, it is desiredfor Ipand INto be nearly symmetrical, as illustrated in the example in Fig. 5.3. This requires the threshold voltages of the n- and pMOSFETs to be symmetrically matched. In addition, since the pMOSFETcurrent per width, Ip = [pi WI" is inherently lower than that of the nMOSFET, In = III Wm the device width ratio in a CMOS inverter should be Wp In (5.1) Wn lp' such that Ip-:::;IN• In the long-channe-1 limit, Inllp r:x PnlPp ~ 4 from Eq. (3.28) and Figs 3.15 and 3.16, assuming matched channel lengths and threshold voltages. For short-channel devices, however, the ratio is smaller since nMOSFETs are more saturated than pMOSFETs. Typically, the current-per-width ratio IJIp is about 2-2.5 for deep-submicron CMOS technologies; therefore, W/WI! =2 is a good-choice for CMOS inverter design. 5.1.1.2 CMOS Inverter Noise Because of the nonlinear saturation characteristics of the MOSFET curves, the curve is also nonlinear_ The maximum slope ofthe high-to-Iow transition 260 5 CMOS Performance Factors Flgure5.S. _____~~lJ;,,~outl ~V;n3 V~VO"12 ........... --'4." __ _ ........... Noise Noise Noise ........... Noise Voul4 -----...... Noise A cascade chain of identical CMOS inverters. The noise voltages at the input of each stage are for the discussion of Fig. 5.7. figure 5.6. Vdd .....1 ;/t'''''' _;/t"-'" .~"" ~~ JJ 1i .. ~~ ......, .,.' .........""...... .' ')-"'-'-~-­ - _,>,., .' , :"'.~ HU ••••••••• ac5l .// ! '\ .' ". / " ~: \ '. : : "\ 0o·" Solid: V;nl' V!n3 .... Dashed: v..a.V..,4'·" Vdd The solid transfer curve is for odd numbered inverter stages. The flipped, dashed !ransfer curve is for even numbered stages. The connected line segments between the curves depict the trajectory of node voltages through successive inverter stages. ofthe v"UI-Vin curve, IdVQU1Idfi"l, referred to as the maximum voltage gain, is a measure of the (Exercise 4.8) ratio of the two transistors. From the condition W"l,,(Vgsm Vdsn) WpIP(Vgsp, Vdsp), it can be shown that Wngmn + Wpgmp dVin Wngdsn + Wpgdsp ! (5.2) wheregmn == aI.joVgsn, gmp -8Ipj8Vgsp(>O),gdsn == (> 0), etc. gd,p == -8lpj8Vdsp A commonly employed scheme to quantify the noise margin of a transfer curve is to consider a chain of identical inverters in cascade as shown in Fig. 5.5. The solid curve in Fig. 5.6 represents the transfer curve ofinverters #1, #3, ... , i.e., v"u,! vs. f'tnlt v"u13 vs. f'tn3, etc. A complcmentary dashed curve is generated by flipping or mirror imaging the solid curve with respect to the chained line, f'tn = v"",. It represents the inverse transfer curve of inverters #2, #4, #6, ... , i.e., f'tn2 vs.voutb f'tn4 vs. VQut4, etc. In this graphical construction, one can visualize a trajectory of alternating horizontal and vertical lines between the two curves as the node voltal1e makes its transitions through the inverter 5.1 Basic CMOS Circuit Bements 261 stages. Starting with dot il on the solid curve at coordinates (f'tnlt Vautl), the next point i2 is on the dashed curve at coordinates-(v"ut2, f'td. The line between il and i2 is horizontal. since Vin2 Voutl ' The next point i3 is back on the solid curve with coordinates (Vln3, v,,"(3), and is connected to i2 by a vertical line as fin3 =Y:;,ut2, etc. In this example, the . node voltage is pushed after each inverter stage closer and closer to the upper left comer corresponding to v,,"1 Vdd for subsequent odd stages and v"", = 0 for subsequent even stages. Ifthe starting point is below the fin == Vou, intercept such as the circle in Fig. it will be pushed in dotted line segments to the lower right comer, i.e., 0 for subsequent odd stages and v,,"1 Vdd for subsequent even stages. Such a characteristic is called "regenerative" which widens the noise margin as the node voltage is restored to one of the extremes of the binary digital states. To add noise to the above picture, we consider only two inverter stages with the transfer curves depicted in 5.7(a). A positive noise voltage at the input to inverter #1 (Fig. 5.5) kicks the starting point from il to i1' on the solid curve. Ifthere is no noise at the to inverter #2, the output after two inverter stages will end up at point i3 shown. Ifi3 is to the left of il, then there is a net gain of noise margin after the two inverters with noise. On the other hand, ifi3 is to the right of il, then there is a net loss ofnoise margin. In that case, the input voltage to the odd-numbered inverters may keep increasing through repeated cycles with noise. Finally it will cross over the fin VOUI line and the logic state is lost (flipped). The maximum noise voltage that can. be tolerated is then the one that causes i3 to fall back on top of i1. We now add a negative going noise voltage of the same magnitude to the input of inverter #2 (Fig. 5.5). Note that for this example, while a positive going noise voltage is worst at input I, a negative going noise is worst at input 2. As shown in Fig. 5.7(b), the negative noise voltage kicks the input to inverter #2 from i2 to i2' . The maximum noise magnitude that can be tolerated without eventually losing the logic state is the one that returns exactly to il after two noisy stages. Therefore, the noise margin for a given transfer curve is measured by the size ofthe maximum square that canfit between itself and its complementary curve (Hill, 1968). A different way of arriving at the same result is described in 9.7 for the noise margin ofSRAM cells. It is evident that for given n­ and pMOSFETs, a wider noise margin is achieved with the width ratio ofEq. (5.1) so that the high-to-Iow transition of the transfer curve happens at VdJ2. Since most ofthe noise interference in a chip environment originates from coupling of voltage transients in the neighboring lines or devices, the noise magnitude is expected to scale with the power supply voltage (except those with other natural origins such as "soft error" due to high-energy particles). Thermal noise has too Iowa magnitude ofconcern as long as Vdd» kTlq. Therefore, a relevant measure ofthe noise margin in a CMOS circuit is the normalized VNMVdd, where VNM is the side ofthe maximum square in Fig. 5.7(b). Large VN/jVdd (up to 0.5 in principle) is obtained with a highly skewed, symmetric transfer curve, i.e., one that has VOUI staying high at low to medium f'tnt then making an abrupt high-to-low transition at f'tn VdJ2. It can be seen from the construction of the transfer curve in Fig. 5.3(c) that for a given Vdd, VNljVdd improves with a higher threshold voltage, V/Vdd. In fact, the best noise margin is achieved with subthreshold operation (Frank et al., 200 I), although with poor delay performance. As Vdd is scaled 262 5 CMOS Performance Factors (a) Vdd / ,­ ,.,.,.,. ;:;~,_ ;:;'.0i 1] i2\~''''''-'--' i1' .,..,'/ .;,' .................. - .'." /.~---" i"/'- ......, .. ot5l ,/ .' .' . ./ ... .' / .' " .'\ ' '\ \ \ '\ \ Solid: \»nl Vdd Dashed: VO"t2 -~"i:i ].. ot5l Figure 5.7. Solid: \».1 \'ad Dashed: Vout2 (a) Node voltage trajectory with noise added to the input to inverter#l. (b) Node voltage trajectory with positive noise at inverter #1 and negative noise at inverter #2. The shaded area represents the largest square that can be circumscribed in between the two transfer curves. The side of the square, VNM, is a measure of the noise margin. down, VN~Vdd is not particularly sensitive toVdd until Vdd becomes comparable to kTlq. In order to have the nonlinear I-V characteristics necessary for digital circuit function, a minimum Vdd of several kTlq, e.g., 100-200 mY, is required (Swanson and Meindl, 1972). At I V level, the choice of power supply voltage for static CMOS logic circuits is largely based on power and performance considerations discussed in Section 5.3.3, not noise margin. 5.1.1.3 CMOS Inverter Switching Characteristics We now consider the basic switching characteristics of a CMOS inverter. The simplest waveform is when the gate voltage makes an abrupt or infinitely sharp transition 5.1 Basic CMOS Circuit Elements 263 from low to high or vice versa. For example, consider the inverter biased at point A in Fig. 5.3(a) when ~n makes asreptransition from 0 to Vdd. Before the transition, the nMOSFET is off and the pMOSFET is on. After the transition, the nMOSFET is on and the pMOSFET is off. The trajectory of v.,ut from point A to point B follows the ~n = Vdd curve ofthe nMOSFET as shown in Fig. 5.3(a). lfthe total capacitance ofthe output node (including both the output capacitance ofthe switching inverter and the input capacitance of the next stage or stages it drives) is represented by two capacitors one (C) to the ground and one (C+) to the Vdd rail, as illustrated in Fig. 5.2 - then the pull-down switching characteristics are described by C + C d(Vout - Vdd) -J (V = - + dt Nm or (C_ + C+) dV"ut = Vdd ), (5.3) with the initial condition Vouit=O)= Vdd. Here C = C_ + C+ includes both the capacitance to ground and the capacitance to Vdd. For simplicity, we approximate the IN ( ~n = Vdd) curve by two piecewise continuous lines. In the saturation region (v.,ut > V Vdd -> 0) or down-up (Vdd -> 0 -+ Vdd). In that case, we sayan energy of CV~d is dissipated per cycle. (An exception is Miller capacitances between two switching nodes, to be discussed in Section 5.3.4.) Since dc power dissipation is negligible in CMOS circuits, the only power consump­ tion comes from switching. (Standby power dissipation oflow- VI devices is discussed in Section 5.3.3.) While!!:e peak power dissipation in a CMOS inverter can reach Vdd lonN 5.1 Basic CMOS CircuH Elements 265 or Vdd I onP, the average power dissipation depends on how often it switches. In a CMOS processor, the switching oflogic gates .is-controlled by a clock generator offrequencyf If on the average a total equivalent capacitance C is charged and discharged within a clock ­ cycle ofperiod T= lifo the average power dissipation is - r P CV3d CVJdf (5.6) Note here that each up or down transition of a capacitor within the period T contributes half of that capacitance to C. If, for example, a capacitor is switched four times (goes through the up-down cycle twice) within the clock period, its capacitance is counted twice in C. Equation (5.6) will be used in the discussion of power-delay tradeoff in Section 5.3. The above simplified delay and power analysis assumes abrupt switching of Vin' In general, Vi. is fed from a previous logic stage and has a finite rise or fall time associated with it. The switching trajectory from A to B or from B to A in Fig. 5.3 then becomes much more complicated. Instead of staying on one constant-fin curve, the bias point moves through different curves as Vi. ramps up or down. Furthermore, both IN and Ip must be considered during either a pull~up or a pull-down transitioll, since the other transistor is not switched offcompletely as one transistor is turned on. This also means that there is a crossover, or short-circuit, current that flows momentarily between the power-supply terminal and the ground in a switching event, which adds another power dissipation component to Eq. (5.6). One last complication is that the output node capacitances C and C+ are generally voltage-dependent rather than being constant as assumed above. More extensive numerical analysis ofthe general case will be given in Section 5.3. 5.1.1.5 Quasistatic Assumption In the above discussion ofCMOS switching characteristics, it was implicitly assumed that the device response time,the time required for charge redistribution, is fast compared with the time scale the terminal voltage is changed. This is called the quasistatic assump­ tion. In other words, the device current responds instantaneously to an external voltage change. This assumption is valid ifthe input rise or fall time is much longer than the carrier transit time across the channel. In general, the carrier transit time can be expressed as L dy J tr 0 v(y)' (5.7) where v(y) is the carrier velocity at a point y in the channel. Current continuity requires 1= WQ,{Y)V(Y) be a constant, independent ofy. Equation (5.7) then becomes WjL Ir I 0 Q;(y)dy =[Q/' (5.8)' . where QJ is the total mobile charge in the device. For a long-channel MOSFET in saturation, I is given by Eq, (3.;:8)apd Q/ is given the integration of Eq. (3.59) or the expression above (3.60). Therefore, the transit 266 5 CMOS Performance Factors time is of the order of L2/J1ejjVdd. For a completely velocity saturated device, the transit time approaches L/VSQ" which is of the order of lOps for 1 f.UI1 MOSFETs and 1 ps for 0.1 f.UI1 MOSFETs. These numbers are at least an order of magnitude shorter than the delay of an unloaded CMOS inverter made in the corresponding technology (Taur et ai., 1985; Taur et at., I 993c). This indicates that the switching time is limited by the parasitic capacitances rather than by the time required for charge re-distribution within the transistor itself and thus validates the QuaSistatic approach. 5.1.2 CMOS NAND and NOR Gates CMOS inverters described in the last subsection are used to invert a logic signal, to act as a buffer or output driver, or to form a latch (two inverters connected back to back). However, they cannot perform logic computation, since there is only one input voltage. In the static CMOS logic family, the most widely used circuits with multiple inputs are NAND and NOR gates as shown in Fig. 5.9. In a NAND gate, a number ofnMOSFETs are connected in series between the output node and the ground. The same number of pMOSFETs are connected in parallel between Vdd and the output node. Each input signal is connected to the gates of a pair of n- and pMOSFETs as in the inverter case. In this configuration, the output node is pulled to ground only if all the nMOSFETs are turned on, i.e., only ifall the input voltages are high ( Vdd). Ifone ofthe input signals is low (zero voltage), the low-resistance path between the output node and ground is broken, but one of the pMOSFETs is turned on, which pulls the output node to Vdd . On the contrary, the NOR circuit in Fig. 5.9(b) consists of parallel-connected nMOSFETs between the output node and ground, but serially connected pMOSFETs between Vdd and the output node. The output voltage is high only if all the input voltages are low, i.e., all the pMOSFETs are on and all the nMOSFETs are off. Otherwise, the output is low. Due to the complementary nature of n- and pMOSFETs and the serial-versus-parallel connections, there is no direct low-resistance path between Vdd and ground except during switching. In other words, just like CMOS inverters, there is no static current or stIlndby power dissipation for any combination of inputs in either the CMOS NAND or NOR circuits. The circuit output resistance is low, however, because ofthe conducting transistor(s). In CMOS technology, NAND circuits are much more frequently used than NOR. This is because it is preferable to put the transistors with the higher resistance in parallel and those with the lower resistance in series. Since pMOSFETs have a higher resistance due to the lower hole mobility, they are rarely used in series (stacked). By connecting low­ resistance nMOSFETs in series and high-resistance pMOSFETs in parallel, a NAND gate is more balanced in terms ofthe pull-up and the pull-down operations and achieves better noise immunity as well as a higher overall circuit speed. 5.1.2.1 Two-Input CMOS NAND Gate As an example, we will examine the transfer curve and the switching characteristics of a two-input NAND gate, also referred to as a two-way NAND, or NAND with a fan-in of two, shown in Fig. 5.1 O. With the two pMOSFETs connected in parallel between Vdd and the output node, the pull-up operation of a two-way NAND is similar to that of an 5.1 Basic CMOS Circuit Elements 267 Vdd vmll (8) v. 2o---L--i In J 0 Vout Vdd (b) Vin2 o----,----d ) 0 Vout Fioll.... !ilt rirr.nit ni~or"m "f(o' rMOS NANn "nn (hi f'MOS NOR MlIltinlp innllt ';(7n.'. "rp loh"lf\n 268 5 CMOS Performance Factors Vdd YOU! 5.t Basic CMOS Circuit Elements 269 Vout Vdd 1-1- - _ _ . ; : ' " Vjn2 C>---L--.I Figure 5.10. Circuit diagram of a two-input CMOS NAND. The transistors are labeled PI, P2 and Nl, N2. inverter. If either one of the transistors is being turned on while the other one is off, the charging current is identical to that of the pMOSFET pull-up in a CMOS inverter discussed in the previous subsection. Ifboth transistors are pulling up, the total charging current is doubled as ifthe pMOSFETwidth had been increased by a factor oftwo. On the other hand, the two nMOSFETs are connected in series (stacked) between the output and ground, and their switching behavior is quite different from that of the inverters. For the bottom transistor N2, its source is connected to the ground and the gate-to-source voltage is simply the input voltage Vi,,2' However, for the top transistor Nl, its source is at a voltage V;r (Fig. 5.10) higher than the ground. Vx plays a crucial role in the switching characteristics of NI, since the gate-to-source voltage that determines how far N1 is turned on is given by Vi" I - Transistor N1 is also subject to the body-bias effect, as a source voltage Vx is analogous to a reverse body (substrate) bias Vbs = -Vx in Fig 3.13, which raises the threshold voltage ofNI as described by Eq. (3.44). There are three possible switching scenarios, each with different characteristics. They are described below. • Case A. Bottom switching: Input 2 switches while input 1 stays at Vdd. Initially, even though Vi" I Vdd, but Vo: > Vdr V, so that Vgs(Nl) Vdd Vx < Vt and both NI and N2 are in subthreshold. The pull-down transition in case A when input 2 rises from 0 to Vdd is most similar to the nMOSFET pull-down in an inverter. For low input voltages Vin2 <:; Vdd!2, transistor N2 is in saturation. Transistor N1 can be in the linear region or in saturation. In either case, NI only acts to reduce the drain voltage ofN2 with little effect on the current. The transfer CUNe of Vout versus Vin2 in this case is similar to that of a CMOS inverter, which exhibits symmetrical characteristics if Wp/ W" = In! Ip ~ 2, as shown in Fig. 5.11. For high input voltages Vin2 > Vdd/2, the current is somewhat degraded by the resistance ofNI as transistor N2 moves out of saturation. • Case B. Top switching: Input 1 switches while input 2 stays at Vdd• For the pull-down transition in case B, transistor Nl is in saturation while N2 is in linear mode during o Vddl2 Vdd Vin2 Figure 5.11. Transfer curves ofa two-input CMOS NAND for different cases ofswitching discussed in the text. The device width ratio Wp / W. is taken to be 2 in this illustration. most part of the switching cycle. Transistor N2 therefore acts like a series resistance connected in the source terminal ofN!. The voltage Vo: between the two transistors rises slightly above ground, depending on the current level. This degrades the pull­ down current as the gate-to-source voltage of Nl is reduced to Vi,,1 - Vx and its threshold voltage is increased by (m-l)Vx due to the body effect. As a result, a slightly higher input voltage Vi"l is needed to reach the high-to-low transition of the transfer curve in Fig. 5.11. Even though the pull-down current in case B is slightly less than in case A, the switching time in case B is comparable to that in A if the output is not too heavily loaded. This is because of the additional capacitance in case A associated with the top transistor Nl that needs to be discharged from Vda to ground when the bottom device is switching. These factors are further discussed in detail in Section 5.3.5. • Case C. Both input I and input 2 switch simultaneously. The worst case for pull-down in a two-input CMOS NAND is case C, in which both inputs rise from 0 to Vdd. It can be seen that transistor N2 is always biased in the linear region, while transistor N 1 is in the linear region for small values of Vout and in saturation for large Vout. In this case, the nMOSFET pull-down current is reduced by approximately a factor of two from the inverter case becausle ofthe serial connection. The pull-up current, on the other hand, is twice that of the inverter case due to the parallel connection of pMOSFETs. This moves the high-ta-low transition in the transfer curve to a Vi" significantly higher than VdJ2, as shown in case C of Fig. 5.11. 5.1.2.2 Noise Margin of NAND Circuits Because of the spread of transfer curves under different switching conditions, the noise margin of a CMOS NAND gate is inferior to that of a CMOS inverter. In an 270 5 CMOS Performance Factors Vddr ,<;:: == '" :::;.$ .i:::j ~O]a " ,,,,,, o ~----_'='_-" Solid: Vi" Vcid Dashed: 'fout Figure 5.12. An example of worst-case noise margin of NAND circuits. Curve C' is the mirror image of C with respect to the axis Vin Vout (Liu et at., 2006). exaggerated case shown in Fig. 5.12, curves A and C represent the extremes of all possible transfer curves. The best that can be done with the width selection (WpIWn) is such that A and C are symmetric on either side of V Lmet (Section 4.3.3). 5.2.1.2 Sheet Resistance Next, we examine Rsh and Reo. In diffusion region is simply, 5.16, the sheet resistance of the source-drain S Rsh = Psd W' (5. 276 5 CMOS Performance Factors where W is the device width, S is the spacing between the gate edge and the contact edge, and Psd is the sheet resistivity of the source-drain diffusion, typically of the order of 50-500 Q/o. Since Psd «Peh ofthe device, this term is usually negligible ifS is kept to a minimum limited by the overlay tolerance between the contact and the gate lithography levels. In a nonsilicided technology, S= a in Fig. 5.13, provided that most of the device width dimension is covered by contacts. 5.2.1.3 Contact Resistance Based on a transmission-line model (Berger, 1972), the contact resistance can be expressed as V R ";PsdPc coth (Ie ~), eo W Pc I) where Ie is the width of the contact window (Fig.·5.16), and Pc is the interfacial contact resistivity (in O-cm2) of the ohmic contact between the metal and silicon. Reo includes the resistance of the current crowding region in silicon underneath the contact. In a non­ silicided technology, le= c in Fig. 5.13. Equation (5.11) has two limiting cases: short contact and long contact. In the short-contact limit, Ic«(pjPsd/tl, and R Pc co Wlc (5.12) is dominated by the interfacial contact resistance. The current flows more or less unifonnly across the entire contact. In the long-contact limit, Ie» (PjPsd)ltl, and R ";PsdPc co W (5.13) This is independent of the contact width I", since most of the current flows into the front· edge ofthe contact. Once in the long-contact regime, there is no advantage increasing the contact width; (PjPsd)ltl is referred to as the transfer length in some literature. For ohmic contacts between metal and heavily doped silicon, current conduction is dominated by tunneling or field emission. The contact resistivity Pc depends exponen­ tially on the barrier height : due to bird's-beak near the gate edge resulting from a reoxidation step (Wong et aI., 1989). Therefore, loy should be interpreted as an equivalent overlap length, rather than an actual physical length. By solving Laplace's equation analytically with proper boundary conditions, the outer and inner fringe components can be expressed as (Shrivastava and Fitzpatrick, 1982) + Co! 2f.oXWln(1 tgate ), 11: tox (5.18) and Xj) Clf -2e-siIWn ( 1 +-2- , 11: tox (5.19) where tgate is the height of the polysilicon gate, and Xj is the depth of the source or drain junction. Equations (5.18) and (5.19) assume ideal shapes of the polysilicon gate and source-drain regions with square corners. In case the source-drain junctions are deeper than the gate depletion depth Wd , Xj in (5.19) should be replaced by Wd . For typical values of tgal VI> the inversion layer forms, which effectively shields any electrostatic coupling between the gate and the inner edges of the source or drainjunction. Similar shielding ofthe inner fringe capacitance also takes place when the gate voltage is negative (for nMOSFETs) and the surface is accumulated. Under these 280 5 CMOS Performance Factors conditions, the overlap capacitance consists ofonly the direct overlap and the outer fringe components. From the above numerical estimates, one can write the total overlap capacitance at o(silicon is depleted under the gate) as 7). Cov(VgS = 0) = Cdo + Coj+ Cif ~ eoxw(lov tox + (S.20) Note that Eq. (S.20) is the maximum overlap capacitance per edge. It assumes perfectly conducting source and drain regions. In reality, because of the lateral source-drain doping gradient at the surface, the overlap capacitance depends on the drain voltage. When the drain voltage increases in an nMOSFET (with the same gate-to-substrate voltage), the overlap capacitance tends to decrease slightly because the reverse bias widens the depletion region at the surface and therefore reduces the effective overlap length (Oh et aI., 1990). This is especially the case with LDD (lightly doped drain) MOSFETs. It has been reported that a minimum length of direct overlap region of the order of lov:'::: (2-3)to.< is needed to avoid reliability problems arising from hot-carrier injection into the ungated region (Chan et al., 1987b). In other words, such a margin is required to avoid "underlap" of the gate and the source-drain. Combining this requirement with Eq. (S.20), one obtains Co.! W ~ 10 Box ~ 0.3 fF!1ffil at zero gate voltage, independent of technology generation. 5.2.3 Gate Resistance In modern CMOS technologies, silicides are formed over polysilicon gates to lower the resistance and provide ohmic contacts to both n+ and p+ gates. The sheet resistivity of silicides is of the order of 2-10 illo, which is generally adequate for O.S-Ilm CMOS technology and above. For 0.2S-llm CMOS technology and below, however, the device delay improves and gate RC delays may not be negligible. Compounding the problem is a tendency for silicide resistivity to increase in fine-line structures. This is due to either agglomeration or lack ofnucleation sites to initiate the phase transformation in the case of TiSi2 . Gate RC delay is an ac effect ~ot observable in dc I-V curves. It shows up as an additional delay component in ring oscillators, delay chains, and other logic circuits. Gate RC delay can be analyzed with a distributed network shown in Fig. S.21 for a MOSFET device of width Wand length L. The resistance per unit length R is related to the silicide sheet resistivity pg (illo) by R (5.21) The capacitance per unit length, C, mainly arises from the inversion charge that must be supplied (or taken away) when the voltage at a particular point along the gate increases (or decreases). To a good approximation, C is given by the gate oxide capacitance, C C L = Box L . ox tox (S.22) 5.2 Parasitic Elements 281 Gate I ' " I .1 "'1 I mr! 1L Figure 5.21. x=o x=W A distributed network for gate RC delay analysis. The lower rail represents the MOSFET channel, which is connected to the source-ins Cw = In(b/a) . (5.30) connect scaling. All materialpararneters, such as the metal resistivity Pw and dielectric constant E:il'lS' are assumed to remain the same. The wire capacitance then scales down by Ie, the same as the device capacitance (Table 4.1), while the wire capacitance per If one takes Gin.,'''' Gox and b/a '" 2, then Cw ::;' 21l:Gox::;' 2 pF/cm. Ifan alternative insulator with a lower dielectric constant than that of oxide is used, Cw will decrease proportionally. uni~ length, C"" remains unchanged (approximately 2 pF/cm for silicon dioxide insula­ tion, as mentioned above). The wire resistance, on the other hand, scales up by 1(, in contrast to the device resistance, which does not change with scaling (Table 4.1). The Interconnect Scaling wire resistance per unit length, R"" then scales up by K2, as indicated in Table 5.1. It is Based on the above discussions, one can easily set a strategy for interconnect. scaling also noted that the current density of interconnects increases with K, which implies that 286 5 CMOS Performance Factors Table 5.1 Scaling of Local Interconnect Parameters Scaling assumptions Derived wire scaling behavior Interconnect Parameters Interconnect dimensions (t"" L"" W,." tillS' W.p ) Resistivity of conductor (p,.,) Insulator pel1l1ittivity (8ins) Wire capacitance per unit length (Cw) Wire resistance per unit length (Rw) Wire RC delay (rw) Wire current density (IIW,.,tw) Scaling Factor (,,~ 1) 1/" I 1 1 x? " Ground plane oJ L~.~ ~ Agure 5.26. Scaling of interconnect lines and insulator thicknesses. (After Dennard, 1986.) reliability issues such as electromigration may become more serious as. the wire dimension is scaled down. In reality, a few material and process advances in metallurgy have taken place over the generations to keep electromigration under control in VLSI technologies. 5.2.4.3 Interconnect Resistance The interconnect RC delay can be examined using the same distributed RC network model introduced in Section 5.2.3. From Fig. 5.22 or Eq. (5.28), the voltage at the receiving end of an interconnect line rises to Ie-I::::; 63% of the source voltage after a delay of t=RCW2/2. If one takes this value as the equivalent RC delay ('w) of an interconnect line and substitutes R.." Cm Lw for R, C, Iv, one obtains 5.2 Parasitic Elements 287 ' w -1 .2.R W C W L2w ' (5.31) Using Rw=pwlWwtw and Eq. (5.30) for Cw with In(bla) ::::; I, one can express Eq. (5.31) as 'Ill L2 ~ 11:SinsPw W:tw' (5.32) where Wwand tw are the wire width and thickness, respectively. One of the key conclu­ 'w sions of interconnect scaling is that the wire RC delay does not change as the device dimension and intrinsic delay are scaled down. Eventually, this will impose a limit on VLSI performance. Fortunately, for conventional aluminum metallurgy with silicon dioxide insulation, Pw ~ 3 x 10-6 O-cm and '''' ~ (3 x _L2_'" . W",t", (5.33) It is easy to see that the RC delay of local wires is negligible as long as L!/ Wwtlll < 3 X 105• For example, a 0.25 11m x 0.25 11m wire 100 11m long has an RC delay of 0.5 ps, which is quite negligible even when compared with the intrinsic delay (::::; 20ps) of a O.l-J.lm CMOS inverter (TaUT et ai., 1993c). Therefore, a local circuit macro can be scaled down with aU W... I ... and Lw reduced by the same factor without running into serious RCproblems. 5.2.4.4 RC Delay of Global Interconnects Based on the above discussion, the RC delay oflocal wires will not limit the circuit speed even though it cannot be reduced through scaling. The RC delay of global wires, on the other hand, is an entirely different matter. Unlike local wires, the length of global wires, on the order of the chip dimension, does not scale down, since the chip size actually increases slightly for advanced technologies with better yield and defect density to accommodate a much larger number of circuit counts. Even if we assume the chip size does not change, the RC delay of global wires scales up by ,(l from Eq. (5.33). It is clear that one quickly runs into trouble if the cross-sectional area of global wires is scaled down the same way as the local wires. For example, in a 0.25-fJm CMOS technology, L;,/Wwtw"" 108_109 and 'w"" 1ns, severely degrading the system performance. The use of copper wires instead of aluminum would reduce the numerical factor in Eq. (5.33) by a factor of about 1.5 and provide some relief. A number of solutions have been proposed to deal with the problem. The most obvious one is to minimize the number of cross-chip global interconnects in the critical paths through custom layout/design and use of sophisticated design tools. One can also use repeaters to reduce the dependence of RC delay on wire length from a quadratic one to a linear one (Bakoglu, 1990). A more fundamental solution is to increase or not to scale the cross-sectional area of global wires. However, just increasing the width and thickness of global wires is not enough, since the wire 288 5 CMOS Performance Factors I •••••••••• •••••••••••••••••••• Figure 5.27. Schematic cross section of a wiring hierarchy that addresses both the density and the global RC delay in a high-perfonnance CMOS processor. (After Sai-Halasz, 1995.) capacitance will then increase significantly, which degrades both perfonnance and power. The intennetal dielectric thickness must be increased in proportion to keep the wire capacitance per unit length constant Of course, there is a technology price to pay in building such low-RC global wires. It also means more levels of interconnects, since one still needs several levels of thin, dense local wires to make the chip wirable. The best strategy for interconnect scaling is then to scali! down the size and spacing oflower levels in step with device scalingfor local wiring, and to use unsealed or even scaled-up levels on top for global wiring, as shown schematically in Fig. 5.27 (Sai­ Halasz, 1995). Unscaled wires allow the global RC delay to remain essentially unchanged, as seen from Eq. (5.33). Scaled-up (together with the insulator thickness) wires allow the global RC delay to scale down together with the device delay. This is even more necessary ifthe chip size increases with every generation. Ultimately, the scaled-up global wires will approach the transmission-line limit when the inductive effect becomes more important than the resistive effect. This happens when the signal rise time is shorter than the time offlight over the length of the line. Signal propagation is then limited by the speed of electromagnetic waves, cI(e;n/eo)1I2, instead of by RC delay. Here c= 3 x 10 10 cmls is the velocity of light in vacuum. For oxide insulators, (e;n/eo)1f2:::: 2, the time of flight is approximately 70pslcm. Figure 5.28 shows the interconnect delay versus wire length Lw calculated from Eq. (5.33) for three different wire cross sections. Note that the RC delays vary quadratically with Lw- Below a certain wire length, the delay is limited by the time of flight which varies linearly with Lw. For a longer global wire to reach the speed-of-light limit, a larger wire cross section is needed. The transmission-line situation is more often encountered in packaging wires (Bakoglu, 1990). 5.3 SenSitivity of CMOS Delay to Device Parameters 289 1E-8 'UI' IE- 9 '-' ~ ~. IE-IO i8 lE.-ll ~ - IE-12 Wire size: .-..... 0.1 J.lIll _. - -0.3 J.lIll / / / ,/ / / / / / - - 1.0 J.lIll / / ? / / / / / / / / / Limited by speed of / electromagnetic-wave / / IE-13 I 4 "01'" 0.001 om ......' 0.1 ,,,, .. ' , .... ,I 10 Wire length (em) Rgure 5.28. RC delay versus wire length for three different wire sizes (assuming square wire cross sections). Wires become limited by electromagnetic-wave propagation when the RC delay equals the time of flight, (smslso)lf2L.,..lc, over the line length Lw- An oxide insulator is assumed here. 5.3 Sensitivity of CMOS Delay to Device Parameters This section focuses on the perfonnance fuctors ofbasic CMOS circuit elements and their sensitivities to both the intrinsic device parameters and the parasitic resistances and capacitances. Using 1.5 V, 0.1 J.l.m CMOS devices as an example, we first define the propagation delay of an inverter chain and discuss the loading effect due to fan-out and wiring capacitances. Three performance factors - the switching resistance Rsw> input capacitance Cin, and output capacitance Cout - are introduced in terms of a delay equation, followed by several subsections detailing their sensitivity to various device parameters. The last subsection deals with the performance factors of two-way NAND circuits. 5.3.1 Propagation Delay and Delay Equation In this subsection, we define the propagation delay and the delay equation of a static CMOS gate. While CMOS inverters are used as an example to build the basic framework, most of the fonnulation and performance factors are equally applicable to other NAND and NOR circuits that perfonn more general logic functions. 5.3.1.1 Propagation Delay of a CMOS Inverter Chain The basic switching characteristics ofa CMOS inverter with a step input waveform have been briefly touched upon in Section 5.1.1. In a practical logic circuit, a CMOS inverter is driven by the output from a previous stage whose wavefonn has a finite rise or fall time associated with it. One way to characterize the switching delay or the performance of an inverter is to construct a cascaded chain of identical inverters as shown in Fig. 5.29, and consider the propagation delay of a logic signal going through them. Load capacitors 290 5 CMOS Performance Factors ~ ~ Vl'l - - ~~ ~rlLYIlYCL-IILY~ -llC~L- - Vl'l Rgure5.29. A linear chain of CMOS inverters (fan-out = 1). Each triangular symbol represents a CMOS inverter consisting of an nMOSFET and a pMOSFET as shown in Fig. 5.2. Power-supply connections are not shown. can be added to the output node ofeach inverter to simulate the wiring capacitance it may drive in addition to the next inverter. For a given CMOS technology, the propagation delay is experimentally determined by constructing a ring oscillator with a large, odd number of CMOS inverters connected head to tail and measuring the oscillating frequency of the signal at any given point in the ring when the power-supply voltage is applied. The sustained oscillation is a result of v propagation ofalternating logic states (0 ...... dd ...... 0 ..........) around a ring with an odd number of stages. The period of the oscillation is given by n(1n + 'p), where n is the number of stages (an odd number) and 1n. 1p are inverter delays per stage for rising and falling inputs, respectively. In other words, in one period the logic signal propagates around the ring twice. Because ofthe complexity of the current expressions for short-channel MOSFETs and the voltage dependence of both intrinsic and extrinsic capacitances, a circuit model such as BSIM in SPICE is needed to solve the propagation delay numerically (Cai et at., 2000). In order to gain insight into how the voltage and current waveforms look during a switching event, we consider the example of a 0.1 tun CMOS inverter with the device parameters listed in Table 5.2 (http://www.eas.asu.edul-ptm/). All lithography dimen­ sions and contact borders, e.g., a, b, and c in Fig. 5.13, are assumed to be 0.15 tun (nonfolded). The power-supply voltage is 1.5 V (Taur et at., 1993c). The propagation delay is evaluated by introducing a step voltage signal at the input of the linear inverter chain in Fig. 5.29. After a few stages, the signal waveform has become a standardized signal, i.e., one that has stabilized and remains a constant shape indepen­ dent of the number of stages of propagation. There are also a few stages following the ones of interest for .maintaining the same capacitive loading of each stage. For any stage with input voltage Vi,. and output voltage Vaut (see Fig. 5.2), Cd~;.1t = Ip(Vin,vou,) IN(Vin,vout), (5.34) where C lumps all the capacitances connected to the output node. (Capacitance compo­ nents to a node with time-varying voltage are discussed in Section 5.3.4.3.) If Vi,.(t) is known, then Va.,(t) can be solved from the above differential equation. Numerically, given V;n and V,,"t at any time instant t, Ip and IN can be evaluated, and the next VOId is given by Vout(t + 6.t) . (5.35) A VollAt) curve canbe generated by repeating these steps. , , 5.3 Sensitivity of CMOS Delay to Device Parameters 291 Table 5.2 0.1 !llTl CMOS parameters for circuit modeling (25°C) Assumed Computed Power supply voltage, Vaa (V) Channel length, L (11I11) Lithography ground rules, a,b,c (11I11) Gate oxide thickness, tax (nro) Linearly extrapolated threshold voltage, Van (V) Source and drain series resistance, Rsa (Q-I1I11) Saturation velocity, VSal (cm/s) Substrate/well doping concentration, No, Na (cm·-3) Gate to source or drain (per edge) overlap capacitance, COl' (fF/l1I11) Drain induced barrier lowering, L\ V, between Vdr = 0 and Vdr = Vaa,(V) Body-effect coefficient, m Device width, Wn, Wp (11I11) Intrinsic channel capacitance per unit width, which is inversely proportional to the large-signal transconductance Io'/vdd appropriate for digital circuits (Solomon, 1982). The switching resistance can be decom­ 'n posed into Rswn and Rswp in terms ofthe pull-down and pull-up delays and rp defined in Fig. 5.30, i.e., Rswn drn/dCL and Rswp == drp/dCL . Since r = (rn + rp)/2, it follows that Rsw (Rswn + Rswp)/2. From Eqs. (5.36) and (5.37), Vdd / 2 Rswll (IN) (5041) and Vdd/ 2 Rswp = (Ip) , (5.42) where (IN) and (Ip) are about 3/5 of the on-currents at Vgs Vds ± Vdt}, as stated before. The switching resistances extracted from the above specific example are listed in Table 5.3. For the CMOS inverters, WJWn was chosen to be 2 to compensate for the difference between Ion,n and Ion,p, so that Rswn;::: Rswp;::: Rsw and 'I'n;::: 'I'p;::: r. Both the input and the output capacitances, C in and Caul> in Eq. (5.39) are approxi­ mately proportional to Wn + Wp , since both nMOSFET and pMOSFET contribute more or less equally per unit width to the node capacitance whether they are being turned on or being turned off. This assumes that all the capacitances per unit width are symme­ trical between the n- and p-devices, as is the case in Table 5.2. The specific numbers for the case in Fig. 5.32 are listed in Table 5.3. Note that (Cin + Cout) /( Wn + Wp ) is about three times the intrinsic channel capacitance per unit width, 0.96 fF/flm, listed in Table 5.2. 5.3.1.4 CMOS Delay Scaling It is instructive to reexamine, from the delay-equation point of view, how CMOS perfor­ mance improves under the rules of constant-field scaling outlined in Section 4.1.1. Let us assume that the first five parameters in Table 5.2 are scaled down by a factor of two, i.e., Vdd= 0.75 Y, L = 0.05 flm, tox =1.8 nm, ± 0.2 Y, and a, b, c= 0.075 flm (litho- ~ graphy ground rules). Ifthe source and drain series resistances in the scaled CMOS are also reduced by a factor of two, i.e., Rsdn= 100 O-flm and Rsdp= 250 O-flm, the on currents per unit device width will remain essentially unchanged, i.e., Ion,1I 0.56 mA/flffi and Ion,p 0.25 mA/~m (both the mobility and the saturation velocity are the same as 296 5 CMOS Perfonnance Factors before). Since Vdd is reduced by a factor of two, both n- and p-switching resistances normalized to unit device width, W"Rswn and WpRswp, improve by a factor of two. At the same time, all the capacitances per unit width should be kept the same. These include the gate capacitance f.oxL/ tox, the overlap capacitance (0.3 fF/~m), and the junction capacitance. Note that the junction capacitance per unit area, 0, may go up by a factor of two due to the higher doping needed to control the short-channel effect, but the junction capacitance per unit device width is proportional to (a + b + c)0 and therefore remains unchanged. Combining all the above factors, one obtains that both C;,/(Wn + Wp) and CouJ(Wn + Wp) are unchanged and the intrinsic delay given by Eq. (5.40) improves by a factor of two to II ps. In practice, one cannot follow the above ideal scaling for various reasons. The most important one is that the threshold voltage cannot be reduced without a substantial increase in the off current, as discussed extensively in Section 4.2. A more detailed tradeoffamong CMOS performance, active power, and standby power will be considered in Section 5.3.3. 5.3.2 Delay Sensitivity to Channel Width. length, and Gate Oxide Thickness The next few subsections examine CMOS delay sensitivity to various device parameters, both intrinsic and parasitic, as listed in Table 5.2. To begin with, this subsection discusses the effect ofdevice width, channel length, and gate oxide thickness on CMOS performance. 5.3.2.1 CMOS Delay Sensitivity to pMOSFET/nMOSFET Width Ratio When the p- to n-device width ratio W;Wn is varied in a CMOS inverter, the relative current drive capabilities Rswn and Rswp' and therefore Tn and "Cp , also vary. Figure 5.33 plots the intrinsic delay (FO = I, CL= 0) of CMOS inverters as a function of the device 50 40 B. ';::: 30 ""il "0 ,~ "'E" 20 ..s IO[ ~ Table 5.2 value 01L-_ _L -_ _~_ _~_ _- L_ _- L_ _~_ _~ o 0.5 1.5 2 2.5 3 3.5 Device width ratio. Wpl W. Figure 5.33. Intrinsic CMOS inverter delays fn. 'p, and ,for FO = I and CL = 0 versus p- to n-device width ratio. 5.3 Sensitivity of CMOS Delay to Device Parameters 297 5.3.2.2 width ratio. The rest of the device parameters are the same as in Table 5.2. As W;Wn increases, ip decreases but in increases. At W;Wn '" 2, the pull-up time becomes equal to the pull-down time, which gives the best noise margin, as discussed ·in Section 5.1.1. The overall delay, i (in + i p)/2, on the other hand, is rather insensitive to the width ratio, showing a shallow minimum at W p/ Wn ~ 1.5. The specific example in the last subsec­ tion used Wp/Wn 2, so that in ~ fp ~ , = 22 ps, which is within 5% of the minimum delay at W;Wn:= 1.5. It should be noted that only the intrinsic or unloaded delay exhibits a minimum at WplW.= 1.5. The minimum delay for wire-loaded circuits tends to occur at a larger W;W. Fatio. Device Width Effect with Respect to Load Capacitance w., From the discussions in Section 5.3.1, it is clear that if and Wp are scaled up by the same factor without changing the ratio W;Wno the intrinsic delay remains the same. The switching resistance, R"w= dr/dCL, however, is reduced by that same factor. So for a given capacitive load CL, the delay improves. In fact, it has been argued that for high­ perfonnance purposes, one can scale up the device size until the circuit delays are mostly device-limited, i.e., approaching intrinsic delays (Sai-Halasz, 1995). This can be accom­ plished, if necessary, by increasing the chip size, because the capacitance due to wire loading increases only as the linear dimension of the chip (2 pF/cm in Section 5.2.4), while the effective device width can increase as the area ofthe chip if one uses corrugated (folded) gate structures. Of course, delays of global interconnects, as well as chip power and cost, will go up as a result. In practical CMOS circuits, one tries to avoid the situation where a device drives a capacitive load much greater than its own capacitance, as that results in delays much longer than the intrinsic delay. One solution is to insert a buffer, or driver, between the original sending stage and the load. A driver consists of one or multiple stages ofCMOS inverters with progressively wider widths. To illustrate how it works, we consider an inverter with a switching resistance RSK' an input capacitance Cim and an output capaci­ tance COUI> driving a load capacitance Without any buffer, the single-stage delay is i = RSII'(Cou, + Cd· (5.43) IfCL » Cin and C QUb the delay may be improved by inserting an inverter with k (> I) times wider widths than the original inverter. Such a buffer stllge would present an equivalent FO = k to the sending stage but would have a much improved switching resistance, RnJk. The overall delay including the delay of the buffer stage would bel "Ch R.m·(CaUl + k'ell) + RSII' (kCOUf + CL ) Rs>I' (2COUI + kCill + ~L). (5.44) It is easy to see that the best choice of the buffer width is k = (CdCin)II2, which yields a minimum delay of I Here we apply Eq. (5.39) as an approximation. Strictly speaking, it is not propagation delay without a few repeated stages of identical driving-receiving conditions. 298 5 CMOS Performance Factors 5.3 Sensitivity of CMOS Delay to Device Parameters 299 40 ~30 :s.. ~ . ~'" .$,! '5" ..".. 20 z1 15 \ 0.07 I 0.\ Channellenglb (j.llI1) 0.\5 I Figure 5.34. Intrinsic CMOS inverter delay versus channel length for the devices listed in Table 5.2. Both n- and pMOSFETs are assumed to have the same channel length. L). Tbmin = Rsw (2Cout + 2y'C;nC (5.45) For heavy loads (CL » Cin, Cout), tbmin can be substantially shorter than the unbuffered delay r. To drive even heavier loads, multiple-stage buffers can be designed for best results (see Exercis~s 5.8, 5.9, 5.10). 5.3.2.3 Sensitivity of Delay to Channel Length Channel length offers the biggest lever for CMOS performance improvement. At shorter channel lengths, not only does the switching resistance of the driving stage decrease due to higher on-currents, the intrinsic capacitance in the receiving stage is also lower. Figure 5.34 shows the variation of inverter delay with channel length assuming the rest ofthe device parameters are given by Table 5.2 (with no threshold voltage dependence on channel length). It is observed that the inverter delay improves approximately linearly with channel length at and above the O.l-~m design point, but sub-linearly below it. 5.3.2.4 Sensitivity of Delay to Gate Oxide Thickness Switching resistance or current drive capability can also be improved by using a thinner gate oxide. In contrast, however, to shortening the channel length, which helps both the resistance and the capacitance, a thinner oxide leads to a higher gate capacitance. It is shown in Fig. 5.35 that the improvement of intrinsic delay with oxide thickness is not as much as with channel length. Loaded delays improve more as indicated by the switching resistance curve in Fig. 5.35. The Rsw dependence on tox is still sub-linear because mobility decreases in thinner-oxide devices due to the higher vertical field. It should be pointed out that the above sensitivity study only considers tox variations at the level of the circuit model, while keeping all other parameters unchanged. In other words, the interdependence between tox and Vt or L at the process or device level is not 0.1 11m CMOS 401­ ,';;e;' ~ 30 'ii '0 ~ OJ .i:>; 20 / ~ • -13.000 E ~ 2.000 f""J 1;; .~ 1.500 ~""" .~ U) 15 I 2 3 4 5I 1•000 Gate oxide thickness (11m) Figure 5.35. Intrinsic delay and switching resistance versus gate oxide thickness for the O.l-Ilffi CMOS listed in Table 5.2. Both log scales are of the same proportion for comparison. taken into account. From a device-design point of view, thinner oxides would allow shorter channel lengths and therefore additional performance benefit. 5.3.3 Sensitivity of Delay to Power-Supply Voltage and Threshold Voltage This subsection addresses the dependence of CMOS delay on power-supply voltage and threshold voltage. The effect is mainly through the switching resistance factor as the large-signal transconductance, lon/Vdd, degrades with higher V, or lower Vdd. Both the input and output capacitances are relatively insensitive to Vdd and VI' The effect of threshold voltage on the delay ofO.I-~ CMOS for a given Vdd= L5V was discussed in Subsection 4.2.1.3 and shown in Fig. 4.2. In that case, the delay for V/Vdd < 0.5 can be fitted to an empirical factor, 11(0.6 - V/Vdd). The dependence of inverter delay on power supply voltage for a fixed threshold voltage (Table 5.2) is shown in Fig. 5.36. The delay increases more rapidly than 1/(0.6 - V/Vdd) as the supply voltage is reduced, indicating that while the factor 11(0.6 V/Vdd) captures the VI-dependence of the delay, there is additional Vdadependence. The delays of2-way NAND gates exhibit a very similar Vda dependence as the inverter delay. More discussions on 2-way NAND delays can be found in Subsection 5.3.5. 5.3.3.1 Power and Delay Tradeoff The delay versus supply voltage curve in Fig. 5.36 can be re-plotted as a power versus delay curve with Vdd as a parameter in Fig. 5;37. Here the active power is calculated from Pac (Cin + CoUl )Vdi/(2r), (5.46) under the assumption that the inverters are clocked at the highest frequency possible, f"" 1/(2r), where 2r is the time it takes to complete a high-to-Iow-to-high switching cycle 300 5 CMOS Performance Factors 5.3 Sensitivity of CMOS Delay to Device Parameters 301 JOO ~ 70 O.I~mCMOS ~ 50 >. oj 45 "0 .~ 30 .'.."5s 20 I Standard voltage I ! 0.5 1.5 2 2.5 Power supply voltage (V) Agure 5.36. CMOS intrinsic delay versus power supply voltage for a constant threshold voltage (Table 5.2). 2 f\ ~ 2.0 V O.l/.1mCMOS 0.5 ~ [~ 0.2 ~.>, 0.1 .;:: 0.05 ~ t.1.5V pa::j4 0.02 W.=l/.1lJl Wp=2/.11Jl 1.0 V ~ pa::j2 0.01 L'-----'----'--~-'--~-'-~ 10 20 30 50 70 100 Delay (ps) Figure 5.37. CMOS power versus delay by varying the power supply voltage for a constant threshold voltage (Table 5.2). (Fig. 5.30). Equation. (5.46) accounts for about 90% of the power drained from the power supply source (rail to rail current times Vdd)' The rest is the cross-over or short-circuit power. For the devices in Table 5.2, the standby power due to subthreshold leakage at room temperature is about I nW, negligible during the active switching transient. In Fig. 5.37, lower power-delay product or switching energy is obtained at low supply voltages where P (X f2. For high-performance CMOS operated toward the high end of the supply voltage, premium performance comes at a steep expense of active power (P (Xf4). It is possible to reduce Vdd without a severe loss in performance if VI is reduced as well. Of course, standby power will go up as a result. The tradeoff among performance, active power, and standby power is depicted conceptually in a VdaV, design plane in Fig. 4.8. While the standby portion of the total power stays constant with time, the active portion of the total power depends on the circuit activity factor, i.e., how often the circuit switches on average. For high-activity circuits such as clock drivers, active power dominates. In principle, their power can be reduced by operating at low Vdd and low V, while maintaining a similar performance (Cai et aI., 2002b). The majority ofcircuits in a typical VLSI logic chip, however, are of the low-activity type, such as those found in static memories. High- V, devices are needed in those circuits to limit their collective standby power. High Vdd may also be needed for performance. In practice, circuits of different logic swings are rarely mixed in the same chip (except for input from and output to other systems ofdifferent voltage level) due to delay and area penalties associated with level translation at their interfaces. 5.3.4 5.3.4.1 Sensitivity of Delay to Parasitic Resistance and capacitance This subsection examines the sensitivity ofCMOS delay to parasitic source-drain series resistance, overlap capacitance, and junction capacitance, using the O.l-~m devices listed in Table 5.2 as an example. Sensitivity of Delay to Series Resis1ance The effect of source-drain series resistance on CMOS delay comes through n- and pMOSFET currents and therefore their switching resistances. Figure 538 shows the sensitivity of n- and p-switching resistances to the n- and p-series resistances Rsdn and R,dp' Since pMOSFETs have a lower current per unit width, they can tolerate a higher series resistance for the same percentage of degradation. For the default values assumed 6,000 ~ 5~[ g., 4,000 cu .!\~! 3,000 ~" WpR,",p 12'OOOr~ " .~ WnR,nl',J but not on Cin• From Fig. 5.41, it is estimated that the junction capacitance accounts for more than 50% of the output capacitance in the straight-gate layout and that the folded layout improves the intrinsic inverter delay (FO 1) by about 15%. 304 5 CMOS Perfonnance Factors Table 5.4 Components of Cin and CO<1I Component Intrinsic gate oxide capacitance Overlap capacitance Junction capacitance (nonfolded) Input Capacitance (%) 49 51 Output Capacitance (%) 18 26 56 2 5 ::L S 1.! s" '0 't"i" 1.5 0 :; 8­ -"0g ~'" .:l Folded layr C"",I(W. + Wp) C1.t(W.+ W;,) 10 0.1 0.2 0.3 0.4 0.5 0.6 Diffusion layout widtn (pm) Figure 5.41. Input and output capacitances versus diffusion width d in Fig. 5.13. In the straight-gate layout (default case thus far), d = a + b + c 0.45).l1l1. In the folded-gate layout (Fig. 5.14), d is effectively cut to half. It is instructive to break Cin and Caul for the O.l-jlm CMOS devices listed in Table 5.2 into various components: intrinsic gate capacitance, overlap capacitance, and junction capacitance. This can be done by extrapolating the simulation results in Figs. 5.39, 5.41, and the capacitance components in Fig. 5.34. The results are given in Table 5.4. Note that the values of Cin and COUI are given in Table 5.3. The unloaded delay is proportional to + Cin Cou" in which only about a third comes from the intrinsic gate oxide capacitance. 5.3.5 Delay of Two-Way NAND and Body Effect So far we have been using CMOS inverters, i.e., with fun-in of 1, for studying the performance factors. Many of the basic characteristics also apply to more general CMOS circuits. There are, however, a few other factors associated with the mUltiple fan-in NAND gates in which two or more nMOSFETs are stacked between the output node and the power-supply ground. This subsection examines these factors using a two-way NAND (Fig. 5.10) as an example. 5.3.5.1 Top and Bottom Switching of a Two-Way NAND Gate The simulation is set up with the layout shown in Fig. 5.15 and with the same O.l-Jlm CMOS devices listed in Table 5.2, except the p- to n-device width ratio. Because the 5.3 Sensitivity of CMOS Delay to Device Parameters 305 Two-way NAND (top switching) L5 0.5 1.5.1 ---==, Two-way NAND (bottom switching) ~ f 105 so 100 ISO 200 Time (ps) (a) so 100 150 200 T;m.(p$) (b) Figure 5.42. Wavefonns of /linl (top gate), /lin2 (bottom gate), Va., (drain of the top nMOSFET and both pMOSFETs), and Vx (node between the two stacked nMOSFETs) for (a) top switching and (b) bottom switching in the pull-down' event ofa 2-way NAND gate. The device parameters are those listed in Table 5.2, except that WnlWp= I.O/1.5}ll1l. pull-down current in a NAND gate is somewhat lower than that in an inverter due to stacking ofnMOSFETs, both the transfer curves and the up and down delays are better matched with a W/Wn ratio of 1.5 instead of 2. In this configuration, the two parallel pMOSFETs are naturally folded. The nMOSFETs are nonfolded. The width of the diffusion region (V,,-node) between the two stacked nMOSFETs is assumed to be the minimum lithography dimension, 0.15 Jlm in this case. To construct a linear chain of two­ way NAND gates, one must distinguish between the two cases: top switching and bottom switching, as was first outlined in Section 5.1.2. Referring to Fig. 5.10, top switching means that transistors N I and P I are driven by a logic transition propagated through input I, Input 2 is tied to Vdd in this case, so that N2 is always on and P2 is always off. On the other hand, in bottom switching transistors N2 and P2 are driven by a logic signal from the output of the previous stage through input 2, while input 1 is tied to Vdd• These two switching modes have somewhat different delay characteristics as discussed below. It is instructive to examine the switching waveforms of various node voltages in a two way NAND. Figure 5.42 plots the input, output, and Vx-node voltages versus time during an nMOSFET pull-down event. In the top-switching case in Fig. 5.42(a), the Vx-node voltage starts at zero, rises momentarily to a peak about 15% of Vdd, then falls back to zero together with J!;,1t/. The rise of liT is a result of the discharging current when the top transistor is turned on. In the bottom-switching case in Fig. 5.42(b), the Vx-node voltage starts at a high value, but quite a bit lower than Vdd• Even though its gate is tied to Vdd, the top transistor is initially biased in the subthreshold region since Vdd V, < V, + (m 1) V., (the factor m comes from the body effect; see the discus­ sion in Section 5.1.2). The exact starting value of Vx depends on a detailed matching of the subthreshold currents in the top and bottom nMOSFETs. When the bottom nMOSFET is turned on, the Vx-node is pulled down to ground, followed by Va"t. One can easily figure out the bias point of each transistor, e.g., in the linear or saturation region, from the values of V;", V" and Vaw Vx at any given instant. 306 5 CMOS Perfonnance Factors 70 r ,- - - - - - - - - - - - - - - - , 60 Two-way NAND: ~ 50 " ..... "" .ig40~ ---------------------- --' & 30 """"...,..,.. ...' ""Iol: 20 ••-.' Inverter Fan·out= 1 10 W.=l.Of,l.m Wp= l.51Jll1 0' , , I ~ o2 4 6 8 10 Load capacitance (if) Figure 5.43. Propagation delay versus load capacitance. The two solid lines are for the top switching and the bottom switching cases of a 2-way NAND gate. The dashed line shows the delay of a CMOS inverter ofthe same device widths for comparison. Figure 5.43 plots the propagation delay of a two-way NAND gate (solid lines), as described above, versus the load capacitance CL . The dashed line shows the delay of an inverter of the same widths for comparison. A delay equation of the same form as Eq. (5.39) also applies to the two-way NAND, but with different values of Rsw> Cln> and CO"" The intrinsic delay (CL = 0) of the two-way NAND is about 34% (1.34 x) longer than that of the inverter, for the following reasons. First, let us consider the capacitances. The input capacitance of a two-way NAND stage is essentially the same as that of an inverter. However, a two-way NAND has a higher output capacitance. In the top­ switching case, there is an additional gate-to-drain overlap capacitance COy (no Miller effect) on the pMOSFETside ofthe two-way NAND layout in Fig. 5.15, compared with the inverter layout in Fig. 5.14(a). In the bottom-switching case, the output capacitance is further increased by additional components on the nMOSFET side. These include the gate capacitance ofNI, some overlap capacitance associated with the gate ofNI, and a small junction capacitance of the V..-node. In addition to the higher capacitances, the switching resistances, i.e., the slopes ofthe lines in Fig. 5.43, of the two-way NAND are also higher than that of the inverter. This primarily sterns from the stacking of the two nMOSFETs between the output node and the ground such that when one nMOSFET is switching, the other acts like a series resistance, which degrades the current. In terms of switching resistances, top switching is worse than bottom switching, since the series resistance in the former case is placed between the source and the g;ound, which results in additional loss ofgate drive. This is evident in Fig. 5.43. Forthe intrinsic delays in this example, bottom switching is worse than top switching because the extra capacitance outweighs the slight difference in the switching resistance. Under heavy loading condi­ tions,.however, top switching is the worst case, in which the switching resistance is about 21 % (1.21 x) worse than that of the inverter in Fig. 5.43. 5.4 Performance Factors of Advanced CMOS Devices 307 The degradation of switching resistance in NAND circuits with fan-in> I can be roughly estimated using the foItowing.simple modeL In the pull-down operation ofa two­ way NAND, the nonswitching nMOSFET has its gate voltage fixed at Vddand acts like a series resistor to the switching transistor. Since it operates mainly in the linear region during a switching event (see the discussion in Section 5.1.2.), its effective resistance can be approximated by Vd"'a!IonN, where Vdsal and IonN are the saturation voltage and current at VgS = Vdd. This increases the nMOSFET switching resistance by roughly the same amount, i.e., t1Rswn Vdso!IonN, based on the discussion following Fig. 5.38. UsingRsw (Rswn + t1Rswn +Rswp)/2 with Rswn andR.m:o for inverters given by Eqs. (5.41) and (5.42), one can write the switching resistance of a two-way NAND gate as Vdd V> Cgd in saturation. For the 0.1-J.U11 nMOSFET example in Table 5.2, gm "" 600 mS/mm and /r"" 80 GHz. The general condition for power gain in a two-port network is discussed in Appendix 13. The unity-power-gain frequency or the maximum oscillation frequency,fmax, can be solved from the condition, Eq. (AB.8). For an intrinsic MOSFET, the power gain condition is always met since Re( Yll ) == 0 for the matrix in Eq. (5.52). It is mathematically tedious to deal with an extrinsic MOSFET with parasitic resistances. The unity-current­ gain and unity-power-gain frequencies,frand/max, of an extrinsic MOSFET are solved in Appendix 14. A simplified expression for /max often found in the literature is Eq. (AI4.l5), /max = fr 817:Rg Cg/ (5.56) where Rg is the parasitic gate resistance. The/rand/max figures ofa modem nMOSFETwith sub-50-nm channel lengths can be in the range of 200 GHz, rivaling those of modem bipolar transistors. However, as an RF amplifier, the voltage gain of a MOSFET is inferior to that of a bipolar transistor due to the transconductance and output characteristics. Using Eq. (5.52) with an open circuit at the output, i.e., it!.< = 0, one can find the voltage gain at low frequencies as IVdSI(w -t 0) gm Vgs gds (5.57) This has the same form as the maximum slope of an inverter transfer curve, IdVout!dVinl, discussed in Section 5.1.1.2. High gm andji-figures are obtained with short-channel devices which also have high gds due to drain-induced-barrier­ lowering effects. In the O.I-J.U11 nMOSFET example in Fig. 5.31(a), gmlgds"" 17, significantly lower than the typical voltage gain of bipolar transistors discussed in Section 8.5.1. 5.4 Performance Factors lof Advanced CMOS Devices 311 5.4.2 Effect of Transport Parameters on CMOS Performance When CMOS devices were scaled to 0.1-J.U11 channel length around the tum of the millennium, technologists began to develop strained silicon MOSFETs that have mobilities higher than those "universal" values discussed in Section 3.1.5. The strain is either process induced, such as by depositing stressful nitride films on a silicon substrate, or produced by epitaxial alloy growth, such as SiGe (Kesanet at., 1991), with a lattice constant mis­ matched to that of silicon. Theoretically, the hole mobility increases in silicon under either tensile or compressive strain due to breaking of the valence band degeneracy and reduction ofthe conductivity mass (Fischetti and Laux, 1996). The electron mobility is also enhanced in silicon under tensile strain because of increased electron populations in the two lower energy valleys with a lower conductivity mass. Reduction of the effective mass may also benefit the source injection velocity in the ballistic model [Eq. (3.99)]. Tensile strain can be created by growing an epitaxial silicon layer on a relaxed SiGe film whose lattice constant is slightly larger than that ofbulk silicon. Alloy scattering in SiGe, however, has a negative effect on both. the electron and the hole mobilities (Fischetti and Laux, 1996). The benefit ofincreased mobilities on CMOS delay can be investigated using the same circuit model as before. The base device case is that of a O.I-J.U11 CMOS with the parameters listed in Table 5.2. The performance gain due to higher mobilities comes in through the switching resistance factor and is therefore independent of fan-out and wire loading conditions. Similar improvement factors are also found in the delay of 2-way NAND circuits. For given carrier densities and fields, MOSFET current is determined by three transport related parameters: mobility, saturation velocity, and series resistance. If both the mobility and the saturation velocity improve by a factor K > I, and if the series resistance decreases by 11K, the current improves by K, or equivalently, the switching resistance decreases by 11K. Empirically, one may write Rs.. ex: Il-efl-aV sat -bRsdC , (5.58) where a + b + c I, for small changes ofll-efl, Vs"" and Rsdwith respect to their Table 5.2 values. Here, changing each parameter means changing both the n- and p-device corre­ sponding parameters by the same factor. Figure 5,47(a) shows t!Je simulated variation of Rsw with the above parameters in a log-log scale. It is observed that a "" 0.61, b '" 0.28, and c '" 0.11 for theO. I -J.U11 CMOS example considered here. Relatively speaking, mobility is the most importlmtparameterfor CMOSperformance. Even at 0.1 pm length, MOSFETs are not as velocity saturated as one might expect. This is mainly because of the universal mobility behavior, i.e., mobility degradation with vertical fields (Section 3.1.5). As MOSFETs are scaled down, the voltage cannot be scaled as much as the device dimension because of subthreshold non-scaling. Lateral fields in the source-drain direction go up as a result. This leads to higher vertical fields as well whi,ch are necessary to keep the 2-D short­ channel effects in check. The net result is the decrease ofmobility as device lengths become shorter, as discussed in Section 4.1.3.2. Therefore, MOSFETs do not necessarily become more velocity saturated as they are scaled down. Figure 5.47(b) further breaks out the sensitivity of switching resistance to electron and hole mobilities separately. Not surprisingly, higher hole mobility is more advantageous 312 5 CMOS Performance Factors g 21 lu[ ~ .j I .e ~ 0.7 !'or (n,p): v_ (n,p): IIR",{n,p): I O.II'tI'lCMOS Ir·5 ~ i t.~ 110 0.7 .~ Ct) 0.5 ,~I_-::-_--:'-:~~......._ ___I._ 0.2 0.3 0.5 2 Ratio to Table 5.2 value (a) !'or (n,p): !'or (P): !'or (n): 0.1 ",mCMOS 0.3 0.5 I 2 Ratio to Table 5.2 value (b) ADore 5.47. Ca) Sensitivity of switching resistance to transport parameters: fJ.eff. Vsab and IIRsa. Each curve depicts relative change ofR,w with respect to relative change ofthe specific transport parameter for both n- and pMOSFETs while others are kept constant (b) Breakdown ofthe mobility dependence into the electron and hole factors separately. 5.4.3. than higher electron mobility because pMOSFETs are not as velocity saturated as nMOSFETs. Quantitatively, the mobility exponent a in Eq. (5.58) can be decomposed into a an + ap such that Rsw ex: fJ.n - a ,. 'fJ.p - O p Vsat - b RsdC , (5.59) where an = 0.24 and ap = 0.37 in this case. Low-Temperature CMOS The performance advantage oflow-temperature operation of MOSFETs has been recog­ nized for some time (Gaensslen et al.. 1977; Sun et al., 1987). The benefit is mainly derived/rom two aspects o/the MOSFETcharacteristics at low temperature: higher carrier mobiUties and steeper subthreshold slope. Field-dependent electron and hole mobilities at 300 and 77 K are shown in Figs 3.15 and 3.16. In this temperature range, the electron mobility improves by a factor of 2-5, depending on the magnitude of the vertical field. This is because of the much reduced electron-phonon scattering at low temperatures. Similarly, hole mobility also improves from 300 to 77 K. although by a more moderate factor of 1.7-4. The improvement factors of both electron and hole mobilities decrease at higher vertical fields where surface roughness scattering, which is largely insensitive to temperature, becomes important. In addition to the mobilities. the saturation velocities of carners in bulk silicon also improve slightly at low temperatures. There are no extensive experimental data on the saturation velocities in a MOSFET channel as a function of temperature and field. In general, it is expected that Vsat improves by some 10--30% from 300 to 77 K (Taur et al., 1993a). Another important aspect of the MOSFET characteristics at low temperatures is that the subthreshold current slope steepens by a factor proportional ~o the absolute temperature 5.4 Performance Factors of Advanced CMOS Devices 313 rl - - -__ 10-4 ~4 -=-~-----::-:=::;;==-~ 1~1 $ 10-81 ....{. i /////1 L=91!m WIL=9.7 V",=O.l v Vbs=OV 10'-10 Experiment 10'-121 ; ( / 1/ ~ Lil -0- Calculated -0.2 0 0.2 0.4 0.6 0.8 1.0 V,,(V) ADore 5.48. Subthreshold I-V characteristics ofnMOSFETs as a function oftemperature. The gate oxide is 200 A thick. (After Gaensslen et aI., 1977). (Section 3.1.3), making it much easier to turn off a MOSFET than at room temperature. An example is shown in Fig. 5.48 (Gaensslen et al., 'I977).,This allows the threshold voltage v" and therefore the power-supply voltage Vdd, to scale down further below their permissible values at room temperature. For example, a subthreshold slope of 25 mY/decade at 80 K (Taur et al., 1993b) would allow a Vt of 0.1-0.2 V and a Vdd of 0.4-D.8 V, provided that the threshold voltage tolerances from short-channel effects can be tightened as well through the use of optimized channel doping profiles (Taur et al., 1997). To estimate the performance gain of CMOS circuits at low temperatures, we consider the example of O.I-J.1m CMOS arId evaluate the intrinsic inverter delay as a function of temperature. At each temperature, the electron and the .hole mobilities are adjusted according to the published data, e.g., in Figs 3.15 and 3.16. A slight temperature dependence of the saturation velocities is also included in the model. Threshold voltages are adjusted following various strategies described below. In Fig. 5.49, the relative performance factor, defined as inversely proportional to the inverter delay, is plotted versus temperature. Since the capacitances to the first order are independent of tempera­ ture, the performance factor mainly reflects the reciprocal of the switching resistance in Eq. (5.39) and should be applicable to various static CMOS circuits with different fan-out and loading conditions. Three different scenarios are considered in Fig. 5.49, depending on the assumption about the threshold voltage. In each case, the performance factor is normalized to the value at 100°C, which is the temperature specified for most of the IC products. In the same-hardware case, the magnitude of threshold voltage increases toward lower tem­ peratures, .governed by the '" -0.8-mVt'C coefficient discussed inSection 3.1.4. The 314 5 CMOS Perfonnance Factors 2.5 .,- - - - - - - - - - - - , B <.> 07 5.5 A similar distributed network to the one in Fig. 5.21 can be used to formulate the transmission-line model of contact resistance in a planar geometry (Berger, 1972). Here we consider the current flow from a thin resistive film (diffusion with a sheet resistivity Psd) into a ground plane (metal) with an interfacial contact resistivity Pc between them (Fig. 5.16). Thus, i~Fig. 5.21, R dxcorresponds to (Psd/ W)dx, and C dx is replaced by a shunt conductance G dx, which corresponds to (W/Pc)dx. Show 316 5 CMOS Performance Factors that both the current and voltage along the current flow direction satisfy the following differential equation: d2j ==RGf= PsdJ, dx2 Pc ) wherej{x) = V(x) or /(x) defined in Fig. 5.21. 5.6 Following the above transmission-line model, with the boundary condition l(x Ie) =0 where x =0 is the leading edge and x = Ie is the far end of the contact window (Fig. 5.16), solve for V(x) and l(x) within a mUltiplying factor and show' that the total contact resistance, Reo = V(x =OY/(x= 0), is given by Eq.(5.11). 5.7 The insertion of a buffer stage (Section 5.3.2) between the inverter and the load is beneficial only ifthe load capacitance is higher than a certain value. Find, in terms of Cin and COUI, the minimum load capacitance CL above which the single-stage buffered delay given by Eq. (5.45) is shorter than the unbuffured delay given by Eq. (5.43). 5.8 Generalize Eq. (5.44) for one-stage buffered delay to n stages: if the width ratios of the successive buffer stages are kl> k2, k3, ... , kn (all >1), show that the n-stage buffered delay is 'ben) == Rsw [(n+ I)Cout + (k1 + k2 + ... + kn)Cin + klk~~. kJ 5.9 Following the previous exercise, show that for a given n, the n-stage buffered delay is a minimum, CL) l/(n+l'] 'Cbmin(n)=Rsw (n+I)Coul + (n+l)Cin ·C ' [ ( in whenkl k2 = ... =kn (CL/Cin}I/(n+1).Here'Cbmin(n),asexpected,isreduced to Eq. (5.45) if n = I. 5.10 Ifone plots the minimum n-stage buffered delay from the previous exercise versus n, it win first decrease and then increase with n. In other words, depending on the ratios of CdC" and CadCm, there is an optimum number of buffer stages for which the overall delay is the shortest. Show that this optimum n is given by the closeSt integer to In(CL/Cin ) I n Ink -, where k is a solution of k(ln k-I) = Caul Cm For typical Cou/Cjn ratios not too different from unity, kis in the range of3-5. Note that k also gives the optimum width ratio between the successive buffer stages, i.e., kl =k2 = ... = kn=k. Also show that the minimum buffered delay is given by 'Cbmin ~ kRswCin In(CL/Cin ), which only increases logarithmically with load capacitance. Exercises 317 5.11 Consider a chain of CMOS inverters with power supply Vdd. The propagation delay between the waveforms can he..expressed by Eq. (5.39) with FO =1. What is the power dissipation while the signal is propagating down the chain? If the device widths are increased or decreased by a factor of k (>lor 'TY'Oh.....l'" .fA... ""'" .... '" .... h ...·..... ";"'t....? <:>""A .,.. ...............rq.... t>; ...f"'... 320 6 Bipolar Devices layer on top of the base region. Adjacent transistors are isolated from one another by p-type pockets, as illustrated in Fig. 6.1 (b), or by oxide-filled trenches. The process for fabricating a typical advanced vertical n-p-n bipolar transistor having an implanted base region is outlined in Appendix 2. Figure 6.1 (c) shows the bias condition for an n-p-n transistor in normal operation. The emitter-base diode is forward biased with a voltage VBE, and the base-collector diode is reverse biased with a voltage VCB' The corresponding energy-band diagram is shown schematically in Fig. 6.1 (d). The forward-biased emitter-base diode causes electrons to flow from the emitter into the base and holes to flow from the base into the emitter. Those electrons not recombined in the base layer arrive at the collector and give rise to a collector current. The holes injected into the emitter recombine either inside the emitter or at the emitter contact. This flow of holes gives rise to a base current. (The operation of a bipolar transistor having both the emitter-base and collector-base diodes forward biased will be discussed in Section 9.1.3 in the context of bipolar inverter circuits and memory cells.) Also illustrated in Fig. 6.1 (d) are the coordinates which we will follow in describing the flow of electrons and holes. Thus, electrons flow in the x-direction, i.e., In(x) is negative, and holes flow in the -x direction, i.e., Jp(x) is also negative. The physical junction of the emitter-base diode is assumed to be located at "x=O". However, to accommodate the finite thickness of the depletion layer of the emitter-base diode, the mathematical origin (x = 0) for the quasineutral emitter region is shifted to the left of the physical junction, as illustrated in Fig. 6.I(d). Similarly, the mathematical origin (x=0) for the quasineutral base region is shifted to the right ofthe physical junction. The emitter contact is located at x=-WE, and the quasineutral base region ends at x= WB. It should be noted that, due to the finite thickness of a junction depletion layer, the widths of the quasineutral p- and n-regions of a diode are always smaller than their corresponding physical widths. Unfortunately, in the literature as well as here, the same symbol is often used to denote both the physical width and the quasineutral width. For example, WB is used to denote the base width. Sometimes WB refers to the physical base width, and sometimes it refers to the quasineutral base width. The important point to remember is that all the carrier-transport equations for p-n diodes and for bipolar transistors refer to the quasineutral widths. In the literature, several different circuit symbols have been used for a bipolar transistor. In this book, we adopt the symbols illustrated in Fig. 6.1 (e). The arrow indicates the direction of positive current flow in the emitter. For instance, in the n-p-n transistor, the emitter current is due primarily to electrons flowing from the emitter region towards the base region. Hence, the direction of positive current flow is from the base towards the emitter terminal. Similarly, in the p-n--p transistor, the emitter current is due primarily to holes flowing from the emitter region towards the base region, thus giving rise to a positive current flow from the emitter terminal towards the base. Figure 6.2(a) illustrates the vertical doping profile of an n-p-n transistor with a diffused, or implanted and then diffused, emitter. The emitter junction depth XjE is typically 0.2 )lm or larger (Ning and Isaac, 1980). The base junction depth is XjB, and the physical base width is equal to XjB - XjE' Figure 6.2(b) illustrates the vertical doping 6.1 Jl-IH1 Transistors 321 f--- xjB ----: ,~ xjE " ------l ': IE+21 : ;;;' JE+20 E ~ c:: IE+!9 0 .~ 1: IE+18 gQ) 0 U lE+17 IE+16! ,!,'!, ,! , o 0.2 0.4 0.6 0.8 Depth ().Lm) (e) XjE -... ...-- JE+2P1o~! l"ysilico.n.!.~ ,:x'B n-type:, :, :::- IE+20 I S (.) 'c-:' 1E+19 .: 1: ..9... ~ 1E+18 n .I; "~ "" ! !1.) " (c.:) 0 U lE+17 Figure 6.2. IE+16 0 0.2 0.4 0.6 0.8 Depth (j.lm) (b) Vertical doping profiles of typical n-p-n transistors: (a) with implanted and/or diffused emitter, and (b) with poJysilicon emitter. 322 6 Bipolar Devices profile ofan n-p-n transistor with a polysilicon emitter. The polysilicon layer is typically about 0.2 llm thick, with an n+ diffusion into the single-crystal region of only about 30 nm (Nakamura and Nishizawa, 1995). That is, XjE is only about 30 nm. The base widths of most modem bipolar transistors are typically O.lllm or less. While one of the goals in bipolar transistor design is to achieve a base width as small as possible, there are tradeoffs in thin-base designs, as well as difficulties in fabricating thin-base devices. Suffice it to say that the base of a polysilicon-emitter transistor can be made much thinner than that of a diffused-emitter transistor. Details of the doping profiles of the base and collector regions are determined by the desired device dc and ac character­ istics and will be discussed in Chapter 7. 6.1.1 Basic Operation of a Bipolar Transistor As illustrated in Fig. 6. I (a), a bipolar transistor physically consists of two p-n diodes connected back to back. The basic operation of a bipolar transistor, therefore, can be described by the operation of two back-lo-back diodes. To tum on an n-p-n transistor, the emitter-base diode is forward biased, resulting in holes being injected from the base into the emitter, and electrons being injected from the emitter into the base. In normal operation, the base--colleclor diode is reverse biased so that there is no forward current flow in the base-collector diode. (In some circuits, e.g., in simple bipolar inverters and bipolar memory cells, a bipolar transistor may operate having both the emitter-base and collector-base diodes forward biased. Operation of such circuits is discussed in Section 9.1.3.) The bias condition and the energy-band diagram of an n-p-n transistor in normal operation are illustrated in Figs 6.l(c) and 6.1 (d). As described earlier, as the electrons injected from the emitter into the base reach the collector, they give rise to a collector current. The holes injected from the base into the emitter give rise to a base current. One basic objective in bipolar transistor design is to achieve a collector current significantly larger than the base current The current gain of a bipolar transistor is defined as the ratio of its collector current to its base current. To first order, the behavior of a bipolar transistor is determined by the characteristics of the forward-biased emitter-base diode, since the collector usually acts only as a sink for the carriers injected from the emitter into the base. The emitter-base diode. behaves like a thin-base diode. Thus, qualitatively, the current-voltage characteristics of a thin­ base diode discussed in Section 2.2.4 can be applied to describe the current-voltage characteristics of a bipolar transistor. 6.1.2 Modifying the Simple Diode Theory for Describing Bipolar Transistors In order to extend the simple diode theory discussed in Section 2.2 to describe the behavior of a bipolar transistor quantitatively, three important effects ignored in it must be included. These are the effects of finite electric field in a quasineutral region, heavy doping, and nonuniform energy bandgap. These effects are discussed below. 6.1 n-p-n Transistors 323 6.1.2.1 Electric Field in a Quasineutral Region with a Uniform Energy 8andgap In Section 2.2.4, the current~voltage 'characteristics of a p-n diode were derived for the case of zero electric field in the p- and n-type quasineutral regions. As will be shown below, the zero-field approximation is valid only where the majority-carrier current is zero and concentration is uniform. For bipolar transistors, as shown in Fig. 6.2(a) and (b), the doping profiles are rather nonuniform. A nonuniform doping profile means that the majority-carrier concentration is also nonuniform. Furthermore, at large emitter-base forward biases, to maintain quasineutrality the high concentration of injected minority carriers can cause significant nonuniformity in the majority-carrier concentration as well. Therefore, the effect of nonuniform majority-carrier concentration in a quasineutral region cannot be ignored in determining the current-voltage characteristics of a bipolar transistor. For a p-type region, Eq. (2.66) gives (p) = CPP !{Ii+kT- In ..!!. , (6.1) q ni where CPP is the hole quasi-Fermi potential and !{Ij is the intrinsic potential. (Note that Pp is equal to Na only for the case of low electron injection, i.e., only at low currents.) The electric field is given by Eq. (2.41), namely q ~_ d!{li kT I dpp dcpp Ii' = - dx Pp dx - dx -kT-I -dpp+ -Jp­ (6.2) q Pp dx qPP/-Lp' where we have used Eq. (2.64), which relates d¢p/dx to Jp. In Eq. (6.2), the intrinsic­ carrier concentration is assumed to be independent of x. The dependence of energy bandgap on x will be discussed later in connection with heavy-doping effects. Let us apply Eq. (6.2) to the intrinsic-base region of an n-p-n transistor with a typical current gain of 100. At a typical but high collector current density of I mA/J.l.m2, om the base current density is mNjlID2, i.e., Jp =0.0 I roNjlID2 in the base layer. As can be seen from Fig. 6.2, the base doping concentration is lyJJ.ically on the order ofl018 cm-3, and the corresponding hole mobility is about 150cm2N-s (Fig. 2.8). That is, Pp "" 1018 cm­ 3 andpp "" 150cm2N-s, and Jplqpppp "" 40 Vlcm, which is a negligibly small electric field in nonnal device operation. Therefore, for a p-type region Eq. (6,2) gives (6.3) Similarly, for an n-type region, ~(n-region) ~ _ kT I dnn (6.4) q nn Equations (6.3) and (6.4) show that the electricjield is negligible in a region o/uniform majority-carrier concentration. 324 6 Bipolar Devices To include the effect of finite electric field, the current-density equations (2.54) and (2.55), which include both the drift and the diffusion ~omponents. should be used. These are repeated here: In(x) = qnlln'if + qDn dn dx' (6.5) and dp lp(x) = qPllp'if ­ qDp dx' (6.6) It should be noted that ifEq. (6.4) is substituted into Eq. (6.5), the RHS ofEq. (6.5) is equal to zero. Similarly, if Eq. (6.3) is substituted into Eq. (6.6), the RHS of Eq. (6.6) is equal to zero. What this means is that the approximations for the electric fields represented by Eqs. (6.3) and (6.4) are good approximations only for describing minority-carrier currents. The dp Idx term, although very small in a p-region, is entirely responsible for the majority-carrier current in a p-region. In fact, from Eq. (2.64), the hole current density in a p-region is lp "" -qpppd¢p Idx. Thus, for describing hole current in a p-region, Eq. (6.2), instead ofEq. (6.3), should be used for the electric field. The electron current in a p-region due to the d¢p Idx term, on the other hand, is negligible. Therefore, Eqs. (6.3) and (6.4) are good approximations for describing minority-carrier currents, i.e., for electron current in a p-region and hole current in an n-region. That is, these approximations are applicable to currents in a diode or in a bipolar transistor. • Built-in electric field in a nonuniformly doped base region. CO::lsider the electron current in the p-type base of a forward-biased emitter-base diode. Let N~) be the doping concentration in the base, and, for simplicity, all the dopants are assumed to be ionized. Quasineutrality requires that pp(x) = NB(X) + np(x). (6.7) Therefore, -ddpxp=d-dNxB+dd-nxp ' (6.8) The built-in electric field ~o is defined as the electric field from the nonuniform base dopant distribution alone, ignoring any effect of injected minority carriers. It can be obtained by substituting NB for Pp in Eq. (6.3), namely == 'f(l1p (6.9) Substituting Eq. (6.3) into Eq. (6.5), and using Eqs. (6.8) and (6.9) and the Einstein relationship, we have, for electron current in a nonuniformly doped p-type base region, lll(x) = qnplln'ifo~ + qDn (2np + NB) dl1p p+NB np+NB dx' (6.1 0) 6.1 n-p-n Transistors 325 Equation (6.10) suggests that the effective electric field 'ife!f in the p-type base can be written as 'ifo~. np+NB (6.11) It should be pointed out that Eqs. (6.1 0) and (6.11) are valid for all levels of electron injection from the emitter, Le., for all values of np­ • Electric field and current denSity in the low-injection limit. At low levels of electron injection from the emitter, i.e., for np « NB, 'ifeffreduces to 'if!) and Eq. (6. 10) reduces to In(X) ~ qnplln'ifo + qDn ~: ' (6.12) which simply says that the electron current flowing in the base consists of a drift component due to the built-in field from the nonuniform base dopant distrIbution, and a diffusion component from the electron concentration gradient in the base. • Electric field and current density in the high-injection limit. When the electron injection level is very high, i.e., when np »NB, 'if""becomes very small. The built­ in electric field is screened out by the large concentration of injected minority carriers. Therefore, the electron current component associated with the built-in field becomes negligible, and the electron current density approaches I In(x) n -N ~ ph" B dnp q2Dn -d-X · (6.13) That is, at the high-injection limit, the minority-carrier current behaves as if it were purely a diffusion current, but with a diffusion coefficient twice its low-injection value. This is known as the Webster effect (Webster, 1954). 6.1.2.2 Heavy-Doping Effect As discussed in Section 2.1.2.3, the effective ionization energy for impurities in a heavily doped semiconductor decreases with its doping concentration, resulting in a decrease in its effective energy bandgap. For a lightly doped silicon region at thermal equilibrium, Eqs. (2.13) and (2.16) give the relationship between the product Polio and the energy gap Eg . As the energy gap changes and/or as the densities of states change due the effect of heavy doping, the pono product will also change. For modeling purposes, it is convenient to define an effective intrinsic-carrier concentration n,e and lump all the heavy-doping effects into a parameter called apparent bandgap narrowing, AEg , given by the equation pQ (6.Eg )no (6.EI() n;. = nfexp(6.Eg/kT). (6. The heavy-doping effect increases the effective intrinsic carrier concentration. To include the heavy-doping effect, n; should be rep/aced by nie' Thus, including heavy-doping effect, the product pn in Eq. (2.67) becomes pn = n;eexp[q(p 11)l . kT }' (6.15) 326 6 Bipolar Devices Figure 6.3. ~ -;; 140 120 ~ _ p'type silicon .~ o I- -- - n-type silicon 100 I- - -_. Unified (p and nJ ~ 80 .gg. 60 1! 40 ;: ~ 20 IV..­ ..­ V ..... .1.:5: o 1-;:::'.-., IE+17 IE+IS. v v v ..' _.' ..... IE+19 Doping concentration (cm-3) IE+20 Apparent bandgap narrowing as given by the empirical expressions in Eqs. (6.16H6.18). where ¢p and ¢. are the hole and electron quasi-Fermi potentials, respectively. It is extremely difficult to determine Mg experimentally and there is considerable scattering in the reported data in the literature (del Alamo et al., 1985a). Careful analyses of the reported data suggest the following empirical expressions for the apparent bandgap-narrowing parameter: , t::.Eg(Nd) 18.71n ( 7 xNd1017 ) meV (6.16) for Nd ? 7 x 10! 7 cm- 3, and zero for lower doping levels, for n-type silicon (del Alamo et al., 1985b), and t::.Eg(Na) 9(F+ ..jF2 + 0.5) meV, (6.17) where F = In(N) 1017), for No > 1017 cm-3, and zero for lower doping levels, for p-type silicon (Slotboom and de Graaff, 1976; Swirhun et al., 1986). More recently, using a new model that treats both the majority-carrier and minority-carrier mobilities in a unified manner (Klaassen, 1990), Klaassen et al. (1992) showed that the heavy-doping effect in both n-type silicon and p-type silicon can be described well by a unified apparent bandgap narrowing parameter. If N represents Nd in n-type silicon and Na in p-type silicon, then the Klaassen unified apparent bandgap narrowing parameter is given by r H M,(N) ~ 69+ (L3 :10") + L3 :10") +O+'V (6.18) Figure 6.3 is a plot of Mg a~ a function of doping concentration, as given by Eqs. (6.16) to (6.18). 6.1.2.3 Electric Field in a Quasineutral Region with a Nonuniform Energy Bandgap Aside from the heavy-doping effect, the energy bandgap can also be modified by incorporating a relatively large amount of germanium into silicon. In this case, the 6.2 Ideal Current-Voltage Characteristics 327 bandgap becomes narrower (people, 1986). If both heavy-doping effect and the effect of germanium are included in.the. parameter Mg in Eq. (6.14), then the product pn given by Eq. (6.15) can be used to describe transport in heavily-doped SiGe alloys. When the energy bandgap is nonuniform, the electric field is no longer simply given by Eqs. (6.3) and (6.4), which include only the effect of nonuniform dopant distribution. When the effect of nonuniform energy bandgap is included, the electric fields are given by (van Overstraeten et al., 1973) q~(;p-regl.O)n for a p-type region, and kTU-d- pp - "I 2dn-Te ) q p dx nie dx (6.19) '¥'( fI' n-regl.O)n = -k-T ( -1 -dn-n " 2 I dn-Te ) q nn dx nje dx (6.20) for an n-type region. Derivation ofEq. (6.19) will be shown in Section 7.2.3 in connec­ tion with the design of the base region of an n-p--n transistor (see Section 7.2.3). 6.2 Ideal Current-Voltage Characteristics In Section 2.2.4, the current-voltage characteristics of a p-n diode were derived assum­ ing implicitly that the externally applied voltage appears totally across the immediate junction. All parasitic resistances, and the associated voltage drops due to current flow, were assumed to be negligible. With these assumptions, the currents or current densities in a forward-biased diode increase exponentially with the applied voltage. These are the ideal current-voltage characteristics. In practice, the measured current-voltage characteristics of a bipolar transistor are ideal only over a certain range of applied voltage. At low voltages, the base current is larger than the ideal base current. At large voltages, both the base and the collector currents are significantly smaller than the corresponding ideal currents. In this section, the ideal current-voltage characteristics are discussed. Deviations from the ideal char­ acteristics are discussed in the next section. It was shown in Section 2.2.5 that, for modem bipolar transistors, the base transit time is much smaUer than the minority-carrier lifetime in the base, and there is negligible recombinadon in the ba.~e region. For an n-p-n transistor, neglecting second-order effects, such as avalanche multiplication and generation currents due to defect~ andlor surface states, the base current is due entirely to the injection ofholes from the base into the emitter. Similarly, the collector current is due entirely to the injection of electrons from the emitter into the base. (The effect ofavalanche multiplication in the base--collector junction is considered in Section 6.5, where breakdown voltages are discussed. Also, that recombi­ nation in the base of modem bipolar transistors is negligible is confirmed in Exercise 6.6). Referring to Fig. 6. I(a), we see that the base terminal contact is located at the. side of the base region. Therefore, the hole current :first flows horizontally from the base tenninal 328 6 Bipolar Devices into the base region and then bends upward and enters the emitter. The horizontal hole current flow causes a lateral voltage drop within the base region, which in tum causes the forward-bias voltage across the immediate emitter-base junction to vary laterally, with the emitter-base forward bias largest nearest the base contact, and smallest furthest away from the base contact This is known as emitter current-crowding effect. When emitter current crowding is significant, the base and collector current densities are not just a function of x [Fig. 6.1 (d)], but also a function of distance from the base contact. Fortunately, as shown in Appendix 16, emitter current crowding is negligible in modern bipolar d£'llices because of their narrow emitter stripe widths. Therefore, we shall ignore emitter current-crowding effect and assume both the base and collector current densities to be uniform over the entire emitter-base junction area. current-Density Equation for Electrons in a p-Type Base Let us consider the electrons injected from the emitter into the p-type base region of an n-p-n transistor. Instead of starting with Eq. (6.10), it is often convenient to reformulate the electron current density in terms of carrier concentrations (Moll and Ross, 1956). To this end, we start with the electron current density given by Eq. (2.63), namely l,,(x) = -qnpp,,, d¢in dx ' (6.21) where ¢in is the electron quasi-Fermi potential. As we shall show later, the hole current density in the p-type base is small, being smaller than the electron current density by a factor ofabout 100 (see Section 6.2.3). Also, as indicated in Fig. 6.2, the base region has a reasonably high doping concentration, typically greater than 10 18 cm- 3 for a modem bipolar transistor. Therefore, the lR drop along the electron-current flow path (which is perpendicular to the intrinsic-base layer) in the p-type base is negligible, which, as discussed in Appendix 4, implies that the hole quasi-Fermi potential ¢ip is approximately constant. That is, we have d¢ip ~ 0 dx . (6.22) in the p-type base region. Combining Eqs. (6.21) and (6.22), we obtain l,,(x) ~ qnp/tn d( VOE, the collector-base diode is reverse biased and the transistor is said to be in its normal forward-active mode of operation. All the electrons injected from the emitter into the base are collected by the collector, as recombination in the intrinsic base is negligible in modem transistors, and there is no electron injection from the collector into the base. The collector current is therefore constant, independent of VCE. The current gain is also constant, and the constant-18 curves are spaced apart by an amount deter­ mined by the base-current step, as illustrated in Fig. 6.4. 6.3 Characteristics of a Typical n-p-n Transistor 337 Note that the schematic in Fig. 6.4 suggests that the collector current is zero when VCE equals zero. This is only a good appn)~imation. Strictly speaking, the collector current in the saturation region has a component due to the injection of holes from the base into the collector. It will be shown later in Section 6.4.1 that in theory the electron current injected from the emitter into the base at VCE "" 0 cancels exactly the electron current injected from the collector into the base. That this cancellation is almost exact in practical transistors will be shown in Section 7:4.8. Thus, we should expect a small but finite collector current at VeE= 0 owing to the injection of holes from the base into the collector. This current is negative because the holes injected from the base are flowing out of the collector. In a linear plot ofIe versus VeE for a typical bipolar transistor, this hole current is usually too small to be noticeable (see Exercise 9.1 in Chapter 9). The measured current-voltage characteristics of typical bipolar devices are not ideal. The degree of deviation from ideal characteristics depends on the device structure, the device design, the device fabrication process, and on the bias condition of the transistor. The behavior of a typical n-p-n transistor is discussed next. 6.3 Characteristics of a Typical n-p-n Transistor Figure 6.5 is the Gummel plot of a typical n-p-n transistor. It plots both the collector current Ie and the base current IB on a logarithmic scale as a function of the forward-bias voltage VBE applied to the emitter and base terminals. The theoretical ideal base and collector currents, discussed in Section 6.2, are indicated by the dashed lines. Figure 6.5 IE-Ir'--------~~------_, IG~,' : 180 IE-2 II I Ie IE-3 fa $ lE-4 "5 IE-5 ~ U lE-6 IE-7 lE-8 AE= 9!-1Jll' Figure 6.5. IE-9[ I !It IJ 0.4 0.6 0.8 I 1.2 1.4 Emitter-base voltage (V) Gummel plot of a typical n-p--n bipolar transistor. The dashed lines represent the theoretical ideal base and collector currents. (After Ning and Tang, 1984.) 338 6 Bipolar Devices c: il~ Figure 6.6. Collector current Schematic illustration of the current gain IdIB as a function of collector current for a typical bipolar transistor, B E c p n F"1IIur8 6.7. Schematic illustrating the parasitic resistances in a typical modem n-p-n transistor. shows that the measured collector current is ideal except at large VSE, while the measured base current is ideal except at small and at large VBE·, Figure 6.6 illustrates the typical measured current gain, leiIs, as a function ofcollector current. For the voltage range where both the base and the collector currents are approximately ideal, the current gain is approximately constant. At low currents, the current gain is less than its ideal value because the base current is larger than its ideal value. At high currents, the current gain rolls off with collector current because the percentage by which the collector current is smaller than its ideal value is larger than the percentage by which the base current is smaller than its ideal value. The dominant physical mechanisms responsible' for the nonideal behavior of the base and collector currents are discussed in the subsections below. 6.3.1 Effect of Emitter and Base Series Resistances Figure 6.7 shows schematically the physical origins of the parasitic resistances in a typical n-p--n transistor. These resistances are ignored in Section 6.2 in the description of 6.3 Characteristics of a Typical n-p-n Transistor 339 the ideal current-voltage characteristics. As the currents flow through these parasitic resistors, voltage drops are developed, which tend to offset the externally applied voltages. The parasitic resistances can therefore be neglected at low currents but can be very important at large currents. In normal forward-active operation, the base-<:ollectorjunction is reverse biased. In most bipolar circuits, particularly those designed for high-speed applications, the collector--base junction is designed to remain reverse biased at all times, even at high currents. This is accomplished by employing a heavily doped subcollector layer (to reduce rd and a heavily doped reach-through (to reduce rc3) to bring the collector contact to the surface. With the base-{;ollector junction reverse biased, to first order, the collector resistance componentB shown in Fig. 6.7 have no effect on the current flows in the emitter--base diode, and only the parasitic resistances associated with the emitter and the base need to be considered. (The effect ofcollector-base voltage on collector current is discussed in the following subsection.) The emitter series resistance r. is determined primarily by the emitter contact resistance, since the resistance associated with the thin n+ emitter region is small. The base resistance rh can be separated into two components: the intrinsic-base resistance rhi, which is determined by the design of the intrinsic-base region, and the extrinsic-base resistance rbx, which includes all other resistances associated with the base terminal. The emitter-base diode voltage drop due to the flow of emitter and base currents is 1J.VSE -fer. + Isrb = Iere + Is(re + (6.59) where we have used the fact that Ie + Is + Ie O. The relation between the voltage VSE applied to the emitter and base terminals and the voltage V~E appearing across the immediate emitter--base junction is V~E = VSE -1J.Vm;· (6.60) To include the effect ofthe emitter and base series resistances, the equations in Section 6.2 for the ideal collector and base currents should be modified by replacing VBE by V~E This results in both the meaSured collector and base currents, when plotted as a function of VBE, being significantly smaller than the ideal currents at liuge VSE, as illustrated in Fig. 6.5. As can be seen- from Eq. (6.33), even in the ideal case, the collector saturation current density is a function ofthe majority-carrier concentration in the base and the base width. Therefore, the measured collector current is afunction oftfVBE as well as afunction. of the base majority-carrier concentration and the base width, which in turn depend on VBE. The dependence of Ie on VBE is very complex, as can be seen in later subsections. On the other hand, as can be seen from Eqs. (6.43) and (6.49), the base saturation current density is a function of the emitter parameters only, which, due to the emitter being very heavily doped, do not vary with the minority-carrier injection level: Therefore, at high currents, deviation of the base current from its ideal behavior is due to .t1VBE alone (Ning and Tang, 1984). The relation between the ideal base current IBo and the measured base current IB is therefore 180 = IBexp(q1J.VsdkT), (6.61) 340 6 Bipolar Devices which can be used to evaluate the emitter and base series resistances. This is shown in Appendix 15. Many other methods for detennining the emitter and base series resistances have been discussed in the literature (Schroder, 1990). Some of these are discussed in Appendix 15 as well. 6.3.2 6.3.2.1 Effect of Base-Collector Voltage on Collector Current In many transistors, particularly in modem high-speed transistors where the base width is very small, the measured collector current, and hence the measured current gain, increases as the base-collector reverse-bias voltage is increased. This is due to two effects, or a combination of them. The first effect is the dependence of the quasineutral base width on collector-base voltage. The second effect is the avalanche multiplication in the base­ collector junction. We shall discuss these two effects individually in this subsection. Modulation of Quasineutral Base Width by Base-Collector Voltage As the reverse bias across the base-collector junction is increased, the base-collector junction depletion-layer width increases, and hence the quasineutral base width WB decreases. This in turn causes the collector current to increase, as can be seen from Eq. (6.31). Thus, instead of as illustrated in Fig. 6.4, where the collector current is independent of collector voltage for VCE > VBE, the collector current of a typical bipolar transistor increases with collector voltage, as illustrated in Fig. 6.8. • Early voltage. For circuit modeling purposes, the collector current in the nonsaturation region is often assumed to depend linearly on the collector voltage. The collector voltage at which the linearly extrapolated lcreaches zero is denoted by -VA' As we shall show later, it is a good and useful approximation to assume that VA is independent of VBE. This is illustrated in Fig. 6.8. VA is called the Early voltage (Early, 1952). It is defined by alc -1 VA + VCE == lC(avCE) (6.62) In practice, except for transistors that tend to punch through (to be discussed later), VA is much larger than the operation range of VCEo Therefore, VA can be approximated by IBI IB2 IB3 IB4 Figure 6.8. o ~-I 'BS VCE Schematic illustrating the approximately linear dependence oflc on VCE. The linearly extrapolated Ic intersects the VcE.-axis at - VA' 6.3 Characteristics of a Typical n-p-n Transistor 341 v.~ ~Ie{(,,{:o)VJ~E)-1 (6.63) The collector current is given by Eq, (6.32), which canbe written as qAEexp(qVBslkT) Ie = AEJcOexp(qVBslkT) = F(WB) , (6.64) where, for convenience, a function F has been introduced (Kroemer, 1985) which is defined by r F(WB) q leo = Jo WD DnB(px)pn(~xe)B(x)dx. (6.65) The majority-carrier hole charge per unit area in the base is r QpB q Jo W• pp(x)dx. (6.66) Since VBE is fixed for a given IB, Eq. (6.63) can be rewritten as VA ~Ic ( -IC of --­ F oVCE ) - 1 _(2 of OWB OQPB)-I - F aWBOQpBOVCE _(2 of aWB aQpB)-1 - F aWBOQpBOVcB (6.67) Notice that VCB = -VBC' As explained in Section 2.2.2.2 in the derivation ofEq. (2.83) for the depletion-layer capacitance for a p-n junction, when the p-side (base) voltage is changed relative to the n-side (collector) by fj, VBC, the p-side depletion charge changes by an amount equal to the change in the majoritychole charge AQpB in the p-side. Therefore, OQpB = OQpB C o~ o~ ~, (6 .68) where CdBC is the base-collector junction depletion-layer capacitance per unit area [cf. Eq. (2.83)]. The other two derivatives in Eq. (6.67) can be evaluated directly, namely. of --= pp(WB) 2 OWB DnB(WB)nieB(WB) and (6.69) OWB _ (OQPB)-I _ __I OQpB - oWB - qpp(WB)' (6,70) l Therefore, Eq. (6.67) gives VA ~ ~ qDnB( WB)n7eB( WB) . W ' pp(X) d ') X. C4BC 0 DnB(x)nieB(x) (6.71) 342 6 Bipolar Devices For a uniformly doped base, Eq. (6.71) reduces to VA ~ QpB CdBC' (6.72) At sufficiently low collector currents such that the base majority-carrier concentration is approximately the same as its equilibrium value, i.e.,pp ~PpO NB, Eq. (6.71) gives VA ~qDnB(WB)n;cB(WB)lWB ~ CdBC 0 NB(X) d DnB( x)ni2eB ( x) X. (6.73) Equation (6.73) is independent ofbase current, so that the slope ofthe curves in Fig. 6.8 intercept the VCE-axis at the same value, namely VA, as illustrated. It is instructive to estimate the magnitude of Eq. (6.73) for a uniformly doped base. In this case, VA ~ qWsNBICdBe. For a base of WB=O.l ~ and NB= IOIScm- 3, we have qWsNB ~ 1.6 x 1O- 6 C/cm2. For a collector of Ne =2 x 1016 cm-3, then, from Fig. 2.16, CdBC ~ 4 x 10- 8 F/cm2• Therefore, VA::; 40 V. In practice, "A can vary a lot as the transistor design is "optimized." This will be discussed further later in this section and in Chapter 7. As can be seen in Eq. (6.71), VA is a function of WB , which, as discussed earlier, is a function of the collector voltage. Therefore, strictly speaking, the Early voltage is a function of the collector voltage at which the slope is used for extrapolating to Ie =0. In other words, strictly speaking, Ie does not increase lineraly with However, the linear dependence is a good approximation and is a useful approximation for circuit analyses and modeling purposes. The Early voltage is a figure of merit for devices used in analog circuits. The larger the Early voltage, the more independent is the collector current on collector voltage. Another device figure ofmerit is the product ofthe current gain and Early voltage. Using Eqs. (6.33), (6.51), and (6.71), this product can be written as (Prinz and Sturm, 1991) (3o VA q2DnB (WB)n7eB(WB) CdBeJBQ (6.74) where the base saturated current density JBO is a function of the emitter parameters. That is, while VA is a function of the base parameters only, the product /lOVA is a function of both the emitter and the base parameters. • Emitter-collector punch-through. As shown in Eq. (6.72), the Early voltage is propor­ tional to the majority-carrier charge in the base. As the collector voltage is increased, the width of the quasineutral base region, and hence the majority-carrier charge in the base, is reduced. For a device with a small majority-carrier base charge or small Early voltage to start with, it does not take much increase in collector voltage before all the majority­ carrier base charge is depleted, or before the collector punches through to the emitter. At collector--emitter punch-through, the collector current becomes excessively large, being limi ted only by the emitter and collector series resistances. The collector current at or close to punch-through is no longer controlled adequately by the base voltage for proper device operation. Punch-through must be avoided under normal device operation, by designing the device to have a sufficiently large majority-carrier base charge. 6.3 CharacteristiCS of a Typical n-p-n Transistor 343 6.3.2.2 Base-Collector Junction Avalanche For a device with a large majority~carrier base charge or large Early voltage to hegin with, as the collector voltage is increased, usually the condition of significant base-collector junction avalanche is reached before punch-through is reached. This is certainly the case for transistors where the collector side of the base-llectorjunction space-charge-layer boundary reaches the subcollector region before punch-through occurs, hecause as the base-collector junction space-cbarge-Iayer boundary reaches the heavily doped subcol­ lector, further increase of the base-collector reverse bias will increase the junction electric field very rapidly. For an n-p-n transistor, the base-collector junction avalanche process is illustrated in Fig. 6.9(a) (Lu and Chen, 1989). As the electrons injected from the emitter into the base reach the base-collector junction space-charge region, they can cause impact ionization and generate electron-hole pairs. The secondary electrons flow towards the collector terminal, adding to the measured collector current, while the secondary holes flow towards the base terminal, subtracting from the measured base current. If the secondary hole current is large enough, the' current measured at the base terminal could be negative (Lu and Chen, 1989). This is illustrated in Fig. 6.9(b). At very small emitter-base forward biases, the measured base current is positive as usual. The secondary hole current is not large enough to completely offset the usual base current. As the electron current injected from the emitter into the base-collector space­ charge region increases with increased emitter-base forward bias, the secondary hole current increases and may reach a point at which the measured base current turns negative. At sufficiently large emitter-base forward biases, as will be discussed in the next subsection, significant base widening can occur and the electric field in the base­ collector junction can be reduced. As a result, avalanche multiplication is reduced and the measured base current returns to positive. The magnitude ofbase-collectorjunction avalanche depends on the maximum electric field in the base-llector junction. To minimize base-collector junction avalanche, techniques for reducing the maximum electric field in a p-n junction, such as retro­ grading the collector doping profile or sandwiching a lightly doped layer between the base and the collector, can be used (Tang and Lu, 1989). The concept is similar to that ofa p-i-n diode discussed in Section 2.2.2. 6.3.3 Collector Current Falloff at High Currents The collector saturation current density for an n-p-n transistor is given by Eq. (6.33), namely l Jeo W • q pp(x) dx o DnB(x)nfeB(x) (6.75) There are a number ofphysical mechanisms that can cause the denominator in Eq. (6.75) to increase, and hence Jeo to decrease, as the collector current density is increased. As Jeo falls otT, the collector current Ie falls off with it [see Eq. (6.32)]. This collector current 344 6 Bipolar Devices B • E ~ n 11 i p II ---,--­ IO! i n 1--1 C e - r ­ : II' -------I Ec ............ \;::: ./ ......... E·--~o ~ Ec -0 E. la) i'" Ie .,_ 18 ~ .0 ." Iii j '8 .so Figure 6.9. Base-ernitter voltage (b) (a) Schematics of an n-p-n transistor operated in the forward-active mode with a large base-collector voltage. As electron-hole pairs are generated in the base-collector junction space-charge region, the secondary hole current, IBn subtracts from the usual forward base current, 18f: The current measured at the base terminal is IB IBf - IB" (b) Typical Gummel plot of an n-p-n transistor where significant avalanche multiplication occurs in the base-collector junction space-charge region. (After Lu and Chen, 1989.) falloff at high currents is on top of the effect of emitter and base series resistances discussed in Section 6.3.1. These physical mechanisms are discussed in this subsection. As electrons are injccted into the p-type base, the hole concentrdtion in the base,pix), increases in order to maintain charge neutrality. If this increase in hole concentration is appreciable, leo decreases. At the same time, as the injected electrons reach the base­ collector junction, they add to the space charge in the base-collector junction space­ charge region, resulting in widening ofthe quasineutraI base layer. An increase in WB also causes leo to decrease. This is known as base-conductivity modulation effect. It should be 6.3 Characteristics of a Typical n-p-n Transistor 345 pointed out that in the Iiterature,pix) in Eq. (6.75) is often approximated by N8(x). This approximation is good only at-small-emitter-base biases where the injected minority electron density in the base is small compared to the base doping concentration. At large emitter-base biases, this approximation underestimates the base-conductivity modula­ tion effect. As We increases, the collector side of the base-collector space-charge layer also widens into the collector. At sufficiently high collector current densities, base widening can push the "base-collector junction" deep into the collector region. This is known as base-Widening or Kirk effect (Kirk, 1962), and it also causes leo to decrease. Base-conductivity modulation and base-widening effects are not really separate and do not act independently. Dependent on the details of the device design, their combined effect can contribute significantly to the observed saturation ofthe collector current in a Gummel plot. A combination of base-conductivity modulation and base widening is responsible for the current-gain rolloff at high collector currents depicted in Fig. 6.6. In this subsection we discuss base widening in more detail. 6.3.3.1 Base Widening at Low Currents Consider the base-collector junction of an n-p-n transistor. For simplicity, let us assume the base region to have a uniform doping concentration NB , and the collector region to have a uniform doping concentration Nc. When the transistor is turned off, the charge distribution in the base-collector junction is as shown schematically in Fig. 6.10(a), where XBO and Xeo are the widths of the depletion regions on the base side and on the collector side, respectively. The relationship between these widths is given by Eq. (2.78), namely, 1:1 B N8 (a) P• . , ( x ) Nc !-W80~ ++-- -++ + + x -XB(J 0 X(1l - -NB + Bound clIarge.<,; (b) p"" (x) • Mobile electrons +. +. i - W B - i -XiJ • 0 •-. • (Nell/l) X Xc - I -(NB+lln) Figure 6.10. Schematics illustrating the charge distribution in the base-collector junction of an n--p-n transistor. (a) Emitter-base diode is not forward biased, and (b) emitter-base diode is forward biased. 346 6 Bipolar Devices XB(JNB = xcoNc· (6.76) The maximum potential drop across the base-collector junction, IfmBC, is given by Eq. (2.79), which can be rewritten as IfmBC = Q 2e... (NB x2BO + Nc~o)· (6.77) When the n-p--n transistor is turned on, electrons are injected into the base and collector regions. These mobile electrons add to the space charge in the base-collector junction region. As long as this additional mobile-electron concentration is small compared with the ionized doping concentrations, the depletion approximation discussed in Section 2.2.2 can be used to estimate its effect. For simplicity, let us assume these mobile electrons traverse the base-collector junction space-charge region at a saturated velocity Vaal' The mobile electron concentration An in the space-charge region is given by the relation JC = qVsatfln , (6.78) where Jc is the collector current density. The space-charge concentration on the base side is increased from Ne to Ne + f:..n, and the space-charge concentration on the collector side is decreased from Ncto Nc - f:..n. As a result, the width ofthe depletion region on the base side is decreased to XB, and the width of the depletion region on the collector side is increased to Xc, such that xB(NB + fln) = xc(Nc - fln). (6.79) This is illustrated schematically in Fig. 6.1 O(b). The width of the quasineutral base layer is widened by an amount equal to Xeo - Xe. An estimation of the amount ofbase widening can be made quantitatively ifthe emitter­ base junction is assumed to be forward biased so that the base-collector junction voltage remains unchanged (Ghandhi, 1968). In this case, Eq. (6.77) is replaced by IfmBC = 2!Si [(NB + fln)x1 + (Nc - fln)~]. (6.80) Combining Eqs. (6.77) and (6.80), and assuming AnINc« 1, we have I + (fln/NB) Xc Xco 1- (fln/Nc) ~ Xco ~ JI - (fln/Nc) (6.81) where we have used the fact that Ne is typically much larger than Nc, so that AnINe « 1. Similarly {I (fln/Nc) XB = XBOY-I + (fln/ NB ) ~ xBOVI - (fln/Nc). (6.82) 6.3 Characteristics of a Typical n-p-n Transistor 347 6.3.3.2 Base Widening at High Currents At high current densities, the assumpt10n of f:..n being small compared to Nc is no longer valid, and the above equations cannot be used to estimate the base-widening effect. With the mobile-charge concentration comparable to or larger than the fixed ionized-impurity concentration, the depletion approximation is certainly not valid. furthermore, the excess electrons in the n-type collector can produce a substantial electric field in the collector, according to Eq. (6.4), and the classical concept of a well-defined junction boundary in the base-collector diode is no longer valid. Also, in order to maintain quasineutrality, the excess electrons induce an excess of holes in the n-type collector. The region of the collector with excess holes becomes an extension of the p-type base. In other words, the base region widens into the collector region, until it reaches the subcollector where the excess electron concentration is small compared with the n-type doping concentration. As a result, the high-field region, originally located at the physical base-<:ollector junction, is relocated to near the collector-subcollector intersection (Poon et al., 1969). The numerical simulation results (poon et al., 1969) shown in Fig. 6.11 illustrate clearly the effects of base widening at high currents. They show that the relocation of the high-field region is accompanied by a buildup of excess electrons and holes in the collector region. It is instructive to estimate the collector current density at which substantial base widening occurs. The saturated velocity Vsat for electrons in silicon is about I x 107 crn/s, as indicated in Fig. 2.10. At low collector currents, the maximum electron concentration in the n-type collector region is equal to the collector doping concentration Nc. The maximum electron current density that can be supported by an electron concentration of Nc is J max = qVsatNc. When the injected electron current density approaches Jrnru<, the electron concentration has to increase to a value larger than Nc in order to support the injected electron current flow, i.e., there is a density of excess electrons caused by the high electron current density. As the excess electrons build up, there is a build up of excess holes in order to maintain quasineutrality, and a relocation ofthe high-field region. The results shown in Fig. 6.11 suggest that significant base widening starts at a collector current density of approximately O.3Jmax• This value is consistent with the reported peak. cutoff-frequency data for modem VLSI bipolar devices (Crabbe et al., 1993a). Thus, to avoid significant base widening, a bipolar transistor should not be operated at collector current densities approaching Jm.... For a relatively high Nc of2 x 10 17 cm- 3 , Jmax is about 3.2 mAlJlm2. To avoid significant base widening, Jc should be less than about 1mA/Jlm2• 6.3.4 Nonideal Base Current at Low Currents As shown in Fig. 6.5, for small emitter-base voltages, the base current is larger than its ideal value. The origins of this excess base current are (a) the generation-recombination current in the emitter-base junction depletion region and (b) the tunneling ctHTent in the emitter-base junction (Li et al., 1988). The amount of deviation from ideal beinrvior depends strongly on the transistor structure, device design, and fabrication process. For 6.3 'Characteristics of a Typical n-p-n Transistor 349 ""' 1:-3­ 10"1­ g .~ 10'" (s) g n+ 8 17 c 10 8til) ='0.. 16 8 10 '_' 101'l 2' 4 ~ ~ 10 1~ 14 I Distance (/lm) -2.8 x 10" : -2.4 x 104 I- I ~ -2.0 x, 10" IL ] I ~ -1.6 x 10" ~ -J" l -1.2 x 10" rII 'S I 11 -8,0 x loJ I- p:j I f -4.0 x loJ (b) 0k 1111 II h *' JII' /\ )I 5.56 x loJ l - _3.329,7x7lOxlOl - . 1.95 X 103 _. 1.38 X 10l _. 9.86x 102 ._ 6.95 x 102 2 - 4.28xlO 2 .9.92 -. 2.09 x 10 x 10 • -. ii' " • •• ... BI Epitaxial layer S 1!,(Alcm2) '.11, Rgure 6.11. o 5 Distance (11m) 10 15 ,"fI' Numerical simulation results showing the effect~ of base widening in an n-p--n transistor at ,~ high collector current densities: Ca) the doping profiles ofthe device simulated, (b) relocation of the.~ high-field region from the physical base-collector junction to the collector-subcollector intersection, (c) buildup of excess holes in the collector, and (d) buildup of excess electrons in the collector. (AfterPoon eta!., 1969.) 11 6 x 10 5 X 1017 ~~ 17~ "';;' 4xl0 .=0 ig 3 x 1017 ~8 2x 1017 :r: 1017 o ~ ~J'=5'56Xl3O.93lxAlloJc m2 f\' 2.77 x 103 / 1.38 x loJ ,6.95 x 1Q2 2 3 4 5 6 7 8 9 10 11 12 13 Distance (~m) Ie) 8 x 10" ­ 7 X 1017 '1 17 6 X 10 ~§ 5 X 1017 .~ t ii 4xlO17 ~ c:: g 3x 1017 11 "-l 2x1017 l~/J,=5.56XIO3 Alcrn2 3.93 X \03 / 2.77 x loJ . / ,L38x loJ 1OJ7 0 1~ 9 I. .9 .. 2. ~ .~ .) .J 1 2 3 4 5 6 7 8 9 10 11 12 13 Distance (~m) [dJ Rgure 6.11. (cont.) 350 6 Bipolar Devices Emitter-base diode depletion region Silicon dioxide B p+ p+ p n C Extrinsic base base Figure 6.12. Schematic illustrating the cross section of an emitter-base diode. The extrinsic base is usually much more heavily doped than the intrinsic. base. The presence of surfu.ce states, indicated by x x x, can cause excessive base current, as discussed in the text. most well-designed bipolar transistors and fabrication processes, this excess current is often negligibly small. In any case, since this excess current is often quite noticeable in experimental devices, particularly before the fabrication process has been optimized, its physical origins are discussed here. Figure 6.12 illustrates schematically the cross section of an emitter-base diode. The base region directly underneath the emitter is referred to as the intrinsic base, and the remaining parts of the base are collectively referred to as the extrinsic base. The entire emitter-base diode can be considered as two diodes connected in parallel, one formed by the emitter and the intrinsic base, and the other by the emitter and the extrinsic base. The intrinsic base has been the subject of our discussion so far. The function of the extrinsic base is to provide electrical connection to the intrinsic base from the silicon surface. To minimize parasitic resistance and to minimize electron injection from the emitter into the extrinsic base region, the extrinsic base is usually doped much more heavily than the intrinsic base. As a result, the collector-current component due to electrons injected from the emitter into the extrinsic base and reaching the collector is negligible compared to the collector-current component due to electrons traversing the intrinsic base. This can be concluded readily from Eq. (6.31). The large width of and high doping concentration in the extrinsic base make its contribution to the collector current very small compared to contribution from the intrinsic base. Nonetheless, the extrinsic-base--emitter diode can contribute appreciably to the mea­ sured base current. This extrinsic-base current has three components, namely (a) the current associated with the injection of holes from the extrinsic base into the emitter, (b) the generation-recombination current, and (c) the tunneling current. The current associated with the injection ofholes from the extrinsic base into the emitter has the same dependence on VBE as the current associated with the injection ofholes from the intrinsic base infu the emitter. Therefore, this current simply adds to the ideal intrinsic-base current 6.3 Characteristics of a Typical n-p-n Transistor 351 and will not show up as deviation of the measured base current from its ideal behavior. Only the gerieration-recoll1biItati()tLand tunneling currents contribute to the nonideal behavior of the measured base' currents. Therefore, only these two components are discussed further here. 6.3.4.1 Base Current Due to Generation-Recombination Generation-recombination current due to defect centers in silicon is negligible in modem VLSI devices because, unless there is a contamination problem, the concentration of defects that can cause generation-recombination current is'negligibly low for all modem VLSI fabrication processes. This may not be true for processes in early development, but it is certainly true by the time a process reaches manufacturing. However, as can be seen from Fig. 6.12, the extrinsic-base--emitter diode has a surface component. The presence of interface states, as indicated in the figure, could give rise to significant surface generation-recombination current, as discussed in Section 2.3.7. The generation­ recombination hole current adds to the base current and hence degrades the current gain (Werner, 1976). Surface generation-recombination current, by itself, usually can be recognized by its exp(VBd2k1) dependence on VBE, as discussed in Section 2.2.4.10. Fortunately, for properly designed fabrication processes, the density of interfuce states can be so low that this current component, though usually observable, is not significant in modem bipolar devices. 6.3.4.2 Base Current due to Tunneling The tunneling current in the emitter-base junction, on the .other hand, is expected to increase as the transistor dimensions are scaled down (Stork and Isaac, 1983). The emitter-base Junction is a fairly abrupt junction. The emitter is very heavily doped, and the base doping concentration is typically in excess of 1 x 1018 cm- 3, as can be seen from Fig. 6.2. Furthermore, as discussed in Chapters 7 and 8, the peak base doping concentra­ tion is increased as the physical dimensions of a bipolar transistor are scaled down, resulting in enhanced tunneling current in the emitter-base diode. Since the extrinsic base is always more heavily doped than the intrinsic base, the observed tunneling current is usually dominated by the component from the extrinsic­ base--emitter diode. Furthermore, the interface states in the extrinsic-base--emitter diode can assist in the tunneling process and thus can enhance the tunneling current very significantly (Li et al., 1988). Figure 6.13 illustrates the typical current-voltage char­ acteristics ofa bipolar transistor which has excessive base current due to tunneling in the emitter-base diode. When excessive emitter-base ~nneling dominates the base current, the base current is usually much larger than suggested by an exp(VsE!2k1) dependence. Furthermore, as expected from a tunneling process, the excessive emitter-base tunneling current is nearly independent of temperature (Li et aI" 1988). Also, the excessive emitter-base tunneling current increases very rapidly with voltage when the emitter­ base diode is reverse biased, as can be seen from Fig. 6.13. Fortunately, excessive tunneling current in the emitter-base diode can be suppressed easily by optimizing the emitter-base diode doping profile and the device fabrication process. 352 6 Bipolar Devices 18-1 lE-3 '<.-..'' IE-5 J:: ~ lE-7 ;::l U I -Ia lE-9 IE-11 -J -0.8-0.6-0.4-0.2 0 0.2 0.4 0.6 0.8 I Emitter-base voltage (V) Rgore 6.13. Typical voltage-current characteristics of an n-p-n transistor which has excessive tunneling current in the extrinsic-base-emitter diode. (After Li et aI., 1988.) 6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses The merits of a bipolar device should be discussed in the context ofthe circuit in which it is used. For circuit applications, the device electrical characteristics must be first trans­ formed into equivalent circuit parameters. The merits of a device are then interpreted from the behavior of the circuit or from the characteristics of the equivalent-circuit parameters. In this section, the equivalent-circuit models needed for the discussion of bipolar device design, which will be covered in Chapter 7, and device optimization, which will be covered in Chapter 8, are developed. The models suitable for dc or large ­ signal analyses will be developed first, followed by the models suitable for small-signal analyses. This is followed by the development of the charge-control model, which is suitable for quasistatic time-dependent analyses. 6.4.1 Basic de Model The Ebers-Moll model (Ebers and Moll, 1954) for an n-p-n transistor is shown in Fig. 6.14. It describes an n-p-n transistor as two diodes in series, arranged in the common-base mode. When a voltage VBE is applied to the emitter-base diode, a forward current IF flows in the emitter-base diode. This current causes a current aFIFto flow in the collector, where aF is the common-base current gain in the forward direction. Similarly, when a voltage Voe is applied across the base--collector diode, a reverse current IR flows in the collector-base diode, causing a current aRIRto flow in the emitter, where aR is the common-base current gain in the reverse direction. These currents are indicated in Fig. 6.14. They are related by IE Cl'.RIR - IF, (6.83) Ic = Cl'.FTF IR, (6.84) 6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses 353 Ci.RIR ClFIp Eo k' ')I oC IE Ie IF lIB 11/ B Figure 6.14. Equivalent-circuit representation of the basic de Eber&-Moll model of an n-p-n transistor. and Ia (1- Cl'.F)h+ (1- Cl'.R)IR· The emitter, base, and collector currents are related by h+ IB +Ic=O. From Eq. (2.120) we can write IF and IR in the form (6.85) h = l;u[exp(qVaE/kT)-1] (6.86) and IR = IRO[exp(qVBc/kT) - 1]. (6.87) Therefore, Eqs. (6.83) and (6.84) can be rewritten as h -IFO[exp(qVBE/kT) 1] + Cl'.RIRO[exp(qVBc/kT) - IJ (6.88) and Ie Cl'.FIFO[exp(qVBE/kT) 1] IRo[exp(qVBc/kT) - 1]. (6.89) Reciprocity characteristics of the emitter and collector terminals require the off-diagonal coefficients of the equations for h and Ie to be equal (Gray et al., 1964; Muller and Kamins, 1977), i.e., Cl'.RIRO = o'FIFO· (6.90) Alternatively, the reciprocity relationship in Eq. (6.90) can be shown as follows. We note that cqIFO is the saturated collector current in the forward active mode, and Cl'.RIRO is the saturated collector current in the reverse active mode. For simplicity, we consider a hypothetical transistor having a unit cross-sectional area for both the emitter-base junction and the collector-base junction. In this case, o'FIFO is given by Eq. (6.33) with the integral in the denominator being from xo=O to x= WB and Cl'.RIRO is also given by Eq. (6.33) but with the integral in the denominator being from x = WBto x= O. Since the value of an integral of a function is independent of its direction of integration, we have Cl'.FIFO '" Cl'.RIRO for our hypothetical transistor having the same emitter-base and collector-base junction areas. It should be noted that no assumption has been made abol,!t 354 6 Bipolar Devices the doping and bandgap-narrowing parameters in the base, suggesting that the reciprocity relationship applies to Si-base as well as SiGe-base transistors. (See Section 7.4 for discussion ofSiGe-bipolar transistors.) Also, it has been shown through experiments and simulation studies (Rieh et at., 2005) that the saturated collector currents in forward and reverse modes are approximately the same in typical bipolar transistors, even though the collector-base junction area in a typical bipolar transistor is much larger than its emitter-base junction area. The common-emitter form of the Ebers-Moll model is often more desirable for circuit analyses. To accomplish this, let us define ISF CY.Fh, ISR CY.RIR, lCT ISF ISR, fh CY.p (6.91) (6.92) (6.93) (6.94) CY.R fJR =: CY.R (6.95) Comparison with Eq. (6.5!5) shows that J3F and fiR are the common-emitter current gains in the forward and the reverse directions, respectively. Substituting Eqs. (6.90) to (6.95) into Eqs. (6.83) to (6.85) gives lsp /e=-ICT- fJp' (6.96) ISR lc = lCT - fJR ' (6.97) + - . ISF ISR To fJF fJR The equivalent-circuit model for these currents is shown in Fig. 6.15. (6.98) -ISJlfJR Bo-------~----~ ")j -Ie DC ler r IE Figure 6.15. E Common-emitter equivalent-circuit representation of the dc Ebers-Moll model of an n-p-·n transistor. 6.4 Bipolar Device Models for Circuit and TIme-Dependent Analyses 355 6.4.2 6.4.2.1 Basic ac Model To model the ac behavior of a bipolar transistor, the parasitic internal capacitances and resistances of the transistor must be included. In general, the Parasitic resistances can be made rather small by using large device areas and device layout techniques, as well as fabrication process techniques. However, the parasitic capacitances usually can be reduced only by reducing the associated device areas. As a result, the basic behavior of a transistor is determined more by its parasitic capacitances than by its parasitic resis­ tances. For simplicity, we shall first neglect the parasitic resistances and consider only the parasitic capacitances. As discussed in Section 2.2.6, there are two components in the capacitance of a p-n diode, namely the depletion-layer capacitance and the diffusion capacitance. Let CdBS•tot andCdBc,tot be the depletion-layer capacitances of the emitter-base and collector-base diodes, respectively. Let CDS be the diffusion capacitance associated with forward­ biasing the emitter-base diode, and CDC be the diffusion capacitance associated with forward-biasing the collector-base diode. When these capacitances are included, the common-emitter equivalent-circuit model is shown in Fig. 6.16. In Fig. 6.16, the depletion-layer capacitance of the collector-substrate diode, CdCS,tot> is also included for completeness. Model for aTransistor Biased in the Forward-Active Mode of Operation For simplicity, we shall consider only transistors biased in the forward-active mode of operation, i.e., with the emitter-base diodes forward biased and the base-collector diodes reverse biased. (Trausistors biased in the reverse-active mode, i.e., with the base­ collector diodes forward biased, cannot be switched fast because of the very large diffusion capacitance associated with the forward-biased base-<:ollector diodes. As a result, high-speed circuits usually use transistors biased only in the forward-active mode.) In this case, ISR can be neglected compared to IsF'> and CDC O. The model in Fig. 6.16 then simplifies to that shown in Fig. 6.17. I fspl/3F -,~ r~ dCS to1 I C• ~. Ie C + ~ 1er '---_1......-,-­ _ _ E Figure 6.16. Common-emirter equivalent-circuit representation of the ac Ebers-Moll model of a bipolar transistor. Internal capacitances are included. 356 6 Bipolar Devices Cacs.tOt "'111 la I CdlIC•IOt (~Q, I _ 1"~L-- C [SF lIE E Figure 6.17. Equivalent-circuit representation of the ac Ebers-Moll model of an n-p-n transistor biased in the forward-active mode of operation. Internal capacitances are included. CdBCx.lot rbx B o--II.Nv~ Ia Cacs,'Q' edsel,rot rc II--J--.-tvVv--o c ISF Ie E Figure 6.18. Equivalent-circuit representation of the ac Ebers-Moll model of an n-p-n transistor biased in the forward-active mode ofoperation. Internal parasitic resistance and capacitance are included. 6.4.3 If the internal parasitic resistances indicated in Fig. 6.7 are now included in the equivalent circuit of Fig. 6.17, the resultant equivalent circuit is shown in Fig. 6.18. Here, for purposes of discussion in later chapters, the base resistance is shown as two parts, an intrinsic part rbi and an extrinsic part rbx' The depletion-layer capacitance of the base-<:ollection diode is also separated into an intrinsic part CdBCi.to, and an extrinsic part CdBCc..tot. Small-Signal Equivalent-Circuit Model Consider a small-signal voltage applied to the input base terminal of a common-emitter equivalent circuit shown in Fig. 6.17 or Fig. 6.18. !twill cause small variations in the base and collector currents as well as in the collector terminal voltage. A small-signal equivalent-circuit model provides a relationship among these current and voltage varia­ tions. We first develop the small-signal equivalent-circuit model for an intrinsic device 6.4 Bipolar Deviee Models for eireuH and TIme-Dependent Analyses 357 ignoring the transistor parasitic resistances, and then the model for an extrinsic device with these resistances included... • Small-signal model when parasitic resistances are negligible. The Ebers-Moll model for an intrinsic transistor is shown in Fig. 6.17. Let us denote the steady-state base-emitter voltage by V~E and the collector-emittervoltage by VeE' The correspon­ vb. v"•. ding small-signal voltages are denoted as and Here, the convention is such that the primed parameters refer to an intrinsic device, while the unprimed parameters are for an extrinsic device. The corresponding small-signal base and collector currents are ib and ie, respectively. The intrinsic transconductance g'm relates ic to v'Jw , i.e., I ic ale 1 qlc gm = Vbe' = aVSE v' = CE kT' (6.99) where we have used the fact thatlc is proportional to exp(qVsE/kT). The intrinsic vb. input resistance r~ relates to ib, Le., vt. I r =- I " ib aIB kT f30 t) qIs gm (6.100) aVSE V' eE where we have used the fact that [s is proportional to exp(qVsE/kT) and that /30 = lei lB· The intrinsic output resistance to relates ic to v"., i.e., I, VA o ic Ie ' (6.101) where we have used Eq. (6.63) for the Early voltage VA. The capacitances are designated by CII = CdSC,lOl' (6.102) and C" = CdSE,lot + CDE' (6.103) The resulting small-signal equivalent circuit is shown in Fig. 6.19. This is the well­ known small-signal hybrid-1t model (Gray et al., 1964). B 0------- CI~l-,~IcE -+-L"CdC:'f~ Eo-- I ro t t v' g m he oE Figure 6.19. Small·signal hybrid-ll' model of a bipolar transistor when the parasitic resistances are neglected. 358 6 Bipolar Devices • Small-signal model including parasitic resistances. When parasitic resistances are included, the device tenninal voltages Ve, and VB are no longer the same as the internal junction voltages V~, V~ and V~, respectively, owing to the iR drops in the parasitic resistors r e, r e, and rb' For simplicity, we have lumped rbi and rbx into rb' The tenninal voltages and the internal junction voltages are related by Ve V~ + Ie,c, (6.104) VB V~ + iBrh, (6.105) and VE V~+ Iere = V~ (Ie + IB)'" where we have used the fact that h+ Ie+ IB =O. Therefore, VBE = V~E + IBrb + (Ie + IB)'e V~E + Ie r• + IB(rb + re) (6.106) (6.107) and VeE = V~E + Iefe + (Ic + IB)re ~ V~E + le(r. + re), (6.108) where in the last equation we have neglected the iR drop due to IB compared with that due to lc. The extrinsic transconductance g", relates ie to Vbe, i.e., ie ic gm = -Vbe Vb,. + l.ere + I.b (fb + fe ) (1 (I )-1 = g'm + re + ~ rb + re)-I ~ g'm + fe im 1 + g;"re ' where we have neglected (fb + r.)IPo relative to re and used the extrinsic input resistance r" relates Vbe to ib, Le., '1£=Vi-bb=e = vb. + iere + ih ib(rb + 'e) + g~,re) + (rb + re), (6.109) (6.99) for im' Similarly, (6.110) where we have used Eq. (6.100) for r'". The extrinsic output resistance ro relates ic to Vee, i.e., ro Vee = v~e + ic(r, + re) ie ie =10 + (r. + where we have used Eq. (6.101) for 10. (6.111) 6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses 359 CI' rb B~r~ C~L rc c g;,.v"./(1 +g'mTe) o ~~------oE Figure 6.20: Small-signal hybrid-1I: model of a bipolar transistor including parasitic resistances. The device capacitance components are still the same as before, with Cli given by Eq. (6.102) and Co: given by Eq. (6.103). It should be noted that Cli is determined by V'BO and not VBe- Similarly, Co: is detennined by V'BE' and not by VBE. The equivalent circuit can be deduced from Eqs. (6.109) to (6.111), and is shown in Fig. 6.20. 6.4.4 Emitter Diffusion Capacitance Consider a small ac signal superimposed on a dc forward bias across the emitter-base diode. The diffusion capacitance CDE is due to the minority carriers in the transistor that can respond to the small signal. Minority carriers that cannot respond to the signal do not contribute to the capacitance. (See Section 2.2.6 and Appendix 6.) Minority carriers are present in the emitter region, the base region, as well as in the space-charge regions ofthe emitter-base and base~ollector diodes. The total minority-carrier charge can therefore .I be written as the sum of these individual charges: + QDE !QE,IQI,acl + + ~BE.IQI.ael (6.112) where QE,Jot,ac, QB,IOJ,ac, QBE,tot,ac, and QBC,lol,ac represent the minority-carrier charge in the emitter, the base, the emitter-base space-charge region, and the base-collector space­ charge region, respectively, that can respond to the ac signal and contribute to the diffusion capacitance. A note about the symbols used to denote minority-charge quantities here and else­ where in the book is needed. As an illustration, let us consider the minority charge in the base region. In Eq. (2.144), we use QB to denote the minority charge per unit area in the base region ofa diode. We shall use QB,IO/ to denote the total minority charge in the base region. In the case of a simple diode with cross-sectional area Adiode, QB.IOI is simply AdiodeQB' However, in general, QB,/Ol cannot be written simply as AdiodeQB. QB.IOI can be detennined accurately only by using two-dimensional or three-dimensional numerical simulations. Nonetheless, it is often mathematically convenient to assume such a simple relationship, especially for explaining the basic physics governing device operation. Therefore, we shall use AdiodeQB to mean QS.tol in many cases. It should be remembered that it is QB,IOI that should be used in quantitative device modeling. Similar comments apply to the other minority-charge quantities QE, QBE, and Qsc. 360 6 ilipolar Devices Th~ subscript 'ac' on the RHS of Eq. (6.112) is to distinguisl! these quantities from their corresponding steady-state values which can be larger. [As discussed in Section 2.2.6 and in Appendix 6, QE.ac is equal to 1/2 of the steady-state quantity QE for a wide emitter device and QB.ac is equal to 273 of the steady-state quantity QB' QBE.ac and QBC.ac are usually assumed to be the same as the corresponding steady-state quantities. This is a good assumption because of the high field in the space-:eharge regions. In a high field space-charge region, the electrons travel at their saturated velocity Vsat which is about 1 x 107 cmls (see Fig. 2. I0). For a space-charge layer width of0.1 ~m, the average transit time for the electrons is on the order of 10- 12 s. This time is short compared to Iff, wherefis the frequency ofa typical signal. That is, electrons in a space­ charge region should be able to respond to an ac signal.] Notice that QDE is the sum of the absolute values of the individual minority-:earrier charge components, and not the summation of the net charge components. As an illustration of this important distinction, consider a hypothetical transistor having a perfectly symmetrical emitter-base diode, with the n-region doping concentration equal to the p-region doping concentration (not a good transistor design, but a transistor nonetheless). In this case, we have QB.ac =- QE.ac' The contributions of QB.ac and QE.ac to QDE are IQB.acl and IQE.acl, and not QB.ac + QE.ac, which is zero. (Also, see the discussion at end of the next subsection.) Ifthe intrinsic base-emitter forward-bias voltage is V~E(t), then the emitter diffusion capacitance is CDE ~ l)QD.E BE (6.113) For modeling purposes, it is convenient to consider the collector current ic(t) being the charging current and rewrite Eq. (6.112) in the form QDE !Fic(t), (6.114) where !F is referred to as the forward transit time. As we shall show later, at low current densities where base widening is negligible, each of the minority-charge components in Eq. (6.112) is simply proportional to the collector current. In this case, !F is independent of the base-emitter bias. If we write the intrinsic base-emitter forward-bias voltage in the form v~E(t) V~E v~e(t), where V~E is the dc bias and Vlbe(t) is the small signal, then q1i icCt) ~ fe[1 + e t)] (6.115) and Eqs. (6.113) and (6.114) give CDE = = IF qklTc = rFgIm (Iow current den'clty), (6.116) where Ic is the steady-state collector current determined by VAE and g~, is the intrinsic transconductance given by Eq. (6.99). However, at sufficiently large current densities, base-widening occurs, and, as discussed in Section 0.3.3, the total minority charge in the 6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses 361 base, QB.IOh increases rapidly with collector current density. Therefore, we expect QB.wl.ac to increase rapidly with .collector current density as well. In this case, rF is no longer independent of the base-emitter bias. Instead, it inereases rapidly with collector current density, and Eq. (6.116) is no longer valid. Comparing Eqs, (6.112) and (6.114), we see that '1" has contributions from QE.tot.ac, QB,tot.oe> QSE,IOI.OC' and QSC,tot.ac, To help distinguish the various contributions, !F is often written as the sum of these components, namely, + + TF rE +!B TBE TBC· (6.117) .. In Eq. (6.117), TE is the emitter delay time, representing the contribution from QE.tot,oc, IB is the base delay time, representing the contribution from QB.lol.ac, !SE is the base-emitter space-charge region delay time, representing the contribution from QBE.lot.ac, and rBe is the base-collector space-charge-region delay time, representing the contribution from QBC,tol.ac (Ashburn, 1988). The emitter is being charged by the base current, so that we expect IQE,tol.acl to be proportional to fB (see Section 2.2.6). For a wide emitter, Eq. (2.166) suggests that = = IQE,tol,acl fBtpd2 IC!pEI2Po, where 'pE is the hole lifetime in the n+ emitter and Po is the common-emitter current gain. (Remember, here the Qs include only the portion of minority charge that can follow the ac signal and contribute to the emitter diffusion capacitance. For a wide emitter, this portion is 1/2 of the total minority charge in the emitter.) Similarly, the base is being charged by the collector current, so that we expect IQB.lol.acl to be proportional to Ie- However, this is the case only when there is negligible base widening. In this case Eq. (2.165) suggests IQB.lot.acl "" 2IdB /3, where ta is the base transit time. When base widening occurs, IQB.tol.acl increases with Ic at a much faster rate. The space-charge-region delay time is equal to the average transit time for the corresponding space-charge region. This time is Wi2v"a11 where Wd is the depletion layer width and VSfJl is the saturated electron velocity (Meyer and Muller, 1987). Considerations of these delay-time components in the design of a bipolar transistor will be covered in Chapter 8 (see Section 8.3.3). 6.4.5 Charge-Control Analysis The behavio~ ofa bipolar transistor is often analyzed in a charge-control model where the charges within the various regions of the transistor are related to the currents feeding them. The charge-control model is especially useful for transient analyses. It was used in Section 2.2.5 to describe the discharging of a diode that has been switched from forward bias to reverse bias. In this subsection, we describe the time-dependent behavior of an n-p-n transistor using charge-control analysis. As we shall show later, the starting point for applying charge-control analysis is after spatial integration of the continuity equation for the physical region of interest. In other words, an entire transistor region is considered as one lumped component. As a result, a charge-control analysis does notyield or depend on information about the distribution of the minority charge within the region. A charge-control method is thus limited to 362 6 Bipolar Devices 6.4 Bipolar Device Models for CircuH and Time-Dependent Analyses 363 (a) - - - r - Vee RL 1-------0 ve (t) "a(t) (b) iE(t) r. .. • CdlIE,lo/(dvoE/dt) ,,,; E :, B I 0: 00 .-~.- CdlIC•tOi (dv'coldt) ,' I ieU) C vca(t) tiB (I) VE=O ,,,, VB(t) ,,", ,,, Vee ----: ~ --......: ~ !,, WaE , WdBC :, : -WE o I .x WB Figure 6.21. (a) Schematic of an n-p-n transistor biased to operate as an amplifier. The input voltage VB is assumed to be time dependent. (b) Schematic illustrating the resistances and terminal currents in the amplifier. Also illustrated are the displacement currents and the flow of electrons and holes within the transistor. The locations of the emitter contact, the emitter-base boundary, and the base-collector boundary, used in the charge-control model, are also indicated. WdBE and WdQC are the base-emitter and the base-collector junction depletion-layer widths, respectively. denoted by ie(t), io(t), and ic(t), respectively. The displacement currents in the base­ emitter and base-collector junctionnepletion-layer capacitors are also included. As the electrons flow through the emitter-=-base and base-collector junction space­ charge regions, they contribute to the mobile chargesQBE and QBe stored in .these regions. (As the holes flow from the base into the emitter, they also contribute to a mobile charge component in the emitter-base space-charge region. However, this hole component, which is proportional to the base current, is small compared with the electron component, which is proportional to the collector current. For simplicity, the hole component of mobile charge stored in the emitter-base space-charge region is ignored.) To facilitate including QRE and QRC in the charge-control analysis, we define the base region to include the emitter-base space-charge layer and the base-collector space-charge layer. Thus, for our charge-control analysis, the emitter contact is located at x =- WE, the emitter-base boundary is located at x '" 0, and the base-collector boundary is located at x'" WB, as illustrated in Fig. 6.21(b). For mathematical simplicity, let us assume a one-dimensional transistor structure having a cross-section area ofA. From Eq. (2.110), the continuity equation for the excess electrons in the p-type base is A o(np npO) = ~ Oi.(x, t) _ A--'--~ fJt q fJx 1:nB (6.118) where in(x, t) is the electron current in the base and 1:,,0 is the electron lifetime in the base. Multiplying both sides ofEq. (6.118) by -q and integrating over the base region, we have -Aqi-J1WB iJ/ 0 np{l)dx = l wa dx + A (np np{l)dx, (6.119) 7:nR 0 which is the starting equation for charge-control analysis. The excess electron charge per unit area stored in the base is iofWB q (np - npO)dx = QSE + Qs + Qne, (6.120) where QBE, Qo, and QBC are the excess electron charges per unit area stored in the quasistatic situations where all the minority charge within the region of interest can emitter-base space-charge layer, in the quasineutral base layer, and in the base-collector respond fully to a time-dependent Voltage. Charge-control analysis is not suitable for space-charge layer, respectively. Therefore, Eq. (6.119) can be rewritten as situations where the distributed nature of the stored charge is important, e.g., in the derivation of the diffusion capacitance (see Section 2.2.6 and Appendix 6). Charge­ A ddt (QB + QBE + QRC) = ill (O, t) control method should not be used/or small-signal ac analysis ofbipolar transistors W B, t) A _--==..:.....'~lJL !nB (6.121) without great care. Consider an n-p-n transistor biased in an amplifier mode. Its circuit schematic is shown in Fig. 6.21(a). The input voltage, which is the base terminal voltage, is assumed to be time dependent. The currents flowing in the transistor are illustrated schematically in Fig. 6.21 (b). The time-dependent emitter current, base current and collector current are Similarly, integrating the continuity equation for the excess holes.over the emitter region, we obtain dQE A- dt . Ip(-WEl t) I.p(O,t) - AQ-E, 'pE (6. j 22) 364 6 Bipolar Devices where qjO QE = (p" _ pnO)dx _WE (6.123) is the excess hole charge per unit area stored in the emitter, and opE is the hole lifetime in the emitter. From the current components illustrated in Fig. 6.21(b),the emitter current is = in(O, t) + t) - CdSE,tot dVBE(t) dt ' (6.124) where v'BE v'B v'E is the time-dependent intrinsic voltage across the base-emitter junction, and CdSE,lot is the base-emitter junction depletion-layer capacitance. The collector current is ic(t) = -in(WB, t) + CdBC,d/vQ 'CIB~ (t)' (6.125) where veB Ve - v~ is the time-dependent intrinsic voltage across the base-collector junction, and CdBC.tol is the base-collectorjunction depletion-layer capacitance. The base current is is{t) - iE{t) - ic(t) t) - in(Ws , t)]- ip(O, t) + CdBE,101 ~ dv'BE(t) CdBC,IOI ~ dv~s. (t) (6.126) Using Eq. (6.121) for in(O, t)-iiWB , t) and Eq. (6.122) for ip(O, t) in Eq. (6,126), we obtain iB(I) =-A d(QB + QBE + QBd + A dQE A QB + QBE + QBC + A QB dt dl 1;"B 'pE , -lp(-WE,t) + CdBE,dtv'oBEl(~t) CdRC"dVOC/B(~t) _ d(QR,1Of + QBE,IOI + QBC,I<>I) + dQE,101 _ QR.101 + QBE,101 + QBC.101 + dt dl 'nR 'pE WE, I) + CdBE,101 d~ v'BE( t) - CdBC.IOI ~ NCB' (t) (6.127) where, as explained in Section 6.4.4, we have replaced AQB by QB.lO/, AQBE by Q8E,IOI' etc., to make the applicability of Eq. (6.127) not limited to a one-dimensional bipolar transistor but to a bipolar transistor of arbitrary device structure. Equation (6.127) is the charge-control model for the base current of a bipolar transistor. It states that the base current feeds the excess minority charge in the emitter and the base, the t>ase-emitter diode depletion-layer capacitance, the base-collector diode depletion-layer capacitance, the recombination current in the base, the recombination current in the emitter, and the hole recombination current at the emitter contact. 6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses 365 The base-current equation can be reduced to a more useful form by noting the relationship between v~B(t).and "v~E(l). We have v~B(I) v~(t) - Ys(t) = [v'B(I) - v£(t)] + [v~(t) YE(t)] ~ -v'OE(t) + VCE(t) ic(t)(re + rc) = -v'BE(t) + Vcc ic(t)(RI. + re + rc), (6.128) where we have used Eq. (6.108) which relates VeE to VCE, and the fact that VCE= Vcc- icRL• Therefore, NCSCI) = dV~E(t) _ (RL + r + dt dt e Substituting Eq. (6.129) into Eq. (6.127), we have dic(t) ----;Jt . (6,129) 1,8(t) = d(QR,tOI + QBE,IOI + QBC,IOI) +- dQE- ,II + Q8£,10I + QBC,IQt) + QE,!OI] -fpC _ WE)' (6,131) - h 'ro8" 'pE steady stale That is, in the steady state, the base current is simply equal to the sum of the recombina­ tion currents in the base, in the emitter, and at the emitter contact. Ifwe assume the time dependence is quasistatic such that the steady-state relationship in Eq. (6,131) between the collector current and the sum of the recombination currents holds for the nonsteady state as well, i.e., if we assume icC!) -(QO,lol +QB£,IOI + QBc'iOt) +fh.lOt _ ip(-WE,t), flo 'rnO 'rpE then Eq, (6.130) becomes (6.132) is(t) =_ d(QB,101 + QBE,IOI + Q8(',101) + dQE,lol + ic(t) dt dt flo tn, + + [CtlBE,101 + CdBC,101 CtlBc/ol(R/. + re + dic(t) dt (6.133) 366 6 Bipolar Devices This is the differential equation relating the time-dependent base and collector currents for a transistor with a resistive load RL (Ghandhi, 1968). In Section 6.4.4, we made the distinction between the total stored minority charge in a transistor and the portion of minority charge capable of respond.ing to an ac signal and contributing to the emitter diffusion capacitance. In the literature, often this distinction is not made. In that case, the first two terms in Eq. (6.133) related to the change in the total stored charge with time are replaced by the term 1:p didt)ldt [see Eqs. (6.112) and (6.114)]. This is equivalent to using the charge-control method to derive the emitter diffusion capacitance, which, as discussed in Section 6.4.4 and in Appendix 6, over­ estimates the emitter diffusion capacitance. . In writing Eq. (6.112), we indicated that the minority charge responsible for the emitter diffusion capacitance is the sum ofthe absolute amounts coming from the various regions ofthe bipolar transistor. In Eq. (6.133), the minority charge QS.,o' + QSE.to, + Qsc.tot in the base is due to electrons while the minority charge QE.tot in the emitter is due to holes. Therefore, the two dQldt terms, including their signs and the fact that an electron has a charge -q while a hole has a charge q, actually add together to give the derivative of the sum ofthe absolute amounts ofminority charges with respect to time. In other words, the charge-control analysis automatically gives the correct summing ofthe minority charges in the various regions of a bipolar transistor for determining their contributions to the emitter diffusion capacitance. If it were not for the subtle difference between Qand Qac, Eq. (6.133) would have led to the correct emitter diffusion capacitance. Indeed, if we assume substituting TFdidt)/dt for the first two terms in Eq. (6.133) to be valid, then (6.133) would give the expected frequency-dependent behavior ofa bipolar transistor (Ghandhi, 1968). 6.5 Breakdown Voltages The breakdown voltages of a bipolar transistor are often characterized by applying a reverse bias across two of the three device terminals, with the third device terminal left open-circuit. These breakdown voltages are usually denoted by BVEBO emitter-base breakdown voltage with the collector open-circuit, BVCBO = collector-base breakdown voltage with the emitter open-circuit, BVCEO = collector-emitter breakdown voltage with the base open-circuit. Since bipolar transistors are usually operated with the emitter-base junction zero­ biased or forward biased, their BVEBO values are not important as long as they do not adversely affect the other device parameters. On the other hand, BVCBO and BVCEO must be adequately large for the intended circuit application. BVcso and BVCEO are often determined, respectively, from the measured common-base and common­ emitter current-voltage characteristics. The measurement setups for an n-p-n tran­ sistor, and the corresponding I-V characteristics, are illustrated schematically in 6.22. 6.5 Breakdown Voltages 367 (a) Ie 18 ",0 (b) IE=O· Ie ~v~ (c) Ie Common-base 1£",0 o BVCEO BVeBo VeBor VeE Rgure6.22. Circuit schematics for measuring (a) BVcEo and (b) BVcBo of an n-p-n transistor. (c) Common-emitter Ie-VCE characteristics at IB = 0, and common-base Ic.-VeB characteristics at IE = O. 6.5.1 Common-Base Current Gain in the Presence of Base-Collector Junction Avalanche Consider an n-p-n transistor biased in the forward-active mode, as illustrated in Fig. 6.23(a). The corresponding energy-band diagram and the electron and hole current flows inside the transistor are illustrated in Fig. 6.23(b), where the locations ofthe emitter-base junction and the base--collector space-charge layer, where avalanche multiplication takes place, are also indicated. The emitter current Ie is equal to the sum ofthe hole current entering the emitter from the base and the electron current entering the base from the emitter, Ie AE[Jn(O) + (6.134) where AE is the emitter area. It should be noted thatIE, defined as the current entering the emitter, is a negative quantity for an n-p-n transistor, since both I n and Jp are negative. As the electrons traverse the base layer, some of them can recombine within the base layer. Only those electrons reaching x = Ws contribute to the collector current. In the presence of avalanche multiplication in the reverse-biased base--collector junction, the electron current exiting the base--collector space-charge layer is a factor ofM larger than that entering the space-charge layer, where M is the avalanche multiplication factor (see Section 2.5.1). That is, In(Wa + = MJn(Wa). (6.135) The collector current Ic is equal to the electron current exiting the base--collector space­ charge layer, i.e., Ic = -AEJn(Wa + WdBC). (6.J36) 368 6 Bipolar Devices HE V VlCiH I~ (a) IlIlGB_. Base Collector Ie ...Ec - ___-..'i ·1· ~! ,'" t. . ~ Ev O ~.' (b) ; -- Ec l - - - - - EV . ..x -W/i We Wn + WdHC Figure 6.23. (a) Schematic illustrating the voltages and currents in an n-p-n transistor biased in the fOIWard-active mode. (b) The corresponding energy-band diagram and illustration of the electron and hole flows inside the transistor. Also indicated are the locations of the emitter-base junction and the base-collector space-charge layer. The minus sign in Eq. (6.136) is due to the fact that, as defined, Ie is a current entering the collector, Ie is a positive quantity for an n-p-n transistor. Using Eqs. (6.134) to (6.136), we can rewrite the static common-base current gain ao [cf. Eq. (6.54)] as ale Qo aJn(Wn + WdBc) a[In(O) + Jp(O)]" alII (0) aJn(WB ) 81n( WB + Wdnc) a[Jn(O) +lp(O)] 81n(0) aln(WB ) =ycqM, where the emitter injection efficiency y is defined by _ M,(O) In(O) y = 8 [In(O) + l p (O)T In(O) + lp(O)' and the base transport factor aT is defined by (6.137) (6.138) QT'=" aJn(WB } alII (0) =11-/(W-n.) 111(0) (6.139) 6.5 Breakdown Voltages 369 6.5.2 When base--collector junction avalanche effect is negligible, we have M ~ 1, and the common-base current gain is Qo = l'Cl:T (when M (6.140) Ifwe further assume that recombination in the thin base is negligible (see Exercise 6.6), then the common-base current gain is simply + 8Jn(0) ao = y a[JIICO) lp(O)] (when M I and (XT = 1). (6.141) . [Note: Throughout this chapter, by equating the collector current to the electron current entering the intrinsic base, i.e., Eq. (6.31), and by equating the base current to the hole current entering the emitter, i.e., Eq. (6.41), we have implicitly made the assumptions that M= 1 and aT = I. That is, we have implicitly assumed that ao=Y.] Saturation Currents in a Transistor If we define hBO and leBO by (Ebers and Moll, 1954) lEBO lFO(l - Cl:RCl:F) and (6.142) leBO lRO(I - QRQF), (6.143) then Eqs. (6.88) and (6.89) give IE = -hBO[exp(qVndkT) - I] QRle (6.144) and Ie = -IeBo[exp(qVBc/kT) -1] - Cl:Fh... (6.145) The physical meaning of hoo and leBO is apparent from these equations. hBo is the saturation current of the emitter-base diode when the collector is open-circuit, i.e., it is the emitter current when the emitter-base diode is reverse biased and Ie = .o. This is the current one measures in measuring BVEBO' Similarly, leBo is the saturation current ofthe collector-base diode when the emitter is open-circuit, i.e., it is the collector current when the base-collector diode is reverse biased and h = O. This is the current one measures in measuring BVeno. leBO is indicated in Fig. 6.22(c). Let us apply Eq. (6.145) to the BVceo measurement setup shown in Fig. 6.22(a). We note that when VeE is near BVCEO, the collector-base diode is reverse biased. Also, at In .0, Ic = -IE' Therefore, Eq. (6.145) gives, for the common-emitter configuration with the base-colleetor juriction reverse biased and at in = .0, Ie = leBo. 1- Cl:F (6.146) This is the saturation current in the common-emitter configuration. We shall denote this current by 1CEO, i.e., 370 6 Bipolar Devices 6.5.3 ICEO = ICBO - 1- a-o- ' (6.147) where we have used the fact that aF= ao. This current is also indicated in Fig. 6.22(c). His clear from Eq. (6.147) that I CEO is significantly larger than ICBO• since ao is usually less than but close to unity. This is indicated in Fig. 6.22(c). Relation Between BVCEO and BVcoo As pointed out in Section 2.5.1, the breakdown voltages in VLSI devices are usually determined experimentally, rather than calculated from some model. The avalanche multiplication factor M in a reverse-biased diode is often expressed in terms of its break­ down voltage BVusing the empirical formula (Miller, 1955) M(JI) == f ITTI nT.?'I.m' (6.148) where Vis the reverse-bias voltage and m is a number between 3 and 6 depending on the material and its resistivity. Thus, for the reverse-biased collector-base diode, we have M(VCB) = 1- (VCB/1J3V~~oyii' (6.149) Equation (6.147) implies thaticED becomes infinite when ao = 1. From Eq. (6.137), this means that when the collector voltage reaches BVCED, yaTM(VCB) = yaTM(BVcEO ) = 1. (6.150) Equations (6.149) and (6.150) give BVCED BVCBO (1 y a) lT/ m· (6.151) Since l-yaT~ I, Eq. (6.151) indicates that BVCED can be substantially smaller than BVCBO' This is illustrated in Fig. 6.22(c). Another way of comparing these breakdown voltages is to note that it takes M approaching infinity to cause collector-base break­ down, while it takes M only slightly larger than unity to cause collector-emitter break­ down (see Exercise 6.7). From Eq. (6.140), yaT =ao(M= 1)=Pol (l +Po), where we have used (6.55) and Po is the current gain at negligible collector-base junction avalanche. Thus, Eq. (6.151) can also be written as (_I_) BVCEO = Ilm~ (~) 11m BVcBo 1 +,80 ,80 (6.152) Equation (6.152) shows that there is a tradeoff between the coUector-emitter break­ down voltage and the current gain of a transistor. It should be noted that the relationship between BVCEO and BVcBo in Eq. (6.152) is valid only when collector-base junction breakdown is governed by thc intrinsic-base­ collector diode, and not the extrinsic-base-collector diode. This mayor may not be the Excercises 371 8.-------------------------~ 6 f lil 4 ~ t:Q BVCEO=BVCBOI2 _ •• BVcno (V) Figure 6.24. Reported BVCEO versus BVcso data for recently published n--p-n transistors. case in a typical transistor, depending on the device structure and the fabrication process employed. (The BVcBo of a modern bipolar transistor, with its extrinsic base formed independently ofthe intrinsic base and its collector optimized for minimal capacitance, is usually determined by the intrinsic-base-eollector diode rather than the extrinsic-base­ collector diode. The design and characteristics of modern bipolar transistors are covered in Chapter 7.) Figure 6.24 is a plot of BVCED versus BVcBD based on data reported in recent literature for n-p--n transistors. It shows that for modem n-p--n transistors, B VCEO is typically a factor of 2 to 4 smaller than BVCBO. Excercises 6.1 The electric field in an n-type semiconductor is given by Eq. (6.20), i.e. CR( rp n-regl.O)n (J kT -d- nrr - ,1 d- nTe) . q nn dx nie dx Derive this equation, stating clearly the approximations made in the derivation. 6.2 The hole current density in the n-side of a p--n diode is given by Eq. (6.26), i.e" Jp(X) n - 2 qDP..n.n! !d.dx- (nnp~) n-2 • ie Derive this equation, stating clearly the approximations made in the derivation. 6,3 For a polysilicon emitter with the emitter-base junction located at x = 0 and the silicon-polysilicon interface located at x=- WE, the emitter Gummel number is given by Eq. (6.46), namely 1) ( nf)(WE GE NE - -'+­ n7eE DpE Sp . One model (Ning and Isaac, 1980) for relating Sp to the properties of the polysilicon layer is to assume that there is no interfacial oxide, so that the transport of holes 372 6 Bipolar Devices through the interface is simply detennined by the properties ofthe polysilicon layer. Let WEI be the thickness of the polysilicon layer, and let DpEI and LpEI be the hole diffusion coefficient and hole diffusion length, respectively, in the polysilicon. Assume an ohmic metal-polysilicon contact. (a) Let tlpn(- WE) be the excess hole concentration at the polysilicon-silicon interface, and let x' denote the distance from the polysilicon-silicon interface, i.e., Xl = - (x+ WE)' Show that the excess hole distribution in the polysilicon layer, tlpn(x'), is given by [cf. Eq. (2.119)] sinh[(WEI - x)/LpEI ] l::..pn(x' ) = l::..pn(- WE) sinh(WEJ/LpEl) (b) The relationship between Sp and the hole current density entering the polysilicon layer is given by Eq. (6.36). Show that DpE! SP LpEI tanh (WEI / LpGI ). 6.4 Consider an n-p--n transistor with negligible parasitic resistances (which will be included in Exercise 6.5). Equations (6.144) and (6.145) give IE -hBo[exp(qV~E/kT) -1] - CtRle and -IJ - Ie = -leno[exp(qV~e/kT) CtFh, where V~E and V~e are the internal base-emitter and base-collector junction bias voltages. If the transistor is operated in saturation, i.e., both V~E and V~e are positive, show that the internal collector-emitter voltage, Vh = Vc - V~, is related to the currents by VC,.E kTI q n [GAhno aR(IeBo - Ie Ie - aRId] aFh) . [Hint: Use Eqs. (6.90), (6.142), and (6.143) to show that ICBdIEBO= aFt aR.] 6.5 From the expression for VCE in Exercise 6.4, show that if the emitter and collector series resistances re and rc are included, and if the saturation currents leno and ICBO are negligible, the voltage drop across the collector and emitter tenninals, VCE =Ve - VE, is given by kT In [ IB + le(l - aR) ...] + re(TB + Ie) + rcle VCE q aR!IB Ic(1 Ci.F)/Ci.F] _ and that for open-circuit collector (I) VCE(Ie = 0) = -kTIn q -aR + relB' Excercises 373 [The emitter resistance re is often detennined from a plot of the saturation open­ collector voltage, VertIc ",,·0)... as a function of In (Ebers and Moll, 1954; Filensky and Beneking, 1981). The collector resistance rc can be detennined in a similar way by interchanging the emitter and collector connections.] 6.6 For an n-p--n transistor, the base transport factor aT is given in Eq. (6.139), I.e., _ In(x Wn) aT = In(x 0)' where the intrinsic-base layer is located between x=O and x= WB. For a unifonnly doped base, the excess-electron distribution is given by Eq. (2.119), namely sinh[(WB X)/LnB] np-npO=npO!exp(qVnE/kT) 1] sinh(WB/LnB) lfthe electron current in the base is due to diffusion current only, show that Ci.T ( cosW h~) - I LnB Use Fig. 2.24(c) to estimate aT for a unifonnly doped base with NB "" 1 x 1018 cm- 3 and Wn"" 100nm, and show that our assumption of negligible recombination in the intrinsic base is justified. 6.7 If M is the avalanche mUltiplication factor for the base-collector junction, and flo is the common-emitter current gain at negligible base-collector junction avalanche, show that the collector-emitter breakdown occurs when 1 M-l=f30' [Hint: Use Eqs. (6.140) and (6.150).] (It is interesting to note that sincePo is typically about 100, collector-emitter breakdown occurs when M is only slightly larger than unity. That is, it does not take much base--collector junction avalanche to cause collector-emitter breakdown.) '7 Bipolar Device Design Bipolar device design can be considered in two parts. The first part deals with designing bipolar transistors in general, independent of their intended application. In this case, the goal is to reduce as much as possible, consistent with the start-of-the-art fabrication technology, all the internal resistance and capacitance components ofthe transistor. The second part deals with designing a bipolar transistor for a specific circuit application. In this case, the optimal device design point depends on the application. The design of a bipolar transistor in general is covered in this chapter, and the optimization ofa transistor for a specific application is discussed in Chapter 8. 7.1 DeSign of the Emitter Region It was shown in Section 6.2 that the emitter parameters affect only the base current, and have no effect on the collector current. In theory, a device designer can vary the emitter design to vary the base current. In practice, this is rarely done, for two reasons. First, for digital-circuit applications, as long as the current gain is not unusually low or the base current unusually high, the performance of a bipolar transistor is rather insensitive to its base current (Ning et al., 1981). For many analog-(;ircuit applications, once the current gain is adequate, the reproducibility of the base current is more important than its magnitude. Therefore, there is really no particular reason to tune the base current of a bipolar device by tuning the emitter design, once a low and reproducible base current is obtained. Second, as can be seen in Appendix 2, the emitter is formed towards the end of the device fabrication process. Any change to the emitter process to tune the base current could affect the doping profile ofthe other device regions and hence could affect the other device parameters. As a result, once a bipolar technology is ready for manufacturing, its emitter fabrication process is usually fixed. All that a device designer can do to alter the device and circuit characteristics in this bipolar technology is to change the base and the collector designs, which often can be accomplished independently of the emitter process and hence has no effect on the base current. The objective in designing the emitter of a bipolar transistor is then to achieve a low but reproducible base current while at the same time minimizing the emitter series resistance. As illustrated in Fig. 6.2, the commonly used bipolar transistors have either a diffused (or implanted-and-diffused) emitter or a polysilicon emitter. The design ofboth types of emitters is discussed in this section. 7.1 Design of the Emitter Region 375 7.1.1 Diffused or Implanted-and-Diffused Emitter A diffused or implanted-and-diffuSed emitter is formed by predopiug a surface region ofthe silicon above the intrinsic base and then thermally diffusing the dopant to a desired depth. As shown in Eq. (6.48), for a diffused emitter, the base current is inversely proportional to the emitter doping concentration. Therefore, to minimize both the base current and the emitter series resistance, a diffused emitter is usually doped as heavily as possible. For n-p-n transistors, arsenic, instead of phosphorus, is usually used as the dopant, because arsenic gives a more abrupt doping profile than phosphorus. A more abrupt emitter doping profile leads to a shallower emitter junction, and, as we shall see later, a shallow emitter junction is needed for achieving a thin intrinsic base. Also, a shallower emitter has a smaller vertical junction area and associated capacitance. A diffused emitter typically has a peak. doping concentration of about 2 x 1020 cm-3, as indicated in Fig. 6.2(a). A diffused emitter is contacted either directly by a metal, or by a metal via a metal silicide layer. Commonly used silicides for emitter contact include platinum silicide and titanium silicide. If the fabrication process leaves negligible residual oxide on the emitter prior to contact formation, the resultant contact resistivity, as discussed in Section 2.4.4, is a function of the metal or metal silicide used, as well as a function ofthe emitter doping concentration at the contact. For a doping concentration of2 x 1020 cm-3 at the contact, a specific contact resistivity of about (1-2) x 10-7 U-cm2 should be achievable. Using the resistivity values ofsilicon shown in Fig. 2.9, the specific series resistivity of a 0.5-Jlm-deep silicon region, with an averaged doping concentration of I x 1020 cm-3, is about 4 x 10-8 Q_cm2• Therefore, the series resistance of a diffused emitter is dominated by its metal-silicon contact resistance; the series resistance of the doped-silicon region itself is negligible in comparison. For a diffused emitter of I 1J.Il12 in area, the emitter series resistance is typically about 10-20 Q. It can be inferred from Fig. 6.I(b) that the intrinsic-base width WB is related to the emitter junction depth XjE and the base junction depth XjB by WH = XjH - XjE. (7.1) As we shall see in Section 7.2, one of the objectives in the design ofthe intrinsic base is to minimize its width. For WB to be well controlled, reproducible, and thin, XjE should be as small as possible. IfxjE is much larger than WH, then WB is given by the difference oftwo large numbers and hence will have large fluctuation. Commonly used metal silicides are formed by depositing a layer of the appropriate metal on the silicon surface and then reacting the metal with the underlying silicon to form silicide. The emitter width WE is therefore reduced when metal silicide is used for emitter contact, because silicon in the emitter is consumed in the metal silicide formation process. As shown in Section 6.2.2, once WE is less than the minority-carrier diffusion length, the base current increases as 11WE' As a result, the base current, and hence the current gain, ofa bipolar transistor with a shallow diffused emitter varies with the emitter contact process (Ning and Isaac, 1980). Referring to the minority-carrier diffusion lengths shown in Fig. 2.24(c), we see that the junction depth of a diffused n-type emitter should be larger than 0.3 IJ.Il1 in order to 376 7 Bipolar Device Design 7.1.2 have adequately controllable and reproducible base-current characteristics. Diffused emitters are there/ore not suitable for base widths ofless than 100 nm. Polysilicon Emitter Practically all modem high-performance bipolar transistors with base widths of 100 nm or smaller employ a polysilicon emitter. In this case, the emitter is formed by doping a polysilicon layer heavily and then activating the doped polysilicon layer just suffi­ to obtain reproducible base current and low emitter series resistance. The emitter junction depth, measured from the silicon-polysilicon interface, can be as small as 25 nm (Warnock, 1995). Consequently, with polysilicon-emitter technology, base widths of 50 nm or less can be obtained. The polysilicon-emitter process recipes are usually considered proprietary. However, there is a vast amount of literature on the physics of polysilicon-emitter devices (Ashburn, 1988; Kapoor and Roulston, 1989). Interested readers are referred to these publications. The base current of a polysilicon-emitter transistor is given by Eqs. (6.42) to (6.44), with a surface recombination velocity, Sp, appropriate for the particular process used for forming the polysilicon emitter. The Sp is usually used as a fitting parameter to the measured base current. In general, the base current of a polysilicon-emitter transistor is sufficiently low so that current gains in excess of 100 are readily achievable. As will be shown in Chapter 8, the maximum speed of a modem bipolar transistor is determined primarily by its diffusion capacitance. In Section 2.2.6, the diffusion capa­ citance due to minority-carrier storage in the emitter was shown to be small compared to that due to minority-carrier storage in the base. Therefore, the maximum speed of a bipolar transistor is relatively insensitive to the emitter component of its diffusion capacitance. In other words, as long as the desired base-region characteristics are obtained, the details of the emitter region have relatively little effect on the maximum speed of a bipolar transistor (Ning et al., 1981). Nonetheless, a polysilicon-emitter fabrication process should be designed to give low emitter series resistance and adequate emitter-base breakdown voltage, as well as the desired base-region characteristics. The series resistance ofa polysilicon emitter includes the polysilicon-silicon contact resistance, resistance of the polysilicon layer, and resistance of the metal-polysilicon contact. The specific resistivity ofa metal-polysilicon contact is about the same as that ofa metal-silicon contact. For arsenic-doped polysilicon emitters, the reported specific silicide-polysilicon contact resistivity is typically (2-6) x 10-7 il-cm2, depending on the arsenic concentration (!inuma et al., 1995). It is large compared to the series resistance of the polysilicon layer itself. The polysilicon-silicon contact resistance, on the other hand, is a strong function ofthe polysilicon-emitter fabrication process and can vary by large amounts (Chor et al., 1985). In fact, polysilicon-emitter technology is still an area of active development. The recently published data (hnuma et at., 1995; Uchino et al., 1995; Kondo et al., 1995; Shiba et al., 1996) suggest that a total emitter specific resistivity, which includes contributions from both the polysilicon-silicon interface and the metal--polysilicon contact, of7-50 il-flm2 should be obtainable (see Exercise 7.7). 7.2 Design of the Base Region 377 Figure 7.1. .-. .f!J '§ ~ § .~ i OJ) .5 p. .g j Actual emitter profile \ \ \;/~ Emitter SIMS profile \ .\ ~ Base SIMS profile Distance (arb. units) Schematic illustrating the measured SIMS doping profiles of the emitter and base of a modem n-p-n transistor. The measured emitter SIMS profile is usually less abrupt than the real one. The small junction depth of a polysilicon emitter implies a relatively small perimeter, or vertical, extrinsic-base-emitter junction area. The total emitter-base junction capaci­ tance ofa polysilicon emitter is therefore much smaller than that ofa diffused emitter. For a 0.3-fllTI emitter stripe, the total emitter-base junction capacitance of a polysilicon emitter can be less than! of that of a diffused emitter. It should be pointed out that the junctior of a polysilicon emitter is so shallow that the commonly used secondary-ion mass spectroscopy (SIMS) technique for measuring dopant concentration profiles often indicates an emitter junction deeper than it really is. The real emitterjunction depth can be obtained from the p-type base SIMS profile, which shows a dip where the n-type and p-type doping concentrations are equal (Hu and Schmidt, 1968). This is illustrated schematically in Fig. 7.1. 7.2 Design of the Base Region It was shown in Section 6.2 that the base-region parameters affect only the collector current, not the base current. The base current is determined by the emitter parameters. It has been demonstrated experimentally (Ning et ai., 1981), and will be discussed in Chapter 8, that the performance of a bipolar circuit is determined primarily by the collector current, not the base current, at least for circuits where the bipolar transistors do not saturate. Thercfore, as long as current gain is adequate, which is the case with a emitter, the focus in designing or optimizing a bipolar transistor should be on the collector current, and not on the base current. In other words, the focus should be on the intrinsic base when there is negligible base widening, and on both the intrinsic base and the collector when base widening is not negligible. The design of the base of a bipolar transistor can be very complex, because of the tradeofts that must be made between the ac and dc characteristics, which depend on the intended application, and because of the tradeoffs that must be made between the desired 378 7 Bipolar Device Design device characteristics and the complexity of the fabrication process for realizing the design. In this section, the relationship between the physical and electrical parameters of the base is derived, and the design tradeoffs are discussed. Optimization of the base design for various circuit applications will be covered in Chapter 8. Referring to Fig. 6.12, we can divide the base region into two parts. The part directly underneath the emitter is the intrinsic base, and the part connecting the intrinsic base to the base terminal is the extrinsic base. As a first-order but good approximation, the intrinsic base is what determines the collector current characteristics, and hence the intrinsic performance of a transistor. The discussiGns and the collector current characteristics derived in Chapter 6 are all for the intrinsic base. Effects ofthe extrinsic base were ignored. The extrinsic base is an integral part of any bipolar transistor. It is a parasitic component in that it does not contribute appreciably to the collector current, at least for properly designed transistors. In general, designing the extrinsic base is very simple: the extrinsic-base area and its associated capacitance and series resistance should all be as small as possible. How this is accomplished depends on the fabrication process used. A major focus in bipolar-technology research and development has been to minimize the parasitic resistance and capacitance associated with the extrinsic base. The interested reader is referred to the vast literature on the subject (Warnock, 1995; Nakamura and Nishizawa, 1995; Asbeck and Nakamura, 2001; and the references therein), and to Appendix 2, which outlines the fabrication process for one of the most widely used modem bipolar transistors. Any adverse effect ofthe extrinsic base on the breakdown voltages ofthe emitter-base and base-oollector diodes should be minimized. This is accomplished by having the dopant distribution of the extrinsic base not extending appreciably into the intrinsic base. If the extrinsic base encroaches appreciably on the intrinsic base, the encroached-on intrinsic-base region will appear to be wider, as well as more heavily doped, than the rest of the intrinsic base. Extrinsic-base encroachment on the intrinsic base, therefore, will lead to a smaller collector current as well as degraded de and ac characteristics (Lu et ai., !987; Li et al., 1987). For an optimally designed bipolar process, extrinsic-base encroachment is usually negligible. As a result, the extrinsic base usually has little effect on the collector current. Therefore, only the design of the intrinsic base will be discussed further in this section. We first consider the design of a Si-base in this section. The design of a SiGe-base is covered in Section 7.4. 7.2.1 Relationship between Base Sheet Resistivity and Collector Current Density As shown in Fig. 6.5, the collector current of a typical bipolar transistor is ideal, i.e., varying as exp(qVmfkT), for VBE less than about 0.9 V. For this ideal region, the saturated collector current density for an n-p-n transistor is given by Eq. (6.33), which is repeated here: leo q fwa pp(x) , dx (7.2) Jo DnB(x)nfeB{X) 7.2 Design of the Base Region 379 where PP' DnB, and nieB are the hole density,. the electron diffusion coefficient, and the effective intrinsic-carrier concentration, respectively, in the p-type base region. The effective intrinsic-carrier concentration is given by Eq. (6.14). It can be used to allow for heavy-doping effect as well as any bandgap-engineering effect by properly adjusting the bandgap-narrowing pararneter tllSg• We shall first consider the case where nieB is used to allow for heavy-doping effect in the base. The case of using nieB to allow for base-bandgap engineering will be covered in Section 7.4. For device design purposes, it is often convenient to assume that both DnB and njeB are slowly varying functions of x and hence can be approximated by some average values. That is, Eq. (7.2) is often written as - -2 Jeo ~ qDnBnieB IoWa pp(x)dx (7.3) At low currents, the hole concentration in the base is equal to the base doping concentra­ tion NH(X), and Eq. (7.3) can be further simplified to Jeo ~ qD-nBn-2ieB IoWa NB(x)dx (7.4) The integral in the denominator of Eq. (7.4) is simply the total integrated base dose. [In the literature, the denominator in Eq. (7.4) is sometimes referred to as the base Gummel number (Gummel, 1961). However, in this book we follow the convention of de Graaff (de Graaft' et al., 1977), where the base Gummel number GB is defined by Eq. (6.34).J Thus, the collector current density at low currents is approximately inversely proportional to the total integrated base dose. Using ion-implantation techniques for doping the intrinsic base, the integrated base dose, and hence the collector current density, can be controlled quite precisely and reproducibly. The sheet resistivity of the intrinsic base, RSbi, is (q lw RShi = a Pp(x) J.tp (x)dx) -·1 (7.5) Again, for device design purposes, it is convenient to assume .an average mobility and rewrite Eq. (7.5) as ~ 1Wa -I RShi (q{lp PP(X)dX) (7.6) Substituting Eq. (7.6) into Eq. (7.3), we obtain Jeo ~ IlDnB{lpii;eBRSbi' (7.7) That is, the collector current density is approximately proportional to the intrinsic-base sheet resistivity. This direct correlation is v~lid for RShi between 500 and 20 x 103 nlO, which is the range of interest in most bipolar device designs (Tang, 1980). 380 7 Bipolar Device Design 7.2.2 Intrinsic-Base Dopant Distribution For a desired intrinsic-base sheet resistivity, the detailed intrinsic-base dopant distribu­ tion depends on the fabrication process used. Most modem bipolar-transistor processes employ ion implantation, followed by thermal annealing and/or thermal diffusion, to form the intrinsic base. In this case, the intrinsic-base doping profile is approximately a Gaussian distribution, often with an exponentially decreasing taiL As will be shown in Section 7.3, the collector doping concentration ofa modem bipolar transistor is relatively high, often in excess of 1 x 1017 em-3. This concentration is usually high compared with the tail of the base dopant distribution. As a result, the lightly doped tail is often clipped offby the collector doping profile and has little effect on the collector current. Therefore, for simplicity of discussion and analysis, we shall ignore the tail of the base dopant distribution. If the Gaussian base dopant distribution peaks at the emitter-base junction located at x = 0, then the base doping concentration can be described by NB{x) = NBmax exp ( - ;;2), (7.8) where (l andNBmax are the standard deviation and peak concentration, respectively, of the distribution. For most bipolar device designs, the peak doping concentration in the base is approximately 10--100 times that in the collector. Here, for purposes of discussion, we assume NBmaxINC 100. This implies a base width of WB R:i 30' (7.9) for the Gaussian base dopant distribution. With the advent of silicon epitaxy processes, instead of implanting dopant ions into silicon, the intrinsic base can be formed by epitaxial growth ofa thin, in situ doped silicon layer on top of the collector. In this case, the base dopant distribution depends on the in situ doping process used. The simplest distribution is an approximately uniform, or boxlike, distribution. Figure 7.2 illustrates a box profiIe ofNB = I x 1018 cm- 3, and a Gaussian profile ofthe same integrated base dose and the same base width. It shows that the peak concentration of the Gaussian profile is more than twice that of the box profile. The emitter-base depletion-layer capacitance ofa Gaussian base doping profile is therefore larger than that of a boxlike base doping profile. Also, with a higher base doping concentration at the emitter-base junction, high-field effects at the emitter-base junction are also more severe for a Gaussian-profile base than for a box-profile base. In general, for the same base width and integrated base dose, a base doping profile with a higher peak concentration, at or close to the emitter-base junction, will lead to a larger emitter-base junction capacitance. However, this does not imply that a box-profile base is necessarily preferred over a base with a peak concentration located at or near the emitter­ base junction, for there are many other factors or parameters, such as base transit time and ease of fabrication, that must also be considered. (A boxlike base doping profile will certainly lead to a larger Early voltage, as will be shown in Section 8.5.1.) Before we 7.2 Design of the Base Region 381 Figure 7.2. ,-..5E+18 B'"I 2E+18 '-' § lE+18 'E SE+17 c 8 0.3Jm•x. For Nc = I x 1016 cm-3, one has Jmax = 0.16mN!JlIl2, and the allowed Jc is only about 0.05 mN!JlIl2, which is much too small for the modem bipolar devices. To increase the collector current density without increasing base-widening effect, Nc must be increased proportionately. However, as Nc is increased, the base-collector junction capacitance is increased, and other device characteristics, such as base-collector junction avalanche, can be adversely affected. Therefore, tradeoffs have to be made in the design of the collector. These design tradeoffs are discussed below. 7.3.1.1 Tradeoff in Early Voltage The Early voltage of a bipolar transistor is inversely proportional to the base-collector junction depletion-layer capacitance per unit area, CdBC [cf. Eq. (6.71)]. As Nc is increased to allow a larger collector current density, CdBe is increased and VA will decrease. Therefore, there is a tradeoffbetween the current-density capability ofa transistor and its Early voltage. 7.3.1.2 Tradeoff in Base-Collector Junction Avalanche Effect As discussed in Section 6.3.2, base-collectorfunction avalanche occurs when the electric field in the junction space-charge region becomes too large. Excessive base-collector junction avalanche can cause the base and collector currents to increase out ofcontrol and hence can affect the functionality of the circuits using these transistors. Indeed, when base--collector junction avalanche runs away, device breakdown occurs. Bipolar circuits typically operate with a power supply voltage of 3.3 or 5 V. These voltages are suffi­ ciently high that significant base-collector junction avalanche can easily occur unless care has been taken in the collector design to minimize it (Lu and Cheri, 1989). There are several ways to reduce avalanche multiplication in the base-collector junction. The most straightforward way is to reduce Nc, but that will proportionately reduce the allowed collector current density. Alternatively, the base andlor the collector 388 7 Bipolar Device Design 7.3.2 doping profiles, at or near the base~onector junction, can be designed to reduce the electric field in the junction. Referring to Fig. 7.2, the Gaussian base doping profile, with its graded dopant distribution near the base-collector junction, has a lower electric field in the base­ collector junction than the boxlike base doping profile. In practice, ion implantation of boron usually results in an exponential tail in the base doping profile, as can be seen from Fig. 6.2. This tail is caused by a combination ofchanneling effect during ion implantation and defect-induced enhanced-diffusion effect during postimplantation thermal anneal­ ing. The ion-implanted base profile is therefore always graded. Ifthe intrinsic base is formed by epitaxial growth and is doped in situ, its doping profile can be much more boxlike. For the same collector doping profile, such a base doping profile will result in a larger electric field in the base-c<.>lIector junction. However, this does not imply that a graded base doping profile is preferred over a boxlike profile. This point will be discussed further in Chapter 8 in connection with the optimization of a device design. The collector doping profile can also be retrograded (i.e., graded with its concentration increasing with distance into the silicon) to reduce the electric field in the base-collector junction (Lee et al., 1996). Retrograding of the collector doping profile can be achieved readily by high-energy ion implantation. The transistor doping profiles illustrated in Fig. 6.2 show collectors with retrograded doping profiles. Qualitatively, grading the base doping profile, andlor retrograding the collector doping profile, is similar to sandwiching an i-layer between the base and collector doped regions. Introducing a thin i-layer between the p- and n-regions of a diode is quite effective in reducing the electric field in the junction, as discussed in Section 2.2.2. Reducing bas~ollector junction avalanche, either by reducing the collector doping concentration or by grading the base doping profile andlor retrograding the collector doping profile, reduces the bas~ollector junction depletion-layer capacitance as well. This should help to improve the device and circuit performance (Lee et al., 1996). However, as can be seen from Eqs. (6.8J) and (6.82), these techniques for reducing the bas~ollector junction capacitance also lead to more base widening, or to base widening occurring at a lower collector current density. Thus, reducing bas~ollector junction avalanche can reduce the current-density capability, and hence the maximum speed, of a bipolar transistor (Lu and Chen, 1989). The tradeoff between base-collector junction avalanche effect and device and circuit speed will be discussed further in Chapter 8. Collector Design When There Is Appreciable Base Widening As mentioned earlier, the operating currcnt densities ofa modem bipolar transistor could easily be in excess of 1mA/l1m2, if base-widening effect were not a concern. Unfortunately, at these high current densities, base widening does occur. The challenge in designing the collector when base widening is unavoidable is to minimize the deleterious effects of base widening. As shown in Section 6.3.3, when base widening occurs, there are excess minority carriers stored in the collector, and, as shown in Section 6.4.4, these excess minority 7.4 SiGe-Base Bipolar Transistors 389 carriers contribute to the emitter diffusion capacitance. As will be shown in Chapter 8, when a bipolar transistor is operated with significant base widening, it is its emitter diffusion capacitance that limitS its circuit speed and cutoff frequency. To minimize emitter diffusion capacitance, the total excess minority carriers stored in the collector should be minimized. To accomplish this goal, in addition to retrograding the collector doping profile as discussed in the previous subsection, the total collector volume avail­ able for minority-carrier storage should also be minimized. That is, the thickness of the collector layer should be minimized. This is easily accomplished by reducing the thickness of the epitaxial layer grown after the subcollector region is formed (see Appendix 2). However, thinning the collector can lead to an increase in the bas~ollector junction depletion-layer capacitance, ifthe collector thickness is comparable to the bas~ollector depletion-layer width. Thus, when operated at low current densities, where base widen­ ing is negligible, a circuit using thin-collector transistors could run slower than a circuit using thick-collector transistors. However, at high current densities, circuits with thin­ collector transistors often run faster than circuits with thick-collector transistors (Tang et al., 1983). Also, when the collector-base space-charge layer extends all the way to the subcollector, base--collector junction avalanche will increase, and the base-collector junction breakdown voltage will decrease. Designing the collector of a modem bipolar transistor is therefore a complex tradeoff process. The important point to remember is that base widening occurs readily in modern bipolar devices, and optimizing the tradeoffin the collector design is key to realizing the maximum performance ofthese devices. 7.4 SiGe-Base Bipolar Transistors The energy bandgap ofGe (:::: 0.66 eV) is significantly smaller than that ofSi ("" 1.12 eV). By incorporating Ge into the base region ofa Si bipolar transistor, the energy bandgap of the base region, and hence the accompanied device characteristics, can be modified (Iyer et at., 1987). When Ge is incorporated fnto Si, the Si energy bandgap becomes smaller primarily owing to shifting of the valence band edge (People, 1986; Van de Walle and Martin, 1986). The larger the Ge concentration the smaller the energy bandgap. A SiGe­ base bipolar transistor is usually designed to have a graded Ge distribution in the base, i.e. with lower Ge concentration at the emitter end and larger Ge concentration at the collector end, in order to establish a drift field which drives electrons across the quasi­ neutral base layer (Patton et al., 1990; Harame et al., I995a, b). The emitter, of a typical SiGe~base bipolar transistor is the same as that of a regular Si-base bipolar transistor. In both transistors, it is simply a polysilicon emitter. As for the Ge distribution in the base, several variations of a graded Ge profile have been studied. The most commonly used profile is that ofa triangular or linearly graded Ge distribution. This profile assumes a Ge distribution which is zero at the emitter end of the quasineutral base and increases at a constant rate across the base layer. Ifleads to a simple graded base bandgap that decreases linearly from the emitter end to the collector end. 390 7 Bipolar Device Design 7.4.1 In a SiGe-base bipolar device fabrication process, Ge is incorporated into a starting base layer prior to the polysilicon-emitter formation step. Depending on the details ofthe base and emitter formation steps, Ge mayor may not end up in the single-crystalline region of the emitter. Once Ge ends up in the single-crystalline portion of the emitter, the Ge profile within the quasineutral base can become quite complex. In particular, the Ge distribution at the emitter end of the quasineutral base will depend on the depth of the single-crystalline emitter region. Therefore, a trapezoidal Ge profile, with a low but finite Ge concentration near the emitter end and a higher Ge concentration at the collector end, gives a more general description of the Ge distribution in a typical SiGe-base transistor. A SiGe-base transistor having a trapezoidal Ge distribution in its base can be modeled with close-form solutions. Furthermore, a triangular Ge profile and a constant-Ge profile can be treated as special cases of a trapezoidal profile. In Section 7.4.1, the properties of a polysilicon-emitter SiGe-base transistor having a linearly graded base bandgap, corresponding to a simple triangular Ge profile, are discussed and compared to those of a polysilicon-emitter Si-base transistor. A triangular profile describes very well the basic properties of a typical polysilicon-emitter SiGe-base bipolar transistor. For readers who desire only a first-order explanation of the difference between a SiGe-base transistor and a Si-base transistor, this simple description should be adequate. In the remaining sections, the properties of a SiGe-base bipolar transistor having a trapezoidal Ge distribution in the base are discussed in greater depth. These sections are intended for those readers interested in understanding the more subtle properties of a SiGe-base bipolar transistor. The models developed in these sections can also be used for optimizing the Ge distribution, beyond the simple triangular distribution, for improved device characteristics. The presence ofGe in the emitter changes the properties ofthe emitter region, which in tum can change the base current characteristics. The effect on base current due to the presence ofGe in the emitter is considered in Section 7.4.2. The collector current, Early voltage and base transit time are modeled in Section 7.4.3 for a transistor having a trapezoidal Ge distribution, and in Section 7.4.4 for a transistor having a constant Ge distribution. For a given device fabrication process, there is always a distribution in emitter depth and base width caused by process variation. A methodology for evaluating the effect of emitter depth variation on device characteristics is developed in Section 7.4.5. The results are then applied to the optimization of a Ge profile in Section 7.4.6. There are also subtle but interesting effects in a SiGe-base transistor that are either absent or relatively unimportant in a Si-base transistor. They are discussed in Sections 7.4.7 and 7.4.8. Finally, Section 7.4.9 is devoted to a discussion of the heterojunction nature of a SiGe-base bipolar tr.msistor, contrasting a SiGe-base transistor with a traditional wide-gap-emitter heterojunction bipolar transistor (HBT). Transistors Having a Simple Linearly Graded Base Bandgap It is shown in Appendix 17 that a simple triangular Ge distribution in th~ base of a Si­ SiGe n+-p diode produces a bandgap grading in the base such that the valence-band edge 7.4 SiGe-Base Bipolar Transistors 391 Emitter Base Collector WithGe Ec pSi or SiGe ~n~ +Si / ~" ~ nSi ~_ _ Ev Concentration Figure 1.5. ______ __ ______ ~~~~ ~ ~x o Schematic illustration of the energy bands of a SiOe-base n-p-n transistor (dotted) and a Si-base n-p-n transistor (solid). Both transistors are assumed to have the same base doping profile. The base bandgaps of the two transistors are the same near the base-emitter junction. The base bandgap of the SiOe-base transistor narrows gradually towards the base­ collector junction. in the base is essentially spatially constant, while the conduction-band edge has Ii downward slope towards the p-type SiGe contact, i.e. Ec decreases with distance x from the emitter-base junction. As a result, the energy-band diagram for a SiGe-base bipolar transistor having a triangular Ge distribution in the base is as illustrated in Fig. 7.5. As shown in Section 6.2.2, the base current is determined by the emitter para­ meters only, and is independent of the base parameters. A SiGe-base bipolar transis­ tor typically has the same polysilicon emitter as a Si-base transistor. Also, it is shown in Appendix 17 that the presence of Ge in the base does not change the energy barrier for hole injection from the base into the emitter. Therefore, the base current of a SiGe-base transistor should be the same as that of a Si-base transistor. This is indeed the case for most SiGe-base transistors. (Even when Ge ends up in the single­ crystalline emitter region, the effect on base current is still small, as will be explained in Section 7.4.2.) Since base current is not affected by the presence ofGe in the base, we need to consider only the effect of Ge in the base on collector current. The base bandgap-narrowing parameter in Eq. (7 J I) can be extended to include bandgap narrowing caused by the presence ofGe. That is, the effective intrinsic-carrier concentration in the base containing Ge can be written in the form (Kroemer, 1985) ni2eB (S.IGe,x) = ni2eD(S.l, x)')'(x) exp [LlEgBk,STiG(!(X)] ' (7.26) where nleB(Si, x) is the effective intrinsic-carrier concentration without Ge, I!.EgB.SiGAX) is the local bandgap narrowing in the base due to the presence of Ge, and the parameter 392 7 Bipolar Device Design (NcNv)SiGe (NcNv)Si (7.27) is introduced to account for any change in the density of states caused by the presenCe of Ge (Harame et al., 1995a,b). Effects due to heavy doping are contained in the parameter nteB<:Si, x). In addition to reducing the bandgap energy; the incorporation of Ge into Si also lifts the degeneracy of the valence-band and conduction-band edges (People, 1985). The result is a reduction in the densities ofstates Nc and Nv. That is, y(x) < 1 except where the Ge concentration i~ zero. For the Ge distribution being considered here, the Ge­ induced bandgap narrowing is zero at the emitter-base junction and increases linearly to Mgmax at the base-collector junction: .x flEgB,SiG.(X) = Ws flEg max' (7.28) 7.4.1.1 Collector Current and Current Gain The collector current density in a SiGe-base transistor can be obtained simply by substituting nieB(SiGe, x) for n;eB<:Si, x) and DnB(SiGe, x) for Dnn(Si, x) in the equations derived earlier for the collector current density in a Si-base transistor. Thus, the saturated collector current density given in Eq. (6.33) becomes Jco(SiGe) W. q( ) 1 Pp x dx o DnB(SiGe, x)n;B(SiGe, x) (7.29) For a boxlike base doping profile and at low current densities, pp(x) '" No and is independent of x. Dno(Si, x) and nieo(Si, x) are also independent of x. Therefore, Eqs. (7.26) and (7.29) give the ratio of the collector current with Ge to that without Ge as Jco(SiGe) _ Wo Jco(Si) - fWB I exp [-flEgB.siGe(x)/kTj dx .0 Y(X)17(X\ PiWB ~ Ws ' 10 exp[-t..EgB,SiGe(x)/kTj dx (7.30) where the ratio parameter _ DnB(SiGe, x) = DnB(Si,x) (7.31) accounts for the effect of Ge on electron mobility in the base. DnB<:SiGe) is proportional to ,unB<:SiGe) which is found to be a function of both base doping concentration and Ge concentration (Kay and Tang, 1991). Therefore, ,,(x) is a function of base doping 7.4 SiGe-Base Bipolar Transistors 393 concentration and Ge concentration as well. In writing the last part ofEq. (7.30), we have made an assumption that y(x)and 17(x)jnside the integral can be replaced by some average values ji and ii. It should be noted that Eq. (7.30) is valid for any arbitrary dependence of /!;EgB.SiG,(X) on x. For the simple linearly graded bandgap described by Eq. (7.28), Eq. (7.30) can be integrated to give Jco(SiGe) YfiflEg max/kT Jco(Si) 1 - exp(-flEg max/kT) . (7.32) The value of y(x) varies between 1 where there is no Ge to about 0.4 where the Ge concentration is 20% (Prinz et ai., 1989). For a typical SiGe base where the base doping concentration is in excess of I x lOIS cm-3, l'J(x) is about unity (Kay and Tang, 1991; Manku and Nathan, 1992). Therefore, the product YI'J is not far from unity. In the literature, the corrections to density of states and to electron mobility are often ignpred in discussing the effect of Ge on collector current, which is equivalent to setting Y11 to unity in Eq. (7.32). Equation (7.32) is the well-known result for a simple triangular Ge distribution (Hararne et al., 1995a, b). As discussed earlier, the base current of a SiGe-base transistor is the same as that ofa Si-base transistor. The current gain ratio is therefore the same as the collector current ratio, namely fJo(SiGe) _ Jco(SiGe) YI'Jt..Eg max/kT fJo(Si) - Jco(Si) I - exp(-flEg max/kT) . (7.33) Readily achievable values of Mgmax are in the range of 100-150 meV, which means a SiGe-base transistor typically has a collector current and current gain that are 4 to 6 times those of a Si-base transistor having the same base dopant distribution. As shown in Eq. (7.7), the collector current density, and hence the current gain, is proportional to the intrinsic-base sheet resistivity. The enhanced current gain of a SiGe-base transistor can be used to tradeoff for a smaller intrinsic-base sheet resistivity. The resultant smaller intrinsic-base sheet resistivity increases Early voltage as well [cf. Eq. (6.73»). 7.4.1.2 Early Voltage The effect ofbase-bandgap grading on Early voltage can be obtained from Eq. (6.73) in a similar manner by replacing nieB<:Si, x) by ni,B(SiGe, x) and DnB<:Si, x) by DnB<:SiGe, x). The result is VA (SiGe) _ qDnB(SiGe,WB)nTeo(SiGe,Wo) lWD _ No (x) d - CdBC 0 DnB(SiGe,x)nreB(SiGe, x) x, (7.34) where CdBC is the base-collector junction depletion-layer capacitance per unit area. Using Eq. (6.72) for YA(Si) and substituting Eqs. (7.26) and (7.27) into Eq. (7.34) we obtain the ratio ofthe Early voltage ofa SiGe-base transistor to that ofa Si-base transistor having the same boxlike boron distribution in the base as 394 7 Bipolar Device Design VA (SiGe) VA(Si) DnB(SiGe, WB)n~B(SiGe, WB) JWB . dx WB 0 DnB(SiGe,x}n7eB(SiGe,x) ~ DnB(SiGe, WB) y( WB) exp(L\Eg max/kT) lWD exp[-llEgB,SiGe(x)/kT]dx ~ DnB{SiGe) Y WB 0 ~ exp (L\Eg·maxkT) JWD exp[-L\EgS,SiGe(x)/kT]dx, WB 0 (7.35) where, in writing the last part of the equation, we have made a further assumption that the average values ofDna and y are about the same as their values at the base-collector junction. It should be noted that Eq. (7.35) is valid for any arbitrary dependence of MgB.SiOlx) on x. For the simple linearly graded base bandgap described by Eq. (7.28), Eq. (7.35) can be integrated to give VASiGe) VA (Si) kT L\Eg max [exp(L\Eg rnax/kT) - 1]. (7.36) Equation (7.36) is the well-known result for a simple triangular Oe distribution (Harame et al., 1995a). It shows that the Early voltage increases approximately exponentially with Mgmax.1kT when MgmaxlkT > I. For a typical value of Mgrnax = 100 meV, the Early voltage is increased by a factor of 12 at room temperature. Combining Eqs. (7.33) and (7.36), the ratio of130VA for a SiOe-base transistor to that for a Si-base transistor is 130 (SiGe) VA (SiGe) 130 (SI) VASi) _ Y'l exp (L\Eg maxkT). (7.37) The same result could have been obtained from Eq. (6.74) by using Eq. (7.26) for nieaCSiOe,Ws). Again, in the literature, the product Y'1 is often assumed to be unity and dropped. For Mgmax 100 meV, the 130VA product is increased by almost a factor of50 at room temperature. 7.4.1.3 Base Transit Time The graded base bandgap introduces an electric field which drives electrons across the p-type base layer. For a total bandgap narrowing of lOOmeV across a base layer of 100 nm, a SiOe-base transistor has a built-in electric field of 104 V/cm in the base due to the presence ofOe alone. This field is in addition to the electric fields due to base dopant distribution and heavy-doping effect, which have been discussed earlier in Section 7.2.3. As can be seen from comparing this field with the fields plotted in Fig. 7.3, the electric field due to the presence of a graded Ge distribution can be comparable to the maximum fields due to dopant distribution and heavy-doping effect. Consequently, the base transit time ofa SiOe-base transistor can be significantly smaller than that of a Si-base transistor having the same base dopant distribution. The base transit time at low current densities 7.4 SiGe-8ase Bipolar Transistors 395 can be derived by substituting nieaCSi, x) with nieB(SiOe, x) and DnaCSi, x) with DnaCSiGe, x) in Eq. (7.22). The result is lB(SiGe} ~lWBn~B(SiGe'X)JWB NB(x') dx'rLr: o NB(X) x DnB(SiGe, x')n7es{SiGe, x) 7 - - jWB 0 Y(X)nNseB(x(S) i,x) e x p [LAl EgS,SI.Ge (X) / k T j WB X N8(x') Jx y(x'Mx)DnB(Si, x')n7es(Si, x) exp[-L\EgB,SiGe(x'l/kT]dx'dx. (7.38) Again, for a boxlike base dopant distribution, NB(x), DnB(Si, x), and nieB(Si, x) are all independent of x, and Eq. (7.38) simplifies to IB(SiGe) ~" 1 Ie>:\ jWB 0 , exp[L\EgB,siGe(xl/kTJ WD fX .< exp[ -L\EgB,SiGe(X')/kT]dx'dx, (7.39) where, consistent with the approximations made earlier for collector current and Early voltage, we have made the assumption that rex) and 'lex) are relatively slow varying functions ofx and hence can be replaced by their average values )i and ii. The base transit time for a Si-base transistor is tB(Si) = W1/2Dn(Si), given in Eq. (7.24). Therefore, the ratio ofthe base transit time of a SiOe-base transistor to that ofa Si-base transistor having the same base width and boxlike base dopant distribution is t8(SiGe) 2 ts(Si) =iTW~ exp [L\EgS.SiGe(x)/kT) WD J X x exp [-L\EgS,SiGe(x')/kT] dx'dx. (7.40) Equation (7.40) is valid fQr any arbitrary dependence of L\EgS,SiGe(X) on x. For the simple linearly graded base bandgap described by Eq. (7.28), Eq. (7.40) can be integrated to give tB(SiGe) 2kT { ts{Si) = 'lflEg max I kT L\Eg max [I exp( -flEg }. (7.41) Again, in the literature, the diffusion coefficient correction factor 'i is often set to unity and dropped. For Mgm.x == 100 meV, the low-current base transit time of a SiOe-base transistor is about 2.5 times smaller than that ofa Si-base transistor having the same base width and base dopant distribution. Equation (7.41) is the well-known result for a simple triangular Ge distribution (Harame et al., 1995a, b). 396 7 Bipolar Device Design s J§ ~ 1 ~ Cii Figure 7.6. 2 4 6 8 10 tlEgmaxlkT Relative improvement factors for current gain, Early voltage, and base transit time of a SiGe-base bipolar transistor over a Si-base bipolar transistor, as a function of the maximum base bandgap narrowing. A linearly graded Ge profile is assumed. Also, ji and ii are set to unity. 7.4.1.4 Emitter Delay Time It will be shown in Chapter 8 that the cutoff frequency IT of a bipolar transistor is limited by the forward transit time 'F of which the emitter delay time 'E is one of the 'E components. It will also be shown in Chapter 8 [see Eq. (8.16)] that is inversely proportional to the current gain. Thus, with a significantly larger current gain, a SiGe­ base transistor has a much smaller emitter delay time than a Si-base transistor of the same emitter design. 7.4.1.5 SiGe-Base Bipolar as a High-Frequency Transistor It will be shown in Chapter 8 that some of the desirable attributes ofa high-frequency bipolar transistor are: small transit times, small base resistance, and large output resis­ tance or Early voltage. Figure 7.6 is a plot of the improvement factors for current gain [Eq. (7.33)], Early voltage [Eq. (7.36)], and base transit time [Eq. (7.41)], ofa SiGe-base bipolar transistor relative to a Si-base bipolar transistor having the same base width and base dopant distribution, plotted as a function of Mgmax1kT using y = I and r; = I. It shows that incorporating a linearly graded Ge distribution into the base of a bipolar transistor can greatly improve its current gain, Early voltage, and base transit time. As discussed in the previous subsection, the larger current gain also implies a smaller emitter delay time. Alternatively, the larger current gain can be traded off for a smaller intrinsic­ base resistance. Thus, compared to a Si-base bipolar transistor, a SiGe-base bipolar transistor is much superior in frequency performance. 7.4.2 Base Current When Ge Is Present in the Emitter Polysilicon emitter is employed in the fabrication of all modem .silicon bipolar transis­ tors, including SiGe-base transistors. In the fabrication of a SiGe-base transistor, 7.4 SlGe-Base Bipolar Transistors 397 typically a p-type base layer containing the desired Ge distribution is first formed before an n+ emitter polysilico£! laxer is formed on top. There is usually a Ge-free cap in the starting base layer to avoid exposing Ge to any oxidizing ambient in the polysilicon-emitter formation process. During the polysilicon-emitter formation pro­ cess, n-type dopant from the polysilicon layer diffuses into the starting base layer, forming a thin single-crystalline n+ emitter region of depth XjE (see Section 7.1.2 and Fig. 6.2). The final value of XjE is a function of emitter annealing condition (tem­ perature and time), emitter dopant species (arsenic or phosphorus), emitter stripe width, and whether or not metal silicide is formed on top of the emitter polysilicon layer (Kondo et al., 2001). Depending on the thickness of the starting Ge-free cap, the final emitter-base junction mayor may not extend into the Ge-containing region of the base, and hence Ge mayor may not be present in the single-crystalline emitter region. Since any change in the emitter parameters can affect the base current, we want to consider what happens to the base current of a polysilicon-emitter SiGe-base bipolar transistor when Ge from the starting base layer ends up in the single-crystalline emitter region. In the literature,· there are reports of intentionally introducing Ge into the single­ crystalline emitter region (Huizing et aI., 2001) as well as intentionally adding Ge to the emitter polysilicon layer (Martinet et al., 2002; Kunz et al., 2002; Kunz et al., 2003). Often the stated objectives are to reduce current gain ofa SiGe-base transistor. The merits of these and other approaches for reducing current gain ofa SiGe-base transistor will also be discussed. 7.4.2.1 Ge-Induced Bandgap Narrowing in the Emitter The Ge distribution in the emitter and base regions of a polysilicon-emitter SiGe-base bipolar transistor having a boxlike base dopant distribution is illustrated in Fig. 7.7 for the case ofa trapezoidal Ge distribution. The Ge distribution causes a bandgap narrowing of MgO near the emitter-base junction and a peak bandgap narrowing of Mgmax at the base-collector junction. For the case iIlw;trated in Fig. 7.7, the emitter depth XjE is larger than the starting Ge-free cap thickness, Wcap, resulting in a bandgap narrowing of MgOhe > MgO at the emitter-base junction. There is also Ge present within the single­ crystalline emitter region, causing a narrowing of the bandgap in the region. Since base current is determined by the emitter parameters, the Ge-induced bandgap variation in the emitter affects the base current. In the next s~bsection, we examine the base current when there is Ge in the emitter (Ning, 2003a). 7.4.2.2 Base Current When There Is Ge in the Single-Crystalline Emitter Region It is shown in Section 6.2.2 that a polysilicon emitter can be modeled as a shallow or transparent emitter having a finite surface recombination velocity at the eniitter contact, i.e., at the polysilicon-silicon interface. Consistent with the convention used in Section 6.2.2, Fig. 7.8 shows the coordinates for modeling the current flows in the emitter region of the emitter-base diode of Fig. 7.7. The p-n junction is assumed to be located at the origin "0". The emitter is contacted by a polysilicon layer, with the polysilicon-silicon interface located at x -WE, i.e., WE XjE' 398 7 Bipolar Device Design M"gmax XjE -8 ~ n+ ,,,, ,F 'Ge ~,,I 1 i: 6 ----r- _.... -~, I.:..._.~........".-.-.-.---..4.'~....... M"gO p o x FigUlll7.7. ---1 i-- wcap Schematic illustrating the emitter and base regions of a polysilicon-emitter SiGe-base bipolar transistor with a trapezoidal Ge distribution. The starting base layer thickness is WBO, including a Ge-free cap layer of thickness Weap. The quasineutral base width is WB after polysilicon·emitter drive in. The base width is a function of emitter depth XjE, given by WB = WEO - XjE' The emitter-base space·charge region thickness is assumed to be zero, for simplicity of illustration. With XjE > Weap' there is no residual Ge-free region in the final quasineutral base layer, but there is Ge in the single-crystalline n+ emitter region. Figure 7.8. II/ 1\ Ge XjE /I I \ .g ~ "~ 6 8'"­ ~ ~ .~ ::E + " I" yBI\I I p I I I \ I I I I '--1--_" X -WE 0 W8 Coordinates for modeling the current flows in the emitter ofa polysilicon-emitter SiGe-hase bipolar transistor. Following Eqs. (6.43) and (6.44), the saturated base current density in a SiGe-base bipolar transistor can be written as qn; JBO(SiGe) = GE(SiGe)' (7.42) with the emitter Oummel number as 7.4 SiGe-Base Bipolar Transistors 399 GE(SiGe) ro n; Ni:(x')'- dx n7 LwEnTeE(SiGe, x) DpE(SiGe,x) + n~E(SiGe, NE("'-WE) WE) Sp(SiGe) , (7.43) where Sp(SiGe) is the surface recombination velocity for holes at the polysilicon-silicon interface, and Ne(x), Dpe(SiGe, x), and niez,{SiOe, x) an: the doping concentration, hole diffusion coefficient, and effective intrinsic-carrier concentration, respectively, in the single-crystalline emitter region. The surface recombination velocity Sp(SiOe) depends on the transport of holes through the polysilicon-silicon interface and inside the poly­ silicon layer. For example, it is shown in Ex. 6.3 and in the literature (Ning and Isaac, 1980) that for a Si-base bipolar transistor Sp(Si) depends only on the transport of holes inside the polysilicon layer when there is no appreciable hole barrier at the polysilicon­ silicon interface. In this simple case, Sp(Si) is given by Sp(Si) = DpE,poly__ , L pE,po/y tanh ( -WLE,p-o­IY) pE,poly (7.44) where DpE,poly and LpE,poly are the hole diffusion coefficient and hole diffusion length, respectively, in the emitter polysilicon, and WE,poly is the thickness of the emitter polysilicon layer. It should be noted that regardless of the details of the physical model for Sp, the operation of a polysilicon-emitter transistor is based on the experimentally confirmed fact that the hole current is determined primarily by the surface recombination velocity of holes at the polysilicon-silicon interface and is relatively insensitive to the transport of holes within the shallow single-crystalline emitter region. That is, the operation of a polysilicon-emitter transistor is based on the assumption that GE is detennined primarily by the term containing Sp in Eq. (7.43). In other words, for a polysilicon-emitter SiGe­ base bipolar transistor, Ge(SiGe)i'::! .nfNE(-WE) . . nteE(SlGe, - WE)Sp(SlGe) (7.45) Following the same procedure used in Section 7.4.1 to model the SiOe base regi(?n;' we can write the emitter parameter niee(SiGe, x) in the form [f1.E nteE(SiGe, x) = n7eE(Si,x)Ydx) exp gEk,STiG'e(X)] , (7.46) where nieE{Si, x) is the effective intrinsic-carrier concentration without Oe and MgE.Sic;e(X) is the local bandgap narrowing due to the presence of Oe. Also, the parameter (NcN')SiGe l'E(X) (NcNY)Si (7.47) is to account for any change in the densities ofstates in the emitter due to the presence ofGe. Effects due to heavy doping are contained in the parameter nieE!"Si, x): From Eqs. (7.4z), 400 7 Bipolar Device Design (7.45) and (7.46) we can write the ratio of the base current of a polysilicon-emitter SiGe-base bipolar transistor to that of a polysilicon-emitter Si-base bipolar transistor as (Ning, 2003a) Jeo(SiGe) ... ~ Sp(SiGe) ... " )'E(-WE)exp[ll..EgE,SiGe(-WE)/kTJ' (7.48) 7.4.2.3 7.4.2.4 As discussed earlier, there is a Ge-free cap in the starting base layer prior to the emitter formation steps. That is, the Ge concentration is zero at or near the poly­ silicon-silicon interface. Therefore, IlEgE.SiGe(-WE) =0 and )lEC-WE)=1 for a typical polysilicon-emitter SiGe-base transistor. Furthermore, we expect Sp(Si) :;-;: Sp(SiGe) in this case because there is no Ge at or near the interface and there is no Ge inside the emitter polysilicon layer. Equation (7.48) then suggests that, for a typical polysilicon-emitter SiGe-base bipolar transistor, the base current should be insensi­ tive to the Ge distribution in the starting base layer, even when Ge ends up inside the single-crystalline region of the emitter. This explains why the measured base current of a polysilicon-emitter SiGe-base transistor and that of a polysiJicon-emitter Si-base control are approximately the same (Prinz and Sturm, 1990; Harame et al., 1995a, b; Oda et al., 1997). Non-Transparent "Polysilicon Emitter" In an attempt to reduce or control the current gain in a SiGe-base bipolar transistor, sometimes designers intentionally introduce a thin Ge-containing layer within the single­ crystalline emitter region of a polysilicon-emitter SiGe-base bipolar transistor (Huizing et at., 200 I). In this case, the thin Ge-containing layer creates a local potential well for holes, causing a significant increase in Auger recombination of electrons and holes within the single-crystalline emitter region. It results in a significant increase in base current For such a transistor, even though a polysilicon layer is used to form a "poly­ silicon emitter," the single-crystalline part ofthe emitter is not transparent because ofthe large recombination in it. As a result, the conventional transparent-emitter model described in Section 6.2.2 for a polysilicon emitter does not apply. That is, Eqs. (7.43) and (7.45), which are derived based on the assumption that the single-crystalline emitter region is transparent, are no longer valid. Instead, the base current should be evaluated from Eqs. (6.35) and (6.36). Reducing current gain leads to an increase in emitter delay time [see Eq. (8.16»). Thus far, there is no reported data suggesting that adding a high-recombination region within the single-crystalline cmitter region, or using any similar techniques for reducing current gain, will lead to a transistor of better performance. As a result, such non-transparent "polysilicon-emitter" devices will not be discussed any further. Polycrystalline Silicon-Germanium Emitter In some studies (Martinet et at., 2002; Kunz et a/., 2002; Kunz et al., 2003), polycrystal­ line silicon-germanium (polySiGe) instead ofpolysilicon i~ used to form the emitter in an attempt to reduce current gain in a SiGe-base bipolar transistor. The energy bandgap of a polySiGe layer is smaller than that of a polysilicon layer. The reduced bandgap increases 7.4 SiGe-Base Bipolar Transistors 401 the injection of holes from the base into the polySiGe emitter region. In addition, the value of Sp for a polySiGeemjtteL 9.~)Uld be quite different from that for a polysilicon emitter. As discussed in Section 7.1, the polysilicon emitter was developed to ov.ercome the limitation of the diffused emitter. The polysilicon emitter enables the scaling of bipolar transistors to base widths of less than 100 nm. Thin-base bipolar transistors using diffused emitters have excessively large and varying base currents, causing current gains to be too small and to have large variations. Thin-base transistors using polysilicon emitters do not have such problems. SiGe-base transistor designers often want to reduce current gain as a means to increase BVCEO [cf. Eq. (6.152)]. Using thepolySiGe emitter in place ofthe polysilicon emitter indeed leads to an increase in base current, hence smaller current gain and somewhat larger BVCEO. . However, as pointed out in Section 6.2.3, it is important to recognize that current gain can be changed by changing the collector current, the base current, or both. Also, it is important to note that, compared to a Si-base bipolar transistor, the larger current gain in a polysilicon-emitter SiGe-base bipolar transistor is due entirely to an increase in the collector current, and not to any significant change in the base current. It will be shown in Section 7.4.6 that it is possible to reduce collector current, and hence current gain, of a SiGe-base transistor without affecting its transit time advantage over a Si-base transistor. This is accomplished by optimizing the Ge profile in the base. Another effective approach to reduce collector current and current gain ofa transistor is to reduce its intrinsic-base sheet resistivity [cf. Eq. (7.7)]. It will be shown in Chapter 8 that reducing base resistance leads to improved .device and circuit performance. Therefore, if a smaller current gain is desired, a device designer should consider reducing the intrinsic-base sheet resistivity of the transistor. This can be accomplished easily by increasing the base doping concentration. As pointed out earlier, reducing current gain leads to an increase in emitter delay time. Furthermore, there is no theory or experimental results to suggest that replacing a polysilicon emitter with a polySiGe emitter will lead to improved device speed. Therefore, we will not consider the polySiGe emitter any further. 7.4.3 Tninsistors Havivg aTrapezoidal Ge Distribution in the Base Various Ge profiles have been analyzed and/or tested out experimentally by various groups (e.g., see Cressleret al., 1993a, Harame et at., 1995a,b, and Washio et al., 2002). Here we focus on the trapezoidal Ge profile illustrated in Fig. 7.7 because close-form . equations for the various transistor parameters can be readily obtained for it. The close­ form equations enable us to discuss more clearly the device physics and operation, as well as device design optimization. Besides, a trapezoidal profile is more general than the simple triangular profile dis~ussed in Section 7.4.1. Even though a simple triangular Ge distribution may be the design target, the Ge profile in the quasineutral base at the end of the fabrication process is often more like a trapezoid than a triangle. For instance, if the Ge concentration is ramped down a bit 402 7 Bipolar Device Design more slowly than intended during device fabrication, some Ge can be present in the cap region which is intended to be Ge-free. When that happens, the emitter-base junction will be located at a point where the Ge concentration is finite instead of zero. The. resultant Ge distribution in the quasineutral base will have a trapezoidal profile instead of a triangular profile. In this case, a model for a trapezoidal Ge profile gives a more accurate description ofthe SiGe-base transistor than a model for a simple triangular Ge profile. As illustrated in 7.7, for a given Ge distribution in the starting base layer of thickness WBO' which includes a Ge-free cap layer of thickness Wcap, the quasineutral base width WB is a function ofthe emitter depth XjE' namely WBO - XjE' (Note that x == WBO is the location of the collector end of the quasineutral base and x = XjE is the emitter end of the quasineutral base. Whether the value of WBO changes or not duririg device fabrication, the width of the quasineutral base is always given by WB == Woo XjE. For modern polysilicon-emitter SiGe-base transistors fabricated using emitter formation processes of low thermal budgets, WBO usually changes less than XjE during the device fabrication process.) Figure 7.7 depicts the case of XjE > W cap, which means there is no residual Ge-free region in the final base layer. If we have XjE < Wcap instead, the final base layer would contain a residual Ge-free cap of thickness Wcap - XjE' Here we want to extend the SiGe­ base bipolar transistor model to include emitter depth as a parameter. With emitter depth included, the model can be used to evaluate the effect of emitter depth on device characteristics. We shall consider both the case ofXjE > Wcap and the case ofXjE < W cap' 7.4.3.1 Collector Current for a Trapezoidal Ge Distribution The ratio of the collector current of a SiGe-base transistor to that of a Si-base transistor with the same boxlike base dopant distribution is given by Eq. (7.30). It can easily be adapted to include the effect of emitter depth by noting that the quasineutral base statts at x = XjE and ends at x = WBO' From Eq. (7.30), we can write the collector current ratio as a function of emitter depth as Jco(SiGe,xjE) Jco(Si,XjE) ~ ~ Jxw/' m(WBO XjE) exp [-t.EgB,SiGe(x)/kT] dx . (7.49) • Case afGe in the emitter (i.e.,XjE > Wcap). This is the situation depicted in Fig. 7.7. The Ge distribution in the quasineutral base has a simple trapezoidal profile, with a base bandgap narrowing of l:J.EgObe at the emitter end of the base given by t.EgObe(XjE) = t.EgO + (~E _ ~ap) (t.Egmax t.E'gn). DO cap (7.50) The base bandgap narrowing as a function of position in the base is given by = t.EgB,SiGe(X) UE..Obel..t + ( : - XjE ) [t.Egmax .6:.EgObe(XjE)]. (7.51) BO - XjE 7.4 SiGe-Base Bipolar Transistors 403 Xj£ . i~ f .. ilE gmax I, I, n+ I- I" I I I / I I j p \ Ge , , , , ,,,...,...... !lE gO , •x WBO WB .: Figure 7.9. Schematic illustrating the emitter and base regions of a polysilicon-emitter SiGe-base bipolar transistor having the same base dopant and Ge profiles as in Fig. 7.7, but with XjE < Wcap. Substituting Eqs. (7.50) and (7.51) into Eq. we obtain I Jco(SiGe, XjE) Jco (Si, XjE) Xj£ > weap m( Wso - XjE) {[.6. JW'" e x[-tp .EgO'kbTe(XjE)] - Weap X< (7.53) 404 7 Bipolar Device Design Substituting Eq. (7.53) into Eq:(1.49) we obtain C: Jco(SiGe,XJE)! jii1(Woo - XjE) Jco(Si, XjE) Xj£< w,ap Wcap - XjE + exp [-L).EgB,SiGe (x)/k T] dx YTl [ "1'- J W~~p + XjE] [WEO - WCQP][ "'~J e~;[""'MgQ][1 _ exp (L).EgQ L).Egmax\] . WEO - XjE WEO - XjE tlEgmax - L).EgQ kT kT. (7.54) WhenxjE = Wcap, Eq. (7.54) has the same fonn as Eq. (7.52), as it should. Also, when XjE = Wcap and MgO = 0, Eq. (7.54) reduces to (7.32), as it should. 7.4.3.2 Early Voltage for aTrapezoidal Ge Distribution The same procedures can be followed to obtain equations for the Early voltage ratio. The ratio of the Early voltage of a SiGe-base transistor to that of a Si-base transistor with the same boxlike base dopant distribution is given by Eq. (7.35). It can be adapted to include the effect ofemitter depth, by noting that the quasineutral base starts atx = XjE and ends at x Weo. The result is VA(SiGe,XjE) ~ exp[L).EgB,SiGe(Woo)/kT] VA(Si,xjE) ~ WB(j-='XjE WBO J X XiE exp -L).EgB,SiGe (x)/kT] dx. (7.55) • Case ofGe in the emitter (i.e., XjE> Wcap)' For the case ofGe in the emitter, substituting Eqs. (7.50) and (7.51) into Eq. (7.55), we obtain VA(SiGe,XjE)! VA(Si, XjE) x]£> W,." [ kT ] L).Egmax L).EgObe(XjE) I} L).Egmax - L).EgQbe(XjE)] _ x { exp [ kT . (7.56) It should be noted that the Early voltage ratio in this case' depends on the bandgap energy difference [Mgmax -MgObe(XjE)] across the quasineutral base layer. Equation (7.56) has the same fonn as Eq. (7.36), where MgObe(XjE) O. • Case afno Ge in the emitter (i.e., XjE < Wcap). For the caSe with no Ge in the emitter, there is a residual Ge-free layer of thickness Wcap - XjE in the base. Substituting Eq. (7.53) into Eq. (7.55), we obtain 7.4 SiGe-Base Bipolar Transistors 405 VA (Si<:,e, XjE)! (Wcap XjE) exp (L).Egmax ) VA(SI,Xje) " <'" .~ WllO XJ'E kT '''lE "cap " WBO Weap) ( kT ) + ( WEO XjE L).Egmax L).EgO I} X { exp L).Eg [ makx T- L).EgQ] _ . (7.57) When XjE = Eqs. (7.56) and (7.57) have the same fonn, as.they should. Also, when XjE = Wcap and MgO 0, Eqs. (7.57) reduces to Eq. (7.36), as it should. 7.4.3.3 Base Transit Time for a Trapezoidal Ge Distribution The base transit time ratio can be derived in the same manner. The ratio ofthe base transit time of a SiGe-base transistor to that ofa Si-base transistor having the same boxlike base dopant distribution is given by Eq. (7.40). It can be adapted to include the effect ofemitter noting that the quasineutral base starts at x = XjE and ends at WEO. The result is IB(SiGe,xjE) tB(Si,xjE) 2 JWlIO neW x. )2 exp[L).EgB,SiGe(x)/kT] '1 EO JE Xif; WBO J X x exp[-L).EgB,SiGe(x')/kT] dx'dx. (7.58) • CaseofGe in the emitter (Le.,XjE> Wcap). For the case ofGe in the emitter, substituting Eqs. (7.50) and (7.51) into Eq. (7.58), we obtain tB(SiGe, XjE)! lB(Si,xjE) Xj£> w,u, 2[ kT ] 2[ kT ]2 ij L).Egmax - L).EgObe(XjE) ~ L).Egmax - L).EgObe(XjE) x { I _ exp [L).EgObe(XjEk)T- L).Egmax] } . (7.59) It should be noted that, just like the Early voltage ratio in Eq. (7.56), the transit time ratio depends on the bandgap energy difference [AEgmax - MgObe(XjE)]. Equation (7.59) reduces to Eq. (7.41) when MgObe(XjE) 0, as expected. • Case afna Ge in the emitter (Le., XjE < Wcap)' For the case ofno Ge in the emitter, there is a residual Ge-free layer ofthickness Wcap - XjE in the base. Substituting Eq. (7.53) into Eq. (7.58), we obtain lB(SiGe,XjE)! IB(Si,xjE) x]£ Wcap)' As long as the emitter is sufficiently deep so that the emitter-base junction is located in the constant-Ge region, the SiGe-base transistor has a narrowed energy bandgap that is spatially constant across its entire ~ quasineutral base layer. The emitter and base regions are as illustrated in Fig. 7.10. From Eq. (7.52), we have JcJoe(oS(iGS'Ie,X,X) )EjR)1 Xjf:>w,..1' =- }'11 e xp (t:..E~ ·gO I kT ) • (7.61) From (7.56), we have VA(Si~e'.Xjt;)1 = I, VA(SI,XjE) x ~>w . jE cap (7.62) . 7.4 SiGe-Base Bipolar Transistors 407 XjE " ­ Figure 7.10. :9 .!:! n+ j :;:: '" ["PL~I » 8. t-t---- Ge _I m , ­ AE -lJEgma, I: I . " . . I : I !~ I W I . X 0 ilo i· W8 r+-- Weap Schematic illustrating the emitter and base regions of a polysilicon-emitter SiGe-base bipolar transistor having a constant Ge distribution in the base. The emitter depth XjE is assumed to be larger than the thickness Wcap of the starting Ge-free layer. ~'- and from Eq. (7.59), we have tB(SiGe,XjE)! tB(Si, XjE) x~ > jE W cap ij (7.63) That is, compared to a Si-base transistor, the SiGe-base transistor has higher collector current and current gain, by about a factor of exp(AEg Wrap. • Case ofno Ge in the emitter (i.e., XjS < Wcap)' When the emitter depth is smaller than the starting Ge-free cap thickness, the emitter and base regions are as illustrated in Fig. 7.1 L The energy bandgap is no longer spatially constant across the entire .quasineutral base. Instead, the bandgap is larger at the emitter end of the base where there is no Ge. The corresponding collector current ratio, Early voltage ratio, and base transit time ratio can be obtained from Eqs. (7.54), (7.57), and (7.60), respectively. They are Jeo(Si~e'XjE)1 = yr; {(Weal' XiS) + (WBO - Weal') exp(-I:!.EgO/kT) Jeo(SI,XiE) ,.yr) JCO(SI,.\'jE) xiE VA (SI, XjE) y,"/E. < W (tip (WCQP-XJE) W.oo - Xj'E ex.p (t- :.kET­go) , (7,68) and tB(Si~e'XJE)1 -> ~ {(Wwp XjE) 2 +(W.oo Wwp)2}. Is(SI,XjE) v AI£ <'" "rap ." Wno-XjE WBO-XjE (7.69) That is, both the collector current ratio, hence the current gain ratio, and the base transit time ratio become independent of AEgO for AEgrJkT::p 1, while the Early voltage increases exponentially with AE!,.JkT That the base transit time ratio becomes less sensitive to 6.EgO for large AEgaikTis also evident in Fig. 7,12. Equation (7.69) has a minimwn value ofO,S/ii at (Wcap -.XjE)/(WBO - XjE) = 0.5. The corresponding value for Eq. (7.67) is 2yr). For a typical Ge concentration of 20%, y is aboutOA (Prinz et al., 1989), and." is about 1.4 (Kay and Tang, 1991). Since there is no Oe at the emitter end of the base, the corresponding values averaged over the entire quasineutral base layer should be somewhat larger than 0.4 for )i and somewhat less than 1.4 for ii. So far, we have assumed that the Oe distribution drops abruptly to zero at x = Weap- In practice this never happens, either by design or by the fact that it is impossible to realize a truly abrupt rise or fall in a Ge distribution. (See Washio et al., 2002, for an example ofa realistic Ge profile that is designed to ramp up and down abruptly,) Instead oframpiog , down at an infinite rate to zero at the emitter end, a Ge distribution can be ramped down only at some finite rate. A model for a SiOe-base transistor having a base-region Oe distribution that ramps up from zero concentration at the emitter end to some constant concentration some distance towards the collector end is developed in Ex. 7.10. Whether the Ge distribution ramps up at some finite rate as described in Ex. 7.10, or abruptly as 410 7 Bipolar Device Design illustrated in Fig. 7.11, the device characteristics are qualitatively and quantitatively quite, similar to those of a transistor having a simple triangular Ge distribution. Therefore, as long as there is some regwn ofzero or relatively low Ge concentration at the emitter end ofthe quasineutral base, an otherwise constant-Ge SiGe-base transistor behaves, like a SiGe-base transistor having a graded Ge distribution in that the transistor has larger current gain, larger Early voltage, but smaller base transit time compared to a Si-basetransistor having the same polysilicon emitter, base width and base dopant distribution. This explains why "constant-Ge" SiGe-base transistors usually show higher speed, higher current gains and larger Early voltages than Si-base transistors. 7.4.5 Effect of Emitter Depth Variation on Device Characteristics It is apparent from the previous discussions that for a given starting Ge distribution and starting base layer thickness, the final device characteristics depend on the depth of the single-crystalline n+ emitter region. In a typical SiGe-base bipolar fabrication process, the transistors can have somewhat different emitter depths due to subtle or not so subtle process variations. The emitter depth variation within a wafer should be small, but the variation from wafer to wafer and from run to run can be appreciable. In this section, we use the models developed in the previous sections to examine the effect of emitter depth variation on device characteristics. In modeling the effect of emitter depth variation, it is desirable to select a reference emitter depth and then compare the changes in device characteristics as the emitter depth is varied around the reference. In designing a SiGe-base process, often the goal is to choose a combination of starting Ge-free cap thickness and an emitter drive-in thermal cycle to obtain XjE Wcap, i.e., to result in no Ge in the emitter and no residue Ge-free region in the final quasineutral base. Due to process variation, there are always some transistors with XjE > Weap and some with XjE < Weap- Therefore, it is ofinterest to examine how device characteristics vary around the reference emitter depth of XjE = Wcap (Ning, 2003a). • Effect on collector current and current gain. The effects of emitter depth variation on collector current and current gain are the same. This is because any change in current gain is caused by a change in the collector current and not by a change in the base current, as discussed earlier in Section 7.4.2. Therefore, we shall refer to collector current variation and current gain' variation interchangeably when there is no confusion. Let Jco(SiGe, XjE) and Jco(SiGe, Wcap) denote the saturated collector current densities of a SiGe-base transistor when its emitter depth equals XjE and when its emitter depth equals Wcap, respectively. A plot ofthe ratio Jco(SiGe, XjE)lJco(SiGe, Wcap) as a function ofXjE - Wcap gives the relative change ofthe collector current around the reference point ofXjE '" Weap. This current ratio can be written in the form h1J(SiGe, XjE) JOl(Si~e,.xjE) JOl(~i,Xjd (JOl(Si~e, WCQP))-J JOl(SiGe, Wcap) Jco(SI, XjE) JOl(S!, Wcap) JOl(S!, Wrap) (7.70) 7.4 SIGe-Base Bipolar Transistors 411 3r-----------------~--------------------- 2 dEgmlkT=7.5 -<>- dE.gm/~T~5 .:-+-- dEgmlkT=2.5 ~ ---'NoGe §. :s~ e ~ ~ 0.5 3 ~ 0.3 0,2 t;EgOlkT=2.5 o Wcap Woo Figure 7.13 O·~.I -{l.05 o 0.05 0.1 (XjE- Wcap)/(WBO- Wcap ) Relative collector current variation as a function of (XjE - Wcap)/(WBO Wcap) for a trapezoidal Ge profile with AEgelkT~2.5 and llEgrnaxlkTas a parameter. The ratios Jco(SiGe, XjE)lJco(Si, and Jco(SiGe, Wcap)/Jco(Si, Weap) can be obtained from Eqs. (7.52) and (7.54). Also, it can be inferred readily from Eq. (7.29) (also see Section 6.2.1) that the collector current ratio corresponding to Eq. (7.70) for a Si-base transistor with a boxlike base dopant distribution is (7.71) For our reference design point with XjE = Wcap, the base width is WBO - XjE WBO Therefore, (XjE - Wcap)/(WBO - Wcap) is the emitter depth variation nOimalized to the reference base width. Figure 7.13 is a plot of Eq. (7.70) as a function of (XjE ­ Weap)/(WBO Weal') for a trapezoidal Ge distribution with MgrJkT = 2.5, for several values of I1Egtnax1kT. (XjE Wcap) > 0 means that there is Ge in the emitter, and (XjE­ Wcap) 0, collector current variation is much larger when xjl:: < Weal' than when XjE > Weal" For MgO = 0, collector current variation is about the same for XjE < Wcap and XjE> Weal" However, the collector current increases approximately as exp(Mg('/kn, as expected from Eqs. (7.52) and (7.54). Thus, reducing MgO will reduce current gain variation for XjE < Weal" but it will also reduce the magnitude ofthe current gain by a large amount. Optimizing the Ge profile to minimize current gain sensitivity to emitter depth variation will be discussed later in Section 7.4.6.. • Effect on Early voltage, The corresponding ratio for Early voltage is VA (SiGe, XjE) VA(Si~e,.XjE) VA(Si,xjE) (VA(Si~e, WClIP))-I, (7.72) VA (SiGe, Wcap ) VASI,XjE) VA(Sl, Wcap) VAS!, Wcap) 412 7 Bipolar Device Design 7.4 SiGe-Base Bipolar Transistors 413 2.51 dEgmlkT"' 7.5 dEgmlkT=5 dEgrr,lkT=2.5 NoGe 2 ~ -+- ~ --­ "1-1.5 il=:~ ~ ;:,;. i's" ~ M'lrm ~/kT"'O I 0 w~o o Wcap I I 0.05 0.1 (XjE- \¥.,ap)/(Woo- Weap) Figure 7.14. A similar plot as Fig. 7.13, but with MgdkT= O. -' I, , > ';',~ 10r.------------------------------------------. 5 i} 3 ~ ~ 2 ~!!!. ~ ~/kT=2.S o Wcap Wl/O Figure 7.15 0.5 dEgmlkT=7.5 dEgmlkT",S dEgm/kT=2.5 -+- -+- ~ 0.3' I I --NoGe J u __ -0.1 -0.05 0 0.05 0.1 (XjE-Wcap)/(Wso-Weap) Relative Early voltage variation as a function of (XjE - Wcap)/(Woo - We",,) for a trapezoidal Ge profile with MgalkT=2.5 and MgmaxlkTas a parameter, the same as in Fig. 7.13. where VA(Si,XjE) WBO-XjE VA (Si, Wcap ) WBO Wcap (7.73) is the Early voltage ratio for a Si-base bipolar transistor having a boxlike base dopant distribution (see Section 6.3.2). Figure 7.15 is a plotofEq. (7.72) as a function of (XjE - Wcap)/(WSo - Wcap) for the same trapezoidal Ge distribution as in Fig. 7.13. When there is Ge in the emitter, the Early voltage is not a sensitive function ofemitter depth, decreasing only slowly as the emitter depth increases. However, when there is a residual Ge-free layer in the base, the Early voltage is a strong function of emitter 1.3 1.2~ "',/kT." ~.. 1.1 ~8 !! !fl, ~ ~ 0.9 o Wcap WI/O ­ 0.8t dEgm/kT", 7.5 -II- dEgmlkT~5 -+- dEgm/IcT=2.5 -+­ --NoGe 0.7 -0.1 -0.05 0 0.05 0.1 (xjrw"ap)/(WI/O- w"ap) figure 7.16 Relative base transit time variation as a function of(xjE Wcap)/(Woo Wcap) for a trapezoidal Ge profile with MgalkT=2.5 and MgmaxlkTas a parameter, the same as in Fig. 7.13. depth, due primarily to the first term in Eq. (7.57) which contains a large multiplying factor exp(Mgmax1k1). • Effect on base transit time. In a similar manner, we can write the ratio ofthe base transit time as a function ofXjE to that at XjE = Wcap as ts(~iGe,xjE) = tB(Si Wcap in Fig. 7.16, where a decrease in base width is caused by the emitter being deeper than intended. In this region, a decrease in 414 7 Bipolar Device Design base width is accompanied by an increase in the Ge concentration at the emitter end of the quasineutral base layer, i.e., MgObe(}:jE) increases as Ws decreases or as XjE increases. In this case, the base transit time of a SiGe-base transistor still decreases more slowly with base width than a Si-base transistor. The net is that the base transit time of a SiGe-base transistor is less sensitive to base width variation than a Si-base transistor. In particular, the base transit time ofa SiGe-base transistor is relatively insensitive to increase in base width caused by the emitter depth being smaller than intended, particularly when the emitter depth is smaller than the starting Ge-free cap thickness. These results suggest that it is possible to optimize the Ge distribu­ tion to further reduce base transit time. This will be illustrated later in Section 7.4.6.2. 7.4.6 7.4.6.1 Some Optimal Ge Profiles In this section, we apply the models developed in the previous sections to discuss tailoring the Ge profile in the quasineutral base for optimal or improved device char­ acteristics. We first consider it from a current gain perspective, and then from a base transit time perspective. Ge Profile from Current Gain Perspective SiGe-base transistor designers often find current gains too large andlor varying too much among transistors. Compared to a Si-base transistor, the larger current gain in a SiGe-base transistor is caused by an increase in collector current, not by a decrease in base current. Also, as discussed in Section 7.4.2, it is preferable to reduce the current gain of a SiGe-base transistor by reducing its collector current than by increasing its base current. • Reducing current gain without degrading base transit time. The most effective way to reduce collector current is to reduce the amount of bandgap narrowing at the emitter end of the quasineutral base layer. To see this, let us consider the case depicted in Fig. 7.7. The transistor has a trapezoidal Ge distribution with an emitter depth greater than its starting Ge-free cap thickness. The corresponding transit time ratio is given by Eq. (7.59), which shows that the base transit time is a function ofthe energy difference [Mgmax - MgOMXjE)] across the quaslneutral base layer. For this transistorth~ collector current ratio is given by Eq. (7.52), which shows that for a given energy difference [Mgmax - MgOheCXjE)], the collector current increases exponentially with increase in MgObe(XjE). Therefore, if we reduce MgObe(XjE) but keep [Mgmax .iEgOMXjE)] constant, we can reduce collector current, and hen.ce current gain, significantly without affecting base transit time. Reducing MgObe(XjE) while keeping [Mgmax - MgObe(XjE)] constant means that MgJnax is reduced by the same amount. • Minimizing sensitivity ofcurrent gain to emitter depth variation. Designers often want to have a current gain that does not vary much with emitter depth. This can be accomplished by using the Ge distribution illustrated in Fig. 7.17 where the emitter­ base junction is confined to a constant-Ge region (Oda et al., 1997; Ansley et al., 1998; Niu el al., 2003). The model discussed in Section 7.4.3.1 for the case of no Ge in the 7.4 SiGe-Base Bipolar Transistors 415 XjE * - .if'..... gmax !l.E i /\ : /' :2 1 :. " '/ " \ Ge ' ' .Sl n+ : ,/ \ ~ ~e !5 ! / i-+·l . LI ", ~ ::E :: p !i I \ gO \ •! 0 ;. WBO "X I w "1 B c+-- Wcap Agure7.17. Schematic illustrating the emitter and base regions of a polysilicon-emitter SiGe-base bipolar transistor having a Ge distribution that makes the collector current less sensitive to emitter depth variation. For simplicity, the base dopant distribution is not shown. The emitter-base junction is confined to a region of finite but constant Ge concentration. emitter can be readily extended to this case. Instead of a Ge-free cap, we have a constant-Ge region. In this case, the base bandgap narrowing parameter is given t::..EgB,SiGe(X) = t::..Egf) + ( WXoo-_WWcacpap ) (t::..Egmax - t::..Egf») x> Weap t::..EgO x< Weap. (7.76) It is left as an exercise (Ex. 7.11) for the reader to show that the collector current ratio in this case is Jrn(SiGe, XjE) Jrn(Si, XjE) [I 7fi exp(l:lEgO/kT) Wcap XiE) + (WEO - Wcap) ( kT ) ( WEO - XjE Woo - XjE l:lEgmax - l:lEgO exp(l:lEgo -l:lEg;;:;'~)'.]-. kT (7.77) The collector current improvement factors of a SiGe-base transistor relative to a Si-base transistor for three Ge profiles are compared in Fig. 7.18 as a function of emitter depth variation, using YI1 1. Some insights into the dependence of collector current on Ge distribution can be inferred from Fig. 7.18. First, a high Ge concentration at or near the emitter-base junction leads to large collector current arid current gain. Second, a Ge distribution that ramps down steeply or abruptly towards the emitter­ base junction, as depicted by the "Ge-free cap" case in the figure, causes the collector current to be sensitive to emitter depth variation. This is probably the main reason why large current-gain variations are often observed in SiGe-base bipolar transistors. 416 7 Bipolar Device Design Gecap Ge-free cap Triangular ~AE XE gm (: ............ AEg(J llr=b tX~E /"1AEgm XjE I I I o \-l'c"p WBO 100 50L Q 9 9 e e 9 9 o \-l'cap WBO ~ 9 Q/ .. - - j o Weap WBO" 30 ~ Q ~ ~ "'~ § 5~ ~ ~'" 3 t;.EgmaxlkT= 7.5 = AEg(JlkT 2.5 2 ---e- Ge cap - - Ge-free cap - O. When that happens, the base transit time is degraded, or not improved over a Si-base transistor by as much as intended, as demonstrated in Fig. 7.19. And, as discussed in Section 7.4.6.1, when MgObe(xjE) is larger than intended, the collector current and current gain are also larger than intended. Next, let us consider the case when the Ge concentration is ramped down at a rate faster than intended. Let us assume that the target design is to have a simple triangular . Ge distribution withxjE = Weap, Mgo =0, and some desired valued ofMgmax. If the Ge concentration is ramped down at a rate faster than intended during growth of the base layer, there will be a finite region of the quasineutral base at the emitter end with no Ge at all. This is the case of "no Ge in emitter" described in Section 7.4.3.3. The base transit time ratio can be obtained from Eq. (7.60) by setting AEgO O. The quasineutral base width is WBO - XjE and the thickness ofportion of the guasineutral base having no Ge is Weal' ·~XjE. Figure 7.20 is a plot of the relative change of base transit time as a function of (Weap -xjE)/(WBO -XjE), using MgmaxlkT= 7.5. to(Wcal' - XjE) is the base transit time when there is a Ge-free layer of thickness Weal' - XjE at the emitter end of the quasineutral base. to(O) is the base transit time for the intended Ge distribution where the thickness ofthe Ge-free layer is zero. The shape ofthe curve is caused by the balance of the various terms in Eq. (7.60). Figure 7.20 suggests that for a given Mgmax and base width, as the thickness of the Ge-free layer at the emitter end of the base 418 7 Bipolar Device Design Ll 1.05 8 ..~ ~"' I i} ~ ~ 0.95 tlEgmlkT= 7.5 l'~/I~ o Wcap Woo Figure 7.20 0.9 0 0.05 0.1 0.15 0.2 (Wcap- xjE)/(Woo- XjE) Relative change of base transit time at fixed quasineutral base width as a function of thickness of the Ge-free layer at the emitter end of the base. increases from zero to some finite value, the base transit time goes through a minimum at a Ge-free layer thickness of about 10% of the base width. This result together with the dependence on MgO discussed above suggest that it is preferred to ramp down the Ge distribution more rapidly than intended instead ofmore slowly than intended. For a given quasineutral base width and Mgrn:;x, it is better to have a thin Ge-free layer at the emitter end of the base than to have MgObe(XjE) > O. 7.4.6.3 Current Gain and Base Transit Time Tradeoff The Ge distribution illustrated in Fig. 7.17 can be represented as the sum ofa constant-Ge distribution and a graded-Ge distribution. That is, instead ofEq. (7.76), the base bandgap narrowing parameter can be written as llEgO,SiGe(x} llEgO + llE;O,SiG.(X), (7.78) where llEgBI ,SiGe(X) = ( X -'- Wcap ) W.BO _ Wcap (llEg max - llEgO ) x> Wcap o X 0). For the transistor in Fig. 7.21(b), the Ge distribution is such that llEgQhe= 0 for all positive values of VBE, and the Ge-free region within the quasineutral base is thinner at VSE=O than at VBE > O. The rolloffin Jeo for both transistors can be infcrred from Fig. 7.14, which can be interpreted as a plot of variation ofti.le saturated 7.4 SiGe-Base Bipolar Transistors 421 (a) ;" .;;; "il ~ E is ~ t n+ .Ge ,,:,,"ft,~ .Q 8. .~§ "+c I 1/': : 'I V Yl P ': ; : :: '---"'i .... x WB(VBE=O) (b) :'2" .:a2 s E" sis ~ n+ .Ge :I~I ,I I I , I H--T---,,', .Q 8. "I , .~ ,I /P Ii + ,I I '" / ..• B , , I .\ • • tX ' - - - -.•., WB(VB£=O)· ;• >: WB(VBE>O) !• > WB(VBe>O} Figure 7.21. Schematics illustrating base widening at the emitter end for two SiGe-base transistors. (a) For this transistor, the Ge concentration ramps down to zero at a point beyond the emitter end of the quasineutral base laycrwhcn the transistor is biased at V SE = O. As VB£ is increased, t:.Eg!}be( V Bel decreases. (b) For this transistor, the Ge concentration ramps down to zero before reaching the emitter end of the quasineutral base layer when the transistor is biased at VBE = O. As VBE is increased, t:.Eg(Jbe (VBE) remains zero. collector current density as a function of base-width modulation caused by VBE. The situation in Fig. 7.21(a) corresponds to the (XjE Wcap) > 0 part of Fig. 7.14. As VBE is increased, the emitter end of the boundary of the quasineutral base, i.e., the location of XjE, moves from right to left in the right half of Fig. 7.14. The situation in Fig. 7.21(b) corresponds to the (XjE Wcap) < 0 part of Fig. 7.14. As VBE is increased, the emitter end of the boundary of the quasineutral base, i.e., the location ofXjE, moves from right to left in the left half of Fig. 7.14. For the same amount of base widening, i.e., for the same change in I(XjE- Wcap)l, Fig. 7.14 shows that the rolloffinJa) is larger for the transistorin Fig. 7.21(a) than for the transistor in Fig. 7.21(b). Both transistors show significantly larger rolloff in Ja) than a Si-base transistor which is represented by the no-Ge curve in Fig. 7.14. The magnitude of Ja) rolloff due to base widening at the emitter end is a strong function of the details of the Ge distribution near the emitter end, particularly If the Ge profile is more like a trapezoid than a triangle. This can be seen by comparing Figs 7.13 and 7.14. Very large rolloffin Ja) can be expected from a trapezoidal-like Ge distribution. A rolloffin Ja) should lead to arolloffin current gain. Figure 7.22 is a plot of observed current gain rolloffin a SiGe-base bipolar transistor (Crabbe et aI., 1993b). The initial rise, instead offalloff, in current gain at very low currents is caused by the nonideal nature of base current. (See Section 6.3.4 for a discussion on the ideality of base current in practical transistors.) The nonideal nature of base current causes JBO to decrease with increasing VBE- When JBO decreases more rapidly with VBE than Jco, current gain will rise " ..~ with increasing VBE or with increasing collector current. This causes the measured current gain to increase at low collector currents. Consider the data at 300 K in Fig. 7.22. The rapid rolloff in current gain at current densities greatcr than about 1.5 mAlJ.l.m2 is caused by Kirk effect, which is base widening at the collector end. The slow current gain falloff at current densities less than 1.5 mA/llm2 is caused by base-width modulation by VBE, which is base widening at the emitter end. 422 7 Bipolar Device Design 7.4 SiGe-Base Bipolar Transistors 423 1200 r 1000 ,,,, , , ,, \ 85K l63K \ "';;'; 800 1":": ~ 600 U'" ------- I I I I I \ \ \ \ 300K ~. 400 / .................. ­ 2001­ !;~* ........ IE-I Collector current density IE+O lE+l Figure 7.22. Measured current gain rolloff in a typical SiGe-base transistor as a function of collector current density. (AfterCrabbeetal., \993b.) , 7.4.7.3 7.4.7.4 Figure 7.22 also shows that current gain rolloff due to Voe-induced base widening increases rapidly as temperature decreases. This is to be expected because the values of t.Egmax and t.EgO are fixed for a SiGe-base transistor, but the values of t.Egmax/kT and MgO/kT increase as temperature decreases, causing both current gain and "emitter depth variation" effect to increase. Ideality of the Collector Current As shown in Fig. 6.5, the collector current of a Si-base bipolar transistor is quite ideal, i.e., it is proportional to exp(qVBE/mkT) with m very close to unity at VOE less than about 0.9 V (before Kirk effect sets in and/or before emitter series resistance effect becomes significant). This fact is often used to determine the operating temperature of a Si-base transistor. As discussed in the subsection above, base widening at the emitter end can cause appreciable Jco rolloff in a SiGe-base bipolar transistor even before Kirk effect sets in. That is, the measured collector current ofa SiGe-base transistor often has an exp(qVoE/mkT) dependence with m greater than unity. Therefore, unless the ideality factor m can be determined separately, there can be an appreciable error in using the collector current of a SiGe-base bipolar transistor to determine the device operating temperature. VSE as a Reference Circuit designers often use VOE as a reference. VBE'referenced circuits are based on the assumption that the collector current Ie of a bipolar transistor is determined by its emitter area and Circuit designers often refer to "VBE" ofa transistor as the VBE value needed to achieve a target Ie value. For a Si-base bipolar transistor, the relationship between Ie = and VBEis simply Ie AeJcoexp(qVodkT) [see Eq. (6.32)], andJco is independent of VBE for VOE less than about 0.9 V. However, as mentioned above, the dependence ofJ co on VBE may not be negligible for a SiGe-base bipolar transistbr. Furthermore, Jco of a SiGe-base bipolar transistor is a strong function of its Ge profile near the emitter end of the quasineutral base. It has been shown that a small change in the Ge profile shape can cause an appreciable change in (Salmon et aI., 1997; Deixler et al., 2001). Therefore, special attention should be paid to the nonideality nature of the collector current when designing VOE"referenced circuits using SiGe-base bipolar transistors. 7.4.7.5 Mininizing V8E'lnduced Base-Width Modulation Effects Base widening atthe emitter end can be minimized by minimizing the dependence of WdOE on VBE. This can be accomplished easily by increasing base doping concentration NB, as can be inferred from Eq. (7.80) and discussed in Section 7.4.7.2. Additionally, the '" base and emitter fabrication processes should also be designed so that XjE is located in a region ofconstant or slowly varying Ge concentration (XjE is the sum of the depth of the single-crystalline emitter region and the width of the emitter-base diode space-charge layer). Preferably, XjE should be located in a region of relatively low Ge concentration, or in a Ge-free region such as the case illustrated in Fig. 7.21(b). As discussed in Section 7.4.6.2, such a design is also preferred from base transit time consideration. 7.4.8 Reverse-Mode I- VCharacteristics A bipolar transistor is normally operated in the Jorward-active mode. Occasionally, a transistor is operated in the reverse-active mode either unintentionally or by design. For instance, when a transistor goes into saturation in a circuit, its collector-base junction becomes forward biased and its collector current is the difference between a forward component and a reverse component. In this section we compare the reverse-mode currents to the forward-mode currents. The normal (or forward) and reverse modes of operation of a SiGe-base bipolar transistor are depicted schematically in Fig. 7.23. Here, for simplicity of illustration, we assume a simple triangular Ge distribution in the quasineutral base. As discussed in Section 6.4.1, the reciprocity relationship between emitter and collector implies that the magnitude of the collector current in normiJ,1 mode is equal to the magnitude of the collector current in reverse mode. That is, we have in theory Electron flow (normal) Electron flow (reverse) e junction. 7.4.9.2 Heterojunction Nature of a Constant-Bandgap SiGe-Base Transistor To clearly distinguish a constant-Ge SiGe-base transistor from a graded-Ge SiGe-base transistor, we assume the Ge distribution in the constant-Ge transistor to ramp down near the emitter end, such as those illustrated in Figs 7.10 and 7.11, instead ofat some fini,te rate. 428 7 Bipolar Device Design 7.5 Modem Bipolar Transistor Structures 429 t Ee =~~~-~-=-......-. -l----~~!~--h- Ee EI Si /. n+ Ev Ev r' Iquasineutral base B E C Figure 727. Energy-band diagram corresponding to the emitter-base diodes illustrated in Fig.. 7.1 0, at VEE; O. w"ap-XjE ~ :.....­ E r\SiGe E,; c ------------------------------- EI +S' E, nI / E, quasineutral base Polysilicon-filled deep-trench isolation Figure 7.29. Schematic illustrating the structure of the commonly used bipolar transistor and its salient features. the device properties that depend on electron injection into and transport across the base. It is the electron injection and transport across the base region that makes a SiGe­ base transistor superior to a Si-base transistor. Figure 7.28. Energy-band diagram corresponding to the emitter-base diodes illustrated in Fig. 7.11, at VEE =O. 7.5 Modem Bipolar Transistor Structures • Case of Ge in the emitter (i.e., XjE > Wcap). The Ge distribution and the dopant distributions in the emitter and base regions are illustrated schematically in Fig. 7.10. The corresponding energy-band diagram is illustrated in Fig. 7.27. The emitter bandgap is large compared to the base bandgap. Indeed, one can think of this transistor as a wide-gap-emitter HBT. However, as discussed in Section 7.4.2.2, compared with a Si-base transistor having the same polysilicon emitter and base dopant distribution, this transistor has the same, instead of smaller, base current. It has larger current gain, consistent with a wide-gap-emitter transistor, but the larger current gain is due to an increase in collector current, not a reduction in base current. Also, just like a wide-gap­ emitter HBT without base-bandgap grading, there is little improvement in Early voltage or in base transit time (other than from the correction factors 7f and • Case ofno Ge in the emitter (i.e., XjE < Wcap)' In this case, the Ge distribution and the dopant distributions in the emitter and base regions are as illustrated schematically in Fig. 7.11. The corresponding energy-band diagram is illustrated in Fig. 7.28. If we focus at the region near the emitter-base junction, the transistor appears not to be a wide-gap-emitter device at all because the emitter and the emitter end of the quasi­ neutral base have the same energy bandgap. Indeed, compared to a Si-base transistor having the same polysilicon emitter and base dopant distribution, this transistor has the same base current. However, as discussed in Section 7.4.4 and shown in Ex. 7.10, this transistor not only has higher. current gain, due to its larger collector current, but also After a relatively large research and development effort worldwide in the 1970s and I980s, bipolar technology has become fairly mature. Since the mid 1990s, the growth in wireless and RF applications has revived the interest in bipolar technology research and development. This time, the focus is on optimizing the SiGe-base bipolar transistor. Techniques for implementing the device design concepts discussed in this chapter have been developed, and in most cases implemented. The most widely used bipolar technol­ ogy today is probably the deep-trench-isolated, double-polysilicon, self-aligned bipolar technology (Ning et gl., 1981; Chen et al. , 1989) and variations of it. This device structure is illustrated schematically in Fig. 7.29. The process flow for fabricating this transistor structure is outlined in Appendix 2. The salient features of this device are: (i) deep-trench isolation between adjacent transistors, (ii) polysilicon emitter, (iii) poly­ silicon base contact, which is self-aligned to the emitter, and (iv) pedestal collector, i.e., the collector region directly underneath the emitter is more heavily doped than its surrounding regions. Also, for analog circuit applicatioml" a SiGe-base transistor is particularly advan­ tageous. The basic concept for each of these features is discussed below. More recently, vertical bipolar transistors employing silicon-on-insulator (SOl) sub­ strate with silicon thickness that are compatible with SOl CMOS have been demonstrated (Cai etal., 2002a; 2003). The idea is to develop high-speed and low-power SOl BiCMOS for mixed-signal applications. The subject of SOl bipolar is discussed -in Section 10.2. larger Early voltage and smaller base transit time. The high-low energy gap in the base makes this transistor behave more like a graded-base-bandgap transistor than a 7.5.1 Deep-Trench Isolation constant-base-bandgap transistor. The isolation region must be deep enough to isolate the subcollectors of adjaeent transis­ The net of all these is that it is best to think ofa SiGe-base device as a graded­ tors. prior to the advent ofdeep-trench isolation, p-type diffusion regions are used to isolate base-bandgap bipolar transistor instead ofan HBT. By focusing on the base-bandgap subcollectors, as illustrated in Fig. 7.4. A p-type diffusion-isolation region is typically grading characteristics instead of the emitter-base junction parameters, we focus on as wide as it is deep. This is because of the fact that, as the p-type impurities diffuse 430 7 Bipolar Device Design . 7.5.2 7.5.3 downward, they also diffuse laterally. Furthermore, to minimize junction capacitance and to avoid excessively low collector-substrate junction breakdown voltage, the p-type diffusion-isolation regions should not butt against the heavily doped n-type subcollector regions. There is usually an n- region between a p-type isolation and a subcollector or reach-through, as illustrated in Fig. 7.4. As a result, the total silicon area taken up by the diffusion-isolation regions is very large. The area ofa diffusion-isolated bipolar transistor is completely dominated by its isolation. Replacing diffusion isolation by deep-trench isolation reduces very significantly the area taken up by isolation. The horizontal dimension of the deep trenches is. usually defined by lithography. With deep-trench isolation, the trenches can cut right through the subcollector layer, resulting in much smaller collector-substrate area and capacitance than with diffusion isolation. The diffusion-isolation process is less complex, and hence may cost less, than the trench-isolation process. For reason of cost, diffusion isolation is still used in some bipolar products. However, the area taken up by isolation translates into cost as welL Also, as power dissipation is a factor of growing importance in the choice of a technol­ ogy, product designers often favor trench isolation over diffusi<;>n isolation because ofits smaller parasitic capacitance, which leads to systems with lower power dissipation. Polysilicon Emitter The benefit of polysilicon emitter has already been discussed in Section 7.1. Polysilicon emitter allows extremely small emitter-junction depths to be achieved without the large base current associated with a metal-contacted shallow emitter. Small emitter-junction depths are needed for making thin-base transistors with reproducible base-region para­ meters, and hence reproducible collector current characteristics. Thus, in many respects, polysilicon emitter is the enabling technology for scaling bipolar transistors to small dimensions. All modem bipolar transistors, including SiGe-base transistors, employ polysilicon-emitter technology. The very low thermal cycle associated with the formation of a polysilicon emitter, compared with that associated with a diffused-emitter process, has resulted in a drastic reduction in the density of defects called pipes, which are localized emitter-collector shorts formed in the intrinsic-base layer. In general, the ,emitter thermal cycle can be further minimized by using phosphorus instead of arsenic to dope the polysilicon layer, particularly if the polysilicon layer is in-situ doped. Furthermore, rapid thermal annealing, instead of furnace annealing, leads to the shallowest emitters with low series resistance. The reader is referred to the literature for reports on using phosphorus-doped polysilicon for emitter (Nanba et al., 199\; Crabbe et al., 1992; Shiba et al., 1996). Self-Aligned Polysilicon Base Contact As illustrated in Fig. 7.29, instead ofbeing contacted directly by metal, the extrinsic base is contacted indirectly via a layer of p-type polysilicon. Metal contact to the p-type polysilicon is made on top of the field-oxide region. In this way, the extrinsic-base area 7.5 Modem Bipolar Transistor Structures 431 does not have to accommodate the base metal contact, and hence can be made quite small, resulting in very small extrinsic-base-collector junction area and capacitance. Furthermore, by separating the extrinsic-base polysilicon layer and the emitter poly­ silicon layer by only a· thin vertical insulator layer, the extrinsic-base area is further reduced. This thin vertical insulator layer is often referred to as a sidewall insulator layer. It is typically formed by the deposition of a thin insulator layer of the desired thickness followed by anisotropic reactive-ion etching, removing the insulatorcompietely everywhere except where the insulator covers a vertical surface. The ratio of the total collector-base (extrinsic base + intrinsic base) junction area to the emitter-base junction area is typically 3:l or less (Ning et al., 1981). Perhaps more important is the fact that polysilicon-base technology allows the extrin­ sic base to be formed independently ofthe intrinsic base. This decoupling ofthe intrinsic and extrinsic base greatly enlarges the intrinsic-base design and process window. It allows thin-base transistors to be made readily. Practically all modem