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Fundamentals of Modern VLSI Devices (2nd Edition)

Tak Ning的经典教材

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Fundamentals of Modern" VLSI Devices SECOND EDITION YUAN TAUR University of California, san Diego TAK H. NING IBM T. J. Watson Research Center, New York CAMBRIDGE UNIVERSITY PRESS CAMBRIDGE UNIVERSITY PRESS Cambridge, New York, Melbourne, Madrid, Cape Town, Singapore, Sao Paulo, Delhi Cambridge University Press The Edinburgh Building, Cambridge CB2 8RU, UK Published in the United States of America by Cambridge University Press, New York www..cambridge.org Information on this title: www.cambridge.orgl9780521832946 © Cambridge University Press 1998, 2009 This publication is in copyright. Subject to statutory exception and to the provisions of relevant collective licensing agreements, no reproduction of any part may take place without the written pennission of Cambridge University Press. First published 1998 Second edition 2009 Printed in the United Kingdom at the University Press, Cambridge A catalog recordfor this publication is availablefrom the British Library Library ofCongress Cataloging in Publication data Taur, Yuan, 1946 Fundamentals of modem VLSI devices / Yuan Taur, Tak H. Ning. 2nd ed. p. cm. ISBN 978-0-521-83294-6 1. Metal oxide semiconductors, Complementary. 2. Bipolar transistors. 3. Integrated circuits Very large scale integration. l. Ning, Tak H., 1943- 11. Title. TK7871.99.M44T38 2009 621.39'5-dc22 2009007334 ISBN 978-0-521-83294-6 hardback Cambridge University Press has no responsibility for the persistence or accuracy of URLs for external or third-party Internet websites referred to in this publ.ication, and does not guarantee thai any content on such websites is, or will remain, accurate or appropriate. Contents Preface to the first edition Preface to the second edition Physical constants and unit conversions List ofsymbols page xi xiii xv XVI 1 Introduction 1.1 Evolution ofVLSI Device Technology 1.1.1 Historical Perspective 1.1.2 Recent Developments 4 1.2 Modern VLSI Devices 4 1.2.1 Modern CMOS Transistors 4 1.2.2 Modern Bipolar Transistors 5 1.3 Scope and Brief Description of the Book 6 2 Basic Device PhysiCS 11 2.1 Electrons and Holes in Silicon II 2.Ll Energy Bands in Silicon 11 2.1.2 n-Type and p-Type Silicon 17 2.1.3 Carrier Transport in Silicon 23 2.1.4 Basic Equations for Device Operation 27 2.2 p-n Junctions 35 2.2.1 Energy-Band Diagrams for a p-n Diode 35 2.2.2 Abrupt Junctions 38 2.2.3 The Diode Equation 46 2.2.4 Current-Voltage Characteristics 51 2.2.5 Time-Dependent and Switching Characteristics 64 2.2.6 Diffusion Capacitance 70 2.3 MOS Capacitors 72 23.1 Surface Potential: Accumulation, Depletion, and Inversion 72 2.3.2 Electrostatic Potential and Charge Distribution in Silicon 78 2.3.3 Capacitances in an MOS Structure 85 2.3.4 Polysilicon-Gate Work Function and Depletion Effects 91 2.3.5 MOS under Nonequilibrium and Gated Diodes 94 vi Contents Contents vii 2.3.6 Charge in Silicon Dioxide and at the Silicon-Oxide Interface 98 4.3 MOSFET Channel Length 242 2.3.7 Effect of Interface Traps and Oxide Charge on Device Characteristics 103 4.3.1 Various Definitions ofChannel Length 242 2.4 Metal-Silicon Contacts 108 4.3.2 Extraction ofthe Effective Channel Length 244 2.4.1 Static Characteristics of a Schottky Barrier Diode 108 4.3.3 Physical Meaning of Effective Channel Length 248 2.4.2 Current Transport in a Schottky Barrier Diode 115 4.3.4 Extraction of Channel Length by C-VMeasurements 252 2.4.3 Current-Voltage Characteristics of a Schottky Barrier Diode ll5 Exercises 254 2.4.4 Ohmic Contacts 120 2.5 High-Field Effects 122 5 CMOS Perfonnance Factors 256 2.5.1 Impact Ionization and Avalanche Breakdown 122 2.5.2 Band-to-Band Tunneling 125 2.5.3 Tunneling into and through Silicon Dioxide 127 2.5.4 Injection of Hot Carriers from Silicon into Silicon Dioxide 133 2.5.5 High-Field Effects in Gated Diodes 135 2.5.6 Dielectric Breakdown 137 Exercises 141 5.1 Basic CMOS Circuit Elements 5.1.1 CMOS Inverters 5.1.2 CMOS NAND and NOR Gates 5.1.3 Inverter and NAND Layouts 5.2 Parasitic Elements 5.2.1 Source-Drain Resistance 5.2.2 Parasitic Capacitances 256 256 266 270 273 274 277 3 MOSFET Devices 5.2.3 Gate Resistance 148 5.2.4 Interconnect R and C 280 283 3.1 Long-Channel MOSFETs 148 5.3 Sensitivity of CMOS Delay to Device Parameters 289 3.1.1 Drain-Current Model 149 5.3.1 Propagation Delay and Delay Equation 289 3.1.2 MOSFET J- V Characteristics 155 5.3.2 Delay Sensitivity to Channel Width, Length, and Gate Oxide Thickness 296 3.1.3 Subthreshold Characteristics 163 5.3.3 Sensitivity of Delay to Power-Supply and Threshold Voltage 299 3.1.4 Substrate Bias and Temperature Dependence of Threshold Voltage 166 5.3.4 Sensitivity of Delay to Parasitic Resistance and Capacitance 301 3.1.5 MOSFET Channel Mobility 169 5.3.5 Delay of Two-Way NAND and Body Effect 304 3.1.6 MOSFET Capacitances and Inversion-Layer Capacitance Effect 172 5.4 Performance Factors of Advanced CMOS Devices 307 3.2 Short-Channel MOSFETs 175 5.4.1 MOSFETs in RF Circuits 308 3.2.1 Short-Channel Effect 176 5.4.2 Effect of Transport Parameters on CMOS Performance 311 3.2.2 Velocity Saturation and High-Field Transport 186 5.4.3 Low-Temperature CMOS 312 3.2.3 Channel Length Modulation 195 Exercises 315 3.2.4 Source-Drain Series Resistance 196 3.2.5 MOSFET Degradation and Breakdown at High Fields Exercises I 196 6 201 Bipolar Devices 6.1 n-p-n Transistors 318 318 4 CMOS Device Design 204 6.1.1 Basic Operation of a Bipolar Transistor 322 6.1.2 Modifying the Simple Diode Theory for Describing Bipolar Transistors 322 4.1 MOSFET Scaling 204 6.2 Ideal Current-Voltage Characteristics 327 4.1.1 Constant-Field Scaling 204 6.2.1 Collector Current 329 4.1.2 Generalized Scaling 207 6.2.2 Base Current 330 4.1.3 Nonscaling Effects 210 6.2.3 Current Gains 334 4.2 Threshold Voltage 212 6.2.4 Ideal Characteristics 336 4.2.1 Threshold-Voltage Requirement 213 6.3 Characteristics of a Typical n-p-n Transistor 337 4.2.2 Channel Profile Design 217 6.3.1 Effect of Emitter and Base Series Resistances 338 4.2.3 Nonuniform Doping 224 6.3.2 Effect of Base-Collector Voltage on Collector Current 340 4.2.4 Quantum Effect on Threshold Voltage 234 6.3.3 Collector Current Falloff at High Currents 343 4.2.5 Discrete Dopant Effects on Threshold Voltage 239 6.3.4 Nonideal Base Current at Low Currents 347 Contents 6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses 6.4.1 Basic dc Model 6.4.2 Basic ac Model 6.4.3 Small-Signal Equivalent-Circuit Model 6.4.4 Emitter Diffusion Capacitance 6.4.5 Charge-Control Analysis 6.5 Breakdown Voltages Common-Base Current Gain in the Presence of Base-Collector Junction Avalanche 6.5.2 Saturation Currents in a Transistor 6.5.3 Relation Between BVCEO and BVCBO Exercises 352 352 355 356 359 361 366 367 369 370 371 7 Bipolar Device Design 374 7.1 Design of the Emitter Region 7.1.1 Diffused or Implanted-and-Diffused Emitter 7.1.2 Polysilicon Emitter 7.2 Design of the Base Region 7.2.1 Relationship between Base Sheet Resistivity and Collector Current Density 7.2.2 Intrinsic-Base Dopant Distribution 7.2.3 Electric Field in the Quasineutral Intrinsic Base 7.2.4 Base Transit Time 7.3 Design of the Collector Region 7.3.1 Collector Design When There Is Negligible Base Widening 7.3.2 Collector Design When There Is Appreciable Base Widening 7.4 SiGe-Base Bipolar Transistors 7.4.1 Transistors Having a Simple Linearly Graded Base Bandgap 7.4.2 Base Current When Ge Is Present in the Emitter 7.4.3 Transistors Having a Trapezoidal Ge Distribution in the Base 7.4.4 Transistors Having a Constant Ge Distribution in the Base 7.4.5 Effect of Emitter Depth Variation on Device Characteristics 7.4.6 Some Optimal Ge Profiles 7.4.7 Base-Width Modulation by VBE 7.4.8 Reverse-Mode I-V Characteristics 7.4.9 Heterojunction Nature of a SiGe-Base Bipolar Transistor 7.5 Modem Binolar Transistor Structures Isolation 7.5.2 Polysilicon Emitter 7.5.3 Self-Aligned Polysilicon Base Contact 7.5.4 Pedestal Collector 7.5.5 SiGe-Base Exercises 374 375 376 377 378 380 381 384 385 387 388 389 390 396 401 406 410 414 419 423 426 429 429 430 430 431 431 432 Contents ix 8 Bipolar Performance Factors 437 8.1 Figures of Merit of a Bipolar Transistor 8.1.1 Cutoff Frequency 8.1.2 Maximum Oscillation Frequency 8.1.3 Ring Oscillator and Gate Delay 8.2 Digital Bipolar Circuits 8.2.1 Delay Components of a Logic Gate 8.2.2 Device Structure and Layout for Digital Circuits 8.3 Bipolar Device Optimization for Digital Circuits 8.3.1 Design Points for a Digital Circuit 8.3.2 Device Optimization When There Is Significant Base Widening 8.3.3 Device Optimization When There Is Negligible Base Widening 8.3.4 Device Optimization for Small Power-Delay Product 8.3.5 Bipolar Device Optimization from Some Data Analyses 8.4 Bipolar Device Scaling for ECL Circuits 8.4.1 Device Scaling Rules 8.4.2 Limits in Bipolar Device Scaling for ECL Circuits 8.5 Bipolar Device Optimization and Scaling for RF and Analog Circuits 8.5.1 The Single-Transistor Amplifier 8.5.2 Optimizing the Individual Parameters 8.5.3 Technology for RF and Analog Bipolar Devices 8.5.4 Limits in Scaling Bipolar Transistors for RF and Analog Applications 8.6 Comparing a SiGe-Base Bipolar Transistor with a GaAs HBT Exercises 437 437 440 440 44] 442 445 447 447 448 449 453 455 457 458 460 463 463 464 467 468 469 472 9 Memory Devices 476 9.1 Static Random-Access Memory 9.1.1 CMOS SRAM Cell 9.1.2 Other Bistable MOSFET SRAM Cells 9.1.3 Bipolar SRAM Cell 9.2 Dynamic Random-Access Memory 9.2.1 Basic DRAM Cell and Its Operation 9.2.2 Device Design and Scaling Considerations for a DRAM Cell 9.3 Nonvolatile Memory 9.3.1 MOSFET Nonvolatile Memory Devices 9.3.2 Flash Memory Arrays 9.3.3 Floating-Gate Nonvolatile Memory Cells 9.3.4 Nonvolatile Memory Cells with Charge Stored in Insulator Exercise 477 478 486 487 495 496 499 500 501 507 511 514 516 x Contents 10 Silicon-on-Insulator Devices 517 10.1 SOl CMOS 517 10.1.1 Partially Depleted SOl MOSFETs 518 10.1.2 Fully Depleted SOl MOSFETs 520 10.2 Thin-Silicon SOl Bipolar 523 10.2.1 Fully Depleted Collector Mode 524 10.2.2 Partially Depleted Collector Mode 526 10.2.3 Accumulation Collector Mode 527 10.2.4 Discussion 527 10.3 Double-Gate MOSFETs 529 10.3.1 An Analytic Drain Current Model for Symmetric DG MOSFETs 529 10.3.2 The Scale Length of Double-Gate MOSFETs 533 10.3.3 Fabrication Requirements and Challenges ofDG MOSFETs 534 10.3.4 Multiple-Gate MOSFETs 536 Exercise 537 Appendix 1 CMOS Process Flow 538 Appendix 2 Outline of a Process for Fabricating Modem n-p-n Bipolar Transistors 542 Appendix 3 Einstein Relations 543 Appendix 4 Spatial Variation of Quasi-Fermi Potentials 546 Appendix 5 Generation and Recombination Processes and Space-Charge Region Current 553 Appendix 6 Diffusion Capacitance of a p-n Diode 562 Appendix 7 Image-Force-Induced Barrier Lowering 569 Appendix 8 Electron-Initiated and Hole-Initiated Avalanche Breakdown 573 Appendix 9 An Analytical Solution for the Short-Channel Effect in Subthreshold 575 Appendix 10 Generalized MOSFET Scale Length Model 582 Appendix 11 Drain Current Model of a Ballistic MOSFET 588 Appendix 12 Quantum-Mechanical Solution in Weak Inversion 594 Appendix 13 Power Gain of a Two-Port Network 598 Appendix 14 Frequencies of a MOSFET Transistor 601 Appendix 15 DeterminatioIJ.,ofEmitter and Base Series Resistances 605 Appendix 16 Intrinsic-Base Resistance 610 Appendix 17 Energy-Band Diagram of a Si-SiGe n-p Diode 614 Appendix 18 IT and Imax of a Bipolar Transistor 617 References 623 Index 644 Preface to the first edition It has been fifty years since the invention of the bipolar transistor, more than forty years since the invention of the integrated~circuit (IC) technology, and more than thirty-five years since the invention ofthe MOSFET. During this time, there has been a tremendous and steady progress in the development of the IC technology with a the IC industry. One distinct characteristic in the evolution ofthe IC tecnnOlogy physical feature sizes of the transistors are reduced continually over time as the litho graphy technologies used to define these features become available. For almost thirty years now, the minimum lithography feature size used in IC manufacturing has been reduced at a rate ofO.7x every three years. In 1997, the leading-edge IC products have a minimum feature size of 0.25 1Jll1. The basic operating principles oflarge and small transistors are the same. However, the relative importance of the various device parameters and performance factors for tran sistors of the l-1Jll1 and smaller generations is quite different from those for transistors of larger-dimension generations. For example, in the case of CMOS, the power-supp voltage was lowered from the standard 5 V, starting with the 0.6- to 0.8-1Jll1 generation. Since then CMOS power supply voltage has been lowered in steps once every few years as the device physical dimensions are reduced. At the same time, many physical phenomena, such as short-channel effect and velocity saturation, which are negligible in large-dimension MOSFETs, are becoming more and more important in determining the behavior ofMOSFETs of deep-submicron dimensions. In the case of bipolar devices, breakdown voltage and base-widening effects are limiting their performance, and power dissipation is limiting their level of integration on a chip. Also, the advent of SiGe base bipolar technology has extended the frequency capability of small-dimension bipolar transistors into the range previously reserved for GaAs and other compound semiconductor devices. The purpose of this book is to bring together the device fundamentals that govern the behavior of CMOS and bipolar transistors into a single text, with emphasis on those parameters and eerformance factors that are particularly important for VLSI (very-large scale-integration) devices of deep-submicron dimensions. The book starts with a com prehensive review of the properties of the silicon material, and the basic physics ofp-n junctions and MOS capacitors, as they relate to the fundamental principles of MOSFET and bipolar transistors. From there, the basic operation of MOSFET and bipolar devices, and their design and optimization for VLSI applications are developed. A great deal of the volume is devoted to in-depth discussions of the intricate interdependence and subtle tradeoffs of the various device parameters pertaining to circuit performance and manu facturability. The effects which are particularly important in small-dimension devices, xii Preface to the first edition e.g., quantization of the two-dimensional surface inversion layer in a MOSFET device and the heavy-doping effect in the intrinsic base of a bipolar transistor, are covered in detail. Also included in this book are extensive discussions on scaling and limitations to scaling of MOSFET and bipolar devices. This book is suitable for use as a textbook by senior undergraduate or graduate students in electrical engineering and microelectronics. The necessary background assumed is an introductory understanding of solid-state physics and semiconductor physics. For practicing engineers and scientists actively involved in research and devel opment in the IC industry, this book serves as a reference in providing a body of knowledge in modem VLSI devices for them to stay up to date in this field. VLSI devices are too huge a subject area to cover thoroughly in one book. We have chosen to cover only the fundamentals necessary for discussing the design and optimiza tion of the state-of-the-art CMOS and bipolar devices in the sub-0.5-)Jl11 regime. Even then, the specific topics covered in this book are based on our own experience ofwhat the most important device parameters and performance factors are in modem VLSI devices. Many people have contributed directly and indirectly to the topics covered in this book. We have benefited enormously from the years of collaboration and interaction we had with our colleagues at IBM, particularly in the areas of advanced silicon-device research and development. These include Douglas Buchanan, Hu Chao, T. C. Chen, Wei Chen, Kent Chuang, Peter Cook, Emmanuel Crabbe, John Cressler, Bijan Davari, Robert Dennard, Max Fischetti, David Frank, Charles Hsu, Genda Hu, Randall Isaac, Khalid G. P. Li, Shih-Hsien Lo, Yuh-Jier Mii, Edward Nowak, George Sai-Halasz, Stanley Schuster, Paul Solomon, Hans Stork, Jack Sun, Denny Tang, Lewis Terman, Clement Wann, James Warnock, Siegfried Wiedmann, Philip Wong, Matthew Wordeman, Ben Wu, and Hwa Yu. We would like to acknowledge the secretarial support of Barbara Grady and the support of our management at IBM Thomas J. Watson Research Center where this book was written. Finally, we would like to give special thanks to our families _ Adrienne, and Brenda Ning and Betty, Ying, and Hsuan Taur for their support and understanding during this seemingly endless task. Yuan Taur Tak H. Ning Yorktown Heights, New York, October, 1997 Preface to the second edition Since the publication of the first edition of Fundamentals ofModern VLSI Devices by Cambridge University Press in 1998, we received much praise and many encouraging reviews on the book. It has been adopted as a textbook for first-year graduate courses on microelectronics in many major universities in the United States and worldwide. The first edition was translated into Japanese by a team led by Professor Shibahara of Hiroshima University in 2002. During the past 10 years, the evolution and scaling of VLSI (very-Iarge-scale integration) technology has continued. Now, sixty years after the first invention of the transistor, the number of transistors per chip for both microprocessors and DRAM (dynamic random access memory) has increased to over one billion, and the highest clock frequency of microprocessors has reached 5 GHz. In 2007, the worldwide IC (integrated circuits) sales grew to $250 billion. In 2008, the IC industry reached the 45-nm generation, meaning that the leading-edge IC products employ a minimum lithography feature size of 45 nm. As bulk CMOS (complementary metal-oxide semiconductor field-effect transistor) technologies are scaled to dimensions below 100 nm, the very factor that makes CMOS technology the technology of choice for digital VLSI circuits, namely, its low standby power, can no longer be taken for granted. Not only has the off-state current gone up with the power supply voltage down scaled to the I V level, the gate leakage has also increased exponentially from quantum mechanical tunneling through gate oxides only a few atomic layers thick. Power management. both active and standby, has become a key challenge to continued increase ofclock frequency and transistor count in microprocessors. New materials and device structures are being explored to replace conventional bulk CMOS in order to extend scaling to IQnm. The purpose of writing the second edition is to update the book with additional material developed after the completion of the first edition. Key new material added includes MOSFET scale length theory and high-field transport model, and the section on SiGe-base bipolar devices has been greatly expanded. We have also expanded the discussions on basic device physics and circuits to include metal-silicon contacts, noise margin of CMOS circuits, and figures of merit for RF applications. Furthermore, two new chapters are added to the second edition. Chapter 9 is on memory devices and covers the fundamentals of read and write operations ofcommonly used SRAM, DRAM, and nonv.olatile memory arrays. Chapter 10 is on silicon-on-insulator (SOl) devices, including advanced devices of future potential. We would like to take this opportunity to thank all the friends and colleagues who gave us encouragement and valuable suggestions for improvement of the book. In particular, Professor Mark Lundstrom of Purdue University who adoptcd the first edition early on, xiv Preface to the second edition and Dr. Constantin Bulucea of National Semiconductor Corporation who suggested the treatment on diffusion capacitance. Thanks also go to Professor James Meindl ofGeorgia Institute of Technology, Professor Peter Asbeck of University of California, San Diego, and Professor Jerry Fossum of University of Florida for their support of the book. We would like to thank many of our colleagues at IBM, particularly in the areas of advanced silicon-device research and development, for their direct or indirect contribu tions. Yuan Taurwould like to thank many ofhis students at University ofCalifornia, San Diego, in particular Jooyoung Song and Bo Yu, for their help with the completion of the second edition. He would also like to thank Katie Kahng for her love, support, and patience during the course of the work. We would like to give special thanks to our families for their support and under standing during this seemingly endless task. Yuan Taur TakH. Ning June, 2008 Physical constants and unit conversions Description Electronic charge Boltzmann's constant Vacuum permittivity Silicon permittivity Oxide permittivity Velocity of light in vacuum Planck's constant Free-electron mass Thermal voltage (T= 300 K) Angstrom Nanometer Micrometer (micron) Millimeter Meter Electron-volt Energy = charge x voltage Charge = capacitance x voltage Power current x voltage Time = resistance x capacitance Current = charge/time Resistance = voltage/current Symbol q k eo f.:si eox c h rno kTlq A nm IJl1l mm m eV E=qV Q=CV P IV t=RC I= Qlt R VII Value and unit 1.6xlO-19 C 1.38 x 10-23 JIK 8.85 x 1O-14 F/cm 1.04 x 1O-12 F/cm 3.45 x 1O-13 F/cm 3 x 1010 cm/s 6.63 x 10-34 J-s 9.1 x 10-31 0.0259 V lA 1O-s cm 1nm= 10-7 cm IIJl1l = 10-4 cm 1mm=O.l em 1m= lO2cm leV= 1.6 x 10-19 J Joule = Coulomb x Volt - Coulomb = Farad x Volt Watt.= ~pere x Volt n ~econd = (ohm) x !::arad Ampere = Coulomb/second n (ohm) .:'{oltlAmpere Aword ofcaution about the length units: strictly speaking, MKS units should be used for all the equations in the book. As a matter ofconvention, electronics engineers often work with centimeter as the unit oflength. While some equations work with lengths in either meter or centimeter, not all ofthem do. It is prudent always to check for unit consistency when doing calculations. It may be necessary to convert the length unit to meter before plugging into the equations. List of symbols Symbol A a aa aF aR aT an ap BV BVCBO BVCEO BVEs'o P flo p,., c C Cd Cd,lol CdBC CdBE,/ol Cdm CD Description Area Emitter area Common-base current gain Static common-base current gain Forward common-base current gain in the Ebers-Moll model Reverse common-base current gain in the Ebers-Moll model Base transport factor Electron-initiated rate of electron-hole pair generation per unit distance Hole-initiated rate of electron-hole pair generation per unit distance Breakdown voltage Collector-base junction breakdown voltage with emitter open circuit Collector-emitter breakdown voltage with base open circuit Emitter-base junction breakdown voltage with collector open circuit Current gain Static common-emitter current gain Forward common-emitter current gain in the Ebers-Moll model Reverse common-emitter current gain in the Ebers-Moll model Velocity in vacuum (= 3 x em/s) Capacitance Depletion-layer capacitance per unit area Total depletion-layer capacitance Base·-collector diode depletion-layer capacitance per unit area Total base·-~ollector diode depletion-layer capacitance Base-emitter diode depletion-layer capacitance per unit area Total base-emitter diode depletion-layer capacitance Maximum depletion-layer capacitance (per unit area) Diffusion capacitance Unit cm2 cm2 None None None None None cm-! cm-l v V V V None None None None cm/s F F/cm2 F F F/cm2 F F (F/cm2) F List of symbols xvii CDn CDp CDE CFC Cg CG Cj Cit Cj CL Cin Cinv Cmin COUI Cov Cox Cp Csi Cw Cil d Dn DnB Dp DpE AV, AEg AEg,SiGe AI AQtotal E Ec Eo Diffusion capacitance due to excess electrons Diffusion capacitanC'ellue to excess holes Emitter diffusion capacitance Equivalent density-of-states capacitance MOS capacitance at flat band per unit area Capacitance between the floating gate and the control gate of a MOSFET nonvolatile memory device Intrinsic gate capacitance per unit area Total gate capacitance of MOSFET Inversion-layer capacitance per unit area Interface trap capacitance per unit area Junction capacitance per unit area Junction capacitance Load capacitance Equivalent input capacitance of a logic gate MOSFET capacitance in inversion per unit area Minimum MOS capacitance per unit area Equivalent output capacitance ofa logic gate Gate-to-source (-drain) overlap capacitance (per edge) Oxide capacitance per unit area Polysilicon-gate depletion-layer capacitance per unit area Silicon capacitance per unit area Wire capacitance per unit length Base-emitter capacitance in the small-signal hybrid-x equivalent-circuit model Base-collector capacitance in the small-signal hybrid-x equivalent-circuit model Width of diffusion region in a MOSFET Electron diffusion coefficient Electron diffusion coefficient in the base ofan n-p-n transistor Hole diffusion coefficient Hole diffusion coefficient in the emitter ofan n-p-n transistor Threshold voltage rolloff due to short-channel effect Apparent bandgap narrowing Bandgap-narrowing parameter in the base region Maximum bandgap narrowing due to the presence of Ge Local bandgap narrowing due to the presence ofGe Channel length modulation in MOSFET Total charge stored in a nonvolatile memory device Energy Conduction-band edge Valence-band edge Ionized-acceptor energy level F F F F/cm2 F F/cm2 F F/cm2 F/cm2 F/cm2 F F F F/cm2 F/em2 F F F/cm2 F/cm2 F/cm2 F/em F F em cm 2/s cm2/s em2/s cm2/s V J J J ] cm C J J J J xviii Ust of symbols Ionized-donor energy level J Ef Fermi energy level J Eg Energy gap of silicon J E; Intrinsic Fermi level J Fermi energy level on the n-side of a p-n diode J Efp Fermi energy level on the p-side of a p-n diode 'iff Electric field J V/cm Critical field for velocity saturation 'iffeff Effective vertical field in MOSFET 'iffox Oxide electric field V/cm Vlcm V/cm 'iffs Electric field at silicon surface Vlcm 'iffx Vertical field in silicon V/cm 'iffy Lateral field in silicon eo Vacuum permittivity (= 8.85 x 10-14 F/em) V/cm F/cm G; Permittivity of gate insulator eSi Silicon permittivity (= 1.04 x 1O-12 F/cm) eax Oxide permittivity (= 3.45 x 10-13 F/cm) F/cm F/em F/cm fD Probability that an electronic state is filled None f Frequency, clock frequency Hz fmax Unity power gain frequency Hz fr Unity current gain frequency Hz FI Fan-in None FO Fan-out None 4> Barrier height V 4>ox Silicon-silicon dioxide interface potential barrier fo~ electrons V 4>ms Work-function difference between metal and silicon V 4>0 Electron quasi-Fermi potential V 4>p Hole quasi-Fermi potential V 4>sn Schottky barrier height for electrons V 4>Bp Schottky barrier height for holes V g Number of degeneracy None gds Small-signal output conductance AIV gm Small-signal transconductance AIV GE Emitter Gummel number s/cm4 Gs Base Gummel number s/cm4 Gn Electron emission rate (also called electron generation rate) I/cm3-s Gp Hole emission rate (also called hole generation rate) lIcm3-s y Emitter injection efficiency h Planck's constant (= 6.63 x 10-34 J-8) None J-s Time-dependent current A is Time-dependent base current in a bipolar transistor A h Time-dependent small-signal base current A ie Time-dependent collector current in a bipolar transistor A Ust of symbols xix ie Time-dependent small-signal collector current A ie Time-dependent-emitter current in a bipolar transistor A I Current A IB Static base current in a bipolar transistor A Ie Static collector current in a bipolar transistor A h Static emitter current in a bipolar transistor A Is Switch current in an EeL circuit A Ig Gate current in a MOSFET A 10 MOSFET current per unit width to length ratio for threshold A definition Idsot MOSFET saturation currerit A Ion MOSFET on current A IOff MOSFET off current A In nMOSFET current per unit width Ncm Ip pMOSFET current per unit width Nem IN nMOSFET current A Ip pMOSFET current A Ids Drain-to-source current in a MOSFET A Isx Substrate current in a MOSFET A Ids,Vt MOSFET current at threshold A 100.n nMOSFET on current per device width Ncm looN nMOSFET on current A Ion.p pMOSFET on current per device width A/cm IonP pMOSFET on current A A. MOSFET scale length J Current density is Base current density ic Collector current density in Electron current density ip Hole current density k Boltzmann's constant (= 1.38 x 10-23 JIK) cm Ncm2 Ncm2 Ncm2 Ncm2 Ncm2 11K K Scaling factor (> 1) None Mean free path cm L Length, MOSFET channel length cm LD Debye length em Ln Electron diffusion length em Lp Hole diffusion length cm Lmet Metallurgical ehannellength of MOSFET cm Leff Effective channel length of MOSFET em Lw Wire length m MOSFET body-effect coefficient mo Free-electron mass (= 9.1 x 10--31 kg) cm None kg m* Electron effective mass kg xx List of symbols M mI mt I-l I-leff fl.,. I-lp n no ni nie nieB nieE n" np Na Nd Nb Nc NB Nc NE N(E) P Po Pn Pp P Pac Pojf q Q QB QB,/ol QBE QBE,/Ol QBC QBC,/o/ Avalanche multiplication factor Electron effective mass in the longitudinal direction Electron effective mass in the transverse direction Carrier mobility Effective mobility Electron mobility Hole mobility Density of free electrons Density of free electrons at thermal equilibrium Intrinsic carrier density Effective intrinsic carrier density Effective intrinsic carrier density in base ofbipolar transistor Effective intrinsic carrier density in emitter ofbipolar transistor Density of electrons in n-region Density of electrons in p-region Acceptor impurity density Donor impurity density Impurity concentration in bulk silicon Effective density of states of conduction band Effective density of states of valence band Base doping concentration Collector doping concentration Emitter doping concentration Density of electronic states per unit energy per volume Density of free holes Density of free holes at thermal equilibrium Density of holes in n-region Density of holes in p-region Power dissipation Active power dissipation Standby power dissipation Electronic charge (= 1.6 x 10- 19 C) Charge Excess minority charge per llllit area in the base Total excess minority charge in the base Excess minority charge per unit area in the base-emitter space-charge region Total excess minority charge in the base-emitter space- charge region Excess minority charge per llllit area in the base-collector space-charge region Total excess minority charge in the base-collector spacecharge region None kg kg cm2N-s cm2N-s cm2N-s cm2N-s cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 cm-3 l/J-m3 cm-3 cm-3 cm-3 cm-3 W W W C C C/cm2 C C/cm2 C C/cm2 C List of symbols xxi QDE QE QE,to/ QpB Q$ Qd Qi Qf Qg Qm Qit Q" Qot Qox Qp r,R rb rbi rbx rc r. ro r" RL Rs ~ R" Rp Rsd Rch Rw RSbi Rsw Rswn Rswp p Psh Pen Psd Pc Total stored minority-carrier charge in a bipolar transistor biased in the .forward-active mode Excess minority charge per llllit area in the emitter Total excess minority charge in the emitter Hole charge per unit area in base of n-p-n transistor Total charge per llllit area in silicon Depletion charge per unit area Inversion charge per llllit area Fixed oxide charge per llllit area Charge on MOS gate per llllit area Mobile charge per llllit area Interface trapped charge per unit area Excess electron charge per llllit area Oxide trapped charge per llllit area Equivalent oxide charge density per llllit area Excess hole charge per unit area Resistance Base resistance Intrinsic base resistance Extrinsic base resistance Collector series resistance Emitter series resistance Output resistance in small-signal hybrid-1r equivalent-circuit model Input resistance in small-signal hybrid-1r equivalent-circuit model Load resistance in a circuit Source series resistance Drain series resistance Electron capture rate (also called electron recombination rate) Hole capture rate (also called hole recombination rate) Source-drain series resistance MOSFET channel resistance Wire resistance per llllit length Sheet'resistance of intrinsic-base layer Equivalent switching resistance of a CMOS gate Equivalent switching resistance of nMOSFET pulldown Equivalent switching resistance ofpMOSFET pullup Resistivity Sheet resistivity Sheet resistivity of MOSFET channel Sheet resistivity of source or drain region Specific contact resistivity C C/cm2 C C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 C/cm2 Q Q Q Q Q Q Q Q Q Q n 1/cm3-s l/cm3-s n Q ntcm nto Q n n n-cm nto nto nto n_cm2 xxii Ust of symbols Pne, Volume density of net charge C/cm3 S MOSFET inverse subthreshold current slope Vldecade Sp Surface recombination velocity for holes cm/s (h Lateral straggle of Gaussian doping profile em t Time s tB Base transit time s tE Emitter transit time s tBE Base-emitter depletion-layer transit time s tBC Base--collector depletion-layer transit time s ti Thickness of gate insulator cm tinv Equivalent oxide thickness for inversion charge calculations cm tox Oxide thickness cm tr Transit time s tw Thickness of wire cm lsi Thickness of silicon film cm ,T , Absolute temperature Lifetime Circuit delay K s s 'b Buffered delay s Lint Intrinsic, unloaded delay s 'F Forward transit time of bipolar transistor Tn Electron lifetime s Tn nMOSFET pulldown delay s 'ne Electron lifetime in base of n-p-n transistor s 'p Hole lifetime s 'p pMOSFET pullup delay s 'pE Hole lifetime in emitter ofn-p-n transistor s 'R Reverse transit time of bipolar transistor s 'w Wire RC delay s 'E Emitter delay time s fB Base delay time s 'BE Base-emitter depletion-region delay time s 'BC Base--collector depletion-region delay time U Net recombination rate s l / c m3 -s v Velocity cm/s v Small-signal voltage V V,h Thermal velocity cm/s Vd Carrier drift velocity cm/s Vsat Saturation velocity of carriers cm/s Vr Thermal injection velocity at MOSFET source cm/s V Voltage V V Quasi-Fermi potential along MOSFET channel V VA Early voltage V Ust of symbols xxiii v.,pp Va~p VeE Vec VCE VCG VFG Vdd Vds Vdsat Vjb Vox Vg Vgs Vbs V, Von "in VOUI Vx V"high v,,/ow W Wn Wp WB Wd WdBE WaBc Warn WE Ws WD w Xj Xc,Xj If' If'B IfIbi If't lfIi If's Applied voltage across p-n diode Applied voltage.appearing immediately across p-n junction (smaller than v.,pp by IR drops in series resistances) Base-ernitter bias voltage Base-<;ollector bias voltage Collector-to-emitter voltage Control gate voltage in a nonvolatile memory device Floating gate voltage in a nonvolatile memory device Power-supply voltage Source-to-drain voltage MOSFET drain saturation voltage Flat-band voltage Potential drop across oxide Gate voltage in MOS Gate-to-source voltage in a MOSFET MOSFET body bias voltage Threshold.voltage (21f1B definition) Linearly extrapolated threshold voltage Input node voltage of a logic gate Output node voltage of a logic gate Node voltage between stacked nMOSFETs of a NAND gate The higher threshold voltage ofa nonvolatile memory device The lower threshold voltage of a nonvolatile memory device Width, MOSFET width nMOSFET width pMOSFET width Intrinsic-base width Depletion-layer width Base-emitter junction depletion-layer width Base-<;ollector junction depletion-layer width Maximum depletion-layer width in MOS Emitter-layer width (thickness) Source junction depletion-layer width Drain junction depletion-layer width Angular frequency Junction depth Depth of inversion channel Potential Difference between Fermi potential and intrinsic potential Built-in potentia] Fermi potential Intrinsic potential Surface potential V V V V V V V V V V V V V V V V V V V V V V cm em cm em cm cm cm cm cm cm em radls em em V V Y V V V 1 Introduction Since the invention of the bipolar transistor in 1947, there has been an unprecedented growth ofthe semiconductor industry, with an enormous impact on the way people work and live. In the last thirty years or so, by far the strongest growth area of the semicon ductor industry has been in silicon very-Iarge-scale-integration (VLSI) technology. The sustained growth in VLSI technology is fueled by the continued shrinking of transistors to ever smaller dimensions. The benefits of miniaturization - higher packing densities, higher circuit speeds, and lower power dissipation - have been key in the evolutionary progress leading to today's computers, wireless units, and communication systems that offer superior performance, dramatically reduced cost per function, and much reduced physical size, in comparison with their predecessors. On the economic side, the integrated-circuit (IC) business has grown worldwide in sales from $1 billion in 1970 to $20 billion in 1984 and has reached $250 billion in 2007. The electronics industry is now among the largest industries in terms of o~tput as well as employment in many nations. The importance of microelectronics in economic, social, and even political development throughout the world will no doubt continue to ascend. The large world wide investment in VLSI technology constitutes a formidable driving force that will all but guarantee the continued progress in Ie integration density and speed, for as long as physical principles will allow. ._j 1.1 Evolution of VLSI Device Technology 1.1.1 Historical Perspective An excellent account of the evolution of the metal--oxide-semiconductor field-effect transistor (MOSFET), from its initial concept to VLSI applications in the mid 1980s, can be found in the paper by Sah (Sah, 1988). Figure 1.1 gives a chronology of the major milestone events in the development of VLSI techoology. The bipolar transistor technol ogy was developed early on and was applied to the first integrated-circuit memory in mainframe computers in the 1960s. Bipolar transistors have been used all along where raw circuit speed is most important, for bipolar circuits remain the fastest at the individual-circuit level. However, the large power dissipation of bipolar circuits has severely limited their integration level, to about 104 circuits per chip. This integration level is Quite low by today's VLSI standard. 2 1 Introduction 1.1 Evolution ofVLSI Device Technology 3 First bipolar transistor (1947) One-transistor DRAM cell invented (1968) First MOSFET (l960) VLSI era 1940 1950 1970 1980 1990 2000 2010 CMOS invented (1963) IC invented (1958) FITst micro processor (1971) Figure 1.1. A brief chronology of the major milestones in the development of VLSI. The idea ofmodulating the surface conductance ofa semiconductor by the application of an electric field was first reported in 1930. However, early attempts to fabricate a surface-field-controlled device were not successful because of the presence of large densities of surface states which effectively shielded the surface potential from the influence of an external field. The first MOSFET on a silicon substrate using SiOz as the gate insulator was fabricated in 1960 (Kahng and Atalla, 1960). During the 1960s and 1970s, n-channe1 and p-channel MOSFETs were widely used, along with bipolar tran sistors, for implementing circuit functions on a silicon chip. Although the MOSFET devices were slow compared to the bipolar devices, they had a higher layout density and were relatively simple to fabricate; the simplest MOSFETchip could be made using four masks and a single doping step. However, just like bipolar circuits, single-polarity MOSFET circuits suffered from large standby power dissipation, and hence were limited in the level of integration on a chip. The major breakthrough in the level of integration came in 1963 with the invention of CMOS (complementary MOS) (Wanlass and Sah, 1963),· in which n-channel and p-channel MOSFETs are constructed side by side on the same substrate. A CMOS circuit typically consists of an n-channel MOSFET and a p-channel MOSFET connected in series between the power-supply terminals, so that there is negligible standby power dissipation. Significant power is dissipated only during switching of the circuit (i.e., only when the circuits are active.) By cleverly designing thc "switch activities" of the circuits on a chip to minimize active power dissipation, engineers have been able to integrate hundreds of millions of CMOS .transistors on a single chip and still have the chip readily air-coolable. Until the minimum feature size of lithography reached 180 nm, the integra tion level of CMOS was not limited by chip-level power dissipation, but by chip fabrication technology. Another advantage of CMOS circuits comes from the ratioless, full rail-to-raillogic swing, which improves the noise margin and makes a CMOS chip easier to design. lE+l1 5 lE+10 IE+9 :.Qa. "8. IB+8 i 1E+7 'Vj .g.c.. lE+6 0 "" lE+5 lE+4 iP!Aiill IMPul 2 E 2 "N 'Vj e 0.5 ~ 107 1600-1700 0.014 1.0 0.006 0.5 x 10-6 let N(E) dE be the number of electronic states per unit volume with an energy between E and E+ dE in the conduction band, then N(E) dE = 2g dpx dPy dp= h3 ' (2.1) where dpx dpy dpz is the volume in the momentum space within which the electron energy lies between E and E + dE, g is the number ofequivalent minima in the conduction band, and the factor of two arises from the two possible directions of electron spin. The conduction band of silicon has a sixfold degeneracy, so g = 6. Note that MKS units are used here (e.g., length must be in meters, not centimeters). If the electron kinetic energy is not too high, one can consider the energy-momentum relationship near the conduction-band minima as being parabolic and write p2 2 E Ec = + -Y +..!!L. (2.2) 2m). 2m,' where E - Ec is the electron kinetic energy, and nix, nip mz are the effective masses. The constant energy surface in momentum space is an ellipsoid with the lengths of the symmetry axes proportional to the square roots of nix, mY' and m,. For the silicon conduction band in the <100> direction, two of the effective masses are the transverse mass mt = O.19mo, and the third is the longitudinal massm,= 0.92mo, where mo is the free electron mass. The volume ofthe ellipsoid given by Eq. (2.2)in momentum space is (4m3) (8m"m..,mz)1/2(E- Ec)312. Therefore, the volume dPxdpydpz within which the electron energy lies between E and E + dE is 41t(2m"m..,mz)Jl2(E- Ee)1I2dE and Eq. (2.1) becomes 14 2 Basic Device Physics 2.1 Electrons and Holes in Silicon 15 E +E +E 1 Conduction band -- ~ ---~·r- 1 ; Figure 2.2. j Valence :..:...:..::.=-------,------:----- band N(E) -1/-2 ID(E) N(E)ID(E) Schematic plots of density of states, Fermi-Dirac distribution function, and their products versus electron energy in a band diagram. (After Sze, 1981.) N(E) dE = 8ngv2m m, m7 ,-,x } - ~ y E - Ee dE = 8ngJ2m2 m[ L1 t ~ Y E - Ee dE. (2.3) The 3-D electron density of states in an energy diagram is then a parabolic function with its downward apex at the conduction-band edge, and vice versa for the hole density of states in the valence band. These are shown schematically in Fig. 2.2 (Sze, 1981). 2.1.1.3 Statistical Distribution Function The energy distribution of electrons in a solid is governed by the laws of Fermi-Dirac statistics. For a system in thermal equilibrium, the principal result of these statistics is the Fermi-Dirac distribution fimction, which gives the probability that an electronic state at energy E is occupied by an electron, !D (E) = ---= (2.4) Here k= 1.38 x 10-23 JIK. is Boltzmann's constant, and Tis the absolute temperature. This function contains a parameter, Eft called the Fermi level. The Fermi level is the energy at which the probability of occupation ofan energy state by an electron is exactly one-half. At absolute zero temperature, T=O K, all the states below the Fermi level are filled UD= I for E < Ef), and all the states above the Fermi level are empty UD = 0 for E > Ef). At finite temperatures, some states above the Fermi level are filled as some states below become empty. In other words, the probability distribution!D(E) makes a smooth transition from unity to zero as the energy increases across the Fermi level. The width of the transition is governed by the thermal energy, kT. This is plotted schematically in Fig. 2.2, with a Fermi level in the middle of the forbidden gap (for reasons that will soon be clear). It is important fo to keep in mind that the thermal energy at room temperature is 0.026 eV, or roughly of the silicon bandgap. In most cases when the energy is at least several kT above or below the Fermi level, Eq. (2.4) can be approximated by the simple formulas !D(E) ~ e-(E-Er)/kT for E > Ef and !D (E) ~ 1- e-(Er-E)/kT for E Ep, thenfDI(E) > fD2(E), which means that at every energy E where electronic states are available in both systems, a larger fraction of the states in system I are occupied by electrons than in system 2. Equivalently, a larger fraction of the states in system 2 are empty than in system I at energies where electronic states exist. Since the two systems in contact are free to exchange electrons, there is a higher probability for the electrons in system I to re-distribute to system 2 than vice versa. This leads to a net electron transport from system I to system 2, i.e., current flows (defined in terms ofpositive charges) from system 2 to system I. If there are no power sources connected to the systems to sustain the Fermi level imbalance, eventually the two systems will come to an equilibrium and EfJ = Ep. No further net electron flow takes place once the same fractions ofthe electronic states in the two systems are occupied at every energy E. Note that this conclusion is reached regardless of the specific density of states in each of the two systems. For example, the two systems can be two metals, a metal and a semiconductor, two semiconductors of different doping or different composition. When two systems are in thermal equilibrium with no current flow between them, their Fermi levels must be equal. A direct extension is that, for a continuous region of metals and/or semiconductors in contact, the Fermi leJJel at thermal equilibrium is flat, i.e., spatially constant, throughout the region. The role of Fermi level at the contacts when there is an applied voltage driving a steady-state current is further discussed in Section 2.1.4.5. 2.1.1.4 Carrier Concentration Since fD(E) is the probability that an electronic state at energy E is occupied by an electron, the total number ofelectrons per unit volume in the conduction band is given by n = lEro,o N(E)fD(E)dE. (2.7) Here the upper limit of integration (the top of the conduction band) is taken as infinity. Both the product N(E)fD(E) and n, p are shown schematically in Fig. 2.2. In general, Eq. (2.7) is a Fermi integral of the order 112 and must be evaluated numerically (Ghandhi, 1968). For nondegenerate silicon with a Fermi level at least 3kT/q below the edge of the 16 2 Basic Device Physics 2.1 Electrons and Holes in Silicon 17 conduction band, the Penni-Dirac distribution function can be approximated by the Maxwell-Boltzmann distribution, Eq. (2.5). Equation (2.7) then becomes r"; V n = 8ng~ E - Ece-(E-Ej)/kTdE. (2.8) hiE, With a change ofvariable, the integral can be expressed in the fonn of a gamma function, r(3/2), which equals nll2l2. The electron concentration in the conduction band is then n = Nce-(E,-Ef)/kT, (2.9) where the pre-exponential factor is defined as the effective density ofstates, Nc = 2 g V; ; ; ; 1 ;m;2/ (2nkT) h2 3(2 A similar expression can be derived for the hole density in the valence band, (2.lO) p = Nve-(Er-E,)/kT, (2.11 ) where Nv is the effective density of states of the valence band, which depends on the hole effective mass and the valence band degeneracy. Both Nc and Nvare proportional to r3J2. Their values at room temperature are listed in Table 2.1 (Green, 1990). Por an intrinsic silicon, n = p, since for every electron excited into the conduction band, a vacancy or hole is left behind in the valence band. The Penni level for intrinsic silicon, or the intrinsic Fermi level, Ei, is then obtained by equating Eq. (2.9) and Eq. (2.11) and solving for Ef £. = Ef= Ec + Ev _ kTln(Nc) I 2 2 Nv ' (2.12) By substituting Eq. (2.12) for Ef in Eq. (2.9) or Eq. (2.11), one obtains the intrinsic carrier concentration, ni = n = p: ni = VNcNve-(E,-E,,)/2kT = VNcN,.e-Eg/2kT. (2.13) Since the thennal energy, kT, is much smaller than the silicon bandgap Eg , the intrinsic Fermi level is very close to the midpoint between the conduction band and the valence band. In fact, Ei is sometimes referred to as the midgap energy level, since the error in assuming Ei to be (Ec+ Ev)/2 is only about 0.3 kT. The intrinsic carrier concentration ni at room temperature is 1.0 x 1010 cm-3, as given in Table 2.1, which is very small compared with the atomic density of silicon. Equations (2.9) and (2.11) can be rewritten in tenns of ni and Ei : n = l1ie(ErEi)/kT, (2.14) p = nie(Ei-Er)/kT (2.15) These equations give the equilibrium electron and hole densities for any Penni level position (not too close tothe.band,edges) relative to the intrinsic 'Penni level at the midgap. In the next section, we will show how the Penni level varies with the type and concentration of impurity atoms in silicon. Since any change in Ef causes reciprocal changes in nand p, a useful, general relationship is that the product pn =n~ I in equilibrium is a constant, independent ofthe Fermi level position. (2.16) 2.1.2 n-Type and p-Type Silicon Intrinsic silicon at room temperature has an extremely low free-carrier concentration; therefore, its resistivity is very high. In practice, intrinsic silicon hardly exists at room temperature, since it,would require materials with an unobtainably high purity. Most impurities in silicon introduce additional energy levels in the forbidden gap and can be easily ionized to add either electrons to the conduction band or holes to the valence band, depending on where the impurity level is (Kittel, 1976). The electrical conductivity of silicon is then dominated by the type and concentration of the impurity atoms, or dopants, and the silicon is called extrinsic. 2.1.2.1 Donors and Acceptors Silicon is a column-IV element with four valence electrons per atom. There are two types of impurities in silicon that are electrically active: those from column V such as arsenic or phosphorus, and those from column III such as boron. As is shown in Pig. 2.3, a column-V atom in a silicon lattice tends to have one extra electron loosely bonded after fonning covalent bonds with other silicon atoms. In most cases, the thennal energy at room temperature is sufficient to ionize the impurity atom and free the extra electron to the conduction band. Such types of impurities are called donors; they become positively charged when ionized. Silicon material doped with column-V impurities or donors is '0'0'0' '0'®-0' ;0 0=0: • 1 .. 1• I• • I• 1• I• •• -q• •• '0:0 0 0:6:0: :0 6:0 ',' •• O+q •• '0:0:0 0:0 0 0 0:0 Figure 2.3. (a) (b) (c) Three basic bond pictures of silicon: (a) intrinsic Si with no impurities, (b) n-type silicon with donor (Phosphorus), (c) p-type silicon with acceptor (boron), (After Sze, 1981.) 18 2 Basic Device Physics ,_. -. Ed Ee Ef Eg E; - -Ei Ev --• • • • • _. ~f E. Ev Figure 2.4. • Free electron H o Free hole (+) (a) n-type (b) p-type Energy-band diagram representation of (a) donor level Ed and Fermi level Efin n-type silicon, (b) acceptor level Ea and Fermi level Ejin p-type silicon. called n-type silicon, and its electrical conductivity is dominated by electrons in the conduction band. On the other hand, a column-III impurity atom in a silicon lattice tends to be deficient by one electron when forming covalent bonds with other silicon atoms 2.3). Such an impurity atom can also be ionized by accepting an electron from the valence band, which leaves a free-moving hole that contributes to electrical conduction. These impurities are called acceptors; they become negatively charged when ionized. Silicon material doped with column-III impurities or acceptors is called p-type silicon, and its electrical conductivity is dominated by holes in the valence band. It should be noted that impurity atoms must be in a substitutional site (as opposed to interstitia/) in silicon in order to be electrically active. In terms ofthe energy-band diagrams in 2.4, donors add allowed electron states in the bandgap close to the conduction-band edge, while acceptors add allowed states just above the valence-band Donor levels contain positive charge when ionized (emp tied). Acceptor levels contain negative charge when ionized (filled). The ionization energies are denoted by Ed for donors and Ea-- Ev for acceptors, respectively. Figure 2.5 shows the donor and acceptor levels of common impurities in silicon and their ionization energies (Sze, 1981). Phosphorus and arsenic are commonly used donors, or n-type dopants, with low ionization energies on the order of 2kT, while boron is a used acceptor or p-type dopant with a comparable ionization energy. Figure 2.6 shows the solid solubility of important impurities in silicon as a function of annealing temperature (Trumbore, 1960). Arsenic, boron, and phosphorus have the highest solid solubility among all the impurities, which makes them the most important species in VLSI technology. !I -,,:10 ~I ~I< II :;:1 !:I ::; Vi I I "r1-:I I' I ;:1iMiO ~I I 0:::;, I' ~I :S10 &11 ":1 ~I ~I ~I 10 ;;':<)1'1"< I "'10 I "'10 I I ;:';~IO .~ ;:';1 ;:1i11'0 0 81 ~II ":1 :;;I~ 1:Sl ~I :E :E '."0, 1018 ~ Vl 1017 1016 Figure 2.6. lOIS 500 600 700 800 900 1000 11 00 1200 1300 1400 T("C) Solid solubility of various elements in silicon as a function of temperature. (Afief Trumbore, 1960.) 2.1.2.2 Fermi Level in Extrinsic Silicon In contrast to intrinsic silicon, the Fenni level in an extrinsic silicon is not located at the midgap. The Fenni level in n-type silicon moves up towards the conduction band, consistent with the increase in electron density as described by Eq. (2.9). On the other hand, the Fenni level in p-type silicon moves down towards the valence band, consistent with the increase in hole density as described by Eq. (2.11). These cases are depicted in 1:1 Fig. 2.4. The exact position ofthe Fenni level depends on both the ionization energy and the concentration of dopants. For example, for an n-type material with a donor impurity concentration N.J. the charge neutrality condition in silicon requires that n N"d +p, where N"d is the density of ionized donors given by N:; (I - N,tli - fD(Ed)] = Nd --;---',.-;0;--:::-:-;-:-::: 1+ (2.17) (2.18) 2.1 Electrons and Holes in Silicon 21 since the probability that a donor state is occupied by an electron (i.e., in the neutral state) is fD(Ed). The factor! in tlie denominator offD(Ed) arises from the spin degeneracy (up or available electronic states associated with an ionized donor level] (Ghandhi, 1968). Substituting Eq. (2.9) and Eq. (2.11) for nand pin Eq. (2.17), one obtains N ce-(E,.-E11/kT Nd + (2.19) which is an algebraic equation that can be solved for In n-type silicon, electrons are the majority current carriers, while holes are the minority current carriers, which means that the second tenn on the right-hand side (RHS) of Eq. (2.19) can be neglected. For shallow donor impurities with low to moderate concentration at room temperature, (NdiNe) exp [(Ee - Ed) Ik 11 « I, a good approximate solution for (Z:). Ec Ef = kTln (2.20) In this case, the Fenni level is at least a few kTbelow and essentially all the donor N'd levels are empty (ionized), i.e., n = n;, It was shown earlier (Eq. (2.16» that, in equilibrium, the product of majority and minority carrier densities equals independent of the dopant type and Fenni level position. The hole density in n-type silicon is then given by p=niINd. Likewise, for p-type silicon with a shallow acceptor concentration given by (Z:) - Ev = kTIn (2.21) the Fermi level is (2.22) the hole density is p N;; Nu , and the electron density is n n7lNa . (2.23) Figure 2.7 plots the Fenni-Ievel position in the energy gap versus temperature for a wide range of impurity concentration (Grove, 1967). The slight variation of the silicon bandgap with temperature is also incorporated in the figure. It is seen that as the temperature increases, the Fenni level approaches the intrinsic value near midgap. When the intrinsic carrier concentration becomes larger than the doping concentration, the silicon is intrinsic. In an intennediate range of temperature including room tempera ture, all the donors or acceptors are ionized. The majority carrier concentration is then given by the doping concentration, independent of temperature. For temperatures below this range, freeze-out occurs, i.e., the thennal energy is no longer sufficient to ionize all the impurity atoms even with their shallow levels 1981). In this case, the Detailed study showed that there are no other degeneracy with the electronic ground state in a donor except for spin (Ning and Sah, 1971). 22 2 Basic Device Physics 0.6 Conduction-band edge Ec 0.4 0.2 ;; .!', ~- 0 I "-1..... -0.2 -0.4 Figure 2.7. -0.6 L 0 100 200 300 400 500 Temperature (K) The Fenni level in silicon as a function of temperature for various impurity concentrations. (After Grove, 1967.) majority-carrier concentration is less than the doping concentration, and one would have to solve Eq. (2.19) numerically to find Efi n, and p (Shockley, 1950). Instead of using Ne, Nv and referring to and Ev, Eq. (2.20) and Eq. (2.22) can be written in a more useful form in terms of nj and Ej defined by Eq. (2.12) and Eq. (2.13): Er Ei kTln(~~) (2.24) for n-type silicon, and E; - Ef= kTln(~;') (2.25) for p-type silicon. In other words, the distance between the Fermi level and the intrinsic Fermi level near the midgap is a logarithmic function ofdoping concentration. These expressions will be used extensively throughout the book. 2.1.2.3 Fermi Level in Degenerately Doped Silicon For heavily doped silicon, the impurity concentration Nd or Na can exceed the effective density ofstates Nc or N", so that Ec or Ef ,,)/kT I . (2.67) nl It equals when tPP tPn 'IIf. Quasi-Fermi potentials are used extensively in the rest of the book for current calculations. 2.1.4.7 Continuity Equations The next set of equations are continuity equations based on the conservation of mobile charge: an _ - ~ q oaJx n R" + G" (2.68) 2 While it appears to be physically inconsistent to have half of the electron stales occupied at one energy and half oflhe electron slates empty at a different energy, quasi-Fcmli levels are defined mainly for mathematical convenience. 34 2 Basic Device Physics and ~ot ~ 0, (2.69) where Gn and Gp are the electron and hole generation rates, Rn and Rp are the electron a and hole recombination rates, and 0 J,/ox and Jlax are the net flux of mobile charges in and out of x. At thermal equilibrium, the generation rate is equal to the recombination rate and np = n;. When excess minority carriers are injected by light or other means, the recombination rate exceeds the generation rate, which establishes a tendency to return to equilibrium. In silicon, the probability ofdirect band-to-band recombination by a radiative (transfer of energy to a photon) or Auger (transfer of energy to another carrier) process is very low due to its indirect bandgap. Most of the recombination processes take place indirectly via a trap or a deep impurity level near the middle of the forbidden gap. This is often referred to as the Shockley-Read recombination (Shockley and Read, 1952). Under low-injection conditions, the recombination rate is inversely proportional to the minority-carrier time, 1:, which is in the range of 10-4 to 10-9 s, depending on the quality of the silicon crystal. The minority-carrier diffusion length, which is the average distance a minority carrier travels before it recombines with a majority carrier, is given by L '" (lh)ll2, where D is the diffusion coefficient. The diffusion length is typically a few microns to a few millimeters in silicon. (A discussion of the minority-carrier diffusion process can be found in Section 2.2.4.) Since L is much larger than the active dimensions ofa VLSI device, generation-recombination in general plays very little role in device operation. Only in a few special circumstances, such as CMOS latch-up, the SOl floating-bod effect, junction leakage current, and radiation-induced soft error, must the cr..nprnt;nn_ recombination mechanism be taken into account. More detailed discussions on generation and recombination can be found in Appendix 5. In the steady state, an/at apia! = 0. Also, the net electron reduction rate must equal the net hole reduction rate, Gn = Rp- Gp, so that there is no buildup ofnet immobile charge with time at any point. Subtracting Eq. (2.69) from Eq. (2.68) then yields (Xln +Jp)/ax = 0, or continuity ofthe total current, I n +Jp• In a device region where generation and recombi nation are negligible, the continuity equations in the steady state are reduced to dJ,/dx dJ/dx 0, which simply states the conservation of electron current and conservation of hole current, respectively. 2.1.4.8 Dielectric Relaxation Time In contrast to the minority-carrier lifetime discussed above, the majority-carrier response time is very short in a semiconductor. It can be estimated for a one-dimensional (I-D) homogeneous n-type silicon as follows. Suppose there is a local perturbation in the carrier density, iln. From Poisson'8 equation, the resulting charge imbalance sets up a field a'it/fu: around the point of perturbation. This, in tum, leads to according to Ohm's law,}" = 'it/Pm which tends to restore the majority carrier concentration back to its equilibrium, charge neutral value. Neglecting and Gn in the continuity equation, Eq. (2.68), one then obtains 2.2 p-n Junctions 35 o6,.n 1oJ" 1 o'it 6,.n ot q8x- qpn Pnilsi (2.70) The solution to this equation takes the form of 6,.n (t) ex where Pnesi is the majority-carrier response time, 'or dielectric relaxation time. The majority-carrier response time in silicon is typically on the order of 10-12 s, which is shorter than most device switching times. Note that Pnesi is the minimum response time for an ideal I-D case without any parasitic capacitances. In practice, the majority-carrier response time may be limited the RC delay of the specific silicon device structure and contacts. 2.2 2.2.1 p-n Junctions p-n Junctions, also called Jrn diodes, are important devices as well as important components of all MOSFET and bipolar devices. The characteristics of p-n diodes are therefore important in determining the characteristics ofVLSI devices and circuits. A p-n is formed when one region of a semiconductor substrate is doped n-type and an immediately adjacent region is doped p-type. In practice, a silicon p-n diode is usually local region ofa larger region ofdoped silicon. For instance, a region of a p-type silicon substrate or "well" can be counterdoped with n-type impurities to form the n-type region of a p--n diode. The n-type region thus formed has a donor concentration higher than its acceptor concentration. A doped semiconductor region is called compensated if it contains both donor and acceptor impurities such that neither impurity concentration is negligible compared to the other. For a compensated semiconductor region, it is the net doping concentration, Nd Na if it is n-type and Na - Nd if it is p-type, that determines its Fermi level and its mobile carrier concentration. However, for simplicity, we shall derive the char acteristics and behavior ofp-n diodes assuming none of the doped regions are compen sated, i.e., the n-sides ofthe diodes have a net donor concentration of Nd and the p-sides have a net acceptor concentration of No- The resultant equations can be extended to diodes with compensated doped regions simply by replacing Nd by Nd - Na for the n-regions and replacing No by No - Nd for the p-regions. Energy-Band Diagrams for a p-n Diode It was shown in Sections 2.1.1.3 and 2.1.4.5 that at thermal equilibrium or when there is no net electron or hole current, the Fenni level is spatially constant. Furthermore, when an extemal voltage Vupp is connected to two contacts ofa piece of silicon, the Fenni level at the lower voltage contact is shifted relative to the Fermi level at the higher voltage contact by q Vapp. In this section, we apply these results to establish the energy-band diagrams for a p-n diode under various bias conditions_ Consider a p-silicon region and an n-silicon region physically separate from each other. As discussed in Section 2.1.2.2, the Fermi level for a p-type silicon lies close to its 36 2 Basic Device Physics (a) Ec EI Ef E, p-Iype n-type ----Ec ·-·····························-·i I -----E" (0) Ec - - - - , ~ ~ ~ ~ ~ ~ '------Ev (e) ;, ~ ,V_ ,: Vapp Rgure 2.12. Energy-band diagrams for a p-n diode. (a) A p-silicon region and an n-silicon region physically separate from each other. (b) A p-n junction at thermal equilibrium. (c) A p-n diode connected to a battery, with the n-side connected to the negative end and the p-side connected to the positive end of the battery. The solid vertical bars represent the ohmic contacts of the p- and n-regions. For simplicity and clarity of the figure, Ei is not shown. valence band, and that for an n-type silicon lies close to its conduction band. The energy band diagrams for the two silicon pieces are illustrated schematically in Fig. 2. 12(a). Ifthe p-silicon and the n-silicon are brought together to form a p-n diode, the resulting energy-band diagram is as shown in Fig. 2.12(b). At thermal equilibrium, the Fermi level must remain flat across the entire p-n diode structure, causing the energy bands of the p-region to lie higher than those of the n-region. Near the physical junction, the energy bands are bent in order to maintain energy-band continuity between the p-region and the n-region. The band bending implies an electric field, 'I = -d//fJdx, in this transition region. This electric field causes a drift componcnt of electron and hole currents to flow. At thermal equilibrium, this drift-current component is exactly balanced by a diffusion component of clectron and hole currents flowing in the opposite direction caused by the large electron and hole concentration gradients across the junction. The net result is zero electron and hole currents across thc p-n junction at thermal equilibrium. On both sides of the band-bending region, the energy bands are flat and there is no electric field. These regions are referred to as the quasineutral regions. If a battery of voltage Yapp is connected to the diode, with the p-side connected to the end of the battery and the n-side connected to the negative end of the battery, the 2.2 p-n Junctions 37 Fermi level at the n-side contact becomes shifted by qVapp relative to the Fermi level at the p-side contact. This isil1us.trated in Fig. 2.12(c). 2.2.1.1 Built-in Potential Consider the energy-band diagram in Fig. 2.12(b). The difference between the energy bands on the p-side and the corresponding energy bands on the n-side is Eccp-side) - Ec q//fb;, where //fbi is the built-in potential of the p-n junction. In this subsection, we want to establish the relationship between //fbi and the p- and n-side doping concentrations. To facilitate description of both the n-side and the p-side of a diode simultaneously, when necessary for clarity, we shall distinguish the parameters on the n-side from the corresponding ones on the p-side by adding a subscript n to the symbols associated with the parameters on the n-side, and a subscript p to the symbols associated with the parameters on the p-side (Shockley, 1950). For example, Efn and E in denote the Fermi level and intrinsic Fermi level, respectively, on the n-side, and Ef'p and Eip denote the Fermi level and intrinsic Fermi level, respectively, on the p-side. Similarly, nn and Pn denote the electron concentration and hole concentration, respectively, on the n-side, and lip and Pp denote the electron concentration and hole concentration, respectively, on the p-side. Thus, lin and Pp signifY majority-carrier concentrations, while np and Pn signifY minority-carrier concentrations. Consider the n-side ofa p-n diode at thermal equilibrium. Ifthe n-side is non-degenerately doped to a concentraon of N", then the separation between its Fermi level, which is fiat across the diode, and its intrinsic Fermi level is given by (2.24), namely C:;) E;n kTln kTln (~;'), where nnO denotes the n-side electron concentration at thermal equilibrium. Similarly, for the nondegenerately doped p-side of a p-n diode at thermal equilibrium, with a doping concentration of No, we have Eli' kTlne:) kTln(~;), (2.72) where PpO is the p-side hole concentration at thermal equilibrium. The built-in potential across the p-n diode is Since Eq. q//fbi = Ein = kTln (2.73) gives nllopnO = npOppO = liT, Eq. (2.73) can also be written as q//fbi kTln(P\PPllO()) kTln(l1nO ), 111'0 (2.74) 38 2 Basic Device Physics which relates the built-in potential to the electron and hole densities on the two sides of the p-n diode. 2.2.2 2.2.2.1 Abrupt Junctions n.11alY"'" of a p-n diode is much simpler if the junction is assumed to be abrupt, i.e., the doping impurities are assumed to change abruptly from p-type on one side to n-type on the other side of the junction. The abrupt-junction approximation is reasonable for modem VLSI devices, where the use of ion implantation for doping the junctions, followed by low-thermal-cycle diffusion andlor annealing, results in junctions that are fairly abrupt. Besides, the abrupt-junction approximation often leads to closed-form solutions which render the device physics much easier.to understand. Depletion Approximation The spatial dependence of the electrostatic potential 'II;ex) is governed by Poisson's (2.44). For a diode at thermal equilibrium, the electron and hole and p(x), are given by Eqs. (2.49) and (2.50), respectively. As suggested is independent of x in the uniformly doped quasineutral regions. changes from being at the p-region end of the band-bending region to being -E;"lq at the n-region end of the band-bending region. Within the band-bending region, Eq. (2.49) suggests that the electron density drops very rapidly as 'II;(x) changes, being equal to the ionized donor density at the n region end and dropping lOx at room temperature for every 60 mV change in Thus, the density ofelectrons within the band-bending region is negligible compared to the density of ionized donors except for a very narrow region adjacent the quasineutral n-region where q('II; - 'II;) is less than about 3kT. Similarly, Eq. (2.50) suggests that, within the band-bending region, the density of holes is negligible compared to the density of ionized acceptors except for a very narrow region adjacent to the quasineu tral A closed-form solution to Poisson's equation can be obtained if the electron and hole densities are assumed to be negligible in the entire band-bending region. This is called the depletion approximation. In this case, the abrupt junction is approximated by three regions as illustrated in Fig. 2.13(a). Both the quasineutral p-region, i.e., the with x < -XI) and the quasineutral n-region, i.e., the region with x> X n, are assumed to be charge-neutral, while the transition region, the region with - xl' < X < X n, is assumed to be depleted of mobile electrons and holes. As we shall show later, the depletion-layer widths, xp and x", are dependent on the donor concentration Nd on the n-side and the acceptor concentration No (lTI the p-side, as well as on the applied voltage Vapp across the junction. The depletion approximation is quite accurate for all applied voltages except at large forward biases, where the mobile-charge densities are not negligible eompared to the ionized impurity concentrations in the transition region. The transition is often referred to as the depletion region or depletion layer. Since the transition is not charge-neutral, it is also referred to as the space-charge or space charge layer. 2.2 p-n Junctions 39 QuasineutraJ p-region (a) Depletion region ~ fJ,Je'(x) . -xp 0 Quasineutral n·region -qNd x x. -qNa (b) x (e) W;(X)-'h(-X p) ~ I. -Xp Figure 2.13. Depletion approximation of a electrostatic potential. V;m •x x. (a) charge distribution, (b) electric field, and (c) Poisson's equation, i.e., (2.44), for the depletion region is = d'if;' -d = i..[P(x) - n(x) + N/i(x) Xes; q N;(x)] (2.75) Gsi where is the ionized-donor concentration and is the ionized-acceptor concentra tion, and where the mobile-electron and -hole concentrations have been set to zero, consistent with the depletion approximation. For simplicity, we shall assume that all the donors and acceptors within the depletion region are ionized, and that the junction is abrupt and not compensated, i.e., there are no donor impurities on the p-side and no acceptor impurities on the n-side. With these assumptions, Eq. (2.75) becomes d21J1i - dx2 qN" for 0 5 x 5 Xn est (2.76) 40 2 Basic Device Physics , 2.2 p-n Junctions 41 2.2.2.2 and d 2'f1i - dx2 fisi for -Xp ::; x::; O. (2.77) the p-side is biased positively relative to the n-side, as in the case illustrated in Fig. 2.12(c). The total potential drop 'fImand.theextemally applied voltage Vapp are related by 'fIm = 'fIbi Vapp , (2.81) Integrating Eq. (2.76) once from x 0 to x = XI!, and Eq. (2.77) once from x = -xp to x = 0, subject to the boundary conditions of d'fld dx 0 at x = - xp and at x XI!, we obtain the maximum electric field, which is located at x O. That is, 'f", == = qNdxn 8si est (2.78) It is clear from (2.78) that the total space charge inside the n-side of the depletion region is equal (but opposite in sign) to the total space charge inside the p-side of the depletion region. Thus, in Fig. 2.13(a), the two charge distribution plots have the same where Vapp > 0 means the diode is forward biased and v;.pp < 0 means the diode is reverse biased. If Eq. (2.81) is used in Eq. (2.80), it the total depletion-layer width of a forward- or reverse-biased diode. A quasineutral region has a finite resistivity determined by its dopant impurity concentration Fig. 2.9). When a current flows in a region of finite resistivity, there is a corresponding voltage drop, or lR drop, along the current path. In writing Eq. (2.81), the lR drops in the quasineutral regions are assumed to be negligible so that Vapp is the same as the voltage across the space-charge region, V'app' -If IR drops in the quasineutral regions are not negligible, then Vapp should be replaced by V'app in Eq. (2.81). area. Equation (2.78) could have been obtained directly from Gauss's law, i.e., Eq. (2.43). • p-n diode as a rectifier. When a diode is forward biased, the energy barrier limiting Let 1/1_ be the total potential drop across the p--n junction, 'fIm = ['fIi(xn) current flow is lowered, causing electrons to be injected from the n-side into the p-side The total potential drop can be obtained by integrating twice, the second time from x -xp to X xn • That is, (2.76) and L:~ 'fIm d'fli(X) L:~ 'f(x)dx ~mWd (2.79) 2 where Wd XI! + xp is the total width ofthe depletion layer. It can be see from Eq. (2.79) that 'fIm is equal to the area in the ~(x) -x plot, i.e., Fig. 2.l3(b). Eliminating 'I ~ from Eqs. (2.78) and (2.79) gives 2esi(Na + Nd)'fIm qNaNd (2.80) This equation relates the total width of the depletion layer to the total potential drop and holes injected from the p-side into the n-side, resulting in a current flow through the diode. As we shall show in Section 2.2.4, the forward current increases exponen tially with V'app and hence can be very large. When a diode is reverse biased, the energy barrier limiting current flow is increased. There is no current flow due to electron and hole injection, only a relatively low background or leakage current. Thus a diode has rectifying current-voltage characteristics, being conducting when it is forward biased, and nonconducting when it is reverse biased. This is illustrated in 2.14. The equations governing the current-voltage characteristics ofa diode will be derived in Sections 2.2.3 and 2.2.4. • Depletion-layer capacitance. Consider a small change dVapp in the applied voltage. dVapp causes a charge per unit area dQ to flow into the p-side, which is equal to the change in the charge in the p-side depletion region. Since all mobile carriers are 0.08 across the junction and to the doping concentrations of the two sides of the diode. Externally Biased Junctions in the absence of any externally applied voltage, the total electrostatic potential drop 111m across a p-n diode is equal to the built-in potential 'fIbi, as indicated in 2.12(b). This built-in potential represents an energy barrier limiting the flow ofelectrons from the n-side to the p-side and the flow of holes from the p-side to the n-side. An externally applied voltage across a p--n diode shifts the Fermi level at the n-region contact relative to the Fenni level at the p-region contact. )fthe applied voltage causes 'fIm to be reduced, the diode is said to beforward biased. Ifthe applied voltage causes lI'm to be increased, the diode is said to be reverse biased. In considering a p--n diodc in the context of VLSI devices, the forward-bias characteristics are more interesting than the reverse-bias characteristics. 0.06 :? § t; ~ 0.04 '".".. r '0 0 is 0.02 01 -0.5 ,J I 1 0 0.5 Applied voltage (V) Therefore, we shall adopt the convention where a positive applied voltage also means a forward-bias voltage. Physically, this means the external voltage is connected such that Figure 2.14. A schematic linear plol of the current of a typical silicon diode as a function of its On a linear plot, the reverse current is too low to be observable. voltage. 42 2 Basic Device Physics 2.2 p-n Junctions 43 2.2.2.3 ignored in our depletion approximation, we can write the charge per unit area in the p side depletion region as Qip-side)= - qNaxp(Vapp) , (2.82) where we have indicated that the p-side depletion-layer width, xpo is a function of Vapp. Notice that Qd for the p-side is negative because ionized acceptors have a charge--q. LOS 1.00 '1~ 0.95 'd - _. 0.90 .1 I ,,- V ,/ i The depletion-layer capacitance pet unit area is Cd == dQ = dQdCp-side) = Ssi dVapp dVapp (2.83) That is, the depletion-layer capacitance of a diode is equivalent to a parallel-plate capacitor ofseparation Wd and dielectric constant lOs;. Physically, this is due to the fact that only the majority carriers at the edges ofthe depletion layer, not the space charge ."S 0.85 .ll: ~ 0.80 ,/ V ;--- 0.75 0.70 IE+14 ,,/' .. !! lE+1S lE+16 IE+17 Doping concentration (cm-3) 113+18 within the depletion region, respond to changes in the applied voltage. Figure 2.15. Built-in potential for a one-sided p-n junction versus the doping concentration of the lightly • Extending the depletion approximation to include injected currentflows in the space doped side. charge region. When a diode is forward biased, the electrons flowing from the n-side to the p-side and the holes flowing from the p-side to the n-side add to the space charge in the transition region of the diode. To be accurate, we cannot assume the transition region to be depleted of mobile charge carriers. However, as long as the density of it is a good approximation to assume its Fermi level to be at the conduction-band edge. Therefore, the built-in potential for an n+-p diode, from Eqs. (2.72) and (2.73), is given by mobile carriers is small compared to the densities of ionized donors and acceptors, we have a well-defined space-charge region. (When the density of mobile carriers is E E kTin + q'llbi = fn - in (~~) comparable to or larger than the densities ofionized donors or acceptors, the boundaries ofthe space-charge region are no longer well defined. This situation will be discussed ~ -Em+kTln(:;) (2.84) further in Section 6.3.3.2 in the context ofbase widening at high injection in a bipolar transistor.) For a well-defined space-charge layer of width Wd, the associated capaci tance per unit area is the same as a parallel-plate capacitor, namely, Eq. (2.83). In this ~ 2 +kTln(:;), case, Wd can be obtained from integrating Poisson's equation, i.e., (2.44). An example of how mobile charge carriers flowing through a space-charge region affect the space-charge-region thickness is given in Section 6.3.3.1 in the context of base widening at low injection in a bipolar transistor. where we have made a further approximation that the intrinsic Fermi level is located half way between the conduction- and valence-band edges, Ern and Evn, on the n-side. [See Eq. (2.12) and the discussion that follows.] Figure 2.15 is a plot of'llbi, as approxi mated by Eq. (2.84), as a function of the doping concentration ofthe lightly doped side. The depletion-layer width, from Eqs. (2.80) and (2.8\), is One-Sided Junctions In many applications, such as the source or drain junction ofa MOSFET or the ernitter-base diode of a bipolar transistor, one side of the p-n diode is degenerately doped while the other side is lightly to moderately doped. In this case, practically all the voltage drop and the .depletion layer occur across the lightly doped side of the diode. That this is the case can be inferred readily from Eq. (2.78), which implies thatXn = NaWd/(Na + Nd) and xp = N"Wd/(Na + Nd). The characteristics ofa one-sided p-n diode are therefore deter mined primarily by the properties ofthe lightly doped side alone. In this sub-subsection, we shall derive the equations for an n+-p diode where the characteristics are determined by the p-side. The results can be extended straightforwardly to a p+-n diode. As discussed in Section 2.1.2, for a lightly to moderately doped p-type silicon, the Fermi level is given by Eq. (2.25), and for a heavily or degenerately doped n-type silicon, Wd= 2Ssi (lfIbi - Vapp ) qNa (2.85) where Vapp > 0 if the diode is forward biased and Vapp < 0 if the diode is reverse biased. The depletion-layer capacitance per unit area is given by Eq. (2.83). Figure 2.16 is a plot of the depletion-layer width and capacitance as a function of doping concentration for Vapp O. Again, in Eg. (2.85) should be replaced by V'app whenever the IR drops in the guasineutral regions are not negligible. 2.2.2.4 Thin-i-Layer p-i-n Diodes Many modem VLSI devices operate at very high electric fields within the depletion regions of some of their p-n diodes. In fact, the junction fields are often so high that 44 2 Basic Device Physics I 1l l~ In I III gIl g 0.1 .~ ~ om lE+14 IE+1S 1E+16 IE+t7 Doping concentration (cm-3) 10 ~ -s j :u >. ~'" 0.1 .g .g£ o om IE+lS Figure 2.16. Depletion-layer width and depletion-layer capacitane, at zero bias, as a function of doping concentration of the lightly doped side of a one-sided p-n junction. p-region Depletion region Pn" (x) n-region _I W \"!:II ... x i-layer Figure 2.17. Charge distribution in a p-i-n diode. detrimental high-field effects, such as avalanche multiplication and hot-carrier effects, limit the attainable device and circuit performance. To overcome the constraints imposed by high fields in a diode, device designers often introduce a thin but lightly doped region between the n- and the p-sides. In practice, this can be accomplished by sandwiching a lightly doped layer during epitaxial growth ofthe doped layers, or by grading the doping concentrations at or near the junction by ion implantation and/or diffusion. Analyses of such a diode structure become very simple if the lightly doped region is assumed to be intrinsic or undoped, i.e., if the lightly doped region is assumed to be an i-layer. This actually is not a bad approximation as long as the net charge concentration in the i-layer is at least several times smaller than the space-charge concentration on either side ofthe p---n junction, so that the contribution by the i-layer charge to the junction electric field is negligible. Figure 2.17 shows the charge distribution in such a p---i-n diode. The corres ponding Poisson equation is - qNd for d~:-./--": :~'\_'"~_:L::7:::<:::1_~>'::p:"'=-_--_-___-'__.__..... Efc , ' xn ! ,--- -xp Ev o x p·type n-type Figure 2.18. Schematics showing the variations of the quasi-Fenni potentials, 0) with negligible lR drops in the quasineutral regions. (c) A reverse biased diode (Vapp < 0). In the case of reverse bias, the drops in 1' across the space-charge region increase with iVappl. and rPp are essentially constant across the space-charge region, as illustrated schema tically in Fig. 2.18(b). • Reverse-biased diode. In the case of reverse bias, the results in Appendix 4 show that the drops in rPn and rPp across the space-charge layer are small compared to kT/q only for small reverse bias (Iv"pplless than about 4kT/q). For larger reverse bias, the drops in rP" and rPp across the space-charge layer increase approximately linearly with increase in reverse bias. Therefore, rP. and rPp are also relatively constant across the space-charge region for the case of small reverse bias, as illustrated schematically in 2.18(c). 2.2.3.3 Relationship Between MinOrity-Carrier Density and Applied Voltage The relationship between the voltage across the space-charge region, Vlapp, and the majority-carrier quasi-Fermi potentials at the space-charge-region boundaries, and rPn(xn) is 50 2 Basic Device Physics v.pp == Vapp IR(p-side) - IR(n-sidel == Vapp [1>p(p-contact) -1>p( -xp)] 1>p(-xp) - [1>n(Xn) 1>n(n-contact)] (2.106) In Eq. (2.106), we have used the results discussed in Sections 2.1.4.5 and 2.1.4.6 which state that = (Ejn(n-contact) EiP(p-contact)l/q 1>p(p-contact) -1>n(n-contact). For forward bias and small reverse bias, the drops in the quasi-Fenni potentials across the space-charge region are small compared to kTlq, i.e., 1>p(-xp) ~ 1>p(Xn) and 4>n (-xp) ~ 1>n(xn). Therefore, Eqs. (2.102) and (2.106) can be combined,forforward bias and small reverse bias, to give the electron density on the p-side at the space-charge-Iayer edge as np(-xp) - Pp n2 (--x'-p) e xp{q[4>p(-xp) - 4>n(-xplJlkT} ~ n2 - (-'-) exp{q[4>p( -xp) - 4>n(xnl]lkT} Pp -xp = -Pp(n--2x 'p-) exp(qV.pplkT) npO(-Pxpp()p_pxop)( -xp) exp(Tq7yfapp /kT) ~ npO( -xp) exp(qv.pp/kT), (2.107) where we have used the low-injection approximation to write Pp ~ PpO. (The case ofhigh injection will be discussed later.) Similarly, we have Pn(Xn) ~ PnO(xn) exp(qv.pp/kT) forward bias and small reverse bias (2.108) is the hole density at the space-charge-layer edge on the n-side. Equations (2.107) and (2.108) are the most important boundary conditions governing a )rn diode. They relate the minority-carrier concentrations at the space-charge-region boundaries of the quasi neutral regions to their thermal-equilibrium values and to the voltage across the space charge region. For a forward-biased diode (V~pp > 0), we have an excess of minority carriers at the boundaries of the quasineutral regions. For a reverse-biased diode (V~pp <0), we have a depletion of minority carriers at the boundaries of the quasineutral regions. Equations (2.107) and (2.108) are often referred to as the Shockley diode equations (Shockley, 1950). The fact that Eqs. (2.107) and (2.108) are valid only for small reverse bias is often overlooked in the literature. It is shown in Appendix 4 that for reverse biases more negative than about -4kTlq, Eqs. (2.107) and (2.108) overestimate the degree of minority-carrier depletion at the quasineutral-region boundaries. However, it is also shown in Appendix 4 that once the. depletion of minority carriers at the boundaries has reached 90%, corresponding to IVappl ~ 3 kTlq, further depletion of minority carriers has little effect on the diode current. In other words, using Eqs. (2.107) and (2.108) for > 3kTlq does not lead to any significant error in the calculated reverse-biased diode 2.2 p-n Junctions 51 currents. Therefore, Eqs. (2.107) and (2.10&) can be used to describe the transport properties in a reverse-biased diode.as if they are valid for arbitrary reverse biases. The distinction between V'ap; and Vapp is important whenever there is significant parasitic series resistance in a forward-biased diode, for instance, in the forward-biased emitter-base diode of a bipolar transistor. In most cases, the parasitic resistance can be modeled as a lump resistor in series with the diode, allowing us to quantify the difference between V'app and Vapp readily. For simplicity in writing the equations, we shall not make the distinction between Vapp and Vlapp when we use Eqs. (2.107) and (2.108) to derive the equations for the current-voltage characteristics. The distinction between Vapp and V'app will be pointed out wherever it is important to do so. 2.2.3.4 Diode Equation at High Minority-Carrier Injection As stated in the derivation of Eqs. (2.107) and (2.108), these equations are valid at low injection. If the low-injection condition is not met, these equations are not valid and (2.102) should be used instead. At sufficiently large forward biases, the injected minority-carrier concentration, particularly on the lightly doped side of the diode, can be so large that, in order to maintain quasineutrality, the electron and hole concentrations become approximately equaL In this case, Eq. (2.1 02) gives n P Rj ~ ni exp (q V;pp/2kT). At such high levels of minority-carrier injection, the concept of a well-defined transition region is no longer valid, and the quasi-Fermi potentials do not have simple behavior in any region of the diode (Gummel, 1967). The effect of high minority-carrier injection on the measured current-voltage characteristics of a diode will be discussed further in Section 2.2.4.10. An example of how the "boundary" of a p-n junction can be "relocated" at high minority-carrier injection can be found in Section 6.3.3 in connection with the discussion of base-widening effects in a bipolar transistor. 2.2.4 Current-Voltage Characteristics As discussed in Section 2.2.1, at thermal equilibrium, the drift component ofthe current caused by the electric field in the space-charge region is exactly balanced out by the diffusion component of the current caused by the electron and hole concentration gradients across the junction, resulting in zero current flow in the diode. When an external voltage is applied, this current component balance is upset, and current will flow in the diode. If carriers are generated by light or some other means, thermal equilibrium is disturbed, and current can also flow in the diode. Here only the current flow in a diode as a result of an externally applied voltage is discussed. We first consider the current-voltage characteristics of an ideal diode govemed by the Shockley diode equations (2.107) and (2.1 08). The space-charge-region current will be added later in Section 2.2.4.10 when we consider the deviation of a practical diode from ideal behavior. Consider a forward-biased p--n diode. Electrons are injected from the n-side into the and holes are injected from the p-side .into the n-side. Since space-charge-region current is ignored, the hole current leaving the p-side is the same as the hole current 52 2 Basic Device Physics entering the n-side. Similarly, the eleGtron current leaving the n-side is equal to the electron current entering the p-side. To determine the total current flowing in the diode, all we need to do is to determine the hole current entering the n-side and the electron current entering the p-side. The starting point for describing the current-voltage characteristics is the continuity equations. For electrons, it is given by Eq. (2.68) which is repeated here: aant Rn + (2.109) where Rn and Gn are the electron recombination and generation rates, respectively. (A detailed discussion of generation and recombination processes is given in Appendix 5.) Equation (2.109) can be rewritten as q on 10Jn n - no ot = ax 'II (2.110) where n-no 'n Rn - Gn 11) is the electron lifetime, and no is the electron concentration at thermal equilibrium. Substituting Eq. (2.54) for I n into Eq. (2.110) gives I on -;:;- = nfJ-n a'l! + fJ-n ' an '(J" + Dn i:i2 n - no (2.1 ut uX uX 'n 2.2.4.1 Diodes with Uniformly Doped Regions Let us consider electrons in the p-region of a p-n diode. For simplicity, we assume the p-region to be uniformly doped so that at low electron injection currents the hole density is uniform in the p-region. As will be shown in Section 6.1.2, the electric field is zero for a region where the majority-carrier concentration is uniform. Thus, for the a lax p-region under discussion, 'I! 0 and $' = O. For electrons in this p-region, Eq. (2.112) reduces to rf2np = Dn ax2 'n (2.ll3) At steady state, Eq. (2,113) becomes -aon=tI' O=Dn which can be rewritten as -np --Tn n-pO (2.114) cPnp np - npO = 0, dx2 L"!, 2.2 p-n Junctions 53 where LII =='VTnDn = JkT~n!n (2.1 is the electron diffosion length in the p-region. It should be noted that the quantities in Eq. (2.116) are all for minority carriers, not majority carriers. In deriving the equations for minority-carrier transport, we can focus on minority electrons or minority holes. As we shall show later, the current-voltage characteristics of a one-sided diode are determined primarily by the transport of minority carriers in the lightly doped side. Forward-biased diodes are usually found in the operation of bipolar transistors. High-speed bipolar transistors are n-p-n type, instead of p-n-p type. That is, most commonly encountered one-sided forward-biased diodes are of the n+-p type, instead of -n type. Therefore, we choose to focus on minority electrons in deriving the transport equations. Also, we like to make some rearrangement to simplify the algebra in deriving the current equations. Earlier in this chapter, the physical junction of a p-n diode is assumed to be located atx=O with the p-silicon to the left side ofthe junction and the p-side depletion-layer edge located at x = -xp• The n-silicon is located to the right side of the junction. The excess electrons in the p-region of the diode are injected from the n-side. These excess electrons will then move further into the p-region, contributing to electron current and becoming recombined along the way. That is, the p-side space charge-region boundary is really the starting location for considering the distribution and transport of the excess electrons in the p-region. For considering the transport ofelectrons in the p-region, the algebra is simpler if we flip the p-n diode in Fig. 2.18 such that the n-region is on the left and the p-region is on the right, resulting in electrons flowing in the x-direction. The algebra can be further simplified if we shift the origin such that the quasineutral region of the p-side starts at x = 0 and ends at x = Wp- Note that in this arrangement, the electron current in the p-region has a negative sign (negative charges flowing in the x-direction). This is illustrated in Fig. 2.19 for an n+-p diode. In this rearranged coordinate system, the electron density atx = 0 is given by the Shockley diode equation, i.e., Eq. (2.107), while the electron density at:x = Wp is equal to npO, ie., np(O) npO exp(q VapplkT) (2.117) Space-c,harg,e region ~,, :~ Emitter: Base ._~__ J oI •x t'1lure 2.19. Schematic showing the coordinates u.~ed to develop the transport equations for a p-n diode. An n+-p diode is assumed with the quasineutral p-region starting at x = 0 and ending at x 54 2 Basic Device Physics and np(Wp) npo· (2.118) be accurate, Vapp should be replaced by V'app in Eq. (2.l17). For simplicity in writmg the equations, we are not making the distinction between Vapp and V'app unless there is confusion.] Solving Eq. (2.115) subject to these boundary conditions gives 1] qVapp) _ sinh[(Wp x)/Lnl. npO = npO [exp ( kT sinh(Wp/ Ln) 19) Since there is no electric field in the quasineutral p-region, there is no electron drift current component, only an electron diffusion-current component. The electron current density entering the p-region is (~) 1.(0) = qDn .<=0 = qDnnpO[exp(q VaEE/kT) 1] Ln tanh(Wp / Ln) qDnnHexp(qVapp/kT) -1] ppOLn tanh( Wp/ Ln) (2.120) where in writing the last equation we have used the fact that npOppO = nj. Equations (2.119) and (2.120) are valid for a p-region ofarbitrary width Wp. Note thatJn is negative in sign because electrons have a charge --q and are flowing in the x-direction. The hole density in the n-region and the hole current density entering the n-side have the same forms as Eq. (2.119) and Eq. (2.120), respectively, and can be derived in an analogous manner (cf. Exercise 2.16). The total currentflowing through a p-n diode is the sum ofthe electron cu"ent on the p-side and the hole current on the n-side. That is, the diode current density is qDnnT[exp(qVapp/kT) - IJ qDpnnexp(qVapp/kT) 1] PpOLn tanh (Wp / Ln) - nnOLp tanh( Wn / Lp) I] [NaTn qLnnr tanh(Wp/Ln) + N,rrp qLpnr ] tanh(Wn/Lp) [exp(qVapp ) kT ' (2.121) where we have assumed that all the dopants are ionized so that PpO = Na and nnO = Nd. diode current represented by Eq. (2.121) is due to the diffusion of minority carriers in the quasineutral regions. It does not include the generation-recombination current in the space-charge region, which will be discussed in Section 2.2.4.10. The total diode current is the sum ofthe diffusion current and the generation-recombination current.] The negative sign in Eq. (2.121) is due to the fact that we placed thep-region to the right of the n-region, causing electrons to flow in the +x direction and holes to flow in the -x direction. The negative sign will not be there if we place the p-region to the left of the Ignoring the (2.121) is often referred to as the Shockley diode current equation, or simply the Shockley diode equation. It is applicable to both forward bias (v"pp > 0) and reverse bias (v;,pp < 0). Figure 2.20 is a semi-log plot of the diode current 2.2 p-n Junctions 55 lE-1 ~ '''-J E - - Forward bias. -----. Reverse bias R E ~ lE-5 S .~ c "." 1E-7 C ~ B ~" 1E-9 IE-II Figure 2.20. lE-13_1 --0.5 0 0.5 Applied voltage (V) The currentdensityofan ideal diode as given by Eq. (2.121). We assumeNa = Nd= 1017 cm-3, and use the corresponding values for Land, in Fig. 2.24. WIL is assumed to be large so that tanh (WiL) = I. density given by (2.121) as a function applied voltage. It represents the I-V characteristics of an ideal diode. It is of interest to contrast Fig. 2.20 with Fig. 2.14. On a linear plot (Fig. 2.14), the rectifYing characteristics of the diode current are evident, with a tum-on voltage ofabout 0.8 V. On a semi-log plot (Fig. 2.20), only the exponential dependence of the forward-bias current on voltage and a low-level reverse-bias back ground current are obvious. Deviations of a practical diode from an ideal case are usually observable in a semi-log plot, but not in a linear plot, and will be discussed later in Section 2.2.4.10. At sufficiently large reverse bias, the diode will break down (not shown in Fig. 2.20). High-field effects, including avalanche breakdown of a p--n diode, will be covered in Section 2.5. 2.2.4.2 Emitter and Base of a Diode Equation (2.121) shows that the minority-carrier current is inversely proportional to the doping concentration. Thus, in a one-sided diode, the minority-carrier current in the lightly doped side is much larger than that in the heavily doped side. The diode current is dominated by the flow of minority carriers in the lightly doped side of the diode, while minority-carrier current in the heavily doped side usually can be neglected in comparison. (The effect ofheavy doping can increase the minority-current flowing in the heavily doped region substantially. Heavy-doping effect is particularly important in bipolar devices, and will be covered in Chapter 6. The effect of heavy doping on the magnitudes of the currents in a diode will be discussed as exercises.) The lightly doped side is often referred to as the base of the diode. The heavily doped side is often referred 56 2 Basic Device Physics 2.2 p-n Junctions 57 2.2.4.3 2.2.4.4 to as the emitter of the diode, since the minority carriers entering the base are emitted from it. In discussing the current-voltage characteristics of a diode, often only the minority carrier current flow in the base is considered, since the minority-carrier current flow in the emitter is small in comparison. (However, if the width of an emitter is not larger than its minority-carrier diffusion length, the minority-carrier current flow in the emitter may not be negligible. Diodes with such emitters will be discussed further in Section 2.2.4.9.) As a result, unless stated explicitly, the region of the diode under discussion is assumed to be the base. That is, only the term in Eq. (2.121) corresponding to the base is kept. Whenever the emitter term is not negligible, both terms in Eq. (2.121) should be kept. In the following subsections, we examine in detail the current-voltage characteristics of one-sided n+-p diodes. The equations derived can be modified readily to describe p+-n diodes by changing the parameters for electrons in p-silicon to parameters for holes in n-silicon. is the electron diffusion component of the leakage current in a reverse-biased diode. It is also referred to as the. electron.satur.ation current of a diode. The hole saturation current can be inferred from Eq. (2.121). The total diffusion leakage current in a diode is the sum of the electron and hole saturation currents. Notice that the diffusion leakage current is independent ofthe applied voltage. 2.2.4.5 Wide-Base n+-p Diodes A diode is wide-base if its base width is large compared to the minority-carrier diffusion » length in the base. For an n+-p diode, this means Wp / Ln 1. For a forward-biased wide base diode, Eqs. (2.122) and (2.123) reduce to np(x) - npo = npfJ exp(q Vapp/kT) exp(-xlLn) (forward, wide base) (2.126) and JnCO) qpDpfnJnL2~exp (qkVaTI'P) (forward,wl.debase). (2.127) Forward-Biased n+-p Diodes We first consider the case where the -p diode is moderately forward biased, i.e., Vapp > 0, and qVapp I kT» 1. In this case, Eqs. (2.119) and (2.120) become 5inh[( Wp - x)/ Lnl . np(x) - npfJ = npo exp(q Vapp/kT) sinh ( W / Ln) (forward bIased) p (2.122) Thus, for a forward-biased wide-base diode, the excess minority-carrier concentration decreases exponentially with distance from the depletion-region boundary, and the minority-carrier current is independent of the base width. For a reverse-biased wide-base diode, Eqs. (2.124) and (2.125) reduce to np(x) npfJ -npfJexp(-x/Ln ) (reverse, wide base) (2.128) and and JI1 (O) = qDnni exp(qVapp/kT) PpfJLn tanh( Wp / Ln) (forward biased). 123) = qDnn; (reverse, wide base). ppOLn (2.129) That is, the minority-carrier electrons in the base within a diffusion length of the That is, both the excess minority.carrier concentration and the minority-carrier cur depletion-region boundary diffuse towards the depletion region, with a saturation current rent increase exponentially with the applied voltage (see Fig. 2.20). density given by (2.129) which is independent of the base width. Reverse-Biased n+-p Diodes » Next we consider the case where the n+-p diode is reverse-biased, i.e., Vapp < 0, and kT. In this case, Eqs. (2.119) and (2.120) become sinh[( Wp x)/ Lnl (reverse biased) npo = -npfJ sinh(WI'/Ln) (2.124) and In(O) = -_.--=-c:-~~ (reverse biased). 125) Notice that np(x) - nl'o is negative, andJn is positive. The reverse bias causes a gradual depletion of electrons in the p-region near the depletion-region boundary, and this electron concentration gradient causes an electron current to flow from the quasineutral p-region towards the depletion region (in -x direction according to our coordinates). This 2.2.4.6 Narrow-Base n+-p Diodes A diode is called narrow-base if its base width is small compared to the minority-carrier « diffusion length in the base. In this case, this means Wp/ Ln L For a forward-biased narrow-base diode, Eqs. (2.122) and (2.123) reduce to npo npfJ exp ( kqVTapp) ( I -~Wp) (forward, narrow base) (2.130) and J (0) --qD-nenTxp (q-V-ap.p) (forward, narrow base). 11 PpoWp kT (2.131) For a reverse"biased narrow-base diode, the corresponding equations are -npo(l - ;J np(x) npD (reverse, narrow base) (2.132) 58 2 Basic Device Pltysics and In(O) = -qD-nn'2 (reverse, narrow base). ppoWp (2.133) For both forward and reverse biases, the minority-carrier current density in a narrow-base n+-p diode increases as I/Wp. That is, for a narrow-base diode, the base current increases rapidly as the base width is reduced. 2.2.4.7 Spatial Distribution of Excess Minority Carriers It can be seen from Eqs. (2.122) and (2.124) that both a forward-biased diode and a reverse-biased diode have the same sinh [(W - x)/L] spatial dependence for the distribu tion ofexcess minority carriers (actually depletion ofminority carriers in a reverse-biased diode). Figure 2.21 is a plot of the relative magnitude of the excess minority-carrier density as a function ofxIL with WIL as a parameter. The exp(-xlL) distribution is for the case of WIL = 00. It shows that a diode behaves like a wide-base diode for WIL> 2. For WIL < 2, the diode behavior depends strongly on W For WIL < 1, the distribution can be approximated by the I - xIW dependence of a narrow-base diode. 2.2.4.8 Dependence of Minority-Carrier Current on Base Width Figure 2.22 is a plot of the minority-carrier current density given by Eq. (2.120), normalized to its wide-base value. It shows that when WIL < 1, the minority-carrier current increases very reapidly as the diode base width decreases. 2.2.4.9 Shallow-Junction or Shallow-Emitter Diodes Thus far, we have assumed the minority-carrier current in the emitter to be negligible compared to that in the base. A diode has a shallow emitter if the minority-carrier diffusion length in the emitter is comparable to or smaller than the width of the emitter 6 i., ~ ] -Ea 0.2 * 0 0 0.5 1.0 1.5 2.0 2.5 3 x/L Figure 2.21. Relative magnitude of the excess minority-carrier concentration in the base ofa diode as a mnction of distance from the base depletion-layer edge, with WIL as a parameter, where L is the minority carrier diffusion length in the base and Wis the base-region width. The case of WIL 00 is given by exp(-xIL). 2.2 p-n Junctions 59 12 10 .~ "~ 8 't:I C ~6 "0 .~ 4 0 ~ 2 Figure 2.22. 0 0 0.5 1.0 1.5 2 W/L Relative maganitude of the minority-carrier current density in the base region of a diode as a function of WIL, normalized to the current at WIL = 00. Here L is the minority-carrier diffusion length in the base, and Wis the width of the base region. region. The width of the emitter region of a p-n diode is also referred to as the junction depth. Therefore, a shallow-emitter diode is also a p-n junction having an electrically shallow junction. Figure 2.22 applies to the emitter region as well. Thus, we see from Fig. 2.22 that when WIL < I in the emitter, the minority-carrier current in the emitter increases very rapidly as the emitter depth decreases. As can be inferred from Fig. 2.24(c), to be developed later in Section 2.2.4.12, the minority-carrier diffusion length is about 0.3 11m for a doping concentration of I x IOZo em- 3, and much larger for lower doping concentrations. This length is larger than the emitter depth ofa typical one-sided p-n diode in a modem VLSI device (e.g., the emitter of a bipolar transistor and the source and/or drain of a CMOS device). That is, typicalp-n diodes in modern VLSI devices should be treated as shallow-juncnon diodes. There are effective means for reducing the minority-carrier current in a shallow-emitter diode. For instance, a shallow emitter can be contacted using a doped polysilicon layer instead of a metal or metal silicide layer. The physics of minority-carrier transport in a shallow emitter will be covered in detail in Chapters 6 and 7 in the context of modem bipolar transistors. 2.2.4.10 Space-Charge-Region Current and Ideality Factor of a Diode Thus far, we have neglected the current originating from the generation and recombina tion ofelectrons and holes within the space"charge region. In practical silicon diodes, the space-charge region current can be larger than the Shockley diode current at reverse bias and at low forward bias. It is shown in Appendix 5 that the space-charge-region current can be written in the form Isc(Vapp) = ISC1l[exp(qVapp/2kT) IJ, 134) with Isco = AdiodeqniWd 'n +'p (2.135) 60 2 Basic Device Physics where Wd is the width of the space-charge region, Adiode is the cross-sectional area of the diode, and Ln and Lp are the electron and hole lifetimes, respectively. Equation (2.134) is often referred to as the Sah-Noyce-Shockley diode equation (Sah et al., 1957; Sah, From Eq. (2.121), we can write the Shockley diode current in the form IdioM = Io[exp(qVapp/kT) 1], with 10 = Adiodeqni2 ~ poL. Dn tanh(Wp/Ln) + npOLp Dp J. tanh(Wn/Lp) (2.l36) (2.137) As discussed in Section 2.2.3.4, Eq. (2.136) is valid only at low injection levels. For an n+-p diode, high injection occurs when np approaches No where Na is the acceptor concentration of the p-side. At high injection, IR drops in the quasineutral regions can be significant. Also, Idiode changes to an exp(q V~pp 12kT) dependence (see the discussion in Section 2.2.3.4). The onset of high injection can be pushed to higher voltage by increasing Na. The current measured at the diode terminals is llOtat = Idiode + Isc· (2.138) Figure 2.23 is a schematic semi-log plot of a diode current as a function of its forward bias terminal voltage, with series resistances neglected. A semi-log current-voltage plot exp(qVapp/2k1) IE+ll '"c- ">. ~ :a ~ i:i ~ IE+5 u" exp(qVapplkTJ Isc '''iode floral IE+2 Resistance effect ignored IE_1LU~LU~LU~LU~~~~WW~~~~~LLU 0.7 0.8 0.9 Applied voltage (V) Figure 2.23. A schematic Gummel plot of the forward-bias current of a p-n diode. Series resistance effects are ignored. [diude is the Shockley diode current. lsc is the space-charge-region current. 2.2 p-n Junctions 61 for a diode or a bipolar transistor is called a Gummel plot. The slope in a Gummel plot is often used to infer the ideality oLa. diode. That is, the forward diode current is often expressed in the form Itotat(forward) ~ exp(qVapp/mkT), (2.139) where m is called the ideality factor. Note that it is the diode terminal voltage VapP' not V' app across the space-charge region that is in Eq. (2.139). The difference between Vapp and V'app is contained in the ideality factor. When m is unity, the current is considered "ideal." Figure 2.23 suggests that a forward diode current is ideal except at very small and very large forward biases. The nonideality at small forward bias is caused by the space-charge-region current. Space-charge-region current leads to m - 2 [see Eq. (2.134)1. The nonideality with m-2 at very large forward bias is due to injection effect in the Shockley diode current (see the discussion in Section 2.2.3.4). At intermediate voltages, we have 1 < m < 2. Finite resistivity of the p- and n-regions results in voltage drops between the ohmic contacts and the junction. Finite resistivity effect is important only at very large forward biases. On a Gummel plot, finite resistivity effect can lead to m being very large. In general, when 1 < m < 2 at large forward bias, it is not easy to clearly tell ifthe nonideality is caused by series resistance or by high injection. It may be a combination of both. However, when m > 2, we know that the series resistance effect dominates because the injection effect by itself has an ideality factor of no larger than 2. Series resistance effects can be reduced by increasing the diode doping concentrations, narticularlv the doping concentration of the base side ofthe diode. As discussed earlier, concentration also delays the onset of high injection. Practical silicon can be such that it appears quite ideal for forward biases of up higher. Degradation in ideality factor is usually observable only at low forward biases and only in diodes having significant amounts of generation recombination centers in the space-charge region. (An example of how the ideality factor changes with forward bias can be seen in the base current of a modem bipolar transistor shown in 6.13.) 2.2.4.11 Temperature Dependence and Magnitude of Diode leakage Currents For a reverse-biased diode, the total leakage current is the sum ofthe space-charge-region saturation current Isco and the diffusion saturation current 10 given by Eqs. (2.l35) nt and (2.l37), respectively. The temperature dependence of 10 is dominated by the tem perature dependence of the factor, which, as shown in Eq. (2.13), is proportional to exp (- Eg / kT) where Eg is the bandgap energy. The space-charge-region leakage current Isco, being proportional to nj, has a temperature dependence ofexp( -Eg /2kT). In other words, the diffusion leakage current has an activation energy of about 1.1 eV while the generation-recombination leakage current has an activation energy of about 0.5 eV. This difference in activation energy can be used to distinguish the sources of the observed leakage current (Grove and Fitzgerald, 1966). [The diffusion leakage current is indepen dent of reverse-bias voltage. The space-charge-region current is proportional to the space-charge-Iayer width which increases with revt 2 x 1018cm-3) doping concentrations and about 30% lower mobilities at low « I x IOI8cm '3) doping concentrations (Klaassen et al., 1992). 22 p-n Junctions 63 800 1 ~ 1600 .. J.lrfl "/1111 ~ ~4001 .~ 1=1--LHIIII I- 1111111 "? ·igc::' 200 ~ 1~+17 lE+18 lE+19 Doping concentration (cm-3) (a) lE-4 ~ 18-5 .§ J! lE-6 "."~ IB-7 "? ·€ c lE-1l .~ ~ lB-9 300FHHi-· 100 ~ } .2 @ is IE+1S Doping concentration (cm-3) (b) Doping concentration (cm-3) (c) Figure 2.24. Minority-carrier (a) mobilities, (b) lifetimes, and (c) diffusion lengths as a function of doping concentration, calculated using the empirical equations (2.140) to (2.143). 64 2 Basic Device Physics 2.2.5 2.2.5.1 Time-Dependent and Switching Characteristics As discussed in Section 2.2.2, there is a capacitance associated with the depletion layer of a diode. As the diode is switched from off (zero-biased or reverse-biased) to on (forward biased), it takes some time before the diode is turned on and reaches the steady state. This time is associated with charging up the depletion-layer capacitor and filling up the p- and n-regions with excess minority carriers. Similarly, when a diode is switched from the on state to the off state, it takes some time before the diode is turned off. This time is associated with discharging the depletion-layer capacitor and discharging the excess minority carriers stored in the p- and n-regions. The majority-carrier response time, or dielectric relaxation time, is negligibly short, on the order of 10-12 s, as shown in Section 2.1.4.8. Consider the time needed to charge and discharge the depletion-layer capacitor. From Fig. 2.16, the depletion-layer capacitance Cd is typically on the order of! iF111m2• To turn a diode from offto on, and from on to off, the voltage swing Vis typically about 1 V. If the diode is connected so that it carries a current density J of 1 mA/!1ffi2, then the time associated with charging and discharging the deplection-layer capacitor is on the order of CdVIJ, which is on the order of 10-12 s. Of course, this time changes in proportion to the current density J. However, as we shall show below, the time needed to charge and discharge the depletion-layer capacitor is usually very short compared' with the time associated with charging and discharging the p- and n-regions of their minority carriers. Excess Minority Carriers in the Base and Base Charging Time Consider an n+-p diode with a p-region base width W. When a forward bias is applied to it, minority-carrier electrons are injected into the base. As discussed in Section 2.2.4, for a wide-base diode, the minority-carrier density decreases exponentially with increasing distance, and practically all the minority carriers recombine before they reach the minority-carrier sink at x W. For a narrow-base diode, on the other hand, practically all the minority carriers can travel across the base region without recombining. The total excess minority-carrier charge (electrons) per unit area in the p-type base region is QB r-q (np npO)dx. (2.144) For a wide-base diode, substituting Eqs. (2.126) and (2.127) into Eq. (2.144), we obtain Qs (wide base) npO)x=o LII = 0)1:11, where we have used 1:" L~/Dn from Eq. (2.1 For a narrow-base diode, substituting Eqs. (2.130) and (2.131) into (2.144), we obtain Qa (narrow base) -q(np npO)x=o (~ 1n (x = (2.146) 2.2 p-n Junctions 65 where the base-transit time tB is defined 'Q~ Tnarrow base) lB 1n (x 0) W2 (2.147) As will be shown below, tB is also equal to the average time for the minority carriers to traverse the narrow base region. In a wide-base diode, it takes a time equal to the minority-carrier lifetime to fill the base with minority carriers. In a narrow-base diode, it takes a time equal to the base-transit time to fill the base with minority carriers. It should be noted that the charging current, In(x''' 0), is different for wide-base and narrow-base diodes. The dependence ofIn(x '" 0) on base width is shown in Fig. 2.22. 2.2.5.2 Average Time for Traversing a Narrow Base From Eq. (2.130), the excess electron concep.tration at any base region is np - npo = (np (I - ~). x in the narrow p-type (2.148) Let vex) be the apparent velocity of these excess carriers at point x. The current density due to those excess carriers at x is then In(x) = -qv(x)(np - = -qv(x)(np - npO)x=o(l ~). (2.149) The electron current density at x= 0 is given by Eq. (2.131), i.e., I n (x 0) = (np (2.150) Assuming negligible recombination in the narrow base region, then current continuity requires In(x) to be independent ofx, i.e., Dn vex) W-x' (2.151) The average time for traversing the base is thus given by {w dx tavg Jo w2 2Dn ' (2.152) Comparison of Eqs. (2.147) and (2.152) shows that the base-transit time is equal to the average time for the minority carriers to traverse the narrow base. It is instructive to esimate the magnitude of tB' Modem n-p-n bipolar. transistors typically have base widths of about 0.1 11m, and a peak base doping concentration of about 2 x 1018 cm-3 (Nakamura and Nishizawa, 1995). The corresponding minority electron mobility, from Fig. 2.24, is about 300 cm2N-s. The base-transit time is therefore less than 1xl 0- 11 s, which is extremely short compared with the corresponding 66 2 Basic Device Physics (al VF R VR R .r o t (b) ----i(t-) j fF _fRIO i(t) 1<0 i(l) 1>0 •x Is ~- (c) (np-npIJ) ~~~~~....... x o Figure 2.25. Schematics showing the switching ofan n+-p diode from forward bias to reverse bias: (a) the circuit schematics, (b) the diode current as a function of time, and (c) the excess-electron distribution in the base for different times. minority-carrier lifetime on the order of 1x 10-7s. Recombination is negligible in the base layers o/modern bipolar transistors. 2.2.5.3 Discharge Time of a Forward-Biased Diode Consider an n+'-p diode in a circuit configuration shown in Fig. 2.25(a). For simplicity, let us assume the external voltage, VF or VR, driving the circuit to be large compared to the internal junction voltage, i.e., the voltage immediately across the diode depletion layer, which is typically less than 1.0 V. At t < 0, there is a forward current of lp::::: VF I R as illustrated in Fig. 2.25(b), and an excess electron distribution in the base region as illustrated in Fig. 2.25(c). At time t 0, the external bias is switched to a reverse voltage of VR . The excess electrons in the base start to diffuse back towards the depletion region ofthe diode. Those. electrons at the edge of the depletion region are swept away by the electric field in the depletion region towards the n+ emitter at a saturated velocity of about 107 cmls. As shown in Fig. 2.16, the depletion-layer width is typically on the order of 0.1 pm. The .transit time across the depletion region is typically on the order of I0-128. As we shall see later, except for diodes of very narrow base widths, this time is extremely short compared to the total time for emotving the excess electrons out of the base Thus, as long as 2.2 p-n Junctions 67 there are sufficient excess electrons in the base region, the reverse current is limited not by the diffusion ofexcess electrons but by the external resistor and has a value of1R::::: VR / R, and the slope (dnp / dx)x=o, being proportional to is approximately constant. As the excess electrons are discharged, part of the external voltage starts to appear across the p-njunction, and the junction becomes less forward biased. However, as long as there is still an appreciable amount of excess electrons stored in the base, the amount of external voltage appearing across the p-njunction remains very smalL This is evident from Eq. (2.107), which indicates that even after the excess-electron concentration at the edge of the depletion layer has decreased by a factor of 10, the junction voltage has changed by 2.3kT I q, or 60mY. This is consistent with our assumptions that the reverse current remains essentially constant. During this time, the diode remains in the on condition. At time t= ts, the excess electrons have been depleted to the point that the reverse current is limited by the diffusion ofelectrons instead ofby the external resistor. The rate of voltage change across the junction increases. Finally, when all the excess electrons are removed, the p-n diode is completely off The external reverse-bias voltage appears entirely across the junction, and the reverse current is limited by the diode leakage current. The time needed to switch off a forward-biased diode can be estimated from a charge control analysis (Kuno, 1964). For simplicity, we shall estimate only the time during which the reverse current is approximately constant, and during which the diode remains in the on condition. Since the junction voltage remains approximately constant during this time, charging and discharging ofthe depletion-layer capacitance ofthe junction can be ignored. Let us consider the change in the amount of charge within the p-type base region. From Eq. (2.110), the continuity equation governing the electron concentration in the base region is ot a(np npO) A diode loin (t) A np npO q -0X - diode 'tn (2.153) where in(t) is the time-dependent electron current in the base region and Adiode is the cross sectional area of the diode. Multiplying (2.153) by -q and integrating over the base region, we have o - Adiodeq npO) dx IW o ~ [)in d(t)x (2.154) + 'n Adiode JW (np 0 dx, or . In(O, t) = A,liode dQn (t) -d- + QB (t) Adiode - + . In (W, t 'tn (2.155) where Qo(t) is the excess minority charge per unit area stored in the base region, given by (2.144). Equation (2.155) is simply the continuity equation for the base region stated in the charge-control form. in(O, t) is the electron current entering the base region. and 68 2 Basic Device Physics iiW, t) is the electron current leaving the base region. At x W, the electrons represented by in(W, t) can simply exit the base region and continue on as an electron current outside the base, which is the case for electrons exiting the base ofan n-p-n bipolar transistor (to be discussed in Chapter 6). Alternatively, the electrons represented by in{W, t) can recombine with holes at the base ohmic contact located at x W. The recombination gives rise to a current equal to iiW, t) outside the base region. In either case, the current iiW, t) is continuous across the base boundary atx = W, as required by charge conserva tion. The current flowing through the external resistor R is In(O, t). It is tempting to equate the current difference in (0, t) - in t) to the resistor current, but that is an inaccurate picture of current continuity. To see this, let us consider the steady-state situation when dQB(t)ldt = 0, and the special situation where recombina tion within the base is negligible (1'» -> 00). In this case, Eq. (2.155) gives i nCO) -i iw)= O. However, the resistor current is not zero. The resistor current is in(O), which is equal to inCW) in this special case. Consider a forward-biased diode being discharged. In this case, In(O, t) is due to electrons diffusing back towards the n+ emitter. For the coordinates system used here (see Section 2.2.4.1), these electrons travel in the -x direction. Therefore, In(O, t) is a positive quantity, and Eq. (2.155) gives Adiode dQB (t) -d- t + Adiode QB (t) -'n- + . In (W,t) h (2.156) Equation (2.156) is the continuity equation stated in the charge-control form for the base region of a diode at the initial stage of being discharged. • Discharge time for a wide-base diode. For a wide-base diode, in(W, t) =0 and the solution for Eo. (2.156) is Adiode QB (1) = lr.f. 'tn + [Adiode QB I R '1:,,] exp( -1/'t/l) , (2.157) or QB 1 I R '1:/I Adiode QB (0) [I exp(-t + exp(-tl (2.158) where QeeO) is the excess minority charge per unit area justafter the diode is switched from forward bias to reverse bias. For a wide-base diode, (2.145) gives AdiodeQB(O) -rnh· (Note the negative sign in QB, since QB is negative for elec trons.) Therefore, Eq. (2.158) QB IR [I QB h +exp(-( 1 Figure 2.26 is a plot ofthe charge ratio QIi(t)/QB(O) as a function of tlrn with the current ratio IR1IF as a parameter. It shows that a forward-biased wide-base diode discharges with a time constant approximately equal to the minority-carrier lifetime, unless the reverse discharge current is much larger than the forward charging current. Even for IRIh 10, the diode discharges in a time ofapproximately 'n 110 which, as can be seen 2.2 p-n Junctions 69 ell .~ 0.8 1\\ \ 'I "' '1 j o 1 'Ci ,g £ -+-1-1- - + - [RifF'" 0.5 00 0.2 0.4 0.6 0.8 Ttme/lifetime (t1r,,) Figure 2.26. Plot of charges ratio Qa(t) / Qa(0) as a function of tI,,, during the discharge of a fOlWard-biased diode, with the ratio of discharge current to charging current, 111/iF, as a parameter. from Fig. 2.24(b), is larger than 10-8 s for most diodes ofpractical doping concentrations. This time is very long compared to the typical switching delays of VLSI circuits. The important point is that it takes a long time to drain offthe excess minority ca"iers stored in a wide-base diode and turn it off It is important to minimize excess minority carriers stored in forward-biased diodes if these diodes are to be switched off fast. • Discharge time for a narrow-base diode. For a narrow-base diode, recombination can be ignored. Therefore, we have lin(O)1 = linCw)1 IF while the diode is in forward bias, and the distribution of excess electrons in the base has a constant gradient given by Eq. (2.130). At t> 0, after the diode has been switched from forward bias to reverse bias, electrons continue to flow towards and recombine at the base contact, lin(W, t)1 > O. As we shall show below, a narrow-base diode discharges in a time very small compared to Tn' That is, during the discharge of a narrow-base diode, the recombination term can be neglected, and the minority electrons are discharged only through back diffusion towards the n+ emitter and recombination at the base contact. With this approximation, (2.156) reduces to Adiode dQB(t) ---;;;- = IR . In (W,/). (2. To get an idea of how fast a narrow-base diode can be discharged, let us assume that the gradient ofthe electron distribution atx = Wremains about the same for a short time immediately after the diode is switched to reverse bias as during forward bias. That is, for a short time after switching from forward bias to reverse bias, we have W, I) ~ -h. [Note the negative sign for in(W, I). Electrons flowing in the x-direction lead to a negative current.] Also, we note that Eq. (2.146) gives AdiodeQB(O) = -IBIF for a narrow-base diode, where Is is the base transit time. With these assumptions, Eq. (2.160) gives QB (t) QB (0) ~ I (2. 70 2 Basic Device Physics for a short time after switching from on to off. Equation (2.161) shows that the discharge time for a narrow-base diode lasts approximately tB/;-/(/R + IF) which, for a large IR/IF ratio, can be much shorter than the base transit time. A complex but closed-form solution can be obtained in the large I R/h limit (Lindmayer and Wrigley, 1965), which shows that most of the charge has come out by about tB/3. The important point is that a forward-biased narrow-base diode can be switched offfast. 2.2.6 Diffusion Capacitance For a forward-biased diode, in addition to the capacitance associated with the space-charge layer, there is an important capacitance component associated with the rearrangement of the excess minority carriers in the diode in response to a change in the applied voltage. This minority-carrier capacitance is called diffitsion capacitance Consider an n+-p wide-emitter narrow-base diode, a diode where the depth or width of the n+ emitter region is large compared to its hole diffusion length and the width of the p-type base region is small compared to its electron diffusion length. (This diode is of interest because it represents the emitter-base diode of an n-p-n bipolar transistor.) When a voltage Vapp is applied across the diode, an electron current of magnitude In is injected from the emitter into the base and a hole current ofmagnitude Ip is injected from the base into the emitter. The diode current is In + Ip. Both In and Ip are proportional to exp(qVapp/kT). • Quasisteady state. In a quasisteady state, the voltage is assumed to vary slowly in time such that the minority charge distribution can respond to the applied voltage folly without any delay. In this case, the excess electron charge in the base is given by Eq. (2.146), i.e., Adiode IQn ( Vapp)tB (narrow base), (2.162) which in tum gives 6. IQn(Vapp) I Adiode---z:;:v;;;- q( ) kT In Vapp ts In(Vapp) (2~:J (narrow base), (2.163) whcre we have used Eq. (2.147) for the base transit time te. In Eq. (2.163), WB is the base width and DlIs is the electron diffusion coefficient in the base. Similarly, using (2.145) and Eq. (2.116), we have A"iode 6.IQ6p. V(aVpappp )I Ip( Vapp)rpE kqT Ip(Vapp ) (L~E) DpE emitter) (2.164) 2.2 p-n Junctions 71 for the stored holes in the n+ emitter, where LpE, DpE, and 'pE are the diffusion length, diffusion coefficient, and.lifetime, respectively, ofholes in the emitter. Equations (2.163) and (2.164) relate the change in the stored charge caused by a change in the voltage across the diode in a quasisteady state. However they do not represent the true diffusion capacitance components of a forward-biased diode, which we shall discuss next. • Diffitsion capacitance components. Consider the discharge of a forward-biased base ° region illustrated schematically in Fig. 2.25(c). When the diode is forward biased, the electron distribution is represented by the curve. When the forward bias is reduced, or when the diode is switched to reverse bias, the electron distribution evolves as a function of time, as indicated by the t> 0 curves. Part of the excess electrons diffuses to the left (back towards the emitter) and part ofthem diffuses to the right. The opposing electron currents suggest that the net charge moved through the external circuit in the discharge process is less than the total stored charge represented by the t= 0 curve in Fig. 2.25(c). When an ac voltage is applied across the diode, only those electrons iocated sufficiently close to the depletion-region boundaries can keep up with the signal and get into and out of the base. The exact amount depends on the signal frequency. These signal-following electrons give rise to in(O, t), the time dependent electron current at the emitter end of the quasineutral base region. As discussed in Section 2.2.5.3, inCO, t) is the electron component of the current in the external circuit. Similarly, if we consider the stored holes in the emitter, the signal following holes in the n+ emitter give rise to a hole current component iiD, t) at the base end ofthe emitter region and in the external circuit. These signal-following stored charges are responsible for the diffi.).sion capacitance. The exact diffusion capacitance components can be derived from a frequency dependent small-signal analysis of the current through a diode starting from the differential equations governing the transport of minority carriers (Shockley, 1949; Lindmayer and Wrigley, 1965; Pritchard, 1967). This is done for a wide-emitter narrow-base diode in Appendix 6. Here we simply state the results. For a wide-emitter and narrow-base n+-p diode, the low-frequency diffusion capa citance due to the excess electrons in the base is C DII _ - qIn k(VTapp) ( W~) 3DnB ="32 kqTIn(Vapp)tB {narrow base), (2.165) and that due to the excess holes in the emitter is C Dp qIp(kVTapp) (L~E) 2DpE 2I" kqT Ip (VapP)'pE (wide emitter). (2.166) The total diffusion capacitance is + CD CDlI C Dp . (2.167) Comparison with Eqs. (2.163) and (2.164) shows that 2/3 of the stored charge in the narrow base and \12 ofthe stored charge in the wide emitter contribute to the diffusion capacitance of a forward-biased diode. [In the case of a narrow base, a closed-fonn 72 2 Basic Device Physics solution can be obtained in the large-discharge-current limit for the transient discharge current Integration of the transient discharge current shows that 2/3 ofthe total stored charge in the narrow base diffuses back to the emitter when the base region is discharged. This fraction is the same as the fraction oftotal stored charge in the base contributing to the diffusion capacitance. In other words, one can think of the diffusion capacitance as coming from the portion ofthe stored minority charge that is "reclaimable" in the form of an ac current as the diode responds to an ac signal (Lindmayer and Wrigley, 1965).] It is instructive to examine the relative magnitude of the two capacitance compo nents GDn and Using the hole equivalent ofEq. (2.127) for hole current and Eq. (2.131) for electron current, and the relationship in Eq. (2.116), we have GDn (narrow base) GDp (wide ernitter) - 2 N- E W-B 3 NB LpE (2.168) The ratio NE/NB is typically about 100 for an n+-p diode. For an emitter with NE = 1 x 102ocm-3, is about 0.3 j.lm (see Fig. 2.24). Therefore, for one-sided diodes where the base width is larger than 0.03 j.lm, the ratio CDnlGDp is much larger than unity. That is, the diffusion capacitance of a one-sided p-n diode is dominated by the minority charge stored in the base of the diode. The diffusion capacitance due to the minority charge stored in the emitter is small in comparison. The effect of heavy doping, when included, will increase the amount of stored charge and hence the diffusion capacitance. Since the heavy-doping effect is larger in the more heavily doped emitter than in the I it will make the ratio CDn CDp smaller than that given by Eq. (2.168) Exercise 2.18). 2.3 MOS Capacitors The metal-oxide-semiconductor (MOS) structure is the basis of CMOS technology. The Si-Si02 MOS system has been studied extensively (Nicollian and Brews, 1982) because it is directly related to most planar devices and integrated circuits. In this section, we review the fundamental properties ofMOS capacitors and the basic equations that govern their operation. The effects ofcharges in the oxide layer and at the oxide-silicon interface are discussed in Section 2.3.6. 2.3.1 2.3.1.1 Surface Potential: Accumulation, Depletion, and Inversion Energy-Band Diagram of an MOS System The cross section of an MOS capacitor is shown in 2.27. It consists of a conducting gate electrode (metal or heavily doped polysilicon) on top of a thin layer of silicon dioxide grown on a silicon substrate. The energy band diagrams ofthe three components when separate are shown in Figure. 2.28. Before we discuss the energy band diagram of an MOS device, it is necessary to first introduce the concept electron level and work jUnction which play keyro1cs in the relative energy band placement when two different materials are brought into contact. Figure 2.28(c) shows the band diagram ofa 2.3 MOS Capacitors 73 Gate electrode (metal or polysilicon) t", Silicon substtate Silicon '"dioxide Figure 2.27. Schematic cross section of an MOS capacitor. Free · elevleel ctrol.lT Ec q,. =4.lOeV 95ev Free -,----,- electron level r :i.............I.. IE Ef 8-9 eV .Epe t _._--_. Ei 8= V qB E 1.12 e f Ev Metal (aluminum) Silicon Ev (p-type) Figure 2.28. Silicon dioxide (al (b) (c) Energy-band diagram of the three components of an MOS capacitor: (a) metal (aluminum), (b) silicon dioxide, and (c) p-type silicon. p-type silicon with the addition of the free electron level at some energy above the conduction band. The free electron level is defined as the energy level above which the electron is free, no longer bonded to the lattice.) In silicon, the free electron level is 4.05 eV above the conduction band edge, as shown in Figure. 2.28(c). In other words, an electron at the conduction band edge must gain an additional energy of 4.05 eV the electron affinity, in order to break loose from the crystal field of silicon. 2.28(b) shows the band diagram of silicon dioxide - an insulator with a large energy gap in the range of 8-9 eV. The free electron level in silicon dioxide is 0.95 eV above its conduction band. 3 In other texts, the free electron level is often referred to as the vacuum level. Here we use a dif~;rent term to avoid the implication that the vacuum level is universal. 2 Basic Device Physics Free ---.-,-""71"--.---. electron level Free __ electron level Ef Ee f.---.-I---.~~l.. Ef Ef i--·t:===== Ef SiC. SiOz (a) (b) Rgure 2.29. BanddiagramsofanMOS system under (a) theflatband condition, and (b) zero gate-voltage condition. Work function is defined as the energy difference between the free electron level and the Fermi level. For the p-type silicon example in Fig. 2.28(c), the work function, q

s = qX + Eg 2 + qlf/IJ. (2.169) Here If/B is the difference between the Fermi potential and the intrinsic potential given by Eq. (2,48). The same definition of work function, q 0), the current is dominated by the emission from the semiconductor into the metal. For a reverse-biased diode (Vapp < 0), the current is dominated by the emission from the metal into the semiconductor. Equation (2.242) shows that, when barrier lowering effect is ignored, a Schottky barrier diode has 1- V characteristics similar to those of a p-n diode [cf. Eq. (2.102)], with an exp(q J!.,p,Jk1) dependence on Vopp in forward bias, and a saturation current that is independent of V"pp in reverse bias. • Including Barrier Lowering Effect. There is a subtle difference between a Schottky diode and a p-n diode when barrier lowering effect is included When barrier lowering effect is included, the Schottky barrier qtPBn in Fig. 2.55 and in Eqs. (2.237) to (2.242) should be replaced by an effective Schottky barrier q(tPan - I1tP). The barrier-lowering term q I1tP depends on the applied voltage through the electric field ifm [see Eq. (2.232)]. As'discussed in Section 2.4.1.4, a forward bias (J!.,pp > 0) reduces ql1tP and hence increases the effective Schottky barrier, while a reverse bias (J!.,pp < 0) increases ql1tP and hence reduces the effective Schottky barrier. Thus, replacing q¢Bn by q(¢Bn -11¢) in Eq. (2.242) suggests that the forward-bias current ofa Schottky diode increases with v"pp at a rate somewhat slower than exp(q v"pJk1). This should be compared with the forward-bias current of a p-n diode which is proportional to exp(qVupplk1) [see (2.123)]. See also Fig. 2.23. In the literature, more complex theories have been proposed for describing the trans port process in Schottky diodes. There is a diffusion emission theory which includes the effect of electron collisions within the semiconductor depletion region. There is also a theory which combines the physics involved in the simple thermionic emission process and the diffusion emission process (Crowell and Sze, 1966a). All theories result in an equation similar to Eq. (2.242), with the difference only in the pre-exponential factor. The interested reader is referred to the literature for the details (Sze, 1981; Henisch, 1984). From a device point ofview, the important I-Vcharacteristics of a Schottky barrier diode are contained in the exponential factors in Eq. (2.242), namely in the exp(-q¢B"Ik1) dependence on q¢Bn and the [exp(qVapplk1) I] dependence on qv"pp. 2.4.3.2 Field Emission and Thermionic~field Emission If the semiconductor is heavily doped, the depletion region thickness will be thin, and the electron transport can become dominated by a combination of field emission and thermionic-field emission. In this case, large currents can flow even at low applied biases. In general, when field emission and thermionic-field emission dominate the electron transport, a metal-semiconductor contact is no longer useful as a rectifYing diode. As a result, we will not consider the general theory of field emission and thermionic-field emission any further. The interested reader is referred to the literature for details (Padovani and Stratton, 1966; Crowell and Rideout, 1969). 120 2 Basic Device Physics -r E --r jq1/Jm I-#«)Y-I E ,,& ~. ~ ,""u_-;~-w)UT-U--- x ~Ef Silicon 1---;::;:; Figure 2.57. Schematic showing the energy bands appropriate for considering field emission in a metal-silicon contact. As illustrated, the Schottky diode is forward biased, as indicated by the Fermi level in the silicon being higher than that in the metal. 2.4.3.3 Schottky Barrier Diode as an Active Device A rectifYing Schottky bamer diode has /-V characteristics similar to those ofa p-n diode, but a Schottky barrier diode is a much faster device than a p-n diode because it is a majority-carner device. As a result, Schottky barrier diodes are often used as microwave diodes and as gates ofmicrowave transistors where speed is important (see e.g., Irvin and Vanderwal, 1969). Also, Schottky barrier diodes are often added to bioolar circuits as voltage clamps to improve circuit speed. 2.4.4 Ohmic Contacts Ohmic contacts are usually made with metal or metal silicide in contact with doped semiconductor. The electron transport process in this case is dominated emission. Let us first consider the tunneling of a conduction-band electron from the quasineutral semiconductor region into the metal. The band bending near the metal semiconductor contact is illustrated in Fig. 2.57. The total band bending is qV'm = q(V'hi Vapp) when a forward bias of Vapp is applied. For a given V"",p, let us assume the conduction-band starts to bend upward at x 0, and the interface is located at x Wd, where Wd is the depletion-layer thickness. Since we are considering an electron in the conduction band, it is convenient to use the conduction-band edge of the quasineutral silicon region Ec{x < 0) as the energy reference, as indicated in Fig. 2.57. II/(X) is the electrostatic potential at location x relative to E,.{x < 0), i.e., -q!p(O) Ec(x < 0), and is thc potential energy ofan electron at location x. The Poisson equation [Eq. (2.44)1 can be integrated twice to give qNdx2 I/f(X ) 2cs; q (2.243) where is semiconductor doping concentration. From Eq. (2.188), we have 2.4 Metal-Silicon Contacts 121 (2.244) In the WK.B approximation for tunneling through an energy barner, the transmission coefficient through the energy barrier represented by -qV'(x) for an electron with energy E is [-4nJW exp I I x, d ~J-qV'(x) - Edx] W -4nI =exp - ,' ~Jq-2N-dX+ 2 [ h Xi 2os; <0) EdX]' (2.245) where the lower integration limit XI is given by -q!p(xl) E. In considering an ohmic contact, we are interested in the current due to electrons tunneling from the quasineutral region of the silicon through the potential barrier into the metal at small applied voltages. These electrons have only thermal energy (kT ~ 26 meV at room temperature) which is small compared to the maximum tunneling bamer height q(l/fbi - which is approximately equal to qV'bi at small Therefore, we can assume the tunneling electrons to have an energy E ~ Ec(x < 0). For these electrons, the tunneling process starts at x I = 0 and the corresponding transmission coefficient is where = Ec(x 0 or I < O. The directions of the currents are depicted in Fig. 5.2. 5.1 Basic CMOS Circuit Elements 259 VOlt, Vdd r--- .-..., Figure 5.4. Va., versus Vm curve (transfer curve) ofa CMOS inverter. Points labeled A, C, E, D, B correspond to the steady state points of operation (circles) indicated in Fig. 5.3(c). There are two points ofoperation where both II' and where and Vdd, and point B where Yin = Vdd and v"w= O. In between, the corresponding v"w is obtained from the intersection of two curves, IMVin) and IP(Yin), as shown in Fig. 5.3(c). In this way, one can construct a v"UI versus Yin curve, ora transfer curve ofthe CMOS inverter in Fig. 5.4. For low values of Yin such as point C, v"UI is high and the nMOSFET is biased in saturation while the pMOSFET is biased in the linear region [Vi"i in Fig. 5.3(c)]. For high Yin such as point D, v"w is low and the nMOSFET is in the linear region while the pMOSFET is in saturation in Fig. 5.3(c)). For point E near Yin Vdj2 [Vin2 in Fig. 5.3(c)], both devices are in saturation. It is in a transition region where v"., changes steeply with Yin. In order for the high-to-low transition of the transfer curve to occur close to the midpoint, Vin = Vd/2, it is desiredfor Ipand INto be nearly symmetrical, as illustrated in the example in Fig. 5.3. This requires the threshold voltages of the n- and pMOSFETs to be symmetrically matched. In addition, since the pMOSFETcurrent per width, Ip = [pi WI" is inherently lower than that of the nMOSFET, In = III Wm the device width ratio in a CMOS inverter should be Wp In (5.1) Wn lp' such that Ip-:::;IN• In the long-channe-1 limit, Inllp r:x PnlPp ~ 4 from Eq. (3.28) and Figs 3.15 and 3.16, assuming matched channel lengths and threshold voltages. For short-channel devices, however, the ratio is smaller since nMOSFETs are more saturated than pMOSFETs. Typically, the current-per-width ratio IJIp is about 2-2.5 for deep-submicron CMOS technologies; therefore, W/WI! =2 is a good-choice for CMOS inverter design. 5.1.1.2 CMOS Inverter Noise Because of the nonlinear saturation characteristics of the MOSFET curves, the curve is also nonlinear_ The maximum slope ofthe high-to-Iow transition 260 5 CMOS Performance Factors Flgure5.S. _____~~lJ;,,~outl ~V;n3 V~VO"12 ........... --'4." __ _ ........... Noise Noise Noise ........... Noise Voul4 -----...... Noise A cascade chain of identical CMOS inverters. The noise voltages at the input of each stage are for the discussion of Fig. 5.7. figure 5.6. Vdd .....1 ;/t'''''' _;/t"-'" .~"" ~~ JJ 1i .. ~~ ......, .,.' .........""...... .' ')-"'-'-~- - _,>,., .' , :"'.~ HU ••••••••• ac5l .// ! '\ .' ". / " ~: \ '. : : "\ 0o·" Solid: V;nl' V!n3 .... Dashed: v..a.V..,4'·" Vdd The solid transfer curve is for odd numbered inverter stages. The flipped, dashed !ransfer curve is for even numbered stages. The connected line segments between the curves depict the trajectory of node voltages through successive inverter stages. ofthe v"UI-Vin curve, IdVQU1Idfi"l, referred to as the maximum voltage gain, is a measure of the (Exercise 4.8) ratio of the two transistors. From the condition W"l,,(Vgsm Vdsn) WpIP(Vgsp, Vdsp), it can be shown that Wngmn + Wpgmp dVin Wngdsn + Wpgdsp ! (5.2) wheregmn == aI.joVgsn, gmp -8Ipj8Vgsp(>O),gdsn == (> 0), etc. gd,p == -8lpj8Vdsp A commonly employed scheme to quantify the noise margin of a transfer curve is to consider a chain of identical inverters in cascade as shown in Fig. 5.5. The solid curve in Fig. 5.6 represents the transfer curve ofinverters #1, #3, ... , i.e., v"u,! vs. f'tnlt v"u13 vs. f'tn3, etc. A complcmentary dashed curve is generated by flipping or mirror imaging the solid curve with respect to the chained line, f'tn = v"",. It represents the inverse transfer curve of inverters #2, #4, #6, ... , i.e., f'tn2 vs.voutb f'tn4 vs. VQut4, etc. In this graphical construction, one can visualize a trajectory of alternating horizontal and vertical lines between the two curves as the node voltal1e makes its transitions through the inverter 5.1 Basic CMOS Circuit Bements 261 stages. Starting with dot il on the solid curve at coordinates (f'tnlt Vautl), the next point i2 is on the dashed curve at coordinates-(v"ut2, f'td. The line between il and i2 is horizontal. since Vin2 Voutl ' The next point i3 is back on the solid curve with coordinates (Vln3, v,,"(3), and is connected to i2 by a vertical line as fin3 =Y:;,ut2, etc. In this example, the . node voltage is pushed after each inverter stage closer and closer to the upper left comer corresponding to v,,"1 Vdd for subsequent odd stages and v"", = 0 for subsequent even stages. Ifthe starting point is below the fin == Vou, intercept such as the circle in Fig. it will be pushed in dotted line segments to the lower right comer, i.e., 0 for subsequent odd stages and v,,"1 Vdd for subsequent even stages. Such a characteristic is called "regenerative" which widens the noise margin as the node voltage is restored to one of the extremes of the binary digital states. To add noise to the above picture, we consider only two inverter stages with the transfer curves depicted in 5.7(a). A positive noise voltage at the input to inverter #1 (Fig. 5.5) kicks the starting point from il to i1' on the solid curve. Ifthere is no noise at the to inverter #2, the output after two inverter stages will end up at point i3 shown. Ifi3 is to the left of il, then there is a net gain of noise margin after the two inverters with noise. On the other hand, ifi3 is to the right of il, then there is a net loss ofnoise margin. In that case, the input voltage to the odd-numbered inverters may keep increasing through repeated cycles with noise. Finally it will cross over the fin VOUI line and the logic state is lost (flipped). The maximum noise voltage that can. be tolerated is then the one that causes i3 to fall back on top of i1. We now add a negative going noise voltage of the same magnitude to the input of inverter #2 (Fig. 5.5). Note that for this example, while a positive going noise voltage is worst at input I, a negative going noise is worst at input 2. As shown in Fig. 5.7(b), the negative noise voltage kicks the input to inverter #2 from i2 to i2' . The maximum noise magnitude that can be tolerated without eventually losing the logic state is the one that returns exactly to il after two noisy stages. Therefore, the noise margin for a given transfer curve is measured by the size ofthe maximum square that canfit between itself and its complementary curve (Hill, 1968). A different way of arriving at the same result is described in 9.7 for the noise margin ofSRAM cells. It is evident that for given n and pMOSFETs, a wider noise margin is achieved with the width ratio ofEq. (5.1) so that the high-to-Iow transition of the transfer curve happens at VdJ2. Since most ofthe noise interference in a chip environment originates from coupling of voltage transients in the neighboring lines or devices, the noise magnitude is expected to scale with the power supply voltage (except those with other natural origins such as "soft error" due to high-energy particles). Thermal noise has too Iowa magnitude ofconcern as long as Vdd» kTlq. Therefore, a relevant measure ofthe noise margin in a CMOS circuit is the normalized VNMVdd, where VNM is the side ofthe maximum square in Fig. 5.7(b). Large VN/jVdd (up to 0.5 in principle) is obtained with a highly skewed, symmetric transfer curve, i.e., one that has VOUI staying high at low to medium f'tnt then making an abrupt high-to-low transition at f'tn VdJ2. It can be seen from the construction of the transfer curve in Fig. 5.3(c) that for a given Vdd, VNljVdd improves with a higher threshold voltage, V/Vdd. In fact, the best noise margin is achieved with subthreshold operation (Frank et al., 200 I), although with poor delay performance. As Vdd is scaled 262 5 CMOS Performance Factors (a) Vdd / , ,.,.,.,. ;:;~,_ ;:;'.0i 1] i2\~''''''-'--' i1' .,..,'/ .;,' .................. - .'." /.~---" i"/'- ......, .. ot5l ,/ .' .' . ./ ... .' / .' " .'\ ' '\ \ \ '\ \ Solid: \»nl Vdd Dashed: VO"t2 -~"i:i ].. ot5l Figure 5.7. Solid: \».1 \'ad Dashed: Vout2 (a) Node voltage trajectory with noise added to the input to inverter#l. (b) Node voltage trajectory with positive noise at inverter #1 and negative noise at inverter #2. The shaded area represents the largest square that can be circumscribed in between the two transfer curves. The side of the square, VNM, is a measure of the noise margin. down, VN~Vdd is not particularly sensitive toVdd until Vdd becomes comparable to kTlq. In order to have the nonlinear I-V characteristics necessary for digital circuit function, a minimum Vdd of several kTlq, e.g., 100-200 mY, is required (Swanson and Meindl, 1972). At I V level, the choice of power supply voltage for static CMOS logic circuits is largely based on power and performance considerations discussed in Section 5.3.3, not noise margin. 5.1.1.3 CMOS Inverter Switching Characteristics We now consider the basic switching characteristics of a CMOS inverter. The simplest waveform is when the gate voltage makes an abrupt or infinitely sharp transition 5.1 Basic CMOS Circuit Elements 263 from low to high or vice versa. For example, consider the inverter biased at point A in Fig. 5.3(a) when ~n makes asreptransition from 0 to Vdd. Before the transition, the nMOSFET is off and the pMOSFET is on. After the transition, the nMOSFET is on and the pMOSFET is off. The trajectory of v.,ut from point A to point B follows the ~n = Vdd curve ofthe nMOSFET as shown in Fig. 5.3(a). lfthe total capacitance ofthe output node (including both the output capacitance ofthe switching inverter and the input capacitance of the next stage or stages it drives) is represented by two capacitors one (C) to the ground and one (C+) to the Vdd rail, as illustrated in Fig. 5.2 - then the pull-down switching characteristics are described by C + C d(Vout - Vdd) -J (V = - + dt Nm or (C_ + C+) dV"ut = Vdd ), (5.3) with the initial condition Vouit=O)= Vdd. Here C = C_ + C+ includes both the capacitance to ground and the capacitance to Vdd. For simplicity, we approximate the IN ( ~n = Vdd) curve by two piecewise continuous lines. In the saturation region (v.,ut > V~~ 07 5.5 A similar distributed network to the one in Fig. 5.21 can be used to formulate the transmission-line model of contact resistance in a planar geometry (Berger, 1972). Here we consider the current flow from a thin resistive film (diffusion with a sheet resistivity Psd) into a ground plane (metal) with an interfacial contact resistivity Pc between them (Fig. 5.16). Thus, i~Fig. 5.21, R dxcorresponds to (Psd/ W)dx, and C dx is replaced by a shunt conductance G dx, which corresponds to (W/Pc)dx. Show 316 5 CMOS Performance Factors that both the current and voltage along the current flow direction satisfy the following differential equation: d2j ==RGf= PsdJ, dx2 Pc ) wherej{x) = V(x) or /(x) defined in Fig. 5.21. 5.6 Following the above transmission-line model, with the boundary condition l(x Ie) =0 where x =0 is the leading edge and x = Ie is the far end of the contact window (Fig. 5.16), solve for V(x) and l(x) within a mUltiplying factor and show' that the total contact resistance, Reo = V(x =OY/(x= 0), is given by Eq.(5.11). 5.7 The insertion of a buffer stage (Section 5.3.2) between the inverter and the load is beneficial only ifthe load capacitance is higher than a certain value. Find, in terms of Cin and COUI, the minimum load capacitance CL above which the single-stage buffered delay given by Eq. (5.45) is shorter than the unbuffured delay given by Eq. (5.43). 5.8 Generalize Eq. (5.44) for one-stage buffered delay to n stages: if the width ratios of the successive buffer stages are kl> k2, k3, ... , kn (all >1), show that the n-stage buffered delay is 'ben) == Rsw [(n+ I)Cout + (k1 + k2 + ... + kn)Cin + klk~~. kJ 5.9 Following the previous exercise, show that for a given n, the n-stage buffered delay is a minimum, CL) l/(n+l'] 'Cbmin(n)=Rsw (n+I)Coul + (n+l)Cin ·C ' [ ( in whenkl k2 = ... =kn (CL/Cin}I/(n+1).Here'Cbmin(n),asexpected,isreduced to Eq. (5.45) if n = I. 5.10 Ifone plots the minimum n-stage buffered delay from the previous exercise versus n, it win first decrease and then increase with n. In other words, depending on the ratios of CdC" and CadCm, there is an optimum number of buffer stages for which the overall delay is the shortest. Show that this optimum n is given by the closeSt integer to In(CL/Cin ) I n Ink -, where k is a solution of k(ln k-I) = Caul Cm For typical Cou/Cjn ratios not too different from unity, kis in the range of3-5. Note that k also gives the optimum width ratio between the successive buffer stages, i.e., kl =k2 = ... = kn=k. Also show that the minimum buffered delay is given by 'Cbmin ~ kRswCin In(CL/Cin ), which only increases logarithmically with load capacitance. Exercises 317 5.11 Consider a chain of CMOS inverters with power supply Vdd. The propagation delay between the waveforms can he..expressed by Eq. (5.39) with FO =1. What is the power dissipation while the signal is propagating down the chain? If the device widths are increased or decreased by a factor of k (>lor ~~*'TY'Oh.....l'" .fA... ""'" .... '" .... h ...·..... ";"'t....? <:>""A .,.. ...............rq.... t>; ...f"'... 320 6 Bipolar Devices layer on top of the base region. Adjacent transistors are isolated from one another by p-type pockets, as illustrated in Fig. 6.1 (b), or by oxide-filled trenches. The process for fabricating a typical advanced vertical n-p-n bipolar transistor having an implanted base region is outlined in Appendix 2. Figure 6.1 (c) shows the bias condition for an n-p-n transistor in normal operation. The emitter-base diode is forward biased with a voltage VBE, and the base-collector diode is reverse biased with a voltage VCB' The corresponding energy-band diagram is shown schematically in Fig. 6.1 (d). The forward-biased emitter-base diode causes electrons to flow from the emitter into the base and holes to flow from the base into the emitter. Those electrons not recombined in the base layer arrive at the collector and give rise to a collector current. The holes injected into the emitter recombine either inside the emitter or at the emitter contact. This flow of holes gives rise to a base current. (The operation of a bipolar transistor having both the emitter-base and collector-base diodes forward biased will be discussed in Section 9.1.3 in the context of bipolar inverter circuits and memory cells.) Also illustrated in Fig. 6.1 (d) are the coordinates which we will follow in describing the flow of electrons and holes. Thus, electrons flow in the x-direction, i.e., In(x) is negative, and holes flow in the -x direction, i.e., Jp(x) is also negative. The physical junction of the emitter-base diode is assumed to be located at "x=O". However, to accommodate the finite thickness of the depletion layer of the emitter-base diode, the mathematical origin (x = 0) for the quasineutral emitter region is shifted to the left of the physical junction, as illustrated in Fig. 6.I(d). Similarly, the mathematical origin (x=0) for the quasineutral base region is shifted to the right ofthe physical junction. The emitter contact is located at x=-WE, and the quasineutral base region ends at x= WB. It should be noted that, due to the finite thickness of a junction depletion layer, the widths of the quasineutral p- and n-regions of a diode are always smaller than their corresponding physical widths. Unfortunately, in the literature as well as here, the same symbol is often used to denote both the physical width and the quasineutral width. For example, WB is used to denote the base width. Sometimes WB refers to the physical base width, and sometimes it refers to the quasineutral base width. The important point to remember is that all the carrier-transport equations for p-n diodes and for bipolar transistors refer to the quasineutral widths. In the literature, several different circuit symbols have been used for a bipolar transistor. In this book, we adopt the symbols illustrated in Fig. 6.1 (e). The arrow indicates the direction of positive current flow in the emitter. For instance, in the n-p-n transistor, the emitter current is due primarily to electrons flowing from the emitter region towards the base region. Hence, the direction of positive current flow is from the base towards the emitter terminal. Similarly, in the p-n--p transistor, the emitter current is due primarily to holes flowing from the emitter region towards the base region, thus giving rise to a positive current flow from the emitter terminal towards the base. Figure 6.2(a) illustrates the vertical doping profile of an n-p-n transistor with a diffused, or implanted and then diffused, emitter. The emitter junction depth XjE is typically 0.2 )lm or larger (Ning and Isaac, 1980). The base junction depth is XjB, and the physical base width is equal to XjB - XjE' Figure 6.2(b) illustrates the vertical doping 6.1 Jl-IH1 Transistors 321 f--- xjB ----: ,~ xjE " ------l ': IE+21 : ;;;' JE+20 E ~ c:: IE+!9 0 .~ 1: IE+18 gQ) 0 U lE+17 IE+16! ,!,'!, ,! , o 0.2 0.4 0.6 0.8 Depth ().Lm) (e) XjE -... ...-- JE+2P1o~! l"ysilico.n.!.~ ,:x'B n-type:, :, :::- IE+20 I S (.) 'c-:' 1E+19 .: 1: ..9... ~ 1E+18 n .I; "~ "" ! !1.) " (c.:) 0 U lE+17 Figure 6.2. IE+16 0 0.2 0.4 0.6 0.8 Depth (j.lm) (b) Vertical doping profiles of typical n-p-n transistors: (a) with implanted and/or diffused emitter, and (b) with poJysilicon emitter. 322 6 Bipolar Devices profile ofan n-p-n transistor with a polysilicon emitter. The polysilicon layer is typically about 0.2 llm thick, with an n+ diffusion into the single-crystal region of only about 30 nm (Nakamura and Nishizawa, 1995). That is, XjE is only about 30 nm. The base widths of most modem bipolar transistors are typically O.lllm or less. While one of the goals in bipolar transistor design is to achieve a base width as small as possible, there are tradeoffs in thin-base designs, as well as difficulties in fabricating thin-base devices. Suffice it to say that the base of a polysilicon-emitter transistor can be made much thinner than that of a diffused-emitter transistor. Details of the doping profiles of the base and collector regions are determined by the desired device dc and ac character istics and will be discussed in Chapter 7. 6.1.1 Basic Operation of a Bipolar Transistor As illustrated in Fig. 6. I (a), a bipolar transistor physically consists of two p-n diodes connected back to back. The basic operation of a bipolar transistor, therefore, can be described by the operation of two back-lo-back diodes. To tum on an n-p-n transistor, the emitter-base diode is forward biased, resulting in holes being injected from the base into the emitter, and electrons being injected from the emitter into the base. In normal operation, the base--colleclor diode is reverse biased so that there is no forward current flow in the base-collector diode. (In some circuits, e.g., in simple bipolar inverters and bipolar memory cells, a bipolar transistor may operate having both the emitter-base and collector-base diodes forward biased. Operation of such circuits is discussed in Section 9.1.3.) The bias condition and the energy-band diagram of an n-p-n transistor in normal operation are illustrated in Figs 6.l(c) and 6.1 (d). As described earlier, as the electrons injected from the emitter into the base reach the collector, they give rise to a collector current. The holes injected from the base into the emitter give rise to a base current. One basic objective in bipolar transistor design is to achieve a collector current significantly larger than the base current The current gain of a bipolar transistor is defined as the ratio of its collector current to its base current. To first order, the behavior of a bipolar transistor is determined by the characteristics of the forward-biased emitter-base diode, since the collector usually acts only as a sink for the carriers injected from the emitter into the base. The emitter-base diode. behaves like a thin-base diode. Thus, qualitatively, the current-voltage characteristics of a thin base diode discussed in Section 2.2.4 can be applied to describe the current-voltage characteristics of a bipolar transistor. 6.1.2 Modifying the Simple Diode Theory for Describing Bipolar Transistors In order to extend the simple diode theory discussed in Section 2.2 to describe the behavior of a bipolar transistor quantitatively, three important effects ignored in it must be included. These are the effects of finite electric field in a quasineutral region, heavy doping, and nonuniform energy bandgap. These effects are discussed below. 6.1 n-p-n Transistors 323 6.1.2.1 Electric Field in a Quasineutral Region with a Uniform Energy 8andgap In Section 2.2.4, the current~voltage 'characteristics of a p-n diode were derived for the case of zero electric field in the p- and n-type quasineutral regions. As will be shown below, the zero-field approximation is valid only where the majority-carrier current is zero and concentration is uniform. For bipolar transistors, as shown in Fig. 6.2(a) and (b), the doping profiles are rather nonuniform. A nonuniform doping profile means that the majority-carrier concentration is also nonuniform. Furthermore, at large emitter-base forward biases, to maintain quasineutrality the high concentration of injected minority carriers can cause significant nonuniformity in the majority-carrier concentration as well. Therefore, the effect of nonuniform majority-carrier concentration in a quasineutral region cannot be ignored in determining the current-voltage characteristics of a bipolar transistor. For a p-type region, Eq. (2.66) gives (p) = CPP !{Ii+kT- In ..!!. , (6.1) q ni where CPP is the hole quasi-Fermi potential and !{Ij is the intrinsic potential. (Note that Pp is equal to Na only for the case of low electron injection, i.e., only at low currents.) The electric field is given by Eq. (2.41), namely q ~_ d!{li kT I dpp dcpp Ii' = - dx Pp dx - dx -kT-I -dpp+ -Jp (6.2) q Pp dx qPP/-Lp' where we have used Eq. (2.64), which relates d¢p/dx to Jp. In Eq. (6.2), the intrinsic carrier concentration is assumed to be independent of x. The dependence of energy bandgap on x will be discussed later in connection with heavy-doping effects. Let us apply Eq. (6.2) to the intrinsic-base region of an n-p-n transistor with a typical current gain of 100. At a typical but high collector current density of I mA/J.l.m2, om the base current density is mNjlID2, i.e., Jp =0.0 I roNjlID2 in the base layer. As can be seen from Fig. 6.2, the base doping concentration is lyJJ.ically on the order ofl018 cm-3, and the corresponding hole mobility is about 150cm2N-s (Fig. 2.8). That is, Pp "" 1018 cm 3 andpp "" 150cm2N-s, and Jplqpppp "" 40 Vlcm, which is a negligibly small electric field in nonnal device operation. Therefore, for a p-type region Eq. (6,2) gives (6.3) Similarly, for an n-type region, ~(n-region) ~ _ kT I dnn (6.4) q nn Equations (6.3) and (6.4) show that the electricjield is negligible in a region o/uniform majority-carrier concentration. 324 6 Bipolar Devices To include the effect of finite electric field, the current-density equations (2.54) and (2.55), which include both the drift and the diffusion ~omponents. should be used. These are repeated here: In(x) = qnlln'if + qDn dn dx' (6.5) and dp lp(x) = qPllp'if qDp dx' (6.6) It should be noted that ifEq. (6.4) is substituted into Eq. (6.5), the RHS ofEq. (6.5) is equal to zero. Similarly, if Eq. (6.3) is substituted into Eq. (6.6), the RHS of Eq. (6.6) is equal to zero. What this means is that the approximations for the electric fields represented by Eqs. (6.3) and (6.4) are good approximations only for describing minority-carrier currents. The dp Idx term, although very small in a p-region, is entirely responsible for the majority-carrier current in a p-region. In fact, from Eq. (2.64), the hole current density in a p-region is lp "" -qpppd¢p Idx. Thus, for describing hole current in a p-region, Eq. (6.2), instead ofEq. (6.3), should be used for the electric field. The electron current in a p-region due to the d¢p Idx term, on the other hand, is negligible. Therefore, Eqs. (6.3) and (6.4) are good approximations for describing minority-carrier currents, i.e., for electron current in a p-region and hole current in an n-region. That is, these approximations are applicable to currents in a diode or in a bipolar transistor. • Built-in electric field in a nonuniformly doped base region. CO::lsider the electron current in the p-type base of a forward-biased emitter-base diode. Let N~) be the doping concentration in the base, and, for simplicity, all the dopants are assumed to be ionized. Quasineutrality requires that pp(x) = NB(X) + np(x). (6.7) Therefore, -ddpxp=d-dNxB+dd-nxp ' (6.8) The built-in electric field ~o is defined as the electric field from the nonuniform base dopant distribution alone, ignoring any effect of injected minority carriers. It can be obtained by substituting NB for Pp in Eq. (6.3), namely == 'f(l1p (6.9) Substituting Eq. (6.3) into Eq. (6.5), and using Eqs. (6.8) and (6.9) and the Einstein relationship, we have, for electron current in a nonuniformly doped p-type base region, lll(x) = qnplln'ifo~ + qDn (2np + NB) dl1p p+NB np+NB dx' (6.1 0) 6.1 n-p-n Transistors 325 Equation (6.10) suggests that the effective electric field 'ife!f in the p-type base can be written as 'ifo~. np+NB (6.11) It should be pointed out that Eqs. (6.1 0) and (6.11) are valid for all levels of electron injection from the emitter, Le., for all values of np • Electric field and current denSity in the low-injection limit. At low levels of electron injection from the emitter, i.e., for np « NB, 'ifeffreduces to 'if!) and Eq. (6. 10) reduces to In(X) ~ qnplln'ifo + qDn ~: ' (6.12) which simply says that the electron current flowing in the base consists of a drift component due to the built-in field from the nonuniform base dopant distrIbution, and a diffusion component from the electron concentration gradient in the base. • Electric field and current density in the high-injection limit. When the electron injection level is very high, i.e., when np »NB, 'if""becomes very small. The built in electric field is screened out by the large concentration of injected minority carriers. Therefore, the electron current component associated with the built-in field becomes negligible, and the electron current density approaches I In(x) n -N ~ ph" B dnp q2Dn -d-X · (6.13) That is, at the high-injection limit, the minority-carrier current behaves as if it were purely a diffusion current, but with a diffusion coefficient twice its low-injection value. This is known as the Webster effect (Webster, 1954). 6.1.2.2 Heavy-Doping Effect As discussed in Section 2.1.2.3, the effective ionization energy for impurities in a heavily doped semiconductor decreases with its doping concentration, resulting in a decrease in its effective energy bandgap. For a lightly doped silicon region at thermal equilibrium, Eqs. (2.13) and (2.16) give the relationship between the product Polio and the energy gap Eg . As the energy gap changes and/or as the densities of states change due the effect of heavy doping, the pono product will also change. For modeling purposes, it is convenient to define an effective intrinsic-carrier concentration n,e and lump all the heavy-doping effects into a parameter called apparent bandgap narrowing, AEg , given by the equation pQ (6.Eg )no (6.EI() n;. = nfexp(6.Eg/kT). (6. The heavy-doping effect increases the effective intrinsic carrier concentration. To include the heavy-doping effect, n; should be rep/aced by nie' Thus, including heavy-doping effect, the product pn in Eq. (2.67) becomes pn = n;eexp[q(p 11)l . kT }' (6.15) 326 6 Bipolar Devices Figure 6.3. ~ -;; 140 120 ~ _ p'type silicon .~ o I- -- - n-type silicon 100 I- - -_. Unified (p and nJ ~ 80 .gg. 60 1! 40 ;: ~ 20 IV.. .. V ..... .1.:5: o 1-;:::'.-., IE+17 IE+IS. v v v ..' _.' ..... IE+19 Doping concentration (cm-3) IE+20 Apparent bandgap narrowing as given by the empirical expressions in Eqs. (6.16H6.18). where ¢p and ¢. are the hole and electron quasi-Fermi potentials, respectively. It is extremely difficult to determine Mg experimentally and there is considerable scattering in the reported data in the literature (del Alamo et al., 1985a). Careful analyses of the reported data suggest the following empirical expressions for the apparent bandgap-narrowing parameter: , t::.Eg(Nd) 18.71n ( 7 xNd1017 ) meV (6.16) for Nd ? 7 x 10! 7 cm- 3, and zero for lower doping levels, for n-type silicon (del Alamo et al., 1985b), and t::.Eg(Na) 9(F+ ..jF2 + 0.5) meV, (6.17) where F = In(N) 1017), for No > 1017 cm-3, and zero for lower doping levels, for p-type silicon (Slotboom and de Graaff, 1976; Swirhun et al., 1986). More recently, using a new model that treats both the majority-carrier and minority-carrier mobilities in a unified manner (Klaassen, 1990), Klaassen et al. (1992) showed that the heavy-doping effect in both n-type silicon and p-type silicon can be described well by a unified apparent bandgap narrowing parameter. If N represents Nd in n-type silicon and Na in p-type silicon, then the Klaassen unified apparent bandgap narrowing parameter is given by r H M,(N) ~ 69+ (L3 :10") + L3 :10") +O+'V (6.18) Figure 6.3 is a plot of Mg a~ a function of doping concentration, as given by Eqs. (6.16) to (6.18). 6.1.2.3 Electric Field in a Quasineutral Region with a Nonuniform Energy Bandgap Aside from the heavy-doping effect, the energy bandgap can also be modified by incorporating a relatively large amount of germanium into silicon. In this case, the 6.2 Ideal Current-Voltage Characteristics 327 bandgap becomes narrower (people, 1986). If both heavy-doping effect and the effect of germanium are included in.the. parameter Mg in Eq. (6.14), then the product pn given by Eq. (6.15) can be used to describe transport in heavily-doped SiGe alloys. When the energy bandgap is nonuniform, the electric field is no longer simply given by Eqs. (6.3) and (6.4), which include only the effect of nonuniform dopant distribution. When the effect of nonuniform energy bandgap is included, the electric fields are given by (van Overstraeten et al., 1973) q~(;p-regl.O)n for a p-type region, and kTU-d- pp - "I 2dn-Te ) q p dx nie dx (6.19) '¥'( fI' n-regl.O)n = -k-T ( -1 -dn-n " 2 I dn-Te ) q nn dx nje dx (6.20) for an n-type region. Derivation ofEq. (6.19) will be shown in Section 7.2.3 in connec tion with the design of the base region of an n-p--n transistor (see Section 7.2.3). 6.2 Ideal Current-Voltage Characteristics In Section 2.2.4, the current-voltage characteristics of a p-n diode were derived assum ing implicitly that the externally applied voltage appears totally across the immediate junction. All parasitic resistances, and the associated voltage drops due to current flow, were assumed to be negligible. With these assumptions, the currents or current densities in a forward-biased diode increase exponentially with the applied voltage. These are the ideal current-voltage characteristics. In practice, the measured current-voltage characteristics of a bipolar transistor are ideal only over a certain range of applied voltage. At low voltages, the base current is larger than the ideal base current. At large voltages, both the base and the collector currents are significantly smaller than the corresponding ideal currents. In this section, the ideal current-voltage characteristics are discussed. Deviations from the ideal char acteristics are discussed in the next section. It was shown in Section 2.2.5 that, for modem bipolar transistors, the base transit time is much smaUer than the minority-carrier lifetime in the base, and there is negligible recombinadon in the ba.~e region. For an n-p-n transistor, neglecting second-order effects, such as avalanche multiplication and generation currents due to defect~ andlor surface states, the base current is due entirely to the injection ofholes from the base into the emitter. Similarly, the collector current is due entirely to the injection of electrons from the emitter into the base. (The effect ofavalanche multiplication in the base--collector junction is considered in Section 6.5, where breakdown voltages are discussed. Also, that recombi nation in the base of modem bipolar transistors is negligible is confirmed in Exercise 6.6). Referring to Fig. 6. I(a), we see that the base terminal contact is located at the. side of the base region. Therefore, the hole current :first flows horizontally from the base tenninal 328 6 Bipolar Devices into the base region and then bends upward and enters the emitter. The horizontal hole current flow causes a lateral voltage drop within the base region, which in tum causes the forward-bias voltage across the immediate emitter-base junction to vary laterally, with the emitter-base forward bias largest nearest the base contact, and smallest furthest away from the base contact This is known as emitter current-crowding effect. When emitter current crowding is significant, the base and collector current densities are not just a function of x [Fig. 6.1 (d)], but also a function of distance from the base contact. Fortunately, as shown in Appendix 16, emitter current crowding is negligible in modern bipolar d£'llices because of their narrow emitter stripe widths. Therefore, we shall ignore emitter current-crowding effect and assume both the base and collector current densities to be uniform over the entire emitter-base junction area. current-Density Equation for Electrons in a p-Type Base Let us consider the electrons injected from the emitter into the p-type base region of an n-p-n transistor. Instead of starting with Eq. (6.10), it is often convenient to reformulate the electron current density in terms of carrier concentrations (Moll and Ross, 1956). To this end, we start with the electron current density given by Eq. (2.63), namely l,,(x) = -qnpp,,, d¢in dx ' (6.21) where ¢in is the electron quasi-Fermi potential. As we shall show later, the hole current density in the p-type base is small, being smaller than the electron current density by a factor ofabout 100 (see Section 6.2.3). Also, as indicated in Fig. 6.2, the base region has a reasonably high doping concentration, typically greater than 10 18 cm- 3 for a modem bipolar transistor. Therefore, the lR drop along the electron-current flow path (which is perpendicular to the intrinsic-base layer) in the p-type base is negligible, which, as discussed in Appendix 4, implies that the hole quasi-Fermi potential ¢ip is approximately constant. That is, we have d¢ip ~ 0 dx . (6.22) in the p-type base region. Combining Eqs. (6.21) and (6.22), we obtain l,,(x) ~ qnp/tn d( VOE, the collector-base diode is reverse biased and the transistor is said to be in its normal forward-active mode of operation. All the electrons injected from the emitter into the base are collected by the collector, as recombination in the intrinsic base is negligible in modem transistors, and there is no electron injection from the collector into the base. The collector current is therefore constant, independent of VCE. The current gain is also constant, and the constant-18 curves are spaced apart by an amount deter mined by the base-current step, as illustrated in Fig. 6.4. 6.3 Characteristics of a Typical n-p-n Transistor 337 Note that the schematic in Fig. 6.4 suggests that the collector current is zero when VCE equals zero. This is only a good appn)~imation. Strictly speaking, the collector current in the saturation region has a component due to the injection of holes from the base into the collector. It will be shown later in Section 6.4.1 that in theory the electron current injected from the emitter into the base at VCE "" 0 cancels exactly the electron current injected from the collector into the base. That this cancellation is almost exact in practical transistors will be shown in Section 7:4.8. Thus, we should expect a small but finite collector current at VeE= 0 owing to the injection of holes from the base into the collector. This current is negative because the holes injected from the base are flowing out of the collector. In a linear plot ofIe versus VeE for a typical bipolar transistor, this hole current is usually too small to be noticeable (see Exercise 9.1 in Chapter 9). The measured current-voltage characteristics of typical bipolar devices are not ideal. The degree of deviation from ideal characteristics depends on the device structure, the device design, the device fabrication process, and on the bias condition of the transistor. The behavior of a typical n-p-n transistor is discussed next. 6.3 Characteristics of a Typical n-p-n Transistor Figure 6.5 is the Gummel plot of a typical n-p-n transistor. It plots both the collector current Ie and the base current IB on a logarithmic scale as a function of the forward-bias voltage VBE applied to the emitter and base terminals. The theoretical ideal base and collector currents, discussed in Section 6.2, are indicated by the dashed lines. Figure 6.5 IE-Ir'--------~~------_, IG~,' : 180 IE-2 II I Ie IE-3 fa $ lE-4 "5 IE-5 ~ U lE-6 IE-7 lE-8 AE= 9!-1Jll' Figure 6.5. IE-9[ I !It IJ 0.4 0.6 0.8 I 1.2 1.4 Emitter-base voltage (V) Gummel plot of a typical n-p--n bipolar transistor. The dashed lines represent the theoretical ideal base and collector currents. (After Ning and Tang, 1984.) 338 6 Bipolar Devices c: il~ Figure 6.6. Collector current Schematic illustration of the current gain IdIB as a function of collector current for a typical bipolar transistor, B E c p n F"1IIur8 6.7. Schematic illustrating the parasitic resistances in a typical modem n-p-n transistor. shows that the measured collector current is ideal except at large VSE, while the measured base current is ideal except at small and at large VBE·, Figure 6.6 illustrates the typical measured current gain, leiIs, as a function ofcollector current. For the voltage range where both the base and the collector currents are approximately ideal, the current gain is approximately constant. At low currents, the current gain is less than its ideal value because the base current is larger than its ideal value. At high currents, the current gain rolls off with collector current because the percentage by which the collector current is smaller than its ideal value is larger than the percentage by which the base current is smaller than its ideal value. The dominant physical mechanisms responsible' for the nonideal behavior of the base and collector currents are discussed in the subsections below. 6.3.1 Effect of Emitter and Base Series Resistances Figure 6.7 shows schematically the physical origins of the parasitic resistances in a typical n-p--n transistor. These resistances are ignored in Section 6.2 in the description of 6.3 Characteristics of a Typical n-p-n Transistor 339 the ideal current-voltage characteristics. As the currents flow through these parasitic resistors, voltage drops are developed, which tend to offset the externally applied voltages. The parasitic resistances can therefore be neglected at low currents but can be very important at large currents. In normal forward-active operation, the base-<:ollectorjunction is reverse biased. In most bipolar circuits, particularly those designed for high-speed applications, the collector--base junction is designed to remain reverse biased at all times, even at high currents. This is accomplished by employing a heavily doped subcollector layer (to reduce rd and a heavily doped reach-through (to reduce rc3) to bring the collector contact to the surface. With the base-{;ollector junction reverse biased, to first order, the collector resistance componentB shown in Fig. 6.7 have no effect on the current flows in the emitter--base diode, and only the parasitic resistances associated with the emitter and the base need to be considered. (The effect ofcollector-base voltage on collector current is discussed in the following subsection.) The emitter series resistance r. is determined primarily by the emitter contact resistance, since the resistance associated with the thin n+ emitter region is small. The base resistance rh can be separated into two components: the intrinsic-base resistance rhi, which is determined by the design of the intrinsic-base region, and the extrinsic-base resistance rbx, which includes all other resistances associated with the base terminal. The emitter-base diode voltage drop due to the flow of emitter and base currents is 1J.VSE -fer. + Isrb = Iere + Is(re + (6.59) where we have used the fact that Ie + Is + Ie O. The relation between the voltage VSE applied to the emitter and base terminals and the voltage V~E appearing across the immediate emitter--base junction is V~E = VSE -1J.Vm;· (6.60) To include the effect ofthe emitter and base series resistances, the equations in Section 6.2 for the ideal collector and base currents should be modified by replacing VBE by V~E This results in both the meaSured collector and base currents, when plotted as a function of VBE, being significantly smaller than the ideal currents at liuge VSE, as illustrated in Fig. 6.5. As can be seen- from Eq. (6.33), even in the ideal case, the collector saturation current density is a function ofthe majority-carrier concentration in the base and the base width. Therefore, the measured collector current is afunction oftfVBE as well as afunction. of the base majority-carrier concentration and the base width, which in turn depend on VBE. The dependence of Ie on VBE is very complex, as can be seen in later subsections. On the other hand, as can be seen from Eqs. (6.43) and (6.49), the base saturation current density is a function of the emitter parameters only, which, due to the emitter being very heavily doped, do not vary with the minority-carrier injection level: Therefore, at high currents, deviation of the base current from its ideal behavior is due to .t1VBE alone (Ning and Tang, 1984). The relation between the ideal base current IBo and the measured base current IB is therefore 180 = IBexp(q1J.VsdkT), (6.61) 340 6 Bipolar Devices which can be used to evaluate the emitter and base series resistances. This is shown in Appendix 15. Many other methods for detennining the emitter and base series resistances have been discussed in the literature (Schroder, 1990). Some of these are discussed in Appendix 15 as well. 6.3.2 6.3.2.1 Effect of Base-Collector Voltage on Collector Current In many transistors, particularly in modem high-speed transistors where the base width is very small, the measured collector current, and hence the measured current gain, increases as the base-collector reverse-bias voltage is increased. This is due to two effects, or a combination of them. The first effect is the dependence of the quasineutral base width on collector-base voltage. The second effect is the avalanche multiplication in the base collector junction. We shall discuss these two effects individually in this subsection. Modulation of Quasineutral Base Width by Base-Collector Voltage As the reverse bias across the base-collector junction is increased, the base-collector junction depletion-layer width increases, and hence the quasineutral base width WB decreases. This in turn causes the collector current to increase, as can be seen from Eq. (6.31). Thus, instead of as illustrated in Fig. 6.4, where the collector current is independent of collector voltage for VCE > VBE, the collector current of a typical bipolar transistor increases with collector voltage, as illustrated in Fig. 6.8. • Early voltage. For circuit modeling purposes, the collector current in the nonsaturation region is often assumed to depend linearly on the collector voltage. The collector voltage at which the linearly extrapolated lcreaches zero is denoted by -VA' As we shall show later, it is a good and useful approximation to assume that VA is independent of VBE. This is illustrated in Fig. 6.8. VA is called the Early voltage (Early, 1952). It is defined by alc -1 VA + VCE == lC(avCE) (6.62) In practice, except for transistors that tend to punch through (to be discussed later), VA is much larger than the operation range of VCEo Therefore, VA can be approximated by IBI IB2 IB3 IB4 Figure 6.8. o ~-I 'BS VCE Schematic illustrating the approximately linear dependence oflc on VCE. The linearly extrapolated Ic intersects the VcE.-axis at - VA' 6.3 Characteristics of a Typical n-p-n Transistor 341 v.~ ~Ie{(,,{:o)VJ~E)-1 (6.63) The collector current is given by Eq, (6.32), which canbe written as qAEexp(qVBslkT) Ie = AEJcOexp(qVBslkT) = F(WB) , (6.64) where, for convenience, a function F has been introduced (Kroemer, 1985) which is defined by r F(WB) q leo = Jo WD DnB(px)pn(~xe)B(x)dx. (6.65) The majority-carrier hole charge per unit area in the base is r QpB q Jo W• pp(x)dx. (6.66) Since VBE is fixed for a given IB, Eq. (6.63) can be rewritten as VA ~Ic ( -IC of -- F oVCE ) - 1 _(2 of OWB OQPB)-I - F aWBOQpBOVCE _(2 of aWB aQpB)-1 - F aWBOQpBOVcB (6.67) Notice that VCB = -VBC' As explained in Section 2.2.2.2 in the derivation ofEq. (2.83) for the depletion-layer capacitance for a p-n junction, when the p-side (base) voltage is changed relative to the n-side (collector) by fj, VBC, the p-side depletion charge changes by an amount equal to the change in the majoritychole charge AQpB in the p-side. Therefore, OQpB = OQpB C o~ o~ ~, (6 .68) where CdBC is the base-collector junction depletion-layer capacitance per unit area [cf. Eq. (2.83)]. The other two derivatives in Eq. (6.67) can be evaluated directly, namely. of --= pp(WB) 2 OWB DnB(WB)nieB(WB) and (6.69) OWB _ (OQPB)-I _ __I OQpB - oWB - qpp(WB)' (6,70) l Therefore, Eq. (6.67) gives VA ~ ~ qDnB( WB)n7eB( WB) . W ' pp(X) d ') X. C4BC 0 DnB(x)nieB(x) (6.71) 342 6 Bipolar Devices For a uniformly doped base, Eq. (6.71) reduces to VA ~ QpB CdBC' (6.72) At sufficiently low collector currents such that the base majority-carrier concentration is approximately the same as its equilibrium value, i.e.,pp ~PpO NB, Eq. (6.71) gives VA ~qDnB(WB)n;cB(WB)lWB ~ CdBC 0 NB(X) d DnB( x)ni2eB ( x) X. (6.73) Equation (6.73) is independent ofbase current, so that the slope ofthe curves in Fig. 6.8 intercept the VCE-axis at the same value, namely VA, as illustrated. It is instructive to estimate the magnitude of Eq. (6.73) for a uniformly doped base. In this case, VA ~ qWsNBICdBe. For a base of WB=O.l ~ and NB= IOIScm- 3, we have qWsNB ~ 1.6 x 1O- 6 C/cm2. For a collector of Ne =2 x 1016 cm-3, then, from Fig. 2.16, CdBC ~ 4 x 10- 8 F/cm2• Therefore, VA::; 40 V. In practice, "A can vary a lot as the transistor design is "optimized." This will be discussed further later in this section and in Chapter 7. As can be seen in Eq. (6.71), VA is a function of WB , which, as discussed earlier, is a function of the collector voltage. Therefore, strictly speaking, the Early voltage is a function of the collector voltage at which the slope is used for extrapolating to Ie =0. In other words, strictly speaking, Ie does not increase lineraly with However, the linear dependence is a good approximation and is a useful approximation for circuit analyses and modeling purposes. The Early voltage is a figure of merit for devices used in analog circuits. The larger the Early voltage, the more independent is the collector current on collector voltage. Another device figure ofmerit is the product ofthe current gain and Early voltage. Using Eqs. (6.33), (6.51), and (6.71), this product can be written as (Prinz and Sturm, 1991) (3o VA q2DnB (WB)n7eB(WB) CdBeJBQ (6.74) where the base saturated current density JBO is a function of the emitter parameters. That is, while VA is a function of the base parameters only, the product /lOVA is a function of both the emitter and the base parameters. • Emitter-collector punch-through. As shown in Eq. (6.72), the Early voltage is propor tional to the majority-carrier charge in the base. As the collector voltage is increased, the width of the quasineutral base region, and hence the majority-carrier charge in the base, is reduced. For a device with a small majority-carrier base charge or small Early voltage to start with, it does not take much increase in collector voltage before all the majority carrier base charge is depleted, or before the collector punches through to the emitter. At collector--emitter punch-through, the collector current becomes excessively large, being limi ted only by the emitter and collector series resistances. The collector current at or close to punch-through is no longer controlled adequately by the base voltage for proper device operation. Punch-through must be avoided under normal device operation, by designing the device to have a sufficiently large majority-carrier base charge. 6.3 CharacteristiCS of a Typical n-p-n Transistor 343 6.3.2.2 Base-Collector Junction Avalanche For a device with a large majority~carrier base charge or large Early voltage to hegin with, as the collector voltage is increased, usually the condition of significant base-collector junction avalanche is reached before punch-through is reached. This is certainly the case for transistors where the collector side of the base-*