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EMCP H9TP64A8JDMCPR-KGM规格书

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    EMCP H9TP64A8JDMCPR-KGM规格书

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    CI-MCP Specification 8GB eNAND (x8) + 8Gb LPDDR2-S4B (x32, 2CS) This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / Nov. 2014 1 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Document Title CI-MCP 8GB eNAND(x8) Flash / 8Gb (x32, 2CS) LPDDR2-S4B Revision History Revision No. History 0.1 - Initial Draft 0.2 - Corrected Ball assignment 0.3 - Editorial Change Final Version 1.0 - Updated eNAND and IDD specification - Changed Refresh Command 1.1 - Updated PRV value Draft Date May. 2014 Jun. 2014 Jul. 2014 Remark Preliminary Preliminary Preliminary Sep. 2014 Nov. 2014 Rev 1.1 / Nov. 2014 2 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) FEATURES [ CI-MCP ] ● Operation Temperature - (-25)oC ~ 85oC ● Package - 162-ball FBGA - 11.5x13.0mm2, 1.0t, 0.5mm pitch - Lead & Halogen Free [ e-NAND ] • eMMC5.0 compatible (Backward compatible to eMMC4.5) • Bus mode - Data bus width : 1 bit(default), 4 bits, 8 bits - Data transfer rate: up to 400MB/s (HS400) - MMC I/F Clock frequency : 0~200MHz - MMC I/F Boot frequency : 0~52MHz • Operating voltage range - Vcc (NAND) : 2.7 - 3.6V - Vccq (Controller) : 1.7 - 1.95V / 2.7 - 3.6V • Temperature - Operation (-25℃ ~ +85℃) - Storage without operation (-40℃ ~ +85℃) • Others - This product is compliance with the RoHS directive • Supported features - HS400, HS200 - HPI, BKOPS - Packed CMD, Cache - Partitioning, RPMB - Discard, Trim, Erase, Sanitize - Write protect, Lock / Unlock - PON, Sleep / Awake - Reliable write - Boot feature, Boot partition - HW / SW Reset - Field firmware update - Configurable driver strength - Health(Smart) report - Production state awareness - Secure removal type [ LPDDR2 S4B ] ● VDD1 = 1.8V (1.7V to 1.95V) ● VDD2, VDDCA and VDDQ = 1.2V (1.14V to 1.30) ● HSUL_12 interface (High Speed Unterminated Logic 1.2V) ● Double data rate architecture for command, address and data Bus; - all control and address except CS_n, CKE latched at both rising and falling edge of the clock - CS_n, CKE latched at rising edge of the clock - two data accesses per clock cycle ● Differential clock inputs (CK_t, CK_c) ● Bi-directional differential data strobe (DQS_t, DQS_c) - Source synchronous data transaction aligned to bi-directional differential data strobe (DQS_t, DQS_c) - Data outputs aligned to the edge of the data strobe (DQS_t, DQS_c) when READ operation - Data inputs aligned to the center of the data strobe (DQS_t, DQS_c) when WRITE operation ● DM masks write data at the both rising and falling edge of the data strobe ● Programmable RL (Read Latency) and WL (Write Latency) ● Programmable burst length: 4, 8 and 16 ● Auto refresh and self refresh supported ● All bank auto refresh and per bank auto refresh supported ● Auto TCSR (Temperature Compensated Self Refresh) ● PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask ● DS (Drive Strength) ● DPD (Deep Power Down) ● ZQ (Calibration) Rev 1.1 / Nov. 2014 3 Functional Block Diagram e-NAND Block Diagram H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) MultiMediaCard Interface MMC Controller Data In/Out Control NAND Flash DRAM Block Diagram e-NAND CA0 ~ CA9 CS0, CKE0 DM0~DM3, DQS0_t~DQS3_t, DQS0_c~DQS3_c, DQ0~DQ31 8Gb x32 device (256M x 32) CK_t, CK_c ZQ VDD1, VDD2, VDDCA, VDDQ, Vref(CA/DQ) VSS, VSSCA, VSSQ Note 1. Total current consumption is dependent to user operating conditions. AC and DC Characteristics shown in this specification are based on a single die. See the section of “DC Parameters and Operating Conditions” Rev 1.1 / Nov. 2014 4 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) ORDERING INFORMATION Part Number Memory Combination Operation Voltage Density Speed Package H9TP64A8JDMCPR-KGM e-NAND 3.3V 8GB (x8) 200MHz 162Ball FBGA mobile DDR2 S4B 1.8V/1.2/1.2/1.2 8Gb (x32) DDR2 1066 (Lead & Halogen Free) H9TP6 4 A 8 JDMCPR-KGM SK Hynix Memory MCP/PoP Product Mode : CI-MCP NAND DDR2 Density, Stack, Block Size & Page Buffer for NVM : 64Gb, SDP, LB, MLC Voltage & I/O for NVM : 3.3V, x8 Density, Stack, CH & CS for DRAM : 8Gb, DDP, 1Ch, 2CS Voltage, I/O & Option for DRAM : 1.2v, x32, LPDDR2-S4 Temperature : Standard (-25~85’C) DRAM Speed : LPDDR2 1066Mbps Ci-NAND Speed : 200Mhz Package Material : Lead & Halogen Free Package Type : FBGA 162 Ball 11.5x13 Generation : 1st Rev 1.1 / Nov. 2014 5 Ball ASSIGNMENT H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 1 2 3 4 5 6 7 8 9 10 A VSF VSF DAT0 DAT6 VDDI DAT5 DAT3 VCC DNU DNU A B DNU VCC DAT1 DAT7 CLKm DAT4 DAT2 VCCQ VSSm DNU B C RST VCCQ VSSQ m DS CMD VSSQ m D NC NC NC NC NC NC C LPDDR2 Commend/Address D LPDDR2 Data IO E VSSm NC NC VDD2 VDD1 DQ31 DQ29 DQ26 DNU E eMMC4.41 F VDD1 VSS NC VSS VSSQ VDDQ DQ25 VSSQ VDDQ F IO/Commend G VSS VDD2 ZQ VDDQ DQ30 DQ27 DQS3 _t DQS3 _c VSSQ G Power H VSSCA CA9 CA8 DQ28 DQ24 DM3 DQ15 VDDQ VSSQ H (VDD1,VDD2, VDDCA,VREF) J VDDCA CA6 CA7 VSSQ DQ11 DQ13 DQ14 DQ12 VDDQ J Ground (VSS,VSSCA,VSSQ) K VDD2 CA5 VREFCA DQS1 _c DQS1 _t DQ10 DQ9 DQ8 VSSQ K L VDDCA VSS CLK_ c DM1 VDDQ L M VSSCA NC CLK_t VSSQ VDDQ VDD2 VSS VREFDQ M N CKE0 CKE1 NC DM0 VDDQ N P CS0_ CS1_ nn NC DQS0 DQS0 _c _t DQ5 DQ6 DQ7 VSSQ P R CA4 CA3 CA2 VSSQ DQ4 DQ2 DQ1 DQ3 VDDQ R T VSSCA VDDCA CA1 DQ19 DQ23 DM2 DQ0 VDDQ VSSQ T U VSS VDD2 CA0 VDDQ DQ17 DQ20 DQS2 _t DQS2 _c VSSQ U V VDD1 VSS NC VSS VSSQ VDDQ DQ22 VSSQ VDDQ V W DNU NC NC VDD2 VDD1 DQ16 DQ18 DQ21 DNU W Y DNU DNU DNU DNU Y 1 2 3 4 5 6 7 8 9 10 Top View 162ball MCP eMMC + x32 LPDDR2 (1CH) Rev 1.1 / Nov. 2014 6 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Pin Description SYMBOL < 8GB (x8, MMC) e-NAND > CLK CMD DAT0~DAT7 VCC VCCQ VSS VDDI < 8Gb (x32, 2CS) LPDDR2-S4B > CS0_n, CS1_n CK_c, CK_t CKE0, CKE1 CA0 ~ CA9 DQ0 ~ DQ31 DM0 ~ DM1 DQS0_t ~ DQS1_t DQS0_c ~ DQS1_c ZQ VDD1 VDD2 VSS VDDQ VDDCA VSSCA VSSQ VREF(CA) / VREF(DQ) DESCRIPTION Clock Command Data Input/Output Core Power Supply I/O Power Supply Ground By pass Chip Select Differential Clocks Clock Enable Command / Address Data I/O Input Data Mask Differential Data Strobe (pos.) Differential Data Strobe (neg.) Drive Strength Calibration Core Power Supply Core Power Supply Ground I/O Power Supply CA Power Supply CA Ground I/O Ground Reference Voltage Type Input Input/Output Input/Output Power Power Ground Power Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Power Power Ground Power Power Ground Ground Power Rev 1.1 / Nov. 2014 7 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) PACKAGE INFORMATION 162 Ball 0.5mm pitch 11.5mm x 13.0mm FBGA [t = 1.0mm max] 3.50 ± 0.10 0.50 x 9 = 4.50 0.50 10 9 8 7 6 5 4 3 2 1 A1 INDEX MARK 0.50 x 19 = 9.50 0.25 13.00 ± 0.10 A B C D E F G H J K L M N P R T U V W Y 0.5 0 1.75 ± 0.10 162 x Ø0.300±0.050 (Post Reflow Ø0.320±0.050) Ø0.15 M C A B 11.50 ± 0.10 Bottom View 0.90±0.10 0.22±0.05 Rev 1.1 / Nov. 2014 Front View SEATING PLANE C 0.08 C 8 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 8GB(x8) e-NAND Flash Rev 1.1 / Nov. 2014 9 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 1. Introduction 1.1 General description SK hynix e-NAND consists of NAND flash and MMC controller. e-NAND has the built-in intelligent controller which manages interface protocols, wear leveling, bad block management, garbage collection, and ECC. e-NAND protects the data contents from the host sudden power off failure. e-NAND is compatible with JEDEC standard eMMC5.0 specification. Rev 1.1 / Nov. 2014 10 2. e-NAND Characteristics 2.1 Performance H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Density 8GB Sequential read (MB/s) 160 Sequential write (MB/s) 20 Test condition • Option: Cache / Packed / HS400 • Test tool: uBOOT (Without O/S) • Chunk size : 1MB, Test area : 1GB 2.2 Power 2.1.1 Active power consumption during operation Density 32GB(QDP) Avg. Peak Max RMS current Icc Iccq 150 200 250 350 • Room temperature : 25℃ • Average current consumption is over a period of 100ms • Peak current consumption is over a period of 20us • Vcc : 3.3V & Vccq : 1.8V • HS400 enabled 2.1.2 Low power mode (Standby) Density 32GB(QDP) Icc 70uA • In Standby Power mode, CTRL Vccq & NAND Vcc power supply is switched on • No data transaction period before entering sleep status • Room temperature : 25℃ 2.1.3 Low power mode (Sleep) Iccq 100uA Density Icc 32GB(QDP) 0 Iccq 100uA • In sleep state, triggered by CMD5, NAND Vcc power supply is switched off (CTRL Vccq on) • Room temperature : 25℃ Rev 1.1 / Nov. 2014 11 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 2.3 Endurance This section provides “TBW(Total Bytes Written)” information that indicates how much data can be written on an eNAND before the device reaches its end of life. The data is based on the SK hynix’s data pattern which is designed to be a good indication of endurance for mainstream application users. Density 8GB TBW 4TB [Table 1]Write endurance Rev 1.1 / Nov. 2014 12 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3. e-NAND New features for eMMC5.0 3.1 HS400 mode e-NAND supports HS400 signaling to achieve a bus speed of 400MB/s via a 200MHz DDR clock frequency. HS400 mode supports only 8-bit bus width and the 1.8V Vccq. Due to the speed, the host may need to have an adjustable sampling point to reliably receive the incoming data (Read Data and CRC Response) with DS pin. e-NAND supports up to 5 Driver Strength. Driver type values 0 Support Mandatory Nominal Impedance 50Ω Approximated driving capability compared to Type_0 x1 Remark Default Driver Type. Supports up to 200MHz operation. 1 33Ω 2 66Ω Optional 3 100Ω 4 40Ω x 1.5 x 0.75 x 0.5 x 1.2 Supports up to 200MHz operation. The weakest driver that supports up to 200MHz operation. For low noise and low EMI systems. Maximal operating frequency is decided by host design. [Table 2]I/O Driver strength types Selecting HS_Timing depends on Host I/F speed, default is 0, but all of value can be selected by host. Value 0x00 0x01 0x02 0x03 Timing Selecting backward compatibility interface timing High speed HS200 HS400 [Table 3]HS_Timing values Supportability for e-NAND Support Support Support Support Rev 1.1 / Nov. 2014 13 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3.1.1 Bus timing specification in HS400 mode ■ HS400 Device input timing The CMD input timing for HS400 mode is the same as CMD input timing for HS200 mode. Parameter Input CLK Cycle time data transfer mode Slew rate Symbol tPERIOD SR Duty cycle distortion tCKDCD Minimum pulse width tCKMPW Input DAT (referenced to CLK) Input set-up time tISUddr Input hold time Slew rate tIHddr SR [Figure 1]HS400 Device input timing Min Max Unit Remark 5 1.125 0.0 0.3 2.2 V/ns ns ns 200MHz(Max), between rising edges with respect to VT With respect to VIH/VIL Allowable deviation from an ideal 50% duty cycle. With respect to VT. Includes jitter, phase noise With respect to VT 0.4 0.4 1.125 ns ns V/ns CDEVICE ≤ 6pF With respect to VIH/VIL CDEVICE ≤ 6pF With respect to VIH/VIL With respect to VIH/VIL [Table 4]HS400 Device input timing Rev 1.1 / Nov. 2014 14 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) ■ HS400 Device output timing Data strobe is for reading data in HS400 mode. Data strobe is toggled only during data read or CRC status response. Parameter Data strobe Cycle time data transfer mode Slew rate Symbol tPERIOD SR Duty cycle distortion tDSDCD Minimum pulse width Read pre-amble tDSMPW tRPRE Read post-amble tRPST Output DAT (referenced to data strobe) Input set-up time tISUddr Output skew Output hold skew Slew rate tRQ tRQH SR [Figure 2]HS400 Device output timing Min Max Unit Remark 5 1.125 0.0 2.0 0.4 0.4 0.2 5 (One Clock Cycle) 2.5 (Half Clock Cycle) V/ns ns ns ns ns 200MHz(Max), between rising edges with respect to VT With respect to VIH/VIL and HS400 reference load Allowable deviation from the input CLK duty cycle distortion(tCKDCD) With respect to VT Includes jitter, phase noise With respect to VT 0.4 0.4 1.125 ns ns ns V/ns CDEVICE ≤ 6pF With respect to VIH/VIL With respect to VOH/VOL and HS400 reference load With respect to VOH/VOL and HS400 reference load With respect to VOH/VOL and HS400 reference load [Table 5]HS400 Device output timing Rev 1.1 / Nov. 2014 15 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Parameter Pull-up resistance for CMD Pull-up resistance for DAT0-7 Pull-down resistance for Data strobe Internal pull up resistance DAT1-DAT7 Bus signal line capacitance Single Device capacitance Symbol RCMD RDAT RDS Rint CL CDevice Min 4.7 10 10 10 Type Max 100 100 100 150 13 6 [Table 6]HS400 Capacitance Unit Kohm Kohm Kohm Kohm pF pF Remark Rev 1.1 / Nov. 2014 16 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3.1.2 HS400 Mode selection Following JEDEC standard for eMMC5.0, changing bus mode directly from HS200 to HS400 is not allowed. It has a rule for changing bus width from SDR mode to DDR mode that HS_TIMING must be set to “0x01”(HS mode : 52MHz) before setting BUS_WIDTH for DDR operation. We recommend the HS400 bus mode selection sequence as following. [Figure 3]HS400 Bus mode selection sequence Rev 1.1 / Nov. 2014 17 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3.2 Field firmware update (FFU) To download a new firmware, the e-NAND requires instruction sequence following JEDEC standard. SK hynix e-NAND only supports Manual mode (MODE_OPERATION_CODES is not supported). For more details, see as the following chart and register table given below. [Figure 4]FFU flow chart ■ SM2716 Field F/W update flow - CMD sequence Operation Set bus width (1bit or 4bit) Set block length 512B Enter FFU mode Send FW to device(Download) CMD12 : Stop CMD6 : Exit FFU mode CMD0/HW Reset/Power cycle Re-Init to trans state CMD CMD16, arg : 0x00000200 CMD6, arg : 0x031E0100 CMD25, arg : 0x00006600 CMD12, arg : 0x00000000 CMD6, arg : 0x031E0000 CMD0, CMD1 ... Check if FFU is succeeded CMD8, arg : 0x00000000 Remark Bus width should be 1bit or 4bit Sending CMD25 is followed by sending FW data Check EXT_CSD[26] : FFU_SUCCESS If FFU_SUCCESS is 0, FFU is succeeded, otherwise FFU is failed. Rev 1.1 / Nov. 2014 18 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) ■ SUPPORTED_MODE[493] (Read Only) BIT[0] : ‘0’ FFU is not supported by the device. ‘1’ FFU is supported by the device. BIT[1] : ‘0’ Vendor specific mode (VSM) is not supported by the device. ‘1’ Vendor specific mode is supported by the device. Bit Bit[7:2] Bit[1] Bit[0] Field Reserved VSM FFU Supportability Not support Support ■ FFU_FEATURE[492] (Read Only) BIT[0] : ‘0’ Device does not support MODE_OPERATION_CODES field (Manual mode) ‘1’ Device supports MODE_OPERATION_CODES field (Auto mode) Bit Bit[7:1] Bit[0] Field Reserved SUPPORTED_MODE_OPERATION_CODES Supportability Not support Rev 1.1 / Nov. 2014 19 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) ■ FFU_ARG[490-487] (Read Only) Using this field the device reports to the host which value the host should set as an argument for read and write commands in FFU mode. ■ FW_CONFIG[169] (R/W) BIT[0] : Update disable 0x0 : FW updates enabled. / 0x1 : FW update disabled permanently Bit Bit[7:1] Bit[0] Field Reserved Update disable Supportability FW updates enabled (0x0) ■ FFU_STATUS[26] (R/W/E_P) Using this field the device reports to the host the state of FFU process. Value 0x13 ~ 0xFF 0x12 0x11 0x10 0x01 ~ 0x0F 0x00 Description Reserved Error in downloading Firmware Firmware install error General error Reserved Success ■ OPERATION_CODES_TIMEOUT[491](Read Only) Maximum timeout for the SWITCH command when setting a value to the MODE_OPERATION_CODES field The register is set to ‘0’, because the e-NAND doesn’t support MODE_OPERATION_CODES. Value 0x01 ~ 0x17 0x18 ~ 0xFF Description MODE_OPERATION_CODES_TIMEOUT = 100us x 2OPERATION_CODES_TIMEOUT Reserved Timeout value 0 (Not defined) - ■ MODE_OPERATION_CODES[29] (W/E_P) The host sets the operation to be performed at the selected mode, in case MODE_CONFIGS is set to FFU_MODE, MODE_OPERATION_CODES could have the following values : Value 0x01 0x02 0x00, others Description FFU_INSTALL FFU_ABORT Reserved Rev 1.1 / Nov. 2014 20 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3.3 Health(Smart) report Using this feature is for monitoring device status and preventing the error and failure in advance. Host can check device information with EXT_CSD as the register table given below. Field VENDOR_PROPRIETARY_HEALTH_REPORT DEVICE_LIFE_TIME_EST_TYPE_ A / B PRE_EOL_INFO OPTIMAL_TRIM/WRITE_READ_SIZE DEVICE_VERSION FIRMWARE_VERSION CSD slice [301:270] [268:269] [267] [264:266] [263:262] [261:254] Description Reserved for vendor proprietary health report. [301:286] Number of factory bad blocks for 4CE (4bytes for each CE) [285:270] Number of runtime bad blocks for 4CE (4bytes for each CE) Current average P/E cycle of memory of Type A(SLC) / Type B(MLC) relative to its maximum estimated capability Consumed reserved blocks to notify before reaching the EOL (End of life) status Minimum optimal (for the device) Erase / Write / Read unit size for the different partitions Device version Device FW version [Table 7]Using EXT_CSD for health report (Read only) ■ VENDOR_PROPRIETARY_HEALTH_REPORT Example Rev 1.1 / Nov. 2014 21 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3.4 Production state awareness This new feature is added for eMMC5.0 JEDEC Spec. to prevent the data break during device soldering. For this feature implementation, e-NAND supports only manual mode and PRODUCT_STATE_AWARENESS_TIMEOUT is 0x17(maximum). For more detail, see as the flow chart and register table given below. [Figure 5]Production State Awareness manual mode flowchart ■ PRODUCTION_STATE_AWARENESS_TIMEOUT[218] (Read Only) This field indicates maximum timeout for the SWITCH command when setting a value to the PRODUCTION_STATE_AWARENESS[133]field Value 0x00 ~ 0x17 0x18 ~ 0xFF Description Production State Timeout = 100us x 2PRODUCTION_STATE_AWARENESS_TIMEOUT Reserved Timeout value 0x17 (838.86s) - Rev 1.1 / Nov. 2014 22 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) ■ PRODUCTION_STATE_AWARENESS[133](R/W/E) e-NAND doesn’t support 0x03 state. Value 0x00 0x01 0x02 0x03 0x04 ~ 0x0F 0x10 ~ 0x1F Device State NORMAL (Field) PRE_SOLDERING_WRITES PRE_SOLDERING_POST_WRITES AUTO_PRE_SOLDERING Reserved Reserved for Vendor Proprietary Usage Description Regular operation Once transferred to this state the host should not write content to the device Not supported - ■ PRODUCTION_STATE_AWARENESS_ENABLEMENT[17] e-NAND only supports manual mode for PRODUCTION_STATE_AWARENESS Enablement(R/W/E) Bit7 Bit6 Bit5 Bit4 Reserved Mode Production State Awareness enable Cleared when PRODUCTION_STATE_AWARENESS is charged to Normal (either automatically or by setting PRODUCTION_STATE_AWARENESS to Normal) Bit3 Capabilities(R) Bit2 Bit1 Reserved Auto mode Supported Bit0 Manual mode Supported This bit could be set to ‘1’ only once Rev 1.1 / Nov. 2014 23 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3.5 Sleep notification Host may use to a power off notification when it intends to turn-off Vcc after moving the device to sleep state. Some features are added to clarify the spec for entering sleep mode when power off notification is enabled. ■ Add the SLEEP_NOTIFICATION on the interruptible Command List CMD CMD6 Description SWITCH, Byte POWER_OFF_NOTIFICATION, Value POWER_OFF_LONG or SLEEP_NOTIFICATION Is interruptible? Yes ■ SLEEP_NOTIFICATION_TIME[216](Read Only) Maximum timeout for the SWITCH command when notifying the device that it is about to move to sleep state by writ- ing SLEEP_NOTIFICATION to POWER_OFF_NOTIFICATION[34]byte. (unit : 10us) Value 0x01 ~ 0x17 0x18 ~ 0xFF Description Sleep Notification Timeout = 10us x 2 SLEEP_NOTIFICATION_TIME Reserved Timeout value 0xC (40.96ms) - ■ POWER_OFF_NOTIFICATION[34] (R/W/E_P) Add Ox04h for the SLEEP_NOTIFICATION as a valid value Value : 0x03 0x04 Field : POWER_OFF_LONG SLEEP_NOTIFICATION Description : Host is going to power off the device. The device shall respond within POWER_OFF_LONG_TIME Host is going to put device in sleep mode. The device shall respond within SLEEP_NOTIFICATION_TIME Rev 1.1 / Nov. 2014 24 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3.6 Secure removal type This feature is used for how information is removed from the physical memory during a purge operation. ■ Secure Removal Type[16] Among four options for secure removal type, e-NAND supports 0x3, 0x1 and 0x0 (0x2 option is not supported) e-NAND recommends using a vendor defined removal type(type 3). If host want to erase the device physically using removal type0. Secure erase & Secure trim time is longer than using removal type0 BIT Description of Secure Removal Type BIT[5:4] Configure Secure Removal Type (R/W) BIT[3:0] Supported Secure Removal Type (R) 0x3 0x2 0x1 0x0 BIT[3] BIT[2] BIT[1] BIT[0] Description Information removed using a vendor defined Information removed by an overwriting the addressed locations with a character, its complement, then a random character Information removed by an overwriting the addressed locations with a character followed by an erase Information removed by an erase of the physical memory Information removed using a vendor defined Information removed by an overwriting the addressed locations with a character, its complement, then a random character Information removed by an overwriting the addressed locations with a character followed by an erase Information removed by an erase of the physical memory Supportability Support - Support Not support Support Support Rev 1.1 / Nov. 2014 25 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3.7 RPMB throughput improvement (For future spec in eMMC) This feature is proposed for RPMB write data size to improve the RPMB throughput at eMMC5.x spec. The supported maximum data size of RPMB write access is 8KB (32ea). At this moment for e-NAND device, supported Max.data size is up to 64ea(16KB). More information is shown as the following tables. ■ RPMB Throughput SK hynix e-NAND provides up to 64ea for RPMB write data size. eMMC5.x Spec. SK hynix e-NAND Max. data size 32ea (<=8KB) Available Max. data size is 64ea (<=16KB) Present setting RPMB write data size is 8KB Using for improve RPMB Throughput Setting the EN_RPMB_REL_WR (Bit[4] of EXT_CSD)[166] ) Value REL_WR_SEC_C[222] value is set to ‘10’ (512B chunk based, 8KB) ■ RPMB Performance with e-NAND Following table shows the RPMB performance with 8KB chunk data on the e-NAND device. RPMB Performance Sequential Write (Unite : MB/s) Sequential Read (Unite : MB/s) 512B Data transfer unit 0.6 4 1KB Data transfer unit 1 7 2KB Data transfer unit 2 11 4KB Data transfer unit 3 15 8KB Data transfer unit 5 20 Rev 1.1 / Nov. 2014 26 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 3.8 Enhanced features from eMMC4.5 Several e-NAND features are changed from eMMC4.5 to enhance the e-NAND performance. Parameter HPI Features Max. Packed CMD size (Read/Write) Cache size I/O Driver strength eMMC4.5 CMD12 8ea 64KB Support Type0 eMMC5.0 CMD13 63ea 128KB Support all type Description Following industry wise common configuration. Expended the packed CMD size for optimized device performance. Cache size is up to 128KB for optimized device performance with 4-way interleave implementation. e-NAND supports all of driver strength types for eMMC5.0 [Table 8]Enhanced features from eMMC4.5 Rev 1.1 / Nov. 2014 27 4. e-NAND general parameters 4.1 Timing 4.1.1 Bus timing H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Data must always be sampled on the rising edge of the clock. [Figure 6]Timing diagram: data input/output Rev 1.1 / Nov. 2014 28 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Clock CLK(1) Parameter Clock frequency data transfer mode (PP)(2) Clock frequency identification mode (OD) Clock high time Clock low time Clock rise time(4) Clock fall time Inputs CMD, DAT (referenced to CLK) Input set-up time Input hold time Outputs CMD, DAT (referenced to CLK) Output delay time during data transfer Output hold time Signal rise time(5) Signal fall time Symbol fPP fOD tWH tWL tTLH tTHL tISU tIH tODLY tOH tRISE tFALL Min 0 0 6.5 6.5 3 3 2.5 Max 52(3) 400 3 3 13.7 3 3 Unit Remark MHz CL ≤30 pF Tolerance: +100KHz kHz Tolerance: +20KHz ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF [Table 9] High-speed e-NAND interface timing • CLK timing is measured at 50% of VDD. • e-NAND shall support the full frequency range from 0-26Mhz, or 0-52MHz • CLK rising and falling times are measured by min (VIH) and max (VIL). • Input CMD, DAT rising and falling times are measured by min (VIH) and max (VIL), and output CMD, DAT rising and falingl times are measured by min (VOH) and max (VOL). Rev 1.1 / Nov. 2014 29 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Parameter Clock CLK(2) Clock frequency Data Transfer Mode (PP)(3) Clock frequency Identification Mode (OD) Clock high time Clock low time Clock rise time(4) Clock fall time Inputs CMD, DAT (referenced to CLK) Input set-up time Input hold time Outputs CMD, DAT (referenced to CLK) Output set-up time(5) Output hold time(5) Symbol fPP fOD tWH tWL tTLH tTHL tISU tIH tOSU tOH Min 0 0 10 10 3 3 11.7 8.3 Max 26 400 10 10 Unit Remark(1) MHz CL ≤ 30 pF kHz ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF ns CL ≤ 30 pF [Table 10]Backward-compatible e-NAND interface timing • e-NAND must always start with the backward-compatible interface timing. The timing mode can be switched to high-speed timing by the host sending the switch command (CMD6) with the argument for high speed interface select. • CLK timing is measured at 50% of VDD. • CLK rising and falling times are measured by min (VIH) and max (VIL). • tOSU and tOH are defined as values from clock rising edge. However, there may be cards or devices which utilize clock falling edge to output data in backward compatibility mode. Therefore, it is recommended for hosts either to set tWL value as long as possible within the range which should not go over tCK-tOH(min) in the system or to use slow clock frequency, so that host could have data set up margin for those devices. In this case, each device which utilizes clock falling edge might show the correlation either between tWL and tOSU or between tCK and tOSU for the device. Rev 1.1 / Nov. 2014 30 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 4.1.2 Bus Timing for DAT Signals During 2x Data Rate Operation These timings apply to the DAT[7:0] signals only when the device is configured for dual data mode operation. In dual data mode, the DAT signals operate synchronously of both the rising and the falling edges of CLK. [Figure 7]Timing diagram: data input/output in dual data rate mode Rev 1.1 / Nov. 2014 31 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Parameter Input CLK(1) Clock duty cycle Clock rise time Clock fail time Input CMD (referenced to CLK-SDR mode) Input set-up time Input hold time Output CMD (referenced to CLK-SDR mode) Output delay time during data transfer Output hold time Signal rise time Signal fall time Input DAT (referenced to CLK-DDR mode) Input set-up time Input hold time Outputs DAT (referenced to CLK-DDR mode) Output delay time during data transfer Signal rise time(DAT0-7)(2) Signal fall time (DAT0-7) Symbol Min. Max. 45 55 tTLH 3 tTHL 3 tISUddr 3 tIHDDR 3 tODLY tOH tRISE tFALL 13.7 2.5 3 3 tISUddr 2.5 tIHddr 2.5 tODLYddr 1.5 7 tRISE 2 tFALL 2 Unit Remark % Includes jitter, phase noise ns CL≤30 pF ns CL≤30 pF ns CL≤20 pF ns CL≤20 pF ns CL≤20 pF ns CL≤20 pF ns CL≤20 pF ns CL≤20 pF ns CL≤20 pF ns CL≤20 pF ns CL≤20 pF ns CL≤20 pF ns CL≤20 pF [Table 11]Dual data rate interface timings • NOTE 1. CLK timing is measured at 50% of VDD. • NOTE 2. Inputs DAT rising and falling times are measured by min (VIH) and max (VIL), and outputs CMD, DAT rising and falling times are measured by min (VOH) and max (VOL) Rev 1.1 / Nov. 2014 32 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 4.2 Power mode 4.2.1 e-NAND power-up guidelines e-NAND power-up must adhere to the following guidelines: • When power-up is initiated, either Vcc or Vccq can be ramped up first, or both can be ramped up simultaneously. • After power up, e-NAND enters the pre-idle state. The power up time of each supply voltage should be less than the specified tPRU (tPRUH, tPRUL or tPRUV) for the appropriate voltage range. • If e-NAND does not support boot mode or its BOOT_PARTITION_ENABLE bit is cleared, e-NAND moves immediately to the idle state. While in the idle state, e-NAND ignores all bus transactions until receiving CMD1. e-NAND begins boot operation with the argument of 0xFFFFFFFA. If boot acknowledge is finished, e-NAND shall send acknowledge pattern “010” to the host within the specified time. After boot operation is terminated, e-NAND enters the idle state and shall be ready for CMD1 operation. If e-NAND receives CMD1 in the pre-boot state, it begins to respond to the command and moves to the card identification mode. • When e-NAND is initiated by alternative boot command(CMD0 with arg=0xFFFFFFFA), all the data will be read from the boot partition and then e-NAND automatically goes to idle state, but hosts are still required to issue CMD0 with arg=0x0000000000 in order to complete a boot mode properly and move to the idle state. While in the idle state, eNAND ignores all bus transactions until it receives CMD1. • CMD1 is a special synchronization command which is used to negotiate the operating voltage range and poll the device until it is out of its power-up sequence. In addition to the operating voltage profile of the device, the response to CMD1 contains a busy flag indicating that the device is still working on its power-up procedure and is not ready for identification. This bit informs the host that the device is not ready, and the host must wait until this bit is cleared. The device must complete its initialization within 1 second of the first CMD1 issued with a valid OCR range. • If the e-NAND device was successfully partitioned during the previous power up session (bit 0 of EXT_CSD byte [155] PARTITION_SETTING_COMPLETE successfully set) then the initialization delay is (instead of 1s) calculated from INI_TIMEOUT_PA (EXT_CSD byte [241]). This timeout applies only for the very first initialization after successful partitioning. For all the consecutive initialization 1sec time out will be applied. • The bus master moves the device out of the idle state. Because the power-up time and the supply ramp-up time depend on the application parameters such as the bus length and the power supply unit, the host must ensure that power is built up to the operating level (the same level that will be specified in CMD1) before CMD1 is transmitted. • After power-up, the host starts the clock and sends the initializing sequence on the CMD line. The sequence length is the longest of: 1ms, 74 clocks, the supply ramp-up time, or the boot operation period. An additional 10 clocks (beyond the 64 clocks of the power-up sequence) are provided to eliminate power-up synchronization problems. • Every bus master must implement CMD1. Rev 1.1 / Nov. 2014 33 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 4.2.2 e-NAND Power Cycling The master can execute any sequence of Vcc and Vccq power-up/power-down. However, the master must not issue any commands until Vcc and Vccq are stable within each operating voltage range. After the slave enters sleep mode, the master can power-down Vcc to reduce power consumption. It is necessary for the slave to be ramped up to Vcc before the host issues CMD5 (SLEEP_AWAKE) to wake the slave unit. [Figure 8]e-NAND power cycle If Vcc or Vccq is below 0.5 V for longer than 1 ms, the slave shall always return to the pre-idle state, and perform the appropriate boot behavior. The slave will behave as in a standard power up condition once the voltages have returned to their functional ranges. An exception to this behavior is if the device is in sleep state, in which the voltage on Vcc is not monitored. Rev 1.1 / Nov. 2014 34 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 4.2.3 Leakage Parameter BGA All inputs Input leakage current (before initialization sequenceand/or the internalpull up resistors connected) Input leakage current (after initialization sequence and the internal pull up resistors disconnected) All outputs Output leakage current (before initialization sequence) Output leakage current (after initialization sequence) Symbol Min -0.5 -100 -2 -100 -2 Max. Vccq+0.5 Unit V Remark 100 A 2 A 100 A 2 A 4.2.4 Power Supply [Table 12]General operation conditions In e-NAND, Vcc is used for the NAND core voltage and NAND interface; Vccq is for the controller core and e-NAND interface voltage shown in Figure 9. The core regulator is optional and only required when internal core logic voltage is regulated from Vccq. A Creg capacitor must be connected to the VDDi terminal to stabilize regulator output on the system. [Figure 9]e-NAND internal power diagram Rev 1.1 / Nov. 2014 35 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) e-NAND supports one or more combinations of Vcc and Vccq as shown in Table 15. The available voltage configuration is shown in Table 16. Parameter Supply voltage (NAND) Supply voltage (I/O) Supply power-up for 3.3V Supply power-up for 1.8V Symbol Vcc Vccq tPRUH tPRUL Min 2.7 1.7 2.7 1.7 Max. 3.6 1.95 3.6 1.95 35 25 [Table 13]e-NAND power supply voltage Unit V V V V ms ms Remark Not supported Vccq 1.7V ~ 1.95V 2.7V ~ 3.6V 2.7V–3.6V Valid Vcc 1.7V–1.95V Not Valid Valid Not Valid [Table 14]e-NAND voltage combinations Rev 1.1 / Nov. 2014 36 4.3 Connection Guide H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) R-DAT7 R-DAT6 R-DAT5 R-DAT4 R-DAT3 R-DAT2 R-DAT1 R-DAT0 R-RSTn R-CMD H_VCCQ H_VCC HOST VCCQ VCC VDDi C1 C2 C3 C4 C5 C6 eMMC H_CLK H_CMD H_RSTn H_DS H_DATO H_DAT1 H_DAT2 H_DAT3 H_DAT4 H_DAT5 H_DAT6 H_DAT7 Parameter Pull-up resistance for CMD Pull-up resistance for DAT0~7 Data strobe(DS) Pull-up resistance for RSTn Serial resistance on CLK Vccq capacitor value Vcc capacitor value(≤8GB) VCC capacitor value(>8GB) VDDi capacitor value R-CLK CLK CMD RSTn DS DATO DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 [Figure 10]Connection guide drawing Symbol R_CMD R_DAT R_DS R_RSTn R_CLK C1 & C2 C3 & C4 C5 & C6 Min 4.7 10 NC 10 0 2±0.22 4.72±10% 0 Max 100 100 NC 100 30 4.7 10 2.2 Recommend 10 50 NC 50 27 2.2±0.22 4.7±10% 0.1 Unit kohm kohm kohm ohm uF uF uF Remark Pull-up resistance should be put on CMD line to prevent bus floating. Pull-up resistance should be put on DAT line to prevent bus floating. It is not necessary to put pull-up/pull-down resistance on DS line since DS is internally pulled down. Direct connection to host is required and please float this pin if it is not used It is not necessary to put pull-up resistance on RSTn line if host does not use H/W reset. (Extended CSD register [162] = 0b) To reduce overshooting/undershooting Note: If the host uses HS200, we recommend to remove this resister for better CLK signal Coupling cap should be connected with Vccq and Vssqm as closely possible. Coupling cap should be connected with Vcc and Vssm as closely possible. Vcc /Vccq cap. value would be up to Host requirement and the application system characteristics. Coupling cap should be connected with VDDi and Vssq as closely possible. (Internal Cap : 1uF) [Table 15]Connection guide specification Rev 1.1 / Nov. 2014 37 5. e-NAND basic operations 5.1 Partitioning 5.1.1 User density H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) ■ Boot partition size [Figure 11]Partition diagram Density 8GB Boot Partition 1,2 4096KB Rev 1.1 / Nov. 2014 38 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) ■ User density size Capacity 8GB LBA(Hex) 0xE90000 LBA(Dec) 15,269,888 Capacity(Bytes) 7,818,182,656 • 1sector=512 bytes. • The total usable capacity of the e-NAND may be less than total physical capacity because a small portion of the capacity is used for NAND flash management and maintenance purpose. ■ Maximum enhanced partition size Enhanced user data area can be configured to store read-centric data such as sensitive data or for other host usage models. SK hynix e-NAND supports Enhanced User Data Area as SLC Mode. When customer adopts some portion as enhanced user data area in User Data Area, that area occupies double the size of the original set-up size. Enhanced User Data Area of e-NAND guarantees 20K program and erase cycles Capacity 8GB Max ENH_SIZE_MULTI 1D2h HC_ERASE_GRP_SIZE 1h HC_WP_GRP_SIZE 10h • 1sector = 512 bytes. Max Enhanced Partition Size is defined as MAX_ENH_SIZE_MULT x HC_WP_GRP_SIZE x HC_ERASE_GRP_SIZE x 512Byte. (refer to Table 21. Extended CSD) Capacity 8GB LBA(Hex) 1D20h LBA(Dec) 7,456 Capacity(Bytes) 3,817,472 Rev 1.1 / Nov. 2014 39 5.1.2 Erase / Write protect group size H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Density 8GB Erase group size ERASE_GROUP_DEF=0 ERASE_GROUP_DEF=1 512KB 512KB [Table 16]Erase / Write protect Group size Write protect group size 8MB Rev 1.1 / Nov. 2014 40 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 5.2 Boot operation e-NAND supports boot mode and alternative boot mode. e-NAND also, supports high speed timing and dual data rate during boot. CLK CMD AT[0] CMD 1 RESP CMD 2 RESP S 010 E (1) (2) S 512 bytes + CRC E Boot terminated (4) (3) (4) Min 8 clocks + 48 clocks = 56 clocks required from CMD signal high to next MMC Command. (1) Boot ACK Time (2) Boot Data Time (3) Initialization Time [Figure 12]e-NAND state diagram (Boot mode) CLK CMD CMD 0 CMD 0 Reset CMD 1 DAT[0] Min 74 clocks required after pow er is stable to start boot com m and S 010 E (1) (2) S 512 bytes + CRC E Boot term inated * (1) Boot ACK Tim e (2) Boot Data Tim e (3) CMD 1 Tim e * CMD0 w ith argum ent 0xFFFFFFFA [Figure 13]e-NAND state diagram (Alternative boot mode) Timing Factor (1) Boot ACK Time (2) Boot Data Time (3) Initialization Time Value < 50 ms < 1 sec < 1 sec RESP CMD 2 (3) • Initialization time includes partition setting, Please refer to INI_TIMEOUT_AP in 7.4 Extended CSD Register. Initialization time is completed within 1sec from issuing CMD1 until receiving response. • The device has to send the acknowledge pattern “010” to the master within 50ms after the CMD0 with the argument of 0xFFFFFFFA is received. Rev 1.1 / Nov. 2014 41 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 6. Time out Timing parameter Read timeout Write timeout (CMD to write Done) Erase timeout Force erase timeout Discard timeout Trim timeout Secure trim Sanitize Secure erase Initialization timeout 1st Initialization timeout after partitioning PON busy Time (Short / Long) Initialization after PON (Short / Long) BKOP exit Time Auto-BKOP exit Time HPI CMD5 sleep In Value 100ms Max 500ms Max 600 ms Max 3 min Max 600ms Max 600ms Max 6s 8GB : 8min Max 6s Max 1s Max 1s Max 50ms / 1000ms Max 180ms Max 100ms Max 100ms Max 100ms 3ms Remark Erase group size : 512KB Unmapping only SKhynix recommends to erase all blocks before sanitize operation to shorten the sanitize time Unmapping only CMD to Response BOOT1/2, RPMB, UDA & EUDA PON long busy time includes garbage collection time. BKOP off time after HPI BKOP off time after any CMD from host Response after HPI [Table 17]Time out value • eMMC I/F : HS400 • Pre-conditioning states - Clean state / Test Range : Random write - 1GB, Random read - 1GB • Sequential read / write chunk size : 1MB • Current numbers are based on aligned 4KB • Maximum 4-way interleaving Rev 1.1 / Nov. 2014 42 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 7. Device registers There are six different registers within the device interface: •Operation conditions register (OCR) •Card identification register (CID) •Card specific data register (CSD) •Relative card address register (RCA) •DSR (Driver Stage Register) •Extended card specific data register (EXT_CSD). These registers are used for the serial data communication and can be accessed only using the corresponding commands. e-NAND has a status register to provide information about the current device state and completion codes for the last host command. 7.1 Operation conditions register (OCR) The 32-bit operation conditions register (OCR) stores the VDD voltage profile of e-NAND and the access mode indication. In addition, this register includes a status information bit. This status bit is set if e-NAND power up procedure has been finished. OCR bit [6:0] [7] [14:8] [23:15] [28:24] [30:29] [31] Description Reserved 1.70 - 1.95V 2.0 - 2.6 2.7 - 3.6 (High Vccq range) Reserved Access mode (card power up status bit (busy))(1) SK hynix e-NAND 000 0000b 1b 000 0000b 1111 1111 1b 000 000b 10b (sector mode) [Table 18]OCR register definition 1) This bit is set to LOW if the card has not finished the power up routine Rev 1.1 / Nov. 2014 43 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 7.2 Card identification (CID) register The card identification (CID) register is 128 bits wide. It contains e-NAND identification information used during eNAND identification phase (e-NAND protocol). Every individual e-NAND has a unique identification number. The structure of the CID register is defined in the following sections. Name Manufacturer ID Reserved Card/BGA OEM/application ID Product name Product revision Product serial number Manufacturing date CRC7 checksum Not used, always '1' Field MID CBX OID PNM PRV PSN MDT CRC Reserved Width 8 6 2 8 48 8 32 8 7 1 CID slice [127:120] [119:114] [113:112] [111:104] [103:56] [55:48] [47:16] [15:8] [7:1] [0:0] CID value 90h 1h 4Ah 8GB: 483847316505 7h 1 [Table 19]Card identification (CID) fields Remark BGA Not Fixed Not Fixed Not Fixed 7.3 Card specific data register (CSD) The card specific data (CSD) register provides information on how to access e-NAND contents. The CSD defines the data format, error correction type, maximum data access time, data transfer speed and so on. The programmable part of the register (entries marked by W or E, see below) can be changed by CMD27. The type of the CSD Registry entries in the Table 20 below is coded as follows: • R: Read only. • W: One time programmable and not readable. • R/W: One time programmable and readable. • W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and not readable. • R/W/E: Multiple writable with value kept after power failure, H/W reset assertion and any CMD0 reset and readable. • R/W/C_P: Writable after value cleared by power failure and HW/rest assertion (the value not cleared by CMD0 reset) and readable. • R/W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset and readable. • W/E_P: Multiple writable with value reset after power failure, H/W reset assertion and any CMD0 reset and not readable. Rev 1.1 / Nov. 2014 44 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Name CSD structure System specification version Reserved Data read access-time 1 Data read access-time 2 in CLK cycles (NSAC*100) Max. bus clock frequency Card command classes Max. read data block length Partial blocks for read allowed Write block misalignment Read block misalignment DSR implemented Reserved Device size Max. read current @ VDD min Max. read current @ VDD max Max. write current @ VDD min Max. write current @ VDD max Device size multiplier Erase group size Erase group size multiplier Write protect group size Write protect group enable Manufacturer default ECC Write speed factor Field CSD_STRUCTURE SPEC_VERS TAAC NSAC TRAN_SPEED CCC READ_BL_LEN READ_BL_PARTIAL WRITE_BLK_MISALIGN READ_BLK_MISALIGN DSR_IMP C_SIZE VDD_R_CURR_MIN VDD_R_CURR_MAX VDD_W_CURR_MIN VDD_W_CURR_MAX C_SIZE_MULT ERASE_GRP_SIZE ERASE_GRP_MULT WP_GRP_SIZE WP_GRP_ENABLE DEFAULT_ECC R2W_FACTOR Width 2 4 2 8 8 Cell type R R R R R CSD slice [127:126] [125:122] [121:120] [119:112] [111:104] CSD value 3h 4h Remark 27h 1h 8 R [103:96] 32h 12 R [95:84] F5h 4 R [83:80] 9h 1 R [79:79] 0h 1 R [78:78] 0h 1 R [77:77] 0h 1 R [76:76] 0h 2 R [75:74] 12 R [73:62] FFFh 3 R [61:59] 7h 3 R [58:56] 7h 3 R [55:53] 7h 3 R [52:50] 7h 3 R [49:47] 7h 5 R [46:42] 1Fh 5 R [41:37] 1Fh 5 R [36:32] Fh 1 R [31:31] 1h 2 R [30:29] 0h 3 R [28:26] 2h [Table 20]CSD fields Rev 1.1 / Nov. 2014 45 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Name Max. write data block length Partial blocks for write allowed Reserved Content protection application File format group Copy flag (OTP) Permanent write protection Temporary write protection File format ECC code CRC Not used, always ‘1’ Field WRITE_BL_LEN WRITE_BL_PARTIAL CONTENT_PROT_APP FILE_FORMAT_GRP COPY PERM_WRITE_PROTECT TMP_WRITE_PROTECT FILE_FORMAT ECC CRC Width 4 1 4 1 1 1 1 1 2 2 7 1 Cell type R R R R R/W R/W R/W R/W/E R/W R/W/E R/W/E CSD slice [25:22] [21:21] [20:17] [16:16] [15:15] [14:14] [13:13] [12:12] [11:10] [9:8] [7:1] [0:0] CSD value 9h 0h 0h 0h 1h 0h 0h 0h 0h 1 Remark Not fixed [Table 20]CSD fields (continued) The following sections describe the CSD fields and the relevant data types. If not explicitly defined otherwise, all bit strings are interpreted as binary coded numbers starting with the left bit first. Rev 1.1 / Nov. 2014 46 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 7.4 Extended CSD register The Extended CSD register defines e-NAND properties and selected modes. It is 512 bytes long. The most significant 320 bytes are the Properties segment, which defines e-NAND capabilities and cannot be modified by the host. The lower 192 bytes are the modes segment, which defines the configuration e-NAND is working in. These modes can be changed by the host by means of the switch command. Name Field CSD slice Properties segment Reserved Extended Security Commands Error Supported command sets HPI features Background operations support Max packed read commands Max packed write commands Data Tag Support Tag Unit Size Tag Resources Size Context management capabilities Large Unit size Extended partitions attribute support Supported modes FFU features Operation codes timeout FFU Argument Reserved Number of FW sectors correctly programmed Vendor proprietary health report Device life time estimation type B Device life time estimation type A Pre EOL information Optimal read size Optimal write size Optimal trim unit size Device version Firmware version Power class for 200MHz, DDR at Vcc=3.6V EXT_SECURITY_ERR S_CMD_SET HPI_FEATURES BKOPS_SUPPORT MAX_PACKED_READS MAX_PACKED_WRITES DATA_TAG_SUPPORT TAG_UNIT_SIZE TAG_RES_SIZE CONTEXT_CAPABILITIES LARGE_UNIT_SIZE_M1 EXT_SUPPORT SUPPORTED_MODES FFU_FEATURES OPERATION_CODE_TIME OUT FFU_ARG NUMBER_OF_FW_SECTORS_CORRECTL Y_PROGRAMMED VENDOR_PROPRIETARY_HEALTH_REP ORT DEVICE_LIFE_TIME_EST_TYP_B DEVICE_LIFE_TIME_EST_TYP_A PRE_EOL_INFO OPTIMAL_READ_SIZE OPTIMAL_WRITE_SIZE OPTIMAL_TRIM_UNIT_SIZE DEVICE_VERSION FIRMWARE_VERSION PWR_CL_DDR_200_360 [511:506] [505] [504] [503] [502] [501] [500] [499] [498] [497] [496] [495] [494] [493] [492] [491] [490:487] [486:306] [305:302] [301:270] [269] [268] [267] [266] [265] [264] [263:262] [261:254] [253] Cell Type R R R R R R R R R R R R R R R R R R R R R R R R R R R EXT_CSD value Remark 0h 1h 1h 1h 3Fh 3Fh 1h 0h 0h 78h 1h 3h 1h 0h 17h 6600h Allocated by MMCA 0 Refer to section 4.3 1h 1h 1h 40h 40h 07h 38 05h 0h 0h [Table 21]Extended CSD Rev 1.1 / Nov. 2014 47 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Name Field Cache size Generic CMD6 timeout Power off notification(long)timeout Background operations status Number of correctly programmed sectors 1st initialization time after partitioning Reserved Power class for 52MHz, DDR at Vcc=3.6V Power class for 52MHz, DDR at Vcc=1.95V Power class for 200MHz at Vccq=1.95, Vcc=3.6V Power class for 200MHz at Vccq=1.3, Vcc=3.6V Minimum write performance for 8bit at 52MHz in DDR mode Minimum read performance for 8bit at 52MHz in DDR mode Reserved TRIM multiplier Secure feature support Secure erase multiplier Secure TRIM multiplier Boot information Reserved Boot partition size Access size High-capacity erase unit size High_capacity erase timeout CACHE_SIZE GENERIC_CMD6_TIME POWER_OFF_LONG_TIME BKOPS_STATUS CORRECTLY_PRG_ SECTORS_NUM INI_TIMEOUT_AP PWR_CL_DDR_ 52_360 PWR_CL_DDR_ 52_195 PWR_CL_200_195 PWR_CL_200_130 MIN_PERF_DDR_W_8_52 MIN_PERF_DDR_ R_8_52 TRIM_MULT SEC_FEATURE_ SUPPORT SEC_ERASE_MULT SEC_TRIM_MULT BOOT_INFO BOOT_SIZE_ MULTI ACC_SIZE HC_ERASE_GRP_SIZE ERASE_TIMEOUT_MULT CSD slice [252:249] [248] [247] [246] [245:242] [241] [240] [239] [238] [237] Cell Type R R R R R R R R R [236] R [235] R [234] R [233] [232] R [231] R [230] R [229] R [228] R [227] [226] R [225] R [224] R [223] R Reliable write sector count REL_WR_SEC_C [222] R High-capacity write protect group size HC_WP_GRP_SIZE [221] R [Table 21]Extended CSD EXT_CSD value 400h 5h 64h 0h 0h Ah Remark 0h 0h 0h 0h 0h 0h 2h 55h Ah Ah 7h 20h 6h 1h 2h 10h 8GB:10h TRIM Timeout=300ms*2=600ms Boot partition size = 128Kbytes * BOOT_SIZE_MULTI Erase Unit Size=512KB*1=512KB Erase Timeout=300ms*2=600ms 1 sector supported for reliable write feature 8 high-capacity erase unit size Rev 1.1 / Nov. 2014 48 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Name Field CSD slice Sleep current(Vcc) Sleep current(Vccq) Production state awareness timeout Sleep/awake timeout Sleep Notification Timeout Sector count Reserved Minimum write performance for 8bit at52MHz Minimum read performance for 8bit at 52MHz Minimum write performance for 8bit at 26MHz, for 4bit at 52MHz Minimum read performance for 8bit at 26MHz, for 4bit at 52MHz Minimum write performance for 4bit at 26MHz Minimum read performance for 4bit at 26MHz Reserved Power class for 26MHz at 3.6V Power class for 52MHz at 3.6V Power class for 26MHz at 1.95V Power class for 52MHz at 1.95V S_C_Vcc S_C_Vccq PRODUCTION_STATE_AWARENES S_TIMEOUT S_A_TIMEOUT SLEEP_NOTIFICATION_TIME SEC_COUNT MIN_PERF_W_8_52 MIN_PERF_R_8_52 MIN_PERF_W_8_26_4_52 MIN_PERF_R_8_26_4_52 MIN_PERF_W_4_26 MIN_PERF_R_4_26 PWR_CL_26_360 PWR_CL_52_360 PWR_CL_26_195 PWR_CL_52_195 [220] [219] [218] [217] [216] [215:212] [211] [210] [209] [208] [207] [206] [205] [204] [203] [202] [201] [200] Partition switching timing PARTITION_ SWITCH_TIME [199] Cell Type R R R R R R R R R R R R R R R R R Out-of-interrupt busy timing I/O Driver Strength Device type Reserved CSD structure Reserved Extended CSD revision Modes Segment Command set Reserved OUT_OF_INTERRUPT_TIME DRIVER_STRENGTH DEVICE_TYPE CSD_STRUCTURE EXT_CSD_REV [198] R [197] R [196] R [195] [194] R [193] [192] R CMD_SET [191] R/W/E_P [190] [Table 21]Extended CSD Rev 1.1 / Nov. 2014 EXT_CSD value 7h 7h 17h 11h 0Ch 8GB:E90000h 0h 0h Remark Reserved 0h 0h 0h 0h 0h 0h 0h 0h 1h Maximum partition switch timeout = 10ms*1=10ms Ah Maximum out-of-interrupt timeout = 10ms*10=100ms 1Fh 57h 2h 7h 0h Currently active command set. It can be 1 by host. 49 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Name Field CSD slice Cell Type Command set revision CMD_SET_REV [189] R Reserved Power class Reserved High-speed interface timing Reserved Bus width mode Reserved Erased memory content Reserved Partition configuration POWER_CLASS HS_TIMING BUS_WIDTH ERASED_MEM_CONT PARTITION_CONFIG Boot config protection BOOT_CONFIG_PROT Boot bus conditions Reserved High-density erase group definition Boot area write protection register Reserved BOOT_BUS_CONDITIONS ERASE_GROUP_DEF BOOT_WP User area write protection register USER_WP Reserved FW configuration RPMB Size Write reliability setting register Write reliability parameter register Sanitize start Manually start background operations Enable background operations handshake H/W reset function HPI management Partitioning support Max enhanced area size FW_CONFIG RPMB_SIZE_MULT WR_REL_SET WR_REL_PARAM SANITIZE_START BKOPS_START BKOPS_EN RST_n_FUNCTION HPI_MGMT PARTITIONING_ SUPPORT MAX_ENH_SIZE_ MULT [188] [187] [186] [185] [184] [183] [182] [181] [180] [179] [178] [177] [176] [175] [173] [172] [171] [170] [169] [168] [167] [166] [165] [164] R/W/E_P R/W/E_P W/E_P R R/W/E & R/ W/E_P R/W & R/W/ C_P R/W/E TBD R/W/E_P R/W & R/W/C_P TBD R/W,R/W/ C_P & R/W/ E_P TBD R/W R R/W R W/E_P W/E_P [163] [162] [161] [160] R/W R/W R/W/E_P R [159:157] R [Table 21]Extended CSD EXT_CSD value 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 20h 1Fh 5h 0h 0h 0h 0h 0h 7h 8GB:1D2h Remark See EXT_CSD in spec. It does not have a fixed rule. See EXT_CSD in spec. Rev 1.1 / Nov. 2014 50 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Name Field CSD slice Partitions attribute Partitioning setting General purpose partition size Enhanced user data area size Enhanced user data start address Reserved Bad Block management mode Production state awareness Package Case Temperature is controlled Periodic Wake-up Program CID/CSD in DDR mode support Reserved PARTITIONS_ATTRIBUTE PARTITION_SETTING_COMPLETE D GP_SIZE_MULT ENH_SIZE_MULT ENH_START_ADDR SEC_BAD_BLK_ MGMNT PRODUCTION_STATE_AWARENES S TCASE_SUPPORT PERIODIC_WAKEUP PROGRAM_CID_CSD_DDR_SUPP ORT [156] [155] [154:143] [142:140] [139:136] [135] [134] [133] [132] [131] [130] [129:128] Vendor Specific Fields VENDOR_SPECIFIC_FIELD [127:64] Native sector size Sector size emulation Sector size 1st initialization after disabling sector size emulation Class 6 commands control Number of addressed group to be Released Exception events control Exception events status Extended Partitions Attribute Context configuration Packed command status Packed command failure index Power Off Notification Control to turn the Cache ON/ OFF Flushing of the cache NATIVE_SECTOR_SIZE USE_NATIVE_SECTOR DATA_SECTOR_SIZE INI_TIMEOUT_EMU Class6_CTRL DYNCAP_NEEDED EXCEPTION_EVENTS_CTRL EXCEPTION_EVENTS_STATUS EXT_PARTITIONS_ATTRIBUTE CONTEXT_CONF PACKED_COMMAND_STATUS PACKED_FAILURE_INDEX POWER_OFF_NOTIFICATION CACHE_CTRL FLUSH_CACHE [63] [62] [61] [60] [59] [58] [57:56] [55:54] [53:52] [51:37] [36] [35] [34] [33] [32] Cell Type R/W R/W R/W R/W R/W R/W R/W/E W/E_P R/W/E R Vendor Specific R R/W R R R/W/E_P R R/W/E_P R R/W R/W/E_P R R R/W/E_P R/W/E_P W/E_P [Table 21]Extended CSD EXT_CSD value 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 1h 0h 0h Ah 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h Remark Rev 1.1 / Nov. 2014 51 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Name Reserved Mode config Mode operation codes Reserved FFU Status Pre loading data size Max pre loading data size Product state awareness enablement Secure Removal Type Reserved Field MODE_CONFIG MODE_OPERATION_CODES FFU_STATUS PRE_LOADING_DATA_SIZE MAX_PRE_LOADING_DATA_SIZE PRODUCT_STATE_AWARENESS_E NABLEMENT SECURE_REMOVAL_TYPE CSD slice [31:0] [30] [29] [28:27] [26] [25:22] [21:18] [17] [16] [15:0] Cell Type TBD R/W/E_P W/E_P EXT_CSD value 0h 0h R R/W/E_P R 0h 0h 8GB:E90000h R/W/E & R 1 R/W & R 3Bh [Table 21]Extended CSD • Reserved bits should read as “0” • Obsolete values should be don’t care Remark Rev 1.1 / Nov. 2014 52 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 7.5 RCA (Relative card address) The writable 16-bit relative card address (RCA) register carries the card address assigned by the host during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The default value of the RCA register is 0x0001. The value 0x0000 is reserved to set all cards into the Stand-by State with CMD7. 7.6 DSR (Driver stage register) It can be optionally used to improve the bus performance for extended operating conditions (depending on parameters like bus length, transfer rate or number of Devices). The CSD register carries the information about the DSR register usage. The default value of the DSR register is 0x404. Rev 1.1 / Nov. 2014 53 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 4Gb LPDDR2-S4B SDRAM Rev 1.1 / Nov. 2014 54 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Addressing Table Parameter Configuration Bank Address Row Address Column Address x16 32Mb x 8banks x 16 BA0 ~ BA2 R0 ~ R13 C0 ~ C10 4Gb x32 16Mb x 8banks x 32 BA0 ~ BA2 R0 ~ R13 C0 ~ C9 Note: 1. The least-significant column address CA0 is not transmitted on the CA bus, and is implied to be zero. 2. Row and Column Address values on the CA bus that are not used don’t care. Rev 1.1 / Nov. 2014 55 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) LPDDR2 SDRAM PIN DESCRIPTIONS SYMBOL TYPE DESCRIPTION CK_t, CK_c Input Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK_t. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled at the positive Clock edge. Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by the crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is defined by the crosspoint of a falling CK_t and a rising CK_c. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and CKE Input therefore device input buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is considered part of the command code. CKE is sam- pled at the positive Clock edge. CS_n CA0 - CA9 DQ0-DQ15 (x16) DQ0-DQ31 (x32) DQS0_t -DQS1_t, DQS0_c - DQS1_c (x16) DQS0_t -DQS3_t, DQS0_c - DQS3_c (x32) DM0-DM1 (x16) DM0-DM3 (x32) VDD1 VDD2 Input Input I/O I/O Input Supply Supply Chip Select: CS_n is considered part of the command code. CS_n is sampled at the positive Clock edge. DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. Data Inputs/Output: Bi-directional data bus Data Strobe (Bi-directional, Differential): The data strobe is bi-directional (used for read and write data) and differential (DQS_t and DQS_c). It is output with read data and input with write data. DQS is edge-aligned to read data and centered with write data. For x16, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7 and DQS1_t and DQS1_c to the data on DQ8 - DQ15. For x32, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and DQS1_c to the data on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23, DQS3_t and DQS3_c to the data on DQ24 - DQ31. Input Data Mask: DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both edges of DQS_t. Although DM is for input only, the DM loading shall match the DQ and DQS_t (or DQS_c) loading. DM0 is the input data mask signal for the data on DQ0-7. For x16 and x32 devices, DM1 is the input data mask signal for the data on DQ8-15. For x32 devices, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data on DQ24-31. Core Power Supply 1 Core Power Supply 2 VDDCA VDDQ VREFCA VREFDQ VSS VSSCA VSSQ ZQ Supply Supply Supply Supply Supply Supply Supply I/O Input Receiver Power Supply: Power for CA0-9, CKE, CS_n, CK_t and CK_c input buffers. I/O Power Supply: Power supply for data input/output buffers. Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all CA0-9, CKE, CS_n, CK_t and CK_c input buffers. Reference Voltage for DQ Input Receiver: Reference voltage for all Data input buffers. Ground Ground for Input Receivers I/O Ground Reference Pin for Output Drive Strength Calibration Note 1. Data includes DQ and DM Rev 1.1 / Nov. 2014 56 STATE DIAGRAM H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Power Applied Resetting MR Reading Resetting Power Down PR, PRA Power On DPDX MRR RESET Resetting PD PDX RESET MR Writing MRW MRR Idle MR Reading Deep Power Down DPD Idle1 ACT SREF Self Refreshing SREFX REF PD PDX Idle Power Down Active Power Down BST Write PDX PD WR Active MRR Active MR Reading BST RD RD Refreshing Automatic Sequence Command Sequence Writing WRA WRA Reading RDA RDA Writing with Autoprecharge PR, PRA Reading with Autoprecharge Precharging PD = Enter Power Down PDX = Exit Power Down ACT = Activate WR(A) = Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) PR(A) = Precharge (All) MRW = Mode Register Write MRR = Mode Register Read SREF = Enter Self Refresh SREFX = Exit Self Refresh REF = Refresh BST = Burst Terminate DPD = Enter Deep Power Down DPDX = Exit Deep Power Down RESET = Reset is achieved through MRW command Note 1. For LPDDR2 SDRAM in the Idle state, all banks are precharged. Rev 1.1 / Nov. 2014 57 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) POWER-UP, INITIALIZATION and POWER-OFF LPDDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power Ramp and Device Initialization The following sequence shall be used to power up an LPDDR2 device. Unless specified otherwise, these steps are mandatory and apply to the device. 1. Power Ramp While applying power (after Ta), CKE shall be held at a logic low level ( 0.2 x VDDCA), all other inputs shall be between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is held low. On or before the completion of the power ramp (Tb) CKE must be held low. DQ, DM, DQS_t and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp to avoid latch-up. CK_t, CK_c, CS_n, and CA input levels must be between VSSCA and VDDCA during voltage ramp to avoid latch-up. The following conditions apply: Ta is the point where any power supply first reaches 300 mV. After Ta is reached, VDD1 must be greater than VDD2 - 200 mV. After Ta is reached, VDD1 and VDD2 must be greater than VDDCA - 200 mV. After Ta is reached, VDD1 and VDD2 must be greater than VDDQ - 200 mV. After Ta is reached, VREF must always be less than all other supply voltages. The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100 mV. The above conditions apply between Ta and power-off (controlled or uncontrolled). Tb is the point when all supply voltages are within their respective min/max operating conditions. Reference voltages shall be within their respective min/max operating conditions a minimum of 5 clocks before CKE goes high. For supply and reference voltage operating conditions, see the section of AC and DC Operating Condition. Power ramp duration tINIT0 (Tb - Ta) must be no greater than 20 ms. Note: VDD2 is not present in some systems. Rules related to VDD2 in those cases do not apply. 2. CKE and clock Beginning at Tb, CKE must remain low for at least tINIT1 = 100 ns, after which it may be asserted high. Clock must be stable at least tINIT2 = 5 x tCK} prior to the first low to high transition of CKE (Tc). CKE, CS_n and CA inputs must observe setup and hold time (tIS, tIH) requirements with respect to the first rising clock edge (as well as to the subsequent falling and rising edges). The clock period shall be within the range defined for tCKb (18 ns to 100 ns), if any Mode Register Reads are performed. Mode Register Writes can be sent at normal clock operating frequencies so long as all AC Timings are met. Furthermore, some AC parameters (e.g. tDQSCK) may have relaxed timings (e.g. tDQSCKb) before the system is appropriately configured. While keeping CKE high, issue NOP commands for at least tINIT3 = 200 us. (Td). 3. Reset command After tINIT3 is satisfied, a MRW(Reset) command shall be issued (Td). The memory controller may optionally issue a Precharge-All command prior to the MRW(Reset) command. Wait for at least tINIT4 = 1 us while keeping CKE asserted and issuing NOP commands. Rev 1.1 / Nov. 2014 58 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 4. Mode Registers Reads and Device Auto-Initialization (DAI) polling: After tINIT4 is satisfied (Te) only MRR commands and power-down entry/exit commands are allowed. Therefore, after Te, CKE may go low in accordance to Power-Down entry and exit specification (see the section of "Power-down"). The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is complete or the memory controller shall wait a minimum of tINIT5 before proceeding. As the memory output buffers are not properly configured yet, some AC parameters may have relaxed timings before the system is appropriately configured. After the DAI-bit (MR0, “DAI”) is set to zero “DAI complete” by the memory device, the device is in idle state (Tf). The state of the DAI status bit can be determined by an MRR command to MR0. The SDRAM will set the DAI-bit no later than tINIT5 (10 us) after the Reset command. The memory controller shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding. After the DAI-Bit is set, it is recommended to determine the device type and other device characteristics by issuing MRR commands (see the section of “Mode Register Definition”). 5. ZQ Calibration: After tINIT5 (Tf), an MRW ZQ Initialization Calibration command may be issued to the memory (MR10). For LPDDR2 devices which do not support the ZQ Calibration command (meaning that RON is connected to VDDCA), this command shall be ignored. This command is used to calibrate the LPDDR2 output drivers (RON) over process, voltage, and temperature. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. In systems in which more than one LPDDR2 device exists on the same bus, the controller must not overlap ZQ Calibration commands. The device is ready for normal operation after tZQINIT. 6. Normal Operation: After tZQINIT (Tg), MRW commands shall be used to properly configure the memory, for example the output buffer driver strength, latencies etc. Specifically, MR1, MR2 and MR3 shall be set to configure the memory for the target frequency and memory configuration. To support simple boot from the NVM, some Mode Registers are reset to default values during Device Auto-Initialization. See the Mode Register section of this specification for default values. The LPDDR2 device will now be in IDLE state and ready for any valid command. After Tg, the clock frequency may be changed according to the clock frequency change procedure described in section “Input clock stop and frequency change”. Symbol tINIT0 tINIT1 tINIT2 tINIT3 tINIT4 tINIT5 Table. Timing Parameters for initialization Parameter Maximum Power Ramp Time Minimum CKE low time after completion of power ramp Minimum stable clock before first CKE high Minimum idle time after first CKE assertion Minimum idle time after Reset command Maximum duration of Device Auto-Initialization Value min max - 20 100 - 5 - 200 - 1 - - 10 Unit ms ns tCK us us us Rev 1.1 / Nov. 2014 59 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Symbol tZQINIT tCKb Parameter ZQ Initial Calibration for LPDDR2-S4 devices Clock cycle time during boot Value min max 1 - 18 100 Unit us ns Ta CK_t / CK_c Tb Tc Td Te tINIT2 = 5 tCK (min) Tf Tg Supplies tINIT0 = 20 ms (max) CKE CA* RTT DQ tINIT3 = 200 us (min) tINIT1 = 100 ns (min) tISCKE RESET PD tINIT5 tINIT4 = 1 us (min) tZQINIT MRR ZQC Valid * Midlevel on CA bus means: valid NOP Figure. Power Ramp and Initialization Sequence Initialization After Reset (without Power ramp) If the RESET command is issued outside the power up initialization sequence, the re-installation procedure shall begin with step 3 (Td). Power-off Sequence The following sequence shall be used to power off the LPDDR2 device. Unless specified otherwise, these steps are mandatory and apply to the devices. While removing power, CKE shall be held at a logic low level ( 0.2 x VDDCA), all other inputs shall be between VILmin and VIHmax. The LPDDR2 device will only guarantee that outputs are in a high impedance state while CKE is held low. DQ, DM, DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during power off sequence to avoid latch-up. CK_t, CK_c, CS_n, and CA input levels must be between VSSCA and VDDCA during power off sequence to avoid latch-up. Rev 1.1 / Nov. 2014 60 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition table. Tz is the point where all power supplies are below 300 mV. After Tz, the device is powered off. The time between Tx and Tz(tPOFF) shall be less than 2s. The following conditions apply: - Between Tx and Tz, VDD1 must be greater than VDD2 - 200 mV. - Between Tx and Tz, VDD1 and VDD2 must be greater than VDDCA - 200 mV. - Between Tx and Tz, VDD1 and VDD2 must be greater than VDDQ - 200 mV. - Between Tx and Tz, VREF must always be less than all other supply voltages. The voltage difference between any of VSS, VSSQ, and VSSCA pins may not exceed 100 mV. For supply and reference voltage operating conditions, see the section of AC and DC Operating Conditions. Note: VDD2 is not present in some systems. Rules related to VDD2 in those cases do not apply. Symbol tPOFF Table. Timing Parameters for Uncontrolled Power-off Parameter Maximum Power-off ramp time Value min max - 2 Unit s Uncontrolled Power-Off Sequence The following sequence shall be used to power off the LPDDR2 device under uncontrolled condition. Unless specified otherwise, these steps are mandatory and apply to the devices. Tx is the point where any power supply decreases under its minimum value specified in the DC operating condition table. After turning off all power supplies, any power supply current capacity must be zero, except for any static charge remaining in the system. Tz is the point where all power supply first reaches 300 mV. After Tz, the device is powered off. The time between Tx and Tz (tPOFF) shall be less than 2s. The relative level between supply voltages are uncontrolled during this period. VDD1 and VDD2 shall decrease with a slope lower than 0.5 V/usec between Tx and Tz. Uncontrolled power off sequence can be applied only up to 400 times in the life of the device. Rev 1.1 / Nov. 2014 61 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Mode Register Definition Table below shows the mode registers for LPDDR2 SDRAM. Each register is denoted as “R” if it can be read but not written, “W” if it can be written but not read, and “R/W” if it can be read and written. Mode Register Read command shall be used to read a register. Mode Register Write command shall be used to write a register. MR# MA <7:0> Function Table. Mode Register Assignment Access OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Link 0 00H Device Info. R (RFU) RZQI (Optional) DNVI DI DAI go to MR0 1 01H Device Feature1 W nWR (for AP) WC BT BL go to MR1 2 02H Device Feature 2 W (RFU) RL & WL go to MR2 3 03H I/O Config-1 W (RFU) DS go to MR3 4 04H Refresh Rate R TUF (RFU) Refresh Rate go to MR4 5 05H Basic Config-1 R Manufacturer ID go to MR5 6 06H Basic Config-2 R Revision ID1 go to MR6 7 07H Basic Config-3 R Revision ID2 go to MR7 8 08H Basic Config-4 R I/O width Density Type go to MR8 9 09H Test Mode W Vendor-Specific Test Mode go to MR9 10 0AH IO Calibration W Calibration Code go to MR10 16 10H PASR_Bank W Bank Mask go to MR16 17 11H PASR_Segment W Segment Mask go to MR17 32 20H DQ Calibration Pattern A R See the section of DQ Calibration go to MR32 40 28H DQ Calibration Pattern B R See the section of DQ Calibration go to MR40 63 3FH Reset W X go to MR63 Note: 1. RFU bits shall be set to `0' during Mode Register writes. 2. RFU bits shall be read as `0' during Mode Register reads. 3. All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS_t, DQS_c shall be toggled. 4. All Mode Registers that are specified as RFU shall not be written. 5. Writes to read-only registers shall have no impacts on the functionality of the device. Rev 1.1 / Nov. 2014 62 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) MR0 Device Information (MA<7:0> = 00H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 (RFU) RZQI (Optional) DNVI DI DAI 0B: DAI complete DAI (Device Auto-Initialization Status) Read-only OP0 1B: DAI still in progress DI (Device Information) Read-only OP1 0B: SDRAM DNVI (Data Not Valid Information) Read-only OP2 0B: DNV not supported 1, 2 00B: ZQ self test not supported 01B: ZQ-pin may connect to VDDCA or float RZQI (Built in Self Test for RZQ Information) Read-only P4:OP3 10B: ZQ-pin may short to GND 3 11B: ZQ-pin self test completed, no error condition detected (ZQ-pin may not connect to VDD or float nor short to GND) Note: 1. LPDDR2 SDRAM will not implement DNV functionality. 2. If DNV functionality is not implemented, the device shall not drive the DM/DNV signals. 3. RZQI, if supported, will be set upon completion of the MRW ZQ Initialization Calibration command. 4. If ZQ is connected to VDDCA to set default calibration, OP[4:3] shall be set to 01. If ZQ is not connected to VDDCA, either OP[4:3]=01 or OP[4:3]=10 might indicate a ZQ-pin assembly error. It is recommended that the assembly error is corrected. 5. In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 4), the LPDDR2 device will default to factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the system may not function as intended. 6. In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a resistor connection to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e. 240-ohm +/-1%). MR1 Device Feature 1 (MA<7:0> = 01H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 nWR (for AP) WC BT BL 010B: BL4 (default) BL Write-only OP<2:0> 011B: BL8 100B: BL16 All others: reserved 0B: Sequential (default) BT Write-only OP<3> 1B: Interleaved 1 0B: Wrap (default) WC Write-only OP<4> 1B: No wrap (allowed for BL4 only) Rev 1.1 / Nov. 2014 63 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 001B: nWR=3 (default) 010B: nWR=4 011B: nWR=5 nWR Write-only OP<7:5> 100B: nWR=6 2 101B: nWR=7 110B: nWR=8 All others: reserved Note: 1. BL 16, interleaved is not an official combination to be supported. 2. Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write burst with AP enabled. It is determined by RU (tWR/tCK). Table. Burst Sequence by BL, BT, and WC Burst Cycle Number and Burst Address Sequence C3 C2 C1 C0 WC BT BL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X X 0B 1B 0B 0B wrap any 4 0 2 1 3 2 0 3 1 X X X 0B nw any y y+1 y+2 y+3 X 0B 0B 0B 01234567 X 0B 1B 0B X 1B 0B 0B seq 23456701 45670123 X X 1B 0B 1B 0B 0B 0B wrap 8 6 0 7 1 0 2 1 3 2 4 3 5 4 6 5 7 X 0B 1B 0B X 1B 0B 0B int 23016745 45670123 X 1B 1B 0B 67452301 X X X 0B nw any illegal (not allowed) 0B 0B 0B 0B 0 123 456 78 9ABCDE F 0B 0B 1B 0B 2 345 678 9ABCDEF 0 1 0B 1B 0B 0B 456789ABCDEF 0123 0B 1B 1B 1B 0B 0B 1B 0B 1B 0B 0B wrap seq 0B 16 6 8 A 7 9 B 8 A C 9 B D A C E B D F C E 0 D F 1 E 0 2 F 1 3 0 2 4 1 3 5 2 4 6 3 5 7 4 6 8 5 7 9 1B 1B 0B 0B CDEF 0123456789AB 1B 1B 1B 0B EF 0123456789ABCD X X X 0B int illegal (not allowed) X X X 0B nw any illegal (not allowed) Note: 1. C0 input is not present on CA bus. It is implied zero. 2. For BL=4, the burst address represents C1 - C0. 3. For BL=8, the burst address represents C2 - C0. 4. For BL=16, the burst address represents C3 - C0. 5. For no-wrap (nw), BL4, the burst shall not cross the page boundary and shall not cross sub-page boundary. The variable y may start at any address with C0 equal to 0 and may not start at any address in Table. Non Wrap Restrictions below for the respective density and bus width combinations. 6. ‘nw’ means Non Wrap. ‘any’ means Sequential and interleaved. ‘seq’ means sequential and ‘int’ means interleaved. Rev 1.1 / Nov. 2014 64 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Table. Non Wrap Restrictions 4Gb Not across full page boundary x16 7FE,7FF,000,001 x32 3FE,3FF,000,001 Not across sub page boundary x16 3FE,3FF,400,401 x32 None Note: Non-wrap BL=4 data-orders shown above are prohibited. MR2 Device Feature 2 (MA<7:0> = 02H) OP7 OP6 OP5 OP4 (RFU) OP3 OP2 OP1 RL & WL RL & WL Write-only OP<3:0> 0001B: RL3/WL1(default) 0010B: RL4/WL2 0011B: RL5/WL2 0100B: RL6/WL3 0101B: RL7/WL4 0110B: RL8/WL4 All others: reserved OP0 MR3 I/O Configuration 1 (MA<7:0> = 03H) OP7 OP6 OP5 OP4 (RFU) OP3 OP2 OP1 DS 0000B: reserved 0001B: 34.3 0010B: 40 (default) 0011B: 48 DS Write-only OP<3:0> 0100B: 60 0101B: reserved 0110B: 80 0111B: 120 All others: reserved OP0 Rev 1.1 / Nov. 2014 65 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) MR4 Refresh Mode (MA<7:0> = 04H) OP7 OP6 OP5 OP4 TUF (RFU) OP3 OP2 OP1 Refresh Rate OP0 Refresh Rate Temperature Update Flag (TUF) Read-only Read-only 000B: Low temperature operating limit exceeded 001B: 4 x tREFI, 4 x tREFIpb, 4 x tREFW 010B: 2 x tREFI, 2 x tREFIpb, 2 x tREFW 011B: 1 x tREFI, 1 x tREFIpb, 1 x tREFW (85C) OP<2:0> 100B: reserved 101B: 0.25 x tREFI, 0.25 x tREFIpb, 0.25 x tREFW, do not de-rate AC timing 110B: 0.25 x tREFI, 0.25 x tREFIpb, 0.25 x tREFW, de-rate AC timing 111B: High temperature operating limit exceeded 0B: OP<2:0> value has not changed since last read of MR4 OP<7> 1B: OP<2:0> value has changed since last read of MR4 Note: 1. A Mode Register Read from MR4 will reset OP7 to ‘0’. 2. OP7 is reset to ‘0’ at power-up 3. If OP2 equals `1', the device temperature is greater than 85oC. 4. OP7 is set to ‘1’ if OP2:OP0 has changed at any time since the last read of MR4. 5. LPDDR2 might not operate properly when OP[2:0] = 000B or 111B. 6. See the section of Temperature Sensor for information on the recommended frequency of reading MR4. 7. Some of the code for Refresh rate are not supported. Please ask Hynix office in detail. 8. LPDDR2-S4 devices shall be de-rated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP and tRRD. tDQSCK shall be de-rated according to the tDQSCK de-rating in “AC timing table”. Prevailing clock frequency spec and related setup and hold timings shall remain unchanged. MR5 Basic Configuration1 (MA<7:0> = 05H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Manufacturer ID Company ID Read-only OP<7:0> 0000 0110B: Hynix Semiconductor MR6 Basic Configuration2 (MA<7:0> = 06H) OP7 OP6 OP5 OP4 OP3 Revision ID 1 Revision ID1 Read-only OP<7:0> 00000011B OP2 OP1 OP0 MR7 Basic Configuration3 (MA<7:0> = 07H) OP7 OP6 OP5 OP4 OP3 Revision ID 2 OP2 Revision ID2 Read-only OP<7:0> 00000000B: A-version OP1 OP0 Rev 1.1 / Nov. 2014 66 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) MR8 Basic Configuration4 (MA<7:0> = 08BH) OP7 OP6 I/O width OP5 OP4 OP3 Density OP2 OP1 OP0 Type Type Density I/O width Read-only Read-only Read-only OP<1:0> OP<5:2> OP<7:6> 00B: S4 SDRAM 0110B: 4Gb 00B: x32 01B: x16 MR9 Test Mode (MA<7:0> = 09H) OP7 OP6 OP5 OP4 OP3 Vendor-specific Test Mode OP2 OP1 OP0 MR10 ZQ Calibration (MA<7:0> = 0AH) OP7 OP6 OP5 OP4 OP3 Calibration Code OP2 OP1 OP0 Calibration Code Write Only OP<7:0> 0xFF: Calibration command after initialization 0xAB Long Calibration 0x56: Short Calibration 0xC3: ZQ Reset others: reserved Note: 1. Host processor shall not write MR10 with "reserved" values 2. LPDDR2 devices shall ignore calibration command when a "reserved" value is written into MR10. 3. See AC timing table for the calibration latency. 4. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see the section of "Mode Register Write ZQ Calibration Command") or default calibration (through the ZQRESET command) is supported. If ZQ is connected to VDDCA, the device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection shall not change after power is applied to the device. 5. LPDDR2 devices that do not support calibration shall ignore the ZQ Calibration command. 6. Optionally, the MRW ZQ Initialization Calibration command will update MR0 to indicate RZQ pin connection. Rev 1.1 / Nov. 2014 67 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) MR16 PASR Bank Mask (MA<7:0> = 10H) OP7 OP6 OP5 OP4 OP3 OP2 OP1 S4 SDRAM Bank Mask S4 SDRAM Bank Mask Write-only OP<7:0> 0B: refresh enable to the bank (unmasked, default) 1B: refresh blocked (masked) Note: For 4bank S4 SDRAM (64Mb ~ 512Mb), only OP<3:0> are used. OP0 OP Bank Mask 4-Bank LPDDR2-S4 8-Bank LPDDR2-S4 0 XXXXXXX1 Bank 0 Bank 0 1 XXXXXX1X Bank 1 Bank 1 2 XXXXX1XX Bank 2 Bank 2 3 XXXX1XXX Bank 3 Bank 3 4 XXX1XXXX - Bank 4 5 XX1XXXXX - Bank 5 6 X1XXXXXX - Bank 6 7 1XXXXXXX - Bank 7 MR17 PASR Segment Mask (MA<7:0> = 11H) OP7 OP6 OP5 OP4 OP3 Segment Mask OP2 OP1 OP0 Segment Mask Write-only OP<7:0> 0B: refresh enable to the segment (unmasked, default) 1B: refresh blocked (masked) Segment OP Segment Mask 4Gb R<13:11> 0 0 XXXXXXX1 1 1 XXXXXX1X 2 2 XXXXX1XX 3 3 XXXX1XXX 4 4 XXX1XXXX 5 5 XX1XXXXX 6 6 X1XXXXXX 7 7 1XXXXXXX 000B 001B 010B 011B 100B 101B 110B 111B Note: This table indicates the range of row address in each masked segment. X is do not care for a particular segment. Rev 1.1 / Nov. 2014 68 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) MR32 DQ Calibration Pattern A (MA<7:0> = 20H): MRR only Reads to MR32 return DQ Calibration Pattern A. See the section of DQ Calibration. MR40 DQ Calibration Pattern B (MA<7:0> = 28H): MRR only Reads to MR40 return DQ Calibration Pattern B. See the section of DQ Calibration. MR63 Reset (MA<7:0> = 3FH): MRW only OP7 OP6 OP5 OP4 OP3 OP2 X Note: For additional information on MRW RESET, see Mode Register Write Command section. OP1 OP0 Rev 1.1 / Nov. 2014 69 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) TRUTH TABLE Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the LPDDR2 device must be powered down and then restarted through the specified initialization sequence before normal operation can continue. Rev 1.1 / Nov. 2014 70 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) COMMAND TRUTH TABLE Command MRW MRR Refresh (per bank)11 Refresh (all bank) Enter Self Refresh Active (bank) Write (bank) SDR Command Pins (2) CKE CK_t(n-1) CK_t(n) CS_n L H H X L H H X L H H X L H H X H L L X X L H H X L H H X Read (bank) L H H X Precharge (per bank, H all bank) BST H Enter H Deep Power Down X NOP H Maintain SREF, PD, DPD L (NOP) NOP H Maintain SREF, PD, DPD L (NOP) Enter H Power Down X Exit SREF, PD, L DPD X L H X L H X L L X L H X L L X H H X H L X H L X H H X CA0 L MA6 L MA6 L L L L R0 H AP3,4 H AP3,4 H X H H H H CA1 L MA7 L MA7 L L L H R1 L C3 L C3 H X H H H H CA2 L OP0 L H H H R8 R2 L C4 H C4 L X L L H H DDR CA Pins (10) CA3 CA4 CA5 CA6 CA7 L MA0 MA1 MA2 MA3 OP1 OP2 OP3 OP4 OP5 H MA0 MA1 MA2 MA3 X L X X H X X X X R9 R10 R11 R12 BA0 R3 R4 R5 R6 R7 X X C1 C2 BA0 C5 C6 C7 C8 C9 X X C1 C2 BA0 C5 C6 C7 C8 C9 H AB2 X X BA0 X X X X X L X X X X X X X X X X X X X X X X CA8 MA4 OP6 MA4 BA1 R13 BA1 C10 BA1 C10 BA1 X CA9 MA5 OP7 MA5 BA2 R14 BA2 C11 BA2 C11 BA2 X CK_t edge rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling rising falling Rev 1.1 / Nov. 2014 71 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Note: 1. All commands are defined by states of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock. 2. Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. 3. AP is significant only to SDRAM. 4. AP “high” during a READ or WRITE command indicates that an auto-precharge will occur to the bank associated with the READ or WRITE command. 5. “X” means “H or L (but a defined logic level)” 6. Self refresh exit and Deep Power Down exit are asynchronous. 7. VREF must be between 0 and VDDQ during Self Refresh and Deep Power Down operation. 8. CAxr refers to command/address bit “x” on the rising edge of clock. 9. CAxf refers to command/address bit “x” on the falling edge of clock. 10. CS_n and CKE are sampled at the rising edge of clock. 11. Per Bank Refresh is only allowed in devices with 8 banks. 12. The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero. 13. AB “high” during Precharge command indicates that all bank Precharge will occur. In this case, Bank Address is do-not-care. Rev 1.1 / Nov. 2014 72 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) CKE TRUTH TABLE Current State*3 CKEn-1 *1 CKEn *1 Active Power L L Down L H Idle Power L L Down L H L L Resetting Power Down L H Deep Power L L Down L H L L Self Refresh L H Bank(s) Active H L H L All Banks Idle H L H L Resetting H L H H CS_n *2 X H X H X H X H X H H H L L H Command n *4 Operation n *4 Next State Note X Maintain Active Power Down Active Power Down NOP Exit Active Power Down Active 6, 9 X Maintain Idle Power Down Idle Power Down NOP Exit Idle Power Down Idle 6, 9 X Maintain Resetting Power Down Resetting Power Down NOP Exit Resetting Power Down Idle or Resetting 6, 9, 12 X Maintain Deep Power Down Deep Power Down NOP Exit Deep Power Down Power On 8 X Maintain Self Refresh Self Refresh NOP Exit Self Refresh Idle 7, 10 NOP Enter Active Power Down Active Power Down NOP Enter Idle Power Down Idle Power Down Enter SELF REFRESH Enter Self Refresh Self Refresh Deep Power Down Enter Deep Power Down Deep Power Down NOP Enter Resetting Power Down Resetting Power Down Refer to the Command Truth Table Note: 1. "CKEn" is the logic state of CKE at clock rising edge n; "CKEn-1" was the state of CKE at the previous clock edge. 2. "CS_n" is the logic state of CS_n at the clock rising edge n; 3. "Current state" is the state of the LPDDR2 device immediately prior to clock edge n. 4. "Command n" is the command registered at clock edge N, and "Operation n" is a result of "Command n". 5. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 6. Power Down exit time (tXP) should elapse before a command other than NOP is issued. 7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP is issued. 8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional Description. 9. The clock must toggle at least twice during the tXP period. 10. The clock must toggle at least twice during the tXSR time. 11. 'X' means `Don't care'. 12. Upon exiting Resetting Power Down, the device will return to the Idle state if tINIT5 has expired. Rev 1.1 / Nov. 2014 73 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Current State Bank n - Command to Bank n Current State Command Operation Next State Note Any Idle Row Active Reading Writing Power On Resetting NOP ACTIVATE AUTO REFRESH(Per Bank) AUTO REFRESH(All Bank) MRW MRR Reset Precharge READ WRITE MRR Precharge READ WRITE BST WRITE READ BST Reset MRR Continue previous operation Select and activate row Begin to refresh Begin to refresh Load value to Mode Register Read value from Mode Register Begin Device Auto-Initialization Deactive row in bank or banks Select Column, and start read burst Select Column, and start write burst Read value from Mode Register Deactivate row in bank or banks Select column, and start new read burst Select column, and start write burst Read burst terminate Select Column, and start new write burst Select column, and start read burst Write burst terminate Begin Device Auto-Initialization Read value from Mode Register Current State Active Refreshing (Per Bank) Refreshing (All Bank) MR Writing Idle MR Reading Resetting Precharging Reading Writing Active MR Reading Precharging Reading Writing Active Writing Reading Active Resetting Resetting MR Reading 6 7 7 7,8 9, 15 9 10,11 10,11,12 13 10,11 10,11,14 13 7,9 Note: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Power Down. 2. All states and sequences not shown are illegal or reserved. 3. Current State Definitions: Idle: The bank or banks have been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress. Reading: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Writing: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other banks are determined by its current state and Table “Current State Bank n - Command to Bank n”, and according to Table “Current State Bank n Command to Bank m”. Precharging: starts with the registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the ‘Active’ state. Read with AP Enabled: starts with the registration of the READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP has been met, the bank will be in the idle state. Write with AP Enabled: starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; NOP commands must be applied to each positive clock edge during these states. Rev 1.1 / Nov. 2014 74 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Refreshing (Per Bank): starts with registration of a REFRESH (Per Bank) command and ends when tRFCpb is met. Once tRFCpb is met, the bank will be in an ‘idle’ state. Refreshing (All Bank): starts with registration of a REFRESH(All Bank) command and ends when tRFCab is met. Once tRFCab is met, the device will be in an ‘all banks idle’ state. Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Idle state. Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Resetting state. Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Row Active state. MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will be in the Idle state. Precharging All: starts with the registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. 6. Bank-specific; requires that the bank is idle and no bursts are in progress. 7. Not bank-specific; requires that all banks are idle and no bursts are in progress. 8. Not bank-specific reset command is achieved through MODE REGISTER WRITE command. 9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 10. A command other than NOP should not be issued to the same bank while a READ or WRITE burst with Auto Precharge is enabled. 11. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled. 12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BST must be used to end the READ prior to asserting a WRITE command. 13. Not bank-specific. BURST TERMINATE command affects the most recent read/write burst started by the most recent READ/WRITE command, regardless of bank. 14. A READ command may be applied after the completion of the WRITE burst; otherwise, a BST must be used to end the WRITE prior to asserting a READ command. 15. If a Precharge command is issued to a bank in the Idle state, tRP shall still apply. Rev 1.1 / Nov. 2014 75 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Current State Bank n - Command to Bank m Current State of Bank n Any Idle Row Activating, Active, or Precharging Reading (Autoprecharge disabled) Writing (Autoprecharge disabled) Reading with Autoprecharge Writing with Autoprecharge Power On Resetting Command for Bank m NOP Any ACTIVATE READ WRITE Precharge MRR BST READ WRITE ACTIVATE Precharge READ WRITE ACTIVATE Precharge READ WRITE ACTIVATE Precharge READ WRITE ACTIVATE Precharge Reset MRR Operation Continue previous operation Any command allowed to Bank m Select and activate row in Bank m Select column, and start read burst from Bank m Select column, and start write burst to Bank m Deactivate row in bank or banks Read value from Mode Register Read or Write burst terminate an ongoing Read/Write from/to Bank m Select column, and start read burst from Bank m Select column, and start write burst to Bank m Select and activate row in Bank m Deactivate row in bank or banks Select column, and start read burst from Bank m Select column, and start write burst to Bank m Select and activate row in Bank m Deactivate row in bank or banks Select column, and start read burst from Bank m Select column, and start write burst to Bank m Select and activate row in Bank m Deactivate row in bank or banks Select column, and start read burst from Bank m Select column, and start write burst to Bank m Select and activate row in Bank m Deactivate row in bank or banks Begin Device Auto-Initialization Read value from Mode Register Next State for Bank m Note Current State of Bank m - Active Reading Writing Precharging Idle MR Reading or Active MR Reading 18 7 8 8 9 10,11,13 Active 18 Reading Writing Active Precharging Reading Writing Active Precharging Reading Writing Active Precharging Reading Writing Active Precharging Resetting Resetting MR Reading 8 8,14 9 8,16 8 9 8,15 8,14,15 9 8,15,16 8,15 9 12, 17 Note: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. All states and sequences not shown are illegal or reserved. 3. Current State Definitions: Idle: the bank has been precharged, and tRP has been met. Active: a row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in Rev 1.1 / Nov. 2014 76 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) progress. Reading: a READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Writing: a WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4. REFRESH, SELF REFRESH, and MODE REGISTER write commands may only be issued when all bank are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. The following states must not be interrupted by any executable command; NOP commands must be applied during each clock cycle while in these states: Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Idle state. Resetting MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Resetting state. Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Row Active state. MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will be in the Idle state. 7. tRRD must be met between Activate command to Bank n and a subsequent Activate command to Bank m. 8. READs or WRITEs listed in the Command column include READs and WRITEs with Auto Precharge enabled and READs and WRITEs with Auto Precharge disabled. 9. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 10. MRR is allowed during the Row Activating state and MRW is prohibited during the Row Activating state. (Row Activating starts with registration of an Activate command and ends when tRCD is met.) 11. MRR is allowed during the Precharging state. (Precharging starts with registration of a Precharge command and ends when tRP is met. 12. Not bank-specific; requires that all banks are idle and no bursts are in progress. 13. The next state for Bank m depends on the current state of Bank m (Idle, Row Activating, Precharging, or Active). The reader shall note that the state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating state and Precharging, the next state may be Active and Precharge dependent upon tRCD and tRP respectively. 14. A WRITE command may be applied after the completion of the READ burst, otherwise a BST must be issued to end the READ prior to asserting a WRITE command. 15. Read with auto precharge enabled or a Write with auto precharge enabled may be followed by any valid command to other banks provided that the timing restrictions in the section of Precharge and Auto Precharge clarification are followed. 16. A READ command may be applied after the completion of the WRITE burst; otherwise, a BST must be issued to end the WRITE prior to asserting a READ command. 17. Reset command is achieved through MODE REGISTER WRITE command. 18. BST is allowed only if a Read or Write burst is ongoing Rev 1.1 / Nov. 2014 77 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) DATA MASK TRUTH TABLE Function DM Write Enable L Write Inhibit H Note: 1. Used to mask write data, provided coincident with the corresponding data. DQ Valid X Note 1 1 Rev 1.1 / Nov. 2014 78 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Absolute Maximum DC Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Voltage on VDD1 relative to VSS Voltage on VDD2 relative to VSS Voltage on VDDCA relative to VSSCA Voltage on VDDQ relative to VSSQ Voltage on Any Pin relative to VSS Storage Temperature Symbol VDD1 VDD2 VDDCA VDDQ VIN, VOUT TSTG Rating -0.4 ~ 2.3 -0.4 ~ 1.6 -0.4 ~ 1.6 -0.4 ~ 1.6 -0.4 ~ 1.6 -55 ~ 125 Unit V V V V V oC Notes 1 1 1, 3 1, 2 4 Note: 1. See "Power-Ramp" section in "Power-up, Initialization, and Power-Off" for relationships between power supplies. 2. VREFDQ 0.6 x VDDQ; however, VREFDQ may be  VDDQ provided that VREFDQ  300mV. 3. VREFCA  0.6 x VDDCA; however, VREFCA may be  VDDCA provided that VREFCA  300mV. 4. Storage Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement conditions, please refer to JESD51-2 standard. AC and DC Operating Conditions Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the LPDDR2 Device must be powered down and then restarted through the specialized initialization sequence before normal operation can continue. DC Operating Conditions Parameter Symbol Min Typ Core Power 1 VDD1 1.70 1.80 Core Power 2 VDD2 1.14 1.20 Input Buffer Power VDDCA 1.14 1.20 I/O Buffer Power VDDQ 1.14 1.20 Note: 1. When VDD2 is used, VDD1 uses significantly less power than VDD2. Max 1.95 1.30 1.30 1.30 Unit V V V V Input Leakage Current Parameter Symbol Min Max Unit Note Input Leakage current For CA, CKE, CS_n, CK_t, CK_c Any input 0V  VIN  VDDCA (All other pins not under test = 0V) IL -2 2 uA 2 VREF supply leakage current; VREFDQ = VDDQ/2 or VREFCA = VDDCA/2 IVREF -1 (All other pins not under test = 0V) 1 uA 1 Note: 1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ pins should be minimal. 2. Although DM is for input only, the DM leakage shall match the DQ and DQS_t/DQS_c output leakage specification. Rev 1.1 / Nov. 2014 79 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Operating Temperature Parameter Symbol Min Operating Temperature Standard Extended TOPER -25 -25 Max 85 105 Unit oC Note 1 1 Note: 1. Operating Temperature is the case surface temperature on the center/top side of the LPDDR2 device. For the measurement condi- tions, please refer to JESD51-2 standard. Please ask to SK hynix for the availability of Extended temperature range products. 2. Either the device case temperature rating or the temperature sensor may be issued to set an appropriate refresh rate, determine the need for AC timing derating and/or monitor the operating temperature. When using the temperature sensor, the actual device case temperature may be higher than the TOPER rating that applies for the Standard or Extended Temperature Ranges. For example, TCASE may be above 85oC when the temperature sensor indicates a temperature of less than 85oC. AC and DC Logic Input Levels for Single-Ended CA and CS_n Signals Parameter AC Input Logic High AC Input Logic Low DC Input Logic High DC Input Logic Low Reference Voltage for CA and CS_n Inputs Symbol VIHCA(AC) VILCA(AC) VIHCA(DC) VILCA(DC) VREFCA(DC) LPDDR2 200 to 400 Min Max CA and CS_n Inputs VREF+0.3 Note 2 Note 2 VREF - 0.3 VREF+0.2 VDDCA VSSCA VREF - 0.2 LPDDR2 533 to 1066 Min Max VREF+0.22 Note 2 VREF+0.13 VSSCA Note 2 VREF - 0.22 VDDCA VREF - 0.13 0.49*VDDCA 0.51*VDDCA 0.49*VDDCA 0.51*VDDCA Unit V V V V V Note 1, 2 1, 2 1 1 3, 4 Note: 1. For CA and CS_n input only pins. VREF = VREFCA(DC). 2. See the section of Overshoot and Undershoot Specifications. 3. The ac peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than +/-1% VDDCA (for reference: approx. +/- 12 mV). 4. For reference: approx. VDDCA/2 +/- 12 mV. AC and DC Logic Input Levels for CKE Parameter CKE Input High Level CKE Input Low Level Symbol Min CKE Inputs VIHCKE 0.8*VDDCA VILCKE Note 1 Note: 1. See the section of Overshoot and Undershoot Specifications. Max Note 1 0.2*VDDCA Unit Note V 1 V 1 Rev 1.1 / Nov. 2014 80 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) AC and DC Logic Input Levels for Single-Ended Data (DQ and DM) Signals Parameter AC Input High Voltage AC Input Low Voltage DC Input High Voltage DC Input Low Voltage Reference Voltage for DQ and DM Inputs Symbol VIHDQ(AC) VILDQ(AC) VIHDQ(DC) VILDQ(DC) VREFDQ(DC) LPDDR2 200 to 400 Min Max Data Inputs (DQ and DM) VREF+0.3 Note 2 Note 2 VREF-0.3 VREF+0.2 VDDQ VSSQ VREF-0.2 LPDDR2 533 to 1066 Min Max VREF+0.22 Note 2 VREF+0.13 VSSQ Note 2 VREF-0.22 VDDQ VREF-0.13 0.49*VDDQ 0.51*VDDQ 0.49*VDDQ 0.51*VDDQ Unit Note V 1, 2 V 1, 2 V 1 V 1 V 3, 4 Note: 1. For DQ input only pins. VREF = VREFDQ(DC). 2. See the section of Overshoot and Undershoot Specifications. 3. The ac peak noise on VREFDQ may not allow VREFDQ to deviate from VREFDQ(DC) by more than +/-1% VDDQ (for reference: approx. +/- 12 mV). 4. For reference: approx. VDDQ/2 +/- 12 mV. Rev 1.1 / Nov. 2014 81 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrated in Figure below. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VDD stands for VDDCS for VREFCA and VDDQ for VREFDQ. VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec) and is specified as a fraction of the linear average of VDDCA or VDDQ also over a very long period of time (e.g. 1sec). This average has to meet the min/max requirements in Table “Electrical Characteristics and Operating Conditions”. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than +/- 1% VDD. VREF(t) cannot track noise on VDDQ or VDDCA if this would send VREF outside these specifications. voltage VDD VREF(DC) VREF ac-noise VREF(t) VREF(DC)max VDD/2 VREF(DC)min VSS Figure. Illustration of VREF(DC) tolerance and VREF ac-noise limits time The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF " shall be understood as VREF(DC), as defined in Figure above. This clarifies that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. Devices will function correctly with appropriate timing deratings with VREF outside these specified levels so long as VREF is maintained between 0.44 x VDDQ (or VDDCA) and 0.56 x VDDQ (or VDDCA) and so long as the controller achieves the required single-ended AC and DC input levels from instantaneous VREF (see the Electrical Characteristics and Operating Conditions.) Therefore, system timing and voltage budgets need to account for VREF deviations outside of this range. This also clarifies that the LPDDR2 setup/hold specification and derating values need to include time and voltage asso- ciated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in LPDDR2 timings and their associated deratings. Rev 1.1 / Nov. 2014 82 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) AC and DC Logic Input Levels for Differential Signals (Clock and Strobe) Differential Signal Definition differential voltage tDVAC VIHDIFF(AC)MIN VIHDIFF(DC)MIN 0.0 VILDIFF(DC)MAX CK_t - CK_c DQS_t - DQS_c VILDIFF(AC)MAX half cycle tDVAC Figure. Definition of differential ac-swing and Time above ac-level tDVAC time Rev 1.1 / Nov. 2014 83 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Differential AC and DC Input Levels for Clock and Strobe Parameter DC Differential Input High DC Differential Input Low AC Differential Input High AC Differential Input Low Symbol LPDDR2 200 to 400 LPDDR2 533 to 1066 Min Max Min Max Clock (CK_t - CK_c) and Strobe(DQS_t - DQS_c) VIHDIFF(DC) 2 x (VIH(DC) - VREF) Note 3 2 x (VIH(DC) - VREF) Note 3 Unit Note V1 VILDIFF(DC) Note 3 2 x (VIL(DC) - VREF) Note 3 2 x (VIL(DC) - VREF) V 1 VIHDIFF(AC) 2 x (VIH(AC) - VREF) Note 3 2 x (VIH(AC) - VREF) Note 3 V2 VILDIFF(AC) Note 3 2 x (VIL(AC) - VREF) Note 3 2 x (VIL(AC) - VREF) V 2 Note: 1. Used to define a differential signal slew-rate. For CK_t - CK_c use VIH/VIL(DC) of CA and VREFCA; for DQS_t - DQS_c, use VIH/ VIL(DC) of DQs and VREFDQ; if a reduced dc-high or dc-low level is used for a signal group, then the reduced level applies also here. 2. For CK_t - CK_c use VIH/VIL(AC) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(AC) of DQs and VREFDQ; if a reduced achigh or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t, and DQS_c need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to the section "Overshoot and Undershoot Specifications". 4. For CK_t and CK_c, VREF = VREFCA(DC). For DQS_t and DQS_c, VREF = VREFDQ(DC). Table. Allowed time before ringback (tDVAC) for CK_t - CK_c and DQS_t - DQS_c tDVAC [ps] tDVAC [ps] Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 <1.0 @ |VIH/Ldiff(ac)| = 440mV MIN MAX 175 - 170 - 167 - 163 - 162 - 161 - 159 - 155 - 150 - 150 - @ |VIH/Ldiff(ac)| = 600mV MIN MAX 75 - 57 - 50 - 38 - 34 - 29 - 22 - 13 - 0 - 0 - Rev 1.1 / Nov. 2014 84 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK_t, DQS_t, CK_c, or DQS_c) has also to comply with certain requirements for single-ended signals. CK_t and CK_c shall meet VSEH(AC)min / VSEL(AC)max in every half-cycle. DQS_t, DQS_c shall meet VSEH(AC)min / VSEL(AC)max in every half-cycle proceeding and following a valid transition. Note that the applicable ac-levels for CA and DQ's are different per speed-bin. VDDCA or VDDQ VSEH(AC)min VDDCA/2 or VDDQ/2 VSEL(AC)max VSEH(AC) CK_t, CK_c DQS_t, or DQS_c VSSCA or VSSQ VSEL(AC) time Figure. Single-ended requirement for differential signals Note that while CA and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDDQ/2 for DQS_t, DQS_C and VDDCA/2 for CK_t, CK_c; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSEL(AC)max, VSEH(AC)min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. Rev 1.1 / Nov. 2014 85 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Single-ended Levels for Clock and Strobe Parameter Symbol LPDDR2 200 to 400 Min Max LPDDR2 533 to 1066 Min Max Clock (CK_t - CK_c) and Strobe(DQS_t - DQS_c) Unit Note Single-ended High Level for CK_t and CK_c Single-ended High Level for DQS_t and DQS_c VSEH(AC) (VDDCA/2)+0.3 (VDDQ/2)+0.3 Note 3 Note 3 (VDDCA/2)+0.22 (VDDQ/2)+0.22 Note 3 Note 3 V 1, 2 V 1, 2 Single-ended Low Level for CK_t and CK_c Single-ended Low Level for DQS_t and DQS_c VSEL(AC) Note 3 Note 3 (VDDCA/2)-0.3 (VDDQ/2)-0.3 Note 3 Note 3 (VDDCA/2)-0.22 V 1, 2 (VDDQ/2)-0.22 V 1, 2 Note: 1. For CK_t, CK_c use VSEH/VSEL(AC) of CA; for strobes (DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VSEH(AC)/VSEL(AC) for CA is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however the single-ended signals CK_t, CK_c, DQS0_t, DQS0_c, DQS1_t, DQS1_c, DQS2_t, DQS2_c, DQS3_t, DQS3_c need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to the section of Overshoot and Undershoot Specifications. Rev 1.1 / Nov. 2014 86 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK_t, CK_c and DQS_t, DQS_c) must meet the requirements in “Single-ended Levels for Clock and Strobe”. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS. VDDCA or VDDQ CK_c, DQS_c VIX VIX VDDCA/2 or VDDQ/2 VIX CK_t, DQS_t Figure. VIX definition VSSCA or VSSQ Cross Point Voltage for Differential Input Signals (Clock and Strobe) Parameter Symbol LPDDR2 200 to 1066 Min Max Clock (CK_t - CK_c) and Strobe(DQS_t - DQS_c) Differential Input Cross Point Voltage relative to VDDCA/2 for CK_t and CK_c VIXCA -120 120 Differential Input Cross Point Voltage relative to VDDQ/2 for DQS_t and DQS_c VIXDQ -120 120 Unit Note mV 1, 2 mV 1, 2 Note: 1. The typical value of VIX(AC) is expected to be about 0.5 x VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. 2. For CK_t and CK_c, VREF = VREFCA(DC). For DQS_t and DQS_c, VREF = VREFDQ(DC). Rev 1.1 / Nov. 2014 87 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Slew Rate Definitions for Single-ended Input Signals See "CA and CS_n Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals. Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK_t, CK_c and DQS_t, DQS_c) are defined and measured as shown in below Table and Figure. Differential Input Slew Rate Definition Parameter Measured From To Defined by Clock (CK_t - CK_c) and Strobe(DQS_t - DQS_c) Differential Input Slew Rate for Rising Edge (CK_t - CK_c and DQS_t - DQS_c) VILDIFFmax VIHDIFFmin [VIHDIFFmin - VILDIFFmax] / Delta tRDIFF Differential Input Slew Rate for Falling Edge (CK_t - CK_c and DQS_t - DQS_c) VIHDIFFmin VILDIFFmax [VIHDIFFmin - VILDIFFmax] / Delta tFDIFF Note: 1. The differential signal (i.e. CK_t - CK_c and DQS_t - DQS_c) must be linear between these thresholds. Delta tRDIFF Differential Input Voltage (i.e. CK_t - CK_c, DQS_t - DQS_c) VIHDIFFmin 0 VILDIFFmax Delta tFDIFF Figure. Differential Input Slew Rate Definition for CK_t, CK_c and DQS_t, DQS_c Rev 1.1 / Nov. 2014 88 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) AC and DC Logic Output Levels Single Ended AC and DC Output Levels Parameter DC Output Logic High Level (for IV curve linearity) DC Output Logic Low Level (for IV curve linearity) AC Output Logic High Level (for output slew rate) AC Output Logic Low Level (for output slew rate) Output Leakage current For DQ, DM, DQS_t and DQS_c (DQ, DQS_t and DQS_c are disabled; 0V  VOUT  VDDQ) Delta RON between pull-up and pull-down for DQ and DM Note: 1. IOH = -0.1mA, 2. IOL = 0.1mA Symbol VOH(DC) VOL(DC) VOH(AC) VOL(AC) LPDDR2 200 to 1066 Min Max 0.9 x VDDQ - - 0.1 x VDDQ VREF+0.12 - - VREF-0.12 Unit V V V V Note 1 2 IOZ -5 5 uA MMPUPD -15 15 % Differential AC and DC Output Levels (DQS_t, DQS_c) Parameter Symbol AC Differential Output High Level (for Output SR) VOHDIFF(AC) AC Differential Output Low Level (for Output SR) VOLDIFF(AC) Note: 1. IOH = -0.1mA, 2. IOL = 0.1mA LPDDR2 200 to 1066 + 0.20 x VDDQ - 0.20 x VDDQ Unit V V Note Single Ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and mea- sured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure. Parameter Single Ended Output Slew Rate for Rising Edge Single Ended Output Slew Rate for Falling Edge Measured From To VOL(AC) VOH(AC) VOH(AC) VOL(AC) Defined by [VOH(AC) - VOL(AC)] / Delta tRSE [VOH(AC) - VOL(AC)] / Delta tFSE Note: Output slew rate is verified by design and characterization and may not be subject to production test. Delta tRSE Single Ended Output Voltage (i.e. DQ) VOH(AC) VREF VOL(AC) Delta tFSE Figure. Single Ended Output Slew Rate Definition Rev 1.1 / Nov. 2014 89 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Output Slew Rate (Single Ended) Parameter Symbol Single-ended Output Slew Rate (RON = 40 +/- 30%) Single-ended Output Slew Rate (RON = 60 +/- 30%) Output slew-rate matching Ratio (Pull-up to Pull-down) SRQse SRQse LPDDR2 200 to 1066 Min Max 1.5 3.5 1.0 2.5 0.7 1.4 Unit Note V/ns V/ns Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals Note: 1. Measured with output reference load. 2. The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 3. The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC). 4. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of DQ signals per data byte driving logic-low. Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLDIFF(AC) and VOHDIFF(AC) for differential signals as shown in below Table and Figure. Parameter Differential Output Slew Rate for Rising Edge Differential Output Slew Rate for Falling Edge Measured From To VOLDIFF(AC) VOHDIFF(AC) VOHDIFF(AC) VOLDIFF(AC) Defined by [VOHDIFF(AC) - VOLDIFF(AC)] / Delta tRDIFF [VOHDIFF(AC) - VOLDIFF(AC)] / Delta tFDIFF Note: 1. Output slew rate is verified by design and characterization, and may not be subject to production test. Delta tRDIFF Differential Output Voltage (i.e. DQS_t - DQS_c) VOHDIFF(AC) 0 VOLDIFF(AC) Delta tFDIFF Figure. Differential Output Slew Rate Definition Rev 1.1 / Nov. 2014 90 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Output Slew Rate (Differential) Parameter Differential Output Slew Rate (RON = 40 +/- 30%) Differential Output Slew Rate (RON = 60 +/- 30%) Symbol SRQdiff SRQdiff LPDDR2 200 to 1066 Min Max 3.0 7.0 2.0 5.0 Unit Note V/ns V/ns Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals Note: 1. Measured with output reference load. 2. The output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC). 3. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte driving logic-high and 1/2 of DQ signals per data byte driving logic-low. Overshoot and Undershoot Specifications Parameter 1066 933 800 667 533 400 333 266 200 Units CA0-9, CS_n, CKE, CK_t, CK_c, DQ, DQS_t, DQS_c, DM Maximum peak amplitude allowed for overshoot 0.35 V Maximum peak amplitude allowed for undershoot 0.35 V Maximum overshoot area above VDDCA or VDDQ 0.15 0.17 0.20 0.24 0.30 0.40 0.48 0.60 0.80 V-ns Maximum undershoot area below VSSCA or VSSQ 0.15 0.17 0.20 0.24 0.30 0.40 0.48 0.60 0.80 V-ns Maximum Amplitude Volts (V) VDDCA or VDDQ VSSCA or VSSQ Time (ns) Figure. Overshoot and Undershoot Definition Overshoot Area Undershoot Area Rev 1.1 / Nov. 2014 91 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Output Buffer Characteristics HSUL_12 Driver Output Timing Reference Load These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VREF LPDDR2 SDRAM Output 0.5 x VDDQ RTT = 50  VTT = 0.5 x VDDQ Cload = 5pF Note: 1. All output timing parameter values (like tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc.) are reported with respect to this reference load. This reference load is also used to report slew rate. Figure. HSUL_12 Driver Output Reference Load for Timing and Slew Rate RONPU and RONPD Resistor Definition Note 1: This is under the condition that RONPD is turned off Note 1: This is under the condition that RONPU is turned off Chip in Drive Mode Output Driver To other circuitry like RCV, ... IPU RONPU RONPD IPD VDDQ IOut DQ VOut VSSQ Figure. Output Driver: Definition of Voltages and Currents Rev 1.1 / Nov. 2014 92 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) RONPU and RONPD Characteristics with ZQ Calibration Output driver impedance RON is defined by the value of the external reference resistor RZQ. Nominal RZQ is 240. Table - Output Driver DC Electrical Characteristics with ZQ Calibration RONNOM Resistor Vout Min Typ Max Unit Notes 34.3 RON34PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1,2,3,4 RON34PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/7 1,2,3,4 40.0 RON40PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1,2,3,4 RON40PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/6 1,2,3,4 48.0 RON48PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1,2,3,4 RON48PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/5 1,2,3,4 60.0 RON60PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1,2,3,4 RON60PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/4 1,2,3,4 80.0 RON80PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1,2,3,4 RON80PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/3 1,2,3,4 120.0 RON120PD 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1,2,3,4 RON120PU 0.5 x VDDQ 0.85 1.00 1.15 RZQ/2 1,2,3,4 Mismatch between pull-up and pull-down MMPUPD -15.00 +15.00 % 1,2,3,4,5 Note: 1. Across entire operating temperature range, after calibration. 2. RZQ = 240. 3. The tolerance limits are specified after calibration with fixed voltage and temperature. For behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 4. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. 5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD: Measure RONPU and RONPD, both at 0.5 x VDDQ: For example, with MMPUPD(max) = 15% and RONPD = 0.85, RONPU must be less than 1.0. Rev 1.1 / Nov. 2014 93 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to the Tables shown below. Table. Output Driver Sensitivity Definition Resistor Vout Min Max Unit Notes RONPD RONPU 0.5 x VDDQ 5 – dRONdT  T  – dRONdV  V 115 + dRONdT  T  + dRONdV  V % 1,2 Note 1. (T = T – T@ calibration), V = V – V(@ calibration) 2. dRONdT and dRONdV are not subject to production test but are verified by design and characterization. Table. Output Driver Temperature and Voltage Sensitivity Symbol Parameter Min Max Unit Notes dRONdT RON Temperature Sensitivity 0.00 0.75 %/C dRONdV RON Voltage Sensitivity 0.00 0.20 % / mV RONPU and RONPD Characteristics without ZQ Calibration Output driver impedance RON is defined by design and characterization as default setting. Table. Output Driver DC Electrical Characteristics without ZQ Calibration RONNOM Resistor Vout Min Nom Max Unit 34.3 RON34PD 0.5 x VDDQ 24 34.3 44.6  RON34PU 0.5 x VDDQ 24 34.3 44.6  40.0 RON40PD 0.5 x VDDQ 28 40 52  RON40PU 0.5 x VDDQ 28 40 52  48.0 RON48PD 0.5 x VDDQ 33.6 48 62.4  RON48PU 0.5 x VDDQ 33.6 48 62.4  60.0 RON60PD 0.5 x VDDQ 42 60 78  RON60PU 0.5 x VDDQ 42 60 78  80.0 RON80PD 0.5 x VDDQ 56 80 104  RON80PU 0.5 x VDDQ 56 80 104  120.0 RON120PD 0.5 x VDDQ 84 120 156  RON120PU 0.5 x VDDQ 84 120 156  Note: 1. Across entire operating temperature range, without calibration. Notes 1 1 1 1 1 1 1 1 1 1 1 1 Rev 1.1 / Nov. 2014 94 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) RZQ I-V Curve Voltage(V) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 Table. RZQ I-V Curve RON = 240(RZQ) Pull-Down Pull-Up Current [mA] / RON [] Current [mA] / RON [] default value after ZQReset Min Max with Calibration Min Max default value after ZQReset Min Max with Calibration Min Max [mA] [mA] [mA] [mA] [mA] [mA] [mA] [mA] 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.19 0.32 0.21 0.26 -0.19 -0.32 -0.21 -0.26 0.38 0.64 0.40 0.53 -0.38 -0.64 -0.40 -0.53 0.56 0.94 0.60 0.78 -0.56 -0.94 -0.60 -0.78 0.74 1.26 0.79 1.04 -0.74 -1.26 -0.79 -1.04 0.92 1.57 0.98 1.29 -0.92 -1.57 -0.98 -1.29 1.08 1.86 1.17 1.53 -1.08 -1.86 -1.17 -1.53 1.25 2.17 1.35 1.79 -1.25 -2.17 -1.35 -1.79 1.40 2.46 1.52 2.03 -1.40 -2.46 -1.52 -2.03 1.54 2.74 1.69 2.26 -1.54 -2.74 -1.69 -2.26 1.68 3.02 1.86 2.49 -1.68 -3.02 -1.86 -2.49 1.81 3.30 2.02 2.72 -1.81 -3.30 -2.02 -2.72 1.92 3.57 2.17 2.94 -1.92 -3.57 -2.17 -2.94 2.02 3.83 2.32 3.15 -2.02 -3.83 -2.32 -3.15 2.11 4.08 2.46 3.36 -2.11 -4.08 -2.46 -3.36 2.19 4.31 2.58 3.55 -2.19 -4.31 -2.58 -3.55 2.25 4.54 2.74 3.74 -2.25 -4.54 -2.74 -3.74 2.30 4.74 2.81 3.91 -2.30 -4.74 -2.81 -3.91 2.34 4.92 2.89 4.05 -2.34 -4.92 -2.89 -4.05 2.37 5.08 2.97 4.23 -2.37 -5.08 -2.97 -4.23 2.41 5.20 3.04 4.33 -2.41 -5.20 -3.04 -4.33 2.43 5.31 3.09 4.44 -2.43 -5.31 -3.09 -4.44 2.46 5.41 3.14 4.52 -2.46 -5.41 -3.14 -4.52 2.48 5.48 3.19 4.59 -2.48 -5.48 -3.19 -4.59 2.50 5.55 3.23 4.65 -2.50 -5.55 -3.23 -4.65 Rev 1.1 / Nov. 2014 95 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) 6 PDIn-Fab Min PDIn-Fab Max 4 PUIn-Fab Min PUIn-Fab Max 2 0 -2 -4 mA -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Voltage Figure 1 — RON = 240 Ohms IV Curve after ZQReset 6 PDCal Min PDCal Max 4 PUCal Min PUCal Max 2 0 -2 -4 mA -6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 Voltage Figure 2 — RON = 240 Ohms IV Curve after calibration Rev 1.1 / Nov. 2014 96 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Input/Output Capacitance Die Only1 1066-466 400-200 Parameter Symbol Min Max Min Max Unit Input capacitance, CK_t and CK_c CCK 1.0 2.0 1.0 2.0 pF Input capacitance delta, CK_t and CK_c CDCK 0 0.2 0 0.25 pF Input capacitance, all other input-only pins CI 1.0 2.0 1.0 2.0 pF Input capacitance delta, all other input-only pins CDI -0.40 0.40 -0.50 0.50 pF Input/output capacitance, DQ, DM, DQS_t, DQS_c CIO 1.25 2.5 1.25 2.5 pF Input/output capacitance delta, DQS_t and DQS_c CDDQS 0 0.25 0 0.30 pF Input/output capacitance delta, DQ and DM CDIO -0.5 0.5 -0.6 0.6 pF Input/Output Capacitance ZQ CZQ 0 2.5 0 2.5 pF (TOPER; VDDQ = 1.14-1.3V; VDDCA = 1.14-1.3V; VDD1 = 1.7-1.95V, VDD2 = 1.14-1.3V) Note: 1. This parameter applies to die device only (does not include package capacitance). 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147 (Procedure for measuring input capacitance using a vector network analyzer (VNA) with VDD1, VDD2, VDDQ, VSS, VSSCA, VSSQ applied and all other pins floating). 3. Absolute value of CCK_t - CCK_c. 4. CI applies to CS_n, CKE, CA0-CA9. 5. CDI = CI - 0.5 * (CCK_t + CCK_c) 6. DM loading matches DQ and DQS. 7. MR3 I/O configuration DS OP3-OP0 = 0001B (34.3 Ohm typical) 8. Absolute value of CDQS_t and CDQS_c. 9. CDIO = CIO - 0.5 * (CDQS_t + CDQS_c) in byte-lane. 10. Maximum external load capacitance on ZQ pin, including packaging, board, pin, resistor, and other LPDDR2 devices: 5pF. Rev 1.1 / Nov. 2014 97 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) IDD Specification Parameters and Test Conditions IDD Measurement Conditions The following definitions are used within the IDD measurement tables: LOW: VIN VIL(DC) MAX; HIGH: VIN  VIH(DC) MIN; STABLE: Inputs are stable at a HIGH or LOW level; SWITCHING: See tables below. Table. Definition of Switching for CA Input Signals Switching for CA CK_t (RISING) / CK_c (FALLING) CK_t (FALLING) / CK_c (RISING) CK_t (RISING) / CK_c (FALLING) CK_t (FALLING) / CK_c (RISING) CK_t (RISING) / CK_c (FALLING) CK_t (FALLING) / CK_c (RISING) CK_t (RISING) / CK_c (FALLING) CK_t (FALLING) / CK_c (RISING) Cycle N N+1 N+2 N+3 CS_n HIGH HIGH HIGH HIGH CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA6 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA7 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA8 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA9 HIGH HIGH HIGH LOW LOW LOW LOW HIGH Note: 1. CS_n must always be driven HIGH. 2. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus. 3. The above pattern (N, N+1, N+2, N+3...) is used continuously during IDD measurement for IDD values that require SWITCHING on the CA bus. Rev 1.1 / Nov. 2014 98 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Table. Definition of Switching for IDD4R Clock CKE CS_n Clock Cycle Number Command CA0 - CA2 Rising Falling HIGH HIGH LOW LOW Read_Rising HLH N Read_Falling LLL Rising Falling Rising Falling HIGH HIGH HIGH HIGH HIGH HIGH LOW LOW LLL N+1 NOP HLH Read_Rising HLH N+2 Read_Falling LLL Rising HIGH HIGH N+3 Falling HIGH HIGH NOP LLL HLH Note: 1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle. 2. The above pattern (N, N+1, ...) is used continuously during IDD measurement for IDD4R. CA3 - CA9 LHLHLHL LLLLLLL LLLLLLL HLHLLHL HLHLLHL HHHHHHH HHHHHHH LHLHLHL All DQs L L H L H H H L Table. Definition of Switching for IDD4W Clock CKE CS_n Clock Cycle Number Command CA0 - CA2 Rising Falling HIGH HIGH LOW LOW Write_Rising HLL N Write_Falling LLL Rising HIGH HIGH LLL N+1 NOP Falling HIGH HIGH HLH Rising Falling HIGH HIGH LOW LOW Write_Rising HLL N+2 Write_Falling LLL Rising HIGH HIGH LLL N+3 NOP Falling HIGH HIGH HLH Note: 1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle. 2. Data masking (DM) must always be driven LOW. 3. The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4W. CA3 - CA9 LHLHLHL LLLLLLL LLLLLLL HLHLLHL HLHLLHL HHHHHHH HHHHHHH LHLHLHL All DQs L L H L H H H L Rev 1.1 / Nov. 2014 99 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) DC Parameters and Operating Conditions (for x32 devices - sheet 1 of 2) - All IDD values are single-die-equivalent values. Total current consumption is dependent on user operating condition. Parameter Test Condition Symbol Power Supply Max DDR 1066 Unit Note Operating one bank active-precharge current tCK = tCK(min); tRC = tRC(min); CKE is HIGH; CS_n is HIGH between valid commands; CA bus inputs are SWITCHING; Data bus inputs are STABLE IDD01 IDD02 IDD0IN VDD1 VDD2 VDDCA VDDQ 8 30 5 mA 3 mA 3 mA 3, 4 tCK = tCK(min); CKE is LOW; CS_n is HIGH; all IDD2P1 VDD1 1 Idle power-down standby current banks idle; CA bus inputs are SWITCHING; IDD2P2 VDD2 2 Data bus inputs are STABLE IDD2PIN VDDCA VDDQ 0.1 mA 3 mA 3 mA 3, 4 CK_t = LOW; CK_c = HIGH; Idle power-down CKE is LOW; standby current with CS_n is HIGH; all banks idle; clock stop CA bus inputs are STABLE; Data bus inputs are STABLE IDD2PS1 VDD1 1 IDD2PS2 VDD2 2 IDD2PSIN VDDCA VDDQ 0.1 mA 3 mA 3 mA 3, 4 tCK = tCK(min); CKE is HIGH; CS_n is HIGH, all IDD2N1 VDD1 2 Idle non power-down banks idle; standby current CA bus inputs are SWITCHING; IDD2N2 VDD2 4 Data bus inputs are STABLE IDD2NIN VDDCA VDDQ 5 mA 3 mA 3 mA 3, 4 CK_t = LOW; CK_c = HIGH; Idle non power-down CKE is HIGH; standby current CS_n is HIGH; all banks idle; with clock stop CA bus inputs are STABLE; Data bus inputs are STABLE IDD2NS1 VDD1 2 IDD2NS2 VDD2 3 IDD2NSIN VDDCA VDDQ 5 mA 3 mA 3 mA 3, 4 tCK = tCK(min); CKE is LOW; CS_n is HIGH; one IDD3P1 VDD1 2 Active power-down bank active; standby current CA bus inputs are SWITCHING; IDD3P2 VDD2 6 Data bus inputs are STABLE IDD3PIN VDDCA VDDQ 0.1 mA 3 mA 3 mA 3, 4 Active power-down standby current with clock stop CK_t = LOW; CK_c = HIGH; CKE is LOW; CS_n is HIGH; one bank active; CA bus inputs are STABLE; Data bus inputs are STABLE IDD3PS1 IDD3PS2 IDD3PSIN VDD1 VDD2 VDDCA VDDQ 2 6 0.1 mA 3 mA 3 mA 3, 4 Active non powerdown standby current tCK = tCK(min); CKE is HIGH; CS_n is HIGH; one bank active; CA bus inputs are SWITCHING; Data bus inputs are STABLE IDD3N1 IDD3N2 IDD3NIN VDD1 VDD2 VDDCA VDDQ 2 7 5 mA 3 mA 3 mA 3, 4 Rev 1.1 / Nov. 2014 100 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) DC Parameters and Operating Conditions (for x32 devices - sheet 2 of 2) - All IDD values are single-die-equivalent values. Total current consumption is dependent on user operating condition. Parameter Test Condition Symbol Power Supply Max DDR 1066 Unit Note Active non powerdown standby current with clock stop CK_t=LOW; CK_c=HIGH; CKE is HIGH CS_n is HIGH One bank active; CA bus inputs are STABLE; Data bus inputs are STABLE IDD3NS1 VDD1 2 IDD3NS2 VDD2 7 IDD3NSIN VDDCA VDDQ 5 mA 3 mA 3 mA 3, 4 IDD4R1 VDD1 2 tCK = tCK(min); CS_n is HIGH between valid comOperating burst read mands; one bank active; BL=4; RL=RLmin; IDD4R2 VDD2 140 current CA bus inputs are SWITCHING, 50% data change each burst transfer IDD4RIN VDDCA 5 IDD4RQ VDDQ 140 mA 3 mA 3 mA 3 mA 3, 6 tCK = tCK(min); CS_n is HIGH between valid com- IDD4W1 VDD1 2 Operating burst write mands; one bank active; BL=4; WL=WL(min); current CA bus inputs are SWITCHING; IDD4W2 VDD2 130 50% data change each burst transfer IDD4WIN VDDCA VDDQ 14 mA 3 mA 3 mA 3, 4 tCK=tCK(min); CS_n is HIGH between valid com- IDD51 VDD1 35 All Bank Auto Refresh mands; tRC=tRFCab(min); Burst refresh; Burst Current CA bus inputs are SWITCHING; Data bus inputs are STABLE IDD52 VDD2 130 IDD5IN VDDCA VDDQ 5 mA 3 mA 3 mA 3, 4 tCK=tCK(min); CKE is HIGH between valid com- IDD5ab1 VDD1 3 All Bank Auto Refresh mands; tRC=tREFI; Average Current CA bus inputs are SWITCHING; Data bus inputs are STABLE IDD5ab2 VDD2 9 IDD5abIN VDDCA VDDQ 5 mA 4 mA 4 mA 3, 4 Per Bank Auto Refresh Average Current tCK=tCK(min); CKE is HIGH between valid commands; tRC=tREFI/8; CA bus inputs are SWITCHING; Data bus inputs are STABLE IDD5pb1 VDD1 IDD5pb2 IDD5pbIN VDD2 VDDCA VDDQ 3 9 5 mA 1, 3 mA 1, 3 mA 1,3,4 Self Refresh Current (Standard Temperature Range -30’C ~ 85’C) CK_t=LOW; CK_c=HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE; Maximum 1 x Self-refresh rate IDD61 VDD1 1.6 IDD62 VDD2 5.5 IDD6IN VDDCA VDDQ 0.1 mA 2,3,8 mA 2,3,8 mA 2,3, 4,8 Self Refresh Current (Extended Temperature Range: 85’C ~ 105’C) CK_t=LOW; CK_c=HIGH; CKE is LOW; CA bus inputs are STABLE; Data bus inputs are STABLE IDD6ET1 VDD1 2.2 IDD6ET2 VDD2 9 IDD6ETIN VDDCA VDDQ 0.1 mA 2,3,8 mA 2,3,8 mA 2,3, 4,8 Rev 1.1 / Nov. 2014 101 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Note: 1. Per Bank Refresh only applicable for LPDDR2-S4 devices of 1Gb or higher densities. 2. This is the general definition that applies to full array Self Refresh. Refer to IDD6 Partial Array Self-Refresh Current on next table. 3. IDD values published are the maximum of the distribution of the arithmetic mean at 85oC. 4. Measured currents are the summation of VDDQ and VDDCA. 5. To calculate total current consumption, the currents of all active operations must be considered. 6. Guaranteed by design with output load of 5pF and RON = 40Ohm. 7. IDD current specifications are tested after the device is properly initialized. 8. 1 x Self-refresh rate is the rate at which the LPDDR2-S4 device is refreshed internally during Self-refresh before going into the Extended temperature range. IDD6 Partial Array Self Refresh Current Temp. (oC) 25 85 105 Memory Array 8 Banks 4 Banks 2 Banks 1 Bank 0.34 / 0.31 / 0.10 0.32 / 0.22 / 0.10 0.31 / 0.18 / 0.10 0.30 / 0.17 / 0.10 1.60 / 5.50 / 0.10 1.20 / 4.10 / 0.10 1.00 / 3.40 / 0.10 0.90 / 3.00 / 0.10 2.20 / 9.00 / 0.10 TBD TBD TBD Unit mA mA mA Note: 1. Related numerical values in this 25oC and 105oC are examples for reference sample value only. 2. With a on-chip temperature sensor, auto temperature compensated self refresh will automatically adjust the interval of self-refresh operation according to case temperature variations. 3. LPDDR2-S4 SDRAM uses the same IDD6 current value categorization as LPDDR2-S2 SDRAM. Some LPDDR2-S4 SDRAM densities support both bank masking and segment masking. The IDD6 currents are measured using bank-masking only. 4. IDD values published are the maximum of the distribution of the arithmethic mean. Rev 1.1 / Nov. 2014 102 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) AC TIMING PARAMETERS (Sheet 1 of 4) Parameter Symbol min DDR2 1066 DDR2 800 DDR2 667 DDR2 533 DDR2 400 tCK min max min max min max min max min max Unit Note Clock Timing Average Clock Period tCK(avg) 1.875 100 2.5 100 3 100 3.75 100 5 100 ns Average high pulse width tCH(avg) 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) Average low pulse width tCL(avg) 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK(avg) Absolute Clock Period tCK(abs) min{tCK(avg),min + tJIT(per),min} ps Absolute clock HIGH pulse width tCH(abs), (with allowed jitter) allowed 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 tCK(avg) Absolute clock LOW pulse width (with allowed jitter) tCL(abs), allowed 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 tCK(avg) Clock Period Jitter (with allowed jit- tJIT(per), ter) allowed -90 90 -100 100 -110 110 -120 120 -140 140 ps Maximum Clock Jitter between consecutive clock cycles (with allowed jitter) two tJIT(cc), allowed - 180 - 200 - 220 - 240 - 280 ps Duty cycle Jitter (with allowed jitter) tJIT(duty), allowed min{ min((tCH(abs),min - tCH(avg),min), (tCH(abs),min - tCH(avg),min)) * tCK(avg) } min{ -0.02 * tCK(avg) } max{ max((tCH(abs),max - tCH(avg),max), (tCH(abs),max - ps tCH(avg),max)) * tCK(avg) } max{ 0.02 * tCK(avg) } Cumulative error across 2 cycles tERR(2per), allowed -132 132 -147 147 -162 162 -177 177 -206 206 ps Cumulative error across 3 cycles tERR(3per), allowed -157 157 -175 175 -192 192 -210 210 -245 245 ps Cumulative error across 4 cycles tERR(4per), allowed -175 175 -194 194 -214 214 -233 233 -272 272 ps Cumulative error across 5 cycles tERR(5per), allowed -188 188 -209 209 -230 230 -251 251 -293 293 ps Cumulative error across 6 cycles tERR(6per), allowed -200 200 -222 222 -244 244 -266 266 -311 311 ps Cumulative error across 7 cycles tERR(7per), allowed -209 209 -232 232 -256 256 -279 279 -325 325 ps Cumulative error across 8 cycles tERR(8per), allowed -217 217 -241 241 -266 266 -290 290 -338 338 ps Cumulative error across 9 cycles tERR(9per), allowed -224 224 -249 249 -274 274 -299 299 -349 349 ps Cumulative error across 10 cycles tERR(10per), allowed -231 231 -257 257 -282 282 -308 308 -359 359 ps Cumulative error across 11 cycles tERR(11per), allowed -237 237 -263 263 -289 289 -316 316 -368 368 ps Cumulative error across 12 cycles tERR(12per), allowed -242 242 -269 269 -296 296 -323 323 -377 377 ps Cumulative error across n cycles tERR(nper), (n = 13, 14 . . . 49, 50) allowed min{tERR(nper),allowed,min = (1 + 0.68ln(n)) * tJIT(per),allowed,min } max{ tERR(nper),allowed,max = (1 + 0.68ln(n)) * ps tJIT(per),allowed,max } Rev 1.1 / Nov. 2014 103 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) AC TIMING PARAMETERS (Sheet 2 of 4) Parameter Symbol Initialization Calibration Time Long Calibration Time Short Calibration Time Calibration Reset Time tZQINIT tZQCL tZQCS tZQRESET DQS CK# output access time from CK/ tDQSCK DQSCK Delta short tDQSCKDS DQSCK Delta Medium tDQSCKDM DQSCK Delta Long tDQSCKDL DQS-DQ skew tDQSQ Data hold skew factor tQHS DQ/DQS output hold time from DQS tQH Data Half Period tQHP DQS Output High Pulse Width tQSH DQS Output Low Pulse Width tQSL Read preamble tRPRE Read postamble tRPST DQS low-Z from clock tLZ(DQS) DQ low-Z from clock tLZ(DQ) DQS high-Z from clock tHZ(DQS) DQ high-Z from clock tHZ(DQ) DQ and DM input setup time (VREF based) tDS DQ and based) DM input hold time(VREF tDH DQ and DM input pulse width tDIPW Write command transition to 1st DQS latching tDQSS DQS input high-level width tDQSH DQS input low-level width tDQSL DQS falling edge to CK setup time tDSS DQS falling edge hold time from CK tDSH Write postamble tWPST Write preamble tWPRE CKE min. pulse pulse width) width (high/low tCKE CKE input setup time tISCKE CKE input hold time tIHCKE Address and control time (Vref based) input setup tIS Address and (Vref based) control input hold time tIH Address width and control input pulse tIPW min DDR2 1066 DDR2 800 DDR2 667 DDR2 533 DDR2 400 tCK min max min max min max min max min max ZQ Calibration Parameters 1 1 1 1 1 6 360 360 360 360 360 6 90 90 90 90 90 3 50 50 50 50 50 Read Parameters Unit us ns ns ns Note 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 2.5 5.5 ns 330 450 540 670 680 900 1050 1350 920 1200 1400 1800 200 240 280 340 230 280 340 400 min{ tQHP-tQHS } min(tQSH, tQSL) min{ tCH(abs) - 0.05 } min{ tCL(abs) - 0.05 } 0.9 0.9 0.9 0.9 0.9 min{ tCL(abs)-0.05 } min{tDQSCK(min) - 300} min{tDQSCK(min) - (1.4 x tQHSmax)} max{tDQSCK(max) - 100} max{tDQSCK(max) + (1.4 x tDQSQmax)} Write Parameters 900 ps 14 1800 ps 15 2400 ps 16 400 ps 480 ps ps tCK(avg) tCK(avg) tCK(avg) tCK(avg) 11,12 tCK(avg) 11,13 ps 11 ps 11 ps 11 ps 11 210 270 350 430 480 ps 210 270 350 430 480 ps 0.35 0.35 0.35 0.35 0.35 tCK(avg) 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK(avg) 0.4 0.4 0.4 0.4 0.4 tCK(avg) 0.4 0.4 0.4 0.4 0.4 tCK(avg) 0.2 0.2 0.2 0.2 0.2 tCK(avg) 0.2 0.2 0.2 0.2 0.2 tCK(avg) 0.4 0.4 0.4 0.4 0.4 tCK(avg) 0.35 0.35 0.35 0.35 0.35 tCK(avg) CKE Input Parameters 33 3 3 3 3 tCK(avg) 0.25 0.25 0.25 0.25 0.25 tCK(avg) 2 0.25 0.25 0.25 0.25 0.25 tCK(avg) 3 Command Address Input Parameters 220 290 370 460 600 ps 1,10 220 290 370 460 600 ps 1,10 0.40 0.40 0.40 0.40 0.40 tCK(avg) Rev 1.1 / Nov. 2014 104 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) AC TIMING PARAMETERS (Sheet 3 of 4) Parameter Symbol min DDR2 1066 tCK min max DDR2 800 min max DDR2 667 min max DDR2 533 min max DDR2 400 min max Unit Note Boot Parameters (10MHz-55MHz) Clock Cycle Time tCKb 18 100 18 100 18 100 18 100 18 100 ns 4,6,7 CKE Input Setup Time tISCKEb 2.5 2.5 2.5 2.5 2.5 ns 4,6,7 CKE Input Hold Time tIHCKEb 2.5 2.5 2.5 2.5 2.5 ns 4,6,7 Address & Control Input Setup Time tISb 1150 1150 1150 1150 1150 ps 4,6,7 Address & Control Input Hold Time tIHb 1150 1150 1150 1150 1150 ps 4,6,7 DQS Output CK/CK# Data Access Time from tDQSCKb 2.0 10.0 2.0 10.0 2.0 10.0 2.0 10.0 2.0 10.0 ns 4,6,7 Data Edge Strobe Edge tDQSQb to Output Data tDQSQb 1.2 1.2 1.2 1.2 1.2 ns 4,6,7 Data Hold Skew Factor tQHSb 1.2 1.2 1.2 1.2 1.2 ns 4,6,7 Mode Register Parameters MODE period REGISTER Write command tMRW 55 5 5 5 5 tCK(avg) MODE period REGISTER Read command tMRR 22 2 2 2 2 tCK(avg) Core Parameters Read Latency RL 38 6 5 4 3 tCK(avg) Write Latency WL 14 3 2 2 1 tCK(avg) ACTIVE to ACTIVE command period tRC min{tRAS+tRPab(all-bank)} min{tRAS+tRPpb(per-bank)} ns CKE min. pulse width during Self- Refresh (low pulse width during Self-Re- tCKESR 3 15 15 15 15 15 ns fresh) Self refresh mand delay exit to next valid com- tXSR tRF2 Cab +10 tRFCab +10 tRFCab +10 tRFCab +10 tRFCab +10 ns Exit power down mand delay to next valid com- tXP 2 7.5 7.5 7.5 7.5 7.5 ns LPDDR2-S4 CAS to CAS delay tCCD 22 2 2 2 2 tCK(avg) Internal Read mand delay to Precharge com- tRTP 2 7.5 7.5 7.5 7.5 7.5 ns RAS to CAS Delay tRCD 3 18 18 18 18 18 ns Row Precharge Time (single bank) tRPpb 3 18 18 18 18 18 ns Row Precharge bank Time (all banks) - 4- tRPab 3 18 18 18 18 18 ns Row Precharge bank Time (all banks) - 8- tRPab 3 21 21 21 21 21 ns Row Active Time tRAS 42 70,00 0 42 70,00 0 42 70,00 0 42 70,00 0 42 70,00 0 ns Write Recovery Time tWR 3 15 15 15 15 15 ns Internal Delay Write to Read Command tWTR 2 7.5 7.5 7.5 7.5 10 ns Active bank A to Active bank B tRRD 2 10 10 10 10 10 ns Four Bank Activate Window tFAW 8 50 50 50 50 50 ns Minimum Deep Power Down Time tDPD 500 500 500 500 500 us Rev 1.1 / Nov. 2014 105 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) AC TIMING PARAMETERS (Sheet 4 of 4) Parameter tDQSCK De-Rating Core Timings Temperature De-Rating Symbol tDQSCK (Derated) tRCD (Derated) tRC (Derated) tRAS (Derated) tRP (Derated) tRRD (Derated) min DDR2 1066 DDR2 800 DDR2 667 DDR2 533 tCK min max min max min max min max Temperature De-Rating 5620 6000 6000 6000 min{tRCD + 1.875} min{tRC + 1.875} min{tRAS + 1.875} min{tRP + 1.875} min{tRRD + 1.875} DDR2 400 min max 6000 Unit ps ns ns ns ns ns Note 17 Note: 1. Input set-up/hold time for signal(CA0 ~ 9, CS_n) 2. CKE input setup time is measured from CKE reaching high/low voltage level to CK_t/CK_c crossing. 3. CKE input hold time is measured from CK_t/CK_c crossing to CKE reaching high/low voltage level. 4. To guarantee device operation before the LPDDR2 device is configured a number of AC boot timing parameters are defined in the Table. Boot parameter symbols have the letter b appended, e.g. tCK during boot is tCKb. 5. Frequency values are for reference only. Clock cycle time (tCK or tCKb) shall be used to determine device capabilities. 6. The SDRAM will set some Mode register default values upon receiving a RESET (MRW) command as specified in "Mode Register Definition". 7. The output skew parameters are measured with Ron default settings into the reference load. 8. The min tCK column applies only when tCK is greater than 6ns for LPDDR2-S4 devices. In this case, both min tCK values and analog timings (ns) shall be satisfied. 9. All AC timings assume an input slew rate of 1V/ns. 10. Read, Write, and Input Setup and Hold values are referenced to VREF. 11. For low-to-high and high-to-low transitions, the timing reference will be at the point when the signal crosses VTT. tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ)). Figure below shows a method to calculate the point when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. Rev 1.1 / Nov. 2014 106 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) VTT + 2x Y mV VTT + Y mV VOH tLZ(DQS), tLZ(DQ) X 2x X VOH - X mV VOH - 2x X mV VTT actual waveform VTT - Y mV VTT - 2x Y mV Y 2x Y tHZ(DQS), tHZ(DQ) VTT VOL + 2x X mV VOL + X mV T1 T2 VOL T1 T2 begin driving point = 2 x T1 - T2 stop driving point = 2 x T1 - T2 The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are determined from the differential signal DQS_t-DQS_c. Figure. HSUL_12 Driver Output Reference Load for Timing and Slew Rate 12. Measured from the start driving of DQS_t - DQS_c to the start driving the first rising strobe edge. 13. Measured from the from start driving the last falling strobe edge to the stop driving DQS_t - DQS_c. 14. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts within a 160ns rolling window. tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is <10C/s. Values do not include clock jitter. 15. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 1.6us rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is <10C/s. Values do not include clock jitter. 16. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (within a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is <10C/s. Values do not include clock jitter. 17. It is applied when Self Refresh Rate OP<2:0> = 110B in MR4. LPDDR2-S4 devices shall be de-rated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP and tRRD. tDQSCK shall be de-rated according to the tDQSCK derating in "AC timing table". Prevailing clock frequency spec and related setup and hold timings shall remain unchanged. Rev 1.1 / Nov. 2014 107 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Clock Specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the LPDDR2 device. Definition for tCK(avg) and nCK tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. Unit `tCK(avg)' represents the actual clock average tCK(avg) of the input clock under operation. Unit `nCK' represents one clock cycle of the input clock, counting the actual clock edges. tCK(avg) may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and timing specs are met Definition for tCK(abs) tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test. Definition for tCH(avg) and tCL(avg) tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. Rev 1.1 / Nov. 2014 108 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Definition for tJIT(per) Symbol tJIT(per) tJIT(per),act tJIT(per),allowed Definition The single period jitter defined as the largest deviation of any signal tCK from tCK(avg). tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}. The actual clock jitter for a given system. The specified allowed clock period jitter. Note: 1. tJIT(per) is not subject to production test. Definition for tJIT(cc) Symbol tJIT(cc) Definition Defined as the absolute difference in clock period between two consecutive clock cycles. tJIT(cc) = Max of |{tCKi +1 - tCKi}|. Defines the cycle to cycle jitter. Note: 1. tJIT(cc) is not subject to production test. Definition for tERR(nper) Symbol tERR(nper) tERR(nper),act tERR(nper),allowed Definition Defined as the cumulative error across n multiple consecutive cycles from tCK(avg). The actual clock jitter over n cycles for a given system. The specified allowed clock period jitter over n cycles. Note: 1. tERR(nper) is not subject to production test. tERR(nper) can be calculated by the formula shown below: tERR(nper),min can be calculated by the formula shown below: tERR(nper),max can be caculated by the formula shown below: Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value Rev 1.1 / Nov. 2014 109 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Definition for duty cycle jitter tJIT(duty) tJIT(duty) is defined with absolute and average specification of tCH / tCL. tJIT(duty),min can be caculated by the formula shown below: tJIT(duty),max can be caculated by the formula shown below: Definition for tCK(abs), tCH(abs) and tCL(abs) These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. Parameter Absolute Clock Period Absolute Clock HIGH Pulse Width Absolute Clock LOW Pulse Width Symbol tCK(abs) tCH(abs) tCL(abs) Note: 1. tCK(avg),min is expressed in ps for this table 2. tJIT(duty),min is a negative value Min tCK(avg),min + tJIT(per),min tCH(avg),min + tJIT(duty),min / tCK(avg)min tCL(avg),min + tJIT(duty),min / tCK(avg)min Unit ps tCK(avg) tCK(avg) Rev 1.1 / Nov. 2014 110 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Period Clock Jitter LPDDR2 devices can tolerate some clock period jitter without core timing parameter de-rating. This section describes device timing requirements in the presence of clock period jitter (tJIT(per)) in excess of the values found in “AC timing table” and how to determine cycle time de-rating and clock cycle de-rating. Clock period jitter effects on core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW ) Core timing parameters extend across multiple clock cycles. Period clock jitter will impact these parameters when measured in numbers of clock cycles. When the device is operated with clock jitter within the specification limits, the LPDDR2 device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}. When the device is operated with clock jitter outside specification limits, the number of clocks or tCK(avg) may need to be increased based on the values for each core timing parameter. Cycle time de-rating for core timing parameters For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed), the equation below calculates the amount of cycle time de-rating (in ns) required if the equation results in a positive value for a core timing parameter (tCORE). A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating required is the maximum of the cycle time de-ratings determined for each individual core timing parameter. Clock Cycle de-rating for core timing parameters For a given number of clocks (tnPARAM) for each core timing parameter, clock cycle de-rating should be specified with amount of period jitter (tJIT(per)). For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed), the equation below calculates the clock cycle derating (in clocks) required if the equation results in a positive value for a core timing parameter (tCORE). A clock cycle de-rating analysis should be conducted for each core timing parameter. Clock jitter effects on Command/Address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb, tIHCKEb) These parameters are measured from a command/address signal (CKE, CS, CA0 - CA9) transition edge to its respective clock signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values shall be met. Rev 1.1 / Nov. 2014 111 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Clock jitter effects on Read timing parameters tRPRE When the device is operated with input clock jitter, tRPRE needs to be de-rated by the actual period jitter (tJIT(per),act,max) of the input clock in excess of the allowed period jitter (tJIT(per),allowed,max). Output de-ratings are relative to the input clock. For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500 ps, tJIT(per),act,min = -172 ps and tJIT(per),act,max = + 193 ps, then, tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500= .8628 tCK(avg) tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) These parameters are measured from a specific clock edge to a data signal (DMn, DQm.: n=0,1,2,3. m=0-31) transition and will be met with respect to that clock edge. Therefore, they are not affected by the amount of clock jitter applied (i.e. tJIT(per). tQSH, tQSL These parameters are affected by duty cycle jitter which is represented by tCH(abs)min and tCL(abs)min. tQSH(abs)min = tCH(abs)min - 0.05 tQSL(abs)min = tCL(abs)min - 0.05 These parameters determine absolute Data-Valid window at the LPDDR2 device pin. Absolute min data-valid window @ LPDDR2 device pin = min { ( tQSH(abs)min * tCK(avg)min - tDQSQmax - tQHSmax ), ( tQSL(abs)min * tCK(avg)min - tDQSQmax - tQHSmax )} This minimum data-valid window shall be met at the target frequency regardless of clock jitter. tRPST tRPST is affected by duty cycle jitter which is represented by tCL(abs). Therefore tRPST(abs)min can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min Rev 1.1 / Nov. 2014 112 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Clock jitter effects on Write timing parameters tDS, tDH These parameters are measured from a data signal (DMn, DQm.: n=0,1,2,3. m=0 -31) transition edge to its respective data strobe signal (DQSn_t, DQSn_c : n=0,1,2,3) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/ address. Regardless of clock jitter values, these values shall be met. tDSS, tDSH These parameters are measured from a data strobe signal (DQSx_t, DQSx_c) crossing to its respective clock signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values shall be met. tDQSS This parameter is measured from a data strobe signal (DQSx_t, DQSx_c) crossing to the subsequent clock signal (CK_t/CK_c) crossing. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual period jitter tJIT(per),act of the input clock in excess of the allowed period jitter tJIT(per),allowed. tDQSS(min,derated) can be caculated by the formula shown below: tDQSS(max,derated) can be caculated by the formula shown below: For example, if the measured jitter into a LPDDR2-800 device has tCK(avg)= 2500 ps, tJIT(per),act,min= -172 ps and tJIT(per),act,max= + 193 ps, then tDQSS,(min,derated) = 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0.75 - (-172 + 100)/2500 = .7788 tCK(avg) and tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (193 - 100)/2500 = 1.2128 tCK(avg) Rev 1.1 / Nov. 2014 113 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) CA and CS_n Setup, Hold and Derating For all input signals (CA and CS_n) the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the tIS and tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded `VREF(DC) to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(DC) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between shaded `DC to VREF(DC) region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded `DC to VREF(DC) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/ IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in Table, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. Rev 1.1 / Nov. 2014 114 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Unit [ps] tIS(base) tIH(base) Table. CA and CS_n Setup and Hold Base-Values for 1V/ns LPDDR2 1066 933 800 667 533 466 Reference 0 30 70 150 240 300 VIH/L(AC)=VREF(DC)+/-220mV 90 120 160 240 330 390 VIH/L(DC)=VREF(DC)+/-130mV Unit [ps] 400 tIS(base) 300 tIH(base) 400 LPDDR2 333 266 440 600 540 700 Reference 200 850 VIH/L(AC)=VREF(DC)+/-300mV 950 VIH/L(DC)=VREF(DC)+/-200mV Note 1: AC/DC referenced for 1V/ns CA and CS_n slew rate and 2V/ns differential CK_t-CK_c slew rate. Table. Derating values LPDDR2 tIS/tIH - AC/DC based AC220 tIS, tIH derating in [ps] AC/DC based AC220 Threshold -> VIH(AC)=VREF(DC)+220mV, VIL(AC)=VREF(DC)-220mV DC130 Threshold -> VIH(DC)=VREF(DC)+130mV, VIL(DC)=VREF(DC)-130mV CK_t, CK_c Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH 2.0 110 65 110 65 110 65 1.5 74 43 73 43 73 43 89 59 1.0 0 0 0 0 0 0 16 16 32 32 CA, 0.9 CS_n Slew 0.8 rate V/ns 0.7 -3 -5 -3 -5 13 11 29 27 45 43 -8 -13 8 3 24 19 40 35 56 55 2 -6 18 10 34 26 50 46 66 78 0.6 10 -3 26 13 42 33 58 65 0.5 4 -4 20 16 36 48 0.4 -7 2 17 34 Note 1: Cell contents shaded in red are defined as ‘not supported’ Rev 1.1 / Nov. 2014 115 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Table. Derating values LPDDR2 tIS/tIH - AC/DC based AC300 tIS, tIH derating in [ps] AC/DC based AC300 Threshold -> VIH(AC)=VREF(DC)+300mV, VIL(AC)=VREF(DC)-300mV DC200 Threshold -> VIH(DC)=VREF(DC)+200mV, VIL(DC)=VREF(DC)-200mV CK_t, CK_c Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH 2.0 150 100 150 100 150 100 1.5 100 67 100 67 100 67 116 83 1.0 0 0 0 0 0 0 16 16 32 32 CA, CS_n 0.9 -4 -8 -4 -8 12 8 28 24 44 40 Slew 0.8 -12 -20 4 -4 20 12 36 28 52 48 rate V/ns 0.7 -3 -18 13 -2 29 14 45 34 61 66 0.6 2 -21 18 -5 34 15 50 47 0.5 -12 -32 4 -12 20 20 0.4 -35 -40 -11 -8 Note 1: Cell contents shaded in red are defined as ‘not supported’ Table. Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition Slew Rate [V/ns] > 2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 tVAC@ 300mV [ps] MIN MAX 75 - 57 - 50 - 38 - 34 - 29 - 22 - 13 - 0 - 0 - tVAC@220mV [ps] MIN MAX 175 - 170 - 167 - 163 - 162 - 161 - 159 - 155 - 150 - 150 - Rev 1.1 / Nov. 2014 116 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) CK_c CK_t VDDCA tIS tIH tIS tIH tVAC VIH(AC) min VIH(DC) min VREF to AC region VREF(DC) VIL(DC) max VIL(AC) max nominal slew rate nominal slew rate VREF to AC region VSSCA tVAC TF TR Setup Slew Rate Falling Signal = VREF(DC) - VIL(AC)max TF Setup Slew Rate Rising Signal = VIH(AC)min - VREF(DC) TR Figure. Illustration of nominal slew rate and tVAC for setup time tIS for CA and CS_n with respect to clock Rev 1.1 / Nov. 2014 117 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) CK_c CK_t VDDCA tIS tIH VIH(AC) min VIH(DC) min DC to VREF region VREF(DC) nominal slew rate VIL(DC) max VIL(AC) max tIS tIH nominal slew rate DC to VREF region VSSCA TR TF Hold Slew Rate Rising Signal = VREF(DC) - VIL(DC)max TR Hold Slew Rate Falling Signal = VIH(DC)min - VREF(DC) TF Figure. Illustration of nominal slew rate for hold time tIH for CA and CS_n with respect to clock Rev 1.1 / Nov. 2014 118 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) CK_c CK_t VDDCA tIS tIH VIH(AC) min VREF to AC region VIH(DC) min nominal line tIS tIH tVAC tangent line VREF(DC) VIL(DC) max VIL(AC) max VSSCA nominal line tangent line VREF to AC region tVAC TR SRetiuspingSlSewignRaal te= tangent line[VIH(AC)min TR - VREF(DC)] TF SFeatullpinSg lSewignRaal te = tangent line[VREF(DC) - VIL(AC)max] TF Figure. Illustration of tangent line for setup time tIS for CA and CS_n with respect to clock Rev 1.1 / Nov. 2014 119 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) CK_c CK_t VDDCA tIS tIH tIS tIH VIH(AC) min VIH(DC min DC to VREF region VREF(DC) DC to VREF region VIL(DC) max tangent line nominal line tangent line nominal line VIL(AC) max VSSCA TR TF HRoisldinSgleSwignRaalte= tangent line [VREF(DC) - VIL(DC)max] TR Hold Slew Rate Falling Signal = tangent line [VIH(DC)min - VREF(DC)] TF Figure. Illustration of tangent line for hold time tIH for CA and CS_n with respect to clock Rev 1.1 / Nov. 2014 120 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Data Setup, Hold and Slew Rate Derating For all input signals (DQ, DM) the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the tDS and tDH derating value respectively. Example: tDS (total setup time) = tDS(base) + tDS. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded `VREF(DC) to ac region', use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(DC) to ac region', the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between shaded `dc level to VREF(DC) region', use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(DC) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/ IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. Rev 1.1 / Nov. 2014 121 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Unit [ps] tDS(base) tDH(base) 1066 -10 80 Table. Data Setup and Hold Base-Values LPDDR2 933 800 667 533 466 Reference 15 50 130 210 230 105 140 220 300 320 VIH/L(AC)=VREF(DC)+/-220mV VIH/L(DC)=VREF(DC)+/-130mV LPDDR2 Unit [ps] 400 333 266 200 Reference tDS(base) 180 300 450 700 VIH/L(AC)=VREF(DC)+/-300mV tDH(base) 280 400 550 800 VIH/L(DC)=VREF(DC)+/-200mV Note 1: AC/DC referenced for 1V/ns DQ, DM slew rate and 2V/ns differential DQS_t-DQS_c slew rate. Table. Derating values LPDDR2 tDS/tDH - AC/DC based AC220 tDS, DH derating in [ps] AC/DC based AC220 Threshold -> VIH(AC)=VREF(DC)+220mV, VIL(AC)=VREF(DC)-220mV DC130 Threshold -> VIH(AC)=VREF(DC)+130mV, VIL(DC)=VREF(DC)-130mV DQS_t, DQS_c Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 2.0 110 65 110 65 110 65 - - - - - - - - - - 1.5 74 43 73 43 73 43 89 59 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - DQ,DM 0.9 - Slew rate V/ns 0.8 - 0.7 - - -3 -5 -3 -5 13 11 29 27 45 43 - - - - - - -8 -13 8 3 24 19 40 35 56 55 - - - - - - 2 -6 18 10 34 26 50 46 66 78 0.6 - - - - - - - - 10 -3 26 13 42 33 58 65 0.5 - - - - - - - - - - 4 -4 20 16 36 48 0.4 - - - - - - - - - - - - -7 2 17 34 Note 1: Cell contents shaded in red are defined as ‘not supported’ Rev 1.1 / Nov. 2014 122 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Table. Derating values LPDDR2 tDS/tDH - AC/DC based AC300 tDS, DH derating in [ps] AC/DC based AC300 Threshold -> VIH(AC)=VREF(DC)+300mV, VIL(AC)=VREF(DC)-300mV DC200 Threshold -> VIH(DC)=VREF(DC)+200mV, VIL(DC)=VREF(DC)-200mV DQS_t, DQS_c Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH 2.0 150 100 150 100 150 100 - - - - - - - - - - 1.5 100 67 100 67 100 67 116 83 - - - - - - - - 1.0 0 0 0 0 0 0 16 16 32 32 - - - - - - DQ,DM 0.9 - Slew rate V/ns 0.8 - 0.7 - - -4 -8 -4 -8 12 8 28 24 44 40 - - - - - - -12 -20 4 -4 20 12 36 28 52 48 - - - - - - -3 -18 13 -2 29 14 45 34 61 66 0.6 - - - - - - - - 2 -21 18 -5 34 15 50 47 0.5 - - - - - - - - - - -12 -32 4 -12 20 20 0.4 - - - - - - - - - - - - -35 -40 -11 -8 Note 1: Cell contents shaded in red are defined as ‘not supported’ Table. Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition Slew Rate [V/ns] tVAC@ 300mV [ps] MIN MAX tVAC@220mV [ps] MIN MAX > 2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - <0.5 0 - 150 - Rev 1.1 / Nov. 2014 123 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) DQS_c DQS_t VDDQ tDS tDH tDS tDH tVAC VIH(AC) min VIH(DC) min VREF to AC region VREF(DC) VIL(DC) max VIL(AC) max nominal slew rate nominal slew rate VREF to AC region VSSQ tVAC TF TR Setup Slew Rate Falling Signal = VREF(DC) - VIL(AC)max TF Setup Slew Rate Rising Signal = VIH(AC)min - VREF(DC) TR Figure. Illustration of nominal slew rate and tVAC for setup time tDS for DQ with respect to strobe Rev 1.1 / Nov. 2014 124 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) DQS_c DQS_t VDDQ tDS tDH VIH(AC) min VIH(DC) min DCregtoioVnREF VREF(DC) nominal slew rate VIL(DC) max VIL(DC) max tDS tDH nominal slew rate DC to VREF region VSSQ TR TF Hold Slew Rate Rising Signal = VREF(DC) - VIL(DC)max TR Hold Slew Rate Falling Signal = VIH(DC)min - VREF(DC) TF Figure. Illustration of nominal slew rate for hold time tDH for DQ with respect to strobe Rev 1.1 / Nov. 2014 125 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) DQS_c DQS_t VDDQ tDS tDH VIH(AC) min VREF to AC region VIH(DC) min nominal line tDS tDH tVAC tangent line VREF(DC) VIL(DC) max VIL(AC) max VSSQ nominal line TF tangent line VREF to AC region tVAC TR SRetiuspingSlSewignRaal te= tangent line[VIH(AC)min TR - VREF(DC)] Setup Slew Rate Falling Signal = tangent line[VREF(DC) - VIL(AC)max] TF Figure. Illustration of tangent line for setup time tDS for DQ with respect to strobe Rev 1.1 / Nov. 2014 126 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) DQS_c DQS_t VDDQ VIH(AC) min tDS tDH VIH(DC) min DC to VREF region VREF(DC) DC to VREF region VIL(DC) max tangent line VIL(AC) max tDS tDH nominal line tangent line nominal line VSSQ TR TF HRoisldinSgleSwignRaalte= tangent line [VREF(DC) - VIL(DC)max] TR Hold Slew Rate Falling Signal = tangent line [VIH(DC)min - VREF(DC)] TF Figure. Illustration of tangent line for hold time tDH for DQ with respect to strobe Rev 1.1 / Nov. 2014 127 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Command Definitions Activate command The SDRAM Activate command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at the rising edge of the clock. The bank addresses BA0 - BA2 are used to select the desired bank. The row address R0 through R14 is used to determine which row to activate in the selected bank. The Activate command must be applied before any Read or Write operation can be executed. The LPDDR2 SDRAM can accept a read or write command at time tRCD after the activate command is sent. Once a bank has been activated it must be precharged before another Activate command can be applied to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between Activate commands to different banks is tRRD. Certain restrictions on operation of the 8 bank devices must be observed. There are two rules. One for restricting the number of sequential Activate commands that can be issued and another for allowing more time for RAS precharge for a Precharge All command. The rules are as follows: • 8 bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated (or refreshed, in the case of REFpb) in a rolling tFAW window. Converting to clocks is done by dividing tFAW [ns] by tCK [ns], and rounding up to next integer value. As an example of the rolling window, if RU {(tFAW / tCK)} is 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued at or between clock N+1 and N+9. REFpb also counts as bank-activation for the purposes of tFAW. • 8 bank device Precharge All Allowance: tRP for a Precharge All command for an 8 Bank device shall equal to tRPab, which is greater than tRPpb. T0 T1 T2 T3 CK_t/CK_c Tn Tn+1 Tn+2 Tn+3 CA0-9 Bank A Row Row Addr Addr Bank B Bank A Row Row Col Col Addr Addr Addr Addr RAS to CAS delay = tRCD RAS to RAS delay = tRRD Read Begins Bank A BRaonwk A Row Addr Addr Bank Precharge time = tRP [CMD] Activate Nop Activate Read Precharge Nop Bank Active = tRAS Row Cycle time = tRC Nop Activate Note: 1. A Precharge-All command uses tRPab timing, while a Single Bank Precharge command uses tRPpb timing. In this figure, tRP is used to denote either an All-bank Precharge or a Single Bank Precharge. Figure. LPDDR2-S4: Activate command cycle tRCD = 3, tRP = 3, tRRD = 2 Rev 1.1 / Nov. 2014 128 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) Tn CK_t/ CK_c Tn+1 CA0-9 Bank A Tm Tm+1 Bank B Tx Tx+1 Bank C Ty Ty+1 Tz Tz+1 Bank D Bank E [CMD] ACT Nop ACT tRRD ACT Nop tRRD ACT Nop tRRD tFAW ACT Nop Nop ACT Note: 1. For 8-bank devices only. No more than 4 banks may be activated in a rolling tFAW window. Figure. LPDDR2-S4: tFAW timing T0 T1 T2 T3 CK_t/CK_c tIS tIH tIS tIH CS_n VIL(AC) VIH(AC) VIL(DC) VIH(DC) tIS tIH tIS tIH CA0-9 CA Rise CA Fall CA CA Rise Fall CA CA Rise Fall CA CA Rise Fall [CMD] Nop Command Nop Command High or LOW (but a defined logic level) Note: 1. Setup and hold conditions also apply to the CKE pin. See section related to power down for timing diagrams related to the CKE pin. Figure. LPDDR2-S4 Command Input Setup and Hold timing Rev 1.1 / Nov. 2014 129 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) T0 T1 CK_t/CK_c CKE tIHCKE VIHCKE VILCKE tISCKE Tx Tx+1 tIHCKE VIHCKE VILCKE tISCKE High or LOW (but a defined logic level) Note: 1. After CKE is registered LOW, CKE signal level shall be maintained below VILCKE for tCKE specification (LOW pulse width). 2. After CKE is registered HIGH, CKE signal level shall be maintained above VIHCKE for tCKE specification (HIGH pulse width). Figure. LPDDR2-S4 CKE Input Setup and Hold timing Read and Write access modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting CS_n LOW, CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at this time to determine whether the access cycle is a read operation (CA2 HIGH) or a write operation (CA2 LOW). The LPDDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a burst read or write operation on successive clock cycles. For LPDDR2-S4 devices, a new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. In case of BL = 8 and BL=16 settings, reads may be interrupted by Reads and Writes may be interrupted by Writes provided that this occurs on even clock cycles after the Read or Write command and tCCD is met. The Minimum CAS to CAS delay is defined by tCCD Burst read command The Burst Read command is initiated by having CS_n LOW, CA0 HIGH, CA1 LOW and CA2 HIGH at the rising edge of the clock. The command address bus inputs, CA5r-CA6r and CA1f-CA9f, determine the starting column address for the burst. The Read Latency (RL) is defined from the rising edge of the clock on which the Read Command is issued to the rising edge of the clock from which the tDQSCK delay is measured. The first valid datum is available (RL x tCK) + tDQSCK + tDQSQ after the rising edge of the clock where the Read Command is issued. The data strobe output is driven LOW tRPRE before the first rising valid strobe edge. The first bit of the burst is synchronized with the first rising edge of the data strobe. Each subsequent data-out appears on each DQ pin edge aligned with the data strobe. The RL is programmed in the mode registers. Timings for the data strobe are measured relative to the crosspoint of DQS_t and its complement, DQS_c. Rev 1.1 / Nov. 2014 130 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) CK_c RL -1 CK_t RL tCH tCL DQS_t/DQS_c tLZ(DQS) tDQSCKmax DQS_c DQS_t tRPRE RL+BL/2 tQSH tQSL tHZ(DQS) tRPST DQ Q tLZ(DQ) tDQSQmax tQH Q Q Q tDQSQmax tQH tHZ(DQ) Figure. LPDDR2-S4: Data Output (Read) Timing (tDQSCKmax) Note: 1. tDQSCK may span multiple clock periods. 2. An effective Burst Length of 4 is shown. CK_C RL -1 RL tCH tCL CK_t tLZ(DQS) DQS_t/DQS_c DQS_c DQS tDQSCKmin tRPRE RL+BL/2 tHZ(DQS) tRPST DQ tDQSQmax tLZ(DQ) Q tQH Q Q Q tDQSQmax tQH tHZ(DQ) Figure. LPDDR2-S4: Data Output (Read) Timing (tDQSCKmin) Note: 1. An effective Burst Length of 4 is shown. Rev 1.1 / Nov. 2014 131 H9TP64A8JDMCPR 8GB eNAND (x8) / LPDDR2-S4B 8Gb(x32, 2CS) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t/CK_c CA0-9 Bank A Col Col Addr Addr [CMD] Read Nop Nop Nop Nop Nop Nop Nop Nop tDQSCK DQS_t/DQS_c RL = 5 DQs DOUT DOUT DOUT DOUT A0 A1 A2 A3 Figure. LPDDR2-S4: Burst read: RL = 5, BL = 4, tDQSCK>tCK T0 T1 T2 T3 T4 T5 T6 T7 T8 CK_t/CK_c CA0-9 Bank Col A Col Addr Addr [CMD] Read DQS_t/DQS_c DQs Nop Nop RL = 3 Nop Nop Nop Nop Nop Nop tDQSCK DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT A0 A1 A2 A3 A4 A5 A6 A7 Figure. LPDDR2-S4: Burst read: RL = 3, BL = 8, tDQSCK

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