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LM3243 www.ti.com SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 LM3243 High-Current Step-Down Converter for 2G/3G/4G RF Power Amplifiers Check for Samples: LM3243 FEATURES 1 •2 High-Efficiency PFM and PWM modes with Internal Synchronous Rectification • Analog Bypass Function with Low Dropout Resistance (45 mΩ typ.) • Dynamically Adjustable Output Voltage, 0.4V to 3.6V (typ.), in PFM and PWM Modes • 2.5A Maximum Load Current in PWM Mode • 2.7 MHz (average) PWM Switching Frequency • Modulated switching frequency to aid Rx Band Compliance • Operates from a Single Li-ion Cell (2.7V to 5.5V) • ACB reduces inductor requirements and size • Minimum total solution size by using small footprint and case size inductor and capacitors • 16-bump thin DSBGA Package • Current and Thermal Overload Protection APPLICATIONS • Cellular Phones • Hand-Held Radios • RF PC Cards • Battery-Powered RF Devices DESCRIPTION The LM3243 is a DC-DC converter optimized for powering multi-mode 2G/3G/4G RF power amplifiers (PAs) from a single Lithium-Ion cell. The LM3243 steps down an input voltage from 2.7V to 5.5V to a dynamically adjustable output voltage of 0.4V to 3.6V. The output voltage is set through a VCON analog input that adjusts the output voltage to ensure efficient operation at all power levels of the RF PA. The LM3243 operates in constant frequency PWM mode producing a small and predictable amount of output voltage ripple. This enables best ECTEL power requirements in GMSK and EDGE spectral compliance, with the minimal amount of filtering and excess headroom. When operating in PFM mode, the LM3243 enables the lowest DG09 current consumption and therefore maximizes system efficiency. The LM3243 has a unique Active Current assist and analog Bypass (ACB) feature to minimize inductor size without any loss of output regulation for the entire battery voltage and RF output power range, until dropout. ACB provides a parallel current path, when needed, to limit the maximum inductor current to 1.4A (typ.) while still driving a 2.5A load. The ACB also enables operation with minimal dropout voltage. The LM3243 is available in a small 2 mm x 2 mm chip-scale 16-bump DSBGA package. If you are considering using the LM3243 in a system design, please see the PCB Layout Considerations section of this data sheet. TYPICAL SYSTEM APPLICATION DIAGRAM VBATT 10 µF GPO1 GPO2 DAC BB or RFIC EN PVIN VDD SW BP LM3243 FB MODE ACB VCON PGND SGND BGND 1.5 µH VOUT 10 µF VCC_PA_3G 1.0 µF VCC_PA_2G 4.7 µF PA PA(s) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. 2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2013, Texas Instruments Incorporated LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 Connection Diagram 16-Bump 0.4 mm Pitch Thin DSBGA Package www.ti.com PGND SW PVIN ACB A A ACB PVIN SW PGND PGND SW PVIN ACB B B ACB PVIN SW PGND SGND EN BP BGND C C BGND BP EN SGND VDD VCON MODE FB D D FB MODE VCON VDD 1 2 3 4 Top View 4 3 2 1 Bottom View Pin # A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3 A4 B4 C4 D4 Name PGND SGND VDD SW EN VCON PVIN BP MODE ACB BGND FB PIN DESCRIPTIONS Description Power Ground to the internal NFET switch. Signal Analog and Control Ground (Low Current) Analog Supply Input. Switching Node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor with a saturation current rating that exceeds the ILIM,PFET,Steady State Current Limit specification of the LM3243. Enable Input. Set this digital input HIGH for normal operation. For shutdown, set low. Pin has an 800 kΩ internal pulldown resistor. Voltage Control Analog input. VOUT = 2.5 x VCON. Power Supply Voltage Input to the internal PFET switch and ACB. Bypass mode Input. Set the pin HIGH for forced Bypass mode operation. Set the pin LOW for automatic Analog Bypass mode (recommended). PWM/PFM Mode Selection Input. Setting the pin HIGH allows for PFM or PWM, depending on the load current. Setting the pin LOW forces the part to be in PWM only. Analog Current Bypass. Connect to the output at the output filter capacitor. Active Current assist and analog Bypass Ground (High Current). Feedback Analog Input. Connect to the output at the output filter capacitor. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated LM3243 www.ti.com SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 ABSOLUTE MAXIMUM RATINGS (1)(2) (3) VDD, PVIN to SGND PGND to SGND EN, FB, VCON, BP, MODE SW, ACB PVIN to VDD Continuous Power Dissipation (4) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature ESD Rating (5), (6) Human Body Model: (Soldering, 10 sec) −0.2V to +6.0V −0.2V to +0.2V (SGND −0.2V) to (VDD +0.2V) (PGND −0.2V) to (PVIN +0.2V −0.2V to +0.2V Internally Limited +150°C −65°C to +150°C +260°C 2kV (1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply verified performance limits. For performance limits and associated test conditions, see the Electrical Characteristics tables. (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (3) All voltages are with respect to the potential at the GND pins. The LM3243 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin LOW until the input voltage exceeds 2.7V. (4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.). (5) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MIL-STD-883 3015.7) (6) Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper ESD handling procedures can result in damage. OPERATING RATINGS (1) (2) Input Voltage Range 2.7V to 5.5V Recommended Load Current 0A to 2.5A Junction Temperature (TJ) Range Ambient Temperature (TA) Range (3) −30°C to +125°C −30°C to +90°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the potential at the GND pins. The LM3243 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin LOW until the input voltage exceeds 2.7V. (3) In applications where high-power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). At higher power levels duty cycle usage is assumed to drop (i.e., max power 12.5% usage is assumed) for 2G mode. THERMAL PROPERTIES Junction-to-Ambient Thermal Resistance (θJA), YFQ16 Package (1) 50°C/W (1) Junction-to-ambient thermal resistance (θJA) is taken from thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 3 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (1) (2) (3) Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA = TJ ≤ +90°C). Unless otherwise noted, all specifications apply to the Typical System Application Diagram (page 2) with: PVIN = VDD = EN = 3.8V, BP = 0V. Symbol Parameter Conditions Min Typ Max Units VFB, LOW Feedback voltage at low setting VCON = 0.16V, MODE = LOW (3) 0.350 0.400 0.450 V VFB, HIGH ISHDN Iq_PFM Iq_PWM Feedback voltage at high setting Shutdown supply current DC bias current into VDD DC bias current into VDD VCON = 1.44V, VIN = 3.9V, MODE = LOW (3) EN = SW = VCON = 0V (4) No switching (5) MODE = HIGH No Switching (5) MODE = LOW 3.492 3.6 3.708 V 0.02 4 µA 260 310 µA 975 1100 ILIM,PFET, Transient Positive transient peak current limit VCON = 0.6V (6) 1.9 2.1 A ILIM,PFET,Steady State ILIM, P_ACB Positive steady state peak current limit Positive active current assist peak current limit VACB = 3.05V VCON = 0.6V (6) VCON = 0.6V, VACB = 2.8V (6) 1.34 1.45 1.65 A 1.40 1.70 2.00 A ILIM, NFET NFET Switch negative peak current limit VCON = 1.0V (6) −1.69 −1.50 −1.31 A FOSC Average Internal oscillator frequency VCON = 1.0V 2.43 2.70 2.97 MHz VIH VIL IEN IIN IVCON Gain Logic HIGH input threshold Logic LOW input threshold EN pin pulldown current Pin input current VCON pin leakage current VCON to VOUT Gain BP, EN, MODE BP, EN, MODE EN = 3.6V BP, MODE VCON = 1.0V 0.16V ≤ VCON ≤ 1.44V (7) 1.2 V 0.5 0 5 10 −1 1 µA −1 1 2.5 V/V (1) All voltages are with respect to the potential at the GND pins. The LM3243 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin LOW until the input voltage exceeds 2.7V. (2) Min and Max limits are specified by design, test, or statistical analysis. (3) The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = VDD = 3.8V. For performance over the input voltage range and closed-loop results, refer to the datasheet curves. (4) Shutdown current includes leakage current of PFET. (5) Iq specified here is when the part is not switching. For operating input current at no load, refer to datasheet curves. (6) Current limit is built-in, fixed, and not adjustable. (7) Linearity limits are ±3% or ±50 mV, whichever is larger. 4 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated LM3243 www.ti.com SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 SYSTEM CHARACTERISTICS The following spec table entries are specified by design and verifications providing the component values in the Typical Application Circuit are used (L = 1.5 µH, DCR = 120 mΩ, TOKO DFE201610C-1R5N, CIN = 10 µF, 6.3V, 0402, Samsung CL05A106MQ5NUN, COUT = 10 µF + 4.7 µF + 3 x 1.0 µF + 3300 pF: 6.3V, 0402, Samsung CL05A106MQ5NUN, CL05A475MQNRN; 6.3V, 0201 Samsung CL03A105MQ3CSN; 6.3V, 01005 Murata GRM022R60J332K). These parameters are not verified by production testing. Min and Max values are specified over the ambient temperature range TA = −30°C to 90°C. Typical values are specified at PVIN = VDD = EN = 3.8V, BP = 0V and TA = 25°C unless otherwise stated. Symbol Parameter Conditions Min Typ Max Units TSETUP Time for SW pin to become active upon power-up EN = LOW-to-HIGH 30 TON Turn-on time (time for output to reach 90% of final value after EN LOW-to-HIGH transition) EN = LOW-to-HIGH, VIN = 4.2V, VCON = 1.36V, VOUT = 3.4V, IOUT ≤ 1mA µs 50 Time for VOUT to rise from 0V to 3V (90% or 2.7V) VIN = 4.2V RLOAD = 6.8Ω, VCON = 0V to 1.2V 20 Time for VOUT to fall from 3.6V to 2.6V (10% or 2.7V) VIN = 4.2V, RLOAD = 6.8Ω, VCON = 1.44V to 1.04V TRESPONSE Time for VOUT to rise from 1.8V to 2.8V (90% or 2.7V) Time for VOUT to fall from 2.8V to 1.8V (10% or 1.9V) VIN = 4.2V, RLOAD = 1.9Ω, VCON = 0.72V to 1.12V VIN = 4.2V, RLOAD = 1.9Ω, VCON = 1.12V to 0.72V 15 µs Time for VOUT to rise from 0V VIN = 4.2V, RLOAD = 1.9Ω, to 3.4V (90% or 3.1V) VCON = 0V to 1.36V 20 Time for VOUT to fall from VIN = 4.2V, RLOAD = 1.9Ω, VCON = 3.4V to 0.4V (10% or 0.7V) 1.36V to 0.16V TBypass TBypass, ON Time for VOUT to rise from 0V to PVIN after BP LOW-toHIGH transition (90%) Bypass turn-on time. Time for VOUT to rise from 0V to PVIN after EN LOW-to-HIGH transition (90% or 3.24) VCON = 0V, IOUT ≤ 1mA EN = VIN= 3.8V, IOUT ≤ 1mA 20 µs 50 Rtot_drop Total dropout resistance in bypass mode VCON = 1.5V, Max value at VIN = 3.1V, Inductor ESR ≤ 151 mΩ 45 55 mΩ CIN Pin input capacitance for BP, EN, MODE Test frequency = 100 KHz 5 pF IOUT Maximum load current in PWM mode Switcher + ACB 2.5 IOUT, PU IOUT, PD, PWM Maximum output transient pullup current limit PWM maximum output Switcher + ACB (1) transient pulldown current limit 3.0 A −3.0 IOUT, MAX-PFM Maximum output load current VIN = 3.8V, VCON < 1.0 in PFM mode MODE = HIGH (1) 85 mA Linearity Linearity in control range of VCON = 0.16V to 1.44V VIN = 4.2V (2) Monotonic in nature −3 +3 % −50 +50 mV (1) Current limit is built-in, fixed, and not adjustable. (2) Linearity limits are ±3% or ±50 mV, whichever is larger. Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 5 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 www.ti.com SYSTEM CHARACTERISTICS (continued) The following spec table entries are specified by design and verifications providing the component values in the Typical Application Circuit are used (L = 1.5 µH, DCR = 120 mΩ, TOKO DFE201610C-1R5N, CIN = 10 µF, 6.3V, 0402, Samsung CL05A106MQ5NUN, COUT = 10 µF + 4.7 µF + 3 x 1.0 µF + 3300 pF: 6.3V, 0402, Samsung CL05A106MQ5NUN, CL05A475MQNRN; 6.3V, 0201 Samsung CL03A105MQ3CSN; 6.3V, 01005 Murata GRM022R60J332K). These parameters are not verified by production testing. Min and Max values are specified over the ambient temperature range TA = −30°C to 90°C. Typical values are specified at PVIN = VDD = EN = 3.8V, BP = 0V and TA = 25°C unless otherwise stated. Symbol Parameter Conditions Min Typ Max Units VIN = 3.8V, VOUT = 1.8V, IOUT = 10 mA MODE = HIGH (PFM) 79 82 VIN = 3.8V, VOUT = 0.5V, IOUT = 5 mA MODE = HIGH (PFM) 58 60 VIN = 3.8V, VOUT = 3.5V, IOUT = 1900 mA 89 92 MODE = LOW (PWM) η Efficiency % VIN = 3.8V, VOUT = 2.5V, IOUT = 250 mA 90 93 MODE = LOW (PWM) VIN = 3.8V, VOUT = 1.6V, IOUT = 130 mA MODE = LOW (PWM) 83 86 VIN = 3.8V, VOUT = 1.0V, IOUT = 400 mA MODE = LOW (PWM) 81 84 Ripple voltage at no pulse skipping condition VIN = 0.4V to 3.6V, VOUT = 0.4V to 3.6V, ROUT = 1.9Ω (3) MODE = LOW 1 3 VRIPPLE Line_tr Ripple voltage at pulse skipping condition PFM Ripple Voltage Line transient response VIN = 5.5V to dropout, VOUT = 3.6V, ROUT = 1.9Ω (3) VIN = 3.2V, VOUT < 1.125V, IOUT =10 mA, MODE = HIGH VIN = 3.2V, VOUT ≤ 0.5V, IOUT = 5mA, MODE = HIGH VIN = 3.6V to 4.2V, TR = TF = 10 µs, VOUT = 1V, IOUT = 600 mA MODE = LOW 8 mVpp 50 50 50 mVpk Load_tr Load transient response VOUT = 3.0V, TR = TF = 10 µs, IOUT = 0A to 1.2A MODE = LOW 40 mVpk Max Duty cycle Maximum duty cycle MODE = LOW 100 % VIN = 3.2V, VOUT = 1.0V, IOUT = 10 mA 100 160 PFM_Freq Minimum PFM Frequency MODE = HIGH kHz VIN = 3.2V, VOUT = 0.5V, IOUT = 5mA MODE = HIGH 34 55 (3) Ripple voltage should be measured at COUT electrode on a well-designed PC board and using the suggested inductor and capacitors. 6 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated LM3243 www.ti.com SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs. Load Current VIN = 3.8V, IOUT = 10mA to 150mA 100 Efficiency vs. Load Current VIN = 3.8V, IOUT = 150mA to 750mA 100 95 95 90 90 EFFICENCY (%) EFFICIENCY (%) 85 85 80 80 75 70 65 60 0 VOUT = 1.0V VOUT = 1.5V VOUT = 2.0V VOUT = 2.5V VOUT = 3.0V 20 40 60 80 100 120 140 160 LOAD CURRENT (mA) Figure 1. 75 70 65 60 0 VOUT = 1.6V VOUT = 2.0V VOUT = 2.5V VOUT = 3.0V VOUT = 3.5V 100 200 300 400 500 600 700 800 LOAD CURRENT (mA) Figure 2. EFFICIENCY (%) Efficiency vs. Load Current VIN = 3.8V, IOUT = 100mA to 1A 100 95 90 85 80 75 70 0 VOUT = 1.6V VOUT = 2.0V VOUT = 2.5V VOUT = 3.0V VOUT = 3.5V 200 400 600 800 LOAD CURRENT (mA) Figure 3. 1000 EFFICIENCY (%) Efficiency vs. Load Current VIN = 3.8V, IOUT = 1A to 2.5A 100 90 80 70 60 50 VOUT = 2.0V 40 VOUT = 2.5V VOUT = 3.0V 30 VOUT = 3.5V 20 900 1200 1500 1800 2100 2400 2700 LOAD CURRENT (mA) Figure 4. OUTPUT VOLTAGE (V) Output Voltage vs. Supply Voltage VOUT = 3.4V, VIN = 4.3V down to dropout 3.6 3.4 3.2 DROPOUT 3.0 2.8 2.6 IOUT= 1.5A 2.4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) Figure 5. OUTPUT VOLTAGE (V) Output Voltage vs. VCON Voltage VIN = 4.2V, RLOAD = 6.8Ω, 0.16V < VCON < 1.4V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.5X GAIN 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VCON (V) Figure 6. Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 7 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Center-Switching Frequency vs. Supply Voltage VOUT = 2.5V, IOUT = 700mA, VIN = 3.8V 3.00 Quiescent Current (PFM) vs. Supply Voltage VOUT = 1V, 2.7V < VIN< 5.5V (No Load) 290 QUIESCENT CURRENT ( A) SWITCHING FREQUENCY (MHz) 2.95 280 2.90 270 2.85 2.80 260 2.75 250 2.70 240 2.65 230 2.60 2.55 220 2.50 210 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE (V) Figure 7. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE (V) Figure 8. Quiescent Current (PWM) vs. Supply Voltage VOUT = 2.5V, 2.7V < VIN< 5.5V (No Load) 12 VCON Transient (3G/4G) VOUT = 0V to 3V, RLOAD = 6.8Ω, VIN = 3.8V QUIESCENT CURRENT (mA) 10 VOUT 2V/DIV 8 6 VCON 2V/DIV 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE (V) Figure 9. VCON Transient (PWM) VOUT = 1.4V to 3.4V, RLOAD = 1.9Ω, VIN = 4.2V IOUT 20 s/DIV 500 mA/DIV Figure 10. Load Transient in PFM Mode VOUT = 1V, IOUT = 0mA to 60mA, VIN = 3.6V VOUT 2V/DIV VOUT 5 mV/DIV VCON 2V/DIV IOUT 20 s/DIV Figure 11. 1A/DIV IOUT 20 s/DIV Figure 12. 50 mA/DIV 8 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated LM3243 www.ti.com SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Load Transient in PWM Mode VIN = 3.8V, VOUT = 2.5V, IOUT = 0mA to 300mA Load Transient in PWM Mode VIN = 3.8V, VOUT = 3.0V, IOUT = 0mA to 700mA VOUT 20 mV/ DIV VOUT 50 mV/ DIV IOUT 100 Ps/DIV Figure 13. 200 mA/ DIV Load Transient in PWM Mode VIN = 4.2V, VOUT = 3.0V, IOUT = 0mA to 1.2A VOUT 100 mV/ DIV IOUT 100 Ps/DIV Figure 15. 500 mA/ DIV Line Transient VIN = 3.6V to 4.2V, VOUT = 1.0V, RLOAD = 6.8Ω VOUT 50 mV/DIV VIN 1V/DIV 100 s/DIV Figure 17. IOUT 100 Ps/DIV Figure 14. 500 mA/ DIV Line Transient VIN = 3.6V to 4.2V, VOUT = 2.5V, RLOAD = 6.8Ω VOUT VIN 50 mV/DIV 1V/DIV 100 s/DIV Figure 16. Startup in PFM Mode VIN = 3.8V, VOUT = 1.0V, No Load, EN = LOW to HIGH VSW VOUT EN 20 s/DIV Figure 18. 2V/DIV 1V/DIV 2V/DIV Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 9 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Startup in PWM Mode VIN = 4.2V, VOUT = 3.4V, No Load, EN = LOW to HIGH Timed-Current Limit VIN = 4.2V, VOUT = 2.5V, RLOAD = 6.8Ω to VOUT Shorted VSW VOUT 2V/DIV 2V/DIV VOUT VSW 2V/DIV 2V/DIV 2V/DIV Inductor 1A/DIV EN Current 20 s/DIV Figure 19. 40 s/DIV Figure 20. 10 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated LM3243 www.ti.com SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 FUNCTIONAL DESCRIPTION Device Information The LM3243 is a high-efficiency step-down DC-DC converter optimized to power the RF power amplifier (PA) in cell phones, portable communication devices, or battery-powered RF devices with a single Li-Ion battery. It operates in fixed-frequency PWM mode for 2G transmissions (with MODE = LOW), automatic mode transition between PFM and PWM mode for 3G/4G RF PA operation (with MODE = HIGH), forced bypass mode (with BP = HIGH) or in shutdown mode (with EN = LOW). The fixed-frequency PWM mode provides high efficiency and very low output voltage ripple. In PFM mode, the converter operates with reduced switching frequencies and lower supply current to maintain high efficiencies. The forced bypass mode allows the user to drive the output directly from the input supply through a bypass FET. The shutdown mode turns the LM3243 off and reduces current consumption to 0.02 µA (typ.). In PWM and PFM modes of operation, the output voltage of the LM3243 can be dynamically programmed from 0.4V to 3.6V (typ.) by adjusting the voltage on VCON. Current overload protection and thermal overload protection are also provided. The LM3243 was engineered with Active Current assist and analog Bypass (ACB). This unique feature allows the converter to support maximum load currents of 2.5A (min.) while keeping a small footprint inductor and meeting all of the transient behaviors required for operation of a multi-mode RF Power Amplifier. The ACB circuit provides an additional current path when the load current exceeds 1.4A (typ.) or as the switcher approaches dropout. Similarly, the ACB circuit allows the converter to respond with faster VCON output voltage transition times by providing extra output current on rising and falling output edges. The ACB circuit also performs the function of analog bypass. Depending upon the input voltage, output voltage and load current, the ACB circuit automatically and seamlessly transitions the converter into analog bypass while maintaining output voltage regulation and low output voltage ripple. Full bypass (100% duty cycle operation) will occur if the total dropout resistance in bypass mode (Rtot_drop = 45 mΩ) is insufficient to regulate the output voltage. LM3243’s 16-bump DSBGA package is the best solution for space-constrained applications such as cell phones and other hand-held devices. The high switching frequency, 2.7 MHz (typ.) in PWM mode, reduces the size of input capacitors, output capacitors and of the inductor. Use of a DSBGA package is best suited for opaque case applications and requires special design considerations for implementation. (Refer to DSBGA Package Assembly and Use section below). As the LM3243 does not implement UVLO, the system controller should set EN = LOW during power-up and UVLO conditions. (Refer to Shutdown Mode below). PWM Operation When the LM3243 operates in PWM (Pulse Width Modulation) mode, the switching frequency is constant, and the switcher regulates the output voltage by changing the energy-per-cycle to support the load required. During the first portion of each switching cycle, the control block in the LM3243 turns on the internal PFET switch. This allows current to flow from the input through the inductor and to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN – VOUT)/L, by storing energy in its magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET and to the output filter capacitor and load, which ramps the inductor current down with a slope of -VOUT/L. The output filter capacitor stores charge when the inductor current is greater than the load current and releases it when the inductor current is less than the load current, smoothing the voltage across the load. At the next rising edge of the clock, the cycle repeats. An increase of load pulls the output voltage down, increasing the error signal. As the error signal increases, the peak inductor current becomes higher, thus increasing the average inductor current. The output voltage is therefore regulated by modulating the PFET switch on-time to control the average current sent to the load. The circuit generates a duty-cycle modulated rectangular signal that is averaged using a low pass filter formed by the inductor and output capacitor. The output voltage is equal to the average of the duty-cycle modulated rectangular signal. Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 11 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 www.ti.com PFM Mode With MODE = HIGH, the LM3243 automatically transitions to from PWM into PFM (Pulse Frequency Modulation) operation if the average inductor current is less than 75 mA (typ.) and VIN − VOUT > 0.6V. The switcher regulates the fixed output voltage by transferring a fixed amount of energy during each cycle and modulating the frequency to control the total power delivered to the output. The converter switches only as needed to support the demand of the load current, therefore maximizing efficiency. If the load current should increase during PFM mode to more than 95 mA (typ.), the part will automatically transition into constant frequency PWM mode. A 20 mA (typ.) hysteresis window exists between PFM and PWM transitions. After a transient event, the part temporarily operates in 2.7 MHz (typ.) fixed-frequency PWM mode to quickly charge or discharge the output. This is true for start-up conditions or if MODE pin is toggled LOW-to-HIGH. Once the output reaches its target output voltage, and the load is less than 75 mA (typ.), then the part will seamlessly transition into PFM mode (assuming it is not in forced bypass or auto bypass condition). Active Current Assist and Analog Bypass (ACB) The 3GPP time mask requirement for 2G requires high current to be sourced by the LM3243. These high currents are required for a small time during transients or under a heavy load. Over-rating the switching inductor for these higher currents would increase the solution size and will not be an optimum solution. So to allow an optimal inductor size for such a load, an alternate current path is provided from the input supply through the ACB pin. Once the switcher current limit ILIM,PFET,SteadyState is reached, the ACB circuit starts providing the additional current required to support the load. The ACB circuit also minimizes the dropout voltage by having the analog bypass FET in parallel with VOUT. The LM3243 can provide up to 2.5A (min.) of current in bypass mode with a 4.0A (max.) peak current limit. Bypass Operation The Bypass Circuit provides an analog bypass function with very low dropout resistance (Rtot_drop = 45 mΩ typ). When BP = LOW the part will be in automatic bypass mode which will automatically determine the amount of bypass needed to maintain voltage regulation. When the input supply voltage to the LM3243 is lowered to a level where the commanded duty cycle is higher than what the converter is capable of providing, the part will go into pulse-skipping mode. The switching frequency will be reduced to maintain a low and well-behaved output voltage ripple. The analog bypass circuit will allow the converter to stay in regulation until full bypass is reached (100% duty cycle operation). The converter comes out of full bypass and back into analog bypass regulation mode with a similar reverse process. To override the automatic bypass mode, either set VCON > (VIN)/(2.5) (but less than VIN) or set BP = HIGH for forced bypass function. Forced bypass function is valid for 2.7V < VIN < 5.5V. Shutdown Mode To shut down the LM3243 pull the EN pin LOW (<0.5V). In shutdown mode, the current consumption is 0.02 µA (typ.) and the PFET switch, NFET synchronous rectifier, reference voltage source, control and bias circuit are turned OFF. To enable LM3243 pull EN HIGH (>1.2V), and the mode of operation will be dependent on the voltage applied to the MODE pin. Since the LM3243 does not feature a UVLO (Under Voltage Lock-Out) circuit, the EN pin should be set LOW to turn off the LM3243 during power-up and during UVLO conditions. For cell-phone applications, the system controller determines the power supply sequence; thus, it is up to the system controller to ensure proper sequencing by using all of the available pins and functions properly. Mode Pin The MODE pin changes the state of the converter to one of the two allowed modes of operation. Setting the MODE pin HIGH (>1.2V) sets the device for automatic transition between PFM/PWM mode operation. In this mode, the converter operates in PFM mode to maintain the output voltage regulation at very light loads and transitions into PWM mode at loads exceeding 95 mA (typ.). The PWM switching frequency is 2.7 MHz (typ.). Setting the MODE pin LOW (<0.5V) sets the device for PWM mode operation. The switching operation is in PWM mode only, and the switching frequency is also 2.7 MHz (typ.). 12 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated LM3243 www.ti.com SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 Dynamic Adjustment of Output Voltage The output voltage of the LM3243 can be dynamically adjusted by changing the voltage on the VCON pin. In RF PA applications, peak power is required when the handset is far away from the base station. To maximize the power savings, the LM3243 output should be set just high enough to achieve the desired PA linearity. Hence, during low-power requirements, reduction of supply voltage to the PA can reduce power consumption from the PA, making the operation more efficient and promote longer battery life. Please refer to the Setting the Output Voltage section for further details. Mode Selection Table 1 shows the LM3243 parameters for the given modes (PWM or PFM/PWM). Table 1. Parameters under Different Modes Parameter/Mode MODE pin BP pin Frequency at loads = 75 mA (typ.) Frequency at loads = 95 mA (typ.) VOUT Max Load Steady State PWM LOW LOW 2.7 MHz (typ.) 2.7 MHz (typ.) 2.5 x VCON 2.5A (min.) PFM/PWM HIGH LOW Variable 2.7 MHz (typ.) 2.5 x VCON 75 mA (min in PFM) or 2.5A (min. in PWM) Internal Synchronous Rectification The LM3243 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop, thus increasing efficiency. The reduced forward voltage drop in the internal NFET synchronous rectifier significantly improves efficiency for low output voltage operation. The NFET is designed to conduct through its intrinsic body diode during the transient intervals, eliminating the need of an external diode. Current Limit The LM3243 current limit feature protects the converter during current overload conditions. Both SW and ACB pins have positive and negative current limits. The positive and negative current limits bound the SW and ACB currents in both directions. The SW pin has two positive current limits. The ILIM,PFET,SteadyState current limit triggers the ACB circuit. Once the peak inductor current exceeds ILIM,PFET,SteadyState, the ACB circuit starts assisting the switcher and provides just enough current to keep the inductor current from exceeding ILIM,PFET,SteadyState allowing the switcher to operate at maximum efficiency. Transiently a second current limit ILIM,PFET,Transient of 1.9A (typ. or 2.1 max.) limits the maximum peak inductor current possible. The output voltage will fall out of regulation only after both SW and ACB output pin currents reach their respective current limits of ILIM,PFET,Transient and ILIM,P-ACB. Timed Current Limit If the load or output short circuit pulls the output voltage to 0.3V or lower and the peak inductor current sustains ILIM, PFET Transient more than 10 µs, the LM3243 switches to a timed current limit mode. In this mode, the internal PFET switch is turned off. After approximately 30 µs, the device will return to the normal operation. Thermal Overload Protection The LM3243 IC has a thermal overload protection that protects itself from short-term misuse and overload conditions. If the junction temperature exceeds 150°C, the LM3243 shuts down. Normal operation resumes after the temperature drops below 130°C. Prolonged operation in thermal overload condition may damage the device and is therefore not recommended. Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 13 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 APPLICATION INFORMATION www.ti.com Setting the Output Voltage DAC Control An analog voltage to the VCON pin can dynamically program the output voltage from 0.4V (typ.) to 3.6V (typ.) in both PFM and PWM modes of operation, without the need for external resistors. The output voltage is governed by Table 2. Table 2. Output Voltage Selection VCON (V) VCON = 0.16V to 1.44V VOUT (V) 2.5 x VCON VIN DAC GPIO GPIO 10 µF PVIN VDD SW EN LM3243 FB MODE BP ACB VCON 1.5 µH 10 µF VOUT 4.7 µF SGND PGND BGND PDM Output Figure 21. Dynamic Adjustment of Output Voltage with DAC or PDM PDM-Based VCON Signal Figure 21 shows the application circuit that enables the LM3243 to dynamically adjust the output voltage using a GPIO pin from the system controller. Figure 22 shows the waveforms when adjusted dynamically. The PDM signal of the GPIO is filtered using a low-pass filter and fed to the VCON pin. As the bitstream of the PDM signal changes, the voltage on the VCON pin changes. Thus, the GPIO pin can be used to dynamically adjust the output voltage. The double low-pass filter reduces the ripple at VCON to avoid any excessive VCON-induced ripple at the output voltage. 14 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated www.ti.com LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 EN VCON 8 30 Ps VOUT 0V 7 20 Ps VCON = 0.4V 3.4V 1.7A 1V 7 20 Ps 3.4V 8 30 Ps 3.4V 7 20 Ps ILOAD < 200 mA 7 20 Ps 0A Figure 22. Dynamic Adjustment of Output Voltage with GPIO VCON Pin Figure 23 shows the equivalent CRC circuit for the VCON pin. This circuit is internal to the part and should be taken into consideration when driving this pin. R1 = 100 k: C1 = 1.7 pF C2 = 9 pF Figure 23. VCON Pin Equivalent CRC Circuit Inductor Selection A 1.5 µH inductor is needed for optimum performance and functionality of the LM3243. In the case of 2G transmission current bursts, the effective overall RMS current requirements are reduced. Therefore, please consult with the inductor manufacturers to determine if some of their smaller components will meet your application needs even though the classical inductor specification does not appear to meet the LM3243 RMS current specifications. LM3243 automatically manages the inductor peak and RMS (or steady current peak) current through the SW pin. The SW pin has two positive current limits. The first is the 1.45A typical (or 1.65A maximum.) over-limit current protection. It sets the upper steady-state inductor peak current (as detailed in the Electrical Characteristics Table - ILIM,PFET,SteadyState). It is the dominant factor limiting the inductor's ISAT requirement. The second is a over-limit current protection. It limits the maximum peak inductor current during large signal transients (i.e., < 20 µs) to 1.9A typical (or 2.1A maximum). A minimum inductance of 0.3 µH should be maintained at the second current limit. The ACB circuit automatically adjusts its output current to keep the steady-state inductor current below the steady-state peak current limit. Thus, the inductor RMS current will effectively always be less than the ILIM,PFET,SteadyState during the transmit burst. In addition, as in the case with 2G where the output current comes in bursts, the effective overall RMS current would be much lower. For good efficiency, the inductor’s resistance should be less than 0.2Ω; low DCR inductors (<0.2Ω) are recommended. Table 3 suggests some inductors and suppliers. Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 15 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 Model DFE201610C-1R5M (1285AS-H-1R5M) PSD20161T-1R5MS TFM201610-1R5M Table 3. Suggested Inductors and Their Suppliers Vendor Size TOKO 2.0 mm x 1.6 mm x 1.0 mm CYNTEC TDK 2.0 mm x 1.6 mm x 1.0 mm 2.0 mm x 1.6 mm x 1.0 mm ISAT −30% 2.2A 1.6A 2.2A www.ti.com DCR 120 mΩ 143 mΩ 140 mΩ Capacitor Selection The LM3243 is designed to use ceramic capacitors for its input and output filters. Use a 10 µF capacitor for the input and approximately 10 µF actual total output capacitance. Capacitor types such as X5R, X7R are recommended for both filters. These provide an optimal balance between small size, cost, reliability and performance for cell phones and similar applications. Table 4 lists suggested part numbers and suppliers. DC bias characteristics of the capacitors must be considered while selecting the voltage rating and case size of the capacitor. Smaller case sizes for the output capacitor mitigate piezo-electric vibrations of the capacitor when the output voltage is stepped up and down at fast rates. However, they have a bigger percentage drop in value with DC bias. For even smaller total solution size, 0402 case size capacitors are recommended for filtering. Use of multiple 2.2 µF or 1 µF capacitors can also be considered. For RF Power Amplifier applications, split the output capacitor between DC-DC converter and RF Power Amplifiers: 10 µF (COUT1) + 4.7 µF (COUT2) + 3 x 1.0 µF (COUT3) is recommended. The optimum capacitance split is application dependent, and for stability the actual total capacitance (taking into account effects of capacitor DC bias, temperature de-rating, aging and other capacitor tolerances) should target 10 µF with 2.5V DC bias (measured at 0.5 VRMS). Place all the output capacitors very close to the respective device. A high-frequency capacitor (3300 pF) is highly recommended to be placed next to COUT1. Capacitance 10 µF 10 µF 4.7 µF 1.0 µF 3300 pF Table 4. Suggested Capacitors and Their Suppliers Model GRM185R60J106M CL05A106MQ5NUN CL05A475MQ5NRN CL03A105MQ3CSN GRM022R60J332K Size (Wx L) (mm) 1.6 x 0.8 1.0 x 0.5 1.0 x 0.5 0.6 x 0.3 0.4 x 0.2 Vendor Murata Samsung Samsung Samsung Murata EN Input Control Use the system controller to drive the EN HIGH or LOW with a comparator, Schmitt trigger or logic gate. Set EN = HIGH (>1.2V) for normal operation and LOW (<0.5V) for shutdown mode to reduce current consumption to 0.02 µA (typ.) current. Startup The waveform Figure 24 in shows the startup condition. First, VIN should take on a value between 2.7V and 5.5V. Next, EN should go HIGH (>1.2V). Finally, VCON should be set to a value that corresponds to the required output voltage (VOUT = VCON x 2.5). VOUT will reach its steady-state value in less than 50 µs. To optimize the startup time and behavior of the output voltage, the LM3243 will always start up in PWM mode (even when MODE = HIGH and output load current ≤ 75mA), then seamlessly transition into PFM mode. 16 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated www.ti.com LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 VIN EN VCON BP 8 30 µs VOUT 7 20 µs Figure 24. Startup Sequence and Conditions DSBGA Package Assembly And Use Use of the DSBGA package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in Texas Instruments Application Note AN-1112. Please refer to the section Surface Mount Assembly Considerations. For best results in assembly, local alignment fiducials on the PC board should be used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that would otherwise form if the soldermask and pad overlap, which would hold the device off the surface of the board and interfere with mounting. See Application Note AN-1112 for specific instructions how to do this. The 16-bump package used for LM3243 has 265 micron solder balls and requires 0.225 mm pads for mounting the circuit board. The trace to each pad should enter the pad with a 90°entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 5.6 mil wide, for a section approximately 5 mil long, as a thermal relief. Then each trace should neck up or down to its optimal width. An important criterion is symmetry to insure the solder bumps on the LM3243 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1, A3, B1, and B3 since PGND and PVIN are typically connected to large copper planes, inadequate thermal reliefs can result in inadequate re-flow of these bumps. The DSBGA package is optimized for the smallest possible size in applications with red-opaque or infraredopaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges that are sensitive to light in the read and infrared range shining on the package’s exposed die edges. Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 17 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 PCB LAYOUT CONSIDERATIONS www.ti.com Overview PC board layout is critical to successfully designing a DC-DC converter into a product. A properly planned board layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also addressing manufacturing issues that can have adverse impacts on board quality and final product yield. PCB Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC converter IC, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or degraded performance of the converter. Energy Efficiency Minimize resistive losses by using wide traces between the power components and doubling up traces on multiple layers when possible EMI By its very nature, any switching converter generates electrical noise. The circuit board designer’s challenge is to minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the LM3243, switches Ampere level currents within nanoseconds, and the traces interconnecting the associated components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is maintained within tolerable levels. To help minimize radiated noise: • Place the LM3243 switcher, its input capacitor, and output filter inductor and capacitor close together, and make the interconnecting traces as short as possible. • Arrange the components so that the switching current loops curl in the same direction. During the first half of each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3243 and the inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3243 by the inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing these loops so the current curls in the same direction prevents magnetic field reversal between the two halfcycles and reduces radiated noise. • Make the current loop area(s) as small as possible. Interleave doubled traces with ground planes or return paths, where possible, to further minimize trace inductances. To help minimize conducted noise in the ground-plane: • Reduce the amount of switching current that circulates through the ground plane: Connect the ground bumps of the LM3243 and its input filter capacitor together using generous component-side copper fill as a pseudoground plane. Then connect this copper fill to the system ground-plane (if one is used) by multiple vias located at the input filter capacitor ground terminal. The multiple vias help to minimize ground bounce at the LM3243 by giving it a low-impedance ground connection. To help minimize coupling to the DC-DC converter's own voltage feedback trace: • Route noise sensitive traces, such as the voltage feedback path (FB), as directly as possible from the switcher FB pad to the VOUT pad of the output capacitor, but keep it away from noisy traces between the power components. 18 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated LM3243 www.ti.com SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 To help minimize noise coupled back into power supplies: • Use a star connection to route from the VBATT power input to Switcher PVIN and to VBATT_PA. • Route traces for minimum inductance between supply pins and bypass capacitor(s). • Route traces to minimize inductance between bypass capacitors and the ground plane. • Maximize power supply trace inductance(s) to reduce coupling among function blocks. • Inserting a ferrite bead in-line with power supply traces can offer a favorable tradeoff in terms of board area, by attenuating noise that might otherwise propagate through the supply connections, allowing the use of fewer bypass capacitors. Manufacturing Considerations The LM3243 package employs a 16-bump (4x4) array of 0.24 mm solder balls, with a 0.4mm pad pitch. A few simple design rules will go a long way to ensuring a good layout. • Pad size should be 0.225 ± 0.02 mm. Solder mask opening should be 0.325 ± 0.02 mm. • As a thermal relief, connect to each pad with 9 mil wide, 6 mil long traces and incrementally increase each trace to its optimal width. Symmetry is important to ensure the solder bumps re-flow evenly. Refer to TI Application Note AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). LM3243 RF Evaluation Board Figure 25. Simplified LM3243 RF Evaluation Board Schematic Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 19 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 www.ti.com Figure 26. Top View of RF Evaluation Board with PAs DC-DC Converter Section Figure 27. Top Layer 20 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated www.ti.com LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 Figure 28. Board Layer 2 - FB, VDD, Additional Routing for PGND, PVIN Figure 29. Board Layer 2 - Switcher Detail Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 21 LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 www.ti.com Figure 30. Board Layer 4 - GND Plane VCC_PA Figure 31. Board Layer 5 - VBATT_SW Connection 22 Submit Documentation Feedback Product Folder Links: LM3243 Copyright © 2010–2013, Texas Instruments Incorporated www.ti.com VBATT Star Supply Connection LM3243 SNVS782B – OCTOBER 2010 – REVISED FEBRUARY 2013 Figure 32. Multiple Board Layers - VBATT Supply Star Connection VBATT Star Connection: It is critically important to use a ‘Star’ connection from VBATT supply to LM3243 PVIN and from VBATT to PA modules as implementing a ‘daisy chain’ supply connection may add noise to the PA output. Star connection at VBATT VBATT _ VIN DC-DC VIN + LM3243 VBATT_PA * + - VBATT_PA * + - *Proper decoupling on VBATT_PA is strongly recommended. Figure 33. VBATT Star Connection on VIN and VBATT_PA Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: LM3243 Submit Documentation Feedback 23 PACKAGE OPTION ADDENDUM www.ti.com 10-Jul-2013 PACKAGING INFORMATION Orderable Device LM3243TME/NOPB LM3243TMX/NOPB Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) (1) Drawing Qty (2) (3) ACTIVE DSBGA YFQ 16 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -30 to 90 & no Sb/Br) ACTIVE DSBGA YFQ 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -30 to 90 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Device Marking (4/5) S57 S57 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Samples Addendum-Page 1 www.ti.com TAPE AND REEL INFORMATION PACKAGE MATERIALS INFORMATION 25-Jun-2013 *All dimensions are nominal Device Package Package Pins Type Drawing LM3243TME/NOPB DSBGA YFQ 16 LM3243TMX/NOPB DSBGA YFQ 16 SPQ 250 3000 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 178.0 8.4 2.08 178.0 8.4 2.08 B0 (mm) 2.08 2.08 K0 (mm) 0.76 0.76 P1 (mm) 4.0 4.0 W Pin1 (mm) Quadrant 8.0 Q1 8.0 Q1 Pack Materials-Page 1 www.ti.com PACKAGE MATERIALS INFORMATION 25-Jun-2013 *All dimensions are nominal Device LM3243TME/NOPB LM3243TMX/NOPB Package Type DSBGA DSBGA Package Drawing Pins YFQ 16 YFQ 16 SPQ 250 3000 Length (mm) 210.0 210.0 Width (mm) 185.0 185.0 Height (mm) 35.0 35.0 Pack Materials-Page 2 YFQ0016xxx MECHANICAL DATA 0.600±0.075 D E TMD16XXX (Rev A) D: Max = 2.049 mm, Min =1.989 mm E: Max = 2.049 mm, Min =1.989 mm NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated

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