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MT6572 原理图

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Principle circuit for MT6572

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5 4 3 Project : MT6572 REF_SCH TOP LEVEL EMI x32 EMI Memory MCP D NFI NFI micro SD + hot-plug MSDC 4-bit MSDC1 ATV MT5193 MT6572 i2S NFC MT6605 C Camera Module Camera IF CAM (MIPI / Parallel) 2nd Camera Module Camera IF I2C i2C_0 LCD module LCD IF LCD (MIPI / Parallel) CTP controller I2C EINT i2C_1 B Motion Sensor I2C EINT ALS + PXS I2C EINT Magnetic sensor I2C EINT Gyro sensor I2C EINT Keypad A JTAG Debug port UART ABB USB 5 4 3 2 1 Celullar ANT BPI, APC FEM TX RX RF IQ D BSI ctrl MT6166 RX balun 26M_BB 26M_AUD 26M_CN DCXO ctrl 26M_CN 26M CONN IQ CONN ctrl MT6627 TCXO Connectivity ANT C 32K_BB RTC 32K MT6323 Headset (HPL, HPR, AU_VIN1) AUD I/F Audio Speech Class D/AB Receiver POWER AU_VIN0 B SPI BC1.1 Power Management Charger SIM2 SIM1 VIB SIM2 SIM1 USB 2.0 Charger BJT Battery A micro USB Title MT6572 Block diagram Size Document Number C MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 0 of 99 2 1 5 4 3 2 cap Close to BB IC cap Close to BB IC U101H C108 100nF VIO18_PMU DVDD18_MIPIRX DVSS18_MIPIRX AVDD28_DAC AVDD18_AP VTCXO_PMU VIO18_PMU Based on your system level design 1. use RTP AVDD18_AP = ext. 1.8V LDO DVDD18_MIPITX DVSS18_MIPITX DVDD18_PLLGP VIO18_PMU cap = 0.1uF 2. use AUXADC, no RTP D AVDD18_AP = VIO18 VIO18_PMU VUSB_PMU AVDD18_USB AVDD18_MD AVSS18_MD VIO18_PMU cap = 0.1uF (NC) C113 AVDD33_USB AVSS33_USB AVSS18_MD AVSS18_MD AVSS18_MD C128 100nF 3. no use AUXADC, no RTP AVDD18_AP = VIO18 1uF C112 cap = none (share with C112) 100nF 100nF 100nF C107 C101 C104 100nF REFP REFP BG (i.e : DO NOT use VIO18 when touch is RTP) C109 1uF REFN MT6572 MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 1 D dedicate VSS ball, must return to cap then to main GND: 1. REFN(G6) => C109 VIO_EMI 2. DVSS18_MIPIRX(U25) => C107 U101B 1.8V IO for DDR1 3. DVSS18_MIPITX(P25) => C101 1.2V IO for DDR2 VCCIO_EMI GND GND GND VCC Memory VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI C405 C406 If double-sided SMT, put C405 & C406 below BB. 100nF 100nF If single-sided SMT, put C405 & C406 around memory. GND C GND C GND GND GND DVDD Peripheral DVDD18_MC0 VIO18_PMU GND DVDD18_CAM GND DVDD18_VIO_1 GND DVDD18_VIO_2 GND GND DVDD18_VIO_3 DVDD18_LCD R119 GND 0R GND GND GND DVDD3_MC1 VMC_PMU C126 GND 1uF GND DVDD3_LCD GND GND DVDD28_BPI VIO28_PMU C121 GND C117 NC GND GND 1uF GND GND GND VCC CPU GND VCCK_CPU VCCK_CPU VCCK_CPU Close to BB IC, recommand < 150mil Based on your system level GND GND GND VCCK_CPU VCCK_CPU VCCK_CPU design , if better FM performance is needed on your system , GND GND GND VCCK_CPU VCCK_CPU VCCK_CPU please refer to FM desense performance enhance proposal GND VCCK_CPU GND VCCK_CPU GND VCCK_CPU GND VCCK_CPU GND VCCK_CPU GND B GND GND GND 120mil VPROC_PMU B GND GND GND VCC Core VCCK VCCK GND VCCK GND VCCK C106 10uF C102 10uF C103 10uF C111 4.7uF 2.2uF 2.2uF 1uF 1uF 1uF 1uF 100nF 100nF 100nF 100nF GND VCCK GND VCCK GND VCCK GND VCCK C136 C137 C119 C134 C120 C135 C114 C115 C118 C116 GND VCCK GND VCCK VSS VCCK VCCK VSS VSS VCCK VCCK Vproc remote sense : VSS VSS VCCK VCCK differential 4mil with good shielding, from the BB to PMIC VSS VCCK VCCK VCCK SH102 GND_VPROC_FB [3] VCCK 4mil - defferential - GND shielding VCCK VCCK SH101 VPROC_FB [3] VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK A VCCK A VCCK VCCK Dummy MT6572 MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 Title BB- Power Size Document Number C MT6572 REF PHONE Rev V1.0 Date: Friday, March 29, 2013 Sheet 1 of 99 5 4 3 2 1 5 4 3 2 1 U101A [6] RX_I_P [6] RX_I_N [6] RX_Q_P [6] RX_Q_N DL_I_P DL_I_N DL_Q_P DL_Q_N BPI_BUS0 BPI_BUS1 BPI_BUS2 BPI_BUS3 ASM_VCTRL_A [6] ASM_VCTRL_B [6] ASM_VCTRL_C [6] WG_GGE_PA_ENABLE [6] U101D D [6] TX_I_P [6] TX_I_N [6] TX_Q_P [6] TX_Q_N UL_I_P UL_I_N UL_Q_P UL_Q_N BPI_BUS4 BPI_BUS5 BPI_BUS6 BPI_BUS7 BPI_BUS8 BPI_BUS9 BPI_BUS10 EINT_HP [5] GPIO_ATV_EN [17] W_PA_B1_EN [6] GPIO_FLASH_EN [80] W_PA_B8_EN [6] Must be sure BPI_BUS4 & 5 is under 0.2*VDD28_BPI during booting (please refer to HW design notice V0.4) [3] AUD_MISO [3] AUD_CLK [3] AUD_MOSI [3] PMIC_SPI_MOSI [3] PMIC_SPI_MISO [3] PMIC_SPI_SCK [3,4] PMIC_SPI_CS AUD_DAT_MISO AUD_CLK_MOSI AUD_DAT_MOSI PMIC_SPI_MOSI PMIC_SPI_MISO PMIC_SPI_SCK PMIC_SPI_CSN reserve for JTAG debug R208 VIO18_PMU D VM0 VM1 BPI_BUS11 BPI_BUS12 BPI_BUS13 BPI_BUS14 BPI_BUS15 GPIO_GPS_LNA_EN [10] EINT_Mag [80] EINT_ALPXS [21] EINT_ACC [21] EINT_IRQ_NFC [15] [3,4] WATCHDOG [3,6] SRCLKENA [3] EINT_PMIC W ATCHDOG SRCLKENA EINTX [3] SIM1_SCLK NC_20K Normal : NC [6] TXBPI [6] WG_GGE_PA_VRAMP TXBPI APC VBIAS BSI_DATA2 BSI_DATA1 BSI_DATA0 BSI_EN BSI_CLK BSI-A_DAT2 [6] BSI-A_DAT1 [6] BSI-A_DAT0 [6] BSI-A_EN [6] BSI-A_CK [6] for NFC need default low [3] SIM1_SCLK [3] SIM1_SIO [3] SIM2_SCLK [3] SIM2_SIO SIM1_SCLK SIM1_SIO SIM2_SCLK SIM2_SIO JTAG : 20K Reserve R footprint for JTAG debugging MT6572 MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 MT6572 MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 U101E C [6] CLK1_BB CLK26M SYSTEM PWM PW M_A PW M_B EINT_CTP [12] C [3] CLK32K_BB CLK32K_IN Based on your system level design , if better desense performance is needed on your [3] RESETB SYSRSTB TESTMODE LCD Parallel LPD17 LPD16 LPD15 system , please refer to desense performance enhance proposal FSOURCE LPD14 LPD13 LPD12 LPD11 for NFC application [3] CHD_DP [3] CHD_DM CHD_DP BC 1.1 CHD_DM LPD10 LPD9 MC1_INS [18] SRCLKENAI [15] LPD8 GPIO_NFC_RST [15] U101G [14] USB_DM [14] USB_DP 90-ohm differential USB_VRT USB_DM USB_DP USB_VRT USB 2.0 LPD7 LPD6 LPD5 LPD4 GPIO_NFC_VENB [15] GPIO_AP_WAKE_NFC [15] [13] GPIO_CMPDN2 [13] GPIO_CMRST2 [13] GPIO_CMPDN [13] GPIO_CMRST CMPDN2 CMRST2 CMPDN CMRST MIPI_2nd_CAM Parallel 8-bit close to R203 5.1K BB [13,15,17] [13,15,17] [12,21] SCL_0 SDA_0 SCL_1 i2C SCL_0 SDA_0 SCL_1 LPD3 LPD2 LPD1 LPD0 MT6572 support JTAG from below : CMMCLK CMMCLK [13] [12,21] SDA_1 SDA_1 1. KP (recommand) [13] MIPI_RDN0 [13] MIPI_RDP0 100-ohm different[i1a3l] MIPI_RDN1 [13] MIPI_RDP1 [13] MIPI_RCN [13] MIPI_RCP [12] MIPI_TDN0 [12] MIPI_TDP0 100-ohm differentia[1l2] MIPI_TDN1 [12] MIPI_TDP1 B [12] MIPI_TCN [12] MIPI_TCP RDN0 RDP0 RDN1 RDP1 RCN RCP MIPI_CAM TDN0 TDP0 TDN1 TDP1 TDN2 TDP2 TCN TCP MIPI_LCD CMPCLK RCN_A RCP_A RDN1_A RDP1_A RDN0_A RDP0_A CMDAT3 CMDAT2 CMDAT1 CMDAT0 CMPCLK [13,17] CMVSYNC [13,17] CMHSYNC [13,17] CMDAT7 [13,17] CMDAT6 [13,17] CMDAT5 [13,17] CMDAT4 [13,17] CMDAT3 [13,17] CMDAT2 [13,17] CMDAT1 [13,17] CMDAT0 [13,17] [17] SPI_MOSI [17] SPI_SCK [17] SPI_CSB [18] MC1CMD [18] MC1CK [18] MC1DAT0 [18] MC1DAT1 [18] MC1DAT2 [18] MC1DAT3 SPI_MISO SPI_MOSI SPI SPI_SCK SPI_CS MC1_CMD T-flash KP MC1_CK MC1_DAT0 MC1_DAT1 MC1_DAT2 MC1_DAT3 LPCE0B LPTE LRSTB LPRDB LPA0 LPW RB KROW 0 KROW 1 KROW 2 KCOL0 KCOL1 KCOL2 EINT_GY [80] LPTE [12] GPIO_LRSTB [12] GPIO_FLASH_SEL [80] GPIO_TV_RST [17] GPIO_CTP_RSTB [12] KCOL0 [20] KCOL1 [20] 2. MC1 3. CAM for JTAG pin out from MC1/CAM, refer to HW design notice JTMS JTCK TP205 TP206 B R202 1.5K close to BB MIPI_VRT VRT MT6572 MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 AUX_IN0 AUX_IN1 ADC AUX_IN2_XP AUX_IN3_YP AUX_IN4_XM AUX_IN5_YM UART UTXD1 URXD1 UTXD2 URXD2 UTXD1 URXD1 UTXD2 URXD2 TP201 TP202 UART1 : MD UART TP204 UART2 : AP UART TP203 MT6572 MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 VCAMD_IO_PMU R204 2.2K [13,15,17] SCL_0 [13,15,17] SDA_0 R205 2.2K Power by CAM_IO A VIO18_PMU A R206 2.2K R207 2.2K [12,21] SCL_1 [12,21] SDA_1 Power by CTP, MEMS sensor Title BB - peripheral Size Document Number C MT6572 REF PHONE Rev V1.0 Date: Friday, March 29, 2013 Sheet 2 of 99 5 4 3 2 1 5 4 3 2 Before you select BJT , please take power dissipation into consideration. Refer to MT6323 design notice Charger 1. Close to Battery Connector. VBUS (Rsense (R328) <10mm) 2. Main path should be 40mil. (VBUS -> U303's E, -> U303's C -> R328 -> VBAT) D 3. Star connection from R328 to BAT Connector 330K(1%) cap rating depends on Phone OVP spec. C329 1uF(25V) C0603 R329 330K 40mils R324 39K 39K(1%) VCDT VCDT rating: 1.268V 3.3K R331 3.3K CHR_LDO C 40mils C E U303 STT818B if you use digital MIC, please change cap (C312) to 1.0uF VBAT MICBIAS0 C312 100nF C313 2.2uF MICBIAS1 U301 MT6323 MT6323/VFBGA145/P0.4/B0.25/5.8X5.8 VBAT_SPK GND_SPK AU_MICBIAS0 AU_MICBIAS1 SPK_P SPK_N AU_HSP AU_HSN AU_HPL AU_HPR AU_SPKP [5] AU_SPKN [5] AU_HSP [5] AU_HSN [5] AU_HPL [5] AU_HPR [5] Based on your system level design , if lower LX voltage swing is needed on your system, please refer to Buck LX voltage swing enhance proposal C C B 40mils 40mils 4mil U305 SSM3K35MFV VDRV VA_PMU C314 1uF [5] AU_VIN0_P [5] AU_VIN0_N [5] AU_VIN1_P [5] AU_VIN1_N [96] AU_VIN2_P [96] AU_VIN2_N AU_VIN0_P AUDIO AU_VIN0_N AU_VIN1_P AU_VIN1_N AU_VIN2_P AU_VIN2_N AVDD28_ABB DRIVER ISINK0 ISINK1 ISINK2 ISINK3 iSINK0 [12] iSINK1 [12] iSINK2 [12] iSINK3 [12] Please use inductor recommand by MTK Refer to MT6323 design notice Rsense R328 0.2R Differential ISENSE BATSNS AVDD28_AUXADC GND_ABB BATTERY 40mils R0805 4mil SH302 AUXADC_REF AUXADC_REF [6] ISENSE/BSTSNS 4mil [5] ACCDET [6] CLK4_Audio ACCDET CLK26M BUCK OUTPUT VPROC VPROC VPROC VPROC_SW 0.68uH L301 0.68uH L/IND/SMD/2520 VPROC_PMU CONNECTOR C CON301 R334 16.9K 16.9K(1%) 80mils from battery connector to MT6323 chip differential to Rsense BATSNS ISENSE BAT_ON VCDT VDRV BATSNS ISENSE BAT_ON VCDT VDRV CHARGER BATSNS ISENSE BATON VCDT VDRV VPROC_FB GND_VPROC_FB VPA VPA VPA_FB VPA_SW L304 2.2uH VPROC_FB [1] GND_VPROC_FB [1] VPA_PMU near-end cap C357 VBAT+ VBAT C / 2200 / nF / 0402 NC NTC R317 VBAT [6,12,15] BAT_ON CHR_LDO CHR_LDO CHRLDO 0.68uH L303 0.68uH GNDNC NC 27K(1%) R335 1K R334,R335 must to be close to C316 1uF R316 1K CONTROL SIGNAL VSYS VSYS_SW L/IND/SMD/2520 VSYS_PMU 27K PMIC AUXADC_REF pin NC [20] PWRKEY [2,4] WATCHDOG PWRKEY SYSRSTB KEIRAKU KBC13S3A2R BAT/SMD/KBC23S3D4XR/KEIRAKU Close to PMIC [2] RESETB [2] EINT_PMIC RESETB FSOURCE INT EXT_PMIC_EN ALDO OUTPUT VA VCN28 VA_PMU VCN_2V8_PMU VTCXO VTCXO_PMU VEMC_3V3_PMU PMU_TESTMODE VCAMA VCAMA_PMU [2] AUD_MOSI AUD_MOSI VCN33 VCN_3V3_PMU Based on your system level design , if better ESD performance is needed on your system, please refer to ESD performance enhance proposal if battery NTC is 10kohm, R334=16.9K, R335=27K if battery NTC is 47kohm, R334=61.9K, R335=100K Refer to MT6323 HW design notice TP301 [2] AUD_CLK [2] AUD_MISO [2,6] SRCLKENA FCHR_ENB FCHR_ENB [2] PMIC_SPI_SCK AUD_CLK AUD_MISO SRCLKEN FCHR_ENB SPI_CLK AVDD33_RTC DLDO OUTPUT VM VRF18 VRTC C355 1uF VM_PMU VRF18_PMU C354 100nF [2,4] PMIC_SPI_CS SPI_CSN VIO18 VIO18_PMU [2] PMIC_SPI_MOSI SPI_MOSI VIO28 VIO28_PMU Add Zenar Diode Place on the path from VBAT to IC (Battery connector VBAT 80mil 40mil 4mil (VPA no use) [2] PMIC_SPI_MISO SPI_MISO VBAT INPUT VBAT_VPROC VBAT_VPROC VBAT_VPROC VBAT_VPA VCN18 VCAMD VCAM_IO VEMC_3V3 VMC VCN_1V8_PMU VCAMD_PMU VCAMD_IO_PMU VEMC_3V3_PMU VMC_PMU or test point or IO connector) 500mW C310 15mil 20mil 20mil 20mil VBAT_VSYS VBAT_LDOS3 VBAT_LDOS3 VBAT_LDOS2 VBAT_LDOS1 VMCH VUSB VSIM1 VSIM2 VGP1 VMCH_PMU VUSB_PMU VSIM1_PMU VSIM2_PMU D302 D / UDZS 5.1B SOD323/SMD/MM3Z2V4T1 10uF VSYS_PMU 20mil C323 AVDD22_BUCK AVDD22_BUCK VIBR VGP2 VGP3 VCAM_AF VIBR_PMU VCAM_AF_PMU VF : 4.85V~5.36V VIO18_PMU DVDD18_DIG_PMIC 100nF C323 must to be close to PMIC DVDD18_DIG DVDD18_IO Between IC and IO port B Refer to MT6323 design Based on your system level design , if better EOS performance is needed on your system, please refer to EOS performance enhance proposal 10uF 10uF NC_1uF 10uF 10uF 1uF 1uF [6] AUXADC_TSX [6] AUXADC_REF AUXADC_REF AUXADC_TSX [6] GND_AUXADC GND_AUXADC C322 100nF C322 must to be close to PMIC AUXADC_AUXIN_GPS pin [2] CHD_DM [2] CHD_DP AUXADC AUXADC_VREF18 AUXADC_AUXIN_GPS AVSS28_AUXADC BC 1.1 CHG_DM CHG_DP VREF GND_VREF VREF C320 100nF dedicate VSS ball, must return to cap then to main GND: 1. GND_VREF(N14) => C320 notice for Zener selection Refer to MT6323 design notice C301 C303 C304 C306 C309 C307 C308 SH301 Connect TSX/XTAL GND to AUXADC_GND first than connect to main GND refer to system analog LDO performance improve proposal [2] SIM1_SCLK [2] SIM1_SIO [2] SIM2_SCLK [2] SIM2_SIO [19] SCLK [19] SIO [19] SRST [19] SCLK2 [19] SIO2 [19] SRST2 GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO SIM LVS SIM1_AP_SCLK SIMLS1_AP_SIO SIM1_AP_SRST SIM2_AP_SCLK SIMLS2_AP_SIO SIM2_AP_SRST SIMLS1_SCLK SIMLS1_SIO SIMLS1_SRST SIMLS2_SCLK SIMLS2_SIO SIMLS2_SRST RTC RTC_32K1V8 RTC_32K2V8 XIN XOUT GND_ISINK GND_VSYS GND_VPA GND_VPROC GND_VPROC GND_VPROC GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO CLK32K_BB [2] 32K_IN 32K_OUT RTC 32K : X301+C324+C319=> mount, R333=> NC 32K-less: X301+C324=> remove, C319+R333=> 0R X301 SSP-T7-F C324 18pF SSP-T7 C319 18pF Close to chip R333 NC DCXO_32K [6] RTC for Buck GND layout rule VRTC C318 A 100nF R312 1K Refer to GPS co-clock layout rule C325 22uF ==> for longer RTC time sustain after battery remove, please refer to RTC design notice 5 4 3 2 1 D C B Vibra VIBR_PMU + C311 1uF - VIB301 Vibrator A Title PMIC Size Document Number Rev D MT6572 REF PHONE V1.0 Date: Monday, March 25, 2013 Sheet 3 of 99 1 5 4 3 2 1 [2,3] PMIC_SPI_CS HW trapping PIN R403 20K: VM=1.8V 20K NC : VM=1.2V U101F D ED31 ED30 ED31_(DDR1) ED30_(DDR1) ECS0_B_(DDR1) ECS0_B D ED29 ED29_(DDR1) ECS1_B_(DDR1) ECS1_B ED28 ED28_(DDR1) ED27 ED26 ED27_(DDR1) ED26_(DDR1) EW R_B_(DDR1) ERAS_B_(DDR1) EWR_B ERAS_B ED25 ED24 ED23 ED25_(DDR1) ED24_(DDR1) ED23_(DDR1) ECAS_B_(DDR1) ECKE_(DDR1) ECAS_B ECKE VM_PMU 0R R401 VIO_EMI Memory MCP ED22 ED21 ED22_(DDR1) ED21_(DDR1) EDQM0_(DDR1) EDQM1_(DDR1) EDQM0 EDQM1 ED20 ED19 ED20_(DDR1) ED19_(DDR1) EDQM2_(DDR1) EDQM3_(DDR1) EDQM2 EDQM3 ED18 ED17 ED18_(DDR1) ED17_(DDR1) EDQS0_(DDR1) EDQS0 ED16 ED15 ED14 ED16_(DDR1) ED15_(DDR1) ED14_(DDR1) EDQS1_(DDR1) EDQS2_(DDR1) EDQS3_(DDR1) EDQS1 EDQS2 EDQS3 ED13 ED13_(DDR1) ED12 ED11 ED12_(DDR1) ED11_(DDR1) EDQS0_B EDQS1_B VIO_EMI ED10 ED9 ED10_(DDR1) ED9_(DDR1) EDQS2_B EDQS3_B U401 ED8 ED8_(DDR1) ED7 ED7_(DDR1) EDCLK0_B ED6 ED6_(DDR1) EDCLK0 EDCLK_B EDCLK C401 4.7uF VDDQ VDDQ VDDQ CLK CLK# CKE0 EDCLK EDCLK_B ECKE ED5 ED4 ED3 ED5_(DDR1) ED4_(DDR1) ED3_(DDR1) EDCLK1_B EDCLK1 for DDR1 : AA19+Y19 must NC for DDR2 : AA18+Y18 must NC Put C402 & C403 between BB & memory. ED2 ED2_(DDR1) VDDQ VDDQ VDDQ VDDQ CS0# RAS# CAS# W E# ECS0_B ERAS_B ECAS_B EWR_B ED1 ED1_(DDR1) VDDQ BA0 EBA0 ED0 ED0_(DDR1) ND0_(DDR1) NLD0 ND1_(DDR1) NLD1 C402 100nF VDDQ VDDQ BA1 DM0 EBA1 EDQM0 BA[1:0] = EA[15:14] (LPDDR1) VREF1 ND2_(DDR1) NLD2 C403 100nF DM1 EDQM1 VREF0 ND3_(DDR1) NLD3 VDDd DM2 EDQM2 ND4_(DDR1) NLD4 VDDd DM3 EDQM3 ND5_(DDR1) NLD5 VDDd DQS0 EDQS0 EA18_(DDR1) ND6_(DDR1) NLD6 VDDd DQS1 EDQS1 C EA17_(DDR1) ND7_(DDR1) NLD7 VDDd DQS2 EDQS2 C EA16_(DDR1) ND8_(DDR1) NLD8 VDDd DQS3 EDQS3 EBA1 EBA0 EA15_(DDR1) EA14_(DDR1) ND9_(DDR1) ND10_(DDR1) NLD9 NLD10 C129 1uF VSSd DQ0 ED0 BA[1:0] = EA[15:14] (LPDDR1) EA13 EA12 EA11 EA10 EA9 EA13_(DDR1) EA12_(DDR1) EA11_(DDR1) EA10_(DDR1) EA9_(DDR1) ND11_(DDR1) ND12_(DDR1) ND13_(DDR1) ND14_(DDR1) ND15_(DDR1) NLD11 NLD12 NLD13 NLD14 NLD15 C110 4.7uF VSSd DQ1 ED1 VSSd DQ2 ED2 VSSd DQ3 ED3 VSSd DQ4 ED4 VSSd DQ5 ED5 EA8 EA8_(DDR1) EA7 EA7_(DDR1) DQ6 ED6 VSSQ DQ7 ED7 EA6 EA6_(DDR1) EA5 EA5_(DDR1) NCEB_(DDR1) NCEB VSSQ DQ8 ED8 VSSQ DQ9 ED9 EA4 EA4_(DDR1) NW RB_(DDR1) EA3 EA3_(DDR1) NREB_(DDR1) NWRB NREB VSSQ VSSQ DQ10 DQ11 ED10 ED11 EA2 EA2_(DDR1) NCLE_(DDR1) EA1 EA1_(DDR1) NALE_(DDR1) EA0 EA0_(DDR1) NRNB_(DDR1) NCLE NALE NRNB VSSQ VSSQ VSSQ VSSQ VSSQ DQ12 DQ13 DQ14 DQ15 DQ16 ED12 ED13 ED14 ED15 ED16 ERESET NW PB_(DDR1) DQ17 ED17 EA0 A0 DQ18 ED18 MT6572 MT6572_NAND_DDR1 MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 DO NOT use this pin, Please use WATCHDOG as write-protect signal @ NAND boot EA1 A1 DQ19 ED19 EA2 A2 DQ20 ED20 EA3 A3 DQ21 ED21 EA4 A4 DQ22 ED22 EA5 A5 DQ23 ED23 EA6 A6 DQ24 ED24 EA7 A7 DQ25 ED25 EA8 A8 DQ26 ED26 EA9 A9 DQ27 ED27 EA10 EA11 A10 DQ28 A11 DQ29 ED28 ED29 EA12 A12 DQ30 DQ31 ED30 ED31 DNU VIO18_PMU DNU NLD8 NLD8 DNU NLD9 NLD9 B Please make sure the ball map is DNU NLD10 NLD10 B VCCn NLD11 NLD11 match to the MCP type you selected C404 1uF VCCn VSSn VSSn NLD12 NLD13 NLD14 NLD12 NLD13 NLD14 NC NLD15 NLD15 For other memory pin mux, please refer to Design Notice "DDR1/DDR2 Pin Mux" ECKE ECS1_B NLD0 NC CKE1 NC NC CS1# NLD0 DNU NC NC A13 NC EA13 EA13 VIO18_PMU and "NAND/eMMC Pin Mux" NLD1 NLD2 NLD3 NLD4 NLD1 CLE NLD2 ALE NLD3 /CE NLD4 /RE NCLE NALE NCEB NREB R402 47K NLD5 NLD5 /W E NWRB NLD6 NLD6 /W P WATCHDOG [2,3] NLD7 NLD7 R/#B NRNB NC DNU NC DNU MT6572 QVL Memory A A Title Memory Size Document Number C MT6572 REF PHONE Rev V1.0 Date: Monday, March 25, 2013 Sheet 4 of 99 5 4 3 2 1 5 Speaker close to IC close to connector C501 33pF [3] AU_SPKP C502 100pF [3] AU_SPKN C503 D Based on your system level design , if better 33pF desense performance is needed on your system , please refer to desense performance enhance proposal Receiver close to IC close to connector [3] AU_HSP C506 33pF [3] AU_HSN C505 100pF C504 33pF Based on your system level design , if better TDD performance is needed on your system, please C refer to speech performance enhance proposal 4 3 2 1 SPK501 LOUD SPEAKER Earphone Audio same power domain close to IC close to connector VIO28_PMU R505 470K 470K R506 Reserve bead+C footprint for FM [2] EINT_HP 47K performance tuning D REC501 BEAD503 BLM18BD252SN1 C519 10uF [3] AU_HPL [3] AU_HPR BEAD504 BLM18BD252SN1 C520 10uF C530 NC 100R 100R R507 R508 C529 NC HP_MP3L HP_MP3R C521 33pF C522 33pF HP_MIC BEAD501 BEAD502 BEAD505 BLM18BD252SN1 BLM18BD252SN1 BLM18BD252SN1 EAR_DET VR505 VR0402 VR0402 CON501 EARJACK1 470R 470R 470R 470R RECEIVER Based on your system level design , if better ESD performance is needed on your system, please refer to ESD performance enhance proposal R509 R510 FM_ANT [10] L502 100nH SH503 C FM_RX_N_6572 [10] Handset Microphone 1 Earphone MICPHONE MICBIAS1 GND of C(4.7uF) and headset 100nF C511 MICBIAS0 R514 1K R515 1.5K Close to BB Close to MIC Analog MIC [3] AU_VIN1_N Close to BB C523 100nF Close to MIC AU_VIN1_N1 C526 33pF C525 100pF R511 1K C531 should tie together and single via to GND plane 4.7uF Close to EarJack R512 1.5K [3] AU_VIN0_P [3] AU_VIN0_N 100nF C512 C513 4.7uF C508 100pF MIC1 Microphone [3] AU_VIN1_P C524 100nF C527 33pF HP_MIC together then single B R516 1.5K R513 via to main GND 1K C510 C509 [3] ACCDET 33pF 33pF Single via to GND plane B R517 1K together then single via to main GND A A Title Audio Size Document Number C MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 5 of 21 5 4 3 2 1 5 4 3 2 1 SKY77590 control logic table Enable VctC VctB VctA LB_GMSK_TX HLLH HB_GMSK_TX HLHH LB_EDGE_TX HHLH HB_EDGE_TX HHHH TRX1 LHLL TRX2 LHHL TRX3 LHLH D TRX4 LHHH TRX5 LLHL TRX6 LLLH C VPA_PMU VBAT R622 R / NC / 0603 VBAT W_PA_VCC C631 C / 2200 / nF / 0402 VBATT VBAT VBAT_RF VBAT VBAT [3,12,15] B BPI0~4 and 10~11 are 2G+3G mode both BPI5~9 and 12~14 are 3G mode only (suggest BPI5~9 = 1.8V) [2] ASM_VCTRL_A [2] ASM_VCTRL_B [2] ASM_VCTRL_C [2] WG_GGE_PA_ENABLE [2] W_PA_B1_EN ASM_VCTRL_A [2] ASM_VCTRL_B [2] ASM_VCTRL_C [2] WG_GGE_PA_ENABLE [2] W_PA_B1_EN [2] [2] W_PA_B8_EN W_PA_B8_EN [2] VM1 VM0 [2] WG_GGE_PA_VRAMP VM1 VM0 WG_GGE_PA_VRAMP [2] [3] DCXO_32K DCXO_32K [3] VTCXO_PMU VRF18_PMU R633 R / 0 / ohm / 0402 R634 R / 0 / ohm / 0402 VTCXO28-1 VRF18-1 VIO18_PMU [2] BSI-A_EN [2] BSI-A_CK [2] BSI-A_DAT0 [2] BSI-A_DAT1 [2] BSI-A_DAT2 BSI-A_EN [2] BSI-A_CK [2] BSI-A_DAT0 [2] BSI-A_DAT1 [2] BSI-A_DAT2 [2] A [2] TXBPI [2,3] SRCLKENA [2] [10] [15,17] [3] CLK1_BB SYSCLK_WCN CLK3_ATV CLK4_Audio TXBPI [2] ENBB [2,3] CLK_SEL [2,3] CLK1_BB [2] CLK2_WCN [10] CLK3_ATV [15,17] CLK4_Audio [3] [2] RX_Q_P [2] RX_Q_N [2] RX_I_N [2] RX_I_P RX_BBQP [2] RX_BBQN [2] RX_BBIN [2] RX_BBIP [2] [2] TX_Q_P [2] TX_Q_N [2] TX_I_N [2] TX_I_P TX_BBQP [2] TX_BBQN [2] TX_BBIN [2] TX_BBIP [2] 5 GGE_PA_HB_IN GGE_PA_LB_IN [2] ASM_VCTRL_A [2] ASM_VCTRL_B [2] ASM_VCTRL_C [2] WG_GGE_PA_ENABLE C606 C / 18 / pF / 0402 R603 R / 0 / ohm / 0402 R607 R / NC / 0402 R605 R / NC / 0402 C607 C / 56 / pF / 0402 R609 R / 0 / ohm / 0402 R610 R / NC / 0402 R611 R / NC / 0402 R / 1 / K / 0201 R / 1 / K / 0201 R606 R602 VBATT C611 C / 22 / pF / 0201 C612 C / 22 / pF / 0201 R608 R / 1 / K / 0201 R615 R / 1 / K / 0201 TX_HB_IN TX_LB_IN BS2 BS1 VBATT VCC C604 C613 C / 22 / pF / 0201 C614 C / 22 / pF / 0201 [2] WG_GGE_PA_VRAMP R612 R / 10 / K / 0201 R613 R / 24K / 0201 C608 C / 220 / pF / 0201 B1_CPL_IN B8_CPL_IN R628 R / 51 / ohm / 0201 B1_CPL_OUT C637 C / 10 / uF / 0603 C625 C / 10 / uF / 0603 C615 C / 100 / nF / 0402 C / 22 / pF / 0402 GND MODE TxEN VRAMP TRX_1 TRX_2 TRX_3 TRX_4 GND GND GND GND GND GND GND GND SKY77590 U601 PA / SKY77590 GND GND GND ANT GND TRX_6 TRX_5 R / 51 / ohm / 0201 R616 TRXB8 R / 51 / ohm / 0201 R618 TRXB1 2G_LB 2G_HB EDGE TXM ASM_ANT_3 R620 R / 0 / ohm / 0402 C610 C / NC / 0402 ASM_ANT_2 C609 C / 39 / pF / 0402 ASM_ANT_1 C624 L / 39 / nH / 0402 CON600 Car_Kit / MM8430-2610 ASM_ANT2 W_PA_B1_IN VM1 VM0 C626 C / 18 / pF / 0402 R617 R / 0 / ohm / 0402 R619 R / NC / 0402 B1_CPL_IN [2] W_PA_B1_EN WCDMA_Band1_PA C683 C / 1.5 / nF / 0402 C694 C / 1 / uF / 0402 VBAT_RF W_PA_VCC C693 C / 1.5 / nF / 0402 C671 C / NC / nF / 0402 VMODE_0 VMODE_1 VCC1 VCC2 RF_IN CPL_IN VEN RF_OUT U605 RF7241 CPL_OUT GND GND R661 R / NC / 0201 C627 L / 1 / nH / 0402 W_PA_OUT_B1 C629 C / NC / 0402 C630 NC_C / 0.5 / pF / 0402 B1_CPL_OUT 3G_PA_CPL_OUT PDET B8_CPL_OUT R629 R / 26 / ohm / 0402 R630 R / 26 / ohm / 0402 R632 R / 35 / ohm / 0402 3G_PA_CPL_OUT WCDMA_Power Detector VM1 VM0 C680 C / 1.5 / nF / 0402 W_PA_B8_IN C602 C647 C / 56 / pF / 0402 R / 0 / ohm / 0402 C619 C681 C / 120 / pF / 0402 VMODE_0 VMODE_1 VCC1 VCC2 C / NC / 0402 B8_CPL_IN [2] W_PA_B8_EN RF_IN CPL_IN VEN RF_OUT U609 RF7248 CPL_OUT C636 C / 1 / uF / 0402 VBAT_RF W_PA_VCC C635 C / NC / nF / 0402 C646 L/ 1 / nH / 0402 C649 L / 22/ nH / 0402 C650 W_PA_OUT_B8 C / NC / 0402 GND GND WCDMA_Band8_PA B8_CPL_OUT Antenna matching, depends on antenna design C618 C / NC / 0402 L605 C623 C / NC / 0402 ANT602 ANT / 1.7mmX2.9mm R / 0 / ohm / 0402 D ANT603 ANT / 1.7mmX2.9mm ANT604 ANT / 1.7mmX2.9mm GND_SIGNAL [17] VBAT VBAT [3,12,15] GND_SIGNAL [17] L620 L / NC / nH / 0402 L621 L / NC / nH / 0402 C662 C / 4.3 / pF / 0402 C663 C / NC / pF / 0402 L617 L / 4.3 / nH / 0402 C664 C / 4.3 / pF / 0402 G G G U611 SAYRF1G95HN0F0A TX ANT RX RX G G W_PA_OUT_B1 L606 R / 0 / ohm / 0402 L601 L / 2 / nH / 0402 TRXB1 C603 C / NC / 0402 C WCDMA_Band1_Rx 3GB8_RXN L613 L / NC / 0402 3GB8_RXP C661 L / 1.8 / nH / 0402 L612 L / 33 / nH / 0402 C658 L / 1.8 / nH / 0402 WCDMA_Band8_Rx G RX RX TX ANT U612 SAYFH897MHA0F00 G G G G C660 L / 1 / nH / 0402 L / 9.1 / nH / 0402 C659 L614 L / 27 / nH / 0402 TRXB8 W_PA_OUT_B8 W_PA_B1_IN 2G_Rx L600 L / 12 / nH / 0402 LB_RX_P W_PA_B8_IN GGE_PA_LB_IN GGE_PA_HB_IN L627 L / 2 / nH / 0201 2G_LB 2G_HB C600 C / 22 / pF / 0402 C667 C / 22 / pF / 0402 L618 L / 2.2/ nH / 0402 C665 C / NC / pF / 0402 L622 C666 C / NC / pF / 0402 L / 3 / nH / 0402 C668 C / NC / pF / 0402 C670 C / 1.5 / pF / 0402 Z600 Balun / RFBLN2012090BM5T25 GND LBin LBout GND LBout GND HBout HBin HBout GND L615 L / NC / 0402 L619 L / 12 / nH / 0402 L623 L / 6.2 / nH / 0402 L624 L / NC / 0402 L626 L / 6.2 / nH / 0402 L616 L / 39 / nH / 0402 LB_RX_N HB_RX_P L625 L / 7.5 / nH / 0402 HB_RX_N VRF18-1 VTXHF_VRF18 C669 C / 470 / nF / 0402 / X5R B DET PDET 3GH1_B8_TX 2GLB_TX 2GHB_TX 3GH1_B1_TX 3GB8_RXP 3GB8_RXN 3GB1_RXP 3GB1_RXN U600 GND GND GND GND GND 3GB1_RXP 3GB1_RXN 3GB5_RXP 3GB5_RXN 3GB2_RXP 3GB2_RXN 3GB8_RXP 3GB8_RXN 2GHB_TX 3GH1_TX 3GH2_TX 3GL5_TX 2GLB_TX VTXHF DET GND GND GND GND GND GND GND Two Application Circuit Conditions, 1.TSX Circuit : X600=TSX, R653=R656=NC, R654=100K+-1%, R655=R657=0ohm 2.XTAL Circuit :X600=Mobile XTAL, R653=R656=0ohm, R654=R655=R657=NC LB_RX_P 2GLB_RXP Route AUXADC_REF with 4mil trace width [3] AUXADC_REF C685 C / 1000 / nF / 0402 connect to main GND R654 NC / 100K / 1% / 0402 R656 VRF18-1 R / 0 / ohm / 0402 LB_RX_N 2GLB_RXN HB_RX_P 2GHB_RXP HB_RX_N 2GHB_RXN VRXHF_VRF18 C675 C / 470 / nF / 0402 / X5R XTAL1 Route AUXADC_TSX with 4mil trace width [3] AUXADC_TSX R657 R / NC / 0402 GND X600 HOT XTAL2 Route AUXADC_GND with 24mil trace width under AUXADC_REF/AUXADC_TSX trace [3] GND_AUXADC Connect TSX/XTAL GND to GND_AUXADC first than connect to main GND Close to each other and nearby X600 R655 R / NC / 0402 R653 R / 0 / ohm / 0402 MT6166 QVL 26M HOT GND VTCXO28-1 R646 R / 0 / ohm / 0402 C677 C / 470 / nF / 0402 / X5R VTCXO28_IC DCXO_32K_EN EN_BB CLK_SEL XO3 GND GND GND GND GND GND FDD RX TXO GND GND GND GND GND GND B40_RXP DETGND B40_RXN TMEAS LB_RXP LB_RXN TDD RX V28 3GTX_IP HB_RXP HB_RXN VRXHF RFVCO_MON MT6166 TX(I/Q) 3GTX_IN 3GTX_QP 3GTX_QN TXVCO_MON XTAL1 MT6166/VFBGA104/P0.4/B0.25/4.6X4.6 VTXLF XTAL2 XO VTCXO28 32K_EN Test pin TXBPI RCAL TST2 EN_BB CLK_SEL 26M output XO3 BSI TST1 BSI_DATA2 BSI_DATA1 TMEAS 3GTX_IP 3GTX_IN 3GTX_QP 3GTX_QN V28 TX_BBIP [2] TX_BBIN [2] TX_BBQP [2] TX_BBQN [2] VTXLF_VRF18 C / 470 / nF / 0402 / X5R TX_BPI RCAL C676 TXBPI [2] BSI_DATA[2] BSI_DATA[1] BSI-A_DAT2 [2] BSI-A_DAT1 [2] VTCXO28-1 C674 C / 470 / nF / 0402 / X5R R639 R / 0 / ohm / 0201 VRF18-1 R645 NCP15WF104F03RC R610 close to 3G PA R600 R / 2 / K / 0201 / 1% GND GND GND GND GND GND XO4 XO2 XO1 OUT32K XMODE AVDD_VIO18 VXODIG VRXLF RX_IP RX_IN RX_QP RX_QN BSI_EN BSI_CLK BSI_DATA0 GND GND GND GND GND GND Route AUXADC_REF/AUXADC_TSX as differential trace with well GND shielding and route AUXADC_GND with 24mil trace width under connect to main GND [2,3] ENBB GND GND GND GND RX(I/Q) GND GND GND GND AUXADC_TSX/AUXADC_REF trace to provide return current path. [2,3] CLK_SEL [15,17] CLK3_ATV MT6166 A R647 R / 0 / ohm / 0201-3P(1-2) RX_QP RX_QN MODE Logic DCXO_ 32K_EN XMODE VXODIG DCXO + 32K XO 0(GND) 1(VIO18) 1(VIO18) DCXO + 32K-Less 1(VTXCO28) 1(VTXCO28) 1(VTXCO28) VTCXO28-1 DCXO_32K_EN VIO18_VGPIO VTCXO28-1 R649 R / 0 / ohm / 0201-3P(1-2) XMODE VIO18_VGPIO VTCXO28-1 R648 R / 0 / ohm / 0201-3P(1-2) VXODIG [3] CLK4_Audio [10] CLK2_WCN [2] CLK1_BB [3] DCXO_32K XMODE R650 R / NC / 0201 VIO18_PMU VXODIG XO4 XO2 XO1 DCXO_32K L630 R / 0 / ohm / 0402 C682 C / 1000 / nF / 0402 Reserved LC filter VIO18_VGPIO VRXLF_VRF18 [2] RX_BBIP RX_IP RX_IN BSI_DATA[0] BSI_CLK BSI_EN BSI-A_DAT0 [2] BSI-A_CK [2] BSI-A_EN [2] RX_BBQP [2] RX_BBQN [2] RX_BBIN [2] C / 470 / nF / 0402 / X5R C684 VRF18-1 Title RF-2G Size Document Number A1 MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 6 of 99 4 3 2 1 5 D 4 3 2 1 U101C GPS_RX_IN GPS_RX_IP GPS_RXIN GPS_RXIP GND_WBG GND_WBG GND_WBG GPS_RX_QN GPS_RX_QP GPS_RXQN GPS_RXQP GND_WBG GND_WBG GND_WBG GND_WBG W B_TXIN W B_TXIP WB_TXIN WB_TXIP GND_WBG GND_WBG GND_WBG W B_TXQN GND_WBG W B_TXQP WB_TXQN GND_WBG WB_TXQP GND_WBG W B_RXIN GND_WBG D W B_RXIP WB_RXIN WB_RXIP W B_CTRL0 W B_RXQN CONN_WB_CTRL0 W B_CTRL1 U1006 W B_RXQP WB_RXQN CONN_WB_CTRL1 W B_CTRL2 R1013 OUT VCC VCN_2V8_PMU WB_RXQP CONN_WB_CTRL2 CONN_WB_CTRL3 W B_CTRL3 W B_CTRL4 0R CONN_WB_CTRL4 W B_CTRL5 GND NC C1022 CONN_WB_CTRL5 CONN_XO_IN MT6627 QVL TCXO 1uF SYSCLK_WCN [6] AVDD18_W BG AVDD18_WBG CONN_RSTB CONN_SEN CONN_SDATA CONN_SCLK CONN_F2W_DAT CONN_F2W_CLK CONN_RSTB CONN_SEN CONN_SDATA CONN_SCLK FM_DATA FM_CLK CONN_XO_IN CONN_XO_IN MT6572 MT6572/TFBGA428/P0.4/B0.25/10.6X10.6 WIFI/BT/GPS Single ANT Ref. Feed 1 Feed 1 G G G ANT1004 ANT1003 C 101266-1 101266-1 R1007 0R 50 Ohm C1042 NC 50 Ohm R1006 50 Ohm 0R L1004 NC CON1001 Car_Kit / MM8430-2610 50 Ohm R1023 NC Same pad F1002 GND WiFi 50 Ohm C1043 NC ANT GND GND GPS 50 Ohm DP1608-V1524CA C1044 18pF GPS_RF_LNA W B_CTRL4 W B_CTRL5 U1000 Optional: L1004 for better ESD performance B Based on your system level design , if better GPS performance is needed on your system, please refer to GPS performance enhance proposal FM [5] FM_RX_N_6572 [5] FM_ANT Based on your system level design , if better WiFi TX performance is needed on your system, please refer to WiFi performance enhance proposal L1011 82nH L1012 NC FM_LANT_N FM_LANT_P W BG_ANT GPS_RF R1016 0R 50 Ohm 50 Ohm AVDD33_W B WB_GPS_RF_IN GPS_DPX_RFOUT AVDD33_WBT 50 Ohm AVDD28_FM NC NC AVDD28_FM FM_LANT_N R1010 Same pad GPS_RFIN 50 Ohm 0R R1015 NC AVDD18_GPS FM_LANT_P GPS_RFIN AVDD18_GPS DVSS GPS VCN_2V8_PMU R1019 NC Close to ANT C1051 CONN_RSTB U1010 1uF A 50 OhmGPS_RF_LNA C1037 L1006 GNDRF VCC GPS_ANT FM_DATA IN OUT AI AO 50 Ohm 18pF U1005 7.5nH PON GND FM_CLK C1050 NC BGA725L6 SAFEB1G57KE0F00 Infineon LNA CONN_SCLK R1020 NC GPIO_GPS_LNA_EN [2] CONN_SDATA CONN_SEN 5 4 3 AVDD28_FSOURCE HRST_B FM_DBG F2W_DATA F2W_CLK SCLK SDATA SEN CEXT XO_IN W_LNA_EXT AVDD18_WBT AVDD18_WB WB_CTRL5 WB_CTRL4 MT6627 MT6627-NS/MQFN40/SMD/P0.4/5X5 WB_CTRL3 WB_CTRL2 WB_CTRL1 WB_CTRL0 WB_RX_IP WB_RX_IN W B_CTRL3 W B_CTRL2 W B_CTRL1 W B_CTRL0 W B_RXIP W B_RXIN WB_RX_QP W B_RXQP WB_RX_QN W B_RXQN WB_TX_IP W B_TXIP WB_TX_IN W B_TXIN WB_TX_QP W B_TXQP WB_TX_QN W B_TXQN GPS_RX_IP GPS_RX_IP GPS_RX_IN GPS_RX_IN GPS_RX_QP GPS_RX_QP GPS_RX_QN GPS_RX_QN MT6627 SMD QFN40 1uF 100pF CONN_XO_IN C1012 C1011 2 Close to MT6572 AVDD18_W BG SH1001 C1001 100nF C VCN_1V8_PMU AVDD18_W B AVDD18_GPS SH1002 SH1003 C1007 100nF C1008 100pF VCN_1V8_PMU VCN_1V8_PMU Star Conn for WB/GPS/WBG 1V8 C1005 4.7nF C1006 1uF B refer to FM desense performance enhance proposal AVDD28_FM C1002 10nF VCN_2V8_PMU Close to MT6627 AVDD33_W B C1004 100pF SH1004 C1003 2.2uF VCN_3V3_PMU C1009 2.2uF C1010 220nF A Title Wireless Connectivity Size Document Number A2 MT6572 REF PHONE Rev V1.0 Date: Friday, March 29, 2013 Sheet 10 of 99 1 5 4 3 VBAT VBAT [3,6,15] cap for iSINK BL flicking improve, close to LCM connector LCM CON1201 VBAT LCD_LEDK1 LEDK1 LEDA C1203 YU D 1uF XR YD XL VIO28_PMU VIO18_PMU LCD_LEDK8 VDD2 (AVDD) VDD1 (IOVDD) LEDK8 Based on your system level design , if better LCD uniformity is needed on your system , please refer to BL uniformity with iSINK improve proposal [2] LPTE [2] GPIO_LRSTB LCD_LEDK7 LCD_LEDK6 LCD_LEDK5 LCD_LEDK4 LCD_LEDK3 LCD_LEDK2 TE IM0 IM1 IM2 LANSEL RESETB LEDK7 LEDK6 LEDK5 LEDK4 LEDK3 LEDK2 [3] iSINK0 [3] iSINK1 [3] iSINK2 [3] iSINK3 C Based on your system level design , if better desense performance is needed on your system , please refer to desense performance enhance proposal LCD_LEDK1 LCD_LEDK8 LCD_LEDK2 LCD_LEDK3 LCD_LEDK4 LCD_LEDK5 LCD_LEDK6 LCD_LEDK7 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RDX W RX DCX CSX Based on your system level design , if better NC desense performance is needed on your NC NC system , please refer to desense NC NC performance enhance proposal GND [2] MIPI_TDP1 [2] MIPI_TDN1 100-ohm [2] MIPI_TCP [2] MIPI_TCN 100-ohm NC DSI_VSS DSI_D1P DSI_D1N DSI_VSS DSI_CLKP DSI_CLKN DSI_VSS DSI_D0P DSI_D0N DSI_VSS VDD3(NC) [2] MIPI_TDP0 [2] MIPI_TDN0 MT6572 DRL LCD B 0R YAGEO PN: YC102-FR-070R A 5 4 3 2 1 D CTP GT_DRV0 GT_DRV1 GT_DRV2 GT_DRV3 GT_DRV4 GT_DRV5 GT_DRV6 GT_DRV7 GT_DRV8 U1201 EP AGND DRV0 DRV1 DRV2 DRV3 DRV4 DRV5 DRV6 DRV7 DRV8 GT_SENS0 GT_SENS1 GT_SENS2 GT_SENS3 GT_SENS4 GT_SENS5 GT_SENS6 GT_SENS7 GT_SENS8 GT_SENS9 SENS0 Goodix GT968 DRV9 SENS1 DRV10 SENS2 DRV11 SENS3 DRV12 SENS4 DRV13 SENS5 DRV14 SENS6 DRV15 SENS7 DRV16 SENS8 NC SENS9 RSTB GT_DRV9 GT_DRV10 GT_DRV11 GT_DRV12 GT_DRV13 GT_DRV14 GT_DRV15 GT_DRV16 GPIO_CTP_RSTB [2] C AVDD28 AVDD18 DVDD12 DGND INT Sensor_OPT1 Sensor_OPT2 I2C_SDA I2C_SCL DVDDIO C1204 1uF DVDDIO_CTP C1207 1uF AVDD18_CTP DVDD12_CTP VIO28_PMU C1205 2.2uF C1206 2.2uF SCL_1 [2,21] SDA_1 [2,21] EINT_CTP [2] B GT_DRV9 GT_DRV10 GT_DRV11 GT_DRV12 GT_SENS0 GT_SENS1 GT_SENS2 GT_SENS3 GT_SENS4 GT_SENS5 GT_SENS6 GT_SENS7 GT_SENS8 GT_SENS9 GT_DRV16 GT_DRV15 GT_DRV14 GT_DRV13 GT_DRV8 GT_DRV7 GT_DRV6 GT_DRV5 GT_DRV4 GT_DRV3 GT_DRV2 GT_DRV1 GT_DRV0 CON1202 Panasonic AXT340124 A Title LCD, Touch Size Document Number C MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 12 of 99 2 1 5 4 3 2 Main CAM D C1301 1uF 2V8 VCAM_AF_PMU [2,15,17] SDA_0 [2,15,17] SCL_0 [2] GPIO_CMRST [2] GPIO_CMPDN CON1301 AGND STROBE SIOD SIOC RESETB PCLK VSYNC HREF PW DN DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 DGND AF_AGND AF_VCC PD AVDD INTD INTC DGND MDP1 MDN1 DGND MCP MCN DGND MDP0 MDN0 DGND XCLK DVDD DOVDD DGND C1302 2.2uF SDA_0 [2,15,17] SCL_0 [2,15,17] CMMCLK [2] 2v8 VCAMA_PMU Reserve cap footprint for better camera performance please refer camera power noise improve proposal 100-ohm Based on your system level design , if better desense performance is needed on your system , please refer to desense performance enhance proposal 100-ohm MIPI_RDP1 [2] MIPI_RDN1 [2] MIPI_RCP [2] MIPI_RCN [2] MIPI_RDP0 [2] MIPI_RDN0 [2] MT6572 DRL Camera C 1v2 VCAMD_PMU C1303 1uF C1310 1uF 1v8 VCAMD_IO_PMU only 150mA from VCAMD please check your CAM module DVDD current external LDO is required for DVDD current > 150mA Sub CAM CON1302 PW DN SUB_HSYNC GPIO_CMPDN2 [2] B HREF VSYNC SUB_VSYNC RESET GPIO_CMRST2 [2] DVDD DOVDD VCAMD_PMU VCAMD_IO_PMU AVDD VCAMA_PMU DGND PCLK SUB_PCLK DGND XCLK SUB_MCLK Based on your system level design , if better AGND SIO-D SIO-C D9 D8 D7 D6 D5 D4 D3 D2 D1 SUB_D7 SUB_D6 SUB_D5 SUB_D4 SUB_D3 SUB_D2 SUB_D1 SUB_D0 SDA_0 [2,15,17] SCL_0 [2,15,17] desense performance is needed on your system , please refer to desense performance enhance proposal SUB_HSYNC SUB_VSYNC SUB_PCLK [2] CMMCLK SUB_MCLK CMHSYNC [2,17] CMVSYNC [2,17] CMPCLK [2,17] D0 MT6572 DRL Camera SUB_D4 SUB_D5 SUB_D6 SUB_D7 CMDAT4 [2,17] CMDAT5 [2,17] CMDAT6 [2,17] CMDAT7 [2,17] A SUB_D0 SUB_D1 SUB_D2 SUB_D3 CMDAT0 [2,17] CMDAT1 [2,17] CMDAT2 [2,17] CMDAT3 [2,17] 5 4 3 2 1 D C B A Title Camera Size Document Number C MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 1 Sheet 13 of 99 5 4 3 GND0 GND1 USB HS IF D Based on your system level design , if better ESD performance is needed on your system, please refer to ESD performance enhance proposal [2] USB_DP [2] USB_DM C Based on your system level design , if better VBUS desense performance is needed on your system , please refer to desense performance enhance proposal CON1401 USBCONN1 GND ID D+ DVBUS GND3 GND2 B A 5 4 3 2 1 D C B A Title USB Size Document Number B MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 14 of 99 2 1 5 4 3 2 1 ANT1501 ANT / R2.2 ANT1502 ANT / R2.2 MT6605 will MP at 2013 6/E, R1503 R / 0 / ohm / 0402 ANT_N C / 47 / pF / 0402 C1511,C1512,C1513,C1514,C1515,C1516,C1517, C1518, please contact MTK support ANT_P C / 47 / pF / 0402 R1501 R / 0 / ohm / 0402 C1519 need to use 2% accuracy and 50V tolerance capacitor, C1511 D PS: 0201 cap can't tolerance 50V C1513 C1512 window for detail POWER MODE[1:0]=[NFC_RST:NFC_VENB] Power Mode NFC_RST NFC_VENB D C / NC / 0402 NFC enable (configure, R/W, card, C1514 C1515 polling loop, polling loop card 1 0 listening) C / 4.7 / pF/0402 C / 4.7 /pF/ 0402 NFC disable (HPD) 0 1 C1516 C1517 C / 56/ pF / 0402 C / 56 / pF / 0402 Hign battery card listening 1 1 C1518 C1519 Reset 0 0 C / 18 / pF / 0402 C / 18 / pF / 0402 C VSIM1_NFC VSIM1_PMU [19] SIM1_NFC_SWP1 R1521 R / 0 / ohm / 0402 DVDD_SIM1 R1517 Close R / 0 / ohm / 0402 DVDD_EPMU1 R1524 R / 0 / ohm / 0402 NFC_SWP1 VSIM2_NFC VSIM2_PMU [19] SIM2_NFC_SWP2 [18] MSDC_NFC_VCCSWP [18] MSDC_NFC_SWPIO R1522 R / 0 / ohm / 0402 DVDD_SIM2 R1518 Close R / 0 / ohm / 0402 DVDD_EPMU2 R1525 R / 0 / ohm / 0402 NFC_SWP2 R1520 R / 0 / ohm / 0402 R1523 R / 0 / ohm / 0402 NFC_VCCSWP NFC_SWPIO B VIO18_PMU R1516 R / 0 / ohm / 0402 VRTC VBAT SH1509 R1515 R / 0 / ohm / 0402 VBAT VBAT [3,6,12] DVDD_IO_NFC VRTC_NFC VBAT_NFC 1.8V IO domain [2] GPIO_AP_WAKE_NFC SH1501 [2] EINT_IRQ_NFC SH1502 [2] GPIO_NFC_RST SH1503 [2] GPIO_NFC_VENB SH1504 NFC_EINT NFC_IRQ NFC_RST NFC_VENB A [6,17] CLK3_ATV SH1505 NFC_CLK1 [2] SRCLKENAI [2,13,17] SCL_0 [2,13,17] SDA_0 SH1506 NFC_OSC_EN R1519 R / 0 / ohm / 040N2FC_I2C_SCL R1526 R / 0 / ohm / 040N2FC_I2C_SDA 5 RXIN_P TX_P TX_N RXIN_N C1524 C1520 C1521 C1523 R1504 6k C / 180 / pF / 0402 C / 180 / pF / 0402 C / 180 / pF / 0402 NC/C / 180 / pF / 0402 L1501 L1502 R1505 560nH/MLF1608DR56J 560nH/MLF1608DR56J NC/6k R1507 0 Components in this region use 5% accuracy VBAT_NFC U1501 ENB (NFC_VEN) 1.Input pin 2.Internal pull low 3.Low active 4.If default NFC would like to disable, please configure to high C1501 C / 2200 / nF / 0402 / X5R NFC_VENB C1502 close to pin19 C1502 C / 1000 / nF / 0402 / X5R C1503 C / 1000 / nF / 0402 / X5R C1505 C / 470/ nF / 0402 / X5R C1506 VRTC_NFC C / 100 / nF / 0402 / X5R C1504 DVDD_IO_NFC C / 1000 / nF / 0402 / X5R VBAT ENB AVDD_PA AVDD DVDD12 DVDD18 DVDD28 DVDD_IO MT6605 I2C address : 0X28 MT6605 QFN32 4x4 DVDD_SE SWIO_SE DVDD_EPMU1 DVDD_SIM1 SWIO1/GPIO6 DVDD_EPMU2 DVDD_SIM2 SWIO2 ANT_P RXIN_P TX_P TX_N RXIN_N ANT_N CLK_IN SYSRST_B MAIN_GND ANT_P RXIN_P TX_P TX_N RXIN_N ANT_N NFC_CLK1 C1510/R1502 are close to each other C1510 C / NC / 0402 R1502 R / 0 / ohm / 0402 X1501 QUARTZ 27.12 Mhz C NFC_RST SYSRST_B (NFC_RST) 1.Input pin 2.Internal pull high 3.Low active Test_Mode/GPIO1/OSC_EN/JTAG_TDO UART_TXD/I2C_DAT/SPI_CS UART_RXD/I2C_CK/SPI_CK SPI_MISO/GPIO2/JTAG_TMS/DBG_TXD SPI_MOSI/GPIO3/JTAG_TCK/DBG_RXD IRQ/GPIO4 EINT/GPIO5/JTAG_TDI GPIO0/JTAG_TRST NFC_OSC_EN NFC_I2C_SDA NFC_I2C_SCL R1506 R / 10 / K / 0402 (NC) 1.OSC_EN is output pin, and high active. 2.Need to connect to host SRCLKENAI pin and SRCLKENAI pin need default low Only can use HW I2C. SW I2C is not allowed. DVDD_IO_NFC R1506 NC : XTAL MODE R1506 10K : Co-Clock NFC_IRQ NFC_EINT B 1.IRQ is output pin, and is high active 2.IRQ is also strap pin and host I/F connected with IRQ need to be default low. MT6605/MQFN32/SMD/P0.4/4X4/S MT6605 QFN (32 Pins, 0.4mm pitch) NFC_VCCSWP C1507 C / 470 / nF / 0402 / X5R NFC_SWPIO C1522 DVDD_EPMU1 C / 1000 / nF / 0402 DVDD_SIM1 C1508 C / 470 / nF / 0402 / X5R NFC_SWP1 C1525 DVDD_EPMU2 C / 1000 / nF / 0402 DVDD_SIM2 C1509 C / 470 / nF / 0402 / X5R NFC_SWP2 NFC_SWPIO R1551 R / 0 / ohm / 0402 U1502 VPS R1550 R / 0/ ohm / 0402 NFC_VCCSWP GND SW IO NC2 RST R1552 R / NC/ ohm / 0402 DVDD_IO_NFC NC1 CLK IO0 MAIN_GND OTS080CD(NC) R1553 R /0/ ohm / 0402 DFN8/SMD/P1.0/OTS0800D (NC) T-Card SIM1 SIM2 4 3 2 A Title NFC MT6605 Size Document Number Rev C MT6572 REF PHONE V1.0 Date: Tuesday, February 05, 2013 Sheet 15 of 99 1 5 [2] GPIO_TV_RST SH1703 ATV_RSTN [2] GPIO_ATV_EN SH1704 [2,13,15] SDA_0 [2,13,15] SCL_0 SH1701 SH1702 D ATV_EN ATV_SDA ATV_SCL [6] GND_SIGNAL 4 3 [6,15] CLK3_ATV C1713 C / 1 / nF / 0402 R1703 R / 0 / ohm / 0402 XTAL_26M C1714 NC Optional Dig out layer 2 of this xtal and layer 3 is solide ground If use Xtal, pls let C1713/R1703 NC TCXO3225 X1700 TXC 26M (7M26000018 ) VCON OUT 2 1 CAM interface D CMVSYNC [2,13] CMHSYNC [2,13] CMDAT6 [2,13] CMDAT5 [2,13] CMDAT4 [2,13] CMDAT3 [2,13] CMDAT2 [2,13] CMDAT1 [2,13] CMDAT0 [2,13] CMPCLK [2,13] GND GND ATV_RSTN ATV_SDA ATV_SCL ANT1701 ANT / 1.7mmX2.9mm VCC_RF C1705 C / 100 / nF / 0201 VIO C1712 CMVSYNC [2,13] CMHSYNC [2,13] CMDAT7 [2,13] CMDAT6 [2,13] In 1.8V IO case, pls 1. Pin21/31 connect to 1.8V power 2. make sure pin36/37(I2C) are pull high to 1.8V power In 2.8V IO case, pls VCC_RF 1. Pin21/31 connect to 2.8V power C1701 C / 1 / pF / 0402 C1706 C / 100 / nF / 0201 U1701 C / 1000 / nF / 0402 2. make sure pin36/37(I2C) are pull high to 2.8V power C C E-PAD AVDD28_SX2 PAD_OSC1 RSTN SDA SCL VSYNC HSYNC D7 D6 VIO R1701 R / 0 / ohm / 0402 L1700 NC L0402 D1700 ESD1P0RFL L1701 NC L0402 L1702 8.2nH/LQG15HS/Murata C1702 L1703 68nH/LQG15HS/Murata C1703 L1704 180nH/LQG15HS/Murata C1704 C / 100 / pF / 0201 C / 220 / pF / 0402 C / 390 / pF / 0402 TP30MIL TP30MIL VCC_RF TP1701 TP1702 PAD_T1P PAD_T1N ATV_EN C1707 C / 100 / nF / 0201 NC AVDD28_FE RFU_P RFV2_P GND_EXT RFV1_P PAD_T1P PAD_T1N AVDD28_VA PU D5 D4 D3 D2 MT5193 VCORE D1 MT5193/QFN40/P0.4/5X5 D0 PCKO MCKI VIO CMDAT5 [2,13] CMDAT4 [2,13] for current leakage issue, pls alway give VIO power or CMDAT3 CMDAT2 [2,13] [2,13] give VIO when Camera is turned ON DVDD12 CMDAT1 [2,13] CMDAT0 [2,13] CMPCLK [2,13] VIO C1711 C / 1000 / nF / 0402 DVDD28_VCORE DVDD12_VCORE VIO_PWM AL AR AODATA AOBCK AOLRCK GPIO1 GPIO0 Put ouside metal casing B GPIO0_5193 pin10 just can be controled by "2.8V" GIO in both VIO=2.8V or 1.8V DVDD_PMU DVDD12 C1709 C / 100 / nF / 0402 C1710 C / 1000 / nF / 0402 VCC_RF C1708 C / 100 / nF / 0402 AODATA AOBCK AOLRCK R1707 R / 0 / ohm / 0402 GPIO0 R1707 NC: XTAL_26M ref. R1707 on: Ext. BB_26M ref Power plan DVDD_PMU SH1708 External 1.5/1.8/2.8V supply (VCAMD) VCAMD_PMU VIO SH1709 1.8V or 2.8V supply (VIO) VCAMD_IO_PMU B VCC_RF SH1710 2.8V supply (VCAMA) VCAMA_PMU Internal LDO mode : put 1.5 or 1.8 or 2.8V supply at Pin11, and connect Pin12 to P26 Exter LDO mode: Put 1.2 or 1.3Vsupply at Pin11, Pin12 and Pin26 if using external Vcore power ( not use internal 1.2v Vcore LDO), pls short pin11,12,26, and connect to 1.3v external power. I2S If using I2S, connect AODATA/AOBCK/AOLRCK to baseband MT6572 IO MUX AODATA AOBCK AOLRCK AODATA SH1705 AOBCK SH1706 AOLRCK SH1707 SPI_MOSI [2] SPI_SCK [2] SPI_CSB [2] A A Title ATV Size Document Number Rev C MT6572 REF PHONE V1.0 Date: Tuesday, February 05, 2013 Sheet 17 of 99 5 4 3 2 1 5 4 Micro SD CARD D VMCH_PMU Based on your system level design , if better MSDC signal quality is needed on your system, please refer to SD card D performance enhance proposal [2] MC1DAT2 [2] MC1DAT3 [2] MC1CMD [2] MC1CK [2] MC1DAT0 [2] MC1DAT1 C C1801 2.2uF [2] MC1_INS B 3 2 U1401 SWPIO DATA2 VCCSWP CD/DATA3 CMD VDD CD CLK VSS GND DATA0 GND DATA1 GND GND GND MSDN-F-700-0-0 MICROSD/SMD/MSDN-F-700-0-0 for NFC application MSDC_NFC_SWPIO [15] MSDC_NFC_VCCSWP [15] Shielding connect to ground 1 D C B A A Title Memory CARD Size Document Number B MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 18 of 99 5 4 3 2 1 5 4 3 2 1 Based on your system level design , if better ESD performance is needed D on your system, please refer to ESD performance enhance proposal D [3] SCLK [3] SRST for NFC application R1901 0R C VSIM1_NFC VSIM1_PMU VSIM2_NFC B [3] SCLK2 [3] SRST2 VSIM2_PMU R1902 0R C1901 1uF C1902 1uF CON1901 SIM1 G G G DP DM SIM1 CLK I/O RST VPP VCC GND R1903 NC DUAL_SIM_SOCKET1 CLK SIM2 I/O RST VPP VCC GND SIM2 SIO [3] for NFC application SIM1_NFC_SWP1 [15] C SIO2 [3] SIM2_NFC_SWP2 [15] G G R1904 NC B for NFC application A A Title SIM Size Document Number B MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 19 of 99 5 4 3 2 1 5 4 3 2 D DO NOT put pull-up resistor on PWRKEY [3] PWRKEY SW2001 KEY / LS10N2 Power Key Based on your system level design , if better ESD performance is needed on your system, please refer to ESD performance enhance proposal C [2] KCOL0 R2002 1K SW2002 Volume Up KEY / LS10N2 1 D C B B [2] KCOL1 R2003 1K SW2003 Volume Down KEY / LS10N2 A A Title KP Size Document Number B MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 20 of 99 5 4 3 2 1 5 4 G-Sensor G Sensor I2C address 0000 111X D X : pin ADDR VIO18_PMU U2106 MT6572 DRL G-sensor VDD ADD VDDIO SDA SDA_1 [2,12] VDDIO2 SCL SCL_1 [2,12] VDD2 INT EINT_ACC [2] GND GNDIO C2116 100nF RES GND2 C 3 2 ALS & PS Sensor ALS I2C address: 0X90 to 0X92 VIO28_PMU PS I2C address : 0XF0 to 0XF2 C2103 1uF R2126 5.1R 5.1R D2110 CM36521 CM36521 U2103 GND VDD SCL SDA LED INT MT6572 DRL ALPXS C2104 100nF SCL_1 [2,12] SDA_1 [2,12] EINT_ALPXS [2] 1 D C B B A A Title MEMS Sensors Size Document Number B MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 21 of 99 5 4 3 2 1 5 4 3 2 1 Net Splitter, can remove in PCB D D C C [2] GPIO_FLASH_EN [2] GPIO_FLASH_SEL SH8007 SH8008 Flash LED driver GPIO_FLASH_EN [2] GPIO_FLASH_SEL [2] [2] EINT_Mag [2] EINT_GY SH8005 SH8006 EINT_Mag [2] Magnetic, Gyro sensor EINT_GY [2] B B A A Title Others Size Document Number B MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 80 of 99 5 4 3 2 1 5 4 3 2 1 V0.2 -------------------------------------------------------------------------- [Page1-BB Power] 1. add application notice for AVDD18_AP [Page2-BB Peripheral] 1. add notice for BPI_BUS4, BPI_BUS5 [Page3-PMIC] 1. add C323 0.1uF for AUXADC_REF [Page5-CONN] 1. reserve GPS ext. LNA circuit D [Page6-Memory] D 1. for DDR1 : AA19+Y19 NC for DDR2 : AA18+Y18 NC C C B B A A Title History Size Document Number C MT6572 REF PHONE Rev V1.0 Date: Friday, March 29, 2013 Sheet 88 of 99 5 4 3 2 1 5 4 3 2 D Camera Flash Torch : <150mA Flash : <1000mA LED1301 OSRAM LUW FQEL FLASH_LED/LUW_F8DN U1304 A K VBAT VIN C1 C1329 C / 1000 / nF / 0402 C2 VOUT PGND SGND C1326 C / 10 / uF / 0603 GPIO_FLASH_SEL FLASH FB GND C GPIO_FLASH_EN EN RSET VIH = 1.3V C1325 C / 4700 / nF / 0603 R1316 47K SGMICRO SGM3141B R1315 R / 43 / K / 0402 Rset R1317 0.4R(0.25W)_RL0805FR-7W0R4L R0805 Rsen SENSOR_FLASH_SEL H: Flash mode L: Torch mode Yageo : RL0805FR-7W0R4L Vfb(Torch) = 47mV Vfb(Flash) = 1.26/Rset x10.2K I_out = Vfb / Rsen B 1 D C B A A Title LED flash Size Document Number B MT6572 REF PHONE Rev V1.0 Date: Monday, January 28, 2013 Sheet 91 of 99 5 4 3 2 1 5 4 M-Sensor M Sensor I2C address CAD1 / CAD0 / Add 0 / 0 / 0x0C 0 / 1 / 0x0D 1 / 0 / 0x0E D 1 / 1 / 0x0F VIO28_PMU VIO18_PMU C2118 C / 100 / nF / 0201 C2117 C / 100 / nF / 0201 U2105 VDD RSTN VID TRG TST1 SCL/SK RSV SDA/SI CAD0 SO CAD1 CSB VSS DRDY SCL_1 SDA_1 VIO18_PMU EINT_Mag C MT6572 DRL M-sensor 3 2 Gyro Sensor I2C Address: 0x68 (Write:0xD0, Read:0xD1) SCL_1 SDA_1 U2102 C2110 50V C / 2200 / pF / 0402 / X7R MT6572 DRL Gyro GND SDA SCL CLKOUT RESV CPOUT RESV CLKIN NC NC NC NC IME_DA VIO18_PMU C2107 C / 10 / nF / 0201 IME_CL VLOGIC AD0 REGOUT FSYNC INT GND NC NC NC NC VDD VIO28_PMU C2109 C / 100 / nF / 0201 EINT_GY C2108 C / 100 / nF / 0201 B 1 D C B A A Title eCompass, Gyro Size Document Number B MT6572 REF PHONE Rev V1.0 Date: Monday, January 28, 2013 Sheet 92 of 99 5 4 3 2 1 5 4 3 2 1 MICBIAS0 D Handset Microphone 2 D R521 1K Close to BB Close to MIC [3] AU_VIN2_P 100nF C516 R519 1.5K Analog MIC C517 C515 4.7uF C518 100pF MIC2 C 100nF Microphone C [3] AU_VIN2_N R518 1.5K C528 33pF C514 33pF R520 1K B B together then single via to main GND A A Title Audio Size Document Number A MT6572 REF PHONE Rev V1.0 Date: Tuesday, February 05, 2013 Sheet 96 of 21 5 4 3 2 1

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