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MT6572 design guide

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MT6572 Design notice

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Internal Use Design notice V0.1 (MT6572) Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Content introduction -- Block diagram -- Baseband -- Extend key -- GPIO Selection -- System application notice for USB Download -- Nand+LPDDR1 & LPDDR2 -- LCM -- Camera -- SD and eMMC -- USB 2.0 HS Internal Use 1 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Internal Use Block diagram Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Internal Use 3 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Internal Use Baseband Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 BB design notice (DRAM type, eFUSE) MUInSteTrnRaelaUdse 1. MT6572 support different type DRAM. Please configure correct HW setting for selected DRAM. 2. If you want to enable efuse , following HW configuration should be set correctly. Pin name PMIC_SPI_CSN TESTMODE FSOURCE KCOL0 Pin out K2 G4 AC24 C24 Normal mode LP-DDR1 Normal mode LP-DDR2 eFUSE Enable 20K-ohm Pull to GND No pull Follow DDR1/2 GND GND GND GND GND VGP2 (2.0V) Not pull-down, just floating or PU. Refer to USB download notice • For normal usage, please configure above pins to be “Normal mode”. - All pins must follow, otherwise system may not download or boot-up • For eFUSE Enable, please contact MTK support window 5 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 BB design notice (JTAG) MUInSteTrnRaelaUdse JTAG interface is muxed on different interface.You can choose one of them as your wish, Pin name Pin out SIM1_SCLK H5 SIM2_SCLK J5 Normal mode (no JTAG) No pull No pull Debug mode (JTAG  KP) 20K-ohm Pull to VIO18 No pull Debug mode (JTAG  MSDC1) No pull 20K-ohm Pull to VIO18 Debug mode (JTAG  CMRST) 20K-ohm Pull to VIO18 20K-ohm Pull to VIO18 R1 = 20K R2 = NC R1 = NC R2 = 20K R1 = 20K R2 = 20K JTMS JTCK Serial JTAG loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX JTMS JTCK JTDI JTDO Legacy Paralle6l JTAG 2013-1-7 / Serial JTAG JTMS JTCK JTDI JTDO Legacy Parallel JTAG / Serial JTAG MT6572 BB design notice (HW i2C) MUInSteTrnRaelaUdse MT6572 integrate 2 I2C controllers, I2C_0 and I2C_1 I2C_0 support only one I2C interface (1 dedicate , No mux onto other pins) I2C_1 support up to four I2C mux interface (1 dedicate, 3 mux to other IO) external Pull-up resistor requirement  [MUST] add pull-up resistor for open-drain i2C, recommend 2.2K  [Optional] base on your system design, reserve NC pull-up resistor at other muxed i2C Pin name SCL_0 SDA_0 SCL_1 SDA_1 CMRST2 CMPDN2 URXD2 UTXD2 BPI_BUS7 BPI_BUS8 Controller I2C_0 I2C_1 Pin out C25 C26 B24 B23 K25 L25 F26 E26 A10 B10 1.8V V V V V V V V V loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 2.8V V V X X X X X X 7 IO type Open-Drain Open-Drain or Push-Pull (SW configurable) GPIO Aux mode Aux. 1 (SCL) Aux. 1 (SDA) Aux. 1 (SCL) Aux. 1 (SDA) Aux. 2 (SCL) Aux. 2 (SDA) Aux. 3 (SCL) Aux. 3 (SDA) Aux. 3 (SCL) Aux. 3 (SDA) MT6572 BB design notice (Key matrix) MUInSteTrnRaelaUdse ◎ : press this key when Power-ON(PWRKEY, Charging, RTC alarm)  power sequence is normal △ : press this key when Power-ON(PWRKEY, Charging, RTC alarm)  power sequence is USB Download  normal booting will proceed after 3sec if USB download tool/cable is not ready Pin name KCOL0 KCOL1 KCOL2 Pin out C24 D24 A25 KROW0 B25 △ ◎ ◎ KROW1 A24 ◎ ◎ ◎ KROW2 B26 ◎ ◎ ◎ GND △ ◎ ◎ 8 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 BB design notice (Analog BB power) MUInSteTrnRaelaUdse Please follow this table for MT6572 analog BB power Pin Name Pin out Power Bypass Cap. Function DVDD18_MIPIRX T25 VIO18 0.1uF, Note1 MIPI CSI DVSS18_MIPIRX U25 GND DVDD18_MIPITX R25 VIO18 0.1uF, Note1 MIPI DSI DVSS18_MIPITX P25 GND REFP F6 (internal) 1uF, Note1 ABB reference power REFN G6 GND AVDD18_USB H23 VIO18 0.1uF USB AVDD33_USB G24 VUSB 1uF (VUSB bypass) AVDD28_DAC F1 VTCXO 0.1uF RF APC AVDD18_MD D3 VIO18 0.1uF RF IQ DVDD18_PLLGP U9 VIO18 0.1uF PLL AVDD18_AP E5 VIO18 0.1uF, Note2 AUXADC, RTP • Note 1 : dedicate GND Ball must connect to cap, then connect to main GND • Note 2 : if AUXADC not use, cap can share with AVDD18_MD 9 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 BB design notice (EINT) MUInSteTrnRaelaUdse MT6572’s MIPI port can be as EINT/MCINS, these port don’t have internal PU/PD  Need external pull up to VIO18 for these EINT/MCINS Example circuit : add PU for the EINT/MCINS 10 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 BB design notice (SIM hot-plug EINT pin) MT6572 support SIM hot-plug by using MD_EINTx  Choose correct pin to MD_EINTx for SIM hot-plug application MUInSteTrnRaelaUdse Example circuit #1: Use TDP2/TDN2 as SIM hot-plug Example circuit #2: Use LPD14/LPD15 as SIM hot-plug 11 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Internal Use Extend key Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 Extend Key HW design notice Internal Use Traditional key pad MT6572 KCOLx New key pad  Extend key MT6572 KCOLx Should be 20K-ohm KROWx KROWx One KCOL and one KROW connected to one key  EX: 3 KCOL * 3 KROW = 9 keys One KCOL and one KROW connected to 2 keys 18  EX: 3 KCOL * 3 KROW = keys 13 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 Extend Key driver tool introduction 1 Choose Page “KEYPAD Setting” Internal Use 3 MT6572 KCOL0 KROW0 2 Choose “Key Type” as EXTEND_TYPE 20Kohm 4 AB Please notice that there’s new column named “Column0_R”. “R” stands for resistor(20K). 14 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 Extend Key Application notice Internal Use 1. Up to two keys can be connected to same KCOL and KROW simultaneously. 2. There should be a 20Kohm on one Key path. MT6572 KCOL0 KROW0 20Kohm AB 3. Don’t assign keys which will be pressed at the same time on same KCOL and KROW . Ex: CTRL and A may be pressed at the same time. KCOL0 MT6572 CTRL 20Kohm A KROW0 15 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 Extend Key Application notice Example circuit : If 2*2  8 keys , need 2 resistors on KCOL. Internal Use MT6572 KCOL1 KCOL0 20Kohm 20Kohm A B E F KROW0 C D G H KROW1 16 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Internal Use GPIO Selection Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Design Notice – GPIO selection (1/3) Internal Use • 1.8V power domain GPIOs shouldn’t connect to external components whose supplied power is higher than 1.98V. • Power domain of IO supply selection : ▪ Choose GPIO with suitable power domain of IO supply for application • Please choose suitable GPIO for peripheral IC : ▪ Please choose GPIOs with matched direction, pull-up/pull-down, data inversion, data output, gpio mode after reset state for peripheral IC application ▪ DO NOT use GPIO with default pull up enable(PU after HW reset) as enable signal ▪ All power domain should be supplied according to the requirements gave in the data sheet. ▪ More detail information in the next page 18 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Design Notice – GPIO selection (2/3) MUInSteTrnRaelaUdse • DO NOT use these MT6572 GPIO as enable signal (PU/Toggle after HW reset) Pin Name Pin out Default Mode Default State Note KCOL0 KROW2 URXD1 UTXD1 LPA0 LPWRB LPRDB LPCE0B NCEB C24 B26 D25 E25 AB23 AC25 AA22 AD25 W5 GPIO107 PU GPIO112 PU URXD1 PU UTXD1 PU GPIO56 PU GPIO57 PU GPIO58 PU GPIO60 PU These GPIO will be available when LCD use MIPI DSI NWRB Y5 ND0 Y4 ND1 AA2 ND2 ND3 ND6 V5 W1 GPIO32 ~ GPIO43 Toggle at boot-up stage Y3 (between Reset release to GPIO init) These GPIO will be available when Memory use eMMC ND8 Y2 ND9 W2 ND12 W4 ND13 W3 ND15 V1 19 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Design Notice – GPIO selection (3/3) ▪ MT6572 IO power domain table No. Power Domain 1 DVDD28_BPI 2 DVDD3_MC1 3 DVDD3_LCD 4 DVDD18_MC0 5 DVDD18_CAM 6 DVDD18_VIO_1 7 DVDD18_VIO_2 8 DVDD18_VIO_3 9 DVDD18_LCD Application RF_BPI [0:6] GPIO_2v8 T-card LCD ctrl NAND, eMMC Camera PMIC I/F SPI, UART, KP RF_BPI [7:15] LCD data Support 2.8V / 3.3V 2.8V 2.8V / 3.3V (no support) (no support) (no support) (no support) (no support) (no support) (no support) Internal Use Suggest Power Connection VIO28 VMC VIO18 VIO18 VIO18 VIO18 VIO18 VIO18 VIO18 Note: Do Not connect voltage higher than 1.98V to the power domain no-support 2.8V/3.3V Improper design or setting will degrade IO reliability 20 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Design Notice – GPIO selection (3/3) Internal Use Notice of Drv_Tool usage After enable “InPull En”, you can change the PU/PD value by changing “InPull SelHigh”. (Only valid when GPIO is input mode) “InPull En” can enable/disable PU/PD, then GPIO will be the default PU/PD value after reset state. (Only valid when GPIO is input mode) “OutHigh” can change the default output level. (Only valid when GPIO is output mode) In above example : GPIO0 will be PU in input mode GPIO1 will be PD in input mode GPIO2 will be Low in output mode GPIO3 will be High in output mode 21 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Internal Use System application notice for USB Download Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Notification of using USB download Internal Use ▪ There are 2 conditions may let system enter USBDL (3s Timeout mode) which user may think it as system abnormal. • The system booting time will take 3s longer than others – Case1:The system will enter USBDL(3s Timeout mode) if KCOL0+ROW0 or KCOL0+GND is pressed inadvertently when pressing power key for powering up system. – Case2:If KCOL0+ROW0 or KCOL0+GND is pressed while plug USB cable into system, this behavior will also let system enter USBDL (3s Timeout mode) . ▪ To prevent enter USBDL mode inadvertently, please follow below suggestion ▪ If KCOL0 is not necessary for your key implementation , MTK strongly recommended not to use KCOL0 as key function. ▪ If KCOL0 must be used , please take USB/Charger user scenario into consideration. For example , not to assign keys(on KCOL0) on side of phone to prevent user press these keys inadvertently while holding the phone and insert USB/Charger. ▪ There should NOT be external pull down resistors on KCOL0 ▪ USBDL timeout is software configurable ▪ Please refer MT6572_BOOTROM_USB_for_customer_Vx.x.ppt (please request the latest version)for SW setting. 23 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Notification of using USB download Internal Use There should NOT be an external pull down resistor on KCOL0. NG 24 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Notification of using USB download Internal Use ▪ Keypad assignment ▪ Assign keys (on KCOL0) on both side of phone isn’t recommended .This is to prevent pressed these key inadvertently while insert USB or charger cable. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Nand+LPDDR1 & LPDDR2 Together, We make the difference. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Nand+LPDDR1 (1/3)  EMI controller schematic for Nand+LPDDR1: 1. NFI is pin mux to support Nand/eMMC + LPDDR1/LPDDR2, so please make sure the ball map match to Nand+LPDDR1 type. (Must) 2. VIO_EMI output 1V8 or 1V2 by using HW trapping pin (PMIC_SPI_CS). – For LPDDR1, the EMI_IO power domain is 1V8, please connect to VIO_EMI and pull PMIC_SPI_CS to low with 20K ohm. (Must) 3. Please connect chip select from the low bit (ECS0_B) first. (Must) 3. 2. 1. Copyright © MediaTek Inc. All rights reserved loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX PMIC_SPI_CS pin Pull low with 20K NC VIO_EMI output 1V8 1V2 Device support LPDDR1 LPDDR2 Nand+LPDDR1 ball map, please make sure the ball map match to MCP type. 27 Nand+LPDDR1 (2/3)  137b NAND+LPDDR1 schematic: (Please double check the pin assignment in your MCP’s data sheet) 1. Add 47K pull up resistor to VIO18_PMU at R/B# pin.(Must) 2. Reserve 0ohm over power path of MCP_DRAM (ex. VIO_EMI) for MVG ETT tuning.(Must) 3. For memory access stability, it need at least 0.1uF*2 + 1uF*1+4.7uF*2 for VIO_EMI.(Must) 2. 3. Copyright © MediaTek Inc. All rights reserved loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 28 1. 47K pull up resistor eMMC+LPDDR1 (3/3)  153b eMMC+LPDDR1 schematic: (Please double check the pin assignment in your MCP’s data sheet) 1. Reserve 0ohm over power path of MCP_DRAM (ex. VIO_EMI) for MVG ETT tuning.(Must) 2. For memory access stability, it need at least 0.1uF*2 + 1uF*1+4.7uF*2 for VIO_EMI.(Must) 1. 2. Copyright © MediaTek Inc. All rights reserved loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 29 Nand+LPDDR2 (1/4)  EMI controller schematic for Nand+LPDDR2: 1. NFI is pin mux to support Nand/eMMC + LPDDR1/LPDDR2, so please make sure the ball map match to Nand+LPDDR2 type. (Must) 2. The EMI_IO power domain is 1V2, please connect to VIO_EMI and let PMIC_SPI_CS floating. (Must) 3. Please connect chip select from the low bit (ECS0_B) first. (Must) 3. 1. 2. Copyright © MediaTek Inc. All rights reserved loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX PMIC_SPI_CS pin Pull low with 20K NC VIO_EMI output 1V8 1V2 Device support LPDDR1 LPDDR2 Nand+LPDDR2 ball map, please make sure the ball map match to MCP type. 30 Nand+LPDDR2 (2/4)  162b NAND+LPDDR2 schematic: (Please double check the pin assignment in your MCP’s data sheet) 1. Add 47K pull up resistor to VIO18_PMU at R/B# pin.(Must) 2. Reserve 0ohm over power path of MCP_DRAM (ex. VIO_EMI) for MVG ETT tuning.(Must) 3. Pull ZQ0 & ZQ1 to low with 240 ohm.(Must) 4. VREFCA & VREFDQ connect to 0.5*VDDQ.(Must) 5. For memory access stability, it need at least 0.1uF*2 + 1uF*1+4.7uF*2 for VIO_EMI.(Must) Power domain: VDD1=1.8V VDD2=1.20V VDDCA=1.2V VDDQ= 1.20V 5. 2. 1. 3. 47K pull up resistor Copyright © MediaTek Inc. All rights reserved loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 31 4. Nand/eMMC+LPDDR2 (3/4)  162b NAND+LPDDR2 & eMMC+LPDDR2 compatible schematic: (Please double check the pin assignment in your MCP’s data sheet) – Please reserve the pins and resistors below for compatible uses. (conditional) 1. 2. 3. Copyright © MediaTek Inc. All rights reserved loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 32 Nand & eMMC compatible method MCP pin Reserved resistor Purpose & resistor connect method For Nand For eMMC A8,B2 R403 1–2 2–3 B8 R404 1–2 2–3 A5 R405 ON Off C3 R406 1–2 2–3 Design Notice ▪ Please refer to the memory test case SOP and finish validation before MP. The test case SOP mainly focuses on 1) Memory quality. 2) Memory timing modification according to the PCB layout. Since LPDDR1 & LPDDR2 are sensitive to PCB layout, the test Case is must ! About information of memory test Case SOP , please contact with MTK . 33 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX LCM Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX LCM Design Note – Overview ▪ Interface – Supports CPU 8/9/16/18 bit interface – Supports MIPI DSI command/video mode, 3-Lane interface – Dedicated HW tearing free control pin for CPU and MIPI DSI interface ▪ IO Power – Support 1.8v IO level LCM (DVDD18_VIO_1/DVDD18_VIO_2/DVDD18_VIO_3/DVDD18_LCD/ DVDD3_LCD, pin L3/J19/H13/AB24/W24) Copyright © MediaTek Inc. All rights reserved loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 35 LCM Design Note ▪ LCM side design notice – Power • AVDD(VCI) : connect to 2.8v for LCM analog power • IOVDD : connect to 1.8v for LCM I/O power – LCM Control • All LCM control pin are reserved at BB side • IM[2:0] : Interface Mode should reference IOVDD level – LCM Data • All LCM data pin are reserved at BB side • For 8 bit interface, some LCM use lower byte D[7:0], some use D[17:10]. Be sure data pin connect to the correct LCM pins. – Touch Panel • Connect to dedicated 4-wire R-type TP pin – CABC • LCM BLC pin or MT6572 PWM_BL pin connect to external backlight driver • MT6323 internal backlight driver can also support CABC. (Please refer to MT6323 design notice and MT6572 ref schematic) – System performance • EMI filter / Common Choke over LCM control pin & data bus are optional (Trade-off between performance & cost). It could reserve at 1st version SMT. Copyright © MediaTek Inc. All rights reserved 36 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX LCM Design Note – CPU Interface ▪ BB side design notice LPCE0B LPWRB LPA0 LPRDB LRSTB LPD[17:0] MT6572(Pin definition) AD25 AC25 AB23 AB22 AC26 M3,N2,N3,P2,N4,R2,N5,R1,P5, T1,R5,T2,T5,U2,T3,V2,T4,V1 LPTE AB26 LCM side /CS /WR RS /RD /RESET D[17:0] FMARK / F_Sync Copyright © MediaTek Inc. All rights reserved loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 37 LCM Design Note – MIPI DSI Interface ▪ BB side design notice – MIPI DSI Interface do good to system design simplicity – MIPI DSI clk/data are differential pair and trace layout should meet 100ohm differential impedance • MIPI_TCP / MIPI_TCN • MIPI_TDP0 / MIPI_TDN0 • MIPI_TDP1 / MIPI TDN1 • MIPI_TDP2 / MIPI TDN2 MT6572 (Pin definition) TCP N19 TCN N20 TDP0 P20 TDN0 P19 TDP1 N26 TDN1 N25 TDP2 P24 TDN2 P23 LRSTB AC26 LPTE AB26 LCM side MIPI_CLKP MIPI_CLKN MIPI_DATAP0 MIPI_DATAN0 MIPI_DATAP1 MIPI_DATAN1 MIPI_DATAP2 MIPI_DATAN2 /RESET FMARK / F_Sync Copyright © MediaTek Inc. All rights reserved 38 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX LCM Design Note – MIPI DSI Interface ▪ All MIPI Power domain connect to 1.8v ▪ By pass cap for MIPI power domain need to close to BB chip Copyright © MediaTek Inc. All rights reserved loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 39 Camera Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Schematic Notice – Camera (1/x) ▪ MT6572 Image Sensor Interfaces – MIPI CSI-2 (1/2) – Power • Power name: DVDD18_MIPIRX. – Front-facing (Sub-camera) and Rear-facing camera (Main) sensor’s MIPI CSI analog portion is powered by DVDD18_MIPIRX. – MIPI CSI-2 – 2 Lane interface for main camera • Differential pair of MIPI CSI-2: – RCP / RCN – RDP0 / RDN0 – RDP1 / RDN1 • The data lane number of MIPI CSI-2 2-Lane can be configured to support 1 or 2 lane. – Signals to support 1~n data lane, where n= 2: { RCP / RCN } ; { RDP0 / RDN0 } to { RDP(n-1) / RDN(n-1) } – The data receiving throughput of MIPI CSI-2 – 2 Lane can up to 1Gbps. Copyright © MediaTek Inc. All rights reserved. 41 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Schematic Notice – Camera (2/x) ▪ MT6572 Image Sensor Interfaces – MIPI CSI-2 (2/2) – MIPI CSI-2, two lane interface which pin-multiplexed with parallel interface for front facing (Sub camera) • Differential pair of MIPI CSI, two lane: – RCP_A / RCN_A – RDP0_A / RDN0_A – RDP1_A / RDN1_A • The data lane number of MIPI CSI two lane-A can be 1 or 2. – Signals for 1 data lane: { RCP_A / RCN_A } ; { RDP0_A / RDN0_A } – Signals for 2 data lane: { RCP_A / RCN_A } ; { RDP0_A / RDN0_A } } ; { RDP1_A / RDN1_A } • The data receiving throughput of MIPI CSI two lane – A can up to 800Mbps. Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 42 Schematic Notice – Camera (3/x) ▪ MT6572 Image Sensor Interfaces – Parallel 8-bit (1/2) – Parallel interface (CM) that pin multiplexed with MIPI CSI-two lane-A. • CM signals – CMMCLK (MCLK) – CMPCLK (PCLK) – CMHREF (HSYNC) – CMVREF (VSYNC) – CMDAT[7:0] (8-bit data) – CMPDN (Power down for main CAM) – CMRST (Reset for main CAM) – CMPDN2 (Power down for Sub-CAM) – CMRST2 (Reset for Sub-CAM) – I2C-0 • IO level is defined by “DVDD18_VIO”. Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 43 Schematic Notice – Camera (4/x) ▪ Application circuit of rear facing camera – Power supply (1/2) • Auto focus (AF) 3.3V power of camera module is powered by PMU’s VCAM_AF. [1] • Analog 2.8V power of camera module is powered by PMU’s VCAM_A. [2] • I/O 1.8V power of camera module is powered by PMU’s VCAM_IO. [3] [1] [2] [3] NOTE : Please check the voltage / current requirement of your selected camera and compare with the relevant spec of their power source. Copyright © MediaTek Inc. All rights reserved. 44 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Schematic Notice – Camera (5/x) ▪ Application circuit of rear facing camera – Power supply (2/2) • Core power of camera module is powered by PMU’s VCAM_D. [1] [1] NOTE : Please check the voltage / current requirement of your selected camera and compare with the relevant spec of their power source. Copyright © MediaTek Inc. All rights reserved. 45 loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Schematic Notice – Camera (6/x) ▪ Application circuit of rear facing camera – MIPI CSI interface • It is recommended to insert a ground (G) signal between differential pairs to improve inter-lane cross coupling. [1] • It is recommended to reserve common-mode choke to prevent RF de-sense, the max. cap loading of common-mode choke must be less than 3pF. [2] [1] [2] Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 46 Schematic Notice – Camera (7/x) ▪ Application circuit of rear facing camera – I2C/SCCB control interface • The I2C-0 (SCL0 & SDA0) is used to control the main and sub-camera sensor module. [1] • Must have external pull-up resistors for I2C open-drain I/O. [2] [1] [2] Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 47 Schematic Notice – Camera (8/x) ▪ EMI filter: – For parallel sensor interface, the max. cap loading of EMI filter must be less than 30pF. For Parallel Sensor : EMI filter cap. max. loading is 30pf Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 48 Schematic Notice – Camera (9/x) ▪ Front facing (Sub camera) camera module – The camera data bus width of MT6572 only support 8-bit (CMDAT[0:7]). – Sensor output format is YUV / JPEG, connect sensor data output DAT[2:9] to MT6572’s CMDAT*0:7] as typical application(please double check your camera spec). [1] [1] Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 49 For more information about camera generic design notice, please refer to DMS ( ..\HW (For Customer Release) \ Common Design Notes \ Camera ) Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 50 SD and eMMC Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 MSDC HW Configuration MSDC1 for SD card MSDC0 for eMMC 52 Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 MSDC I/O Pad Power •The C117 must close to BB IC. The trace length limit is 150mil.(Must) MT6323 default on ? VIO18 Y VMC Y VMCH Y VEMC_3V3 Y Voltage 1.8V 1.8V / 3.3V 3.0V / 3.3V 3.0V / 3.3V Max. Current (mA) 300 100 400 400 53 Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 8-bit eMMC (Using MSDC0 interface) • eMMC_RST is mandatory for eMMC booting .(Must) • Reserve a damping resistor position on the CLK interface •Check eMMC data sheet for the resistor value .(conditional) • eMMC core power (VCC) should be 3.3V.(Must) •Suggest to use MT6323 VEMC_3V3 for eMMC VCC •Check the eMMC data sheet for the capacitor value. • eMMC I/O power (VCCQ) should be 1.8V .(Must) •1.8V power with 100mA capability is necessary Please follow the pin mux table for the eMMC signal •Suggest to use MT6323 VIO_18 VCC (NAND power): 3.3V VCCQ (IO power): 1.8V •Check the eMMC data sheet for the capacitor value. Check eMM5C4 spec foCropVyDrigDhit c©aMpevdaialuTeek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 MSDC1, SD Card •Reverse damping resistor to fine tune the SD card AC timing if layout trace > 2000 mil. (conditional) If the layout trace>2000 mil, the damping resistors are recommended. •Reserve ESD protection device on CMD/CLK/DAT/MCINS with Cap < 15pF 55 Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 MSDC1, SD 2.0 T-Card •for SD 2.0 application (must) - 3.3V/200mA is necessary. -VMCH for both MT6572 (DVDD3_MC1) and SD card. VMC can be used for other peripherals. VMCH_PMU VMCH_PMU 56 Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 MSDC1, SD 3.0 T-Card •for SD 3.0 (SDR50/DDR50) application: (must) - 3.3V/400mA is necessary. VMCH for the SD card. -3.3V/1.8V switchable VMC for the MT6572 (DVDD3_MC1) and. VMCH_PMU •for SD 3.0 (SDR104) application: (must) -The 3.3V/800mA is necessary. The external LDO is mandatory for the SD card. -3.3V/1.8V switchable VMC is for MT6572 DVDD3_MC1. External_LDO 57 Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX USB 2.0 HS Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX Schematic Notice – USB (1/x) ▪ MT6572 USB Power supply – USB Power • 3.3V power name: AVDD33_USB. [1] – “AVDD33_USB” is powered by LDO “VUSB” of PMU for typical USB application. – Reserve bead and bypass capacitor. • 1.8V power name: AVDD18_USB. [1] – “AVDD18_USB ” is powered by LDO “VIO18” of PMU for typical USB application. – Reserve bead and bypass capacitor. [1] (PMIC) Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX MT6572 (Baseband) 59 Schematic Notice – USB (2/x) ▪ MT6572 USB schematic (1/2) – USB_VRT: 5.1K reference resistor for USB PHY reference current source. [1] • The USB_VRT resistor must be 5.1K-Ohm and with 1% precision. • The USB_VRT resistor must be placed as close to main chip’s USB_VRT ball as possible in PCB layout. • Be aware of USB_VRT pin and it’s trace routing should keep away from noise source and high speed clock data like camera data bus. – USB Differential pair: USB_DM/ USB_DP. [2] • The USB 90-Ohm characteristic impedance must be implemented in PCB layout. • The rating voltage of USB_DM/ USB_DP is 3.63V (3.3V+ 10%). – Only support USB2.0 device, not support OTG (Host). [2] 0 Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 60 [1] Schematic Notice – USB (3/x) ▪ MT6572 USB schematic (2/2) – USB application circuit on receptacle side • Reserve ESD protection device for USB differential pair and USB ID pin. [1] • The equivalent capacitance loading of ESD protection device should be less than 3pF. [1] [1] Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 61 For more information about USB generic design notice, please refer to DMS ( ..\HW (For Customer Release) \ Common Design Notes \ USB ) Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX 62 Internal Use www.mediatek.com Copyright © MediaTek Inc. All rights reserved. loginid=guobin.du@signaltech.cn,time=2013-01-07 17:15:39,ip=114.88.65.127,doctitle=MT6572_design_notice_V0.1.pptx,company=Signaltech_WCX

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