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神舟笔记本原理图

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标签: E410

神舟E410 优雅系列主板原理图

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D C B A 5 4 3 2 1 E410 Mobile Arrandale Processor With IBEXPEAKM September 25 2010 Revision 12 5 4 3 2 Saturday September 25 2010 Saturday September 25 2010 Saturday September 25 2010 Scale Scale Scale Model Model Model E410 E410 E410 Sheet Sheet Sheet 1 1 1 1 of of of 48 48 48 HASEE TECHNOLOGY INC HASEE TECHNOLOGY INC HASEE TECHNOLOGY INC Cover Page Cover Page Cover Page Draw by Draw by Draw by Size Size Size CAGE Code CAGE Code CAGE Code DWG NO DWG NO DWG NO Custom Custom Custom Cage Code Cage......

D C B A 5 4 3 2 1 E410 Mobile Arrandale Processor With IBEXPEAK-M September 25 2010 Revision 1.2 5 4 3 2 Saturday, September 25, 2010 Saturday, September 25, 2010 Saturday, September 25, 2010 Scale Scale Scale Model Model Model E410 E410 E410 Sheet Sheet Sheet 1 1 1 1 of of of 48 48 48 HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., Cover Page Cover Page Cover Page Draw by Draw by Draw by Size Size Size CAGE Code CAGE Code CAGE Code DWG NO DWG NO DWG NO Custom Custom Custom Rev Rev Rev 1.2 1.2 1.2 D C B A 5 4 3 2 1 D C B A Arrandale processor 37.5×37.5mm rPGA 988A DDR3(800/1066) SO-DIMM CK505M THERMAL SENSOR VGA LVDS HDA USB1.1/2.0 FDI DMI IBEXPEAK-M BGA1071 27X25mm PCIE PORT1 PCIE PORT2 PCIE PORT0 SATAO(R1.0) LPC(33MHz) PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 MINICARD SLOT1 DC RAILs MINICARD SLOT2 SYSTEM CHARGER 10M/100M LAN RJ45 SATA HDD(2.5) SPI FLASH ISL6251 SYSTEM VR ISL6238 CHIPSET/DDR2 VR ISL6545 CPU VR ISL6261 CRT LCD/LVDS HDA CODEC USB PORT USB PORT USB PORT USB PORT BLUETOOTH WIFI SD/MMC CAMERA MINI PCIE MINIPCIE SMC/KBC LPC HDR DEBUG BOARD FWH SPI HDR KB/JTAG 5 4 3 2 Draw by Draw by Draw by Size Size Size CAGE Code CAGE Code CAGE Code DWG NO DWG NO DWG NO Custom Custom Custom Saturday, September 25, 2010 Saturday, September 25, 2010 Saturday, September 25, 2010 Scale Scale Scale Model Model Model E410 E410 E410 Rev Rev Rev 1.2 1.2 1.2 Cover Page Cover Page Cover Page Sheet Sheet Sheet 1 2 2 2 of of of 48 48 48 HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., Block Diagram Block Diagram Block Diagram D C B A D C B A 5 4 3 2 1 PEG_IRCOMP_R R6 R6 49.9/1% 49.9/1% EXP_RBIAS R7 R7 750/1% 750/1% 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 17 FDI_TXN[7:0] 17 FDI_TXP[7:0] 17 17 FDI_FSYNC0 FDI_FSYNC1 17 FDI_INT 17 17 FDI_LSYNC0 FDI_LSYNC1 U1A U1A A24 C23 B22 A21 B24 D23 B23 A22 D24 G24 F23 H23 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] D25 DMI_TX[0] F24 DMI_TX[1] E23 G23 DMI_TX[2] DMI_TX[3] E22 D21 D19 D18 G21 E19 F21 G18 D22 C21 D20 C18 G22 E20 F20 G19 F17 E17 C17 F18 D17 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] FDI_FSYNC[0] FDI_FSYNC[1] FDI_INT FDI_LSYNC[0] FDI_LSYNC[1] D D M M I I I I n n t t e e l l ( ( R R ) ) F F D D I I S S C C I I H H P P A A R R G G - - - - S S S S E E R R P P X X E E I I C C P P PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] B26 A26 B27 A25 K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 OK-GL! IC,ARD_CFD_rPGA,R1P5 IC,ARD_CFD_rPGA,R1P5 HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., Arrandale-DMI(1/7) Arrandale-DMI(1/7) Arrandale-DMI(1/7) Draw by Draw by Draw by Size Size Size CAGE Code CAGE Code CAGE Code DWG NO DWG NO DWG NO B B B Rev Rev Rev 1.2 1.2 1.2 5 4 3 2 Tuesday, September 28, 2010 Tuesday, September 28, 2010 Tuesday, September 28, 2010 Scale Scale Scale Model Model Model E410 E410 E410 Sheet Sheet Sheet 1 3 3 3 of of of 48 48 48 D C B A H_COMP3 H_COMP2 H_COMP1 AT23 AT24 G16 H_COMP0 AT26 U1B U1B COMP3 COMP2 COMP1 COMP0 -SKTOCC_R AH24 SKTOCC# -H_CATERR AK14 CATERR# 20 H_PECI R8 R8 0 0 H_PECI_ISO AT15 PECI 32 -H_PROCHOT AN26 PROCHOT# 20 -H_THRMTRIP R136 0 R136 0 -H_THRMTRIP_R AK15 THERMTRIP# M M I I S S C C T T H H E E R R M M A A L L -H_CPURST R13 R13 0 0 -H_CPURST_R 17 H_PM_SYNC R99 R99 0 0 H_PM_SYN_R R177 0 R177 0 AP26 AL15 AN14 RESET_OBS# PM_SYNC VCCPWRGOOD_1 VCCPWRGOOD_0 SM_DRAMPWROK 20 H_CPUPWRGD 17 PM_DRAM_PWRGD 31 H_VTTPWRGD R110 0 R110 0 VCCPWRGOOD_0_R AN27 R115 0 R115 0 VDDPWRGOOD_R AK13 AM15 VTTPWRGOOD H_PWRGD_XDP_R AM26 TAPPWRGOOD 19 -BUF_PLT_RST R131 1.5K/1% R131 1.5K/1% PLT_RST_R AL14 RSTIN# R135 R135 750/1% 750/1% IC,ARD_CFD_rPGA,R1P5 IC,ARD_CFD_rPGA,R1P5 7,13,14,22,31 +V1.5 VDDPWRGOOD_R R43 R43 1.1K/1% 1.1K/1% R66 R66 3.01K/1% 3.01K/1% Processor Pullups D C B A 6,7,20,21,22,29,31,32,34 +V1.05S_VTT Processor Compensation Signals DDR3 Compensation Signals R108 R108 R117 R117 49.9/1% 49.9/1% 68 68 R123 R123 68/X 68/X -H_CATERR -H_PROCHOT -H_CPURST H_COMP0 H_COMP1 H_COMP2 H_COMP3 R51 R51 R54 R54 49.9/1% 49.9/1% 49.9/1% 49.9/1% R121 R121 R122 R122 20/1% 20/1% 20/1% 20/1% SM_RCOMP_2 SM_RCOMP_1 SM_RCOMP_0 R132 R132 R133 R133 R52 R52 100/1% 100/1% 24.9/1% 24.9/1% 130/1% 130/1% 5 4 3 5 4 3 2 1 BCLK BCLK# A16 B16 R18 R18 R112 R112 AR30 AT30 BCLK_ITP_P_R BCLK_ITP_N_R 0 0 0 0 0 0 0 0 BCLK_CPU_P 20 BCLK_CPU_N 20 CLK_EXP_P 16 CLK_EXP_N 16 R23 R23 R91 R91 S S K K C C O O L L C C BCLK_ITP BCLK_ITP# PEG_CLK PEG_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# CLK_DP_P 16 CLK_DP_N 16 6,7,20,21,22,29,31,32,34 +V1.05S_VTT -DDR3_DRAMRST 13,14 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 R106 R106 10k 10k R107 R107 10k 10k -XDP_PRDY -XDP_PREQ XDP_TCLK XDP_TMS -XDP_TRST R160 R160 R167 R167 0/X 0/X 0/X 0/X R35 R35 12.4k/1%/X 12.4k/1%/X -PM_EXTTS0 10,41 -PM_EXTTS1 10 E16 D16 A18 A17 F6 AL1 AM1 AN1 AN15 AP15 AT28 AP27 AN28 AP28 AT27 AT29 AR27 AR29 AP29 SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] PM_EXT_TS#[0] PM_EXT_TS#[1] PRDY# PREQ# TCK TMS TRST# TDI TDO TDI_M TDO_M 3 3 R R D D D D C C S S I I M M M M P P B B & & G G A A T T J J P P W W R R M M A A N N A A G G E E M M E E N N T T 10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,29,30,32,34,35,36,37,39,40,41 +V3.3S 6,7,20,21,22,29,31,32,34 +V1.05S_VTT XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDI_M AN25 -H_DBR_R R53 R53 1K 1K AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] XDP_TMS XDP_TDI_R NO STUFF R128 R128 51/X 51/X NO STUFF R84 R84 51/X 51/X -XDP_PREQ R97 R97 NO STUFF 51/X 51/X NO STUFF XDP_TCLK R98 R98 51/X 51/X D C B A JTAG MAPPING XDP_TDI_R R114 R114 0 0 XDP_TDO_M R118 R118 0/X 0/X NO STUFF R111 R111 0 0 XDP_TDI_M R57 R57 0/X 0/X NO STUFF XDP_TDO_R R58 R58 0 0 XDP_TDI XDP_TDO -XDP_TRST R87 R87 51 51 Scan Chain (Default) STUFF -> R53, R57,R56 NO STUFF -> R54, R55 CPU ONLY STUFF -> R53, R54 NO STUFF -> R57, R55, R56 GMCH ONLY STUFF -> R55, R56 NO STUFF -> R53, R54, R7 OK-GL! HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., Calpella Processer (CLK,MISC,JTAG) Calpella Processer (CLK,MISC,JTAG) Calpella Processer (CLK,MISC,JTAG) Draw by Draw by Draw by Tuesday, September 28, 2010 Tuesday, September 28, 2010 Tuesday, September 28, 2010 2 Size Size Size C C C Scale Scale Scale CAGE Code CAGE Code CAGE Code DWG NO DWG NO DWG NO Rev Rev Rev 1.2 1.2 1.2 Model Model Model E410 E410 E410 Sheet Sheet Sheet 1 4 4 4 of of of 48 48 48 D C B A 5 4 3 2 1 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 U1C U1C SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 AC3 AB2 U7 AE1 AB3 AE9 13 M_A_DQ[63:0] 13 13 13 13 13 13 M_A_BS0 M_A_BS1 M_A_BS2 -M_A_CAS -M_A_RAS -M_A_WE SA_CK[0] SA_CK#[0] SA_CKE[0] SA_CK[1] SA_CK#[1] SA_CKE[1] SA_CS#[0] SA_CS#[1] SA_ODT[0] SA_ODT[1] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] AA6 AA7 P7 Y6 Y5 P6 AE2 AE8 AD8 AF9 B9 D7 H7 M7 AG6 AM7 AN10 AN13 C9 F8 J9 N9 AH7 AK9 AP11 AT13 C8 F9 H9 M9 AH8 AK10 AN11 AR13 Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 -M_A_DQS0 -M_A_DQS1 -M_A_DQS2 -M_A_DQS3 -M_A_DQS4 -M_A_DQS5 -M_A_DQS6 -M_A_DQS7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 A A Y Y R R O O M M E E M M M M E E T T S S Y Y S S R R D D D D 14 M_B_DQ[63:0] 双双双双双双双双双双双双 M_CLK_DDR0 -M_CLK_DDR0 M_CKE0 13 13 13 M_CLK_DDR1 -M_CLK_DDR1 M_CKE1 13 13 13 -M_CS0 13 -M_CS1 13 M_ODT0 13 M_ODT1 13 M_A_DM[7:0] 13 -M_A_DQS[7:0] 13 M_A_DQS[7:0] 13 M_A_A[15:0] 13 14 14 14 14 14 14 M_B_BS0 M_B_BS1 M_B_BS2 -M_B_CAS -M_B_RAS -M_B_WE M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 U1D U1D SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 AB1 W5 R7 AC5 Y7 AC6 SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# SB_CK[0] SB_CK#[0] SB_CKE[0] SB_CK[1] SB_CK#[1] SB_CKE[1] SB_CS#[0] SB_CS#[1] SB_ODT[0] SB_ODT[1] SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] W8 W9 M3 V7 V6 M2 AB8 AD6 AC7 AD1 D4 E1 H3 K1 AH1 AL2 AR4 AT8 D5 F4 J4 L4 AH2 AL4 AR5 AR8 C5 E3 H4 M5 AG2 AL5 AP5 AR7 U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 -M_B_DQS0 -M_B_DQS1 -M_B_DQS2 -M_B_DQS3 -M_B_DQS4 -M_B_DQS5 -M_B_DQS6 -M_B_DQS7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 B B - - Y Y R R O O M M E E M M M M E E T T S S Y Y S S R R D D D D M_CLK_DDR2 -M_CLK_DDR2 M_CKE2 14 M_CLK_DDR3 -M_CLK_DDR3 M_CKE3 14 14 14 14 14 -M_CS2 14 -M_CS3 14 M_ODT2 14 M_ODT3 14 M_B_DM[7:0] 14 -M_B_DQS[7:0] 14 M_B_DQS[7:0] 14 双双双双双双双双双双双双 M_B_A[15:0] 14 IC,ARD_CFD_rPGA,R1P5 IC,ARD_CFD_rPGA,R1P5 IC,ARD_CFD_rPGA,R1P5 IC,ARD_CFD_rPGA,R1P5 5 4 3 OK-GL! HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., HASEE TECHNOLOGY INC., Calpella Processer (DDR3) Calpella Processer (DDR3) Calpella Processer (DDR3) Draw by Draw by Draw by Tuesday, September 28, 2010 Tuesday, September 28, 2010 Tuesday, September 28, 2010 2 Size Size Size C C C Scale Scale Scale CAGE Code CAGE Code CAGE Code DWG NO DWG NO DWG NO Rev Rev Rev 1.2 1.2 1.2 Model Model Model E410 E410 E410 Sheet Sheet Sheet 1 5 5 5 of of of 48 48 48 D C B A
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sf116 【GD32 MCU】
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alan000345 电源技术
2808的相关原理图
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hlx3012 【微控制器 MCU】
原理图精品资料集合
在方案开发等正向研究中,原理图的作用是非常重要的,而对原理图的把关也关乎整个项目的质量甚至生命。分享一些经典的原理图资料: MSP430 LaunchPad学习板原理图(Altium Design9格式):http://download.eeworld.com.cn/detail/qwqwqw2088/8838 蓝牙模块原理图(PCB板+BC3+Flash的芯片):http://dow
juice58 下载中心专版
关于原理图和PCB的同步问题
请教大家一个问题: 假设有一个网络的名字为:Net14,从原理图和PCB上检查Net14连接都没错误,但是从原理图到PCB同步的时候总是会把Net14的一部分删除掉(不是完全删除,还剩下一段连接), 另外, 1.        从原理图重新导入一个新的PCB,Net14的连接是正确存在的(现在的PCB是以前用Logic同步的,现在设计上用DX处理原理图) 2.        Net14有
傻傻天子 嵌入式系统编程
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ddllxxrr 【微控制器 MCU】

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