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    PIC32MX Family Reference Manual © 2008 Microchip Technology Inc. DS61132B Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS61132B-page ii © 2008 Microchip Technology Inc. Introduction 1 Section 1. Introduction HIGHLIGHTS This section of the manual contains the following topics: 1.1 Introduction .................................................................................................................... 1-2 1.2 Objective of This Manual ............................................................................................... 1-2 1.3 Device Structure............................................................................................................. 1-2 1.4 Development Support .................................................................................................... 1-4 1.5 Style and Symbol Conventions ...................................................................................... 1-4 1.6 Related Documents ....................................................................................................... 1-6 1.7 Revision History ............................................................................................................. 1-7 © 2008 Microchip Technology Inc. Preliminary DS61127C-page 1-1 PIC32MX Family Reference Manual 1.1 INTRODUCTION Microchip’s PIC32MX series of 32-bit microcontrollers is designed to fulfill customers’ requirements for enhanced features and performance for their MCU-based applications. Common attributes among all devices in the PIC32MX series are: • Pin, peripheral and source code compatibility with the PIC24F128GAXXX family • MIPS32® M4K™ processor core • Common development tools 1.2 OBJECTIVE OF THIS MANUAL This manual describes the PIC32MX series of 32-bit microcontrollers. It explains the family architecture and operation of the peripheral modules, but does not cover the specifics of each device in the family. Users should refer to the respective device’s data sheet for device-specific details, such as: • Pinout and packaging details • Memory map • List of peripherals included on the device, including multiple instances of peripherals • Device-specific electrical specifications and characteristics 1.3 DEVICE STRUCTURE The PIC32MX architecture has been broken down into the following functional blocks: • MCU Core • System Memory • System Integration • Peripherals 1.3.1 MCU Core The MCU core consists of these essential basic features. • 32-bit RISC MIPS32 M4K Core • Single Cycle ALU • Load-Store Execution Unit • 5-Stage Pipeline • 32-bit Address and 32-bit Data Buses • Two 32-element, 32-bit General Purpose Register Files • FMT – Fixed Mapping Translation Memory Management • FMDU – Fast-Multiply-Divide Unit • MIPS32® Compatible Instruction Set • MIPS16e™ Code Compression Instruction Set Architecture Support The CPU section of this manual discusses the PIC32MX MCU core. 1.3.2 System Memory The system memory provides on-chip nonvolatile Flash memory and volatile SRAM memory, featuring user and protected kernel-segment-partitioning for real-time operating systems. The following sections of this manual discuss the PIC32MX system memory: • Section 3. Memory Organization • Section 5. Flash Programming DS61127C-page 1-2 Preliminary © 2008 Microchip Technology Inc. Introduction Section 1. Introduction 1 Flash Memory Technology • The Flash can be used for program memory or data. • The Flash allows program memory to be electrically erased or programmed under software control during normal device operation. • The PIC32MX series has full-speed execution directly from program Flash through the use of on-chip prefetch buffering by the Prefetch module. • The Flash has the capability to page erase, word or row program. 1.3.3 System Integration System integration consists of a comprehensive set of modules and features that tie the MCU core and peripheral modules into a single operational unit. System integration features also provide these advantages: • Decreased system cost, by bringing traditionally off-chip functions into the microcontroller • Increased design flexibility, by adding a wider range of operating modes • Increased system reliability, by enhancing the ability to recover from unexpected events The following sections of this manual discuss the PIC32MX system integration: • Section 3. Memory Organization • Section 4. Prefetch Module • Section 5. Flash Programming • Section 6. Oscillator • Section 7. Resets • Section 8. Interrupts • Section 9. Watchdog Timer and Power-up Timer • Section 10. Power-Saving Modes • Section 31. Direct Memory Access (DMA) Controller with programmable Cyclic Redundancy Check (CRC) • Section 32. High-Level Integration (Configuration, Code Protection and Voltage Regulation) • Section 33. Device Programming, Debugging, In-Circuit and In-Circuit Testing 1.3.4 Peripherals The PIC32MX devices have many peripherals that allow it to interface with the external world. The following sections of this manual discuss the PIC32MX peripherals: • Section 12. I/O Ports • Section 13. Parallel Master Port • Section 14. Timers • Section 15. Input Capture Module • Section 16. Output Compare/Pulse Width Modulation (PWM) Module • Section 17. 10-bit A/D Converter • Section 19. Comparator Module • Section 20. Comparator Voltage Reference Module • Section 21. UART Module • Section 23. SPI Module • Section 24. I2CTM Module • Section 27. USB OTG • Section 29. Real-Time Clock/Calendar (RTCC) Module © 2008 Microchip Technology Inc. Preliminary DS61127C-page 1-3 PIC32MX Family Reference Manual 1.4 DEVELOPMENT SUPPORT Microchip offers a wide range of development tools that allow users to efficiently develop and debug application code. Microchip’s development tools can be broken down into four categories: • Code generation • Hardware/software debug • Device programmer • Product evaluation boards As new tools are developed, the latest product briefs and user guides can be obtained from the Microchip web site (www.microchip.com) or from local Microchip Sales Offices. Microchip offers other references and support to speed the development cycle. These include: • Application notes • Reference designs • Microchip web site • Local sales offices with field application support • Corporate Applications support line • Getting Stated guide • “How to” brochures • Masters Conferences • Webinars • Design Centers These can all be found on the Microchip web site. Also, the Microchip web site lists other sites that may provide useful references. 1.5 STYLE AND SYMBOL CONVENTIONS Throughout this document, certain style, format, and font conventions are used to signal particular distinctions for the affected text. Table 1-1 lists these conventions, the MCU-industry-specific symbols, and non-conventional word definitions and abbreviations used in this manual. Located at the rear of this document, a glossary provides additional word and abbreviation definitions for content used in this manual. DS61127C-page 1-4 Preliminary © 2008 Microchip Technology Inc. Introduction Section 1. Introduction 1 1.5.1 Document Conventions Table 1-1 defines some of the symbols, terms and typographic conventions used in this manual. Table 1-1: Document Conventions SYMBOL AND TERM CONVENTIONS: Convention Description set To force a bit/register to a value of logic ‘1’. clear To force a bit/register to a value of logic ‘0’. reset 1. To force a register/bit to its default state. 2. A condition in which the device places itself after a device Reset occurs. Some bits will be forced to ‘0’ (such as interrupt enable bits), while others will be forced to ‘1’ (such as the I/O data direction bits). : (colon) Specifies a range or concatenation of registers/bits/pins. Concatenation order (left to right) usually specifies a positional relationship (MSb to LSb, higher to lower). For example, TMR3:TMR2 indicates the concatenation of two 16-bit registers to form a 32-bit timer value, with the value of TMR3 representing the most significant half-word of the value. <> Specifies a bit location or range of locations within a particular register or field of similarly-named bits. For example, PTCON<2:0> specifies the range of the 3 Least Significant bits of the register PTCON. MSb LSb Most Significant bit and Least Significant bit. MSB, LSB Most Significant Byte, Least Significant Byte. (A Byte is 8-bits wide.) mshw, lshw Most Significant half-word and least significant half-word A Half-Word is 16-bits wide msw, lsw Most Significant Word and Least Significant Word. (A Word is 32-bits wide.) 0xnn Designates the number ‘nn’ in the hexadecimal number system. This convention is used in code examples, and is equivalent to the notation ‘nnh’ used in text. For example, 0x13 is equivalent to 13h. FONT CONVENTIONS: Arial Font The standard font used for all text, figures and tables within this manual. Other fonts, as described below, are used to set off mathematical and logical expressions, or device instruction code, from descriptive text. Courier New Font Within text, this font is used for contrast with the standard text font and specifically denote the following: 1. an instruction set mnemonic or assembler code fragment. 2. the binary value of a bit, range of bits, or a register. 3. the logical state of a digital signal. Within code examples, this font is used exclusively to denote an assembly or high-level language instruction sequence. Times New Roman Font The standard font for mathematical expressions and variables. GRAPHIC CONVENTIONS: Note A note presents information that requires emphasis: either to help users avoid a common pitfall, or to make them aware of operating differences between some device family members. A note is usually in a shaded box, unless it is used in a bit description, or as a table or diagram footnote. Note: This is a Note in a shaded note box. Register Cells A bit name that appears in a grayed-out cell of a register signals that the bit is not relevant to the peripheral module described in that particular section of the manual. FRZ © 2008 Microchip Technology Inc. Preliminary DS61127C-page 1-5 PIC32MX Family Reference Manual 1.5.2 Electrical Specifications Throughout this manual, there are references to electrical specifications and their parameter numbers. Table 1-2 shows the parameter numbering convention for PIC32MX devices. A parameter number represents a unique set of characteristics and conditions that is consistent between every data sheet, though the actual parameter value may vary from device to device. This manual describes a family of devices and, therefore, does not specify the parameter values. To determine the parameter values for a specific device, users should refer to the “Electrical Specifications” section of that device’s data sheet. Table 1-2: Electrical Specification Parameter Numbering Convention Parameter Number Format Comment DXXX AXXX XXX PDXXX PXXX DC Specification DC Specification for Analog Peripherals Timing (AC) Specification Device Programming DC Specification Device Programming Timing (AC) Specification Legend: XXX represents a parameter number. 1.6 RELATED DOCUMENTS Microchip, as well as other sources, offers additional documentation to aid you as you develop PIC32MX-based applications. The list below contains the most common documentation, but other documents may also be available. Please check the Microchip web site (www.microchip.com) for the latest published technical documentation. 1.6.1 Microchip Documentation The following PIC32MX documentation is available from Microchip. Many of these documents provide application-specific information that gives actual examples of using, programming, and designing with PIC32MX microcontrollers. 1. PIC32MX Family Reference Manual The family reference manual describes the PIC32MX architecture and operation of the peripheral modules, but does not cover the specifics of each device in the family. 2. PIC32MX Data Sheets The data sheets contain device-specific information, such as pinout and packaging details, electrical specifications and memory maps. 3. PIC32MX Programming Specification The programming specifications contain detailed descriptions of, and electrical and timing specifications for, the programming process. Both In-Circuit Serial Programming™ (ICSP™) and Enhanced ICSP are described in detail. 1.6.2 Third-Party Documentation Microchip does not review third-party documentation for technical accuracy, but these references may be helpful to understand operation of the devices. The Microchip web site may have information on these third-party documents. DS61127C-page 1-6 Preliminary © 2008 Microchip Technology Inc. Introduction Section 1. Introduction 1 1.7 REVISION HISTORY Revision A (September 2007) This is the initial version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised Section 1.1. © 2008 Microchip Technology Inc. Preliminary DS61127C-page 1-7 PIC32MX Family Reference Manual NOTES: DS61127C-page 1-8 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU HIGHLIGHTS This section of the manual contains the following topics: 2 2.1 Introduction................................................................................................................ 2-2 2.2 Architecture Overview ............................................................................................... 2-3 2.3 PIC32MX CPU Details............................................................................................... 2-6 2.4 Special Considerations when Writing to CP0 Registers .......................................... 2-11 2.5 Architecture Release 2 Details ................................................................................ 2-12 2.6 Split CPU bus .......................................................................................................... 2-12 2.7 Internal system busses ............................................................................................ 2-13 2.8 Set/Clear/Invert........................................................................................................ 2-13 2.9 ALU Status Bits........................................................................................................ 2-14 2.10 Interrupt and Exception Mechanism ........................................................................ 2-14 2.11 Programming Model ................................................................................................ 2-15 2.12 CP0 Registers ......................................................................................................... 2-22 2.13 MIPS16e™ Execution ............................................................................................. 2-58 2.14 Memory Model ......................................................................................................... 2-58 2.15 CPU Instructions, Grouped By Function.................................................................. 2-60 2.16 CPU Initialization ..................................................................................................... 2-64 2.17 Effects of a Reset .................................................................................................... 2-65 2.18 Related Application Notes ....................................................................................... 2-67 2.19 Revision History....................................................................................................... 2-68 © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-1 PIC32MX Family Reference Manual 2.1 INTRODUCTION The PIC32MX Microcontroller Unit (MCU) is a complex system-on-a-chip that is based on a M4K™ core from MIPS® Technologies. M4K™ is a state-of-the-art 32-bit, low-power, RISC processor core with the enhanced MIPS32® Release 2 Instruction Set Architecture. This chapter provides an overview of the CPU features and system architecture of the PIC32MX family of microcontrollers. Key Features • Up to 1.5 DMIPS/MHz of performance • Programmable prefetch cache memory to enhance execution from Flash memory • 16-bit Instruction mode (MIPS16e) for compact code • Vectored interrupt controller with 63 priority levels • Programmable User and Kernel modes of operation • Atomic bit manipulations on peripheral registers (Single cycle) • Multiply-Divide unit with a maximum issue rate of one 32 × 16 multiply per clock • High speed Microchip ICD port with hardware-based non-intrusive data monitoring and application data streaming functions • EJTAG debug port allows extensive third party debug, programming and test tools support • Instruction controlled power management modes • Five stage piplined instruction execution • Internal Code protection to help protect intellectual property Related MIPS® Documentation • MIPS M4K™ Software User’s Manual – MD00249-2B-M4K-SUM • MIPS® Instruction Set – MD00086-2B-MIPS32BIS-AFP • MIPS16e™ – MD00076-2B-MIPS1632-AFP • MIPS32® Privileged Resource Architecture – MD00090-2B-MIPS32PRA-AFP DS61113C-page 2-2 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.2 ARCHITECTURE OVERVIEW The PIC32MX family processors are complex systems-on-a-chip that contain many features. Included in all processors of the PIC32MX family is a high-performance RISC CPU, which can be programmed in 32-bit and 16-bit modes, and even mixed modes. The PIC32MX MCU contains a high-performance interrupt controller, DMA controller, USB controller, in-circuit debugger, high performance switching matrix for high-speed data accesses to the peripherals, on-chip data RAM memory that holds data and programs. The unique prefetch cache and prefetch buffer for the Flash memory, which hides the latency of the Flash, gives zero Wait state equivalent performance. Figure 2-1: PIC32MX MCU Block Diagram 2 JTAG/BSCAN Priority Interrupt Controller LDO VREG EJTAG INT PIC32MX CPU IS DS USB DMAC ICD Bus Matrix PORTS Prefetch Cache Data RAM Peripheral Bridge 128-bit Flash Memory Flash Controller PMP/PSP ADC RTCC Timers Input Capture PWM/Output Compare Dual Compare Clock Control/ Generation Reset Generation SSP/SPI I2C™ UART © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-3 PIC32MX Family Reference Manual Figure 2-2: There are two internal buses in the chip to connect all the peripherals. The main peripheral bus connects most of the peripheral units to the bus matrix through a peripheral bridge. There is also a high-speed peripheral bridge that connects the interrupt controller DMA controller, in-circuit debugger, and USB peripherals. The heart of the PIC32MX MCU is the M4K CPU core. The CPU performs operations under program control. Instructions are fetched by the CPU, decoded and executed synchronously. Instructions exist in either the Program Flash memory or Data RAM memory. The PIC32MX CPU is based on a load/store architecture and performs most operations on a set of internal registers. Specific load and store instructions are used to move data between these internal registers and the outside world. M4K™ Processor Core Block Diagram On-Chip Memory MDU Execution Core (RF/ALU/Shift) MMU System Coprocessor FMT EJTAG Trace TAP Off-Chip Trace I/F Off-Chip Debug I/F Memory Interface Dual Memory I/F Power Mgmt 2.2.1 Busses There are two separate busses on the PIC32MX MCU. One bus is responsible for the fetching of instructions to the CPU, and the other is the data path for load and store instructions. Both the instruction, or I-side bus, and the data, or D-side bus, are connected to the bus matrix unit. The bus matrix is a switch that allows multiple accesses to occur concurrently in a system. The bus matrix allows simultaneous accesses between different bus masters that are not attempting accesses to the same target. The bus matrix serializes accesses between different masters to the same target through an arbitration algorithm. Since the CPU has two different data paths to the bus matrix, the CPU is effectively two different bus masters to the system. When running from Flash memory, load and store operations to SRAM and the internal peripherals will occur in parallel to instruction fetches from Flash memory. In addition to the CPU, there are three other bus masters in the PIC32MX MCU – the DMA controller, In-Circuit-Debugger Unit, and the USB controller. DS61113C-page 2-4 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.2.2 Introduction to the Programming Model The PIC32MX processor has the following features: • 5-stage pipeline • 32-bit Address and Data Paths • DSP-like Multiply-add and multiply-subtract instructions (MADD, MADDU, MSUB, MSUBU) • Targeted multiply instruction (MUL) • Zero and One detect instructions (CLZ, CLO) • Wait instruction (WAIT) • Conditional move instructions (MOVZ, MOVN) • Implements MIPS32 Enhanced Architecture (Release 2) 2 • Vectored interrupts • Programmable exception vector base • Atomic interrupt enable/disable • General Purpose Register (GPR) shadow sets • Bit field manipulation instructions • MIPS16e Application Specific Extension improves code density • Special PC-relative instructions for efficient loading of addresses and constants • Data type conversion instructions (ZEB, SEB, ZEH, SEH) • Compact jumps (JRC, JALRC) • Stack frame set-up and tear down “macro” instructions (SAVE and RESTORE) • Memory Management Unit with simple Fixed Mapping Translation (FMT) • Processor to/from Coprocessor register data transfers • Direct memory to/from Coprocessor register data transfers • Performance-optimized Multiply-Divide Unit (High-performance build-time option) • Maximum issue rate of one 32 × 16 multiply per clock • Maximum issue rate of one 32 × 32 multiply every other clock • Early-in divide control – 11 to 34 clock latency • Low-Power mode (triggered by WAIT instruction) • Software breakpoints via the SDBBP instruction 2.2.3 Core Timer The PIC32MX architecture includes a core timer that is available to application programs. This timer is implemented in the form of two co-processor registers–the Count register (CP0_COUNT), and the Compare register (CP0_COMPARE). The Count register is incremented every two system clock (SYSCLK) cycles. The incrementing of Count can be optionally suspended during Debug mode. The Compare register is used to cause a timer interrupt if desired. An interrupt is generated when the Compare register matches the Count register. An interrupt is taken only if it is enabled in the interrupt controller. For more information on the core timer, see Section 2.12. “CP0 Registers” and Section 8. “Interrupts.” © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-5 PIC32MX Family Reference Manual 2.3 PIC32MX CPU DETAILS 2.3.1 Pipeline Stages The pipeline consists of five stages: • Instruction (I ) Stage • Execution (E) Stage • Memory (M) Stage • Align (A) Stage • Writeback (W) Stage 2.3.1.1 I Stage – Instruction Fetch During I stage: • An instruction is fetched from the instruction SRAM. • MIPS16e instructions are converted into MIPS32-like instructions. 2.3.1.2 E Stage – Execution During E stage: • Operands are fetched from the register file. • Operands from the M and A stage are bypassed to this stage. • The Arithmetic Logic Unit (ALU) begins the arithmetic or logical operation for regis- ter-to-register instructions. • The ALU calculates the data virtual address for load and store instructions and the MMU performs the fixed virtual-to-physical address translation. • The ALU determines whether the branch condition is true and calculates the virtual branch target address for branch instructions. • Instruction logic selects an instruction address and the MMU performs the fixed virtual-to-physical address translation. • All multiply divide operations begin in this stage. 2.3.1.3 M Stage – Memory Fetch During M stage: • The arithmetic or logic ALU operation completes. • The data SRAM access is performed for load and store instructions. • A 16 × 16 or 32 × 16 MUL operation completes in the array and stalls for one clock in the M stage to complete the carry-propagate-add in the M stage. • A 32 × 32 MUL operation stalls for two clocks in the M stage to complete the second cycle of the array and the carry-propagate-add in the M stage. • Multiply and divide calculations proceed in the MDU. If the calculation completes before the IU moves the instruction past the M stage, then the MDU holds the result in a temporary register until the IU moves the instructions to the A stage (and it is consequently known that it won’t be killed). 2.3.1.4 A Stage – Align During A stage: • A separate aligner aligns loaded data with its word boundary. • A MUL operation makes the result available for writeback. The actual register writeback is performed in the W stage. • From this stage, load data or a result from the MDU are available in the E stage for bypassing. DS61113C-page 2-6 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU Figure 2-3: 2.3.1.5 W Stage – Writeback During W stage: For register-to-register or load instructions, the result is written back to the register file. A M4K core implements a “Bypass” mechanism that allows the result of an operation to be sent directly to the instruction that needs it without having to write the result to the register and then read it back. Simplified PIC32MX CPU Pipeline I Stage Instruction E Stage Reg File Rs Addr Rs Read Rt Addr Rd Write Rt Read A to E Bypass M to E Bypass ALU E Stage M Stage A Stage W Stage 2 ALU M Stage Bypass Multiplexers Load Data, HI/LO Data or CP0 Data Figure 2-4: The results of using instruction pipelining in the PIC32MX core is a fast, single-cycle instruction execution environment. Single-Cycle Execution Throughput One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle One Cycle I E M A W I E M A W I E M A W I E M A W I E M A W © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-7 PIC32MX Family Reference Manual 2.3.2 Execution Unit The PIC32MX Execution Unit is responsible for carrying out the processing of most of the instructions of the MIPS instruction set. The Execution Unit provides single-cycle throughput for most instructions by means of pipelined execution. Pipelined execution, sometimes referred to as “pipelining”, is where complex operations are broken into smaller pieces called stages. Operation stages are executed over multiple clock cycles. The Execution Unit contains the following features: • 32-bit adder used for calculating the data address • Address unit for calculating the next instruction address • Logic for branch determination and branch target address calculation • Load aligner • Bypass multiplexers used to avoid stalls when executing instructions streams where data producing instructions are followed closely by consumers of their results • Leading Zero/One detect unit for implementing the CLZ and CLO instructions • Arithmetic Logic Unit (ALU) for performing bitwise logical operations • Shifter and Store Aligner 2.3.3 MDU The Multiply/Divide unit performs multiply and divide operations. The MDU consists of a 32 × 16 multiplier, result-accumulation registers (HI and LO), multiply and divide state machines, and all multiplexers and control logic required to perform these functions. The high-performance, pipelined MDU supports execution of a 16 × 16 or 32 × 16 multiply operation every clock cycle; 32 × 32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issue of back-to-back 32 × 32 multiply operations. Divide operations are implemented with a simple 1 bit per clock iterative algorithm and require 35 clock cycles in worst case to complete. Early-in to the algorithm detects sign extension of the dividend, if it is actual size is 24, 16 or 8 bit. the divider will skip 7, 15, or 23 of the 32 iterations. An attempt to issue a subsequent MDU instruction while a divide is still active causes a pipeline stall until the divide operation is completed. The M4K implements an additional multiply instruction, MUL, which specifies that lower 32-bits of the multiply result be placed in the register file instead of the HI/LO register pair. By avoiding the explicit move from LO (MFLO) instruction, required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two instructions, multiply-add (MADD/MADDU) and multiply-subtract (MSUB/MSUBU), are used to perform the multiply-add and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD/MADDU and MSUB/MSUBU operations are commonly used in Digital Signal Processor (DSP) algorithms. 2.3.4 Shadow Register Sets The PIC32MX processor implements a copy of the General Purpose Registers (GPR) for use by high-priority interrupts. This extra bank of registers is known as a shadow register set. When a high-priority interrupt occurs the processor automatically switches to the shadow register set without software intervention. This reduces overhead in the interrupt handler and reduces effective latency. The shadow register set is controlled by registers located in the System Coprocessor (CP0) as well as the interrupt controller hardware located outside of the CPU core. For more information on shadow register sets, see the XREF Interrupt chapter. DS61113C-page 2-8 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.3.5 Pipeline Interlock Handling Smooth pipeline flow is interrupted when an instruction in a pipeline stage can not advance due to a data dependency or a similar external condition. Pipeline interruptions are handled entirely in hardware. These dependencies, are referred to as interlocks. At each cycle, interlock conditions are checked for all active instructions. An instruction that depends on the result of a previous instruction is an example of an interlock condition. In general, MIPS processors support two types of hardware interlocks: • Stalls Stalls are resolved by halting the entire pipeline. All instructions currently executing in each pipeline stage are affected by a stall. • Slips 2 Slips allow one part of the pipeline to advance while another part of the pipeline is held static. In the PIC32MX processor core, all interlocks are handled as slips. These slips are minimized by grabbing results from other pipeline stages by using a method called register bypassing, which is described below. Note: To illustrate the concept of a pipeline slip, the following example is what would happen if the PIC32MX core did not implement register bypassing. As shown in Figure 2-5, the sub instruction has a source operand dependency on register r3 with the previous add instruction. The sub instruction slips by two clocks waiting until the result of the add is written back to register r3. This slipping does not occur on the PIC32MX family of processors. Figure 2-5: Pipeline Slip (If Bypassing Was Not Implemented) Add r3, r2, r1 (r3 = r2 + r1) One One One One One One One One Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle I E M A W Sub r4, r3, r7 (r4 = r3 – r7) I ESLIP ESLIP E M A W © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-9 PIC32MX Family Reference Manual Figure 2-6: 2.3.6 Register Bypassing As mentioned previously, the PIC32MX processor implements a mechanism called register bypassing that helps reduce pipeline slips during execution. When an instruction is in the E stage of the pipeline, the operands must be available for that instruction to continue. If an instruction has a source operand that is computed from another instruction in the execution pipeline, register bypassing allows a shortcut to get the source operands directly from the pipeline. An instruction in the E stage can retrieve a source operand from another instruction that is executing in either the M stage or the A stage of the pipeline. As seen in Figure 2-6, a sequence of three instructions with interdependencies does not slip at all during execution. This example uses both A to E, and M to E register bypassing. Figure 2-7 shows the operation of a load instruction utilizing A to E bypassing. Since the result of load instructions are not available until the A pipeline stage, M to E bypassing is not needed. The performance benefit of register bypassing is that instruction throughput is increased to the rate of one instruction per clock for ALU operations, even in the presence of register dependencies. IU Pipeline M to E Bypass Add1 r3 = r2 + r1 Sub2 r4 = r3 – r7 Add3 r5 = r3 + r4 One One One One One One Cycle Cycle Cycle Cycle Cycle Cycle I E M A W M to E Bypass A to E Bypass I E M A W M to E Bypass I E M A Figure 2-7: IU Pipeline A to E Data Bypass Load Instruction One One One One One One Cycle Cycle Cycle Cycle Cycle Cycle I E M A W Data Bypass from A to E I E M A W Consumer of Load Data Instruction I One Clock Load Delay E M A DS61113C-page 2-10 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.4 SPECIAL CONSIDERATIONS WHEN WRITING TO CP0 REGISTERS In general, the PIC32MX core ensures that instructions are executed following a fully sequential program model. Each instruction in the program sees the results of the previous instruction. There are some deviations to this model. These deviations are referred to as hazards. In privileged software, there are two different types of hazards: • Execution Hazards • Instruction Hazards 2.4.0.1 Execution Hazards Execution hazards are those created by the execution of one instruction, and seen by the 2 execution of another instruction. Table 2-1 lists execution hazards. Table 2-1: Execution Hazards Producer = Consumer Hazard On MTC0 MTC0 MTC0 MTC0, EI, DI MTC0 MTC0 MTC0 MTC0 = Coprocessor instruction execution depends on the new value of StatusCU = ERET StatusCU EPC DEPC ErrorEPC = ERET Status = Interrupted Instruction = Interrupted Instruction = RDPGPR WRPGPR StatusIE CauseIP SRSCtlPSS = Instruction not seeing a Timer Interrupt Compare update that clears Timer Interrupt = Instruction affected by change Any other CP0 register Spacing (Instructions) 1 1 0 1 3 1 4 2 Table 2-2: MTC0 2.4.0.2 Instruction Hazards Instruction hazards are those created by the execution of one instruction, and seen by the instruction fetch of another instruction. Table 2-2 lists instruction hazards. Instruction Hazards Producer = Consumer Instruction fetch seeing the new value (including a = change to ERL followed by an instruction fetch from the useg segment) Hazard On Status © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-11 PIC32MX Family Reference Manual 2.5 ARCHITECTURE RELEASE 2 DETAILS The PIC32MX CPU utilizes Release 2 of the MIPS 32-bit architecture. The PIC32MX CPU implements the following Release 2 features: • Vectored interrupts using and external-to-core interrupt controller Provide the ability to vector interrupts directly to a handler for that interrupt. • Programmable exception vector base Allows the base address of the exception vectors to be moved for exceptions that occur when StatusBEV is ‘0’. This allows any system to place the exception vectors in memory that is appropriate to the system environment. • Atomic interrupt enable/disable Two instructions have been added to atomically enable or disable interrupts, and return the previous value of the Status register. • The ability to disable the Count register for highly power-sensitive applications. • GPR shadow registers Provides the addition of GPR shadow registers and the ability to bind these registers to a vectored interrupt or exception. • Field, Rotate and Shuffle instructions Add additional capability in processing bit fields in registers. • Explicit hazard management Provides a set of instructions to explicitly manage hazards, in place of the cycle-based SSNOP method of dealing with hazards. 2.6 SPLIT CPU BUS The PIC32MX CPU core has two distinct busses to help improve system performance over a single-bus system. This improvement is achieved through parallelism. Load and store operations occur at the same time as instruction fetches. The two busses are known as the I-side bus which is used for feeding instructions into the CPU, and the D-side bus used for data transfers. The CPU fetches instructions during the I pipeline stage. A fetch is issued to the I-side bus and is handled by the bus matrix unit. Depending on the address, the BMX will do one of the following: • Forward the fetch request to the Prefetch Cache Unit • Forward the fetch request to the DRM unit or • Cause an exception Instruction fetches always use the I-side bus independent of the addresses being fetched. The BMX decides what action to perform for each fetch request based on the address and the values in the BMX registers. (See BMX chapter). The D-side bus processes all load and store operations executed by the CPU. When a load or store instruction is executed the request is routed to the BMX by the D-side bus. This operation occurs during the M pipeline stage and is routed to one of several targets devices: • Data Ram • Prefetch Cache/Flash Memory • Fast Peripheral Bus (Interrupt controller, DMA, Debug unit, USB, GPIO Ports) • General Peripheral Bus (UART, SPI, Flash Controller, EPMP/EPSP, TRCC Timers, Input Capture, PWM/Output Compare, ADC, Dual Compare, I2C, Clock SIB, and Reset SIB) DS61113C-page 2-12 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.7 INTERNAL SYSTEM BUSSES The PIC32MX processor internal busses connect the peripherals to the bus matrix unit. The bus matrix routes bus accesses from 5 different initiators to a set of targets utilizing several data paths throughout the chip to help eliminate performance bottlenecks. Some of the paths that the bus matrix uses serve a dedicated purpose, while others are shared between several targets. The data RAM and Flash memory read paths are dedicated paths, allowing low-latency access to the memory resources without being delayed by peripheral bus activity. The high-bandwidth peripherals are placed on a high-speed bus. These include the Interrupt controller, debug unit, DMA engine, and the USB host/peripheral unit. Peripherals that do not require high-bandwidth are located on a separate peripheral bus to save 2 power. 2.8 SET/CLEAR/INVERT To provide single-cycle bit operations on peripherals, the registers in the peripheral units can be accessed in three different ways depending on peripheral addresses. Each register has four different addresses. Although the four different addresses appear as different registers, they are really just four different methods to address the same physical register. Figure 2-8: Four Addresses for a Single Physical Register Register Address Register Address + 4 Register Address + 8 Register Address + 12 Clear Bits Set Bits Invert Bits Peripheral Register The base register address provides normal Read/Write access, the other three provide special write-only functions. 1. Normal access 2. Set bit atomic RMW access 3. Clear bit atomic RMW access 4. Invert bit atomic RMW access Peripheral reads must occur from the base address of each peripheral register. Reading from a set/clear/invert address has an undefined meaning, and may be different for each peripheral. Writing to the base address writes an entire value to the peripheral register. All bits are written. For example, assume a register contains 0xaaaa5555 before a write of 0x000000ff. After the write, the register will contain 0x000000ff (assuming that all bits are R/W bits). Writing to the Set address for any peripheral register causes only the bits written as ‘1’s to be set in the destination register. For example, assume that a register contains 0xaaaa5555 before a write of 0x000000ff to the set register address. After the write to the Set register address, the value of the peripheral register will contain 0xaaaa55ff. Writing to the Clear address for any peripheral register causes only the bits written as ‘1’s to be cleared to ‘0’s in the destination register. For example, assume that a register contains 0xaaaa5555 before a write of 0x000000ff to the Clear register address. After the write to the Clear register address, the value of the peripheral register will contain 0xaaaa5500. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-13 PIC32MX Family Reference Manual 2.9 2.10 Writing to the Invert address for any peripheral register causes only the bits written as ‘1’s to be inverted, or toggled, in the destination register. For example, assume that a register contains 0xaaaa5555 before a write of 0x000000ff to the invert register address. After the write to the Invert register, the value of the peripheral register will contain 0xaaaa55aa. ALU STATUS BITS Unlike most other PIC® microcontrollers, the PIC32MX Processor does not use STATUS register flags. Condition flags are used on many processors to help perform decision making operations during program execution. Flags are set based on the results of comparison operations or some arithmetic operations. Conditional branch instructions on these machines then make decisions based on the values of the single set of condition codes. The PIC32MX processor, instead, uses instructions that perform a comparison and stores a flag or value into a General Purpose Register. A conditional branch is then executed with this general purpose register used as an operand. INTERRUPT AND EXCEPTION MECHANISM The PIC32MX family of processors implement an efficient and flexible interrupt and exception handling mechanism. Interrupts and exceptions both behave similarly in that the current instruction flow is changed temporarily to execute special procedures to handle an interrupt or exception. The difference between the two is that interrupts are usually a result of normal operation, and exceptions are a result of error conditions such as bus errors. When an interrupt or exception occurs, the processor does the following: 1. The PC of the next instruction to execute after the handler returns is saved into a coprocessor register. 2. Cause register is updated to reflect the reason for exception or interrupt 3. Status EXL or ERL is set to cause Kernel mode execution 4. Handler PC is calculated from EBASE and SPACING values 5. Processor starts execution from new PC This is a simplified overview of the interrupt and exception mechanism. See Section 8. “Interrupts” for more information regarding interrupt and exception handling. DS61113C-page 2-14 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.11 PROGRAMMING MODEL The PIC32MX family of processors is designed to be used with a high-level language such as the C programming language. It supports several data types and uses simple but flexible addressing modes needed for a high-level language. There are 32 General Purpose Registers and two special registers for multiplying and dividing. There are three different formats for the machine language instructions on the PIC32MX processor: • immediate or I-type CPU instructions • jump or J-type CPU instructions and • registered or R-type CPU instructions 2 Most operations are performed in registers. The register type CPU instructions have three oper- ands; two source operands and a destination operand. Having three operands and a large register set allows assembly language programmers and compilers to use the CPU resources efficiently. This creates faster and smaller programs by allowing intermediate results to stay in registers rather than constantly moving data to and from memory. The immediate format instructions have an immediate operand, a source operand and a destination operand. The jump instructions have a 26-bit relative instruction offset field that is used to calculate the jump destination. 2.11.1 CPU Instruction Formats Table 2-3: A CPU instruction is a single 32-bit aligned word. The CPU instruction formats are shown below: • Immediate (see Figure 2-9) • Jump (see Figure 2-10) • Register (see Figure 2-11) Table 2-3 describes the fields used in these instructions. CPU Instruction Format Fields Field Description opcode rd rs rt immediate instr_index sa function 6-bit primary operation code 5-bit specifier for the destination register 5-bit specifier for the source register 5-bit specifier for the target (source/destination) register or used to specify functions within the primary opcode REGIMM 16-bit signed immediate used for logical operands, arithmetic signed operands, load/store address byte offsets, and PC-relative branch signed instruction displacement 26-bit index shifted left two bits to supply the low-order 28 bits of the jump target address 5-bit shift amount 6-bit function field used to specify functions within the primary opcode SPECIAL © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-15 PIC32MX Family Reference Manual Figure 2-9: Immediate (I-Type) CPU Instruction Format 31 26 25 21 20 16 15 0 opcode rs rt immediate 6 5 5 16 Figure 2-10: Jump (J-Type) CPU Instruction Format 31 26 25 21 20 16 15 11 10 65 0 opcode instr_index 6 26 Figure 2-11: Register (R-Type) CPU Instruction Format 31 26 25 21 20 16 15 opcode rs rt rd 6 5 5 5 11 10 sa 5 65 0 function 6 2.11.2 CPU Registers The PIC32MX architecture defines the following CPU registers: • 32 32-bit General Purpose Registers (GPRs) • 2 special purpose registers to hold the results of integer multiply, divide, and multiply-accu- mulate operations (HI and LO) • a special purpose program counter (PC), which is affected only indirectly by certain instruc- tions – it is not an architecturally visible register. 2.11.2.1 CPU General Purpose Registers Two of the CPU General Purpose Registers have assigned functions: • r0 r0 is hard-wired to a value of ‘0’, and can be used as the target register for any instruction the result of which will be discarded. r0 can also be used as a source when a ‘0’ value is needed. • r31 r31 is the destination register used by JAL, BLTZAL, BLTZALL, BGEZAL, and BGEZALL, without being explicitly specified in the instruction word. Otherwise r31 is used as a normal register. The remaining registers are available for general purpose use. DS61113C-page 2-16 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.11.2.2 Register Conventions Although most of the registers in the PIC32MX architecture are designated as General Purpose Registers, there are some recommended uses of the registers for correct software operation with high-level languages such as the Microchip C compiler. Table 2-4: Register Conventions CPU Symbolic Register Register Usage r0 zero Always 0(1) r1 at Assembler Temporary 2 r2 - r3 v0-v1 Function Return Values r4 - r7 a0-a3 Function Arguments r8 - r15 t0-t7 Temporary – Caller does not need to preserve contents r16 - r23 s0-s7 Saved Temporary – Caller must preserve contents r24 - r25 t8 - t9 Temporary – Caller does not need to preserve contents r26 - r27 k0 - k1 Kernel temporary – Used for interrupt and exception handling r28 gp Global Pointer – Used for fast-access common data r29 sp Stack Pointer – Software stack r30 s8 or fp Saved Temporary – Caller must preserve contents OR Frame Pointer – Pointer to procedure frame on stack r31 ra Return Address(1) Note 1: Hardware enforced, not just convention. 2.11.2.3 CPU Special Purpose Registers The CPU contains three special purpose registers: • PC – Program Counter register • HI – Multiply and Divide register higher result • LO – Multiply and Divide register lower result - During a multiply operation, the HI and LO registers store the product of integer multiply. - During a multiply-add or multiply-subtract operation, the HI and LO registers store the result of the integer multiply-add or multiply-subtract. - During a division, the HI and LO registers store the quotient (in LO) and remainder (in HI) of integer divide. - During a multiply-accumulate, the HI and LO registers store the accumulated result of the operation. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-17 PIC32MX Family Reference Manual Figure 2-12 shows the layout of the CPU registers. Table 2-5: CPU Register 31 0 31 0 r0 (zero) HI r1 (at) LO r2 (v0) r3 (v1) r4 (a0) r5 (a1) r6 (a2) r7 (a3) r8 (t0) r9 (t1) r10 (t2) r11 (t3) r12 (t4) r13 (t5) r14 (t6) r15 (t7) r16 (s0) r17 (s1) r18 (s2) r19 (s3) r20 (s4) r21 (s5) r22 (s6) r23 (s7) r24 (t8) r25 (t9) r26 (k0) r27 (k1) r28 (gp) r29 (sp) r30 (s8 or fp) 31 0 r31 (ra) PC General Purpose Registers Special Purpose Registers DS61113C-page 2-18 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU Table 2-6: MIPS16e Register Usage MIPS16e Register Encoding 32-Bit MIPS Register Encoding Symbolic Name Description 0 16 s0 General Purpose Register 1 17 s1 General Purpose Register 2 2 v0 General Purpose Register 3 3 v1 General Purpose Register 4 4 a0 General Purpose Register 2 5 5 a1 General Purpose Register 6 6 a2 General Purpose Register 7 7 a3 General Purpose Register N/A 24 t8 MIPS16e Condition Code register; implicitly referenced by the BTEQZ, BTNEZ, CMP, CMPI, SLT, SLTU, SLTI, and SLTIU instructions N/A 29 sp Stack Pointer register N/A 31 ra Return Address register Table 2-7: MIPS16e Special Registers Symbolic Name Purpose PC Program counter. PC-relative Add and Load instructions can access this register as an operand. HI Contains high-order word of multiply or divide result. LO Contains low-order word of multiply or divide result. 2.11.3 How to implement a stack/MIPS calling conventions The PIC32MX CPU does not have hardware stacks. Instead, the processor relies on software to provide this functionality. Since the hardware does not perform stack operations itself, a convention must exist for all software within a system to use the same mechanism. For example, a stack can grow either toward lower address, or grow toward higher addresses. If one piece of software assumes that the stack grows toward lower address, and calls a routine that assumes that the stack grows toward higher address, the stack would become corrupted. Using a system-wide calling convention prevents this problem from occurring. The Microchip C compiler assumes the stack grows toward lower addresses. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-19 PIC32MX Family Reference Manual 2.11.4 Processor Modes There are two operational modes and one special mode of execution in the PIC32MX family CPUs; User mode, Kernel mode and DEBUG mode. The processor starts execution in Kernel mode, and if desired, can stay in Kernel mode for normal operation. User mode is an optional mode that allows a system designer to partition code between privileged and un-privileged software. DEBUG mode is normally only used by a debugger or monitor. One of the main differences between the modes of operation is the memory addresses that software is allowed to access. Peripherals are not accessible in User mode. Figure 2-12 shows the different memory maps for each mode. For more information on the processor’s memory map, see Section 3. “Memory Organization”. Figure 2-12: CPU Modes Virtual Address 0xFFFF_FFFF 0xFF40_0000 0xFF3F_FFFF 0xFF20_0000 0xFF1F_FFFF 0xE000_0000 0xDFFF_FFFF User Mode Kernel Mode kseg3 kseg2 DEBUG Mode kseg3 dseg kseg3 kseg2 0xC000_0000 0xBFFF_FFFF kseg1 kseg1 0xA000_0000 0x9FFF_FFFF 0x8000_0000 0x7FFF_FFFF kseg0 kseg0 useg kuseg kuseg 0x0000_0000 DS61113C-page 2-20 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU 2.11.4.1 Kernel Mode In order to access many of the hardware resources, the processor must be operating in Kernel mode. Kernel mode gives software access to the entire address space of the processor as well as access to privileged instructions. The processor operates in Kernel mode when the DM bit in the DEBUG register is ‘0’ and the STATUS register contains one, or more, of the following values: UM = 0 ERL = 1 EXL = 1 When a non-debug exception is detected, EXL or ERL will be set and the processor will enter Kernel mode. At the end of the exception handler routine, an Exception Return (ERET) instruction is generally executed. The ERET instruction jumps to the Exception PC (EPC or ErrorPC depending on the exception), clears ERL, and clears EXL if ERL= 0. 2 If UM = 1 the processor will return to User mode after returning from the exception when ERL and EXL are cleared back to ‘0’. 2.11.4.2 User Mode When executing in User mode, software is restricted to use a subset of the processor’s resources. In many cases it is desirable to keep application-level code running in User mode where if an error occurs it can be contained and not be allowed to affect the Kernel mode code. Applications can access Kernel mode functions through controlled interfaces such as the SYSCALL mechanism. As seen in Figure 2-12, User mode software has access to the USEG memory area. To operate in User mode, the STATUS register must contain each the following bit values: UM = 1 EXL = 0 ERL = 0 2.11.4.3 DEBUG Mode DEBUG mode is a special mode of the processor normally only used by debuggers and system monitors. DEBUG mode is entered through a debug exception and has access to all the Kernel mode resources as well as special hardware resources used to debug applications. The processor is in DEBUG mode when the DM bit in the DEBUG register is ‘1’. DEBUG mode is normally exited by executing a DERET instruction from the debug handler. MCU © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-21 PIC32MX Family Reference Manual 2.12 CP0 REGISTERS The PIC32MX uses a special register interface to communicate status and control information between system software and the CPU. This interface is called Coprocessor 0. The features of the CPU that are visible through Coprocessor 0 are core timer, interrupt and exception control, virtual memory configuration, shadow register set control, processor identification, and debugger control. System software accesses the registers in CP0 using coprocessor instructions such as MFC0 and MTC0. Table 2-8 describes the CP0 registers found on the PIC32MX MCU. Table 2-8: Register Number 0-6 7 8 9 10 11 12 13 14 15 16 17-22 23 24 25-29 30 31 CP0 Registers Register Name Function Reserved HWREna BadVAddr Count Reserved Compare Status/ IntCtl/ SRSCtl/ SRSMap Cause EPC PRId/ EBASE/ Config/ Config1/ Config2/ Config3 Reserved Debug/ Debug2/ DEPC Reserved ErrorEPC DeSAVE Reserved in the PIC32MX core Enables access via the RDHWR instruction to selected hardware registers in Non-privileged mode Reports the address for the most recent address-related exception Processor cycle count Reserved in the PIC32MX core Timer interrupt control Processor status and control; interrupt control; and shadow set control Cause of last exception Program counter at last exception Processor identification and revision; exception base address Configuration registers Reserved in the PIC32MX core Debug control/exception status and EJTAG trace control Program counter at last debug exception Reserved in the PIC32MX core Program counter at last error Debug handler scratchpad register DS61113C-page 2-22 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.12.1 HWREna Register (CP0 Register 7, Select 0) HWREna contains a bit mask that determines which hardware registers are accessible via the RDHWR instruction. Register 2-1: HWREna: Hardware Accessibility Register; CP0 Register 7, Select 0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 — — — — — — — bit 31 r-0 — bit 24 r-0 — bit 23 r-0 r-0 r-0 r-0 r-0 r-0 r-0 2 — — — — — — — bit 16 r-0 — bit 15 r-0 r-0 r-0 r-0 r-0 r-0 r-0 — — — — — — — bit 8 r-0 — bit 7 r-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — MASK<3:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-4 bit 3-0 Reserved: Write ‘0’; returns ‘0’ on read MASK<3:0>: Bit Mask bits 1 = Access is enabled to corresponding hardware register 0 = Access is disabled Each bit in this field enables access by the RDHWR instruction to a particular hardware register (which may not be an actual register). See the RDHWR instruction for a list of valid hardware registers. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-23 PIC32MX Family Reference Manual 2.12.2 BadVAddr Register (CP0 Register 8, Select 0) BadVAddr is a read-only register that captures the most recent virtual address that caused an address error exception. Address errors are caused by executing load, store, or fetch operations from unaligned addresses, and also by trying to access Kernel mode addresses from User mode. BadVAddr does not capture address information for bus errors, because they are not addressing errors. Register 2-2: BadVAddr: Bad Virtual Address Register; CP0 Register 8, Select 0 R-x R-x R-x R-x R-x R-x R-x BadVAddr<31:24> bit 31 R-x bit 24 R-x bit 23 R-x R-x R-x R-x R-x R-x R-x BadVAddr<23:16> bit 16 R-x bit 15 R-x R-x R-x R-x R-x R-x R-x BadVAddr<15:8> bit 8 R-x bit 7 R-x R-x R-x R-x R-x R-x R-x BadVAddr<7:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 BadVAddr<31:0>: Bad Virtual Address bits Captures the virtual address that caused the most recent address error exception. DS61113C-page 2-24 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.12.3 COUNT Register (CP0 Register 9, Select 0) COUNT acts as a timer, incrementing at a constant rate, whether or not an instruction is executed, retired, or any forward progress is made through the pipeline. The counter increments every other clock, if the DC bit in the CAUSE register is ‘0’. COUNT can be written for functional or diagnostic purposes, including at Reset or to synchronize processors. By writing the CountDM bit in DEBUG register, it is possible to control whether COUNT continues to increment while the processor is in DEBUG mode. Register 2-3: R/W-x COUNT: Interval Counter Register; CP0 Register 9, Select 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x 2 COUNT<31:24> bit 31 bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x COUNT<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x COUNT<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x COUNT<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 COUNT<31:0>: Interval Counter bits This value is incremented every other clock cycle. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-25 PIC32MX Family Reference Manual 2.12.4 COMPARE Register (CP0 Register 11, Select 0) COMPARE acts in conjunction with COUNT to implement a timer and timer interrupt function. COMPARE maintains a stable value and does not change on its own. When the value of COUNT equals the value of COMPARE, the CPU asserts an interrupt signal to the system interrupt controller. This signal will remain asserted until COMPARE is written. Register 2-4: R/W-x bit 31 COMPARE: Interval Count Compare Register; CP0 Register 11, Select 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x COMPARE<31:24> R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x COMPARE<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x COMPARE<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x COMPARE<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 COMPARE<31:0>: Interval Count Compare Value bits DS61113C-page 2-26 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU 2.12.5 STATUS Register (CP0 Register 12, Select 0) STATUS is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. Fields of this register combine to create operating modes for the processor. 2.12.5.0.1 Interrupt Enable Interrupts are enabled when all of the following conditions are true: IE = 1 EXL = 0 ERL = 0 DM = 0 If these conditions are met, then the settings of the IPL bits enable the interrupts. 2.12.5.0.2 Operating Modes 2 If the DM bit in the Debug register is ‘1’, then the processor is in DEBUG mode; otherwise, the processor is in either Kernel or User mode. The following CPU STATUS register bit settings determine User or Kernel mode: Table 2-9: CPU Status Bits that Determine Processor Mode User Mode (requires all of the following bits and values) UM = 1 EXL = 0 ERL = 0 Kernal Mode (requires one or more of the following bit values) UM = 0 EXL = 1 ERL = 1 Note: The STATUS register CU bits <31:28> control coprocessor accessibility. If any coprocessor is unusable, then an instruction that accesses it generates an exception. MCU © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-27 PIC32MX Family Reference Manual Register 2-5: STATUS: Status Register; CP0 Register 12, Select 0 R-0 R-0 R-0 R/W-x R/W-0(1) r-x CU3 CU2 CU1 CU0 RP FR bit 31 R/W-x RE r-0 — bit 24 r-0 R/W-1 r-0 R/W-0 R/W-0 r-0 r-0 r-0 — BEV Reserved SR NMI — — — bit 23 bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x IPL<15:10> R/W-x R/W-x R/W-x R/W-x R<9:8> bit 8 R/W-x — bit 7 R/W-x — R/W-x — R/W-x UM R/W-x — R/W-x ERL R/W-x EXL R/W-x IE bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24:23 CU3: Coprocessor 3 Usable bit Controls access to Coprocessor 3 COP3 is not supported. This bit cannot be written and will read as ‘0’ CU2: Coprocessor 2 Usable bit Controls access to Coprocessor 2. COP2 is not supported. This bit cannot be written and will read as ‘0’ CU1: Coprocessor 1 Usable bit Controls access to Coprocessor 1 COP1 is not supported. This bit cannot be written and will read as ‘0’ CU0: Coprocessor 0 Usable bit Controls access to Coprocessor 0 0 = access not allowed 1 = access allowed Coprocessor 0 is always usable when the processor is running in Kernel mode, independent of the state of the CU0 bit. RP: Reduced Powerbit Enables reduced power mode FR: FR bit Reserved on PIC32MX processors RE: Used to enable reverse-endian memory references while the processor is running in User mode 0 = User mode uses configured endianness 1 = User mode uses reversed endianness Neither DEBUG mode nor Kernel mode nor Supervisor mode references are affected by the state of this bit. R<24:23>: Reserved. Ignored on write and read as ‘0’. DS61113C-page 2-28 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU Register 2-5: STATUS: Status Register; CP0 Register 12, Select 0 (Continued) bit 22 BEV: Control bit. Controls the location of exception vectors. 0 = Normal 1 = Bootstrap bit 21 Reserved bit 20 SR: Soft Reset bit Indicates that the entry through the Reset exception vector was due to a Soft Reset. 0 = Not Soft Reset (NMI or Reset) 1 = Soft Reset Software can only write a ‘0’ to this bit to clear it and cannot force a 0-1 transition. 2 bit 19 NMI: Soft Reset bit Indicates that the entry through the reset exception vector was due to an NMI. 0 = Not NMI (Soft Reset or Reset) 1 = NMI Software can only write a ‘0’ to this bit to clear it and cannot force a 0-1 transition. bit 18 R: Reserved. ignored on write and read as ‘0’. bit 17 R: Reserved. ignored on write and read as ‘0’. bit 16 R: Reserved. ignored on write and read as ‘0’. bit 15-10 IPL<15:10>: Interrupt Priority Level bits This field is the encoded (0..63) value of the current IPL. An interrupt will be signaled only if the requested IPL is higher than this value bit 9-8 R<9:8>: Reserved These bits are writable, but have no effect on the interrupt system. bit 7-5 R<7:5>: Reserved. Ignored on write and read as ‘0’ bit 4 UM: This bit denotes the base operating mode of the processor. On the encoding of this bit is: 0 = Base mode in Kernal mode 1 = Base mode is User mode Note: The processor can also be in Kernel mode if ERL or EXL is set, regardless of the state of the UM bit. bit 3 R: Reserved. Ignored on write and read as ‘0’ bit 2 ERL: Error Level bit Set by the processor when a Reset, Soft Reset, NMI or Cache Error exception are taken. 0 = Normal level 1 = Error level When ERL is set: - Processor is running in Kernel mode - Interrupts are disabled - ERET instruction will use the return address held in ErrorEPC instead of EPC - Lower 229 bytes of kuseg are treated as an unmapped and uncached region. This allows main memory to be accessed in the presence of cache errors. The operation of the processor is undefined if the ERL bit is set while the processor is executing instructions from kuseg. bit 1 EXL: Exception Level bit Set by the processor when any exception other than Reset, Soft Reset, or NMI exceptions is taken. 0 = Normal level 1 = Exception level When EXL is set: - Processor is running in Kernel Mode - Interrupts are disabled EPC, CauseBD and SRSCtl will not be updated if another exception is taken. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-29 PIC32MX Family Reference Manual Register 2-5: bit 0 STATUS: Status Register; CP0 Register 12, Select 0 (Continued) IE: Interrupt Enable bit Acts as the master enable for software and hardware interrupts: 0 = Interrupts are disabled 1 = Interrupts are enabled This bit may be modified separately via the DI and EI instructions DS61113C-page 2-30 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.12.6 Intctl: Interrupt Control Register (CP0 Register 12, Select 1) The Intctl register controls the vector spacing of the PIC32MX architecture. Register 2-6: R-0 — bit 31 Intctl: Interrupt Control Register; CP0 Register 12, Select 1 R-0 R-0 R-0 R-0 R-0 — — — — — r-x r-x — — bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — 2 bit 16 r-x — bit 15 r-x r-x r-x r-x r-x R/W-0 R/W-0 — — — — — VS<9:8> bit 8 R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x r-x VS<7:5> — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-29 bit 28-26 bit 25-10 bit 9-5 bit 4-0 R: Reserved R: Reserved Reserved: Write ‘0’; ignore read Must be written as ‘0’; returns ‘0’ on read. VS<9:5>: Vector Spacing bits This field specifies the spacing between each interrupt vector. Encoding Spacing Between Vectors (hex) Spacing Between Vectors (decimal) 16#00 16#000 0x 0 16#01 16#020 32 16#02 16#040 64 16#04 16#080 128 16#08 16#100 256 16#10 16#200 512 All other values are reserved. The operation of the processor is undefined if a reserved value is written to this field. Unimplemented: Read as ‘0’ Must be written as ‘0’; returns ‘0’ on read. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-31 PIC32MX Family Reference Manual 2.12.7 SRSCtl Register (CP0 Register 12, Select 2) The SRSCtl register controls the operation of GPR shadow sets in the processor. Table 2-10: Sources for New SRSCtlCSS on an Exception or Interrupt Exception Type Condition SRSCtlCSS Source Comment Exception All Non-Vectored Interrupt CauseIV = 0 Vectored EIC Interrupt CauseIV = 1 and Config3VEIC = 1 SRSCtlESS SRSCtlESS SRSCtlEICSS Treat as exception Source is external interrupt controller. Register 2-7: SRSCtl: Register; CP0 Register 12, Select 2 r-x r-x R-0 R-0 R-0 R-1 — — HSS<29:26> bit 31 r-x r-x — — bit 24 r-x — bit 23 r-x R-x R-x R-x R-x r-x r-x — EICSS<21:18> — — bit 16 R/W-0 R/W-0 R/W-0 R/W-0 r-x ESS<15:12> — bit 15 r-x R/W-0 R/W-0 — PSS<9:8> bit 8 R/W-0 R/W-0 r-0 r-0 R-0 R-0 R-0 R-0 PSS<7:6> 0<5:4> CSS<3:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-30 bit 29-26 bit 25-22 Reserved: Write ‘0’; ignore read Must be written as zeros; returns ‘0’ on read. HSS<29:26>: High Shadow Set bit This field contains the highest shadow set number that is implemented by this processor. A value of ‘0’ in this field indicates that only the normal GPRs are implemented. Possible values of this field for the PIC32MX processor are: 0 = One shadow set (normal GPR set) is present 1 = Two shadow sets are present 3 = Four shadow sets are present 2, 3-15 = Reserved The value in this field also represents the highest value that can be written to the ESS, EICSS, PSS, and CSS fields of this register, or to any of the fields of the SRSMAP register. The operation of the processor is undefined if a value larger than the one in this field is written to any of these other fields. Reserved: Write ‘0’; ignore read Must be written as ‘0’; returns ‘0’ on read. DS61113C-page 2-32 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU Register 2-7: bit 21-18 SRSCtl: Register; CP0 Register 12, Select 2 (Continued) EICSS<21:18>: External Interrupt Controller Shadow Set bits EIC Interrupt mode shadow set. This field is loaded from the external interrupt controller for each interrupt request and is used in place of the SRSMAP register to select the current shadow set for the interrupt. bit 17-16 Reserved: Write ‘0’; ignore read Must be written as ‘0’; returns ‘0’ on read. bit 15-12 ESS<15:12>: Exception Shadow Set bits This field specifies the shadow set to use on entry to Kernel mode caused by any exception other than a vectored interrupt. The operation of the processor is undefined if software writes a value into this field that is greater than 2 the value in the HSS field. bit 11-10 Reserved: Write ‘0’; ignore read Must be written as ‘0’; returns ‘0’ on read. bit 9-6 PSS<9:6>: Previous Shadow Set bits Since GPR shadow registers are implemented, this field is copied from the CSS field when an excep- tion or interrupt occurs. An ERET instruction copies this value back into the CSS field if StatusBEV = 0. This field is not updated on any exception which sets StatusERL to 1 (i.e., Reset, Soft Reset, NMI, cache error), an entry into EJTAG DEBUG mode, or any exception or interrupt that occurs with Sta- tusEXL = 1, or StatusBEV = 1. This field is not updated on an exception that occurs while StatusERL = 1. The operation of the processor is undefined if software writes a value into this field that is greater than the value in the HSS field. bit 5-4 Reserved: Write ‘0’; ignore read Must be written as ‘0’; returns ‘0’ on read. 3-0 CSS<3:0>: Current Shadow Set bits Since GPR shadow registers are implemented, this field is the number of the current GPR set. This field is updated with a new value on any interrupt or exception, and restored from the PSS field on an ERET. Table 2-10 describes the various sources from which the CSS field is updated on an exception or interrupt. This field is not updated on any exception which sets StatusERL to 1 (i.e., Reset, Soft Reset, NMI, cache error), an entry into EJTAG DEBUG mode, or any exception or interrupt that occurs with Sta- tusEXL = 1, or StatusBEV = 1. Neither is it updated on an ERET with StatusERL = 1 or StatusBEV = 1. This field is not updated on an exception that occurs while StatusERL = 1. The value of CSS can be changed directly by software only by writing the PSS field and executing an ERET instruction. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-33 PIC32MX Family Reference Manual 2.12.8 SRSMAP: Register (CP0 Register 12, Select 3) The SRSMAP register contains eight 4-bit fields that provide the mapping from an vector number to the shadow set number to use when servicing such an interrupt. The values from this register are not used for a non-interrupt exception, or a non-vectored interrupt (CauseIV = 0 or IntCtlVS = 0). In such cases, the shadow set number comes from SRSCtlESS. If SRSCtlHSS is ‘0’, the results of a software read or write of this register are unpredictable. The operation of the processor is undefined if a value is written to any field in this register that is greater than the value of SRSCtlHSS. The SRSMAP register contains the shadow register set numbers for vector numbers 7..0. The same shadow set number can be established for multiple interrupt vectors, creating a many-to-one mapping from a vector to a single shadow register set number. Register 2-8: R/W-0 bit 31 SRSMAP: Register; CP0 Register 12, Select 3 R/W-0 R/W-0 R/W-0 R/W-0 SSV7<31:28> R/W-0 R/W-0 SSV6<27:24> R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 SSV5<23:20> R/W-0 R/W-0 R/W-0 R/W-0 SSV4<19:16> R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 SSV3<15:12> R/W-0 R/W-0 R/W-0 R/W-0 SSV2<11:8> R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 SSV1<7:4> R/W-0 R/W-0 R/W-0 R/W-0 SSV0<3:0> R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-28 bit 27-24 bit 23-20 bit 19-16 bit 15-12 bit 11-8 bit 7-4 SSV7<31:28>: Shadow Set Vector 7 bits Shadow register set number for Vector Number 7 SSV6<27:24>: Shadow Set Vector 6 bits Shadow register set number for Vector Number 6 SSV5<23:20>: Shadow Set Vector 5 bits Shadow register set number for Vector Number 5 SSV4<19:16>: Shadow Set Vector 4 bits Shadow register set number for Vector Number 4 SSV3<15:12>: Shadow Set Vector 3 bits Shadow register set number for Vector Number 3 SSV2<11:8>: Shadow Set Vector 2 bits Shadow register set number for Vector Number 2 SSV1<7:4>: Shadow Set Vector 1 bits Shadow register set number for Vector Number 1 DS61113C-page 2-34 Preliminary © 2008 Microchip Technology Inc. Register 2-8: bit 3-0 SRSMAP: Register; CP0 Register 12, Select 3 (Continued) SSV0<3:0>: Shadow Set Vector 0 bit Shadow register set number for Vector Number 0 Section 2. MCU 2 MCU © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-35 PIC32MX Family Reference Manual 2.12.9 CAUSE Register (CP0 Register 13, Select 0) The CAUSE register primarily describes the cause of the most recent exception. In addition, fields also control software interrupt requests and the vector through which interrupts are dispatched. With the exception of the IP1..0, DC, IV and WP fields, all fields in the CAUSE register are read-only. IP7..2 are interpreted as the Requested Interrupt Priority Level (RIPL). Table 2-11: Cause Register ExcCode Field Exception Code Value Decimal Hex Mnemonic Description 0 16#00 Int Interrupt 4 16#04 AdEL Address error exception (load or instruction fetch) 5 16#05 AdES Address error exception (store) 6 16#06 IBE Bus error exception (instruction fetch) 7 16#07 DBE Bus error exception (data reference: load or store) 8 16#08 Sys Syscall exception 9 16#09 Bp Breakpoint exception 10 16#0a RI Reserved instruction exception 11 16#0b CPU Coprocessor Unusable exception 12 16#0c Ov Arithmetic Overflow exception 13 14-18 16#0d 16#0e-16#12 Tr Trap exception – Reserved DS61113C-page 2-36 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU Register 2-9: CAUSE: Register; CP0 Register 13, Select 0 R-x R-x R-x R-x R/W-0 R-0 BD TI CE<29:28> DC R bit 31 r-x r-x 0<25:24> bit 24 R/W-x R/W-0 r-x r-x r-x r-x r-x r-x IV R 0<21:16> bit 23 bit 16 2 R-x R-x R-x R-x R-x R-x R/W-x R/W-x RIPL<15:10> IP1..IP0<9:8> bit 15 bit 8 r-x 0 bit 7 R-x R-x R-x R-x R-x r-x r-x EXCCODE<6:2> 0<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 bit 30 bit 29-28 bit 27 bit 26 bit 25-24 BD: Branch Delay bit Indicates whether the last exception taken occurred in a branch delay slot: 0 = Not in delay slot 1 = In delay slot The processor updates BD only if StatusEXL was ‘0’ when the exception occurred. TI: Timer Interrupt bit Timer Interrupt. This bit denotes whether a timer interrupt is pending (analogous to the IP bits for other interrupt types): 0 = No timer interrupt is pending 1 = Timer interrupt is pending CE<29:28>: Coprocessor Exception bits Coprocessor unit number referenced when a Coprocessor Unusable exception is taken. This field is loaded by hardware on every exception, but is unpredictable for all exceptions except for Coprocessor Unusable. DC: Disable Count bit Disable Count register. In some power-sensitive applications, the COUNT register is not used and can be stopped to avoid unnecessary toggling 0 = Enable counting of COUNT register 1 = Disable counting of COUNT register R: bit Reserved: Write ‘0’; ignore read Must be written as ‘0’; returns ‘0’ on read. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-37 PIC32MX Family Reference Manual Register 2-9: bit 23 bit 22 bit 21-16 bit 15-10 bit 9-8 bit 7 bit 6-2 bit 1-0 CAUSE: Register; CP0 Register 13, Select 0 (Continued) IV: Interrupt Vector bit Indicates whether an interrupt exception uses the general exception vector or a special interrupt vector 0 = Use the general exception vector (16#180) 1 = Use the special interrupt vector (16#200) If the CauseIV is 1 and StatusBEV is 0, the special interrupt vector represents the base of the vectored interrupt table. R: bit Reserved: Write ‘0’; ignore read Must be written as ‘0’; returns ‘0’ on read. RIPL<15:10>: Requested Interrupt Priority Level bits Requested Interrupt Priority Level.\ This field is the encoded (0..63) value of the requested interrupt. A value of ‘0’ indicates that no interrupt is requested. IP1..IP0<9:8>: Controls the request for software interrupts: 0 = No interrupt requested 1 = Request software interrupt These bits are exported to the system interrupt controller for prioritization in EIC interrupt mode with other interrupt sources Reserved: Write ‘0’; ignore read Must be written as ‘0’; returns ‘0’ on read. EXCCODE<6:2>: Exception Code bits Exception code - see Table 2-11 Reserved: Write ‘0’; ignore read Must be written as ‘0’; returns ‘0’ on read. DS61113C-page 2-38 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.12.10 EPC Register (CP0 Register 14, Select 0) The Exception Program Counter (EPC) is a read/write register that contains the address at which processing resumes after an exception has been serviced. All bits of the EPC register are significant and are writable. For synchronous (precise) exceptions, the EPC contains one of the following: • The virtual address of the instruction that was the direct cause of the exception. • The virtual address of the immediately preceding BRANCH or JUMP instruction, when the exception causing instruction is in a branch delay slot and the Branch Delay bit in the CAUSE register is set. On new exceptions, the processor does not write to the EPC register when the EXL bit in the 2 STATUS register is set, however, the register can still be written via the MTC0 instruction. Since the PIC32 family implements MIPS16e ASE, a read of the EPC register (via MFC0) returns the following value in the destination GPR: GPR[rt] ← ExceptionPC31..1 || ISAMode0 That is, the upper 31 bits of the exception PC are combined with the lower bit of the ISAMode field and written to the GPR. Similarly, a write to the EPC register (via MTC0) takes the value from the GPR and distributes that value to the exception PC and the ISAMode field, as follows ExceptionPC ← GPR[rt]31..1 || 0 ISAMode ← 2#0 || GPR[rt]0 That is, the upper 31 bits of the GPR are written to the upper 31 bits of the exception PC, and the lower bit of the exception PC is cleared. The upper bit of the ISAMode field is cleared and the lower bit is loaded from the lower bit of the GPR. Register 2-10: R/W-x bit 31 EPC: Register; CP0 Register 14, Select 0 R/W-x R/W-x R/W-x R/W-x EPC<31:24> R/W-x R/W-x R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x EPC<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x EPC<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x EPC<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 EPC<31:0>: Exception Program Counter bits © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-39 PIC32MX Family Reference Manual 2.12.11 PRID Register (CP0 Register 15, Select 0) The Processor Identification (PRID) register is a 32 bit read-only register that contains information identifying the manufacturer, manufacturer options, processor identification, and revision level of the processor. Register 2-11: PRID: Register; CP0 Register 15, Select 0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R<31:24> bit 31 bit 24 R-1 bit 23 R-1 R-1 R-1 R-1 R-1 R-1 R-1 COMPANY ID<23:16> bit 16 R-0x87 bit 15 R-0x87 R-0x87 R-0x87 R-0x87 PROCESSOR ID<15:8> R-0x87 R-0x87 R-0x87 bit 8 R-Preset bit 7 R-Preset R-Preset R-Preset R-Preset REVISION<7:0> R-Preset R-Preset R-Preset bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-24 bit 23-16 bit 15-8 bit 7-0 bit 7-5 bit 4-2 bit 1-0 R<31:24>: Reserved Must be ignored on write and read as ‘0’ COMPANY ID<23:16>: Identifies the company that designed or manufactured the processor. In the PIC32MX this field contains a value of 1 to indicate MIPS Technologies, Inc. PROCESSOR ID<15:8>: Identifies the type of processor. This field allows software to distinguish between the various types of MIPS Technologies processors. REVISION<7:0>: Specifies the revision number of the processor. This field allows software to distinguish between one revision and another of the same processor type. This field is broken up into the following three subfields. MAJOR REVISION<7:5>: This number is increased on major revisions of the processor core. MINOR REVISION<4:2>: This number is increased on each incremental revision of the processor and reset on each new major revision. PATCH LEVEL<1:0>: If a patch is made to modify an older revision of the processor, this field will be incremented. DS61113C-page 2-40 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU MCU 2.12.12 EBASE Register (CP0 Register 15, Select 1) The EBASE register is a read/write register containing the base address of the exception vectors used when StatusBEV equals ‘0’, and a read-only CPU number value that may be used by software to distinguish different processors in a multi-processor system. The EBASE register provides the ability for software to identify the specific processor within a multi-processor system, and allows the exception vectors for each processor to be different, especially in systems composed of heterogeneous processors. Bits 31..12 of the EBASE register are concatenated with zeros to form the base of the exception vectors when StatusBEV is ‘0’. The exception vector base address comes from the fixed defaults when StatusBEV is ‘1’, or for any EJTAG Debug exception. The Reset state of bits 31..12 of the EBASE register initialize the exception base register to 16#8000.0000. 2 Bits 31..30 of the EBASE Register are fixed with the value 2#10 to force the exception base address to be in the kseg0 or kseg1 unmapped virtual address segments. If the value of the exception base register is to be changed, this must be done with StatusBEV equal ‘1’. The operation of the processor is undefined if the Exception Base field is written with a different value when StatusBEV is ‘0’. Combining bits 31..20 with the Exception Base field allows the base address of the exception vectors to be placed at any 4 KBbyte page boundary. Register 2-12: R-1 1 bit 31 EBASE: Register; CP0 Register 15, Select 1 R-0 R/W-0 R/W-0 R/W-0 R/W-0 0 EXCEPTION BASE<29:24> R/W-0 R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 R/W-0 R/W-0 EXCEPTION BASE<23:16> R/W-0 R/W-0 R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 EXCEPTION BASE<15:12> R/W-0 r-0 r-0 r R-0 R-0 CPUNUM<9:8> bit 8 R-0 bit 7 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CPUNUM<7:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 bit 30 bit 29-12 bit 11-10 1: One bit This bit is ignored on write and returns one on read. 0: Zero bit This bit is ignored on write and returns ‘0’ on read. EXCEPTION BASE<29:12>: In conjunction with bits 31..30, this field specifies the base address of the exception vectors when StatusBEV is ‘0’. Reserved: Must be written as ‘0’; returns ‘0’ on read. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-41 PIC32MX Family Reference Manual Register 2-12: EBASE: Register; CP0 Register 15, Select 1 (Continued) bit 9-0 CPUNUM<9:0>: This field specifies the number of the CPU in a multi-processor system and can be used by software to distinguish a particular processor from the others. In a single processor system, this value is set to ‘0’. DS61113C-page 2-42 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.12.13 CONFIG Register (CP0 Register 16, Select 0) The CONFIG register specifies various configuration and capabilities information. Most of the fields in the CONFIG register are initialized by hardware during the Reset exception process, or are constant. Table 2-12: Cache Coherency Attributes C(2:0) Value Cache Coherency Attribute 2 Uncached 3 Cacheable 2 Register 2-13: CONFIG: Register; CP0 Register 16, Select 0 R-1 R-0 R-1 R-0 R/W-0 R/W-1 R/W-0 r-0 M K23<30:28> KU<27:25> 0 bit 31 bit 24 r-x R-0 R-0 R-0 r-x r-x r-x R-1 0 UDI SB MDU DS bit 23 bit 16 R-0 BE bit 15 R-0 R-0 AT<14:13> R-0 R-0 R-1 AR<12:10> R-0 R-1 MT<9:8> bit 8 R-1 r-x r-x r-x r-x R/W-0 R/W-1 R/W-0 MT K0<2:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 bit 30-28 bit 27-25 bit 24-23 bit 22 M: This bit is hardwired to ‘1’ to indicate the presence of the CONFIG1 register. K23<30:28>: kseg2 and kseg3 bits This field controls the cacheability of the kseg2 and kseg3 address segments. Refer to Table 2-12 for the field encoding. KU<27:25>: kuseg and useg bits This field controls the cacheability of the kuseg and useg address segments. Refer to Table 2-12 for the field encoding. Reserved: Write ‘0’; ignore read Must be written as ‘0’. Returns ‘0’ on reads. UDI: User Defined bit This bit indicates that CorExtend User Defined Instructions have been implemented. 0 = No User Defined Instructions are implemented 1 = User Defined Instructions are implemented © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-43 PIC32MX Family Reference Manual Register 2-13: CONFIG: Register; CP0 Register 16, Select 0 (Continued) bit 21 SB: SimpleBE bit Indicates whether SimpleBE Bus mode is enabled. 0 = No reserved byte enables on internal bus interface 1 = Only simple byte enables allowed on internal bus interface bit 20 MDU: Multiply/Divide Unit bit This bit indicates the type of Multiply/Divide Unit present 0 = Fast, high-performance MDU bit 19-17 Reserved: Write ‘0’; ignore read Must be written as 0. Returns ‘0’ on reads. bit 16 DS: Dual SRAM bit 0 = Unified instruction/data SRAM internal bus interface 1 = Dual instruction/data SRAM internal bus interfaces Note: The PIC32MX family currently uses Dual SRAM-style interfaces internally. bit 15 BE: Big Endian bit Indicates the Endian mode in which the processor is running, PIC32MX is always little endian. 0 = Little endian 1 = Big enidan bit 14-13 AT<14:13>: Architecture Type bits Architecture type implemented by the processor. This field is always ‘00’ to indicate the MIPS32 architecture. bit 12-10 AR<12:10>: Architecture Revision Level bits Architecture revision level. This field is always ‘001’ to indicate MIPS32 Release 2. 0: Release 1 1: Release 2 2-7: Reserved bit 9-7 MT<9:7>: MMU Type bits 3: Fixed mapping 0-2, 4-7: Reserved bit 6-3 Reserved: Write ‘0’; ignore read Must be written as zeros; returns zeros on reads bit 2-0 K0<2:0>: Kseg0 bits Kseg0 coherency algorithm. Refer to XREF Table 2-12 for the field encoding. DS61113C-page 2-44 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU MCU 2.12.14 CONFIG1 Register (CP0 Register 16, Select 1) The CONFIG1 register is an adjunct to the CONFIG register and encodes additional information about capabilities present on the core. All fields in the CONFIG1 register are read-only. Register 2-14: CONFIG1: CONFIG1 Register; CP0 Register 16, Select 1 R-1 R-x R-x R-x R-x R-x R-x R-x M MMU Size<30:25> IS bit 31 bit 24 R-x R-x IS<23:22> bit 23 R-x R-x R-x IL<21:19> R-x R-x R-x 2 IA<18:16> bit 16 R-x R-x R-x DS<15:13> bit 15 R-x R-x R-x DL<12:10> R-x R-x DA<9:8> bit 8 R-x DA bit 7 R-0 R-0 R-0 R-0 R-1 R-x R-0 C2 MD PC WR CA EP FP bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 bit 30-25 bit 24-22 bit 21-19 bit 18-16 bit 15-13 bit 12-10 bit 9-7 M: bit This bit is hardwired to ‘1’ to indicate the presence of the CONFIG2 register. MMU Size: bits This field contains the number of entries in the TLB minus one; since the PIC32MX has no TLB, this field is ‘0’. IS: Instruction Cache Sets bits This field contains the number of instruction cache sets per way; since the M4K core does not include caches, this field is always read as ‘0’. IL: Instruction-Cache Line bits This field contains the instruction cache line size; since the M4K core does not include caches, this field is always read as ‘0’. IA: Instruction-Cache Associativity bits This field contains the level of instruction cache associativity; since the M4K core does not include caches, this field is always read as ‘0’. DS: Data-Cache Sets bits This field contains the number of data cache sets per way; since the M4K core does not include caches, this field is always read as ‘0’. DL: Data-Cache Line bits This field contains the data cache line size; since the M4K core does not include caches, this field is always read as ‘0’. DA: Data-Cache Associativity bits This field contains the type of set associativity for the data cache; since the M4K core does not include caches, this field is always read as ‘0’. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-45 PIC32MX Family Reference Manual Register 2-14: CONFIG1: CONFIG1 Register; CP0 Register 16, Select 1 (Continued) bit 6 C2: Coprocessor 2 bit Coprocessor 2 present. 0 = No coprocessor is attached to the COP2 interface 1 = A coprocessor is attached to the COP2 interface Since coprocessor 2 is not implemented in the PIC32MX family of microcontrollers, this bit will read ‘0’. bit 5 MD: MDMX bit MDMX implemented. This bit always reads as ‘0‘ because MDMX is not supported. bit 4 PC: Performance Counter bit Performance Counter registers implemented. Always a ‘0‘ since the PIC32MX core does not contain Performance Counters. bit 3 WR: Watch Register bit Watch registers implemented. 0 = No Watch registers are present 1 = One or more Watch registers are present Note: The PIC32MX does not implement watch registers, therefore this bit always reads ‘0’. bit 2 CA: Code Compression Implemented bit 0 = No MIPS16e present 1 = MIPS16e is implemented bit 1 EP: EJTAG Present bit This bit is always set to indicate that the core implements EJTAG. bit 0 FP: FPU Implemented bit This bit is always ‘0’ since the core does not contain a floating point unit. DS61113C-page 2-46 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.12.15 CONFIG2 (CP0 Register 16, Select 2) The CONFIG2 register is an adjunct to the CONFIG register and is reserved to encode additional capabilities information. CONFIG2 is allocated for showing the configuration of level 2/3 caches. These fields are reset to ‘0’ because L2/L3 caches are not supported by the PIC32MX core. All fields in the CONFIG2 register are read-only. Register 2-15: CONFIG2: CONFIG2 Register; CP0 Register 16, Select 2 R-1 r-0 r-0 r-0 r-0 r-0 r-0 r-0 M 0 0 0 0 0 0 0 bit 31 bit 24 2 r-0 0 bit 23 r-0 r-0 r-0 r-0 r-0 r-0 r-0 0 0 0 0 0 0 0 bit 16 r-0 0 bit 15 r-0 r-0 r-0 r-0 r-0 r-0 r-0 0 0 0 0 0 0 0 bit 8 r-0 0 bit 7 r-0 r-0 r-0 r-0 r-0 r-0 r-0 0 0 0 0 0 0 0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 bit 30-0 M: bit This bit is hardwired to ‘1’ to indicate the presence of the CONFIG3 register. Reserved © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-47 PIC32MX Family Reference Manual 2.12.16 CONFIG3 Register (CP0 Register 16, Select 3) The CONFIG3 register encodes additional capabilities. All fields in the CONFIG3 register are read-only. Register 2-16: CONFIG3: CONFIG3 Register; CP0 Register 16, Select 3 R-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 M 0 0 0 0 0 0 0 bit 31 bit 24 r-0 0 bit 23 r-0 r-0 r-0 r-0 r-0 r-0 r-0 0 0 0 0 0 0 0 bit 16 r-0 0 bit 15 r-0 r-0 r-0 r-0 r-0 r-0 r-0 0 0 0 0 0 0 0 bit 8 r-0 R-1 R-1 R-0 r-0 r-0 R-0 R-0 0 VEIC VInt SP 0 0 SM TL bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 bit 30-7 bit 6 bit 5 bit 4 bit 3-2 M: Reserved This bit is reserved to indicate that a CONFIG4 register is present. With the current architectural definition, this bit should always read as a ‘0’. Reserved: Write ‘0’; ignore read Must be written as zeros; returns zeros on read. VEIC: Support for an external interrupt controller is implemented. 0 = Support for EIC Interrupt mode is not implemented 1 = Support for EIC Interrupt mode is implemented Note: PIC32MX internally implements a MIPS “external interrupt controller”, therefore this bit reads ‘1’. VINT: Vector Interrupt bit Vectored interrupts implemented. This bit indicates whether vectored interrupts are implemented. 0 = Vector interrupts are not implemented 1 = Vector interrupts are implemented On the PIC32MX core, this bit is always a ‘1’ since vectored interrupts are implemented. SP: Support Page bit Small (1 KByte) page support is implemented, and the PAGEGRAIN register exists. 0 = Small page support is not implemented 1 = Small page support is implemented Note: PIC32MX always reads ‘0’ since PIC32MX does not implement small page support. 0: Must be written as zeros; returns zeros on read. DS61113C-page 2-48 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU Register 2-16: CONFIG3: CONFIG3 Register; CP0 Register 16, Select 3 (Continued) bit 1 SM: SmartMIPS™ bit SmartMIPS™ ASE implemented. This bit indicates whether the SmartMIPS ASE is implemented. Since SmartMIPS is present on the PIC32MX core, this bit will always be ‘0’. 0 = SmartMIPS ASE is not implemented 1 = SmartMIPS ASE is implemented bit 0 TL: Trace Logic bit Trace Logic implemented. This bit indicates whether PC or data trace is implemented. 0 = On-chip trace logic (PDTrace™) is not implemented 1 = On-chip trace logic (PDTrace™) is implemented Note: PIC32MX does not implement PDTrace™ on-chip trace logic, therefore this bit always 2 reads ‘0’. MCU © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-49 PIC32MX Family Reference Manual 2.12.17 DEBUG Register (CP0 Register 23, Select 0) The DEBUG register is used to control the debug exception and provide information about the cause of the debug exception and when re-entering at the debug exception vector due to a normal exception in DEBUG mode. The read-only information bits are updated every time the debug exception is taken or when a normal exception is taken when already in DEBUG mode. Only the DM bit and the EJTAGver field are valid when read from Non-DEBUG mode; the values of all other bits and fields are unpredictable. Operation of the processor is undefined if the DEBUG register is written from Non-DEBUG mode. Some of the bits and fields are only updated on debug exceptions and/or exceptions in DEBUG mode, as shown below: • DSS, DBp, DDBL, DDBS, DIB, DINT are updated on both debug exceptions and on exceptions in Debug modes • DExcCode is updated on exceptions in DEBUG mode, and is undefined after a debug exception • Halt and Doze are updated on a debug exception, and are undefined after an exception in DEBUG mode • DBD is updated on both debug and on exceptions in Debug modes All bits and fields are undefined when read from normal mode, except EJTAGver and DM. DS61113C-page 2-50 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU Register 2-17: R-U DBD bit 31 DEBUG: Register; CP0 Register 23, Select 0 R-0 R-0 R/W-0 R-U DM NODCR LSNM DOZE R-U HALT R/W-1 COUNTDM R/W-0 IBUSEP bit 24 R-0 R-0 R/W-0 R/W-0 R-0 R-0 R-0 R-1 MCHECKP CACHEEP DBUSEP IEXI DDBSIMPR DDBLIMPR VER<7:6> bit 23 bit 16 2 R-0 R-U R-U R-U R-U R-U R-0 R/W-0 VER DEXCCODE<14:10 NOSST SST bit 15 bit 8 R-0 R-0 R<7:6> bit 7 R-U DINT R-U R-U R-U R-U R-U DIB DDBS DDBL DBP DSS bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 DBD: Indicates whether the last debug exception or exception in DEBUG mode, occurred in a branch delay slot: 0 = Not in delay slot 1 = In delay slot DM: Indicates that the processor is operating in DEBUG mode: 0 = Processor is operating in Non-DEBUG mode 1 = Processor is operating in DEBUG mode NODCR: Indicates whether the dseg memory segment is present and the Debug Control Register is accessible: 0 = dseg is present 1 = No dseg present LSNM: Controls access of load/store between dseg and main memory: 0 = Load/stores in dseg address range goes to dseg 1 = Load/stores in dseg address range goes to main memory DOZE: Indicates that the processor was in any kind of Low-Power mode when a debug exception occurred: 0 = Processor not in Low-Power mode when debug exception occurred 1 = Processor in Low-Power mode when debug exception occurred HALT: Indicates that the internal system bus clock was stopped when the debug exception occurred: 0 = Internal system bus clock stopped 1 = Internal system bus clock running © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-51 PIC32MX Family Reference Manual Register 2-17: DEBUG: Register; CP0 Register 23, Select 0 (Continued) bit 25 COUNTDM: Indicates the Count register behavior in DEBUG mode. 0 = Count register stopped in DEBUG mode 1 = Count register is running in DEBUG mode bit 24 IBUSEP: Instruction fetch Bus Error exception Pending. Set when an instruction fetch bus error event occurs or if a ‘1’ is written to the bit by software. Cleared when a Bus Error exception on instruction fetch is taken by the processor, and by Reset. If IBUSEP is set when IEXI is cleared, a Bus Error exception on instruction fetch is taken by the processor, and IBUSEP is cleared. bit 23 MCHECKP: Indicates that an imprecise Machine Check exception is pending. All Machine Check exceptions are precise on the PIC32MX processor so this bit will always read as ‘0’. bit 22 CACHEEP: Indicates that an imprecise Cache Error is pending. Cache Errors cannot be taken by the PIC32MX core so this bit will always read as ‘0’. bit 21 DBUSEP: Data access Bus Error exception Pending. Covers imprecise bus errors on data access, similar to behavior of IBUSEP for imprecise bus errors on an instruction fetch. bit 20 IEXI: Imprecise Error eXception Inhibit controls exceptions taken due to imprecise error indications. Set when the processor takes a debug exception or exception in DEBUG mode. Cleared by execution of the DERET instruction; otherwise modifiable by DEBUG mode software. When IEXI is set, the imprecise error exception from a bus error on an instruction fetch or data access, cache error, or machine check is inhibited and deferred until the bit is cleared. bit 19 DDBSIMPR: Indicates that an imprecise Debug Data Break Store exception was taken. All data breaks are precise on the PIC32MX core, so this bit will always read as ‘0’. bit 18 DDBLIMPR: Indicates that an imprecise Debug Data Break Load exception was taken. All data breaks are precise on the PIC32MX core, so this bit will always read as ‘0’. bit 17-15 VER: EJTAG version bit 14-10 DEXCCODE: Indicates the cause of the latest exception in DEBUG mode. The field is encoded as the ExcCode field in the CAUSE register for those normal exceptions that may occur in DEBUG mode. Value is undefined after a debug exception. bit 9 NOSST: Indicates whether the single-step feature controllable by the SST bit is available in this implementation: 0 = Single-step feature available 1 = No single-step feature available bit 8 SST: Controls if debug single step exception is enabled: 0 = No debug single-step exception enabled 1 = Debug single step exception enabled bit 7-6 Reserved: Must be written as zeros; returns zeros on reads. bit 5 DINT: Indicates that a debug interrupt exception occurred. Cleared on exception in DEBUG mode. 0 = No debug interrupt exception 1 = Debug interrupt exception DS61113C-page 2-52 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU Register 2-17: DEBUG: Register; CP0 Register 23, Select 0 (Continued) bit 4 DIB: Indicates that a debug instruction break exception occurred. Cleared on exception in DEBUG mode. 0 = No debug instruction exception 1 = Debug instruction exception bit 3 DDBS: Indicates that a debug data break exception occurred on a store. Cleared on exception in DEBUG mode. 0 = No debug data exception on a store 1 = Debug instruction exception on a store bit 2 DDBL: 2 Indicates that a debug data break exception occurred on a load. Cleared on exception in DEBUG mode. 0 = No debug data exception on a load 1 = Debug instruction exception on a load bit 1 DBP: Indicates that a debug software breakpoint exception occurred. Cleared on exception in DEBUG mode. 0 = No debug software breakpoint exception 1 = Debug software breakpoint exception bit 0 DSS: Indicates that a debug single-step exception occurred. Cleared on exception in DEBUG mode. 0 = No debug single-step exception 1 = Debug single-step exception MCU © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-53 PIC32MX Family Reference Manual 2.12.18 DEPC Register (CP0 Register 24, Select 0) The Debug Exception Program Counter (DEPC) register is a read/write register that contains the address at which processing resumes after a debug exception or DEBUG mode exception has been serviced. For synchronous (precise) debug and DEBUG mode exceptions, the DEPC contains either: • The virtual address of the instruction that was the direct cause of the debug exception, or • The virtual address of the immediately preceding branch or jump instruction, when the debug exception causing instruction is in a branch delay slot, and the Debug Branch Delay (DBD) bit in the Debug register is set. For asynchronous debug exceptions (debug interrupt), the DEPC contains the virtual address of the instruction where execution should resume after the debug handler code is executed. Since the PIC32 family implements the MIPS16e ASE, a read of the DEPC register (via MFC0) returns the following value in the destination GPR: GPR[rt] = DebugExceptionPC31..1 || ISAMode0 That is, the upper 31 bits of the debug exception PC are combined with the lower bit of the ISAMode field and written to the GPR. Similarly, a write to the DEPC register (via MTC0) takes the value from the GPR and distributes that value to the debug exception PC and the ISAMode field, as follows: DebugExceptionPC = GPR[rt]31..1 || 0 ISAMode = 2#0 || GPR[rt]0 That is, the upper 31 bits of the GPR are written to the upper 31 bits of the debug exception PC, and the lower bit of the debug exception PC is cleared. The upper bit of the ISAMode field is cleared and the lower bit is loaded from the lower bit of the GPR. DS61113C-page 2-54 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU Register 2-18: R/W-x bit 31 DEPC: Debug Exception Program Counter Register; CP0 Register 24, Select 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x DEPC<31:24> R/W-x bit 24 R/W-x bit 23 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x DEPC<23:16> R/W-x R/W-x DEPC<15:8> R/W-x R/W-x R/W-x R/W-x bit 16 2 R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x DEPC<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 DEPC<31:0>: Debug Exception Program Counter bits The DEPC register is updated with the virtual address of the instruction that caused the debug exception. If the instruction is in the branch delay slot, then the virtual address of the immediately preceding branch or jump instruction is placed in this register. Execution of the DERET instruction causes a jump to the address in the DEPC. MCU © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-55 PIC32MX Family Reference Manual 2.12.19 ErrorEPC (CP0 Register 30, Select 0) The ErrorEPC register is a read/write register, similar to the EPC register, except that ErrorEPC is used on error exceptions. All bits of the ErrorEPC register are significant and must be writable. It is also used to store the program counter on Reset, Soft Reset, and nonmaskable interrupt (NMI) exceptions. The ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error. This address can be: • The virtual address of the instruction that caused the exception • The virtual address of the immediately preceding branch or jump instruction when the error causing instruction is in a branch delay slot Unlike the EPC register, there is no corresponding branch delay slot indication for the ErrorEPC register. Since the PIC32 family implements the MIPS16e ASE, a read of the ErrorEPC register (via MFC0) returns the following value in the destination GPR: GPR[rt] = ErrorExceptionPC31..1 || ISAMode0 That is, the upper 31 bits of the error exception PC are combined with the lower bit of the ISAMode field and written to the GPR. Similarly, a write to the ErrorEPC register (via MTC0) takes the value from the GPR and distributes that value to the error exception PC and the ISAMode field, as follows: ErrprExceptionPC = GPR[rt]31..1 || 0 ISAMode = 2#0 || GPR[rt]0 That is, the upper 31 bits of the GPR are written to the upper 31 bits of the error exception PC, and the lower bit of the error exception PC is cleared. The upper bit of the ISAMode field is cleared and the lower bit is loaded from the lower bit of the GPR. Register 2-19: R/W-x bit 31 ErrorEPC: Error Exception Program Counter Register; CP0 Register 30, Select 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ErrorEPC<31:24> R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x ErrorEPC<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x ErrorEPC<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x ErrorEPC<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 ErrorEPC<31:0>: Error Exception Program Counter bits DS61113C-page 2-56 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.12.20 DeSave Register (CP0 Register 31, Select 0) The Debug Exception Save (DeSave) register is a read/write register that functions as a simple memory location. This register is used by the debug exception handler to save one of the GPRs that is then used to save the rest of the context to a pre-determined memory area (such as in the EJTAG Probe). This register allows the safe debugging of exception handlers and other types of code where the existence of a valid stack for context saving cannot be assumed. Register 2-20: DeSave: Debug Exception Save Register; CP0 Register 31, Select 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 31 DESAVE<31:24> bit 24 2 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x DESAVE<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x DESAVE<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x DESAVE<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 DESAVE<31:0>: Debug Exception Save bits Scratch Pad register used by Debug Exception code. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-57 PIC32MX Family Reference Manual 2.13 MIPS16e™ EXECUTION When the core is operating in MIPS16e mode, instruction fetches only require 16-bits of data to be returned. For improved efficiency, however, the core will fetch 32-bits of instruction data whenever the address is word-aligned. Thus for sequential MIPS16e code, fetches only occur for every other instruction, resulting in better performance and reduced system power. 2.14 MEMORY MODEL Virtual addresses used by software are converted to physical addresses by the memory management unit (MMU) before being sent to the CPU busses. The PIC32MX CPU uses a fixed mapping for this conversion. For more information regarding the system memory model, see Section 3. “Memory Organization”. Figure 2-13: Address Translation During SRAM Access Instruction Address Calculator Virtual Address Physical Address FMT SRAM Interface Instn SRAM Data Address Calculator Virtual Address Physical Address Data SRAM 2.14.1 Cacheability The CPU uses the virtual address of an instruction fetch, load or store to determine whether to access the cache or not. Memory accesses within kseg0, or useg/kuseg can be cached, while accesses within kseg1 are non-cacheable. The CPU uses the CCA bits in the CONFIG register to determine the cacheability of a memory segment. A memory access is cacheable if its corresponding CCA = 0112. For more information on cache operation, see Section 4. “Prefetch Cache Module”. 2.14.1.1 Little Endian Byte Ordering On CPUs that address memory with byte resolution, there is a convention for multi-byte data items that specify the order of high-order to low-order bytes. Big-endian byte-ordering is where the lowest address has the Most Significant Byte. Little-endian ordering is where the lowest address has the Least Significant Byte of a multi-byte datum. The PIC32MX CPU family supports little-endian byte ordering. DS61113C-page 2-58 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU Figure 2-14: Big Endian Byte Ordering Higher Address Lower Address Word Address 12 8 4 0 Bit # 31 24 23 16 15 12 13 14 8 9 10 4 5 6 0 1 2 87 15 11 7 3 0 } 1 word = 4 bytes 2 Figure 2-15: Little Endian Byte Ordering Higher Address Lower Address Word Address 12 8 4 0 Bit # 31 24 23 16 15 87 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MCU © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-59 PIC32MX Family Reference Manual 2.15 CPU INSTRUCTIONS, GROUPED BY FUNCTION CPU instructions are organized into the following functional groups: • Load and store • Computational • Jump and branch • Miscellaneous • Coprocessor Each instruction is 32 bits long. 2.15.1 CPU Load and Store Instructions MIPS processors use a load/store architecture; all operations are performed on operands held in processor registers and main memory is accessed only through load and store instructions. 2.15.1.1 Types of Loads and Stores There are several different types of load and store instructions, each designed for a different purpose: • Transferring variously-sized fields (for example, LB, SW) • Trading transferred data as signed or unsigned integers (for example, LHU) • Accessing unaligned fields (for example, LWR, SWL) • Atomic memory update (read-modify-write: for instance, LL/SC) 2.15.1.2 List of CPU Load and Store Instructions The following data sizes (as defined in the AccessLength field) are transferred by CPU load and store instructions: • Byte • Halfword • Word Signed and unsigned integers of different sizes are supported by loads that either sign-extend or zero-extend the data loaded into the register. Unaligned words and doublewords can be loaded or stored in just two instructions by using a pair of special instructions. For loads a LWL instruction is paired with a LWR instruction. The load instructions read the left-side or right-side bytes (left or right side of register) from an aligned word and merge them into the correct bytes of the destination register. 2.15.1.3 Loads and Stores Used for Atomic Updates The paired instructions, Load Linked and Store Conditional, can be used to perform an atomic read-modify-write of word or doubleword cached memory locations. These instructions are used in carefully coded sequences to provide one of several synchronization primitives, including test-and-set, bit-level locks, semaphores, and sequencers and event counts. 2.15.1.4 Coprocessor Loads and Stores If a particular coprocessor is not enabled, loads and stores to that processor cannot execute and the attempted load or store causes a Coprocessor Unusable exception. Enabling a coprocessor is a privileged operation provided by the System Control Coprocessor, CP0. DS61113C-page 2-60 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.15.2 Computational Instructions Two’s complement arithmetic is performed on integers represented in 2s complement notation. These are signed versions of the following operations: • Add • Subtract • Multiply • Divide The add and subtract operations labelled “unsigned” are actually modulo arithmetic without over- flow detection. There are also unsigned versions of multiply and divide, as well as a full complement of shift and 2 logical operations. Logical operations are not sensitive to the width of the register. MIPS32 provided 32-bit integers and 32-bit arithmetic. 2.15.2.1 Shift Instructions The ISA defines two types of shift instructions: • Those that take a fixed shift amount from a 5-bit field in the instruction word (for instance, SLL, SRL) • Those that take a shift amount from the low-order bits of a general register (for instance, SRAV, SRLV) 2.15.2.2 Multiply and Divide Instructions The multiply instruction performs 32-bit by 32-bit multiplication and creates either 64-bit or 32-bit results. Divide instructions divide a 64-bit value by a 32-bit value and create 32-bit results. With one exception, they deliver their results into the HI and LO special registers. The MUL instruction delivers the lower half of the result directly to a GPR. • Multiply produces a full-width product twice the width of the input operands; the low half is loaded into LO and the high half is loaded into HI. • Multiply-Add and Multiply-Subtract produce a full-width product twice the width of the input operations and adds or subtracts the product from the concatenated value of HI and LO. The low half of the addition is loaded into LO and the high half is loaded into HI. • Divide produces a quotient that is loaded into LO and a remainder that is loaded into HI. The results are accessed by instructions that transfer data between HI/LO and the general registers. © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-61 PIC32MX Family Reference Manual 2.15.3 Jump and Branch Instructions 2.15.3.1 Types of Jump and Branch Instructions Defined by the ISA The architecture defines the following jump and branch instructions: • PC-relative conditional branch • PC-region unconditional jump • Absolute (register) unconditional jump • A set of procedure calls that record a return link address in a general register. 2.15.3.2 Branch Delays and the Branch Delay Slot All branches have an architectural delay of one instruction. The instruction immediately following a branch is said to be in the branch delay slot. If a branch or jump instruction is placed in the branch delay slot, the operation of both instructions is undefined. By convention, if an exception or interrupt prevents the completion of an instruction in the branch delay slot, the instruction stream is continued by re-executing the branch instruction. To permit this, branches must be restartable; procedure calls may not use the register in which the return link is stored (usually GPR 31) to determine the branch target address. 2.15.3.3 Branch and Branch Likely There are two versions of conditional branches; they differ in the manner in which they handle the instruction in the delay slot when the branch is not taken and execution falls through. • Branch instructions execute the instruction in the delay slot. • Branch likely instructions do not execute the instruction in the delay slot if the branch is not taken (they are said to nullify the instruction in the delay slot). Although the Branch Likely instructions are included in this specification, software is strongly encouraged to avoid the use of the Branch Likely instructions, as they will be removed from a future revision of the MIPS Architecture. 2.15.4 Miscellaneous Instructions 2.15.4.1 Instruction Serialization (SYNC and SYNCI) In normal operation, the order in which load and store memory accesses appear to a viewer outside the executing processor (for instance, in a multiprocessor system) is not specified by the architecture. The SYNC instruction can be used to create a point in the executing instruction stream at which the relative order of some loads and stores can be determined: loads and stores executed before the SYNC are completed before loads and stores after the SYNC can start. The SYNCI instruction synchronizes the processor caches with previous writes or other modifications to the instruction stream. 2.15.4.2 Exception Instructions Exception instructions transfer control to a software exception handler in the kernel. There are two types of exceptions, conditional and unconditional. These are caused by the following instructions: syscall, trap, and break. Trap instructions, which cause conditional exceptions based upon the result of a comparison System call and breakpoint instructions, which cause unconditional exceptions 2.15.4.3 Conditional Move Instructions MIPS32 includes instructions to conditionally move one CPU general register to another, based on the value in a third general register. DS61113C-page 2-62 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU 2.15.4.4 NOP Instructions The NOP instruction is actually encoded as an all-zero instruction. MIPS processors special-case this encoding as performing no operation, and optimize execution of the instruction. In addition, SSNOP instruction, takes up one issue cycle on any processor, including super-scalar implementations of the architecture. 2.15.5 Coprocessor Instructions 2.15.5.1 What Coprocessors Do Coprocessors are alternate execution units, with register files separate from the CPU. In abstrac- tion, the MIPS architecture provides for up to four coprocessor units, numbered 0 to 3. Each level 2 of the ISA defines a number of these coprocessors. Coprocessor 0 is always used for system control and coprocessor 1 and 3 are used for the floating point unit. Coprocessor 2 is reserved for implementation-specific use. A coprocessor may have two different register sets: • Coprocessor general registers • Coprocessor control registers Each set contains up to 32 registers. Coprocessor computational instructions may use the registers in either set. 2.15.5.2 System Control Coprocessor 0 (CP0) The system controller for all MIPS processors is implemented as coprocessor 0 (CP0), the System Control Coprocessor. It provides the processor control, memory management, and exception handling functions. 2.15.5.3 Coprocessor Load and Store Instructions Explicit load and store instructions are not defined for CP0; for CP0 only, the move to and from coprocessor instructions must be used to write and read the CP0 registers. The loads and stores for the remaining coprocessors are summarized in “Coprocessor Loads and Stores” on page 60. MCU © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-63 PIC32MX Family Reference Manual 2.16 CPU INITIALIZATION Software is required to initialize the following parts of the device after a Reset event. 2.16.1 General Purpose Registers The CPU register file powers up in an unknown state with the exception of r0 which is always ‘0’. Initializing the rest of the register file is not required for proper operation in hardware. Depending on the software environment however, several registers may need to be initialized. Some of these are: • sp – stack pointer • gp – global pointer • fp – frame pointer 2.16.2 Coprocessor 0 State Miscellaneous CP0 states need to be initialized prior to leaving the boot code. There are various exceptions which are blocked by ERL = 1 or EXL = 1 and which are not cleared by Reset. These can be cleared to avoid taking spurious exceptions when leaving the boot code. Table 2-13: CP0 Initialization CP0 Register Action CAUSE WP (Watch Pending), SW0/1 (Software Interrupts) should be cleared. CONFIG COUNT(1) COMPARE(1) Typically, the K0, KU and K23 fields should be set to the desired Cache Coherency Algorithm (CCA) value prior to accessing the corresponding memory regions. Should be set to a known value if Timer Interrupts are used. Should be set to a known value if Timer Interrupts are used. The write to compare will also clear any pending Timer Interrupts (Thus, Count should be set before Compare to avoid any unexpected interrupts). STATUS Desired state of the device should be set. Other CP0 state Other registers should be written before they are read. Some registers are not explicitly writable, and are only updated as a by-product of instruction execution or a taken exception. Uninitialized bits should be masked off after reading these registers. Note 1: When the Count register is equal to the Compare register a timer interrupt is signaled. There is a mask bit in the interrupt controller to disable passing this interrupt to the CPU if desired. 2.16.3 Bus Matrix The BMX should be initialized before switching to User mode or before executing from DRM. The values written to the bus matrix are based on the memory layout of the application to be run. DS61113C-page 2-64 Preliminary © 2008 Microchip Technology Inc. MCU Section 2. MCU 2.17 EFFECTS OF A RESET 2.17.1 MCLR Reset The PIC32MX core is not fully initialized by hardware Reset. Only a minimal subset of the processor state is cleared. This is enough to bring the core up while running in unmapped and uncached code space. All other processor state can then be initialized by software. Power-up Reset brings the device into a known state. Soft Reset can be forced by asserting the MCLR pin. This distinction is made for compatibility with other MIPS processors. In practice, both Resets are handled identically with the exception of the setting of StatusSR. 2.17.1.1 Coprocessor 0 State 2 Much of the hardware initialization occurs in Coprocessor 0. Table 2-14: Bits Cleared or Set by Reset Bit Name Cleared or Set Value By Cleared or Set Value By StatusBEV StatusTS StatusSR Cleared 1 Cleared 0 Cleared 0 Reset or Soft Reset Reset or Soft Reset Reset Set StatusNMI Cleared 0 Reset or Soft Reset StatusERL Set 1 Reset or Soft Reset StatusRP Cleared 0 Reset or Soft Reset Configuration fields related to static inputs Set input value Reset or Soft Reset ConfigK0 Set 010 Reset or (uncached) Soft Reset ConfigKU Set 010 Reset or (uncached) Soft Reset ConfigK23 Set 010 Reset or (uncached) Soft Reset DebugDM Cleared 0 Reset or Soft Reset(1) DebugLSNM Cleared 0 Reset or Soft Reset DebugIBusEP Cleared 0 Reset or Soft Reset DebugIEXI Cleared 0 Reset or Soft Reset DebugSSt Cleared 0 Reset or Soft Reset Note 1: Unless EJTAGBOOT option is used to boot into DEBUG mode. 1 Soft Reset © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-65 PIC32MX Family Reference Manual 2.17.1.2 Bus State Machines All pending bus transactions are aborted and the state machines in the SRAM interface unit are reset when a Reset or Soft Reset exception is taken. 2.17.2 Fetch Address Upon Reset/SoftReset, unless the EJTAGBOOT option is used, the fetch is directed to VA 0xBFC00000 (PA 0x1FC00000). This address is in KSeg1, which is unmapped and uncached. 2.17.3 WDT Reset The status of the CPU registers after a WDT event depends on the operational mode of the CPU prior to the WDT event. If the device was not in Sleep a WDT event will force registers to a Reset value. DS61113C-page 2-66 Preliminary © 2008 Microchip Technology Inc. Section 2. MCU 2.18 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the CPU of the PIC32MX family include the following: Title Application Note # No related application notes at this time. N/A Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. 2 MCU © 2008 Microchip Technology Inc. Preliminary DS61113C-page 2-67 PIC32MX Family Reference Manual 2.19 REVISION HISTORY Revision A (October 2007) This is the initial released version of this document. Revision B (April 2008) Revised status to Preliminary; Revised Section 2.1 (Key Features); Revised Figure 2-1; Revised U-0 to r-x. Revision C (May 2008) Revise Figure 2-1; Added Section 2.2.3, Core Timer; Change Reserved bits from “Maintain as” to “Write”. DS61113C-page 2-68 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization HIGHLIGHTS This section of the manual contains the following topics: 3.1 Introduction................................................................................................................ 3-2 3.2 Control Registers....................................................................................................... 3-3 3.3 PIC32MX Memory Layout ....................................................................................... 3-19 3.4 PIC32MX Address Map ........................................................................................... 3-22 3.5 Bus Matrix................................................................................................................ 3-35 3.6 I/O Pin Control ......................................................................................................... 3-39 3.7 Operation in Power-Saving and DEBUG Modes ..................................................... 3-39 3.8 Code Examples ....................................................................................................... 3-40 3.9 Design Tips .............................................................................................................. 3-41 3.10 Related Application Notes ....................................................................................... 3-42 3 3.11 Revision History....................................................................................................... 3-43 Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-1 PIC32MX Family Reference Manual 3.1 INTRODUCTION The PIC32MX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program memory, data memory, SFRs, and Configuration registers reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing the PIC32MX to execute from data memory. Key features of PIC32MX memory organization include the following: • 32-bit native data width • Separate User and Kernel mode address spaces • Flexible program Flash memory partitioning • Flexible data RAM partitioning for data and program space • Separate boot Flash memory for protected code • Robust bus-exception handling to intercept runaway code • Simple memory mapping with Fixed Mapping Translation (FMT) unit • Cacheable and non-cacheable address regions DS61115D-page 3-2 Preliminary © 2008 Microchip Technology Inc. Memory Organization Section 3. Memory Organization 3.2 CONTROL REGISTERS This section lists the Special Function Registers (SFRs) registers used for setting the RAM and Flash memory partitions for data and code (for both User and Kernel mode). The following is a list of available SFRs: • BMXCON: Configuration Register BMXCONCLR, BMXCONSET, BMXCONINV: Atomic Bit Manipulation Registers for BMXCON • BMXxxxBA: Memory Partition Base Address Registers BMXxxxBACLR, BMXxxxBASET, BMXxxxBAINV: Atomic Bit Manipulation Registers for BMXxxxBA • BMXDRMSZ: Data RAM Size Register • BMXPFMSZ: Program Flash Size Register • BMXBOOTSZ: Boot Flash Size Register Table 3-1 provides a brief summary of all Memory Organization-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Table 3-1: Memory Organization SFR Summary Name Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 BMXCON 31:24 — — — — — BMX- — — CHEDMA 3 23:16 — — — BMXER- BMXER- BMXER- BMXER- BMXERRIS RIXI RICD RDMA RDS 15:8 — — — — — — — — 7:0 — BMXWS- — — — DRM BMXARB BMXCONCLR 31:0 Write clears selected bits in BMXCON, read yields undefined value BMXCONSET 31:0 Write sets selected bits in BMXCON, read yields undefined value BMXCONINV 31:0 Write inverts selected bits in BMXCON, read yields undefined value BMXDKPBA 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 BMXDKPBA<15:8> 7:0 BMXDKPBA<7:0> BMXDKPBACLR 31:0 Write clears selected bits in BMXDKPBA, read yields undefined value BMXDKPBASET 31:0 Write sets selected bits in BMXDKPBA, read yields undefined value BMXDKPBAINV 31:0 Write inverts selected bits in BMXDKPBA, read yields undefined value BMXDUDBA 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 BMXDUDBA<15:8> 7:0 BMXDUDBA<7:0> BMXDUDBACLR 31:0 Write clears selected bits in BMXDUDBA, read yields undefined value BMXDUDBASET 31:0 Write sets selected bits in BMXDUDBA, read yields undefined value BMXDUDBAINV 31:0 Write inverts selected bits in BMXDUDBA, read yields undefined value BMXDUPBA 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 BMXDUPBA<15:8> 7:0 BMXDUPBA<7:0> BMXDUPBACLR 31:0 Write clears selected bits in BMXDUPBA, read yields undefined value BMXDUPBASET 31:0 Write sets selected bits in BMXDUPBA, read yields undefined value BMXDUPBAINV 31:0 Write inverts selected bits in BMXDUPBA, read yields undefined value © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-3 PIC32MX Family Reference Manual Table 3-1: Memory Organization SFR Summary (Continued) Name Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 BMXDRMSZ 31:24 23:16 15:8 7:0 BMXPUPBA 31:24 — 23:16 — 15:8 7:0 BMXPUPBACLR 31:0 BMXPUPBASET 31:0 BMXPUPBAINV 31:0 BMXPFMSZ 31:24 23:16 15:8 7:0 BMXBOOTSZ 31:24 23:16 15:8 7:0 BMXDRMSZ<31:24> BMXDRMSZ<23:16> BMXDRMSZ<15:8> BMXDRMSZ<7:0> — — — — — — — — — BMXPUPBA<19:16> BMXPUPBA<15:8> BMXPUPBA<7:0> Write clears selected bits in BMXPUPBA, read yields undefined value Write sets selected bits in BMXPUPBA, read yields undefined value Write inverts selected bits in BMXPUPBA, read yields undefined value BMXPFMSZ<31:24> BMXPFMSZ<23:16> BMXPFMSZ<15:8> BMXPFMSZ<7:0> BMXBOOTSZ<31:24> BMXBOOTSZ<23:16> BMXBOOTSZ<15:8> BMXBOOTSZ<7:0> Bit 24/16/8/0 — DS61115D-page 3-4 Preliminary © 2008 Microchip Technology Inc. Memory Organization Section 3. Memory Organization Register 3-1: BMXCON: Bus Matrix Configuration Register r-x r-x r-x r-x r-x R/W-0 r-x — — — — — BMX- — CHEDMA bit 31 r-x — bit 24 r-x r-x — — bit 23 r-x R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — BMXERRIXI BMXER- BMXER- BMXER- BMXERRIS RICD RDMA RDS bit 16 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 15 bit 8 r-x R/W-1 r-x r-x r-x R/W-0 R/W-0 R/W-0 — BMXWS- — — — DRM BMXARB<2:0> bit 7 bit 0 3 Legend: R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit U = Unimplemented bit n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) bit 31-27 bit 26 bit 25 - 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 - 7 Reserved: Write ‘0’; ignore read BMXCHEDMA: BMX PFM Cacheability for DMA Accesses bit 1 = Enable program Flash memory (data) cacheability for DMA accesses (requires cache to have data caching enabled) 0 = Disable program Flash memory (data) cacheability for DMA accesses (hits are still read from the cache, but misses do not update the cache) Reserved: Write ‘0’; ignore read BMXERRIXI: Enable Bus Error from IXI bit 1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus 0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus BMXERRICD: Enable Bus Error from ICD Debug Unit bit 1 = Enable bus error exceptions for unmapped address accesses initiated from ICD 0 = Disable bus error exceptions for unmapped address accesses initiated from ICD BMXERRDMA: Bus Error from DMA bit 1 = Enable bus error exceptions for unmapped address accesses initiated from DMA 0 = Disable bus error exceptions for unmapped address accesses initiated from DMA BMXERRDS: Bus Error from CPU Data Access bit (disabled in DEBUG mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access BMXERRIS: Bus error from CPU Instruction Access bit (disabled in DEBUG mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access Reserved: Write ‘0’; ignore read © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-5 PIC32MX Family Reference Manual Register 3-1: bit 6 bit 5-3 bit 2-0 BMXCON: Bus Matrix Configuration Register (Continued) BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit 1 = Data RAM accesses from CPU have one wait state for address setup 0 = Data RAM accesses from CPU have zero wait states for address setup Reserved: Write ‘0’; ignore read BMXARB<2:0>: Bus Matrix Arbitration Mode bits 111...011 = Reserved (using these Configuration modes will produce undefined behavior) 010 = Arbitration Mode 2 001 = Arbitration Mode 1 000 = Arbitration Mode 0 DS61115D-page 3-6 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Register 3-2: BMXCONCLR: BMXCON Clear Register Write clears selected bits in BMXCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in BMXCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in BMXCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXCONCLR = 0x00000101 will clear bits 15 and 0 in BMXCON register. Register 3-3: BMXCONSET: BMXCON Set Register Write sets selected bits in BMXCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in BMXCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in BMXCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXCONSET = 0x00000101 will set bits 15 and 0 in BMXCON register. 3 Register 3-4: BMXCONINV: BMXCON Invert Register Write inverts selected bits in BMXCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in BMXCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in BMXCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXCONINV = 0x00000101 will invert bits 15 and 0 in BMXCON register. Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-7 PIC32MX Family Reference Manual Register 3-5: BMXDKPBA: Data RAM Kernel Program Base Address Register r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 31 r-x — bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 BMXDKPBA<15:8> bit 15 bit 8 R-0 bit 7 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDKPBA<7:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-11 bit 10-0 Reserved: Write ‘0’; ignore read BMXDKPBA<15:11>: DRM Kernel Program Base Address bits When non-zero, this value selects the relative base address for kernel program space in RAM BMXDKPBA<10:0>: Read-Only bits Value is always ‘0’, which forces 2 KB increments DS61115D-page 3-8 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Register 3-6: BMXDKPBACLR: BMXDKPBA Clear Register Write clears selected bits in BMXDKPBA, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in BMXDKPBA A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in BMXDKPBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXDKPBACLR = 0x00000101 will clear bits 15 and 0 in BMXDKPBA register. Register 3-7: BMXDKPBASET: BMXDKPBA Set Register Write sets selected bits in BMXDKPBA, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in BMXDKPBA A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in BMXDKPBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXDKPBASET = 0x00000101 will set bits 15 and 0 in BMXDKPBA register. 3 Register 3-8: BMXDKPBAINV: BMXDKPBA Invert Register Write inverts selected bits in BMXDKPBA, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in BMXDKPBA A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in BMXDKPBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXDKPBAINV = 0x00000101 will invert bits 15 and 0 in BMXDKPBA register. Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-9 PIC32MX Family Reference Manual Register 3-9: BMXDUDBA: Data RAM User Data Base Address Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 BMXDUDBA<15:8> bit 15 bit 8 R-0 bit 7 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUDBA<7:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-11 bit 10-0 Reserved: Write ‘0’; ignore read BMXDUDBA<15:11>: DRM User Data Base Address bits When non-zero, the value selects the relative base address for User mode data space in RAM Note: If non-zero, the value must be greater than BMXDKPBA. BMXDUDBA<10:0>: Read-Only bits Value is always ‘0’, which forces 2 KB increments DS61115D-page 3-10 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Register 3-10: BMXDUDBACLR: BMXDUDBA Clear Register Write clears selected bits in BMXDUDBA, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in BMXDUDBA A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in BMXDUDBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXDUDBACLR = 0x00000101 will clear bits 15 and 0 in BMXDUDBA register. Register 3-11: BMXDUDBASET: BMXDUDBA Set Register Write sets selected bits in BMXDUDBA, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in BMXDUDBA A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in BMXDUDBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXDUDBASET = 0x00000101 will set bits 15 and 0 in BMXDUDBA register. 3 Register 3-12: BMXDUDBAINV: BMXDUDBA Invert Register Write inverts selected bits in BMXDUDBA, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in BMXDUDBA A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in BMXDUDBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXDUDBAINV = 0x00000101 will invert bits 15 and 0 in BMXDUDBA register. Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-11 PIC32MX Family Reference Manual Register 3-13: BMXDUPBA: Data RAM User Program Base Address Register r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 31 r-x — bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 BMXDUPBA<15:8> bit 15 bit 8 R-0 bit 7 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUPBA<7:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-11 bit 10-0 Reserved: Write ‘0’; ignore read BMXDUPBA<15:11>: DRM User Program Base Address bits When non-zero, the value selects the relative base address for User mode program space in RAM Note: If non-zero, BMXDUPBA must be greater than BMXDUDBA. BMXDUPBA<10:0>: Read-Only bits Value is always ‘0’, which forces 2 KB increments DS61115D-page 3-12 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Register 3-14: BMXDUPBACLR: BMXDUPBA Clear Register Write clears selected bits in BMXDUPBA, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in BMXDUPBA A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in BMXDUPBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXDUPBACLR = 0x00000101 will clear bits 15 and 0 in BMXDUPBA register. Register 3-15: BMXDUPBASET: BMXDUPBA Set Register Write sets selected bits in BMXDUPBA, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in BMXDUPBA A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in BMXDUPBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXDUPBASET = 0x00000101 will set bits 15 and 0 in BMXDUPBA register. 3 Register 3-16: BMXDUPBAINV: BMXDUPBA Invert Register Write inverts selected bits in BMXDUPBA, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in BMXDUPBA A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in BMXDUPBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXDUPBAINV = 0x00000101 will invert bits 15 and 0 in BMXDUPBA register. Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-13 PIC32MX Family Reference Manual Register 3-17: BMXDRMSZ: Data RAM Size Register R R R R R R BMXDRMSZ<31:24> bit 31 R bit 23 R R R R R BMXDRMSZ<23:16> R bit 15 R R R R R BMXDRMSZ<15:8> R bit 7 R R R R R BMXDRMSZ<7:0> Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) bit 31-0 BMXDRMSZ: Data RAM Memory (DRM) Size bits Static value that indicates the size of the Data RAM in bytes: .......0x00002000 = device has 8 KB RAM 0x00004000 = device has 16 KB RAM 0x00008000 = device has 32 KB RAM R R bit 24 R R bit 16 R R bit 8 R R bit 0 r = Reserved bit DS61115D-page 3-14 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Register 3-18: r-x — bit 31 BMXPUPBA: Program Flash (PFM) User Program Base Address Register r-x r-x r-x r-x r-x r-x — — — — — — r-x — bit 24 r-x — bit 23 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — BMXPUPBA<19:16> bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 BMXPUPBA<15:8> bit 15 bit 8 R-0 bit 7 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXPUPBA<7:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit 3 bit 31-20 bit 19-11 bit 10-0 Unimplemented: Read as ‘0’ BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits BMXPUPBA<10:0>: Read-Only bits Value is always ‘0’, which forces 2 KB increments Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-15 PIC32MX Family Reference Manual Register 3-19: BMXPUPBACLR: BMXPUPBA Clear Register Write clears selected bits in BMXPUPBA, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in BMXPUPBA A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in BMXPUPBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXPUPBACLR = 0x00000101 will clear bits 15 and 0 in BMXPUPBA register. Register 3-20: BMXPUPBASET: BMXPUPBA Set Register Write sets selected bits in BMXPUPBA, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in BMXPUPBA A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in BMXPUPBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXPUPBASET = 0x00000101 will set bits 15 and 0 in BMXPUPBA register. Register 3-21: BMXPUPBAINV: BMXPUPBA Invert Register Write inverts selected bits in BMXPUPBA, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in BMXPUPBA A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in BMXPUPBA register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: BMXPUPBAINV = 0x00000101 will invert bits 15 and 0 in BMXPUPBA register. DS61115D-page 3-16 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Register 3-22: BMXPFMSZ: Program Flash (PFM) Size Register R R R R R R R R BMXPFMSZ<31:24> bit 31 bit 24 R bit 23 R R R R R R R BMXPFMSZ<23:16> bit 16 R bit 15 R R R R R R R BMXPFMSZ<15:8> bit 8 R bit 7 R R R R R R R BMXPFMSZ<7:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit 3 bit 31-0 BMXPFMSZ: Program Flash Memory (PFM) Size bits Static value that indicates the size of the PFM in bytes: 0x00008000 = device has 32 KB Flash .......0x00010000 = device has 64 KB Flash 0x00020000 = device has 128 KB Flash 0x00040000 = device has 256 KB Flash 0x00080000 = device has 512 KB Flash Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-17 PIC32MX Family Reference Manual Register 3-23: BMXBOOTSZ: Boot Flash (IFM) Size Register R R R R R R BMXBOOTSZ<31:24> bit 31 R bit 23 R R R R R BMXBOOTSZ<23:16> R bit 15 R R R R R BMXBOOTSZ<15:8> R bit 7 R R R R R BMXBOOTSZ<7:0> Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) bit 31-0 BMXBOOTSZ: Boot Flash Memory (BFM) Size bits Static value that indicates the size of the Boot PFM in bytes: 0x00003000 = device has 12 KB boot Flash R R bit 24 R R bit 16 R R bit 8 R R bit 0 r = Reserved bit DS61115D-page 3-18 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization 3.3 PIC32MX MEMORY LAYOUT The PIC32MX microcontrollers implement two address spaces: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions. Physical addresses are used by peripherals, such as DMA and Flash controllers, that access memory independently of the CPU. Figure 3-1: Virtual to Physical Fixed Memory Mapping Virtual Memory Map 0xFFFFFFFF Physical Memory Map 0xFFFFFFFF KSEG2/KSEG3 Memory Organization KSEG1 0xC0000000 0xBFC00000 Internal Boot Flash Internal Peripherals 0xBF800000 Internal Program Flash 0xBD000000 0xAFFFFFFF Reserved 0xA0000000 Internal RAM 0x9FC00000 Internal Boot Flash Internal RAM (User Partition) 0xBF000000 + BMXDUDBA 3 Internal Flash (User Partition) 0xBD000000 + BMXPUPBA Reserved 0x4FFFFFFF 0x40000000 KSEG0 USEG/KUSEG 0x9D000000 Internal Program Flash 0x8FFFFFFF Reserved 0x80000000 Internal RAM Internal Boot Flash 0x1FC00000 Internal RAM (User 0x7F000000 Partition) Internal Peripherals 0x1F800000 0x7D000000+ BMXPUPBA 0x0FFFFFFF 0x00000000 Program Flash (User Partition) Internal Program Flash 0x1D000000 Reserved 0x0FFFFFFF BMXDUDBA Reserved Internal RAM 0x00000000 Figure 13.1 : Virtual to Physical Fixed Memory Mapping © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-19 PIC32MX Family Reference Manual The entire 4 GB virtual address space is divided into two primary regions: user and kernel space. The lower 2 GB of space from the User mode segment is called useg/kuseg. A User mode application must reside and execute in the useg segment. The useg segment is also available to all Kernel mode applications, which is why it is also named kuseg – to indicate that it is available to both User and Kernel modes. When operating in User mode, the bus matrix must be configured to make part of the Flash and data memory available in the useg/kuseg segment. See Section 3.4 for more information. Figure 3-2: User/Kernel Address Segments 0xFFFFFFFF KERNEL SEGMENTS (KSEG 0,1,2,3) 0x80000000 0x7FFFFFFF USER / KERNEL SEGMENT (USEG / KUSEG) 0x00000000 The upper 2 GB of virtual address space forms the kernel only space. The kernel space is divided into four segments of 512 MB each: kseg 0, kseg 1, kseg 2 and kseg 3. Only Kernel mode applications can access kernel space memory. The kernel space includes all peripheral registers. Consequently, only Kernel mode applications can monitor and manipulate peripherals. Only kseg 0 and kseg 1 segments point to real memory resources. Segment kseg 2 is available to the EJTAG probe debugger, as explained in the MIPS documentation (refer to the EJTAG specification). The PIC32MX only uses kseg 0 and kseg 1 segments. The Boot Flash Memory (BFM), Program Flash Memory (PFM), Data RAM Memory (DRM), and peripheral SFRs are accessible from either kseg 0 or kseg 1. The Fixed Mapping Translation (FMT) unit translates the memory segments into corresponding physical address regions. Figure 3-1 shows the fixed mapping scheme implemented by the PIC32MX core between the virtual and physical address space. A virtual memory segment may also be cached, provided the cache module is available on the device. Please note that the kseg-1 memory segment is not cacheable, while kseg-0 and useg/kuseg are cacheable. The mapping of the memory segments depend on the CPU error level (set by the ERL bit in the CPU Status register). Error Level is set (ERL = 1) by the CPU on a Reset, Soft Reset, or NMI. In this mode, the processor runs in Kernel mode and useg/kuseg are treated as unmapped and uncached regions, and the mapping in Figure 3-1 does not apply. This mode is provided for compatibility with other MIPS processor cores that use a TLB-based MMU. The C start-up code clears the ERL bit to zero, so that when application software starts up, it sees the proper virtual to physical memory mapping as depicted in Figure 3-1. DS61115D-page 3-20 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Segments kseg 0 and kseg 1 are always translated to physical address 0x0. This translation arrangement allows the CPU to access identical physical addresses from two separate virtual addresses: one from kseg 0 and the other from kseg 1. As a result, the application can choose to execute the same piece of code as either cached or uncached. See Section 4. “Prefetch Cache Module” for more information. The on-chip peripherals are visible through kseg 1 segment only (uncached access). 3 Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-21 PIC32MX Family Reference Manual 3.4 PIC32MX ADDRESS MAP The Program Flash Memory is divided into kernel and user partitions. The kernel program Flash space starts at physical address 0x1D000000, whereas the user program Flash space starts at physical address 0xBD000000 + BMXPUDBA register value. Similarly, the internal RAM is also divided into kernel and user partitions. The kernel RAM space starts at physical address 0x00000000, whereas the user RAM space starts at physical address 0xBF000000 + BMXDUDBA register value. By default, the full Flash memory and RAM are mapped to Kernel mode application only. Please note that the BMXxxxBA register settings must match the memory model of the target software application. If the linked code does not match the register values, the program may not run and may generate bus error exceptions on start-up. Note: The Program Flash Memory is not writable through its address map. A write to the PFM address range causes a bus error exception. 3.4.1 Virtual to Physical Address Calculation (and Vice-Versa) To translate the kernel address (KSEG0 or KSEG1) to a physical address, perform a “Bitwise AND” operation of the virtual address with 0x1FFFFFFF: Physical Address = Virtual Address and 0x1FFFFFFF For physical address to KSEG0 virtual address translation, perform a “Bitewise OR” operation of the physical address with 0x80000000: KSEG0 Virtual Address = Physical Address | 0x80000000 For physical address to KSEG1 virtual address translation, perform a “Bitewise OR” operation of the physical address with 0xA0000000: KSEG1 Virtual Address = Physical Address | 0xA0000000 To translate from KSEG0 to KSEG1 virtual address, perform a “Bitewise OR” operation of the KSEG0 virtual address with 0x20000000: KSEG1 Virtual Address = KSEG0 Virtual Address | 0x20000000 DS61115D-page 3-22 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Table 3-2: PIC32MX Address Map Virtual Addresses Physical Addresses Size in Bytes Memory Type Begin Address End Address Begin Address End Address calculation User Address Space Kernel Address Space Boot Flash Program Flash(1) Program Flash(2) RAM (Data) RAM (Prog) Peripheral Program Flash RAM (Data) RAM (Prog) 0xBFC00000 0xBD000000 0x9D000000 0x80000000 0x80000000 + BMXDKPBA 0xBF800000 0x7D000000 + BMXPUPBA 0x7F000000 + BMXDUDBA 0x7F000000 + BMXDUPBA 0xBFC02FFF 0xBD000000 + BMXPUPBA - 1 0x9D000000 + BMXPUPBA - 1 0x80000000 + BMXDKPBA - 1 0x80000000 + BMXDUDBA -1 0xBF8FFFFF 0x7D000000 + PFM Size - 1 0x7F000000 + BMXDUPBA - 1 0x7F000000 + RAM Size(3) - 1 0x1FC00000 0x1D000000 0x1D000000 0x00000000 BMXDKPBA 0x1F800000 0xBD000000 + BMXPUPBA 0xBF000000 + BMXDUDBA 0xBF000000 + BMXDUPBA 0x1FC02FFF 0x1D00000 + BMXPUPBA - 1 0x1D000000 + BMXPUPBA - 1 BMXDKPBA - 1 BMXDUDBA -1 0x1F8FFFFF 0xBD000000 + PFM Size - 1 0xBF000000 + BMXDUPBA - 1 0xBF000000 + RAM Size(3) - 1 12 KB BMXPUPBA BMXPUPBA BMXDKPBA BMXDUDBA BMXDKPBA 1 MB PFM Size BMXPUPBA BMXDUPBA BMXDUDBA DRM Size BMXDUPBA 3 Note 1: Program Flash virtual addresses in the non-cacheable range (KSEG1). 2: Program Flash virtual addresses in the cacheable and prefetchable range (KSEG0). 3: The RAM size varies between PIC32MX device variants. 3.4.2 Program Flash Memory Partitioning The Program Flash Memory can be partitioned for User and Kernel mode programs as shown in Figure 3-1. At Reset, the User mode partition does not exist (BMXPUPBA is initialized to 0). The entire Program Flash Memory is mapped to Kernel mode program space starting at virtual address KSEG1: 0xBD000000 (or KSEG0: 0x9D000000). To set up a partition for the User mode program, initialize BMXPUPBA as follows: BMXPUPBA = BMXPFMSZ – USER_FLASH_PGM_SZ The USER_FLASH_PGM_SZ is the partition size of the User mode program. BMXPFMSZ is the bus matrix register that holds the total size of Program Flash Memory. Example: Assuming the PIC32MX device has 512 Kbytes of Flash memory, the BMXPFMSZ will contain 0x00080000. To create a user Flash program partition of 20 Kbytes (0x5000): BMXPUPBA = 0x80000 – 0x5000 = 0x7B000 The size of the user Flash will be 20K and the size left for the Kernel Flash will be 512k – 20k = 492K. The user Flash partition will extend from 0x7D07B000 to 0x7D07FFFF (virtual addresses). The Kernel mode partition always starts from KSEG1: 0xBD000000 or KSEG0: 0x9D000000. In the above example, the Kernel partition will extend from 0xBD000000 to 0xBD07AFFF (492 Kbytes in size). Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-23 PIC32MX Family Reference Manual Figure 3-3: Flash Partitioning Virtual Address KSEG0: 0x9D000000 +BMXPUPBA KSEG1: 0xBD000000 +BMXPUPBA KSEG0: 0x9D000000 KSEG1: 0xBD000000 Flash Partition for Kernel Program (KSEG 0/1) Physical Address 0x1D000000 Kernel Flash Size(1) User Flash Size(2) 0x7D000000+ BMXPUPBA Optional Flash Partition for User Program (USEG/KUSEG) 0xBD000000+ BMXPUPBA 0x00000000 Note 1: Kernel Flash Size = BMXPUPBA 2: User Flash Size = BMXPFMSZ-BMXPUPBA 3: If BMXPUPBA is ‘0’, then: K Flash Size = BMXPFMSZ (i.e., all the Flash) Usr Flash Size = 0 3.4.3 RAM Partitioning The RAM memory can be divided into 4 partitions. These are: 1. Kernel Data 2. Kernel Program 3. User Data 4. User Program In order to execute from data RAM, a kernel or user program partition must be defined. At Power-on Reset, the entire data RAM is assigned to the kernel data partition. This partition always starts from the base of the data RAM. See Figure 3-4 for details. Note 1: To properly partition the RAM, you have to program all of the following registers: BMXDKPBA, BMXDUDBA and BMXDUPBA. 2: The size of the available RAM is given by the BMXDRMSZ register. DS61115D-page 3-24 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Figure 3-4: RAM Partitioning Kernel Program Kernel Data RAM Size(2) RAM Size(1) Virtual Address Physical Address KSEG0: 0x80000000 +BMXDUDBA KSEG1: 0xA0000000 +BMXDUDBA KSEG0: 0x80000000 +BMXDKPBA KSEG1: 0xA0000000 +BMXDKPBA KSEG0: 0x80000000 KSEG1: 0xA0000000 Optional Kernel Program Partition KSEG 0/1 Kernel Data Partition KSEG 0/1 0x00000000 +BMXDUDBA 0x00000000 +BMXDKPBA 0x00000000 User Program User Data RAM Size(4) RAM Size(3) Optional User Program RAM Partition (USEG/KUSEG) 3 0x7F000000 0xBF000000 +BMXDUPBA +BMXDUPBA Optional User RAM Partition (USEG/KUSEG) 0x7F000000 +BMXDUDBA 0xBF000000 +BMXDUDBA 0x00000000 Note 1: Kernel Data RAM Size = BMXDKPBA 2: Kernel Program RAM Size = BMXDUDBA – BMXDKPBA 3: User Data RAM Size = BMXDUPBA – BMXDUDBA 4: User Program RAM Size = DRM Size – BMXDUPBA 5: If BMXDKPBA, BMXDUDBA or BMXDUPBA is ‘0’, then: Kernel Data RAM Size = BMXDRMSZ (i.e., all RAM) Kernel Program RAM Size = 0 User Data RAM Size = 0 User Program RAM Size = 0 Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-25 PIC32MX Family Reference Manual 3.4.3.1 Kernel Data RAM Partition The kernel data RAM partition is located at virtual address KSEG0:0x80000000, KSEG1:0xA0000000. It is always active and cannot be disabled. Please note that if any of the BMXDKPBA, BMXDUDBA or BMXDUPBA register is ‘0’, then the whole RAM is assigned to kernel data RAM (i.e., the size of the kernel data RAM partition is given by the BMXDRMSZ register value; see Figure 3-5). Otherwise, the size of the kernel data RAM partition is given by the value of the BMXDKPBA register. See Figure 3-6. The kernel data RAM partition exists on Reset and takes up all the available RAM, as the BMXDKPBA, BMXDUDBA and BMXDUPBA registers default to zero at any Reset. Figure 3-5: RAM Partitioning When BMXDKPBA, BMXDUDBA or BMXDUPBA = 0 Virtual Address Physical Address BMXDRMSZ Kernel Data RAM Partition KSEG 0/1 Kernel Data RAM Size KSEG0: 0x80000000 KSEG1: 0xA0000000 Note: Kernel Data RAM Size = BMXDRMSZ DS61115D-page 3-26 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Figure 3-6: Kernel Data RAM Partitioning Virtual Address Physical Address BMXDRMSZ Other Data RAM Partitions KSEG0: 0x80000000 +BMXDKPBA KSEG1: 0xA0000000 +BMXDKPBA Kernel Data RAM Partition KSEG 0/1 3 KSEG0: 0x80000000 KSEG1: 0xA0000000 Note 1: Kernel Data RAM Size = BMXDKPBA. 2: None of the registers BMXDKPBA, BMXDUDBA or BMXDUPBA = 0. Memory Organization Kernel Data RAM Size © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-27 PIC32MX Family Reference Manual 3.4.3.2 Kernel Program RAM Partition The kernel program RAM partition is required if code needs to be executed from data RAM in Kernel mode. This partition starts at KSEG0:0x80000000 + BMXDKPBA (KSEG1:0xA0000000 + BMXDKPBA), and its size is given by BMXDUDBA – BMXDKPBA. See Figure 3-7. The kernel program RAM partition does not exist on Reset, as the BMXDKPBA and BMXDUDBA registers default to zero at Reset. Figure 3-7: Kernel Program RAM Partitioning Virtual Address Physical Address BMXDRMSZ KSEG0: 0x80000000 +BMXDUDBA KSEG1: 0xA0000000 +BMXDUDBA User Data RAM Partitions Kernel Program RAM Partition KSEG 0/1 KSEG0: 0x80000000 +BMXDKPBA KSEG1: 0xA0000000 +BMXDKPBA Kernel Data RAM Partition KSEG 0/1 Kernel Program RAM Size Kernel Data RAM Size KSEG0: 0x80000000 KSEG1: 0xA0000000 Note 1: Kernel Program RAM Size = BMXDUDBA - BMXDKPBA 2: None of BMXDKPBA, BMXDUDBA, BMXDUPBA = 0 DS61115D-page 3-28 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization 3.4.3.3 User Data RAM Partition For User mode applications, a User mode data partition in RAM is required. This partition starts at address 0x7F000000 + BMXDUDBA, and its size is given by BMXDUPBA – BMXDUDBA. See Figure 3-8. The user data RAM partition does not exist on Reset, as the BMXDUDBA and BMXDUPBA registers default to zero at Reset. Figure 3-8: User Data RAM Partitioning Virtual Address Physical Address BMXDRMSZ User Program RAM Partitions 0x7F000000 +BMXDUPBA User Data RAM Partitions 3 0x7F000000 +BMXDUDBA Note 1: User Data RAM Size = BMXDUPBA – BMXDUDBA. 2: None of the registers BMXDKPBA, BMXDUDBA, or BMXDUPBA = 0. Memory Organization User Data RAM Size © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-29 PIC32MX Family Reference Manual 3.4.3.4 User Program RAM Partition The user program partition in data RAM is required if code needs to be executed from data RAM in User mode. This partition starts at address 0x7F000000 + BMXDUPBA, and its size is given by BMXDRMSZ – BMXDUPBA. See Figure 3-9. The User Program RAM partition does not exist on Reset, as the BMXDUPBA register defaults to zero at Reset. Figure 3-9: User Program RAM Partitioning Virtual Address Physical Address BMXDRMSZ User Program RAM Size User Program RAM Partition 0x7F000000 +BMXDUPBA User Data RAM Partition 0x7F000000 +BMXDUDBA Note 1: User Program RAM Size = BMXDRMSZ – BMXDUPBA. 2: None of the registers BMXDKPBA, BMXDUDBA, or BMXDUPBA = 0. 3.4.3.5 RAM Partitioning Examples This section provides the following practical examples of RAM partitioning. 1. RAM Partitioned as Kernel Data 2. RAM Partitioned as Kernel Data and Kernel Program 3. RAM Partitioned as Kernel Data and User Data 4. RAM Partitioned as Kernel Data, Kernel Program and User Data 5. RAM Partitioned as Kernel Data, Kernel Program, User Data and User Program Example 1. RAM Partitioned as Kernel Data The entire RAM is partitioned as kernel data RAM after a Reset. No other programming is required. Setting the BMXDKPBA, BMXDUDBA, or BMXDUPBA register to ‘0’ will partition the entire RAM space to a kernel data partition. See Figure 3-5. DS61115D-page 3-30 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Example 2. RAM Partitioned as Kernel Data and Kernel Program For this example, assume that the available RAM on the PIC32MX device is 32 KB, of which 8 KB kernel data RAM and 24 KB of kernel program RAM are needed. In this example, the user data RAM and user program RAM will have their sizes set to ‘0’. Please note that a kernel data RAM partition is always required. See Figure 3-10 for details. The values of the registers are as follows: BMXDRMSZ = 0x00008000 (read-only value) BMXDKPBA = 0x00002000 (i.e., 8 KB kernel data) BMXDUDBA = 0x00008000 (i.e., 0x6000 kernel program) BMXDUPBA = 0x00008000 (i.e., user data size = 0, and user program size = 0) Figure 3-10: RAM Partitioning for 8 KB Kernel Data and 16 KB Kernel Program Virtual Address Physical Address Kernel Program RAM Size KSEG0: 0x80008000 = 0x80000000 +BMXDUDBA BMXDRMSZ = 0x00008000 3 Kernel Program RAM Partition KSEG 0/1 24 KB Kernel Data RAM Size KSEG0: 0x80002000 = 0x80000000 +BMXDKPBA KSEG0: 0x80000000 Kernel Data RAM Partition KSEG 0/1 8 KB BMXDKPBA = 0x2000 BMXDUDBA = 0x8000 BMXDUPBA = 0x8000 Note: Only KSEG0 addresses are shown. For KSEG1 addresses, start at 0xA000000. Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-31 PIC32MX Family Reference Manual Example 3. RAM Partitioned as Kernel Data and User Data For this example, assume that the available RAM on the PIC32MX device is 32 KB, of which 16 KB of kernel data RAM and 16 KB of user data RAM are needed. In this example, the kernel program RAM and user program RAM will have their sizes set to ‘0’. See Figure 3-11 for details. The values of the registers are as follows: BMXDRMSZ = 0x00008000 (read-only value) BMXDKPBA = 0x00004000 (i.e., 16 KB kernel data) BMXDUDBA = 0x00004000 (i.e., 0 kernel program) BMXDUPBA = 0x00008000 (i.e., user data size = 16 KB, and user program size = 0) Figure 3-11: RAM Partitioning for 16 KB Kernel Data and 16 KB User Data Virtual Address Physical Address Kernel Data RAM Size KSEG0: 0x80004000 = 0x80000000 +BMXDKPBA KSEG0: 0x80000000 Kernel Data RAM 16 KB User Data RAM Size 0x7F008000 = 0x7F000000 +BMXDUPBA 0x7F004000 = 0x7F000000 +BMXDUDBA 0x00000000 User Data RAM 16 KB BMXDKPBA = 0x4000 BMXDUDBA = 0x4000 BMXDUPBA = 0x8000 Note: Only KSEG0 addresses are shown. For KSEG1 addresses, start at 0xA0000000. DS61115D-page 3-32 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization Example 4. RAM Partitioned as Kernel Data, Kernel Program and User Data For this example, assume that the available RAM on the PIC32MX device is 32 KB, and 4 KB of kernel data RAM, 6 KB of kernel program and 22 KB of user data RAM are needed. In this example, the user program RAM will have its size set to ‘0’. See Figure 3-12 for details. The values of the registers are as follows: BMXDRMSZ = 0x00008000 (read-only value) BMXDKPBA = 0x00001000 (i.e., 4 KB kernel data) BMXDUDBA = 0x00002800 (i.e., 6 KB kernel program) BMXDUPBA = 0x00008000 (i.e., user data size = 22 KB, and user program size = 0) Figure 3-12: RAM Partitioning for 4 KB K-Data, 6 KB K-Program and 22 KB U-Data Virtual Address Physical Address KSEG0: 0x80002800 = 0x80000000 +BMXDUDBA Kernel Program RAM Size Kernel Program RAM 6 KB KSEG0: 0x80001000 3 = 0x80000000 +BMXDKPBA Kernel Data RAM 4 KB Kernel Data RAM Size KSEG0: 0x80000000 User Data RAM Size 0x7F008000 = 0x7F000000 +BMXDUPBA 0x7F002800 = 0x7F000000 +BMXDUDBA 0x00000000 User Data RAM 22 KB BMXDKPBA = 0x1000 BMXDUDBA = 0x2800 BMXDUPBA = 0x8000 Note: Only KSEG0 addresses are shown. For KSEG1 addresses, start at 0xA0000000. Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-33 PIC32MX Family Reference Manual Example 5. RAM Partitioned as Kernel Data, Kernel Program, User Data and User Program For this example, assume that the available RAM on the PIC32MX device is 32 KB, and 6 KB of kernel data RAM, 5 KB of kernel program RAM, 12 KB of user data RAM and 9 KB of user program RAM are needed. See Figure 3-13 for details. The values of the registers are as follows: BMXDRMSZ = 0x00008000 (read-only value) BMXDKPBA = 0x00001800 (i.e., 6 KB kernel data) BMXDUDBA = 0x00002C00 (i.e., 5 KB kernel program) BMXDUPBA = 0x00005C00 (i.e., user data size = 12 KB, and user program size = 9 KB) Figure 3-13: RAM Partitioning for 6 KB K-Data, 5 KB K-Program, 12 KB U-Data and 9 KB U-Program Virtual Address Physical Address Kernel Program RAM Size KSEG0: 0x80002C00 = 0x80000000 +BMXDUDBA KSEG0: 0x80001800 = 0x80000000 +BMXDKPBA KSEG0: 0x80000000 Kernel Program RAM 5 KB Kernel Data RAM 6 KB Kernel Data RAM Size User Program User Data RAM Size RAM Size 0x7F008000 = 0x7F000000 +BMXDRMSZ 0x7F005C00 = 0x7F000000 +BMXDUPBA 0x7F002C00 = 0x7F000000 +BMXDUDBA 0x00000000 User Program RAM 9 KB User Data RAM 12 KB BMXDKPBA = 0x1800 BMXDUDBA = 0x2c00 BMXDUPBA = 0x5c00 Note: Only KSEG0 addresses are shown. For KSEG1 addresses, start at 0xA0000000. DS61115D-page 3-34 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization 3.5 BUS MATRIX The processor supports two modes of operation, Kernel mode and User mode. The Bus Matrix controls the allocation of memory for each of these modes. It also controls the type of access, program or data, for a given region of address space. The Bus Matrix connects master devices, generically called initiators, to slave devices, generically called targets. The PIC32MX product family can have up to five initiators and three targets (e.g., Flash, RAM, ...) on the main bus structure. Of the five possible initiators, the CPU Instruction Bus (CPU IS), CPU Data Bus (CPU DS), In-Circuit Debug (ICD) and DMA Controller (DMA) are the default set of initiators and are always present. The PIC32MX also includes an Initiator Expansion Interface (IXI) to support additional initiators for future expansion. The Bus Matrix decodes a general range of addresses that map to a target. The target (memory or peripherals) may provide additional addresses depending on its functionality. Table 3-3 shows which initiators can access which targets. Table 3-3: Initiator Access Map Initiator CPU IS CPU DS DMA IXI ICD Flash Y Y Y Y Y Target RAM Peripheral Bus Y N Y Y 3 Y Y Y N Y Y Figure 3-14: Bus Matrix Initiators and Targets Initiators CPU IS CPU DS DMA Initiator Expansion Debug Module PFM DRM Peripherals Program Flash Memory Data RAM Memory Peripheral Bus (PBM) Targets Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-35 PIC32MX Family Reference Manual 3.5.1 Initiator Arbitration Modes Since there can be more than one initiator attempting to access the same target, an arbitration scheme must be used to control access to the target. The arbitration modes assign priority levels to all the initiators. The initiator with the higher priority level will always win target access over a lower priority initiator. 3.5.1.1 Arbitration Mode 0 The fixed priority scheme in Arbitrition Mode 0 is shown in Figure 3-15. The CPU data and instruction access are given higher priority than DMA access. This mode can starve the DMA, so chose this mode when DMA is not being used. As shown in Figure 3-15, each initiator is assigned a fixed priority level. Programming the register field BMXARB (BMXCON<2:0>) to ‘0’ selects Mode 0 operation. Figure 3-15: Priority Assignment in Arbitration Mode 0 ICD/Debug CPU Data Access CPU Instruction Access DMA Initiator Expansion Higher Priority DS61115D-page 3-36 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization 3.5.1.2 Arbitration Mode 1 Arbitrition Mode 1 is a fixed priority scheme like Mode 0; however, the CPU IS is always the lowest priority. Figure 3-16 shows the priority scheme in Mode 1. Mode 1 arbitration is the default mode. Programming the register field BMXARB (BMXCON<2:0>) to ‘1’ selects Mode 1 operation. Figure 3-16: Priority Assignment in Arbitration Mode 1 Higher Priority ICD/Debug CPU Data Access DMA Initiator Expansion CPU 3 Instruction Access Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-37 PIC32MX Family Reference Manual 3.5.1.3 Arbitration Mode 2 Mode 2 arbitration supports rotating priority assignments to all initiators. Instead of a fixed priority assignment, each initiator is assigned the highest priority in a rotating fashion. In this mode, the rotating priority is applied with the following exceptions: 1. CPU data is always selected over CPU instruction. 2. ICD is always the highest priority. 3. When the CPU is processing an exception (EXL = 1) or an error (ERL = 1), the arbiter temporarily reverts to Mode 0. Figure 3-17: Priority Assignments in Arbitration Mode 2 Pr Seq #1 Pr Seq #2 Pr Seq #3 Pr Seq #4 Higher Priority ICD/Debug ICD/Debug ICD/Debug ICD/Debug CPU Data Access CPU Instruction Access DMA Initiator Expansion CPU Instruction Access DMA Initiator Expansion CPU Data Access DMA Initiator Expansion CPU Data Access CPU Instruction Access Initiator Expansion CPU Data Access CPU Instruction Access DMA Rotating Priority Sequence Note that priority sequence #2 is not selected in the rotating priority scheme if there is a pending CPU data access. In this case, once the data access is complete, sequence #2 is selected. Programming the register field BMXARB (BMXCON<2:0>) to ‘2’ selects Mode 2 operation. 3.5.2 Bus Error Exceptions The Bus Matrix generates a bus error exception on: - Any attempt to access unimplemented memory - Any attempt to access an illegal target - Any attempt to write to program Flash memory Bus Error Exceptions may be temporarily disabled by clearing the BMXERRxxx bits in the BMXCON register. This is not recommended. The Bus Matrix disables bus error exceptions for accesses from CPU IS and CPU DS while in DEBUG mode. 3.5.3 Break Exact Breakpoint Support The PIC32MX supports break exact breakpoints by inserting one Wait state to data RAM access. This method allows the CPU to stop execution just before the breakpoint address instruction. This is useful in case of breakpointed store instructions. When the Wait state is not used, the break will still occur at the store instruction, however, the DRM location is updated with the store value. If the Wait state is enabled the DRM is not updated with the store value. DS61115D-page 3-38 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization 3.6 I/O PIN CONTROL There are no pins associated with this module. 3.7 OPERATION IN POWER-SAVING AND DEBUG MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 3.7.1 Memory Operation on Power-up or Brown-out Reset: • The contents of data RAM are undefined. • The BMXxxxBA registers are reset to ‘0’. • CPU is switched to Kernel mode. 3.7.2 Memory Operation on Reset: • The data RAM contents are retained. If the device is code-protected, the RAM contents are cleared. • The BMX base address registers (BMXxxxBA) are set to ‘0’. • CPU is switched to Kernel mode. 3 3.7.3 Memory Operation on Wake-up from SLEEP or IDLE Mode: • The RAM contents are retained. • The BMX base address register (BMXxxxBA) contents are not changed. • CPU mode is unchanged. Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-39 PIC32MX Family Reference Manual 3.8 CODE EXAMPLES Example 3-1: Create a User Mode Partition of 12K in Program Flash BMXPUPBA = BMXPFMSZ - (12*1024); // User Mode Flash 12K, // Kernel Mode Flash 500K (512K-12K) Example 3-2: Create a Kernel Mode Data RAM Partition of 16K; Rest of RAM for Kernel Program BMXDKPBA = 16*1024; BMXDUDBA = BMXDRMSZ; BMXDUPBA = BMXDRMSZ; Example 3-3 can be used to create the following partitions in RAM: Kernel mode data = 12K Kernel mode program = 6K User mode data = 8K User mode program = 6K Example 3-3: Create RAM Partitions BMXDKPBA = 12*1024; BMXDUDBA = BMXDKPBA + (6*1024); BMXDUPBA = BMXDUDBA + (8*1024); // Kernel Data Partition of 12K. // Start offset of Kernel Program Partition // Kernel Program Partition of 6K // Start offset of User Data Partition // User Data Partition of 8K // Start offset of User Program Partition. // This partition will go up to the size of // RAM (32K). So the partition size will be // 6K (32K - 8K - 6K - 12K) DS61115D-page 3-40 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization 3.9 DESIGN TIPS Question 1: At Reset, which mode is the CPU running in? Answer: The CPU starts in Kernel mode. The entire RAM is mapped to kernel data segments in KSEG0 and KSEG1. Flash memory is mapped to kernel program segments in KSEG0 and KSEG1. Also ERL = 1, which should be reset to zero (normally in the C start-up code). Question 2 Do I need to initialize the BMX registers? Answer: Generally, no. You can leave the BMX registers at their default values, which allows maximum RAM and Flash memories for Kernel mode applications. If you want to run code from RAM or set up User mode partitions, you will need to configure the BMX registers. Question 3 What is the CPU Reset vector address? Answer: The CPU Reset address is 0xBFC00000. Question 4 What is a Bus-Error Exception? Answer: The bus-error exceptions are generated when the CPU tries to access unimplemented addresses. Also, when the CPU tries to execute a program from RAM without defining a RAM program partition, a bus-error exception is generated. 3 Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-41 PIC32MX Family Reference Manual 3.10 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Memory Organization of the PIC32MX family include the following: Title Application Note # No related application notes at this time. N/A Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. DS61115D-page 3-42 Preliminary © 2008 Microchip Technology Inc. Section 3. Memory Organization 3.11 REVISION HISTORY Revision A (August 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x. Revision D (June 2008) Change Reserved bits from “Maintain as” to “Write”. 3 Memory Organization © 2008 Microchip Technology Inc. Preliminary DS61115D-page 3-43 PIC32MX Family Reference Manual NOTES: DS61115D-page 3-44 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Module HIGHLIGHTS This section of the manual contains the following topics: 4.1 Introduction .................................................................................................................... 4-2 4.2 Cache Overview............................................................................................................. 4-3 4.3 Control Registers ........................................................................................................... 4-7 4.4 Cache Operation.......................................................................................................... 4-27 4.5 Cache Configurations .................................................................................................. 4-27 4.6 Coherency Support ...................................................................................................... 4-30 4.7 Effects of Reset............................................................................................................ 4-31 4.8 Design Tips .................................................................................................................. 4-31 4.9 Operation In Power-Saving Modes .............................................................................. 4-32 4.10 Related Application Notes............................................................................................ 4-33 4.11 Revision History ........................................................................................................... 4-34 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-1 PIC32MX Family Reference Manual 4.1 INTRODUCTION Note: Prefetch cache is available in select devices only. Refer to the appropriate data sheet for the availability of a prefetch cache module on specific devices. This section describes the features and operation of the prefetch cache module in the PIC32MX device family. Prefetch cache features increase system performance for most applications. PFM cache and prefetch cache modules increase performance for applications that execute out of the cacheable Program Flash Memory (PFM) region by implementing the following features: • Instruction Caching The 16-line cache supplies an instruction every clock, for loops up to 256 bytes long. • Data Caching Prefetch cache also allows the allocation of up to 4 cache lines for data storage to provide improved access for Flash-stored constant data. • Predictive Prefetching The prefetch cache module provides instructions once per clock for linear code even without caching by prefetching ahead of the current program counter, hiding the access time of the Flash memory. 4.1.1 Additional Prefetch Cache Module Features The prefetch cache module also include the following features: • 16 Fully Associative Lockable Cache Lines • 16-Byte Cache Lines • Up to 4 Cache Lines Allocated to Data • 2 Cache Lines with Address Mask to Hold Repeated Instructions • Pseudo Least-Recently-Used (LRU) Replacement Policy • All Cache Lines are Software Writable • 16-Byte Parallel Memory Fetch • Predictive Instruction Prefetch Cache DS61119D-page 4-2 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache 4.2 CACHE OVERVIEW The prefetch cache module is a performance enhancing module included in some processors of the PIC32MX. When running at high clock rates, Wait states must be inserted into PFM Read transactions to meet the access time of the PFM. Wait states can be hidden to the core by prefetching and storing instructions in a temporary holding area that the CPU can access quickly. Although the data path to the CPU is 32-bits wide, the data path to the Program Memory Flash is 128-bits wide. This wide data path provides the same bandwidth to the CPU as a 32-bit path running at four times the frequency. There are two main functions that the prefetch cache module performs: caching instructions when they are accessed, and prefetching instructions from the PFM before they are needed. The cache holds a subset of the cacheable memory in temporary holding spaces known as cache lines. Each cache line has a tag describing what it is currently holding, and the address where it is mapped. Normally, the cache lines just hold a copy of what is currently in memory to make data available to the CPU without Wait states. CPU requested data may or may not be in the cache. A cache-miss occurs if the CPU requests cacheable data that is not in the cache. In this case, a read is performed to the PFM at the correct address, the data is supplied to the cache and to the CPU. A cache-hit occurs if the cache contains the data that the CPU requests. In the case of a cache-hit, data is supplied to the CPU without Wait states. The second main function of the prefetch cache module is to prefetch cache instructions. The module calculates the address of the next cache line and performs a read of the PFM to get the next 16-byte cache line. This line is placed into a 16-byte-wide prefetch cache buffer in anticipation of executing straight-line code. Figure 4-1 shows a block diagram of the prefetch cache module. Logically, the prefetch cache module fits between the Bus Matrix (BMX) module and the PFM module. Figure 4-1: Prefetch Cache Block Diagram BMX/CPU FSM CTRL Bus Ctrl Cache Ctrl Prefetch Ctrl Hit LRU Miss LRU Tag Logic Hit Logic Prefetch Tag CTRL Cache Line Cache Line Address Encode Prefetch 4 RDATA RDATA BMX/CPU Prefetch Cache CTRL Program Flash Memory © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-3 PIC32MX Family Reference Manual Figure 4-2: To illustrate the basic operation of the prefetch cache, Figure 4-2 shows an example of the CPU requesting data from physical address 0x1FC01234. The prefetch cache simultaneously compares this address to all of the tags marked “valid”. Since the shaded entry below has this address, and is marked as valid, this is a cache hit. The proper data word from the data array is then directed to the CPU in a single clock period. Cache Look-up Example(2) ⎫ ⎪ ⎪ ⎬ LLLVAOLCIKD⎪⎪ LTYPE ⎭ ⎫ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎬ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎭ Cache Tags(1) Cache Data 0x1fc01234 HIT 0x00001000 1 0 1 0x00001300 1 0 1 0x00002200 1 0 1 0x0000a030 1 0 1 0x80001230 1 0 1 0x00002210 1 0 1 0x00002230 1 0 1 0x00002220 1 0 1 0x00001200 1 0 1 0x00001230 0 0 1 0x00001230 1 0 1 0x00001320 1 0 1 0x00001330 1 0 0 0x00001310 1 0 0 0x00001340 1 0 0 0x00001350 1 0 0 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 3 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 2 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 1 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 WORD 0 Note 1: Bits 0-3 of the address in the Cache Tags register are always implied ‘0’. 2: Mask Fields are not shown and are assumed to be ‘0’. 4.2.1 Cache Organization The cache consists of two arrays: tag and data. A data array could consist of program instructions or program data. The cache is physically tagged and address matches are based on the physical address not the virtual address. Each line in the tag array contains the following information: • Mask – address mask value • Tag – tag address to match against • Valid bit • Lock bit • Type – an instruction and/or data type-indicator bit DS61119D-page 4-4 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Figure 4-3: 31 Each line in the data array contains 16-bytes of program instruction, or program data, depending on the value of the type-indicator bit. Figure 4-3 shows the organization of a line. Note that the LMASK (CHEMSK<15:5>) and LTYPE (CHETAG<1>) fields are not programmable for every line. The LTAG (CHETAG<23:4>) field only implements the number of bits needed to fully map to the size of the PFM, e.g., if the Flash size is 512 KB, the LTAG (CHETAG<23:4>) field only implements bits 18 through 4. Mask Line RSVD 16 15 LMASK<15:5> 54 0 RSVD Figure 4-4: Tag Line 31 24 23 RSVD LTAG<23:4> 43210 LTAGBOOT LVALID LLOCK LTYPE RSVD Figure 4-5: 31 Data Line 31 31 31 WORD 3 WORD 2 WORD 1 WORD 0 0 0 0 0 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-5 PIC32MX Family Reference Manual Cache arrays are shown in Table 4-1. Software can modify values in both the Tag Line and the Data Line of the cache. Configuration register field CHEIDX (CHEACC<3:0>) selects a line for access. That line can then be modified via the CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3 registers. Table 4-1: Cache Arrays Line # Tag Array 0 000h(1) TAG V L T(3) 1 000h(1) TAG V L T(3) 2 000h(1) TAG V L T(3) 3 000h(1) TAG V L T(3) 4 000h(1) TAG V L T(3) 5 000h(1) TAG V L T(3) 6 000h(1) TAG V L T(3) 7 000h(1) TAG V L T(3) 8 000h(1) TAG V L T(3) 9 000h(1) TAG V L T(3) A MASK TAG V L T(3) B MASK TAG V L T(3) C 000h(1) TAG V L T D 000h(1) TAG V L T E 000h(1) TAG V L T F 000h(1) TAG V L T Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Word 3 Note 1: Read-only field. 2: Read zeros when device is code-protected. Read/write otherwise. 3: Type is fixed as instruction. Data Array(2) Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 2 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 1 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 Word 0 It is recommended that cache lines be modified while executing from non-cacheable addresses, since the cache controller does not protect against modifying the cache while executing from cacheable address. Not all fields are writable. The LMASK (CHEMSK<15:5>) field is only writable for lines 10 and 11, and the LTYPE (CHETAG<1>) field is fixed to the “Instruction” setting for lines 0 through 11. Note that lines allocated for Lock and Data affect the selection of the line to replace on a miss. However, they do not affect the usage order or pseudo LRU value. DS61119D-page 4-6 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache 4.3 CONTROL REGISTERS Note: Some devices in the PIC32MX family do not contain a prefetch cache module. For these devices, all prefetch cache register locations are reserved and should not be accessed. The prefetch cache module contains the following Special Functions Registers (SFRs): • CHECON: Prefetch Cache Control Register Manages configuration of the Prefetch Cache and controls Wait states. • CHECONCLR, CHECONSET, CHECONINV: Atomic Bit Manipulation Write-only Registers for CHECON • CHEACC: Prefetch Cache Access Register Points to one of the 16 cache lines to access using the CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3 registers. • CHEACCCLR, CHEACCSET, CHEACCINV: Atomic Bit Manipulation Write-only Registers for CHEACC • CHETAG: Prefetch Cache TAG Register Contains the address and type of information stored in a cache line. • CHETAGCLR, CHETAGSET, CHETAGINV: Atomic Bit Manipulation Write-only Registers for CHETAG • CHEMSK: Prefetch Cache TAG Mask Register Provides a mechanism to ignore TAG bits in CHETAG. • CHEMSKCLR, CHEMSKSET, CHEMSKINV: Atomic Bit Manipulation Write-only Registers for CHEMSK • CHEW0: Cache Word 0 Register Provides Access to the Prefetch Cache Data Array • CHEW1: Cache Word 1 Register Provides Access to the Prefetch Cache Data Array • CHEW2: Cache Word 2 Register Provides Access to the Prefetch Cache Data Array • CHEW3: Cache Word 3 Register Provides Access to the Prefetch Cache Data Array • CHELRU: Cache LRU Register • CHEHIT: Cache Hit Statistics Register • CHEMIS: Cache Miss Statistics Register 4 • PFABT: Prefetch Cache Abort Statistics Register A statistical register that contains the number of aborted Prefetch Cache operations. The following table provides a brief summary of prefetch cache-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-7 PIC32MX Family Reference Manual Table 4-2: Name Prefetch Cache SFRs Summary Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 CHECON 31:24 — — — — — — — — 23:16 — — — — — — — CHECOH 15:8 — — — — — — DCSZ<1:0> 7:0 — — PREFEN<1:0> — PFMWS<2:0> CHECONCLR 31:0 Clears selected bits in CHECON, read yields undefined value CHECONSET 31:0 Sets selected bits in CHECON, read yields undefined value CHECONINV 31:0 Inverts selected bits in CHECON, read yields undefined value CHEACC 31:24 CHEWEN — — — — — — — 23:16 — — — — — — — — 15:8 — — — — — — — — 7:0 — — — — CHEIDX<3:0> CHEACCCLR 31:0 Clears selected bits in CHEACC, read yields undefined value CHEACCSET 31:0 Sets selected bits in CHEACC, read yields undefined value CHEACCINV 31:0 Inverts selected bits CHEACC, read yields undefined value CHETAG 31:24 LTAGBOOT — — — — — — — 23:16 LTAG<23:16> 15:8 LTAG<15:8> 7:0 LTAG<7:4> LVALID LLOCK LTYPE — CHETAGCLR 31:0 Clears selected bits in CHETAG, read yields undefined value CHETAGSET 31:0 Sets selected bits in CHETAG, read yields undefined value CHETAGINV 31:0 Inverts selected bits CHETAG, read yields undefined value CHEMSK 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 LMASK<15:8> 7:0 LMASK<7:5> — — — — — CHEMSKCLR 31:0 Clears selected bits in CHEMSK, read yields undefined value CHEMSKSET 31:0 Sets selected bits in CHEMSK, read yields undefined value CHEMSKINV 31:0 Inverts selected bits CHEMSK, read yields undefined value CHEW0 31:24 CHEW0<31:24> 23:16 CHEW0<23:16> 15:8 CHEW0<15:8> 7:0 CHEW0<7:0> CHEW1 31:24 CHEW1<31:24> 23:16 CHEW1<23:16> 15:8 CHEW1<15:8> 7:0 CHEW1<7:0> CHEW2 31:24 CHEW2<31:24> 23:16 CHEW2<23:16> 15:8 CHEW2<15:8> 7:0 CHEW2<7:0> CHEW3 31:24 CHEW3<31:24> 23:16 CHEW3<23:16> 15:8 CHEW3<15:8> 7:0 CHEW3<7:0> DS61119D-page 4-8 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Table 4-2: Name CHELRU CHEHIT CHEMIS PFABT Prefetch Cache SFRs Summary Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31:24 — — — — — — 23:16 15:8 7:0 CHELRU<23:16> CHELRU<15:8> CHELRU<7:0>> 31:24 23:16 15:8 CHEHIT<31:24> CHEHIT<23:16> CHEHIT<15:8> 7:0 31:24 23:16 15:8 7:0 CHENIT<7:0> CHEMIS<31:24> CHEMIS<23:16> CHEMIS<15:8> CHEMIS<7:0> 31:24 23:16 15:8 PFABT<31:24> PFABT<23:16> PFABT<15:8> 7:0 PFABT<7:0> Bit 25/17/9/1 Bit 24/16/8/0 — CHELRU<24> 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-9 PIC32MX Family Reference Manual Register 4-1: CHECON: Cache Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x R/W-0 — — — — — — CHECOH bit 16 r-x — bit 15 r-x r-0 r-0 r-x r-x R/W-0 R/W-0 — — — — — DCSZ<1:0> bit 8 r-x — bit 7 r-x R/W-0 R/W-0 r-x R/W-1 R/W-1 R/W-1 — PREFEN<1:0> — PFMWS<2:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-17 bit 16 bit 15-14 bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3 Reserved: Write ‘0’; ignore read CHECOH: Cache Coherency setting on a PFM Program Cycle bit 1 = Invalidate all data and instruction lines 0 = Invalidate all data lnes and instruction lines that are not locked Reserved: Write ‘0’; ignore read Reserved: Must be written with zeros Reserved: Write ‘0’; ignore read DCSZ<1:0>: Data Cache Size in Lines bits 11 = Enable data caching with a size of 4 Lines 10 = Enable data caching with a size of 2 Lines 01 = Enable data caching with a size of 1 Line 00 = Disable data caching Changing this field causes all lines to be re-initialized to the “invalid” state. Reserved: Write ‘0’; ignore read PREFEN<1:0>: Predictive Prefetch Cache Enable bits 11 = Enable predictive prefetch cache for both cacheable and non-cacheable regions 10 = Enable predictive prefetch cache for non-cacheable regions only 01 = Enable predictive prefetch cache for cacheable regions only 00 = Disable predictive prefetch cache Reserved: Write ‘0’; ignore read DS61119D-page 4-10 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Register 4-1: bit 2-0 CHECON: Cache Control Register (Continued) PFMWS<2:0>: PFM Access Time Defined in terms of SYSLK Wait states bits 111 = Seven Wait states 110 = Six Wait states 101 = Five Wait state 100 = Four Wait states 011 = Three Wait states 010 = Two Wait states 001 = One Wait state 000 = Zero Wait states Prefetch Cache 4 © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-11 PIC32MX Family Reference Manual Register 4-2: CHECONCLR: CHECON Clear Register Write clears selected bits in CHECON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in CHECON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in CHECON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHECONCLR = 0x00010020 will clear bits 16 and 5 in CHECON register. Register 4-3: CHECONSET: CHECON Set Register Write sets selected bits in CHECON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in CHECON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in CHECON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHECONSET = 0x00010020 will set bits 16 and 5 in CHECON register. Register 4-4: CHECONINV: CHECON Invert Register Write inverts selected bits in CHECON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in CHECON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in CHECON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHECONINV = 0x00010020 will invert bits 16 and 5 in CHECON register. DS61119D-page 4-12 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Register 4-5: CHEACC: Cache Access R/W-0 r-x r-x r-x r-x r-x r-x r-x CHEWEN — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 r-x — bit 15 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 8 r-x — bit 7 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — CHEIDX<3:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 CHEWEN: Cache Access Enable bits for registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3 1 = The cache line selected by CHEIDX is writeable 0 = The cache line selected by CHEIDX is not writeable bit 30-4 Reserved: Write ‘0’; ignore read bit 3-0 CHEIDX<3:0>: Cache Line Index bits The value selects the cache line for reading or writing. 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-13 PIC32MX Family Reference Manual Register 4-6: CHEACCCLR: CHEACC Clear Register Write clears selected bits in CHEACC, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in CHEACC A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in CHEACC register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHEACCCLR = 0x80000000 will clear bit 31 in CHEACC register. Register 4-7: CHEACCSET: CHEACC Set Register Write sets selected bits in CHEACC, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in CHEACC A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in CHEACC register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHEACCSET = 0x80000000 will clear bit 31 in CHEACC register. Register 4-8: CHEACCINV: CHEACC Invert Register Write inverts selected bits in CHEACC, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in CHEACC A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in CHEACC register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHEACCINV = 0x80000000 will invert bit 31 in CHEACC register. DS61119D-page 4-14 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Register 4-9: CHETAG(1): Cache TAG Register R/W-0 r-x r-x r-x r-x r-x r-x r-x LTAGBOOT — — — — — — — bit 31 bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x LTAG<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x LTAG<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x LTAG<7:4> R/W-x R/W-0 LVALID R/W-0 LLOCK R/W-1 LTYPE r-0 — bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 LTAGBOOT: Line TAG Address Boot 1 = The line is in the 0x1D000000 (physical) area of memory 0 = The line is in the 0x1FC00000 (physical) area of memory bit 30-24 Reserved: Write ‘0’; ignore read bit 23-4 LTAG<23:4>: Line TAG Address bits LTAG bits are compared against physical address <23:4> to determine a hit. Because its address range and position of Flash in kernel space and user space, the LTAG Flash address is identical for virtual addresses, (system) physical addresses, and Flash physical addresses. 4 bit 3 LVALID: Line Valid bit 1 = The line is valid and is compared to the physical address for hit detection 0 = The line is not valid and is not compared to the physical address for hit detection bit 2 LLOCK: Line Lock bit 1 = The line is locked and will not be replaced 0 = The line is not locked and can be replaced bit 1 LTYPE: Line Type bit 1 = The line caches instruction words 0 = The line caches data words bit 0 Reserved: Write ‘0’; ignore read Note 1: The TAG and Status of the Line pointed to by CHEIDX (CHEACC<3:0>). Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-15 PIC32MX Family Reference Manual Register 4-10: CHETAGCLR: CHETAG Clear Register Write clears selected bits in CHETAG, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in CHETAG A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in CHETAG register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHETAGCLR = 0x0000000C will clear bits 2 and 3 in CHETAG register. Register 4-11: CHETAGSET: CHETAG Set Register Write sets selected bits in CHETAG, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in CHETAG A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in CHETAG register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHETAGSET = 0x00000004 will set bit 2 in CHETAG register. Register 4-12: CHETAGINV: CHETAG Invert Register Write inverts selected bits in CHETAG, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in CHETAG A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in CHETAG register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHETAGINV = 0x00000010 will invert bit 4 in CHETAG register. DS61119D-page 4-16 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Register 4-13: CHEMSK(1): Cache TAG Mask Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 LMASK<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x r-x LMASK<7:5> — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 Reserved: Write ‘0’; ignore read bit 15-5 LMASK<15:5>: Line Mask bits 1 = Enables mask logic to force a match on the corresponding bit position in LTAG (CHETAG<23:4>) and the physical address. 0 = Only writeable for values of CHEIDX (CHEACC<3:0>) equal to OxOA and OxOB. Disables mask logic. bit 4-0 Reserved: Write ‘0’; ignore read Note 1: The TAG Mask of the Line pointed to by CHEIDX (CHEACC<3:07>). 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-17 PIC32MX Family Reference Manual Register 4-14: CHEMSKCLR: CHEMSK Clear Register Write clears selected bits in CHEMSK, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in CHEMSK A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in CHEMSK register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHEMSKCLR = 0x00008020 will clear bits 15 and 5 in CHEMSK register. Register 4-15: CHEMSKSET: CHEMSK Set Register Write sets selected bits in CHEMSK, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in CHEMSK A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in CHEMSK register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHEMSKSET = 0x00008020 will set bits 15 and 5 in CHEMSK register. Register 4-16: CHEMSKINV: CHEMSK Invert Register Write inverts selected bits in CHEMSK, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in CHEMSK A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in CHEMSK register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CHEMSKINV = 0x00008020 will invert bits 15 and 5 in CHEMSK register. DS61119D-page 4-18 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Register 4-17: CHEW0: Cache Word 0 R/W-x R/W-x R/W-x bit 31 R/W-x R/W-x CHEW0<31:24> R/W-x R/W-x R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x CHEW0<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x CHEW0<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x CHEW0<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 CHEW0<31:0>: Word 0 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-19 PIC32MX Family Reference Manual Register 4-18: CHEW1: Cache Word 1 R/W-x R/W-x R/W-x bit 31 R/W-x R/W-x CHEW1<31:24> R/W-x R/W-x R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x CHEW1<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x CHEW1<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x CHEW1<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 CHEW1<31:0>: Word 1 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. DS61119D-page 4-20 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Register 4-19: CHEW2 Cache Word 2 R/W-x R/W-x R/W-x bit 31 R/W-x R/W-x CHEW2<31:24> R/W-x R/W-x R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x CHEW2<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x CHEW2<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x CHEW2<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 CHEW2<31:0>: Word 2 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-21 PIC32MX Family Reference Manual Register 4-20: CHEW3(1): Cache Word 3 R/W-x R/W-x R/W-x bit 31 R/W-x R/W-x CHEW3<31:24> R/W-x R/W-x R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x CHEW3<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x CHEW3<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x CHEW3<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 Note 1: CHEW3<31:0>: Word 3 of the cache line selected by CHEACC.CHEIDX Readable only if the device is not code-protected. This register is a window into the cache data array and is readable only if the device is not code-protected. DS61119D-page 4-22 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Register 4-21: CHELRU: Cache LRU Register r-x r-x r-x r-x r-x r-x r-x R-0 — — — — — — — CHELRU<24> bit 31 bit 24 R-0 bit 23 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHELRU<23-16> bit 16 R-0 bit 15 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHELRU<15-8> bit 8 R-0 bit 7 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHELRU<7-0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-25 bit 24-0 Reserved: Write ‘0’; ignore read CHELRU<24:0>: Cache Least Recently Used State Encoding bits CHELRU indicates the Pseudo-LRU state of the cache. 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-23 PIC32MX Family Reference Manual Register 4-22: R/W-x bit 31 CHEHIT: Cache Hit Statistics Register R/W-x R/W-x R/W-x R/W-x CHEHIT<31:24> R/W-x R/W-x R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x CHEHIT<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x CHEHIT<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x CHEHIT<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 CHEHIT<31:0>: Cache Hit Count bits Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from a cacheable region. Non-cacheable accesses do not modify this value. DS61119D-page 4-24 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache Register 4-23: R/W-x bit 31 CHEMIS: Cache Miss Statistics Register R/W-x R/W-x R/W-x R/W-x CHEMIS<31:24> R/W-x R/W-x R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x CHEMIS<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x CHEMIS<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x CHEMIS<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 CHEMIS<31:0>: Cache Miss Count bits Incremented each time the processor issues an instruction fetch from a cacheable region that misses the prefetch cache. Non-cacheable accesses do not modify this value. 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-25 PIC32MX Family Reference Manual Register 4-24: R/W-x bit 31 PFABT: Prefetch Cache Abort Statistics Register R/W-x R/W-x R/W-x R/W-x PFABT<31:24> R/W-x R/W-x R/W-x bit 24 R/W-x bit 23 R/W-x R/W-x R/W-x R/W-x PFABT<23:16> R/W-x R/W-x R/W-x bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x PFABT<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x PFABT<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 PFABT<31:0>: Prefab Abort Count bits Incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction fetch, load or store. DS61119D-page 4-26 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache 4.4 CACHE OPERATION The cache and prefetch cache module implements a fully associative 16-line cache. Each line consists of 128 bits (16 bytes). The cache and prefetch cache module only request 16-byte aligned instruction data from the PFM. If the CPU requested address is not aligned to a 16-byte boundary, the module will align the address by dropping address bits<3:0>. When configured only as a cache, the module loads multiple instructions into a line on a miss. It uses the pseudo LRU algorithm to select which line receives the new set of instructions. The cache controller uses the Wait states state values from PFMWS (CHECON<2:0>) to determine how long it must wait for a Flash access when it detects a miss. On a hit, the cache returns data in zero Wait states. If the code is 100% linear, the Cache-Only mode will provide instructions back to the CPU with Wait states only on the first instruction of a cache line. For 32-bit linear code, Wait states are seen every four instructions. For 16-bit linear code, Wait states occur only once for every eight instructions executed. 4.5 CACHE CONFIGURATIONS The CHECON register controls the configurations available for instruction and data caching of PFM. Two parameters control the allocation of cache lines to specific features. The DCSZ (CHECON<9:8>) field controls the number of lines allocated to program data caching. Table 4-3 shows the cache line relationship for values of DCSZ (CHECON<9:8>). The data caching capability is for read-only data, e.g., constants, parameters, table data, etc., that are not modified. Table 4-3: Program Data Cache DCSZ<1:0> Lines Allocated to Program Data 00 None 01 Cache Line Number 15 10 Cache Lines Number 14 and 15 11 Cache Lines Number 12 through 15 The PREFEN (CHECON<5:4>) field controls predictive prefetching, which allows the cache controller to speculatively fetch the next 16-byte aligned set of instructions. 4.5.1 Line Locking Each line in the cache can be locked to hold its contents. A line is locked if both LVALID (CHETAG<3>) = 1 and LLOCK (CHETAG<2>) = 1. If LVALID = 0 and LLOCK = 1, the cache 4 controller issues a preload request (see Section 4.5.3 “Preload Behavior”). Locking cache lines may reduce the performance of general program flow. However, if one or two function calls consume a significant percent of overall processing, locking their addresses can provide improved performance. Though any number of lines can be locked, the cache works more efficiently when locking either 1 or 4 lines. If locking 4 lines, choose those lines in which the line numbers, when divide by 4, have the same quotient. This locks an entire LRU group which benefits the LRU algorithm. For example, lines 8, 9, A, and B each have a quotient of 2 when divided by 4. Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-27 PIC32MX Family Reference Manual 4.5.2 Address Mask Cache lines 10 and 11 allow masking of the CPU address, and the tag address, to force a match on corresponding bits. The LMASK (CHEMSK<15:5>) field is set up to complement the interrupt vector spacing field in the CPU. This feature allows boot code to lock the first four instructions of a vector in the cache. If all vectors contain identical instructions in their first four locations, then setting the LMASK (CHEMSK<15:5>) to match the vector spacing, and the LTAG (CHETAG<23:4>) to match the vector base address, causes all the vector addresses to hit the cache. The cache responds with zero Wait states and immediately initiates a fetch of the next set of four instructions for the requesting vector if prefetch cache is enabled. Using LMASK (CHEMSK<15:5>) is restricted to aligned address ranges. Its size allows for a maximum range of 32 KB and a minimum spacing of 32 B. Using the two lines in conjunction provides the ability to have different ranges and different spacing. Setting up the address mask such that more than one line will match an address causes undefined results. Therefore, it is highly recommended that masking is set up before entering cacheable code. 4.5.3 Preload Behavior Application code can direct the cache controller to preform a preload of a cache line and lock it with instructions or data from the Flash. The preload function uses the CHEACC.CHEIDX register field to select the cache line into which the load is directed. Setting CHEACC.CHEWEN to ‘1’ enables writes to the CHETAG register. Writing LVALID (CHETAG<3>) = 0 and LLOCK (CHETAG<2>) = 1 causes a preload request to the cache controller. The controller acknowledges the request in the cycle after the write and, if possible, stops any outstanding Flash access, and stalls any CPU load from the cache or Flash. When the controller has finished or stalled the previous transaction, it initiates a Flash read to fetch the instructions, or data, requested using the address in LTAG (CHETAG<23:4>). After the programmed number of Wait states, as defined by PFMWS (CHECON<2:0>), the controller updates the data array with the values read from Flash. On the update, it sets LVALID (CHETAG<3>) = 1. The LRU state of the line is not affected. Once the controller finishes updating the cache, it allows CPU requests to complete. If this request misses the cache, the controller initiates a Flash read, which incurs the full Flash access time. 4.5.4 Bypass Behavior Processor accesses in which cache coherency attributes indicate uncacheable addresses bypass the cache. In bypass, the module accesses the PFM for every instruction, incurring the Flash access time as defined by PFMWS (CHECON<2:0>). DS61119D-page 4-28 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache 4.5.5 Predictive Prefetch Cache Behavior When configured for predictive prefetch cache on cacheable addresses, the module predicts the next line address and returns it into the pseudo LRU line of the cache. If enabled, the prefetch cache function starts predicting based on the first CPU instruction fetch. When the first line is placed in the cache, the module simply increments the address to the next 16-byte aligned address and starts a Flash access. When running linear code (i.e. no jumps), the Flash returns the next set of instructions into the prefetch cache buffer on or before all instructions can be executed from the previous line. If, at any time during a predicted Flash access, a new CPU address does not match the predicted one, the Flash access will be changed to the correct address. This behavior does not cause the CPU access to take any longer than it does without prediction. If an access that misses the cache hits the prefetch cache buffer, the instructions are placed in the pseudo LRU line, along with its address tag. The pseudo LRU value is marked as the most recently used line, and other lines are updated accordingly. If an access misses both the cache and the prefetch cache buffer, the access passes to the Flash, and those returning instructions are placed in the pseudo LRU line. When configured for predictive prefetch cache on non-cacheable addresses, the controller only uses the prefetch cache buffer. The LRU cache line is not updated for hits or fills, so the cache remains intact. For linear code, enabling predictive prefetch cache for non-cacheable addresses allows the CPU to fetch instructions in zero Wait states. It is not useful to use non-cacheable predictive prefetching when accesses to the Flash are set for zero Wait states. The controller holds prefetched instructions on the output of the Flash for up to 3 clock cycles (while the CPU is fetching from the buffer). This consumes more power, without any benefit, for zero-Wait-state Flash accesses. Predictive data prefetching is not supported. However, a data access in the middle of a predictive instruction fetch causes the cache controller to stop the Flash access for the instruction fetch, and to start the data load from Flash. The predictive prefetch cache does not resume, but instead, waits for another instruction fetch. At which time, it either fills the buffer because of a miss, or starts a prefetch cache because of a hit. 4.5.6 Cache Replacement Policy The cache controller uses a pseudo-LRU replacement policy for cache line fills that are caused by a read miss. The policy allows any line in the last quarter of least recently used lines to be replaced. Enabling locking and data caching affect the line to be replaced, but not the actual value of the pseudo-LRU. 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-29 PIC32MX Family Reference Manual 4.6 COHERENCY SUPPORT It is not possible to execute out of cache while programming the Flash memory. The Flash controller stalls the cache during the programming sequence. Therefore, user code that initiates a programming sequence should not be located in a cacheable address region. During a programming operation, the prefetch cache is flushed by invalidating either all, or some of the cache lines. If CHECOH (CHECON<16>) is set, every cache line is invalidated and unlocked during a Flash program memory write operation. The cache tags and masks are also cleared for all lines. If CHECOH is not set, only lines that are not locked are forced invalid. Lines that are locked are retained. DS61119D-page 4-30 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache 4.7 EFFECTS OF RESET 4.7.1 On Reset • All cache lines are invalidated • All cache lines revert to instruction • All cache lines are unlocked • The LRU order is sequential, with line 0 being the least recently used • All mask bits are cleared • All registers revert to their Reset state 4.7.2 After Reset • The module operates as per the values in the CHECON register • The cache obeys the core’s cache coherency attributes 4.8 DESIGN TIPS Even while running at clock frequencies allowing for zero-Wait-state operation, the cache function proves useful as a power-saving technique. Accesses to the Flash memory consume more power than accesses to the cache. 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-31 PIC32MX Family Reference Manual 4.9 OPERATION IN POWER-SAVING MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 4.9.1 SLEEP Mode When the device enters SLEEP mode, the prefetch cache is disabled and placed into a low-power state where no clocking occurs in the prefetch cache module. 4.9.2 IDLE Mode When the device enters IDLE mode, the cache and prefetch cache clock source remains functional and the CPU stops executing code. Any outstanding prefetch cache completes before the module stops its clock via automatic clock gating. 4.9.3 DEBUG Mode The behavior of the prefetch cache is unaltered by DEBUG mode. Care must be taken to make sure the cache remains coherent during DEBUG mode execution when using software breakpoints. If a debugger places a software break instruction in the cache, the line should be locked before returning control to the application. When a locked software breakpoint is removed, the line should be unlocked and invalidated, causing the original instructions to be reloaded from the PFM upon execution. DS61119D-page 4-32 Preliminary © 2008 Microchip Technology Inc. Section 4. Prefetch Cache 4.10 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the prefetch cache module are: Title No related application notes at this time. Application Note # N/A Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. 4 Prefetch Cache © 2008 Microchip Technology Inc. Preliminary DS61119D-page 4-33 PIC32MX Family Reference Manual 4.11 REVISION HISTORY Revision A (October 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revise U-0 to r-x. Revision D (June 2008) Change Reserved bits from “Maintain as” to “Write”. DS61119D-page 4-34 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming HIGHLIGHTS This section of the manual contains the following topics: 5.1 Introduction................................................................................................................ 5-2 5.2 Control Registers....................................................................................................... 5-3 5.3 RTSP Operation ...................................................................................................... 5-17 5.4 Lock-Out Feature..................................................................................................... 5-18 5.5 Word Programming Sequence ................................................................................ 5-20 5.6 Row Programming Sequence.................................................................................. 5-21 5.7 Page Erase Sequence............................................................................................. 5-22 5.8 Program Flash Memory Erase Sequence ............................................................... 5-23 5.9 Operation in Power-Saving and DEBUG Modes ..................................................... 5-24 5.10 Effects of Various Resets......................................................................................... 5-24 5.11 Interrupts.................................................................................................................. 5-25 5.12 Related Application Notes ....................................................................................... 5-27 5.13 Revision History....................................................................................................... 5-28 Flash Programming © 2008 Microchip Technology Inc. Preliminary 5 DS61121D-page 5-1 PIC32MX Family Reference Manual 5.1 INTRODUCTION This section describes techniques for programming the Flash memory. PIC32MX devices contain internal Flash memory for executing user code. There are three methods by which the user can program this memory: • Run-Time Self Programming (RTSP) – performed by the user’s software • In-Circuit Serial Programming™ (ICSP™) – performed using a serial data connection to the device, allows much faster programming than RTSP • EJTAG Programming – performed by an EJTAG-capable programmer, using the EJTAG port of the device RTSP techniques are described in this chapter. The ICSP and EJTAG methods are described in the PIC32MX Programming Specification document, which can be downloaded from the Microchip web site at www.microchip.com. DS61121D-page 5-2 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming 5.2 CONTROL REGISTERS Flash program and erase operations are controlled using the following Nonvolatile Memory (NVM) control registers: • NVMCON: Nonvolatile Memory Control Register NVMCONCLR, NVMCONSET, NVMCONINV: Atomic Bit Manipulation, Write-only Registers for NVMCON • NVMKEY: Nonvolatile Memory Key Register • NVMADDR: Nonvolatile Memory Address Register NVMADDRCLR, NVMADDRSET, NVMADDRINV: Atomic Bit Manipulation, Write-only Registers for NVMADDR • NVMDATA: Nonvolatile Memory Data Register • NVMSRCADDR: Nonvolatile Memory SRAM Source Address Register • IFSx: Interrupt Flag Status Registers IFSxCLR, IFSxSET, IFSxINV: Atomic Bit Manipulation, Write-only Registers for IFSx • IECx: Interrupt Enable Control Registers IECxCLR, IECxSET, IECxINV: Atomic Bit Manipulation, Write-only Registers for IECx • IPCx: Interrupt Priority Control Registers • IPCxCLR, IPCxSET, IPCxINV: Atomic Bit Manipulation, Write-only Registers for IPCx The following table provides a brief summary of all the Flash-programming-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Table 5-1: Flash Controller SFR Summary Name Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 NVMCON 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 NVMWR NVMWREN NVMERR LVDERR LVDSTAT — — — 7:0 — — — — NVMOP<3:0> NVMCONCLR 31:0 Write clears selected bits in NVMCON, read yields undefined value NVMCONSET NVMCONINV NVMKEY 31:0 31:0 31:24 Write sets selected bits in NVMCON, read yields undefined value Write inverts selected bits in NVMCON, read yields undefined value NVMKEY<31:24> 23:16 15:8 NVMKEY<23:16> NVMKEY<15:8> NVMADDR 7:0 31:24 23:16 NVMKEY<7:0> NVMADDR<31:24> NVMADDR<23:16> 15:8 NVMADDR<15:8> 7:0 NVMADDR<7:0> NVMADDRCLR 31:0 Write clears selected bits in NVMADDR, read yields undefined value 5 NVMADDRSET 31:0 Write sets selected bits in NVMADDR, read yields undefined value NVMADDRINV 31:0 Write inverts selected bits in NVMADDR, read yields undefined value Flash Programming © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-3 PIC32MX Family Reference Manual Table 5-1: Name Flash Controller SFR Summary (Continued) Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 NVMDATA 31:24 23:16 15:8 7:0 NVMSRCADDR 31:24 23:16 15:8 7:0 NVMDATA<31:24> NVMDATA<23:16> NVMDATA<15:8> NVMDATA<7:0> NVMSRCADDR<31:24> NVMSRCADDR<23:16> NVMSRCADDR<15:8> NVMSRCADDR<7:0> Bit 25/17/9/1 Bit 24/16/8/0 Table 5-2: IFS1 IFS1CLR IFS1SET IFS1INV IEC1 IEC1CLR IEC1SET IEC1INV IPC11 IPC11CLR IPC11SET IPC11INV Flash Controller Interrupt SFR Summary 31:24 — — — — — — USBIF FCEIF 23:16 — — — — DMA3IF DMA2IF DMA1IF DMA0IF 15:8 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF 7:0 SPI2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 31:0 Write clears the selected bits in IFS1, read yields undefined value 31:0 Write sets the selected bits in IFS1, read yields undefined value 31:0 Write inverts the selected bits in IFS1, read yields undefined value 31:24 — — — — — — USBIE FCEIE 23:16 — — — — DMA3IE DMA2IE DMA1IE DMA0IE 15:8 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE 7:0 SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 31:0 Write clears the selected bits in IEC1, read yields undefined value 31:0 Write sets the selected bits in IEC1, read yields undefined value 31:0 Write inverts the selected bits in IEC1, read yields undefined value 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 — — — — — — — — 7:0 — — — FCEIP<2:0> FCEIS<1:0> 31:0 Write clears the selected bits in IPC11, read yields undefined value 31:0 Write sets the selected bits in IPC11, read yields undefined value 31:0 Write inverts the selected bits in IPC11, read yields undefined value DS61121D-page 5-4 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming Register 5-1: NVMCON: Programming Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R-0 R-0 R-x r-x r-x r-x NVMWR NVMWREN NVMERR LVDERR LVDSTAT — — — bit 15 bit 8 r-x — bit 7 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 Reserved: Write ‘0’; ignore read bit 15 NVMWR: Write Control bit This bit is writable when NVMWREN = 1 and the unlock sequence is followed 1 = Initiate a Flash operation. Hardware clears this bit when the operation completes. 0 = Flash operation complete or inactive bit 14 NVMWREN: Write Enable bit 1 = Enable writes to NVMWR bit and enables LVD circuit 0 = Disable writes to NVMWR bit and disables LVD circuit Note: This is the only bit in this register reset by a device Reset. bit 13 NVMERR: Write Error bit This bit is read-only and is automatically set by hardware 1 = Program or erase sequence did not complete successfully 0 = Program or erase sequence completed normally Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR). bit 12 LVDERR: Low Voltage Detect Error Bit (LVD circuit must be enabled) This bit is read-only and is automatically set by hardware 1 = Low voltage detected (possible data corruption, if NMVERR is set) 0 = Voltage level is acceptable for programming Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR). bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled) This bit is read-only and is automatically set, and cleared, by hardware 1 = Low voltage event active 5 0 = Low voltage event NOT active Note: Cleared by setting NVMOP==0000b, and initiating a Flash operation (i.e., NVMWR). bit 10-4 Reserved: Write ‘0’; ignore read Flash Programming © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-5 PIC32MX Family Reference Manual Register 5-1: bit 3-0 NVMCON: Programming Control Register (Continued) NVMOP<3:0>: NVM Operation bits These bits are writeable when NVMWREN = 1 and the unlock sequence is followed 0111 = Reserved 0110 = No operation 0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected 0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected 0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected 0010 = No operation 0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected 0000 = No operation DS61121D-page 5-6 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming Register 5-2: NVMCONCLR: Programming Control Clear Register Write clears selected bits in NVMCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in NVMCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in NVMCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: NVMCONCLR = 0x00008001 will clear bits 15 and 0 in NVMCON register. Register 5-3: NVMCONSET: Programming Control Set Register Write sets selected bits in NVMCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in NVMCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in NVMCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: NVMCONSET = 0x00008001 will set bits 15 and 0 in NVMCON register. Register 5-4: NVMCONINV: Programming Control Invert Register Write inverts selected bits in NVMCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in NVMCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in NVMCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: NVMCONINV = 0x00008001 will invert bits 15 and 0 in NVMCON register. 5 Flash Programming © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-7 PIC32MX Family Reference Manual Register 5-5: NVMKEY: Programming Unlock Register W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<31:24> bit 31 bit 24 W-0 bit 23 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<23:16> bit 16 W-0 bit 15 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<15:8> bit 8 W-0 bit 7 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 NVMKEY<31:0>: Unlock Register bits These bits are write-only, and read as ‘0’ on any read Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM. DS61121D-page 5-8 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming Register 5-6: R/W-0 bit 31 NVMADDR: Flash Address Register R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<31:24> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<23:16> R/W-0 R/W-0 R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x NVMADDR<7:0> bit 7 r-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-3 bit 2-0 NVMADDR<31:0>: Flash Address bits Bulk/Chip/PFM Erase: Address is ignored Page Erase: Address identifies the page to erase Row Program: Address identifies the row to program Word Program: Address identifies the word to program Reserved: Write ‘0’; ignore read Flash Programming © 2008 Microchip Technology Inc. Preliminary 5 DS61121D-page 5-9 PIC32MX Family Reference Manual Register 5-7: NVMADDRCLR: Flash Address Clear Register Write clears selected bits in NVMADDR, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in NVMADDR A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in NVMADDR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: NVMADDRCLR = 0x00008001 will clear bits 15 and 0 in NVMADDR register. Register 5-8: NVMADDRSET: Flash Address Set Register Write sets selected bits in NVMADDR, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in NVMADDR A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in NVMADDR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: NVMADDRSET = 0x00008001 will set bits 15 and 0 in NVMADDR register. Register 5-9: NVMADDRINV: Flash Address Invert Register Write inverts selected bits in NVMADDR, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in NVMADDR A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in NVMADDR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: NVMADDRINV = 0x00008001 will invert bits 15 and 0 in NVMADDR register. DS61121D-page 5-10 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming Register 5-10: R/W-0 bit 31 NVMDATA: Flash Program Data Register R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<31:24> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<23:16> R/W-0 R/W-0 R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 NVMDATA<31:0>: Flash Programming Data bits Note: These bits are only reset by a Power-on Reset (POR). Flash Programming 5 © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-11 PIC32MX Family Reference Manual Register 5-11: R/W-0 bit 31 NVMSRCADDR: Source Data Address Register R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<31:24> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<23:16> R/W-0 R/W-0 R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x NVMSRCADDR<7:0> bit 7 r-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-3 bit 2-0 NVMSRCADDR<31:0>: Source Data Address bits The system physical address of the data to be programmed into the Flash when NVMCON.NVMOP is set to perform row programming Reserved: Write ‘0’; ignore read DS61121D-page 5-12 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming Register 5-12: IFS1: Interrupt Flag Status Register 1(1) r-x r-x r-x r-x r-x — — — — — bit 31 r-x R/W-0 R/W-0 — USBIF FCEIF bit 24 r-x — bit 23 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IF DMA2IF DMA1IF DMA0IF bit 16 R/W-0 RTCCIF bit 15 R/W-0 FSCMIF R/W-0 I2C2MIF R/W-0 I2C2SIF R/W-0 I2C2BIF R/W-0 U2TXIF R/W-0 U2RXIF R/W-0 U2EIF bit 8 R/W-0 SPI2RXIF bit 7 R/W-0 SPI2TXIF R/W-0 SPI2EIF R/W-0 CMP2IF R/W-0 CMP1IF R/W-0 PMPIF R/W-0 AD1IF R/W-0 CNIF bit 0 Legend: R = Readable bit HC = Hardware clear -n = Bit Value at POR W = Writable bit HS = Hardware set ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ C = Clearable by software ‘0’ = Bit is cleared x = Bit is unknown bit 24 Note 1: FCEIF: Flash Control Event Interrupt Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has occurred Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the NVM. Flash Programming 5 © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-13 PIC32MX Family Reference Manual Register 5-13: r-x — bit 31 IEC1: Interrupt Enable Control Register 1(1) r-x r-x r-x r-x — — — — r-x R/W-0 R/W-0 — USBIE FCEIE bit 24 r-x — bit 23 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IE DMA2IE DMA1IE DMA0IE bit 16 R/W-0 RTCCIE bit 15 R/W-0 FSCMIE R/W-0 I2C2MIE R/W-0 I2C2SIE R/W-0 I2C2BIE R/W-0 U2TXIE R/W-0 U2RXIE R/W-0 U2EIE bit 8 R/W-0 SPI2RXIE bit 7 R/W-0 SPI2TXIE R/W-0 SPI2EIE R/W-0 CMP2IE R/W-0 CMP1IE R/W-0 PMPIE R/W-0 AD1IE R/W-0 CNIE bit 0 Legend: R = Readable bit HC = Hardware clear -n = Bit Value at POR W = Writable bit HS = Hardware set ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ C = Clearable by software ‘0’ = Bit is cleared x = Bit is unknown bit 24 Note 1: FCEIE: Flash Control Event Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the NVM. DS61121D-page 5-14 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming Register 5-14: IPC11: Interrupt Priority Control Register 11(1) r-x r-x r-x r-x r-x r-x r-x r-x — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — USBIP<2:0> USBIS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — FCEIP<2:0> FCEIS<1:0> bit 0 Legend: R = Readable bit HC = Hardware clear -n = Bit Value at POR W = Writable bit HS = Hardware set ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ C = Clearable by software ‘0’ = Bit is cleared x = Bit is unknown bit 4-2 bit 1-0 Note 1: FCEIP<2:0>: Flash Control Event INterrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled FCEIS<1:0>: Flash Control Event Interrupt Subpriority bits 11 = Interrupt Subpriority is 3 10 = Interrupt Subpriority is 2 01 = Interrupt Subpriority is 1 00 = Interrupt Subpriority is 0 Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the NVM. 5 Flash Programming © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-15 PIC32MX Family Reference Manual 5.2.1 NVMCON Register The NVMCON register is the control register for Flash program/erase operations. This register selects whether an erase or program operation can be performed and is used to start the program or erase cycle. The NVMCON register is shown in Register 5-1. The lower byte of NVMCON configures the type of NVM operation that will be performed. A summary of the NVMCON setup values for various program and erase operations is given in Table 5-3. Table 5-3: NVMCON Register Values Operation Page Erase Program Word Program Row NOP NVMCON Value 0x8004 0x8001 0x8003 0x8000 5.2.2 NVMADDR Register The NVM Address register selects the row for Flash memory writes, the address location for word writes, and the page address for Flash memory erase operations. 5.2.3 NVMKEY Register NVMKEY is a write-only register that is used to prevent accidental writes/erasures of Flash or EEPROM memory. To start a programming or an erase sequence, the following steps must be taken in the exact order shown: 1. Write 0xAA996655 to NVMKEY. 2. Write 0x556699AA to NVMKEY. After this sequence, only the next transaction on the peripheral bus is allowed to write the NVMCON register. In most cases, the user will simply need to set the NVMWR bit in the NVMCON register to start the program or erase cycle. Interrupts should be disabled during the unlock sequence. 5.2.4 NVMSRCADDR Register The NVM Source Address register selects the source data buffer address in SRAM for performing row programming operations. Note: The address must be word aligned. DS61121D-page 5-16 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming 5.3 RTSP OPERATION RTSP allows the user code to modify Flash program memory contents. The device Flash memory is divided into two logical Flash partitions: the Program Flash Memory (PFM), and the Boot Flash Memory (BFM). The last page in Boot Flash Memory contains the DEBUG Page, which is reserved for use by the debugger tool while debugging. The program Flash array for the PIC32MX device is built up of a series of rows. A row contains 128 32-bit instruction words or 512 bytes. A group of 8 rows compose a page; which, therefore, contains 8 × 512 = 4096 bytes or 1024 instruction words. A page of Flash is the smallest unit of memory that can be erased at a single time. The program Flash array can be programmed in one of two ways: • Row programming, with 128 instruction words at a time. • Word programming, with 1 instruction word at a time. The CPU stalls (waits) until the programming operation is finished. The CPU will not execute any instruction, or respond to interrupts, during this time. If any interrupts occur during the programming cycle, they remain pending until the cycle completes. Note: A minimum VDD requirement for Flash erase and write operations is required. Refer to the specific device data sheet for further details. Flash Programming 5 © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-17 PIC32MX Family Reference Manual 5.4 LOCK-OUT FEATURE 5.4.1 NVMWREN A number of mechanisms exist within the device to ensure that inadvertent writes to program Flash do not occur. The NVMWREN (NVMCON<14>) bit should be zero, unless the software intends to write to the program Flash. When NVMWREN = 1, the Flash write control bit NVMWR (NVMCON<15>) is writable and the Flash LVD circuit is enabled. 5.4.2 NVMKEY In addition to the write protection provided by the NVMWREN bit, an unlock sequence needs to be performed before the NVMCON.NVMWR bit can be set. If the NVMWR (NVMCON<15>) bit is not set on the next peripheral bus transaction (read or write), NVMWR is locked and the unlock sequence must be restarted. 5.4.3 Unlock Sequence To unlock Flash operations, steps 3 through 8 below must be performed exactly in order. If the sequence is not followed exactly, NVMWR is not set. 1. Suspend or disable all initiators that can access the Peripheral Bus and interrupt the unlock sequence, e.g., DMA and interrupts. 2. Set NVMWREN (NVMCON<14>) to allow writes to NVMWR and set NVMOP<3:0> (NVMCON<3:0>) to the desired operation with a single store instruction. 3. Load 0xAA996655 to CPU register X. 4. Load 0x556699AA to CPU register Y. 5. Load 0x00008000 to CPU register Z. 6. Store CPU register X to NVMKEY. 7. Store CPU register Y to NVMKEY. 8. Store CPU register Z to NVMCONSET. 9. Wait for NVMWR (NVMCON<15>) bit to be clean. 10. Clear the NVMWREN (NVMCON<14>) bit. 11. Check the NVMERR (NVMCON<13>) and LVDERR (NVMCON<12>) bits to ensure that the program/erase sequence completed successfully. When the NVMWR bit is set, the program/erase sequence starts and the CPU is unable to execute from Flash memory for the duration of the sequence. DS61121D-page 5-18 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming Example 5-1: Unlock Example unsigned int NVMUnlock (unsigned int nvmop) { unsigned int status; // Suspend or Disable all Interrupts asm volatile (“di %0” : “=r” (status)); // Enable Flash Write/Erase Operations and Select // Flash operation to perform NVMCON = nvmop; // Write Keys NVMKEY = 0xAA996655; NVMKEY = 0x556699AA; // Start the operation using the Set Register NVMCONSET = 0x8000; // Wait for operation to complete while (NVMCON & 0x8000); // Restore Interrupts if (status & 0x00000001 asm volatile (“ei”); else asm volatile (“di”); // Return NVMERR and LVDERR Error Status Bits return (NVMCON & 0x3000) } Flash Programming 5 © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-19 PIC32MX Family Reference Manual 5.5 WORD PROGRAMMING SEQUENCE The smallest block of data that can be programmed in a single operation is one 32-bit word. The data to be programmed must be written to the NVMDATA register, and the address of the word must be loaded into the NVMADDR register before the programming sequence is initiated. The instruction word at the location pointed to by NVMADDR is then programmed. A program sequence comprises the following steps: 1. Write 32-bit data to be programmed to the NVMDATA register. 2. Load the NVMADDR register with the address to be programmed. 3. Run the unlock sequence using the Word Program command (see Section 5.4.3 “Unlock Sequence”). The program sequence completes, and the NVMWR (NVMCON<15>) bit is cleared by hardware. Example 5-2: Word Program Example unsigned int NVMWriteWord (void* address, unsigned int data) { unsigned int res; // Load data into NVMDATA register NVMDATA = data; // Load address to program into NVMADDR register NVMADDR = (unsigned int) address; // Unlock and Write Word res = NVMUnlock (0x4001); // Return Result return res; } DS61121D-page 5-20 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming 5.6 ROW PROGRAMMING SEQUENCE The largest block of data that can be programmed is 1 row, which equates to 512 bytes of data. The row of data must first be loaded into a buffer in SRAM. The NVMADDR register then points to the Flash address where the Flash controller will start programming the row of data. Note: The controller ignores the sub-row address bits and always starts programming at the beginning of a row. A row program sequence comprises the following steps: 1. Write the entire row of data to be programmed into system SRAM. The source address must be word aligned. 2. Set the NVMADDR register with the start address of the Flash row to be programmed. 3. Set the NVMSRCADDR register with the physical source address from step 1. 4. Run the unlock sequence using the Row Program command (see Section 5.4.3 “Unlock Sequence”). 5. The program sequence completes, and the NVMWR (NVMCON<15>) bit is cleared by hardware. Example 5-3: Row Program Example unsigned int NVMWriteRow (void* address, void* data) { unsigned int res; // Set NVMADDR to Start Address of row to program NVMADDR = (unsigned int) address; // Set NVMSRCADDR to the SRAM data buffer Address NVMSRCADDR = (unsigned int) data; // Unlock and Write Row res = NVMUnlock(0x4003); // Return Result return res; } Flash Programming 5 © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-21 PIC32MX Family Reference Manual 5.7 PAGE ERASE SEQUENCE A page erase performs an erase of a single page of either PFM or BFM, which equates to 4096 bytes. The page to be erased is selected using the NVMADDR register. Note: The lower bits of the address are ignored in page selection. A page of Flash can only be erased if its associated page write protection is not enabled. • All BFM pages are affected by the Boot write protection Configuration bit. • PFM pages are affected by the Program Flash write protection Configuration bits. If in Mission mode, the application must not be executing from the erased page. A page erase sequence comprises the following steps: 1. Set the NVMADDR register with the address of the page to be erased. 2. Run the unlock sequence using the desired Erase command (see Section 5.4.3 “Unlock Sequence”). The erase sequence completes and the NVMWR (NVMCON<15>) bit is cleared by hardware. Example 5-4: Page Erase Example unsigned int NVMErasePage(void* address) { unsigned int res; // Set NVMADDR to the Start Address of page to erase NVMADDR = (unsigned int) address; // Unlock and Erase Page res = NVMUnlock(0x4004); // Return Result return res; } DS61121D-page 5-22 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming 5.8 PROGRAM FLASH MEMORY ERASE SEQUENCE It is possible to erase the entire PFM area. This mode leaves the Boot Flash intact and is intended to be used by a field upgradeable device. The Program Flash can be erased if all pages in the Program Flash are not write-protected. Note: The application must NOT be executing from the PFM address range. A PFM erase sequence comprises the following steps: 1. Run the unlock sequence using the Program Flash memory Erase command (see Sec- tion 5.4.3 “Unlock Sequence”) The erase sequence completes and the NVMWR (NVMCON<15>) bit is cleared by hardware. Example 5-5: Program Flash Erase Example unsigned int NVMErasePFM(void) { unsigned int res; // Unlock and Erase Program Flash res = NVMUnlock(0x4005); // Return Result return res; } Flash Programming 5 © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-23 PIC32MX Family Reference Manual 5.9 5.10 OPERATION IN POWER-SAVING AND DEBUG MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 5.9.1 Operation in SLEEP Mode When the PIC32MX device enters SLEEP mode, the system clock is disabled. The Flash controller does not function in SLEEP mode. If entry into SLEEP mode occurs while an NVM operation is in progress, then the device will not go into sleep until the NVM operation is complete. 5.9.2 Operation in IDLE Mode IDLE mode has no effect on the Flash controller module when a programming operation is active. The CPU continues to be stalled until the programming operation completes. 5.9.3 Operation in DEBUG Mode The Flash controller does not provide debug Freeze capability and therefore has no effect on the Flash controller module when a programming operation is active. The CPU continues to be stalled until the programming operation completes. Interrupting the normal programming sequence could cause the device to latch-up. The only exception to this is the NVMKEY unlock sequence, which is suspended when in DEBUG mode, allowing the user to single step through the unlock sequence. Note: The FRZ bit is readable and writable only when the CPU is executing in Debug Exception mode. In all other modes, the FRZ bit reads as ‘0’. If FRZ bit is changed during DEBUG mode, the new value does not take effect until the current Debug Exception mode is exited and re-entered. During the Debug Exception mode, the FRZ bit reads the state of the peripheral when entering DEBUG mode. EFFECTS OF VARIOUS RESETS 5.10.1 Device Reset Only the NVMCON bits for NVMWREN and LVDSTAT are reset on a device Reset. All other SFR bits are only reset by POR. The state of the NUMKEY is reset by a device Reset however. 5.10.2 Power-on Reset All Flash controller registers are forced to their reset states upon a POR. 5.10.3 Watchdog Timer Reset All Flash controller registers are unchanged upon a Watchdog Timer Reset DS61121D-page 5-24 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming 5.11 INTERRUPTS The Flash Controller has the ability to generate an interrupt reflecting the events that occur during the programming operations. The following interrupt can be generated: Flash Control Event Interrupt FCEIF (IFS1<24> The interrupt flag must be cleared in software.The Flash Controller is enabled as a source of interrupt via the following respective Flash Controller interrupt enable bit: • FCEIE (IE1<24>) The interrupt priority-level bits and interrupt subpriority-level bits must also be configured: • FCEIP (IPC11<2:0> and FCEIS (IPC11<1:0>) Refer to Section 8. “Interrupts” in this manual for details. 5.11.1 Interrupt Configuration The Flash Controller module has the following dedicated interrupt flag bit. • FCEIF The Flash Controller module also has the following corresponding interrupt enable/mask bit: • FCEIE The bits determine the source of an interrupt and enable or disable an individual interrupt source. Note that all the interrupt sources for a specific Flash Controller module share just one interrupt vector. Note that the FCEIF bit will be set without regard to the state of the corresponding enable bit, and the IF bit can be polled by software if desired. The FCEIE bit is used to define the behavior of the Vector Interrupt Controller (VIC) when a corresponding FCEIF bit is set. When the corresponding IE bit is clear the VIC module does not generate a CPU interrupt for the event. If the IE bit is set, the VIC module will generate an interrupt to the CPU when the corresponding IF bit is set (subject to the priority and subpriority as outlined in the following paragraphs). It is the responsibility of the user’s software routine that services a particular interrupt to clear the appropriate Interrupt Flag bit before the service routine is complete. The priority of the Flash Controller module can be set independently with the FCEIP<2:0> bits. This priority defines the priority group to which the interrupt source is assigned. The priority groups range from a value of 7 (the highest priority), to a value of 0, which does not generate an interrupt. An interrupt being serviced is preempted by an interrupt in a higher priority group. The subpriority bits allow setting the priority of a interrupt source within a priority group. The values of the subpriority, FCEIS<1:0>, range from 3 (the highest priority), to 0 the lowest priority. An interrupt with the same priority group but having a higher subpriority value, does not preempt a lower subpriority interrupt that is in progress. The priority group and subpriority bits allow more than one interrupt source to share the same priority and subpriority. If simultaneous interrupts occur in this configuration the natural order of the interrupt sources within a priority/subpriority group pair determine the interrupt generated. The natural priority is based on the vector numbers of the interrupt sources. The lower the vector number, the higher the natural priority of the interrupt. Any interrupts that are overridden by natural order generate their respective interrupts based on priority, subpriority, and natural order, after the interrupt flag for the current interrupt is cleared. After an enabled interrupt is generated, the CPU jumps to the vector assigned to that interrupt. 5 The vector number for the interrupt is the same as the natural order number. Then the CPU begins executing code at the vector address. The user’s code at this vector address should perform any application specific operations, clear the FCEIF interrupt flag, and then exit. Refer to Section 8. “Interrupts” in this manual for the vector address table details and more information on interrupts. Flash Programming © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-25 PIC32MX Family Reference Manual Table 5-4: Interrupt FCE UART Interrupt Vectors for Various Offsets with EBASE = 0x8000:0000 Vector/ Natural Order IRQ Number Vector Address IntCtl.VS = 0x01 Vector Address IntCtl.VS = 0x02 Vector Address IntCtl.VS = 0x04 Vector Address IntCtl.VS = 0x08 43 56 80000760 80000CC0 80001780 80002D00 Vector Address IntCtl.VS = 0x10 80005800 DS61121D-page 5-26 Preliminary © 2008 Microchip Technology Inc. Section 5. Flash Programming 5.12 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Flash module include the following: Title No related application notes at this time. Application Note # N/A Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. Flash Programming 5 © 2008 Microchip Technology Inc. Preliminary DS61121D-page 5-27 PIC32MX Family Reference Manual 5.13 REVISION HISTORY Revision A (September 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x. Revision D (June 2008) Revised Register 5-1, bit 14 NVMWREN; Add footnote 1 to Registers 5-12-5-14; Add note to Section 5.3; Revise Section 5.4.1; Revised Example 5-1; Change Reserved bits “Maintain as” to “Write”. DS61121D-page 5-28 Preliminary © 2008 Microchip Technology Inc. Oscillators 6 Section 6. Oscillators HIGHLIGHTS This section of the manual contains the following topics: 6.1 Introduction................................................................................................................ 6-2 6.2 Control Registers....................................................................................................... 6-3 6.3 Operation: Clock Generation and Clock Sources.................................................... 6-20 6.4 Interrupts.................................................................................................................. 6-35 6.5 Input/Output Pins..................................................................................................... 6-37 6.6 Operation in Power-Saving Modes.......................................................................... 6-38 6.7 Effects of Various Resets......................................................................................... 6-39 6.8 Design Tips .............................................................................................................. 6-39 6.9 Related Application Notes ....................................................................................... 6-43 6.10 Revision History....................................................................................................... 6-44 © 2008 Microchip Technology Inc. Preliminary DS61112E-page 6-1 PIC32MX Family Reference Manual 6.1 INTRODUCTION This section describes the PIC32MX oscillator system and its operation. The PIC32MX oscillator system has the following modules and features: • A total of four external and internal oscillator options as clock sources • On-chip PLL with user-selectable input divider, multiplier, and output divider to boost operating frequency on select internal and external oscillator sources • On-chip user selectable divisor postscaler on select oscillator sources • Software-controllable switching between various clock sources • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown A simplified diagram of the oscillator system is shown in Figure 6-1. Figure 6-1: PIC32MX Family Clock Diagram OSCI OSCO Primary Oscillator (POSC) PBCLK out available on OSCO pin in certain clock modes div x UFIN PLL x24 div 2 4 MHz ≤ UFIN ≤ 5 MHz PLLDIV<2:0> USB Clock (48 MHz) UFRCEN UPLLEN XT, HS, EC 4 MHz ≤ FIN ≤ 5 MHz XTPLL, HSPLL, FIN div x PLL div y ECPLL, FRCPLL Peripherals Postscaler div x PBCLK FRC Oscillator 8 MHz typical TUN<5:0> PLL Input Divider FPLLIDIV<2:0> PLL Output Divider PLLODIV<2:0> COSC<2:0> PLL Multiplier PLLMULT<2:0> FRC div 16 FRC /16 PBDIV<2:0> CPU & Select Peripherals Postscaler FRCDIV SOSCO SOSCI LPRC Oscillator FRCDIV<2:0> 32 kHz typical Secondary Oscillator (SOSC) 32.768 kHz SOSCEN and FSOSCEN LPRC SOSC Clock Control Logic Fail-Safe Clock Monitor FSCM INT FSCM Event NOSC<2:0> COSC<2:0> FSCMEN<1:0> OSWEN WDT, PWRT Timer1, RTCC DS61112E-page 6-2 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.2 CONTROL REGISTERS The Oscillator module consists of the following Special Function Registers (SFRs): • OSCCON: Control Register for the Oscillator module OSCCONCLR, OSCCONSET, OSCCONINV: Atomic Bit Manipulation Write-only Registers for OSCCON register • OSCTUN: FRC Tuning Register for the Oscillator module OSCTUNCLR, OSCTUNSET, OSCTUNINV: Atomic Bit Manipulation Write-only Registers for OSCTUN register The Oscillator module also has the following associated bits for interrupt control: • Interrupt Flag Status bits (IFS1<14>) for Clock Fail FSCMIF in IFS1 Interrupt register • Interrupt Enable Control bits (IEC1<14>) for Clock Fail FSCMIE in IEC1 Interrupt register • Interrupt Priority Control bits (FSCMIP<12:10>) for Clock Fail in IPC8 Interrupt register • Interrupt Subpriority Control bits (FSCMIP<9:8>) for Clock Fail in IPC8 Interrupt register The following tables provide brief summaries of Oscillator-module-related registers. Corresponding registers appear after the summaries, followed by a detailed description of each register. Table 6-1: Name Oscillators SFR Summary Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 OSCCON 31:24 — — PLLODIV<2:0> 23:16 — SOSCRDY — PBDIV<1:0> 15:8 — COSC<2:0> — 7:0 CLKLOCK ULOCK LOCK SLPEN CF FRCDIV<2:0> PLLMULT<2:0> NOSC<2:0> UFRCEN SOSCEN OSWEN OSCCONCLR 31:0 OSCCONSET 31:0 OSCCONINV 31:0 OSCTUN 31:24 — 23:16 — 15:8 — 7:0 — OSCTUNCLR 31:0 OSCTUNSET 31:0 OSCTUNINV 31:0 WDTCON — — 15:8 ON — WDTCONCLR 31:0 WDTCONSET 31:0 WDTCONINV 31:0 IFS1 31:24 — 23:16 — 15:8 RTCCIF 7:0 SPI2RXIF IFS1CLR 31:0 IFS1SET 31:0 IFS1INV 31:0 Write clears selected bits in OSCCON, read yields undefined value Write sets selected bits in OSCCON, read yields undefined value Write inverts selected bits in OSCCON, read yields undefined value — — — — — — — — — — — — — — — — — — — TUN<5:0> Write clears selected bits in OSCTUN, read yields undefined value Write sets selected bits in OSCTUN, read yields undefined value Write inverts selected bits in OSCTUN, read yields undefined value — — — — — — — — — — — — — — — — — — SWDTPS<4:0> — Write clears selected bits in WDTCON, read yields an undefined value Write sets selected bits in WDTCON, read yields an undefined value Write inverts selected bits in WDTCON, read yields an undefined value — — — — — USBIF — — — DMA3IF DMA2IF DMA1IF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF Clears the selected bits in IFS1, read yields undefined value Sets the selected bits in IFS1, read yields undefined value Inverts the selected bits in IFS1, read yields undefined value — — — — — — WDTCLR FCEIF DMA0IF U2EIF CNIF Preliminary Preliminary DS61112E-page 6-3 PIC32MX Family Reference Manual Table 6-1: Name IEC1 IEC1CLR IEC1SET IEC1INV IPC8 IPC8CLR IPC8SET IPC8INV DEVCFG1 DEVCFG2 Oscillators SFR Summary (Continued) Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 31:24 — — — — — — USBIE FCEIE 23:16 — — — — DMA3IE DMA2IE DMA1IE DMA0IE 15:8 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE 7:0 SPI2RXIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 31:0 Write clears the selected bits in IE0, read yields undefined value 31:0 Write sets the selected bits in IE0, read yields undefined value 31:0 Write inverts the selected bits in IE0, read yields undefined value 31:24 — — — DMA0IP<2:0> DMA0IS<1:0> 23:16 — — — RTCCIP<2:0> RTCCIS<1:0> 15:8 — — — FSCMIP<2:0> FSCMIS<1:0> 7:0 — — — I2C2IP<2:0> I2C2IS<1:0> 31:0 Write clears the selected bits in IPC8, read yields undefined value 31:0 Write sets the selected bits in IPC8, read yields undefined value 31:0 Write inverts the selected bits in IPC8, read yields undefined value 31:24 — — — — — — — — 23:16 FWDTEN — — FWDTPS<4:0> 15:8 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMD<1:0> 7:0 IESO — FSOSCEN — — FNOSC<2:0> 31:24 — — — — — — — — 23:16 — — — — — FPLLODIV<2:0> 15:8 FUPLLEN — — — — FUPLLIDIV<2:0> 7:0 — FPLLMULT<2:0> — FPLLIDIV<2:0> DS61112E-page 6-4 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 Register 6-1: r-x — bit 31 OSCCON: Oscillator Control Register r-x R/W-x R/W-x — PLLODIV<2:0> R/W-x R/W-0 R/W-0 FRCDIV<2:0> R/W-1 bit 24 r-x R-0 r-x — SOSCRDY — bit 23 R/W-x R/W-x PBDIV<1:0> R/W-x R/W-x PLLMULT<2:0> R/W-x bit 16 r-x — bit 15 R-0 R-0 R-0 COSC<2:0> r-x R/W-x R/W-x R/W-x — NOSC<2:0> bit 8 R/W-0 CLKLOCK bit 7 R-0 ULOCK R-0 LOCK R/W-0 SLPEN R/W-0 CF R/W-0 UFRCEN R/W-x SOSCEN R/W-0 OSWEN bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-30 bit 29-27 bit 26-24 bit 23 bit 22 bit 21 Reserved: Write ‘0’; ignore read PLLODIV<2:0>: Output Divider for PLL 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 Note: On Reset these bits are set to the value of the FPLLODIV configuration bits (DEVCFG2<18:16>) FRCDIV<2:0>: Fast Internal RC Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 Reserved: Write ‘0’; ignore read SOSCRDY: Secondary Oscillator Ready Indicator bit 1 = Indicates that the Secondary Oscillator is running and is stable 0 = Secondary oscillator is either turned off or is still warming up Reserved: Write ‘0’; ignore read Preliminary Preliminary DS61112E-page 6-5 PIC32MX Family Reference Manual Register 6-1: OSCCON: Oscillator Control Register bit 20-19 PBDIV<1:0>: Peripheral Bus Clock Divisor 11 = PBCLK is SYSCLK divided by 8(default) 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note: On Reset these bits are set to the value of the Configuration bits (DEVCFG1<13:12>). bit 18-16 PLLMULT<2:0>: PLL Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 Note: On Reset these bits are set to the value of the FPLLMULT Configuration bits (DEVCFG2<6:4>). bit 15 Reserved: Write ‘0’; ignore read bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Fast Internal RC Oscillator divided by OSCCON bits 110 = Fast Internal RC Oscillator divided by 16 101 = Low-Power Internal RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Fast RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Fast RC Oscillator (FRC) Note: On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). bit 11 Reserved: Write ‘0’; ignore read bit 10-8 NOSC<2:0>: New Oscillator Selection bits 111 = Fast Internal RC Oscillator divided by OSCCON bits 110 = Fast Internal RC Oscillator divided by 16 101 = Low-Power Internal RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Fast Internal RC Oscillator (FRC) Note: On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). bit 7 CLKLOCK: Clock Selection Lock Enable bit If FSCM is enabled (FCKSM1 =1): 1 = Clock and PLL selections are locked. 0 = Clock and PLL selections are not locked and may be modified If FSCM is disabled (FCKSM1 =0): Note: Clock and PLL selections are never locked and may be modified. bit 6 ULOCK: USB PLL Lock Status bit 1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled bit 5 LOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 SLPEN: SLEEP Mode Enable bit 1 = Device will enter SLEEP mode when a WAIT instruction is executed 0 = Device will enter IDLE mode when a WAIT instruction is executed DS61112E-page 6-6 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 Register 6-1: OSCCON: Oscillator Control Register bit 3 CF: Clock Fail Detect bit 1 = FSCM (Fail Safe Clock Monitor) has detected a clock failure 0 = No clock failure has been detected bit 2 UFRCEN: USB FRC Clock Enable bit 1 = Enable FRC as the clock source for the USB clock source 0 = Use the primary oscillator or USB PLL as the USB clock source bit 1 SOSCEN: 32.768 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator Note: On Reset this bit is set to the value of the FSOSCEN Configuration bit (DEVCFG1<5>). bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC2:NOSC0 bits 0 = Oscillator switch is complete Preliminary Preliminary DS61112E-page 6-7 PIC32MX Family Reference Manual Register 6-2: OSCCONCLR: Oscillator Control Clear Register Write clears selected bits in OSCCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in OSCCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in OSCCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: OSCCONCLR = 0x00000101 will clear bits 8 and 0 in OSCCON register. Register 6-3: OSCCONSET: Oscillator Control Set Register Write sets selected bits in OSCCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in OSCCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in OSCCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: OSCCONSET = 0x00000101 will set bits 8 and 0 in OSCCON register. Register 6-4: OSCCONINV: Oscillator Control Invert Register Write inverts selected bits in OSCCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in OSCCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in OSCCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: OSCCONINV = 0x00000101 will invert bits 8 and 0 in OSCCON register. DS61112E-page 6-8 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 Register 6-5: OSCTUN: FRC Tuning Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 15 bit 8 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31:6 bit 5-0 Reserved: Write ‘0’; ignore read TUN<5:0>: FRC Oscillator Tuning bits 011111 =Maximum frequency. 011110 = • 000001 = 000000 =Center frequency. Oscillator runs at calibrated frequency. 111111 = • 100001 = 100000 =Minimum frequency. Preliminary Preliminary DS61112E-page 6-9 PIC32MX Family Reference Manual Register 6-6: OSCTUNCLR: FRC Tuning Clear Register Write clears selected bits in OSCTUN, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in OSCTUN A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in OSCTUN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: OSCTUNCLR = 0x00000021 will clear bits 5 and 0 in OSCTUN register. Register 6-7: OSCTUNSET: FRC Tuning Set Register Write sets selected bits in OSCTUN, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in OSCTUN A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in OSCTUN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: OSCTUNSET = 0x00000021 will set bits 5 and 0 in OSCTUN register. Register 6-8: OSCTUNINV: FRC Tuning Invert Register Write inverts selected bits in OSCTUN, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in OSCTUN A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in OSCTUN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: OSCTUNINV = 0x00000021 will invert bits 5 and 0 in OSCTUN register. DS61112E-page 6-10 Preliminary © 2008 Microchip Technology Inc. Oscillators Register 6-9: r-x — bit 31 WDTCON: Watchdog Timer Control Register r-x r-x r-x r-x — — — — Section 6. Oscillators 6 r-x r-x r-x — — — bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 r-x r-x r-x r-x r-x r-x r-x ON — — — — — — — bit 15 bit 8 r-x — bit 7 R-x R-x R-x R-x R-x r-0 R/W-0 WDTPS<4:0> — WDTCLR bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 15 ON: Watchdog Timer Enable bit 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if it was enabled in software Note 1: A read of this bit will result in a ‘1’ if the WDT is enabled by the device configuration or by software. 2: The LPRC oscillator will automatically be enabled when this bit is set. 3: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. Preliminary Preliminary DS61112E-page 6-11 PIC32MX Family Reference Manual Register 6-10: WDTCONCLR: Comparator Control Clear Register Write clears selected bits in WDTCON, read yields undefined value bit 31 bit 0 bit 31-0 Clear selected bits in WDTCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in WDTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: WDTCONCLR = 0x00008001 clears bits 15 and 0 in WDTCON register. Register 6-11: WDTCONSET: Comparator Control Set Register Write sets selected bits in WDTCON, read yields undefined value bit 31 bit 0 bit 31-0 Set selected bits in WDTCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in WDTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: WDTCONSET = 0x00008001 sets bits 15 and 0 in WDTCON register. Register 6-12: WDTCONINV: Comparator Control Invert Register Write inverts selected bits in WDTCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in WDTCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in WDTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: WDTCONINV = 0x00008001 inverts bits 15 and 0 in WDTCON register. DS61112E-page 6-12 Preliminary © 2008 Microchip Technology Inc. Oscillators Register 6-13: IFS1: Interrupt Flag Status Register(1) r-x r-x r-x r-x r-x — — — — — bit 31 Section 6. Oscillators 6 r-x R/W-0 R/W-0 — USBIF FCEIF bit 24 r-x r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — — DMA3IF DMA2IF DMA1IF DMA0IF bit 23 bit 16 R/W-0 RTCCIF bit 15 R/W-0 FSCMIF R/W-0 I2C2MIF R/W-0 I2C2SIF R/W-0 I2C2BIF R/W-0 U2TXIF R/W-0 U2RXIF R/W-0 U2EIF bit 8 R/W-0 SPI2RXIF bit 7 R/W-0 SPI2TXIF R/W-0 SPI2EIF R/W-0 CMP2IF R/W-0 CMP1IF R/W-0 PMPIF R/W-0 AD1IF R/W-0 CNIF bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 14 Note 1: FSCMIF: Fail-Safe Clock Monitor Interrupt Flag bit 1 = Interrupt request has occured 0 = No interrupt request has a occurred Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the oscillator. Preliminary Preliminary DS61112E-page 6-13 PIC32MX Family Reference Manual Register 6-14: r-x — bit 31 IEC1: Interrupt Enable Control Register(1) r-x r-x r-x r-x — — — — r-x R/W-0 R/W-0 — USBIE FCEIE bit 24 r-x r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — — DMA3IE DMA2IE DMA1IE DMA0IE bit 23 bit 16 R/W-0 RTCCIE bit 15 R/W-0 FSCMIE R/W-0 I2C2MIE R/W-0 I2C2SIE R/W-0 I2C2BIE R/W-0 U2TXIE R/W-0 U2RXIE R/W-0 U2EIE bit 8 R/W-0 SPI2RXIE bit 7 R/W-0 SPI2TXIE R/W-0 SPI2EIE R/W-0 CMP2IE R/W-0 CMP1IE R/W-0 PMPIE R/W-0 AD1IE R/W-0 CNIE bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 14 Note 1: FSCMIE: Fail-Safe Clock Monitor Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the oscillator. DS61112E-page 6-14 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 Register 6-15: r-x — bit 31 IPC8: Interrupt Priority Control Register 8(1) r-x r-x R/W-0 R/W-0 — — DMA0IP<2:0> R/W-0 R/W-0 R/W-0 DMA0IS<1:0> bit 24 r-x r-x — — bit 23 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — RTCCIP<2:0> RTCCIS<1:0> bit 16 r-x r-x — — bit 15 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — FSCMIP<2:0> FSCMIS<1:0> bit 8 r-x r-x — — bit 7 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — I2C2IP<2:0> I2C2IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 12-10 FSCMIP<2:0>: Fail-Safe Clock Monitor Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 9-8 FSCMIS<1:0>: Fail-Safe Clock Monitor Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the oscillator. Preliminary Preliminary DS61112E-page 6-15 PIC32MX Family Reference Manual Register 6-16: DEVCFG1 Boot Configuration Register r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — bit 31 bit 24 R/P-1 FWDTEN bit 23 R/P-1 — r-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — FWDTPS4 FWDTPS3 FWDTPS2 FWDTPS1 FWDTPS0 bit 16 R/P-1 R/P-1 FCKSM<1:0> bit 15 R/P-1 R/P-1 FPBDIV<1:0> r-1 R/P-1 R/P-1 R/P-1 — OSCIOFNC POSCMD<1:0> bit 8 R/P-1 IESO bit 7 r-1 R/P-1 r-1 — FSOSCEN — r-1 R/P-1 R/P-1 R/P-1 — FNOSC2 FNOSC1 FNOSC0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-14 bit 10 bit 13-12 bit 11 bit 9-8 bit 7 bit 5 Unimplemented: Maintain ‘1’ FCKSM<1:0>: Fail-safe Clock Monitor (FSCM) and Clock Switch Configuration bits 1x = FSCM and Clock Switching are disabled 01 = Clock Switching is enabled, FSCM is disabled 00 = Clock Switching and FSCM are enabled OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 or = 00) 0 = CLKO output disabled FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Unimplemented: Maintain as ‘1’ POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator Disabled 10 = HS mode 01 = XT Mode 00 = EC Mode IESO: Internal External Clock Switch Over Select bit 1 = Internal External Clock Switch Over Mode Enabled. Two-Speed Start-up mode. 0 = Internal External Clock Switch Over Mode Disabled. Single-Speed Start-up mode. FSOSCEN: Secondary Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator DS61112E-page 6-16 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 Register 6-16: DEVCFG1 Boot Configuration Register bit 2-0 FNOSC<2:0>: CPU Clock Oscillator Select bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRC Divided by 16 (FRCDIV16) 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL (XTPLL, HSPLL, or ECPLL) 010 = Primary Oscillator without PLL (XT, HS, or EC) 001 = Fast RC Oscillator with PLL 000 = Fast RC Oscillator (FRC) Preliminary Preliminary DS61112E-page 6-17 PIC32MX Family Reference Manual Register 6-17: DEVCFG2 Boot Configuration Register r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 — — — — — — — — bit 31 bit 24 r-1 r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1 — — — — — FPLLODIV<2:0> bit 23 bit 16 R/P-1 r-1 r-1 r-1 r-1 R/P-1 R/P-1 R/P-1 FUPLLEN — — — — FUPLLIDIV<2:0> bit 15 bit 8 U-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 — FPLLMULT<2:0> — FPLLIDIV<2:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 18-16 bit 15 bit 10-8 bit 6-4 FPLLODIV<2:0>: Default postscaler for PLL. 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 (default setting) FUPLLEN: USB PLL Enable bit 00 = Enable USB PLL 00 = Disable and bypass USB PLL FUPLLIDIV<2:0>: PLL Input Divider bits 000 = 1x divider 001 = 2x divider 010 = 3x divider 011 = 4x divider 100 = 5x divider 101 = 6x divider 110 = 10x divider 111 = 12x divider FPLLMULT<2:0>: Default PLL Multiplier Value bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier DS61112E-page 6-18 Preliminary © 2008 Microchip Technology Inc. Oscillators Register 6-17: DEVCFG2 Boot Configuration Register bit 2-0 FPLLIDIV<2:0>: Default PLL Input Divider Value bits 111 = Divide by 12 110 = Divide by 10 101 = Divide by 6 100 = Divide by 5 011 = Divide by 4 010 = Divide by 3 001 = Divide by 2 000 = Divide by 1 Section 6. Oscillators 6 Preliminary Preliminary DS61112E-page 6-19 PIC32MX Family Reference Manual 6.3 OPERATION: CLOCK GENERATION AND CLOCK SOURCES The PIC32MX family has multiple internal clocks that are derived from internal or external clock sources. Some of these clock sources have Phase Locked Loops (PLLs), programmable output divider, or input divider to scale the input frequency to suit the application. The clock source can be changed on the fly by software. The oscillator control register is locked by hardware, it must be unlocked by a series of writes before software can perform a clock switch. There are three main clocks in the PIC32MX device • The System clock (SYSCLK) used by CPU and some peripherals • The Peripheral Bus Clock (PBCLK) used by most peripherals • The USB Clock (USBCLK) used by USB peripheral The PIC32MX clocks are derived from one of the following sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Internal Fast RC Oscillator (FRC) • Internal Low-Power RC Oscillator (LPRC) Each of the clock sources has unique configurable options, such as a PLL, input divider, and/or output divider, that are detailed in their respective sections. There are up to four internal clocks depending on the specific device. The clocks are derived from the currently selected oscillator source. Note: Clock sources for peripherals that use external clocks, such as the RTC and Timer1, are covered in their respective sections. 6.3.1 System Clock (SYSCLK) Generation Table 6-2: The SYSCLK is primarily used by the CPU and select peripherals such as DMA, Interrupt Controller, and Prefetch Cache. The SYSCLK is derived from one of the four clock sources: POSC, SOSC, FRC, and LPRC. Some of the clock sources have specific clock multipliers and/or divider options. No clock scaling is applied other than the user specified values. The SYSCLK source is selected by the device configuration and can be changed by software during operation. The ability to switch clock sources during operation allows the application to reduce power consumption by reducing the clock speed. Refer to Table for a list of SYSCLK sources. Clock Selection Configuration Bit Values Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC2: FNOSC0 ADIV Notes Fast RC Oscillator with Postscaler (FRCDIV) Internal xx 111 1, 2 Fast RC Oscillator divided by 16 (FRCDIV16) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal xx 101 1 Secondary (Timer1/RTCC) Oscillator (SOSC) Secondary xx 100 1 Primary Oscillator (HS) with PLL Module Primary 10 011 3 (HSPLL) Primary Oscillator (XT) with PLL Module Primary 01 011 3 (XTPLL) Primary Oscillator (EC) with PLL Module Primary 00 011 3 (ECPLL) Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Note 1: OSCO pin function as PBCLK out or Digital I/O is determined by the OSCIOFNC Configuration bit. When the pin is not required by the Oscillator mode it may be configured for one of these options. 2: Default Oscillator mode for an unprogrammed (erased) device. 3: When using the PLL modes the input divider must be chosen such that resulting frequency applied to the PLL is in the range of 4 MHz to 5 MHz. DS61112E-page 6-20 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 Table 6-2: Clock Selection Configuration Bit Values (Continued) Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC2: FNOSC0 ADIV Notes Primary Oscillator (EC) Primary 00 010 Fast RC Oscillator with PLL Module Internal 10 001 1 (FRCPLL) Fast RC Oscillator (FRC) Internal xx 000 1 Note 1: OSCO pin function as PBCLK out or Digital I/O is determined by the OSCIOFNC Configuration bit. When the pin is not required by the Oscillator mode it may be configured for one of these options. 2: Default Oscillator mode for an unprogrammed (erased) device. 3: When using the PLL modes the input divider must be chosen such that resulting frequency applied to the PLL is in the range of 4 MHz to 5 MHz. 6.3.1.1 Primary Oscillator (POSC) The POSC has six operating modes, as summarized in Table 6-3: High Speed (HS), External Resonator (XT), and the External Clock (EC) mode make up the first three modes. These modes can each be combined with a PLL module to form the last three modes: High Speed PLL (HSPLL), External Resonator PLL (XTPLL), and External Clock (ECPLL). Figures 6-2 through 6-4 show various POSC configurations. The primary oscillator is connected to the OSCI and OSCO pins of the device family. The primary oscillator can be configured for an external clock input or an external crystal or resonator. The XT, XTPLL, HS, and HSPLL modes are external crystal or resonator controller oscillator modes. The XT and HS modes are functionally very similar. The primary difference is the gain of the internal inverter of the oscillator circuit (see Figure 6-2). The XT mode is a medium power, medium frequency mode and has medium inverter gain. HS mode is higher power and provides the highest oscillator frequencies and has the highest inverter gain. OSCO provides crystal/resonator feedback in both XT and HS Oscillator modes and hence is not available for use as a input or output in these modes. The XTPLL and HSPLL modes have a Phase Locked Loop (PLL) with user selectable input divider, multiplier, and output divider to provide a wide range of output frequencies. The oscillator circuit will consume more current when the PLL is enabled. The External Clock modes, EC and ECPLL, allow the system clock to be derived from an external clock source. The EC/ECPLL modes configure the OSCI pin as a high-impedance input that can be driven by a CMOS driver. The external clock can be used to drive the system clock directly (EC) or the ECPLL module with prescale and postscaler can be used to change the input clock frequency (ECPLL). The External Clock mode also disables the internal feedback buffer allowing the OSCO pin to be used for other functions. In the External Clock mode the OSCO pin can be used as an additional device I/O pin (see Figure 6-4) or a PBCLK output pin (see Figure 6-3). Note: When using the PLL modes the input divider must be chosen such that resulting frequency applied to the PLL is in the range of 4 MHz to 5 MHz. Table 6-3: Primary Oscillator Operating Modes Oscillator Mode Description HS XT EC HSPLL XTPLL 10 MHz-40 MHz crystal, high speed crystal 3.5 MHz-10 MHz resonator, crystal or resonator External clock input Crystal, PLL enabled Crystal resonator, PLL enabled ECPLL External clock input, PLL enabled Note: The clock applied to the CPU after applicable prescalers, postscalers, and PLL multipliers must not exceed the maximum allowable processor frequency. Preliminary Preliminary DS61112E-page 6-21 PIC32MX Family Reference Manual Figure 6-2: Crystal or Ceramic Resonator Operation (XT, XTPLL, HS, or HSPLL Oscillator Mode) C1(3) C2(3) OSCI XTAL OSCO RS(1) RF(2) To Internal Logic Enable PIC32MX Note 1: 2: 3: A series resistor, Rs, may be required for AT strip cut crystals. The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ. See 6.8.3.1 “Determining the Best Values for Oscillator Components”. Figure 6-3: External Clock Input Operation With Clock-Out (EC, ECPLL Mode) Clock from Ext. System PBCLK OSCI PIC32MX OSCO (Clock Out) Figure 6-4: External Clock Input Operation with no Clock-Out (EC, ECPLL Mode) Clock from Ext. System I/O OSCI PIC32MX I/O (OSCO) 6.3.1.1.1 Primary Oscillator (POSC) Configuration To configure the POSC the following steps should be performed: 1. Select POSC as the default oscillator in the device Configuration register DEVCFG1 by setting FNOSC<2:0> = ‘010’ without PLL or ‘011’ with PLL 2. Select the desired mode HS, XT, or EC, using POSCMD<1:0> in DEVCFG1. 3. If the PLL is to be used: a)Select the appropriate Configuration bits for the PLL input divider to scale the input frequency to be between 4 MHz and 5 MHz using FPLLIDIV<2:0> in DEVCFG2. b)Select the desired PLL multiplier ratio using FPLLMULT<2:0>) in DEVCFG2. c)At runtime, select the desired PLL output divider using PLLODIV (OSCCON<29:27>) to provide the desired clock frequency. The default value is set by DEVCFG1. DS61112E-page 6-22 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.3.1.1.2 Oscillator Start-up Timer In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an Oscillator Start-up Timer (OST) is provided. The OST is a simple 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system. This time-out period is designated as TOST. The amplitude of the oscillator signal must reach the VIL and VIH thresholds for the oscillator pins before the OST can begin to count cycles. The TOST interval is required every time the oscillator has to restart (i.e., on POR, BOR and wake-up from SLEEP mode). The Oscillator Start-up Timer is applied to the MS and HS modes for the primary oscillator, as well as the secondary oscillator, see 6.3.1.2 “Secondary Oscillator (SOSC)”. 6.3.1.1.3 System Clock Phase Locked Loop (PLL) The system clock PLL provides a user configurable input divider, multiplier, and output divider which can be used with the XT, HS and EC primary oscillator modes and with the Internal Fast RC Oscillator (FRC) mode to create a variety of clock frequencies from a single clock source. The Input divider, multiplier, and output divider control initial value bits are contained in the in the DEVCFG2 device Configuration register. The multiplier and output divider bits are also contained in the OSCCON register. As part of a device Reset, values from the device configuration register DEVCFG2 are copied to the OSCCON register. This allows the user to preset the input divider to provide the appropriate input frequency to the PLL and set an initial PLL multiplier when programming the device. At runtime the multiplier, divider and output divider can be changed by software to scale the clock frequency to suit the application. The PLL input divider cannot be changed at run time. This is to prevent applying an input frequency outside the specified limits to the PLL. To configure the PLL the following steps are required: 1. Calculate the PLL input divider, PLL multiplier, and PLL output divider values. 2. Set the PLL input divider and the initial PLL multiplier value in the DEVCFG2 register when programming the part. 3. At runtime the PLL multiplier and PLL output divider can be changed to suit the applica- tion. Combinations of PLL input divider, multiplier and output divider provide a combined multiplier of approximately 0.006 to 24 times the input frequency. For reliable operation the output of the PLL module must not exceed the maximum clock frequency of the device. The PLL input divider value should be chosen to limit the input frequency to the PLL to the range of 4 MHz to 5 MHz. Due to the time required for the PLL to provide a stable output, a Status bit LOCK (OSCCON<5>) is provided. When the clock input to the PLL is changed, this bit is driven low (‘0’). After the PLL has achieved a lock or the PLL start-up timer has expired, the bit is set. The bit will be set upon the expiration of the timer even if the PLL has not achieved a lock. Preliminary Preliminary DS61112E-page 6-23 PIC32MX Family Reference Manual Table 6-4: Multiplier 15 16 17 18 19 20 21 24 Net Multiplier Output for Selected PLL and Output Divider Values Output Divider Net Multiplication factor PLLODIV <2:0> PLLMULT <2:0> Multiplier Postscaler Net Multiplication factor PLLODIV <2:0> PLLMULT <2:0> 1 15 ‘000’ ‘000’ 15 16 .938 ‘100’ ‘000’ 1 16 ‘000’ ‘001’ 16 16 1 ‘100’ ‘001’ 1 17 ‘000’ ‘010’ 17 16 1.063 ‘100’ ‘010’ 1 18 ‘000’ ‘011’ 18 16 1.125 ‘100’ ‘011’ 1 19 ‘000’ ‘100’ 19 16 1.188 ‘100’ ‘100’ 1 20 ‘000’ ‘101’ 20 16 1.250 ‘100’ ‘101’ 1 21 ‘000’ ‘110’ 21 16 1.313 ‘100’ ‘110’ 1 24 ‘000’ ‘111’ 24 16 1.5 ‘100’ ‘111’ 15 2 16 2 17 2 18 2 19 2 20 2 21 2 24 2 7.5 ‘001’ ‘000’ 15 32 .4688 ‘101’ ‘000’ 8 ‘001’ ‘001’ 16 32 .5 ‘101’ ‘001’ 8.5 ‘001’ ‘010’ 17 32 .5313 ‘101’ ‘010’ 9 ‘001’ ‘011’ 18 32 .5625 ‘101’ ‘011’ 9.5 ‘001’ ‘100’ 19 32 .5938 ‘101’ ‘100’ 10 ‘001’ ‘101’ 20 32 .6250 ‘101’ ‘101’ 10.5 ‘001’ ‘110’ 21 32 .6563 ‘101’ ‘110’ 12 ‘001’ ‘111’ 24 32 .7500 ‘101’ ‘111’ 15 4 16 4 17 4 18 4 19 4 20 4 21 4 24 4 3.75 ‘010’ ‘000’ 15 64 4 ‘010’ ‘001’ 16 64 4.25 ‘010’ ‘010’ 17 64 4.5 ‘010’ ‘011’ 18 64 4.75 ‘010’ ‘100’ 19 64 5 ‘010’ ‘101’ 20 64 5.25 ‘010’ ‘110’ 21 64 6 ‘010’ ‘111’ 24 64 .234 ‘110’ ‘000’ .250 ‘110’ ‘001’ .266 ‘110’ ‘010’ .281 ‘110’ ‘011’ .297 ‘110’ ‘100’ .313 ‘110’ ‘101’ .328 ‘110’ ‘110’ .375 ‘110’ ‘111’ 15 8 1.875 ‘011’ ‘000’ 15 256 .05859 ‘111’ ‘000’ 16 8 2 ‘011’ ‘001’ 16 256 .06250 ‘111’ ‘001’ 17 8 2.125 ‘011’ ‘010’ 17 256 .06641 ‘111’ ‘010’ 18 8 2.250 ‘011’ ‘011’ 18 256 .07031 ‘111’ ‘011’ 19 8 2.375 ‘011’ ‘100’ 19 256 .07422 ‘111’ ‘100’ 20 8 2.5 ‘011’ ‘101’ 20 256 .07813 ‘111’ ‘101’ 21 8 2.625 ‘011’ ‘110’ 21 256 .08203 ‘111’ ‘110’ 24 8 3 ‘011’ ‘111’ 24 256 .09375 ‘111’ ‘111’ 6.3.1.1.4 USB PLL Lock Status The ULOCK bit (OSCCON<6>) is a read-only status bit that indicates the lock status of the USB PLL. It is automatically set after the typical time delay for the PLL to achieve lock, also designated as TLOCK. If the PLL does not stabilize properly during start-up, LOCK may not reflect the actual status of PLL lock, nor does it detect when the PLL loses lock during normal operation. The ULOCK bit is cleared at a Power-on Reset. It remains clear when any clock source not using the PLL is selected. DS61112E-page 6-24 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 Refer to the Electrical Characteristics section in the specific device data sheet for further information on the PLL lock interval. 6.3.1.1.5 Primary Oscillator Start-up from SLEEP Mode To ensure reliable wake-up from SLEEP, care must be taken to properly design the primary oscillator circuit. This is because the load capacitors have both partially charged to some quiescent value and phase differential at wake-up is minimal. Thus, more time is required to achieve stable oscillation. Remember also that low voltage, high temperatures and the lower frequency clock modes also impose limitations on loop gain, which in turn, affects start-up. Each of the following factors increases the start-up time: • Low-frequency design (with a Low Gain Clock mode) • Quiet environment (such as a battery operated device) • Operating in a shielded box (away from the noisy RF area) • Low voltage • High temperature • Wake-up from SLEEP mode 6.3.1.2 Secondary Oscillator (SOSC) The Secondary Oscillator (SOSC) is designed specifically for low-power operation with a external 32.768 kHz crystal. The oscillator is located on the SOSCO and SOSCI device pins and serves as a secondary crystal clock source for low-power operation. It can also drive Timer1 and/or the Real-Time Clock/Calendar module for Real-Time Clock applications. 6.3.1.2.1 Enabling the SOSC Oscillator The SOSC is hardware enabled by the FSOSCEN Configuration bit (DEVCFG1<5>). Once SOSC is enabled, software can control it by modifying SOSCEN bit (OSCCON<1>). Setting SOSCEN enables the oscillator; the SOSCO and SOSCI pins are controlled by the oscillator and cannot be used for port I/O or other functions. Note: An unlock sequence is required before a write to OSCCON can occur. Refer to 6.3.5.2 “Oscillator Switching Sequence” for more information. The Secondary Oscillator requires a warm-up period before it can be used as a clock source. When the oscillator is enabled, a warm-up counter increments to 1024. When the counter expires the SOSCRDY (OSCCON<22>) is set to ‘1’. Refer to 6.3.1.1.2 “Oscillator Start-up Timer”. 6.3.1.2.2 SOSC Continuous Operation The SOSC is always enabled when SOSCEN (OSCCON<1>) is set. Leaving the oscillator running at all times allows a fast switch to the 32 kHz system clock for lower power operation. Returning to the faster main oscillator will still require an oscillator start-up time if it is a crystal type source and/or uses the PLL (see 6.3.1.1.2 “Oscillator Start-up Timer”). In addition, the oscillator will need to remain running at all times for Real-Time Clock applications and may be required for Timer1. Refer to Section 14. “Timers” and Section 29. “Real-Time Clock and Calendar” for further details. Example 6-1: Enabling the SOSC SYSKEY = 0x0; SYSKEY = 0xAA996655; SYSKEY = 0x556699AA; OSCCONSET = 2; SYSKEY = 0x0; // ensure OSCCON is locked // Write Key1 to SYSKEY // Write Key2 to SYSKEY // OSCCON is now unlocked // make the desired change // enable SOSC // Relock the SYSKEY // Write any value other than Key1 or Key2 // OSCCON is relocked Preliminary Preliminary DS61112E-page 6-25 PIC32MX Family Reference Manual 6.3.1.3 Internal Fast RC Oscillator (FRC) The FRC oscillator is a fast (8 MHz nominal), user trimmable, internal RC oscillator with user selectable input divider, PLL multiplier, and output divider. See device data sheet for more information about the FRC oscillator. 6.3.1.3.1 FRC Postscaler Mode (FRCDIV) Users are not limited to the nominal 8 MHz FRC output if they wish to use the fast internal oscillator as a clock source. An additional FRC mode, FRCDIV, implements a selectable output divider that allows the choice of a lower clock frequency from 7 different options, plus the direct 8 MHz output. The output divider is configured using the FRCDIV<2:0> bits (OSCCON<26:24>). Assuming a nominal 8 MHz output, available lower frequency options range from 4 MHz (divide-by-2) to 31 kHz (divide-by-256). The range of frequencies allows users the ability to save power at any time in an application by simply changing the FRCDIV bits. The FRCDIV mode is selected whenever the COSC bits (OSCCON<14:12>) are ‘111’. 6.3.1.3.2 FRC Oscillator with PLL Mode (FRCPLL) The output of the FRC may also be combined with a user selectable PLL multiplier and output divider to produce a SYSCLK across a wide range of frequencies. The FRC PLL mode is selected whenever the COSC bits (OSCCON<14:12>) are ‘001’. In this mode the PLL input divider is forced to ‘2’ to provide a 4 MHz input to the PLL. The desired PLL multiplier and output divider values can be chosen to provide the desired device frequency 6.3.1.3.3 Oscillator Tune Register (OSCTUN) The FRC Oscillator Tuning register OSCTUN allows the user to fine tune the FRC oscillator over a range of approximately ±12% (typical). Each bit increment or decrement changes the factory calibrated frequency of the FRC oscillator by a fixed amount. Refer to the Electrical Characteristics section of the specific device data sheet for additional information on the available tuning range. 6.3.1.4 Internal Low-Power RC Oscillator (LPRC) The LPRC oscillator is separate from the FRC. It oscillates at a nominal frequency of 31.25 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail Safe Clock Monitor (FSCM) and PLL reference circuits. It may also be used to provide a low-frequency clock source option for the device in those applications where power consumption is critical, and timing accuracy is not required. 6.3.1.4.1 Enabling the LPRC Oscillator Since it serves the PWRT clock source, the LPRC oscillator is disabled at Power-on Reset whenever the on-board voltage regulator is enabled. After the PWRT expires, the LPRC oscillator will remain on if any one of the following is true: • The Fail-Safe Clock Monitor is enabled. • The WDT is enabled. • The LPRC oscillator is selected as the system clock (COSC2:COSC0 = 100). If none of the above is true, the LPRC will shut off after the PWRT expires. DS61112E-page 6-26 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.3.2 Peripheral Bus Clock (PBCLK) Generation The PBCLK is derived from the System Clock (SYSCLK) divided by PBDIV<1:0> (OSCCON<20:19>). The PBCLK Divisor bits PBDIV<1:0> allow postscalers of 1:1, 1:2, 1:4, and 1:8. Refer to the individual peripheral module section(s) for information regarding which bus a specific peripheral uses. Notes: When the PBDIV divisor is set to a ratio of ‘1:1’ the SYSCLK and PBCLK are equivalent in frequency. The PBCLK frequency is never greater than the processor clock frequency. The effect of changing the PBCLK frequency on individual peripherals should be taken into account when selecting or changing the PBDIV value. Performing back-to-back operations on PBCLK peripheral registers when the PB divisor is not set at 1:1 will cause the CPU to stall for a number of cycles. This stall occurs to prevent an operation from occurring before the pervious one has completed. The length of the stall is determined by the ratio of the CPU and PBCLK and synchronizing time between the two busses. Changing the PBCLK frequency has no effect on the SYSCLK peripherals operation. 6.3.3 USB Clock (USBCLK) generation The USBCLK can be derived from 8MHz internal FRC oscillator, 48MHz POSC, or 96MHz PLL from POSC. For normal operation, the USB module requires exact 48MHz clock. When using 96MHz PLL, the output is internally divided to obtain 48MHz clock. The FRC clock source is used to detect USB activity and bring USB module out of SUSPEND mode. Once USB module is out of SUSPEND mode, it starts using any of two 48MHz clock sources. The internal FRC oscillator is not used for normal USB module operation. 6.3.3.0.1 USB Clock Phase Locked Loop (UPLL) The USB clock PLL provides a user configurable input divider which can be used with the XT, HS and EC primary oscillator modes and with the Internal Fast RC Oscillator (FRC) mode to create a variety of clock frequencies from a clock source. The actual source must be able to provide stable clock as required by the USB specifications. The UPLL enable and Input divider bits are contained in the in the DEVCFG2 device configuration register. The input to the UPLL must be limited to 4MHz only. Appropriate input divider must be selected to ensure that the UPLL input is 4MHz. To configure the UPLL the following steps are required: 1. Enable USB PLL by setting UPLLEN bit in DEVCFG2 register. 2. Based on the source clock, calculate the UPLL input divider value such that the PLL input is 4MHz 3. Set the UPLL input divider UPLLIDIV bits in the DEVCFG2 register when programming the part. 6.3.3.0.2 USB PLL Lock Status The ULOCK bit (OSCCON<6>) is a read-only status bit that indicates the lock status of the USB PLL. It is automatically set after the typical time delay for the PLL to achieve lock, also designated as TULOCK. If the PLL does not stabilize properly during start-up, ULOCK may not reflect the actual status of PLL lock, nor does it detect when the PLL loses lock during normal operation. The ULOCK bit is cleared at a Power-on Reset. It remains clear when any clock source not using the PLL is selected. Refer to the Electrical Characteristics section in the specific device data sheet for further information on the USB PLL lock interval. Preliminary Preliminary DS61112E-page 6-27 PIC32MX Family Reference Manual 6.3.3.0.3 Using Internal FRC Oscillator with USB The internal 8MHz FRC oscillator is available as a clock source to detect any USB activity during USB SUSPEND mode and bring the module out of the SUSPEND mode. To enable FRC for USB usage, the UFRCEN bit (OSCCON<2>) must be set ‘1’ before putting USB module to SUSPEND mode. 6.3.4 Two Speed Start-up Two Speed Start-up mode can be used to reduce the device start-up latency when using all external crystal POSC modes including PLL. Two-Speed Start-up uses the FRC clock as the SYSCLK source until the Primary Oscillator (POSC) has stabilized. After the user selected oscillator has stabilized, the clock source will switch to POSC. This allows the CPU to begin running code, at a lower speed, while the oscillator is stabilizing. When the POSC has met the start-up criteria an automatic clock switch occurs to switch to POSC. This mode is enabled by the device configuration bits FCKSM<1:0> (DEVCFG1<15:14>). Two-Speed Start-up operates after a Power-on Reset (POR) or exit from SLEEP. Software can determine the oscillator source currently in use by reading the COSC<2:0> bits in the OSCCON register. Note: The Watchdog Timer (WDT), if enabled, will continue to count at the same rate regardless of the SYSCLK frequency. Care must be taken to service the WDT during Two-Speed Start-up, taking into account the change in SYSCLK. DS61112E-page 6-28 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.3.5 Fail-Safe Clock Monitor Operation The Fail-Safe Clock Monitor (FSCM) is designed to allow continued device operation if the current oscillator fails. It is intended for use with the Primary Oscillator (POSC) and automatically switches to the FRC oscillator if a POSC failure is detected. The switch to the Fast Internal RC Oscillator (FRC) oscillator allows continued device operation and the ability to retry the POSC or to execute code appropriate for a clock failure. The FSCM mode is controlled by the FCKSM<1:0> bits in the device configuration DEVCFG1. Any of the POSC modes can be used with FSCM. When a clock failure is detected with FSCM enabled and the FSCM Interrupt Enable bit FSCMIE (IEC1<14>) set, the clock source will be switched from POSC to FRC. An Oscillator Fail interrupt will be generated, with the CF bit (OSCCON<3>) set. This interrupt has a user settable priority FSCMIP<2:0> (IPC8<12:10>) and subpriority FSCMIS<1:0> (IPC8<9:8>). The clock source will remain FRC until a device Reset or a clock switch is performed. Failure to enable the FSCM interrupt will not inhibit the actual clock switch. The FSCM module takes the following actions when switching to the FRC oscillator: 1. The COSC bits (OSCCON<14:12>) are loaded with ‘000’. 2. The CF (OSCCON<3>) bit is set to indicate the clock failure 3. The OSWEN control bit (OSCCON<0>) is cleared to cancel any pending clock switches. To enable FSCM the following steps should be performed: 1. Enable the FSCM in the Device Configuration register DEVCFG1 by configuring the FCKSM<1:0> bits. 01 = Clock Switching is enabled, FSCM is disabled 00 = Clock Switching and FSCM are enabled 2. Select the desired mode HS, XT, or EC using FNOSC<2:0> in DEVCFG1. 3. Select POSC as the default oscillator in the device configuration DEVCFG1 by configuring FNOSC<2:0> = 010 without PLL or ‘011’ with PLL. If the PLL is to be used: 1. Select the appropriate Configuration bits for the PLL input divider to scale the input frequency to be between 4 MHz and 5 MHz using FPLLIDIV<2:0> (DEVCFG2<2:0>). 2. Select the desired PLL multiplier using FPLLMULT<2:0> (DEVCFG2<6:4>). 3. Select the desired PLL output divider using FPLLODIV<2:0> (DEVCFG2<18:16>). If a FSCM interrupt is desired when a FSCM event occurs, the following steps should be performed during start-up code: 1. Clear the FSCM interrupt bit FSCMIF (IFS1<14>) 2. Set the Interrupt priority FSCMIP<2:0> (IPC8<12:10>) and subpriority FSCMIS<1:0> (IPC8<9:8>). 3. Set the FSCM Interrupt Enable bit FSCMIE (IEC1<14>) Note: The Watchdog Timer, if enabled, will continue to count at the same rate regardless of the SYSCLK frequency. Care must be taken to service the WDT after a Fail-Safe Clock Monitor event, taking into account the change in SYSCLK. Preliminary Preliminary DS61112E-page 6-29 PIC32MX Family Reference Manual 6.3.5.1 FSCM Delay On a POR, BOR or wake from SLEEP mode event, a nominal delay (TFSCM) may be inserted before the FSCM begins to monitor the system clock source. The purpose of the FSCM delay is to provide time for the oscillator and/or PLL to stabilize when the Power-up Timer (PWRT) is not utilized. The FSCM delay will be generated after the internal System Reset signal, SYSRST, has been released. Refer to Section 7. “Resets” for FSCM delay timing information. The TFSCM interval is applied whenever the FSCM is enabled and the HS, HSPLL, XT, XTPLL, or SOSC Oscillator modes are selected as the system clock. Note: Please refer to the Electrical Characteristics section of the specific device data sheet for TFSCM specification values. 6.3.5.2 FSCM and Slow Oscillator Start-up If the chosen device oscillator has a slow start-up time coming out of POR, BOR or SLEEP mode, it is possible that the FSCM delay will expire before the oscillator has started. In this case, the FSCM will initiate a clock failure trap. As this happens, the COSC bits (OSCCON<14:12>) are loaded with the FRC oscillator selection. This will effectively shut off the original oscillator that was trying to start. Software can detect a clock failure using a Interrupt Service Routine (SFR) or by polling the clock fail interrupt flag FSCMIF (IFS1<14>). 6.3.5.3 FSCM and WDT The FSCM and the WDT both use the LPRC oscillator as their time base. In the event of a clock failure, the WDT is unaffected and continues to run. 6.3.6 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC32MX devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMD Configuration bits in DEVCFG1. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. Note: The device will not permit direct switching between PLL clock sources. The user should not change the PLL multiplier values or postscaler values when running from the affected PLL source. To perform either of the above clock switching functions, the clock switch should be performed in two steps. The clock source should first be switched to a non-PLL source, such as FRC, and then switched to the desired source. This requirement only applies to PLL-based clock sources. 6.3.6.1 Enabling Clock Switching To enable clock switching, the FCKSM1 Configuration bit (DEVCFG1<15>) must be programmed to ‘0’. (Refer to Section 32. “Configuration” for further details.) If the FCKSM1 Configuration bit is unprogrammed (= 1), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSC bits (OSCCON<14:12>) will reflect the clock source selected by the FNOSC Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at ‘0’ at all times. DS61112E-page 6-30 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.3.6.2 Oscillator Switching Sequence At a minimum, performing a clock switch requires the following sequence: 1. If desired, read the COSC<2:0> bits (OSCCON<14:12>) to determine the current oscillator source. 2. Perform the unlock sequence to allow a write to the OSCCON register. The unlock sequence has critical timing requirements and should be performed with interrupts and DMA disabled. 3. Write the appropriate value to the NOSC<2:0> control bits (OSCCON<10:8>) for the new oscillator source. 4. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. 5. Optionally perform the lock sequence to lock the OSCCON. The lock sequence must be performed separately from any other operation. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC<2:0> Status bits with the new value of the NOSC control bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. 2. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the Oscillator Start-up timer (OST) expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). 3. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSC bit values are transferred to the COSC Status bits. 4. The old clock source is turned off at this time if the clock is not being used by any modules. The timing of the transition between clock sources in shown in Figure 6-5. Note: The processor will continue to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. Figure 6-5: Clock Transition Timing Diagram New Source Enabled New Source Stable Old Source Disabled Old Clock Source New Clock Source SYSCLK OSWEN bit Both Oscillators Active Note: The SYSCLK can be any selected source (POSC, SOSC, FRC or LPRC). Preliminary Preliminary DS61112E-page 6-31 PIC32MX Family Reference Manual The following is a recommended code sequence for a clock switch: 1. Disable interrupts and DMA prior to the system unlock sequence. 2. Execute the system unlock sequence by writing the Key values of 0xAA996655 and 0x556699AA to the SYSKEY register in two back-to-back assembly or ‘C’ instructions. 3. Write the new oscillator source value to the NOSC control bits. 4. Set the OSWEN bit in the OSCCON register to initiate the clock switch. 5. Write a non-key value (such as 0x33333333) to the SYSKEY register to perform a lock. Continue to execute code that is not clock-sensitive (optional). 6. Check to see if OSWEN is ‘0’. If it is, the switch was successful. Loop until the bit is ‘0’. 7. Re-enable interrupts and DMA. Notes: There are no timing requirements for the steps other than the initial back-to-back writing of the Key values to perform the unlock sequence. The unlock sequence unlocks all registers that are secured by the lock function. It is recommended that amount to time is the system is unlock is kept to a minimum. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 6-2. 6.3.6.3 Clock Switching Considerations When incorporating clock switching into an application, users should keep certain things in mind when designing their code. • The SYSLOCK unlock sequence is timing critical. The two Key values must be written back-to-back with no in-between peripheral register access. To prevent unintended peripheral register accesses, it is recommended that all interrupts and DMA transfers are disbaled. • The system will not relock automatically. The user should perform the relock sequence as soon after the clock switch as is possible. • The unlock sequence unlocks other registers such as the those related to Real-Time Clock control. • If the destination clock source is a crystal oscillator, the clock switch time will be dictated by the oscillator start-up time. • If the new clock source does not start, or is not present, the OSWEN bit remain set. • A clock switch to a different frequency will affect the clocks to peripherals. Peripherals may require reconfiguration to continue operation at the same rate as they did before the clock switch occurred. • If the new clock source uses the PLL, a clock switch will not occur until lock has been achieved. • If the WDT is used, care must be taken to ensure it can be serviced in a timely manner at the new clock rate. Note: The application should not attempt to switch to a clock with a frequency lower than 100 kHz when the Fail-Safe Clock Monitor is enabled. Clock switching in these instances may generate a false oscillator fail event and result in a switch to the Internal Fast RC oscillator. Note: The device will not permit direct switching between PLL clock sources. The user should not change the PLL multiplier values or postscaler values when running from the affected PLL source. To perform either of the above clock switching functions, the clock switch should be performed in two steps. The clock source should first be switched to a non-PLL source, such as FRC, and then switched to the desired source. This requirement only applies to PLL-based clock sources. DS61112E-page 6-32 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.3.6.4 Aborting a Clock Switch In the event the clock switch did not complete, the clock switch logic can be reset by clearing the OSWEN bit (OSCCON<0>). This will abandon the clock switch process, stop and reset the Oscillator Start-up Timer (OST) (if applicable) and stop the PLL (if applicable). A clock switch procedure can be aborted at any time. A clock switch that is already in progress can also be aborted by performing a second clock switch. Example 6-2: Performing a Clock Switch configuration SYSKEY = 0x0; SYSKEY = 0xAA996655; SYSKEY = 0x556699AA; OSCCONCLR = 7 << 8; OSCCONSET = 7 << 8; OSCCONSET = 1; SYSKEY = 0x0; // note: clock switching must be enabled in the device // write invalid key to force lock // Write Key1 to SYSKEY // Write Key2 to SYSKEY // OSCCON is now unlocked // make the desired change // clear the clock select bits // set the new clock source to FRC // request clock switch // Relock the SYSKEY // Write any value other than Key1 or Key2 // OSCCON is relocked 6.3.6.5 Entering SLEEP Mode During a Clock Switch If the device enters SLEEP mode during a clock switch operation, the clock switch operation is not aborted. If the clock switch does not complete before entering Sleep mode it will perform the switch when exiting Sleep. The WAIT instruction is then executed normally. 6.3.7 Real-Time Clock Oscillator To provide accurate timekeeping the Real-Time Clock and Calendar (RTCC) requires a precise time base. To achieve this requirement the Secondary Oscillator (SOSC) is used as the time base for the RTCC. The SOSC uses an external 32.768 kHz crystal connected to the SOSCI and SOSCO pins. 6.3.7.1 SOSC Control The SOSC can be used by modules other than the RTCC, therefore, the SOSC is controlled by a combination of software and hardware. Setting the SOSCEN bit (OSCCON<1>) to a ‘1’ enables the SOSC. The SOSC is disabled when it is not being used by the CPU module and the SOSCEN bit is ‘0’. If the SOSC is being used as SYSCLK, such as after a clock switch, it cannot be disabled by writing to the SOSCEN bit. If the SOSC is enabled by the SOSCEN bit, it will continue to operate when the device is in SLEEP. To prevent inadvertent clock changes the OSCCON register is locked. It must be unlocked prior to software enabling or disabling the SOSC. Notes: If the RTCC is to be used when the CPU clock source is to be switched between SOSC and another clock source the SOSCEN bit should be set to a ‘1’ in software. Failure to set the bit will cause the SOSC to be disabled when the CPU is switched to another clock source. Due to the start-up time for an external crystal the user should wait for stable SOCSC oscillator output before enabling the RTCC. This typically requires a 32 ms delay between enabling the SOSC and enabling the RTCC. The actual time required will depend on the crystal in use and the application. There are numerous system and peripheral registers that are protected from inadvertent writes by the SYSREG lock. Performing a lock or unlock affects all registers protected by SYSREG including OSCCON. Preliminary Preliminary DS61112E-page 6-33 PIC32MX Family Reference Manual 6.3.8 Timer1 External Oscillator The Timer1 module has the ability to use the SOSC as a clock source to increment Timer1. The SOSC is designed to use an external 32.768 kHz crystal connected to the SOSCI and SOSCO pins. 6.3.8.1 SOSC Control The SOSC can be used by modules other than Timer1, therefore, the SOSC is controlled by a combination of software and hardware. Setting the SOSCEN bit (OSCCON<1>) to a ‘1’ enables the SOSC. The SOSC is disabled when it is not being used by the CPU module and the SOSCEN bit is ‘0’. If the SOSC is being used as SYSCLK, such as after a clock switch, it cannot be disabled by writing to the SOSCEN bit. If the SOSC is enabled by the SOSCEN bit, it will continue to operate when the device is in SLEEP. To prevent inadvertent clock changes the OSCCON register is locked. It must be unlocked prior to software enabling or disabling the SOSC. Notes: If the TIMER1 is to be used when the CPU clock source is to be switched between SOSC and another clock source, the SOSCEN bit should be set to a ‘1’ in software. Failure to set the bit will cause the SOSC to be disabled when the CPU is switched to another clock source. Due to the start-up time for an external crystal the user should wait for stable SOCSC oscillator output before attempting to use Timer1 for accurate measurements. This typically requires a 10 ms delay between enabling the SOSC and use of Timer1. The actual time required will depend on the crystal in use and the application. There are numerous system and peripheral registers that are protected from inadvertent writes by the SYSREG lock. Performing a lock or unlock affects all registers protected by SYSREG including OSCCON. DS61112E-page 6-34 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.4 INTERRUPTS The only interrupt generated by the oscillator module is the Fail-Safe Clock Monitor (FSCM) event interrupt. When the FSCM mode is enabled and the corresponding interrupts have been configured, a FSCM event will generate a interrupt. This interrupt has both priority and subpriorities that must be configured. 6.4.1 Interrupt Operation The FSCM has a dedicated interrupt bit FSCMIF (IFS1<14>) and a corresponding interrupt enable/mask bit FSCMIE (IEC1<14>). These bits are used to determine the source of an interrupt and to enable or disable an individual interrupt source. The priority level of the FSCM can be set independently of other interrupt sources. The FSCMIF bit is set when a FSCM detects a POSC clock failure. The FSCMIF bit will then be set without regard to the state of the corresponding FSCMIE bit. The FSCMIF bit can be polled by software if desired. The FSCMIE bit controls the interrupt generation. If the FSCMIE bit is set, the CPU will be interrupted whenever an FSCM event occurs (subject to the priority and subpriority as outlined below). The FSCMIF bit will be set regardless of interrupt priority. It is the responsibility of the routine that services a particular interrupt to clear the appropriate Interrupt Flag bit before the service routine is complete. The priority of the FSCM interrupt can be set independently via the FSCMIP<2:0> bits (IPC8<20:18>). This priority defines the priority group that interrupt source will be assigned to. The priority groups range from a value of 7, the highest priority, to a value of 0, which does not generate an interrupt. An interrupt being serviced will be preempted by an interrupt in a higher priority group. The subpriority bits allow setting the priority of a interrupt source within a priority group. The values of the subpriority, FSCMIS<1:0> (IPC8<8:9>), range from 3, the highest priority, to 0 the lowest priority. An interrupt with the same priority group but having a higher subpriority value will preempt a lower subpriority interrupt that is in progress. The priority group and subpriority bits allow more than one interrupt source to share the same priority and subpriority. If simultaneous interrupts occur in this configuration, the natural order of the interrupt sources within a priority/subgroup pair determine the interrupt generated. The natural priority is based on the vector numbers of the interrupt sources. The lower the vector number the higher the natural priority of the interrupt. Any interrupts that were overridden by natural order will then generate their respective interrupts based on priority, subpriority, and natural order after the interrupt flag for the current interrupt is cleared. After an enabled interrupt is generated, the CPU will jump to the vector assigned to that interrupt (refer to Table 6-5). The vector number for the interrupt is the same as the natural order number. The IRQ number is not always the same as the vector number due to some interrupts sharing a single vector. The CPU will then begin executing code at the vector address. The users code at this vector address should perform an operations required, such as reloading the duty cycle, clear the interrupt flag, and then exit. Refer to Section 8. “Interrupts” for the vector address table details and for more information on interrupts. Table 6-5: FSCM Interrupt Vectors for Various Offsets with EBASE = 0x8000:0000 Interrupt Vector/Natural Order IRQ Number Vector Address IntCtl.VS = 0x01 Vector Address IntCtl.VS = 0x02 Vector Address IntCtl.VS = 0x04 Vector Address IntCtl.VS = 0x08 FSCM 33 45 8000 0620 8000 0A40 8000 1280 8000 2300 Vector Address IntCtl.VS = 0x10 8000 4400 Preliminary Preliminary DS61112E-page 6-35 PIC32MX Family Reference Manual Example 6-3: FSCM Interrupt Configuration // FSCM must be enabled in the device configuration if ( OSCCON & 0x8000 ) { start-up } else { IPC8CLR = 0x1F << 16; IPC8SET = 7 << 18; IPC8SET = 3 << 16; IFS1CLR = 1 << 24; IEC1SET = 1 << 24; } // Setup the FSCM interrupt // located in the users start-up code // check for a FSCM during start-up // user handler for a FSCM event occurred during // normal start-up // clear the FSCM priority bits // set the FSCM interrupt priority // set the FSCM interrupt subpriority // clear the FSCM interrupt bit // Enable the FSCM interrupt void __ISR(_FAIL_SAFE_MONITOR_VECTOR, ipl7) FSCM_HANDLER(void) { // interrupt handler // Insert user code here IFS1CLR = 1 << 3; // Clear the CMP2 interrupt flag } DS61112E-page 6-36 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.5 INPUT/OUTPUT PINS The pins used by the POSC and SOSC are shared by other peripherals modules. Table shows the function of these shared pins in the available oscillator modes. When the pins are not used by a oscillator they are available for use as general I/O pins or by use by a peripheral sharing the pin. Refer to Section 29. “Real-Time Clock and Calendar” and Section 9. “Watchdog Timer and Power-up Timer” for more information. Table 6-6: Pin Name Configuration of Pins Associated with the Oscillator Module Clock Mode Configuration Bit FIeld(1) TRIS Pin Type OSCI HS, HSPLL, XT, XTPLL COSC<2:0>, POSCMD<1:0> X OSC OSCO HS, HSPLL, XT, XTPLL COSC<2:0>, POSCMD X OSC OSCI EC, ECPLL COSC<2:0>, POSCMD X CLOCK IN OSCO EC, ECPLL COSC<2:0>, POSCMD, OSCOFNC X PBCLK OUT OSCO EC, ECPLL COSC<2:0>, POSCMD, OSCOFNC INPUT INPUT OSCO EC, ECPLL COSC<2:0>, POSCMD, OSCOFNC OUTPUT OUTPUT N/A FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC COSC<2:0> X GPIO N/A FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC COSC<2:0> X GPIO N/A FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC COSC<2:0> X GPIO N/A FRC, FRCPLL, FRCDIV16, FRCDIV, LPRC COSC<2:0> X GPIO SOSCI SOSC COSC<2:0> X OSC SOSCO SOSC COSC<2:0> X OSC Note 1: During device start-up, the Device Oscillator configuration data is copied from device configuration to COSC. 6.5.1 OSCI and OSCO Pin Functions in Non-External Oscillator Modes When the primary oscillator (POSC) on OSCI and OSCO is not configured as a clock source the OSCI pin is automatically reconfigured as a digital I/O. In this configuration, as well as when the primary oscillator is configured for EC mode (POSCMD1:POSCMD0 = 00), the OSCO pin can also be configured as a digital I/O by programming the OSCIOFCN Configuration bit. When OSCIOFCN is unprogrammed (‘1’), a PBCLK is available on OSCO for testing or synchronization purposes. With OSCIOFCN programmed (‘0’), the OSCO pin becomes a general purpose I/O pin. In both of these configurations, the feedback device between OSCI and OSCO is turned off to save current. 6.5.2 SOSCI and SOCI Pin Functions in Non-External Oscillator Modes When the secondary oscillator (SOSC) on SOSCI and SOSCO pin is not configured as a clock source the pins are automatically reconfigured as a digital I/O. Preliminary Preliminary DS61112E-page 6-37 PIC32MX Family Reference Manual 6.6 OPERATION IN POWER-SAVING MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 6.6.1 Oscillator Operation in SLEEP Mode Clock sources are disabled in SLEEP unless they are being used by a peripheral. The following sub-sections outline the behavior of each of the clock sources in SLEEP. 6.6.1.1 POSC The Primary Oscillator POSC is always disabled in SLEEP. Start-up delays apply when exiting SLEEP. 6.6.1.2 SOSC The Secondary Oscillator is disabled in SLEEP unless the SOSCEN bit is set or it is in use by an enabled module that operates in SLEEP. Start-up delays apply when exiting SLEEP if the secondary oscillator is not already running. 6.6.1.3 FRC The Fast RC (FRC) oscillator is disabled in SLEEP. 6.6.1.4 LPRC The Low-Power RC oscillator is disabled in SLEEP if the Watchdog Timer (WDT) is disabled. 6.6.2 Oscillator Operation in IDLE Mode Clock sources are not disabled in IDLE mode. Start-up delays do not apply when exiting Idle mode. 6.6.3 Oscillator Operation in DEBUG Mode The Oscillator module continues to operate while the device is in DEBUG mode. Note: There is no FRZ mode for this module. DS61112E-page 6-38 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.7 EFFECTS OF VARIOUS RESETS On all forms of Device Reset OSCCON is set to the default value and the COSC<2:0>, PLLIDIV<2:0>, and PLLMULT<2:0>, and UPLLIDIV<2:0> values are forced to the values defined in the DEVCFG1 and DEVCFG2 Device Configuration Registers. The Oscillator source is transferred to the source as defined in the DEVCFG1 register. Oscillator start-up delays will apply. 6.8 DESIGN TIPS Figure 6-6: 6.8.1 Crystal Oscillators and Ceramic Resonators In HS and XT modes, a crystal or ceramic resonator is connected to the OSCI and OSCO pins to establish oscillation (Figure 6-2). The PIC32MX oscillator design requires the use of a parallel cut crystal. Using a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. In general, users should select the oscillator option with the lowest possible gain that still meets their specifications. This will result in lower dynamic currents (IDD). The frequency range of each oscillator mode is the recommended frequency cutoff, but the selection of a different gain mode is acceptable as long as a thorough validation is performed (voltage, temperature and component variations, such as resistor, capacitor and internal oscillator circuitry). 6.8.2 Oscillator/Resonator Start-up As the device voltage increases from VSS, the oscillator will start its oscillations. The time required for the oscillator to start oscillating depends on many factors, including: • Crystal/resonator frequency • Capacitor values used • Series resistor, if used, and its value and type • Device VDD rise time • System temperature • Oscillator mode selection of device (selects the gain of the internal oscillator inverter) • Crystal quality • Oscillator circuit layout • System noise The course of a typical crystal or resonator start-up is shown in Figure 6-6. Notice that the time to achieve stable oscillation is not instantaneous. Refer to the Electrical Characteristics section in the specific device data sheet for further information regarding frequency range for each crystal mode. Example of Oscillator/Resonator Start-up Characteristics Maximum VDD of System VIH Device VDD Voltage VIL 0V Crystal Start-up Time Time Preliminary Preliminary DS61112E-page 6-39 PIC32MX Family Reference Manual 6.8.3 Tuning the Oscillator Circuit Since Microchip devices have wide operating ranges (frequency, voltage and temperature; depending on the part and version ordered) and external components (crystals, capacitors, etc.) of varying quality and manufacture, validation of operation needs to be performed to ensure that the component selection will comply with the requirements of the application. There are many factors that go into the selection and arrangement of these external components. Depending on the application, these may include any of the following: • Amplifier gain • Desired frequency • Resonant frequency(s) of the crystal • Temperature of operation • Supply voltage range • Start-up time • Stability • Crystal life • Power consumption • Simplification of the circuit • Use of standard components • Component count 6.8.3.1 Determining the Best Values for Oscillator Components The best method for selecting components is to apply a little knowledge and a lot of trial measurement and testing. Crystals are usually selected by their parallel resonant frequency only; however, other parameters may be important to your design, such as temperature or frequency tolerance. Microchip application note AN588, “PICmicro® Microcontroller Oscillator Design Guide” is an excellent reference to learn more about crystal operation and ordering information. The PIC32MX internal oscillator circuit is a parallel oscillator circuit which requires that a parallel resonant crystal be selected. The load capacitance is usually specified in the 22 pF to 33 pF range. The crystal will oscillate closest to the desired frequency with a load capacitance in this range. It may be necessary to alter these values, as described later, in order to achieve other benefits. The Clock mode is primarily chosen based on the desired frequency of the crystal oscillator. The main difference between the XT and HS Oscillator modes is the gain of the internal inverter of the oscillator circuit which allows the different frequency ranges. In general, use the oscillator option with the lowest possible gain that still meets specifications. This will result in lower dynamic currents (IDD). The frequency range of each oscillator mode is the recommended frequency cutoff, but the selection of a different gain mode is acceptable as long as a thorough validation is performed (voltage, temperature and component variations, such as resistor, capacitor and internal oscillator circuitry). C1 and C2 should also be initially selected based on the load capacitance, as suggested by the crystal manufacturer, and the tables supplied in the device data sheet. The values given in the device data sheet can only be used as a starting point since the crystal manufacturer, supply voltage, PCB layout and other factors already mentioned may cause your circuit to differ from the one used in the factory characterization process. Ideally, the capacitance is chosen so that it will oscillate at the highest temperature and the lowest VDD that the circuit will be expected to perform under. High temperature and low VDD both have a limiting effect on the loop gain, such that if the circuit functions at these extremes, the designer can be more assured of proper operation at other temperatures and supply voltage combinations. The output sine wave should not be clipped in the highest gain environment (highest VDD and lowest temperature) and the sine output amplitude should be large enough in the lowest gain environment (lowest VDD and highest temperature) to cover the logic input requirements of the clock as listed in the device data sheet. DS61112E-page 6-40 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 A method for improving start-up is to use a value of C2 that is greater than the value of C1. This causes a greater phase shift across the crystal at power-up which speeds oscillator start-up. Besides loading the crystal for proper frequency response, these capacitors can have the effect of lowering loop gain if their value is increased. C2 can be selected to affect the overall gain of the circuit. A higher C2 can lower the gain if the crystal is being overdriven (also, see discussion on Rs). Capacitance values that are too high can store and dump too much current through the crystal, so C1 and C2 should not become excessively large. Unfortunately, measuring the wattage through a crystal is difficult, but if you do not stray too far from the suggested values you should not have to be concerned with this. A series resistor, Rs, is added to the circuit if, after all other external components are selected to satisfaction, the crystal is still being overdriven. This can be determined by looking at the OSCO pin, which is the driven pin, with an oscilloscope. Connecting the probe to the OSCI pin will load the pin too much and negatively affect performance. Remember that a scope probe adds its own capacitance to the circuit, so this may have to be accounted for in your design (i.e., if the circuit worked best with a C2 of 22 pF and the scope probe was 10 pF, a 33 pF capacitor may actually be called for). The output signal should not be clipping or flattened. Overdriving the crystal can also lead to the circuit jumping to a higher harmonic level, or even, crystal damage. The OSCO signal should be a clean sine wave that easily spans the input minimum and maximum of the clock input pin. An easy way to set this is to again test the circuit at the minimum temperature and maximum VDD that the design will be expected to perform in, then look at the output. This should be the maximum amplitude of the clock output. If there is clipping, or the sine wave is distorted near VDD and VSS, increasing load capacitors may cause too much current to flow through the crystal or push the value too far from the manufacturer’s load specification. To adjust the crystal current, add a trimmer potentiometer between the crystal inverter output pin and C2 and adjust it until the sine wave is clean. The crystal will experience the highest drive currents at the low temperature and high VDD extremes. The trimmer potentiometer should be adjusted at these limits to prevent overdriving. A series resistor, Rs, of the closest standard value can now be inserted in place of the trimmer. If Rs is too high, perhaps more than 20 kΩ, the input will be too isolated from the output, making the clock more susceptible to noise. If you find a value this high is needed to prevent overdriving the crystal, try increasing C2 to compensate or changing the Oscillator Operating mode. Try to get a combination where Rs is around 10 kΩ or less and load capacitance is not too far from the manufacturer’s specification. Preliminary Preliminary DS61112E-page 6-41 PIC32MX Family Reference Manual 6.8.4 FAQs Question 1: When looking at the OSCO pin after power-up with an oscilloscope, there is no clock. What can cause this? Answer: There are several possible causes: 1. Entering SLEEP mode with no source for wake-up (such as WDT, MCLR or an interrupt). Verify that the code does not put the device to SLEEP without providing for wake-up. If it is possible, try waking it up with a low pulse on MCLR. Powering up with MCLR held low will also give the crystal oscillator more time to start-up, but the Program Counter will not advance until the MCLR pin is high. 2. The wrong clock mode is selected for the desired frequency. For a blank device, the default oscillator is FRC. Most parts come with the clock selected in the Default mode which will not start oscillation with a crystal or resonator. Verify that the clock mode has been programmed correctly. 3. The proper power-up sequence has not been followed. If a CMOS part is powered through an I/O pin prior to power-up, bad things can happen (latch-up, improper start-up, etc.). It is also possible for brown-out conditions, noisy power lines at start-up and slow VDD rise times to cause problems. Try powering up the device with nothing connected to the I/O, and power-up with a known, good, fast rise power supply. Refer to the power-up information in the specific device data sheet for considerations on brown-out and power-up sequences. 4. The C1 and C2 capacitors attached to the crystal have not been connected properly or are not the correct values. Make sure all connections are correct. The device data sheet values for these components will usually get the oscillator running; however, they just might not be the optimal values for your design. Question 2: Why does my device run at a frequency much higher than the resonant frequency of the crystal? Answer: The gain is too high for this oscillator circuit. Refer to 6.8.3.1 “Determining the Best Values for Oscillator Components” to aid in the selection of C2 (may need to be higher), Rs (may be needed) and Clock mode (wrong mode may be selected). This is especially possible for low-frequency crystals, like the common 32.768 kHz. Question 3: The design runs fine, but the frequency is slightly off. What can be done to adjust this? Answer: Changing the value of C1 has some effect on the oscillator frequency. If a series resonant crystal is used, it will resonate at a different frequency than a parallel resonant crystal of the same frequency call-out. Ensure that you are using a parallel resonant crystal. Question 4: What would cause my application to work fine, but then suddenly quit or lose time? Answer: Other than the obvious software checks that should be done to investigate losing time, it is possible that the amplitude of the oscillator output is not high enough to reliably trigger the oscillator input. Also, look at the C1 and C2 values and ensure that the device Configuration bits are correct for the desired oscillator mode. Question 5: If I put an oscilloscope probe on an oscillator pin, I don’t see what I expect. Why? Answer: Remember that an oscilloscope probe has capacitance. Connecting the probe to the oscillator circuitry will modify the oscillator characteristics. Consider using a low capacitance (active) probe. DS61112E-page 6-42 Preliminary © 2008 Microchip Technology Inc. Oscillators Section 6. Oscillators 6 6.9 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Oscillator module are: Title Application Note # Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® MCU Devices AN826 Basic PIC® Microcontroller Oscillator Design AN849 Practical PIC® Microcontroller Oscillator Analysis and Design AN943 Making Your Oscillator Work AN949 Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. Preliminary Preliminary DS61112E-page 6-43 PIC32MX Family Reference Manual 6.10 REVISION HISTORY Revision A (October 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revise U-0 to r-x; Revise Figure 6-1. Revision D (May 2008) Revised Figure 6-1, Table 6-1 (WDTCON); Revised Registers 6-9, 6-13, 6-14, 6-15; Revised Example 6-3; Change Reserved bits from “Maintain as” to “Write”; Added Note to ON bit (WDTCON Register). Revision E (July 2008) Revised Figure 6-1; Examples 6-1, 6-2, 6-3. DS61112E-page 6-44 Preliminary © 2008 Microchip Technology Inc. Section 7. Resets HIGHLIGHTS This section of the manual contains the following topics: 7 7.1 Introduction................................................................................................................ 7-2 7.2 Control Registers....................................................................................................... 7-3 7.3 Modes of Operation ................................................................................................... 7-9 7.4 Effects of Various Resets......................................................................................... 7-12 7.5 Design Tips .............................................................................................................. 7-14 7.6 Related Application Notes ....................................................................................... 7-15 7.7 Revision History....................................................................................................... 7-16 Resets © 2008 Microchip Technology Inc. Preliminary DS61118E-page 7-1 PIC32MX Family Reference Manual 7.1 INTRODUCTION The Resets module combines all Reset sources and controls the system Reset signal SYSRST. The following is a list of device Reset sources: • POR: Power-on Reset • MCLR: Pin Reset • SWR: Software Reset • WDTR: Watchdog Timer Reset • BOR: Brown-out Reset • CMR: Configuration Mismatch Reset A simplified block diagram of the Reset module is shown in Figure 7-1. Any active source of Reset will make the system Reset signal active. Many registers associated with the CPU and peripherals are forced to a known “Reset state”. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. Note: Refer to the specific peripheral or the CPU section of this manual for register Reset states. Figure 7-1: System Reset Block Diagram MCLR Glitch Filter SLEEP or IDLE Voltage Regulator Enabled VDD WDT Time-Out VDD Rise Detect Power-up Timer Configuration Mismatch Reset Software Reset Brown-out Reset MCLR WDTR POR BOR CMR SWR SYSRST DS61118E-page 7-2 Preliminary © 2008 Microchip Technology Inc. Section 7. Resets 7.2 CONTROL REGISTERS All types of device Resets will set corresponding Status bits in the RCON register to indicate the type of Reset (see Register 7-1). A Power-on Reset will clear all bits, except for the BOR and POR bits (RCON<1:0>), which are set. The user may set or clear any of the bits at any time during code execution. The RCON bits serve only as Status bits. Setting a particular Reset Status bit in software will not cause a system Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. For more information on the function of these bits, refer to Section 7.4.3 “Using the RCON Status Bits”. The RSWRST control register has only one bit, SWRST. This bit is used to force a software Reset condition. The Resets module consists of the following Special Function Registers (SFRs): • RCON: Control register for Resets RCONCLR, RCONSET, RCONINV: Atomic Bit Manipulation Write-only Registers for RCON • RSWRST: Data Register for Resets RSWRSTCLR, RSWRSTSET, RSWRSTINV: Atomic Bit Manipulation Write-only Registers for RSWRST The following table summarizes all Resets-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Table 7-1: Reset SFR Summary Name Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 RCON 31:24 23:16 15:8 7:0 RCONCLR 31:0 RCONSET 31:0 RCONINV 31:0 RSWRST 31:24 23:16 15:8 7:0 RSWRSTCLR 31:0 RSWRSTSET 31:0 RSWRSTINV 31:0 — — — EXTR — — — — — — — — — — — — — — — — — — — — — CMR SWR — WDTO SLEEP IDLE BOR Write clears selected bits in RCON, read yields undefined value Write sets selected bits in RCON, read yields undefined value Write inverts selected bits in RCON, read yields undefined value — — — — — — — — — — — — — — — — — — — — — — — — Write clears selected bits in RSWRST, read yields undefined value Write sets selected bits in RSWRST, read yields undefined value Write inverts selected bits in RSWRST, read yields undefined value Bit 24/16/8/0 — — VREGS POR — — — SWRST Resets 170 © 2008 Microchip Technology Inc. Preliminary DS61118E-page 7-3 PIC32MX Family Reference Manual Register 7-1: RCON: Reset Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 r-x r-x r-x r-x r-x r-0 R/W-0 R/W-0 — — — — — — CMR VREGS bit 15 bit 8 R/W-0 R/W-0 r-x R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR — WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Reserved: Write ‘0’; ignore read Reserved: Write ‘0’; ignore read CMR: Configuration Mismatch Reset Flag bit 1 = Configuration mismatch Reset has occurred 0 = Configuration mismatch Reset has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. VREGS: Voltage Regulator Standby Enable bit 1 = Regulator is enabled and is on during SLEEP mode 0 = Regulator is disabled and is off during SLEEP mode EXTR: External Reset (MCLR) Pin Flag bit 1 = Master Clear (pin) Reset has occurred 0 = Master Clear (pin) Reset has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. SWR: Software Reset Flag bit 1 = Software Reset was executed 0 = Software Reset as not executed Note: This bit is set in hardware, it can only be cleared (= 0) in software. Reserved: Write ‘0’; ignore read WDTO: Watchdog Timer Time-out Flag bit 1 = WDT Time-out has occurred 0 = WDT Time-out has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. SLEEP: Wake From SLEEP Flag bit 1 = Device was in SLEEP mode 0 = Device was not in SLEEP mode Note: This bit is set in hardware, it can only be cleared (= 0) in software. IDLE: Wake From IDLE Flag bit 1 = Device was in IDLE mode 0 = Device was not in IDLE mode Note: This bit is set in hardware, it can only be cleared (= 0) in software. DS61118E-page 7-4 Preliminary © 2008 Microchip Technology Inc. Section 7. Resets Register 7-1: RCON: Reset Control Register bit 1 BOR: Brown-out Reset Flag bit User software must clear this bit to view next detection. 1 = Brown-out Reset has occurred 0 = Brown-out Reset has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. bit 0 POR: Power-on Reset Flag bit User software must clear this bit to view next detection. 1 = Power-on Reset has occurred 0 = Power-on Reset has not occurred Note: This bit is set in hardware, it can only be cleared (= 0) in software. 170 Resets © 2008 Microchip Technology Inc. Preliminary DS61118E-page 7-5 PIC32MX Family Reference Manual Register 7-2: RCONCLR: RCON Clear Register Write clears selected bits in RCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in RCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in RCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RCONCLR = 0x00008001 will clear bits 15 and 5 in RCON register. Register 7-3: RCONSET: RCON Set Register Write sets selected bits in RCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in RCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in RCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RCONSET = 0x00008001 will set bits 15 and 5 in RCON register. Register 7-4: RCONINV: RCON Invert Register Write inverts selected bits in RCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in RCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in RCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RCONINV = 0x00008001 will invert bits 15 and 5 in RCON register. DS61118E-page 7-6 Preliminary © 2008 Microchip Technology Inc. Section 7. Resets Register 7-5: RSWRST: Software Reset Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-x W-0 — — — — — — — SWRST bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-1 bit 0 Note: Reserved: Write ‘0’; ignore read SWRST: Software Reset Trigger bit 1 = Enable software Reset event 0 = No effect The system unlock sequence must be performed before the SWRST bit can be written. See 7.3.4 “Software Reset (SWR)”. Resets 170 © 2008 Microchip Technology Inc. Preliminary DS61118E-page 7-7 PIC32MX Family Reference Manual Register 7-6: RSWRSTCLR: RSWRST Clear Register Write clears selected bits in RSWRST, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in RSWRST A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in RSWRST register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RSWRSTCLR = 0x00008001 will clear bits 15 and 5 in RSWRST register. Register 7-7: RSWRSTSET: RSWRST Set Register Write sets selected bits in RSWRST, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in RSWRST A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in RSWRST register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RSWRSTSET = 0x00008001 will set bits 15 and 5 in RSWRST register. Register 7-8: RSWRSTINV: RSWRST Invert Register Write inverts selected bits in RSWRST, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in RSWRST A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in RSWRST register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RSWRSTINV = 0x00008001 will invert bits 15 and 5 in RSWRST register. DS61118E-page 7-8 Preliminary © 2008 Microchip Technology Inc. Section 7. Resets 7.3 MODES OF OPERATION 7.3.1 System Reset The PIC32MX Internal System Reset (SYSRST) can be generated from multiple Reset sources, such as POR (Power-on Reset), BOR (Brown-out Reset), MCLR (Master Clear Reset), WDTO (Watchdog Time-out Reset), SWR (Software Reset) and CMR (Configuration Mis-match Reset). A system Reset is active at first POR and asserted until device configuration settings are loaded and the clock oscillator sources become stable. The system Reset is then de-asserted allowing the CPU to start fetching code after 8 system clock cycles (SYSCLK). BOR, MCLR and WDTO Resets are asynchronous events and to avoid SFR (Special Function Register) and RAM corruptions, the system Reset is synchronized with the system clock. All other Reset events are synchronous. 170 Resets 7.3.2 Power-on Reset (POR) A power-on event generates an internal Power-on Reset pulse when a VDD rise is detected above VPOR. The device supply-voltage-characteristics must meet the specified starting-voltage and rise-rate requirements to generate the POR pulse. In particular, VDD must fall below VPOR before a new POR is initiated. For more information on the VPOR and VDD rise-rate specifications, refer to the Electrical Characteristics section of the specific device data sheet for details. For those PIC32MX variants that have the on-chip voltage regulator enabled, the Power-up Timer (PWRT) is automatically disabled. For those PIC32MX variants that have the on-chip voltage regulator disabled, the core is supplied from an external power supply and the Power-up Timer is automatically enabled and is used to extend the duration of a power-up sequence. The PWRT adds a fixed 64 ms nominal delay at device start-up. Hence, the Power-on delay can either be the on-chip voltage regulator output delay, designated as TPU, or the power-up timer delay, designated as TPWRT. At this point the POR event has expired, but the device Reset is still asserted while device configuration settings are loaded and the clock oscillator sources are configured and the clock monitoring circuitry waits for the oscillator source to become stable. The clock source used by the PIC32MX device when exiting from Reset is always selected from the FNOSC<2:0> bits in the DEVCFG1 Configuration Word. This additional delay depends on the clock and can include delays for TOSC, TLOCK and TFSCM. For details on the oscillator, PLL and Fail-Safe clock monitoring, refer to Section 6.3.5 “Fail-Safe Clock Monitor Operation”. After these delays expire, the system Reset SYSRST is de-asserted. Before allowing the CPU to start code execution, 8 system clock cycles are required before the synchronized Reset to the CPU core is de-asserted. The power-on event sets the BOR and POR Status bits (RCON<1:0>). Refer to the Electrical Characteristics section of the specific device data sheet for more information on the values of the delay parameters. Note: When the device exits the Reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device will not function correctly. The user must ensure that the delay between the time power is first applied and the time system Reset is released is long enough to get all operating parameters within specification. © 2008 Microchip Technology Inc. Preliminary DS61118E-page 7-9 PIC32MX Family Reference Manual 7.3.3 MCLR Reset Whenever the MCLR pin is driven low, the Reset event is synchronized with the system clock SYSCLK before asserting the system Reset SYSRST, provided the input pulse on MCLR is longer than a certain minimum width, as specified in the Electrical Characteristics section of the specific device data sheet for details. MCLR provides a filter to minimize the effects of noise and to avoid unwanted Reset events. The EXTR Status bit (RCON<7>) is set to indicate the MCLR Reset. 7.3.4 Software Reset (SWR) The PIC32MX CPU core doesn’t provide a specific RESET “instruction”; however, a hardware Reset can be performed in software (Software Reset) by executing a software Reset-command sequence. The software Reset command acts like a MCLR Reset. The software Reset sequence requires the system unlock sequence to be executed before the SWRST bit can be written. Refer to Section 6.3.6 “Clock Switching Operation” regarding the system unlock details. A software Reset is performed as follows: • Write the system unlock sequence • Set bit SWRST (RSWRST<0>) = 1 • Read the RSWRST register • Follow with “while(1);” or 4 “NOP” instructions Writing a ‘1’ to RSWRST register sets bit SWRST, arming the software Reset. The subsequent read of the RSWRST register triggers the software Reset, which should occur on the next clock cycle following the read operation. To ensure no other user code is executed before the Reset event occurs, it is recommended that 4 ‘NOP’ instructions or a “while(1);” statement be placed after the READ instruction. The SWR Status bit (RCON<6>) is set to indicate the Software Reset. Example 7-1: Software Reset Command Sequence /* The following code illustrates a software Reset */ /* perform a system unlock sequence */ SYSTEMUnlock(); /* set SWRST bit to arm reset */ RSWRSTSET = 1; /* read RSWRST register to trigger reset */ volatile int* p = &RSWRST; *p; /* prevent any unwanted code execution until reset occurs*/ while(1); DS61118E-page 7-10 Preliminary © 2008 Microchip Technology Inc. Section 7. Resets 7.3.5 Watchdog Timer Reset Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. A Watchdog Timer (WDT) Reset event is synchronized with the system clock SYSCLK before asserting the system Reset. Note that a WDT Time-out during SLEEP or IDLE mode will wake-up the processor and branch to the PIC32MX Reset vector, but not reset the processor. The only bits affected are WDTO and SLEEP or IDLE in the RCON register. Refer to Section 9. “Watchdog Timer and Power-up Timer” in this manual. 7.3.6 Brown-out Reset PIC32MX family devices have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a BOR event which is synchronized with the system clock SYSCLK before asserting the system Reset. This event is captured by the BOR flag bit (RCON<1>). Refer to the Electrical Characteristics section of the specific device data sheet for further details. 7.3.7 Configuration Mismatch Reset To maintain the integrity of the stored configuration values, all device Configuration bits are loaded and implemented as a complementary set of bits. As the Configuration Words are being loaded, for each bit loaded as ‘1’, a complementary value of ‘0’, is stored into its corresponding background word location and vice versa. The bit pairs are compared every time the Configuration Words are loaded, including SLEEP mode. During this comparison, if the Configuration bit values are not found opposite to each other, a configuration mismatch event is generated which causes a device Reset. If a device Reset occurs as a result of a configuration mismatch, the CMR Status bit (RCON<9>) is set. Resets 170 © 2008 Microchip Technology Inc. Preliminary DS61118E-page 7-11 PIC32MX Family Reference Manual 7.4 EFFECTS OF VARIOUS RESETS The Reset value for the Reset Control register, RCON, will depend on the type of device Reset, as indicated in Table 7-2. Table 7-2: Status Bits, Their Significance and the Initialization Condition for RCON Register EXTR SWR WDTO SLEEP IDLE CMR BOR POR Condition Program Counter Power-on Reset Brown-out Reset MCLR Reset during Run Mode MCLR Reset during IDLE Mode MCLR Reset during SLEEP Mode Software Reset Command Configuration Word Mismatch Reset WDT Time-out Reset during Run Mode WDT Time-out Reset during IDLE Mode WDT Time-out Reset during SLEEP Mode Interrupt Exit from IDLE Mode Interrupt Exit from SLEEP Mode Legend: u = unchanged BFC0_0000h BFC0_0000h BFC0_0000h BFC0_0000h BFC0_0000h BFC0_0000h BFC0_0000h BFC0_0000h BFC0_0000h BFC0_0000h Vector Vector 00000011 0000001u 1uuuuuuu 1 u u u 1(1) u u u 1 u u 1(1) u u u u u1uuuuuu uuuuu1uu uu1uuuuu u u 1 u 1(1) u u u u u 1 1(1) u u u u u u u u 1(1)) u u u u u u 1(1) u u u u Note 1: SLEEP and IDLE bits states defined by previously executed WAIT instruction. 7.4.1 Special Function Register Reset States Most of the Special Function Registers (SFRs) associated with the PIC32MX CPU and peripherals are reset to a particular value at a device Reset. Reset values are specified in the corresponding section of this manual. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. 7.4.2 Configuration Word Register Reset States All Reset conditions force the configuration settings to be re-loaded. The POR Reset sets all the Configuration Word register locations = 1 before loading the configuration settings. For all other Reset conditions, the Configuration Word register locations are not reset prior to being re-loaded. This difference in behavior accommodates MCLR assertions during DEBUG mode without affecting the state of the DEBUG operations. Independent of the source of a Reset, the system clock is always re-loaded and is specified by the FNOSC<2:0> value in the DEVCFG1 Configuration Word. When the device is executing code, the user may change the primary system clock source by using the OSCCON register. Refer to Section 6. “Oscillators” in this manual for further details. DS61118E-page 7-12 Preliminary © 2008 Microchip Technology Inc. Section 7. Resets 7.4.3 Using the RCON Status Bits The user can read the RCON register after any system Reset to determine the cause of the Reset. Table 7-3 provides a summary of the Reset flag bit operation. Note: The Status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. Table 7-3: Reset Flag Bit Operation Flag Bit Set by: Cleared by: POR (RCON<0>) POR user software BOR (RCON<1>) EXTR (RCON<7>) SWR (RCON<6>) CMR (RCON<9>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) POR, BOR MCLR Reset Software Reset command Configuration mis-match WDT time-out WAIT instruction WAIT instruction user software user software, POR, BOR user software, POR, BOR user software, POR, BOR user software, POR, BOR user software, POR, BOR user software, POR, BOR Note: All Reset flag bits may be set or cleared by the user software. 7.4.4 Device Reset to Code Execution Start Time The delay between the end of a Reset event and when the device actually begins to execute code is determined by two main factors: the type of Reset, and the system clock source coming out of the Reset. The code execution start time for various types of device Resets are summarized in Table 7-4. Individual delays are characterized in the Electrical Characteristics section of the specific device data sheet for details. Table 7-4: Code Execution Start Time for Various Device Resets Reset Type Clock Source Power-Up Delay(1)(2)(3) System Clock Delay(4)(5) FSCM Delay(6) POR EC, FRC, FRCDIV, LPRC (TPU OR TPWRT) + TSYSDLY — ECPLL, FRCPLL (TPU OR TPWRT) + TSYSDLY TLOCK XT, HS, SOSC (TPU OR TPWRT) + TSYSDLY TOST XTPLL, HSPLL (TPU OR TPWRT) + TSYSDLY TOST + TLOCK BOR EC, FRC, FRCDIV, LPRC TSYSDLY — ECPLL, FRCPLL TSYSDLY TLOCK XT, HS, SOSC TSYSDLY TOST XTPLL TSYSDLY TOST + TLOCK MCLR, CMR, Any Clock SWR, WDTO TSYSDLY — Note 1: TPU = Power-up Period with on-chip regulator enabled. 2: TPWRT = Power-up Period (POWER-UP TIMER) with on-chip regulator disabled. 3: TSYSDLY = Time required to reload Device Configuration Fuses plus 8 SYSCLK cycles. 4: TOST = Oscillator Start-up Timer. 5: TLOCK = PLL lock time. 6: TFSCM = Fail-Safe Clock Monitor delay. — TFSCM TFSCM TFSCM — TFSCM TFSCM TFSCM — Note: For parameter specifictions, see Section 30.2 “AC Characteristics and Timing Parameters.” Resets 170 © 2008 Microchip Technology Inc. Preliminary DS61118E-page 7-13 PIC32MX Family Reference Manual 7.5 DESIGN TIPS Question 1: How can I use the RCON register to determine the source of the device reset? Answer: Initialization code after a Reset can examine the RCON register and confirm the source of the Reset. In certain applications, this information can be used to take appropriate action to correct the problem that caused the Reset to occur. All Reset Status bits in the RCON register should be cleared after reading them to ensure the RCON value will provide meaningful results after the next device Reset. int main(void) { //... perform application specific startup tasks // next, check the cause of the Reset if(RCON & 0x0003) { // execute a Power-on-Reset handler // ... } else if(RCON & 0x0002) { // execute a Brown-out-Reset handler // ... } else if(RCON & 0x0080) { // execute a Master Clear Reset handler // ... } else if(RCON & 0x0040) { // execute a Software Reset handler // ... } else if (RCON & 0x0200) { // execute a Configuration Mismatch Reset handler // ... } else if (RCON & 0x0010) { // execute Watchdog Timeout Reset handler // ... } //... perform other application specific tasks while(1); } DS61118E-page 7-14 Preliminary © 2008 Microchip Technology Inc. Section 7. Resets 7.6 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to Resets are: Title No related application notes at this time. Application Note # N/A Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. 170 Resets © 2008 Microchip Technology Inc. Preliminary DS61118E-page 7-15 PIC32MX Family Reference Manual 7.7 REVISION HISTORY Revision A (September 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x. Revision D (June 2008) Revised Figure 7-2; Deleted Figure 7-3; Revised Sections 7.3.2, 7.3.3, 7.3.4; Revised Table 7-4; Delete Figure 7.2 and 7.3; Change Reserved bits from “Maintain as” to “Write”. Revision E (July 2008) Revised Section 7.3.2, 7.3.3, 7.3.6, 7.4.4. DS61118E-page 7-16 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts HIGHLIGHTS This section of the manual contains the following topics: 8.1 Introduction ................................................................................................................... 8-2 8.2 Control Registers .......................................................................................................... 8-3 8.3 Operation .................................................................................................................... 8-19 8.4 Single Vector Mode ..................................................................................................... 8-21 8.5 Multi-Vector Mode ....................................................................................................... 8-22 8.6 Interrupt Vector Address Calculation........................................................................... 8-23 8.7 Interrupt Priorities........................................................................................................ 8-24 8.8 Interrupts and Register Sets ....................................................................................... 8-25 8.9 Interrupt Processing .................................................................................................... 8-26 8.10 External Interrupts....................................................................................................... 8-30 8 8.11 Temporal Proximity Interrupt Coalescing .................................................................... 8-31 8.12 Effects of Interrupts After Reset .................................................................................. 8-32 8.13 Operation in Power-Saving and DEBUG Modes......................................................... 8-32 8.14 Design Tips ................................................................................................................. 8-33 8.15 Related Application Notes........................................................................................... 8-34 8.16 Revision History .......................................................................................................... 8-35 Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-1 PIC32MX Family Reference Manual 8.1 INTRODUCTION PIC32MX generates interrupt requests in response to interrupt events from peripheral modules. The interrupts module exists external to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. The PIC32MX Interrupts module includes the following features: • Up to 96 interrupt sources • Up to 64 interrupt vectors • Single and Multi-Vector mode operations • 5 External interrupts with edge polarity control • Interrupt proximity timer • Module freeze in Debug mode • 7 user-selectable priority levels for each vector • 4 user-selectable subpriority levels within each priority • Dedicated shadow set for highest priority level • Software can generate any interrupt • User-configurable interrupt vector table location • User-configurable interrupt vector spacing Figure 8-1: Interrupt Controller Module Interrupt Requests Vector Number Interrupt Controller Priority Level Shadow Set Number CPU Core Note: Several of the registers cited in this section are not in the interrupt controller module. These registers (and bits) are associated with the CPU. Details about them is available in Section 2. “MCU”. To avoid confusion, a typographic distinction is made for registers in the CPU. The register names in this section, and all other sections of this manual, are signified by uppercase letters only (except for cases in which variables are used). CPU register names are signified by upper and lowercase letters. For example, INTSTAT is an Interrupts register; whereas, IntCtl is a CPU register. DS61108D-page 8-2 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.2 CONTROL REGISTERS Note: Each PIC32MX device variant may have one or more Interrupt channels. An ‘x’ used in the names of control/Status bits and registers denotes the particular channel. Refer to the specific device data sheets for more details. The Interrupts module consists of the following Special Function Registers (SFRs). • INTCON: Interrupt Control Register INTCONCLR, INTCONSET, INTCONINV: Atomic Bit Manipulation, Write-only Registers for INTCON • INTSTAT: Interrupt Status Register INTSTATCLR, INTSTATSET, INTSTATINV: Atomic Bit Manipulation, Write-only Registers for INTSTAT • TPTMR: Temporal Proximity Timer Register TPTMRCLR, TPTMRSET, TPTMRNINV: Atomic Bit Manipulation, Write-only Registers for TPTMR • IFSx: Interrupt Flag Status Registers IFSxCLR, IFSxSET, IFSxINV: Atomic Bit Manipulation, Write-only Registers for IFSx • IECx: Interrupt Enable Control Registers IECxCLR, IECxSET, IECxINV: Atomic Bit Manipulation, Write-only Registers for IECx 8 • IPCx: Interrupt Priority Control Registers IPCxCLR, IPCxSET, IPCxINV: Atomic Bit Manipulation, Write-only Registers for IPCx The following table provides a brief summary of Interrupts-module-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Table 8-1: Interrupt SFR Summary Name Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 INTCON 31:24 — — — — — — — 23:16 — — — — — — — 15:8 — FRZ — MVEC — TPC<2:0> 7:0 — — — INT4EP INT3EP INT2EP INT1EP INTCONCLR 31:0 INTCONSET 31:0 INTCONINV 31:0 Write clears the selected bits in INTCON, read yields undefined value Write sets the selected bits in INTCON, read yields undefined value Write inverts the selected bits in INTCON, read yields undefined value INTSTAT 31:24 — — — — — — — 23:16 — — — — — — — 15:8 — 7:0 — INTSTATCLR 31:0 — — — — RIPL<2:0> — VEC<5:0> Write clears the selected bits in INTSTAT, read yields undefined value INTSTATSET 31:0 INTSTATINV 31:0 TPTMR 31:24 Write sets the selected bits in INTSTAT, read yields undefined value Write inverts the selected bits in INTSTAT, read yields undefined value 23:16 15:8 7:0 TPTMR<31:0> Bit 24/16/8/0 — SS0 INT0EP — — Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-3 PIC32MX Family Reference Manual Table 8-1: Interrupt SFR Summary (Continued) Name Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 TPTMRCLR 31:0 Write clears the selected bits in TPTMR, read yields undefined value TPTMRSET TPTMRINV IFSx 31:0 31:0 31:24 IFS31 Write sets the selected bits in TPTMR, read yields undefined value Write inverts the selected bits in TPTMR, read yields undefined value IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24 23:16 15:8 7:0 IFS23 IFS15 IFS07 IFS22 IFS14 IFS06 IFS21 IFS13 IFS05 IFS20 IFS12 IFS04 IFS19 IFS11 IFS03 IFS18 IFS10 IFS02 IFS17 IFS09 IFS01 IFS16 IFS08 IFS00 IFSxCLR IFSxSET IFSxINV IECx 31:0 31:0 31:0 31:24 23:16 IEC31 IEC23 Write clears the selected bits in IFSx, read yields undefined value Write sets the selected bits in IFSx, read yields undefined value Write inverts the selected bits in IFSx, read yields undefined value IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC24 IEC16 IECxCLR 15:8 IEC15 7:0 IEC07 31:0 IEC14 IEC13 IEC12 IEC11 IEC10 IEC09 IEC06 IEC05 IEC04 IEC03 IEC02 IEC01 Write clears the selected bits in IECx, read yields undefined value IEC08 IEC00 IECxSET 31:0 IECxINV 31:0 IPCx 31:24 — Write sets the selected bits in IECx, read yields undefined value Write inverts the selected bits in IECx read yields undefined value — — IP03<2:0> IS03<1:0> 23:16 — — — 15:8 — — — 7:0 — — — IP02<2:0> IP01<2:0> IP00<2:0> IS02<1:0> IS01<1:0> IS00<1:0> IPCxCLR 31:0 IPCxSET 31:0 IPCxINV 31:0 Write clears the selected bits in IPCx, read yields undefined value Write sets the selected bits in IPCx, read yields undefined value Write inverts the selected bits in IPCx, read yields undefined value DS61108D-page 8-4 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts Register 8-1: INTCON: Interrupt Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x R/W-0 — — — — — — SS0 bit 16 r-x — bit 15 R/W-0 r-x R/W-0 r-x R/W-0 R/W-0 R/W-0 FRZ — MVEC — TPC<2:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit 8 bit 31-17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10-8 bit 7-5 bit 4 Reserved: Write ‘0’; ignore read SS0: Single Vector Shadow Register Set bit 1 = Single vector is presented with a shadow register set 0 = Single vector is not presented with a shadow register set Reserved: Write ‘0’; ignore read FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation even when CPU is in Debug Exception mode Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode. Reserved: Write ‘0’; ignore read MVEC: Multi Vector Configuration bit 1 = Interrupt controller configured for multi vectored mode 0 = Interrupt controller configured for single vectored mode Reserved: Write ‘0’; ignore read TPC: Temporal Proximity Control bits 111 = Interrupt of group priority 7 or lower start the TP timer 110 = Interrupt of group priority 6 or lower start the TP timer 101 = Interrupt of group priority 5 or lower start the TP timer 100 = Interrupt of group priority 4 or lower start the TP timer 011 = Interrupt of group priority 3 or lower start the TP timer 010 = Interrupt of group priority 2 or lower start the TP timer 001 = Interrupt of group priority 1 start the IP timer 000 = Disables proximity timer Reserved: Write ‘0’; ignore read INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-5 PIC32MX Family Reference Manual Register 8-1: bit 3 bit 2 bit 1 bit 0 INTCON: Interrupt Control Register INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge DS61108D-page 8-6 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts Register 8-2: INTCONCLR: INTCON Clear Register Write clears selected bits in INTCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in INTCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in INTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: INTCONCLR = 0x00000101 will clear bits 8 and 0 in INTCON register. Register 8-3: INTCONSET: INTCON Set Register Write sets selected bits in INTCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in INTCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in INTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: INTCONSET = 0x00000101 will set bits 8 and 0 in INTCON register. 8 Register 8-4: INTCONINV: INTCON Invert Register Write inverts selected bits in INTCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in INTCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in INTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: INTCONINV = 0x00000101 will invert bits 8 and 0 in INTCON register. Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-7 PIC32MX Family Reference Manual Register 8-5: INTSTAT: Interrupt Status Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 r-x — bit 15 r-x r-x r-x r-x R-0 R-0 R-0 — — — — RIPL<2:0> bit 8 r-x — bit 7 r-x R-0 R-0 R-0 R-0 R-0 R-0 — VEC<5:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-11 bit 10-8 bit 5-0 Reserved: Write ‘0’; ignore read RIPL: Requested Priority Level bits 000-111 = The priority level of the latest interrupt presented to the CPU Note: This value should only be used when the interrupt controller is configured for Single Vector mode. VEC: Interrupt Vector bits 00000-11111 =The interrupt vector that is presented to the CPU Note: This value should only be used when the interrupt controller is configured for Single Vector mode. DS61108D-page 8-8 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts Register 8-6: INTSTATCLR: INTSTAT Clear Register Write clears selected bits in INTSTAT, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in INTSTAT A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in INTSTAT register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: INTSTATCLR = 0x00000101 will clear bits 8 and 0 in INTSTAT register. Register 8-7: INTSTATSET: INTSTAT Set Register Write sets selected bits in INTSTAT, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in INTSTAT A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in INTSTAT register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: INTSTATSET = 0x00000101 will set bits 8 and 0 in INTSTAT register. 8 Register 8-8: INTSTATINV: INTSTAT Invert Register Write inverts selected bits in INTSTAT, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in INTSTAT A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in INTSTAT register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: INTSTATINV = 0x00000101 will invert bits 8 and 0 in INTSTAT register. Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-9 PIC32MX Family Reference Manual Register 8-9: R/W-0 bit 31 TPTMR: Temporal Proximity Timer Register R/W-0 R/W-0 R/W-0 R/W-0 TPTMR<31:24> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR<23:16> R/W-0 R/W-0 R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 TPTMR: Temporal Proximity Timer Reload bits Used by the Temporal Proximity Timer as a reload value when the Temporal Proximity timer is triggered by an interrupt event. DS61108D-page 8-10 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts Register 8-10: TPTMRCLR: TPTMR Clear Register Write clears selected bits in TPTMR, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in TPTMR A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in TPTMR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TPTMRCLR = 0x00000101 will clear bits 8 and 0 in TPTMR register. Register 8-11: TPTMRSET: TPTMR Set Register Write sets selected bits in TPTMR, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in TPTMR A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in TPTMR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TPTMRSET = 0x00000101 will set bits 8 and 0 in TPTMR register. 8 Register 8-12: TPTMRINV: TPTMR Invert Register Write inverts selected bits in TPTMR, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in TPTMR A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in TPTMR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TPTMRINV = 0x00000101 will toggle bits 8 and 0 in TPTMR register. Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-11 PIC32MX Family Reference Manual Register 8-13: R/W-0 IFS31 bit 31 IFSx: Interrupt Flag Status Register(1) R/W-0 R/W-0 R/W-0 IFS30 IFS29 IFS28 R/W-0 IFS27 R/W-0 IFS26 R/W-0 IFS25 R/W-0 IFS24 bit 24 R/W-0 IFS23 bit 23 R/W-0 IFS22 R/W-0 IFS21 R/W-0 IFS20 R/W-0 IFS19 R/W-0 IFS18 R/W-0 IFS17 R/W-0 IFS16 bit 16 R/W-0 IFS15 bit 15 R/W-0 IFS14 R/W-0 IFS13 R/W-0 IFS12 R/W-0 IFS11 R/W-0 IFS10 R/W-0 IFS09 R/W-0 IFS08 bit 8 R/W-0 IFS07 bit 7 R/W-0 IFS06 R/W-0 IFS05 R/W-0 IFS04 R/W-0 IFS03 R/W-0 IFS02 R/W-0 IFS01 R/W-0 IFS00 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 IFS31-IFS00: Interrupt Flag Status bits 1 = Interrupt request has occurred 0 = No interrupt request has occurred Note 1: This register represents a generic definition of the IFSx register. Refer to the “Interrupts” chapter in the device data sheet to learn exact bit definitions. DS61108D-page 8-12 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts Register 8-14: IFSxCLR: IFSx Clear Register Write clears selected bits in IFSx, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in IFSx A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in IFSx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: IFSxCLR = 0x00000101 will clear bits 8 and 0 in IFSx register. Register 8-15: IFSxSET: IFSx Set Register Write sets selected bits in IFSx, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in IFSx A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in IFSx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: IFSxSET = 0x00000101 will set bits 8 and 0 in IFSx register. 8 Register 8-16: IFSxINV: IFSx Invert Register Write inverts selected bits in IFSx, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in IFSx A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in IFSx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: IFSxINV = 0x00000101 will invert bits 8 and 0 in IFSx register. Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-13 PIC32MX Family Reference Manual Register 8-17: R/W-0 IEC31 bit 31 IECx: Interrupt Enable Control Register(1) R/W-0 R/W-0 R/W-0 R/W-0 IEC30 IEC29 IEC28 IEC27 R/W-0 IEC26 R/W-0 IEC25 R/W-0 IEC24 bit 24 R/W-0 IEC23 bit 23 R/W-0 IEC22 R/W-0 IEC21 R/W-0 IEC20 R/W-0 IEC19 R/W-0 IEC18 R/W-0 IEC17 R/W-0 IEC16 bit 16 R/W-0 IEC15 bit 15 R/W-0 IEC14 R/W-0 IEC13 R/W-0 IEC12 R/W-0 IEC11 R/W-0 IEC10 R/W-0 IEC09 R/W-0 IEC08 bit 8 R/W-0 IEC07 bit 7 R/W-0 IEC06 R/W-0 IEC05 R/W-0 IEC04 R/W-0 IEC03 R/W-0 IEC02 R/W-0 IEC01 R/W-0 IEC00 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-0 IEC31-IEC00: Interrupt Enable bits 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: This register represents a generic definition of the IFSx register. Refer to the “Interrupts” chapter in the device data sheet to learn exact bit definitions. DS61108D-page 8-14 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts Register 8-18: IECxCLR: IECx Clear Register Write clears selected bits in IECx, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in IECx A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in IECx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: IECxCLR = 0x00000101 will clear bits 8 and 0 in IECx register. Register 8-19: IECxSET: IECx Set Register Write sets selected bits in IECx, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in IECx A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in IECx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: IECxSET = 0x00000101 will set bits 8 and 0 in IECx register. 8 Register 8-20: IECxINV: IECx Invert Register Write inverts selected bits in IECx, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in IECx A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in IECx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: IECxINV = 0x00000101 will invert bits 8 and 0 in IECx register. Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-15 PIC32MX Family Reference Manual Register 8-21: r-x — bit 31 IPCx: Interrupt Priority Control Register(1) r-x r-x R/W-0 R/W-0 — — IP03<2:0> R/W-0 R/W-0 R/W-0 IS03<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IP02<2:0> IS02<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IP01<2:0> IS01<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IP00<2:0> IS00<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-29 bit 28-26 bit 25-24 bit 23-21 bit 20-18 bit 17-16 bit 15-13 Reserved: Write ‘0’; ignore read IP03<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS03<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt Subpiority is 0 Reserved: Write ‘0’; ignore read IP02<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS02<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Reserved: Write ‘0’; ignore read DS61108D-page 8-16 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts Register 8-21: IPCx: Interrupt Priority Control Register(1) (Continued) bit 12-10 IP01<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 9-8 IS01<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 7-5 Reserved: Write ‘0’; ignore read bit 4-2 IP00<2:0>: Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 8 000 = Interrupt is disabled bit 1-0 IS00<1:0>: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: This register represents a generic definition of the IFSx register. Refer to the “Interrupts” chapter in the device data sheet to learn exact bit definitions. Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-17 PIC32MX Family Reference Manual Register 8-22: IPCxCLR: IPCx Clear Register Write clears selected bits in IPCx, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in IPCx A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in IPCx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: IPCxCLR = 0x00000101 will clear bits 8 and 0 in IPCx register. Register 8-23: IPCxSET: IPCx Set Register Write sets selected bits in IPCx, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in IPCx A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in IPCx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: IPCxSET = 0x00000101 will set bits 8 and 0 in IPCx register. Register 8-24: IPCxINV: IPCx Invert Register Write inverts selected bits in IPCx, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in IPCx A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in IPCx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: IPCxINV = 0x00000101 will invert bits 8 and 0 in IPCx register. DS61108D-page 8-18 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.3 OPERATION The interrupt controller is responsible for pre-processing interrupt requests (IRQ) from a number of on-chip peripherals and presenting them in the appropriate order to the processor. Figure 8-2 depicts the process within the interrupt controller module. The interrupt controller is designed to receive up to 96 IRQs from the processor core and from on-chip peripherals capable of generating interrupts. All IRQs are sampled on the rising edge of the SYSCLK and latched in associated IFSx registers. A pending IRQ is indicated by the flag bit being equal to ‘1’ in an IFSx register. The pending IRQ will not cause further processing if the corresponding bit in the interrupt enable (IECx) register is clear. The IECx bits act to gate the interrupt flag. If the interrupt is enabled, all IRQs are encoded into a 5-bit-wide vector number. The 5-bit vector results in 0 to 63 unique interrupt vector numbers. Since there are more IRQs than available vector numbers, some IRQs share common vector numbers. Each vector number is assigned an interrupt-priority-level and shadow-set number. The priority level is determined by the IPCx register setting of associated vector. In Multi-Vector mode, all priority-level-7 interrupts use a dedicated register set, while in Single Vector mode, all interrupts may receive a dedicated shadow set. The interrupt controller selects the highest priority IRQ among all pending IRQs and presents the associated vector number, priority-level and shadow-set number to the processor core. The processor core samples the presented vector information between ‘E’ and ‘M’ stage of the pipeline. If the vector’s priority level presented to the core is greater than the current priority indicated by the CPU Interrupt Priority bits IPL (Status<15:10>), the interrupt is serviced, other- wise it will remain pending until the current priority is less than the interrupt’s priority. When ser- vicing an interrupt, the processor core pushes the program counter into the Exception Program Counter (EPC) register in the CPU and sets Exception Level bit EXL (Status<1>) in the CPU. The EXL bit disables further interrupts until the application explicitly re-enables them by clearing EXL 8 bit. Next, it branches to the vector address calculated from the presented vector number. The INTSTAT register contains the Interrupt Vector Number bits VEC (INTSTAT<5:0>) and Requested Interrupt Priority bits RIPL (INTSTAT<10:8>) of the current pending interrupt. This may not be the same as the interrupt which caused the core to diverge from normal execution. The processor returns to the previous state when the ERET (Exception Return) instruction is executed. ERET clears the EXL bit, restores the program counter, and reverts the current shadow set to the previous one. The PIC32MX interrupt controller can be configured to operate in one of two modes: • Single Vector mode – all interrupt requests will be serviced at one vector address (mode out of reset). • Multi-Vector mode – interrupt requests will be serviced at the calculated vector address. Notes: While the user can, during run time, reconfigure the interrupt controller from Single Vector to Multi-Vector mode (or vice versa), such action is strongly discouraged. Changing interrupt controller modes after initialization may result in undefined behavior. The M4K core supports several different interrupt processing modes. The interrupt controller is designed to work in External Interrupt Controller mode. Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-19 PIC32MX Family Reference Manual Figure 8-2: Interrupt Process ENCODE LATCH COMPARE GENERATE Vector Number StatusIPL RIPL Any Request > IPL StatusIE Load IntCtlVS Fields • Interrupt Request Interrupt Exception Requested IPL Exception Vector Offset Offset Generator Interrupt Sources Interrupt Module Shadow Set Number Shadow Set Number SRSCtlEICSS CauseRIPL Note: SRSCtl, Cause, Status, and IntCtl registers are CPU registers and are described in Section 2. “CPU”. DS61108D-page 8-20 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.4 SINGLE VECTOR MODE On any form of Reset, the interrupt controller initializes to Single Vector mode. When the MVEC (INTCON<12>) bit is ‘0’, the interrupt controller operates in Single Vector mode. In this mode, the CPU always vectors to the same address. Note: Users familiar with MIPS32 architecture must note that the M4K core in PIC32MX is still operating in External Interrupt Controller (EIC) mode. The PIC32MX achieves Single Vector mode by forcing all IRQs to use a vector number of 0x00. Because the M4K core in PIC32MX always operates in EIC mode, the single vector behavior through “Interrupt Compatibility Mode” as defined by MIPS32 architecture is not recommended. To configure the CPU in PIC32MX Single Vector mode, the following CPU registers (IntCtl, Cause, and Status) and INTCON register must be configured as follows: • EBase ≠ 00000 • VS (IntCtl<9:5>) ≠ 00000 • IV (Cause<23>) = 1 • EXL (Status<1>) = 0 • BEV (Status<22>) = 0 • MVEC (INTCON<12>) = 0 • IE (Status<0>) = 1 Example 8-1: Single Vector Mode Initialization 8 /* Set the CP0 registers for multi-vector interrupt Place EBASE at 0xBD000000 This code example uses MPLAB C32 intrinsic functions to access CP0 registers. Check your compiler documentation to find equivalent functions or use inline assembly */ unsigned int temp; asm volatile(“di”); // Disable all interrupts temp = mips_getsr(); temp |= 0x00400000; mips_setsr(temp); // Get Status // Set BEV bit // Update Status _mips_mtc0(C0_EBASE, 0xBD000000); // Set an EBase value of 0xBD000000 _mips_mtc0(C0_INTCTL, 0x00000020); // Set the Vector Spacing to non-zero value temp = mips_getcr(); temp |= 0x00800000; mips_setcr(temp); // Get Cause // Set IV // Update Cause temp = mips_getsr(); temp &= 0xFFBFFFFD; mips_setsr(temp); // Get Status // Clear BEV and EXL // Update Status INTCONCLR = 0x800; // Clear MVEC bit asm volatile(“ie”); // Enable all interrupts Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-21 PIC32MX Family Reference Manual 8.5 MULTI-VECTOR MODE When the MVEC (INTCON<12>) bit is ‘1’, the interrupt controller operates in Multi-Vector mode. In this mode, the CPU vectors to the unique address for each vector number. Each vector is located at a specific offset, with respect to a base address specified by the EBase register in the CPU. The individual vector address offset is determined by the vector space that is specified by the VS bits in IntCtl register. (The IntCtl register is located in the CPU; refer to Section 2. “MCU” of this manual for more information.) To configure the CPU in PIC32MX Multi-Vector mode, the following CPU registers (IntCtl, Cause, and Status) and the INTCON register must be configured as follows: • EBase ≠ 00000 • VS (IntCtl<9:5>) ≠ 00000 • IV (Cause<23>) = 1 • EXL (Status<1>) = 0 • BEV (Status<22>) = 0 • MVEC (INTCON<12>) = 1 • IE (Status<0>) = 1 Example 8-2: Multi-Vector Mode Initialization /* Set the CP0 registers for multi-vector interrupt Place EBASE at 0xBD000000 and Vector Spacing to 32 bytes This code example uses MPLAB C32 intrinsic functions to access CP0 registers. Check your compiler documentation to find equivalent functions or use inline assembly */ unsigned int temp; asm volatile(“di”); // Disable all interrupts temp = mips_getsr(); temp |= 0x00400000; mips_setsr(temp); // Get Status // Set BEV bit // Update Status _mips_mtc0(C0_EBASE, 0xBD000000); // Set an EBase value of 0xBD000000 _mips_mtc0(C0_INTCTL, 0x00000020); // Set the Vector Spacing of 32 bytes temp = mips_getcr(); // Get Cause temp |= 0x00800000; // Set IV mips_setcr(temp); // Update Cause temp = mips_getsr(); temp &= 0xFFBFFFFD; mips_setsr(temp); // Get Status // Clear BEV and EXL // Update Status INTCONSET = 0x800; // Set MVEC bit asm volatile(“ie”); // Enable all interrupts DS61108D-page 8-22 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.6 INTERRUPT VECTOR ADDRESS CALCULATION The vector address for a particular interrupt depends on how the interrupt controller is configured. If the interrupt controller is configured for Single Vectored mode (see Section 8.4), all interrupt vectors use the same vector address. When it is configured for Multi-Vectored mode (see Section 8.5), each interrupt vector has a unique vector address. On all forms of Reset, the processor enters in Bootstrap mode with Control bit BEV (Status<22>) set. (The Status register is located in the CPU; refer to Section 2. “MCU” of this manual for more information.) While the processor is in Bootstrap mode, all interrupts are disabled and all general exceptions are redirected to one interrupt vector address, 0xBFC00380. When configuring the interrupt controller to the desired mode of operation, several registers must be set to specific values (See Section 8.4 and Section 8.5) before the BEV bit is cleared. The vector address of a given interrupt is calculated using Exception Base (EBase<31:12>) register, which provides a 4 KB page-aligned base address value located in the kernel segment (kseg) address space. (EBase is a CPU register.) 8.6.1 Multi-Vector Mode Address Calculation The Multi-Vector mode address is calculated by using EBase and VS (IntCtl<9:5>) values. (The IntCtl and Status registers are located in the CPU.) The VS bits provide the spacing between adjacent vector addresses. Allowable vector spacing values are 32, 64, 128, 256 and 512 bytes. Modifications to EBase and VS values are only allowed when the BEV (Status<22>) bit is ‘1’ in the CPU. Example 8-3 shows how a multi-vector address is calculated for a given vector. Note: The Multi-Vector mode address calculation depends on the interrupt vector number. Each PIC32MX device family may have its own set of vector numbers depending on 8 its feature set. See the respective device data sheet to find out vector numbers associated with each interrupt source. Example 8-3: Vector Address for Vector Number 16 vector address = vector number X (VS << 5) + 0x200 + vector base. Exception Base is 0xBD000000 Vector Spacing(VS) is 2, which is 64(0x40) vector address(T4) = 0x10 X 0x40 + 0x200 + 0xBD000000 vector address(T4) = 0xBD000600 8.6.2 Single Vector Mode Address Calculation The Single Vector mode address is calculated by using the Exception Base (EBase<31:12>) register value. In Single Vector mode, the interrupt controller always presents a vector number of ‘0’ The exact formula for Single Vector mode is as follows: Equation 8-1: Single Vector Mode Address Calculation Single Vector Address = EBase + 0x200 Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-23 PIC32MX Family Reference Manual 8.7 INTERRUPT PRIORITIES 8.7.1 Interrupt Group Priority The user is able to assign a group priority to each of the interrupt vectors. The groups’ priority-level bits are located in IPCx register. Each IPCx register contains group priority bits for four interrupt vectors. The user-selectable priority levels range from 1 (the lowest priority) to 7 (the highest). If an interrupt priority is set to zero, the interrupt vector is disabled for both interrupt and wake-up purposes. Interrupt vectors with a higher priority level preempt lower priority interrupts. The user must move the Requested Interrupt Priority bit of the Cause register RIPL (Cause<15:10>) into the Status register’s Interrupt Priority bits IPL (Status<15:10>) before re-enabling interrupts. (The Cause and Status registers are located in the CPU; refer to Section 2. “MCU” of this manual for more information.) This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. Note: The Interrupt Service Routine (ISR) must clear the associated interrupt flag in the IFSx register before lowering the interrupt priority level to avoid recursive interrupts. Example 8-4: Setting Group Priority Level /* The following code example will set the priority to level 2. Multi-Vector initialization must be performed (See Example 8-2) */ IPC0CLR = 0x0000001C; // clear the priority level IPC0SET = 0x00000008; // set priority level to 2 8.7.2 Interrupt Subpriority The user can assign a subpriority level within each group priority. The subpriority will not cause preemption of an interrupt in the same priority; rather, if two interrupts with the same priority are pending, the interrupt with the highest subpriority will be handled first. The subpriority bits are located in the IPCx register. Each IPCx register contains subpriority bits for four of the interrupt vectors. These bits define the subpriority within the priority level of the vector. The user-selectable subpriority levels range from 0 (the lowest subpriority) to 3 (the highest). Example 8-5: Setting Subpriority Level /* The following code example will set the subpriority to level 2. initialization must be performed (See Example 8-2) */ Multi-Vector IPC0CLR = 0x00000003; IPC0SET = 0x00000002; // clear the subpriority level // set the subpriority to 2 8.7.3 Interrupt Natural Priority When multiple interrupts are assigned to same group priority and subpriority, they are prioritized by their natural priority. The natural priority is a fixed priority scheme, where the highest natural priority starts at the lowest interrupt vector, meaning that interrupt vector 0 is the highest and interrupt vector 63 is the lowest natural priority. See the interrupt vector table in the respective device data sheet to learn the natural priority order of each IRQ. DS61108D-page 8-24 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.8 INTERRUPTS AND REGISTER SETS The PIC32MX family of devices employs two register sets, a primary register set for normal program execution and a shadow register set for highest priority interrupt processing. Register set selection is automatically performed by the interrupt controller. The exact method of register set selection varies by the interrupt controller modes of operation. In Single Vector and Multi-Vector modes of operation, the CSS field in SRSCtl register provides the current number of the register set in use, while the PSS field provides the number of the previous register set. (SRSCtl is a CPU register, refer to Section 2. “MCU” of this manual for details.) This information is useful to determine if the Stack and Global Data Pointers should be copied to the new register set, or not. If the current and previous register set are different, the interrupt handler prologue may need to copy Stack and Global Data Pointers from one set to another. Most C compilers supporting PIC32MX automatically generate the necessary interrupt prologue code to handle this operation. 8.8.1 Register Set Selection in Single Vector Mode In Single Vector mode, SS0 (INTCON<16>) bit determines which register set will be used. If the SS0 is ‘1’, the interrupt controller will instruct the CPU to use the second register set for all interrupts. If the SS0 is ‘0’, the interrupt controller will instruct the CPU to use the first register set. Unlike Multi-Vector mode, there is no linkage between register set and interrupt priority. The application decides if the second shadow set will be used at all. 8.8.2 Register Set Selection in Multi-Vector Mode When a priority level 7 interrupt is detected in Multi-Vector mode, the interrupt controller instructs the CPU to select the second register set. For interrupts below priority level 7, the interrupt con- 8 troller instructs the CPU to select the first register set. Because priority level 7 interrupts are unin- terruptable, the second register set is dedicated to those interrupts. As a result, priority level 7 interrupts do not need to save and restore General Purpose Register context, resulting in the shortest interrupt latency. Unlike register set selection in Single Vector mode, the selection of a second register set is automatically linked to priority level 7. The application does not have to set any register to enable a second register set. All interrupts with priority level of 7 are automatically assigned with the second register set. Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-25 PIC32MX Family Reference Manual 8.9 INTERRUPT PROCESSING When the priority of a requested interrupt is greater than the current CPU priority, the interrupt request is taken and the CPU branches to the vector address associated with the requested interrupt. Depending on the priority of the interrupt, the prologue and epilogue of the interrupt handler must perform certain tasks before executing any useful code. The following examples provide recommended prologues and epilogues. 8.9.1 Interrupt Processing in Single Vector Mode When the interrupt controller is configured in Single Vector mode, all of the interrupt requests are serviced at the same vector address. The interrupt handler routine must generate a prologue and an epilogue to properly configure, save, and restore all of the core registers, along with General Purpose Registers. At a worst case, all of the modifiable General Purpose Registers must be saved and restored by the prologue and epilogue. 8.9.1.1 Single Vector Mode Prologue When entering the interrupt handler routine, the interrupt controller must first save the current priority and exception PC counter from Interrupt Priority bits IPL (Status<15:10>) and the ErrorEPC register, respectively, on the stack. (Status and ErrorEPC are CPU registers.) If the routine is presented a new register set, the previous register set’s stack register must be copied to the current set’s stack register. Then the requested priority may be stored in the IPL from the Requested Interrupt Priority bits RIPL (Cause<15:10>), Exception Level bit EXL and Error Level bit ERL in the Status register (Status<1> and Status<2>) are cleared, and the Master Interrupt Enable bit (Status<0>) is set. Finally, the General Purpose Registers will be saved on the stack. (The Cause and Status registers are located in the CPU.) Example 8-6: Single Vector Interrupt Handler Prologue in Assembly Code rdpgpr sp, sp mfc0 k0, Cause mfc0 k1, EPC srl k0, k0, 0xa addiu sp, sp, -76 sw k1, 0(sp) mfc0 k1, Status sw k1, 4(sp) ins k1, k0, 10, 6 ins k1,zero, 1, 4 mtc0 k1, Status sw s8, 8(sp) sw a0, 12(sp) sw a1, 16(sp) sw a2, 20(sp) sw a3, 24(sp) sw v0, 28(sp) sw v1, 32(sp) sw t0, 36(sp) sw t1, 40(sp) sw t2, 44(sp) sw t3, 48(sp) sw t4, 52(sp) sw t5, 56(sp) sw t6, 60(sp) sw t7, 64(sp) sw t8, 68(sp) sw t9, 72(sp) addu s8, sp, zero // start interrupt handler code here DS61108D-page 8-26 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.9.1.2 Single Vector Mode Epilogue After completing all useful code of the interrupt handler routine, the original state of the Status and EPC registers, along with the General Purpose Registers saved on the stack, must be restored. Example 8-7: Single Vector Interrupt Handler Epilogue in Assembly Code // end of interrupt handler code addu sp, s8, zero lw t9, 72(sp) lw t8, 68(sp) lw t7, 64(sp) lw t6, 60(sp) lw t5, 56(sp) lw t4, 52(sp) lw t3, 48(sp) lw t2, 44(sp) lw t1, 40(sp) lw t0, 36(sp) lw v1, 32(sp) lw v0, 28(sp) lw a3, 24(sp) lw a2, 20(sp) lw a1, 16(sp) lw a0, 12(sp) lw s8, 8(sp) di 8 lw k0, 0(sp) mtc0 k0, EPC lw k0, 4(sp) mtc0 k0, Status eret 8.9.2 Interrupt Processing in Multi-Vector Mode When the interrupt controller is configured in Multi-Vector mode, the interrupt requests are serviced at the calculated vector addresses. The interrupt handler routine must generate a prologue and an epilogue to properly configure, save, and restore all of the core registers, along with General Purpose Registers. At a worst case, all of the modifiable General Purpose Registers must be saved and restored by the prologue and epilogue. If the interrupt priority is set to receive it’s own General Purpose Register set, the prologue and epilogue will not need to save or restore any of the modifiable General Purpose Registers, thus providing the lowest latency. 8.9.2.1 Multi-Vector Mode Prologue When entering the interrupt handler routine, the Interrupt Service Routine (ISR) must first save the current priority and exception PC counter from Interrupt Priority bits IPL (Status<15:10>) and the ErrorEPC register, respectively, on the stack. If the routine is presented a new register set, the previous register set’s stack register must be copied to the current set’s stack register. Then the requested priority may be stored in the IPL from Requested Interrupt Priority bits RIPL (Cause<15:10>), Exception Level bit EXL and Error Level bit ERL in the Status register (Status<1> and Status<2>) are cleared, and the Master Interrupt Enable bit (Status<0>) is set. If the interrupt handler is not presented a new General Purpose Register set, these resisters will be saved on the stack. (Cause and Status are CPU registers; refer to Section 2. “MCU” of this manual for more information.) Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-27 PIC32MX Family Reference Manual Example 8-8: Prologue Without a Dedicated General Purpose Register Set in Assembly Code rdpgpr sp, sp mfc0 k0, Cause mfc0 k1, EPC srl k0, k0, 0xa addiu sp, sp, -76 sw k1, 0(sp) mfc0 k1, Status sw k1, 4(sp) ins k1, k0, 10, 6 ins k1,zero, 1, 4 mtc0 k1, Status sw s8, 8(sp) sw a0, 12(sp) sw a1, 16(sp) sw a2, 20(sp) sw a3, 24(sp) sw v0, 28(sp) sw v1, 32(sp) sw t0, 36(sp) sw t1, 40(sp) sw t2, 44(sp) sw t3, 48(sp) sw t4, 52(sp) sw t5, 56(sp) sw t6, 60(sp) sw t7, 64(sp) sw t8, 68(sp) sw t9, 72(sp) addu s8, sp, zero // start interrupt handler code here Example 8-9: Prologue With a Dedicated General Purpose Register Set in Assembly Code rdpgpr sp, sp mfc0 k0, Cause mfc0 k1, EPC srl k0, k0, 0xa addiu sp, sp, -76 sw k1, 0(sp) mfc0 k1, Status sw k1, 4(sp) ins k1, k0, 10, 6 ins k1,zero, 1, 4 mtc0 k1, Status addu s8, sp, zero // start interrupt handler code here DS61108D-page 8-28 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.9.2.2 Multi-Vector Mode Epilogue After completing all useful code of the interrupt handler routine, the original state of the Status and ErrorEPC registers, along with the General Purpose Registers saved on the stack, must be restored. (The Status and ErrorEPC registers are located in the CPU; refer to Section 2. “MCU” of this manual for more information.) Example 8-10: Epilogue Without a Dedicated General Purpose Register Set in Assembly Code // end of interrupt handler code addu sp, s8, zero lw t9, 72(sp) lw t8, 68(sp) lw t7, 64(sp) lw t6, 60(sp) lw t5, 56(sp) lw t4, 52(sp) lw t3, 48(sp) lw t2, 44(sp) lw t1, 40(sp) lw t0, 36(sp) lw v1, 32(sp) lw v0, 28(sp) lw a3, 24(sp) lw a2, 20(sp) 8 lw a1, 16(sp) lw a0, 12(sp) lw s8, 8(sp) di lw k0, 0(sp) mtc0 k0, EPC lw k0, 4(sp) mtc0 k0, Status eret Example 8-11: Epilogue With a Dedicated General Purpose Register Set in Assembly Code // end of interrupt handler code addu di lw mtc0 lw mtc0 eret sp, s8, zero k0, 0(sp) k0, EPC k0, 4(sp) k0, Status Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-29 PIC32MX Family Reference Manual 8.10 EXTERNAL INTERRUPTS The interrupt controller supports five external interrupt-request signals (INT4-INT0). These inputs are edge sensitive, they require a low-to-high or a high-to-low transition to create an interrupt request. The INTCON register has five bits that select the polarity of the edge detection circuitry: INT4EP (INTCON<4>), INT3EP (INTCON<3>), INT2EP (INTCON<2>), INT1EP (INTCON<1>), and INT0EP (INTCON<0>). Note: Changing the external interrupt polarity may trigger an interrupt request. It is recommended that before changing the polarity, the user disables that interrupt, changes the polarity, clears the interrupt flag, and re-enables the interrupt. Example 8-12: Setting External Interrupt Polarity /* The following code example will set INT3 to trigger on a high to low transitio edge. The CPU must be set up for either multi or single vector interrupts to handle external interrupts */ IEC0CLR = 0x00008000; // disable INT3 INTCONCLR = 0x00000008; // clear the bit for falling edge trigger IFS0CLR = 0x00008000; // clear the interrupt flag IEC0SET = 0x00008000; // enable INT3 DS61108D-page 8-30 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.11 TEMPORAL PROXIMITY INTERRUPT COALESCING The PIC32MX CPU responds to interrupt events as if they are all immediately critical because the interrupt controller asserts the interrupt request to the CPU when the interrupt request occurs. The CPU immediately recognizes the interrupt if the current CPU priority is lower than the pending priority. Entering and exiting an ISR consumes clock cycles for saving and restoring context. Events are asynchronous with respect to the main program and have a limited possibility of occurring simultaneously or close together in time. This prevents the ability of a shared ISR to process multiple interrupts at one time. Temporal Proximity Interrupt uses the interrupt proximity timer, TPTMR, to create a temporal window in which a group of interrupts of the same, or lower, priority will be held off. This provides an opportunity to queue these interrupt requests and process them using tail-chaining single ISR. Figure 8-3 shows a block diagram of the temporal proximity interrupt coalescing. The interrupt priority group level that triggers the temporal proximity timer is set up in the TPC bits (INTCON<10:8>). TPC selects the interrupt group priority value, and those values below, that will trigger the temporal proximity timer to be reset and loaded with the value in TPTMR. After the timer is loaded with the value in TPTMR, reads to the TPTMR will indicate the current state of the timer. When the timer decrements to zero, the queued interrupt requests are serviced if IPL (Status<15:10>) is less than RIPL (Cause<15:10>). Figure 8-3: Temporal Proximity Interrupt Coalescing Block Diagram INTCON Latency 8 Value Proximity Timer Time Out Queued Interrupt Request Interrupt Registers First Interrupt Detect The user can activate temporal proximity interrupt coalescing by performing the following steps: • Set the TPC to the preferred priority level. (Setting TPC to zero will disable the proximity timer.) • Load the preferred 32-bit value to TPTMR The interrupt proximity timer will trigger when an interrupt request of a priority equal, or lower, matches the TPC value. Example 8-13: Temporal Proximity Interrupt Coalescing Example /* The following code example will set the Temporal Proximity Coalescing to trigger on interrupt priority level of 3 or below and the temporal timer to be set to 0x12345678. */ INTCONCLR = 0x00000700; TPTMPCLR = 0xFFFFFFFF; NTCONSET = 0x00000300; TPTMR = 0x12345678; // clear TPC // clear the timer // set TPC->3 // set the timer to 0x12345678 Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-31 PIC32MX Family Reference Manual 8.12 8.13 EFFECTS OF INTERRUPTS AFTER RESET 8.12.1 Device Reset All interrupt controller registers are forced to their reset states upon a device Reset. 8.12.2 Power-on Reset All interrupt controller registers are forced to their reset states upon a device Reset. 8.12.3 Watchdog Timer Reset All interrupt controller registers are forced to their reset states upon a device Reset. OPERATION IN POWER-SAVING AND DEBUG MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 8.13.1 Interrupt Operation in SLEEP Mode During SLEEP mode, the interrupt controller will only recognize interrupts from peripherals that can operate in SLEEP mode. Peripherals such as RTCC, Change Notice, External Interrupts, ADC, and SPI Slave can continue to operate in SLEEP mode and interrupts from these peripherals can be used to wake up the device. An interrupt with its Interrupt Enable bit set may switch the device to either RUN or IDLE mode, subject to its Interrupt Enable bit status and priority level. An interrupt event with its Interrupt Enable bit cleared or a priority of zero will not be recognized by the interrupt controller and cannot change device status. If the priority of the interrupt request is higher than the current processor priority level, the device will switch to RUN mode and processor will execute the corresponding interrupt request. If the proximity timer is enabled and the pending interrupt priority is less than the temporal proximity priority, the device will remain in SLEEP and the processor will not take the interrupt until after the proximity timer is expired. If the priority of the interrupt request is less than, or equal to, the current processor priority level, the device will switch to IDLE mode and the processor will remain halted. 8.13.2 Interrupt Operation in IDLE Mode During IDLE mode, interrupt events, with their respective Interrupt Enable bits set, may switch the device to RUN mode subject to its Interrupt Enable bit status and priority level. An interrupt event with its Interrupt Enable bit cleared or a priority of zero will not be recognized by the interrupt controller and cannot change device status. If the priority of the interrupt request is higher than the current CPU priority level, the device will switch to RUN mode and the CPU will execute the corresponding interrupt request. If the proximity timer is enabled and the pending interrupt priority is less than the temporal proximity priority, the device will remain in IDLE and the processor will not take the interrupt until after the proximity time has expired. If the priority of the interrupt request is less than, or equal to, the current CPU priority level, the device will remain in IDLE mode. The corresponding Interrupt Flag bits will remain set and the interrupt request will remain pending. DS61108D-page 8-32 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.13.3 Interrupt Operation in DEBUG Mode While the CPU is executing in Debug Exception mode (i.e., the application is halted), all interrupts, regardless of their priority level, are not taken and they will remain pending. Once the CPU exits Debug Exception mode, all pending interrupts will be taken in their order of priority. Note: The FRZ bit is readable and writable only when the CPU is executing in Debug Exception mode. In all other modes, the FRZ bit reads as ‘0’. If FRZ bit is changed during DEBUG mode, the new value does not take effect until the current Debug Exception mode is exited and re-entered. During the Debug Exception mode, the FRZ bit reads the state of the peripheral when entering DEBUG mode. 8.14 DESIGN TIPS Question 1: Can I just enable the interrupt in the IEC registers to start receiving interrupt requests? Answer 1: No, you must first enable system interrupts for the core to service any interrupt request. Then, when you enable the interrupt in the IEC register, you will receive interrupt requests. Question 2: When should I clear the interrupt request flag in my interrupt handler? Answer 2: You should clear the interrupt request flag as soon as you enter the routine. Handlers that service more than one interrupt request flag can copy the interrupt request flags into a local variable, clear the IFS register, and then service the request. 8 Question 3: After the proximity timer has counted down, which interrupt request is serviced? Answer 3: When the proximity timer reaches zero, the interrupt request of the highest priority will be serviced. Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-33 PIC32MX Family Reference Manual 8.15 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Interrupts module are: Title No related application notes at this time. Application Note # N/A Note: Visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. DS61108D-page 8-34 Preliminary © 2008 Microchip Technology Inc. Section 8. Interrupts 8.16 REVISION HISTORY Revision A (August 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x. Revision D (June 2008) Revise Register 8-1, FRZ note; Revise Examples 8-1 and 8-2; Change Reserved bits from “Maintain as” to “Write”. 8 Interrupts © 2008 Microchip Technology Inc. Preliminary DS61108D-page 8-35 PIC32MX Family Reference Manual NOTES: DS61108D-page 8-36 Preliminary © 2008 Microchip Technology Inc. Section 9. Watchdog Timer and Power-up Timer HIGHLIGHTS This section of the manual contains the following topics: 9.1 Introduction................................................................................................................ 9-2 9.2 Watchdog Timer and Power-up Timer Control Registers .......................................... 9-3 9.3 Operation................................................................................................................... 9-9 9.4 Interrupt and Reset Generation ............................................................................... 9-13 9.5 I/O Pins .................................................................................................................... 9-14 9.6 Operation in DEBUG and Power-Saving Modes ..................................................... 9-14 9.7 Effects of Various Resets......................................................................................... 9-15 9.8 Design Tips .............................................................................................................. 9-15 9.9 Related Application Notes ....................................................................................... 9-16 9.10 Revision History....................................................................................................... 9-17 9 Watchdog Timer Power-up Timer © 2008 Microchip Technology Inc. Preliminary DS61114D-page 9-1 PIC32MX Family Reference Manual 9.1 INTRODUCTION The PIC32MX Watchdog Timer (WDT) and Power-up Timer (PWRT) modules are described in this section. Refer to Figure 9-1 for a block diagram of the WDT and PWRT. The WDT, when enabled, operates from the internal Low-Power RC (LPRC) oscillator clock source. The WDT can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from SLEEP or IDLE mode. The PWRT, when active, holds the device in Reset for a 64 millisecond period after the normal Power-on Reset (POR) start-up period is complete. This allows additional time for the Primary Oscillator (POSC) clock source and the power supply to stabilize. Like the WDT, the PWRT also uses the LPRC as its clock source. Refer to Figure 9-1 for details. Following are some of the key features of the WDT module: • Configuration or software controlled • User configurable time-out period • Can wake the device from SLEEP or IDLE Figure 9-1: Watchdog and Power-up Timer Block Diagram PWRT Enable WDT Enable LPRC Oscillator WDTCLR = 1 WDT Enable Wake 1:64 Output PWRT Enable LPRC Control PWRT Clock 1 25-Bit Counter 25 WDT Counter Reset 0 Device Reset 1 NMI (Wake-up) Power Save Decoder FWDTPS<4:0>(DEVCFG1<20:16>) DS61114D-page 9-2 Preliminary © 2008 Microchip Technology Inc. Section 9. Watchdog Timer and Power-up Timer 9.2 WATCHDOG TIMER AND POWER-UP TIMER CONTROL REGISTERS The WDT and PWRT modules consist of the following Special Function Registers (SFRs): • WDTCON: Watchdog Timer Control Register WDTCONCLR, WDTCONSET, WDTCONINV: Atomic Bit Manipulation Registers for WDTCON • RCON: Resets Control and Status Register RCONCLR, RCONSET, RCONINV: Atomic Bit Manipulation Registers for RCON • DEVCFG1: Device Configuration Register The following table provides a brief summary of WDT and PWRT-related registers. Corresponding registers appear after the summary, followed by a detailed description of each registers. Table 9-1: Watchdog Timer and Power-up Timer SFR Summary Name Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 WDTCON — — — — — — — — — — — — — — — — 15:8 ON — — — — — — — 7:0 — WDTPS<4:0> — WDTCLR WDTCONCLR 31:0 WDTCONSET 31:0 Write clears selected bits in WDTCON, read yields an undefined value Write sets selected bits in WDTCON, read yields an undefined value WDTCONINV 31:0 Write inverts selected bits in WDTCON, read yields an undefined value RCON — — — — — — — — — — — — — — — — RCONCLR RCONSET RCONINV 15:8 TRAPR 7:0 EXTR 31:0 31:0 31:0 — — — — — CM SWR — WDTO SLEEP IDLE BOR Write clears selected bits in RCON, read yields an undefined value Write sets selected bits in RCON, read yields an undefined value Write inverts selected bits in RCON, read yields an undefined value VREGS POR DEVCFG1 31:24 — — — — — — — — 23:16 FWDTEN — — FWDTPS<4:0> 9 15:8 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMD<1:0> 7:0 IESO — FSOSCEN — — FNOSC<2:0> Watchdog Timer Power-up Timer © 2008 Microchip Technology Inc. Preliminary DS61114D-page 9-3 PIC32MX Family Reference Manual Register 9-1: WDTCON: Watchdog Timer Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 r-x r-x r-x r-x R-1 R-1 R-0 ON — — — — — — — bit 15 bit 8 r-x — bit 7 R-x R-x R-x R-x R-x r-0 R/W-0 WDTPS<4:0> — WDTCLR bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14-7 bit 6-2 bit 1 bit 0 Reserved: Write ‘0’; ignore read ON: Watchdog Timer Enable bit 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if it was enabled in software Note 1: A read of this bit will result in a ‘1’ if the WDT is enabled by the device configuration or by software. 2: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. Reserved: Write ‘0’; ignore read WDTPS<4:0>: Watchdog Timer Postscaler Value. On Reset these bits are set to the values of the FWTDPS[4:0] of Configuration bits reserved: Write ‘0’; ignore read WDTCLR: Watchdog Timer Reset bit 1 = Writing a ‘1’ will clear the WDT. 0 = Software cannot force this bit to a ‘0’ DS61114D-page 9-4 Preliminary © 2008 Microchip Technology Inc. Section 9. Watchdog Timer and Power-up Timer Register 9-2: WDTCONCLR: Comparator Control Clear Register Write clears selected bits in WDTCON, read yields undefined value bit 31 bit 0 bit 31-0 Clear selected bits in WDTCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in WDTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: WDTCONCLR = 0x00008001 clears bits 15 and 0 in WDTCON register. Register 9-3: WDTCONSET: Comparator Control Set Register Write sets selected bits in WDTCON, read yields undefined value bit 31 bit 0 bit 31-0 Set selected bits in WDTCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in WDTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: WDTCONSET = 0x00008001 sets bits 15 and 0 in WDTCON register. Register 9-4: WDTCONINV: Comparator Control Invert Register Write inverts selected bits in WDTCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in WDTCON 9 A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in WDTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: WDTCONINV = 0x00008001 inverts bits 15 and 0 in WDTCON register. Watchdog Timer Power-up Timer © 2008 Microchip Technology Inc. Preliminary DS61114D-page 9-5 PIC32MX Family Reference Manual Register 9-5: RCON: Resets Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 r-x r-x r-x r-x R-0 R/W-0 R/W-0 TRAPR — — — — — CM VREGS bit 15 bit 8 R/W-0 R/W-0 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EXTR SWR — WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 4 WDTO: Watchdog Time-out bit 1 = A WDT time out has occurred since either the device was powered up or the WDTO bit was last cleared by software 0 = A WDT time out has not occurred since either the WDTO bit was cleared by software or the device was reset bit 3 SLEEP: SLEEP Event bit 1 = The device was in SLEEP since either the device was powered up or the SLEEP bit was last cleared by software 0 = The device was not in SLEEP since either the SLEEP bit was cleared by software or the device was reset bit 2 IDLE: IDLE Event bit 1 = The device has been in IDLE mode since either the device was powered up or the IDLE bit was last cleared by software 0 = The device has not been in IDLE mode since either the IDLE bit was cleared by software or the device was reset DS61114D-page 9-6 Preliminary © 2008 Microchip Technology Inc. Section 9. Watchdog Timer and Power-up Timer Register 9-6: RCONCLR: Comparator Control Clear Register Write clears selected bits in RCON, read yields undefined value bit 31 bit 0 bit 31-0 Clear selected bits in RCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in RCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RCONCLR = 0x00008001 clears bits 15 and 0 in RCON register. Register 9-7: RCONSET: Comparator Control Set Register Write sets selected bits in RCON, read yields undefined value bit 31 bit 0 bit 31-0 Set selected bits in RCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in RCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RCONSET = 0x00008001 sets bits 15 and 0 in RCON register. Register 9-8: RCONINV: Comparator Control Invert Register Write inverts selected bits in RCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in RCON 9 A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in RCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RCONINV = 0x00008001 inverts bits 15 and 0 in RCON register. Watchdog Timer Power-up Timer © 2008 Microchip Technology Inc. Preliminary DS61114D-page 9-7 PIC32MX Family Reference Manual Register 9-9: DEVCFG1 Device Configuration Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 R/P-1 r-1 FWDTEN — bit 23 r-x R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — WDTPS<4:0> bit 16 R/P-1 R/P-1 FCKSM<1:0> bit 15 R/P-1 R/P-1 FPBDIV<1:0> r-x R/P-1 R/P-1 R/P-1 — OSCIOFNC POSCMD<1:0> bit 8 R/P-1 IESO bit 7 r-x R/P-1 r-x — FSOSCEN — r-x R/P-1 R/P-1 R/P-1 — FNOSC<2:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 23 bit 22 bit 20-16 FWDTEN: Watchdog Timer Enable bit 1 = WDT is enabled and cannot be disabled by software 0 = WDT is not enabled and can be enabled in software Reserved: Write ‘1’; ignore read FWDTPS<4:0>: Watchdog Timer Postscale Select bits. These bits define the WDT period. 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = 10100 DS61114D-page 9-8 Preliminary © 2008 Microchip Technology Inc. Section 9. Watchdog Timer and Power-up Timer 9.3 OPERATION If enabled, the WDT will increment until it overflows or “times out”. A WDT time out will force a device Reset, except during SLEEP or IDLE mode. To prevent a WDT time-out Reset, the user must periodically clear the WDT by setting the WDTCLR (WDTCON<0>) bit. To prevent a device Reset the WDTCLR bit must be periodically set within the selected WDT period. Table 9-2: Results of a WDT Time-out Event for Available Modes of Device Operation Device Mode Device Reset Generated Non-Maskable Interrupt Generated WDTO(1) Bit Set SLEEP(1) Bit Set IDLE(1) Bit Set Device Registers Reset Awake Yes No Yes No No Yes SLEEP No Yes Yes Yes No No IDLE No Yes Yes No Yes No Note 1: Status bits are in the RCON register. . Note: The LPRC oscillator is automatically enabled whenever the WDT is enabled. 9.3.1 Enabling and Disabling the WDT The WDT is either enabled or disabled by the device configuration, or controlled via software by writing to the WDTCON register. 9.3.2 Device Configuration Controlled WDT If the FWDTEN device Configuration bit (DEVCFG1<23>) is set, the WDT is always enabled. The WDT ON control bit (WDTCON<15>) will reflect this by reading a ‘1’. In this mode, the ON bit cannot be cleared in software or any form of Reset. To disable the WDT in this mode, the configuration must be rewritten to the device. Note: The default state for the WDT on an unprogrammed device is WDT enabled. 9.3.3 Software Controlled WDT If the FWDTEN device Configuration bit (DEVCFG1<23>) has a value of ‘0’, the WDT can be enabled and disabled by software. In this mode, the ON bit (WDTCON<15>) reflects the status 9 of the WDT under software control. A value of ‘1’ indicates the WDT is enabled and a ‘0’ indicates it is disabled. The WDT is enabled in software by setting WDT ON control bit. WDT ON control bit is cleared on any device Reset. The bit is not cleared on a wake-up from SLEEP mode or an exit from IDLE mode. The software WDT option allows the user to enable the WDT for critical code segments, and disable the WDT during non-critical segments, for maximum power savings. The WDT ON control bit can also be used to disable the WDT while the device is awake to eliminate the need for WDT servicing, and then re-enable it before the device is put into IDLE or SLEEP mode to wake-up the device at a later time. Watchdog Timer Power-up Timer © 2008 Microchip Technology Inc. Preliminary DS61114D-page 9-9 PIC32MX Family Reference Manual Example 9-1: Sample WDT Initialization and Servicing // This code fragment assumes the WDT was not enabled by // the device configuration // The Postscaler value must be set with the device configuration WDTCONSET = 0x8000; // Turn on the WDT main() { WDTCONSET = 0x01; // Service the WDT ... User code goes here ... } DS61114D-page 9-10 Preliminary © 2008 Microchip Technology Inc. Section 9. Watchdog Timer and Power-up Timer 9.3.4 Resetting the WDT Timer The WDT is cleared by any of the following: • On any device Reset. • By a WDTCONSET = 0x01, or equivalent instruction, during normal execution. Refer to Example 9-2. • Exiting from IDLE or SLEEP mode, due to an interrupt. Note: The WDT timer is not cleared when the device enters a Power-Saving mode. The WDT should be serviced prior to entering a Power-Saving mode. Example 9-2: Determining Power-Saving Mode After a Reset OSCCONSET = 0x10; // set Power-Saving mode to SLEEP // OSCCONCLR = 0x10; // set Power-Saving mode to IDLE WDTCONSET = 0x8000; // Enable WDT while (1) { ... user code ... WDTCONSET = 0x01; asm volatile( “wait” ); // service the WDT // put device is selected Power-Saving mode // code execution will resume here after wake ... user code ... } if ( RCON & 0x18 ) { asm volatile( “eret” ); } if ( RCON & 0x14 ) { asm volatile( “eret” ); } if ( RCON & 0x10 ) { } // The following code fragment is at the top of the // device start-up code // The WDT caused a wake-from-SLEEP // return from interrupt 9 // The WDT caused a wake-from-IDLE // return from interrupt // The WDT timed-out while the device was awake Watchdog Timer Power-up Timer © 2008 Microchip Technology Inc. Preliminary DS61114D-page 9-11 PIC32MX Family Reference Manual 9.3.5 WDT Period Selection The WDT clock source is the internal LPRC oscillator, which has a nominal frequency of 31.25 kHz. This creates a nominal time-out period for the WDT (TWDT) of 1 millisecond when no postscaler is used. Note: The WDT time-out period is directly related to the frequency of the LPRC oscillator. The frequency of the oscillator will vary as a function of device operating voltage and temperature. Please refer to the specific device data sheet for LPRC oscillator clock frequency specifications. 9.3.5.1 WDT Postscalers The WDT has a 5-bit postscaler to create a wide variety of time-out periods. This postscaler provides 1:1 through 1:1048576 divider ratios. Time-out periods that range between 1 ms and 1048.576 seconds (nominal) can be achieved using the postscaler. The postscaler settings are selected using the FWDTPS<4:0> Configuration bits in the DEVCFG1 device configuration register. For more information on the WDT Configuration bits, please refer to Section 32. “Configuration”. Equation 9-1: WDT Time-out Period Calculation WDT Period = 1 ms • 2 Prescaler The time-out period of the WDT is calculated as follows: Table 9-3: WDT Time-out Period vs. Postscaler Settings(1, 2) FWDTPS<4:0> Postscaler Ratio Time-out Period 00000 1:1 1 ms 00001 1:2 2 ms 00010 1:4 4 ms 00011 1:8 8 ms 00100 1:16 16 ms 00101 1:32 32 ms 00110 1:64 64 ms 00111 1:128 128 ms 01000 1:256 256 ms 01001 1:512 512 ms 01010 1:1024 1.024 s 01011 1:2048 2.048 s 01100 1:4096 4.096 s 01101 1:8192 8.192 s 01110 1:16384 16.384 s 01111 1:32768 32.768 s 10000 1:65536 65.536 s 10001 1:131072 131.072 s 10010 1:262144 262.144 s 10011 1:524288 524.288 s 10100 1:1045876 1048.576 s Note 1: All other combinations will result in operation as if the prescaler was set to 10100. 2: The periods listed are based on a 32 kHz (nominal) input clock. DS61114D-page 9-12 Preliminary © 2008 Microchip Technology Inc. Section 9. Watchdog Timer and Power-up Timer 9.3.6 PWRT Timer Operation The PWRT provides an additional delay between the device POR delay and the beginning of code execution to allow the oscillator to stabilize. Devices that do not have an on-board voltage regulator have the PWRT permanently enabled. Devices that incorporate an on-board voltage regulator automatically enable the PWRT only when the on-board voltage regulator is disabled. The PWRT cannot be enabled or disabled by the device configuration or software. 9.4 INTERRUPT AND RESET GENERATION The WDT will either cause an Non-Maskable Interrupt (NMI) or a device Reset when it expires. The Power-Saving mode of the device determines which event occurs. The PWRT does not generate interrupts or Resets. 9.4.1 Watchdog Timer Reset When the WDT expires and the device is not in SLEEP or IDLE mode, a device Reset is generated. The CPU code execution jumps to the Device Reset Vector and the registers and peripherals are forced to their Reset values. 9.4.2 Watchdog Timer NMI When the WDT expires in SLEEP or IDLE mode, a NMI is generated. The NMI causes the CPU code execution to jump to the Device Reset Vector. While the NMI shares the same Vector as a device Reset, registers and peripherals are not reset. To cause a WDT time out in SLEEP mode to act like an interrupt, a return-from-interrupt (RETFIE) instruction may be used in the start-up code after the event was determined to be a WDT wake-up. This will cause code execution to continue with the opcode, following the WAIT instruction that put the device into Power-Saving mode. Refer to Example 9-2. 9.4.3 Determining Device Status When a WDT Event Has Occurred To detect a WDT Reset, the WDTO (RCON<4>), SLEEP (RCON<3>), and IDLE (WDTCON<2>) bits must be tested. If the WDTO bit is a ‘1’, the event was due to a WDT time out. The SLEEP and IDLE bits can then be tested to determine whether the WDT event occurred while the device was awake or if it was in SLEEP or IDLE mode. The user should clear the WDTO, SLEEP, and IDLE bits in the Interrupt Service Routine (ISR) to allow software to correctly determine the source of a subsequent WDT event. 9.4.4 Wake From Power-Saving Mode By a Non-WDT Event 9 When the device is awakened from Power-Saving mode by an interrupt, the WDT is cleared. Practically, this extends the time until the next WDT-generated device Reset occurs, so that an unintended WDT event does not occur too soon after the interrupt that woke the device. Watchdog Timer Power-up Timer © 2008 Microchip Technology Inc. Preliminary DS61114D-page 9-13 PIC32MX Family Reference Manual 9.5 I/O PINS The PWRT is disabled when the internal voltage regulator is enabled. A device without an internal voltage regulator will always have the PWRT enabled. A device with an internal voltage regulator will enable the PWRT when the VREG pin is tied to ground (to disable the regulator). 9.6 OPERATION IN DEBUG AND POWER-SAVING MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 9.6.1 WDT Operation in Power-Saving Modes The WDT can be used to wake the device from SLEEP or IDLE. The WDT continues to operate in Power-Saving mode. A time out can then be used to wake the device. This allows the device to remain in SLEEP mode until the WDT expires or another interrupt wakes the device. If the device does not re-enter SLEEP or IDLE mode following a wake-up, the WDT must be disabled or periodically serviced to prevent a device Reset. 9.6.2 WDT Operation in SLEEP Mode The WDT, if enabled, will continue operation in SLEEP mode. The WDT may be used to wake the device from SLEEP. When the WDT times out in SLEEP, a NMI is generated and the WDTO (RCON<4>) bit is set. The NMI vectors execution to the CPU start-up address, but does not reset registers or peripherals. The SLEEP (RCON<3>) status bit will be set indicating the device was in SLEEP. These bits allow the start-up code to determine the cause of the wake-up. 9.6.3 WDT Operation in IDLE Mode The WDT, if enabled, will continue operation in IDLE mode. The WDT may be used to wake the device from IDLE. When the WDT times out in IDLE, a NMI is generated and the WDTO (RCON<4>) bit is set. The NMI vectors execution to the CPU start-up address, but does not reset registers or peripherals. The IDLE (RCON<2>) status bit will be set indicating the device was in IDLE. These bits allow the start-up code to determine the cause of the wake-up. 9.6.4 Time Delays During Wake-up The delay between a WDT time-out and the beginning of code execution depends on the Power-Saving mode. There will be a time delay between the WDT event in SLEEP mode and the beginning of code execution. The duration of this delay consists of the start-up time for the oscillator in use and the PWRT delay, if it is enabled. Unlike a wake-up from SLEEP mode, there are no time delays associated with wake-up from IDLE mode. The system clock is running during IDLE mode; therefore, no start-up delays are required at wake-up. 9.6.5 WDT Operation in DEBUG Mode The WDT is always frozen and therefore does not time-out in DEBUG mode. DS61114D-page 9-14 Preliminary © 2008 Microchip Technology Inc. Section 9. Watchdog Timer and Power-up Timer 9.7 EFFECTS OF VARIOUS RESETS Any form of device Reset will clear the WDT. The Reset will return the WDTCON register to the default value and the WDT will be disabled unless it is enabled by the device configuration. Note: After a device Reset, the WDT ON (WDTCON<15>) bit will reflect the state of the FWDTEN (DEVCFG1<23>) bit. 9.8 DESIGN TIPS Question 1: Why does the device reset even though I reset the WDT in my main software loop? Answer: Make sure that the timing of the software loop that clears the WDTCLR (WDTCON<0>) bit meets the minimum time-out specification of the WDT (not the typical value) to ensure operation at different voltage and temperatures. Also, make sure that interrupt processing time has been accounted for. Question 2: What should my software do before entering SLEEP or IDLE mode? Answer: Make sure that the sources intended to wake the device have their IEC bits set. In addition, make sure that the particular source of interrupt has the ability to wake the device. Some sources do not function when the device is in SLEEP mode. If the device is to be placed in IDLE mode, make sure that the Stop In Idle (SIDL) control bit for each device peripheral is properly set. These control bits determine whether the peripheral will continue operation in IDLE mode. See the individual peripheral sections of this manual for details. If the WDT is to be used in SLEEP mode, then the WDT should be serviced before entering sleep to provide a complete WDT interval before the device exits SLEEP mode. Question 3: How do I tell if the WDT or other peripheral woke the device from SLEEP or IDLE mode? Answer: Most interrupts have their own unique vector. The vector is determined by the interrupt source. For interrupts that share a vector, the IFS bits for each enabled interrupt source (that shares the vector) can be polled to determine: a.) the source of the interrupt and b.) the source of the wake-up. If the WDT woke the device, the user’s start-up code must check for the WDT time-out event, WDTO (RCON<4>), and branch accordingly. 9 Watchdog Timer Power-up Timer © 2008 Microchip Technology Inc. Preliminary DS61114D-page 9-15 PIC32MX Family Reference Manual 9.9 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the WDT and PWRT modules are: Title No related application notes at this time. Application Note # N/A Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. DS61114D-page 9-16 Preliminary © 2008 Microchip Technology Inc. Section 9. Watchdog Timer and Power-up Timer 9.10 REVISION HISTORY Revision A (September 2007) This is the initial released revision of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x; Revision D (June 2008) Delete note from Section 9.3; Revise Example 9-2; Change Reserved bits from “Maintain as” to “Write”; Added Note to ON bit (WDTCON Register). 9 Watchdog Timer Power-up Timer © 2008 Microchip Technology Inc. Preliminary DS61114D-page 9-17 PIC32MX Family Reference Manual NOTES: DS61114D-page 9-18 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes HIGHLIGHTS This section of the manual contains the following topics: 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 Introduction.............................................................................................................. 10-2 Power-Saving Modes Control Registers.................................................................. 10-3 Operation of Power-Saving Modes........................................................................ 10-12 Interrupts................................................................................................................ 10-19 I/O Pins Associated with Power-Saving Modes..................................................... 10-20 Operation in DEBUG Mode ................................................................................... 10-20 Resets.................................................................................................................... 10-20 Design Tips ............................................................................................................ 10-21 Related Application Notes ..................................................................................... 10-22 Revision History..................................................................................................... 10-23 Power-Saving Modes 10 © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-1 PIC32MX Family Reference Manual 10.1 INTRODUCTION This section describes the Power-Saving modes of operation for the PIC32MX device family. The PIC32MX devices have nine Low-Power modes in two categories that allow the user to balance power consumption with device performance. In all of the modes listed below, the device can select the desired Power-Saving mode via software. 10.1.1 CPU Running Modes In the CPU Running modes, the CPU is running and peripherals can optionally be switched ON or OFF. • FRC RUN mode: the CPU is clocked from the FRC clock source with or without postscalers. • LPRC RUN mode: the CPU is clocked from the LPRC clock source. • SOSC RUN mode: the CPU is clocked from the SOSC clock source. • Peripheral Bus Scaling mode: Peripherals are clocked at programmable fraction of the CPU clock (SYSCLK). 10.1.2 CPU Halted Modes In the CPU Halted modes, the CPU is halted. Depending on the mode, peripherals can continue to operate or be halted as well. • POSC IDLE mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. • FRC IDLE mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. • SOSC IDLE mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. • LPRC IDLE mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. • SLEEP Mode: the CPU, the system clock source, and any peripherals that operate from the system clock source, are halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device. DS61130E-page 10-2 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes 10.2 POWER-SAVING MODES CONTROL REGISTERS Power-Saving modes control consists of the following Special Function Registers (SFRs): • OSCCON: Control Register for the Oscillators Module OSCCONCLR, OSCCONSET, OSCCONINV: Atomic Bit Manipulation Write-only Registers for OSCCON • WDTCON: Control Register for the Watchdog Timer Module WDTCONCLR, WDTCONSET, WDTCONINV: Atomic Bit Manipulation Write-only Registers for WDTCON • RCON: Control Register for the Resets Module RCONCLR, RCONSET, RCONINV: Atomic Bit Manipulation Write-only Registers for RCON The following table summarizes all Power-Saving-modes-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Table 10-1: Name Power-Saving Modes SFR Summary Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 OSCCON 31:24 — 23:16 — — SOSCRDY PLLODIV<2:0> — PBDIV<1:0> FRCDIV<2:0> PLLMULT<2:0> 15:8 — COSC<2:0> — NOSC<2:0> 7:0 CLKLOCK ULOCK LOCK SLPEN CF UFRCEN SOSCEN OSWEN OSCCONCLR 31:0 OSCCONSET 31:0 OSCCONINV 31:0 WDTCON 31:24 23:16 15:8 7:0 WDTCONCLR 31:0 WDTCONSET 31:0 WDTCONINV 31:0 RCON 31:24 23:16 15:8 7:0 RCONCLR 31:0 RCONSET 31:0 RCONINV 31:0 — — ON — — — — EXTR Write clears selected bits in OSCCON, read yields undefined value Write sets selected bits in OSCCON, read yields undefined value Write inverts selected bits in OSCCON, read yields undefined value — — — — — — — — — — — — — — — — — — SWDTPS<4:0> — Write clears selected bits in WDTCON; read yields undefined value Write sets selected bits in WDTCON; read yields undefined value Write inverts selected bits in WDTCON; read yields undefined value — — — — — — — — — — — — — — — — — CM SWR — WDTO SLEEP IDLE BOR Write clears selected bits in RCON; read yields undefined value Write sets selected bits in RCON; read yields undefined value Write inverts selected bits in RCON; read yields undefined value — — — WDTCLR — — VREGS POR 10 Power-Saving Modes © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-3 PIC32MX Family Reference Manual Register 10-1: OSCCON: Oscillator Control Register r-x r-x R/W-x R/W-x — — PLLODIV<2:0> bit 31 R/W-x R/W-0 R/W-0 FRCDIV<2:0> R/W-1 bit 24 r-x R-0 r-x — SOSCRDY — bit 23 R/W-x R/W-x PBDIV<1:0> R/W-x R/W-x PLLMULT<2:0> R/W-x bit 16 r-x — bit 15 R-0 R-0 R-0 COSC<2:0> r-x R/W-x R/W-x R/W-x — NOSC<2:0> bit 8 R/W-0 CLKLOCK bit 7 R-0 ULOCK R-0 LOCK R/W-0 SLPEN R/W-0 CF R/W-0 UFRCEN R/W-x SOSCEN R/W-0 OSWEN bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 29-27 bit 26-24 bit 23 bit 22 bit 21 PLLODIV<2:0>: Output Divider for PLL bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 Note: On Reset these bits are set to the value of the FPLLODIV Configuration bits (DEVCFG2<18:16>) FRCDIV<2:0>: Fast Internal RC Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 Reserved: Write ‘0’; ignore read SOSCRDY: Secondary Oscillator Ready Indicator bit 1 = Indicates that the Secondary Oscillator is running and is stable 0 = Secondary oscillator is either turned off or is still warming up Unimplemented: Read as ‘0’ DS61130E-page 10-4 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes Register 10-1: OSCCON: Oscillator Control Register (Continued) bit 20-19 bit 18-16 bit 15 bit 14-12 bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 PBDIV<1:0>: Peripheral Bus Clock Divisor 11 = PBCLK is SYSCLK divided by 8(default) 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note: On Reset these bits are set to the value of the Configuration bits (DEVCFG1<13:12>). PLLMULT<2:0>: PLL Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 Note: On Reset these bits are set to the value of the PLLMULT Configuration bits (DEVCFG2<6:4>) Reserved: Write ‘0’; ignore read COSC<2:0>: Current Oscillator Selection bits 111 = Fast Internal RC Oscillator divided by OSCCON bits 110 = Fast Internal RC Oscillator divided by 16 101 = Low-Power Internal RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Fast RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Fast RC Oscillator (FRC) Note: On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). Reserved: Write ‘0’; ignore read NOSC<2:0>: New Oscillator Selection bits 111 = Fast Internal RC Oscillator divided by OSCCON (FRCDIV> bits 110 = Fast Internal RC Oscillator divided by 16 101 = Low Power Internal RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Fast Internal RC Oscillator (FRC) On Reset these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>). CLKLOCK: Clock Selection Lock Enable bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified ULOCK: USB PLL Lock Status bit 1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled LOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled SLPEN: SLEEP Mode Enable bit 1 = Device will enter SLEEP mode when a WAIT instruction is executed 0 = Device will enter IDLE mode when a WAIT instruction is executed 10 Power-Saving Modes © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-5 PIC32MX Family Reference Manual Register 10-1: OSCCON: Oscillator Control Register (Continued) bit 3 CF: Clock Fail Detect bit 1 = FSCM (Fail Safe Clock Monitor) has detected a clock failure 0 = No clock failure has been detected bit 2 UFRCEN: USB FRC Clock Enable bit 1 = Enable FRC as the clock source for the USB clock source 0 = Use the primary oscillator or USB PLL as the USB clock source bit 1 SOSCEN: 32.768 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator Note: On Reset this bit is set to the value of the FSOSCEN Configuration bit (DEVCFG1<5>). bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC2:NOSC0 bits 0 = Oscillator switch is complete DS61130E-page 10-6 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes Register 10-2: OSCCONCLR: Programming Control Clear Register Write clears selected bits in OSCCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in OSCCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in OSCCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: OSCCONCLR = 0x00000001 will clear bit 0 in OSCCON register. Register 10-3: OSCCONSET: Programming Control Set Register Write sets selected bits in OSCCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in OSCCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in OSCCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: OSCCONSET = 0x00000001 will set bit 0 in OSCCON register. Register 10-4: OSCCONINV: Programming Control Invert Register Write inverts selected bits in OSCCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in OSCCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in OSCCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: OSCCONINV = 0x00000001 will invert bit 0 in OSCCON register. 10 Power-Saving Modes © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-7 PIC32MX Family Reference Manual Register 10-5: WDTCON: WATCHDOG TIMER CONTROL REGISTER r-x — bit 31 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 r-x r-x r-x r-x r-x r-x r-x ON — — — — — — — bit 15 bit 8 r-x — bit 7 R-x R-x R-x R-x R-x r-0 R/W-0 SWDTPS<4:0> — WDTCLR bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 15 ON: Watchdog Peripheral On bit 1 = Watchdog peripheral is enabled. The status of other bits in the register are not affected by setting this bit. The LPRC oscillator will not be disabled when entering Sleep. 0 = Watchdog peripheral is disabled and not drawing current. SFR modifications are allowed. The status of other bits in this register are not affected by clearing this bit. Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. DS61130E-page 10-8 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes Register 10-6: WDTCONCLR: Comparator Control Clear Register Write clears selected bits in WDTCON, read yields undefined value bit 31 bit 0 bit 31-0 Clear selected bits in WDTCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in WDTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: WDTCONCLR = 0x00008001 clears bits 15 and 0 in WDTCON register. Register 10-7: WDTCONSET: Comparator Control Set Register Write sets selected bits in WDTCON, read yields undefined value bit 31 bit 0 bit 31-0 Set selected bits in WDTCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in WDTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: WDTCONSET = 0x00008001 sets bits 15 and 0 in WDTCON register. Register 10-8: WDTCONINV: Comparator Control Invert Register Write inverts selected bits in WDTCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in WDTCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in WDTCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: WDTCONINV = 0x00008001 inverts bits 15 and 0 in WDTCON register. 10 Power-Saving Modes © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-9 PIC32MX Family Reference Manual Register 10-9: RCON: RESETS CONTROL REGISTER r-x — bit 31 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 r-x — bit 15 r-x r-x r-x r-x r-0 R/W-0 R/W-0 — — — — — CM VREGS bit 8 R/W-0 R/W-0 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EXTR SWR — WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 3 SLEEP: Wake from Sleep bit 1 = The device woke up from SLEEP mode 0 = The device did not wake from SLEEP mode Note: Must clear this bit to detect future wake ups from SLEEP. bit 2 IDLE: Wake from IDLE bit 1 = The device woke up from IDLE mode 0 = The device did not wake from IDLE mode Note: Must clear this bit to detect future wake ups from IDLE. DS61130E-page 10-10 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes Register 10-10: RCONCLR: RCON Clear Register Write clears selected bits in RCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in RCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in RCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RCONCLR = 0x0000000C will clear bits 3 and 2 in RCON register. Register 10-11: RCONSET: RCON Set Register Write sets selected bits in RCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in RCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in RCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RCONSET = 0x0000000C will set bits 3 and 2 in RCON register. Register 10-12: RCONINV: RCON Invert Register Write inverts selected bits in RCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in RCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in RCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: RCONINV = 0x0000000C will invert bits 3 and 2 in RCON register. 10 Power-Saving Modes © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-11 PIC32MX Family Reference Manual 10.3 OPERATION OF POWER-SAVING MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. The PIC32MX device family has nine Power-Saving modes. The purpose of all the Power-Saving modes is to reduce power consumption by reducing the device clock frequency. To achieve this, multiple low-frequency clock sources can be selected. In addition, the peripherals and CPU can be halted or disabled to further reduce power consumption. 10.3.1 SLEEP Mode SLEEP mode has the lowest power consumption of the device Power-Saving operating modes. The CPU and most peripherals are halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep. Some of the characteristics of SLEEP mode are as follows: • The CPU is halted. • The system clock source is typically shut down. See 10.3.1.1 “Oscillator Shutdown in SLEEP Mode” for specific information. • There can be a wake-up delay based on the oscillator selection (refer to Table 10-2). • The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. • The BOR circuit, if enabled, remains operative during SLEEP mode. • The WDT, if enabled, is not automatically cleared prior to entering SLEEP mode. • Some peripherals can continue to operate in SLEEP mode. These peripherals include I/O pins that detect a change in the input signal, WDT, RTCC, ADC, UART, and peripherals that use an external clock input or the internal LPRC oscillator. • I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep. • The USB module can override the disabling of the POSC or FRC. Refer to the USB section for specific details. • Modules can be individually disabled by software prior to entering SLEEP in order to further reduce consumption. The processor will exit, or ‘wake-up’, from SLEEP on one of the following events: • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. • On any form of device Reset. • On a WDT time-out. See 10.4.2 “Wake-up from SLEEP or IDLE on Watchdog Time-out (NMI)”. If the interrupt priority is lower than or equal to current priority, the CPU will remain halted, but the PBCLK will start running and the device will enter in IDLE mode. Refer Example 10-1 for example code. Note: There is no FRZ mode for this module. DS61130E-page 10-12 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes 10.3.1.1 Oscillator Shutdown in SLEEP Mode The criteria for the device disabling the clock source in SLEEP are: the oscillator type, peripherals using the clock source, and (for select sources) the clock enable bit. • If the CPU clock source is POSC, it is turned off in SLEEP. See Table 10-2 for applicable delays when waking from SLEEP. The USB module can override the disabling of the POSC or FRC. Refer to the USB section for specific details. • If the CPU clock source is FRC, it is turned off in SLEEP. See Table 10-2 for applicable delays when waking from SLEEP. The USB module can override the disabling of the POSC or FRC. Refer to the USB section for specific details. • If the CPU clock source is SOSC, it will be turned off if the SOSCEN bit is not set. See Table 10-2 for applicable delays when waking from SLEEP. • If the CPU clock source is LPRC, it will be turned off if the clock source is not being used by a peripheral that will be operating SLEEP such as the WDT. See Table 10-2 for applicable delays when waking from SLEEP. 10.3.1.2 Clock Selection on Wake-up from SLEEP The processor will resume code execution and use the same clock source that was active when SLEEP mode was entered. The device is subject to a start-up delay if a crystal oscillator and/or PLL is used as a clock source when the device exits SLEEP. 10.3.1.3 Delay on Wake-up from SLEEP The oscillator start-up and Fail-Safe Clock Monitor delays, if enabled associated with waking up from SLEEP mode are shown in Table 10-2. Table 10-2: Delay Times for Exit from Sleep Mode Clock Source Oscillator Delay EC, EXTRC EC + PLL XT + PLL XT, HS, XTL LP (OFF during Sleep) LP (ON during Sleep) FRC, LPRC — TLOCK TOST + TLOCK TOST TOST — — FSCM Delay — TFSCM TFSCM TFSCM TFSCM — — Note: Please refer to the “Electrical Specifications” section of the PIC32MX device data sheet for TPOR, TFSCM and TLOCK specification values. 10.3.1.4 Wake-up from SLEEP Mode with Crystal Oscillator or PLL If the system clock source is derived from a crystal oscillator and/or the PLL, then the Oscillator Start-up Timer (OST) and/or PLL lock times will be applied before the system clock source is made available to the device. As an exception to this rule, no oscillator delays are applied if the system clock source is the POSC oscillator and it was running while in SLEEP mode. Note: In spite of the various delays applied the crystal oscillator (and PLL) may not be up and running at the end of the Tost, or Tlock delays. For proper operation the user must design the external oscillator circuit such that reliable oscillation will occur within the delay period. 10 Power-Saving Modes © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-13 PIC32MX Family Reference Manual 10.3.1.5 Fail-Safe Clock Monitor (FSCM) Delay and SLEEP Mode The FSCM does not operate while the device is in Sleep. If the FSCM is enabled it will resume operation when the device wakes from Sleep. A delay of TFSCM is applied to allow the oscillator source to stabilize before the FSCM resumes monitoring. the following conditions are true, a delay of TFSCM will be applied when waking from SLEEP mode: • The oscillator was shutdown while in SLEEP mode. • The system clock is derived from a crystal oscillator source and/or the PLL. In most cases, the TFSCM delay provides time for the OST to expire and the PLL to stabilize before device execution resumes. If the FSCM is enabled, it will begin to monitor the system clock source after the TFSCM delay expires. 10.3.1.6 Slow Oscillator Start-up When an oscillator starts slowly, the OST and PLL lock times may not have expired before FSCM time out. If the FSCM is enabled, then the device will detect this condition as a clock failure and a clock fail trap will occur. The device will switch to the FRC oscillator and the user can re-enable the crystal oscillator source in the clock failure Interrupt Service Routine. If the FSCM is not enabled, then the device will simply not start executing code until the clock is stable. From the user’s perspective, the device will appear to be in SLEEP until the oscillator clock has started. 10.3.1.7 USB Peripheral Control of Oscillators in SLEEP Mode The USB module, when active, will prevent the clock source it is using from being disabled when the device enters sleep. Though the oscillator remains active the CPU and peripherals will remain halted. Example 10-1: Put Device in SLEEP, then Wake with WDT // Code example to put the Device in sleep and then Wake the device // with the WDT OSCCONSET = 0x10; // set Power-Saving mode to Sleep WDTCONCLR = 0x0002; WDTCONSET = 0x8000; // Disable WDT window mode // Enable WDT // WDT timeout period is set in the device configuration while (1) { ... user code ... WDTCONSET = 0x01; // service the WDT asm volatile( “wait” );// put device in selected Power-Saving mode // code execution will resume here after wake ... user code ... } // The following code fragment is at the beginning of the ‘C’ start-up code if ( RCON & 0x18 ) { // The WDT caused a wake from Sleep asm volatile( “eret” );// return from interrupt } DS61130E-page 10-14 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes 10.3.2 Peripheral Bus Scaling Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as the Interrupt Controller, DMA, Bus Matrix, and Prefetch Cache are clocked directly from SYSCLK, as a result, they are not affected by PBCLK divisor changes. Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK-to-PBCLK ratios of 1:1, 1:2, 1:4, and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as USB, Interrupt Controller, DMA, Bus Matrix, and Prefetch Cache are clocked directly from SYSCLK, as a result, they are not affected by PBCLK divisor changes Changing the PBCLK divisor affects: • The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode this results in a latency of one to seven SYSCLKs. • The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements such as baud rate accuracy should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. 10.3.2.1 Dynamic Peripheral Bus Scaling The PBCLK can be scaled dynamically, by software, to save additional power when the device is in a low activity mode. The following issues need to be taken into account when scaling the PBCLK: • All the peripherals clocked from PBCLK will scale at the same ratio, at the same time. This needs to be accounted in peripherals which need to maintain a constant baud rate, or pulse period even in low-power modes. • Any communication through a peripheral on the peripheral bus that is in progress when the PBCLK changes may cause a data or protocol error due to a frequency change during transmission or reception. The following steps are recommended, if the user intends to scale the PBCLK divisor dynamically: • Disable all communication peripherals whose baud rate will be affected. Care should be taken to ensure that no communication is currently in progress before disabling the peripherals as it may result in protocol errors. • Update the Baud Rate Generator (BRG) settings for peripherals as required for operation at the new PBCLK frequency. • Change the peripheral bus ratio to the desired value. • Enable all communication peripherals whose baud rate were affected. Note: Modifying the peripheral baud rate is done by writing to the associated peripheral SFRs. To minimize latency, the peripherals should be modified in the mode where the PBCLK is running at its highest frequency. 10 Power-Saving Modes © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-15 PIC32MX Family Reference Manual Example 10-2: Changing the PB Clock Divisor progress ... user code ... U1BRG = 0x81; ... user code ... SYSKEY = 0x0; SYSKEY = 0xAA996655; SYSKEY = 0x556699AA; OSCCONCLR = 0x3 << 19; SYSKEY = 0x0; // Code example to change the PBCLK divisor // This example is for a device running at 40 MHz // Make sure that there is no UART send/receive in // set baud rate for UART1 for 9600 // write invalid key to force lock // Write Key1 to SYSKEY // Write Key2 to SYSKEY // set PB divisor to minimum (1:1) // write invalid key to force lock ... user code ... U1BRG = 0x0F; // Change Peripheral Clock value // set baud rate for UART1 for 9600 based on SYSKEY = 0x0; SYSKEY = 0xAA996655; SYSKEY = 0x556699AA; OSCCONSET = 0x3 << 19; SYSKEY = 0x0; // new PB clock frequency // write invalid key to force lock // Write Key1 to SYSKEY // Write Key2 to SYSKEY // set PB divisor to maximum (1:8) // write invalid key to force lock SYSKEY = 0x0; SYSKEY = 0xAA996655; SYSKEY = 0x556699AA; OSCCONCLR = 0x3 << 19; SYSKEY = 0x0; // Reset Peripheral Clock // write invalid key to force lock // Write Key1 to SYSKEY // Write Key2 to SYSKEY // set PB divisor to minimum (1:1) // write invalid key to force lock U1BRG = 0x81; // restore baud rate for UART1 to 9600 based // on new PB clock frequency DS61130E-page 10-16 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes 10.3.3 IDLE Modes In the IDLE modes, the CPU is halted but the System clock (SYSCLK) source is still enabled. This allows peripherals to continue to operate when the CPU is halted. Peripherals can be individually configured to halt when entering IDLE by setting their respective SIDL bit. Latency when exiting Idle mode is very low due to the CPU oscillator source remaining active. There are four Idle modes of operation: POSC IDLE, FRC IDLE, SOSC IDLE, and LPRC IDLE. • POSC IDLE mode: The SYSCLK is derived from the POSC. The CPU is halted, but the SYSCLK source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. If the PLL is used, the Multiplier value, PLLMULT<2:0> (OSCCON<18:16>), can also be lowered to reduce power consumption by peripherals. • FRC IDLE mode: The SYSCLK is derived from the FRC. The CPU is halted. Peripherals continue to operate, but can optionally be individually disabled. If the PLL is used, the Multiplier value, PLLMULT<2:0> (OSCCON<18:16>), can also be lowered to reduce power consumption by peripherals. The FRC clock can be further divided by a postscaler using RCDIV<2:0> (OSCCON<26:24>). • SOSC IDLE mode: The SYSCLK is derived from the SOSC. The CPU is halted. Peripherals continue to operate, but can optionally be individually disabled. • LPRC IDLE. The SYSCLK is derived from the LPRC. The CPU is halted. Peripherals continue to operate, but can optionally be individually disabled. Note: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in PB divisor ratio. Note: Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator start-up delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and or Oscillator startup/lock delays would be applied. The device enters IDLE mode when the SLPEN (OSCCON<4>) bit is clear and a WAIT instruction is executed. The processor will wake or exit from Idle mode on the following events: • On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of CPU. If the priority of the interrupt event is lower than or equal to current priority of CPU, the CPU will remain halted and the device will remain in IDLE mode. • On any source of device Reset. • On a WDT time-out interrupt. See 10.4.2 “Wake-up from SLEEP or IDLE on Watchdog Time-out (NMI)” and Section 9. “Watchdog Timer and Power-up Timer”. 10 Power-Saving Modes © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-17 PIC32MX Family Reference Manual Example 10-3: Placing Device in IDLE and Waking by ADC Event SYSKEY = 0x0; SYSKEY = 0xAA996655; SYSKEY = 0x556699AA; OSCCONCLR = 0x10; SYSKEY = 0x0; // Code example to put the Device in Idle and then Wake the device // when the ADC completes a conversion // write invalid key to force lock // Write Key1 to SYSKEY // Write Key2 to SYSKEY // set Power-Saving mode to Idle // write invalid key to force lock asm volatile ( "wait" ); ... user code ... // put device in selected Power-Saving mode // code execution will resume here after wake and the ISR is complete // interrupt handler void __ISR(27_ADC_VECTOR, ipl7) ADC_HANDLER(void) { // interrupt handler unsigned long int result; result = ADC1BUF0; IFS1CLR = 2; } // read the result // Clear ADC conversion interrupt flag DS61130E-page 10-18 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes 10.4 INTERRUPTS There are two sources of interrupts that will wake the device from a Power-Saving mode: Peripheral interrupts and an Non-Maskable Interrupt (NMI) generated by the WDT in Power-Saving mode. 10.4.1 Wake-up from SLEEP or IDLE on Peripheral Interrupt Any source of interrupt that is individually enabled using the corresponding IE control bit in the IECx register and is operational in the current Power-Saving mode will be able to wake up the processor from SLEEP or IDLE mode. When the device wakes, one of two events will occur based on the interrupt priority: • If the assigned priority for the interrupt is less than or equal to the current CPU priority, the CPU will remain halted and the device enters or remains in IDLE mode. • If the assigned priority level for the interrupt source is greater than the current CPU priority, the device will wake-up and the CPU will jump to the corresponding interrupt vector. Upon completion of the ISR, CPU will start executing the next instruction after WAIT. The IDLE Status bit (RCON<2>) is set upon wake-up from IDLE mode. The SLEEP Status bit (RCON<3>) is set upon wake-up from SLEEP mode. Note: A peripheral with an interrupt priority setting of Zero cannot wake the device. Note: Any applicable oscillator start-up delays are applied before the CPU resumes code execution. 10.4.2 Wake-up from SLEEP or IDLE on Watchdog Time-out (NMI) When the WDT times out in SLEEP or IDLE mode, an NMI is generated. The NMI causes the CPU code execution to jump to the device Reset vector. Although CPU executes Reset vector, it is not a device Reset – peripherals and most CPU registers do not change their states. Note: Any applicable oscillator start-up delays are applied before the CPU resumes code execution. To detect a wake from a Power-Saving mode caused by WDT expiration, the WDTO (RCON<4>), SLEEP (RCON<3>) and IDLE (RCON<2>) bits must be tested. If the WDTO bit is a ‘1’ the event was due to a WDT time-out. The SLEEP and IDLE bits can then be tested to determine if the WDT event occurred in Sleep or Idle. To use a WDT time-out during SLEEP mode as a wake-up interrupt, a return from interrupt (ERET) instruction must be used in the start-up code after the event was determined to be a WDT wake-up. This will cause code execution to continue from the instruction following the WAIT instruction that put the device in Power-Saving mode. Note: If a peripheral interrupt and WDT event occur simultaneously, or in close proximity, the NMI may not occur, due to the device being woken-up by the peripheral interrupt. To avoid unexpected WDT Reset in this scenario, the WDT is automatically cleared when the device awakens. 10 See Section 9. “Watchdog Timer and Power-up Timer” for detailed information on the WDT operation. 10.4.3 Interrupts Coincident with Power-Saving Instruction Any peripheral interrupt that coincides with the execution of a WAIT instruction will be held off until entry into SLEEP or IDLE mode has completed. The device will then wake-up from SLEEP or IDLE mode. Power-Saving Modes © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-19 PIC32MX Family Reference Manual 10.5 10.6 10.7 I/O PINS ASSOCIATED WITH POWER-SAVING MODES No device pins are associated with Power-Saving modes. OPERATION IN DEBUG MODE The user cannot change Clock modes when the debugger is active. Clock source changes due to the Fail-Safe Clock Monitor (FSCM) will still occur when the debugger is active. RESETS The behavior of the device after a Reset is determined by the type of Reset that occurred. For behavior related to the Power-Saving modes, Resets can be categorized into two groups: Power-on Reset (POR) and all other Resets (non POR). 10.7.1 Resets Other than POR During SLEEP or IDLE The CPU will wake and code execution will begin at the device Reset vector. Any applicable oscillator delays will apply. The IDLE Status bit (RCON<2>) or SLEEP Status bit (RCON<3>) will be set to indicate the device was in a Power-Saving mode prior to the Reset. 10.7.2 POR Reset During SLEEP or IDLE The CPU will wake and code execution will begin at the device Reset vector. Any applicable oscillator delays will apply. The IDLE Status bit (RCON<2>) or SLEEP Status bit (RCON<3>) will be forced clear. The power-saving state prior to the POR event is lost. DS61130E-page 10-20 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes 10.8 DESIGN TIPS Question 1: What should my software do before entering SLEEP or IDLE mode? Answer: Make sure that the sources intended to wake the device have their IE bits set. In addition, make sure that the particular source of interrupt has the ability to wake the device. Some sources do not function when the device is in SLEEP mode. If the device is to be placed in Idle mode, make sure that the ‘stop-in-idle’ control bit for each device peripheral is properly set. These control bits determine whether the peripheral will continue operation in IDLE mode. See the individual peripheral sections of this manual for further details. Clear the WDT before entering SLEEP. If in Window mode, the WDT can only be cleared within the window period to prevent a device Reset. Question 2: How do I determine which peripheral woke the device from SLEEP or IDLE mode? Answer: Most peripherals have a unique interrupt vector. If needed, you can poll the IF bits for each enabled interrupt source to determine the source of wake-up. Power-Saving Modes 10 © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-21 PIC32MX Family Reference Manual 10.9 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Power-Saving modes include the following: Title Low-Power Design using PIC® Microcontrollers Application Note # AN606 Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. DS61130E-page 10-22 Preliminary © 2008 Microchip Technology Inc. Section 10. Power-Saving Modes 10.10 REVISION HISTORY Revision A (October 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x. Revision D (July 2008) Revised Example 10-1 and 10-3; Revised Table 10-1; Revised Register 10-5 and 10-9; Revised Section 10.3.2 (2nd para.); Change Reserved bits from “Maintain as” to “Write”; Added Note to ON bit (WDTCON Register). Revision E (July 2008) Revised Examples 10-2, 10-3. Power-Saving Modes 10 © 2008 Microchip Technology Inc. Preliminary DS61130E-page 10-23 PIC32MX Family Reference Manual NOTES: DS61130E-page 10-24 Preliminary © 2008 Microchip Technology Inc. 11 Section 11. Reserved for Future Xxxxx © 2008 Microchip Technology Inc. Preliminary DSxxxxxA-page 11-1 PIC32MX Family Reference Manual NOTES: DSxxxxxA-page 11-2 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports HIGHLIGHTS This section of the manual contains the following topics: 12 12.1 Introduction ................................................................................................................. 12-2 12.2 Control Registers ........................................................................................................ 12-4 12.3 Modes of Operation................................................................................................... 12-25 12.4 Interrupts ................................................................................................................... 12-31 12.5 Operation in Power-Saving and DEBUG Modes....................................................... 12-33 12.6 Effects of Various Resets .......................................................................................... 12-34 12.7 I/O Port Application ................................................................................................... 12-35 12.8 I/O Pin Control........................................................................................................... 12-36 12.9 Design Tips ............................................................................................................... 12-37 12.10 Related Application Notes......................................................................................... 12-38 12.11 Revision History ........................................................................................................ 12-39 © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-1 PIC32MX Family Reference Manual 12.1 INTRODUCTION The general purpose I/O pins can be considered the simplest of peripherals. They allow the PIC32MX microcontroller to monitor and control other devices. To add flexibility and functionality to a device, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Following are some of the key features of this module: • Individual output pin open-drain enable/disable • Individual input pin pull-up enable/disable • Monitor select inputs and generate interrupt on mismatch condition • Operate during CPU SLEEP and IDLE modes • Fast bit manipulation using CLR, SET and INV registers A block diagram of a typical I/O port structure is shown in Figure 12-1. The diagram depicts the many peripheral functions that can be multiplexed onto the I/O pin. The I/O Ports module consists of the following Special Function Registers (SFRs): • TRISx: Data Direction register for the module ‘x’ • PORTx: PORT register for the module ‘x’ • LATx: Latch register for the module ‘x’ • ODCx: Open-Drain Control register for the module ‘x’ • CNCON: Interrupt-on-Change Control register • CNEN: Input Change Notification Interrupt Enable register • CNPUE: Input Change Notification Pull-up Enable register The I/O Ports module also has the following associated bits for interrupt control: • Interrupt Enable Control bits for CN events (CNIE) in INT register IEC1: Interrupt Enable Control Register 1. • Interrupt Flag Status bits for CN events (CNIF) in INT register IFS1: Interrupt Flag Status Register 1. • Interrupt Priority Control bits (CNIP<2:0>) in INT register IPC6: Interrupt Priority Control Register 6. DS61120D-page 12-2 Preliminary © 2008 Microchip Technology Inc. I/O Ports Figure 12-1: Typical Port Structure Block Diagram RD ODC Dedicated Port Module Section 12. I/O Ports Data Bus SYSCLK WR ODC RD TRIS WR TRIS WR LAT WR PORT RD LAT RD PORT SLEEP SYSCLK DQ CK EN Q ODC 0 1 DQ CK TRIS EN Q DQ CK LAT EN Q 1 0 QDQD Q CK Q CK Synchronization 12 I/O Cell I/O pin © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-3 PIC32MX Family Reference Manual 12.2 CONTROL REGISTERS Before reading and writing any I/O port, the desired pin(s) should be properly configured for the application. Each I/O port has three registers directly associated with the operation of the port: TRIS, PORT and LAT. Each I/O port pin has a corresponding bit in these registers. Depending on the PIC32MX device variant, up to seven I/O ports are available. Through out this section, the letter ‘x’, denotes any or all port module instances. For example “TRISx” would represent TRISA, TRISB, TRISC, etc. Any bit and its associated data and control registers that is not valid for a particular device will be disabled and will read as zeros. Note: The total number of ports and available I/O pins will depend on the device variant. In a given device, all of the bits in a port control register might not be available. Refer to the specific device data sheet for further details. 12.2.1 TRIS (tri-state) Registers TRIS registers configure the data direction flow through port I/O pin(s). The TRIS register bits determine whether a PORT I/O pin is an input or an output. • A TRIS bit set = 1 configures the corresponding I/O port pin as an input. • A TRIS bit set = 0 configures the corresponding I/O port pin as an output. • A read from a TRIS register reads the last value written to the TRIS register. • All I/O port pins are defined as inputs after a Power-on Reset. 12.2.2 PORT Registers PORT registers allow I/O pins to be accessed (read). • A write to a PORT register writes to the corresponding LAT register (PORT data latch). Those I/O port pin(s) configured as outputs are updated. • A write to a PORT register is the effectively the same as a write to a LAT register. • A read from a PORT register reads the synchronized signal applied to the port I/O pins. 12.2.3 LAT Registers LAT registers (PORT data latch) hold data written to port I/O pin(s). • A write to a LAT register latches data to corresponding port I/O pins. Those I/O port pin(s) configured as outputs are updated. • A read from LAT register reads the data held in the PORT data latch, not from the port I/O pins. 12.2.4 SET, CLR, INV I/O Port Registers In addition to the TRIS, PORT, and LAT base registers, each port module is associated with a SET, CLR and INV register which provides atomic bit manipulations and allowing faster I/O pin operations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as ‘1’ are modified. Bits specified as ‘0’ are not modified. • Writing 0x0001 to TRISASET register sets only bit 0 in base register TRISA • Writing 0x0020 to PORTDCLR register clears only bit 5 in base register PORTD • Writing 0x9000 to LATCINV register inverts only bits 15 and 12 in the base register LATC. Reading SET, CLR and INV registers return an undefined value. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read instead. The SET, CLR and INV registers are not exclusive to TRIS, PORT and LAT registers. Other I/O port module registers ODC, CNEN and CNPUE also feature these bit manipulation registers. DS61120D-page 12-4 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports A typical method to toggle an I/O pin requires a read-modify-write operation performed on a PORT register in software. For example, a read from a PORTx register, mask and modify the desired output bit(s), write the resulting value back to the PORTx register. This method is vulnerable to a read-modify-write issue where the port value may change after it is read and before the modified data can be written back, thus changing the previous state. This method also requires more instructions. PORTA ^= 0x0001; A more efficient and atomic method uses the PORTxINV register. A write to the PORTxINV register effectively performs a read-modify-write operation on the target base register, equivalent to the software operation described above, however, it is done in hardware. To toggle an I/O pin using this method, a “1” is written to the corresponding bit in the PORTxINV register. This operation will read the PORTx register, invert only those bits specified as ‘1’ and write the resulting value to the LATx register, thus toggling the corresponding I/O pin(s) all in a single atomic instruction cycle. PORTAINV = 0x0001; 12 TRISx SET,CLR,INV Register Behavior • A value written to a TRISxSET register reads the TRISx base register, sets any bit(s) specified as ‘1’, writes the modified value back to the TRISx base register. • A value written to a TRISxCLR register reads the TRISx base register, clears any bit(s) specified as ‘1’, writes the modified value back to the TRISx base register. • A value written to a TRISxINV register reads the TRISx base register, inverts any bit(s) specified as ‘1’, writes the modified value back to the TRISx base register. • Any bit(s), specified as ‘0’, are not modified. PORTx SET,CLR,INV Register Behavior • A value written to a PORTxSET register reads the PORTx base register, sets any bit(s) specified as ‘1’, writes the modified value back to the LATx base register. Those I/O port pin(s) configured as outputs are updated. • A value written to a PORTxCLR register reads the PORTx base register, clears any bit(s) specified as ‘1’, writes the modified value back to the LATx base register. Those I/O port pin(s) configured as outputs are updated. • A value written to a PORTxINV register reads the PORTx base register, inverts any bit(s) specified as ‘1’, writes the modified value back to the LATx base register. Those I/O port pin(s) configured as outputs are updated. • Any bit(s), specified as ‘0’, are not modified. LATx SET,CLR,INV Register Behavior • A value written to a LATxSET register reads the LATx base register, sets any bit(s) specified as ‘1’, writes the modified value back to the LATx base register. Those I/O port pin(s) configured as outputs are updated. • A value written to a LATxCLR register reads the LATx base register, clears any bit(s) specified as ‘1’, writes the modified value back to the LATx base register. Those I/O port pin(s) configured as outputs are updated. • A value written to a LATxINV register reads the LATx base register, inverts any bit(s) specified as ‘1’, writes the modified value back to the LATx base register. Those I/O port pin(s) configured as outputs are updated. Any bit(s), specified as ‘0’, are not modified. 12.2.5 ODC Registers Each I/O pin can be individually configured for either normal digital output or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each I/O pin. If the ODC bit for an I/O pin is a ‘1’, then the pin acts as an open-drain output. If the ODC bit for an I/O pin is a ‘0’, then the pin is configured for a normal digital output (ODC bit is valid only for output pins). After a Reset, the status of all the bits of the ODCx register is set to ‘0’. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-5 PIC32MX Family Reference Manual The open- drain feature allows the generation of outputs higher than VDD on any desired digital only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. The ODC register setting takes effect in all the I/O modes, allowing the output to behave as an open-drain even if a peripheral is controlling the pin. Although the user could achieve the same effect by manipulating the corresponding LAT and TRIS bits, this procedure will not allow the peripheral to operate in Open-Drain mode (except for the default operation of the I2C™ pins). Since I2C pins are already open-drain pins, the ODCx settings do not affect the I2C pins. Also, the ODCx settings do not affect the JTAG output characteristics as the JTAG scan cells are inserted between the ODCx logic and the I/O. 12.2.6 CN Control Registers Several I/O pins may be individually configured to generate an interrupt when a change on an input pin is detected. There are three control registers associated with the CN (Change Notice) module. The CNCON control register is used to enable or disable the CN module. The CNEN register contains the CNENx control bits, where ‘x’ denotes the number of the CN input pin. The CNPUE register contains the CNPUEx control bits. Each CN pin has a pull-up device connected to the pin which can be enabled or disabled using the CNPUEx control bits. The pull-up devices act as a current source that is connected to the pin and eliminate the need for external resistors when push button or keypad devices are connected. Refer to the “Electrical Characteristics” section of the specific device data sheet for CN pull-up device current specifications. The following table provides a brief summary of all I/O ports-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Table 12-1: Name TRISx TRISxCLR TRISxSET TRISxINV PORTx PORTxCLR PORTxSET PORTxINV LATx LATxCLR LATxSET LATxINV ODCx ODCxCLR ODCxSET ODCxINV I/O Ports SFR Summary Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 31:0 — 23:16 — 15:8 7:0 31:0 31:0 31:0 31:0 — 23:16 — 15:8 7:0 31:0 31:0 31:0 31:24 — 23:16 — 15:8 7:0 31:0 31:0 31:0 31:24 — 23:16 — 15:8 7:0 31:0 31:0 31:0 — — — — — — — — — — — — TRISx<15:8> TRISx<7:0> Write clears selected bits in TRISx, read yields undefined value Write sets selected bits in TRISx, read yields undefined value Write inverts selected bits in TRISx, read yields undefined value — — — — — — — — — — — — PORTx<15:8> PORTx<7:0> Write clears selected bits in LATx, read yields undefined value Write sets selected bits in LATx, read yields undefined value Write inverts selected bits in LATx, read yields undefined value — — — — — — — — — — — — LATx<15:8> LATx<7:0> Write clears selected bits in LATx, read yields undefined value Write sets selected bits in LATx, read yields undefined value Write inverts selected bits in LATx, read yields undefined value — — — — — — — — — — — — ODCx<5:8> ODCx<7:0> Write clears selected bits in ODCx, read yields undefined value Write sets selected bits in ODCx, read yields undefined value Write inverts selected bits in ODCx, read yields undefined value Bit 24/16/8/0 — — — — — — — — DS61120D-page 12-6 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports Table 12-1: Name CNCON CNCONCLR CNCONSET CNCONINV CNEN CNENCLR CNENSET CNENINV CNPUE CNPUECLR CNPUESET CNPUEINV IEC1 IFS1 IPC6 I/O Ports SFR Summary (Continued) Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0 — — ON — — — — — — — RTCCIE SPI2RXIE — — RTCCIF SPI2RXIF — — — — — — — — — — — — — — — — — — FRZ SIDL — — — — — — — — — — — — Write clears selected bits in CNCON, read yields undefined value Write sets selected bits in CNCON, read yields undefined value Write inverts selected bits in CNCON, read yields undefined value — — — — — — — — CNEN<21:16> CNEN<15:8> CNEN<7:0> Write clears selected bits in CNEN, read yields undefined value Write sets selected bits in CNEN, read yields undefined value Write inverts selected bits in CNEN, read yields undefined value — — — — — — — — CNPUE<21:16> CNPUE<15:8> CNPUE<7:0> Write clears selected bits in CNPUE read yields undefined value Write sets selected bits in CNPUE, read yields undefined value Write inverts selected bits in CNPUE, read yields undefined value — — — — — USBIE FCEIE — — — DMA3IE DMA2IE DMA1IE DMA0IE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE — — — — — USBIF FCEIF — — — DMA3IF DMA2IF DMA1IF DMA0IF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF — — AD1IP<2:0> AD1IS<1:0> — — CNIP<2:0> CNIS<1:0> — — I2C1IP<2:0> I2C1IS<1:0> — — U1IP<2:0> U1IS<1:0> 12 © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-7 PIC32MX Family Reference Manual Register 12-1: TRISx: TRIS Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-1 bit 15 R/W-1 R/W-1 R/W-1 R/W-1 TRIS<15:8> R/W-1 R/W-1 R/W-1 bit 8 R/W-1 bit 7 R/W-1 R/W-1 R/W-1 R/W-1 TRIS<7:0> R/W-1 R/W-1 R/W-1 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-0 Reserved: Write ‘0’; ignore read TRISx<15:0>: TRIS Register bits 1 = Corresponding port pin “Input” 0 = Corresponding port pin ‘Output” DS61120D-page 12-8 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports Register 12-2: TRISxCLR: TRIS Clear Register Write clears selected bits in TRISx, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in TRISx A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in TRISx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TRISxCLR = 0x00008001 will clear bits 15 and 0 in TRISx register. 12 Register 12-3: TRISxSET: TRIS Set Register Write sets selected bits in TRISx, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in TRISx A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in TRISx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TRISxSET = 0x00008001 will set bits 15 and 0 in TRISx register. Register 12-4: TRISxINV: TRIS Invert Register Write inverts selected bits in TRISx, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in TRIS A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in TRISx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TRISxINV = 0x00008001 will invert bits 15 and 0 in TRISx register. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-9 PIC32MX Family Reference Manual Register 12-5: PORTx: PORT Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x PORT<15:8> R/W-x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x PORT<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-0 Reserved: Write ‘0’; ignore read PORTx<15:0>: PORT Register bits Read = Value on port pins Write = Value written to the LATx register, PORT latch and I/O pins DS61120D-page 12-10 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports Register 12-6: PORTxCLR: PORT Clear Register Write clears selected bits in LATx, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in LATx A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in LATx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PORTxCLR = 0x00008001 will clear bits 15 and 0 in LATx register. 12 Register 12-7: PORTxSET: PORT Set Register Write sets selected bits in LATx, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in LATx A writes of ‘1’ in one or more bit positions sets the corresponding bit(s) in LATx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PORTxSET = 0x00008001 will set bits 15 and 0 in LATx register. Register 12-8: PORTxINV: PORT Invert Register Write inverts selected bits in LATx, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in LATx A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in LATx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PORTxINV = 0x00008001 will invert bits 15 and 0 in LATx register. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-11 PIC32MX Family Reference Manual Register 12-9: LATx: LAT Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-x bit 15 R/W-x R/W-x R/W-x R/W-x LAT<15:8> R/W-1x R/W-x R/W-x bit 8 R/W-x bit 7 R/W-x R/W-x R/W-x R/W-x LAT<7:0> R/W-x R/W-x R/W-x bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-0 Reserved: Write ‘0’; ignore read LATx<15:0>: LAT Register bits Read = Value on PORT latch, not I/O pins Write = Value written to PORT latch and I/O pins DS61120D-page 12-12 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports Register 12-10: LATxCLR: LAT Clear Register Write clears selected bits in LATx, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in LATx A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in LATx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: LATxCLR = 0x00008001 will clear bits 15 and 0 in LATx register. 12 Register 12-11: LATxSET: LAT Set Register Write sets selected bits in LATx, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in LATx A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in LATx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: LATxSET = 0x00008001 will set bits 15 and 0 in LATx register. Register 12-12: LATxINV: LAT Invert Register Write inverts selected bits in LATx, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in LATx A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in LATx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: LATxINV = 0x00008001 will invert bits 15 and 0 in LATx register. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-13 PIC32MX Family Reference Manual Register 12-13: ODCx: Open Drain Configuration Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 ODCx<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 ODCx<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-0 Reserved: Write ‘0’; ignore read ODCx<15:0>: ODCx Register bits If a port pin is configured as an output (corresponding TRISx bit = 0) 1 = Port pin open-drain output enabled 0 = Port pin open-drain output disabled If a port pin is configured as an input, ODCx bits have no effect. DS61120D-page 12-14 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports Register 12-14: ODCxCLR: Open Drain Configuration Clear Register Write clears selected bits in ODCx, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in ODCx A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in ODCx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: ODCxCLR = 0x00008001 will clear bits 15 and 0 in ODCx register. 12 Register 12-15: ODCxSET: Open Drain Configuration Set Register Write sets selected bits in ODCx, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in ODCx A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in ODCx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: ODCxSET = 0x00008001 will set bits 15 and 0 in ODCx register. Register 12-16: ODCxINV: Open Drain Configuration Invert Register Write inverts selected bits in ODCx, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in ODCx A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in ODCx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: ODCxINV = 0x00008001 will invert bits 15 and 0 in ODCx register. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-15 PIC32MX Family Reference Manual Register 12-17: CNCON: Interrupt-On-Change Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x r-x ON FRZ SIDL — — — — — bit 15 bit 8 r-x — bit 7 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14 bit 13 bit 12-0 Reserved: Write ‘0’; ignore read ON: Change Notice Module On bit 1 = CN Module is enabled 0 = CN Module is disabled Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation when CPU is in Debug Exception mode Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode. SIDL: Stop in IDLE Mode bit 1 = Discontinue operation when device enters IDLE mode 0 = Continue operation in IDLE mode Reserved: Write ‘0’; ignore read DS61120D-page 12-16 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports Register 12-18: CNCONCLR: Interrupt-On-Change Control Clear Register Write clears selected bits in CNCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in CNCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in CNCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CNCONCLR = 0x00008000 will clear bit 15 in CNCON register. 12 Register 12-19: CNCONSET: Interrupt-On-Change Control Set Register Write sets selected bits in CNCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in CNCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in CNCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CNCONSET = 0x00008000 will set bit 15 in CNCON register. Register 12-20: CNCONINV: Interrupt-On-Change Control Invert Register Write inverts selected bits in CNCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in CNCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in CNCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CNCONINV = 0x00008000 will invert bit 15 in CNCON register. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-17 PIC32MX Family Reference Manual Register 12-21: CNEN: Input Change Notification Interrupt Enable Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 bit 16 R/W-0 CNEN15 bit 15 R/W-0 CNEN14 R/W-0 CNEN13 R/W-0 CNEN12 R/W-0 CNEN11 R/W-0 CNEN10 R/W-0 CNEN9 R/W-0 CNEN8 bit 8 R/W-0 CNEN7 bit 7 R/W-0 CNEN6 R/W-0 CNEN5 R/W-0 CNEN4 R/W-0 CNEN3 R/W-0 CNEN2 R/W-0 CNEN1 R/W-0 CNEN0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-22 bit 21-0 Reserved: Write ‘0’; ignore read CNEN<21:0>: CNEN Register bits If a port pin is configured as an input (corresponding TRISx bit = 1) 1 = Port pin input change notice enabled 0 = Port pin input change notice disabled If a port pin is configured as an output, CNENx bits have no effect. DS61120D-page 12-18 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports Register 12-22: CNENCLR: Input Change Notification Interrupt Enable Register Clear Register Write clears selected bits in CNEN, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in CNEN A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in CNEN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CNENCLR = 0x00008001 will clear bits 15 and 0 in CNEN register. 12 Register 12-23: CNENSET: Input Change Notification Interrupt Enable Register Set Register Write sets selected bits in CNEN, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in CNEN A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in CNEN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CNENSET = 0x00008001 will set bits 15 and 0 in CNEN register. Register 12-24: CNENINV: Input Change Notification Interrupt Enable Register Invert Register Write inverts selected bits in CNEN, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in CNEN A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in CNEN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CNENINV = 0x00008001 will invert bits 15 and 0 in CNEN register. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-19 PIC32MX Family Reference Manual Register 12-25: CNPUE: Input Change Notification Pull-up Enable Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16 bit 16 R/W-0 CNPUE15 bit 15 R/W-0 CNPUE14 R/W-0 CNPUE13 R/W-0 CNPUE12 R/W-0 CNPUE11 R/W-0 CNPUE10 R/W-0 CNPUE9 R/W-0 CNPUE8 bit 8 R/W-0 CNPUE7 bit 7 R/W-0 CNPUE6 R/W-0 CNPUE5 R/W-0 CNPUE4 R/W-0 CNPUE3 R/W-0 CNPUE2 R/W-0 CNPUE1 R/W-0 CNPUE0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-22 bit 21-0 Reserved: Write ‘0’; ignore read CNPUE<21:0>: CNPUE Register bits If a port pin is configured as an input (corresponding TRISx bit = 1) 1 = port pin pull-up enabled 0 = port pin pull-up disabled If a port pin is configured as an output, the corresponding CNPUEx bit should be disabled. DS61120D-page 12-20 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports Register 12-26: CNPUECLR: Interrupt Change Pull-up Enable Clear Register Write clears selected bits in CNPUE, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in CNPUE A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in CNPUE register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CNPUECLR = 0x00008001 will clear bits 15 and 0 in CNPUE register. 12 Register 12-27: CNPUESET: Interrupt Change Pull-up Enable Set Register Write sets selected bits in CNPUE, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in CNPUE A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in CNPUE register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CNPUESET = 0x00008001 will set bits 15 and 0 in CNPUE register. Register 12-28: CNPUEINV: Interrupt Change Pull-up Enable Invert Register Write inverts selected bits in CNPUE, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in CNPUE A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in CNPUE register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: CNPUEINV = 0x00008001 will invert bits 15 and 0 in CNPUE register. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-21 PIC32MX Family Reference Manual Register 12-29: IEC1: Interrupt Enable Control Register 1(1) r-x r-x r-x r-x r-x — — — — — bit 31 r-x R/W-0 R/W-0 — USBIE FCEIE bit 24 r-x — bit 23 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IE DMA2IE DMA1IE DMA0IE bit 16 R/W-0 RTCCIE bit 15 R/W-0 FSCMIE R/W-0 I2C2MIE R/W-0 I2C2SIE R/W-0 I2C2BIE R/W-0 U2TXIE R/W-0 U2RXIE R/W-0 U2EIE bit 8 R/W-0 SPI2RXIE bit 7 R/W-0 SPI2TXIE R/W-0 SPI2EIE R/W-0 CMP2IE R/W-0 CMP1IE R/W-0 PMPIE R/W-0 AD1IE R/W-0 CNIE bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 0 CNIE: Change Notice Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the I/O Port Change Notice. DS61120D-page 12-22 Preliminary © 2008 Microchip Technology Inc. Section 12. I/O Ports Register 12-30: IFS1: Interrupt Flag Status Control Register 1(1) r-x r-x r-x r-x r-x — — — — — bit 31 r-x R/W-0 R/W-0 — USBIF FCEIF bit 24 r-x — bit 23 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IF DMA2IF DMA1IF DMA0IF bit 16 R/W-0 RTCCIF bit 15 R/W-0 FSCMIF R/W-0 I2C2MIF R/W-0 I2C2SIF R/W-0 I2C2BIF R/W-0 U2TXIF R/W-0 U2RXIF R/W-0 U2EIF bit 8 R/W-0 SPI2RXIF bit 7 R/W-0 SPI2TXIF R/W-0 SPI2EIF R/W-0 CMP2IF R/W-0 CMP1IF R/W-0 PMPIF R/W-0 AD1IF R/W-0 CNIF bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 0 CNIE: Change Notice Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the I/O Port Change Notice. 12 I/O Ports © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-23 PIC32MX Family Reference Manual Register 12-31: IPC6: Interrupt Priority Control Register 6(1) r-x r-x r-x R/W-0 R/W-0 — — — AD1IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 AD1IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CNIP<2:0> CNIS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — I2C1IP<2:0> I2C1IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — U1IP<2:0> U1IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 20-18 CNIP<2:0>: Change Notice Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled bit 17-16 CNIS<1:0>: Change Notice Interrupt Subpriority bits 11 = Interrupt Subpriority is 3 10 = Interrupt Subpriority is 2 01 = Interrupt Subpriority is 1 00 = Interrupt Subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the I/O Port Change Notice. DS61120D-page 12-24 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports 12.3 MODES OF OPERATION 12.3.1 Digital Inputs Pins are configured as digital inputs by setting the corresponding TRIS register bits = 1. When configured as inputs, they are Schmitt Triggers. Several digital pins share functionality with analog inputs and default to the analog inputs at Power-on Reset. Setting the corresponding bit in the AD1PCFG register = 1 enables the pin as a digital pin. Note: Refer to the specific device data sheet for further details regarding input buffer types. To use pins that are multiplexed with the 10-bit Analog-to-Digital Converter (A/D) module for digital I/O, the corresponding bits in the AD1PCFG register must be set to ‘1’ – even if the A/D module is turned off. 12 12.3.2 Analog Inputs Certain pins can be configured as analog inputs used by the A/D and Comparator modules. Setting the corresponding bits in the AD1PCFG register = 0 enables the pin as an analog input pin, independent of the TRIS register setting for the corresponding pin. 12.3.3 Digital Outputs Pins are configured as digital outputs by setting the corresponding TRIS register bits = 0. When configured as digital outputs, these pins are CMOS drivers or can be configured as open-drain outputs by setting the corresponding bits in the ODC register. 12.3.4 Analog Outputs Certain pins can be configured as analog outputs, such as the CVREF output voltage used in the Comparator module. Configuring the Comparator module to provide this output will present the analog output voltage on the pin, independent of the TRIS register setting for the corresponding pin. Note: Refer to the specific device data sheet for further details regarding the use of A\D and Comparator modules. 12.3.5 Open-Drain Configuration In addition to the PORT, LAT and TRIS registers for data control, each port pin configured as a digital output can also select between an active drive output and open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. From Power-on Reset, when an I/O pin is configured as a digital output, its output is active drive by default. Setting a bit in the ODCx register = 1 configures the corresponding pin as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired digital-only pins by using external pull up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 12.3.6 Peripheral Multiplexing Many pins also support one or more peripheral modules. When configured to operate with a peripheral, a pin may not be used for general input or output. In many cases, a pin must still be configured for input or output, although some peripherals override the TRIS configuration. Figure 12-2 shows how ports are shared with other peripherals, and the associated I/O pin to which they are connected. For some PIC32MX devices, multiple peripheral functions may be multiplexed on each I/O pin. The priority of the peripheral function depends on the order of the pin description in the pin diagram of the specific product data sheet. Note that the output of a pin can be controlled by the TRISx register bit or, in some cases, by the peripheral itself. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-25 PIC32MX Family Reference Manual Figure 12-2: Block Diagram of a Typical Shared Port Structure PI/O Module RD ODC Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data Data Bus SYSCLK WR ODC RD TRIS WR TRIS WR LAT WR PORT RD LAT RD PORT SLEEP SYSCLK Peripheral Input DQ CK EN Q ODC 1 0 0 1 DQ CK TRIS 1 Q EN 0 DQ CK LAT EN Q Output Multiplexers I/O Cell I/O pin 1 0 QDQD Q CK Q CK R Peripheral input buffer Synchronization Notes: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than what is shown here. R = Peripheral input buffer types may vary. Refer to the PIC32MX data sheet for peripheral details. DS61120D-page 12-26 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports 12.3.6.1 Multiplexed Digital Input Peripheral The following conditions are characteristic of a multiplexed digital input peripheral: • Peripheral does not control the TRISx register. Some peripherals require the pin be configured as an input by setting the corresponding TRISx bit = 1. • Peripheral input path is independent of I/O input path and uses an input buffer that is dependent on the peripheral. • PORTx register data input path is not affected and is able to read the pin value. 12.3.6.2 Multiplexing Digital Output Peripheral The following conditions are characteristic of a multiplexed digital output peripheral: • Peripheral controls the output data. Some peripherals require the pin be configured as an output by setting the corresponding TRISx bit = 0. • If a peripheral pin has an automatic tri-state feature, e.g., PWM outputs, the peripheral has the ability to tri-state the pin. • Pin output driver type could be affected by peripheral, e.g., drive strength, slew rate, etc. • PORTx register output data has no effect. 12.3.6.3 Multiplexing Digital Bidirectional Peripheral The following conditions are characteristic of a multiplexed digital bidirectional peripheral: • Peripheral automatically configures the pin as an output, but not as an input. Some peripherals require the pin be configured as an input by setting the corresponding TRISx bit = 1. • Peripherals control output data. • Pin output driver type could be affected by peripheral (e.g., drive strength, slew rate, etc.). • PORTx register data input path is not affected and is able to read the pin value. • PORTx register output data has no effect. 12.3.6.4 Multiplexing Analog Input Peripheral The following condition is characteristic of a multiplexed analog input peripheral: All digital port input buffers are disabled and PORTx registers read ‘0’ to prevent crowbar current. 12.3.6.5 Multiplexing Analog Output Peripheral The following conditions are characteristic of a multiplexed analog output peripheral: • All digital port input buffers are disabled and PORTx registers read ‘0’ to prevent crowbar current. • Analog output is driven onto the pin independent of the associated TRISx setting. Note: In order to use pins that are multiplexed with the A/D module for digital I/O, the corresponding bits in the AD1PCFG register must be set to ‘1’ – even if the A/D module is turned off. 12 © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-27 PIC32MX Family Reference Manual 12.3.6.6 Software Input Pin Control Some of the functions assigned to an I/O pin may be input functions that do not take control of the pin output driver. An example of one such peripheral is the input capture module. If the I/O pin associated with the input capture is configured as an output, using the appropriate TRIS control bit, the user can manually affect the state of the input capture pin through its corresponding LAT register. This behavior can be useful in some situations, especially for testing purposes, when no external signal is connected to the input pin. As shown in Figure 12-2, the organization of the peripheral multiplexers will determine if the peripheral input pin can be manipulated in software using the PORT register. The conceptual peripherals shown in this figure disconnect the PORT data from the I/O pin when the peripheral function is enabled. In general, the following peripherals allow their input pins to be controlled manually through the LAT registers: • External Interrupt pins • Input Capture pins • Timer Clock Input pins • PWM Fault pins Most serial communication peripherals, when enabled, take full control of the I/O pin so that the input pins associated with the peripheral cannot be affected through the corresponding PORT registers. These peripherals include the following modules: • SPI • I2CUART • UART 12.3.7 Boundary Scan Cell Connections The PIC32MX device supports JTAG boundary scan. A Boundary Scan Cell (BSC) is inserted between the internal I/O logic circuit and the I/O pin, as shown in Figure 12-3. Most of the I/O pads have boundary scan cells, however, JTAG pads do not. For normal I/O operation, the BSC is disabled and hence bypassed: The output enable input of the BSC is directly connected to the BSC output enable, and the output data input of the BSC is directly connected to the BSC output data. The pads that do not have BSC are the power supply pads (VDD, VSS and VCAP/VDDCORE) and the JTAG pads (TCK, TDI, TDO and TMS). Figure 12-3: Boundary Scan Cell Connections Output Multiplexers Open-Drain Selection Peripheral Module Enable Peripheral Output Enable 1 Output LAT Data 0 Peripheral Output Enable 1 TRIS 0 0 Output 1 Enable Output Data Boundary Scan Cell (BSC) BSC Output Enable BSC Output Data BSC Enable Input Data BSC Input Data I/O I/O pin DS61120D-page 12-28 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports 12.3.8 Port Descriptions Refer to the specific device data sheet for a description of the available I/O ports and peripheral multiplexing details. 12.3.9 Change Notification Pins The Change Notification (CN) pins provide PIC32MX devices the ability to generate interrupt requests to the processor in response to a change of state on selected input pins (corresponding TRISx bits must = 1). Up to 22 input pins may be selected (enabled) for generating CN interrupts. The total number of available CN inputs is dependent on the selected PIC32MX device. Refer to the specific device data sheet for further details. The enabled pin values are compared with the values sampled during the last read operation of the designated PORT register. If the pin value is different from the last value read, a mismatch condition is generated. The mismatch condition can occur on any of the enabled input pins. The mismatches are ORed together to provide a single interrupt-on-change signal. The enabled pins are sampled on every internal system clock cycle, SYSCLK. Each CN pin has a pull up connected to it. The pull ups act as a current source that is connected to the pin, and eliminate the need for external resistors when push button or keypad devices are connected. The pull ups are enabled separately using the CNPUE register, which contain the control bits for each of the CN pins. Setting any of the CNPUE register bits enables the pull up for the corresponding pins. Note: Pull up on CN pins should always be disabled whenever the port pin is configured as a digital output. 12 Figure 12-4 shows the basic function of the CN hardware. Figure 12-4: Input Change Notification Block Diagram CNPUE (CNPUE<0>) CN0 pin CN1-CN21 pins (details not shown) DQ C DQ C CNEN (CNEN<0>) CN1 Change CN21 Change CNEN0 Change CN Interrupt © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-29 PIC32MX Family Reference Manual 12.3.9.1 CN Configuration and Operation The CN pins are configured as follows: 1. Disable CPU interrupts. 2. Set desired CN I/O pin as input by setting corresponding TRISx register bits = 1. Note: If the I/O pin is shared with an analog peripheral, it may be necessary to set the corresponding AD1PCFG register bit = 1 to ensure that the I/O pin is a digital input. 3. Enable CN Module ON (CNCON<15>) = 1. 4. Enable individual CN input pin(s), enable optional pull up(s). 5. Read corresponding PORT registers to clear mismatch condition on CN input pins. 6. Configure the CN interrupt priority, CNIP<2:0>, and subpriority CNIS<1:0>. 7. Clear CN interrupt flag, CNIF = 0. 8. Enable CN interrupt enable, CNIE = 1. 9. Enable CPU interrupts. When a CN interrupt occurs, the user should read the PORT register associated with the CN pin(s). This will clear the mismatch condition and set up the CN logic to detect the next pin change. The current PORT value can be compared to the PORT read value obtained at the last CN interrupt or during initialization, and used to determine which pin changed. The CN pins have a minimum input pulse-width specification. Refer to the “Electrical Characteristics” section of the data sheet for the specific device to learn more. DS61120D-page 12-30 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports 12.4 INTERRUPTS 12.4.1 Interrupt Configuration The CN module has a dedicated interrupt flag bit CNIF and a corresponding interrupt enable/mask bit, CNIE. These bits are used to determine the source of an interrupt and to enable or disable an individual interrupt source. The CNIE bit is used to define the behavior of the Interrupt Controller when a corresponding CNIF is set. When the CNIE bit is clear, the Interrupt Controller module does not generate a CPU interrupt for the event. If the CNIE bit is set, the Interrupt Controller module will generate an interrupt to the CPU when the corresponding CNIF bit is set (subject to the priority and subpriority as outlined below). It is the responsibility of the user’s software routine that services a particular interrupt to clear the appropriate interrupt flag bit before the service routine is complete. The priority of the CN module can be set with the CNIP<2:0> bits. This priority defines the priority group to which the interrupt source will be assigned. The priority groups range from a value of 7 (the highest priority), to a value of 0 (which does not generate an interrupt). An interrupt being serviced will be preempted by an interrupt in a higher priority group. The subpriority bits allow setting the priority of a interrupt source within a priority group. The values of the subpriority CNIS<1:0> range from 3 (the highest priority), to 0 (the lowest priority). An interrupt with the same priority group but having a higher subpriority value will preempt a lower subpriority interrupt that is in progress. The priority group and subpriority bits allow more than one interrupt source to share the same Priority and subpriority. If simultaneous interrupts occur in this configuration, the natural order of the interrupt sources within a priority/sub-group pair determine the interrupt generated. The natural priority is based on the vector numbers of the interrupt sources. The lower the vector number the higher the natural priority of the interrupt. Any interrupts that were overridden by natural order will then generate their respective interrupts based on priority, subpriority, and natural order after the interrupt flag for the current interrupt is cleared. After an enabled interrupt is generated, the CPU jumps to the vector assigned to that interrupt. The vector number for the interrupt is the same as the natural order number. The CPU then begins executing code at the vector address. The user’s code at this vector address should perform any application specific operations and clear the CNIF interrupt flag, and then exit. Refer to Section 8. “Interrupts” for the vector address table details for more information on interrupts. 12 Table 12-2: Change Notice Interrupt Vector with EBASE = 0x8000:0000 Interrupt Vector/ Natural Order IRQ Number Vector Address IntCtl.VS = 0x01 Vector Address IntCtl.VS = 0x02 Vector Address IntCtl.VS = 0x04 CN 23 23 8000 04E0 8000 07C0 8000 0D80 Vector Address IntCtl.VS = 0x08 8000 1900 Vector Address IntCtl.VS = 0x10 8000 3000 Table 12-3: Example of Priority and Subpriority Assignment Interrupt Priority Group Subpriority CN 7 3 Vector/Natural Order 23 © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-31 PIC32MX Family Reference Manual Example 12-1: Change Notice Configuration Example /* The following code example illustrates a Change Notice interrupt configuration for pins CN1(PORTC.RC13), CN4(PORTB.RB2) and CN18(PORTF.RF5). */ /* NOTE: disable vector interrupts prior to configuration */ CNCON = 0x8000; CNEN = 0x00040012; CNPUE = 0x00040012; // Enable Change Notice module // Enable individual CN pins CN1, CN4 and CN18 // Enable weak pull ups for pins CN1, CN4 and CN18 /* read port(s) to clear mismatch on change notice pins */ PORTB; PORTC; PORTF; IPC6SET = 0x00140000; IPC6SET = 0x00030000; // Set priority level=5 // Set Subpriority level=3 // Could have also done this in single // operation by assigning IPC6SET = 0x00170000 IFS1CLR = 0x0001; IEC1SET = 0x0001; // Clear the interrupt flag status bit // Enable Change Notice interrupts /* re-enable vector interrupts after configuration */ Example 12-2: Change Notice ISR Code Example /* The following code example demonstrates a simple interrupt service routine for CN interrupts. The user’s code at this vector can perform any application specific operations. The user’s code must read the CN corresponding PORT registers to clear the mismatch conditions before clearing the CN interrupt status flag. Finally, the CN interrupt status flag must be cleared before exiting. */ void __ISR(_CHANGE_NOTICE_VECTOR, ipl5 ChangeNoticeHandler(void) { ... perform application specific operations in response to the interrupt readB = PORTB readC = PORTC readF = PORTF ... IFS1CLR = 0x0001; { // Read PORTB to clear CN4 mismatch condition // Read PORTC to clear CN1 mismatch condition // Read PORTF to clear CN18 mismatch condition // Be sure to clear the CN interrupt status // flag before exiting the service routine. Note: The CN ISR code example shows MPLAB® C32 C compiler specific syntax. Refer to your compiler manual regarding support for ISRs. DS61120D-page 12-32 Preliminary © 2008 Microchip Technology Inc. I/O Ports Section 12. I/O Ports 12.5 OPERATION IN POWER-SAVING AND DEBUG MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 12.5.1 I/O Port Operation in SLEEP Mode As the device enters SLEEP mode, the system clock is disabled; however, the CN 12 module continues to operate. If one of the enabled CN pins changes state, the Status bit CNIF (IFS1<0>) will be set. If the CNIE bit (IEC1<0>) is set, and its priority is greater than current CPU priority, the device will wake from SLEEP or IDLE mode and execute the CN Interrupt Service Routine. If the assigned priority level of the CN interrupt is less than or equal to the current CPU priority level, the CPU will not be awakened and the device will enter IDLE mode. 12.5.2 I/O Port Operation in IDLE Mode As the device enters IDLE mode, the system clock sources remain functional. The SIDL bit (CNCON<13>) selects whether the module will stop or continue functioning on IDLE. • If SIDL = 1, the module will continue to sample Input CN I/O pins in IDLE mode, however, synchronization is disabled. • If SIDL = 0, the module will continue to synchronize and sample Input CN I/O pins in IDLE mode. 12.5.3 I/O Port Operation in DEBUG Mode The FRZ bit (CNCON<14>) determines whether the CN module will run or stop while the CPU is executing DEBUG exception code (i.e., application is halted) in DEBUG mode. • If FRZ = 0, the module continues to operate even when application is halted in DEBUG mode. • If FRZ = 1 and application is halted in DEBUG mode, the module will freeze its operations and make no changes to the state of the CN module. The module will resume its operation after CPU resumes execution. Note: The FRZ bit is readable and writable only when the CPU is executing in Debug Exception mode. In all other modes, the FRZ bit reads as ‘0’. If FRZ bit is changed during DEBUG mode, the new value does not take effect until the current Debug Exception mode is exited and re-entered. During the Debug Exception mode, the FRZ bit reads the state of the peripheral when entering DEBUG mode. © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-33 PIC32MX Family Reference Manual 12.6 EFFECTS OF VARIOUS RESETS 12.6.1 Device Reset All TRIS, LAT, PORT, ODC, CNEN, CNPUE and CNCON registers are forced to their Reset states upon a device Reset. 12.6.2 Power-On Reset All TRIS, LAT, PORT, ODC, CNEN, CNPUE and CNCON registers are forced to their Reset states upon a Power-on Reset. 12.6.3 Watchdog Reset All TRIS, LAT, PORT, ODC, CNEN, CNPUE and CNCON registers are unchanged upon a Watchdog Reset. DS61120D-page 12-34 Preliminary © 2008 Microchip Technology Inc. Section 12. I/O Ports 12.7 I/O Port Application Example 12-3: Code Example /* The following code example illustrates configuring RB0, RB1 as analog (default) inputs, RB2 as a digital input, RB3 as digital output and RB4 as digital output with open-drain enabled using SET, CLR atomic SFR registers.*/ AD1PCFGCLR = 0x0003; TRISBSET = 0x0003; // RB0, RB1 = analog pins // RB0, RB1 = inputs AD1PCFGSET = 0x000C; TRISBSET = 0x0004; TRISBCLR = 0x0018; // RB2, RB3 = digital pins // RB2 = input // RB3, RB4 = outputs ODCBSET = 0x0010; // RB4 open-drain enabled /* The following code example illustrates same configuration above using Base SFR registers directly.*/ AD1PCFG = 0x001C; TRISB = 0x0007; // RB0, RB1 = analog pins; RB2, RB3, RB4 = digital pins // RB0, RB1, RB2 = inputs; RB3, RB4 = outputs ODCB = 0x0010; // RB4 open-drain enabled 12 I/O Ports © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-35 PIC32MX Family Reference Manual 12.8 I/O PIN CONTROL Table provides a summary of I/O pin mode settings. Table 12-4: I/O Pin Configurations Required Settings for Digital Pin Control Mode or Pin Usage Pin Type Buffer Type TRIS Bit ODC Bit CNEN Bit Input CN Output Open Drain IN ST 1 IN ST 1 OUT CMOS 0 OUT OPEN 0 — — — 1 0 — 1 — CNPUE Bit(1) — 1 — — AD1PCFG Bit 1 1 1 1 Mode or Pin Usage ANx Input CV Output Required Settings for Analog Pin Control Pin Type Buffer Type IN A OUT A TRIS Bit 1 — ODC Bit — — CNEN Bit — — CNPUE Bit(1) — — AD1PCFG Bit 0 0 Mode or Pin Usage TCK TDI TMS TDO Required Settings for JTAG Pin Control(2) Pin Type Buffer Type IN IN IN OUT ST ST ST CMOS TRIS Bit — — — — ODC Bit — — — — CNEN Bit — — — — CNPUE Bit(1) — — — — AD1PCFG Bit — — — — Required Settings for ICSP Pin Control(3) Mode or Pin Usage Pin Type Buffer Type TRIS Bit ODC Bit CNEN Bit CNPUE Bit(1) AD1PCFG Bit PGC IN ST — — — — — OUT CMOS — — — — — PGD IN ST — — — — — OUT CMOS — — — — — Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output Note 1: The CN Enable Pull-up bit is optional. 2: The pin control for the JTAG module is automatically set when JTAG is enabled and the corresponding DEBUGGING mode is selected. No user configuration is required. 3: The pin control for the ICSP™ module is set automatically when entering ICSP mode. No user configuration is required. DS61120D-page 12-36 Preliminary © 2008 Microchip Technology Inc. Section 12. I/O Ports 12.9 DESIGN TIPS Question 1: How should I configure my unused I/O pins? Answer: I/O pins that are not used can be set as outputs (corresponding TRIS bit = 0) and driven low (corresponding LAT bit = 0) in software. Question 2: Is it possible to connect PIC32MX I/O pins to a 5V device? Answer: Yes, with limitations. PIC32MX I/O pins are 5V tolerant when configured as an input, which means the pin can tolerate an input up to 5V. When configured as an output, an I/O pin can only drive as high as the voltage supplied to the PIC32MX VDD pin, which is limited to 3.6V. Depending on the 5V device’s input pin design, this may not be sufficient to be correctly read as 12 a logic “high” signal. For a detailed discussion on interfacing different logic level families, refer to the “Microchip 3V Tips ‘n Tricks” (DS41285) guide. I/O Ports © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-37 PIC32MX Family Reference Manual 12.10 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the I/O Ports are: Title Implementing Wake-up on Key Stroke Application Note # AN552 Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. DS61120D-page 12-38 Preliminary © 2008 Microchip Technology Inc. Section 12. I/O Ports 12.11 REVISION HISTORY Revision A (August 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x; Revised Register 12-13; Revised Figure 12-1 and 12-2. Revision D (May 2008) 12 Revised Register 12-17, add note to FRZ; Add note to Registers 12-19, 12-30, 12-31; Revised Example 12-1 and 12-2; Change Reserved bits from “Maintain as” to “Write”; Added Note to ON bit (CNCON Register). I/O Ports © 2008 Microchip Technology Inc. Preliminary DS61120D-page 12-39 PIC32MX Family Reference Manual NOTES: DS61120D-page 12-40 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port HIGHLIGHTS This section of the manual contains the following topics: 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 13.12 13.13 Introduction.............................................................................................................. 13-2 Control Registers..................................................................................................... 13-3 Master Modes of Operation ................................................................................... 13-26 Slave Modes of Operation ..................................................................................... 13-51 Interrupts................................................................................................................ 13-59 Operation in Power-Saving and DEBUG Modes ................................................... 13-61 Effects of Various Resets....................................................................................... 13-62 Parallel Master Port Applications........................................................................... 13-62 Parallel Slave Port Applications............................................................................. 13-68 I/O Pin Control ....................................................................................................... 13-69 Design Tips ............................................................................................................ 13-71 Related Application Notes ..................................................................................... 13-72 Revision History..................................................................................................... 13-73 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-1 PIC32MX Family Reference Manual 13.1 INTRODUCTION The Parallel Master Port (PMP) is a parallel 8-bit/16-bit I/O module specifically designed to communicate with a wide variety of parallel devices such as communications peripherals, LCDs, external memory devices, and microcontrollers. Because the interfaces to parallel peripherals vary significantly, the PMP module is highly configurable. Key features of the PMP module include: • Up to 16 programmable address lines • Up to two Chip Select lines • Programmable strobe options - individual read and write strobes, or - read/write strobe with enable strobe • Address auto-increment/auto-decrement • Programmable address/data multiplexing • Programmable polarity on control signals • Legacy parallel slave port support • Enhanced parallel slave support - address support - 4-bytes-deep, auto-incrementing buffer • Programmable Wait states • Freeze option for in-circuit debugging Figure 13-1: PMP Module Pinout and Connections to External Devices PIC32MX Parallel Master Port PMA0 PMALL PMA1 PMALH PMA<13:2> Address Bus Data Bus Control Lines Up to 16-Bit Address EEPROM PMA14 PMCS1 PMA15 PMCS2 PMRD PMRD/PMWR PMWR PMENB PMA<7:0> PMA<15:8> PMD<7:0> PMD<15:8>(1) Microcontroller LCD FIFO buffer 8-Bit/16-Bit Data (with or without multiplexed addressing) Note 1: Data pins PMD<15:8> are available only on 100-pin PIC32MX device variants and larger. DS61128D-page 13-2 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.2 CONTROL REGISTERS The PMP module uses these Special Function Registers (SFRs): • PMCON: Parallel Master Port Control Register PMCONCLR, PMCONSET, PMCONINV: Atomic Bit Manipulation, Write-only Registers for PMCON • PMMODE: Parallel Master Port Mode Control Register PMMODECLR, PMMODESET, PMMODEINV: Atomic Bit Manipulation, Write-only Registers for PMMODE • PMADDR: Parallel Master Port Address Register PMADDRCLR, PMADDRSET, PMADDRINV: Atomic Bit Manipulation, Write-only Registers for PMDOUT • PMDOUT: Parallel Master Port Data Output Register PMDOUTCLR, PMDOUTSET, PMDOUTINV: Atomic Bit Manipulation, Write-only Registers for PMDOUT • PMDIN: Parallel Master Port Data Input Register PMDINCLR, PMDINSET, PMDININV: Atomic Bit Manipulation, Write-only Registers for PMDIN • PMAEN: Parallel Master Port Address Enable Register PMAENCLR, PMAENSET, PMAENINV: Atomic Bit Manipulation, Write-only Registers for PMAEN • PMSTAT: Parallel Master Port Status Register PMSTATCLR, PMSTATSET, PMSTATINV: Atomic Bit Manipulation, Write-only Registers for PMSTAT The PMP module also has the following associated bits for interrupt control: • Interrupt Enable Control bit (PMPIE) in IEC1: Interrupt Enable Control Register 1 • Interrupt Flag Status bit (PMPIF) in IFS1: Interrupt Flag Status Register 0 • Interrupt Priority Control bits (PMPIP<2:0>) and (PMPIS<1:0>) in IPC7: Interrupt Priority Control Register 7 13 13.2.1 PMCON Register PMCON (Register 13-1) contains the bits that control much of the module’s basic functionality. A key bit is ON, which is used to reset the module enable or disable the module. When the module is disabled, all the associated I/O pins revert to their designated I/O function. In addition, any read or write operations active or pending are stopped, and the BUSY bit is cleared. The data within the module registers is retained, including the data in PMSTAT. Thus, the module could be disabled after a reception, and the last received data and status would still be available for processing. When the module is enabled, all buffer control logic is reset, along with PMSTAT. All other bits in PMCON control address multiplexing, enable various port control signals, and select control signal polarity. These are discussed in more detail in Section 13.3.1 “Parallel Master Port Configuration Options”. 13.2.2 PMMODE Register PMMODE (Register 13-5) contains bits that control the operational modes of the module. Master/Slave mode selection, as well as configuration options for both modes, are set by this register. It also contains the universal status flag BUSY, used in master modes to indicate that an operation by the module in progress. Details on the use of the PMMODE bits to configure PMP operation are provided in Section 13.4 “Slave Modes of Operation” and Section 13.3 “Master Modes of Operation”. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-3 PIC32MX Family Reference Manual 13.2.3 PMADDR Register PMADDR (Register 13-9) functions as PMADDR in master modes. It contains the address to which outgoing data is to be written, as well as the Chip Select control bits for addressing parallel slave devices. The PMADDR register is not used in any of the Slave modes. 13.2.4 PMDOUT Register PMDOUT is only used in Slave mode for buffered output data. 13.2.5 PMDIN Register PMDIN is used by the module in both Master and Slave modes. In Slave mode, this register is used to hold data that is asynchronously clocked in. Its operation is described in Section 13.4.2 “Buffered Parallel Slave Port Mode”. In Master mode, PMDIN is the holding register for both incoming and outgoing data. Its operation in Master mode is described in Section 13.3.3 “Read Operation” and Section 13.3.4 “Write Operation”. 13.2.6 PMAEN Register Parallel Master Port Address Enable register (Register 13-21) controls the operation of address and Chip Select pins associated to this module. Setting these bits allocates the corresponding microcontroller pins to the PMP module; clearing the bits allocates the pins to port I/O or other peripheral modules associated with the pin. 13.2.7 PMSTAT Register The Parallel Port Status register (Register 13-25) contains Status bits associated with buffered operating modes when the port is functioning as a Slave port. This includes overflow, underflow, and full flag bit. These flags are discussed in detail in Section 13.4.2 “Buffered Parallel Slave Port Mode”. DS61128D-page 13-4 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.2.8 PMP SFR Summary The following table provides a brief summary of all PMP-module-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Table 13-1: PMP SFR Summary Name Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 PMCON PMCONCLR PMCONSET PMCONINV PMMODE PMMODECLR PMMODESET PMMODEINV PMADDR PMADDRCLR PMADDRSET PMADDRINV PMDOUT PMDOUTCLR PMDOUTSET PMDOUTINV PMDIN PMDINCLR PMDINSET PMDININV PMAEN PMAENCLR PMAENSET PMAENINV 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 — — — — — — — — — — — — — — — — ON FRZ SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP CS2P CS1P — WRSP RDSP Write clears selected bits in PMCON, read yields undefined value Write sets selected bits in PMCON, read yields undefined value Write inverts selected bits in PMCON, read yields undefined value — — — — — — — — — — — — — — — — BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> Write clears selected bits in PMMODE, read yields undefined value Write sets selected bits in PMMODE, read yields undefined value Write inverts selected bits in PMMODE, read yields undefined value — — — — — — — — — — — — — — — — CS2/A15 CS1/A14 ADDR<13:8> ADDR<7:0> Write clears selected bits in PMADDR, read yields undefined value Write sets selected bits in PMADDR, read yields undefined value Write inverts selected bits in PMADDR, read yields undefined value DATAOUT<31:24> DATAOUT<23:16> DATAOUT<15:8> DATAOUT<7:0> Write clears selected bits in PMDOUT, read yields undefined value Write sets selected bits in PMDOUT, read yields undefined value Write inverts selected bits in PMDOUT, read yields undefined value DATAIN<31:24> DATAIN<23:16> DATAIN<15:8> DATAIN<7:0> Write clears selected bits in PMDIN, read yields undefined value Write sets selected bits in PMDIN, read yields undefined value Write inverts selected bits in PMDIN, read yields undefined value — — — — — — — — — — — — — — — — PTEN<15:8> PTEN<7:0> Write clears selected bits in PMAEN, read yields undefined Write sets selected bits in PMAEN, read yields undefined Write inverts selected bits in PMAEN, read yields undefined 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-5 PIC32MX Family Reference Manual Table 13-1: Name PMSTAT PMSTATCLR PMSTATSET PMSTATINV IEC1 IFS1 IPC7 PMP SFR Summary (Continued) Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0 — — IBF OBE — — RTCCIE SPI2RXIE — — RTCCIF SPI2RXIF — — — — — — — — — — — — — — — — — — IBOV — — IB3F IB2F IB1F IB0F OBUF — — OB3E OB2E OB1E OB0E Write clears selected bits in PMSTAT, read yields undefined value Write sets selected bits in PMSTAT, read yields undefined value Write inverts selected bits in PMSTAT, read yields undefined value — — — — — USBIE FCEIE — — — DMA3IE DMA2IE DMA1IE DMA0IE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE — — — — — USBIF FCEIF — — — DMA3IF DMA2IF DMA1IF DMA0IF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF — — SPI2IP<2:0> SPI2IS<1:0> — — CMP2IP<2:0> CMP2IS<1:0> — — CMP1IP<2:0> CMP1IS<1:0> — — PMPIP<2:0> PMPIS<1:0> DS61128D-page 13-6 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Parallel Master Port Register 13-1: PMCON: Parallel Port Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R/W-0 ON bit 15 R/W-0 FRZ R/W-0 SIDL R/W-0 R/W-0 ADRMUX1 ADRMUX0 R/W-0 PMPTTL R/W-0 PTWREN R/W-0 PTRDEN bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x R/W-0 R/W-0 CSF1 CSF0 ALP CS2P CS1P — WRSP RDSP bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 Reserved: Write ‘0’; ignore read ON: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 14 FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation even when CPU is in Debug Exception mode Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode. bit 13 SIDL: Stop in IDLE Mode bit 1 = Discontinue module operation when device enters IDLE mode 0 = Continue module operation in IDLE mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = All 16 bits of address are multiplexed on PMD<15:0> pins 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8> 00 = Address and data appear on separate pins bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmidt Trigger input buffer bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled Note 1: These bits have no effect when their corresponding pins are used as address lines. 13 © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-7 PIC32MX Family Reference Manual Register 13-1: PMCON: Parallel Port Control Register (Continued) bit 7-6 CSF<1:0>: Chip Select Function bits(1) 11 = Reserved 10 = PMCS2 and PMCS1 function as Chip Select 01 = PMCS2 functions as Chip Select, PMCS1 functions as address bit 14 00 = PMCS2 and PMCS1 function as address bits 15 and 14 bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 CS2P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS2) 0 = Active-low (PMCS2) bit 3 CS1P: Chip Select 0 Polarity bit(1) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) bit 2 Reserved: Write ‘0’; ignore read bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Read Strobe active-high (PMRD) 0 = Read Strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. DS61128D-page 13-8 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Register 13-2: PMCONCLR: PMP Control Clear Register Write clears selected bits in PMCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PMCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PMCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMCONCLR = 0x00008001 will clear bits 15 and 0 in PMCON register. Register 13-3: PMCONSET: PMP Control Set Register Write sets selected bits in PMCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PMCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PMCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMCONSET = 0x00008001 will set bits 15 and 0 in PMCON register. 13 Register 13-4: PMCONINV: PMP Control Invert Register Write inverts selected bits in PMCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PMCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PMCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMCONINV = 0x00008001 will invert bits 15 and 0 in PMCON register. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-9 PIC32MX Family Reference Manual Register 13-5: PMMODE: Parallel Port Mode Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R-0 BUSY bit 15 R/W-0 R/W-0 IRQM<1:0> R/W-0 R/W-0 INCM<1:0> R/W-0 MODE16 R/W-0 R/W-0 MODE<1:0> bit 8 R/W-0 R/W-0 WAITB<1:0> bit 7 R/W-0 R/W-0 R/W-0 WAITM<3:0> R/W-0 R/W-0 R/W-0 WAITE<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 Reserved: Write ‘0’; ignore read bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14-13 IRQM<1:0>: Interrupt Request Mode bits 11 = Reserved, do not use 10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only) 01 = Interrupt generated at the end of the read/write cycle 00 = No Interrupt generated bit 12-11 INCM<1:0>: Increment Mode bits 11 = Slave mode read and write buffers auto-increment (PMMODE<1:0> = 00 only) 10 = Decrement ADDR<15:0> by 1 every read/write cycle(2) (4) 01 = Increment ADDR<15:0> by 1 every read/write cycle(2) (4) 00 = No increment or decrement of address bit 10 MODE16: 8/16-bit Mode bit 1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer 0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA, PMD<7:0> and PMD<8:15>(3)) 10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA, PMD<7:0> and PMD<8:15>(3)) 01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS, PMD<7:0>, and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS, and PMD<7:0>) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bit A15 and A14 are not subject to auto-increment/decrement if configured as Chip Select CS2 and CS1. 3: These pins are active when bit MODE16 = 1 (16-bit mode) 4: The PMPADDR register is always incremented/decremented by 1 regardless of the transfer data width. DS61128D-page 13-10 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Register 13-5: PMMODE: Parallel Port Mode Register (Continued) bit 7-6 WAITB1:WAITB0: Data Setup to Read/Write Strobe Wait States bits(1) 11 =Data wait of 4 TPB; multiplexed address phase of 4 TPB 10 =Data wait of 3 TPB; multiplexed address phase of 3 TPB 01 =Data wait of 2 TPB; multiplexed address phase of 2 TPB 00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (DEFAULT) bit 5-2 WAITM3:WAITM0: Data Read/Write Strobe Wait States bits bit 1-0 1111 =Wait of 16 TPB ... 0001 =Wait of 2 TPB 0000 = Wait of 1 TPB (DEFAULT) WAITE1:WAITE0: Data Hold After Read/Write Strobe Wait States bits(1) 11 =Wait of 4 TPB 10 =Wait of 3 TPB 01 =Wait of 2 TPB 00 =Wait of 1 TPB (DEFAULT) for Read operations: 11 =Wait of 3TPB 10 =Wait of 2TPB 01 =Wait of 1TPB 00 = Wait of 0TPB (DEFAULT) Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bit A15 and A14 are not subject to auto-increment/decrement if configured as Chip Select CS2 and CS1. 3: These pins are active when bit MODE16 = 1 (16-bit mode) 4: The PMPADDR register is always incremented/decremented by 1 regardless of the transfer data width. 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-11 PIC32MX Family Reference Manual Register 13-6: PMMODECLR: PMMODE Clear Register Write clears selected bits in PMMODE, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PMMODE A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PMMODE register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMMODECLR = 0x00008001 will clear bits 15 and 0 in PMMODE register. Register 13-7: PMMODESET: PMMODE Set Register Write sets selected bits in PMMODE, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PMMODE A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PMMODE register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMMODESET = 0x00008001 will set bits 15 and 0 in PMMODE register. Register 13-8: PMMODEINV: PMMODE Invert Register Write inverts selected bits in PMMODE, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PMMODE A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PMMODE register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMMODEINV = 0x00008001 will invert bits 15 and 0 in PMMODE register. DS61128D-page 13-12 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Register 13-9: PMADDR: Parallel Port Address Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R/W-0 CS2 bit 15 R/W-0 CS1 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<13:8> R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14 bit 13-0 Reserved: Write ‘0’; ignore read CS2: Chip Select 2 bit 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive (pin functions as PMA<15>) CS1: Chip Select 1 bit 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive (pin functions as PMA<14>) ADDR<13:0>: Destination Address bits 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-13 PIC32MX Family Reference Manual Register 13-10: PMADDRCLR: PMADDR Clear Register Write clears selected bits in PMADDR, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PMADDR A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PMADDR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMADDRCLR = 0x00008001 will clear bits 15 and 0 in PMADDR register. Register 13-11: PMADDRSET: PMADDR Set Register Write sets selected bits in PMADDR, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PMADDR A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PMADDR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMADDRSET = 0x00008001 will set bits 15 and 0 in PMADDR register. Register 13-12: PMADDRINV: PMADDR Invert Register Write inverts selected bits in PMADDR, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PMADDR A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PMADDR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMADDRINV = 0x00008001 will invert bits 15 and 0 in PMADDR register. DS61128D-page 13-14 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Register 13-13: PMDOUT: Parallel Port Data Output Register R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATAOUT<31:24> bit 31 R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 R/W-0 R/W-0 DATAOUT<23:16> R/W-0 R/W-0 R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 DATAOUT<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 DATAOUT<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit 13 bit 31-0 DATAOUT<31:0>: Output Data Port bits for 8-bit write operations in Slave mode Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-15 PIC32MX Family Reference Manual Register 13-14: PMDOUTCLR: PMDOUT Clear Register Write clears selected bits in PMDOUT, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PMDOUT A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PMDOUT register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMDOUTCLR = 0x00008001 will clear bits 15 and 0 in PMDOUT register. Register 13-15: PMDOUTSET: PMDOUT Set Register Write sets selected bits in PMDOUT, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PMDOUT A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PMDOUT register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMDOUT = 0x00008001 will set bits 15 and 0 in PMDOUT register. Register 13-16: PMDOUTINV: PMDOUT Invert Register Write inverts selected bits in PMDOUT, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PMDOUT A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PMDOUT register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMDOUTINV = 0x00008001 will invert bits 15 and 0 in PMDOUT register. DS61128D-page 13-16 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Register 13-17: PMDIN: Parallel Port Data Input Register R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATAIN<31:24> bit 31 R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 R/W-0 R/W-0 DATAIN<23:16> R/W-0 R/W-0 R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 DATAIN<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 DATAIN<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit 13 bit 31-0 DATAIN<31:0>: Input and Output Data Port bits for 8-bit or 16-bit read/write operations in Master mode Input Data Port for 8-bit read operations in Slave mode. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-17 PIC32MX Family Reference Manual Register 13-18: PMDINCLR: PMDIN Clear Register Write clears selected bits in PMDIN, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PMDIN A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PMDIN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMDINCLR = 0x00008001 will clear bits 15 and 0 in PMDIN register. Register 13-19: PMDINSET: PMDIN Set Register Write sets selected bits in PMDIN, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PMDIN A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PMDIN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMDINSET = 0x00008001 will set bits 15 and 0 in PMDIN register. Register 13-20: PMDININV: PMDIN Invert Register Write inverts selected bits in PMDIN, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PMDIN A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PMDIN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMDININV = 0x00008001 will invert bits 15 and 0 in PMDIN register. DS61128D-page 13-18 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Register 13-21: PMAEN: Parallel Port Pin Enable Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit 13 bit 31-16 Reserved: Write ‘0’; ignore read bit 15-14 PTEN<15:14>: PMCSx Strobe Enable bits 1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1(1) 0 = PMA15 and PMA14 function as port I/O bit 13-2 PTEN<13:2>: PMP Address Port Enable bits 1 = PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2) 0 = PMA1 and PMA0 pads functions as port I/O Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 are selected by bits CSF<1:0> in the PMCON register. 2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depend on the Address/Data Multiplex mode selected by bits ADRMUX<1:0> in the PMCON register. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-19 PIC32MX Family Reference Manual Register 13-22: PMAENCLR: PMAEN Clear Register Write clears selected bits in PMAEN, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PMAEN A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PMAEN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMAENCLR = 0x00008001 will clear bits 15 and 0 in PMAEN register. Register 13-23: PMAENSET: PMAEN Set Register Write sets selected bits in PMAEN, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PMAEN A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PMAEN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMAENSET = 0x00008001 will set bits 15 and 0 in PMAEN register. Register 13-24: PMAENINV: PMAEN Invert Register Write inverts selected bits in PMAEN, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PMAEN A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PMAEN register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMAENINV = 0x00008001 will invert bits 15 and 0 in PMAEN register. DS61128D-page 13-20 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Register 13-25: PMSTAT: Parallel Port Status Register (Slave modes only) r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R-0 R/W-0 r-x IBF IBOV — bit 15 r-x R-0 R-0 R-0 R-0 — IB3F IB2F IB1F IB0F bit 8 R-1 R/W-0 r-x OBE OBUF — bit 7 r-x R-1 R-1 R-1 R-1 — OB3E OB2E OB1E OB0E bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14 bit 13-12 bit 11-8 bit 7 bit 6 bit 5-4 bit 3-0 Reserved: Write ‘0’; ignore read IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte buffer occurred (must be cleared in software) 0 = No overflow occurred This bit is set (= 1) in hardware; can only be cleared (= 0) in software. Reserved: Write ‘0’; ignore read IBnF: Input Buffer n Status Full bits 1 = Input Buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input Buffer does not contain any unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte buffer (must be cleared in software) 0 = No underflow occurred This bit is set (= 1) in hardware; can only be cleared (= 0) in software. Reserved: Write ‘0’; ignore read OBnE: Output Buffer n Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-21 PIC32MX Family Reference Manual Register 13-26: PMSTATCLR: PMSTAT Clear Register Write clears selected bits in PMSTAT, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PMSTAT A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PMSTAT register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMSTATCLR = 0x00008001 will clear bits 15 and 0 in PMSTAT register. Register 13-27: PMSTATSET: PMSTAT Set Register Write sets selected bits in PMSTAT, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PMSTAT A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PMSTAT register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMSTATSET = 0x00008001 will set bits 15 and 0 in PMSTAT register. Register 13-28: PMSTATINV: PMSTAT Invert Register Write inverts selected bits in PMSTAT, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PMSTAT A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PMSTAT register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PMSTATINV = 0x00008001 will invert bits 15 and 0 in PMSTAT register. DS61128D-page 13-22 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Register 13-29: IEC1: Interrupt Enable Control Register 1(1) r-x r-x r-x r-x r-x — — — — — bit 31 r-x R/W-0 R/W-0 — USBIE FCEIE bit 24 r-x — bit 23 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IE DMA2IE DMA1IE DMA0IE bit 16 R/W-0 RTCCIE bit 15 R/W-0 FSCMIE R/W-0 I2C2MIE R/W-0 I2C2SIE R/W-0 I2C2BIE R/W-0 U2TXIE R/W-0 U2RXIE R/W-0 U2EIE bit 8 R/W-0 SPI2RXIE bit 7 R/W-0 SPI2TXIE R/W-0 SPI2EIE R/W-0 CMP2IE R/W-0 CMP1IE R/W-0 PMPIE R/W-0 AD1IE R/W-0 CNIE bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit 13 bit 2 Note 1: PMPIE: PMP Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the PMP. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-23 PIC32MX Family Reference Manual Register 13-30: IFS1: Interrupt Flag Status Control Register 1(1) r-x r-x r-x r-x r-x — — — — — bit 31 r-x R/W-0 R/W-0 — USBIF FCEIF bit 24 r-x — bit 23 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IF DMA2IF DMA1IF DMA0IF bit 16 R/W-0 RTCCIF bit 15 R/W-0 FSCMIF R/W-0 I2C2MIF R/W-0 I2C2SIF R/W-0 I2C2BIF R/W-0 U2TXIF R/W-0 U2RXIF R/W-0 U2EIF bit 8 R/W-0 SPI2RXIF bit 7 R/W-0 SPI2TXIF R/W-0 SPI2EIF R/W-0 CMP2IF R/W-0 CMP1IF R/W-0 PMPIF R/W-0 AD1IF R/W-0 CNIF bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 2 Note 1: PMPIF: PMP Interrupt Flag bits 1 = Interrupt flag is enabled 0 = Interrupt flag is disabled Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the PMP. DS61128D-page 13-24 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Register 13-31: IPC7: Interrupt Priority Control Register 7(1) r-x r-x r-x R/W-0 R/W-0 — — — SPI2IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 SPI2IS<1:0> bit 24 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CMP2IP<2:0> CMP2IS<1:0> bit 23 bit 16 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CMP1IP<2:0> CMP1IS<1:0> bit 15 bit 8 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PMPIP<2:0> PMPIS<1:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 4-2 PMPIP<2:0>: PMP Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled bit 1-0 PMPIS<1:0>: PMP Interrupt Subpriority bits 11 = Interrupt Subpriority is 3 10 = Interrupt Subpriority is 2 01 = Interrupt Subpriority is 1 00 = Interrupt Subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the PMP. 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-25 PIC32MX Family Reference Manual 13.3 MASTER MODES OF OPERATION In its master modes, the PMP module can provide a 16-bit or 8-bit data bus, up to 16 bits of address, and all the necessary control signals to operate a variety of external parallel devices such as memory devices, peripherals, and slave microcontrollers. The PMP master modes provide a simple interface for reading and writing data, but not executing program instructions from external devices, such as SRAM or Flash memories. Because there are a number of parallel devices with a variety of control methods, the PMP module is designed for flexibility to accommodate a range of configurations. Some of these features include: • 8-Bit and 16-Bit Data modes • Configurable address/data multiplexing • Up to 2 Chip Select lines • Up to 16 selectable address lines • Address auto-increment and auto-decrement • Selectable polarity on all control lines • Configurable Wait states at different stages of the read/write cycle 13.3.1 Parallel Master Port Configuration Options 13.3.1.1 8-Bit and 16-Bit Data Modes The PMP in Master mode supports data widths 8 and 16 bits wide. By default, the data width is 8-bit, MODE16 (PMMODE<10>) bit = 0. To select 16-bit data width, set MODE16 = 1. When configured in 8-bit Data mode, the upper 8 bits of the data bus, PMD<15:8>, are not controlled by the PMP module and are available as general purpose I/O pins. Note: Data pins PMD<15:0> are available on 100-pin PIC32MX device variants. For 64-pin device variants, only pins PMD<7:0> are available. Refer to the specific PIC32MX device data sheet for details. 13.3.1.2 Chip Selects Two Chip Select lines, PMCS1 and PMCS2, are available for the master modes. The two Chip Select lines are multiplexed with the Most Significant bits of the address bus A14 and A15. When a pin is configured as a Chip Select, it is not included in any address auto-increment/decrement. It is possible to enable both PMCS2 and PMCS1 as Chip Selects, or enable only PMCS2 as a Chip Select, allowing PMCS1 to function strictly as address line A14. It is not possible to enable PMCS1 alone. The Chip Select signals are configured using the Chip Select Function bits CSF<1:0> (PMCON <7:6>). Table 13-2: Chip Select Control CSF<1:0> 00 01 10 FUNCTION PMCS2 = A15, PMCS1 = A14 PMCS2 = Enabled, PMCS1 = A14 PMCS2, PMCS1 = Enabled DS61128D-page 13-26 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.3.1.3 PORT Pin Control There are several bits available to configure the presence or absence of control and address signals in the module. These bits are PTWREN (PMCON<9>), PTRDEN (PMCON<8>), and PTEN<15:0> (PMAEN<15:0>). They give the user the ability to conserve pins for other functions and allow flexibility to control the external address. When any one of these bits is set, the associated function is present on its associated pin; when clear, the associated pin reverts to its defined I/O port function. Setting a PTEN bit will enable the associated pin as an address pin and drive the corresponding data contained in the PMADDR register. Clearing any PTEN bit will force the pin to revert to its original I/O function. For the pins configured as Chip Select (PMCS1 or PMCS2) with the corresponding PTEN bit set, Chip Select pins drive inactive data when a read or write operation is not being performed. The PTEN0 and PTEN1 bits also control the PMALL and PMALH signals. When multiplexing is used, the associated address latch signals should be enabled. Refer to Section 13.10 “I/O Pin Control” later in this chapter regarding I/O pin configuration. 13.3.1.4 Read/Write Control The PMP module supports two distinct read/write signaling methods. In Master mode 1, read and write strobe are combined into a single control line, PMRD/PMWR; a second control line, PMENB, determines when a read or write action is to be taken. In Master mode 2, read and write strobes (PMRD and PMWR) are supplied on separate pins. 13.3.1.5 Control Line Polarity All control signals (PMRD, PMWR, PMENB, PMALL, PMALH, PMCS2 and PMCS1) can be individually configured for either positive or negative polarity. Configuration is controlled by separate bits in the PMCON register. Table 13-3: PIN POLARITY CONFIGURATION CONTROL PIN PMCON Control Bit Active-High Select Active-Low Select PMRD PMWR PMCS2 PMCS1 PMALL PMALH RDSP WRSP CS2P CS1P ALP ALP 1 0 1 0 1 0 1 0 1 0 1 0 Note that the polarity of control signals that share the same output pin (for example, PMWR and PMENB) are controlled by the same bit; the configuration depends on which master port mode is being used. 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-27 PIC32MX Family Reference Manual 13.3.1.6 Auto-Increment/Decrement While the module is operating in one of the master modes, the INCM<1:0> (PMMODE<12:11>) bits control the behavior of the address value. The address in the PMADDR register can be made to automatically increment or decrement by 1, regardless of the transfer data width, after each read and write operation is completed, and the BUSY bit (PMMODE<15>) goes to ‘0’. . Table 13-4: ADDRESS INC/DEC CONTROL INCM<1:0> FUNCTION 00 No Increment – No Decrement 01 Increment every R/W cycle 10 Decrement every R/W cycle If the Chip Select signals are disabled and configured as address bits, the bits will participate in the increment and decrement operations; otherwise, CS2 and CS1 bit values will be unaffected. 13.3.1.7 Wait States In Master mode, the user can control the duration of the read, write, and address cycles by configuring the module Wait states. One Wait state period is equivalent to one peripheral-bus-clock cycles, TPBCLK. Below is an example of a Master mode 2 Read operation using Wait states Figure 13-2: Read Operation, Wait States Enabled TPB TPB TPB TPB TPB TPB TPB TPB PMCS2 / PMCS1 M B E PMRD PMWR Legend: B = WAITB<1:0> = 01 (2 Wait states) M = WAITM<3:0> = 0010 (3 Wait states) E = WAITE<1:0> = 01 (1 Wait state) Note: If WAITM<3:0> = 0000, M is forced to 1 TPBCLK, WAITB is ignored (B forced to 1 TPBCLK) and WAITE is ignored (E forced to 0 TPBCLK). Wait states can be added to the beginning, middle, and end of any read or write cycle using the corresponding WAITB, WAITM, and WAITE bits in the PMMODE register. The WAITB<1:0> (PMMODE<7:6>) bits define the number of wait cycles for the data setup prior to the PMRD/PMWR strobe in Mode 10, or prior to the PMENB strobe in Mode 11. When multiplexing the address and data bus, ADRMUX<1:0> = 01, 10 or 11, WAITB defines the number of wait cycles for which the addressing period is extended. The WAITM<3:0> (PMMODE<5:2>) bits define the number of wait cycles for the PMRD/PMWR strobe in Mode 10, or for the PMENB strobe in Mode 11. When this Wait state setting is 0000, WAITB and WAITE are ignored. The number of Wait states for the data setup time (WAITB) defaults to one while the number of Wait states for data hold time (WAITE) defaults to one during a write operation and zero during a read operation. The WAITE<1:0> (PMMODE<1:0>) bits define the number of wait cycles for the data hold time after the PMRD/PMWR strobe in Mode 10, or after the PMENB strobe in Mode 11. DS61128D-page 13-28 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.3.1.8 Address Multiplexing Address multiplexing allows some or all address line signals to be generated from the data bus during the address cycle of a read/write operation. This can be a useful option for address lines PMA<15:0> needed as general purpose I/O pins. The user can select to multiplex the lower 8 data bits, upper 8 data bits or full 16 data bits. These multiplexing modes are available in both Master mode 1 and 2. Refer to Section 13.3.8 “Master Mode Timing” for the multiplexing mode timing diagrams. Table 13-5: Address Multiplex Configurations ADRMUX <1:0> Address/Data Multiplex Modes 00 Demultiplexed 01 Partially Multiplexed (lower eight data pins PMD[7:0]) 10 Fully multiplexed (lower eight data pins PMD[7:0]) 11 Fully multiplexed (16 data pins PMD[15:0]) 13.3.1.8.1 Demultiplexed Mode Demultiplexed mode is selected by configuring bits ADRMUX<1:0> = 00, (PMMODE<9:8>). In this mode, address bits are presented on pins PMA<15:0>. When PMCS2 is enabled, address pin PMA15 is not available. When PMCS1 is enabled, Address pin PMA14 is not available. In 16-Bit Data mode, data bits are presented on pins PMD<15:0>. In 8-Bit Data mode, data bits are presented on pins PMD<7:0>. Figure 13-3: Demultiplexed Addressing Mode 13 PIC32MX ADRMUX<1:0> = 00 Note 1: Address pin PMA<15> is not available if PMCS2 is enabled. Address pin PMA<14> is not available if PMCS1 is enabled. PMA<13:0> PMD<7:0> PMD<15:8> (1) PMA14/PMCS1 PMA15/PMCS2 PMRD PMWR Address Bus Data Bus Control Lines Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-29 PIC32MX Family Reference Manual Figure 13-4: Demultiplexed Addressing Example PIC32MX PMA<14:0> PMD<15:0> A<14:0> D<15:0> PMCS2 PMRD PMWR Note: (Master mode 2) MODE<1:0> = 10 (16-bit data width) MODE16 (PMMODE<10>) = 1 (Partial Multiplexed mode) ADRMUX (PMCON<12:11>) = 00 32K x 16-Bit Device A<14:0> D<15:0> CE OE WR Address Bus Data Bus Control Lines DS61128D-page 13-30 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.3.1.8.2 Partially Multiplexed Mode Partially Multiplexed mode (8-Bit data pins) is available in both 8-bit and 16-bit data bus configurations and is selected by setting bits ADRMUX<1:0> = 01. In this mode, the lower eight address bits are multiplexed with the lower eight data bus pins, PMD<7:0>. The upper eight address bits are unaffected and are presented on PMA<15:8>. In this mode, address pins PMA<7:1> are available as general purpose I/O pins. Address pin PMA15 is not available when PMCS2 is enabled; address pin PMA14 is not available when PMCS1 is enabled. Address pin PMA<0> is used as an Address Latch enable strobe, PMALL, during which the lower eight bits of the address are presented on the PMD<7:0> pins. Read and write sequences are extended by at least 3 peripheral-bus-clock cycles (TPBCLK). If WAITM<3:0> (PMMODE<5:2>) is non-zero, the PMALL strobe will be extended by WAITB<1:0> (PMMODE<7:6>) Wait states. Figure 13-5: Partial Multiplexed Addressing Mode PIC32MX PMA<13:8> PMD<7:0> PMD<15:8> (1) PMA14/PMCS1 PMA15/PMCS2 PMA0/PMALL PMRD ADRMUX<1:0> = 01 Note 1: Address pin PMA<15> is not available if PMCS2 is enabled. Address pin PMA<14> is not available if PMCS1 is enabled. PMWR Address Bus Multiplexed Address/Data Bus Data Bus Control Lines 13 Figure 13-6: Partial Multiplexed Addressing Example PIC32MX PMALL PMD<15:0> PMA<14:8> PMCS2 PMRD PMWR D<7:0> 373 A<7:0> D<15:0> A<14:8> Note: (Master mode 2) MODE<1:0> = 10 (16-bit data width) MODE16 (PMMODE<10>) = 1 (Partial Multiplexed mode) ADRMUX (PMCON<12:11>) = 01 The 373 shown in the diagram represents a generic 74XX family 373 latch. 32K x 16-Bit Device A<14:0> D<15:0> CE OE WR Address Bus Data Bus Control Lines Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-31 PIC32MX Family Reference Manual 13.3.1.8.3 Full Multiplexed mode (8-bit data pins) Full multiplexed mode (8-Bit data pins) is available in both 8-bit and 16-bit data bus configurations and is selected by setting bits ADRMUX<1:0> (PMCON<12:11>) = 10. In this mode, the entire 16 bits of the address are multiplexed with the lower eight data bus pins, PMD<7:0>. In this mode, Pins PMA<13:2> available as general purpose I/O pins. In the event the pins PMCS2/PMA15 or PMCS1/PMA14 are configured as Chip Select pins, the corresponding address bits PMADDR<15> or PMADDR<14> are automatically forced to ‘0’. Address pins PMA<0> and PMA<1> are used as an Address Latch enable strobes, PMALL and PMALH, respectively. During the first cycle, the lower eight address bits are presented on the PMD<7:0> pins with the PMALL strobe active. During the second cycle the upper eight address bits are presented on the PMD<7:0> pins with the PMALH strobe active. The read and write sequences are extended by at least 6 peripheral-bus-clock cycles (TPBCLK). If WAITM<3:0> (PMMODE<5:2>) is non-zero, both PMALL and PMALH strobes will be extended by WAITB<1:0> (PMMODE<7:6>) Wait states. Figure 13-7: Full Multiplexed Addressing Mode (8-Bit Bus) PIC32MX ADRMUX<1:0> = 10 PMD<7:0> (1) PMA14/ PMCS1 PMA15/ PMCS2 PMA0/PMALL PMA1/PMALH PMRD PMWR Note 1: Address bit PMADDR<15> is forced = 0 when PMCS2 is enabled. Full Multiplexed Address/Data Bus Address bit PMADDR<14> is forced = 0 when PMCS1 is enabled. Control Lines Figure 13-8: Full Multiplexed Address Example (8-Bit Bus) PIC32MX PMALL PMD<7:0> A<7:0> 373 D<7:0> PMALH A<14:8> 373 PMCS2 PMRD PMWR Note: (Master mode 2) MODE<1:0> = 10 (8-bit data width) MODE16 (PMMODE<10>) = 0 (Full Multiplexed mode) ADRMUX (PMCON<12:11>) = 10 The 373 shown in the diagram represents a generic 74XX family 373 latch. 32K x 8-Bit Device A<14:0> D<7:0> CE OE WR Address Bus Data Bus Control Lines DS61128D-page 13-32 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.3.1.8.4 Full Multiplexed mode (16-bit data pins) Full Multiplexed mode (16-Bit data pins) is only available in the 16-bit data bus configuration and is selected by configuring bits ADRMUX<1:0> (PMCON<12:11>) = 11. In this mode, the entire 16 bits of the address are multiplexed with all 16 data bus pins, PMD<15:0>. In the event the pins PMCS2/PMA15 or PMCS1/PMA14 are configured as Chip Select pins, the corresponding address bits PMADDR<15> or PMADDR<14> are automatically forced to ‘0’. Address pins PMA<0> and PMA<1> are used as an Address Latch enable strobes, PMALL and PMALH respectively, and at the same time. While the PMALL and PMALH strobes are active, the lower eight address bits are presented on the PMD<7:0> pins and the upper eight address bits are presented on the PMD<15:8> pins. The read and write sequences are extended by at least 3 peripheral-bus-clock cycles (TPBCLK). If WAITM<3:0> (PMMODE<5:2>) is non-zero, both PMALL and PMALH strobes will be extended by WAITB<1:0> (PMMODE<7:6>) Wait states. Figure 13-9: Full Multiplexed Addressing Mode (16-Bit Bus) PIC32MX ADRMUX<1:0> = 11 PMD<7:0> PMD<15:8> (1) PMA14/ PMCS1 PMA15/ PMCS2 PMA0/PMALL PMA1/PMALH PMRD PMWR Note 1: Address bit PMADDR<15> is forced = 0 when PMCS2 is enabled. Address bit PMADDR<14> is forced = 0 when PMCS1 is enabled. Full Multiplexed Address/Data Bus Control Lines 13 Figure 13-10: Full Multiplexed Addressing Example (16-Bit Bus) PIC32MX PMALL PMD<15:0> D<7:0> A<7:0> 373 D<15:0> PMALH PMCS2 PMRD PMWR D<15:8> A<14:8> 373 Note: (Master mode 2) MODE<1:0> = 10 (16-bit data width) MODE16 (PMMODE<10>) = 1 (Full Multiplexed mode) ADRMUX (PMCON<12:11>) = 11 The 373 shown in the diagram represents a generic 74XX family 373 latch. 32K x 16-Bit Device A<14:0> D<15:0> CE OE WR Address Bus Data Bus Control Lines Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-33 PIC32MX Family Reference Manual 13.3.2 Master Port Configuration The Master mode configuration is determined primarily by the interface requirements to the external device. Address multiplexing, control signal polarity, data width and Wait states typically dictate the specific configuration of the PMP master port. To use the PMP as a master, the module must be enabled, control bit ON (PMCON<15>) = 1, and the mode must be set to one of two possible master modes. Control bits MODE<1:0> (PMMODE<9:8>) = 10 for Master mode 2 or MODE<1:0> = 11 for Master mode 1. The following Master mode initialization properly prepares the PMP port for communicating with an external device. 1. If interrupts are used, disable the PMP interrupt by clearing the interrupt enable bit PMPIE (IEC1<2>) = 0. 2. Stop and reset the PMP module by clearing the control bit ON (PMCON<15>) = 0. 3. Configure the desired settings in the PMCON, PMMODE and PMAEN control registers. 4. If interrupts are used: a. Clear interrupt flag bit PMPIF (IFS1<2>) = 0. b. Configure the PMP interrupt priority bits PMPIP<2:0> (IPC7<4:2>) and interrupt sub- priority bits PMPIS (IPC7<1:0>. c. Enable PMP interrupt by setting interrupt enable bit PMPIE = 1. 5. Enable the PMP master port by setting control bit ON = 1. Note: It is recommended to wait for any pending read or write operation to be completed before reconfiguring the PMP module. The following illustrates an example setup for a typical Master mode 2 operation: • Select Master mode 2 – MODE<1:0> (PMMODE<9:8>) = 10. • Select 16-bit Data mode – MODE16 (PMMODE<10>) = 0. • Select partially multiplexed addressing – ADRMUX<1:0> (PMCON<12:11>) = 01. • Select auto address increment – INCM<1:0> (PMMODE<12:11>) = 01. • Enable Interrupt Request mode – IRQM<1:0> (PMMODE<14:13>) = 01. • Enable PMRD strobe – PTRDEN (PMCON<8>) = 1. • Enable PMWR strobe – PTWREN (PMCON<9>) = 1. • Enable PMCS2 and PMCS1 Chip Selects – CSF (PMCON<7:6>) = 10. • Select PMRD active-low pin polarity – RDSP (PMCON<0>) = 0. • Select PMWR active-low pin polarity – WRSP (PMCON<1>) = 0. • Select PMCS2, PMCS1 active-low pin polarity – CS2P (PMCON<4>) = 0 and CS1P (PMCON<3>) = 0. • Select 1 wait cycle for data setup – WAITB<1:0>(PMMODE<7:6>) = 00. • Select 2 wait cycles to extend PMRD/PMWR – WAITM<3:0>(PMMODE<5:2>) = 0001. • Select 1 wait cycle for data hold – WAITE<1:0>(PMMODE<1:0>) = 00. • Enable upper 8 PMA<15:8> address pins – PMAEN<15:8> = 1 (the lower 8 bits can be used as general purpose I/O). See the example code shown in Example 13-1. DS61128D-page 13-34 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Example 13-1: Initialization for Master Mode 2, Demultiplexed Address, 16-Bit Data /* Configuration Example: Master mode 2, 16-bit data, partially multiplexed address/data, active-lo polarities. */ IEC1CLR = 0x0004 // Disable PMP interrupt PMCON = 0x0000; // Stop PMP module and clear control register PMCONSET = 0x0B80; // Configure the addressing and polarities PMMODE = 0x2A40; // Configure the mode PMAEN = 0xFF00; // Enable all address and Chip select lines IPC7SET = 0x001C; IPC7SET = 0x0003; // Set priority level=7 and // Set subpriority level=3 // Could have also done this in single // operation by assigning IPC7SET = 0x001F IEC1SET = 0x0004; PMCONSET = 0x8000; // Enable PMP interrupts // Enable PMP module 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-35 PIC32MX Family Reference Manual 13.3.3 Read Operation To perform a read on the parallel bus, the user reads the PMDIN register. The effect of reading the PMDIN register retrieves the current value and causes the PMP to activate the Chip Select lines and the address bus. The read line PMRD is strobed in Master mode 2, PMRD/PMWR and PMENB lines in Master mode 1, and the new data is latched into the PMDIN register making it available for the next time the PMDIN register is read. Note that the read data obtained from the PMDIN register is actually the read value from the previous read operation. Hence, the first user read will be a dummy read to initiate the first bus read and fill the read register. See Figure 13-11 below illustrating this sequence. Also, the requested read value will not be ready until after the BUSY bit is observed low. Thus, in a back-to-back read operation, the data read from the register will be the same for both reads. The next read of the register will yield the new value. In 16-Bit Data mode, PMMODE = 1, the read from the PMDIN register causes the data bus PMD<15:0> to be read into PMDIN<15:0>. In 8-bit mode, PMMODE = 0, the read from the PMDIN register causes the data bus PMD<7:0> to be read into PMDIN<7:0>. The upper 8 bits, PMD<15:8>, are ignored. Figure 13-11: Example Read Sequence Demonstrating ‘Dummy’ Read Operation INCM<1:0> = 01 Enable Auto-Address Increment Data in External Device memory or registers 0x4000 0x4001 0x4002 0x4003 0x4004 0x02 0x33 0xFA 0x7C 0x0A Data in External Device memory or registers 0x4100 0x4101 0x4102 0x4103 0x4104 0x45 0x76 0x00 0x2A 0x93 PMADDR = 0x4000 Set Initial Address = 0x4000 Dummy Read Read PMDIN Read PMDIN 1. User Reads PMDIN = (don’t care) 2. PMDIN updated = 0x02 3. PMADDR = 0x4001 4. User Reads PMDIN = 0x02 5. PMDIN updated = 0x33 6. PMADDR = 0x4002 Read PMDIN 7. User Reads PMDIN = 0x33 8. PMDIN updated = 0xFA 9. PMADDR = 0x4003 PMADDR = 0x4100 Set New Address = 0x4100 Dummy Read Read PMDIN 1. User Reads PMDIN = 0xFA (don’t care) 2. PMDIN updated = 0x45 3. PMADDR = 0x4101 Read PMDIN 4. User Reads PMDIN = 0x45 5. PMDIN updated = 0x76 6. PMADDR = 0x4102 Read PMDIN 7. User Reads PMDIN = 0x76 8. PMDIN updated = 0x00 9. PMADDR = 0x4103 DS61128D-page 13-36 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.3.4 Write Operation To perform a write on the parallel port, the user writes to the PMDIN register (same register as a read operation). This causes the module to first activate the Chip Select lines and the address bus. The write data from the PMDIN register is placed onto the PMD data bus and the write line PMPWR is strobed in Master mode 2, PMRD/PMWR and PMENB lines in Master Mode 1. In 16-Bit Data mode, PMMODE = 1, the write to the PMDIN register causes PMDIN<15:0> to appear on the data bus, (PMD<15:0>). In 8-bit mode, PMMODE = 0, the write to the PMDIN register causes PMDIN<7:0> to appear on the data bus, PMD<7:0>. The upper 8 bits, PMD<15:8>, are ignored. 13.3.5 Master Mode Interrupts In PMP master modes, the PMPIF bit is set on every read or write strobe. An interrupt request is generated when bits IRQM<1:0> (PMMODE<14:13>) are set = 01 and PMP interrupts are enabled, PMPIE (IEC1<2>) = 1. 13.3.6 Parallel Master Port Status – The BUSY Bit In addition to the PMP interrupt, a BUSY bit, (PMMODE<15>), is provided to indicate the status of the module. This bit is only used in Master mode. While any read or write operation is in progress, the BUSY bit is set for all but the very last peripheral bus cycle of the operation. This is helpful when Wait states are enabled or multiplexed address/data is selected. While the bit is set, any request by the user to initiate a new operation will be ignored (i.e., writing or reading the PMDIN register will not initiate a read or a write). Since the system clock, SYSCLK, can operate faster than the peripheral bus clock in certain configurations, or if a large number of Wait states are used, it is possible for the PMP to be in the process of completing a read or write operation when the next CPU instruction is reading or writing to the PMP module. For this reason, it is highly recommended that the BUSY bit be checked prior to any operation that accesses the PMDIN or PMADDR registers. Below is an example of a polling operation of the BUSY bit prior to accessing the PMP module. In most applications, the PMP’s Chip Select pin(s) provide the Chip Select interface and are under the timing control of the PMP module. However, some applications may require the PMP Chip Select pin(s) not be configured as a Chip Select, but as a high order address line, such as PMA<14> or PMA<15>. In this situation, the application’s Chip Select function must be provided by an available I/O port pin under software control. In these cases, it is especially important that the user’s software poll the BUSY bit to ensure any read or write operation is complete before de-asserting the software controlled Chip Select. 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-37 PIC32MX Family Reference Manual Example 13-2: Example Code: Polling the BUSY Bit Flag /* This example reads 256 16-bit words from an external device at address 0x4000 and copies the data to a second external device at address 0x8000. The PMP port is operating in Master mode 2. Note how the PMP’s BUSY bit is polled prior to all operations to the PMDOUT, PMDIN or PMADDR register, except where noted. */ unsigned short DataArray<256>; ... CopyData(); ... // Provide the setup code here including large Wait // states, auto increment. // A call to the copy function is made. void CopyData() { PMADDR = 0x4000; while(PMMODE & 0x8000); PMDIN; // Init the PMP address. First time, no need to poll BUSY // bit. // Poll - if busy, wait before reading. // Read the PMDIN to clear previous data and latch new // data. for(i=0; i<256; i++) { while(PMMODE & 0x8000); DataArray = PMDIN; } // Poll - if busy, wait before reading. // Read the external device. while(PMMODE & 0x8000); PMADDR = 0x8000; // Poll - if busy, wait before changing PMADDR. // Address of second external device. for(i=0; i<256; i++) { while(PMMODE & 0x8000); DataArray = PMDIN; } return(); } // Poll - if busy, wait before writing. // Read the external device. DS61128D-page 13-38 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.3.7 Addressing Considerations PMCS2 and PMCS1 Chip Select pins share functionality with address lines A15 and A14. It is possible to enable both PMCS2 and PMCS1 as Chip Selects, or enable only PMCS2 as a Chip Select; allowing PMCS1 to function strictly as address line A14. It is not possible to enable only PMCS1. Note: Setting both A15 and A14 = 1 when PMCS2 and PMCS1 are enabled as Chip Selects will cause both PMCS2 and PMCS1 to be active during a read or write operation. This may enable two devices simultaneously and should be avoided. When configured as Chip Selects, a ‘1’ must be written into bit position 15 or 14 of the PMADDR register in order for PMCS2 or PMCS1 to become active during a read or write operation. Failing to write a ‘1’ to PMCS2 or PMCS1 does not prevent address pins PMA<13:0> from being active as the specified address appears; however, no Chip Select signal will be active. Note: When using Auto-Increment Address mode, PMCS2 and PMCS1 do not participate and must be controlled by the user's software by writing to ‘1’ to PMADDR<15:14> explicitly. In Full Multiplexed modes, address bits PMADDR<15:0> are multiplexed with the data bus and in the event address bits PMA15 or PMA14 are configured as Chip Selects, the corresponding PMADDR<15:14> address bits are automatically forced = 0. Disabling one or both PMCS2 and PMCS1 makes these bits available as address bits PMADDR<15:14>. In any of the Master mode multiplexing schemes, disabling both Chip Select pins PMCS2 and PMCS1 requires the user to provide Chip Select line control through some other I/O pin under software control. See Figure 13-12. Refer to Section 13.11 “Design Tips” for additional information regarding memory banking. Figure 13-12: PMP Chip Select Address Maps 13 0xFFFF PMCS2, CS1 Both Devices Selected 11 0xC000 (INVALID) 0x8000 Device 2 Selected PMCS2 = 1 10 0x4000 Device 1 Selected PMCS1 = 1 01 No Device Selected 00 0x0000 2 – Chip Selects 2 – 16K Address Ranges PMCS2, A14 Device Selected PMCS2 = 1 11 10 No Device Selected 01 00 1 – Chip Select 1 – 32K Address Range A15, A14, I/Opin Device Selected I/O-pin = 1 111 10 1 011 0 01 I/O-pin = Software-controlled CS 1 – 64K Address Range Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-39 PIC32MX Family Reference Manual 13.3.8 Master Mode Timing A PMP Master mode cycle time is defined as the number of PBCLK cycles required by the PMP to perform a read or write operation and is dependent on PBCLK clock speed, PMP address/data multiplexing modes and the number of PMP wait states, if any. Refer to the PIC32MX Family Data sheet for specific setup and hold timing characteristics. A PMP master mode read or write cycle is initiated by accessing (reading or writing) the PMDIN register. Table 13-6 below provides a summary of read and write PMP cycle times for each multiplex configuration. The actual data rate of the PMP (the rate which user’s code can perform a sequence of read or write operations) will be highly dependent on several factors: • a user’s application code content • code optimization level • internal bus activity • other factors relating to the instruction execution speed. Note: During any Master mode read or write operation, the busy flag will always de-assert 1 peripheral bus clock cycle (TPBCLK), before the end of the operation, including Wait states. The user’s application must check the status of the busy flag to ensure it is = 0 before initiating the next PMP operation. Table 13-6: PMP Read/Write Cycle Times Address/Data Multiplex Configuration ADRMUX bit settings Demultiplexed 00 Partial Multiplex 01 Full Multiplexed (8-bit data) 10 Full Multiplexed (16-bit data) 11 Note: Wait states are not enabled PMP Cycle Time (PBCLK cycles) Read 2 5 8 5 Write 3 6 9 6 DS61128D-page 13-40 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port The following timing examples represent the common master mode configuration options. These options vary from 8-Bit to 16-Bit data, non-multiplexed to full multiplexed address, as well as with and without Wait states. For illustration purposes only, all control signal polarities are shown as “active-high”. 13.3.8.1 Demultiplexed Address and Data Timing This timing diagram illustrates demultiplexed timing (separate address and data bus) for a read operation with no Wait states. A read operation requires 2 TPBCLK, peripheral-bus-clock cycles. Figure 13-13: 8-Bit, 16-Bit Read Operations, ADRMUX = 00, No Wait States TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMA<13:0> PMD<15:0>(1) Address<13:0> Data From Target PMDIN Mode 1 PMRD/PMPWR PMPENB Previous Latched Data New Latched Data Data latched into PMDIN User Read from PMDIN(2) Mode 2 PMRD PMWR PMPIF BUSY Note 1: In 8-bit mode, PMD<15:8> are not implemented. 2: Read data obtained from the PMDIN register is actually the value from the previous read operation. 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-41 PIC32MX Family Reference Manual In this timing diagram with Wait states, the read operation requires 6 TPBCLK, peripheral-bus-clock cycles. Figure 13-14: 8-Bit, 16-Bit Read Operations, ADRMUX = 00, Wait States Enabled TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 Mode 1 PMRD/PMWR PMENB M B E Mode 2 PMRD PMWR BUSY Legend: B = WAITB<1:0> = 01 (2 Wait states) M = WAITM<3:0> = 0010 (3 Wait states) E = WAITE<1:0> = 01 (1 Wait state) Note: If WAITM<3:0> = 0000, M is forced to 1 TPBCLK, WAITB is ignored (B forced to 1 TPBCLK), and WAITE is ignored (E forced to 0 TPBCLK). This timing diagram illustrates demultiplexed timing (separate address and data bus) for a write operation with no Wait states. A write operation requires 3 TPBCLK, peripheral-bus-clock cycles. Figure 13-15: 8-Bit, 16-Bit Write Operations, ADRMUX = 00, No Wait States TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2, PMCS1 PMA<13:0> PMD<15:0>(1) Address<13:0> Data To Target PMDIN Mode 1 PMRD/PMWR PMENB Previous Data New Data User Writes to PMDIN Mode 2 PMRD PMWR PMPIF BUSY Note 1: In 8-bit mode, PMD<15:8> are not implemented. DS61128D-page 13-42 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port In this timing diagram with Wait states, the write operation requires 7 TPBCLK, peripheral-bus-clock cycles. Figure 13-16: 8-Bit, 16-Bit Write Operations, ADRMUX = 00, Wait States Enabled TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 Mode 1 M PMRD/PMWR PMENB B E Mode 2 PMRD PMWR BUSY Legend: B = WAITB<1:0> = 01 (2 Wait states) M = WAITM<3:0> = 0010 (3 Wait states) E = WAITE<1:0> = 01 (2 Wait states) Note: If WAITM<3:0> = 0000, M is forced to 1 TPBCLK, WAITB is ignored (B forced to 1 TPBCLK), and WAITE is ignored (E forced to 1 TPBCLK). 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-43 PIC32MX Family Reference Manual 13.3.8.2 Partially Multiplexed Address and Data Timing This timing diagram illustrates partially multiplexed timing (address bits <7:0> multiplexed with data bus, PMD<7:0>) for a read operation with no Wait states. A read operation requires 5 TPBCLK, peripheral-bus-clock cycles. Figure 13-17: 8-Bit, 16-Bit Read Operations, ADRMUX = 01, No Wait States TPB PMCS2, PMCS1 PMALL PMA<13:8> PMD<7:0> PMD<15:8>(2) PMDIN Mode 1 PMRD/PMWR PMENB Mode 2 PMRD PMWR TPB TPB TPB TPB TPB TPB TPB TPB TPB ADDRESS<13:8> ADDRESS<7:0> Previous Latched Data User Read from PMDIN(1) LSB MSB Data From Target New Latched Data Data latched into PMDIN PMPIF BUSY Note 1: Read data obtained from the PMDIN register is actually the value from the previous read operation. 2: In 8-Bit mode, PMD<15:8> are not implemented. In this timing diagram with Wait states, the read operation requires 10 TPBCLK, peripheral-bus-clock cycles. Figure 13-18: 8-Bit, 16-Bit Read Operations, ADRMUX = 01, Wait States Enabled TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMALL Mode 1 PMRD/PMWR PMENB Mode 2 PMRD PMWR BUSY B M B E Legend: B = WAITB<1:0> = 01 (2 Wait states) M = WAITM<3:0> = 0010 (3 Wait states) E = WAITE<1:0> = 01 (1 Wait state) Note: If WAITM<3:0> = 0000, M is forced to 1 TPBCLK, WAITB is ignored (B forced to 1 TPBCLK) and WAITE is ignored (E forced to 0 TPBCLK). DS61128D-page 13-44 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port This timing diagram illustrates partially multiplexed timing (address bits <7:0> multiplexed with data bus, PMD<7:0>) for a write operation with no Wait states. A write operation requires 6 TPBCLK, peripheral-bus-clock cycles. Figure 13-19: 8-Bit, 16-Bit Write Operations, ADRMUX = 01, No Wait States TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMALL PMA<13:8> ADDRESS<13:8> PMD<7:0> PMD<15:8>(2) ADDRESS<7:0> LSB Data To Target MSB Data To Target Mode 1 PMDIN PMRD/PMWR PMENB Previous Data New Data User Writes to PMDIN Mode 2 PMRD PMWR(1) PMPIF BUSY Note 1: During a write operation, there is one TPBCLK hold cycle following the PMWR signal. 2: In 8-bit mode, PMD<15:8> are not implemented. 13 In this timing diagram with Wait states, the write operation requires 11 TPBCLK, peripheral-bus-clock cycles. Figure 13-20: 8-Bit, 16-Bit Write Operations, ADRMUX = 01, Wait States Enabled TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMALL Mode 1 PMRD/PMWR PMENB Mode 2 PMRD PMWR B M B E BUSY Legend: B = WAITB<1:0> = 01 (2 Wait states) M = WAITM<3:0> = 0010 (3 Wait states) E = WAITE<1:0> = 01 (1 Wait state) Note: If WAITM<3:0> = 0000, M is forced to 1 TPBCLK, WAITB is ignored (B forced to 1 TPBCLK) and WAITE is ignored (E forced to 1 TPBCLK). Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-45 PIC32MX Family Reference Manual 13.3.8.3 Full Multiplexed (8-Bit Bus) Address and Data Timing This timing diagram illustrates full multiplexed timing (address bits <15:0> multiplexed with data bus, PMD<7:0>) for a read operation with no Wait states. A read operation requires 8 TPBCLK, peripheral-bus-clock cycles. Figure 13-21: 8-Bit, 16-Bit Read Operations, ADRMUX = 10, No Wait States TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMALL PMALH PMD<7:0> PMD<15:8>(2) PMDIN Mode 1 PMRD/PMWR PMENB Mode 2 PMRD PMWR PMPIF BUSY ADDRESS<7:0> ADDRESS<13:8>(3) Previous Latched Data User Read from PMDIN(1) LSB MSB Data From Target New Latched Data Data latched into PMDIN Note 1: Read data obtained from the PMDIN register is actually the value from the previous read operation. 2: In 8-bit mode, PMD<15:8> are not implemented. 3: PMADDR Address bit A15 and A14 are forced to ‘0’ if PMCS2 and/or PMCS1 are enabled as Chip Selects. DS61128D-page 13-46 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port In this timing diagram with Wait states, the read operation requires 14 TPBCLK, peripheral-bus-clock cycles. Figure 13-22: 8-Bit, 16-Bit Read Operation, ADRMUX = 10, Wait States Enabled TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 B PMALL PMALH Mode 1 PMRD/PMWR PMENB Mode 2 PMRD PMWR BUSY B M B E Legend: B = WAITB<1:0> = 01 (2 Wait states) M = WAITM<3:0> = 0010 (3 Wait states) E = WAITE<1:0> = 01 (1 Wait state) Note: If WAITM<3:0> = 0000, M is forced to 1 TPBCLK, WAITB is ignored (B forced to 1 TPBCLK) and WAITE is ignored (E forced to 0 TPBCLK). 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-47 PIC32MX Family Reference Manual This timing diagram illustrates full multiplexed timing (address bits <15:0> multiplexed with data bus, PMD<7:0>) for a write operation with no Wait states. A write operation requires 9 TPBCLK, peripheral-bus-clock cycles. Figure 13-23: 8-Bit, 16-Bit Write, ADRMUX = 10, No Wait States TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMALL PMALH PMD<7:0> PMD<15:8>(2) PMDIN Mode 1 PMRD/PMWR PMENB Mode 2 PMRD PMWR(1) PMPIF BUSY Previous Data ADDRESS<7:0> New Data ADDRESS<13:8>(3) LSB DATA To Target MSB DATA To Target User Writes to PMDIN Note 1: During a write operation, there is one TPBCLK hold cycle following the PMWR signal. 2: In 8-bit mode, PMD<15:8> are not implemented. 3: PMADDR Address bit A15 and A14 are forced to ‘0’ if PMCS2 and/or PMCS1 are enabled as Chip Selects. In this timing diagram with Wait states, the write operation requires 15 TPBCLK, peripheral-bus-clock cycles. Figure 13-24: 8-Bit, 16-Bit Write Operations, ADRMUX = 10, Wait States Enabled TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 B PMALL PMALH Mode 1 PMRD/PMWR PMENB B M B E Mode 2 PMRD PMWR BUSY Legend: B = WAITB<1:0> = 01 (2 Wait states) M = WAITM<3:0> = 0010 (3 Wait states) E = WAITE<1:0> = 01 (2 Wait states) Note: If WAITM<3:0> = 0000, M is forced to 1 TPBCLK, WAITB is ignored (B forced to 1 TPBCLK), and WAITE is ignored (E forced to 1 TPBCLK). DS61128D-page 13-48 Preliminary © 2008 Microchip Technology Inc. Parallel Master Port Section 13. Parallel Master Port 13.3.8.4 Full Multiplexed (16-Bit Bus) Address and Data Timing This timing diagram illustrates full multiplexed timing (address bits <15:0> multiplexed with data bus, PMD<15:0>) for a read operation with no Wait states. A read operation requires 5 TPBCLK, peripheral-bus-clock cycles. Figure 13-25: 16-Bit Read Operation, ADRMUX = 11, No Wait States TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMALL PMALH PMD<7:0> PMD<15:8> PMDIN Mode 1 PMRD/PMWR PMENB ADDRESS<7:0> ADDRESS<13:8>(2) Previous Latched Data LSB MSB Data From Target New Latched Data User Read from PMDIN(1) Data latched into PMDIN Mode 2 PMRD PMWR PMPIF BUSY Note 1: Read data obtained from the PMDIN register is actually the value from the previous read operation. 2: PMADDR Address bit A15 and A14 are forced to ‘0’ if PMCS2 and/or PMCS1 are enabled as Chip Selects. 13 In this timing diagram with Wait states, the read operation requires 10 TPBCLK, peripheral-bus-clock cycles. Figure 13-26: 16-Bit Read Operation, ADRMUX = 11, Wait States Enabled TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMALL PMALH Mode 1 PMRD/PMWR PMENB Mode 2 PMRD PMWR BUSY B M B E Legend: B = WAITB<1:0> = 01 (2 Wait states) M = WAITM<3:0> = 0010 (3 Wait states) E = WAITE<1:0> = 01 (1 Wait state) Note: If WAITM<3:0> = 0000, M is forced to 1 TPBCLK, WAITB is ignored (B forced to 1 TPBCLK) and WAITE is ignored (E forced to 0 TPBCLK). © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-49 PIC32MX Family Reference Manual This timing diagram illustrates full multiplexed timing (address bits <15:0> multiplexed with data bus, PMD<15:0>) for a read operation with no Wait states. A read operation requires 6 TPBCLK, peripheral-bus-clock cycles. Figure 13-27: 16-Bit Write, ADRMUX = 11, No Wait States TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMALL PMALH PMD<7:0> PMD<15:8> PMDIN Mode 1 PMRD/PMWR PMENB Mode 2 PMRD PMWR(1) PMPIF BUSY Previous Data ADDRESS<7:0> ADDRESS<13:8>(2) New Data LSB DATA OUT MSB DATA OUT User Writes to PMDIN Note 1: During a write operation, there is one TPB hold cycle following the PMWR signal. 2: PMADDR Address bit A15 and A14 are forced to ‘0’ if PMCS2 and/or PMCS1 are enabled as Chip Selects. In this timing diagram with Wait states, the write operation requires 11 TPBCLK, peripheral-bus-clock cycles. Figure 13-28: 16-Bit Write Operations, ADRMUX = 11, Wait States Enabled TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS2/PMCS1 PMALL PMALH Mode 1 PMRD/PMWR PMENB Mode 2 PMRD PMWR B M B E BUSY Legend: B = WAITB<1:0> = 01 (2 Wait states) M = WAITM<3:0> = 0010 (3 Wait states) E = WAITE<1:0> = 01 (2 Wait states) Note: If WAITM<3:0> = 0000, M is forced to 1 TPBCLK, WAITB is ignored (B forced to 1 TPBCLK), and WAITE is ignored (E forced to 1 TPBCLK). DS61128D-page 13-50 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.4 SLAVE MODES OF OPERATION The PMP module provides 8-Bit (byte) legacy PSP (Parallel Slave Port) functionality as well as new Buffered and Addressable slave modes. Table 13-7: Slave Mode Selection Slave Mode PMCON MODE bits <1:0> PMMODE INCM bits <1:0> Legacy 00 Buffered 00 Addressable 01 x = don’t care ‘11’ x = don’t care All slave modes support 8-bit data only and the module control pins are automatically dedicated when any of these modes are selected. The user only need to configure the polarity of the PMCS1, PMRD and PMWR signals. Table 13-8: Slave Mode Pin Polarity Configuration CONTROL PIN PMCON Control Bit Active-High Select PMRD RDSP 1 PMWR WRSP 1 PMCS1 CS1P 1 Active-Low Select 0 0 0 13.4.1 Legacy Slave Port Mode 13 In 8-bit PMP Legacy Slave mode, the module is configured as a parallel slave port using control bits MODE<1:0> (PMMODE<9:8>) = 00. In this mode, an external device such as another microcontroller or microprocessor can asynchronously read and write data using the 8-bit data bus PMD<7:0>, the read PMRD, write PMWR, and Chip Select PMCS1 inputs. Figure 13-29: Parallel Master/Slave Connection Example Master D<7:0> CS RD WR PIC32MX Slave PMD<7:0> PMCS1 PMRD PMWR Data Bus Control Lines 13.4.1.1 Initialization Steps The following Slave mode initialization properly prepares the PMP port for communicating with an external device. 1. Clear control bit ON (PMCON<15>) = 0 to disable PMP module. 2. Select the Legacy mode with MODE<1:0> (PMMODE<9:8>) = 00. 3. Select the polarity of the Chip Select pin CS1P (PMCON<3>). 4. Select the polarity of the control pins WRSP and RDSP (PMCON<1:0>). Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-51 PIC32MX Family Reference Manual 5. If interrupts are used: a. Clear interrupt flag bit PMPIF (IFS1<2>) = 0. b. Configure the PMP interrupt priority bits PMPIP<2:0> (IPC7<4:2>) and interrupt subpriority bits PMPIS (IPC7<1:0>). c. Enable PMP interrupt by setting interrupt enable bit PMPIE (IEC1<2>) = 1. 6. Set control bit ON = 1 to enable PMP module. Example 13-3: Example Code: Legacy Parallel Slave Port Initialization /* Example Configuration for Legacy Slave mode */ IEC1CLR = 0x0004 // Disable PMP interrupt in case it is already enabled PMCON = 0x0000 // Stop and Configure PMCON register for Legacy mode PMMODE = 0x0000 // Configure PMMODE register IPC7SET = 0x001C; // Set priority level = 7 and IPC7SET = 0x0003; // Set subpriority level = 3 // Could have also done this in single // operation by assigning IPC7SET = 0x001F IFS1CLR = 0x0004; // Clear the PMP interrupt status flag IEC1SET = 0x0004; // Enable PMP interrupts PMCONSET = 0x8000; // Enable PMP module 13.4.1.2 Write to Slave Port When Chip Select is active and a write strobe occurs, the data on the bus pins PMD<7:0> is captured into the lower 8 bits of the PMDIN register, PMDIN<7:0>. The PMPIF (interrupt flag bit) is set during the write strobe, however, IB0F (input buffer full flag) bit requires 2 to 3 peripheral-bus-clock cycles to synchronize before it is set and the PMDIN register can be read. The IB0F bit will remain set until the PMDIN register is read by the user. If a write operation occurs while IB0F bit is = 1, the write data will be ignored and an overflow condition will be generated, IB0V = 1. Refer to timing diagrams in Section 13.4.4. 13.4.1.3 Read from Slave Port When Chip Select is active and a read strobe occurs, the data from the lower 8 bits of the PMDOUT register, PMDOUT<7:0> is presented onto data bus pins PMD<7:0> and read by the master device. The PMPIF (interrupt flag bit) is set during the read strobe, however, OB0E (output buffer empty flag) bit requires 2 to 3 peripheral-bus-clock cycles to synchronize before it is set. The OB0E bit will remain set until the PMDOUT register is written to by the user. If a read operation occurs while OB0E bit is = 1, the read data will be the same as the previous read data and an underflow condition will be generated, OBUF = 1. Refer to timing diagrams in Section 13.4.4. 13.4.1.4 Legacy Mode Interrupt Operation In PMP Legacy Slave mode, the PMPIF bit is set every read or write strobe. If using interrupts, the user’s application vectors to an Interrupt Service Routine (ISR) where the IBF and OBE Status bits can be examined to determine if the buffer is full or empty. If not using interrupts, the user’s application should wait for PMPIF to be set before polling the IBF and OBE Status bits to determine if the buffer is full or empty. DS61128D-page 13-52 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.4.2 Buffered Parallel Slave Port Mode The 8-bit Buffered Parallel Slave Port mode is functionally identical to the Legacy Parallel Slave Port mode with one exception: the implementation of 4-level read and write buffers. Buffered Slave mode is enabled by setting the PMMODE) bits = 00, and the PMMODE bits = 11. When the buffered mode is active, the module uses the PMDIN register as write buffers and the PMDOUT register as read buffers. Each register is divided into four 8-bit buffer registers, four read buffers in PMDOUT and four write buffers in PMDIN. Buffers are numbered 0 through 3, starting with the lower byte <7:0> and progressing upward through the high byte <31:24>. Figure 13-30: Parallel Master/Slave Connection Buffered Example Master D<7:0> CS RD WR PMD<7:0> PIC32MX Slave Write Address Pointer Read Address Pointer PMCS1 PMRD PMWR PMDOUT (0) PMDOUT (1) PMDOUT (2) PMDOUT (3) PMDIN (0) PMDIN (1) PMDIN (2) PMDIN (3) Data Bus Control Lines 13.4.2.1 Initialization Steps The following Buffered Slave mode initialization properly prepares the PMP port for communicating with an external device. 1. Clear control bit ON (PMCON<15>) = 0 to disable PMP module. 2. Select the Legacy mode with MODE<1:0> (PMMODE<9:8>) = 00 3. Select Buffer mode with INCM<1:0> (PMMODE<12:11>) = 11. 4. Select the polarity of the Chip Select CS1P (PMCON<3>). 5. Select the polarity of the control pins with WRSP and RDSP (PMCON<1:0>). 6. If interrupts are used: a. Clear interrupt flag bit PMPIF (IFS1<2>). b. Configure interrupt priority and subpriority levels in IPC7. c. Set interrupt enable bit PMPIE (IEC1<2>). 7. Set control bit ON = 1 to enable PMP module. 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-53 PIC32MX Family Reference Manual Example 13-4: Example Code: Buffered Parallel Slave Port Initialization /* Example Configuration for Buffered Slave mode */ IEC1CLR = 0x0004 // Disable PMP interrupt in case it is already enabled PMCON = 0x0000 // Stop and Configure PMCON register for Buffered mode PMMODE = 0x1800 // Configure PMMODE register IPC7SET = 0x001C; // Set priority level = 7 and IPC7SET = 0x0003; // Set subpriority level = 3 // Could have also done this in single operation by assigning // IPC7SET = 0x001F IFS1CLR = 0x0004; // Clear the PMP interrupt status flag IEC1SET = 0x0004; // Enable PMP interrupts PMCONSET = 0x8000; // Enable PMP module 13.4.2.2 Read from Slave Port For read operations, the bytes will be sent out sequentially, starting with Buffer 0, PMDOUT<7:0>, and ending with Buffer 3, PMDOUT<31:24>, for every read strobe. The module maintains an internal pointer to keep track of which buffer is to be read. Each of the buffers has a corresponding read Status bit, OBnE, in the PMSTAT register. This bit is cleared when a buffer contains data that has not been written to the bus, and is set when data is written to the bus. If the current buffer location being read from is empty, a buffer underflow is generated, and the Buffer Overflow flag bit OBUF is set. If all four OBnE Status bits are set, then the Output Buffer Empty flag OBE will also be set. Refer to timing diagrams in Section 13.4.4. 13.4.2.3 Write to Slave Port For write operations, the data is be stored sequentially, starting with Buffer 0, PMDIN<7:0> and ending with Buffer 3, PMDIN<31:24>. As with read operations, the module maintains an internal pointer to the buffer that is to be written next. The input buffers have their own write Status bits, IBnf. The bit is set when the buffer contains unread incoming data, and cleared when the data has been read. The flag bit is set on the write strobe. If a write occurs on a buffer when its associated IBnf bit is set, the Buffer Overflow flag IBOV is set; any incoming data in the buffer will be lost. If all 4 IBnf flags are set, the Input Buffer Full flag IBF is set. Refer to timing diagrams in Section 13.4.4. 13.4.2.4 Buffered Mode Interrupt Operation In Buffered Slave mode, the module can be configured to generate an interrupt on every read or write strobe, IRQM<1:0> (PMMODE<14:13>) = 01. It can be configured to generate an interrupt on a read from Read Buffer 3 or a write to Write Buffer 3, IRQM<1:0> = 10, which is essentially an interrupt every fourth read or write strobe. When interrupting every fourth byte for input data, all input buffer registers should be read to clear the IBnF flags. If these flags are not cleared then there is a risk of hitting an overflow condition. If using interrupts, the user’s application vectors to an Interrupt Service Routine (ISR) where the IBF and OBE Status bits can be examined to determine if the buffer is full or empty. If not using interrupts, the user’s application should wait for PMPIF to be set before polling the IBF and OBE Status bits to determine if the buffer is full or empty. DS61128D-page 13-54 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.4.3 Addressable Buffered Parallel Slave Port Mode In the 8-bit Addressable Buffered Parallel Slave Port mode the module is configured with two extra inputs, PMA<1:0>. This makes the 4-byte buffer space directly addressable as fixed pairs of read and write buffers. As with Buffered Legacy mode, data is output from register PMDOUT and is input to register PMDIN. Table 20-1 shows the address resolution for the incoming address to the input and output registers. Table 13-9: Slave Mode Buffer Addresses PMA<1:0> Output Register (Buffer) 00 PMDOUT<7:0>(0) 01 PMDOUT<15:8> (1) 10 PMDOUT<23:16> (2) 11 PMDOUT<31:24> (3) Input Register (Buffer) PMDIN<7:0> (0) PMDIN<15:8> (1) PMDIN<23:16> (2) PMDIN<31:24> (3) Figure 13-31: Parallel Master/Slave Connection Addressed Buffer Example Master A<1:0> D<7:0> CS RD WR PMA<1:0> PIC32MX Slave PMD<7:0> Write Address Decode Read Address Decode PMCS1 PMRD PMWR PMDOUT (0) PMDOUT (1) PMDOUT (2) PMDOUT (3) PMDIN (0) PMDIN (1) PMDIN (2) PMDIN (3) 13 Address Bus Data Bus Control Lines 13.4.3.1 Initialization Steps The following Addressable Buffered Slave mode initialization properly prepares the PMP port for communicating with an external device. 1. Clear control bit ON (PMCON<15>) = 0 to disable PMP module. 2. Select the Legacy mode with MODE<1:0> (PMMODE<9:8) = 00. 3. Select the polarity of the Chip Select CS1P (PMCON<3>). 4. Select the polarity of the control pins with WRSP and RDSP (PMCON<1:0>). 5. If interrupts are used: a. Clear interrupt flag bit PMPIF (IFS1<2>). b. Configure interrupt priority and subpriority levels in IPC7. c. Set interrupt enable bit PMPIE (IEC1<2>). 6. Set control bit ON = 1 to enable PMP module. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-55 PIC32MX Family Reference Manual Example 13-5: Example Code: Addressable Parallel Slave Port Initialization /* Example Configuration for Addressable Slave mode */ IEC1CLR = 0x0004 // Disable PMP interrupt in case it is already enabled PMCON = 0x0000 // Stop and Configure PMCON register for Address mode PMMODE = 0x0100 // Configure PMMODE register IPC7SET = 0x001C; // Set priority level = 7 and IPC7SET = 0x0003; // Set subpriority level = 3 // Could have also done this in single operation by assigning // IPC7SET = 0x001F IFS1CLR = 0x0004; // Clear the PMP interrupt status flag IEC1SET = 0x0004; // Enable PMP interrupts PMCONSET = 0x8000; // Enable PMP module 13.4.3.2 Read from Slave Port When Chip Select is active and a read strobe occurs, the data from one of the four output 8-bit buffers is presented onto PMD<7:0>. The byte selected to be read depends on the 2-bit address placed on PMA<1:0>. Table 20-1 shows the corresponding output registers and their associated address. When an output buffer is read, the corresponding OBnE bit is set. The OBE flag bit is set when all the buffers are empty. If any buffer is already empty, OBnE = 1, the next read to that buffer will generate an OBUF event. Refer to timing diagrams in Section 13.4.4. 13.4.3.3 Write to Slave Port When Chip Select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into one of the four input buffer bytes. The byte selected to be written depends on the 2-bit address placed on ADDR<1:0>. Table 20-1 shows the corresponding input registers and their associated address. When an input buffer is written, the corresponding IBnF bit is set. The IBF flag bit is set when all the buffers are written. If any buffer is already written, IBnF = 1, the next write strobe to that buffer will generate an IBOV event, and the byte will be discarded. Refer to timing diagrams in Section 13.4.4. 13.4.3.4 Addressable Buffered Mode Interrupt Operation In Addressable Slave mode, the module can be configured to generate an interrupt on every read or write strobe, IRQM<1:0> (PMMODE<14:13>) = 01. It can also be configured to generate an interrupt on any read from Read Buffer 3 or write to Write Buffer 3, IRQM<1:0> = 10; in other words, an interrupt will occur whenever a read or write occurs when PMA<1:0> is ‘11’. If using interrupts, the user’s application vectors to an Interrupt Service Routine (ISR) where the IBF and OBE Status bits can be examined to determine if the buffer is full or empty. If not using interrupts, the user’s application should wait for PMPIF to be set before polling the IBF and OBE Status bits to determine if the buffer is full or empty. DS61128D-page 13-56 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.4.4 Slave Mode Read and Write Timing Diagrams In all of the slave modes, an external master device is connected to the parallel slave port and is controlling the read and write operations. When an external read or write operation is performed by the external master device, the PMPIF (IFS1<2>) will be set on the active edge of PMRD or PMWR pin. • For any external write operation, the user’s application must poll the IBOV or IB0F buffer Status bits to ensure adequate time for the write operation to be completed before accessing the PMDIN register. • For any external read operation, the user’s application must poll the OBUF or OB0E buffer Status bits to ensure adequate time for the read operation to be completed before accessing PMDOUT register. Figure 13-32: Parallel Slave Port Write Operation 2-3 TPBCLK Cycles TPB TPB TPB TPB TPB TPB TPB PMCS1 PMWR PMRD TPB TPB TPB PMD<7:0> PMDIN IBOV IB0F Data from Master Previous Data New Data PMPIF Buffer Full, Ready To Read User Reads PMDIN Note: Control signal polarity are configurable and are shown active-high in this example. 13 Figure 13-33: Parallel Slave Port Write Operation – Buffer Full, Overflow Condition 2-3 TPBCLK Cycles TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS1 PMWR PMRD PMD<7:0> Data from Master PMDIN IBOV IB0F PMPIF Previous Data Buffer Overflow Condition User Clears IB0V User Reads PMDIN Note: Control signal polarity are configurable and are shown active-high in this example. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-57 PIC32MX Family Reference Manual Figure 13-34: Parallel Slave Port Read Operation 2-3 TPBCLK Cycles TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS1 PMWR PMRD PMD<7:0> Data to Master PMDOUT Data OBUF OB0E Same Data New Data PMPIF Buffer Empty, Ready To Write New Data User Writes New Data to PMDIN Note: Control signal polarity are configurable and are shown active-high in this example. Figure 13-35: Parallel Slave Port Read Operation – Buffer Empty, Underflow Condition 2-3 TPBCLK Cycles TPB TPB TPB TPB TPB TPB TPB TPB TPB TPB PMCS1 PMWR PMRD PMD<7:0> Old Data to Master PMDOUT OBUF OB0E PMPIF Old Data New Data Buffer Underflow Condition User Clears OBUF User Writes PMDIN Note: Control signal polarity are configurable and are shown active-high in this example. DS61128D-page 13-58 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.5 INTERRUPTS The Parallel Master Port has the ability to generate an interrupt, depending on the selected Operating mode. • PMP (Master) mode: - Interrupt on every completed read or write operation. • PSP (Legacy Slave) mode: - Interrupt on every read and write byte • PSP (Buffered Slave) mode: - Interrupt on every read and write byte - Interrupt on read or write byte of Buffer 3 (PMDOUT<31:24>) • EPSP (Enhanced Addressable Slave) mode: - Interrupt on every read and write byte - Interrupt on read or write byte of Buffer 3 (PMDOUT<31:24>), PMA<1:0> = 11. The PMPIF bit must be cleared in software. The PMP module is enabled as a source of interrupt via the PMP Interrupt Enable bit, PMPIE. The Interrupt Priority level bits (PMPIP<2:0>) and Interrupt Subpriority level bits (PMPIS<1:0>) must also be configured. Refer to Section Section 1. “Interrupts” for further details. 13.5.1 Interrupt Configuration The PMP module has a dedicated interrupt flag bit PMPIF and a corresponding interrupt enable/mask bit PMPIE. These bits are used to determine the source of an interrupt and to enable or disable an individual interrupt source. The PMPIE bit is used to define the behavior of the Vector Interrupt Controller or Interrupt Controller when the PMPIF is set. When the PMPIE bit is clear, the Interrupt Controller module does not generate a CPU interrupt for the event. If the PMPIE bit is set, the Interrupt Controller module will generate an interrupt to the CPU when the PMPIF bit is set (subject to the priority and subpriority as outlined below). It is the responsibility of the user’s software routine that services a particular interrupt to clear the appropriate Interrupt Flag bit before the service routine is complete. The priority of PMP module can be set with the PMPIP<2:0> bits. This priority defines the priority group to which the interrupt source will be assigned. The priority groups range from a value of 7, the highest priority, to a value of 0, which does not generate an interrupt. An interrupt being serviced will be preempted by an interrupt in a higher priority group. The subpriority bits allow setting the priority of a interrupt source within a priority group. The values of the subpriority, PMPIS<1:0>, range from 3, the highest priority, to 0 the lowest priority. An interrupt with the same priority group but having a higher subpriority value will preempt a lower subpriority interrupt that is in progress. The priority group and subpriority bits allow more than one interrupt source to share the same priority and subpriority. If simultaneous interrupts occur in this configuration the natural order of the interrupt sources within a priority/subgroup pair determine the interrupt generated. The natural priority is based on the vector numbers of the interrupt sources. The lower the vector number the higher the natural priority of the interrupt. Any interrupts that were overridden by natural order will then generate their respective interrupts based on priority, subpriority, and natural order after the interrupt flag for the current interrupt is cleared. After an enabled interrupt is generated, the CPU will jump to the vector assigned to that interrupt. The vector number for the interrupt is the same as the natural order number. The CPU will then begin executing code at the vector address. The user’s code at this vector address should perform any application specific operations and clear the PMPIF interrupt flag, and then exit. Refer to the Interrupt Controller chapter for the vector address table details for more information on interrupts. 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-59 PIC32MX Family Reference Manual Table 13-10: PMP Interrupt Vectors for Various Offsets with EBASE = 0x8000:0000 Channel Vector/Natural Order IRQ Number Vector Address IntCtl.VS = 0x01 Vector Address IntCtl.VS = 0x02 Vector Address IntCtl.VS = 0x04 Vector Address IntCtl.VS = 0x08 PMP 28 34 8000 0580 8000 0900 8000 1000 8000 1E00 Vector Address IntCtl.VS = 0x10 8000 3A00 Table 13-11: Priority and Subpriority Assignment Example Channel Priority Group PMP 7 Subpriority 3 Vector/Natural Order 28 Example 13-6: PMP Module Interrupt Initialization Code Example /* The following code example illustrates a PMP interrupt configuration. When the PMP interrupt is generated, the cpu will branch to the vector assigned to PMP interrupt. */ // Configure PMP for desired mode of operation ... // Configure the PMP interrupts IPC7SET = 0x0014; // Set priority level = 5 IPC7SET = 0x0003; // Set subpriority level = 3 // Could have also done this in single // operation by assigning IPC7SET = 0x0017 IFS1CLR = 0x0004; IEC1SET = 0x0004; PMCONSET = 0x8000; // Clear the PMP interrupt status flag // Enable PMP interrupts // Enable PMP module Example 13-7: PMP ISR Code Example /* The following code example demonstrates a simple Interrupt Service Routine for PMP interrupts. The user’s code at this vector should perform any application specific operations and must clear the PMP interrupt status flag before exiting. */ void __ISR(_PMP_VECTOR, ipl5) PMP_HANDLER(void) { ... perform application specific operations in response to the interrupt IFS1CLR = 0x0004; } // Be sure to clear the PMP interrupt status // flag before exiting the service routine. Note: The PMP ISR code example shows MPLAB® C32 C compiler-specific syntax. Refer to your compiler manual regarding support for ISRs. DS61128D-page 13-60 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.6 OPERATION IN POWER-SAVING AND DEBUG MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 13.6.1 PMP Operation in SLEEP Mode When the device enters SLEEP mode, the system clock is disabled. The consequences of SLEEP mode depend on which mode the module is configured in at the time that SLEEP mode is invoked. 13.6.1.1 PMP Operation – SLEEP in Master Mode If the microcontroller enters SLEEP mode while the module is operating in Master mode, PMP operation will be suspended in its current state until clock execution resumes. As this may cause unexpected control pin timings, users should avoid invoking SLEEP mode when continuous use of the module is needed. 13.6.1.2 PMP Operation – SLEEP in Slave Mode While the module is inactive but enabled for any Slave mode operation, any read or write operations occurring at that time will be able to complete without the use of the microcontroller 13 clock. Once the operation is completed, the module will issue an interrupt according to the setting of the IRQM bits. If the PMPIE bit is set, and its priority is greater than current CPU priority, the device will wake from SLEEP or IDLE mode and execute the PMP interrupt service routine. If the assigned priority level of the PMP interrupt is less than or equal to the current CPU priority level, the CPU will not be awakened and the device will enter the IDLE mode. 13.6.2 PMP Operation in IDLE Mode When the device enters IDLE mode, the system clock sources remain functional. The PMCON bit selects whether the module will stop or continue functioning on IDLE. If PMCON = 0, the module will continue operation in IDLE mode. If PMCON = 1, the module will stop communications when the microcontroller enters IDLE mode, in the same manner as it does in SLEEP mode. The current transaction in Slave modes will complete and issue an interrupt, while the current transaction in Master mode will be suspended until normal clocking resumes. As with SLEEP mode, IDLE mode should be avoided when using the module in Master mode if continuous use of the module is required. Note: The FRZ bit is readable and writable only when the CPU is executing in Debug Exception mode. In all other modes, the FRZ bit reads as ‘0’. If FRZ bit is changed during DEBUG mode, the new value does not take effect until the current Debug Exception mode is exited and re-entered. During the Debug Exception mode, the FRZ bit reads the state of the peripheral when entering DEBUG mode. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-61 PIC32MX Family Reference Manual 13.7 EFFECTS OF VARIOUS RESETS 13.7.1 Device Reset All PMP module registers are forced to their Reset states on a device Reset. 13.7.2 Power-on Reset All PMP module registers are forced to their Reset states on a POR. 13.7.3 Watchdog Reset All PMP module registers are forced to their Reset states on a Watchdog Reset. 13.8 PARALLEL MASTER PORT APPLICATIONS This section illustrates typical interfaces between the PMP module and external devices for each of the module’s multiplexing modes. Additionally, there are some potential applications shown for the PMP module. Note: Data pins PMD<15:0> are available on 100-pin PIC32MX device variants and larger. For all other device variants, only pins PMD<7:0> are available. Refer to the specific PIC32MX device data sheet for details. 13.8.1 Demultiplexed Memory or Peripheral Figure 13-36 illustrates the connections to an 8-bit memory or addressable peripheral in Demultiplexed mode. This mode does not require any external latches. Figure 13-36: Example of Demultiplexed Addressing, 8-Bit (Up to 15-Bit Address) PIC32MX PMA<14:0> PMD<7:0> PMCS2 PMRD PMWR A<14:0> D<7:0> 32K x 8-Bit Device A<14:0> D<7:0> CE OE WR Note: (Master mode 2) MODE<1:0> = 10 (8-bit data width) MODE16 (PMMODE<10>) = 0 (Demultiplexed mode) ADRMUX (PMCON<12:11>) = 00 Address Bus Data Bus Control Lines DS61128D-page 13-62 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Figure 13-37 illustrates the connections to a 16-bit memory or addressable peripheral in Demultiplexed mode. This mode does not require any external latches. Figure 13-37: Example of Demultiplexed Addressing, 16-Bit Data, (Up to 15-Bit Address) PIC32MX PMA<14:0> PMD<15:0> A<14:0> D<15:0> PMCS2 PMRD PMWR Note: (Master mode 2) MODE<1:0> = 10 (16-bit data width) MODE16 (PMMODE<10>) = 1 (Demultiplexed mode) ADRMUX (PMCON<12:11>) = 00 32K x 16-Bit Device A<14:0> D<15:0> CE OE WR Address Bus Data Bus Control Lines 13.8.2 Partial Multiplexed Memory or Peripheral 13 Figure 13-38 illustrates the connections to an 8-bit memory or other addressable peripheral in Partial Multiplex mode. In this mode, an external latch is required. Consequently, from the microcontroller perspective, this mode achieves some pin savings over the Demultiplexed mode, however, at the price of performance. The lower 8 bits of address are multiplexed with the PMD<7:0> data bus and require one extra peripheral-bus-clock cycle. Figure 13-38: Example of Partial Multiplexed Addressing, 8-Bit Data (Up to 15-Bit Address) PIC32MX PMALL PMD<7:0> PMA<14:8> PMCS2 PMRD PMWR D<7:0> 373 A<14:8> A<7:0> D<7:0> Note: (Master mode 2) MODE<1:0> = 10 (8-bit data width) MODE16 (PMMODE<10>) = 0 (Partial Multiplexed mode) ADRMUX (PMCON<12:11>) = 01 The 373 shown in the diagram represents a generic 74XX family 373 latch. 32K x 8-Bit Device A<14:0> D<7:0> CE OE WR Address Bus Data Bus Control Lines Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-63 PIC32MX Family Reference Manual If the peripheral has internal latches as shown in Figure 13-39, then no extra circuitry is required except for the peripheral itself. Figure 13-39: Example of Partial Multiplexed Addressing, 8-Bit Data PIC32MX PMD<7:0> PMALL PMCS2 PMRD PMWR 8-Bit Device Parallel Peripheral AD<7:0> ALE CS RD WR Note: (Master mode 2) MODE<1:0> = 10 (8-bit data width) MODE16 (PMMODE<10>) = 0 (Partial Multiplexed mode) ADRMUX (PMCON<12:11>) = 01 Data Bus Control Lines Figure 13-40 illustrates the connections to a 16-bit memory or other addressable peripheral in Partial Multiplex mode. In this mode, an external latch is required. Consequently, from the microcontroller perspective, this mode achieves some pin savings over the Demultiplexed mode, however, at the price of performance. The lower 8 bits of address are multiplexed with the PMD<7:0> data bus and require one extra peripheral-bus-clock cycle. Figure 13-40: Example of Partial Multiplexed Addressing,16-Bit Data (Up to 15-Bit Address) PIC32MX PMALL PMD<15:0> PMA<14:8> PMCS2 PMRD PMWR D<7:0> 373 A<7:0> D<15:0> A<14:8> Note: (Master mode 2) MODE<1:0> = 10 (16-bit data width) MODE16 (PMMODE<10>) = 1 (Partial Multiplexed mode) ADRMUX (PMCON<12:11>) = 01 The 373 shown in the diagram represents a generic 74XX family 373 latch. 32K x 16-Bit Device A<14:0> D<15:0> CE OE WR Address Bus Data Bus Control Lines DS61128D-page 13-64 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.8.3 Full Multiplexed Memory or Peripheral Figure 13-41 illustrates the connections to a memory or other addressable peripheral in full 8-bit Multiplexed mode, ADRMUX = 10 (PMCON<12:11>). Consequently, from the microcontroller perspective, this mode achieves the best pin saving over the Demultiplexed mode or Partially Multiplexed mode, however, at the price of performance. The lower 8 address bits are multiplexed with the PMD<7:0> data bus followed by the upper 6 or 7 address bits (if CS2, CS1 or both are enabled) and therefore require two extra peripheral-bus-clock cycles. Figure 13-41: Full Multiplexed Addressing, 8-Bit Data (Up to 15-Bit Address) PIC32MX PMALL PMD<7:0> A<7:0> 373 D<7:0> PMALH PMCS2 PMRD PMWR A<14:8> 373 Note: (Master mode 2) MODE<1:0> = 10 (8-bit data width) MODE16 (PMMODE<10>) = 0 (Full Multiplexed mode) ADRMUX (PMCON<12:11>) = 10 The 373 shown in the diagram represents a generic 74XX family 373 latch. 32K x 8-Bit Device A<14:0> D<7:0> CE OE WR Address Bus Data Bus Control Lines 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-65 PIC32MX Family Reference Manual Figure 13-42 illustrates the connections to a 16-bit memory or other addressable peripheral in full 16-bit Multiplex mode, ADRMUX = 10 (PMCON<12:11>). Consequently, from the microcontroller perspective, this mode achieves the best pin saving over the Demultiplexed mode or Partially Multiplexed mode, however, at the price of performance. The lower 8 address bits are multiplexed with the PMD<7:0> data bus followed by the upper 6 or 7 address bits (if CS2, CS1 or both are enabled) and therefore require two extra peripheral-bus-clock cycles. Figure 13-42: Full Multiplexed Addressing, 16-Bit Data (Up to 15-Bit Address) PIC32MX PMALL PMD<15:0> D<7:0> A<7:0> 373 D<15:0> PMALH PMCS2 PMRD PMWR D<7:0> A<14:8> 373 Note: (Master mode 2) MODE<1:0> = 10 (16-bit data width) MODE16 (PMMODE<10>) = 1 (Full Multiplexed mode) ADRMUX (PMCON<12:11>) = 10 The 373 shown in the diagram represents a generic 74XX family 373 latch. 32K x 16-Bit Device A<14:0> D<15:0> CE OE WR Address Bus Data Bus Control Lines DS61128D-page 13-66 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port Figure 13-43 illustrates the connections to a 16-bit memory or other addressable peripheral in full 16-bit Multiplex mode, ADRMUX = 11 (PMCON<12:11>). Consequently, from the microcontroller perspective, this mode achieves the best pin saving over the Demultiplexed mode or Partially Multiplexed mode, however, at the price of performance. Compared to the previous Full Multiplex mode, ADRMUX = 10, this mode multiplexes 14 or 15 address bits (if CS2, CS1 or both are enabled) simultaneously with the PMD<15:0> bus and therefore requires only one extra peripheral-bus-clock cycle. Figure 13-43: Example 2 of Full 16-Bit Multiplexed Addressing, 16-Bit Data (Up to 15-Bit Address) PIC32MX PMALL PMD<15:0> D<7:0> A<7:0> 373 D<15:0> PMALH PMCS2 PMRD PMWR D<15:8> A<14:8> 373 Note: (Master mode 2) MODE<1:0> = 10 (16-bit data width) MODE16 (PMMODE<10>) = 1 (Full Multiplexed mode) ADRMUX (PMCON<12:11>) = 11 The 373 shown in the diagram represents a generic 74XX family 373 latch. 32K x 16-Bit Device A<14:0> D<15:0> CE OE WR Address Bus Data Bus Control Lines 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-67 PIC32MX Family Reference Manual 13.8.4 8-Bit LCD Controller Example The PMP module can be configured to connect to a typical LCD controller interface as shown in Figure 13-44. In this case the PMP module is configured for Master mode 1, MODE<1:0> = 11 (PMMODE<9:8>), and uses active-high control signals since common LCD displays require active-high control. Figure 13-44: Example of Demultiplexed Addressing, 8-Bit Data, LCD Controller PIC32MX PMD<7:0> PMA0 PMRD/WR PMENB D<7:0> RS R/W E LCD Controller Note: (Master mode 1) MODE<1:0> = 11 (8-bit data width) MODE16 (PMMODE<10>) = 0 (Demultiplexed mode) ADRMUX (PMCON<12:11>) = 00 Address Line Data Bus Control Lines 13.9 PARALLEL SLAVE PORT APPLICATIONS Figure 13-45: Legacy Mode Slave Port PIC32MX PMD<7:0> MASTER D<7:0> PMCS1 CE PMRD OE PMWR WR Note: (Legacy Slave mode) MODE<1:0> (PMMODE<9:8>) = 00 Data Bus Control Lines DS61128D-page 13-68 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.10 I/O PIN CONTROL 13.10.1 I/O Pin Resources When enabling the PMP module for Master mode operations, the PMAEN register must be configured (set = 1) for the corresponding bits of PMA<15:0> I/O pins to be controlled by the PMP module. Those I/O pins not configured for use by the PMP module remain as general purpose I/O pins. Table 13-12: Required I/O Pin Resources for Master Modes I/O Pin Name Demultiplex Partial Multiplex Full Multiplex PMPCS2/PMA15 Yes(2) Yes(2) Yes(2) PMPCS1/PMA14 Yes(2) Yes(2) Yes(2) PMA<13:2> Yes(2) Yes(3) No(1) PMA1/PALH No(1) No(1) Yes(4) PMA0/PALL No(1) Yes(3) Yes(4) Functional Description PMP Chip Select 2/Address A15 PMP Chip Select 1/Address A14 PMP Address A13..A2 PMP Address A1/Address Latch High PMP Address A0/Address Latch Low PMRD/PMWR Yes Yes Yes PMP Read/Write Control PMWR/PMENB PMD<15:0>(6) Yes Yes(5) Yes Yes(5) Yes Yes(5) PMP Write/Enable Control PMP Bidirectional Data Bus D15..D0 Note 1: “No” indicates the pin is not required and is available as a general purpose I/O pin when the corresponding PMAEN bit is cleared = 0. 2: Depending on the application, not all PMA<15:0> or CS2, CS1 may be required. 3: When Partial Multiplex mode is selected (ADDRMUX<1:0> = 01), the lower 8 address lines are multiplexed with PMD<7:0>, PMA<0> becomes (ALL) and PMA<7:1> are available as general purpose I/O pins. 4: When Full Multiplex mode is selected (ADDRMUX<1:0> = 10 or 11), all 16 address lines are multiplexed with PMD<15:0>, PMA<0> becomes (ALL), PMA<1> becomes (ALH) and PMA<13:2> are available as general purpose I/O pins. 5: If MODE16 = 0, then only PMD<7:0> are required. PMD<15:8> are available as general purpose I/O pins. 6: Data pins PMD<15:0> are available on 100-pin PIC32MX device variants and larger. For all other device variants, only pins PMD<7:0> are available. Refer to the specific PIC32MX device data sheet for details. 13 When enabling any of the PMP module for Slave mode operations, the PMPCS1, PMRD, PMWR control pins and PMD<7:0> data pins are automatically enabled and configured. The user is, however, responsible for selecting the appropriate polarity for these control lines. Table 13-13: Required I/O Pin Resources for Slave Modes I/O Pin Name Legacy Buffered Enhanced Functional Description PMPCS1/PMA14 Yes Yes Yes PMA1/PALH No(1) No(1) Yes PMA0/PALL No(1) No(1) Yes Chip Select Address A1 Address A0 PMRD/PMWR Yes Yes Yes Read Control PMWR/PMENB PMD<15:0> Yes Yes(2) Yes Yes(2) Yes Yes(2) Write Control Bidirectional Data Bus D7..D0 Note 1: “No” indicates the pin is not required and is available as a general purpose I/O pin when the corresponding PMAEN bit is cleared = 0. 2: Slave modes use PMD<7:0> only pins. PMD<15:8> are available as general purpose I/O pins. Control bit MODE16 (PMMODE<10>) is ignored. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-69 PIC32MX Family Reference Manual 13.10.2 I/O Pin Configuration The following table provides a summary of the settings required to enable the I/O pin resources used with this module. The PMAEN register controls the functionality of pins PMA<15:0>. Setting any PMAEN bit = 1 configures the corresponding PMA pin as an address line. Those bits set = 0 remain as general purpose I/O pins. Table 13-14: I/O Pin Configuration Required Settings for Module Pin Control I/O Pin Name Required(1) Module Control Bit Field TRIS Pin Type Buffer Type Description PMPCS2/PMA15 Yes PMPCS1/PMA14 Yes PMA<13:2> Yes PMA1/PALH Yes ON CSF<1:0>, CS2, — PTEN15 ON CSF<1:0>, — CS1 PTEN14 ON PTEN<13:2> — ON PTEN<1> — PMA0/PALL Yes ON PTEN<0> — PMRD/PMWR Yes ON PTRDEN — PMWR/PMENB Yes ON PTWREN — PMD<15:0> Yes ON MODE16, — ADRMUX<1:0> Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output O CMOS O CMOS PMP Chip Select 2/ Address A15 PMP Chip Select 1/ Address A14 O CMOS PMP Address A13 .. A2 I,O CMOS PMP Address A1/ Address Latch High I,O CMOS PMP Address A0/ Address Latch Low O CMOS PMP Read/Write Control O CMOS PMP Write/Enable Control I,O CMOS PMP Bidirectional Data Bus D15 .. D0 Note 1: Depending on the PMP mode and the user’s application, these pins may not be required. If not enabled, these pins can be used for general purpose I/O. DS61128D-page 13-70 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.11 DESIGN TIPS Question 1: Is it possible for the PMP module to address memory devices larger than 64K? Answer: Yes, however not directly under the control of the PMP module. When using the PMCS2 or PMCS1 Chip Select pins, the addressable range is limited to 16K or 32K locations, depending on the Chip Select pin being used. Disabling PMCS2 and PMCS1 as Chip Selects allows these pins to function as address lines PMA15 and PMA14, increasing the range to 64K addressable locations. A dedicated I/O pin is required to function as the Chip Select and the user’s software must now control the function of this pin. To interface to memory devices larger than 64K, use additional available I/O pins as the higher order address lines A16, A17, A18, etc. Figure 13-46: Example Interface to a 16 Megabit (1 M x 16-Bit) SRAM Memory Device PIC32MX 1024K x 16-Bit Device RD3 RD2 RD1 RD0 PMA<15:0> PMD<15:0> A<15:0> D<15:0> RG15 PMRD PMWR Note: (Master mode 2) MODE<1:0> = 10 (16-bit Data Width) MODE16 (PMMODE<10>) = 1 (Demultiplexed Mode) ADRMUX (PMCON<12:11>) = 00 A<19> A<18> A<17> A<16> A<15:0> D<15:0> CE OE WR Address Bus Data Bus Control Lines 13 Question 2: Is it possible to execute code from an external memory device connected to the PMP module? Answer: No. Because of the architecture of the PMP module, this is not possible. Only data can be read or written through the PMP. Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-71 PIC32MX Family Reference Manual 13.12 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the PMP module are: Title No related application notes at this time. Application Note # N/A Note: Please visit the Microchip web site (www.microchip.com) for additional Application Notes and code examples for the PIC32MX family of devices. DS61128D-page 13-72 Preliminary © 2008 Microchip Technology Inc. Section 13. Parallel Master Port 13.13 REVISION HISTORY Revision A (August 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x; Revised Table 13-10; Revised Section 13.3.1.6 and Section 13.3.8; Revised Register 13-5; Revised Figures 13-11, 13-37, 13-40, 13-41, 13-42, 13-43, 13-46; Revised Timing Diagram text for Figures 13-16, 13-18, 13-19. Revision D (June 2008) Revised Register 13-1, add note to FRZ; Revised Figures 13-4, 13-6, 13-8, 13-10, 13-36, 13-37, 13-38, 13-45; Revised Table 13-6; Revised Examples 13-6 and 13-7; Change Reserved bits from “Maintain as” to “Write”; Added Note to ON bit (PMCON Register). 13 Parallel Master Port © 2008 Microchip Technology Inc. Preliminary DS61128D-page 13-73 PIC32MX Family Reference Manual NOTES: DS61128D-page 13-74 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers HIGHLIGHTS This section of the manual contains the following topics: 14.1 Introduction ................................................................................................................. 14-2 14.2 Control Registers ........................................................................................................ 14-6 14.3 Modes of Operation................................................................................................... 14-25 14.4 Interrupts ................................................................................................................... 14-40 14.5 Operation in Power-Saving and DEBUG Modes....................................................... 14-43 14.6 Effects of Various Resets .......................................................................................... 14-44 14.7 Peripherals Using Timer Modules ............................................................................. 14-45 14.8 I/O Pin Control........................................................................................................... 14-46 14.9 Frequently Asked Questions ..................................................................................... 14-47 14.10 Related Application Notes......................................................................................... 14-48 14.11 Revision History ........................................................................................................ 14-49 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-1 PIC32MX Family Reference Manual 14.1 INTRODUCTION The PIC32MX device family features two different types of timers, depending on the device variant. Timers are useful for generating accurate time-based periodic interrupt events for software applications or real-time operating systems. Other uses include counting external pulses or accurate timing measurement of external events using the timer’s gate feature. With certain exceptions, all of the timers have the same functional circuitry. All timers are classified into two types to account for their functional differences. • Type A Timer (16-bit synchronous/asynchronous timer/counter with gate) • Type B Timer (16-bit, 32-bit synchronous timer/counter with gate and Special Event Trigger) All Timer modules includes the following common features: • 16-bit timer/counter • Software-selectable internal or external clock source • Programmable interrupt generation and priority • Gated external pulse counter Beyond the common features, each timer type offers these additional features: Type A: • Asynchronous timer/counter with a built-in oscillator • Operational during CPU SLEEP mode • Software selectable prescalers 1:1, 1:8, 1:64 and 1:256 Type B: • Ability to form a 32-bit timer/counter • Software prescalers 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64 and 1:256 • Event trigger capability The following table presents a summary of timer features. For a specific device variant, refer to the PIC32MX device family data sheet for the available type and number of timers. Table 14-1: Available Timer Types Timer Features Secondary Oscillator Asynchronous External Clock Synchronous External Clock 16-Bit Synchronous Timer/Counter 32-Bit(1) Synchronous Timer/Counter Gated Timer Special Event Trigger Type A Yes Yes Yes Yes No Yes No Type B No No Yes Yes Yes Yes Yes Note 1: 32-bit timer/counter configuration requires an even-numbered timer combined with an adjacent odd-numbered timer, e.g., Timer2 and Timer3, or Timer4 and Timer 5. DS61105D-page 14-2 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.1.1 Type A Timer Most PIC32MX devices contain at least one Type A timer; usually, Timer1. The Type A Timer module is distinct from other types of timers, based on the following features: • Operable from the external secondary oscillator • Operable in Asynchronous mode using an external clock source • Operable during CPU SLEEP mode • Software selectable prescalers 1:1, 1:8, 1:64 and 1:256 The Type A Timer does not support 32-bit mode. The unique features of a Type A Timer module allow it to be used for Real-Time Clock (RTC) applications. A block diagram of the Type A Timer module is shown in Figure 14-1. Figure 14-1: Type A Timer Block Diagram PR1 Equal Comparator x 16 Reset TMR1 0 T1IF Event Flag 1 TGATE (T1CON<7>) QD Q SOSCO/T1CK SOSCI 32 kHz Secondary Oscillator (1, 2) (Type A Timers Only) SOSCEN Gate Sync TPBCLK (Type A Timers Only) TSYNC (T1CON<2>) 1 Sync 0 TGATE (T1CON<7>) TCS (T1CON<1>) ON (T1CON<15>) X1 Prescaler 10 1, 8, 64, 256 00 2 TCKPS (T1CON<5:4>) Note 1: Refer to Section 6. “Oscillators” for information on enabling the 32 kHz Secondary Oscillator. 2: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in Configuration Word DEVCFG1. Timers 14 © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-3 PIC32MX Family Reference Manual 14.1.2 Type B Timer The Type B timer is distinct from other types of timers, based on the following features: • Can be combined to form a 32-bit timer • Software selectable prescalers 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64 and 1:256 • ADC event trigger capability A block diagram of Type B timer (16-bit) is shown in Figure 14-2. Figure 14-2: Type B Timer Block Diagram (16-Bit) Data Bus<31:0> <15:0> (Timers 3, Only) ADC Event Trigger Reset TMRx Comparator x 16 Equal PRx Sync 0 TxIF Event Flag 1 TGATE (TxCON<7>) (Type B Timers Only) TxCK(1) QD Q Gate Sync TPBCLK TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) X1 Prescaler 10 1, 2, 4, 8, 16, 32, 64, 256 00 3 TCKPS (TxCON<6:4>) Note 1: In certain variants of the PIC32MX family, the TxCK pin may not be available. Refer to the device data sheet for the I/O pin details. In such cases, the timer must use the peripheral clock as its input clock. DS61105D-page 14-4 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers A block diagram of Type B timer (32-bit) is shown in Figure 14-3. Note: The Timer Configuration bit, T32 (TxCON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the TxCON register. All interrupt bits are respective to the TyCON register. Figure 14-3: Type B Timer Block Diagram (32-Bit) Data Bus<31:0> <31:0> (Timers 3, Only) ADC Event Trigger Reset TMRy TMRx most significant half word least significant half word Equal Comparator x 32 Sync PRy TyIF Event Flag 0 1 TGATE (TxCON<7>) (Type B Timers Only) TxCK(1) PRx QD Q Gate Sync TPBCLK TGATE (TxCON<7>) TCS (TxCON<1>) ON (TxCON<15>) X1 Prescaler 10 1, 2, 4, 8, 16, 32, 64, 256 00 3 TCKPS (TxCON<6:4>) Note 1: In certain variants of the PIC32MX family, the TxCK pin may not be available. Refer to the device data sheet for the I/O pin details. In such cases, the timer must use the peripheral clock as its input clock. 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-5 PIC32MX Family Reference Manual 14.2 CONTROL REGISTERS Note: Each PIC32MX device variant may have one or more Timer modules. An ‘x’ used in the names of pins, control/Status bits, and registers denotes the particular module. Refer to the specific device data sheets for more details. Each timer module is a 16-bit timer/counter that consists of the following Special Function Registers (SFRs): • TxCON: 16-Bit Control Register Associated with the Timer • TxCONCLR, TxCONSET, TxCONINV: Atomic Bit Manipulation Write-only Registers for TxCON • TMRx: 16-Bit Timer Count Register • TMRxCLR, TMRxSET, TMRxINV: Atomic Bit Manipulation Write-only Registers for TMRx • PRx: 16-Bit Period Register Associated with the Timer • PRxCLR, PRxSET, PRxINV: Atomic Bit Manipulation Write-only Registers for PRx Each timer module also has the following associated bits for interrupt control: • TxIE: Interrupt Enable Control Bit – in IEC0 INT Register • TxIF: Interrupt Flag Status Bit – in IFS0 INT Register • TxIP<2:0>: Interrupt Priority Control Bits – in IPC1, IPC2, IPC3, IPC4, IPC5 INT Registers • TxIS<1:0>: Interrupt Subpriority Control Bits – in IPC1, IPC2, IPC3, IPC4, IPC5 INT Registers The following table summarizes all Timer-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Table 14-2: Name Timers SFR Summary Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 T1CON 31:24 — — — — — — — — 23:16 — — — — — — — — 7:0 TGATE — TCKPS<1:0> — TSYNC TCS — T1CONCLR 31:0 Write clears selected bits in T1CON, read yields undefined value T1CONSET 31:0 Write sets selected bits in T1CON, read yields undefined value T1CONINV 31:0 Write inverts selected bits in T1CON, read yields undefined value TxCON 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 ON FRZ SIDL — — — — — 7:0 TGATE TCKPS<2:0>(2) T32(1) — TCS — TxCONCLR 31:0 Write clears selected bits in TxCON, read yields undefined value TxCONSET 31:0 Write sets selected bits in TxCON, read yields undefined value TxCONINV 31:0 Write inverts selected bits in TxCON, read yields undefined value TMRx 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 TMRx<15:8> 7:0 TMRx<7:0> TMRxCLR 31:0 Write clears selected bits in TMRx, read yields undefined value TMRxSET 31:0 Write sets selected bits in TMRx, read yields undefined value TMRxINV 31:0 Write inverts selected bits in TMRx, read yields undefined value Note 1: Bit T32 is available only on even-numbered Type B timers, e.g., Timer2, Timer4. 2: TCKPS<2:0> is available only on even-numbered Type B timers, e.g., Timer2, Timer4 in 32-bit Timer mode. DS61105D-page 14-6 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Table 14-2: Timers SFR Summary (Continued) Name Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 PRx 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 PRx<15:8> 7:0 PRx<7:0> PRxCLR 31:0 Write clears selected bits in PRx, read yields undefined value PRxSET 31:0 Write sets selected bits in PRx, read yields undefined value PRxINV 31:0 Write inverts selected bits in PRx, read yields undefined value IEC0 31:24 I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE 23:16 SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 15:8 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE 7:0 INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE IFS0 31:24 I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF 23:16 SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 15:8 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF 7:0 INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF IPC1 31:24 — — — INT1IP<2:0> INT1IS<1:0> 23:16 — — — OC1IP<2:0> OC1IS<1:0> 15:8 — — — IC1IP<2:0> IC1IS<1:0> 7:0 — — — T1IP<2:0> T1IS<1:0> IPC2 31:24 — — — INT2IP<2:0> INT2IS<1:0> 23:16 — — — OC2IP<2:0> OC2IS<1:0> 15:8 — — — IC2IP<2:0> IC2IS<1:0> 7:0 — — — T2IP<2:0> T2IS<1:0> IPC3 31:24 — — — INT3IP<2:0> INT3IS<1:0> 23:16 — — — OC3IP<2:0> OC3IS<1:0> 15:8 — — — IC3IP<2:0> IC3IS<1:0> 7:0 — — — T3IP<2:0> T3IS<1:0> IPC4 31:24 — — — INT4IP<2:0> INT4IS<1:0> 23:16 — — — OC4IP<2:0> OC4IS<1:0> 15:8 — — — IC4IP<2:0> IC4IS<1:0> 7:0 — — — T4IP<2:0> T4IS<1:0> IPC5 31:24 — — — SPI1IP<2:0> SPI1IS<1:0> 23:16 — — — OC5IP<2:0> OC5IS<1:0> 15:8 — — — IC5IP<2:0> IC5IS<1:0> 7:0 — — — T5IP<2:0> T5IS<1:0> Note 1: Bit T32 is available only on even-numbered Type B timers, e.g., Timer2, Timer4. 2: TCKPS<2:0> is available only on even-numbered Type B timers, e.g., Timer2, Timer4 in 32-bit Timer mode. Timers 14 © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-7 PIC32MX Family Reference Manual Register 14-1: T1CON: Type A Timer Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R-0 r-x r-x r-x ON FRZ SIDL TWDIS TWIP — — — bit 15 bit 8 R/W-0 r-x R/W-0 R/W-0 r-x R/W-0 R/W-0 r-x TGATE — TCKPS<1:0> — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10-8 Reserved: Write ‘0’; ignore read ON: Timer On bit 1 = Timer is enabled 0 = Timer is disabled Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation even when CPU is in Debug Exception mode Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in Normal mode. SIDL: Stop in IDLE Mode bit 1 = Discontinue operation when device enters IDLE mode 0 = Continue operation even in IDLE mode TWDIS: Asynchronous Timer Write Disable bit 1 = Writes to TMR1 are ignored until pending write operation completes 0 = Back to back writes are enabled (Legacy Asynchronous Timer functionality) TWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode: 1 = Asynchronous write to TMR1 register in progress 0 = Asynchronous write to TMR1 register complete In Synchronous Timer mode: This bit is read as ‘0’. Reserved: Write ‘0’; ignore read DS61105D-page 14-8 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Register 14-1: T1CON: Type A Timer Control Register (Continued) bit 7 TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored and read ‘0’. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6 Reserved: Write ‘0’; ignore read bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 Reserved: Write ‘0’; ignore read bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored and read ‘0’. bit 1 TCS: Timer Clock Source Select bit 1 = External clock from TxCKI pin 0 = Internal peripheral clock bit 0 Reserved: Write ‘0’; ignore read 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-9 PIC32MX Family Reference Manual Register 14-2: T1CONCLR: Timer Control Clear Register Write clears selected bits in T1CON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in T1CON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in T1CON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: T1CONCLR = 0x00008001 will clear bits 15 and 0 in T1CON register. Register 14-3: T1CONSET: Timer Control Set Register Write sets selected bits in T1CON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in T1CON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in T1CON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: T1CONSET = 0x00008001 will set bits 15 and 0 in T1CON register. Register 14-4: T1CONINV: Timer Control Invert Register Write inverts selected bits in T1CON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in T1CON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in T1CON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: T1CONINV = 0x00008001 will invert bits 15 and 0 in T1CON register. DS61105D-page 14-10 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Register 14-5: TxCON: Type B Timer Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x r-x ON FRZ SIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x R/W-0 r-x TGATE TCKPS<2:0> T32 — TCS — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14 bit 13 bit 12-8 bit 7 Reserved: Write ‘0’; ignore read ON: Timer On bit 1 = Module is enabled 0 = Module is disabled Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation even when CPU is in Debug Exception mode Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in Normal mode. SIDL: Stop in IDLE Mode bit 1 = Discontinue operation when device enters IDLE mode 0 = Continue operation even in IDLE mode Reserved: Write ‘0’; ignore read TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored and read ‘0’. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled Timers 14 © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-11 PIC32MX Family Reference Manual Register 14-5: TxCON: Type B Timer Control Register (Continued) bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 3 T32: 32-Bit Timer Mode Select bit 1 = TMRx and TMRy form a 32-bit timer 0 = TMRx and TMRy form separate 16-bit timer Note: Bit T32 is available only on even-numbered Type B timers: Timer 2, Timer 4, etc. bit 2 Reserved: Write ‘0’; ignore read bit 1 TCS: Timer Clock Source Select bit 1 = External clock from TxCKI pin 0 = Internal peripheral clock bit 0 Reserved: Write ‘0’; ignore read DS61105D-page 14-12 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Register 14-6: TxCONCLR: Type B Timer Control Clear Register Write clears selected bits in TxCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in TxCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in TxCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TxCONCLR = 0x00008001 will clear bits 15 and 0 in TxCON register. Register 14-7: TxCONSET: Type B Timer Control Set Register Write sets selected bits in TxCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in TxCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in TxCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TxCONSET = 0x00008001 will set bits 15 and 0 in TxCON register. Register 14-8: TxCONINV: Type B Timer Control Invert Register Write inverts selected bits in TxCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in TxCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in TxCON register and does 14 not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TxCONINV = 0x00008001 will invert bits 15 and 0 in TxCON register. Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-13 PIC32MX Family Reference Manual Register 14-9: TMRx: Timer Register R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 TMR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 TMR<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 15-0 TMRx<15:0>: Timer Count Register 16-bit mode: These bits represent the complete 16-bit timer count. 32-bit mode (Timer Type B only): Timer2 and Timer4 These bits represent the least significant half word (16 bits) of the 32-bit timer count. Timer3 and Timer5 These bits represent the most significant half word (16 bits) of the 32-bit timer count. DS61105D-page 14-14 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Register 14-10: TMRxCLR: Timer Clear Register Write clears selected bits in TMRx, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in TMRx A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in TMRx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TMRxCLR = 0x00008001 will clear bits 15 and 0 in TMRx register. Register 14-11: TMRxSET: Timer Set Register Write sets selected bits in TMRx, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in TMRx A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in TMRx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TMRxSET = 0x00008001 will set bits 15 and 0 in TMRx register. Register 14-12: TMRxINV: Timer Invert Register Write inverts selected bits in TMRx, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in TMRx A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in TMRx register and does 14 not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TMRxINV = 0x00008001 will invert bits 15 and 0 in TMRx register. Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-15 PIC32MX Family Reference Manual Register 14-13: PRx: Period Register R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 PR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 PR<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 15-0 PRx<15:0>: Period Register 16-bit mode: These bits represent the complete 16-bit period match 32-bit mode (Timer Type B only): Timer2 and Timer4 These bits represent the least significant half word (16 bits) of the 32-bit period match. Timer3 and Timer5 These bits represent the most significant half word (16 bits) of the 32-bit period match. DS61105D-page 14-16 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Register 14-14: PRxCLR: Period Clear Register Write clears selected bits in PRx, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PRx A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PRx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PRxCLR = 0x00008001 will clear bits 15 and 0 in PRx register. Register 14-15: PRxSET: Period Set Register Write sets selected bits in PRx, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PRx A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PRx register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PRxSET = 0x00008001 will set bits 15 and 0 in PRx register. Register 14-16: PRxINV: Period Invert Register Write inverts selected bits in PRx, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PRx A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PRx register and does not 14 affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PRxINV = 0x00008001 will invert bits 15 and 0 in PRx register. Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-17 PIC32MX Family Reference Manual Register 14-17: IEC0: Interrupt Enable Control Register(1) R/W-0 I2C1MIE bit 31 R/W-0 I2C1SIE R/W-0 I2C1BIE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 U1EIE R/W-0 SPI1RXIE R/W-0 SPI1TXIE bit 24 R/W-0 SPI1EIE bit 23 R/W-0 OC5IE R/W-0 IC5IE R/W-0 T5IE R/W-0 INT4IE R/W-0 OC4IE R/W-0 IC4IE R/W-0 T4IE bit 16 R/W-0 INT3IE bit 15 R/W-0 OC3IE R/W-0 IC3IE R/W-0 T3IE R/W-0 INT2IE R/W-0 OC2IE R/W-0 IC2IE R/W-0 T2IE bit 8 R/W-0 INT1IE bit 7 R/W-0 OC1IE R/W-0 IC1IE R/W-0 T1IE R/W-0 INT0IE R/W-0 CS1IE R/W-0 CS0IE R/W-0 CTIE bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 20 T5IE: Timer5 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 16 T4IE: Timer4 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 12 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 8 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Timers. DS61105D-page 14-18 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Register 14-18: IFS0: Interrupt Flag Status Register 0(1) R/W-0 I2C1MIF bit 31 R/W-0 I2C1SIF R/W-0 I2C1BIF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 U1EIF R/W-0 SPI1RXIF R/W-0 SPI1TXIF bit 24 R/W-0 SPI1EIF bit 23 R/W-0 OC5IF R/W-0 IC5IF R/W-0 T5IF R/W-0 INT4IF R/W-0 OC4IF R/W-0 IC4IF R/W-0 T4IF bit 16 R/W-0 INT3IF bit 15 R/W-0 OC3IF R/W-0 IC3IF R/W-0 T3IF R/W-0 INT2IF R/W-0 OC2IF R/W-0 IC2IF R/W-0 T2IF bit 8 R/W-0 INT1IF bit 7 R/W-0 OC1IF R/W-0 IC1IF R/W-0 T1IF R/W-0 INT0IF R/W-0 CS1IF R/W-0 CS0IF R/W-0 CTIF bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 20 T5IF: Timer5 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has occurred bit 16 T4IF: Timer4 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has occurred bit 12 T3IF: Timer3 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has occurred bit 8 T2IF: Timer2 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has occurred bit 4 T1IF: Timer1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has occurred Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Timers. Timers 14 © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-19 PIC32MX Family Reference Manual Register 14-19: IPC1: Interrupt Priority Control Register 1(1) r-x r-x r-x R/W-0 R/W-0 — — — INT1IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 INT1IS<1:0> bit 24 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — OC1IP<2:0> OC1IS<1:0> bit 23 bit 16 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — IC1IP<2:0> IC1IS<1:0> bit 15 bit 8 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — T1IP<2:0> T1IS<1:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 4-2 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled bit 1-0 T1IS<1:0>: Timer1 Interrupt Subpriority bits 11 = Interrupt Subpriority is 3 10 = Interrupt Subpriority is 2 01 = Interrupt Subpriority is 1 00 = Interrupt Subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Timer1. DS61105D-page 14-20 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Register 14-20: IPC2: Interrupt Priority Control Register 2(1) r-x r-x r-x R/W-0 R/W-0 — — — INT2IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 INT2IS<1:0> bit 24 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — OC2IP<2:0> OC2IS<1:0> bit 23 bit 16 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — IC2IP<2:0> IC2IS<1:0> bit 15 bit 8 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — T2IP<2:0> T2IS<1:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 4-2 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled bit 1-0 T2IS<1:0>: Timer2 Interrupt Subpriority bits 11 = Interrupt Subpriority is 3 10 = Interrupt Subpriority is 2 01 = Interrupt Subpriority is 1 00 = Interrupt Subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Timer2. 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-21 PIC32MX Family Reference Manual Register 14-21: IPC3: Interrupt Priority Control Register 3(1) r-x r-x r-x R/W-0 R/W-0 — — — INT3IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 INT3IS<1:0> bit 24 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — OC3IP<2:0> OC3IS<1:0> bit 23 bit 16 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — IC3IP<2:0> IC3IS<1:0> bit 15 bit 8 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — T3IP<2:0> T3IS<1:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 4-2 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled bit 1-0 T3IS<1:0>: Timer3 Interrupt Subpriority bits 11 = Interrupt Subpriority is 3 10 = Interrupt Subpriority is 2 01 = Interrupt Subpriority is 1 00 = Interrupt Subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Timer3. DS61105D-page 14-22 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Register 14-22: IPC4: Interrupt Priority Control Register 4(1) r-x r-x r-x R/W-0 R/W-0 — — — INT4IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 INT4IS<1:0> bit 24 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — OC4IP<2:0> OC4IS<1:0> bit 23 bit 16 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — IC4IP<2:0> IC4IS<1:0> bit 15 bit 8 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — T4IP<2:0> T4IS<1:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 4-2 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled bit 1-0 T4IS<1:0>: Timer4 Interrupt Subpriority bits 11 = Interrupt Subpriority is 3 10 = Interrupt Subpriority is 2 01 = Interrupt Subpriority is 1 00 = Interrupt Subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Timer4. 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-23 PIC32MX Family Reference Manual Register 14-23: IPC5: Interrupt Priority Control Register 5(1) r-x r-x r-x R/W-0 R/W-0 — — — SPI1IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 SPI1IS<1:0> bit 24 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — OC5IP<2:0> OC5IS<1:0> bit 23 bit 16 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — IC5IP<2:0> IC5IS<1:0> bit 15 bit 8 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — T5IP<2:0> T5IS<1:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 4-2 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled bit 1-0 T5IS<1:0>: Timer5 Interrupt Subpriority bits 11 = Interrupt Subpriority is 3 10 = Interrupt Subpriority is 2 01 = Interrupt Subpriority is 1 00 = Interrupt Subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Timer5. DS61105D-page 14-24 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.3 MODES OF OPERATION 14.3.1 16-Bit Modes Both Type A and Type B timer modules support the following 16-bit modes: • 16-bit Synchronous Clock Counter • 16-bit Synchronous External Clock Counter • 16-bit Asynchronous External Counter (Type A Timer module only) • 16-bit Gated Timer The 16-bit Timer modes are determined by the following bits: • TCS (TxCON<1>): Timer Clock Source Control bit • TSYNC (T1CON<2>): Timer Synchronization Control bit (Type A Timer module only) • TGATE (TxCON<7>): Timer Gate Control bit 14.3.1.1 16-Bit Timer Considerations The following should be considered when using a 16-bit timer: • All timer module SFRs can be written to as a byte (8 bits) or as a half word (16 bits). • All timer module SFRs can be read from as a byte or as a half word. 14.3.2 32-Bit Modes (Type B Timer) Only Type B timer modules support 32-bit modes of operation. A 32-Bit Timer module is formed by combining an even numbered Type B timer (referred to as TimerX) with a consecutive odd numbered Type B timer (referred to as TimerY). For example, 32-bit timer combinations are Timer2 and Timer3, Timer4 and Timer5, etc. The number of timer pairs depends on the device family variant. The 32-Bit Timer pairs can operate in the following modes: • 32-Bit Synchronous Clock Counter • 32-Bit Synchronous External Clock Counter • 32-Bit Gated Timer The 32-Bit Timer modes are determined by the following bits: • T32 (TxCON<3>): 32-Bit mode Control Bit (TimerX only) • TCS (TxCON<1>): Timer Clock Source Control Bit • TGATE (TxCON<7>): Timer Gate Control Bit Specific behavior in 32-bit Timer mode: • TimerX is the master timer; TimerY is the slave timer • TMRx count register is least significant half word (lshw) of the 32-bit timer value • TMRy count register is most significant half word (mshw) of the 32-bit timer value • PRx period register is least significant half word of the 32-bit period value • PRy period register is most significant half word of the 32-bit period value • TimerX control bits (TxCON) configure the operation for the 32-bit timer pair • TimerY control bits (TyCON) have no effect • TimerX interrupt and Status bits are ignored • TimerY provides the interrupt enable, interrupt flag and interrupt priority control bits Timers 14 © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-25 PIC32MX Family Reference Manual 14.3.2.1 32-Bit Timer Considerations The following should be considered when using a 32-bit timer: • Ensure that the timer pair is configured for 32-bit mode by setting T32 (TxCON<3>) = 1, before writing any 32-bit value to the TMRxy count registers or PRxy period registers. • All timer module SFRs can be written to as a byte (8 bits), a half word (16 bits) or a word (32 bits). • All timer module SFRs can be read from as a byte, a half word or a word. • TMRx and TMRy count register pairs can be read as well as written as a single 32-bit value. • PRx and PRy period register pairs can be read as well as written as a single 32-bit value. 14.3.3 16-Bit Synchronous Clock Counter Mode The Synchronous Clock Counter operation provides the following capabilities: • Elapsed time measurements • Time delays • Periodic timer interrupts Type A and B timers have the ability to operate in Synchronous Clock Counter mode. In this mode, the input clock source for the timer is the internal peripheral bus clock, PBCLK, and is selected by clearing the clock source control bit TCS, (TxCON<1>) = 0. Type A and B Timers automatically provide synchronization to the peripheral bus clock; therefore, the Type A Timer Synchronous mode control bit TSYNC (T1CON<2>) is ignored in this mode. Type A and B timers that use a 1:1 clock prescale operate at a timer clock rate which is the same as the PBCLK, and which increments the TMR count register on every rising timer clock edge. The timer continues to increment until the TMR count register matches the PR period register value. The TMR count register resets to 0000h on the next timer clock cycle, then continues to increment and repeat the period match until the timer is disabled. If the PR period register value = 0000h, the TMR count register resets to 0000h on the next timer clock cycle, but does not continue to increment. Type A and B timers using a clock prescale = N (other than 1:1) operate at a timer clock rate (PBCLK/N) and the TMR count register increments on every Nth timer clock rising edge. For example, if the clock prescale is 1:8, then the timer increments on every 8th timer clock cycle. The timer continues to increment until the TMR count register matches the PR period register value. The TMR count register then resets to 0000h after N more timer clock cycles, then continues to increment and repeat the period match until the timer is disabled. If the PR period register value = 0000h, the TMR count register resets to 0000h on the next Nth timer clock cycle, but will not continue to increment. Type A timers generate a timer event one-half timer clock cycle (on the falling edge) after the TMR count register matches the PR period register value. Type B timers generate a timer event within 1 PBCLK + 2 SYSCLK system clock cycles after the TMR count register matches the PR period register value. Both Type A and B timer interrupt flag bits, TxIF, are set within 1 PBCLK + 2 SYSCLK cycles of this event and if the timer interrupt enable bit TxIE is set, an interrupt is generated. 14.3.3.1 16-Bit Synchronous Clock Counter Considerations This section describes items that should be considered when using a 16-bit Synchronous Clock Counter. The timer period is determined by the value in the PR period register. To initialize the timer period, a user may write to the PR period register directly at any time while the timer is disabled, ON bit = 0, or during a timer match Interrupt Service Routine (ISR) while the timer is enabled, ON bit = 1. In all other cases, writing to the period register while the timer is enabled is not recommended and may allow unintended period matches to occur. The maximum period that can be loaded is FFFFh. Writing 0000h to PRx period register allows a TMRx match to occur; however, no interrupt will be generated. DS61105D-page 14-26 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.3.4 32-Bit Synchronous Clock Counter Mode (Type B Timer) Only Type B timers have the ability to operate in 32-bit Synchronous Counter mode. To enable 32-bit Synchronous Clock Counter operation, Type B (TimerX) T32 control bit (TxCON<3>) must be set (= 1). In this mode, the input clock source for the timer is the internal peripheral bus clock, PBCLK, and is selected by clearing the clock source control bit TCS, (TxCON<1>) = 0. Type B timers automatically provide synchronization to the peripheral bus clock. Type B Timers that use a 1:1 clock prescale operate at a timer clock rate which is the same as the PBCLK, and increments the TMRxy count register on every rising timer clock edge. The timer continues to increment until the TMRxy count register matches the PRxy period register value. The TMRxy count register resets to 00000000h on the next timer clock cycle, then continues to increment and repeat the period match until the timer is disabled. If the PR period register value = 00000000h, the TMR count register resets to 00000000h on the next timer clock cycle, but does not continue to increment. Type B timers using a clock prescale = N (other than 1:1) operate at a timer clock rate (PBCLK/N) and the TMRxy count register increments on every Nth timer clock rising edge. For example, if the clock prescale is 1:8, then the timer increments on every 8th timer clock cycle. The timer continues to increment until the TMRxy count register matches the PRxy period register value. The TMRxy count register resets to 00000000h after N more timer clock cycles, then continues to increment and repeat the period match until the timer is disabled. Type B timers generate a timer event within 1 PBCLK + 2 SYSCLK system clock cycles after the TMRxy count register matches the PRxy period register value. The Type B timer interrupt flag bit, TyIF, is set within 1 PBCLK + 2 SYSCLK cycles of this event and if the timer interrupt enable bit TyIE is set, an interrupt is generated. 14.3.4.1 32-Bit Synchronous Clock Counter Considerations This section describes items that should be considered when using the 32-bit Synchronous Clock Counter. The timer period is determined by the value in the PRxy period register. To initialize the timer period, a user may write to the PRxy period register directly at any time while the timer is disabled, ON bit = 0, or during a timer match Interrupt Service Routine while the timer is enabled, ON bit = 1. In all other cases, writing to the period register while the timer is enabled is not recommended, and may allow unintended period matches to occur. The maximum period that can be loaded is FFFFFFFFh. Writing 00000000h to the PRxy period register will allow a TMRxy match to occur; however, no interrupt is generated. 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-27 PIC32MX Family Reference Manual 14.3.4.2 16-Bit Synchronous Counter Initialization Steps Performed the following steps to configure the timer for 16-bit Synchronous Timer mode. 1. Clear control bit ON (TxCON<15> = 0) to disable timer. 2. Clear control bit TCS (TxCON<1> = 0) to select internal PBCLK source. 3. Select desired clock prescale. 4. Load/Clear timer register TMRx. 5. Load period register PRx with desired 16-bit match value. 6. If interrupts are used: i. Clear interrupt flag bit TxIF in IFS0 register. ii. Configure interrupt priority and subpriority levels in IPCn register. iii. Set interrupt enable bit TxIE in IEC0 registers. 7. Set control bit ON (TxCON<15> = 1) to enable the timer. Example 14-1: 16-Bit Synchronous Clock Counter Example Code T2CON = 0x0; TMR2 = 0x0; PR2 = 0xFFFF; T2CONSET = 0x8000; // Stop Timer and clear control register, // set prescaler at 1:1, internal clock source // Clear timer register // Load period register // Start Timer 14.3.4.3 32-Bit Synchronous Clock Counter Initialization Steps Performed the following steps to configure the timer for 32-bit Synchronous Clock Counter mode. 1. Clear control bit ON (TxCON<15> = 0) to disable timer. 2. Clear control bit TCS (TxCON<1> = 0) to select internal PBCLK source. 3. Set control bit T32 (TxCON<3> = 1) to select 32-bit operations. 4. Select desired clock prescale. 5. Load/Clear timer register TMRxy. 6. Load period register PRxy with desired 32-bit match value. 7. If interrupts are used: i. Clear interrupt flag bit TyIF in IFSn register. ii. Configure interrupt priority and subpriority levels in IPCn register. iii. Set interrupt enable bit TyIE in IECn registers. 8. Set control bit ON (TxCON<15> = 1) to enable the timer. Example 14-2: 32-Bit Synchronous Clock Counter Example Code T4CON = 0x0; T5CON = 0x0; T4CONSET = 0x0038; // Stop any 16/32-bit Timer4 operation // Stop any 16-bit Timer5 operation // Enable 32-bit mode, prescaler 1:8, // internal peripheral clock source TMR4= 0x0; PR4 = 0xFFFFFFFF; // Clear contents of the TMR4 and TMR5 // Load PR4 and PR5 registers with 32-bit value T4CONSET = 0x8000; // Start Timer45 DS61105D-page 14-28 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.3.5 16-Bit Synchronous External Clock Counter Mode The Synchronous External Clock Counter operation provides the following capabilities: • Counting periodic or non-periodic pulses • Use external clock as time base for timers Type A and B timers have the ability to operate in Synchronous External Clock Counter mode. In this mode, the input clock source for the timer is an external clock applied to the TxCK pin and is selected by setting the clock source control bit TCS (TxCON<1>) = 1. Type B timers automatically provide synchronization for the external clock source; however, the Type A timer does not, and requires the external clock synchronization bit TSYNC (T1CON<2>) be set = 1. Type A and B timers that use a 1:1 clock prescale increment the TMR count register on every rising external clock edge after synchronization. The timer continues to increment until the TMR count register matches the PR period register value. The TMR count register resets to 0000h on the next timer clock cycle, then continues to increment and repeat the period match until the timer is disabled. If the PR period register value = 0000h, the TMR count register resets to 0000h on the next timer clock cycle, but will not continue to increment. Type A and B timers using a clock prescale = N (other than 1:1) operate at a timer clock rate (external clock/N) and the TMR count register increments on every Nth external clock rising edge after synchronization. For example, if the clock prescale is 1:8, then the timer increments on every 8th external clock cycle. The timer continues to increment until the TMR count register matches the PR period register value. The TMR count register then resets to 0000h after N more external clock cycles, then continues to increment and repeat the period match until the timer is disabled. If the PR period register value = 0000h, the TMR count register resets to 0000h on the next external clock cycle, but does not continue to increment. Type A timers generate a timer event one-half timer clock cycle (on the falling edge) after the TMR count register matches the PR period register value. Type B timers generate a timer event within 1 PBCLK + 2 SYSCLK system clock cycles after the TMR count register matches the PR period register value. Both Type A and B timer interrupt flag bits, TxIF, are set within 1 PBCLK + 2 SYSCLK cycles of this event and if the timer interrupt enable bit TxIE is set, an interrupt is generated. 14.3.5.1 16-Bit Synchronous External Clock Counter Considerations This section describes items that should be considered when using the 16-bit Synchronous External Clock Counter. Type A or Type B timers operating from a synchronized external clock source will not operate in SLEEP mode, since the synchronization circuit is disabled during SLEEP mode. Type A and B Timers using a clock prescale = N (other than 1:1) require 2 to 3 external clock cycles, after the ON bit = 1, before the TMR count register increments. Refer to Section 14.3.12 “Timer Latency Considerations” for more information. When operating the timer in Synchronous Counter mode, the external input clock must meet certain minimum high time and low time requirements. Refer to the device data sheet “Electrical Specifications” section for further details. 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-29 PIC32MX Family Reference Manual 14.3.6 32-Bit Synchronous External Clock Counter Mode The 32-bit Synchronous External Clock counter operation provides the following capabilities: • Counting large number of periodic or non-periodic pulses • Use external clock as large time base for timers Only Type B timers have the ability to operate in 32-bit Synchronous External Clock Counter mode. To enable 32-bit Synchronous External Clock Counter operation, a Type B (TimerX) T32 control bit (TxCON<3>) must be set = 1. In this mode, the input clock source for the timer is an external clock applied to the TxCK pin and is selected by setting the clock source control bit TCS (TxCON<1>) = 1. Type B timers automatically provide synchronization for the external clock source. Type B timers that use a 1:1 clock prescale increment the TMRxy count register on every rising external clock edge after synchronization. The timer continues to increment until the TMRxy count register matches the PRxy period register value. The TMRxy count register resets to 00000000h on the next timer clock cycle, then continues to increment and repeat the period match until the timer is disabled. If the PRxy period register value = 0000h, the TMR count register resets to 00000000h on the next timer clock cycle, but does not continue to increment. Type B timers that use a clock prescale = N (other than 1:1) operate at a timer clock rate (external clock/N) and the TMRxy count register increments on every Nth external clock rising edge after sychronization. For example, if the clock prescale is 1:8, then the timer increments on every 8th external clock cycle. The timer continues to increment until the TMRxy count register matches the PRxy period register value. The TMRxy count register resets to 0000h after N more external clock cycles, then continues to increment and repeat the period match until the timer is disabled. If the PRxy period register value = 00000000h, the TMRxy count register resets to 00000000h on the next external clock cycle, but does not continue to increment. Type B timers generate a timer event within 1 PBCLK + 2 SYSCLK system clock cycles after the TMRxy count register matches the PRxy period register value. The Type B timer interrupt flag bit, TyIF, is set within 1 PBCLK + 2 SYSCLK cycles of this event and if the timer interrupt enable bit TyIE is set, an interrupt is generated. 14.3.6.1 32-Bit Synchronous External Clock Counter Considerations This section describes items that should be considered when using the 32-bit Synchronous External Clock Counter. Type B timers operating from a synchronized external clock source will not operate in SLEEP mode, since the synchronization circuit is disabled during SLEEP mode. Type B timers using a clock prescale = N (other than 1:1) require 2 to 3 external clock cycles, after the ON bit = 1, before the TMR count register increments. Refer to Section 14.3.12 “Timer Latency Considerations”. When operating the timer in Synchronous Counter mode, the external input clock must meet certain minimum high time and low time requirements. Refer to the device data sheet “Electrical Specifications” section for further details. DS61105D-page 14-30 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.3.6.2 16-Bit Synchronous External Counter Initialization Steps Perform the following steps to configure the timer for 16-bit Synchronous Counter mode: 1. Clear control bit ON (TxCON<15> = 0) to disable timer. 2. Set control bit TCS (TxCON<1> = 1) to select external clock source. 3. If Type A Timer, set control bit TSYNC (T1CON<2> = 1) to enable clock synchronization. 4. Select desired clock prescale. 5. Load/Clear timer register TMRx. 6. If using period match: a. Load period register PRx with desired 16-bit match value. 7. If interrupts are used: i. Clear interrupt flag bit TxIF in IFS0 register. ii. Configure interrupt priority and subpriority levels in IPCn register. iii. Set interrupt enable bit TxIE in IEC0 registers. 8. Set control bit ON (TxCON<15> = 1) to enable the timer. Example 14-3: 16-Bit Synchronous External Counter Example Code T3CON = 0x0; T3CONSET = 0x0072; TMR3 = 0x0; PR3 = 0x3FFF; T3CONSET = 0x8000; // Stop Timer and clear control register // Set prescaler at 1:256, external clock source // Clear timer register // Load period register // Start Timer 14.3.6.3 32-Bit Synchronous External Clock Counter Initialization Steps Perform the following steps to configure the timer for 32-bit Synchronous External Clock Counter mode: 1. Clear control bit ON (TxCON<15> = 0) to disable timer. 2. Set control bits TCS (TxCON<1> = 1) to select external clock source. 3. Set T32 (TxCON<3> = 1) to enable 32-bit operations. 4. Select desired clock prescale. 5. Load/Clear timer register TMRxy. 6. Load period register PRxy with desired 32-bit match value. 7. If interrupts are used: i. Clear interrupt flag bit TyIF in IFSn register. ii. Configure interrupt priority and subpriority levels in IPCn register. iii. Set interrupt enable bit TyIE in IECn registers. 8. Set control bit ON (TxCON<15> = 1) to enable the timer. Example 14-4: 32-Bit Synchronous External Clock Counter Example Code T4CON = 0x0; T5CON = 0x0; T4CONSET = 0x006A; TMR4 = 0x0; // Stop any 16/32-bit Timer4 operation // Stop any 16-bit Timer5 operation // 32-bit mode, external clock, 1:64 prescale // Clear contents of the TMR4 and TMR5 PR4 = 0xFFFFFFFF; // Load PR4 and PR5 registers with 32-bit value T4CONSET = 0x8000; // Start 32-bit timer Timers 14 © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-31 PIC32MX Family Reference Manual 14.3.7 16-Bit Gated Timer Mode The gate operation starts on a rising edge of the signal applied to the TxCK pin. The TMRx count register increments while the external gate signal remains high. The gate operation terminates on the falling edge of the signal applied to the TxCK pin. The timer interrupt flag, TxIF, is set. Both Type A and B timers can operate in Gated Timer mode. The timer clock source is the internal peripheral bus clock, PBCLK, and is selected by clearing the TCS control bit = 0, (TxCON<1>). Type A and B Timers automatically provide synchronization to the peripheral bus clock, therefore the Type A Timer Synchronous mode control bit TSYNC (T1CON<2>) is ignored in this mode. In Gated Timer mode, the input clock is gated by the signal applied to the TxCK pin. The Gated Timer mode is enabled by setting the TGATE control bit = 1, (TxCON<7>). Type A and B timers using a 1:1 clock prescale operate at a timer clock rate the same as the PBCLK and increment the TMR count register on every rising timer clock edge. The timer continues to increment until the TMR count register matches the PR period register value. The TMR count register then resets to 0000h on the next timer clock cycle, then continues to increment and repeat the period match until the falling edge of the gate signal or the timer is disabled. The timer does not generate an interrupt when a timer period match occurs. Type A and B timers using a clock prescale = N (other than 1:1) operate at a timer clock rate (PBCLK/N) and the TMR count register increments on every Nth timer clock rising edge. For example, if the clock prescale is 1:8, then the timer increments on every 8th timer clock cycle. The timer continues to increment until the TMR count register matches the PR period register value. The TMR count register then resets to 0000h after N more timer clock cycles, and continues to increment and repeat the period match until the falling edge of the gate signal or the timer is disabled. The timer does not generate an interrupt when a timer period match occurs. On the falling edge of the gate signal, the count operations terminates, a Timer event is generated and the interrupt flag bit TxIF is set 1 PBCLK + 2 SYSCLK system clock cycles after the falling edge of the signal on the gate pin. The TMR count register is not reset to 0000h. The user must reset the TMR count register if it is desired to start from zero on the next rising edge gate input. The resolution of the timer count is directly related to the timer clock period. When the timer prescaler is 1:1, the timer clock period is one peripheral bus clock cycle TPBCLK. For a timer prescaler of 1:8, the timer clock period is 8 times the peripheral bus clock cycle. 14.3.7.1 Special Gated Timer Mode Considerations This section describes items that should be considered when using the special Gated Timer mode. Gated Timer mode is overridden if the clock source bit TCS is set to external clock source, TCS = 1. For Gated Timer operation, the internal clock source must be selected, TCS = 0. Type A and B timers using a clock prescale = N (other than 1:1) require 2 to 3 timer clock cycles, after the ON bit = 1, before the TMR count register increments. Refer to Section 14.3.12 “Timer Latency Considerations” for more information. Refer to the “Electrical Specifications” section in the device data sheet for details on the gate width pulse requirements. DS61105D-page 14-32 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.3.8 32-Bit Gated Timer Mode The gate operation starts on a rising edge of the signal applied to the TxCK pin. The TMRx count register increments while the external gate signal remains high. The gate operation terminates on the falling edge of the signal applied to the TxCK pin. The timer interrupt flag, TyIF, is set. Only Type B timers can operate in 32-bit Gated Timer mode. The timer clock source is the internal peripheral bus clock, PBCLK, and is selected by clearing the TCS control bit = 0, (TxCON<1>). Type B timers automatically provide synchronization to the peripheral bus clock. In 32-bit Gated Timer mode, the input clock is gated by the signal applied to the TxCK pin. The Gated Timer mode is enabled by setting the TGATE control bit (TxCON<7>) = 1. The gate operation starts on a rising edge of the signal applied to the TxCK pin and the TMRxy count register increments while the external gate signal remains high. Type B timers using a 1:1 clock prescale operate at a timer clock rate the same as the PBCLK and increment the TMRxy count register on every rising timer clock edge. The timer continues to increment until the TMRxy count register matches the PRxy period register value. The TMRxy count register then resets to 00000000h on the next timer clock cycle, then continues to increment and repeat the period match until the falling edge of the gate signal or the timer is disabled. The timer does not generate an interrupt when a timer period match occurs. Type B timers using a clock prescale = N (other than 1:1) operate at a timer clock rate (PBCLK/N) and the TMRxy count register increments on every Nth timer clock rising edge. For example, if the clock prescale is 1:8, then the timer increments on every 8th timer clock cycle. The timer continues to increment until the TMRxy count register matches the PRxy period register value. The TMRxy count register then resets to 00000000h after N more timer clock cycles, then continues to increment and repeat the period match until the falling edge of the gate signal or the timer is disabled. The timer does not generate an interrupt when a timer period match occurs. On the falling edge of the gate signal, the count operations terminate, a timer event is generated, and the interrupt flag bit TyIF is set 1 PBCLK + 2 SYSCLK system clock cycles after the falling edge of the signal on the gate pin. The TMR count register is not reset to 00000000h. The user must reset the TMRxy count register if it is desired to start from zero on the next rising edge gate input. The resolution of the timer count is directly related to the timer clock period. When the timer prescaler is 1:1, the timer clock period is 1 PBCLK peripheral bus clock cycle. For a timer prescaler of 1:8, the timer clock period is 8 times the peripheral bus clock cycle. 14.3.8.1 32-Bit Gated Timer Mode Considerations This section describes items that should be considered when using the 32-bit Gated Timer mode. Gated Timer mode is overridden if the clock source bit TCS is set to external clock source, TCS = 1. For Gated Timer operation, the internal clock source must be selected, TCS = 0. Refer to the “Electrical Specifications” section in the device data sheet for details on the gate width pulse requirements. 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-33 PIC32MX Family Reference Manual 14.3.8.2 16-Bit Gated Timer Initialization Steps Perform the following steps to configure the timer for 16-bit Gated Timer mode: 1. Clear control bit ON (TxCON<15> = 0) to disable timer. 2. Set control bits TCS (TxCON<1> = 0) to select internal PBCLK source. 3. Set control bit TGATE (T1CON<7> = 1) to enable gated Timer mode. 4. Select desired prescaler. 5. Clear timer register TMRx. 6. Load period register PRx with desired 16-bit match value. 7. If interrupts are used: i. Clear interrupt flag bit TxIF in IFS0 register. ii. Configure interrupt priority and subpriority levels in IPCn register. iii. Set Interrupt enable bit TxIE in IEC0 registers. 8. Set control bit ON (TxCON<15> = 1) to enable the timer. Example 14-5: 16-Bit Gated Timer Example Code T4CON = 0x0; T4CON = 0x00E0; TMR4 = 0; PR4 = 0xFFFF; T4CONSET = 0x8000; // Stop Timer and clear control register // Gated timer mode, prescaler at 1:64, internal clock source // Clear timer register // Load period register with 16-bit match value // Start Timer 14.3.8.3 32-Bit Gated Timer Initialization Steps Perform the following steps to configure the timer for 32-bit Gated Timer Accumulation mode: 1. Clear control bit ON (TxCON<15> = 0) to disable Timer. 2. Clear control bit TCS (TxCON<1>) = 0 to select internal PBCLK source. 3. Set control bit T32 (TxCON<3>= 1) = 1 to enable 32-bit operations. 4. Set control bit TGATE (TxCON<7> = 1) to enable gated Timer mode. 5. Select desired clock prescale. 6. Load/Clear timer register TMRx. 7. Load period register PRx with desired 32-bit match value. 8. If interrupts are used: i. Clear interrupt flag bit TyIF in IFSn register. ii. Configure interrupt priority and subpriority levels in IPCn register. iii. Set interrupt enable bit TyIE in IECn registers. Set control bit ON (TxCON<15> = 1) to enable the timer. Example 14-6: 32-Bit Gated Timer Example Code T2CON = 0x0; T3CON = 0x0; T2CONSET = 0x00C8; TMR2 = 0x0; // Stops any 16/32-bit Timer2 operation // Stops any 16-bit Timer3 operation // 32-bit mode, gate enable, internal clock, // 1:16 prescale // Clear contents of the TMR2 and TMR3 PR2 = 0xFFFFFFFF; // Load PR2 and PR3 registers with 32-bit match value T2CONSET = 0x8000; // Start 32-bit timer DS61105D-page 14-34 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.3.9 Asynchronous Clock Counter Mode (Type A Timer Only) The Asynchronous Timer operation provides the following capabilities: • The timer can operate during SLEEP mode and can generate an interrupt on period register match that will wake-up the processor from SLEEP or IDLE mode. • The timer can be clocked from the Secondary Oscillator for real-time clock applications. The Type A timer has the ability to operate in an Asynchronous Counting mode, using an external clock source connected to the T1CK pin, and is selected by setting the clock source control bit TCS (TxCON<1>) = 1. This requires the external clock synchronization be disabled, bit TSYNC (T1CON<2>) = 0. It is also possible to utilize the Secondary Oscillator with a 32 kHz crystal connected to SOSCI/SOSCO pins as an asynchronous clock source. Refer to Section 14.3.13 “Secondary Oscillator” for more information. Type A timer using a 1:1 clock prescale operates at the same clock rate as the applied external clock rate, and increments the TMR count register on every rising timer clock edge. The timer continues to increment until the TMR count register matches the PR period register value. The TMR count register resets to 0000h on the next timer clock cycle, then continues to increment and repeat the period match until the timer is disabled. If the PR period register value = 0000h, the TMR count register resets to 0000h on the next timer clock cycle, but will not continue to increment. Type A timers generate a timer event when the TMR count register matches the PR period register value. The timer interrupt flag bit, TxIF is set within 1 PBCLK + 2 SYSCLK system clock cycles of this event. If the timer interrupt enable bit is set, TxIE = 1, an interrupt is generated. 14.3.9.1 Asynchronous Mode TMR1 Read and Write Operations Due to the asynchronous nature of Timer1 operating in this mode, reading and writing to the TMR1 count register requires synchronization between the asynchronous clock source and the internal PBCLK peripheral bus clock. Timer1 features a TWDIS (Timer Write Disable) control bit (T1CON<12>) and a TWIP (TImer Write in Progress) Status bit (T1CON<11>) to provide the user with 2 options for safely writing to the TMR1 count register while Timer1 is enabled. These bits have no affect in Synchronous Clock Counter modes. Option 1 is the legacy Timer1 Write mode, TWDIS bit = 0. To determine when it is safe to write to the TMR1 count register, it is recommended to poll the TWIP bit. When TWIP = 0, it is safe to perform the next write operation to the TMR1 count register. When TWIP = 1, the previous Write operation to the TMR1 count register is still being synchronized and any additional write operations should wait until TWIP = 0. Option 2 is the new synchronized Timer1 Write mode, TWDIS bit = 1. A write to the TMR1 count register can be performed at any time. However, if the previous write operation to the TMR1 count register is still being synchronized, any additional write operations are ignored. When performing a write to the TMR1 count register, 2 to 3 asynchronous external clock cycles are required for the value to be synchronized into the register. When performing a read from the TMR1 count register, synchronization requires 2 PBCLK cycle delays between the current unsynchronized value in the TMR1 count register and the synchronized value returned by the read operation. In other words, the value read is always 2 PBCLK cycles behind the actual value in the TMR1 count register. Timers 14 14.3.9.2 Asynchronous Clock Counter Considerations This section describes items that should be considered when using the Asynchronous Clock Counter. Regardless of the clock prescale, Type A timers require 2 to 3 timer clock cycles, after the ON bit = 1 before the TMR count register increments. Refer to Section 14.3.12 “Timer Latency Considerations” for more information. The external input clock must meet certain minimum high time and low time requirements when used in the Asynchronous Counter mode. Refer to the device data sheet “Electrical Specifications” section for further details. © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-35 PIC32MX Family Reference Manual 14.3.9.3 Asynchronous External Clock Counter Initialization Steps Perform the following steps to configure the Timer for 16-bit Asynchronous Counter mode. 1. Clear control bit ON (T1CON<15> = 0) to disable timer. 2. Set control bit TCS (T1CON<1> = 1) to enable external clock source. 3. Clear control bit TSYNC (T1CON<2> = 0) to disable clock synchronization. 4. Select desired prescaler. 5. Load/Clear timer register TMR1. 6. If using period match: i. Load period register PR1 with desired 16-bit match value. 7. If interrupts are used: i. Clear interrupt flag bit T1IF in IFS0 register. ii. Configure interrupt priority and subpriority levels in IPCn register. iii. Set interrupt enable bit T1IE in IEC0 registers. 8. Set control bit ON (T1CON<15> = 1) to enable the timer. Example 14-7: Example Code: 16-Bit Asynchronous Counter Mode /* 16-bit asynchronous counter mode example */ T1CON = 0x0; // Stops the Timer1 and reset control reg. T1CON = 0x0042; // Set prescaler 1:16, external clock, asynch mode TMR1 = 0x0; PR1 = 0x7FFF; T1CONSET = 0x8000; // Clear timer register // Load period register // Start Timer DS61105D-page 14-36 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.3.10 Timer Prescalers Type A timers provide input clock (peripheral bus clock or external clock) prescale options of 1:1, 1:8, 1:64 and 1:256 selected using TCKPS<1:0> (TxCON<5:4>). Type B timers provide input clock (peripheral bus clock or external clock) prescale options of 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64 and 1:256 selected using TCKPS<2:0> (TxCON<6:4>). The prescaler counter is cleared when any of the following occurs: • A write to the TMRx register • Disabling the timer, ON (TxCON<15>) = 0 • Any device Reset, except Power-on Reset 14.3.11 Writing to TxCON, TMR, and PR Registers A timer module is disabled and powered off when the ON bit (TxCON<15>) = 0, thus providing maximum power savings. To prevent unpredictable timer behavior, it is recommended that the timer be disabled, ON bit = 0, before writing to any of the TxCON register bits or timer prescaler. Attempting to set ON bit = 1 and write to any TxCON register bits in the same instruction may cause erroneous timer operation. The PRx period register can be written to while the module is operating. However, to prevent unintended period matches, writing to the PRx period register while the timer is enabled, (ON bit = 1)is not recommended. The TMRx count register can be written to while the module is operating. The user should be aware of the following when byte writes are performed: • If the timer is incrementing and the low byte of the timer is written to, the upper byte of the timer is not affected. If 0xFF is written into the low byte of the timer, the next timer count clock after this write will cause the low byte to rollover to 0x00 and generate a carry into the high byte of the timer. • If the timer is incrementing and the high byte of the timer is written to, the low byte of the timer is not affected. If the low byte of the timer contains 0xFF when the write occurs, the next timer count clock will generate a carry from the timer low byte and this carry will cause the upper byte of the timer to increment. Additionally, TMR1 count register can be written to while the module is operating. However, see Section 14.3.9.1 “Reading and Writing TMR1 register” regarding asynchronous clock operations. When the TMRx register is written to (a word, half word, or byte) via an instruction, the TMRx register increment is masked and does not occur during that instruction cycle. A TMR count register is not reset to zero when the module is disabled. 14 Timers 14.3.12 Timer Latency Considerations This section describes items that should be considered regarding timer latency. Since both Type A and Type B timers can use the Internal Peripheral Bus Clock (PBCLK) or an external clock (Type A also supports asynchronous clock), there are considerations regarding latencies of operations performed on the timer. These latencies represent the time delay between the moment an operation is executed (read or write) and the moment its first effect begins, as shown in Table 14-3 and Table 14-4. For Type A and Type B timers, reading and writing the TxCON, TMRx, and PRx registers in any Synchronized Clock mode does not require synchronization of data between the main SYSCLK clock domain and the timer module clock domain. Therefore, the operation is immediate. However, when operating Timer1 in Asynchronous Clock mode, reading the TMR1 count register requires 2 PBCLK cycles for synchronization, while writing to theTMR1 count register requires 2 to 3 timer clock cycles for synchronization. © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-37 PIC32MX Family Reference Manual For example, Timer1 is using an asynchronous clock source and a read operation of TMR1 register is executed. There are 2 PBCLK peripheral bus clocks required to synchronize this data to the TMR1 count register. The effect is a value which is always 2 PBCLK cycles behind the actual TMR1 count. Additionally, any timer using an external clock source requires 2-3 external clock cycles, after the ON bit (TxCON<15>) has been set (= 1), before the timer starts incrementing. The interrupt flag latency represents the time delay between the timer event and the moment the timer interrupt flag is active. Table 14-3: Type A Timer Latencies Operation PBCLK Internal clock Synchronous External clock Asynchronous External clock Set ON = 1 (enable timer) 0 PBCLK 2-3 TMRCLKCY 2-3 TMRCLKCY Set ON = 0 (disable timer) 0 PBCLK 2-3 TMRCLKCY 2-3 TMRCLKCY Read PRx 0 PBCLK 0 PBCLK 0 PBCLK Write PRx 0 PBCLK 0 PBCLK 0 PBCLK Read TMRx 0 PBCLK 0 PBCLK 2 PBCLK Write TMRx Interrupt Flag INTF = 1 0 PBCLK 1 PBCLK + 2 to 3 SYSCLK 0 PBCLK 1 PBCLK + 2 to 3 SYSCLK 2-3 TMRCLKCY (TMRCLKCY / 2) + 2 to 3 SYSCLK Note: TMRCLKCY = External synchronous or asynchronous timer clock cycles. Table 14-4: Type B Timer Latencies Operation PBCLK Internal clock Set ON = 1 (enable timer) 0 PBCLK Set ON = 0 (disable timer) Read PRx 0 PBCLK 0 PBCLK Write PRx Read TMRx Write TMRx 0 PBCLK 0 PBCLK 0 PBCLK Interrupt Flag INTF = 1 1 PBCLK + 2 to 3 SYSCLKs Synchronous External clock 0 PBCLK 0 PBCLK 0 PBCLK 0 PBCLK 0 PBCLK 0 PBCLK 1 PBCLK + 2 to 3 SYSCLKs DS61105D-page 14-38 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.3.13 Secondary Oscillator In each device variant, the secondary oscillator is available to the Type A timer module for Real-Time Clock (RTC) applications. • The secondary oscillator becomes the clock source for the timer when the secondary oscillator is enabled and the timer is configured to use the external clock source. • The secondary oscillator is enabled when the Configuration Fuse bit FSOSCEN (DEVCFG1<5>) = 0 and by setting the SOSCEN control bit (OSCCON<1>). Refer to Section 6. “Oscillators” for further details. 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-39 PIC32MX Family Reference Manual 14.4 INTERRUPTS A timer has the ability to generate an interrupt on a period match or falling edge of the external gate signal, depending on the operating mode. The TxIF bit (TyIF bit in 32-bit mode) is set when one of the following conditions is true: • When the timer count matches the respective period register and the timer module is not operating in Gated Time Accumulation mode. • When the falling edge of the gate signal is detected when the timer is operating in Gated Time Accumulation mode. The TxIF bit (TyIF bit in 32-bit mode) must be cleared in software. A timer is enabled as a source of interrupt via the respective timer interrupt enable bit, TxIE (TyIE for 32-bit mode). The interrupt priority level bits TxIP<2:0> (TyIP<2:0> for 32-bit mode) and interrupt subpriority level bits TxIS<1:0> (TyIS<1:0> for 32-bit mode) also must be configured. Refer to Section 8. “Interrupts” in this manual for further details. Note: A special case occurs when the period register is loaded with ‘0’ and the timer is enabled. No timer interrupts will be generated for this configuration. 14.4.1 Interrupt Configuration Each Time Base module has a dedicated interrupt flag bit TxIF and a corresponding interrupt enable/mask bit TxIE. These bits determine the source of an interrupt, and enable or disable an individual interrupt source. Each Timer module can have its own priority level independent of other Timer modules. The TxIF is set when the timer count matches the respective period register and the timer module is not operating in Gated Time Accumulation mode, or when the falling edge of the gate signal is detected when the timer is operating in Gated Time Accumulation mode. The TxIF bit is set without regard to the state of the corresponding TxIE bit. The TxIF bit can be polled by software if desired. The TxIE bit is used to define the behavior of the Interrupt Controller when a corresponding TxIF is set. When the TxIE bit is clear, the Interrupt Controller does not generate a CPU interrupt for the event. If the TxIE bit is set, the Interrupt Controller will generate an interrupt to the CPU when the corresponding TxIF bit is set (subject to the priority and subpriority as outlined below). It is the responsibility of the user’s software routine that services a particular interrupt to clear the appropriate Interrupt Flag bit before the service routine is complete. The priority of each timer module can be set independently with the TxIP<2:0> bits. This priority defines the priority group to which the interrupt source will be assigned. The priority groups range from a value of 7 (the highest priority) to a value of 0 (which does not generate an interrupt). An interrupt being serviced will be preempted by an interrupt in a higher priority group. The subpriority bits allow setting the priority of a interrupt source within a priority group. The values of the subpriority, TxIS<1:0>, range from 3 (the highest priority), to 0 (the lowest priority). An interrupt with the same priority group, but having a higher subpriority value, will preempt a lower subpriority interrupt that is in progress. The priority group and subpriority bits allow more than one interrupt source to share the same priority and subpriority. If simultaneous interrupts occur in this configuration, the natural order of the interrupt sources within a priority/subgroup pair determines the interrupt generated. The natural priority is based on the vector numbers of the interrupt sources. The lower the vector number, the higher the natural priority of the interrupt. Any interrupts that were overridden by natural order will then generate their respective interrupts based on priority, subpriority, and natural order after the interrupt flag for the current interrupt is cleared. After an enabled interrupt is generated, the CPU will jump to the vector assigned to that interrupt. The vector number for the interrupt is the same as the natural order number. The CPU will then begin executing code at the vector address. The user’s code at this vector address should perform any application specific operations and clear the TxIF interrupt flag, and then exit. Refer to Section 8. “Interrupts” for the vector address table details for more information on interrupts. DS61105D-page 14-40 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers Table 14-5: Timer Interrupt Vectors for Various Offsets with EBASE = 0x8000:0000 Interrupt Vector/Natural Order IRQ Number Vector Address IntCtl.VS = 0x01 Vector Address IntCtl.VS = 0x02 Vector Address IntCtl.VS = 0x04 Vector Address IntCtl.VS = 0x08 Timer1 4 Timer2 8 Timer3 12 4 8000_0280 8000 0300 8000_0400 8000_0600 8 8000_0300 8000_0400 8000_0600 8000_0A00 12 8000_0380 8000_0500 8000_0800 8000_0E00 Timer4 16 Timer5 20 16 8000_0400 8000_0600 8000_0A00 8000 1200 20 8000_0480 8000_0700 8000_0C00 8000 1600 Vector Address IntCtl.VS = 0x10 8000 0A00 8000 1200 8000 1A00 8000 2200 8000 2A00 Table 14-6: Example of Priority and Subpriority Assignment Interrupt Priority Group Subpriority Timer1 7 3 Timer2 7 3 Timer3 7 2 Timer4 6 1 Timer5 0 3 Vector/Natural Order 4 8 12 16 20 Example 14-8: 16-Bit Timer Interrupt Initialization Code Example /* The following code example will enable Timer2 interrupts, load the Timer2 Period register and start the Timer. When a Timer2 period match interrupt occurs, the interrupt service routine must clear the Timer2 interrupt status flag in software. */ T2CON = 0x0; // Stop Timer and clear control register, // prescaler at 1:1,internal clock source TMR2 = 0x0; PR2 = 0xFFFF; // Clear timer register // Load period register IPC2SET = 0x0000000C; IPC2SET = 0x00000001; // Set priority level=3 // Set sub-priority level=1 // Could have also done this in single // operation by assigning IPC2SET = 0x0000000D IFS0CLR = 0x00000100; // Clear Timer interrupt status flag IEC0SET = 0x00000100; // Enable Timer interrupts T2CONSET = 0x8000; // Start Timer Timers 14 © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-41 PIC32MX Family Reference Manual Example 14-9: Timer ISR Code Example /* The following code example demonstrates a simple interrupt service routine for Timer interrupts. The user’s code at this ISR handler should perform any application specific operations and must clear the corresponding Timer interrupt status flag before exiting. */ void __ISR(_Timer_1_Vector,ipl3)Timer1Handler(void) { ... perform application specific operations in response to the interrupt IFS0CLR = 0x00000010; // Be sure to clear the Timer 2 interrupt status } Note: The Timer ISR code example shows MPLAB® C32 C-compiler specific syntax. Refer to your compiler manual regarding support for ISRs. Example 14-10: 32-bit Timer Interrupt Initialization Code Example /* The following code example will enable Timer5 interrupts, load the Timer4:Timer5 Period Register pair and start the 32-bit timer module. When a 32-bit period match interrupt occurs, the user must clear the Timer5 interrupt status flag in software. */ T4CON = 0x0; T5CON = 0x0; T4CONSET = 0x0038; // Stop 16-bit Timer4 and clear control register // Stop 16-bit Timer5 and clear control register // Enable 32-bit mode, prescaler at 1:8, // internal clock source TMR4 = 0x0; // Clear contents of the TMR4 and TMR5 PR4 = 0xFFFFFFFF; // Load PR4 and PR5 registers with 32-bit value IPC5SET = 0x00000004; IPC5SET = 0x00000001; // Set priority level=1 and // Set sub-priority level=1 // Could have also done this in single // operation by assigning IPC5SET = 0x00000005 IFS0CLR = 0x00100000; // Clear the Timer5 interrupt status flag IEC0SET = 0x00100000; // Enable Timer5 interrupts T4CONSET = 0x8000; // Start Timer DS61105D-page 14-42 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.5 OPERATION IN POWER-SAVING AND DEBUG MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 14.5.1 Timer Operation in SLEEP Mode As the device enters SLEEP mode, the system clock SYSCLK and peripheral bus clock PBCLK are disabled. For both timer types (A and B) operating in Synchronous mode, the timer module stops operating. Type A timer module is different from the Type B timer module because it can operate asynchronously from an external clock source. Because of this distinction, the Type A timer module can continue to operate during SLEEP mode. To operate in SLEEP mode, Type A timer module must be configured as follows: • Timer1 module is enabled, ON (T1CON<15> = 1) and • Timer1 clock source is selected as external, TCS (T1CON<1> = 1) and • TSYNC bit (T1CON<2>) is set to logic ‘0’ (Asynchronous Counter mode enabled). When all of the preceding conditions are met, Timer1 continues to count and detect period matches when the device is in SLEEP mode. When a match between the timer and the period register occurs, the T1IF Status bit is set. If the T1IE bit is set, and its priority is greater than current CPU priority, the device wakes from SLEEP or IDLE mode and executes the Timer1 Interrupt Service Routine. If the assigned priority level of the Timer1 interrupt is less than, or equal to, the current CPU priority level, the CPU is not awakened and the device enters IDLE mode. 14.5.2 Timer Operation in IDLE Mode When the device enters IDLE mode, the system clock sources remain functional and the CPU stops executing code. The timer modules can optionally continue to operate in IDLE mode. The SIDL bit (TxCON<13>) selects whether the timer module stops in IDLE mode, or continues to operate normally. If TSIDL = 0, the module continues operation in IDLE mode. If SIDL = 1, the module stops in IDLE mode. 14 14.5.3 Timer Operation in DEBUG Mode Timers The FRZ bit (TxCON<14>) determines whether the timer module will run or stop while the CPU is executing debug exception code (i.e., the application is halted) in DEBUG mode. When FRZ = 0, the timer module continues to run, even when application is halted in DEBUG mode. When FRZ = 1 and the application is halted in DEBUG mode, the module freezes its operations and makes no changes to the state of the timer module. The module will resume its operation after the CPU resumes execution. Note: The FRZ bit is readable and writable only when the CPU is executing in DEBUG mode. In all other modes, FRZ reads as ‘0’. If the FRZ bit is changed during DEBUG mode, the new value does not take effect until the current DEBUG mode is exited and reentered. During DEBUG mode, FRZ reads the last written value, which may or may not be in effect (depending on when the last value was written). © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-43 PIC32MX Family Reference Manual 14.6 EFFECTS OF VARIOUS RESETS 14.6.1 Device Reset All timer registers are forced to their reset states upon a device Reset. 14.6.2 Power-on Reset All timer registers are forced to their reset states upon a Power-on Reset. 14.6.3 Watchdog Reset All timer registers are forced to their reset states on a Watchdog Reset. DS61105D-page 14-44 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.7 PERIPHERALS USING TIMER MODULES 14.7.1 Time Base for Input Capture/Output Compare The Input Capture and Output Compare peripherals can select one of two timer modules or a combined 32-bit timer as their timer source. Refer to the device data sheet, and to Section 15. “Input Capture” and Section 16. “Output Compare” in this manual for details. 14.7.2 A/D Special Event Trigger On each device variant, a Type B Timer3 or Timer5 has the capability to generate a special A/D conversion trigger signal on a period match in both 16-bit and 32-bit modes. The timer module provides a conversion Start signal to the A/D sampling logic. • If T32 = 0 when a match occurs between the 16-bit timer register (TMRx) and the respective 16-bit period register (PRx), the A/D Special Event Trigger signal is generated. • If T32 = 1 when a match occurs between the 32-bit timer (TMRx:TMRy) and the 32-bit respective combined period register (PRx:PRy), a A/D Special Event Trigger signal is generated. The Special Event Trigger signal is always generated by the timer. The trigger source must be selected in the A/D converter control registers. Refer to the device data sheet, and to Section 17. “10-Bit A/D Converter” in this manual for additional information. 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-45 PIC32MX Family Reference Manual 14.8 I/O PIN CONTROL Enabling the timer module does not configure the I/O pin direction. When a timer module is enabled and configured for external clock or gate operation, the user must ensure the I/O pin direction is configured as an input by setting the corresponding TRIS control register bit = 1. On PIC32MX devices, the TxCK pins become the gate inputs when Gated Timer mode is selected, TGATE bit (TxCON<7>) = 1, and internal peripheral bus clock source PBCLK, TCS bit (TxCON<1>) = 0, are selected. The TxCK pins can be external clock inputs for other modes when the external clock source TCS (TxCON<1>) = 1 is selected. If not used as a gate or external clock input, these pins can be general purpose I/O pins. 14.8.1 I/O Pin Resources A summary of timer/counter modes, and the specific I/O pins required for each mode is provided in Table 14-7. The table illustrates which I/O pin is required for a certain mode of operation. Refer to Table 14-8 to configure the I/O pins. Table 14-7: Required I/O Pin Resources 16/32-Bit Timer Modes 16/32-Bit Counter Modes I/O Pin Name Internal Clock Source(1) External Clock Source Gate For Internal Clock Source T1CK No Yes Yes T2CK No Yes Yes T3CK No Yes Yes T4CK No Yes Yes T5CK No Yes Yes Note 1: “No” indicates the pin is not required and can be used as a general purpose I/O pin. External Clock Source Yes Yes Yes Yes Yes 14.8.2 I/O Pin Configuration Table 14-8 provides a summary of I/O pin resources associated with the timer modules. The table also shows the settings required to make each I/O pin work with a specific timer module. Table 14-8: I/O Pin Configuration for Use with Timer Modules Required Settings for Module Pin Control I/O Pin Name Required(1) Module Control Bit Field TRIS Pin Type Buffer Type Description T1CK No ON TCS,TGATE Input I ST Timer 1 External Clock/Gate Input T2CK No ON TCS,TGATE Input I ST Timer 2 External Clock/Gate Input T3CK No ON TCS,TGATE Input I ST Timer 3 External Clock/Gate Input T4CK No ON TCS,TGATE Input I ST Timer 4 External Clock/Gate Input T5CK No ON TCS,TGATE Input I ST Timer 5 External Clock/Gate Input Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output Note 1: These pins are only required for modes that use gated timer or external clock inputs. Otherwise, these pins can be used for general purpose I/O and require the user to set the corresponding TRIS control register bits. DS61105D-page 14-46 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.9 FREQUENTLY ASKED QUESTIONS Question 1: Can the lower half of the 32-bit timer generate an interrupt? Answer: No. When two 16-bit timers are combined in 32-bit mode (TxCON = 1), the interrupt enable bit TxIE, interrupt flag bit TxIF, interrupt priority bit TxIP, and interrupt subpriority bit TxIS associated with the upper timer module are used. The interrupt functions of the lower timer module are disabled. Question 2: If I do not use the TxCK input for my timer mode, is this I/O pin available as a general purpose I/O pin? Answer: Yes. If the timer module is configured to use an internal clock source (TxCON) and not use the Gated Timer mode (TxCON = 0), then the associated I/O pin is available for general purpose I/O. Note, though, that when the I/O pin is used as a general purpose I/O pin, the user is responsible for configuring the respective TRIS register to input or output. 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-47 PIC32MX Family Reference Manual 14.10 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Timers module are: Title Application Note # No related application notes at this time. N/A Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. DS61105D-page 14-48 Preliminary © 2008 Microchip Technology Inc. Section 14. Timers 14.11 REVISION HISTORY Revision A (August 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x; Revised Table 14-2; Revised Register 14-1; Revised Section 14.3.9.1 Revision D (May 2008) Added note to Registers 14-17, 14-18, 14-19, 14-20, 14-21, 14-22, 14-23; Revised Tables 14-1, 14-5; Revised Examples 14-9, 14-10; Revised Section 14.3.9.1 Title; Revised Section 14.3.11; Change Reserved bits from “Maintain as” to “Write”; Added Note to ON bit (T1CON, TxCON Registers). 14 Timers © 2008 Microchip Technology Inc. Preliminary DS61105D-page 14-49 PIC32MX Family Reference Manual NOTES: DS61105D-page 14-50 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture HIGHLIGHTS This section of the manual contains the following topics: 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 15.12 15.13 Introduction.............................................................................................................. 15-2 Input Capture Registers........................................................................................... 15-3 Timer Selection...................................................................................................... 15-15 Input Capture Enable............................................................................................. 15-15 Input Capture Event Modes................................................................................... 15-16 Capture Buffer Operation....................................................................................... 15-21 Input Capture Interrupts......................................................................................... 15-22 Operation in Power-Saving Modes........................................................................ 15-24 Input Capture Operation in DEBUG Mode ............................................................ 15-24 I/O Pin Control ....................................................................................................... 15-25 Design Tips ............................................................................................................ 15-25 Related Application Notes ..................................................................................... 15-26 Revision History..................................................................................................... 15-27 Input Capture 15 © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-1 PIC32MX Family Reference Manual 15.1 INTRODUCTION This section describes the Input Capture module and its associated Operational modes. The Input Capture module is used to capture a timer value from one of two selectable time bases on the occurrence of an event on an input pin. The Input Capture features are useful in applications requiring frequency (Time Period) and pulse measurement. Figure 15-1 depicts a simplified block diagram of the Input Capture module. Refer to the specific device data sheet for information on the number of channels available in a particular device. All Input Capture channels are functionally identical. In this section, an ‘x’ in the pin name or register name denotes the specific Input Capture channel. Timer Y and Timer Z each refer to one of two timer inputs which may be associated with the Input Capture channel. The Input Capture module has multiple operating modes, which are selected via the ICxCON register. The operating modes include the following: • Capture timer value on every falling edge of input applied at the ICx pin • Capture timer value on every rising edge of input applied at the ICx pin • Capture timer value on every fourth rising edge of input applied at the ICx pin • Capture timer value on every 16th rising edge of input applied at the ICx pin • Capture timer value on every rising and falling edge of input applied at the ICx pin • Capture timer value on the specified edge and every edge thereafter The Input Capture module has a four-level FIFO buffer. The number of capture events required to generate a CPU interrupt can be selected by the user. An Input Capture Channel can also be configured to generate a CPU interrupt on a rising edge of the capture input when the device is in SLEEP or IDLE mode. Figure 15-1: Input Capture Module Block Diagram ICx Input Timer3 Timer2 Prescaler 1, 4, 16 Edge Detect ICTMR ICC32 FIFO Control 0 1 ICxBUF<31:16> ICxBUF<15:0> ICM<2:0> ICM<2:0> ICFEDGE ICxCON ICBNE ICOV ICI<1:0> Interrupt Event Generation Data Space Interface Interrupt Peripheral Data Bus DS61122D-page 15-2 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture 15.2 INPUT CAPTURE REGISTERS Note: Each PIC32MX device variant may have one or more Input Capture modules. An ‘x’ used in the names of pins, control/Status bits and registers denotes the particular module. Refer to the specific device data sheets for more details. Each capture module available on the PIC32MX devices has the following Special Function Registers (SFRs), where ‘x’ denotes the module number: • ICxCON: Input Capture Control Register ICxCONCLR, ICxCONSET, ICxCONINV: Atomic Bit Manipulation Write-only Registers for ICxCON • ICxBUF: Input Capture Buffer Register Each Input capture module also has the following associated bits for interrupt control: • Interrupt Enable Control bit (ICxIE) • Interrupt Flag Status bit (ICxIF) • Interrupt Priority Control bits (ICxIP) • Interrupt Subpriority Control bits (ICxIS) The tables below provide a brief summary of all the Input Capture related registers, and is followed by a detailed description of each register. Table 15-1: Input Capture SFR Summary Name Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 ICxCON 31:24 23:16 15:8 7:0 ICxCONCLR 31:0 ICxCONSET 31:0 ICxCONINV 31:0 ICxBUF 31:24 23:16 15:8 7:0 IFS0 31:24 23:16 15:8 7:0 IEC0 31:24 23:16 15:8 7:0 IPC1 31:24 23:16 15:8 7:0 IPC2 31:24 23:16 15:8 7:0 — — ON ICTMR I2C1MIF SPI1EIF INT3IF INT1IF I2C1MIE SPI1EIE INT3IE INT1IE — — — — — — — — — — — — — — — — — — — — — — FRZ SIDL — — — ICFEDGE ICC32 ICI<1:0> ICOV ICBNE ICM<2:0> Write clears selected bits in ICxCON, read yields undefined value Write sets selected bits in ICxCON, read yields undefined value Write inverts selected bits in ICxCON, read yields undefined value ICxBUF<31:24> ICxBUF<23:16> ICxBUF<15:8> ICxBUF<7:0> I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF SPI1TXIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE — — INT1IP<2:0> INT1IS<1:0> — — OC1IP<2:0> OC1IS<1:0> — — IC1IP<2:0> IC1IS<1:0> — — T1IP<2:0> T1IS<1:0> — — INT2IP<2:0> INT2IS<1:0> — — OC2IP<2:0> OC2IS<1:0> — — IC2IP<2:0> IC2IS<1:0> — — T2IP<2:0> T2IS<1:0> 15 Input Capture © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-3 PIC32MX Family Reference Manual Table 15-1: Input Capture SFR Summary (Continued) Name Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 IPC3 31:24 — — — INT3IP<2:0> 23:16 — — — 15:8 — — — 7:0 — — — OC3IP<2:0> IC3IP<2:0> T3IP<2:0> IPC4 31:24 — — — 23:16 — — — 15:8 — — — INT4IP<2:0> OC4IP<2:0> IC4IP<2:0> 7:0 — — — IPC5 31:24 — — — 23:16 — — — 15:8 — — — 7:0 — — — T4IP<2:0> SPI1IP<2:0> OC5IP<2:0> IC5IP<2:0> T5IP<2:0> Bit Bit 25/17/9/1 24/16/8/0 INT3IS<1:0> OC3IS<1:0> IC3IS<1:0> T3IS<1:0> INT4IS<1:0> OC4IS<1:0> IC4IS<1:0> T4IS<1:0> SPI1IS<1:0> OC5IS<1:0> IC5IS<1:0> T5IS<1:0> DS61122D-page 15-4 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture Register 15-1: ICXCON: Input Capture X Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 r-x r-x r-x R/W-0 R/W-0 ON FRZ SIDL — — — ICFEDGE ICC32 bit 15 bit 8 R/W-0 ICTMR bit 7 R/W-0 R/W-0 ICI<1:0> R-0 ICOV R-0 ICBNE R/W-0 R/W-0 ICM<2:0> R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7 bit 6-5 Reserved: Write ‘0’; ignore read ON: ON bit 1 = Module enabled 0 = Disable and reset module, disable clocks, disable interrupt generation, and allow SFR modifications Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. FRZ: Freeze in DEBUG Mode Control bit 1 = Freeze module operation when in DEBUG mode 0 = Do not freeze module operation when in DEBUG mode Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode. SIDL: Stop in IDLE Control bit 1 = Halt in CPU IDLE mode 0 = Continue to operate in CPU IDLE mode Unimplemented: Read as ‘0’ ICFEDGE: First Capture Edge Select bit (only used in mode 6, ICxM = 110) 1 = Capture rising edge first 0 = Capture falling edge first ICC32: 32-Bit Capture Select bit 1 = 32-Bit timer resource capture 0 = 16-Bit timer resource capture ICTMR: Timer Select bit (Does not affect timer selection when ICxC32 (ICxCON<8>) is ‘1’) 0 = Timer3 is the counter source for capture 1 = Timer2 is the counter source for capture ICI<1:0>: Interrupt Control bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event 15 © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-5 Input Capture PIC32MX Family Reference Manual Register 15-1: ICXCON: Input Capture X Control Register (Continued) bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (Read Only) 1 = Input capture buffer is not empty; at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture Mode Select bits 111 = Interrupt Only mode 110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode – every 16th rising edge 100 = Prescaled Capture Event mode – every 4th rising edge 011 = Simple Capture Event mode – every rising edge 010 = Simple Capture Event mode – every falling edge 001 = Edge Detect mode – every edge (rising and falling) 000 = Capture Disable mode DS61122D-page 15-6 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture Register 15-2: ICXBUF: Input Capture X Buffer Register R-0 R-0 R-0 R-0 R-0 R-0 ICxBUF<31:24> bit 31 R-0 bit 23 R-0 R-0 R-0 R-0 R-0 ICxBUF<23:16> R-0 bit 15 R-0 R-0 R-0 R-0 R-0 ICxBUF<15:8> R-0 bit 7 R-0 R-0 R-0 R-0 R-0 ICxBUF<7:0> Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) bit 31-0 ICxBUF<31:0>: Buffer Register bits Value of the current captured input timer count R-0 R-0 bit 24 R-0 R-0 bit 16 R-0 R-0 bit 8 R-0 R-0 bit 0 r = Reserved bit Input Capture 15 © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-7 PIC32MX Family Reference Manual Register 15-3: R/W-0 I2C1SIF bit 31 IFS0: Interrupt Flag Status Register 0(1) R/W-0 R/W-0 R/W-0 I2C1BIF U1TXIF U1RXIF R/W-0 U1EIF R/W-0 SPI1RXIF R/W-0 SPI1TXIF R/W-0 SPI1EIF bit 24 R/W-0 CNIF bit 23 R/W-0 OC5IF R/W-0 IC5IF R/W-0 T5IF R/W-0 INT4IF R/W-0 OC4IF R/W-0 IC4IF R/W-0 T4IF bit 16 R/W-0 INT3IF bit 15 R/W-0 OC3IF R/W-0 IC3IF R/W-0 T3IF R/W-0 INT2IF R/W-0 OC2IF R/W-0 IC2IF R/W-0 T2IF bit 8 R/W-0 INT1IF bit 7 R/W-0 OC1IF R/W-0 IC1IF R/W-0 T1IF R/W-0 INT0IF R/W-0 CS1IF R/W-0 CS0IF R/W-0 CTIF bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 21 bit 17 bit 13 bit 9 bit 5 Note 1: IC5IF: Input Capture 5 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred IC4IF: Input Capture 4 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred IC3IF: Input Capture 3 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred IC2IF: Input Capture 2 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred IC1IF: Input Capture 1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Input Capture module. DS61122D-page 15-8 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture Register 15-4: I2C1SIE bit 31 IEC0: Interrupt Enable Control Register 0(1) I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE SPI1EIE bit 24 R/W-0 CNIE bit 23 R/W-0 OC5IE R/W-0 IC5IE R/W-0 T5IE R/W-0 INT4IE R/W-0 OC4IE R/W-0 IC4IE R/W-0 T4IE bit 16 R/W-0 INT3IE bit 15 R/W-0 OC3IE R/W-0 IC3IE R/W-0 T3IE R/W-0 INT2IE R/W-0 OC2IE R/W-0 IC2IE R/W-0 T2IE bit 8 R/W-0 INT1IE bit 7 R/W-0 OC1IE R/W-0 IC1IE R/W-0 T1IE R/W-0 INT0IE R/W-0 CS1IE R/W-0 CS0IE R/W-0 CTIE bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 21 bit 17 bit 13 bit 9 bit 5 Note 1: IC5IE: Input Capture 5 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled IC4IE: Input Capture 4 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled IC3IE: Input Capture 3 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled IC2IE: Input Capture 2 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled IC1IE: Input Capture 1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Input Capture module. 15 Input Capture © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-9 PIC32MX Family Reference Manual Register 15-5: r-x — bit 31 IPC1: Interrupt Priority Control Register 1(1) r-x r-x R/W-0 R/W-0 — — INT1IP<2:0> R/W-0 R/W-0 R/W-0 INT1IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC1IP<2:0> OC1IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC1IP<2:0> IC1IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1IP<2:0> T1IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 12-10 IC1IP<2:0>: Input Capture 1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 9-8 IC1IS<1:0>: Input Capture 1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Input Capture module. DS61122D-page 15-10 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture Register 15-6: r-x — bit 31 IPC2: Interrupt Priority Control Register 2(1) r-x r-x R/W-0 R/W-0 — — INT2IP<2:0> R/W-0 R/W-0 R/W-0 INT2IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC2IP<2:0> OC2IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC2IP<2:0> IC2IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T2IP<2:0> T2IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 12-10 IC2IP<2:0>: Input Capture 2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 9-8 IC2IS<1:0>: Input Capture 2 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Input Capture module. 15 Input Capture © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-11 PIC32MX Family Reference Manual Register 15-7: r-x — bit 31 IPC3: Interrupt Priority Control Register 3(1) r-x r-x R/W-0 R/W-0 — — INT3IP<2:0> R/W-0 R/W-0 R/W-0 INT3IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC3IP<2:0> OC3IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC3IP<2:0> IC3IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T3IP<2:0> T3IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 12-10 IC3IP<2:0>: Input Capture 3 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 9-8 IC3IS<1:0>: Input Capture 3 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Input Capture module. DS61122D-page 15-12 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture Register 15-8: r-x — bit 31 IPC4: Interrupt Priority Control Register 4(1) r-x r-x R/W-0 R/W-0 — — INT4IP<2:0> R/W-0 R/W-0 R/W-0 INT4IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC4IP<2:0> OC4IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC4IP<2:0> IC4IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T4IP<2:0> T4IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 12-10 IC4IP<2:0>: Input Capture 4 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 9-8 IC4IS<1:0>: Input Capture 4 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Input Capture module. 15 Input Capture © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-13 PIC32MX Family Reference Manual Register 15-9: r-x — bit 31 IPC5: Interrupt Priority Control Register 5(1) r-x r-x R/W-0 R/W-0 — — SPI1IP<2:0> R/W-0 R/W-0 R/W-0 SPI1IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC5IP<2:0> OC5IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC5IP<2:0> IC5IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T5IP<2:0> T5IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 12-10 IC5IP<2:0>: Input Capture 5 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 9-8 IC5IS<1:0>: Input Capture 5 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the Input Capture module. DS61122D-page 15-14 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture 15.3 TIMER SELECTION Each PIC32MX device may have one or more input capture channels. Each channel can select between one of two 16-bit timers for the time base or two 16-bit timers together (to form a 32-bit timer). Refer to the device data sheet for the specific timers that can be selected. For 16-bit Capture mode, setting ICTMR (ICxCON<7>) to ‘0’ selects the Timer3 for capture. Setting ICTMR (ICxCON<7>) to ‘1’ selects the Timer2 for capture. An input capture channel configured to support 32-bit capture may use a 32-bit timer resource for capture. By setting ICC32 (ICxCON<8>) to ‘1’, a 32-bit timer resource is captured. The 32-bit timer resource is routed into the module using the existing 16-bit timer inputs. The Timer 2 provides the lower 16-bits and the Timer 3 provides the upper 16-bits, as shown in Figure 15-2. The timers clock can be set up using the internal peripheral clock source or a synchronized external clock source applied at the TxCK pin. Figure 15-2: 32-bit Timer Selection Block Diagram Timer3 Timer2 ICTMR = Don't Care ICC32 = 1 FIFO Control Value = 1 0 1 ICxBUF<31:16> ICxBUF<15:0> 15.4 INPUT CAPTURE ENABLE After configuration, an Input Capture module is enabled by setting the ON bit (ICxCON<15>). When this bit is cleared, the module is reset. Resetting the module has the following effects: • clears the Overflow Condition Flag • resets FIFO to the empty state • resets the event count (for interrupt generation) • resets the prescaler count Register reads and writes are allowed regardless of the ON (ICxCON<15>) bit state. 15 Input Capture © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-15 PIC32MX Family Reference Manual 15.5 INPUT CAPTURE EVENT MODES The input capture module captures the value of the selected time base register when an event occurs at the ICx pin. An input capture channel can be configured in the following modes: 1. Simple Capture Event modes: Capture timer value on every falling edge of input at ICx pin Capture timer value on every rising edge of input at ICx pin Capture timer value on every rising and falling edge of input at ICx pin, starting with a specified edge 2. Prescaled Capture Event modes: Capture timer value on every 4th rising edge of input at ICx pin Capture timer value on every 16th rising edge of input at ICx pin 3. Edge Detect mode (See 15.5.3 “Edge Detect (Hall Sensor) Mode”) 4. Interrupt Only mode (See 15.5.4 “Interrupt Only Mode”) These Input Capture modes are configured by setting the appropriate Input Capture mode bits ICxM (ICxCON<2:0>). When the Input Capture Channel is disabled (ICM = 000), the Input Capture logic ignores incoming capture edges and does not generate further capture events or interrupts. The FIFO continues to be operational for reading. Returning the channel to any of the other modes resumes operation. A state change on the capture input while capture is disabled does not cause a capture event on exiting the Capture Disable mode. Note: The prescaler logic continues to run when the Input Capture module is in Capture Disable mode. 15.5.1 Simple Capture Events The capture module can capture a timer count value based on the selected edge (rising, falling or both, defined by mode) of the input applied to the ICx pin. These modes are specified by setting the ICM (ICxCON<2:0>) bits to ‘010’, ‘011’, or ‘110’. Setting ICM = 011 configures the module to capture the timer value on any rising edge of the capture input. ICM = 010 configures the module to capture the timer on any falling edge of the capture input. Setting ICM = 110 configures the channel to capture the timer on every transition of the capture input, beginning with the edge specified by ICFEDGE (ICxCON<9>). In Simple Capture Event mode, the prescaler is not used. See Figure 15-3, Figure 15-4 and Figure 15-5 for simplified timing diagrams of a simple capture event. The input capture logic detects and synchronizes the rising or falling edge of the capture pin signal on the peripheral clock. When the rising/falling edge has occurred, the capture module logic will write the current time base value to the capture buffer and signal the interrupt generation logic. Note: Since the capture input must be synchronized to the peripheral clock, the module captures the timer count value that is valid 2-3 peripheral clock cycles (TPB) after the capture event. An input capture interrupt event is generated after one, two, three or four timer count captures, as configured by ICI (ICxCON<6:5>). See 15.7 “Input Capture Interrupts” for further details. Since the capture pin is sampled by the peripheral clock, the capture pulse high and low widths must be greater than the peripheral clock period. DS61122D-page 15-16 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture Figure 15-3 depicts two capture events when the Input Capture module is in Simple Capture mode configured to capture every rising edge, ICM = 011 (ICxCON<2:0>), with interrupts generated for every event, ICI = 00 (ICxCON<6:5>). The first capture event occurs when the timer value is ‘n’. Due to synchronization delay, timer value ‘n + 2’ is stored in the capture buffer. The second capture event occurs when the timer value is ‘m’. Note that ‘m + 3’ is stored in the capture buffer due to propagation delay as well as the synchronization delay. Interrupt events are generated on each capture event. Figure 15-3: Simple Capture Event Timing Diagram, Capture Every Rising Edge Peripheral Clock Timer Count n n+1 n+2 m m+1 m+2 m+3 m+4 m+5 ICx Input Synchronized Capture Capture Data Capture Interrupt n+2 m+3 Figure 15-4 depicts a capture event when the Input Capture module is in Simple Capture mode configured to capture every falling edge, ICM = 010 (ICxCON<2:0>), with interrupts generated for every event, ICI = 00 (ICxCON<6:5>). In this example, the timer frequency is slower than the peripheral clock. The capture event occurs when the timer value is ‘n’. Value ‘n’ is stored in the capture buffer and an interrupt event is generated. Figure 15-4: Simple Capture Event Timing Diagram, Capture Every Falling Edge Peripheral Clock Timer Count n n+1 ICx Input Synchronized Capture Capture Data Capture Interrupt n 15 Input Capture © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-17 PIC32MX Family Reference Manual Figure 15-5 depicts a capture event when the Input Capture module is in Simple Capture mode configured to capture every edge, ICM = 011 (ICxCON<2:0>); starting with a falling edge, ICFEDGE = 0 (ICxCON<9>), with interrupts generated for every second event, ICI = 01 (ICxCON<6:5>). The first falling edge occurs when the timer value is ‘n’. Value ‘n + 2’ is stored in the capture buffer. A subsequent rising edge occurs when the timer value is ‘m’. Value ‘m + 2’ is stored in the capture buffer and an interrupt event is generated. Figure 15-5: Simple Capture Event Timing Diagram, Capture Every Edge, Falling Edge First Peripheral Clock Timer Count ICx Input Synchronized Capture Capture Data Capture Interrupts n n+1 n+2 m m+1 m+2 m+3 m+4 n+2 m+2 15.5.2 Prescaled Capture Event Mode In Prescaled Capture Event mode, the Input Capture module triggers a capture event on either every fourth or every sixteenth rising edge. These modes are selected by setting the ICM (ICxCON<2:0>) bits to ‘100’ or ‘101’, respectively. The capture prescaler counter is incremented on every rising edge on the capture input. When the prescaler counter equals four or sixteen (depending on the mode selected), the counter outputs a “valid” capture event signal. The valid capture event signal is then synchronized to the peripheral clock. The synchronized capture event signal triggers a timer count capture. Note: Since the capture input must be synchronized to the peripheral clock, the module captures the timer count value that is valid 2-3 peripheral clock cycles (TPB) after the capture event. An input capture interrupt is generated after one, two, three or four timer count captures, as configured by ICI. See 15.7 “Input Capture Interrupts” for further details. Note: It is recommended that the user disable the capture module (i.e., clear the ON bit, ICxCON<15>), before switching to Prescaler Capture Event mode. Simply switching to Prescaler Capture Event mode from another active mode does not reset the prescaler and may cause an inadvertent capture event. The prescaler counter is cleared when the following events occur: • The Input Capture module is turned off, i.e., ON (ICxCON<15>) = 0. • The Input Capture module is reset. Since the capture pin triggers an internal flip-flop, the input capture pulse high and low widths must be greater than TccL and TccH. DS61122D-page 15-18 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture Figure 15-6 depicts a capture event when the Input Capture module is in Prescaler Capture Event mode. The prescaler is configured to capture a timer value for every fourth rising edge on the capture input, ICM = 100 (ICxCON<2:0>), with interrupts generated for every capture event, ICI = 00 (ICxCON<6:5>). The fourth rising edge on the capture input occurs at time ‘n’. The prescaler output is synchronized. Due to synchronization delay, timer value ‘n + 2’ is stored in the capture buffer. An interrupt signal is generated due to the capture event. Figure 15-6: Prescaler Capture Event Timing Diagram TPB Peripheral Clock Timer Count Capture Input n TICX_IN_L TICX_IN_H n+1 n+2 n+3 n+4 Prescaler Count 1 2 3 4 Prescaler Output Synchronized Capture Capture Data n+2 Capture Interrupt Input Capture 15 © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-19 PIC32MX Family Reference Manual 15.5.3 Edge Detect (Hall Sensor) Mode In Edge Detect mode, the Input Capture module captures a timer count value on every edge of the capture input. Edge Detection mode is selected by setting the ICM bit to ‘001’. In this mode, the capture prescaler is not used and the capture overflow bit, ICOV (ICxCON<4>), is not updated. In this mode, the Interrupt Control bits, ICI (ICxCON<6:5>), are ignored and an interrupt event is generated for every timer count capture. See Figure 15-7 for a simplified timing diagram. As with the Simple Capture Event mode, the Input Capture logic detects and synchronizes the rising and falling edge of the capture input signal on the peripheral clock. When a rising or falling edge occurs, the capture module writes the time base value to the capture buffer. Note: Since the capture input must be synchronized to the peripheral clock, the module captures the timer count value that is valid 2-3 peripheral clock cycles (TPB) after the capture event. Since the capture pin is sampled by the peripheral clock, the capture pulse high and low widths must be greater than the peripheral clock period. Figure 15-7 depicts three capture events when the Input Capture module is in Edge Detect mode, ICM = 001 (ICxCON<2:0). Transitions on the capture input occur at times ‘n’, ‘n + 1’ and ‘n + 3’. Due to synchronization and propagation delay, timer values ‘n + 2’, ‘n + 4’ and ‘n + 5’ are stored in the capture buffer. Interrupt signals are generated due to each capture input transition. Figure 15-7: Edge Detect Capture Event Timing Diagram Peripheral Clock Timer Count Capture Input Synchronized Capture Capture Data Capture Interrupt n n+1 TICX_IN_H n+2 n+3 TICX_IN_L n+4 n+5 n+6 n+2 n+4 n+5 15.5.4 Interrupt Only Mode When the Input Capture module is set for Interrupt Only mode (ICM = 111) and the device is in SLEEP or IDLE mode, the capture input functions as an interrupt pin. Any rising edge on the capture input triggers an interrupt. No timer values are captured and the FIFO buffer is not updated. When the device leaves SLEEP or IDLE mode, the interrupt signal is deasserted. In this mode, since no timer values are captured, the Timer Select bit, ICTMR (ICxCON<7>), is ignored and there is no need to configure the timer source. A wake-up interrupt is generated on the first rising edge. Therefore, the Interrupt Control bits, ICI (ICxCON<6:5>), are also ignored. The prescaler is not used in this mode. Since the capture pin triggers an internal flip-flop, the capture pulse high and low widths must be greater than TccL and TccH. DS61122D-page 15-20 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture 15.6 CAPTURE BUFFER OPERATION Each Input Capture module has an associated four-level deep First-In-First-Out (FIFO) buffer. The buffer is accessible to the user via the buffer register (ICxBUF). ICxBUF is written by the Input Capture logic and can only be read by the user. Writes to ICxBUF are ignored. There are two status flags which provide status on the FIFO buffer: • ICBNE (ICxCON<3>) – Input Capture Buffer Not Empty • ICOV (ICxCON<4>) – Input Capture Overrun When the Input Capture module is disabled, i.e., ON ICxCON<15>) = 0 or Reset, the status flags are cleared and the buffer is cleared to the empty state. The ICBNE flag is set on the first input capture event and remains set until all capture events have been read from the FIFO. For example, if three capture events have occurred, then three reads of the capture FIFO buffer are required before the ICBNE flag is cleared. If four capture events have occurred, then four reads are required to clear the ICBNE flag. Each read of the FIFO buffer adjusts the read pointer, allowing the remaining entries to move to the next available top location of the FIFO. In 32-bit Capture mode, make sure you read the upper 16 bit last if you are reading 16 bits at a time. The FIFO read pointer is advanced when you read the MSB. If the FIFO is full with four capture events and a fifth capture event occurs prior to a read of the FIFO, an overrun condition occurs and the ICOV (ICxCON<4>) bit is set to a logic ‘1’. In addition, the fifth capture event is not recorded and subsequent capture events do not alter the current FIFO contents until the overrun condition is cleared. The overflow condition is cleared in any of the following ways: • Module is disabled, i.e., ON = 0 (ICxCON<15>) • Capture buffer is read until ICBNE = 0 (ICxCON<3>) • Device is reset If the Input Capture module is disabled and at some time reenabled, the FIFO buffer contents are not defined and a read may yield indeterminate results. If a FIFO read is performed when no capture event has been received, the read yields indeterminate results. Input Capture 15 © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-21 PIC32MX Family Reference Manual 15.7 INPUT CAPTURE INTERRUPTS The Input Capture module has the ability to generate an interrupt event signal based upon the selected number of capture events. A capture event is defined by the writing of a timer value into the FIFO. The number of capture events required to trigger an interrupt event is set by control bits ICI (ICxCON<6:5>). If ICBNE = 0 (ICxCON<3>), then the interrupt count is cleared. This allows the user to synchronize the interrupt count to the FIFO status. For example, assume that ICI = 01, specifying an interrupt event every 2nd capture event. 1. Turn on module. 2. Interrupt count = 0. 3. Capture event. FIFO contains 1 entry. 4. Interrupt count = 1. 5. Read FIFO. FIFO is empty => interrupt count = 0. 6. Capture event. FIFO contains 1 entry. 7. Interrupt count = 1. 8. Capture event. FIFO contains 2 entries. 9. Interrupt count = 2. Issue interrupt. 10. Interrupt count = 0. 11. Capture event. FIFO contains 3 entries. 12. Interrupt count = 1. 13. Read FIFO 3 times. 14. FIFO is empty => interrupt count = 0. 15. Capture event. FIFO contains 1 entry. 16. Interrupt count = 1. 17. Read FIFO. FIFO is empty => interrupt count = 0. The first capture event is defined as the capture event occurring after a mode change from the OFF mode or after ICBNE = 0. At overrun, the capture events cease, and therefore, the interrupt events stop – unless ICI = 00 or ICM = 001. Applications often dictate using the Input Capture pins as auxiliary external interrupt sources. When ICI = 00 or ICM = 001, interrupt events occur regardless of FIFO overrun. There is no need to perform a dummy read on the capture buffer to clear the event and prevent an overflow in order to ensure that future interrupt events are not inhibited. The ICOV (ICxCON<4>) flag is still set for the overflow condition. DS61122D-page 15-22 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture Figure 15-8 depicts five capture events when the Input Capture module is configured to capture timer values on every rising edge (ICM = 011) and generate an interrupt for every four captures (ICI = 11). Note that the fourth capture causes the capture of value ‘n + 8’ and triggers an interrupt event. Figure 15-8: Interrupt Event, ICXCON.ICXM<2:0> = 011, ICXCON.ICXI<1:0> = 11 Peripheral Clock Timer Count Capture Input Synchronized Capture Capture Data Capture Interrupt TPB n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 TICX_IN_L TICX_IN_H n+2 n+4 n+6 n+8 n + 10 15.7.1 Interrupt Control Bits Each input capture channel has interrupt flag status bits (ICxIF), interrupt enable bits (ICxIE), interrupt priority control bits (ICxIP) and secondary interrupt priority control bits (ICxIS). Refer to 8.2 “Control Registers” in Section 1. “Interrupts” for further information on peripheral interrupts. Input Capture 15 © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-23 PIC32MX Family Reference Manual 15.8 15.9 OPERATION IN POWER-SAVING MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 15.8.1 Input Capture Operation in SLEEP Mode When the device enters SLEEP mode, the peripheral clock is disabled. In SLEEP mode, the input capture module can only function as an external interrupt source. This mode is enabled by setting control bits ICM = 111 (ICxCON<2:0>). In this mode, a rising edge on the capture pin will generate a device wake-up from SLEEP condition. If the respective module interrupt bit is enabled and the module’s priority is of the required priority level, an interrupt will be generated. See 15.5.4 “Interrupt Only Mode” for more detail. If the capture module has been configured for a mode other than ICM = 111 and the device does enter the SLEEP mode, no external pin stimulus, rising or falling, will generate a wake-up from SLEEP event. 15.8.2 Input Capture Operation in IDLE Mode When the device enters IDLE mode, the peripheral clock sources remain functional and the CPU stops executing code. The SLEEP-In-IDLE control bit, SIDL (ICxCON<13>), determines whether the module will stop in IDLE mode or continue to operate. If SIDL is ‘0’, the module continues normal operation in IDLE mode. Interrupt only mode (ICM = 111) may generate an interrupt when in IDLE if SIDL is ‘0’. See 15.5.4 “Interrupt Only Mode” for further details. If SIDL is ‘1’, the module stops when the device is in IDLE mode. The module performs the same procedures when stopped in IDLE mode as for SLEEP mode. See 15.5.4 “Interrupt Only Mode” for further details. 15.8.3 Device Wake-up on SLEEP/IDLE An input capture event can generate a device wake-up or interrupt, if enabled, when the device is in IDLE or SLEEP mode. See 15.5.4 “Interrupt Only Mode” for further details. INPUT CAPTURE OPERATION IN DEBUG MODE The FRZ bit (ICxCON<14>) determines whether the Input Capture module will run or stop while the CPU is executing Debug Exception code (i.e., the application is halted) in DEBUG mode. When FRZ is ‘0’, the Timer module continues to run even when the application is halted in DEBUG mode. When FRZ is ‘1’ and the application is halted in DEBUG mode, the module will freeze its operations and make no changes to the state of the Input Capture module. The module will resume its operation after the CPU resumes execution. Note: The FRZ bit is readable and writable only when the CPU is executing in Debug Exception mode. In all other modes, the FRZ bit reads as ‘0’. If FRZ bit is changed during DEBUG mode, the new value does not take effect until the current Debug Exception mode is exited and re-entered. During the Debug Exception mode, the FRZ bit reads the state of the peripheral when entering DEBUG mode. DS61122D-page 15-24 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture 15.9.1 Capture Operation During FREEZE (FRZ = 1) When frozen, the capture input does not cause changes to the module. The edge detection logic runs during Freeze so that any state changes that occur during Freeze will not be inadvertently detected after leaving Freeze. Clocks to all of the logic within the Input Capture module, with the exception of the SFR logic and the FIFO read logic, are conditioned on Freeze. Note: The prescaler logic is not frozen during DEBUG mode. When frozen, the emulator is allowed to read the Input Capture FIFO; however, the FIFO status flags as viewed by the user do not change. 15.9.2 Operation of the Capture Buffer in Debug Mode During DEBUG mode, reads from the capture buffer become circular. Reading ICxBUF adjusts only the DEBUG FIFO pointers; no status flags are affected by reads. This allows the DEBUG software to have visibility of the full contents of the FIFO. To enable this, the hardware contains two sets of ICxBUF FIFO pointers: an operating mode set and a DEBUG mode set. 15.10 I/O PIN CONTROL When the capture module is enabled, the user must ensure that the I/O pin direction is configured for an input by setting the associated TRIS bit. The pin direction is not set when the capture module is enabled. Furthermore, all other peripherals multiplexed with the input pin must be disabled. 15.11 DESIGN TIPS Question 1: Can the Input Capture module be used to wake the device from SLEEP mode? Answer: Yes. When the Input Capture module is configured to ICM = 111 (ICxCON<2:0>) and the respective channel interrupt enable bit is asserted (ICIE = 1; see Interrupt registers IE0-IE2), a rising edge on the capture pin will wake-up the device from SLEEP. (See 15.5.4 “Interrupt Only Mode” for further details.) Input Capture 15 © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-25 PIC32MX Family Reference Manual 15.12 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Input Capture module include the following: Title Using the CCP Module(s) Implementing Ultrasonic Ranging Application Note # AN594 AN597 Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. DS61122D-page 15-26 Preliminary © 2008 Microchip Technology Inc. Section 15. Input Capture 15.13 REVISION HISTORY Revision A (October 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x; Removed ‘x’ in bit names. Revision D (June 2008) Revised note for Registers 15-1, 15-3, 15-4, 15-5, 15-6, 15-7, 15-8, 15-9; Change Reserved bits from “Maintain as” to “Write”; Added Note to ON bit (ICxCON Register). Input Capture 15 © 2008 Microchip Technology Inc. Preliminary DS61122D-page 15-27 PIC32MX Family Reference Manual NOTES: DS61122D-page 15-28 Preliminary © 2008 Microchip Technology Inc. Output Compare 16 Section 16. Output Compare HIGHLIGHTS This section of the manual contains the following topics: 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 Introduction.............................................................................................................. 16-2 Output Compare Registers ...................................................................................... 16-3 Operation............................................................................................................... 16-34 Interrupts................................................................................................................ 16-61 I/O Pin Control ....................................................................................................... 16-62 Operation In Power-Saving and DEBUG Modes ................................................... 16-63 Effects of Various Resets....................................................................................... 16-64 Output Compare Application.................................................................................. 16-64 Design Tips ............................................................................................................ 16-67 Related Application Notes ..................................................................................... 16-68 Revision History..................................................................................................... 16-69 © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-1 PIC32MX Family Reference Manual 16.1 INTRODUCTION The Output Compare module is primarily used to generate a single pulse or a train of pulses in response to selected time base events. The following are some of the key features of the Output Compare module: • Multiple output compare modules in a device • Single and Dual Compare modes • Single and continuous output pulse generation • Pulse-Width Modulation (PWM) mode • Programmable interrupt generation on compare event • Hardware-based PWM Fault detection and automatic output disable • Programmable selection of 16 or 32-bit time bases • Can operate from either of two available 16-bit time bases or a single 32-bit time base Figure 16-1: Output Compare Module Block Diagram Set Flag bit OCxIF(1) OCxRS(1) OCxR(1) Comparator Output Logic 3 OCM<2:0> Mode Select SQ R OCx(1) Output Enable OCFA or OCFB(2) 0 1 OCTSEL 0 1 16 16 TMR register inputs from time bases(3) Period match signals from time bases(3) Note 1: 2: 3: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 5. OCFA pin controls OC1-OC4 channels. OCFB pin controls OC5 channels. Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit time base. Refer to the device data sheet for the time bases associated with the module. DS61111D-page 16-2 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 16.2 OUTPUT COMPARE REGISTERS Note: Each PIC32MX device variant may have one or more Output Compare modules. An ‘x’ used in the names of pins, control/Status bits and registers denotes the particular module. Refer to the specific device data sheets for more details. Each Output Compare module consists of the following Special Function Registers (SFRs): • OCxCON: Control register for the OCMP module ‘x’ OCxCONCLR, OCxCONSET, OCxCONINV: Atomic Bit Manipulation Write-only Registers for OCxCON • OCxR: Data register for the module ‘x’ OCxRCLR, OCxRSET, OCxRINV: Atomic Bit Manipulation Write-only Registers for OCxR • OCxRS: Secondary data register for the module ‘x’ OCxRSCLR, OCxRSSET, OCxRSINV: Atomic Bit Manipulation Write-only Registers for OCxRS • T2CON: Time Base Register T2CONCLR, T2CONSET, T2CONINV: Atomic Bit Manipulation Write-only Registers for T2CON • T3CON: Time Base Register T3CONCLR, T3CONSET, T3CONINV: Atomic Bit Manipulation Write-only Registers for T3CON • TMR2: Timer Register TTMR2CLR, TMR2SET, TMR2INV: Atomic Bit Manipulation Write-only Registers for TMR2 • TMR3: Timer Register TMR3CLR, TMR3SET, TMR3INV: Atomic Bit Manipulation Write-only Registers for TMR3 • PR2: Period 2 Register PR2CLR, PR2SET, PR2INV: Atomic Bit Manipulation Write-only Registers for PR2 • PR3: Period 3 Register PR3CLR, PR3SET, PR3INV: Atomic Bit Manipulation Write-only Registers for PR3 Each timer module also has the following associated bits for interrupt control: • OC5IF, OC4IF, OC3IF, OC2IF, OC1IF: Interrupt Flag Status Bits – in IFS0 INT Register • OC5IE, OC4IE, OC3IE, OC2IE, OC1IE: Interrupt Enable Control Bits – in IEC0 INT Register • OC1IP<2:0>: Interrupt Priority Control Bits – in IPC1 INT Registers • OC1IS<1:0>: Interrupt Subpriority Control Bits – in IPC1 INT Registers • OC2IP<2:0>: Interrupt Priority Control Bits – in IPC2 INT Registers • OC2IS<1:0>: Interrupt Subpriority Control Bits – in IPC2 INT Registers • OC3IP<2:0>: Interrupt Priority Control Bits – in IPC3 INT Registers • OC3IS<1:0>: Interrupt Subpriority Control Bits – in IPC3 INT Registers • OC4IP<2:0>: Interrupt Priority Control Bits – in IPC4 INT Registers • OC4IS<1:0>: Interrupt Subpriority Control Bits – in IPC4 INT Registers • OC5IP<2:0>: Interrupt Priority Control Bits – in IPC5 INT Registers • OC5IS<1:0>: Interrupt Subpriority Control Bits – in IPC5 INT Registers © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-3 PIC32MX Family Reference Manual The following table summarizes all Output-Compare-related registers. Corresponding registers appear after the summary, followed by a detailed description of each register. Table 16-1: Output Compare SFR Summary Name Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 OCxCON 31:24 — — — — — — — — 23:16 — 15:8 ON 7:0 — — — — — — — — FRZ SIDL — — — — — — OC32 OCFLT OCTSEL OCM<2:0> OCxCONCLR 31:0 OCxCONSET 31:0 OCxCONINV 31:0 Write clears selected bits in OCxCON; read yields an undefined value Write sets selected bits in OCxCON; read yields an undefined value Write inverts selected bits in OCxCON; read yields an undefined value OCxR 31:24 23:16 15:8 OCxR<31:24> OCxR<23:16> OCxR<15:8> OCxRCLR OCxRSET 7:0 31:0 31:0 OCxR<7:0> Write clears selected bits in OCxR; read yields an undefined value Write sets selected bits in OCxR; read yields an undefined value OCxRINV OCxRS 31:0 31:24 23:16 Write inverts selected bits in OCxR; read yields an undefined value OCxRS<31:24> OCxRS<23:16> OCxRSCLR 15:8 7:0 31:0 OCxRS<15:8> OCxRS<7:0> Write clears selected bits in OCxRS; read yields an undefined value OCxRSSET OCxRSINV IFS0 31:0 31:0 31:24 23:16 15:8 I2C1MIF SPI1EIF INT3IF Write sets selected bits in OCxRS; read yields an undefined value Write inverts selected bits in OCxRS; read yields an undefined value I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF SPI1RXIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF OC3IF IC3IF T3IF INT2IF OC2IF IC3IF SPI1TXIF T4IF T2IF IFS0CLR IFS0SET 7:0 31:0 31:0 INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF Write clears the selected bits in IFS0, read yields undefined value Write sets the selected bits in IFS0, read yields undefined value CTIF IFS0INV IEC0 31:0 31:24 I2C1MIE Write inverts the selected bits in IFS0, read yields undefined value I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE SPI1RXIE SPI1TXIE 23:16 15:8 7:0 SPI1EIE INT3IE INT1IE OC5IE OC3IE OC1IE IC5IE IC3IE IC1IE T5IE T3IE T1IE INT4IE INT2IE INT0IE OC4IE OC2IE CS1IE IC4IE IC2IE CS0IE T4IE T2IE CTIE IEC0CLR IEC0SET IEC0INV 31:0 31:0 31:0 Write clears the selected bits in IEC0, read yields undefined value Write sets the selected bits in IEC0, read yields undefined value Write inverts the selected bits in IEC0, read yields undefined value IPC1 31:24 — — — 23:16 — — — 15:8 — — — INT1IP<2:0> OC1IP<2:0> IC1IP<2:0> INT1IS<1:0> OC1IS<1:0> IC1IS<1:0> 7:0 — IPC1CLR 31:0 IPC1SET 31:0 — — T1IP<2:0> Write clears the selected bits in IPC1, read yields undefined value Write sets the selected bits in IPC1, read yields undefined value T1IS<1:0> IPC1INV 31:0 Write inverts the selected bits in IPC1, read yields undefined value DS61111D-page 16-4 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare Table 16-1: Name IPC2 IPC2CLR IPC2SET IPC2INV IPC3 IPC3CLR IPC3SET IPC3INV IPC4 IPC4CLR IPC4SET IPC4INV IPC5 IPC5CLR IPC5SET IPC5INV T2CON T2CONCLR T2CONSET T2CONINV T3CON T3CONCLR T3CONSET T3CONINV Output Compare SFR Summary (Continued) Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 31:24 — — — INT2IP<2:0> INT2IS<1:0> 23:16 — — — 15:8 — — — 7:0 — — — OC2IP<2:0> IC2IP<2:0> T2IP<2:0> OC2IS<1:0> IC2IS<1:0> T2IS<1:0> 31:0 Write clears the selected bits in IPC2, read yields undefined value 31:0 Write sets the selected bits in IPC2, read yields undefined value 31:0 Write inverts the selected bits in IPC2, read yields undefined value 31:24 — 23:16 — 15:8 — 7:0 — 31:0 — — INT3IP<2:0> INT3IS<1:0> — — OC3IP<2:0> OC3IS<1:0> — — IC3IP<2:0> IC3IS<1:0> — — T3IP<2:0> T3IS<1:0> Write clears the selected bits in IPC3, read yields undefined value 31:0 31:0 31:24 — Write sets the selected bits in IPC3, read yields undefined value Write inverts the selected bits in IPC3, read yields undefined value — — INT4IP<2:0> INT4IS<1:0> 23:16 — — — 15:8 — — — 7:0 — — — OC4IP<2:0> IC4IP<2:0> T4IP<2:0> OC4IS<1:0> IC4IS<1:0> T4IS<1:0> 31:0 Write clears the selected bits in IPC4, read yields undefined value 31:0 Write sets the selected bits in IPC4, read yields undefined value 31:0 Write inverts the selected bits in IPC4, read yields undefined value 31:24 — — — 23:16 — — — 15:8 — — — SPI1IP<2:0> OC5IP<2:0> IC5IP<2:0> SPI1IS<1:0> OC5IS<1:0> IC5IS<1:0> 7:0 — 31:0 31:0 — — T5IP<2:0> Write clears the selected bits in IPC5, read yields undefined value Write sets the selected bits in IPC5, read yields undefined value T5IS<1:0> 31:0 Write inverts the selected bits in IPC5, read yields undefined value 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 ON FRZ SIDL — — — — — 7:0 TGATE TCKPS<2:0> T32 — TCS — 31:0 Write clears selected bits in T2CON; read yields undefined value 31:0 Write sets selected bits in T2CON; read yields undefined value 31:0 Write inverts selected bits in T2CON; read yields undefined value 31:24 — — — — — — — — 23:16 — — — — — — — — 15:8 ON FRZ SIDL — — — — — 7:0 TGATE TCKPS<2:0> — — TCS — 31:0 Write clears selected bits in T3CON; read yields undefined value 31:0 Write sets selected bits in T3CON; read yields undefined value 31:0 Write inverts selected bits in T3CON; read yields undefined value 16 © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-5 PIC32MX Family Reference Manual Table 16-1: Name TMR2 TMR2CLR TMR2SET TMR2INV TMR3 TMR3CLR TMR3SET TMR3INV PR2 PR2CLR PR2SET PR2INV PR3 PR3CLR PR3SET PR3INV Output Compare SFR Summary (Continued) Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 31:24 — — — — — — — 23:16 — — — — — — — 15:8 TMRx<15:8> 7:0 TMRx<7:0> 31:0 31:0 31:0 Write clears selected bits in TMRx, read yields undefined value Write sets selected bits in TMRx, read yields undefined value Write inverts selected bits in TMRx, read yields undefined value 31:24 — 23:16 — 15:8 7:0 31:0 — — — — — — — — — — — — TMRx<15:8> TMRx<7:0> Write clears selected bits in TMRx, read yields undefined value 31:0 31:0 31:24 — Write sets selected bits in TMRx, read yields undefined value Write inverts selected bits in TMRx, read yields undefined value — — — — — — 23:16 — — — — — — — 15:8 PR2<15:8> 7:0 PR2<7:0> 31:0 31:0 31:0 Write clears selected bits in PR2; read yields undefined value Write sets selected bits in PR2; read yields undefined value Write inverts selected bits in PR2; read yields undefined value 31:24 — — — — — — — 23:16 — — — — — — — 15:8 PR3<15:8> 7:0 31:0 31:0 PR3<7:0> Write clears selected bits in PR3; read yields undefined value Write sets selected bits in PR3; read yields undefined value 31:0 Write inverts selected bits in PR3; read yields undefined value Bit 24/16/8/0 — — — — — — — — DS61111D-page 16-6 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-1: OCxCON: Output Compare ‘x’ Control Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x r-x ON FRZ SIDL — — — — — bit 15 bit 8 r-x — bit 7 r-x R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — OC32 OCFLT OCTSEL OCM<2:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14 bit 13 bit 12-6 bit 5 bit 4 bit 3 Reserved: Write ‘0’; ignore read ON: Output Compare Peripheral On bit 1 = Output Compare peripheral is enabled. 0 = Output Compare peripheral is disabled and not drawing current. SFR modifications are allowed. The status of other bits in this register are not affected by setting or clearing this bit. Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU enters Debug Exception mode 0 = Continue operation when CPU enters Debug Exception mode Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode. SIDL: Stop in IDLE Mode bit 1 = Discontinue operation when CPU enters IDLE mode 0 = Continue operation in IDLE mode Reserved: Write ‘0’; ignore read OC32: 32-bit Compare Mode bit 1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source 0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source OCFLT: PWM Fault Condition Status bit(1) 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred Note: This bit is only used when OCM<2:0> = ‘111’. OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for this OCMP module 0 = Timer2 is the clock source for this OCMP module Refer to the device data sheet for specific time bases available to the Output Compare module. Note 1: Reads as ‘0’ in modes other than PWM mode. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-7 PIC32MX Family Reference Manual Register 16-1: OCxCON: Output Compare ‘x’ Control Register (Continued) bit 2-0 OCM<2:0>: Output Compare Mode Select bits 111 = PWM mode on OCx; Fault pin enabled 110 = PWM mode on OCx; Fault pin disabled 101 = Initialize OCx pin low; generate continuous output pulses on OCx pin 100 = Initialize OCx pin low; generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high; compare event forces OCx pin low 001 = Initialize OCx pin low; compare event forces OCx pin high 000 = Output compare peripheral is disabled but continues to draw current Note 1: Reads as ‘0’ in modes other than PWM mode. DS61111D-page 16-8 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-2: OCxCONCLR: Output Compare ‘x’ Control Clear Register R/W-x Write clears selected bits in OCxCON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in OCxCON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in OCxCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Examples: OCxCONCLR = 0x00008001 will clear bits 15 and 0 in the OCxCON register. localValue = OCxCONCLR will yield an undefined value. Register 16-3: OCxCONSET: Output Compare ‘x’ Control Set Register R/W-x Write sets selected bits in OCxCON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in OCxCON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in OCxCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Examples: OCxCONSET = 0x00008001 will set bits 15 and 0 in the OCxCON register. localValue = OCxCONSET will yield an undefined value. Register 16-4: OCxCONINV: Output Compare ‘x’ Control Invert Register R/W-x Write inverts selected bits in OCxCON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in OCxCON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in OCxCON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Examples: OCxCONINV = 0x00008001 will invert bits 15 and 0 in the OCxCON register. localValue = OCxCONINV will yield an undefined value. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-9 PIC32MX Family Reference Manual Register 16-5: R/W-0 bit 31 OCxR: Output Compare ‘x’ Compare Register R/W-0 R/W-0 R/W-0 R/W-0 OCR<31:24> R/W-0 R/W-0 R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 R/W-0 R/W-0 OCR<23:16> R/W-0 R/W-0 R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 OCR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 OCR<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-0 OCxR<31:16>: Upper 16 bits of 32-bit compare value, when OC32 (OCxCON<5>) = 1 OCxR<15:0>: Lower 16 bits of 32-bit compare value or entire 16 bits of 16-bit compare value when OC32 = 0 DS61111D-page 16-10 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-6: OCxRCLR: Output Compare ‘x’ Compare Clear Register R/W-x Write clears selected bits in OCxR, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in OCxR A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in OCxR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Examples: OCxRCLR = 0x00008001 will clear bits 15 and 0 in the OCxR register. localValue = OCxRCLR will yield an undefined value. Register 16-7: OCxRSET: Output Compare ‘x’ Compare Set Register R/W-x Write sets selected bits in OCxR, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in OCxR A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in OCxR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Examples: OCxRSET = 0x00008001 will set bits 15 and 0 in the OCxR register. localValue = OCxRSET will yield an undefined value. Register 16-8: OCxRINV: Output Compare ‘x’ Compare Invert Register R/W-x Write inverts selected bits in OCxR, read yields undefined value bit 31 bit 0 31-0 Inverts selected bits in OCxR A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in OCxR register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Examples: OCxRINV = 0x00008001 will invert bits 15 and 0 in the OCxR register. localValue = OCxRINV will yield an undefined value. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-11 PIC32MX Family Reference Manual Register 16-9: R/W-0 bit 31 OCxRS: Output Compare x Secondary Compare Register R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OCRS<31:24> R/W-0 R/W-0 bit 24 R/W-0 bit 23 R/W-0 R/W-0 R/W-0 R/W-0 OCRS<23:16> R/W-0 R/W-0 R/W-0 bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 OCRS<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 OCRS<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-0 OCxRS<31:16>: Upper 16 bits of 32-bit compare value when OC32 (OCxCON<5>) = 1 OCxRS<15:0>: Lower 16 bits of 32-bit compare value or entire 16 bits of 16-bit compare value when OC32 = 0 DS61111D-page 16-12 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-10: OCxRSCLR: Output Compare ‘x’ Secondary Compare Clear Register R/W-x Write clears selected bits in OCxRS, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in OCxRS A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in OCxRS register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Examples: OCxRSCLR = 0x00008001 will clear bits 15 and 0 in the OCxRS register. localValue = OCxRSCLR will yield an undefined value. Register 16-11: OCxRSSET: Output Compare ‘x’ Secondary Compare Set Register R/W-x Write sets selected bits in OCxRS, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in OCxRS A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in OCxRS register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Examples: OCxRSSET = 0x00008001 will set bits 15 and 0 in the OCxRS register. localValue = OCxRSSET will yield an undefined value. Register 16-12: OCxRSINV: Output Compare ‘x’ Secondary Compare Invert Register R/W-x Write inverts selected bits in OCxRS, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in OCxRS A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in OCxRS register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Examples: OCxRSINV = 0x00008001 will invert bits 15 and 0 in the OCxRS register. localValue = OCxRSINV will yield an undefined value. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-13 PIC32MX Family Reference Manual Register 16-13: IFS0: Interrupt Flag Status Register 0(1) R/W-0 R/W-0 R/W-0 R/W-0 I2C1SIF I2C1BIF U1TXIF U1RXIF bit 31 R/W-0 U1EIF R/W-0 SPI1RXIF R/W-0 SPI1TXIF R/W-0 SPI1EIF bit 24 R/W-0 CNIF bit 23 R/W-0 OC5IF R/W-0 IC5IF R/W-0 T5IF R/W-0 INT4IF R/W-0 OC4IF R/W-0 IC4IF R/W-0 T4IF bit 16 R/W-0 INT3IF bit 15 R/W-0 OC3IF R/W-0 IC3IF R/W-0 T3IF R/W-0 INT2IF R/W-0 OC2IF R/W-0 IC2IF R/W-0 T2IF bit 8 R/W-0 INT1IF bit 7 R/W-0 OC1IF R/W-0 IC1IF R/W-0 T1IF R/W-0 INT0IF R/W-0 CS1IF R/W-0 CS0IF R/W-0 CTIF bit 0 Legend: R = readable bit W = writable bit U = unimplemented bit, read as ‘0’ P = programmable r = reserved bit -n = bit value at POR: (‘0’, ‘1’, x = unknown) bit 22 bit 18 bit 14 bit 10 bit 6 Note 1: OC5IF: Output Compare 5 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred OC4IF: Output Compare 4 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred OC3IF: Output Compare 3 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred OC2IF: Output Compare 2 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred OC1IF: Output Compare 1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the output compare module. DS61111D-page 16-14 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-14: IEC0: Interrupt Enable Control Register 0(1) I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE bit 31 SPI1RXIE SPI1TXIE SPI1EIE bit 24 R/W-0 CNIE bit 23 R/W-0 OC5IE R/W-0 IC5IE R/W-0 T5IE R/W-0 INT4IE R/W-0 OC4IE R/W-0 IC4IE R/W-0 T4IE bit 16 R/W-0 INT3IE bit 15 R/W-0 OC3IE R/W-0 IC3IE R/W-0 T3IE R/W-0 INT2IE R/W-0 OC2IE R/W-0 IC2IE R/W-0 T2IE bit 8 R/W-0 INT1IE bit 7 R/W-0 OC1IE R/W-0 IC1IE R/W-0 T1IE R/W-0 INT0IE R/W-0 CS1IE R/W-0 CS0IE R/W-0 CTIE bit 0 Legend: R = readable bit W = writable bit U = unimplemented bit, read as ‘0’ P = programmable r = reserved bit -n = bit value at POR: (‘0’, ‘1’, x = unknown) bit 22 bit 18 bit 14 bit 10 bit 6 Note 1: OC5IE: Output Compare 5 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled OC4IE: Output Compare 4 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled OC3IE: Output Compare 3 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled OC2IE: Output Compare 2 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled OC1IE: Output Compare 1 Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the output compare module . © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-15 PIC32MX Family Reference Manual Register 16-15: IPC1: Interrupt Priority Control Register 1(1) r-x r-x r-x R/W-0 R/W-0 — — — INT1IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 INT1IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC1IP<2:0> OC1IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC1IP<2:0> IC1IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1IP<2:0> T1IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 20-18 OC1IP<2:0>: Output Compare 1 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 OC1IS<1:0>: Output Compare 1 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the output compare module . DS61111D-page 16-16 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-16: IPC2: Interrupt Priority Control Register 2(1) r-x r-x r-x R/W-0 R/W-0 — — — INT2IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 INT2IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC2IP<2:0> OC2IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC2IP<2:0> IC2IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T2IP<2:0> T2IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 20 - 18 OC2IP<2:0>: Output Compare 2 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 OC2IS<1:0>: Output Compare 2 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the output compare module . © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-17 PIC32MX Family Reference Manual Register 16-17: IPC3: Interrupt Priority Control Register 3(1) r-x r-x r-x R/W-0 R/W-0 — — — INT3IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 INT3IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC3IP<2:0> OC3IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC3IP<2:0> IC3IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T3IP<2:0> T3IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 20-18 OC3IP<2:0>: Output Compare 3 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 OC3IS<1:0>: Output Compare 3 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the output compare module . DS61111D-page 16-18 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-18: IPC4: Interrupt Priority Control Register 4(1) r-x r-x r-x R/W-0 R/W-0 — — — INT4IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 INT4IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC4IP<2:0> OC4IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC4IP<2:0> IC4IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T4IP<2:0> T4IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 20-18 OC4IP<2:0>: Output Compare 4 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 OC4IS<1:0>: Output Compare 4 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the output compare module . © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-19 PIC32MX Family Reference Manual Register 16-19: IPC5: Interrupt Priority Control Register 5(1) r-x r-x r-x R/W-0 R/W-0 — — — SPI1IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 SPI1IS<1:0> bit 24 r-x — bit 23 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC5IP<2:0> OC5IS<1:0> bit 16 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IC5IP<2:0> IC5IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T5IP<2:0> T5IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 20-18 OC5IP<2:0>: Output Compare 5 Interrupt Priority bits 111 = Interrupt priority is 7 110 = Interrupt priority is 6 101 = Interrupt priority is 5 100 = Interrupt priority is 4 011 = Interrupt priority is 3 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 OC5IS<1:0>: Output Compare 5 Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the output compare module . DS61111D-page 16-20 Preliminary © 2008 Microchip Technology Inc. Output Compare Register 16-20: T2CON: Time Base Register r-x r-x r-x r-x — — — — bit 31 Section 16. Output Compare 16 r-x r-x r-x r-x — — — — bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x r-x ON FRZ SIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r-x R/W-0 r-x TGATE TCKPS<2:0> T32 — TCS — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 15 bit 14 bit 13 bit 7 bit 6-4 bit 3 ON: TMR2 On bit 1 = Peripheral is enabled 0 = Peripheral is disabled Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation even when CPU is in Debug Exception mode Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode. SIDL: Stop in IDLE Mode bit 1 = Discontinue operation when device enters IDLE mode 0 = Continue operation even in IDLE mode TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored and reads as ‘0’ When TCS = ‘0’: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled TCKPS<2:0>: Timer Input Clock Prescale Select bits 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value T32: 32-bit Timer Mode Select bits 1 = TMR2 and TMR3 form a 32-bit timer 0 = TMR2 and TMR3 are separate 16-bit timers © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-21 PIC32MX Family Reference Manual Register 16-20: T2CON: Time Base Register (Continued) bit 1 TCS: TMR2 Clock Source Select bit 1 = External clock from T2CK pin 0 = Internal peripheral clock DS61111D-page 16-22 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-21: T2CONCLR: Time Base Register R/W-x Write clears selected bits in T2CON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in T2CON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in T2CON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: T2CONCLR = 0x00008000 will clear bit 15 in the T2CON register. Register 16-22: T2CONSET: Output Compare ‘x’ Secondary Compare Set Register R/W-x Write sets selected bits in T2CON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in T2CON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in T2CON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: T2CONSET = 0x00008000 will set bit 15 in the T2CON register. Register 16-23: T2CONINV: Output Compare ‘x’ Secondary Compare Invert Register R/W-x Write inverts selected bits in T2CON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in T2CON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in T2CON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: T2CONINV = 0x00008000 will invert bit 15 in the T2CON register. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-23 PIC32MX Family Reference Manual Register 16-24: TMR2: Timer Register R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 TMR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 TMR<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 15-0 TMR2<15:0>: Timer Count Register 16-bit mode: These bits represent the complete 16-bit timer count. 32-bit mode (Timer Type B only): Timer2 and Timer4 These bits represent the least significant half word (16 bits) of the 32-bit timer count. DS61111D-page 16-24 Preliminary © 2008 Microchip Technology Inc. Output Compare Register 16-25: TMR2CLR: Timer Clear Register Section 16. Output Compare 16 Write clears selected bits in TMR2, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in TMR2 A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in TMR2 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TMR2CLR = 0x00008001 will clear bits 15 and 0 in TMR2 register. Register 16-26: TMR2SET: Timer Set Register Write sets selected bits in TMR2, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in TMR2 A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in TMR2 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TMR2SET = 0x00008001 will set bits 15 and 0 in TMR2 register. Register 16-27: TMR2INV: Timer Invert Register Write inverts selected bits in TMR2, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in TMR2 A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in TMR2 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TMR2INV = 0x00008001 will invert bits 15 and 0 in TMR2 register. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-25 PIC32MX Family Reference Manual Register 16-28: PR2: Period Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 PR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 PR<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-0 PR<31:16>: Unimplemented PR<15:0>: 16-bit Timer2 period match value. Provides lower half of the 32-bit period match value when Timer2 and Timer3 are configured to form a 32-bit timer. DS61111D-page 16-26 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-29: PR2CLR: Period 2 Clear Register R/W-x Write clears selected bits in PR2, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PR2 A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PR2 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PR2CLR = 0x00008001 will clear bits 15 and 0 in the PR2 register. Register 16-30: PR2SET: Period 2 Set Register R/W-x Write sets selected bits in PR2, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PR2 A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PR2 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PR2SET = 0x00008001 will set bits 15 and 0 in the PR2 register. Register 16-31: PR2INV: Period 2 Invert Register R/W-x Write inverts selected bits in PR2, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PR2 A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PR2 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PR2INV = 0x00008001 will invert bits 15 and 0 in the PR2 register. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-27 PIC32MX Family Reference Manual Register 16-32: T3CON: Time Base Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 R/W-0 R/W-0 r-x r-x r-x r-x r-x ON FRZ SIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 r-0 TGATE TCKPS<2:0> — bit 7 r-x R/W-0 r-x — TCS — bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 15 bit 14 bit 13 bit 7 bit 6-4 bit 1 ON: TMR3 On bit 1 = Peripheral is enabled 0 = Peripheral is disabled Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU is in Debug Exception mode 0 = Continue operation even when CPU is in Debug Exception mode Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode. SIDL: Stop in IDLE Mode bit 1 = Discontinue operation when device enters IDLE mode 0 = Continue operation even in IDLE mode TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored and reads ‘0’ When TCS = ‘0’: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled TCKPS<2:0>: Timer Input Clock Prescale Select bits 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value TCS: TMR3 Clock Source Select bit 1 = External clock from T3CK pin 0 = Internal peripheral clock DS61111D-page 16-28 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-33: T3CONCLR: Time Base Register R/W-x Write clears selected bits in T3CON, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in T3CON A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in T3CON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: T3CONCLR = 0x00008000 will clear bit 15 in the T3CON register. Register 16-34: T3CONSET: Output Compare ‘x’ Secondary Compare Set Register R/W-x Write sets selected bits in T3CON, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in T2CON A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in T3CON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: T3CONSET = 0x00008000 will set bit 15 in the T3CON register. Register 16-35: T3CONINV: Output Compare ‘x’ Secondary Compare Invert Register R/W-x Write inverts selected bits in T3CON, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in T3CON A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in T3CON register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: T3CONINV = 0x00008000 will invert bit 15 in the T3CON register. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-29 PIC32MX Family Reference Manual Register 16-36: TMR3: Timer Register R/W-0 R/W-0 R/W-0 bit 15 R/W-0 R/W-0 TMR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 TMR<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 15-0 TMR3<15:0>: Timer Count Register 16-bit mode: These bits represent the complete 16-bit timer count. 32-bit mode (Timer Type B only): Timer3 and Timer5 These bits represent the most significant half word (16 bits) of the 32-bit timer count. DS61111D-page 16-30 Preliminary © 2008 Microchip Technology Inc. Output Compare Register 16-37: TMR3CLR: Timer Clear Register Section 16. Output Compare 16 Write clears selected bits in TMR3, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in TMR3 A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in TMR3 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TMR3CLR = 0x00008001 will clear bits 15 and 0 in TMR3 register. Register 16-38: TMR3SET: Timer Set Register Write sets selected bits in TMR3, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in TMR3 A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in TMR3 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TMR3SET = 0x00008001 will set bits 15 and 0 in TMR3 register. Register 16-39: TMR3INV: Timer Invert Register Write inverts selected bits in TMR3, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in TMR3 A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in TMR3 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: TMR3INV = 0x00008001 will invert bits 15 and 0 in TMR3 register. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-31 PIC32MX Family Reference Manual Register 16-40: PR3: Period 3 Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x — bit 23 r-x r-x r-x r-x r-x r-x r-x — — — — — — — bit 16 R/W-0 bit 15 R/W-0 R/W-0 R/W-0 R/W-0 PR<15:8> R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 PR<7:0> R/W-0 R/W-0 R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-0 PR<31:16>: Unimplemented PR<15:0>: 16-bit Timer3 period match value. Provides upper half of the 32-bit period match value when Timer 2 and Timer3 are configured to form a 32-bit timer. DS61111D-page 16-32 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Register 16-41: PR3CLR: Period 3 Clear Register R/W-x Write clears selected bits in PR3, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in PR3 A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in PR3 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PR3CLR = 0x8001 will clear bits 15 and 0 in the PR3 register. Register 16-42: PR3SET: Period 3 Set Register R/W-x Write sets selected bits in PR3, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in PR3 A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in PR3 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PR3SET = 0x00008001 will set bits 15 and 0 in the PR3 register. Register 16-43: PR3INV: Period 3 Invert Register R/W-x Write inverts selected bits in PR3, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in PR3 A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in PR3 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: PR3INV = 0x00008001 will invert bits 15 and 0 in the PR3 register. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-33 PIC32MX Family Reference Manual 16.3 OPERATION Each Output Compare module has the following modes of operation: • Single Compare Match mode - With output drive high - With output drive low - With output drive toggles • Dual Compare Match mode - With single output pulse - With continuous output pulses • Simple Pulse-Width Modulation mode - Without fault protection input - With fault protection input Notes: It is required that the user turn off the Output Compare module (i.e., clear OCM<2:0> (OCxCON<2:0>)) before switching to a new mode. Changing modes while the module is in operation may produce unexpected results. In this section, a reference to any SFRs associated with the selected timer source is indicated by a ‘y’ suffix. For example, PR2 is the Period register for the selected timer source, while TyCON is the Timer Control register for the selected timer source. 16.3.1 Single Compare Match Mode When control bits OCM<2:0> (OCxCON<2:0>) are set to ‘001’, ‘010’ or ‘011’, the selected output compare channel is configured for one of three Single Output Compare Match modes. The compare time base must also be enabled. In the Single Compare mode, the OCxR register is loaded with a value and is compared to the selected incrementing timer register, TMRy. On a compare match event, one of the following events will take place: • Compare forces OCx pin high; initial state of pin is low. Interrupt is generated on the single compare match event. • Compare forces OCx pin low; initial state of pin is high. Interrupt is generated on the single compare match event. • Compare toggles OCx pin. Toggle event is continuous and an interrupt is generated for each toggle event. DS61111D-page 16-34 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 16.3.1.1 Compare Mode Output Driven High To configure the Output Compare module for this mode, set control bits OCM<2:0> = ‘001’. The compare time base must also be enabled. Once this Compare mode has been enabled, the output pin, OCx, will be driven low and remain low until a match occurs between the TMRy and OCxR registers. Please note the following key timing events (refer to Figure 16-2): • The OCx pin is driven high one peripheral clock after the compare match occurs between the compare time base and the OCxR register. The OCx pin will remain high until a mode change has been made or the module is disabled. • The compare time base will count up to the value contained in the associated period register and then reset to 0x0000 on the next PBCLK. • The respective channel interrupt flag, OCxIF (refer to the IFS0 register for the position of the interrupt flag bit for each of the Output Compare channels), is asserted when the OCx pin is driven high. Figure 16-2: Single Compare Mode: Set OCx High on Compare Match Event (16-Bit Mode) 1 PBCLK Period TMRy PRy 3000 4000 3001 3002 3003 3004 3FFF 4000 0000 0001 TMRy Resets Here OCxR 3002 OCx pin OCxIF Cleared by User Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. Figure 16-3: Single Compare Mode: Set OCx High on Compare Match Event (32-Bit Mode) 1 PBCLK Period TMRy 0003: 0000 0003: 0001 0003: 0002 0003: 0003 0003: 0004 PRy OCxR 0004: 0000 0003: 0002 0003: FFFF 0004: 0000 0000: 0000 0000: 0001 TMRy Resets Here OCx pin Cleared by User OCxIF Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-35 PIC32MX Family Reference Manual 16.3.1.2 Compare Mode Output Driven Low To configure the output compare module for this mode, set control bits OCM<2:0> = ‘010’. The compare time base must also be enabled. Once this Compare mode has been enabled, the output pin, OCx, will be driven high and remain high until a match occurs between the Timer and OCxR registers. Please note the following key timing events (refer to Figure 16-4): • The OCx pin is driven low one PBCLK after the compare match occurs between the compare time base and the OCxR register. The OCx pin will remain low until a mode change has been made or the module is disabled. • The compare time base will count up to the value contained in the associated period register and then reset to 0x0000 on the next PBCLK . • The respective channel interrupt flag, OCxIF, is asserted when the OCx pin is driven low. Figure 16-4: Single Compare Mode: Force OCx Low on Compare Match Event (16-Bit Mode) 1 PBCLK Period TMRy 47FE PRy 4C00 47FF 4800 4801 4802 4BFF 4C00 0000 0001 TMRy Resets Here OCxR OCx pin 4800 OCxIF Cleared by User Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. Figure 16-5: Single Compare Mode: Set OCx Low on Compare Match Event (32-Bit Mode) 1 PBCLK Period TMRy 0003: 0000 0003: 0001 0003: 0002 0003: 0003 0003: 0004 PRy OCxR 0004: 0000 0003: 0002 0003: FFFF 0004: 0000 0000: 0000 0000: 0001 TMRy Resets Here OCx pin OCxIF Cleared by User Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. DS61111D-page 16-36 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 16.3.1.3 Single Compare Mode Toggle Output To configure the Output Compare module for this mode, set control bits OCM<2:0> = ‘011’. In addition, Timer2 or Timer3 must be selected and enabled. Once this Compare mode has been enabled, the output pin, OCx, will be initially driven low and then toggle on each and every subsequent match event between the Timer and OCxR registers. Please note the following key timing events (refer to Figure 16-6 and Figure 16-8): • The OCx pin is toggled one PBCLK after the compare match occurs between the compare time base and the OCxR register. The OCx pin will remain at this new state until the next toggle event, or until a mode change has been made or the module is disabled. • The compare time base will count up to the contents in the period register and then reset to 0x0000 on the next PBCLK . • The respective channel interrupt flag, OCxIF, is asserted when the OCx pin is toggled. Note: The internal OCx pin output logic is set to a logic ‘0’ on a device Reset. However, the operational OCx pin state for the Toggle mode can be set by the user software. Example 16-1 shows a code example for defining the desired initial OCx pin state in the Toggle mode of operation. Figure 16-6: Single Compare Mode: Toggle Output on Compare Match Event (16-Bit Mode) 1 PBCLK Period TMRy 0500 PRy 0600 0501 0502 0600 0000 0001 TMRy Resets Here 0500 OCxR OCx pin 0500 OCxIF Cleared by User Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. 0501 0502 Figure 16-7: Single Compare Mode: Toggle Output on Compare Match Event (32-Bit Mode) 1 PBCLK Period TMRy 0005: 0000 0005: 0001 0005: 0002 PRy OCxR 0006: 0000 0005: 0000 0006: 0000 0000: 0000 0000: 0001 TMRy Resets Here 0005: 0000 0005: 0001 OCx pin Cleared by User OCxIF Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-37 PIC32MX Family Reference Manual Figure 16-8: Single Compare Mode: Toggle Output on Compare Match Event (PRy = OCxR, 16-Bit Mode) 1 PBCLK Period TMRy 0500 PRy 0500 0000 0001 TMRy Resets Here 0500 0000 0001 TMRy Resets Here 0500 OCxR OCx pin 0500 OCxIF Cleared by User Cleared by User Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. 0000 0001 Figure 16-9: Single Compare Mode: Toggle Output on Compare Match Event (PRy = OCxR, 32-Bit Mode) 1 PBCLK Period TMRy 0005: 0000 0000: 0000 0000: 0001 PRy OCxR 0005: 0000 0005: 0000 0005: 0000 0000: 0000 0000: 0001 TMRy Resets Here 0005: 0000 0000: 0000 OCx pin OCxIF Cleared by User Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. Cleared by User Example 16-1: Compare Mode Toggle Mode Pin State Setup (16-Bit Mode) // The following code example illustrates how to define the initial // OC1 pin state for the output compare toggle mode of operation. // Toggle mode with initial OC1 pin state set low OC1CON = 0x0001; OC1CONSET = 0x8000; // Configure module for OC1 pin low, toggle high // Enable OC1 module DS61111D-page 16-38 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare Example 16-2: Compare Mode Toggle Mode Pin State Setup (32-Bit Mode) // The following code example illustrates how to define the initial // OC1 pin state for the output compare toggle mode of operation. // Toggle mode with initial OC1 pin state set low OC1CON = 0x0021; OC1CONSET = 0x8000; // Configure module for OC1 pin low, toggle high, // 32-bit mode // Enable OC1 module 16 Example 16-3 shows example code for the configuration and interrupt service of the Single Compare mode toggle event. Example 16-3: Compare Mode Toggle Setup and Interrupt Servicing (16-Bit Mode) // The following code example will set the Output Compare 1 module // for interrupts on the toggle event and select Timer2 as the clock // source for the compare time base. T2CON = 0x0010; // Configure Timer2 for a prescaler of 2 OC1CON = 0x0000; OC1CON = 0x0003; OC1R = 0x0500; PR2 = 0x0500; // Turn off OC1 while doing setup. // Configure for compare toggle mode // Initialize Compare Register 1 // Set period IFS0CLR = 0x0040; IEC0SET = 0x040; IPC1SET = 0x001C0000; IPC1SET = 0x00030000; // Configure int // Clear the OC1 interrupt flag // Enable OC1 interrupt // Set OC1 interrupt priority to 7, // the highest level // Set Subpriority to 3, maximum T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable Timer 2 // Enable OC1 // Example code for Output Compare 1 ISR: void __ISR(_OUTPUT_COMPARE_1_VECTOR, ipl7) OC1_IntHandler (void) { // insert user code here IFS0CLR = 0x0040; // Clear the OC1 interrupt flag } © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-39 PIC32MX Family Reference Manual Example 16-4: Compare Mode Toggle Setup and Interrupt Servicing (32-Bit Mode) // The following code example will set the Output Compare 1 module // for interrupts on the toggle event and select the Timer2/Timer3 pair as // the 32-bit as the clock source for the compare time base. T2CON = 0x0018; // Configure Timer2 for 32-bit operation // with a prescaler of 2. The Timer2/Timer3 // pair is accessed via registers associated // with the Timer2 register OC1CON = 0x0000; OC1CON = 0x0023; OC1R = 0x00500000; PR2 = 0x00500000; // Turn off OC1 while doing setup. // Configure for compare toggle mode // Initialize Compare Register 1 // Set period (PR2 is now 32-bits wide) IFS0CLR = 0x00000040; IFS0SET = 0x00000040; IPC1SET = 0x001C0000; IPC1SET = 0x00030000; // configure int // Clear the OC1 interrupt flag // Enable OC1 interrupt // Set OC1 interrupt priority to 7, // the highest level // Set Subpriority to 3, maximum T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable Timer2 // Enable OC1 // Example code for Output Compare 1 ISR: void__ISR (_OUTPUT_COMPARE_1_VECTOR, ipl7) OC1_IntlHandler (void) { // insert user code here IFS0CLR = 0x0040; // Clear the OC1 interrupt flag } DS61111D-page 16-40 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 16.3.2 Dual Compare Match Mode When control bits OCM<2:0> = 100 or ‘101’ (OCxCON<2:0>), the selected output compare channel is configured for one of two Dual Compare Match modes: • Single Output Pulse mode • Continuous Output Pulse mode In the Dual Compare mode, the module uses both the OCxR and OCxRS registers for the compare match events. The OCxR register is compared against the incrementing timer count, TMRy, and the leading (rising) edge of the pulse is generated at the OCx pin on a compare match event. The OCxRS register is then compared to the same incrementing timer count, TMRy, and the trailing (falling) edge of the pulse is generated at the OCx pin on a compare match event. 16.3.2.1 Dual Compare Mode: Single Output Pulse To configure the Output Compare module for the Single Output Pulse mode, set control bits OCM<2:0> = 100. In addition, the compare time base must be selected and enabled. Once this mode has been enabled, the output pin, OCx, will be driven low and remain low until a match occurs between the time base and OCxR registers. Please note the following key timing events (refer to Figure 16-10 and Figure 16-12): • The OCx pin is driven high one peripheral clock after the compare match occurs between the compare time base and the OCxR register. The OCx pin will remain high until the next match event occurs between the time base and the OCxRS register. At this time, the pin will be driven low. The OCx pin will remain low until a mode change has been made or the module is disabled. • The compare time base will count up to the value contained in the associated period register and then reset to 0x0000 on the next instruction clock. • If the time base period register contents are less than the OCxRS register contents, then no falling edge of the pulse is generated. The OCx pin will remain high until OCxRS <= PR2, or a mode change or Reset condition has occurred. • The respective channel interrupt flag, OCxIF, is asserted when the OCx pin is driven low (falling edge of single pulse). Figure 16-10 depicts the General Dual Compare mode generating a single output pulse. Figure 16-12 depicts another timing example where OCxRS > PR2. In this example, no falling edge of the pulse is generated because the compare time base resets before counting up to 0x4100. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-41 PIC32MX Family Reference Manual Figure 16-10: Dual Compare Mode (16-Bit Mode) TMRy PRy OCxR OCxRS 3000 4000 3000 3003 1 PBCLK Period 3001 3002 3003 3004 3005 3006 4000 TMRy Resets Here OCx pin OCxIF Cleared by User Note 1: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. 2: OCxR = Compare Register; OCxRS = Secondary Compare Register. 0000 Figure 16-11: Dual Compare Mode (32-Bit Mode) TMRy 0003: 0000 PRy OCxR OCxRS 0004: 0000 0003: 0000 0003: 0003 1 PBCLK Period 0003: 0001 0003: 0002 0003: 0003 0003: 0004 0003: 0005 0003: 0006 0004: 0000 TMRy Resets Here 0000: 0000 OCx pin OCxIF Cleared by User Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. DS61111D-page 16-42 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare Figure 16-12: Dual Compare Mode: Single Output Pulse (OCxRS > PRy, 16-Bit Mode) TMRy PRy OCxR OCxRS 3000 4000 3000 4100 3001 1 PBCLK Period 3002 3003 3004 3005 3006 4000 TMRy Resets Here 0000 OCx pin OCxIF Compare Interrupt does not occur Note 1: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. 2: OCxR = Compare Register; OCxRS = Secondary Compare Register. 16 Figure 16-13: Dual Compare Mode: Single Output Pulse (OCxRS > PRy, 32-Bit Mode) 1 PBCLK Period TMRy 0003: 0000 PRy OCxR OCxRS 0004: 0000 0003: 0000 0004: 1000 0003: 0001 0003: 0002 0003: 0003 0003: 0004 0003: 0005 0003: 0006 0004: 0000 TMRy Resets Here 0000: 0000 OCx pin OCxIF No Compare Interrupt is generated Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-43 PIC32MX Family Reference Manual 16.3.2.2 Setup for Single Output Pulse Generation When control bits OCM<2:0> (OCxCON<2:0>) are set to ‘100’, the selected output compare channel initializes the OCx pin to the low state and generates a single output pulse. To generate a single output pulse, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): 1. Determine the peripheral clock cycle time. 2. Calculate the time to the rising edge of the output pulse relative to the TMRy start value (0x0000). 3. Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. 4. Write the values computed in steps 2 and 3 above into the compare register, OCxR, and the secondary compare register, OCxRS, respectively. 5. Set the timer period register, PRy, to value equal to or greater than value in OCxRS, the secondary compare register. 6. Set OCM<2:0> = 100 and the OCTSEL (OCxCON<3>) bit to the desired timer source. The OCx pin state will now be driven low. 7. Set the ON (TyCON<15>) bit to ‘1’, to enable the timer. 8. Upon the first match between TMRy and OCxR, the OCx pin will be driven high. 9. When the incrementing timer, TMRy, matches the secondary compare register, OCxRS, the second and trailing edge (high-to-low) of the pulse is driven onto the OCx pin. No additional pulses are driven onto the OCx pin and it remains at low. As a result of the second compare match event, the OCxIF interrupt flag bit is set, which will result in an interrupt (if it is enabled by setting the OCxIE bit). For further information on peripheral interrupts, refer to Section 8. “Interrupts”. 10. To initiate another single pulse output, change the timer and compare register settings, if needed, and then issue a write to set the OCM<2:0> (OCxCON<2:0>) bits to ‘100’. Disabling and re-enabling of the timer and clearing the TMRy register are not required, but may be advantageous for defining a pulse from a known event time boundary. The Output Compare module does not have to be disabled after the falling edge of the output pulse. Another pulse can be initiated by rewriting the value of the OCxCON register. DS61111D-page 16-44 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare Examples 16-5 and 16-6 show example code for configuration of the single output pulse event. Example 16-5: Single Output Pulse Setup and Interrupt Servicing (16-Bit Mode) // The following code example will set the Output Compare 1 module // for interrupts on the single pulse event and select Timer2 // as the clock source for the compare time base. T2CON = 0x0010; // Configure Timer2 for a prescaler of 2 OC1CON = 0x0000; OC1CON = 0x0004; OC1R = 0x3000; OC1RS = 0x3003; PR2 = 0x3003; // Turn off OC1 while doing setup. // Configure for single pulse mode // Initialize primary Compare Register // Initialize secondary Compare Register // Set period (PR2 is now 32-bits wide) IFS0CLR = 0x00000040; IFS0SET = 0x00000040; IPC1SET = 0x001C0000; IPC1SET = 0x00030000; // configure int // Clear the OC1 interrupt flag // Enable OC1 interrupt // Set OC1 interrupt priority to 7, // the highest level // Set Subpriority to 3, maximum T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable Timer2 // Enable OC1 // Example code for Output Compare 1 ISR: void__ISR(_OUTPUT_COMPARE_1_VECTOR, ipl7) OC1_IntHandler (void) { // insert user code here IFS0CLR = 0x0040; // Clear the OC1 interrupt flag } 16 © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-45 PIC32MX Family Reference Manual Example 16-6: Single Output Pulse Setup and Interrupt Servicing (32-Bit Mode) // The following code example will set the Output Compare 1 module // for interrupts on the single pulse event and select Timer2 // as the clock source for the compare time base. T2CON = 0x0018; OC1CON = 0x0000; OC1CON = 0x0004; OC1R = 0x00203000; OC1RS = 0x00203003; PR2 = 0x00500000; // Configure Timer2 for 32-bit operation // with a prescaler of 2. The Timer2/Timer3 // pair is accessed via registers associated // with the Timer2 register // Turn off OC1 while doing setup. // Configure for single pulse mode // Initialize primary Compare Register // Initialize secondary Compare Register // Set period (PR2 is now 32-bits wide) IFS0CLR = 0x00000040; IFS0SET = 0x00000040; IPC1SET = 0x001C0000; IPC1SET = 0x00030000; // configure int // Clear the OC1 interrupt flag // Enable OC1 interrupt // Set OC1 interrupt priority to 7, // the highest level // Set Subpriority to 3, maximum T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable Timer2 // Enable OC1 // Example code for Output Compare 1 ISR: void__ISR(_OUTPUT_COMPARE_1_VECTOR, ipl7) OC1_IntHandler (void) { // insert user code here IFS0CLR = 0x0040; // Clear the OC1 interrupt flag } DS61111D-page 16-46 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16.3.2.3 Special Cases for Dual Compare Mode Generating a Single Output Pulse Depending on the relationship of the OCxR, OCxRS and PRy values, the output compare module has a few unique conditions which should be understood. These special conditions are specified in Table 16-2, along with the resulting behavior of the module. Table 16-2: Special Cases for Dual Compare Mode Generating a Single Output Pulse SFR Logical Relationship Special Conditions Operation Output at OCx PRy >= OCxRS and OCxRS > OCxR OCxR = 0 Initialize TMRy = 0 In the first iteration of the TMRy counting from 0x0000 up to Pulse will be PRy, the OCx pin remains low; no pulse is generated. After the delayed by the TMRy resets to zero (on period match), the OCx pin goes high value in the PRy due to match with OCxR. Upon the next TMRy to OCxRS register, match, the OCx pin goes low and remains there. The OCxIF depending on bit will be set as a result of the second compare. setup There are two alternative initial conditions to consider: a. Initialize TMRy = 0 and set OCxR >= 1 b. Initialize TMRy = PRy (PRy > 0) and set OCxR = 0 PRy >= OCxR and OCxR >= OCxRS OCxR >= 1 and PRy >= 1 TMRy counts up to OCxR and on a compare match event (i.e., Pulse TMRy = OCxR), the OCx pin is driven to a high state. TMRy then continues to count and eventually resets on period match (i.e., PRy =TMRy). The timer then restarts from 0x0000 and counts up to OCxRS. On a compare match event (i.e., TMRy = OCxRS), the OCx pin is driven to a low state. The OCxIF bit will be set as a result of the second compare. OCxRS > PRy and PRy >= OCxR None Only the rising edge will be generated at the OCx pin. The OCxIF will not be set. Rising edge/ transition to high OCxR > PRy None Unsupported mode; timer resets prior to match condition. Remains low Note 1: In all the cases considered herein, the TMRy register is assumed to be initialized to 0x0000. 2: OCxR = Compare Register, OCxRS = Secondary Compare Register, TMRy = Timery Count and PRy = Timery Period Register. 16 © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-47 PIC32MX Family Reference Manual 16.3.2.4 Dual Compare Mode: Continuous Output Pulses To configure the output compare module for this mode, set control bits OCM<2:0> = ‘101’. In addition, the compare time base must be selected and enabled. Once this mode has been enabled, the output pin, OCx, will be driven low and remain low until a match occurs between the compare time base and OCxR register. Please note the following key timing events (refer to Figure 16-14 and Figure 16-16): • The OCx pin is driven high one PBCLK after the compare match occurs between the compare time base and OCxR register. The OCx pin will remain high until the next match event occurs between the time base and the OCxRS register, at which time the pin will be driven low. This pulse generation sequence of a low-to-high and high-to-low edge will repeat on the OCx pin without further user intervention. • Continuous pulses will be generated on the OCx pin until a mode change is made or the module is disabled. • The compare time base will count up to the value contained in the associated period register and then reset to 0x0000 on the next instruction clock. • If the compare time base period register value is less than the OCxRS register value, then no falling edge is generated. The OCx pin will remain high until OCxRS <= PRy, a mode change is made, or the device is reset. • The respective channel interrupt flag, OCxIF, is asserted when the OCx pin is driven low (falling edge of single pulse). General Dual Compare mode generating a continuous output pulse is illustrated in Figure 16-14. Figure 16-16 depicts another timing example where OCxRS > PRy. In this example, no falling edge of the pulse is generated, because the time base will reset before counting up to the contents of OCxRS. Figure 16-14: Dual Compare Mode: Continuous Output Pulse (PRy = OCxRS, 16-Bit Mode) 1 PBCLK Period TMRy PRy 3000 3002 3001 3002 0000 0001 3000 3001 TMRy Resets Here due to PRx match 3002 0000 0001 TMRy Resets Here ... OCxR 3000 OCxRS 3002 3000 OCx pin OCxIF Cleared by User Cleared by User Note 1: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. 2: OCxR = Compare Register; OCxRS = Secondary Compare Register. DS61111D-page 16-48 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 Figure 16-15: Dual Compare Mode: Continuous Output Pulse (PRy = OCxRS, 32-Bit Mode) 1 PBCLK Period TMRy 0003: 0000 0003: 0001 TMRy Resets Here PRy 0003: 0001 OCxR 0003: 0000 OCxRS 0003: 0001 0000: 0000 0000: 0001 0003: 0000 0003: 0001 TMRy Resets Here 0000: 0000 0000: 0001 0000: 0002 OCx pin OCxIF Cleared by User Cleared by User Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. Figure 16-16: Dual Compare Mode: Continuous Output Pulse (PRy = OCxRS, 16-Bit Mode) 1 PBCLK Period TMRy PRy 3000 3001 3002 3003 3003 0000 3000 TMRy Resets Here 3001 3002 3003 0000 3000 TMRy Resets Here OCxR 3000 OCxRS 3003 OCx pin OCxIF Cleared by User Note 1: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. 2: OCxR = Compare Register; OCxRS = Secondary Compare Register. Cleared by User © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-49 PIC32MX Family Reference Manual 16.3.2.5 Setup for Continuous Output Pulse Generation When control bits OCM<2:0> (OCxCON<2:0>) are set to ‘101’, the selected output compare channel initializes the OCx pin to the low state and generates output pulses on each and every compare match event. For the user to configure the module for the generation of a continuous stream of output pulses, the following steps are required (these steps assume the timer source is initially turned off, but this is not a requirement for the module operation): 1. Determine the peripheral clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. 2. Calculate the time to the rising edge of the output pulse, relative to the TMRy start value (0x0000). 3. Calculate the time to the falling edge of the pulse, based on the desired pulse width and the time to the rising edge of the pulse. 4. Write the values computed in step 2 and 3 above into the compare register, OCxR, and the secondary compare register, OCxRS, respectively. 5. Set the timer period register, PRy, to a value equal to or greater than the value in OCxRS, the secondary compare register. 6. Set OCM<2:0> = ‘101’ and the OCTSEL (OCxCON<3>) bit to the desired timer source (for 16-bit mode only). The OCx pin state will now be driven low. 7. Enable the compare time base by setting the TON (TyCON<15>) bit to ‘1’. 8. Upon the first match between TMRy and OCxR, the OCx pin will be driven high. 9. When the compare time base, TMRy, matches the secondary compare register, OCxRS, the second and trailing edge (high-to-low) of the pulse is driven onto the OCx pin. 10. As a result of the second compare match event, the OCxIF interrupt flag bit is set. 11. When the compare time base and the value in its respective period register match, the TMRy register resets to 0x0000 and resumes counting. 12. Steps 8 through 11 are repeated, and a continuous stream of pulses is generated, indefinitely. The OCxIF flag (refer to the IF0 register for the bit position of each channel’s interrupt flag) is set on each OCxRS-TMRy compare match event. DS61111D-page 16-50 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare Example 16-7 shows example code for configuration of the continuous output pulse event. Example 16-7: Continuous Output Pulse Setup and Interrupt Servicing (16-Bit Mode) // The following code example will set the Output Compare 1 module // for interrupts on the continuous pulse event and select Timer2 // as the clock source for the compare time-base. T2CON = 0x0010; // Configure Timer2 for a prescaler of 2 OC1CON = 0x0000; OC1CON = 0x0005; OC1R = 0x3000; OC1RS = 0x3003; PR2 = 0x5000; // disable OC1 module // Configure OC1 module for Pulse output // Initialize Compare Register 1 // Initialize Secondary Compare Register 1 // Set period 16 IFS0CLR = 0x00000040; IFS0SET = 0x00000040; IPC1SET = 0x001C0000; IPC1SET = 0x00030000; // configure int // Clear the OC1 interrupt flag // Enable OC1 interrupt // Set OC1 interrupt priority to 7, // the highest level // Set Subpriority to 3, maximum T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable Timer2 // Enable OC1 // Example code for Output Compare 1 ISR: void__ISR(_OUTPUT_COMPARE_1_VECTOR, ipl7) OC1_IntHandler (void) { // insert user code here IFS0CLR= 0x0040; // Clear the OC1 interrupt flag } © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-51 PIC32MX Family Reference Manual Example 16-8: Continuous Output Pulse Setup and Interrupt Servicing (32-Bit Mode) // The following code example will set the Output Compare 1 module // for interrupts on the continuous pulse event and select Timer2 // as the clock source for the compare time-base. T2CON = 0x0018; // Configure Timer2 for 32-bit operation // with a prescaler of 2. The Timer2/Timer3 // pair is accessed via registers associated // with the Timer2 register OC1CON = 0x0000; OC1CON = 0x0005; OC1R = 0x3000; OC1RS = 0x3003; PR2 = 0x00500000; // disable OC1 module // Configure OC1 module for Pulse output // Initialize Compare Register 1 // Initialize Secondary Compare Register 1 // Set period (PR2 is now 32-bits wide) IFS0CLR = 0x00000040; IFS0SET = 0x00000040; IPC1SET = 0x001C0000; IPC1SET = 0x00030000; // configure int // Clear the OC1 interrupt flag // Enable OC1 interrupt // Set OC1 interrupt priority to 7, // the highest level // Set Subpriority to 3, maximum T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable Timer2 // Enable OC1 // Example code for Output Compare 1 ISR: void__ISR(_OUTPUT_COMPARE_1_VECTOR, ipl7) OC1_IntHandler (void) { // insert user code here IFS0CLR = 0x0040; // Clear the OC1 interrupt flag } DS61111D-page 16-52 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16.3.2.6 Special Cases for Dual Compare Mode Generating Continuous Output Pulses Depending on the relationship of the OCxR, OCxRS and PRy values, the output compare module may not provide the expected results. These special cases are specified in Table 16-3, along with the resulting behavior of the module. Table 16-3: Special Cases for Dual Compare Mode Generating Continuous Output Pulses SFR Logical Relationship Special Conditions Operation Output at OCx PRy >= OCxRS and OCxRS > OCxR OCxR = 0 Initialize TMRy = 0 In the first iteration of the TMRy counting from 0x0000 up Continuous pulses with to PRy, the OCx pin remains low; no pulse is generated. the first pulse delayed After the TMRy resets to zero (on period match), the OCx by the value in the PRy pin goes high. Upon the next TMRy to OCxRS match, the register, depending on OCx pin goes low. If OCxR = 0 and PRy = OCxRS, the pin setup. will remain low for one clock cycle, then be driven high until the next TMRy to OCxRS match. The OCxIF bit will be set as a result of the second compare. There are two alternative initial conditions to consider: a. Initialize TMRy = 0 and set OCxR >= 1 b. Initialize TMRy = PRy (PRy > 0) and set OCxR = 0 PRy >= OCxR and OCxR >= OCxRS OCxR >= 1 and PRy >= 1 TMRy counts up to OCxR and on a compare match event Continuous pulses (i.e., TMRy = OCxR), the OCx pin is driven to a high state. TMRy then continues to count and eventually resets on period match (i.e., PRy =TMRy). The timer then restarts from 0x0000 and counts up to OCxRS. On a compare match event (i.e., TMRy = OCxR), the OCx pin is driven to a low state. The OCxIF bit will be set as a result of the second compare. OCxRS > PRy and PRy >= OCxR None Only one transition will be generated at the OCx pin until the OCxRS register contents have been changed to a value less than or equal to the period register contents (PRy). OCxIF is not set until then. Rising edge/ transition to high OCxR > PRy None Unsupported mode; Timer resets prior to match condition. Remains low Note 1: In all the cases considered herein, the TMRy register is assumed to be initialized to 0x0000. 2: OCxR = Compare Register, OCxRS = Secondary Compare Register, TMRy = Timery Count and PRy = Timery Period Register. 16 © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-53 PIC32MX Family Reference Manual 16.3.3 Pulse Width Modulation Mode When control bits OCM<2:0> (OCxCON<2:0>) are set to ‘110’ or ‘111’, the selected output compare channel is configured for the PWM (Pulse-Width Modulation) mode of operation. The following two PWM modes are available: • PWM without Fault Protection Input • PWM with Fault Protection Input The OCFA or OCFB Fault input pin is utilized for the second PWM mode. In this mode, an asynchronous logic level ‘0’ on the OCFx pin will cause the selected PWM channel to be shut down. (Refer to 16.3.3.1 “PWM with Fault Protection Input Pin”.) In PWM mode, the OCxR register is a read-only slave duty cycle register and OCxRS is a buffer register that is written by the user to update the PWM duty cycle. On every timer to period register match event (end of PWM period), the duty cycle register, OCxR, is loaded with the contents of OCxRS. The TyIF interrupt flag is asserted at each PWM period boundary. The following steps should be taken when configuring the output compare module for PWM operation: 1. Set the PWM period by writing to the selected timer period register (PRy). 2. Set the PWM duty cycle by writing to the OCxRS register. 3. Write the OxCR register with the initial duty cycle. 4. Enable interrupts, if required, for the timer and output compare modules. The output compare interrupt is required for PWM Fault pin utilization. 5. Configure the Output Compare module for one of two PWM Operation modes by writing to the Output Compare mode bits, OCM<2:0> (OCxCON<2:0>). 6. Set the TMRy prescale value and enable the time base by setting TON (TxCON<15>) = ‘1’. Note: The OCxR register should be initialized before the Output Compare module is first enabled. The OCxR register becomes a read-only duty cycle register when the module is operated in the PWM modes. The value held in OCxR will become the PWM duty cycle for the first PWM period. The contents of the duty cycle buffer register, OCxRS, will not be transferred into OCxR until a time base period match occurs. An example PWM output waveform is shown in Figure 16-17. Figure 16-17: PWM Output Waveform Period = (PRy + 1) Duty Cycle = (OCxRS ) 1 2 3 1 Timery is cleared and the new duty cycle value is loaded from OCxRS into OCxR. 2 Timer value equals the value in the OCxR register; OCx Pin is driven low. 3 Timer overflow; value from OCxRS is loaded into OCxR; OCx pin is driven high. TyIF interrupt flag is asserted. DS61111D-page 16-54 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 16.3.3.1 PWM with Fault Protection Input Pin When the Output Compare mode bits, OCM<2:0> (OCxCON<2:0>), are set to ‘111’, the selected output compare channel is configured for the PWM mode of operation. All functions described in 16.3.3 “Pulse Width Modulation Mode” apply, with the addition of input Fault protection. Fault protection is provided via the OCFA and OCFB pins. The OCFA pin is associated with the output compare channels 1 through 4, while the OCFB pin is associated with the output compare channel 5. If a logic ‘0’ is detected on the OCFA/OCFB pin, the selected PWM output pin(s) are placed in the high-impedance state. The user may elect to provide a pull-down or pull-up resistor on the PWM pin to provide for a desired state if a Fault condition occurs. The shutdown of the PWM output is immediate and is not tied to the device clock source. This state will remain until the following conditions are met: • The external Fault condition has been removed • The PWM mode is re-enabled by writing to the appropriate mode bits, OCM<2:0> (OCxCON<2:0>) As a result of the Fault condition, the respective interrupt flag, OCxIF bit, is asserted and an interrupt will be generated, if enabled. Upon detection of the Fault condition, the OCFLT bit (OCxCON<4>) is asserted high (logic ‘1’). This bit is a read-only bit and will only be cleared once the external Fault condition has been removed and the PWM mode is re-enabled by writing to the appropriate mode bits, OCM<2:0> (OCxCON<2:0>). Note: The external Fault pins, if enabled for use, will continue to control the OCx output pins while the device is in SLEEP or IDLE mode. 16.3.3.2 PWM Period The PWM period is specified by writing to PRy, the Timery period register. The PWM period can be calculated using the following formula: Equation 16-1: Calculating the PWM Period PWM Period = [(PR + 1) • TPB • (TMR Prescale Value)] PWM Frequency = 1/[PWM Period] The PWM period must not exceed the width of the Period Register for the selected mode, 16 bits for 16-bit mode or 32 bits for 32-bit mode. If the calculated period is too large, select a larger prescaler to prevent overflow. To maintain maximum PWM resolution, select the smallest prescaler that does not result in an overflow. Note: A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-55 PIC32MX Family Reference Manual 16.3.3.3 PWM Duty Cycle The PWM duty cycle is specified by writing to the OCxRS register. The OCxRS register can be written to at any time, but the duty cycle value is not latched into OCxR until a match between PRy and TMRy occurs (i.e., the period is complete). This provides a double buffer for the PWM duty cycle and is essential for glitchless PWM operation. In the PWM mode, OCxR is a read-only register. Some important boundary parameters of the PWM duty cycle include the following: • If the duty cycle register OCxR is loaded with 0x0000, the OCx pin will remain low (0% duty cycle). • If OCxR is greater than PRy (timer period register), the pin will remain high (100% duty cycle). • If OCxR is equal to PRy, the OCx pin will be low for one time base count value and high for all other count values. See Figure 16-18 for PWM mode timing details. Table 16-4 through Table 16-9 show example PWM frequencies and resolutions for a device with the Peripheral Bus operating at a variety of frequencies. Equation 16-2: Calculation for Maximum PWM Resolution ( ) log10 FPB FPWM • TMRy • Prescaler bits Maximum PWM Resolution (bits) = log10(2) Equation 16-3: PWM Period and Duty Cycle Calculation Desired PWM frequency is 52.08 kHz FPB = 10 MHz Timer 2 prescale setting: 1:1 1/52.08 kHz = (PR2 + 1) • TPB • (Timer 2 prescale value) 19.20 μs = (PR2 + 1) • 0.1 μs • (1) PR2 = 191 Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz PWM frequency and a 10 MHz Peripheral Bus clock rate. • • 1/52.08 kHz = 2PWM RESOLUTION 1/10 MHz 1 • • 19.20 μs = 2PWM RESOLUTION 100 ns 1 192 = 2PWM RESOLUTION log10(192) = (PWM Resolution) • log10(2) PWM Resolution = 7.6 bits DS61111D-page 16-56 Preliminary © 2008 Microchip Technology Inc. Output Compare Figure 16-18: PWM Output Timing Section 16. Output Compare 16 TMR3 1 PBCLK Period 0005 0000 0001 0002 0003 0004 0005 0000 0001 0002 0003 0004 0005 PR3 0005 OCxR 0002 OCxRS 0002 0001 0001 Hardware Loads New Duty Cycle Here OCx pin User Code Writes New Value to OCxRS In ISR T3IF is Set OCxR = OCxRS T3IF is Set OCxR = OCxRS Note 1: An ‘x’ represents the output compare channel number. 2: OCxR = Compare Register; OCxRS = Secondary Compare Register. Figure 16-19: Dual Compare Mode: Continuous Output Pulse (PR2 = OCxRS, 32-Bit Mode) 1 PBCLK Period TMR2 0005: 0000 PR2 OCxR OCxRS 0000: 0005 0000: 0002 0000: 0002 0000: 0000 0000: 0001 0000: 0002 0000: 0003 0000: 0004 0000: 0005 0000: 0000 Hardware Loads New Duty Cycle Here User Code Writes New Value to OCxRS in ISR 0000: 0001 0000: 0001 0000: 0002 0000: 0001 OCx pin Note: An ‘x’ represents the output compare channel number.. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-57 PIC32MX Family Reference Manual Table 16-4: Example PWM Frequencies and Resolutions with a 10 MHz (16-Bit Mode) Peripheral Bus Clock PWM Frequency 19 Hz 153 Hz 305 Hz 2.44 kHz 9.77 kHz 78.1 kHz 313 kHz Timer Prescaler Ratio Period Register Value Resolution (bits) 8 0xFFFF 16 1 0xFFFF 16 1 0x7FFF 15 1 0x0FFF 12 1 0x03FF 10 1 0x007F 7 1 0x001F 5 Table 16-5: Example PWM Frequencies and Resolutions with a 30 MHz (16-Bit Mode) Peripheral Bus Clock PWM Frequency 58 Hz 458 Hz 916 Hz 7.32 kHz 29.3 kHz 234 kHz 938 kHz Timer Prescaler Ratio Period Register Value Resolution (bits) 8 0xFC8E 16 1 0xFFDD 16 1 0x7FEE 15 1 0x1001 12 1 0x03FE 10 1 0x007F 7 1 0x001E 5 Table 16-6: Example PWM Frequencies and Resolutions with a 50 MHz (16-Bit Mode) Peripheral Bus Clock PWM Frequency 57 Hz 458 Hz 916 Hz 7.32 kHz 29.3 kHz 234 kHz 938 kHz Timer Prescaler Ratio Period Register Value Resolution (bits) 64 0x349C 13.7 8 0x354D 13.7 1 0xD538 15.7 1 0x1AAD 12.7 1 0x06A9 10.7 1 0x00D4 7.7 1 0x0034 5.7 Table 16-7: Example PWM Frequencies and Resolutions with a 50 MHz (16-Bit Mode) Peripheral Bus Clock PWM Frequency 100 Hz 200 Hz 500 Hz 1 kHz 2 kHz 5 kHz 10 kHz Timer Prescaler Ratio Period Register Value (hex) Resolution (bits) (decimal) 8 0xF423 15.9 8 0x7A11 14.9 8 0x30D3 13.6 1 0xC34F 15.6 8 0x0C34 11.6 1 0x270F 13.3 1 0x1387 12.3 Table 16-8: Example PWM Frequencies and Resolutions with a 50 MHz (16-Bit Mode) Peripheral Bus Clock PWM Frequency 100 Hz 200 Hz 500 Hz 1 kHz 2 kHz 5 kHz 10 kHz Timer Prescaler Ratio Period Register Value (hex) Resolution (bits) (decimal) 8 0xF423 15.9 4 0xF423 15.9 2 0xC34F 15.6 1 0x0C34F 15.6 1 0x61A7 14.6 1 0x270F 13.3 1 0x1387 12.3 Table 16-9: Example PWM Frequencies and Resolutions with a 50 MHz (32-Bit Mode) Peripheral Bus Clock PWM Frequency 100 Hz 200 Hz 500 Hz 1 kHz 2 kHz 5 kHz 10 kHz Timer Prescaler Ratio Period Register Value (hex) Resolution (bits) (decimal) 1 1 1 1 1 8 1 0x0007A11 F 18.9 0x0003D08 F 17.9 0x0001869 F 16.6 0x0000C34 F 15.6 0x000061A 7 14.6 0x000004E 0x00001387 1 10.3 12.3 DS61111D-page 16-58 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare Example 16-9 shows configuration and interrupt service code for the PWM mode of operation. Example 16-9: PWM Mode Setup and Interrupt Servicing (16-Bit Mode) // The following code example will set the Output Compare 1 module // for PWM mode with FAULT pin disabled, a 50% duty cycle and a // PWM frequency of 52.08 kHz at Fosc = 40 MHz. Timer2 is selected as // the clock for the PWM time base and Timer2 interrupts // are enabled. OC1CON = 0x0000; OC1R = 0x0060; OC1RS = 0x0060; OC1CON = 0x0006; PR2 = 0x00BF; // Turn off OC1 while doing setup. // Initialize primary Compare Register // Initialize secondary Compare Register // Configure for PWM mode // Set period 16 IFS0CLR = 0x00000040; IFS0SET = 0x00000040; IPC1SET = 0x001C0000; IPC1SET = 0x00030000; // configure int // Clear the OC1 interrupt flag // Enable OC1 interrupt // Set OC1 interrupt priority to 7, // the highest level // Set Subpriority to 3, maximum T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable Timer2 // Enable OC1 // Example code for Output Compare 1 ISR: void__ISR(_OUTPUT_COMPARE_1_VECTOR, ipl7) OC1_IntHandler (void) { // insert user code here IFS0CLR = 0x0040; // Clear the OC1 interrupt flag } © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-59 PIC32MX Family Reference Manual Example 16-10: PWM Mode Setup and Interrupt Servicing (32-Bit Mode) // The following code example will set the Output Compare 1 module // for PWM mode with FAULT pin disabled, a 50% duty cycle and a // PWM frequency of 52.08 kHz at Fosc = 40 MHz. Timer2 is selected as // the clock for the PWM time base and Timer2 interrupts // are enabled. OC1CON = 0x0000; OC1R = 0x00600000; OC1RS = 0x00600000; OC1CON = 0x0006; PR2 = 0x00600000; // Turn off OC1 while doing setup. // Initialize primary Compare Register // Initialize secondary Compare Register // Configure for single pulse mode // Set period IFS0CLR = 0x00000040; IFS0SET = 0x00000040; IPC1SET = 0x001C0000; IPC1SET = 0x00030000; // configure int // Clear the OC1 interrupt flag // Enable OC1 interrupt // Set OC1 interrupt priority to 7, // the highest level // Set Subpriority to 3, maximum T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable Timer2 // Enable OC1 // Example code for Output Compare 1 ISR: void__ISR(_OUTPUT_COMPARE_1_VECTOR, ipl7) OC1_IntHandler (void) { // insert user code here IFS0CLR = 0x0040; // Clear the OC1 interrupt flag } DS61111D-page 16-60 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 16.4 INTERRUPTS Each of the available output compare channels has a dedicated interrupt bit OCxIF, and a corresponding interrupt enable/mask bit OCxIE. These bits are used to determine the source of an interrupt and to enable or disable an individual interrupt source. The priority level of each of the channels can also be set independently of the other channels. OCxIF is set when an output compare channel detects a predefined match condition that is defined as an event generating an interrupt. The OCxIF bit will then be set without regard to the state of the corresponding OCxIE bit. The OCxIF bit can be polled by software if desired. The OCxIE bit is used to define the behavior of the Vector Interrupt Controller (VIC) when a corresponding OCxIF is set. When the OCxIE bit is clear, the VIC module does not generate a CPU interrupt for the event. If the OCxIE bit is set, the VIC module will generate an interrupt to the CPU when the corresponding OCxIF bit is set (subject to the priority and subpriority as outlined below). It is the responsibility of the routine that services a particular interrupt to clear the appropriate interrupt flag bit before the service routine is complete. The priority of each output compare channel can be set independently via the OCxIP<2:0> bits. This priority defines the priority group that the interrupt source will be assigned to. The priority groups range from a value of 7, the highest priority, to a value of 0, which does not generate an interrupt. An interrupt being serviced will be preempted by an interrupt in a higher priority group. The subpriority bits allow setting the priority of an interrupt source within a priority group. The values of the subpriority, OCxIS<1:0>, range from 3, the highest priority, to 0, the lowest priority. An interrupt with the same priority group but having a higher subpriority value will preempt a lower subpriority interrupt that is in progress. The priority group and subpriority bits allow more than one interrupt source to share the same priority and subpriority. If simultaneous interrupts occur in this configuration, the natural order of the interrupt sources within a priority/subpriority group pair determines the interrupt generated. The natural priority is based on the vector numbers of the interrupt sources. The lower the vector number, the higher the natural priority of the interrupt. any interrupts that were overridden by natural order will then generate their respective interrupts (based on priority, subpriority, and natural order) after the interrupt flag for the current interrupt is cleared. After an enabled interrupt is generated, the CPU will jump to the vector assigned to that interrupt. The vector number for the interrupt is the same as the natural order number. The CPU will then begin executing code at the vector address. The user’s code at this vector address should perform any operations required (such as reloading the duty cycle and clearing the interrupt flag), and then exit. Refer to Section 8. “Interrupts” for the vector address table details and for more information on interrupts. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-61 PIC32MX Family Reference Manual 16.5 I/O PIN CONTROL When the output compare module is enabled, the I/O pin direction is controlled by the compare module. The compare module returns the I/O pin control back to the appropriate pin LAT and TRIS control bits when it is disabled. When the PWM with Fault Protection Input mode is enabled, the OCFx Fault pin must be configured for an input by setting the respective TRIS SFR bit. The OCFx Fault input pin is not automatically configured as an input when the PWM fault mode is selected. Table 16-10: Pins Associated with Output Compare Modules 1-5 Pin Name Module Control Pin Type Buffer Type Description OC1 ON O — Output Compare/PWM Channel 1 OC2 ON O — Output Compare/PWM Channel 2 OC3 ON O — Output Compare/PWM Channel 3 OC4 ON O — Output Compare/PWM Channel 4 OC5 ON O — Output Compare/PWM Channel 5 OCFA ON I ST PWM Fault Protection A Input (for Channels 1-4) OCFB ON I ST PWM Fault Protection B Input (for Channel 5) Legend: ST = Schmitt Trigger input with CMOS levels I = Input O = Output DS61111D-page 16-62 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 16.6 OPERATION IN POWER-SAVING AND DEBUG MODES Note: In this manual, a distinction is made between a power mode as it is used in a specific module, and a power mode as it is used by the device, e.g., Sleep mode of the Comparator and SLEEP mode of the CPU. To indicate which type of power mode is intended, uppercase and lowercase letters (Sleep, Idle, Debug) signify a module power mode, and all uppercase letters (SLEEP, IDLE, DEBUG) signify a device power mode. 16.6.1 Output Compare Operation in SLEEP Mode When the device enters SLEEP mode, the system clock is disabled. During SLEEP, the Output Compare modules will drive the pin to the same active state as driven prior to entering SLEEP. The module will then halt at this state. For example, if the pin was high and the CPU entered the SLEEP state, the pin will stay high. Likewise, if the pin was low and the CPU entered the SLEEP state, the pin will stay low. In both cases, when the device wakes up, the Output Compare module will resume operation. When the module is operating in PWM Fault mode, the asynchronous portions of the fault circuit remain active. If a fault is detected, the compare output enable signal is deasserted and OCFLT (OCxCON<4>) is set. If the corresponding interrupt is enabled, an interrupt will be generated and the device will wake-up from SLEEP. 16.6.2 Output Compare Operation in IDLE Mode When the device enters IDLE mode, the system clock sources remain functional and the CPU stops executing code. The SIDL bit (OCxCON<13>) selects if the compare module will stop operation when the device enters IDLE mode or whether the module will continue normal operation in IDLE mode. • If SIDL = 1, the module will discontinue operation in IDLE mode. The module will perform the same procedures when stopped in IDLE mode as it does for SLEEP mode. • If SIDL = 0, the module will continue operation in IDLE only if the selected time base is set to operate in IDLE mode. The output compare channel(s) will operate during the CPU IDLE mode if the SIDL bit is a logic ‘0’. Furthermore, the time base must be enabled with the respective SIDL bit set to a logic ‘0’. Note: The external Fault pins, if enabled for use, will continue to control the associated OCx output pins while the device is in SLEEP or IDLE mode. • When the module is operating in PWM Fault mode, the asynchronous portions of the fault circuit remain active. If a fault is detected, the compare output enable signal is deasserted and OCFLT (OCxCON<4>) is set. If the corresponding interrupt is enabled, an interrupt will be generated and the device will wake-up from IDLE. 16.6.3 Output Compare Operation in DEBUG Mode The FRZ bit (OCxCON<14>) determines whether the Output Compare module will run or stop while the CPU is executing Debug Exception code (i.e., the application is halted) in DEBUG mode. When FRZ = ‘0’, the Output Compare module continues to run even when the application is halted in DEBUG mode. When FRZ = 1 and the application is halted in DEBUG mode, the module will freeze its operations and make no changes to the state of the Output Compare module. The module will resume its operation after the CPU resumes execution. When the module is operating in PWM Fault mode, the asynchronous portions of the fault circuit remain active. If a fault is detected, the compare output enable signal is deasserted and OCFLT (OCxCON<4>) is set. If the corresponding interrupt is enabled, an interrupt will be generated. Note: The FRZ bit is readable and writable only when the CPU is executing in Debug Exception mode. In all other modes, the FRZ bit reads as ‘0’. If FRZ bit is changed during DEBUG mode, the new value does not take effect until the current Debug Exception mode is exited and re-entered. During the Debug Exception mode, the FRZ bit reads the state of the peripheral when entering DEBUG mode. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-63 PIC32MX Family Reference Manual 16.7 16.8 EFFECTS OF VARIOUS RESETS 16.7.1 MCLR Reset Following a MCLR event, the OCxCON, OCxR, and OCxRS registers for each Output Compare module are reset to a value of 0x00000000. 16.7.2 Power-on Reset Following a Power-on (POR) event, the OCxCON, OCxR, and OCxRS registers for each Output Compare module are reset to a value of 0x00000000. 16.7.3 Watchdog Timer Reset The status of the OCMP control registers after a Watchdog Timer (WDT) event depends on the operational mode of the CPU prior to the WDT event. If the device is not in SLEEP, a WDT event will force the OCxCON, OCxR, and OCxRS registers to a Reset value of 0x00000000. If the device is in SLEEP when a WDT event occurs, the contents of the OCxCON, OCxR and OCxRS register values are not affected. OUTPUT COMPARE APPLICATION This is an example application using the PWM mode of the Output Compare module to control the speed of a DC motor. The speed of the motor is controlled by changing the PWM duty cycle. The circuit consists of the following: • A PIC32MX device to generate the PWM. • A TC4431 or equivalent MOSFET driver to drive the MOSFET. • A MOSFET to drive the motor. • A pull-up resistor is used to pull the input of the MOSFET driver high when the PIC32MX is in Reset. This prevents unwanted motor operation during start-up. • A DC motor. DS61111D-page 16-64 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare Example 16-11: PWM Mode Example Application (16-Bit Mode) // The following code example will set the Output Compare 1 module // for PWM mode w/o FAULT pin enabled, a 50% duty cycle and a // PWM frequency of 52.08 kHz at FP = 40 MHz. Timer2 is selected as // the clock for the PWM time base and Timer2 interrupts // are enabled. This example ramps the PWM duty cycle from min to max, then // from max to min and repeats. The rate at which the PWM duty cycle is // changed can be adjusted by the rate at which the Timer2 overflows. // The PWM period can be changed by writing a different value to the PR2 // register. If the PR2 value is adjusted the maximum PWM value will also // have to be adjusted so that it is not greater than the PR2 value. unsigned int Pwm; unsigned char Mode = 0; // variable to store calculated PWM value // variable to determine ramp up or ramp down OC1CON = 0x0000; OC1R = 0x0000; OC1RS = 0x0000; OC1CON = 0x0006; PR2 = 0xFFFF; // Turn off OC1 while doing setup. // Initialize primary Compare Register // Initialize secondary Compare Register // Configure for PWM mode // Set period IFS0CLR = 0x00000040; IFS0SET = 0x00000040; IPC1SET = 0x001C0000; IPC1SET = 0x00030000; // configure int // Clear the OC1 interrupt flag // Enable OC1 interrupt // Set OC1 interrupt priority to 7, // the highest level // Set Subpriority to 3, maximum T2CONSET = 0x8000; OC1CONSET = 0x8000; // Enable Timer2 // Enable OC1 // Example code for Output Compare 1 ISR: void__ISR(_OUTPUT_COMPARE_1_VECTOR, ipl7) OC1_IntHandler (void) { if ( Mode ) { if ( Pwm < 0xFFFF ) // ramp up mode { Pwm ++; // If the duty cycle is not at max, increase OC1RS = Pwm; // Write new duty cycle } else { Mode = 0; // PWM is at max, change mode to ramp down } } // end of ramp up else { if ( !Pwm ) // ramp down mode { Pwm --; // If the duty cycle is not at min, increase OC1RS = Pwm; // Write new duty cycle } else { Mode = 1; // PWM is at min, change mode to ramp up } } // end of ramp down // insert user code here IFS0CLR = 0x0040; // Clear the OC1 interrupt flag } 16 © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-65 PIC32MX Family Reference Manual Figure 16-20: DC Motor Speed Control Application Schematic VDD VDD 10K VDD 26 27 100 99 28 29 30 31 98 97 96 95 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AVSS AVDD 32 94 33 93 34 92 35 91 36 90 37 89 38 88 39 87 40 86 VDD 10 uF VDD 41 85 42 84 43 83 44 82 45 81 80 46 47 48 49 50 79 78 77 76 VDD 75 74 73 72 71 70 69 68 67 66 65 64 63 VDD 62 61 60 59 58 57 56 55 54 53 52 51 1K TC4432 12 V 12 V M VDD VDD VDD VDD C8 1 uF C7 C6 0.1 uF 0.01 uF VDD VDD VDD C5 1 uF C4 C3 0.1 uF 0.01 uF DS61111D-page 16-66 Preliminary © 2008 Microchip Technology Inc. Output Compare 16.9 DESIGN TIPS Section 16. Output Compare 16 Question 1: The Output Compare pin stops functioning even when the SIDL bit is not set. Why? Answer: This is most likely to occur when the SIDL bit (TxCON<13>) of the associated timer source is set. Therefore, it is the timer that actually goes into IDLE mode when the PWRSAV instruction is executed. Question 2: Can I use the Output Compare modules with the selected time base configured for 32-bit mode? Answer: Yes. The timer can be used in 32-bit mode as a time base for the Output Compare modules by setting the T32 bit (TxCON<3>). For proper operation, the Output Compare module must be configured for 32-bit Compare mode by setting the OC32 bit (OCxCON<5>) for all Output Compare modules using the 32-bit timer as a time base. © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-67 PIC32MX Family Reference Manual 16.10 RELATED APPLICATION NOTES This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the PIC32MX device family, but the concepts are pertinent and could be used with modification and possible limitations. The current application notes related to the Output Compare module are: Title No related application notes at this time. Application Note # N/A Note: Please visit the Microchip web site (www.microchip.com) for additional application notes and code examples for the PIC32MX family of devices. DS61111D-page 16-68 Preliminary © 2008 Microchip Technology Inc. Output Compare Section 16. Output Compare 16 16.11 REVISION HISTORY Revision A (October 2007) This is the initial released version of this document. Revision B (October 2007) Updated document to remove Confidential status. Revision C (April 2008) Revised status to Preliminary; Revised U-0 to r-x. Revision D (June 2008) Revised Registers 16-1, 16-20, 16-32; Revised Examples 16-3, 16-4, 16-5, 16-6, 16-7, 16-8, 16-9, 16-10, 16-11; Added TMR1 and TMR2 to Summary Table; Revised Section 16.3, Notes; Change Reserved bits from “Maintain as” to “Write”; Added Note to ON bit (0CxCON, T2CON, T3CON Registers). © 2008 Microchip Technology Inc. Preliminary DS61111D-page 16-69 PIC32MX Family Reference Manual NOTES: DS61111D-page 16-70 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter HIGHLIGHTS This section of the manual contains the following topics: 17 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 17.11 17.12 17.13 Introduction.............................................................................................................. 17-2 Control Registers..................................................................................................... 17-4 ADC Operation, Terminology and Conversion Sequence ..................................... 17-24 ADC Module Configuration.................................................................................... 17-26 Miscellaneous ADC Functions............................................................................... 17-38 Initialization ............................................................................................................ 17-59 Interrupts................................................................................................................ 17-61 I/O Pin Control ....................................................................................................... 17-62 Operation During SLEEP and IDLE Modes........................................................... 17-63 Effects of Various Resets....................................................................................... 17-65 Design Tips ............................................................................................................ 17-66 Related Application Notes ..................................................................................... 17-71 Revision History..................................................................................................... 17-72 © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-1 PIC32MX Family Reference Manual 17.1 INTRODUCTION The PIC32MX 10-bit Analog-to-Digital (A/D) converter (or ADC) includes the following features: • Successive Approximation Register (SAR) conversion • Up to 16 analog input pins • External voltage reference input pins • One unipolar differential Sample-and-Hold Amplifier (SHA) • Automatic Channel Scan mode • Selectable conversion trigger source • 16 word conversion result buffer • Selectable Buffer Fill modes • Eight conversion result format options • Operation during CPU SLEEP and IDLE modes A block diagram of the 10-bit ADC is shown in Figure 17-1. The 10-bit ADC can have up to 16 analog input pins, designated AN0-AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. The actual number of analog input pins and external voltage reference input configuration will depend on the specific PIC32MX device. Refer to the device data sheet for further details. The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs can be switched between two sets of analog inputs between conversions. Unipolar differential conversions are possible on all channels, other than the pin used as the reference, using a reference input pin (see Figure 17-1). The Analog Input Scan mode sequentially converts user-specified channels. A Control register specifies which analog input channels will be included in the scanning sequence. The 10-bit ADC is connected to a 16-word result buffer. Each 10-bit result is converted to one of eight 32-bit output formats when it is read from the result buffer. DS61104D-page 17-2 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter Figure 17-1: 10-Bit High-Speed A/D Converter Block Diagram AVDD AVSS VREF+ VREF- AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 VR Select VR+ VR- VINH + VINL SHA - VR- VR+ DAC VINH + 10-bit SAR MUX A CH0NA – VINL ADC1BUF0: ADC1BUFF MUX B + VINH – VINL AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL CH0NB Sample Control Control Logic Pin Config Control Input MUX Control Internal Data Bus 32 Comparator 17 Conversion Logic Data Formatting Conversion Control © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-3 PIC32MX Family Reference Manual 17.2 CONTROL REGISTERS The ADC module includes the following Special Function Registers (SFRs): The AD1CON1, AD1CON2 and AD1CON3 registers control the operation of the ADC module. • AD1CON1: ADC Control Register 1 AD1CON1CLR, AD1CON1SET, AD1CON1INV: Atomic Bit Manipulation, Write-only Registers for AD1CON1. • AD1CON2: ADC Control Register 2 AD1CON2CLR, AD1CON2SET, AD1CON2INV: Atomic Bit Manipulation, Write-only Registers for AD1CON2. • AD1CON3: ADC Control Register 3 AD1CON3CLR, AD1CON3SET, AD1CON3INV: Atomic Bit Manipulation, Write-only Registers for AD1CON3. The AD1CHS register selects the input pins to be connected to the SHA. • AD1CHS: ADC Input Channel Select Register AD1CHSCLR, AD1CHSSET, AD1CHSINV: Atomic Bit Manipulation, Write-only Registers for AD1CHS. The AD1PCFG register configures the analog input pins as analog inputs or as digital I/O. • AD1PCFG: ADC Port Configuration Register AD1PCFGCLR, AD1PCFGSET, AD1PCFGINV: Atomic Bit Manipulation, Write-only Registers for AD1PCFG. The AD1CSSL register selects inputs to be sequentially scanned. • AD1CSSL: ADC Input Scan Selection Register AD1CSSLCLR, AD1CSSLSET, AD1CSSLINV: Atomic Bit Manipulation, Write-only Registers for AD1CSSL. The ADC module also has the following associated bits for interrupt control: • Interrupt Request Flag Status bit (AD1IF) in IFS1: Interrupt Flag Status Register 1 • Interrupt Enable Control bit (AD1IE) in IEC1: Interrupt Enable Control Register 1 • Interrupt Priority Control bits (AD1IP<2:0>) and (AD1IS<1:0>) in IPC6: Interrupt Priority Control Register 6 DS61104D-page 17-4 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter 17.2.1 Special Function Registers Associated with the 10-Bit ADC Table 17-1: Name The following table provides a summary of all ADC-related registers, including their addresses and formats. Corresponding registers appear after the summary, followed by a detailed description of each register. All unimplemented registers and/or bits within a register read as zeros. . ADC SFR Summary Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 AD1CON1 31:24 23:16 15:8 7:0 AD1CON1CLR 31:0 AD1CON1SET 31:0 AD1CON1INV 31:0 AD1CON2 31:24 23:16 15:8 7:0 AD1CON2CLR 31:0 AD1CON2SET 31:0 AD1CON2INV 31:0 AD1CON3 31:24 23:16 15:8 7:0 AD1CON3CLR 31:0 AD1CON3SET 31:0 AD1CON3INV 31:0 AD1CHS 31:24 23:16 15:8 7:0 AD1CHSCLR 31:0 AD1CHSSET 31:0 AD1CHS1INV 31:0 AD1PCFG 31:24 23:16 15:8 7:0 AD1PCFGCLR 31:0 AD1PCFGSET 31:0 AD1PCFGINV 31:0 AD1CSSL 31:24 23:16 15:8 7:0 AD1CSSLCLR 31:0 — — ON SSRC2 — — VCFG2 BUFS — — ADRC ADCS7 CH0NB CH0NA — — — — PCFG15 PCFG7 — — CSSL15 CSSL7 — — — — — — — — — — — — FRZ SIDL — — FORM2 FORM1 SSRC1 SSRC0 CLRASAM — ASAM SAMP Write clears selected bits in AD1CON1, read yields undefined value Write sets selected bits in AD1CON1, read yields undefined value Write inverts selected bits in AD1CON1, read yields undefined value — — — — — — — — — — — — VCFG1 VCFG0 OFFCAL — CSCNA — — SMPI3 SMPI2 SMPI1 SMPI0 BUFM Write clears selected bits in AD1CON2, read yields undefined value Write sets selected bits in AD1CON2, read yields undefined value Write inverts selected bits in AD1CON2, read yields undefined value — — — — — — — — — — — — — — SAMC4 SAMC3 SAMC2 SAMC1 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 Write clears selected bits in AD1CON3, read yields undefined value Write sets selected bits in AD1CON3, read yields undefined value Write inverts selected bits in AD1CON3, read yields undefined value — — — CH0SB3 CH0SB2 CH0SB1 — — — CH0SA3 CH0SA2 CH0SA1 — — — — — — — — — — — — Write clears selected bits in AD1CHS, read yields undefined value Write sets selected bits in AD1CHS, read yields undefined value Write inverts selected bits in AD1CHS, read yields undefined value — — — — — — — — — — — — PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 Write clears selected bits in AD1PCFG, read yields undefined value Write sets selected bits in AD1PCFG, read yields undefined value Write inverts selected bits in AD1PCFG, read yields undefined value — — — — — — — — — — — — CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 Write clears selected bits in AD1CSSL, read yields undefined value — — FORM0 DONE — — — ALTS — — SAMC0 ADCS0 CH0SB0 CH0SA0 — — — — PCFG8 PCFG0 — — CSSL8 CSSL0 17 © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-5 PIC32MX Family Reference Manual Table 17-1: ADC SFR Summary (Continued) Name Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 AD1CSSLSET AD1CSSLINV ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF IFS1 IFS1CLR IFS1SET IFS1INV IEC1 IPC6 IPC6CLR IPC6SET IPC6INV 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0 31:0 31:0 31:0 — — RTCCIF SPI2RXIF — — RTCCIE SPI2RXIE — — — — Write sets selected bits in AD1CSSL, read yields undefined value Write inverts selected bits in AD1CSSL, read yields undefined value ADC Result Word 0 (ADC1BUF0<31:0>) ADC Result Word 1 (ADC1BUF1<31:0>) ADC Result Word 2 (ADC1BUF2<31:0>) ADC Result Word 3 (ADC1BUF3<31:0>) ADC Result Word 4 (ADC1BUF4<31:0>) ADC Result Word 5 (ADC1BUF5<31:0>) ADC Result Word 6 (ADC1BUF6<31:0>) ADC Result Word 7 (ADC1BUF7<31:0>) ADC Result Word 8 (ADC1BUF8<31:0>) ADC Result Word 9 (ADC1BUF9<31:0>) ADC Result Word A (ADC1BUFA<31:0>) ADC Result Word B (ADC1BUFB<31:0>) ADC Result Word C (ADC1BUFC<31:0>) ADC Result Word D (ADC1BUFD<31:0>) ADC Result Word E (ADC1BUFE<31:0>) ADC Result Word F (ADC1BUFF<31:0>) — — — — — USBIF FCEIF — — — DMA3IF DMA2IF DMA1IF DMA0IF FSCMIF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF Write clears the selected bits in IFS1, read yields undefined value Write sets the selected bits in IFS1, read yields undefined value Write inverts the selected bits in IFS1, read yields undefined value — — — — — USBIE FCEIE — — — DMA3IE DMA2IE DMA1IE DMA0IE FSCMIE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE — — AD1IP<2:0> AD1IS<1:0> — — CNIP<2:0> CNIS<1:0> — — I2C1IP<2:0> I2C1IS<1:0> — — U1IP<2:0> U1IS<1:0> Write clears the selected bits in IPC6, read yields undefined value Write sets the selected bits in IPC6, read yields undefined value Write inverts the selected bits in IPC6, read yields undefined value DS61104D-page 17-6 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter Register 17-1: AD1CON1: ADC Control Register 1 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R/W-0 R/W-0 R/W-0 r-x ON FRZ SIDL — bit 15 r-x R/W-0 R/W-0 R/W-0 — FORM<2:0> bit 8 R/W-0 R/W-0 R/W-0 R/W-0 r-x SSRC<2:0> CLRASAM — bit 7 R/W-0 ASAM R/W-0 SAMP R/C-0 DONE bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14 bit 13 bit 12-11 bit 10-8 Reserved: Write ‘0’; ignore read ON: ADC Operating Mode bit 1 = A/D converter module is operating 0 = A/D converter is off Note: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. FRZ: Freeze in Debug Exception Mode bit 1 = Freeze operation when CPU enters Debug Exception mode 0 = Continue operation when CPU enters Debug Exception mode Note: FRZ is writable in Debug Exception mode only. It reads ‘0’ in Normal mode. SIDL: Stop in IDLE Mode bit 1 = Discontinue module operation when device enters IDLE mode 0 = Continue module operation in IDLE mode Reserved: Write ‘0’; ignore read FORM<2:0>: Data Output Format bits 011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) 001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) 101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 17 © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-7 PIC32MX Family Reference Manual Register 17-1: AD1CON1: ADC Control Register 1 (Continued) bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = Reserved 010 = Timer 3 period match ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion bit 4 CLRASAM: Stop Conversion Sequence bit (when the first A/D converter interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated. 0 = Normal operation, buffer contents will be overwritten by the next conversion sequence bit 3 Reserved: Write ‘0’; ignore read bit 2 ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set. 0 = Sampling begins when SAMP bit is set bit 1 SAMP: ADC Sample Enable bit 1 = The ADC SHA is sampling 0 = The ADC sample/hold amplifier is holding When ASAM = 0, writing ‘1’ to this bit starts sampling. When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion. bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is not done or has not started Clearing this bit will not affect any operation in progress. Note: The DONE bit isn’t persistent in automatic modes. It is cleared by hardware at the beginning of the next sample. DS61104D-page 17-8 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter Register 17-2: AD1CON1CLR: ADC Port Configuration Register Write clears selected bits in AD1CON1, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in AD1CON1 A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in AD1CON1 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CON1CLR = 0x00008002 will clear bits 15 and 1 in AD1CON1 register. Register 17-3: AD1CON1SET:ADC Port Configuration Register Write sets selected bits in AD1CON1, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in AD1CON1 A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in AD1CON1 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CON1SET = 0x00008002 will set bits 15 and 1in AD1CON1 register. 17 Register 17-4: AD1CON1INV:ADC Port Configuration Register Write inverts selected bits in AD1CON1, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in AD1CON1 A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in AD1CON1 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CON1INV = 0x00008002 will invert bits 15 and 1 in AD1CON1 register. © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-9 PIC32MX Family Reference Manual Register 17-5: AD1CON2: ADC Control Register 2 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 r-x R/W-0 r-x VCFG<2:0> OFFCAL — CSCNA — bit 15 r-x — bit 8 R-0 BUFS bit 7 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — SMPI<3:0> BUFM ALTS bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15-13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 Reserved: Write ‘0’; ignore read VCFG<2:0>: Voltage Reference Configuration bits ADC VR+ ADC VR- 000 AVDD AVSS 001 External VREF+ pin AVSS 010 AVDD External VREF- pin 011 External VREF+ pin External VREF- pin 1xx AVDD AVSS OFFCAL: Input Offset Calibration Mode Select bit 1 = Enable Offset Calibration mode VINH and VINL of the SHA are connected to VR- 0 = Disable Offset Calibration mode The inputs to the SHA are controlled by AD1CHS or AD1CSSL Reserved: Write ‘0’; ignore read CSCNA: Scan Input Selections for CH0+ SHA Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Reserved: Write ‘0’; ignore read’ BUFS: Buffer Fill Status bit Only valid when BUFM = 1 (ADRES split into 2 x 8-word buffers). 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF Reserved: Write ‘0’; ignore read DS61104D-page 17-10 Preliminary © 2008 Microchip Technology Inc. Section 17. 10-Bit A/D Converter Register 17-5: AD1CON2: ADC Control Register 2 (Continued) bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence bit 1 BUFM: ADC Result Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers, ADC1BUF(7...0), ADC1BUF(15...8) 0 = Buffer configured as one 16-word buffer ADC1BUF(15...0.) bit 0 ALTS: Alternate Input Sample Mode Select bit 17 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always use MUX A input multiplexer settings A/D Converter © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-11 PIC32MX Family Reference Manual Register 17-6: AD1CON2CLR: ADC Port Configuration Register Write clears selected bits in AD1CON2, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in AD1CON2 A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in AD1CON2 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CON2CLR = 0x00008001 will clear bits 15 and 0 in AD1CON2 register. Register 17-7: AD1CON2SET:ADC Port Configuration Register Write sets selected bits in AD1CON2, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in AD1CON2 A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in AD1CON2 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CON2SET = 0x00008001 will set bits 15 and 0 in AD1CON2 register. Register 17-8: AD1CON2INV:ADC Port Configuration Register Write inverts selected bits in AD1CON2, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in AD1CON2 A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in AD1CON2 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CON2INV = 0x00008001 will invert bits 15 and 0 in AD1CON2 register. DS61104D-page 17-12 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter Register 17-9: AD1CON3: ADC Control Register 3 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x — — bit 23 R/W-0 r-x ADRC — bit 15 r-x r-x r-x r-x r-x r-x — — — — — — bit 16 r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 17 — SAMC<4:0> bit 8 R/W-0 bit 7 R/W-0 R/W-0 R/W-0 R/W-0 ADCS<7:0> R/W-0 R/W R/W-0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 bit 15 bit 14-13 bit 12-8 bit 7-0 Reserved: Write ‘0’; ignore read ADRC: ADC Conversion Clock Source bit 1 = ADC internal RC clock 0 = Clock derived from Peripheral Bus Clock (PBclock) Reserved: Write ‘0’; ignore read SAMC<4:0>: Auto-Sample Time bits 11111 = 31 TAD ····· 00001 = 1 TAD 00000 = 0 TAD (Not allowed) ADCS<7:0>: ADC Conversion Clock Select bits 11111111 =TPB • 2 • (ADCS<7:0> + 1) = 512 • TPB = TAD ······ 00000001 =TPB • 2 • (ADCS<7:0> + 1) = 4 • TPB = TAD 00000000 =TPB • 2 • (ADCS<7:0> + 1) = 2 • TPB = TAD © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-13 PIC32MX Family Reference Manual Register 17-10: AD1CON3CLR: ADC Port Configuration Register Write clears selected bits in AD1CON3, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in AD1CON3 A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in AD1CON3 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CON3CLR = 0x00008001 will clear bits 15 and 0 in AD1CON3 register. Register 17-11: AD1CON3SET:ADC Port Configuration Register Write sets selected bits in AD1CON3, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in AD1CON3 A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in AD1CON3 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CON3SET = 0x00008001 will set bits 15 and 0 in AD1CON3 register. Register 17-12: AD1CON3INV:ADC Port Configuration Register Write inverts selected bits in AD1CON3, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in AD1CON3 A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in AD1CON3 register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CON3INV = 0x00008001 will invert bits 15 and 0 in AD1CON3 register. DS61104D-page 17-14 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter Register 17-13: AD1CHS:ADC Input Select Register R/W-0 r-x r-x r-x CH0NB — — — bit 31 R/W-0 R/W-0 R/W-0 CH0SB<3:0> R/W-0 bit 24 R/W-0 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 CH0NA — — — CH0SA<3:0> bit 23 bit 16 r-x r-x r-x r-x r-x r-x r-x r-x 17 — — — — — — — — bit 15 bit 8 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31 bit 30-28 bit 27-24 bit 23 bit 22-20 bit 19-16 bit 15-0 CH0NB: Negative Input Select bit for MUX B 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- Reserved: Write ‘0’; ignore read CH0SB<3:0>: Positive Input Select bits for MUX B 1111 = Channel 0 positive input is AN15 1110 = Channel 0 positive input is AN14 1101 = Channel 0 positive input is AN13 ... ... ... 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 CH0NA: Negative Input Select bit for MUX A Multiplexer Setting(2) 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- Reserved: Write ‘0’; ignore read CH0SA<3:0>: Positive Input Select bits for MUX A Multiplexer Setting 1111 = Channel 0 positive input is AN15 1110 = Channel 0 positive input is AN14 1101 = Channel 0 positive input is AN13 ... ... ... 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 Reserved: Write ‘0’; ignore read © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-15 PIC32MX Family Reference Manual Register 17-14: AD1CHSCLR: ADC Port Configuration Register Write clears selected bits in AD1CHS, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in AD1CHS A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in AD1CHS register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CHSCLR = 0x80010000 will clear bits 15 and 0 in AD1CHS register. Register 17-15: AD1CHSSET:ADC Port Configuration Register Write sets selected bits in AD1CHS, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in AD1CHS A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in AD1CHS register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CHSSET = 0x80010000 will set bits 15 and 0 in AD1CHS register. Register 17-16: AD1CHSINV:ADC Port Configuration Register Write inverts selected bits in AD1CHS, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in AD1CHS A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in AD1CHS register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CHSINV = 0x80010000 will invert bits 15 and 0 in AD1CHS register. DS61104D-page 17-16 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter Register 17-17: AD1PCFG:ADC Port Configuration Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R/W-0 PCFG15 bit 15 R/W-0 PCFG14 R/W-0 PCFG13 R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8 bit 8 R/W-0 PCFG7 bit 7 R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 Reserved: Write ‘0’; ignore read bit 15-0 PCFG<15:0>: Analog Input Pin Configuration Control bits 1 = Analog input pin in Digital mode, port read input enabled, ADC input multiplexer input for this analog input connected to AVss 0 = Analog input pin in Analog mode, digital port read will return as a ‘1’ without regard to the voltage on the pin, ADC samples pin voltage Note: The AD1PCFG register functionality will vary depending on the number of ADC inputs available on the selected device. Please refer to the specific device data sheet for additional details on this register. 17 © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-17 PIC32MX Family Reference Manual Register 17-18: AD1PCFGCLR: ADC Port Configuration Register Write clears selected bits in AD1PCFG, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in AD1PCFG A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in AD1PCFG register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1PCFGCLR = 0x00008001 will clear bits 15 and 0 in AD1PCFG register. Register 17-19: AD1PCFGSET:ADC Port Configuration Register Write sets selected bits in AD1PCFG, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in AD1PCFG A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in AD1PCFG register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1PCFGSET = 0x00008001 will set bits 15 and 0 in AD1PCFG register. Register 17-20: AD1PCFGINV:ADC Port Configuration Register Write inverts selected bits in AD1PCFG, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in AD1PCFG A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in AD1PCFG register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1PCFGINV = 0x00008001 will invert bits 15 and 0 in AD1PCFG register. DS61104D-page 17-18 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter Register 17-21: AD1CSSL: ADC Input Scan Select Register r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R/W-0 CSSL15 bit 15 R/W-0 CSSL14 R/W-0 CSSL13 R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 R/W-0 CSSL8 bit 8 R/W-0 CSSL7 bit 7 R/W-0 CSSL6 R/W-0 CSSL5 R/W-0 CSSL4 R/W-0 CSSL3 R/W-0 CSSL2 R/W-0 CSSL1 R/W-0 CSSL0 bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 31-16 Reserved: Write ‘0’; ignore read bit 15-0 CSSL<15:0>: ADC Input Pin Scan Selection bits 1 = Select ANx for input scan 0 = Skip ANx for input scan Note: The AD1CSSL register functionality will vary depending on the number of ADC inputs available on the selected device. Please refer to the specific device data sheet for additional details on this register. 17 © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-19 PIC32MX Family Reference Manual Register 17-22: AD1CSSLCLR: ADC Port Configuration Register Write clears selected bits in AD1CSSL, read yields undefined value bit 31 bit 0 bit 31-0 Clears selected bits in AD1CSSL A write of ‘1’ in one or more bit positions clears the corresponding bit(s) in AD1CSSL register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CSSLCLR = 0x00008001 will clear bits 15 and 0 in AD1CSSL register. Register 17-23: AD1CSSLSET:ADC Port Configuration Register Write sets selected bits in AD1CSSL, read yields undefined value bit 31 bit 0 bit 31-0 Sets selected bits in AD1CSSL A write of ‘1’ in one or more bit positions sets the corresponding bit(s) in AD1CSSL register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CSSLSET = 0x00008001 will set bits 15 and 0 in AD1CSSL register. Register 17-24: AD1CSSLINV:ADC Port Configuration Register Write inverts selected bits in AD1CSSL, read yields undefined value bit 31 bit 0 bit 31-0 Inverts selected bits in AD1CSSL A write of ‘1’ in one or more bit positions inverts the corresponding bit(s) in AD1CSSL register and does not affect unimplemented or read-only bits. A write of ‘0’ will not affect the register. Example: AD1CSSLINV = 0x00008001 will invert bits 15 and 0 in AD1CSSL register. DS61104D-page 17-20 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter Register 17-25: IFS1: Interrupt Flag Status Register 1(1) r-x r-x r-x r-x r-x — — — — — bit 31 r-x R/W-0 R/W-0 — USBIF FCEIF bit 24 r-x — bit 23 R/W-0 RTCCIF bit 15 r-x r-x r-x R/W-0 — — — DMA3IF R/W-0 FSCMIF R/W-0 I2C2MIF R/W-0 I2C2SIF R/W-0 I2C2BIF R/W-0 DMA2IF R/W-0 U2TXIF R/W-0 DMA1IF R/W-0 DMA0IF bit 16 R/W-0 R/W-0 17 U2RXIF U2EIF bit 8 R/W-0 SPI2RXIF bit 7 R/W-0 SPI2TXIF R/W-0 SPI2EIF R/W-0 CMP2IF R/W-0 CMP1IF R/W-0 PMPIF R/W-0 AD1IF R/W-0 CNIF bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 1 Note 1: AD1IF: Analog-to-Digital Converter 1 Interrupt Request Flag bit 1 = Interrupt request has occurred 0 = No interrupt request has a occurred Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the ADC. © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-21 PIC32MX Family Reference Manual Register 17-26: IEC1: Interrupt Enable Control Register 1(1) r-x r-x r-x r-x r-x — — — — — bit 31 r-x R/W-0 R/W-0 — USBIE FCEIE bit 24 r-x — bit 23 r-x r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 — — — DMA3IE DMA2IE DMA1IE DMA0IE bit 16 R/W-0 RTCCIE bit 15 R/W-0 FSCMIE R/W-0 I2C2MIE R/W-0 I2C2SIE R/W-0 I2C2BIE R/W-0 U2TXIE R/W-0 U2RXIE R/W-0 U2EIE bit 8 R/W-0 SPI2RXIE bit 7 R/W-0 SPI2TXIE R/W-0 SPI2EIE R/W-0 CMP2IE R/W-0 CMP1IE R/W-0 PMPIE R/W-0 AD1IE R/W-0 I2C1MIE bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 1 Note 1: AD1IE: Analog-to-Digital Converter 1 Interrupt Enable bit 1 = Interrupt is enabled. 0 = Interrupt is disabled. Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the ADC. DS61104D-page 17-22 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter Register 17-27: IPC6:Interrupt Priority Control Register 6(1) r-x r-x r-x R/W-0 R/W-0 — — — AD1IP<2:0> bit 31 R/W-0 R/W-0 R/W-0 AD1IS<1:0> bit 24 r-x — bit 23 r-x — bit 15 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CNIP<2:0> CNIS<1:0> bit 16 r-x r-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 17 — — I2C1IP<2:0> I2C1IS<1:0> bit 8 r-x — bit 7 r-x r-x R/W-0 R/W-0 R/W-0 R/W R/W-0 — — U1IP<2:0> U1IS<1:0> bit 0 Legend: R = Readable bit U = Unimplemented bit W = Writable bit P = Programmable bit -n = Bit Value at POR: (‘0’, ‘1’, x = Unknown) r = Reserved bit bit 28 - 26 AD1IP<2:0>: Analog-to-Digital Converter 1 Interrupt Priority bits 111 = Interrupt Priority is 7 110 = Interrupt Priority is 6 101 = Interrupt Priority is 5 100 = Interrupt Priority is 4 011 = Interrupt Priority is 3 010 = Interrupt Priority is 2 001 = Interrupt Priority is 1 000 = Interrupt is disabled bit 25-24 AD1IS<1:0>: Analog-to-Digital 1 Subpriority bits 11 = Interrupt Subpriority is 3 10 = Interrupt Subpriority is 2 01 = Interrupt Subpriority is 1 00 = Interrupt Subpriority is 0 Note 1: Shaded bit names in this Interrupt register control other PIC32MX peripherals and are not related to the ADC. © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-23 PIC32MX Family Reference Manual 17.3 ADC OPERATION, TERMINOLOGY AND CONVERSION SEQUENCE This section will describe the operation the A/D converter, the steps required to configure the converter, describe special feature of the module, and provide examples of ADC configuration with timing diagrams and charts showing the expected output of the converter. 17.3.1 Overview of Operation Analog sampling consists of two steps: acquisition and conversion (see Figure 17-2). During acquisition the analog input pin is connected to the Sample and Hold Amplifier (SHA). After the pin has been sampled for a sufficient period, the sample voltage is equivalent to the input, the pin is disconnected from the SHA to provide a stable input voltage for the conversion process. The conversion process then converts the analog sample voltage to a binary representation. An overview of the ADC is presented in Figure 17-1. The 10-bit A/D converter has a single SHA. The SHA is connected to the analog input pins via the analog input MUXs, MUX A and MUX B. The analog input MUXs are controlled by the AD1CHS register. There are two sets of MUX control bits in the AD1CHS register. These two sets of control bits allow the two different analog input to be independently controlled. The A/D converter can optionally switch between MUX A and MUX B configurations between conversions. The A/D converter can also optionally scan through a series of analog inputs using a single MUX. Acquisition time can be controlled manually or automatically. The acquisition time may be started manually by setting the SAMP bit (AD1CON1<1>), and ended manually by clearing the SAMP in the user software. The acquisition time may be started automatically by the A/D converter hardware and ended automatically by a conversion trigger source. The acquisition time is set by the SAMC bits (AD1CON3<12:8>). The SHA has a minimum acquisition period. Refer to the device data sheet for acquisition time specifications Conversion time is the time required for the A/D converter to convert the voltage held by the SHA. The A/D converter requires one ADC clock cycle (TAD) to convert each bit of the result, plus two additional clock cycles. Therefore a total of 12 TAD cycles are required to perform the complete conversion. When the conversion time is complete, the result is written into one of the 16 ADC result registers (ADC1BUF0...ADC1BUFF). The sum of the acquisition time and the A/D conversion time provides the total sample time (refer to Figure 17-2). There are multiple input clock options for the A/D converter that are used to create the TAD clock. The user must select an input clock option that does not violate the minimum TAD specification. The sampling process can be performed once, periodically, or based on a trigger as defined by the module configuration. Figure 17-2: ADC Sample/Conversion Sequence ADC Total Sample Time Acquisition Time A/D Conversion Time A/D conversion complete, result is written into the ADC result buffer. Optionally generate interrupt. SHA is disconnected from input and holds the signal. A/D conversion is started by the conversion trigger source. SHA is connected to the analog input pin for sampling. DS61104D-page 17-24 Preliminary © 2008 Microchip Technology Inc. Section 17. 10-Bit A/D Converter The start time for sampling can be controlled in software by setting the SAMP control bit. The start of the sampling time can also be controlled automatically by the hardware. When the A/D converter operates in the Auto-Sample mode, the SHA is reconnected to the analog input pin at the end of the conversion in the sample/convert sequence. The auto-sample function is controlled by the ASAM control bit (AD1CON1<2>). The conversion trigger source ends the sampling time and begins an A/D conversion or a sample/convert sequence. The conversion trigger source is selected by the control bits SSRC<2:0> (AD1CON1<7:5>). The conversion trigger can be taken from a variety of hardware sources, or can be controlled manually in software by clearing the SAMP control bit. One of the conversion trigger sources is an auto-conversion. The time between auto-conversions is set by a counter and the ADC clock. The Auto-Sample mode and auto-conversion trigger can be used together to provide endless automatic conversions without software intervention. An interrupt may be generated at the end of each sample sequence or multiple sample sequences as determined by the value of the SMPI<3:0> (AD1CON2<5:2>). The number of sample sequences between interrupts can vary between 1 and 16. The user should note that the A/D conversion buffer holds the results of a single conversion sequence. The next sequence starts filling the buffer from the top even if the number of samples in the previous sequence was less than 16. The total number of conversion results between interrupts is the SMPI value. The total number of conversions between interrupts cannot exceed the physical buffer length. 17 A/D Converter © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-25 PIC32MX Family Reference Manual 17.4 ADC MODULE CONFIGURATION Operation of the ADC module is directed through bit settings in the appropriate registers. The following instructions summarize the actions and the settings. Options and details for each configuration step are provided in subsequent sections. 1. To configure the ADC module, perform the following steps: A-1. Configure analog port pins in AD1PCFG<15:0>, as described in Section 17.4.1 “Configuring Analog Port Pins”. B-1. Select the analog inputs to the ADC MUXs in AD1CHS<32:0>, as described in Section 17.4.2 “Selecting the Analog Inputs to the ADC MUXs”. C-1. Select the format of the ADC result using FORM<2:0> (AD1CON1<10:8>), as described in Section 17.4.3 “Selecting the Format of the ADC Result”. C-2. Select the sample clock source using SSRC<2:0> (AD1CON1<7:5>), as described in Section 17.4.4 “Selecting the Sample Clock Source”. D-1. Select the voltage reference source using VCFG<2:0> (AD1CON2<15:13>), as described in Section 17.4.7 “Selecting the Voltage Reference Source”. D-2. Select the Scan mode using CSCNA (AD1CON2<10>), as described in Section 17.4.8 “Selecting the Scan Mode”. D-3. Set the number of conversions per interrupt SMP<3:0> (AD1CON2<5:2>), if interrupts are to be used, as described in Section 17.4.9 “Setting the Number of Conversions per Interrupt”. D-4. Set Buffer Fill mode using BUFM (AD1CON2<1>), as described in Section 17.4.10 “Buffer Fill Mode”. D-5. Select the MUX to be connected to the ADC in ALTS AD1CON2<0>, as described in Section 17.4.11 “Selecting the MUX to be Connected to the ADC (Alternating Sample Mode)”. E-1. Select the ADC clock source using ADRC (AD1CON3<15>), as described in Section 17.4.12 “Selecting the ADC Conversion Clock Source and Prescaler”. E-2. Select the sample time using SAMC<4:0> (AD1CON3<12:8>), if auto-convert is to be used, as described in Section 17.4.13 “Acquisition Time Considerations”. E-3. Select the ADC clock prescaler using ADCS<7:0> (AD1CON3<7:0>), as described in Section 17.4.12 “Selecting the ADC Conversion Clock Source and Prescaler”. F. Turn on ADC module using AD1CON1<15>, as described in Section 17.4.14 “Turning the ADC On”. Note: Steps A through E, above, can be performed in any order, but Step F must be the final step in every case. 2. To configure ADC interrupt (if required). A-1. Clear AD1IF bit (IFS1<1>), as described in Section 17.7 “Interrupts”. A-2. Select ADC interrupt priority AD1IP<2:0> (IPC<28:26>) and sub priority AD1IS<1:0> (IPC<24:24>), as described in Section 17.7 “Interrupts”, if interrupts are to be used. 3. Start the conversion sequence by initiating sampling, as described in Section 17.4.15 “Initiating Sampling”. DS61104D-page 17-26 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter 17.4.1 Configuring Analog Port Pins The AD1PCFG register and the TRISB register control the operation of the ADC port pins. AD1PCFG specifies the configuration of device pins to be used as analog inputs. A pin is configured as analog input when the corresponding PCFGn bit (AD1PCFG) = 0. When the bit = 1, the pin is set to digital control. When configured for analog input, the associated port I/O digital input buffer is disabled so it does not consume current. The AD1PCFG register is cleared at Reset, causing the ADC input pins to be configured for analog input by default at Reset. TRIS registers control the digital function of the port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bit set, specifying the pin as an input. If the I/O pin associated with an ADC input is configured as an output, TRIS bit is cleared, the ports digital output level (VOH or VOL) will be converted. After a device Reset, all TRIS bits are set. 17 Notes: When reading a PORT register that shares pins with the ADC, any pin configured as an analog input reads as a ‘0’ when the PORT latch is read. Analog levels on any pin that is defined as a digital input (including the AN15:AN0 pins), but is not configured as an analog input, may cause the input buffer to consume current that is out of the device’s specification. 17.4.2 Selecting the Analog Inputs to the ADC MUXs The AD1CHS register is used to select which analog input pin is connected to MUX A and MUX B. Each MUX has two inputs referred to as the positive and the negative input. The positive input to MUX A is controlled by CH0SA<4:0> and the negative input is controlled by CH0NA. The positive input for MUX B is controlled by CH0SB<4:0> and the negative input is controlled by CH0NB. The positive input can be selected from any one of the available analog input pins. The negative input can be selected as the ADC negative reference or AN1. The use of AN1 as the negative input allows the ADC to be used in a Unipolar Differential mode. Refer to the device data sheet for AN1 input voltage restrictions when used as a negative reference. Note: When using Scan mode CH0SA<4:0> may be overridden. Refer to Section 17.4.8 “Selecting the Scan Mode” for more information. 17.4.3 Selecting the Format of the ADC Result The data in the ADC result register can be read as one of eight formats. The format is controlled by FORM<2:0> (AD1CON1<10:8>). The user can select from Integer, Signed Integer, Fractional, or Signed Fractional as a 16-bit or 32-bit result. Figure 17-3 shows how a result is formatted. Table 17-2 and Table 17-3 show examples of results for select results in each of the four formats with 32-bit and 16-bit results. Note: There is no numeric difference between 32-bit and 16-bit modes. In 32-bit mode, the sign extension is applied to all 32-bits; whereas in 16-bit mode, sign extension is only applied to the lower 16-bits of the result. © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-27 PIC32MX Family Reference Manual Figure 17-3: ADC Output Data Formats, 32-Bit Mode DS61104D-page 17-28 Preliminary RAM Contents d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Integer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Signed Integer d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Signed Fractional (1.15) d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 © 2008 Microchip Technology Inc. Section 17. 10-Bit A/D Converter Figure 17-4: ADC Output Data Formats, 16-Bit Mode 17 © 2008 Microchip Technology Inc. Preliminary RAM Contents d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Read to Bus: Integer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Signed Integer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Fractional (1.15) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 Signed Fractional (1.15) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 0 0 0 0 0 DS61104D-page 17-29 A/D Converter PIC32MX Family Reference Manual Table 17-2: Numerical Equivalents of Select Result Codes for FORM<2> (AD1CON1 <10>) = 1, 32-Bit Result VIN/ VR 10-Bit Output Code 32-Bit Integer Format 32-Bit Signed Integer Format 32-Bit Fractional Format 32-Bit Signed Fractional Format 1023/1024 11 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1100 0000 0111 1111 1100 0000 0000 0011 1111 1111 0000 0001 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 = 1023 = 511 = 0.999 = 0.499 1022/1024 11 1111 1110 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1000 0000 0111 1111 1000 0000 0000 0011 1111 1110 0000 0001 1111 1110 0000 0000 0000 0000 0000 0000 0000 0000 = 1022 = 510 = 0.998 = 0.498 ••• 513/1024 10 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0100 0000 0 000 0000 0100 0000 0010 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 = 513 =1 = 0.501 0000 0000 0000 0000 = 0.001 512/1024 10 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 = 512 =0 = 0.500 0000 0000 0000 0000 0000 0000 0000 0000 = 0.000 511/1024 01 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0111 1111 1100 0000 1111 1111 1100 0000 0000 0001 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 = 511 = -1 = .499 = -0.001 ••• 1/1024 00 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0100 0000 1000 0000 0100 0000 0000 0000 0000 0001 1111 1110 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 =1 = -511 = 0.001 = -0.499 0/1024 00 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 1111 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 =0 = -512 = 0.000 = -0.500 Table 17-3: Numerical Equivalents of Select Result Codes for FORM<2> (AD1CON1 <10>) = 0, 16-Bit Result VIN/ VR 10-bit Output Code 16-bit Integer Format 16-Bit Signed Integer Format 16-Bit Fractional Format 16-Bit Signed Fractional Format 1023/1024 11 1111 1111 0000 0011 1111 1111 0000 0001 1111 1111 1111 1111 1100 0000 0111 1111 1100 0000 = 1023 = 511 = 0.999 = 0.499 1022/1024 11 1111 1110 0000 0011 1111 1110 0000 0001 1111 1110 1111 1111 1000 0000 0111 1111 1000 0000 = 1022 = 510 = 0.998 = 0.498 ••• 513/1024 10 0000 0001 0000 0010 0000 0001 0000 0000 0000 0001 1000 0000 0100 0000 = 513 =1 = 0.501 0 000 0000 0100 0000 = 0.001 512/1024 10 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 = 512 =0 = 0.500 = 0.000 511/1024 01 1111 1111 0000 0001 1111 1111 1111 1111 1111 1111 0111 1111 1100 0000 1111 1111 1100 0000 = 511 = -1 = .499 = -0.001 ••• 1/1024 00 0000 0001 0000 0000 0000 0001 1111 1110 0000 0001 0000 0000 0100 0000 1000 0000 0100 0000 =1 = -511 = 0.001 = -0.499 0/1024 00 0000 0000 0000 0000 0000 0000 1111 1110 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 =0 = -512 = 0.000 = -0.500 DS61104D-page 17-30 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter 17.4.4 Selecting the Sample Clock Source It is often desirable to synchronize the end of sampling and the start of conversion with some other time event. The ADC module may use one of four sources as a conversion trigger. The selection of the conversion trigger source is controlled by the SSRC<2:0> (AD1CON1<7:5>) bits. 17.4.4.1 Manual Conversion To configure the ADC to end sampling and start a conversion when SAMP is cleared (= 0), SSRC is set to ‘000’. 17.4.4.2 Timer Compare Trigger The ADC is configured for this Trigger mode by setting SSRC<2:0> = 010. When a period match 17 occurs for the 32-bit timer, TMR3/TMR2, or the 16-bit Timer3 a special A/D converter trigger event signal is generated by Timer3. This feature does not exist for the TMR5/TMR4 timer pair or for 16-bit timers other than Timer3. Refer to Section 14. “Timers” for more details. 17.4.4.2.1 External INT0 Pin Trigger To configure the ADC to begin a conversion on an active transition on the INT0 pin, SSRC<2:0> is set to ‘001’. The INT0 pin may be programmed for either a rising edge input or a falling edge input to trigger the conversion process. 17.4.4.2.2 Auto-Convert The ADC can be configured to automatically perform conversions at the rate selected by the Auto Sample Time bits SAMC<4:0>. The ADC is configured for this Trigger mode by setting SSRC<2:0> = 111. In this mode, the ADC will perform continuous conversions on the selected channels. 17.4.5 Synchronizing ADC Operations to Internal or External Events The modes where an external event trigger pulse ends sampling and starts conversion (SSRC2:SSRC0 = 001, 010 or 011) may be used in combination with auto-sampling (ASAM = 1) to cause the ADC to synchronize the sample conversion events to the trigger pulse source. For example, in Figure 17-13 where SSRC = 010 and ASAM = 1, the ADC will always end sampling and start conversions synchronously with the timer compare trigger event. The ADC will have a sample conversion rate that corresponds to the timer comparison event rate. See Example 17-5 for a code example. 17.4.6 Selecting Automatic or Manual Sampling Sampling can be started manually or automatically when the previous conversion is complete. 17.4.6.1 Manual Clearing the ASAM (AD1CON1<2>) bit disables the Auto-Sample mode. Acquisition will begin when the SAMP (AD1CON1<1>) bit is set by software. Acquisition will not resume until the SAMP bit is once again set. For an example, see Figure 17-8. 17.4.6.2 Automatic Setting the ASAM (AD1CON1<2>) bit enables the Auto-Sample mode. In this mode, the sampling will start automatically after the pervious sample has been converted. For an example, see Figure 17-9. © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-31 PIC32MX Family Reference Manual 17.4.7 Selecting the Voltage Reference Source The user can select the voltage reference for the ADC module. The reference can be internal or external. The VCFG<2:0> control bits (AD1CON2<15:13>) select the voltage reference for A/D conversions. The upper voltage reference (VR+) and the lower voltage reference (VR-) may be the internal AVDD and AVSS voltage rails, or the VREF+ and VREF- input pins. The external ADC voltage reference may be used to reduce noise in the converter. The external voltage reference pins may be shared with the AN0 and AN1 inputs on low pin count devices. The A/D converter can still perform conversions on these pins when they are shared with the VREF+ and VREF- input pins. The voltages applied to the external reference pins must meet certain specifications. Refer to the electrical specifications section of the device data sheet for the electrical specifications. Notes: External references VREF+ and VREF- must be selected for high conversion. See the data sheet for further details. The external VREF+ and VREF- pins may be shared with other analog peripherals. Refer the device data sheet for further details. DS61104D-page 17-32 Preliminary © 2008 Microchip Technology Inc. A/D Converter Section 17. 10-Bit A/D Converter 17.4.8 Selecting the Scan Mode The ADC module has the ability to scan through a selected vector of inputs. The CSCNA bit (AD1CON2<10>) enables the MUX A input to be scanned across a selected number of analog inputs. 17.4.8.1 Scan Mode Enable Scan mode is enabled by setting CSCNA (AD1CON2<10>). When Scan mode is enabled the positive input of MUX A is controlled by the contents of the AD1CSSL register. Each bit in the AD1CSSL register corresponds to an analog input. Bit 0 corresponds to AN0, bit 1 corresponds to AN1 and so on. If a particular bit in the AD1CSSL register is ‘1’, the corresponding input is part of the scan sequence. The inputs are always scanned from lower- to higher-numbered inputs, 17 starting at the first selected channel after each interrupt occurs. When Scan mode is enabled the CH0SA<3:0> bits are ignored. Notes: If the number of scanned inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs will not be sampled. The AD1CSSL bits only specify the input of the positive input of the channel. The CH0NA bit selects the input of the negative input of the channel during scanning. 17.4.8.2 Scan Mode Disable When CSCNA = 0, Scan mode is disabled and the positive input to MUX A is controlled by CH0SA<3:0>. 17.4.8.3 Using Scan and Alternate Modes Together The Scan and Alternate modes may be combined to allow a vector of inputs to be scanned and a single input to be converted every other sample. This mode is enabled by setting the CSCNA bit = 1, and setting the ALTS (AD1CON2<0>) bit = 1. The CSCNA bit enables the scan for MUX A, and the CH0SB<3:0> (AD1CHS<27:24>) and CH0NB (AD1CHS<31>) are used to configure the inputs to MUX B. Scanning only applies to the MUX A input selection. The MUX B input selection, as specified by CH0SB<3:0>, will still select a single input. The following sequence is an example of 3 scanned channels (MUX A) and a single fixed channel (MUX B): 1. The first input in the scan list is sampled. 2. The input selected by CH0SB<3:0> and CH0NB is sampled. 3. The second input in the scan list is sampled. 4. The input selected by CH0SB<3:0> and CH0NB is sampled. 5. The third input in the scan list is sampled. 6. The input selected by CH0SB<3:0> and CH0NB is sampled. The process is repeated. © 2008 Microchip Technology Inc. Preliminary DS61104D-page 17-33 PIC32MX Family Reference Manual 17.4.9 Setting the Number of Conversions per Interrupt The SMPI<3:0> bits (AD1CON2<5:2>) select how many A/D conversions will take place before a CPU interrupt is generated. This also defines the number of locations that will be written in the result buffer stating with ADC1BUF0 (ADC1BUF0 or ADC1BUF8 for Dual Buffer mode). This can vary from 1 sample to 16 samples (1 to 8 samples for Dual Buffer mode). After the interrupt is generated, the sampling sequence restarts; with the result of the first sample being written to the first buffer location. For example, if SMPI<3:0> = 0000, the conversion results will always be written to ADC1BUF0. In this example, no other buffer locations would be used. For example, if SMPI<3:0> = 1110, 15 samples would be converted and stored in buffer locations ADC1BUF0 through ADC1BUFE. An interrupt would be generated after ADC1BUFE was written. The next sample would be written to ADC1BUF0. In this example ADC1BUFF would not be used. The data in the result registers will be overwritten by the next sampling sequence. The data in the result buffer must be read before the completion of the first sample after the interrupt is generated. The Buffer Fill mode can be used to increase the time between interrupt generation and the overwriting of data. Refer to the Buffer Fill Mode section. The user cannot program a combination of samples and SMPI bits that results in more than 16 conversions per interrupt when the BUFM bit (AD1CON2<1>) is ‘1’, or more than 8 conversions per interrupt when the BUFM bit (AD1CON2<1>) is ‘0’. Attempting to create a conversion list with the number of samples greater than 16 will result in the sampling sequence being truncated to 16 samples. 17.4.10 Buffer Fill Mode The Buffer Fill mode allows the output buffer to be used as a single 16-word buffer or two 8-word buffers. When BUFM is ‘0’, the complete 16-word buffer is used for all conversion sequences. Conversion results will be written sequentially in the buffer starting at ADC1BUF0 until the number of samples as defined by SMPI<3:0> (AD1CON2<5:2>) is reached. The next conversion result will be written to ADC1BUF0 and the process repeats. If the ADC interrupt is enabled an interrupt will be generated when the number of samples in the buffer equals SMPI<3:0>. When the BUFM bit (AD1CON2<1>) is ‘1’, the 16-word results buffer (ADRES) will be split into two 8-word groups. Conversion results will be written sequentially into the first buffer starting at ADC1BUF0, BUFS (AD1CON2<7>) will be cleared, until the number of samples as defined by SMPI<3:0> (AD1CON2<5:2>) is reached. The ADC interrupt flag will then be set. After the ADC interrupt flag is set the following result will be written sequentially to the second buffer starting at ADC1BUF8 The next conversion result will be written to the second buffer starting at ADC1BUF8, BUFS (AD1CON2<7>) will be set, until the number of samples as defined by SMPI<3:0> (AD1CON2<5:2>) is reached. The ADC interrupt flag will then be set. T